121 lines
2.7 KiB
Systemverilog
121 lines
2.7 KiB
Systemverilog
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`timescale 1ns/1ps
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module fifo_sync_tb;
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parameter DATA_WIDTH = 8;
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parameter DEPTH = 16;
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parameter USE_RAM = 0;
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parameter OUT_REG = 1;
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reg clk;
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reg rst_n;
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reg wr_en;
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reg [DATA_WIDTH-1:0] din;
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reg rd_en;
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wire [DATA_WIDTH-1:0] dout;
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wire empty;
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wire full;
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wire [$clog2(DEPTH):0] fill_level;
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wire err;
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// 实例化DUT
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fifo_sync #(
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.DATA_WIDTH(DATA_WIDTH),
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.DEPTH(DEPTH),
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.USE_RAM(USE_RAM),
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.OUT_REG(OUT_REG)
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) dut (
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.clk(clk),
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.rst_n(rst_n),
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.wr_en(wr_en),
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.din(din),
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.rd_en(rd_en),
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.dout(dout),
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.empty(empty),
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.full(full),
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.fill_level(fill_level),
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.err(err)
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);
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// 时钟生成
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initial clk = 0;
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always #5 clk = ~clk;
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// 复位
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initial begin
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rst_n = 0;
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wr_en = 0;
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rd_en = 0;
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din = 0;
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#20;
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rst_n = 1;
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end
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// 主测试流程
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initial begin
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wait(rst_n == 1);
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@(negedge clk);
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// 写入DEPTH个数据
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for (int i = 0; i < DEPTH; i++) begin
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@(negedge clk);
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wr_en = 1;
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din = i;
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rd_en = 0;
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end
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@(negedge clk);
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wr_en = 0;
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// 检查full信号
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if (!full) $display("[TB][ERROR] FIFO未满!");
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else $display("[TB][INFO] FIFO已满!");
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// 读出DEPTH个数据
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for (int i = 0; i < DEPTH; i++) begin
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@(negedge clk);
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wr_en = 0;
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rd_en = 1;
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end
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@(negedge clk);
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rd_en = 0;
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// 检查empty信号
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if (!empty) $display("[TB][ERROR] FIFO未空!");
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else $display("[TB][INFO] FIFO已空!");
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// 尝试在empty时读，触发err
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@(negedge clk);
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rd_en = 1;
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@(negedge clk);
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rd_en = 0;
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if (err) $display("[TB][INFO] 读空FIFO触发err信号");
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else $display("[TB][ERROR] 读空FIFO未触发err!");
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// 交错写读
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for (int i = 0; i < 8; i++) begin
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@(negedge clk);
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wr_en = 1;
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din = i + 100;
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rd_en = 1;
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end
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@(negedge clk);
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wr_en = 0;
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rd_en = 0;
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#20;
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$display("[TB][INFO] 测试结束");
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$finish;
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end
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// 监控输出
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always @(posedge clk) begin
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if (wr_en && !full)
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$display("[TB][WRITE] @%0t: din=%0d, wr_ptr=%0d, fill_level=%0d", $time, din, dut.wr_ptr, fill_level);
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if (rd_en && !empty)
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$display("[TB][READ ] @%0t: dout=%0d, rd_ptr=%0d, fill_level=%0d", $time, dout, dut.rd_ptr, fill_level);
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if (err)
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$display("[TB][ERR ] @%0t: 读空FIFO!", $time);
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end
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endmodule
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