79 lines
2.1 KiB
Systemverilog
79 lines
2.1 KiB
Systemverilog
// =============================================================
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// 测试模块：oh2bin_tb
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// 功能描述：onehot到bin编码器仿真测试，默认频率优化方案
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// 仿真时钟频率：1GHz，周期1ns
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// =============================================================
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`timescale 1ns/1ps
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module oh2bin_tb;
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parameter WIDTH = 8;
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parameter BINW = $clog2(WIDTH);
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logic clk;
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logic rst_n;
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logic [WIDTH-1:0] oh;
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logic [BINW-1:0] bin;
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logic [BINW-1:0] bin_q;
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// 实例化被测模块，AREA_OPT=0为频率优化方案
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oh2bin #(
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.WIDTH(WIDTH),
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.AREA_OPT(0)
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) dut (
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.oh(oh),
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.bin(bin)
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);
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// 时钟生成
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// 仿真时钟频率：1GHz，周期1ns
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initial clk = 0;
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always #0.5 clk = ~clk; // 1ns周期，1GHz
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// 采样输出
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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bin_q <= '0;
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else
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bin_q <= bin;
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end
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// 参考模型
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function [BINW-1:0] ref_oh2bin(input [WIDTH-1:0] oh_in);
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integer i;
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ref_oh2bin = '0;
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for (i = 0; i < WIDTH; i = i + 1) begin
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if (oh_in[i]) ref_oh2bin = i[BINW-1:0];
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end
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endfunction
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initial begin
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rst_n = 0;
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oh = '0;
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#20;
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rst_n = 1;
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$display("==== oh2bin 频率优化方案时序仿真 ====");
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for (int i = 0; i < WIDTH; i++) begin
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@(negedge clk);
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oh = '0;
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oh[i] = 1'b1;
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@(negedge clk);
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if (bin_q !== ref_oh2bin(oh)) begin
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$display("[ERROR] oh=%b, bin=%0d, ref=%0d", oh, bin_q, ref_oh2bin(oh));
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end else begin
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$display("[PASS] oh=%b, bin=%0d", oh, bin_q);
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end
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end
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// 非法输入测试
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@(negedge clk);
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oh = '0;
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@(negedge clk);
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$display("[INFO] all zero input, bin=%0d", bin_q);
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@(negedge clk);
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oh = '1;
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@(negedge clk);
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$display("[INFO] all one input, bin=%0d", bin_q);
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$display("==== 测试结束 ====");
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$finish;
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end
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endmodule
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