84 lines
2.6 KiB
Systemverilog
84 lines
2.6 KiB
Systemverilog
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// 同步FIFO模块，可参数化配置
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module fifo_sync #(
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parameter DATA_WIDTH = 8, // 数据位宽
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parameter DEPTH = 16, // FIFO深度
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parameter USE_RAM = 0, // 是否使用RAM存储（0: 寄存器数组, 1: RAM）
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parameter OUT_REG = 1 // 输出是否为reg型（1: 输出寄存器, 0: 直通）
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)(
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input wire clk,
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input wire rst_n,
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input wire wr_en,
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input wire [DATA_WIDTH-1:0] din,
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input wire rd_en,
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output wire [DATA_WIDTH-1:0] dout,
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output wire empty,
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output wire full,
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output wire [$clog2(DEPTH):0] data_count
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);
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localparam ADDR_WIDTH = $clog2(DEPTH);
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reg [ADDR_WIDTH:0] wr_ptr, rd_ptr;
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reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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reg [DATA_WIDTH-1:0] dout_reg;
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wire [DATA_WIDTH-1:0] dout_wire;
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// 写操作
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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wr_ptr <= 0;
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end else if (wr_en && !full) begin
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wr_ptr <= wr_ptr + 1'b1;
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end
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end
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// 读操作
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rd_ptr <= 0;
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end else if (rd_en && !empty) begin
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rd_ptr <= rd_ptr + 1'b1;
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end
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end
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// 数据计数
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assign data_count = wr_ptr - rd_ptr;
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assign empty = (wr_ptr == rd_ptr);
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assign full = (data_count == DEPTH);
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generate
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if (USE_RAM) begin : USE_RAM_BLOCK
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// RAM实现（可替换为实际RAM IP）
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always @(posedge clk) begin
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if (wr_en && !full)
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mem[wr_ptr[ADDR_WIDTH-1:0]] <= din;
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end
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assign dout_wire = mem[rd_ptr[ADDR_WIDTH-1:0]];
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end else begin : USE_REG_BLOCK
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// 寄存器数组实现
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always @(posedge clk) begin
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if (wr_en && !full)
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mem[wr_ptr[ADDR_WIDTH-1:0]] <= din;
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end
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assign dout_wire = mem[rd_ptr[ADDR_WIDTH-1:0]];
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end
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endgenerate
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// 输出寄存器可选
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generate
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if (OUT_REG) begin : OUT_REG_BLOCK
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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dout_reg <= {DATA_WIDTH{1'b0}};
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else if (rd_en && !empty)
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dout_reg <= dout_wire;
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end
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assign dout = dout_reg;
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end else begin : OUT_WIRE_BLOCK
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assign dout = dout_wire;
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end
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endgenerate
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endmodule
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