// =============================================================
// 测试模块：oh2bin_tb
// 功能描述：onehot到bin编码器仿真测试，默认频率优化方案
// 仿真时钟频率：1GHz，周期1ns
// =============================================================
`timescale 1ns/1ps

module oh2bin_tb;
    parameter WIDTH = 8;
    parameter BINW = $clog2(WIDTH);

    logic clk;
    logic rst_n;
    logic [WIDTH-1:0] oh;
    logic [BINW-1:0]  bin;
    logic [BINW-1:0]  bin_q;

    // 实例化被测模块，AREA_OPT=0为频率优化方案
    oh2bin #(
        .WIDTH(WIDTH),
        .AREA_OPT(0)
    ) dut (
        .oh(oh),
        .bin(bin)
    );

    // 时钟生成
    // 仿真时钟频率：1GHz，周期1ns
    initial clk = 0;
    always #0.5 clk = ~clk; // 1ns周期，1GHz

    // 采样输出
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            bin_q <= '0;
        else
            bin_q <= bin;
    end

    // 参考模型
    function [BINW-1:0] ref_oh2bin(input [WIDTH-1:0] oh_in);
        integer i;
        ref_oh2bin = '0;
        for (i = 0; i < WIDTH; i = i + 1) begin
            if (oh_in[i]) ref_oh2bin = i[BINW-1:0];
        end
    endfunction

    initial begin
        rst_n = 0;
        oh = '0;
        #20;
        rst_n = 1;
        $display("==== oh2bin 频率优化方案时序仿真 ====");
        for (int i = 0; i < WIDTH; i++) begin
            @(negedge clk);
            oh = '0;
            oh[i] = 1'b1;
            @(negedge clk);
            if (bin_q !== ref_oh2bin(oh)) begin
                $display("[ERROR] oh=%b, bin=%0d, ref=%0d", oh, bin_q, ref_oh2bin(oh));
            end else begin
                $display("[PASS]  oh=%b, bin=%0d", oh, bin_q);
            end
        end
        // 非法输入测试
        @(negedge clk);
        oh = '0;
        @(negedge clk);
        $display("[INFO] all zero input, bin=%0d", bin_q);
        @(negedge clk);
        oh = '1;
        @(negedge clk);
        $display("[INFO] all one input, bin=%0d", bin_q);
        $display("==== 测试结束 ====");
        $finish;
    end
endmodule