AlderLake Platform Sample Code: AlderLake PlatformSample Package

AlderLake Platform Sample Code
AlderLake PlatformSample Package

1 - Introduction

2 - Platform Sample Module

3 - Build Introduction

4 - MiscInfo

5 - Power Button Override

6 - Post Code

Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: 1 - Introduction

  • AlderLake PlatformSample Package
1 - Introduction

Purpose

The purpose of this document is to describe the external architecture and interfaces provided in the Platform Sample Package.

Note
Platform Sample Code specifications are auto generated via doxygen


AlderLake Platform Sample Code: 2 - Platform Sample Module

  • AlderLake PlatformSample Package
2 - Platform Sample Module

2.1 - SerialIo I2C Devices

Steps for changing SerialIoDevice location (I2C or SPI Bus) & adding new location (I2C or SPI Bus) for SerialIoDevice & adding new type of I2C or SPI device.

Introduction of Main Files

FILE | DESCRIPTION
SetupVariable.h | Defined name of each SerialIo Bus and Device for clearly use, and sync into SerialIoDevices.asl
PchSetup.hfr | Control SerialIo Devices Display behavior in BIOS setup.

This is Current 8 Bits Map of I2C Devices for combinedly use in "PchSetup.hfr"

I2C DEVICES | BIT0 ~ BIT7
SERIAL_IO_I2C_TOUCHPAD | 0x01
SERIAL_IO_I2C_TOUCHPANEL | 0x02
SERIAL_IO_I2C_UCMC | 0x04
4th_SERIAL_IO_I2C_DEVICE_NONE | 0x08
5th_SERIAL_IO_I2C_DEVICE_NONE | 0x10
6th_SERIAL_IO_I2C_DEVICE_NONE | 0x20
7th_SERIAL_IO_I2C_DEVICE_NONE | 0x40
8th_SERIAL_IO_I2C_DEVICE_NONE | 0x80

This is Current 8 Bits Map of SPI Devices for combinedly use in "PchSetup.hfr"

SPI DEVICES | BIT0 ~ BIT7
SERIAL_IO_SPI_FINGERPRINT | 0x01
2nd_SERIAL_IO_SPI_DEVICE_NONE | 0x02
3rd_SERIAL_IO_SPI_DEVICE_NONE | 0x04
4th_SERIAL_IO_SPI_DEVICE_NONE | 0x08
5th_SERIAL_IO_SPI_DEVICE_NONE | 0x10
6th_SERIAL_IO_SPI_DEVICE_NONE | 0x20
7th_SERIAL_IO_SPI_DEVICE_NONE | 0x40
8th_SERIAL_IO_SPI_DEVICE_NONE | 0x80

Examples for Reference

01. Steps for changing SerialIoDevice location (I2C or SPI Bus)

Ex : Platform BoardIdAdlX's Bus I2C4 supported Touch Pad and Touch Panel at same time, and PchI2cTouchPadIrqMode set to GPIO mode.

Please check DoxygenBoard.chm for the detail of Step 01.

02. Steps for adding new location (I2C or SPI Bus) for SerialIoDevice**

Ex : Create new Bus as I2C6, it must be store related info under the Scope of Bus.

Please check DoxygenBoard.chm for the detail of Step 02.

03. Steps for adding new type of I2C or SPI device**

Ex : Add new SPI Device as EyesPrint which is Bit2 in SPI_2 BUS Bitmap, Link to related page and variable and page.

AlderLakePlatSamplePkg\Setup\PchSetup.hfr

#define SERIAL_IO_SPI_FINGERPRINT 0x1
#define SERIAL_IO_SPI_EYESPRINT 0x2 // New Define in "SetupVariable.h"
suppressif NOT ideqvallist SETUP_DATA.PchSpiSensorDevicePort[SERIAL_IO_SPI2] == 2 3 ; <-- *This is a BitMap to judge present Bus whether approved to access this Form in BiosSetup.*
goto EYES_PRINT_FORM_ID, <-- *From & Veriables please create by youself.*
...endif;


AlderLake Platform Sample Code: 3 - Build Introduction

  • AlderLake PlatformSample Package
3 - Build Introduction

The detail for Build Introduction Please check DoxygenBoard.md

Summary for feature switches:

PCDs declared in DEC for efi files

PCDs consumed by DSC or FDF for EFI files (with default setting) | DESCRIPTION
gPlatformModuleTokenSpaceGuid.PcdIccOverClockingBinEnable|TRUE | #IccOverClocking.efi
gPlatformModuleTokenSpaceGuid.PcdUsbFnEnable|TRUE | #UsbDeviceDxe.efi

Summary the paths of all Binary as below, depends on platform design some of them may not be required:

  • AlderLakePlatSamplePkg\Tools\RomImage\*.*
  • AlderLakePlatSamplePkg\Tools\ToolScripts\BpmGen\*.*
  • AlderLakePlatSamplePkg\Tools\ToolScripts\FitGen\*.*
  • AlderLakePlatSamplePkg\Tools\ToolScripts\SignFv\*.* (for SignFvPlatform.bat and keys)


AlderLake Platform Sample Code: 4 - MiscInfo

  • AlderLake PlatformSample Package
4 - MiscInfo
  1. PlatformInitAdvancedPreMem module will install some policy functions for MRC to consume and if those functions were not in code cache region MRC will run slowly and impact both boot time and S3 resume time. Please ensure this module will be always in code cache coverage (according to cache initialization and adjust this module in flash map)
  2. The Secondary NvRam term can be used to describe CMOS as like in RVP BIOS, but it can be EMMC or some other non-volatile memory other than EFI Variable.


AlderLake Platform Sample Code: 5 - Power Button Override

  • AlderLake PlatformSample Package
5 - Power Button Override

Both pre-OS & OS via PCH register programming are enabled 10 seconds override feature but It's not easy to observe in pre-OS phase, because in pre-OS phase Power Button SMI will be triggered first with system shutdown before 10 seconds override timer expiration.

1) Under UEFI Shell : Upon power button press, system goes to shutdown state immediately.

2) Under OS: Upon power button press, OS will perform actions according to OS design (ex: user confirmation with a few seconds of power button pressing).

Until 10 seconds after power button keeping pressed, system goes to shutdown state.


AlderLake Platform Sample Code: 6 - Post Code

  • AlderLake PlatformSample Package
6 - Post Code

  • Post code format aligns to Silicon definition

    Actual Post code displayed will be 16 bits(4 Bytes). Upper 4 bits will be added by Base PostCode Library(either by FSP or EDKII).

    Example : Let's assume Post code as 0xWXYZ

  • Update for platform code

    XYZ is added by component

    W indicate the phase BIOS is running. 0: SEC/PEI; 1: DXE

Post Code | Progress Code | Description
0x0010 | PEI_CORE_STARTED | Stared Core
0x0011 | PEI_CAR_CPU_INIT | Init Car CPU
0x001D | PEI_MEMORY_SPD_READ | Read SPD Memory
0x001E | PEI_MEMORY_PRESENCE_DETECT | Detect Memory Presence
0x001F | PEI_MEMORY_TIMING | Memory Timing
0x0020 | PEI_MEMORY_CONFIGURING | Memory Configuring
0x0021 | PEI_MEMORY_INIT | Init Memory
0x0031 | PEI_MEMORY_INSTALLED | Installed Memory
0x0032 | PEI_CPU_INIT | CPU Init
0x0033 | PEI_CPU_CACHE_INIT | Init CPU Cache
0x0034 | PEI_CPU_BSP_SELECT | Select CPU BSP
0x0035 | PEI_CPU_AP_INIT | Init CPU AP
0x0036 | PEI_CPU_SMM_INIT | Init CPU SMM
0x0037 | PEI_MEM_NB_INIT | Init Memory NB
0x003B | PEI_MEM_SB_INIT | Init Memory SB
0x004F | PEI_DXE_IPL_STARTED | Started PEI DXE IPL
0x00F0 | PEI_RECOVERY_AUTO | Auto Recovery
0x00F1 | PEI_RECOVERY_USER | User Recovery
0x00F2 | PEI_RECOVERY_STARTED | Started Recovery
0x00F3 | PEI_RECOVERY_CAPSULE_FOUND | Found Recovery Capsule
0x00F4 | PEI_RECOVERY_CAPSULE_LOADED | Loaded Recovery Capsule
0x00E0 | PEI_S3_STARTED | Start S3
0x00E1 | PEI_S3_BOOT_SCRIPT | S3 Boot Script
0x00E2 | PEI_S3_VIDEO_REPOST | Repost S3 Video
0x00E3 | PEI_S3_OS_WAKE | Wake S3 OS
0x1060 | DXE_CORE_STARTED | Started Core
0x1062 | DXE_SBRUN_INIT | Init SBRUN
0x1068 | DXE_NB_HB_INIT | Init NB HB
0x1069 | DXE_NB_INIT | Init NB
0x106A | DXE_NB_SMM_INIT | Init NB SMM
0x1070 | DXE_SB_INIT | SInit SB
0x1071 | DXE_SB_SMM_INIT | Init SB SMM
0x1072 | DXE_SB_DEVICES_INIT | Init SB Device
0x1090 | DXE_BDS_STARTED | Started BDS
0x1092 | DXE_PCI_BUS_BEGIN | Begin PCI BUS
0x1093 | DXE_PCI_BUS_HPC_INIT | Init HPC BUS
0x1094 | DXE_PCI_BUS_ENUM | Enum PCI BUS
0x1095 | DXE_PCI_BUS_REQUEST_RESOURCES | Request PCI BUS Resources
0x1096 | DXE_PCI_BUS_ASSIGN_RESOURCES | Assign PCI BUS Resources
0x1097 | DXE_CON_OUT_CONNECT | CON OUT Connect
0x1098 | DXE_CON_IN_CONNECT | CON IN Connect
0x1099 | DXE_SIO_INIT | Init SIO
0x109A | DXE_USB_BEGIN | Begin USB
0x109B | DXE_USB_RESET | Reset USB
0x109C | DXE_USB_DETECT | Detect USB
0x109D | DXE_USB_ENABLE | Enable USB
0x10A1 | DXE_IDE_BEGIN | Begin IDE
0x10A2 | DXE_IDE_RESET | Reset IDE
0x10A3 | DXE_IDE_DETECT | Detect IDE
0x10A4 | DXE_IDE_ENABLE | Enable IDE
0x10A5 | DXE_SCSI_BEGIN | Begin SCSI
0x10A6 | DXE_SCSI_RESET | Reset SCSI
0x10A7 | DXE_SCSI_DETECT | Detect SCSI
0x10A8 | DXE_SCSI_ENABLE | Enable SCSI
0x10AB | DXE_SETUP_START | Start Setup
0x10AC | DXE_SETUP_INPUT_WAIT | Wait Setup Input
0x10AD | DXE_READY_TO_BOOT | Ready To Boot
0x10AE | DXE_LEGACY_BOOT | Legacy Boot
0x10AF | DXE_EXIT_BOOT_SERVICES | Exit Boot Services
0x10B0 | RT_SET_VIRTUAL_ADDRESS_MAP_BEGIN | Begin Set RT Virtual Address Map
0x10B1 | RT_SET_VIRTUAL_ADDRESS_MAP_END | End Set RT Virtual Address Map
0x10B2 | DXE_LEGACY_OPROM_INIT | Init Legacy OPROM
0x10B3 | DXE_RESET_SYSTEM | Reset System
0x10B4 | DXE_USB_HOTPLUG | HotPlug USB
0x10B5 | DXE_PCI_BUS_HOTPLUG | HotPlug PCI BUS
0x0050 | PEI_MEMORY_INVALID_TYPE | Invalid Memory Type
0x0050 | PEI_MEMORY_INVALID_SPEED | Invalid Memory Speed
0x0051 | PEI_MEMORY_SPD_FAIL | SPD Memory Fail
0x0052 | PEI_MEMORY_INVALID_SIZE | Invalid Memory Size
0x0052 | PEI_MEMORY_MISMATCH | Mismatch Memory
0x0053 | PEI_MEMORY_NOT_DETECTED | Not Detected Memory
0x0053 | PEI_MEMORY_NONE_USEFUL | None Useful Memory
0x0054 | PEI_MEMORY_ERROR | Memory Error
0x0055 | PEI_MEMORY_NOT_INSTALLED | Not Installed Memory
0x0056 | PEI_CPU_INVALID_TYPE | Invalid CPU Type
0x0056 | PEI_CPU_INVALID_SPEED | Invalid CPU Speed
0x0057 | PEI_CPU_MISMATCH | Mismatch CPU
0x0058 | PEI_CPU_SELF_TEST_FAILED | Self CPU Tsst Failed
0x0058 | PEI_CPU_CACHE_ERROR | CPU Cache Error
0x0059 | PEI_CPU_MICROCODE_UPDATE_FAILED | CPU Microcode Update Failed
0x0059 | PEI_CPU_NO_MICROCODE | No CPU Microcode
0x005A | PEI_CPU_INTERNAL_ERROR | Internal CPU Error
0x005A | PEI_CPU_ERROR | CPU Error
0x005B | PEI_RESET_NOT_AVAILABLE | Not Available Reset
0x00F8 | PEI_RECOVERY_PPI_NOT_FOUND | Not Found PPI Recovery
0x00F9 | PEI_RECOVERY_NO_CAPSULE | No Capsule Recovery
0x00FA | PEI_RECOVERY_INVALID_CAPSULE | Invalid Capsule Recovery
0x00E8 | PEI_MEMORY_S3_RESUME_FAILED | Memory S3 Resume Failed
0x00E9 | PEI_S3_RESUME_PPI_NOT_FOUND | S3 Resume PPI Not Found
0x00EA | PEI_S3_BOOT_SCRIPT_ERROR | S3 Boot Script Error
0x00EB | PEI_S3_OS_WAKE_ERROR | S3 OS Wake Error
0x1058 | DXE_CPU_SELF_TEST_FAILED | Self CPU Test Failed
0x10D1 | DXE_NB_ERROR | NB Error
0x10D2 | DXE_SB_ERROR | SB Error
0x10D3 | DXE_ARCH_PROTOCOL_NOT_AVAILABLE | Not Available ARCH Protocol
0x10D4 | DXE_PCI_BUS_OUT_OF_RESOURCES | Out of PCI BUS Resources
0x10D5 | DXE_LEGACY_OPROM_NO_SPACE | No Legacy OPROM Space
0x10D6 | DXE_NO_CON_OUT | NO CON OUT
0x10D7 | DXE_NO_CON_IN | NO CON IN
0x10D8 | DXE_INVALID_PASSWORD | Invalid Password
0x10D9 | DXE_BOOT_OPTION_LOAD_ERROR | Boot Option Laod Error
0x10DA | DXE_BOOT_OPTION_FAILED | Boot Option Failed
0x10DB | DXE_FLASH_UPDATE_FAILED | Falsh Update Failed
0x10DC | DXE_RESET_NOT_AVAILABLE | Not Available Reset
  • Other post code format fully aligns to Silicon definition.

  • Platform Post code definition

    PostCode = XYZZ

    X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE \ Y - "6"=platform driver, "5"=board driver \ ZZ - "00"=entry, "7F"=exit

Other Post Code

Post Code | Progress Code | Description
0xD500 | BOARD_INIT_PREMEM_ENTRY | Board Init Premem Entry
0xD57F | BOARD_INIT_PREMEM_EXIT | Board Init Premem Exit
0xD600 | PLATFORM_INIT_PREMEM_ENTRY | Platform Init Premem Entry
0xD67F | PLATFORM_INIT_PREMEM_EXIT | Platform Init Premem Ecit
0x9500 | BOARD_INIT_POSTMEM_ENTRY | Board Init Postmem Entry
0x957F | BOARD_INIT_POSTMEM_EXIT | Board Init Postmem Exit
0x9600 | PLATFORM_INIT_POSTMEM_ENTRY | Platform Init Postmem Entry
0x967F | PLATFORM_INIT_POSTMEM_EXIT | Platform Init Postmem Exit
0x7500 | BOARD_INIT_DXE_ENTRY | Board Init DXE Entry
0x757F | BOARD_INIT_DXE_EXIT | Board Init DXE Exit
0x7600 | PLATFORM_INIT_DXE_ENTRY | Platform Init DXE Entry
0x767F | PLATFORM_INIT_DXE_EXIT | Platform Init DXE Exit
0x8600 | PLATFORM_SMM_INIT_ENTRY | Platform SMM Init Entry
0x867F | PLATFORM_SMM_INIT_EXIT | Platform SMM Init Exit
0xB503 | BIOS_S3_ENTRY | BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
0xB504 | BIOS_S4_ENTRY | BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
0xB505 | BIOS_S5_ENTRY | BIOS S5 entry (0xB505) means BioS PC 05, to differentiate with ACPI _PTS PC

Runtime Post Code

Phase | Module/Functions | XY | ZZ | Comment
Default enabled | S3 | 00 | 03 | S3 enter in the beginning of ACPI _PTS method
 |  | B5 | 03 | S3 BIOS entry in the beginning of Sleep SMI
 |  | AB | 03 | S3 exit in the beginning of ACPI _WAK method
 | S4 | 00 | 04 | S4 enter in the beginning of ACPI _PTS method
 |  | B5 | 04 | S4 BIOS entry in the beginning of Sleep SMI
 |  | AB | 04 | S4 exit in the beginning of ACPI _WAK method
 | S5 | 00 | 05 | S5 enter in the beginning of ACPI _PTS method
 |  | B5 | 05 | S5 BIOS entry in the beginning of Sleep SMI
 |  | AB | 05 | S5 exit in the beginning of ACPI _WAK method
 | S0ix Sleep | 00 | C5 | Low Power S0 Idle _DSM: Display Off Notification
 |  | 01 | C5 | Notify EC in "Low Power S0 Idle _DSM: Low Power S0 Entry Notification"
 | S0ix wake | AA | C5 | Notify EC in "Low Power S0 Idle _DSM: Low Power S0 Exit Notification"
 |  | AB | C5 | Low Power S0 Idle _DSM: Display On Notification
Need to enable BIOS ACPI debug | HID Event Filter | 00 | 5C | Send HID event/wake notification
 |  | 00 | 5D | Sleep Button notification
 | GUAM | AB | E1 | Exit CS
 |  | 00 | E0 | Enter CS
 | EC |  | 37 | _Q37 event (power source change sci)
 |  |  | 40 | _Q40 (dock complete)
 |  |  | 41 | _Q41 (dock Surprise Removal)
 |  |  | 79 | Q76/Q79 event (USB Type C events)
 |  |  | ## (TDP Value) | Max TDP value, only displayed with specific key combination (CAS+M) & cTDP is enabled
 |  |  | E0 | USB TypeC OPM write to EC
 | PCIe | ## (## for event counts) | 01 | _L61 event (PCI Express hotplug wake event) counts
 | TBT | C2 | C2 | TBT notification


AlderLake Platform Sample Code: Todo List

Todo List
File BasePlatformVariableLib.h
ADD DESCRIPTION
File EcCommands.h
ADD DESCRIPTION
File PeiPlatformLib.h
ADD DESCRIPTION
File PeiReadWriteVariableLib.h
ADD DESCRIPTION
Member PlatformInitAdvancedPreMemEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
it should be moved to Si Pkg.


AlderLake Platform Sample Code: Modules

Modules
Here is a list of all modules:
[detail level 123]
▼ Create TCG ComPacket Functions | These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
▼ Create TCG SubPacket Functions | These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Atom Functions | These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Sequence Token Functions | These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Create TCG Control Token Functions | These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification
Parse TCG ComPacket Functions | These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
Common Create TCG Utility Functions | These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification
Parse TCG ComPacket Utility Functions | These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification


AlderLake Platform Sample Code: Create TCG ComPacket Functions

Modules | Classes | Typedefs | Functions
Create TCG ComPacket Functions

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG ComPacket Functions:

Modules

Create TCG SubPacket Functions
These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Classes

struct _TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...

Typedefs

typedef struct _TcgCreateStruct TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...

Functions

TcgResult TCG_CALL | tcgInitTcgCreateStruct (TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct. More...
TcgResult TCG_CALL | tcgStartComPacket (TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure. More...
TcgResult TCG_CALL | tcgStartPacket (TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure. More...
TcgResult TCG_CALL | tcgStartSubPacket (TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndSubPacket (TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndPacket (TcgCreateStruct *createStruct)
Ends the current Packet in the data structure. More...
TcgResult TCG_CALL | tcgEndComPacket (TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret. More...

Detailed Description

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Typedef Documentation

◆ TcgCreateStruct

typedef struct _TcgCreateStruct TcgCreateStruct

Structure that is used to build the Tcg ComPacket.

It contains the start buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgCreateStruct

Function Documentation

◆ tcgEndComPacket()

TcgResult TCG_CALL tcgEndComPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size
 | ) |  |

Ends the ComPacket in the data structure and ret.

Parameters
createStruct | [in/out] Structure used to end the Tcg ComPacket
size | [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.

◆ tcgEndPacket()

TcgResult TCG_CALL tcgEndPacket ( TcgCreateStruct * createStruct )

Ends the current Packet in the data structure.

Parameters
createStruct [in/out] Structure used to end the current Tcg Packet

◆ tcgEndSubPacket()

TcgResult TCG_CALL tcgEndSubPacket ( TcgCreateStruct * createStruct )

Ends the current SubPacket in the data structure.

This function will also perform the 4-byte padding required for Subpackets.

Parameters
createStruct [in/out] Structure used to end the current Tcg SubPacket

◆ tcgInitTcgCreateStruct()

TcgResult TCG_CALL tcgInitTcgCreateStruct | ( | TcgCreateStruct * | createStruct,
 |  | void * | buffer,
 |  | UINT32 | bufferSize
 | ) |  |

Required to be called before calling any other Tcg functions with the TcgCreateStruct.

Initializes the packet variables to NULL. Additionally, the buffer will be memset.

Parameters
createStruct | [in/out] Structure to initialize
[in] | buffer | Buffer allocated by client of library. It will contain the Tcg encoded packet. This cannot be null.
[in] | bufferSize | Size of buffer provided. It cannot be 0.

◆ tcgStartComPacket()

TcgResult TCG_CALL tcgStartComPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension
 | ) |  |

Encodes the ComPacket header to the data structure.

Parameters
createStruct | [in/out] Structure used to build Tcg Compacket
[in] | comId | ComID of the Tcg ComPacket.
[in] | comIdExtension | ComID Extension of the Tcg ComPacket.

◆ tcgStartPacket()

TcgResult TCG_CALL tcgStartPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 | tsn,
 |  | UINT32 | hsn,
 |  | UINT32 | seqNumber,
 |  | UINT16 | ackType,
 |  | UINT32 | ack
 | ) |  |

Starts a new ComPacket in the data structure.

Parameters
createStruct | [in/out] Structure used to add Tcg Packet
[in] | tsn | Packet Tper session number
[in] | hsn | Packet Host session number
[in] | seqNumber | Packet Sequence Number
[in] | ackType | Packet Acknowledge Type
[in] | ack | Packet Acknowledge

◆ tcgStartSubPacket()

TcgResult TCG_CALL tcgStartSubPacket | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | kind
 | ) |  |

Starts a new SubPacket in the data structure.

Parameters
createStruct | [in/out] Structure used to start Tcg SubPacket
[in] | kind | SubPacket kind


AlderLake Platform Sample Code: Create TCG SubPacket Functions

Modules
Create TCG SubPacket Functions
Create TCG ComPacket Functions

These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG SubPacket Functions:

Modules

Create TCG Atom Functions
These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.
Create TCG Sequence Token Functions
These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.
Create TCG Control Token Functions
These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Detailed Description

These functions encode tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.


AlderLake Platform Sample Code: Create TCG Atom Functions

Functions
Create TCG Atom Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Atom Functions:

Functions

TcgResult TCG_CALL | tcgAddRawByte (TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure. More...
TcgResult TCG_CALL | tcgAddByteSequence (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure. More...
TcgResult TCG_CALL | tcgAddInteger (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT8 (TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT16 (TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT32 (TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT64 (TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddBOOLEAN (TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure. More...
TcgResult TCG_CALL | tcgAddTcgUid (TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure. More...

Detailed Description

These functions encode simple atom tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

◆ tcgAddBOOLEAN()

TcgResult TCG_CALL tcgAddBOOLEAN | ( | TcgCreateStruct * | createStruct,
 |  | BOOLEAN | value
 | ) |  |

Adds a BOOLEAN to the data structure.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | value | BOOLEAN value to add

◆ tcgAddByteSequence()

TcgResult TCG_CALL tcgAddByteSequence | ( | TcgCreateStruct * | createStruct,
 |  | const void * | data,
 |  | UINT32 | dataSize,
 |  | BOOLEAN | continued
 | ) |  |

Adds the data parameter as a byte sequence to the data structure.

Parameters
createStruct | [in/out] Structure used to add the byte sequence
[in] | data | Byte sequence that will be encoded and copied into data structure
[in] | dataSize | Length of data provided
[in] | continued | TRUE if byte sequence is continued or FALSE if the data contains the entire byte sequence to be encoded

◆ tcgAddInteger()

TcgResult TCG_CALL tcgAddInteger | ( | TcgCreateStruct * | createStruct,
 |  | const void * | data,
 |  | UINT32 | dataSize,
 |  | BOOLEAN | signedInteger
 | ) |  |

Adds an arbitrary-length integer to the data structure.

The integer will be encoded using the shortest possible atom.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | data | Integer in host byte order that will be encoded and copied into data structure
[in] | dataSize | Length in bytes of the data provided
[in] | signedInteger | TRUE if the integer is signed or FALSE if the integer is unsigned

◆ tcgAddRawByte()

TcgResult TCG_CALL tcgAddRawByte | ( | TcgCreateStruct * | createStruct,
 |  | UINT8 | byte
 | ) |  |

Adds a single raw token byte to the data structure.

Parameters
createStruct | [in/out] Structure used to add the byte
[in] | byte | Byte to add

◆ tcgAddTcgUid()

TcgResult TCG_CALL tcgAddTcgUid | ( | TcgCreateStruct * | createStruct,
 |  | TcgUid | uid
 | ) |  |

Adds a TcgUid to the data structure.

Parameters
createStruct | [in/out] Structure used to add the TcgUid
[in] | uid | TcgUid value to add

◆ tcgAddUINT16()

TcgResult TCG_CALL tcgAddUINT16 | ( | TcgCreateStruct * | createStruct,
 |  | UINT16 | value
 | ) |  |

Adds a 16-bit unsigned integer to the data structure.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | value | Integer value to add

◆ tcgAddUINT32()

TcgResult TCG_CALL tcgAddUINT32 | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 | value
 | ) |  |

Adds a 32-bit unsigned integer to the data structure.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | value | Integer value to add

◆ tcgAddUINT64()

TcgResult TCG_CALL tcgAddUINT64 | ( | TcgCreateStruct * | createStruct,
 |  | UINT64 | value
 | ) |  |

Adds a 64-bit unsigned integer to the data structure.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | value | Integer value to add

◆ tcgAddUINT8()

TcgResult TCG_CALL tcgAddUINT8 | ( | TcgCreateStruct * | createStruct,
 |  | UINT8 | value
 | ) |  |

Adds an 8-bit unsigned integer to the data structure.

Parameters
createStruct | [in/out] Structure used to add the integer
[in] | value | Integer value to add


AlderLake Platform Sample Code: Create TCG Sequence Token Functions

Functions
Create TCG Sequence Token Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Sequence Token Functions:

Functions

TcgResult TCG_CALL | tcgAddStartList (TcgCreateStruct *createStruct)
Adds a Start List token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndList (TcgCreateStruct *createStruct)
Adds an End List token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartName (TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndName (TcgCreateStruct *createStruct)
Adds an End Name token to the data structure. More...

Detailed Description

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

◆ tcgAddEndList()

TcgResult TCG_CALL tcgAddEndList ( TcgCreateStruct * createStruct )

Adds an End List token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddEndName()

TcgResult TCG_CALL tcgAddEndName ( TcgCreateStruct * createStruct )

Adds an End Name token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddStartList()

TcgResult TCG_CALL tcgAddStartList ( TcgCreateStruct * createStruct )

Adds a Start List token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddStartName()

TcgResult TCG_CALL tcgAddStartName ( TcgCreateStruct * createStruct )

Adds a Start Name token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token


AlderLake Platform Sample Code: Create TCG Control Token Functions

Functions
Create TCG Control Token Functions
Create TCG ComPacket Functions » Create TCG SubPacket Functions

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification. More...

Collaboration diagram for Create TCG Control Token Functions:

Functions

TcgResult TCG_CALL | tcgAddCall (TcgCreateStruct *createStruct)
Adds a Call token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfData (TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfSession (TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartTransaction (TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndTransaction (TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure. More...

Detailed Description

These functions encode sequence tokens contained in a SubPacket as defined in the TCG Storage Architecture Core Specification.

Function Documentation

◆ tcgAddCall()

TcgResult TCG_CALL tcgAddCall ( TcgCreateStruct * createStruct )

Adds a Call token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddEndOfData()

TcgResult TCG_CALL tcgAddEndOfData ( TcgCreateStruct * createStruct )

Adds an End of Data token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddEndOfSession()

TcgResult TCG_CALL tcgAddEndOfSession ( TcgCreateStruct * createStruct )

Adds an End of Session token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddEndTransaction()

TcgResult TCG_CALL tcgAddEndTransaction ( TcgCreateStruct * createStruct )

Adds an End Transaction token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token

◆ tcgAddStartTransaction()

TcgResult TCG_CALL tcgAddStartTransaction ( TcgCreateStruct * createStruct )

Adds a Start Transaction token to the data structure.

Parameters
createStruct [in/out] Structure used to add the token


AlderLake Platform Sample Code: _TcgCreateStruct Struct Reference

Public Attributes | List of all members
_TcgCreateStruct Struct Reference
Create TCG ComPacket Functions

Structure that is used to build the Tcg ComPacket. More...

#include <TcgCore.h>

Public Attributes

void * | buffer
Buffer allocated and freed by the client of the Tcg library. More...
UINT32 | bufferSize
Size of the buffer provided.
TcgComPacket * | comPacket
Pointer to the start of the Tcg ComPacket. More...
TcgPacket * | curPacket
Current Tcg Packet that is being created. More...
TcgSubPacket * | curSubPacket
Current Tcg SubPacket that is being created. More...
BOOLEAN | dryRun
Flag used to indicate if the buffer of the structure should be filled out. More...

Detailed Description

Structure that is used to build the Tcg ComPacket.

It contains the start buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgCreateStruct

Definition at line 135 of file TcgCore.h.

Member Data Documentation

◆ buffer

void* _TcgCreateStruct::buffer

Buffer allocated and freed by the client of the Tcg library.

This is the buffer that shall contain the final Tcg encoded compacket.

Definition at line 140 of file TcgCore.h.

◆ comPacket

TcgComPacket* _TcgCreateStruct::comPacket

Pointer to the start of the Tcg ComPacket.

It should point to a location within buffer.

Definition at line 150 of file TcgCore.h.

◆ curPacket

TcgPacket* _TcgCreateStruct::curPacket

Current Tcg Packet that is being created.

It should point to a location within buffer.

Definition at line 155 of file TcgCore.h.

◆ curSubPacket

TcgSubPacket* _TcgCreateStruct::curSubPacket

Current Tcg SubPacket that is being created.

It should point to a location within buffer.

Definition at line 160 of file TcgCore.h.

◆ dryRun

BOOLEAN _TcgCreateStruct::dryRun

Flag used to indicate if the buffer of the structure should be filled out.

This is intended to be used to support a use-case where the client of library can perform all the desired tcg calls to determine what the actual size of the final compacket will be. Then the client can allocate the required buffer size and re-run the tcg calls. THIS MAY NOT BE IMPLEMENTED... REQUIRES MORE THOUGHT BECAUSE YOU CANNOT SOLVE ISSUE FOR RECEIVE

Definition at line 169 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


AlderLake Platform Sample Code: Member List

_TcgCreateStruct Member List

This is the complete list of members for _TcgCreateStruct, including all inherited members.

buffer | _TcgCreateStruct
bufferSize | _TcgCreateStruct
comPacket | _TcgCreateStruct
curPacket | _TcgCreateStruct
curSubPacket | _TcgCreateStruct
dryRun | _TcgCreateStruct


AlderLake Platform Sample Code: Parse TCG ComPacket Functions

Classes | Typedefs | Functions
Parse TCG ComPacket Functions

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Classes

struct | _TcgParseStruct
Structure that is used to parse the Tcg response received. More...
struct | _TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

Typedefs

typedef struct _TcgParseStruct | TcgParseStruct
Structure that is used to parse the Tcg response received. More...
typedef struct _TcgToken | TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Functions

TcgResult TCG_CALL | tcgInitTcgParseStruct (TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response. More...
TcgResult TCG_CALL | tcgGetNextToken (TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetNextTokenType (TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetAtomInfo (const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom. More...
const UINT8 *TCG_CALL | tcgGetTokenByteSequence (const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetTokenUINT64 (const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetNextUINT8 (TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT16 (TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT32 (TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT64 (TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextBOOLEAN (TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextTcgUid (TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextByteSequence (TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextCall (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfData (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfSession (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...

Detailed Description

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Typedef Documentation

◆ TcgParseStruct

typedef struct _TcgParseStruct TcgParseStruct

Structure that is used to parse the Tcg response received.

It contains the response buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed. This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgParseStruct

Function Documentation

◆ tcgGetAtomInfo()

TcgResult TCG_CALL tcgGetAtomInfo | ( | const TcgToken * | tcgToken,
 |  | UINT32 * | headerLength,
 |  | UINT32 * | dataLength,
 |  | UINT8 * | byteOrInt,
 |  | UINT8 * | signOrCont
 | ) |  |

Retrieves information about a simple token containing an atom.

Parameters
tcgToken | [in/out] TCG token containing simple token atom to retrieve
[out] | headerLength | Length of token header.

This is the number of bytes from the start of the token up to the beginning of the data.

Parameters
[out] dataLength Length of data.

This is the size of the byte or integer data following the token header.

Parameters
[out] | byteOrInt | Flag indicating whether the atom is a byte sequence (TCG_ATOM_TYPE_BYTE) or integer (TCG_ATOM_TYPE_INTEGER).
[out] | signOrCont | Flag indicating whether an integer atom is a signed integer or whether a byte sequence atom is continued.

◆ tcgGetNextBOOLEAN()

TcgResult TCG_CALL tcgGetNextBOOLEAN | ( | TcgParseStruct * | parseStruct,
 |  | BOOLEAN * | value
 | ) |  |

Retrieves next token in the current payload.

If it not a BOOLEAN then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
value | [in/out] BOOLEAN value retrieved from current payload

◆ tcgGetNextByteSequence()

TcgResult TCG_CALL tcgGetNextByteSequence | ( | TcgParseStruct * | parseStruct,
 |  | const void ** | data,
 |  | UINT32 * | length
 | ) |  |

Retrieves next token in the current payload.

If it is not a byte sequence, then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
[out] | data | Pointer to the beginning of the byte sequence
[out] | length | Length of the retrieved byte sequence in bytes

◆ tcgGetNextCall()

TcgResult TCG_CALL tcgGetNextCall ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Call token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextEndList()

TcgResult TCG_CALL tcgGetNextEndList ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End List token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextEndName()

TcgResult TCG_CALL tcgGetNextEndName ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End Name token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextEndOfData()

TcgResult TCG_CALL tcgGetNextEndOfData ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End of Data token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextEndOfSession()

TcgResult TCG_CALL tcgGetNextEndOfSession ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End of Session token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextEndTransaction()

TcgResult TCG_CALL tcgGetNextEndTransaction ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not an End Transaction token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextStartList()

TcgResult TCG_CALL tcgGetNextStartList ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start List token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextStartName()

TcgResult TCG_CALL tcgGetNextStartName ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start Name token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextStartTransaction()

TcgResult TCG_CALL tcgGetNextStartTransaction ( TcgParseStruct * parseStruct )

Retrieves next token in the current payload.

If it is not a Start Transaction token, then a failure is reported.

Parameters
parseStruct [in/out] Structure used to parse received TCG response

◆ tcgGetNextTcgUid()

TcgResult TCG_CALL tcgGetNextTcgUid | ( | TcgParseStruct * | parseStruct,
 |  | TcgUid * | uid
 | ) |  |

Retrieves next token in the current payload.

If it is not a TcgUid then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
[out] | uid | TcgUid value retrieved from current payload

◆ tcgGetNextToken()

TcgResult TCG_CALL tcgGetNextToken | ( | TcgParseStruct * | parseStruct,
 |  | TcgToken * | tcgToken
 | ) |  |

Retrieves next Tcg Token from the current subpacket payload.

The first time it is called on a parse structure it starts at the first Subpacket of the first Packet.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
tcgToken | [in/out] Tcg Token that was found. Buffer was verified to guarantee the entire Token can be accessed by caller.

◆ tcgGetNextTokenType()

TcgResult TCG_CALL tcgGetNextTokenType | ( | TcgParseStruct * | parseStruct,
 |  | TcgTokenType | type
 | ) |  |

Retrieves the next TCG token from the current subpacket payload.

If the token is not of the specified type, an error is returned.

This function is intended for use with sequence and control tokens that have no payload, since it does not return the token contents.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
[in] | type | Expected TCG token type

◆ tcgGetNextUINT16()

TcgResult TCG_CALL tcgGetNextUINT16 | ( | TcgParseStruct * | parseStruct,
 |  | UINT16 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT16 then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
value | [in/out] UINT16 value retrieved from current payload

◆ tcgGetNextUINT32()

TcgResult TCG_CALL tcgGetNextUINT32 | ( | TcgParseStruct * | parseStruct,
 |  | UINT32 * | value
 | ) |  |

Retrieves next token in the current payload.

If it not a UINT32 then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
value | [in/out] UINT32 value retrieved from current payload

◆ tcgGetNextUINT64()

TcgResult TCG_CALL tcgGetNextUINT64 | ( | TcgParseStruct * | parseStruct,
 |  | UINT64 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT64 then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
value | [in/out] UINT64 value retrieved from current payload

◆ tcgGetNextUINT8()

TcgResult TCG_CALL tcgGetNextUINT8 | ( | TcgParseStruct * | parseStruct,
 |  | UINT8 * | value
 | ) |  |

Retrieves next token in the current payload.

If it is not a UINT8 then a failure is reported.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
value | [in/out] UINT8 value retrieved from current payload

◆ tcgGetTokenByteSequence()

const UINT8* TCG_CALL tcgGetTokenByteSequence | ( | const TcgToken * | tcgToken,
 |  | UINT32 * | length
 | ) |  |

Retrieves byte sequence from the Tcg Token provided.

Returns
NULL if failure occurs, otherwise pointer to beginning of byte sequence.
Parameters
tcgToken | [in/out] Tcg Token containing byte sequence value to retrieve
[out] | length | Length of the byte sequence retrieved

◆ tcgGetTokenUINT64()

TcgResult TCG_CALL tcgGetTokenUINT64 | ( | const TcgToken * | tcgToken,
 |  | UINT64 * | value
 | ) |  |

Retrieves Integer value up to 64-bits in size from the Tcg Token provided.

Parameters
tcgToken | [in/out] Tcg Token containing integer value to retrieve
value | [in/out] Integer value retrieved

◆ tcgInitTcgParseStruct()

TcgResult TCG_CALL tcgInitTcgParseStruct | ( | TcgParseStruct * | parseStruct,
 |  | const void * | buffer,
 |  | UINT32 | bufferSize
 | ) |  |

Intializes the parsing structure used to parse the Tcg response.

This must be called before using the parseStruct with any other function.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
[in] | buffer | Buffer containing TCG response
[in] | bufferSize | Size of buffer containing TCG response


AlderLake Platform Sample Code: _TcgParseStruct Struct Reference

Public Attributes | List of all members
_TcgParseStruct Struct Reference
Parse TCG ComPacket Functions

Structure that is used to parse the Tcg response received. More...

#include <TcgCore.h>

Public Attributes

const void * | buffer
Buffer allocated and freed by the client of the Tcg library. More...
UINT32 | bufferSize
Size of the buffer provided.
const TcgComPacket * | comPacket
Pointer to the start of the Tcg ComPacket. More...
const TcgPacket * | curPacket
Current Tcg Packet that is being created. More...
const TcgSubPacket * | curSubPacket
Current Tcg SubPacket that is being created. More...
const UINT8 * | curPtr
Current pointer within the current subpacket payload.

Detailed Description

Structure that is used to parse the Tcg response received.

It contains the response buffer pointer and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed. This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function. This structure should NOT be directly modified by the client of this library.

NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY

See also
tcgInitTcgParseStruct

Definition at line 671 of file TcgCore.h.

Member Data Documentation

◆ buffer

const void* _TcgParseStruct::buffer

Buffer allocated and freed by the client of the Tcg library.

This is the buffer that contains the Tcg response to decode/parse.

Definition at line 676 of file TcgCore.h.

◆ comPacket

const TcgComPacket* _TcgParseStruct::comPacket

Pointer to the start of the Tcg ComPacket.

It should point to a location within buffer.

Definition at line 686 of file TcgCore.h.

◆ curPacket

const TcgPacket* _TcgParseStruct::curPacket

Current Tcg Packet that is being created.

It should point to a location within buffer.

Definition at line 691 of file TcgCore.h.

◆ curSubPacket

const TcgSubPacket* _TcgParseStruct::curSubPacket

Current Tcg SubPacket that is being created.

It should point to a location within buffer.

Definition at line 696 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


AlderLake Platform Sample Code: Member List

_TcgParseStruct Member List

This is the complete list of members for _TcgParseStruct, including all inherited members.

buffer | _TcgParseStruct
bufferSize | _TcgParseStruct
comPacket | _TcgParseStruct
curPacket | _TcgParseStruct
curPtr | _TcgParseStruct
curSubPacket | _TcgParseStruct


AlderLake Platform Sample Code: _TcgToken Struct Reference

Public Attributes | List of all members
_TcgToken Struct Reference
Parse TCG ComPacket Functions

Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

#include <TcgCore.h>

Public Attributes

TcgTokenType | type
Describes the type of Tcg token the hdr start points to.
const UINT8 * | hdrStart
Pointer to the beginning of the header of the Tcg token.

Detailed Description

Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Definition at line 708 of file TcgCore.h.

The documentation for this struct was generated from the following file:
  • TcgCore.h


AlderLake Platform Sample Code: Member List

_TcgToken Member List

This is the complete list of members for _TcgToken, including all inherited members.

hdrStart | _TcgToken
type | _TcgToken


AlderLake Platform Sample Code: Common Create TCG Utility Functions

Functions
Common Create TCG Utility Functions

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Functions

TcgResult TCG_CALL | tcgStartMethodCall (TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided. More...
TcgResult TCG_CALL | tcgStartParameters (TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndParameters (TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndMethodCall (TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list. More...
TcgResult TCG_CALL | tcgCreateStartSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure. More...
TcgResult TCG_CALL | tcgCreateSetCPin (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified. More...
TcgResult TCG_CALL | tcgSetAuthorityEnabled (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified. More...
TcgResult TCG_CALL | tcgCreateEndSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession. More...

Detailed Description

These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Function Documentation

◆ tcgCreateEndSession()

TcgResult TCG_CALL tcgCreateEndSession | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSession,
 |  | UINT32 | tpSessionId
 | ) |  |

Creates ComPacket with EndSession.

This assumes a start session has already been opened.

Parameters
createStruct | [in/out] Structure used to add Endsession
size | [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | hostSession | Host Session ID for the Packet
[in] | tpSessionId | Tper Session ID for the Packet

◆ tcgCreateSetCPin()

TcgResult TCG_CALL tcgCreateSetCPin | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | tperSession,
 |  | UINT32 | hostSession,
 |  | TcgUid | sidRow,
 |  | const void * | password,
 |  | UINT32 | passwordSize
 | ) |  |

Creates ComPacket with a Method call that sets the PIN column for the row specified.

This assumes a start session has already been opened with the desired SP.

Parameters
createStruct | [in/out] Structure used to add method call
size | [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | tperSession | Tper Session ID for the Packet
[in] | hostSession | Host Session ID for the Packet
[in] | sidRow | UID of row of current SP to set PIN column
[in] | password | value of PIN to set
[in] | passwordSize | Size of PIN

◆ tcgCreateStartSession()

TcgResult TCG_CALL tcgCreateStartSession | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSessionId,
 |  | TcgUid | spId,
 |  | BOOLEAN | write,
 |  | UINT32 | hostChallengeLength,
 |  | const void * | hostChallenge,
 |  | TcgUid | HostSigningAuthority
 | ) |  |

Adds Start Session call to the data structure.

This creates the entire ComPacket structure and returns the size of the entire compacket in the size parameter.

Parameters
createStruct | [in/out] Structure used to add the start session call
size | [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | hostSessionId | Host Session ID
[in] | spId | Security Provider to start session with
[in] | write | Write option for start session. TRUE = start session requests write access
[in] | hostChallengeLength | Length of the host challenge. Length should be 0 if hostChallenge is NULL
[in] | hostChallenge | Host challenge for Host Signing Authority. If NULL, then no Host Challenge shall be sent.
[in] | HostSigningAuthority | Host Signing Authority used for start session. If NULL, then no Host Signing Authority shall be sent.

◆ tcgEndMethodCall()

TcgResult TCG_CALL tcgEndMethodCall ( TcgCreateStruct * createStruct )

Adds end method call (ENDDATA) to the data structure in addition to the method status list.

Parameters
createStruct [in/out] Structure used to add the method call

◆ tcgEndParameters()

TcgResult TCG_CALL tcgEndParameters ( TcgCreateStruct * createStruct )

Adds end parameters (ENDLIST) to the data structure.

Parameters
createStruct [in/out] Structure used to add the end parameters

◆ tcgSetAuthorityEnabled()

TcgResult TCG_CALL tcgSetAuthorityEnabled | ( | TcgCreateStruct * | createStruct,
 |  | UINT32 * | size,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | tperSession,
 |  | UINT32 | hostSession,
 |  | TcgUid | authorityUid,
 |  | BOOLEAN | enabled
 | ) |  |

Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.

This assumes a start session has already been opened with the desired SP.

Parameters
createStruct | [in/out] Structure used to add method call
size | [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
[in] | comId | ComID for the ComPacket
[in] | comIdExtension | Extended ComID for the ComPacket
[in] | tperSession | Tper Session ID for the Packet
[in] | hostSession | Host Session ID for the Packet
[in] | authorityUid | Authority UID to modify the "Enabled" column for
[in] | enabled | Value to set the "Enabled" column to

◆ tcgStartMethodCall()

TcgResult TCG_CALL tcgStartMethodCall | ( | TcgCreateStruct * | createStruct,
 |  | TcgUid | invokingId,
 |  | TcgUid | methodId
 | ) |  |

Adds start Method Call to the data structure using invoking id and method Id provided.

Parameters
createStruct | [in/out] Structure used to add the method call
[in] | invokingId | Invoking ID for the method call
[in] | methodId | Method ID for the method call

◆ tcgStartParameters()

TcgResult TCG_CALL tcgStartParameters ( TcgCreateStruct * createStruct )

Adds start parameters (STARTLIST) to the data structure.

Parameters
createStruct [in/out] Structure used to add the start parameters


AlderLake Platform Sample Code: Parse TCG ComPacket Utility Functions

Functions
Parse TCG ComPacket Utility Functions

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification. More...

Functions

const char *TCG_CALL | tcgTokenTypeString (TcgTokenType type)
Retrieves human-readable token type name. More...
TcgResult TCG_CALL | tcgGetMethodStatus (const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket. More...
const char *TCG_CALL | tcgMethodStatusString (UINT8 methodStatus)
Returns a human-readable string representing a method status return code. More...
TcgResult TCG_CALL | tcgGetComIds (const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response. More...
TcgResult TCG_CALL | tcgCheckComIds (const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values. More...
TcgResult TCG_CALL | tcgParseSyncSession (const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. More...
BOOLEAN TCG_CALL | tcgIsProtocolSupported (const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list. More...
BOOLEAN TCG_CALL | tcgIsLocked (const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response. More...

Detailed Description

These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens as defined in the TCG Storage Architecture Core Specification.

Function Documentation

◆ tcgCheckComIds()

TcgResult TCG_CALL tcgCheckComIds | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 | expectedComId,
 |  | UINT16 | expectedComIdExtension
 | ) |  |

Checks if the ComIDs of the response match the expected values.

Parameters
[in] | parseStruct | Structure used to parse received TCG response
[in] | expectedComId | Expected comID
[in] | expectedComIdExtension | Expected extended comID

◆ tcgGetComIds()

TcgResult TCG_CALL tcgGetComIds | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 * | comId,
 |  | UINT16 * | comIdExtension
 | ) |  |

Retrieves the comID and Extended comID of the ComPacket in the Tcg response.

It is intended to be used to confirm the received Tcg response is intended for user that received it.

Parameters
[in] | parseStruct | Structure used to parse received TCG response
comId | [in/out] comID retrieved from received ComPacket
comIdExtension | [in/out] Extended comID retrieved from received ComPacket

◆ tcgGetMethodStatus()

TcgResult TCG_CALL tcgGetMethodStatus | ( | const TcgParseStruct * | parseStruct,
 |  | UINT8 * | methodStatus
 | ) |  |

Returns the method status of the current subpacket.

Does not affect the current position in the ComPacket. In other words, it can be called whenever you have a valid SubPacket.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response
methodStatus | [in/out] Method status retrieved of the current SubPacket

◆ tcgIsLocked()

BOOLEAN TCG_CALL tcgIsLocked ( const TCG_LEVEL0_DISCOVERY_HEADER * discovery )

Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response.

Returns
TRUE = Locked is set, FALSE = Locked is false
Parameters
[in] discovery Level 0 discovery response

◆ tcgIsProtocolSupported()

BOOLEAN TCG_CALL tcgIsProtocolSupported | ( | const TCG_SUPPORTED_SECURITY_PROTOCOLS * | protocolList,
 |  | UINT16 | protocol
 | ) |  |

Determines if the protocol provided is part of the provided supported protocol list.

Returns
TRUE = protocol is supported, FALSE = protocol is not supported
Parameters
[in] | protocolList | Supported protocol list to investigate
[in] | protocol | Protocol value to determine if supported

◆ tcgMethodStatusString()

const char* TCG_CALL tcgMethodStatusString ( UINT8 methodStatus )

Returns a human-readable string representing a method status return code.

Parameters
[in] methodStatus Method status to translate to a string

◆ tcgParseSyncSession()

TcgResult TCG_CALL tcgParseSyncSession | ( | const TcgParseStruct * | parseStruct,
 |  | UINT16 | comId,
 |  | UINT16 | comIdExtension,
 |  | UINT32 | hostSessionId,
 |  | UINT32 * | tperSessionId
 | ) |  |

Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID.

If the Sync Session response parameters do not match the comID, extended ComID and host session ID then a failure is returned.

Parameters
parseStruct | [in/out] Structure used to parse received TCG response, contains Sync Session response.
[in] | comId | Expected ComID that is compared to actual ComID of response
[in] | comIdExtension | Expected Extended ComID that is compared to actual Extended ComID of response
[in] | hostSessionId | Expected Host Session ID that is compared to actual Host Session ID of response
tperSessionId | [in/out] Tper Session ID retrieved from the Sync Session response.

◆ tcgTokenTypeString()

const char* TCG_CALL tcgTokenTypeString ( TcgTokenType type )

Retrieves human-readable token type name.

Parameters
[in] type Token type to retrieve
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Class List

Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C _DEBUG_EVENT_HABDLER_PPI | This PPI contains a set of services to print message to debug output device
C _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL | I2C bus configuration management protocol
C _EFI_I2C_MASTER_PROTOCOL | I2C controller mode protocol
C _EFI_SMM_CPU_SAVE_STATE_PROTOCOL | Provides a programatic means to access SMM save state
C _EFI_USB_DEVICE_MODE_PROTOCOL | Usb Device Mode Protocol Structure
C _TcgCreateStruct | Structure that is used to build the Tcg ComPacket
C _TcgParseStruct | Structure that is used to parse the Tcg response received
C _TcgToken | Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions
C AUTHENTICATED_VARIABLE_HEADER | Single Variable Data Header Structure for Auth variable
C EFI_I2C_REQUEST_PACKET | I2C device operation
C EFI_RST_FEATURE_DATA | This variable is needed for VMD to know what Rst features are enabled on platform
C EFI_SMM_CPU_STATE | Union of CPU save-state strcutures for IA32 and X64
C EFI_SMM_CPU_STATE32 | CPU save-state strcuture for IA32 and X64
C EFI_SMM_CPU_STATE64 | This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure
C EFI_USB_INTERFACE_INFO | USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec
C VARIABLE_HEADER | Single Variable Data Header Structure
C VARIABLE_STORE_HEADER | Variable Store region header


AlderLake Platform Sample Code: _DEBUG_EVENT_HABDLER_PPI Struct Reference

List of all members
_DEBUG_EVENT_HABDLER_PPI Struct Reference

This PPI contains a set of services to print message to debug output device. More...

#include <DebugEventHandler.h>

Detailed Description

This PPI contains a set of services to print message to debug output device.

Definition at line 89 of file DebugEventHandler.h.

The documentation for this struct was generated from the following file:
  • DebugEventHandler.h


AlderLake Platform Sample Code: Member List

_DEBUG_EVENT_HABDLER_PPI Member List

This is the complete list of members for _DEBUG_EVENT_HABDLER_PPI, including all inherited members.


AlderLake Platform Sample Code: _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Struct Reference

Public Attributes | List of all members
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Struct Reference

I2C bus configuration management protocol. More...

#include <I2cBusConfigurationManagement.h>

Collaboration diagram for _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL:
[legend]

Public Attributes

EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration
Enable an I2C bus configuration for use.
UINTN I2cBusConfigurationCount
Number of switch and multiplexer configurations for this I2C bus.

Detailed Description

I2C bus configuration management protocol.

Definition at line 178 of file I2cBusConfigurationManagement.h.

The documentation for this struct was generated from the following file:
  • I2cBusConfigurationManagement.h


AlderLake Platform Sample Code: Member List

_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL Member List

This is the complete list of members for _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL, including all inherited members.

EnableI2cBusConfiguration | _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2cBusConfigurationCount | _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL


AlderLake Platform Sample Code: _EFI_I2C_MASTER_PROTOCOL Struct Reference

Public Attributes | List of all members
_EFI_I2C_MASTER_PROTOCOL Struct Reference

I2C controller mode protocol. More...

#include <I2cMaster.h>

Collaboration diagram for _EFI_I2C_MASTER_PROTOCOL:
[legend]

Public Attributes

EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet
Set the clock frequency for the I2C bus.
EFI_I2C_MASTER_RESET Reset
Reset the I2C host controller.
EFI_I2C_MASTER_START_REQUEST StartRequest
Start an I2C transaction in controller mode on the host controller.
UINT32 | MaximumReceiveBytes
The maximum number of bytes the I2C host controller is able to receive from the I2C bus.
UINT32 | MaximumTransmitBytes
The maximum number of bytes the I2C host controller is able to send on the I2C bus.
UINT32 | MaximumTotalBytes
The maximum number of bytes in the I2C bus transaction.

Detailed Description

I2C controller mode protocol.

This protocol manipulates the I2C host controller to perform transactions as a controller on the I2C bus using the current state of any switches or multiplexers in the I2C bus.

Definition at line 511 of file I2cMaster.h.

The documentation for this struct was generated from the following file:
  • I2cMaster.h


AlderLake Platform Sample Code: Member List

_EFI_I2C_MASTER_PROTOCOL Member List

This is the complete list of members for _EFI_I2C_MASTER_PROTOCOL, including all inherited members.

BusFrequencySet | _EFI_I2C_MASTER_PROTOCOL
MaximumReceiveBytes | _EFI_I2C_MASTER_PROTOCOL
MaximumTotalBytes | _EFI_I2C_MASTER_PROTOCOL
MaximumTransmitBytes | _EFI_I2C_MASTER_PROTOCOL
Reset | _EFI_I2C_MASTER_PROTOCOL
StartRequest | _EFI_I2C_MASTER_PROTOCOL


AlderLake Platform Sample Code: _EFI_SMM_CPU_SAVE_STATE_PROTOCOL Struct Reference

Public Attributes | List of all members
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL Struct Reference

Provides a programatic means to access SMM save state. More...

#include <SmmCpuSaveState.h>

Collaboration diagram for _EFI_SMM_CPU_SAVE_STATE_PROTOCOL:
[legend]

Public Attributes

EFI_SMM_CPU_STATE ** CpuSaveState
Reference to a list of save states.

Detailed Description

Provides a programatic means to access SMM save state.

Definition at line 185 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


AlderLake Platform Sample Code: Member List

_EFI_SMM_CPU_SAVE_STATE_PROTOCOL Member List

This is the complete list of members for _EFI_SMM_CPU_SAVE_STATE_PROTOCOL, including all inherited members.

CpuSaveState _EFI_SMM_CPU_SAVE_STATE_PROTOCOL


AlderLake Platform Sample Code: _EFI_USB_DEVICE_MODE_PROTOCOL Struct Reference

List of all members
_EFI_USB_DEVICE_MODE_PROTOCOL Struct Reference

Usb Device Mode Protocol Structure. More...

#include <UsbDeviceModeProtocol.h>

Collaboration diagram for _EFI_USB_DEVICE_MODE_PROTOCOL:
[legend]

Detailed Description

Usb Device Mode Protocol Structure.

Definition at line 108 of file UsbDeviceModeProtocol.h.

The documentation for this struct was generated from the following file:
  • UsbDeviceModeProtocol.h


AlderLake Platform Sample Code: Member List

_EFI_USB_DEVICE_MODE_PROTOCOL Member List

This is the complete list of members for _EFI_USB_DEVICE_MODE_PROTOCOL, including all inherited members.


AlderLake Platform Sample Code: AUTHENTICATED_VARIABLE_HEADER Struct Reference

Public Attributes | List of all members
AUTHENTICATED_VARIABLE_HEADER Struct Reference

Single Variable Data Header Structure for Auth variable. More...

#include <MultiPlatSupport.h>

Public Attributes

UINT16 | StartId
Variable Data Start Flag.
UINT8 | State
Variable State defined above.
UINT32 | Attributes
Attributes of variable defined in UEFI specification.
UINT64 | MonotonicCount
Associated monotonic count value against replay attack.
EFI_TIME | TimeStamp
Associated TimeStamp value against replay attack.
UINT32 | PubKeyIndex
Index of associated public key in database.
UINT32 | NameSize
Size of variable null-terminated Unicode string name.
UINT32 | DataSize
Size of the variable data without this header.
EFI_GUID | VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.

Detailed Description

Single Variable Data Header Structure for Auth variable.

Definition at line 153 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


AlderLake Platform Sample Code: Member List

AUTHENTICATED_VARIABLE_HEADER Member List

This is the complete list of members for AUTHENTICATED_VARIABLE_HEADER, including all inherited members.

Attributes | AUTHENTICATED_VARIABLE_HEADER
DataSize | AUTHENTICATED_VARIABLE_HEADER
MonotonicCount | AUTHENTICATED_VARIABLE_HEADER
NameSize | AUTHENTICATED_VARIABLE_HEADER
PubKeyIndex | AUTHENTICATED_VARIABLE_HEADER
StartId | AUTHENTICATED_VARIABLE_HEADER
State | AUTHENTICATED_VARIABLE_HEADER
TimeStamp | AUTHENTICATED_VARIABLE_HEADER
VendorGuid | AUTHENTICATED_VARIABLE_HEADER


AlderLake Platform Sample Code: EFI_I2C_REQUEST_PACKET Struct Reference

Public Attributes | List of all members
EFI_I2C_REQUEST_PACKET Struct Reference

I2C device operation. More...

#include <I2cMaster.h>

Public Attributes

UINT32 | WriteBytes
Number of bytes to send to the I2C device.
UINT32 | ReadBytes
Number of bytes to read, set to zero for write only operations.
UINT8 * | WriteBuffer
Address of the buffer containing the data to send to the I2C device. More...
UINT8 * | ReadBuffer
Address of the buffer to receive data from the I2C device. More...
UINT32 | Timeout
Timeout for the I2C operation in 100 ns units.

Detailed Description

I2C device operation.

This structure provides the information necessary for an operation on an I2C device

Definition at line 360 of file I2cMaster.h.

Member Data Documentation

◆ ReadBuffer

UINT8* EFI_I2C_REQUEST_PACKET::ReadBuffer

Address of the buffer to receive data from the I2C device.

Use NULL for write only operations. The ReadBuffer must be at least ReadBytes in length.

Definition at line 382 of file I2cMaster.h.

◆ WriteBuffer

UINT8* EFI_I2C_REQUEST_PACKET::WriteBuffer

Address of the buffer containing the data to send to the I2C device.

The WriteBuffer must be at least WriteBytes in length.

Definition at line 375 of file I2cMaster.h.

The documentation for this struct was generated from the following file:
  • I2cMaster.h


AlderLake Platform Sample Code: Member List

EFI_I2C_REQUEST_PACKET Member List

This is the complete list of members for EFI_I2C_REQUEST_PACKET, including all inherited members.

ReadBuffer | EFI_I2C_REQUEST_PACKET
ReadBytes | EFI_I2C_REQUEST_PACKET
Timeout | EFI_I2C_REQUEST_PACKET
WriteBuffer | EFI_I2C_REQUEST_PACKET
WriteBytes | EFI_I2C_REQUEST_PACKET


AlderLake Platform Sample Code: EFI_RST_FEATURE_DATA Struct Reference

List of all members
EFI_RST_FEATURE_DATA Struct Reference

This variable is needed for VMD to know what Rst features are enabled on platform. More...

#include <RstFeaturesVariable.h>

Detailed Description

This variable is needed for VMD to know what Rst features are enabled on platform.

Feature enable values are set up in SA SETUP

Definition at line 47 of file RstFeaturesVariable.h.

The documentation for this struct was generated from the following file:
  • RstFeaturesVariable.h


AlderLake Platform Sample Code: Member List

EFI_RST_FEATURE_DATA Member List

This is the complete list of members for EFI_RST_FEATURE_DATA, including all inherited members.


AlderLake Platform Sample Code: EFI_SMM_CPU_STATE Union Reference

List of all members
EFI_SMM_CPU_STATE Union Reference

Union of CPU save-state strcutures for IA32 and X64. More...

#include <SmmCpuSaveState.h>

Collaboration diagram for EFI_SMM_CPU_STATE:
[legend]

Detailed Description

Union of CPU save-state strcutures for IA32 and X64.

This union declaration does not exctly match the Framework SMM CIS 0.91 because the union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200] field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for the layout and also maintains source comaptibility for access of all fields in this union.

Definition at line 175 of file SmmCpuSaveState.h.

The documentation for this union was generated from the following file:
  • SmmCpuSaveState.h


AlderLake Platform Sample Code: Member List

EFI_SMM_CPU_STATE Member List

This is the complete list of members for EFI_SMM_CPU_STATE, including all inherited members.


AlderLake Platform Sample Code: EFI_SMM_CPU_STATE32 Struct Reference

List of all members
EFI_SMM_CPU_STATE32 Struct Reference

CPU save-state strcuture for IA32 and X64. More...

#include <SmmCpuSaveState.h>

Detailed Description

CPU save-state strcuture for IA32 and X64.

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200] field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for the layout and also maintains source comaptibility for access of all fields in this union.

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These have been changed to use the base types defined in the UEFI Specification.

Definition at line 66 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


AlderLake Platform Sample Code: Member List

EFI_SMM_CPU_STATE32 Member List

This is the complete list of members for EFI_SMM_CPU_STATE32, including all inherited members.


AlderLake Platform Sample Code: EFI_SMM_CPU_STATE64 Struct Reference

List of all members
EFI_SMM_CPU_STATE64 Struct Reference

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. More...

#include <SmmCpuSaveState.h>

Detailed Description

This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure.

These have been changed to use the base types defined in the UEFI Specification.

Definition at line 106 of file SmmCpuSaveState.h.

The documentation for this struct was generated from the following file:
  • SmmCpuSaveState.h


AlderLake Platform Sample Code: Member List

EFI_SMM_CPU_STATE64 Member List

This is the complete list of members for EFI_SMM_CPU_STATE64, including all inherited members.


AlderLake Platform Sample Code: EFI_USB_INTERFACE_INFO Struct Reference

List of all members
EFI_USB_INTERFACE_INFO Struct Reference

USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec. More...

#include <EfiUsbFnIo.h>

Detailed Description

USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec.

Definition at line 75 of file EfiUsbFnIo.h.

The documentation for this struct was generated from the following file:
  • EfiUsbFnIo.h


AlderLake Platform Sample Code: Member List

EFI_USB_INTERFACE_INFO Member List

This is the complete list of members for EFI_USB_INTERFACE_INFO, including all inherited members.


AlderLake Platform Sample Code: VARIABLE_HEADER Struct Reference

Public Attributes | List of all members
VARIABLE_HEADER Struct Reference

Single Variable Data Header Structure. More...

#include <MultiPlatSupport.h>

Public Attributes

UINT16 | StartId
Variable Data Start Flag.
UINT8 | State
Variable State defined above.
UINT32 | Attributes
Attributes of variable defined in UEFI specification.
UINT32 | NameSize
Size of variable null-terminated Unicode string name.
UINT32 | DataSize
Size of the variable data without this header.
EFI_GUID | VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.

Detailed Description

Single Variable Data Header Structure.

Definition at line 122 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


AlderLake Platform Sample Code: Member List

VARIABLE_HEADER Member List

This is the complete list of members for VARIABLE_HEADER, including all inherited members.

Attributes | VARIABLE_HEADER
DataSize | VARIABLE_HEADER
NameSize | VARIABLE_HEADER
StartId | VARIABLE_HEADER
State | VARIABLE_HEADER
VendorGuid | VARIABLE_HEADER


AlderLake Platform Sample Code: VARIABLE_STORE_HEADER Struct Reference

Public Attributes | List of all members
VARIABLE_STORE_HEADER Struct Reference

Variable Store region header. More...

#include <MultiPlatSupport.h>

Public Attributes

EFI_GUID | Signature
Variable store region signature.
UINT32 | Size
Size of entire variable store, including size of variable store header but not including the size of FvHeader.
UINT8 | Format
Variable region format state.
UINT8 | State
Variable region healthy state.

Detailed Description

Variable Store region header.

Definition at line 84 of file MultiPlatSupport.h.

The documentation for this struct was generated from the following file:
  • MultiPlatSupport.h


AlderLake Platform Sample Code: Member List

VARIABLE_STORE_HEADER Member List

This is the complete list of members for VARIABLE_STORE_HEADER, including all inherited members.

Format | VARIABLE_STORE_HEADER
Signature | VARIABLE_STORE_HEADER
Size | VARIABLE_STORE_HEADER
State | VARIABLE_STORE_HEADER


AlderLake Platform Sample Code: Class Index

Class Index
_ | a | e | v
_
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL
a
EFI_RST_FEATURE_DATA
v
_EFI_USB_DEVICE_MODE_PROTOCOL EFI_SMM_CPU_STATE
_DEBUG_EVENT_HABDLER_PPI _TcgCreateStruct AUTHENTICATED_VARIABLE_HEADER EFI_SMM_CPU_STATE32 VARIABLE_HEADER
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL _TcgParseStruct
e
EFI_SMM_CPU_STATE64 VARIABLE_STORE_HEADER
_EFI_I2C_MASTER_PROTOCOL _TcgToken EFI_USB_INTERFACE_INFO
EFI_I2C_REQUEST_PACKET
_ | a | e | v


AlderLake Platform Sample Code: Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • Attributes : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- b -

  • buffer : _TcgCreateStruct , _TcgParseStruct
  • bufferSize : _TcgCreateStruct , _TcgParseStruct
  • BusFrequencySet : _EFI_I2C_MASTER_PROTOCOL

- c -

  • comPacket : _TcgCreateStruct , _TcgParseStruct
  • CpuSaveState : _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
  • curPacket : _TcgCreateStruct , _TcgParseStruct
  • curPtr : _TcgParseStruct
  • curSubPacket : _TcgCreateStruct , _TcgParseStruct

- d -

  • DataSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • dryRun : _TcgCreateStruct

- e -

  • EnableI2cBusConfiguration : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- f -

  • Format : VARIABLE_STORE_HEADER

- h -

  • hdrStart : _TcgToken

- i -

  • I2cBusConfigurationCount : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- m -

  • MaximumReceiveBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTotalBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTransmitBytes : _EFI_I2C_MASTER_PROTOCOL
  • MonotonicCount : AUTHENTICATED_VARIABLE_HEADER

- n -

  • NameSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- p -

  • PubKeyIndex : AUTHENTICATED_VARIABLE_HEADER

- r -

  • ReadBuffer : EFI_I2C_REQUEST_PACKET
  • ReadBytes : EFI_I2C_REQUEST_PACKET
  • Reset : _EFI_I2C_MASTER_PROTOCOL

- s -

  • Signature : VARIABLE_STORE_HEADER
  • Size : VARIABLE_STORE_HEADER
  • StartId : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • StartRequest : _EFI_I2C_MASTER_PROTOCOL
  • State : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER , VARIABLE_STORE_HEADER

- t -

  • Timeout : EFI_I2C_REQUEST_PACKET
  • TimeStamp : AUTHENTICATED_VARIABLE_HEADER
  • type : _TcgToken

- v -

  • VendorGuid : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- w -

  • WriteBuffer : EFI_I2C_REQUEST_PACKET
  • WriteBytes : EFI_I2C_REQUEST_PACKET


AlderLake Platform Sample Code: Class Members - Variables

- a -

  • Attributes : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- b -

  • buffer : _TcgCreateStruct , _TcgParseStruct
  • bufferSize : _TcgCreateStruct , _TcgParseStruct
  • BusFrequencySet : _EFI_I2C_MASTER_PROTOCOL

- c -

  • comPacket : _TcgCreateStruct , _TcgParseStruct
  • CpuSaveState : _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
  • curPacket : _TcgCreateStruct , _TcgParseStruct
  • curPtr : _TcgParseStruct
  • curSubPacket : _TcgCreateStruct , _TcgParseStruct

- d -

  • DataSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • dryRun : _TcgCreateStruct

- e -

  • EnableI2cBusConfiguration : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- f -

  • Format : VARIABLE_STORE_HEADER

- h -

  • hdrStart : _TcgToken

- i -

  • I2cBusConfigurationCount : _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

- m -

  • MaximumReceiveBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTotalBytes : _EFI_I2C_MASTER_PROTOCOL
  • MaximumTransmitBytes : _EFI_I2C_MASTER_PROTOCOL
  • MonotonicCount : AUTHENTICATED_VARIABLE_HEADER

- n -

  • NameSize : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- p -

  • PubKeyIndex : AUTHENTICATED_VARIABLE_HEADER

- r -

  • ReadBuffer : EFI_I2C_REQUEST_PACKET
  • ReadBytes : EFI_I2C_REQUEST_PACKET
  • Reset : _EFI_I2C_MASTER_PROTOCOL

- s -

  • Signature : VARIABLE_STORE_HEADER
  • Size : VARIABLE_STORE_HEADER
  • StartId : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER
  • StartRequest : _EFI_I2C_MASTER_PROTOCOL
  • State : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER , VARIABLE_STORE_HEADER

- t -

  • Timeout : EFI_I2C_REQUEST_PACKET
  • TimeStamp : AUTHENTICATED_VARIABLE_HEADER
  • type : _TcgToken

- v -

  • VendorGuid : AUTHENTICATED_VARIABLE_HEADER , VARIABLE_HEADER

- w -

  • WriteBuffer : EFI_I2C_REQUEST_PACKET
  • WriteBytes : EFI_I2C_REQUEST_PACKET


AlderLake Platform Sample Code: File List

File List
Here is a list of all documented files with brief descriptions:
AcpiVariable.h |
AmtPolicyInitDxe.c | This file is SampleCode for Intel AMT DXE Policy initialization
AmtPolicyInitDxe.h | Header file for the AmtPolicyInitDxe Driver
AttemptUsbFirst.h |
BaseEcFlashLib.h |
BasePlatformVariableLib.h |
BootGuardRevocationLib.h | Header file for Boot Guard revocation notification
BootMaintSetup.h |
BootStateLib.h |
CastroCovePmicNvm.h | This file is for CastroCove Pmic Nvm update
ChassisIntrDetHob.h | Chassis Intrusion Detection Status Structures
CnvVariables.h | Declaration of Intel Connectivity Variables Structures and guids for WLAN, BT and WIGIG
CommonDefinitions.h |
CpuPolicyInitDxe.c | This file is SampleCode for Intel Silicon DXE Platform Policy initialzation
CpuPolicyInitDxe.h | Header file for the SiliconPolicyInitDxe Driver
CrashLog.h |
CustomOptionControl.h |
DebugEventHandler.h |
DimmInfo.h | This header file provides Dimm info definitions used by other modules for dimm info presentation
DxeAcpiGnvsInitLib.h | Acpi Gnvs Init Library header file
DxeAmtPolicyUpdateLib.h |
DxeCpuPolicyUpdateLib.h |
DxeFirmwareVersionInfoLib.h | Private data structures
DxeMePolicyUpdateLib.h |
DxeOpromPatchLib.h |
DxePchPolicyUpdateLib.h |
DxePlatformBootManagerLib.h | Header file for DxePlatformBootManagerLib
DxePolicyBoardConfigLib.h | Header file for the DxePolicyBoardConfig Library
DxePolicyUpdateProtocol.h |
DxeSaPolicyUpdateLib.h |
DxeSmmAcpiCustomLib.h | This header file provides platform specific definitions used by other modules for platform specific initialization
DxeTbtPolicyUpdateLib.h |
EcAccess.h |
EcCommands.h |
EcHwLib.h | EC hardware library functions and definitions
EcLib.h | EC library functions and definitions
EcMiscLib.h | EC miscellaneous library functions
EcSmi.c | This file processes hotkey dispatch and callback event
EcSmi.h | Header file for EC SMI handlers
EcTcssLib.h | EC TCSS library functions
Efi.h |
EfiUsbFnIo.h | EFI USB function IO Protocol This protocol supports Usb Function IO API
FastBootDataDef.h |
FastBootException.h |
FastBootExceptionInfoHob.h |
FastBootFunctionEnabledHob.h | This file defines the HOB data structure to indicate that Fast Boot function is enabled in PEI phase, which may be used by some DXE phase drivers as well
FirwmareConfigurations.h | This header file provides definitions of firmware configuration
GfxInt15Interface.c | This is a driver to produce Int15 hook
GopPolicyInitDxe.c | This file initialises and Installs GopPolicy Protocol
GopPolicyInitDxe.h | Header file for the GopPolicyInitDxe Driver
HidI2cPlatformSupportLib.h | Support for IO expander TCA6424
HstiFeatureBit_1_1a.h | This file contains various definitions for IHV HSTI implementation including STATUS string definitions
HstiIbvFeatureBit.h | This file contains various definitions for IHV HSTI implementation including error string definitions
I2cBusConfigurationManagement.h | I2C bus configuration management interface
I2cMaster.h | I2C Master interface
IccSetupData.h |
LifeCycleState.h |
MePolicyInitDxe.c | This file is SampleCode for Intel ME DXE Policy initialization
MePolicyInitDxe.h | Header file for the MePolicyInitDxe Driver
MultiPlatSupport.h |
MultiPlatSupportLib.h |
OemSetup.h | OEM Specific Setup Variables and Structures
OverClockPpi.h |
PchPolicyInitDxe.c | This file is SampleCode for PCH DXE Policy initialization
PchPolicyInitDxe.h | Header file for the PchPolicyInitDxe Driver
PciBusSetup.h |
PcieDockSmi.c |
PcieDockSmi.h |
PcieWorkaroundOnPolicy.h | Header file for the PCIE Workaround on Policy
PdtUpdateLib.h |
PeiBootGuardEventLogLib.h | This file contains functions for creating TPM Event Log
PeiCpuPolicyDebugLib.h | SampleCode header file of the library for Intel CPU PEI Debug Policy initialization
PeiGetFvInfoLib.h | Header file for PeiGetFvInfoLib
PeiPchPolicyDebugLib.h | SampleCode header file of the library for Intel PCH PEI Debug Policy initialization
PeiPlatformLib.h |
PeiPlatformRecoveryLib.h | This library provides platform recovery module
PeiReadWriteVariableLib.h |
PeiSaPolicyDebugLib.h | SampleCode header file of the library for Intel SA PEI Debug Policy initialization
PeiSiPolicyDebugLib.h | SampleCode header file of the library for Intel SI PEI Debug Policy initialization
PeiSubRegionLib.h | Header file for PeiSubRegionLib
PeiSwbpeLib.h |
PeiTsnFvLib.h | Header file for PeiTsnFvFile
PeiWdtAppLib.h | PEI WDT App library definitions
Platform.h | This header file provides platform specific definitions used by other modules for platform specific initialization
PlatformBoardType.h | BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL
PlatformClock.h |
PlatformConfigurationChangeVariable.h | Platform configuration change variable definitions
PlatformGlobalVariable.h | GUID for Platform (NVRAM) Variables
PlatformInfo.h | GUID used for Platform Info Data entries in the HOB list
PlatformInitAdvancedDxe.c | Source code file for the Platform Init Advanced DXE module
PlatformInitAdvancedDxe.h | Header file for Platform Init Advanced Dxe Driver
PlatformInitAdvancedPostMem.c | Source code file for Platform Init PEI module
PlatformInitAdvancedPreMem.c | Source code file for Platform Init Advanced Pre-Memory PEI module
PlatformInitAdvancedSmm.c | Platform Advanced SMM Driver
PlatformInitAdvancedSmm.h | Header file for the Platform Advanced SMM Driver
PlatformInitLib.h | Function prototype of PlatformInitLib
PlatformNvRamHookLib.h | Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc
PlatformNvsArea.h | This file defines the Platform NVS Area Protocol
PlatformOpRomTable.h |
PlatformOptionRomTable_Default.h |
PlatformPostCode.h |
PlatformSecureLib.h | Provides a secure platform-specific method to detect physically present user
PlatformTelemetryLib.h | Save LastUpdateTime to variable by different ImageTypeID
PolicyInitAdvancedDxe.c | This file is a wrapper for Platform Policy Advanced driver
PolicyInitAdvancedDxe.h | Header file for the PolicyInitAdvancedDxe Driver
PolicyUpdateMacro.h | Macros for platform to update different types of policy
Ps2IoTrapHandler.c |
PssLib.h | PSS(Processor Secured Storage) Chip Operation Library Header
PttInstance.h | GUID definition for the PTT device instance
PttPTPInstanceGuid.h | GUID definition for the PTT device instance
RetimerCapsuleUpdate.h | RetimerCapsuleUpdate driver definitions
RstConfigPpi.h | This file contains RST related PPI definitions
RstConfigSpaceAccess.h | RST config space access protocol for bios
RstFeaturesVariable.h | RST Features variable definition
RstLegacyBootDisabledProtocol.h | RST legacy boot disabled protocol
S3MemoryVariable.h |
SaPlatformInitAdvancedDxe.c | Source code file for the SA Platform Init DXE module
SaPolicyInitDxe.c | This file is SampleCode for SA DXE Policy initialization
SaPolicyInitDxe.h | Header file for the SaPolicyInitDxe Driver
SecureBootSetup.h |
SecurePreMemoryDataLoadLib.h | PEI Secure Pre-Memory Data Load Library
SerialIoUartDebugHelperLib.h |
SerialIoUartDebugPropertyLib.h |
SerialPortParameterLib.h | This library class provides capability to get/set serial port baud rate
Setup.h |
SetupConfiguration.h | Default platform setup configuration settings
SetupVariable.h |
SiliconPolicyInitDxe.c | This file is SampleCode for Intel Silicon DXE Platform Policy initialzation
SiliconPolicyInitDxe.h | Header file for the SiliconPolicyInitDxe Driver
SioRegs.h |
SmbiosPlatformInfoDefault.h | This file contains Default data for Platform SMBIOS tables
SmbiosPlatformInfoDefinition.h | This file contains definition for Platform SMBIOS Info
SmmCpuSaveState.h | This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors
SmmTxtResource.h | This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM
SpiFlashCommon.h | The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib
SystemMonitor.h |
SystemNvDataGuid.h |
TbtPolicyInitDxe.c | This file is SampleCode for TBT DXE Policy initialization
TbtPolicyInitDxe.h | Header file for the TbtPolicyInitDxe Driver
Tcg.h | TCG defined values and structures used by the Tcg Core library
Tcg2ConfigHii.h | GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver
Tcg2ConfigNvData.h | Header file for NV data structure definition
Tcg2PhysicalPresenceLib.h | Ihis library is intended to be used by BDS modules
TcgCore.h | Public API for the Tcg Core library to perform the lowest level TCG data encoding
TcgSetup.h |
TcgUtil.h | Provides TCG high-level API to perform common TCG actions on a TCG data packet
TcoWdtHob.h |
TPSxFwUpdateWrapperProtocol.h | Protocol definitions for TPSxFwUpdateWrapper
TrustedDeviceSetup.h | Intel Trusted Device Setup library services
TrustedDeviceSetupMainProtocol.h | APIs for Intel Trusted Device Setup Main Protocol
TxtOneTouch.h | This file contains definitions required for One-Touch function
TxtOneTouchOp.h | Txt specific PPI operation definition
UsbDeviceLib.h | Header file for USBFN library definition
UsbDeviceModeProtocol.h | Header file for definition of USBFN device mode protocol
VtdEnableDmaBufferPpi.h | The definition for the VTd Enable DMA Buffer PPI
WdtAppVariable.h | Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp
WheaSetup.h |
WifiConnectionManagerConfigHii.h | GUIDs used as HII FormSet and HII Package list GUID in WiFi Connection Manager


AlderLake Platform Sample Code: AcpiVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
AcpiVariable.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiVariable.h.


AlderLake Platform Sample Code: AcpiVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
AcpiVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _ACPI_VARIABLE_H_
36 #define _ACPI_VARIABLE_H_
37 #define ACPI_GLOBAL_VARIABLE L"AcpiGlobalVariable"
38
39 //
40 // The following structure combine all ACPI related variables into one in order
41 // to boost performance
42 //
43
44 typedef struct {
45 //
46 // Acpi Related variables
47 //
48 EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
49 UINT32 AcpiReservedMemorySize;
50 EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase;
51 EFI_PHYSICAL_ADDRESS AcpiBootScriptTable;
52 EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
53 EFI_PHYSICAL_ADDRESS AcpiFacsTable;
54 UINT64 SystemMemoryLength;
55 //
56 // VGA OPROM to support Video Re-POST for Linux S3
57 //
58 EFI_PHYSICAL_ADDRESS VideoOpromAddress;
59 UINT32 VideoOpromSize;
60
61 //
62 // S3 Debug extension
63 //
64 EFI_PHYSICAL_ADDRESS S3DebugBufferAddress;
65 EFI_PHYSICAL_ADDRESS S3ResumeNvsEntryPoint;
66 } ACPI_VARIABLE_SET;
67
68 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: AmtPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
AmtPolicyInitDxe.c File Reference

This file is SampleCode for Intel AMT DXE Policy initialization. More...

#include "AmtPolicyInitDxe.h"
Include dependency graph for AmtPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS AmtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy. More...

Detailed Description

This file is SampleCode for Intel AMT DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AmtPolicyInitDxe.c.

Function Documentation

◆ AmtPolicyInitDxe()

EFI_STATUS AmtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize Intel AMT DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file AmtPolicyInitDxe.c.

Here is the call graph for this function:


AlderLake Platform Sample Code: AmtPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
AmtPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel AMT DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "AmtPolicyInitDxe.h"
35
36 /**
37 Initialize Intel AMT DXE Policy
38
39 @param[in] ImageHandle Image handle of this driver.
40
41 @retval EFI_SUCCESS Initialization complete.
42 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
43 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
44 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
45 **/
46 EFI_STATUS
47 EFIAPI
48 AmtPolicyInitDxe (
49 IN EFI_HANDLE ImageHandle
50 )
51 {
52 EFI_STATUS Status;
53 AMT_POLICY_PROTOCOL *AmtPolicyProtocol;
54
55 DEBUG ((DEBUG_INFO, "AmtPolicyInitDxe\n"));
56 //
57 // Call AmtCreatePolicyDefaults to initialize platform policy structure
58 // and get all default policy settings.
59 //
60 Status = AmtCreatePolicyDefaults (&AmtPolicyProtocol);
61 if (Status == EFI_UNSUPPORTED) {
62 return EFI_SUCCESS;
63 }
64
65 UpdateDxeAmtPolicyBoardConfig (AmtPolicyProtocol);
66
67 if (mFirmwareConfiguration != FwConfigDefault) {
68 UpdateDxeAmtPolicy (AmtPolicyProtocol);
69 }
70
71 //
72 // Install AmtInstallPolicyProtocol.
73 // While installed, RC assumes the Policy is ready and finalized. So please
74 // update and override any setting before calling this function.
75 //
76 Status = AmtInstallPolicyProtocol (ImageHandle, AmtPolicyProtocol);
77
78 return Status;
79 }
80
UpdateDxeAmtPolicy
EFI_STATUS UpdateDxeAmtPolicy(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
Install DxeAmtPolicy with setup values.
UpdateDxeAmtPolicyBoardConfig
EFI_STATUS UpdateDxeAmtPolicyBoardConfig(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration.
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
AmtPolicyInitDxe.h
Header file for the AmtPolicyInitDxe Driver.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: AmtPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
AmtPolicyInitDxe.h File Reference

Header file for the AmtPolicyInitDxe Driver. More...

#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/MePolicy.h>
#include <Protocol/AmtPolicy.h>
#include <Library/DxeAmtPolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeAmtPolicyUpdateLib.h>
Include dependency graph for AmtPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS AmtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy. More...

Detailed Description

Header file for the AmtPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AmtPolicyInitDxe.h.

Function Documentation

◆ AmtPolicyInitDxe()

EFI_STATUS AmtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize Intel AMT DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file AmtPolicyInitDxe.c.

Here is the call graph for this function:


AlderLake Platform Sample Code: AmtPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
AmtPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the AmtPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _AMT_POLICY_INIT_DXE_H_
35 #define _AMT_POLICY_INIT_DXE_H_
36
37 #include <Library/DebugLib.h>
38 #include <Library/UefiBootServicesTableLib.h>
39 #include <FirwmareConfigurations.h>
40 #include <Protocol/MePolicy.h>
41 #include <Protocol/AmtPolicy.h>
42 #include <Library/DxeAmtPolicyLib.h>
43 #include <Library/DxePolicyBoardConfigLib.h>
44 #include <Library/DxeAmtPolicyUpdateLib.h>
45
46 extern UINT8 mFirmwareConfiguration;
47
48 /**
49 Initialize Intel AMT DXE Policy
50
51 @param[in] ImageHandle Image handle of this driver.
52
53 @retval EFI_SUCCESS Initialization complete.
54 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
55 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
56 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
57 **/
58 EFI_STATUS
59 EFIAPI
60 AmtPolicyInitDxe (
61 IN EFI_HANDLE ImageHandle
62 );
63
64 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxeAmtPolicyUpdateLib.h
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: AttemptUsbFirst.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
AttemptUsbFirst.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AttemptUsbFirst.h.


AlderLake Platform Sample Code: AttemptUsbFirst.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
AttemptUsbFirst.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _ATTEMPT_USB_FIRST_H_
35 #define _ATTEMPT_USB_FIRST_H_
36
37 #pragma pack(1)
38 typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
39 UINT8 RevisonId; // Structure Revision ID
40 UINT8 HotkeyTriggered; // Hot key status
41 } ATTEMPT_USB_FIRST_HOTKEY_INFO;
42 #pragma pack()
43
44 #pragma pack(1)
45 typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
46 UINT8 UsbBootPrior;
47 } ATTEMPT_USB_FIRST_VARIABLE;
48 #pragma pack()
49
50 //
51 // Volatile variable definition for Attempt USB first features
52 //
53 #pragma pack(1)
54 typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
55 UINT8 RevisonId; // Structure Revision ID
56 UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
57 } ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
58 #pragma pack()
59
60 //
61 // Volatile variable definition for third party Default Enabling via UEFI Variable.
62 //
63 #pragma pack(1)
64 typedef struct _ENABLE_CUSTOM_DEFAULTS{
65 UINT32 EnableCustomDefaults;
66 } ENABLE_CUSTOM_DEFAULTS;
67 #pragma pack()
68
69 #define COENG_DEFAULTS_UNKNOWN 0
70 #define COENG_DEFAULTS_SUPPORTED 1
71 #define COENG_DEFAULTS_VAR_EXITS 2
72 #define COENG_DEFAULTS_VAR_SET 4
73 #define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULTS_VAR_EXITS |COENG_DEFAULTS_VAR_SET)
74
75 extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
76 extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
77 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: BaseEcFlashLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Macros
BaseEcFlashLib.h File Reference

Go to the source code of this file.

Macros

#define | EC_VIRTUAL_BAT_STATUS 48
Note that capacity and voltage are 16 bit values, thus you need to read them from ACPI space with two reads (little Endian). More...
#define | EC_VIRTUAL_BAT_PRESENT_MASK 0x10
Bit 4 is the indicator.
#define | EC_REAL_BAT1_STATUS 50
Status of the first real battery (present, charging)
#define | EC_REAL_BAT1_REMAINING_PERCENT 52
Remaining capacity in percentage.
#define | EC_REAL_BAT1_REMAINING_CAPACITY 89
Remaining capacity in mWh.
#define | EC_REAL_BAT1_RESOLUTION_VOLTAGE 93
Full resolution voltage in mV.
#define | EC_REAL_BAT2_STATUS 54
Status of the second real battery (present, charging)
#define | EC_REAL_BAT2_REMAINING_PERCENT 56
Remaining capacity in percentage.
#define | EC_REAL_BAT2_REMAINING_CAPACITY 99
Remaining capacity in mWh.
#define | EC_REAL_BAT2_RESOLUTION_VOLTAGE 103
Full resolution voltage in mV.
#define | EC_REAL_BAT_PRESENT_MASK 0x8
Bit 3 is the indicator.
#define | EC_REAL_BAT_CHARGING_MASK 0x1
Bit 1 is the indicator.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BaseEcFlashLib.h.

Macro Definition Documentation

◆ EC_VIRTUAL_BAT_STATUS

#define EC_VIRTUAL_BAT_STATUS 48

Note that capacity and voltage are 16 bit values, thus you need to read them from ACPI space with two reads (little Endian).

Status of the virtual battery (present)

Definition at line 117 of file BaseEcFlashLib.h.


AlderLake Platform Sample Code: BaseEcFlashLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
BaseEcFlashLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _EC_FLASH_H_
35 #define _EC_FLASH_H_
36
37 #define IMAGE_SIGNATURE 0x2202L // Flash image signature (EC) offset.
38 #define IMAGE_VERSION_NUM 0x106L // Flash image version number offset.
39 #define IMAGE_SIZE_OFFSET 0x140L // Flash image size is stored here.
40 #define PLAT_SIG_OFFSET 0x142L // 8 byte platform signature stored here.
41 #define IMAGE_ECFW1_OFFSET 0x20000L // Offset of ECFW Image 1
42 #define IMAGE_ECFW2_OFFSET 0x1000L // Offset of ECFW Image 2(Recovery)
43
44 #define UPDATE_FULL 0x0 // update SPIHeader + ECFW1 + ECFW2
45 #define UPDATE_ECFW1 0x1 // update ECFW1
46 #define UPDATE_ECFW1_ECFW2 0x2 // update ECFW1 + ECFW2
47
48 #define TOTAL_BLKS 0x448 // Total number of 128 byte blocks.
49
50 #define FBLOCK_SIZE 128L // Flash line size
51 #define ECCOMMANDPORT 0x66 // Using EC ports for flashing.
52 #define ECSTATUSPORT 0x66
53 #define ECDATAPORT 0x62
54
55 //
56 // EC FLASH COMMANDS:
57 //
58 #define FLASHLOADER 0x91 // Command for FLASH reprogram mode.
59 #define NMIDISABLE 0x93 // Command for H8 NMI Disable.
60
61 #define INITERASE 0x01 // Load erase code into RAM and initialize
62 #define SETERASEBLKNUM 0x02 // Set block num for erase.
63 #define ERASEFLASHBLK 0x03 // Erase flash block.
64 #define BLANKCHECK 0x04 // Blank check the part.
65 #define INITPROGCODE 0x05 // Initialize programming code.
66 #define LOADFLASHBLK 0x06 // Load flash block for programming.
67 #define SETFLASHWRITEADDR 0x07 // Set starting address for writes.
68 #define PROGRAMFLASHBLK 0x08 // Program flash block.
69 #define VERIFYFLASHBLK 0x09 // Verify flash block.
70 #define ERASEFLASH 0x0A // Erase entire flash.
71 #define RESETEC 0x0B // Controller hard reset.
72 #define READFLASHBYTE 0x0C // Read a byte at address
73 #define READBLOCK 0x0D // Read a block at address
74
75 //
76 // EC RUNTIME COMMANDS:
77 //
78 #define READBYTE 0x01 // Read byte
79 #define WRITEBYTE 0x02 // Write byte
80 #define GETSWITCHSTATUS 0x0A // Get switch status
81 #define ENABLE_POWER_BTN 0x23 // Disable power button functionality
82 #define DISABLE_POWER_BTN 0x24 // Enable power button functionality
83 #define READECREVISION 0x90 // Read EC firmware revision number.
84 #define READECMEM 0x80 // Read the EC memory
85 #define QUERYSYSSTATUS 0x06 // Returns 1 byte of information about the system status
86 #define SYS_STATUS_FAN 0x40 // Fan status (1 = ON)
87 #define SYS_STATUS_DOCK 0x20 // Dock status (1 = Docked)
88 #define SYS_STATUS_AC 0x10 // AC power (1 = AC powered)
89 #define SYS_STATUS_THER 0x0F // CPU thermal state (0 ~ 9)
90
91 #define PLATFORM_UNKNOWN 0xFF // Unknown platform
92
93 #define m_CR 0x0D
94 #define m_LF 0x0A
95
96 #define PCIINDEX 0xCF8
97 #define PCIDATA 0xCFC
98 #define ICH_DEVNUM 0x1F
99 #define ICH_GPIO_BAR 0x58
100 #define FN0 0x00
101 #define NMIGPIO_REG 0x38
102 #define NMIGPIO_BIT 0x01
103 #define DEVINQSIZE 0x32
104 #define RMCMDSTRUCTSIZE 128+32
105 #define BBLKSIZE_OFFSET 0x50 // Offset of boot block size in image
106 #define EC_SEGMENT 8*1024L
107 #define TMKBC_SEGMENT 72*1024L
108 #define ECSEGSIZE_OFFSET 8768L // 8*1024 + 240h
109 #define PORT1 0x3F8
110 #define EC_TIME_OUT 0x50000
111 #define EC_STALL_TIME_OUT 100
112 #define EC_S_OBF BIT0
113 #define EC_S_IBF BIT1
114
115 /// Note that capacity and voltage are 16 bit values, thus you need to read them from
116 /// ACPI space with two reads (little Endian).
117 #define EC_VIRTUAL_BAT_STATUS 48 ///< Status of the virtual battery (present)
118 #define EC_VIRTUAL_BAT_PRESENT_MASK 0x10 ///< Bit 4 is the indicator
119
120 #define EC_REAL_BAT1_STATUS 50 ///< Status of the first real battery (present, charging)
121 #define EC_REAL_BAT1_REMAINING_PERCENT 52 ///< Remaining capacity in percentage
122 #define EC_REAL_BAT1_REMAINING_CAPACITY 89 ///< Remaining capacity in mWh
123 #define EC_REAL_BAT1_RESOLUTION_VOLTAGE 93 ///< Full resolution voltage in mV
124
125 #define EC_REAL_BAT2_STATUS 54 ///< Status of the second real battery (present, charging)
126 #define EC_REAL_BAT2_REMAINING_PERCENT 56 ///< Remaining capacity in percentage
127 #define EC_REAL_BAT2_REMAINING_CAPACITY 99 ///< Remaining capacity in mWh
128 #define EC_REAL_BAT2_RESOLUTION_VOLTAGE 103 ///< Full resolution voltage in mV
129
130 #define EC_REAL_BAT_PRESENT_MASK 0x8 ///< Bit 3 is the indicator
131 #define EC_REAL_BAT_CHARGING_MASK 0x1 ///< Bit 1 is the indicator
132
133 //
134 // Function prototypes
135 //
136 VOID WaitInputBufferEmpty(VOID);
137 VOID WaitOutputBufferFull(VOID);
138 UINT32 EraseFlashBlock(UINT32 BlkNum);
139 UINT32 WriteFlashBlock(UINT32 *FBufPtr);
140 UINT32 ComputeBuffChksum(UINT32 *BufPtr, UINT32 BufSize);
141 void SendEcCommand(UINT32 CmdNum);
142 void SendEcData(UINT32 Data);
143 UINT32 ReceiveEcData(void);
144 UINT32 NmiActive(void);
145 void Port80(UINT32);
146 void EcReset(void);
147 VOID ReadEcRegister(UINT8 Reg, UINT8 *RetValue);
148
149 EFI_STATUS EcFlash(UINT8* pFcntrlBin, UINT32 FcntrlBinSize, UINT8* pEcBin, UINT32 EcBinSize);
150 BOOLEAN IsEcVersionIdentical (UINT8* pEcBin);
151
152 //
153 // Globals
154 //
155 UINT32 FlashBuf[FBLOCK_SIZE];
156 UINT32 *FlashBufPtr;
157 UINT32 FBlkStartAddr;//ulong
158 UINT32 FlashBlock;
159 UINT32 ImageLen;
160 UINT32 ImageVer;
161 UINT64 FcntrlLen; //ulong
162 UINT64 FecSize;
163 UINT32 FcntrlLenLow;
164 UINT32 FcntrlLenHigh;
165 CHAR16 Buff[16];
166 CHAR16* ptBuff;
167 CHAR16 PlatformID[9];
168
169 UINT32 DevInquirySize;
170 UINT32 DevInquiryBuff[DEVINQSIZE];
171 UINT32* DevInqBuffPtr;
172 UINT32 RMDevCode[4];
173 CHAR16 RMProdName[10];
174 UINT32 RMCmdStruct[RMCMDSTRUCTSIZE];
175
176 #define EFI_PROPER_VERSION(MajorVer, MinorVer) (gBS->Hdr.Revision >= (MajorVer << 16 | MinorVer))
177
178 #endif
SendEcData
EFI_STATUS SendEcData(IN UINT8 Data)
Sends data to Keyboard System Controller.
ReceiveEcData
EFI_STATUS ReceiveEcData(OUT UINT8 *Data)
Receives data from Keyboard System Controller.
SendEcCommand
EFI_STATUS SendEcCommand(IN UINT8 Command)
Send a command to the Keyboard System Controller.
EcReset
EFI_STATUS EcReset(VOID)
Do EC reset.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: BasePlatformVariableLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
BasePlatformVariableLib.h File Reference
#include <Uefi.h>
Include dependency graph for BasePlatformVariableLib.h:

Go to the source code of this file.

Functions

EFI_STATUS CheckSataRaidMode (BOOLEAN *SataRaidModeEnabled)
Check the SATA RAID mode and report its status. More...

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BasePlatformVariableLib.h.

Function Documentation

◆ CheckSataRaidMode()

EFI_STATUS CheckSataRaidMode ( BOOLEAN * SataRaidModeEnabled )

Check the SATA RAID mode and report its status.

Parameters
[out] SataRaidModeEnabled The current status of SATA RAID mode.
Return values
EFI_SUCESS | This function always complete successfully.
EFI_ACCESS_DENIED | Cannot not retrieve PchSetup variables.


AlderLake Platform Sample Code: BasePlatformVariableLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
BasePlatformVariableLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35 #ifndef _BASE_PLATFORM_VARIABLE_LIB_H_
36 #define _BASE_PLATFORM_VARIABLE_LIB_H_
37
38 #include <Uefi.h>
39
40
41
42 /**
43 Check the SATA RAID mode and report its status.
44
45 @param[out] SataRaidModeEnabled The current status of SATA RAID mode.
46
47 @retval EFI_SUCESS This function always complete successfully.
48 @retval EFI_ACCESS_DENIED Cannot not retrieve PchSetup variables.
49 **/
50 EFI_STATUS
51 CheckSataRaidMode (
52 BOOLEAN *SataRaidModeEnabled
53 );
54
55 #endif
CheckSataRaidMode
EFI_STATUS CheckSataRaidMode(BOOLEAN *SataRaidModeEnabled)
Check the SATA RAID mode and report its status.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: BootGuardRevocationLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
BootGuardRevocationLib.h File Reference

Header file for Boot Guard revocation notification. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Protocol/SimpleTextIn.h>
Include dependency graph for BootGuardRevocationLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

VOID BootGuardOemRevocationHook (VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.

Detailed Description

Header file for Boot Guard revocation notification.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BootGuardRevocationLib.h.


AlderLake Platform Sample Code: BootGuardRevocationLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
BootGuardRevocationLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Boot Guard revocation notification.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _BOOT_GUARD_REVOCATION_LIB_H_
37 #define _BOOT_GUARD_REVOCATION_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Library/UefiRuntimeServicesTableLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/MemoryAllocationLib.h>
45 #include <Library/DebugLib.h>
46 #include <Protocol/SimpleTextIn.h>
47
48 /**
49 Provide a hook for OEM to deal with Boot Guard revocation flow.
50 **/
51 VOID
52 EFIAPI
53 BootGuardOemRevocationHook (
54 VOID
55 );
56
57 #endif
BootGuardOemRevocationHook
VOID BootGuardOemRevocationHook(VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: BootMaintSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
BootMaintSetup.h File Reference

Go to the source code of this file.

Macros

#define | TOTAL_SERIAL_PORT_INFO_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | TIME_OUT_INFO_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file BootMaintSetup.h.


AlderLake Platform Sample Code: BootMaintSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
BootMaintSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _BOOT_MAINT_SETUP_H_
35 #define _BOOT_MAINT_SETUP_H_
36
37 #pragma pack(1)
38
39 typedef struct {
40 UINT8 ComNum;
41 } SERIAL_PORT_TAG;
42
43 typedef struct _SERIAL_PORT_ATTRIBUTE {
44 UINT64 BaudRate;
45 UINT8 DataBits;
46 UINT8 StopBits;
47 UINT8 Parity;
48 UINT8 TerminalType;
49 UINT8 FlowControl;
50 UINT8 LegacyResolution;
51 UINT8 IsEnabled;
52 UINT8 Length;
53 SERIAL_PORT_TAG ComTag;
54 } SERIAL_PORT_ATTRIBUTE;
55
56 /**
57 Making any setup structure change after code frozen
58 will need to maintain backward compatibility, bump up
59 structure revision and update below history table\n
60 <b>Revision 1</b>: - Initial version.
61 **/
62 #define TOTAL_SERIAL_PORT_INFO_REVISION 1
63
64 typedef struct {
65 UINT64 TotalSize;
66 SERIAL_PORT_ATTRIBUTE PortAttributes[1];
67 } TOTAL_SERIAL_PORT_INFO;
68
69 /**
70 Making any setup structure change after code frozen
71 will need to maintain backward compatibility, bump up
72 structure revision and update below history table\n
73 <b>Revision 1</b>: - Initial version.
74 **/
75 #define TIME_OUT_INFO_REVISION 1
76 typedef struct {
77 UINT16 BootTimeOut;
78 } TIME_OUT_INFO;
79
80
81 #pragma pack()
82 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: BootStateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Functions
BootStateLib.h File Reference

Go to the source code of this file.

Functions

BOOLEAN | IsBootStatePresent (VOID)
This function call Checks BootState variable is NULL or not. More...
EFI_STATUS | GetBootStateAfterCapsule (BOOLEAN *BootStateAfterCapsule)
This function checks is the very first boot after BIOS flash or Capsule update for EC/BIOS. More...
EFI_STATUS | SetBootStateAfterCapsule (IN BOOLEAN BootStateAfterCapsule)
Set BootStateAfterCapsule variable to indicate the following boot is the very first boot after Capsule Update. More...
VOID | SetBootState (VOID)
This function call use to set bootstate variable. More...
VOID | UnsetBootState (VOID)
Delete BootState variable to force next boot is FullConfiguration boot.

Detailed Description

Component Information file for BootState Variable.

# #

Copyright

INTEL CONFIDENTIAL

Copyright 2020 Intel Corporation.

#

The source code contained or described herein and all documents related to the

source code ("Material") are owned by Intel Corporation or its suppliers or

licensors. Title to the Material remains with Intel Corporation or its suppliers

and licensors. The Material may contain trade secrets and proprietary and

confidential information of Intel Corporation and its suppliers and licensors,

and is protected by worldwide copyright and trade secret laws and treaty

provisions. No part of the Material may be used, copied, reproduced, modified,

published, uploaded, posted, transmitted, distributed, or disclosed in any way

without Intel's prior express written permission.

#

No license under any patent, copyright, trade secret or other intellectual

property right is granted to or conferred upon you by disclosure or delivery

of the Materials, either expressly, by implication, inducement, estoppel or

otherwise. Any license under such intellectual property rights must be

express and approved by Intel in writing.

#

Unless otherwise agreed by Intel in writing, you may not remove or alter

this notice or any other notice embedded in Materials by Intel or

Intel's suppliers or licensors in any way.

#

This file contains a 'Sample Driver' and is licensed as such under the terms

of your license agreement with Intel or your vendor. This file may be modified

by the user, subject to the additional terms of the license agreement.

#

@par Specification Reference:

Definition in file BootStateLib.h.

Function Documentation

◆ GetBootStateAfterCapsule()

EFI_STATUS GetBootStateAfterCapsule ( BOOLEAN * BootStateAfterCapsule )

This function checks is the very first boot after BIOS flash or Capsule update for EC/BIOS.

Parameters
[in,out] BootStateAfterCapsule out,0 its second boot after capsule updated out,1 its very first boot after capsule updated
Return values
status | Very first boot after capsule update
EFI_SUCCESS | NOT the first boot path after capsule update

◆ IsBootStatePresent()

BOOLEAN IsBootStatePresent ( VOID )

This function call Checks BootState variable is NULL or not.

Return values
FALSE | It's the first boot after reflashing.
TRUE | It's not the first boot after reflashing.

◆ SetBootState()

VOID SetBootState ( VOID )

This function call use to set bootstate variable.

In DXE phase BootState variable got set using setvariable().Form onward it will treat as second boot.

Parameters
[in] BootState Set value for bootstate

◆ SetBootStateAfterCapsule()

EFI_STATUS SetBootStateAfterCapsule ( IN BOOLEAN BootStateAfterCapsule )

Set BootStateAfterCapsule variable to indicate the following boot is the very first boot after Capsule Update.

Parameters
[in] BootStateAfterCapsule TRUE, Following boot is the first boot after Capsule Update. FALSE, following boot is NOT the first boot after Capsule update.
Return values
EFI_SUCCESS BootStateAfterCapsule variable set.


AlderLake Platform Sample Code: BootStateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
BootStateLib.h
Go to the documentation of this file.
1 /** @file
2 # Component Information file for BootState Variable.
3 #
4 #@copyright
5 # INTEL CONFIDENTIAL
6 # Copyright 2020 Intel Corporation.
7 #
8 # The source code contained or described herein and all documents related to the
9 # source code ("Material") are owned by Intel Corporation or its suppliers or
10 # licensors. Title to the Material remains with Intel Corporation or its suppliers
11 # and licensors. The Material may contain trade secrets and proprietary and
12 # confidential information of Intel Corporation and its suppliers and licensors,
13 # and is protected by worldwide copyright and trade secret laws and treaty
14 # provisions. No part of the Material may be used, copied, reproduced, modified,
15 # published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 # without Intel's prior express written permission.
17 #
18 # No license under any patent, copyright, trade secret or other intellectual
19 # property right is granted to or conferred upon you by disclosure or delivery
20 # of the Materials, either expressly, by implication, inducement, estoppel or
21 # otherwise. Any license under such intellectual property rights must be
22 # express and approved by Intel in writing.
23 #
24 # Unless otherwise agreed by Intel in writing, you may not remove or alter
25 # this notice or any other notice embedded in Materials by Intel or
26 # Intel's suppliers or licensors in any way.
27 #
28 # This file contains a 'Sample Driver' and is licensed as such under the terms
29 # of your license agreement with Intel or your vendor. This file may be modified
30 # by the user, subject to the additional terms of the license agreement.
31 #
32 # @par Specification Reference:
33 **/
34
35 #ifndef _BOOT_STATE_H_
36 #define _BOOT_STATE_H_
37
38 #define BOOT_STATE_VARIABLE_NAME L"BootState"
39
40 #endif
41
42 /**
43 This function call Checks BootState variable is NULL or not
44
45 @retval FALSE It's the first boot after reflashing.
46 @retval TRUE It's not the first boot after reflashing.
47 **/
48
49 BOOLEAN
50 EFIAPI
51 IsBootStatePresent (
52 VOID
53 );
54
55 /**
56 This function checks is the very first boot after BIOS flash or Capsule update for EC/BIOS.
57
58 @param[in, out] BootStateAfterCapsule out,0 its second boot after capsule updated
59 out,1 its very first boot after capsule updated
60 @retval status Very first boot after capsule update
61 @retval EFI_SUCCESS NOT the first boot path after capsule update
62 **/
63
64 EFI_STATUS
65 EFIAPI
66 GetBootStateAfterCapsule (
67 BOOLEAN *BootStateAfterCapsule
68 );
69
70 /**
71 Set BootStateAfterCapsule variable to indicate the following boot is the very first boot after Capsule Update.
72
73 @param[in] BootStateAfterCapsule TRUE, Following boot is the first boot after Capsule Update.
74 FALSE, following boot is NOT the first boot after Capsule update.
75 @retval EFI_SUCCESS BootStateAfterCapsule variable set.
76 **/
77
78 EFI_STATUS
79 EFIAPI
80 SetBootStateAfterCapsule (
81 IN BOOLEAN BootStateAfterCapsule
82 );
83
84 /**
85 This function call use to set bootstate variable.
86 In DXE phase BootState variable got set using setvariable().Form onward it will treat as second boot.
87
88 @param[in] BootState Set value for bootstate
89 **/
90
91 VOID
92 EFIAPI
93 SetBootState (
94 VOID
95 );
96
97 /**
98 Delete BootState variable to force next boot is FullConfiguration boot
99 **/
100
101 VOID
102 EFIAPI
103 UnsetBootState (
104 VOID
105 );
UnsetBootState
VOID UnsetBootState(VOID)
Delete BootState variable to force next boot is FullConfiguration boot.
IsBootStatePresent
BOOLEAN IsBootStatePresent(VOID)
This function call Checks BootState variable is NULL or not.
SetBootState
VOID SetBootState(VOID)
This function call use to set bootstate variable.
SetBootStateAfterCapsule
EFI_STATUS SetBootStateAfterCapsule(IN BOOLEAN BootStateAfterCapsule)
Set BootStateAfterCapsule variable to indicate the following boot is the very first boot after Capsul...
GetBootStateAfterCapsule
EFI_STATUS GetBootStateAfterCapsule(BOOLEAN *BootStateAfterCapsule)
This function checks is the very first boot after BIOS flash or Capsule update for EC/BIOS.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CastroCovePmicNvm.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CastroCovePmicNvm.h File Reference

This file is for CastroCove Pmic Nvm update. More...

Go to the source code of this file.

Detailed Description

This file is for CastroCove Pmic Nvm update.

Copyright
Copyright (c) 2020 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification

Definition in file CastroCovePmicNvm.h.


AlderLake Platform Sample Code: CastroCovePmicNvm.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CastroCovePmicNvm.h
Go to the documentation of this file.
1 /**@file
2 This file is for CastroCove Pmic Nvm update
3
4 @copyright
5 Copyright (c) 2020 Intel Corporation. All rights reserved
6 This software and associated documentation (if any) is furnished
7 under a license and may only be used or copied in accordance
8 with the terms of the license. Except as permitted by the
9 license, no part of this software or documentation may be
10 reproduced, stored in a retrieval system, or transmitted in any
11 form or by any means without the express written consent of
12 Intel Corporation.
13 This file contains an 'Intel Peripheral Driver' and is uniquely
14 identified as "Intel Reference Module" and is licensed for Intel
15 CPUs and chipsets under the terms of your license agreement with
16 Intel or your vendor. This file may be modified by the user, subject
17 to additional terms of the license agreement.
18
19 @par Specification
20 **/
21
22 #ifndef _CASTRO_COVE_PMIC_NVM_H_
23 #define _CASTRO_COVE_PMIC_NVM_H_
24
25 typedef
26 EFI_STATUS
27 (EFIAPI *CASTRO_COVE_PMIC_READ8) (
28 IN UINT32 RegisterOffset,
29 IN UINT8 *Value,
30 IN UINT8 PmicId
31 );
32
33 typedef
34 EFI_STATUS
35 (EFIAPI *CASTRO_COVE_PMIC_WRITE8) (
36 IN UINT32 RegisterOffset,
37 IN UINT8 Value,
38 IN UINT8 PmicId
39 );
40
41 typedef
42 EFI_STATUS
43 (EFIAPI *CASTRO_COVE_PMIC_NVM_READ_FROM_FV) (
44 IN OUT UINT8 **Buffer,
45 IN OUT UINTN *Size,
46 IN EFI_GUID *PmicNvmFvFileGuid
47 );
48
49 typedef
50 EFI_STATUS
51 (EFIAPI *CASTRO_COVE_PMIC_NVM_UPDATE_CRITERIA_CHECK) (
52 IN UINT8 *Buffer,
53 IN UINTN Size,
54 IN UINT8 PmicId
55 );
56
57 typedef
58 EFI_STATUS
59 (EFIAPI *CASTRO_COVE_PMIC_NVM_UPDATE) (
60 IN UINT8 *Buffer,
61 IN UINTN Size,
62 IN UINT8 DesiredPayloadType,
63 IN UINT8 PmicId,
64 IN OUT UINT8 *PayloadFvBuffer,
65 IN OUT UINT16 *PayloadFvSize
66 );
67
68 typedef
69 EFI_STATUS
70 (EFIAPI *CASTRO_COVE_PMIC_NVM_UPDATE_FROM_APP) (
71 IN UINT8 *Buffer,
72 IN UINTN Size
73 );
74
75 typedef
76 EFI_STATUS
77 (EFIAPI *CASTRO_COVE_PMIC_READ_FROM_NVM) (
78 IN OUT UINT8 **Buffer,
79 IN OUT UINT16 *Size,
80 IN UINT16 StartAddress,
81 IN UINT8 PmicId
82 );
83
84 typedef
85 EFI_STATUS
86 (EFIAPI *CASTRO_COVE_PMIC_WRITE_LOCK) (
87 VOID
88 );
89
90 typedef struct _EFI_CASTRO_COVE_PMIC_NVM_PROTOCOL {
91 CASTRO_COVE_PMIC_READ8 CastroCovePmicRead8;
92 CASTRO_COVE_PMIC_WRITE8 CastroCovePmicWrite8;
93 CASTRO_COVE_PMIC_NVM_READ_FROM_FV CastroCovePmicNvmReadFromFv;
94 CASTRO_COVE_PMIC_NVM_UPDATE_CRITERIA_CHECK CastroCovePmicNvmUpdateCriteriaCheck;
95 CASTRO_COVE_PMIC_NVM_UPDATE CastroCovePmicNvmUpdate;
96 CASTRO_COVE_PMIC_NVM_UPDATE_FROM_APP CastroCovePmicNvmUpdatefromApp;
97 CASTRO_COVE_PMIC_READ_FROM_NVM CastroCovePmicReadFromNvm;
98 CASTRO_COVE_PMIC_WRITE_LOCK CastroCovePmicWriteLock;
99 } EFI_CASTRO_COVE_PMIC_NVM_PROTOCOL;
100
101 #endif //_CASTRO_COVE_PMIC_NVM_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: ChassisIntrDetHob.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
ChassisIntrDetHob.h File Reference

Chassis Intrusion Detection Status Structures. More...

#include <Pi/PiHob.h>
Include dependency graph for ChassisIntrDetHob.h:

Go to the source code of this file.

Detailed Description

Chassis Intrusion Detection Status Structures.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file ChassisIntrDetHob.h.


AlderLake Platform Sample Code: ChassisIntrDetHob.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
ChassisIntrDetHob.h
Go to the documentation of this file.
1 /** @file
2 Chassis Intrusion Detection Status Structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _CHASSISINTRDETHOB_H_
36 #define _CHASSISINTRDETHOB_H_
37
38 #include <Pi/PiHob.h>
39
40 typedef struct {
41 EFI_HOB_GUID_TYPE EfiHobGuidType;
42 UINT8 Revision;
43 UINT8 Status;
44 UINT16 Reserved;
45 } CHASSIS_INTR_DET_HOB;
46
47 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CnvVariables.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CnvVariables.h File Reference

Declaration of Intel Connectivity Variables Structures and guids for WLAN, BT and WIGIG. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
Include dependency graph for CnvVariables.h:

Go to the source code of this file.

Detailed Description

Declaration of Intel Connectivity Variables Structures and guids for WLAN, BT and WIGIG.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev4_7_Internal.docx

Definition in file CnvVariables.h.


AlderLake Platform Sample Code: CnvVariables.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CnvVariables.h
Go to the documentation of this file.
1 /** @file
2 Declaration of Intel Connectivity Variables Structures and guids for WLAN, BT and WIGIG.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference: 559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev4_7_Internal.docx
33 **/
34
35 #ifndef __CNV_VARIABLES_H__
36 #define __CNV_VARIABLES_H__
37
38 //
39 // Statements that include other header files
40 //
41 #include <Base.h>
42 #include <Uefi.h>
43 #include <Library/UefiLib.h>
44 #include <Library/UefiBootServicesTableLib.h>
45 #include <Library/UefiRuntimeServicesTableLib.h>
46 #include <Library/DebugLib.h>
47 #include <Library/IoLib.h>
48 #include <Library/BaseMemoryLib.h>
49 #include <Library/MemoryAllocationLib.h>
50
51 // This is a variable GUID where all Intel CNV regulatory, thermal, diversity and general definitions are stored for WLAN
52 #define UEFI_INTEL_CNV_WLAN_VARIABLES_GUID \
53 { \
54 0x92daaf2f, 0xc02b, 0x455b, { 0xb2, 0xec, 0xf5, 0xa3, 0x59, 0x4f, 0x4a, 0xea } \
55 }
56
57 // This is a variable GUID where all Intel CNV regulatory, thermal, diversity and general definitions are stored for BT
58 #define UEFI_INTEL_CNV_BT_VARIABLES_GUID \
59 { \
60 0x42780dd5, 0x9a7d, 0x404c, { 0x80, 0xe4, 0x7f, 0x70, 0x94, 0x36, 0x03, 0x94 } \
61 }
62
63 // This is a variable GUID where all Intel CNV regulatory, thermal, diversity and general definitions are stored for WIGIG
64 #define UEFI_INTEL_CNV_WIGIG_VARIABLES_GUID \
65 { \
66 0xc07a1f7c, 0xfa13, 0x4fcb, { 0x92, 0xca, 0x3b, 0x32, 0xbc, 0x09, 0x2e, 0x13 } \
67 }
68
69 #pragma pack(push, 1)
70 //
71 // CNV Header Definition
72 //
73 typedef struct {
74 UINT8 Revision;
75 } UEFI_CNV_VAR_HEADER;
76
77 //
78 // Definition for Static Power Limit Configuration (SPLC)
79 //
80 #define UEFI_CNV_SPLC_VAR_NAME L"SPLC"
81 #define UEFI_CNV_SPLC_REVISION 0
82
83 typedef struct {
84 UEFI_CNV_VAR_HEADER Header; // Revision
85 UINT32 DefaultPowerLimit; // mW
86 UINT32 DefaultTimeWindow; // ms
87 } UEFI_CNV_VAR_SPLC;
88
89 //
90 // Definition for Wireless Antenna Diversity (WAND)
91 //
92 #define UEFI_CNV_WAND_VAR_NAME L"WAND"
93 #define UEFI_CNV_WAND_REVISION 0
94 #define UEFI_CNV_WIRELESS_ANTENNA_COUNT 2
95 #define UEFI_CNV_ANTENNA_A 0
96 #define UEFI_CNV_ANTENNA_B 1
97
98 typedef struct {
99 UINT8 AntennaId; // 0:Antenna A, 1:Antenna B
100 UINT8 TxRxDelay; // nSecDelay, possible values 1-100 in 0.1ns resolution (0.1 to 10ns).
101 UINT8 TxRxCableLength; // cm ; possible values 1-100cm in 1cm resolution.
102 } ANTENNA_DIVERSITY;
103
104 typedef struct {
105 UEFI_CNV_VAR_HEADER Header; // Revision
106 ANTENNA_DIVERSITY AntDiversity[UEFI_CNV_WIRELESS_ANTENNA_COUNT];
107 } UEFI_CNV_VAR_WAND;
108
109 //
110 // Definition for WiFi Phy Filter Configuration (WPFC)
111 //
112 #define UEFI_CNV_WPFC_VAR_NAME L"WPFC"
113 #define UEFI_CNV_WPFC_REVISION 0
114
115 typedef struct {
116 UINT32 WifiPhyFilterConfigA;
117 UINT32 WifiPhyFilterConfigB;
118 UINT32 WifiPhyFilterConfigC;
119 UINT32 WifiPhyFilterConfigD;
120 } WIFI_PHY_FILTER_CONFIG;
121
122 typedef struct {
123 UEFI_CNV_VAR_HEADER Header; // Revision
124 WIFI_PHY_FILTER_CONFIG Wpfc;
125 } UEFI_CNV_VAR_WPFC;
126 //
127 // Definition for Wireless Regulatory Domain Description (WRDD)
128 //
129 #define UEFI_CNV_WRDD_VAR_NAME L"WRDD"
130 #define UEFI_CNV_WRDD_REVISION 0
131
132 typedef struct {
133 UEFI_CNV_VAR_HEADER Header; // Revision
134 UINT16 RegulatoryDomain; // Country identifier as defined in ISO/IEC 3166-1 Alpha 2 code
135 } UEFI_CNV_VAR_WRDD;
136
137 //
138 // Definition for Wireless Regulatory Domain SAR (WRDS SAR)
139 //
140 #define UEFI_CNV_WRDS_VAR_NAME L"WRDS"
141 #define UEFI_CNV_WRDS_REVISION 0
142 #define UEFI_CNV_WRDS_WIGIG_RFE_CH_COUNT 4
143
144 //
145 // SAR Tx Power Limits
146 //
147 typedef struct {
148 UINT8 From2400; // WiFi SAR Tx Power Limit for 2400 MHz
149 UINT8 From5150To5350; // WiFi SAR Tx Power Limit for 5150-5350 MHz
150 UINT8 From5350To5470; // WiFi SAR Tx Power Limit for 5350-5470 MHz
151 UINT8 From5470To5725; // WiFi SAR Tx Power Limit for 5470-5725 MHz
152 UINT8 From5725To5950; // WiFi SAR Tx Power Limit for 5725-5950 MHz
153 } TX_POWER_LIMITS;
154
155 //
156 // Below structure to be used for WRDS - WIGIG RFE
157 //
158 typedef struct {
159 UEFI_CNV_VAR_HEADER Header; // Revision
160 UINT8 Enable; // Define the mode of RFE control to be used. 0:Tx power shall be mandated by device OTP RFE Class; 1:Tx power shall be the minimum between BIOS RFE table and OTP RFE Class
161 UINT8 Channel[UEFI_CNV_WRDS_WIGIG_RFE_CH_COUNT]; // RFE WiGig Channel 1 to 4
162 } UEFI_CNV_VAR_WRDS_WIGIG_RFE;
163
164 //
165 // Below structure to be used for WRDS - WIFI SAR
166 //
167 typedef struct {
168 TX_POWER_LIMITS ChainATxPowerLimits; // Chain Function A
169 TX_POWER_LIMITS ChainBTxPowerLimits; // Chain Function B
170 } SAR_VALUES;
171
172 typedef struct {
173 UEFI_CNV_VAR_HEADER Header; // Revision
174 UINT8 Enable; // Configures the source location of the WiFi SAR table to be used; 0:Device ignores BIOS configuration; 1:Device uses BIOS configuration
175 SAR_VALUES SarValues; // SAR Values for Chain Function A and B
176 } UEFI_CNV_VAR_WRDS_WIFI_SAR;
177
178 //
179 // Definition for Bluetooth wireless Regulatory Domain SAR (BRDS)
180 //
181 #define UEFI_CNV_BRDS_VAR_NAME L"BRDS"
182 #define UEFI_CNV_BRDS_REVISION 0
183 typedef struct {
184 UEFI_CNV_VAR_HEADER Header; // Revision
185 UINT8 Enable; // Define the mode of SAR control to be used.0: Tx power shall be mandated by device NVM; 1: Tx power shall be the minimum between BIOS SAR table and BT Device NVM (either Module or Platform)
186 UINT8 BrModulation; // Bluetooth SAR BR Modulation
187 UINT8 Edr2Modulation; // Bluetooth SAR EDR2 Modulation
188 UINT8 Edr3Modulation; // Bluetooth SAR EDR3 Modulation
189 UINT8 LeModulation; // Bluetooth SAR LE Modulation
190 UINT8 Le2MhzModulation; // Bluetooth SAR LE 2Mhz Modulation
191 UINT8 LeLrModulation; // Bluetooth SAR LE LR Modulation
192 } UEFI_CNV_VAR_BRDS;
193
194 //
195 // Definition for Extended Wireless Regulatory Domain SAR (EWRD)
196 //
197 #define UEFI_CNV_EWRD_VAR_NAME L"EWRD"
198 #define UEFI_CNV_EWRD_REVISION 0
199 #define UEFI_CNV_EWRD_WIFI_SAR_VALUES_EXT 3
200 typedef struct {
201 UEFI_CNV_VAR_HEADER Header; // Revision
202 UINT8 WifiDynamicSarEnable; // WiFi Dynamic SAR Enable/Disable
203 UINT8 WifiDynamicSarRangeSets; // WiFi SAR Number of Optional added SAR table sets to be used: 0 - Default OTP Table, 1 - Value as mandated in WRDS object, 2-4 - Extended values as mandated in this table
204 SAR_VALUES WifiDynamicSarValuesExt[UEFI_CNV_EWRD_WIFI_SAR_VALUES_EXT]; // Extended SAR Values
205 } UEFI_CNV_VAR_EWRD;
206
207 //
208 // Definition for Wireless Geo Delta Settings (WGDS)
209 //
210 #define UEFI_CNV_WGDS_VAR_NAME L"WGDS"
211 #define UEFI_CNV_WGDS_REVISION 0
212 #define UEFI_CNV_WGDS_SAR_DELTA_GROUP 3 // 1 - FCC , 2 - EC Japan, 3 - ROW, 4-8 - Reserved
213 #define UEFI_CNV_WGDS_GROUP_1_FCC 0
214 #define UEFI_CNV_WGDS_GROUP_2_EC 1
215 #define UEFI_CNV_WGDS_GROUP_3_ROW 2
216
217 typedef struct {
218 UINT8 MaxAllowed; // 2400 and 5200 MHZ Max Allowed
219 UINT8 ChainA; // Chain A Offset
220 UINT8 ChainB; // Chain B Offset
221 } GEO_SAR_OFFSET;
222
223 typedef struct {
224 GEO_SAR_OFFSET GeoSarOffset2400Mhz;
225 GEO_SAR_OFFSET GeoSarOffset5200Mhz;
226 } GEO_SAR_DELTA;
227
228 typedef struct {
229 UEFI_CNV_VAR_HEADER Header; // Revision
230 GEO_SAR_DELTA WifiSarPowerDelta[UEFI_CNV_WGDS_SAR_DELTA_GROUP]; // WiFi SAR Output Power Delta
231 } UEFI_CNV_VAR_WGDS;
232
233 //
234 // Definition for Antenna Weight Vectors Class Index (AWVC)
235 //
236 #define UEFI_CNV_AWVC_VAR_NAME L"AWVC"
237 typedef struct {
238 UINT32 ClassIndex; // Platform Characteristics Reference ID
239 } UEFI_CNV_VAR_AWVC;
240
241 //
242 // Definition for Switched Antenna Diversity Selection (SADS)
243 //
244 #define UEFI_CNV_SADS_VAR_NAME L"SADS"
245 #define UEFI_CNV_SADS_REVISION 0
246 typedef struct {
247 UEFI_CNV_VAR_HEADER Header; // Revision
248 UINT8 AntDiversitySel; // 0:Antenna1, 1:Antenna2, 2:Diversity, 3:Diversity Antenna1, 4:Diversity Antenna2
249 } UEFI_CNV_VAR_SADS;
250
251 //
252 // Definition for General Purpose Configuration (GPC)
253 //
254 #define UEFI_CNV_GPC_VAR_NAME L"GPC"
255 #define UEFI_CNV_GPC_REVISION 0
256 #define UEFI_CNV_GPC_TLV_MAX_DWORD_VALUES 1
257 #define UEFI_CNV_GPC_TLV_MAX_WIFI_BT_CORE 1
258
259 typedef struct {
260 UINT32 Type; // The type of configuration which is defined in the structure
261 UINT32 Length; // The length of the value
262 UINT32 Value[UEFI_CNV_GPC_TLV_MAX_DWORD_VALUES]; // The value/data of the type
263 } TLV;
264
265 typedef struct {
266 UEFI_CNV_VAR_HEADER Header; // Revision
267 TLV Tlv[UEFI_CNV_GPC_TLV_MAX_WIFI_BT_CORE]; // GPC TLV for WiFi / BT Core
268 } UEFI_CNV_VAR_GPC;
269 #pragma pack(pop)
270
271 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CommonDefinitions.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CommonDefinitions.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CommonDefinitions.h.


AlderLake Platform Sample Code: CommonDefinitions.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CommonDefinitions.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _COMMON_DEFINITIONS_H_
34 #define _COMMON_DEFINITIONS_H_
35
36 //
37 // PCI CONFIGURATION MAP REGISTER OFFSETS
38 //
39 #define PCI_VID 0x0000 // Vendor ID Register
40 #define PCI_DID 0x0002 // Device ID Register
41 #define PCI_CMD 0x0004 // PCI Command Register
42 #define PCI_STS 0x0006 // PCI Status Register
43 #define PCI_RID 0x0008 // Revision ID Register
44 #define PCI_IFT 0x0009 // Interface Type
45 #define PCI_SCC 0x000A // Sub Class Code Register
46 #define PCI_BCC 0x000B // Base Class Code Register
47 #define PCI_CLS 0x000C // Cache Line Size
48 #define PCI_PMLT 0x000D // Primary Master Latency Timer
49 #define PCI_HDR 0x000E // Header Type Register
50 #define PCI_BIST 0x000F // Built in Self Test Register
51 #define PCI_BAR0 0x0010 // Base Address Register 0
52 #define PCI_BAR1 0x0014 // Base Address Register 1
53 #define PCI_BAR2 0x0018 // Base Address Register 2
54 #define PCI_PBUS 0x0018 // Primary Bus Number Register
55 #define PCI_SBUS 0x0019 // Secondary Bus Number Register
56 #define PCI_SUBUS 0x001A // Subordinate Bus Number Register
57 #define PCI_SMLT 0x001B // Secondary Master Latency Timer
58 #define PCI_BAR3 0x001C // Base Address Register 3
59 #define PCI_IOBASE 0x001C // I/O base Register
60 #define PCI_IOLIMIT 0x001D // I/O Limit Register
61 #define PCI_SECSTATUS 0x001E // Secondary Status Register
62 #define PCI_BAR4 0x0020 // Base Address Register 4
63 #define PCI_MEMBASE 0x0020 // Memory Base Register
64 #define PCI_MEMLIMIT 0x0022 // Memory Limit Register
65 #define PCI_BAR5 0x0024 // Base Address Register 5
66 #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register
67 #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register
68 #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits
69 #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits
70 #define PCI_SVID 0x002C // Subsystem Vendor ID
71 #define PCI_SID 0x002E // Subsystem ID
72 #define PCI_IOBASE_U 0x0030 // I/O base Upper Register
73 #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register
74 #define PCI_CAPP 0x0034 // Capabilities Pointer
75 #define PCI_EROM 0x0038 // Expansion ROM Base Address
76 #define PCI_INTLINE 0x003C // Interrupt Line Register
77 #define PCI_INTPIN 0x003D // Interrupt Pin Register
78 #define PCI_MAXGNT 0x003E // Max Grant Register
79 #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register
80 #define PCI_MAXLAT 0x003F // Max Latency Register
81
82 //
83 // Bit Difinitions
84 //
85 #ifndef BIT0
86 #define BIT0 0x0001
87 #define BIT1 0x0002
88 #define BIT2 0x0004
89 #define BIT3 0x0008
90 #define BIT4 0x0010
91 #define BIT5 0x0020
92 #define BIT6 0x0040
93 #define BIT7 0x0080
94 #define BIT8 0x0100
95 #define BIT9 0x0200
96 #ifndef BIT10
97 #define BIT10 0x0400
98 #define BIT11 0x0800
99 #define BIT12 0x1000
100 #define BIT13 0x2000
101 #define BIT14 0x4000
102 #define BIT15 0x8000
103 #define BIT16 0x00010000
104 #define BIT17 0x00020000
105 #define BIT18 0x00040000
106 #define BIT19 0x00080000
107 #define BIT20 0x00100000
108 #define BIT21 0x00200000
109 #define BIT22 0x00400000
110 #define BIT23 0x00800000
111 #define BIT24 0x01000000
112 #define BIT25 0x02000000
113 #define BIT26 0x04000000
114 #define BIT27 0x08000000
115 #define BIT28 0x10000000
116 #define BIT29 0x20000000
117 #define BIT30 0x40000000
118 #define BIT31 0x80000000
119 #ifndef BIT32
120 #define BIT32 0x100000000
121 #define BIT33 0x200000000
122 #define BIT34 0x400000000
123 #define BIT35 0x800000000
124 #define BIT36 0x1000000000
125 #define BIT37 0x2000000000
126 #define BIT38 0x4000000000
127 #define BIT39 0x8000000000
128 #define BIT40 0x10000000000
129 #define BIT41 0x20000000000
130 #define BIT42 0x40000000000
131 #define BIT43 0x80000000000
132 #define BIT44 0x100000000000
133 #define BIT45 0x200000000000
134 #define BIT46 0x400000000000
135 #define BIT47 0x800000000000
136 #define BIT48 0x1000000000000
137 #define BIT49 0x2000000000000
138 #define BIT50 0x4000000000000
139 #define BIT51 0x8000000000000
140 #define BIT52 0x10000000000000
141 #define BIT53 0x20000000000000
142 #define BIT54 0x40000000000000
143 #define BIT55 0x80000000000000
144 #define BIT56 0x100000000000000
145 #define BIT57 0x200000000000000
146 #define BIT58 0x400000000000000
147 #define BIT59 0x800000000000000
148 #define BIT60 0x1000000000000000
149 #define BIT61 0x2000000000000000
150 #define BIT62 0x4000000000000000
151 #define BIT63 0x8000000000000000
152 #endif
153 #endif
154 #endif
155
156 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CpuPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
CpuPolicyInitDxe.c File Reference

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation. More...

#include <CpuPolicyInitDxe.h>
Include dependency graph for CpuPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS CpuPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy. More...

Detailed Description

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file CpuPolicyInitDxe.c.

Function Documentation

◆ CpuPolicyInitDxe()

EFI_STATUS CpuPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Platform Policy.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 50 of file CpuPolicyInitDxe.c.


AlderLake Platform Sample Code: CpuPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
CpuPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #include <CpuPolicyInitDxe.h>
35
36 DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
37
38 /**
39 Initilize Intel CPU DXE Platform Policy
40
41 @param[in] ImageHandle Image handle of this driver.
42
43 @retval EFI_SUCCESS Initialization complete.
44 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
45 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
46 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
47 **/
48 EFI_STATUS
49 EFIAPI
50 CpuPolicyInitDxe (
51 IN EFI_HANDLE ImageHandle
52 )
53 {
54 EFI_STATUS Status;
55
56 ZeroMem (&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
57 mCpuPolicyData.Revision = DXE_CPU_POLICY_PROTOCOL_REVISION;
58
59 UpdateDxeSiCpuPolicy (&mCpuPolicyData);
60
61 //
62 // Install CpuInstallPolicyProtocol.
63 // While installed, RC assumes the Policy is ready and finalized. So please
64 // update and override any setting before calling this function.
65 //
66 Status = CpuInstallPolicyProtocol (ImageHandle, &mCpuPolicyData);
67 ASSERT_EFI_ERROR (Status);
68
69 return Status;
70 }
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy.
Definition: CpuPolicyInitDxe.c:50
UpdateDxeSiCpuPolicy
EFI_STATUS UpdateDxeSiCpuPolicy(IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description:
CpuInstallPolicyProtocol
EFI_STATUS CpuInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy.
CpuPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CpuPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
CpuPolicyInitDxe.h File Reference

Header file for the SiliconPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Protocol/CpuPolicyProtocol.h>
#include <Library/DxeCpuPolicyUpdateLib.h>
Include dependency graph for CpuPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS CpuPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy. More...

Detailed Description

Header file for the SiliconPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file CpuPolicyInitDxe.h.

Function Documentation

◆ CpuPolicyInitDxe()

EFI_STATUS CpuPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 50 of file CpuPolicyInitDxe.c.


AlderLake Platform Sample Code: CpuPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
CpuPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SiliconPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef _CPU_POLICY_INIT_DXE_H_
36 #define _CPU_POLICY_INIT_DXE_H_
37
38 #include <Library/BaseMemoryLib.h>
39 #include <Library/MemoryAllocationLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/BaseLib.h>
42
43 #include <Protocol/CpuPolicyProtocol.h>
44 #include <Library/DxeCpuPolicyUpdateLib.h>
45
46
47 /**
48 Initilize Intel CPU DXE Policy
49
50 @param[in] ImageHandle Image handle of this driver.
51
52 @retval EFI_SUCCESS Initialization complete.
53 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
54 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
55 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
56 **/
57 EFI_STATUS
58 EFIAPI
59 CpuPolicyInitDxe (
60 IN EFI_HANDLE ImageHandle
61 );
62
63 #endif
DxeCpuPolicyUpdateLib.h
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy.
Definition: CpuPolicyInitDxe.c:50
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CrashLog.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
CrashLog.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CrashLog.h.


AlderLake Platform Sample Code: CrashLog.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
CrashLog.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2018 - 2020 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __CRASHLOG_H__
35 #define __CRASHLOG_H__
36
37 #define CRASHLOG_SIZE_DEBUG_PURPOSE 0x030 // It will help to verify the extracted binary from BERT by matching the binary content
38 #define CRASHLOG_MECH_LEGACY 0 // Get PMC crash log by using legacy mode
39 #define CRASHLOG_MECH_DESCRIPTOR_TABLE 1 // Get PMC crash log by using descriptor table
40
41 //
42 // Structure of CrashLog Hob data
43 //
44 typedef struct {
45 UINT64 AllocateAddress;
46 UINT32 Size;
47 } CRASHLOG_HOB;
48
49 //
50 // Structure of CPU CrashLog Hob data
51 //
52 typedef struct {
53 CRASHLOG_HOB Main;
54 CRASHLOG_HOB Trace;
55 CRASHLOG_HOB Telemetry;
56 } CPU_CRASHLOG_HOB;
57
58 //
59 // CRASHLOG_VERSON
60 //
61 typedef union {
62 struct {
63 UINT32 Revision : 8; // Revision
64 UINT32 HeaderType : 4; // Crash record header type
65 UINT32 ProductId : 12; // Product ID
66 UINT32 CrashType : 6; // Crash record type
67 UINT32 Rsvd : 1; // Reserved
68 UINT32 Consumed : 1; // Consumed
69 } Bits;
70 UINT32 Uint32;
71 } CRASHLOG_VERSION;
72
73 //
74 // CRASHLOG_REASON
75 //
76 typedef union {
77 struct {
78 UINT32 CWReset : 1; // Cold/Warm reset
79 UINT32 GReset : 1; // Global reset
80 UINT32 Error : 1; // Error
81 UINT32 MInit : 1; // Manually Initiated
82 UINT32 Reserved : 28;
83 } Bits;
84 UINT32 Uint32;
85 } CRASHLOG_REASON;
86
87 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: CustomOptionControl.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CustomOptionControl.h File Reference
#include <SetupVariable.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/DebugLib.h>
Include dependency graph for CustomOptionControl.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file CustomOptionControl.h.


AlderLake Platform Sample Code: CustomOptionControl.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
CustomOptionControl.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2016 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _CUSTOM_OPTION_CONTROL_H_
35 #define _CUSTOM_OPTION_CONTROL_H_
36
37 #include <SetupVariable.h>
38 #include <Ppi/ReadOnlyVariable2.h>
39 #include <Library/DebugLib.h>
40 //#include <PchPolicyCommon.h>
41
42 extern EFI_GUID gMsftGlobalVariableGuid;
43
44
45 #pragma pack(1)
46 typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO {
47 UINT8 RevisonId; // Structure Revision ID
48 UINT8 HotkeyTriggered; // Hot key status
49 } ATTEMPT_USB_FIRST_HOTKEY_INFO;
50 #pragma pack()
51
52 #pragma pack(1)
53 typedef struct _ATTEMPT_USB_FIRST_VARIABLE {
54 UINT8 UsbBootPrior;
55 } ATTEMPT_USB_FIRST_VARIABLE;
56 #pragma pack()
57
58 //
59 // Volatile variable definition for Attempt USB first features
60 //
61 #pragma pack(1)
62 typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE {
63 UINT8 RevisonId; // Structure Revision ID
64 UINT8 UsbFirstEnable; // Attempt USB First is enabled or not
65 } ATTEMPT_USB_FIRST_RUNTIME_VARIABLE;
66 #pragma pack()
67
68 //
69 // Volatile variable definition for Enabling Flash Tools via UEFI Variable
70 //
71 #pragma pack(1)
72 typedef struct _ENABLE_FLASH_TOOLS{
73 UINT32 EnableFlashTools;
74 } ENABLE_FLASH_TOOLS;
75 #pragma pack()
76
77 //
78 // Volatile variable definition for third party Default Enabling via UEFI Variable.
79 //
80 #pragma pack(1)
81 typedef struct _ENABLE_CUSTOM_DEFAULTS{
82 UINT32 EnableCustomDefaults;
83 } ENABLE_CUSTOM_DEFAULTS;
84 #pragma pack()
85
86 #pragma pack(1)
87 typedef struct _ENABLE_CUSTOM_DEFAULTS_STATE{
88 UINT8 CurrentState;
89 } ENABLE_CUSTOM_DEFAULTS_STATE;
90 #pragma pack()
91
92 extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid;
93 extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid;
94
95 #endif // _CUSTOM_OPTION_CONTROL_H_
96
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DebugEventHandler.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
Classes | Typedefs
DebugEventHandler.h File Reference
#include <Pi/PiStatusCode.h>
Include dependency graph for DebugEventHandler.h:

Go to the source code of this file.

Classes

struct _DEBUG_EVENT_HABDLER_PPI
This PPI contains a set of services to print message to debug output device. More...

Typedefs

typedef struct _DEBUG_EVENT_HABDLER_PPI DEBUG_EVENT_HABDLER_PPI
Forward declaration for the DEBUG_EVENT_HABDLER_PPI.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DebugEventHandler.h.


AlderLake Platform Sample Code: DebugEventHandler.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
DebugEventHandler.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2020 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __FSPWRAPPER_DEBUG_EVENT_HABDLER_PPI_H__
35 #define __FSPWRAPPER_DEBUG_EVENT_HABDLER_PPI_H__
36
37 #include <Pi/PiStatusCode.h>
38
39 //
40 // Global ID for the DEBUG_EVENT_HABDLER_PPI
41 //
42 #define DEBUG_EVENT_HABDLER_PPI_GUID \
43 { \
44 0x6e6f5daa, 0x77cb, 0x48ff, { 0xb3, 0x18, 0x2d, 0x5e, 0x62, 0x0, 0xd0, 0x1e } \
45 }
46
47 ///
48 /// Forward declaration for the DEBUG_EVENT_HABDLER_PPI
49 ///
50 typedef struct _DEBUG_EVENT_HABDLER_PPI DEBUG_EVENT_HABDLER_PPI;
51
52 /*
53 FSP Wrapper debug event handler
54
55 @param[in] Type Indicates the type of event being reported.
56 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE.
57 @param[in] Value Describes the current status of a hardware or software entity.
58 This includes information about the class and subclass that is used to classify the entity as well as an operation.
59 For progress events, the operation is the current activity. For error events, it is the exception.
60 For debug events, it is not defined at this time.
61 See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE.
62 @param[in] Instance The enumeration of a hardware or software entity within the system.
63 A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them.
64 An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant.
65 Valid instance numbers start with 1.
66 @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event.
67 This parameter may be NULL.
68 @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data.
69 For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages.
70 This parameter is NULL when no additional data is provided.
71
72 @retval EFI_SUCCESS The event was handled successfully.
73 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
74 @retval EFI_DEVICE_ERROR The event handler failed.
75 */
76 typedef
77 EFI_STATUS
78 (EFIAPI *FSP_EVENT_HANDLER) (
79 IN EFI_STATUS_CODE_TYPE Type,
80 IN EFI_STATUS_CODE_VALUE Value,
81 IN UINT32 Instance,
82 IN OPTIONAL EFI_GUID *CallerId,
83 IN OPTIONAL EFI_STATUS_CODE_DATA *Data
84 );
85
86 ///
87 /// This PPI contains a set of services to print message to debug output device
88 ///
89 struct _DEBUG_EVENT_HABDLER_PPI {
90 FSP_EVENT_HANDLER DebugEventHandler;
91 };
92
93 extern EFI_GUID gDebugEventHandlerPpiGuid;
94
95 #endif
96
_DEBUG_EVENT_HABDLER_PPI
This PPI contains a set of services to print message to debug output device.
Definition: DebugEventHandler.h:89
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DimmInfo.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
DimmInfo.h File Reference

This header file provides Dimm info definitions used by other modules for dimm info presentation. More...

#include <Protocol/MemInfo.h>
Include dependency graph for DimmInfo.h:

Go to the source code of this file.

Detailed Description

This header file provides Dimm info definitions used by other modules for dimm info presentation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DimmInfo.h.


AlderLake Platform Sample Code: DimmInfo.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
DimmInfo.h
Go to the documentation of this file.
1 /** @file
2 This header file provides Dimm info definitions used by other
3 modules for dimm info presentation.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __DIMM_INFO_H__
37 #define __DIMM_INFO_H__
38
39 #include <Protocol/MemInfo.h>
40 #define MAX_LENGTH 10
41
42 typedef struct {
43 UINT16 MfgId;
44 CHAR8 String[16];
45 } MEMORY_MODULE_MANUFACTURER_LIST;
46
47 typedef enum {
48 DDR4,
49 DDR3,
50 LPDDR3,
51 LPDDR4,
52 NUM_DDR_TYPES
53 } DDR_TYPE;
54
55 typedef struct {
56 UINT8 DdrTypeNum;
57 CHAR8 Meaning[MAX_LENGTH];
58 } SMBIOS_MEMORY_DEVICE_TYPE_LIST;
59
60 extern CHAR8 *MemoryTypeStr[];
61 extern MEMORY_MODULE_MANUFACTURER_LIST MemoryModuleManufacturerList[];
62 extern UINT8 MemoryModuleManufacturerListSize;
63 extern SMBIOS_MEMORY_DEVICE_TYPE_LIST MemoryTypeList[];
64 extern UINT8 MemoryTypeListSize;
65
66 #endif // __DIMM_INFO_H__
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeAcpiGnvsInitLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeAcpiGnvsInitLib.h File Reference

Acpi Gnvs Init Library header file. More...

#include <Base.h>
Include dependency graph for DxeAcpiGnvsInitLib.h:

Go to the source code of this file.

Functions

EFI_STATUS AcpiGnvsInit (IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize. More...

Detailed Description

Acpi Gnvs Init Library header file.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeAcpiGnvsInitLib.h.

Function Documentation

◆ AcpiGnvsInit()

EFI_STATUS AcpiGnvsInit ( IN OUT VOID ** PlatformNvsAreaPtr )

Global NVS initialize.

Parameters
[in] PlatformNvsAreaPtr - Pointer of global NVS area
Return values
EFI_SUCCESS | - Allocate Global NVS completed.
EFI_OUT_OF_RESOURCES | - Failed to allocate required page for PlatformNvsAreaProtocol.


AlderLake Platform Sample Code: DxeAcpiGnvsInitLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeAcpiGnvsInitLib.h
Go to the documentation of this file.
1 /** @file
2 Acpi Gnvs Init Library header file.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Base.h>
36
37
38 /**
39 @brief
40 Global NVS initialize.
41
42 @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
43
44 @retval EFI_SUCCESS - Allocate Global NVS completed.
45 @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol.
46 **/
47 EFI_STATUS
48 EFIAPI
49 AcpiGnvsInit (
50 IN OUT VOID **PlatformNvsAreaPtr
51 );
52
AcpiGnvsInit
EFI_STATUS AcpiGnvsInit(IN OUT VOID **PlatformNvsAreaPtr)
Global NVS initialize.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeAmtPolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeAmtPolicyUpdateLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS UpdateDxeAmtPolicy (IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
Install DxeAmtPolicy with setup values. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeAmtPolicyUpdateLib.h.

Function Documentation

◆ UpdateDxeAmtPolicy()

EFI_STATUS UpdateDxeAmtPolicy ( IN OUT AMT_POLICY_PROTOCOL * DxeAmtPolicy )

Install DxeAmtPolicy with setup values.

Parameters
[in,out] DxeAmtPolicy DXE Amt Policy
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.


AlderLake Platform Sample Code: DxeAmtPolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeAmtPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2018 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _DXE_AMT_POLICY_UPDATE_LIB_H_
34 #define _DXE_AMT_POLICY_UPDATE_LIB_H_
35
36 /**
37 Install DxeAmtPolicy with setup values
38
39 @param[in, out] DxeAmtPolicy DXE Amt Policy
40
41 @retval EFI_SUCCESS Initialization complete.
42 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
43 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
44 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
45 **/
46 EFI_STATUS
47 UpdateDxeAmtPolicy (
48 IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy
49 );
50
51 #endif
52
UpdateDxeAmtPolicy
EFI_STATUS UpdateDxeAmtPolicy(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
Install DxeAmtPolicy with setup values.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeCpuPolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeCpuPolicyUpdateLib.h File Reference
#include <PiDxe.h>
#include <SetupVariable.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/CpuPolicyProtocol.h>
Include dependency graph for DxeCpuPolicyUpdateLib.h:
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Functions

VOID | CpuDxePrintPolicyProtocol (IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
This function prints the CPU DXE phase policy. More...
EFI_STATUS | UpdateDxeSiCpuPolicy (IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description: More...
EFI_STATUS | CpuInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeCpuPolicyUpdateLib.h.

Function Documentation

◆ CpuDxePrintPolicyProtocol()

VOID CpuDxePrintPolicyProtocol ( IN DXE_CPU_POLICY_PROTOCOL * DxeCpuPolicy )

This function prints the CPU DXE phase policy.

Parameters
[in] DxeCpuPolicy - CPU DXE Policy protocol

◆ CpuInstallPolicyProtocol()

EFI_STATUS CpuInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN DXE_CPU_POLICY_PROTOCOL * | DxeCpuPolicy
 | ) |  |

CpuInstallPolicyProtocol installs CPU Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | DxeCpuPolicy | The pointer to CPU Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ UpdateDxeSiCpuPolicy()

EFI_STATUS UpdateDxeSiCpuPolicy ( IN OUT DXE_CPU_POLICY_PROTOCOL * DxeCpuPolicy )

Routine Description:

This function updates Dxe Cpu Policy Protocol

Arguments:

Parameters
[in] DxeCpuPolicy The Cpu Policy protocol instance

Returns:

Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.


AlderLake Platform Sample Code: DxeCpuPolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeCpuPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2018 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_
34 #define _DXE_CPU_POLICY_UPDATE_LIB_H_
35
36 #include <PiDxe.h>
37 #include <SetupVariable.h>
38 #include <Library/DebugLib.h>
39 #include <Library/BaseMemoryLib.h>
40 #include <Library/UefiRuntimeServicesTableLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Protocol/CpuPolicyProtocol.h>
43
44 /**
45
46 This function prints the CPU DXE phase policy.
47
48 @param[in] DxeCpuPolicy - CPU DXE Policy protocol
49
50 **/
51 VOID
52 CpuDxePrintPolicyProtocol (
53 IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
54 );
55
56 /**
57
58 Routine Description:
59
60 This function updates Dxe Cpu Policy Protocol
61
62 Arguments:
63
64 @param[in] DxeCpuPolicy The Cpu Policy protocol instance
65
66 Returns:
67
68 @retval EFI_SUCCESS Initialization complete.
69 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
70 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
71 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
72
73 **/
74 EFI_STATUS
75 EFIAPI
76 UpdateDxeSiCpuPolicy (
77 IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
78 );
79
80 /**
81
82 CpuInstallPolicyProtocol installs CPU Policy.
83 While installed, RC assumes the Policy is ready and finalized. So please update and override
84 any setting before calling this function.
85
86 @param[in] ImageHandle Image handle of this driver.
87 @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol instance
88
89 @retval EFI_SUCCESS The policy is installed.
90 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
91
92 **/
93 EFI_STATUS
94 EFIAPI
95 CpuInstallPolicyProtocol (
96 IN EFI_HANDLE ImageHandle,
97 IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
98 );
99
100 #endif
UpdateDxeSiCpuPolicy
EFI_STATUS UpdateDxeSiCpuPolicy(IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
Routine Description:
CpuInstallPolicyProtocol
EFI_STATUS CpuInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
CpuInstallPolicyProtocol installs CPU Policy.
CpuDxePrintPolicyProtocol
VOID CpuDxePrintPolicyProtocol(IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy)
This function prints the CPU DXE phase policy.
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeFirmwareVersionInfoLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeFirmwareVersionInfoLib.h File Reference

Private data structures. More...

Go to the source code of this file.

Detailed Description

Private data structures.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeFirmwareVersionInfoLib.h.


AlderLake Platform Sample Code: DxeFirmwareVersionInfoLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeFirmwareVersionInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Private data structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _DXE_FIRMWARE_VERSION_INFO_LIB_H_
36 #define _DXE_FIRMWARE_VERSION_INFO_LIB_H_
37
38 #define PLATFORM_FVI_STATUS_DISABLED "Disabled"
39 #define PLATFORM_FVI_STATUS_ENABLED "Enabled "
40
41 #define PLATFORM_FVI_SETUP_NAME L"PlatformFviSetupDataVar"
42
43 //
44 // Ensure proper structure formats
45 //
46 #pragma pack(1)
47
48 typedef struct {
49 UINT8 LanPhyVersion;
50 UINT16 IccMajorVersion;
51 UINT16 IccMinorVersion;
52 UINT16 IccHotfixVersion;
53 UINT16 IccBuildVersion;
54 } PLATFORM_FVI_SETUP;
55
56 #pragma pack()
57
58
59 #define SENSOR_FW_FVI_STRING "Sensor Firmware Version"
60 #define SENSOR_FW_VERSION \
61 { \
62 0xFF, 0xFF, 0xFF, 0xFFFF \
63 }
64
65 #define LAN_PHY_FVI_STRING "Lan Phy Version"
66 #define LAN_PHY_VERSION \
67 { \
68 0xFF, 0xFF, 0xFF, 0xFFFF \
69 }
70
71 #define DEBUG_MODE_STATUS "Debug Mode Status"
72 #define DEBUG_MODE_VERSION \
73 { \
74 0xFF, 0xFF, 0xFF, 0xFFFF \
75 }
76
77 #define PERFORMANCE_MODE_STATUS "Performance Mode Status"
78 #define PERFORMANCE_MODE_VERSION \
79 { \
80 0xFF, 0xFF, 0xFF, 0xFFFF \
81 }
82
83 #define DEBUG_USE_USB_STATUS "Debug Use USB(Disabled:Serial)"
84 #define DEBUG_USE_USB_VERSION \
85 { \
86 0xFF, 0xFF, 0xFF, 0xFFFF \
87 }
88
89 #define ICC_OVERLOCKING_FVI_STRING "ICC Overclocking Version"
90 #define ICC_OVERLOCKING_VERSION \
91 { \
92 0xFF, 0xFF, 0xFF, 0xFFFF \
93 }
94
95 #define UNDI_FVI_STRING "UNDI Version"
96 #define UNDI_VERSION \
97 { \
98 0xFF, 0xFF, 0xFF, 0xFFFF \
99 }
100
101 #define EC_FVI_STRING "EC FW Version"
102 #define EC_VERSION \
103 { \
104 0xFF, 0xFF, 0xFF, 0xFFFF \
105 }
106
107 #define GOP_FVI_STRING "GOP Version"
108 #define GOP_VERSION \
109 { \
110 0xFF, 0xFF, 0xFF, 0xFFFF \
111 }
112
113 #define ROYALPARK_FVI_STRING "Royal Park Version"
114 #define ROYALPARK_VERSION \
115 { \
116 0xFF, 0xFF, 0xFF, 0xFFFF \
117 }
118
119 #define PLATFORM_FVI_STRING "Platform Version"
120 #define PLATFORM_VERSION \
121 { \
122 0xFF, 0xFF, 0xFF, 0xFFFF \
123 }
124
125 enum {
126 LAN_PHY_VER = 0,
127 SENSOR_FW_VER,
128 DEBUG_MODE_VER,
129 PERFORMANCE_MODE_VER,
130 DEBUB_USE_USB_VER,
131 ICC_OVERLOCKING_VER,
132 UNDI_VER,
133 EC_VER,
134 GOP_VER,
135 ROYALPARK_VER,
136 PLATFORM_VER,
137 } PLATFORM_FVI_INDEX;
138
139 #define SENSOR_HUB_FW_VERSION_OFFSET 0x1000
140 #define SENSOR_HUB_FW_VERSION_LENGTH 0x04
141
142 //
143 // LAN PHY Revision definitions
144 //
145 #define LAN_PHY_REV_TC 0xA0
146 #define LAN_PHY_REV_A0 0xA1
147 #define LAN_PHY_REV_A1 0xA2
148 #define LAN_PHY_REV_A2 0xA3
149 #define LAN_PHY_REV_A3 0xA4
150 #define LAN_PHY_REV_B1 0xA5
151
152
153 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeMePolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeMePolicyUpdateLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS UpdateDxeMePolicy (IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeMePolicyUpdateLib.h.

Function Documentation

◆ UpdateDxeMePolicy()

EFI_STATUS UpdateDxeMePolicy ( IN OUT ME_POLICY_PROTOCOL * DxeMePolicy )

Update the ME Policy Library.

Parameters
[in,out] DxeMePolicy ME Policy in DXE phase
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.


AlderLake Platform Sample Code: DxeMePolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeMePolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_ME_POLICY_UPDATE_LIB_H_
35 #define _DXE_ME_POLICY_UPDATE_LIB_H_
36
37 /**
38 Update the ME Policy Library
39
40 @param[in, out] DxeMePolicy ME Policy in DXE phase
41
42 @retval EFI_SUCCESS Initialization complete.
43 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
44 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
45 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
46 **/
47 EFI_STATUS
48 UpdateDxeMePolicy (
49 IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
50 );
51
52 #endif // _DXE_ME_POLICY_UPDATE_LIB_H_
UpdateDxeMePolicy
EFI_STATUS UpdateDxeMePolicy(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeOpromPatchLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeOpromPatchLib.h File Reference
#include <Protocol/PciIo.h>
Include dependency graph for DxeOpromPatchLib.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeOpromPatchLib.h.


AlderLake Platform Sample Code: DxeOpromPatchLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeOpromPatchLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_OPROM_PATCH_LIB_H_
35 #define _DXE_OPROM_PATCH_LIB_H_
36
37 #include <Protocol/PciIo.h>
38
39 VOID
40 EFIAPI
41 OpromPatchPciIo (
42 IN EFI_PCI_IO_PROTOCOL *PciIo
43 );
44
45 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxePchPolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxePchPolicyUpdateLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS UpdateDxePchPolicy (IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePchPolicyUpdateLib.h.

Function Documentation

◆ UpdateDxePchPolicy()

EFI_STATUS UpdateDxePchPolicy ( IN OUT PCH_POLICY_PROTOCOL * PchPolicy )

Get data for platform policy from setup options.

Parameters
[in] PchPolicy The pointer to get PCH Policy protocol instance
Return values
EFI_SUCCESS Operation success.


AlderLake Platform Sample Code: DxePchPolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxePchPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_
35 #define _DXE_PCH_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] PchPolicy The pointer to get PCH Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxePchPolicy (
48 IN OUT PCH_POLICY_PROTOCOL *PchPolicy
49 );
50
51 #endif
UpdateDxePchPolicy
EFI_STATUS UpdateDxePchPolicy(IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxePlatformBootManagerLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxePlatformBootManagerLib.h File Reference

Header file for DxePlatformBootManagerLib. More...

Go to the source code of this file.

Functions

EFI_STATUS | ExpandPartitionsDevPath (IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption, OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath)
Tries to expand the given partitions device path to start with physical HDD device path. More...
BOOLEAN | IsItPartitionsDevicePath (IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption)
Checks whenever a given load option starts with a partition device path. More...
CHAR16 * | DevicePathToStr (IN EFI_DEVICE_PATH_PROTOCOL *DevPath)
This function converts an input device structure to a Unicode string. More...

Detailed Description

Header file for DxePlatformBootManagerLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference

Definition in file DxePlatformBootManagerLib.h.

Function Documentation

◆ DevicePathToStr()

CHAR16* DevicePathToStr ( IN EFI_DEVICE_PATH_PROTOCOL * DevPath )

This function converts an input device structure to a Unicode string.

Parameters
DevPath A pointer to the device path structure.
Returns
A new allocated Unicode string that represents the device path.

◆ ExpandPartitionsDevPath()

EFI_STATUS ExpandPartitionsDevPath | ( | IN EFI_BOOT_MANAGER_LOAD_OPTION * | LoadOption,
 |  | OUT EFI_DEVICE_PATH_PROTOCOL ** | BootDevicePath
 | ) |  |

Tries to expand the given partitions device path to start with physical HDD device path.

Parameters
[in] | LoadOption | pointer to an Efi Boot Manager boot option
[out] | BootDevicePath | indirect pointer to retrieved device path
Return values
EFI_SUCCESS Function found

◆ IsItPartitionsDevicePath()

BOOLEAN IsItPartitionsDevicePath ( IN EFI_BOOT_MANAGER_LOAD_OPTION * LoadOption )

Checks whenever a given load option starts with a partition device path.

Parameters
[in] LoadOption Pointer to load option to test
Return values
TRUE
FALSE
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxePlatformBootManagerLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxePlatformBootManagerLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for DxePlatformBootManagerLib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference
33 **/
34
35 #ifndef _DXE_PLATFORM_BOOT_MANAGER_LIB_H_
36 #define _DXE_PLATFORM_BOOT_MANAGER_LIB_H_
37
38
39 /**
40 Tries to expand the given partitions device path to start with physical HDD
41 device path
42 @param[in] LoadOption pointer to an Efi Boot Manager boot option
43 @param[out] BootDevicePath indirect pointer to retrieved device path
44
45 @retval EFI_SUCCESS Function found
46 **/
47 EFI_STATUS
48 ExpandPartitionsDevPath (
49 IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption,
50 OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath
51 );
52
53 /**
54 Checks whenever a given load option starts with a partition device path
55
56 @param[in] LoadOption Pointer to load option to test
57
58 @retval TRUE
59 @retval FALSE
60 **/
61 BOOLEAN
62 IsItPartitionsDevicePath(
63 IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption
64 );
65
66 /**
67 This function converts an input device structure to a Unicode string.
68
69 @param DevPath A pointer to the device path structure.
70
71 @return A new allocated Unicode string that represents the device path.
72 **/
73 CHAR16 *
74 DevicePathToStr (
75 IN EFI_DEVICE_PATH_PROTOCOL *DevPath
76 );
77
78 #endif
DevicePathToStr
CHAR16 * DevicePathToStr(IN EFI_DEVICE_PATH_PROTOCOL *DevPath)
This function converts an input device structure to a Unicode string.
IsItPartitionsDevicePath
BOOLEAN IsItPartitionsDevicePath(IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption)
Checks whenever a given load option starts with a partition device path.
ExpandPartitionsDevPath
EFI_STATUS ExpandPartitionsDevPath(IN EFI_BOOT_MANAGER_LOAD_OPTION *LoadOption, OUT EFI_DEVICE_PATH_PROTOCOL **BootDevicePath)
Tries to expand the given partitions device path to start with physical HDD device path.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxePolicyBoardConfigLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxePolicyBoardConfigLib.h File Reference

Header file for the DxePolicyBoardConfig Library. More...

#include <Protocol/AmtPolicy.h>
#include <Protocol/MePolicy.h>
#include <Protocol/SaPolicy.h>
Include dependency graph for DxePolicyBoardConfigLib.h:
This graph shows which files directly or indirectly include this file:

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Functions

EFI_STATUS | UpdateDxeAmtPolicyBoardConfig (IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration. More...
EFI_STATUS | UpdateDxeMePolicyBoardConfig (IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration. More...
EFI_STATUS | UpdateDxeSaPolicyBoardConfig (IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration. More...

Detailed Description

Header file for the DxePolicyBoardConfig Library.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePolicyBoardConfigLib.h.

Function Documentation

◆ UpdateDxeAmtPolicyBoardConfig()

EFI_STATUS UpdateDxeAmtPolicyBoardConfig ( IN OUT AMT_POLICY_PROTOCOL * DxeAmtPolicy )

This function performs DXE AMT Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE AMT Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.

◆ UpdateDxeMePolicyBoardConfig()

EFI_STATUS UpdateDxeMePolicyBoardConfig ( IN OUT ME_POLICY_PROTOCOL * DxeMePolicy )

This function performs DXE ME Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE ME Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.

◆ UpdateDxeSaPolicyBoardConfig()

EFI_STATUS UpdateDxeSaPolicyBoardConfig ( IN OUT SA_POLICY_PROTOCOL * DxeSaPolicy )

This function performs DXE SA Policy update by board configuration.

Parameters
[in,out] DxeAmtPolicy DXE SA Policy
Return values
EFI_SUCCESS | The SI Policy is successfully updated.
Others | The SI Policy is not successfully updated.


AlderLake Platform Sample Code: DxePolicyBoardConfigLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxePolicyBoardConfigLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the DxePolicyBoardConfig Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_
35 #define _DXE_POLICY_BOARD_CONFIG_LIB_H_
36
37 #include <Protocol/AmtPolicy.h>
38 #include <Protocol/MePolicy.h>
39 #include <Protocol/SaPolicy.h>
40
41 /**
42 This function performs DXE AMT Policy update by board configuration.
43
44 @param[in, out] DxeAmtPolicy DXE AMT Policy
45
46 @retval EFI_SUCCESS The SI Policy is successfully updated.
47 @retval Others The SI Policy is not successfully updated.
48 **/
49 EFI_STATUS
50 EFIAPI
51 UpdateDxeAmtPolicyBoardConfig (
52 IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy
53 );
54
55 /**
56 This function performs DXE ME Policy update by board configuration.
57
58 @param[in, out] DxeAmtPolicy DXE ME Policy
59
60 @retval EFI_SUCCESS The SI Policy is successfully updated.
61 @retval Others The SI Policy is not successfully updated.
62 **/
63 EFI_STATUS
64 EFIAPI
65 UpdateDxeMePolicyBoardConfig (
66 IN OUT ME_POLICY_PROTOCOL *DxeMePolicy
67 );
68
69 /**
70 This function performs DXE SA Policy update by board configuration.
71
72 @param[in, out] DxeAmtPolicy DXE SA Policy
73
74 @retval EFI_SUCCESS The SI Policy is successfully updated.
75 @retval Others The SI Policy is not successfully updated.
76 **/
77 EFI_STATUS
78 EFIAPI
79 UpdateDxeSaPolicyBoardConfig (
80 IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
81 );
82
83 #endif
UpdateDxeAmtPolicyBoardConfig
EFI_STATUS UpdateDxeAmtPolicyBoardConfig(IN OUT AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function performs DXE AMT Policy update by board configuration.
UpdateDxeMePolicyBoardConfig
EFI_STATUS UpdateDxeMePolicyBoardConfig(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration.
UpdateDxeSaPolicyBoardConfig
EFI_STATUS UpdateDxeSaPolicyBoardConfig(IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxePolicyUpdateProtocol.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
DxePolicyUpdateProtocol.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxePolicyUpdateProtocol.h.


AlderLake Platform Sample Code: DxePolicyUpdateProtocol.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
DxePolicyUpdateProtocol.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_POLICY_UPDATE_PROTOCOL_H_
35 #define _DXE_POLICY_UPDATE_PROTOCOL_H_
36
37 //
38 // DXE Policy Update Protocol GUID
39 // {D5E1268B-F62B-4b12-BB27-CBF07AE7B8B9}
40 //
41 #define DXE_POLICY_UPDATE_PROTOCOL_GUID \
42 { \
43 0xd5e1268b, 0xf62b, 0x4b12, 0xbb, 0x27, 0xcb, 0xf0, 0x7a, 0xe7, 0xb8, 0xb9 \
44 }
45
46 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeSaPolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeSaPolicyUpdateLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS UpdateDxeSaPolicy (IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeSaPolicyUpdateLib.h.

Function Documentation

◆ UpdateDxeSaPolicy()

EFI_STATUS UpdateDxeSaPolicy ( IN OUT SA_POLICY_PROTOCOL * SaPolicy )

Get data for platform policy from setup options.

Parameters
[in] SaPolicy The pointer to get SA Policy protocol instance
Return values
EFI_SUCCESS Operation success.


AlderLake Platform Sample Code: DxeSaPolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeSaPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_SA_POLICY_UPDATE_LIB_H_
35 #define _DXE_SA_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] SaPolicy The pointer to get SA Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxeSaPolicy (
48 IN OUT SA_POLICY_PROTOCOL *SaPolicy
49 )
50 ;
51
52 #endif
UpdateDxeSaPolicy
EFI_STATUS UpdateDxeSaPolicy(IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeSmmAcpiCustomLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeSmmAcpiCustomLib.h File Reference

This header file provides platform specific definitions used by other modules for platform specific initialization. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcLib.h>
#include <Protocol/PlatformNvsArea.h>
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Detailed Description

This header file provides platform specific definitions used by other modules for platform specific initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeSmmAcpiCustomLib.h.


AlderLake Platform Sample Code: DxeSmmAcpiCustomLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeSmmAcpiCustomLib.h
Go to the documentation of this file.
1 /** @file
2 This header file provides platform specific definitions used by other modules
3 for platform specific initialization.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2006 - 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36
37 #ifndef _DXE_SMM_ACPI_CUSTOM_LIB_H_
38 #define _DXE_SMM_ACPI_CUSTOM_LIB_H_
39 //
40 // Include files
41 //
42 #include <Base.h>
43 #include <Uefi.h>
44 #include <Library/EcLib.h>
45 #include <Protocol/PlatformNvsArea.h>
46
47 //
48 // Platform NVS area pointer
49 //
50 extern PLATFORM_NVS_AREA *mPlatformNvsAreaPtr;
51
52 //
53 // Function declarations
54 //
55 VOID
56 PlatformSpecificAcpiEnableHook (
57 VOID
58 );
59
60 VOID
61 PlatformSpecificAcpiDisableHook (
62 VOID
63 );
64
65 #endif
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
EcLib.h
EC library functions and definitions.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: DxeTbtPolicyUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
DxeTbtPolicyUpdateLib.h File Reference
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Functions

EFI_STATUS UpdateDxeTbtPolicy (IN OUT ITBT_POLICY_PROTOCOL *ITbtPolicy)
Get data for platform policy from setup options. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file DxeTbtPolicyUpdateLib.h.

Function Documentation

◆ UpdateDxeTbtPolicy()

EFI_STATUS UpdateDxeTbtPolicy ( IN OUT ITBT_POLICY_PROTOCOL * ITbtPolicy )

Get data for platform policy from setup options.

Parameters
[in] ITbtPolicy The pointer to get ITBT Policy protocol instance
Return values
EFI_SUCCESS Operation success.


AlderLake Platform Sample Code: DxeTbtPolicyUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
DxeTbtPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _DXE_TBT_POLICY_UPDATE_LIB_H_
35 #define _DXE_TBT_POLICY_UPDATE_LIB_H_
36
37 /**
38 Get data for platform policy from setup options.
39
40 @param[in] ITbtPolicy The pointer to get ITBT Policy protocol instance
41
42 @retval EFI_SUCCESS Operation success.
43
44 **/
45 EFI_STATUS
46 EFIAPI
47 UpdateDxeTbtPolicy (
48 IN OUT ITBT_POLICY_PROTOCOL *ITbtPolicy
49 )
50 ;
51
52 #endif
UpdateDxeTbtPolicy
EFI_STATUS UpdateDxeTbtPolicy(IN OUT ITBT_POLICY_PROTOCOL *ITbtPolicy)
Get data for platform policy from setup options.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcAccess.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
EcAccess.h File Reference
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Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EcAccess.h.


AlderLake Platform Sample Code: EcAccess.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
EcAccess.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2020 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef __EFI_EC_ACCESS_H___
34 #define __EFI_EC_ACCESS_H___
35
36 //typedef struct gEcAccessProtocolGuid _gEcAccessProtocolGuid;
37 //
38 // EC Access specification constant and types
39 //
40
41
42 //
43 // EC Access specification Data Structures
44 //
45
46
47 typedef
48 EFI_STATUS
49 (EFIAPI *EC_QUERY_COMMAND) (
50 UINT8 *Qdata
51 );
52
53 typedef
54 EFI_STATUS
55 (EFIAPI *EC_WRITE_CMD) (
56 UINT8 cmd
57 );
58
59 typedef
60 EFI_STATUS
61 (EFIAPI *EC_WRITE_DATA) (
62 UINT8 data
63 );
64
65 typedef
66 EFI_STATUS
67 (EFIAPI *EC_READ_DATA) (
68 UINT8 *data
69 );
70
71 typedef
72 EFI_STATUS
73 (EFIAPI *EC_READ_MEM) (
74 UINT8 Index,
75 UINT8 *Data
76 );
77
78 typedef
79 EFI_STATUS
80 (EFIAPI *EC_WRITE_MEM) (
81 UINT8 Index,
82 UINT8 Data
83 );
84
85 typedef
86 EFI_STATUS
87 (EFIAPI *EC_ACPI_ENABLE) (
88 VOID
89 );
90
91
92 typedef
93 EFI_STATUS
94 (EFIAPI *EC_ACPI_DISABLE) (
95 VOID
96 );
97
98 typedef
99 EFI_STATUS
100 (EFIAPI *EC_SMI_NOTIFY_ENABLE) (
101 VOID
102 );
103
104 typedef
105 EFI_STATUS
106 (EFIAPI *EC_SMI_NOTIFY_DISABLE) (
107 VOID
108 );
109
110
111 typedef
112 EFI_STATUS (EFIAPI *EC_SHUTDOWN_SYSTEM)(
113 VOID
114 );
115
116 typedef
117 EFI_STATUS (EFIAPI *EC_GET_MOTHER_BOARD_ID)(
118 UINT8 *FabID
119 );
120
121 typedef
122 EFI_STATUS (EFIAPI *EC_GET_EC_VERSION)(
123 UINT8 *Revision
124 );
125
126 typedef
127 EFI_STATUS (EFIAPI *EC_ENABLE_LAN)(
128 VOID
129 );
130
131 typedef
132 EFI_STATUS (EFIAPI *EC_DISABLE_LAN)(
133 VOID
134 );
135
136 typedef
137 EFI_STATUS (EFIAPI *EC_DEEPSX_CONFIG)(
138 UINT8 ECData
139 );
140
141 typedef
142 EFI_STATUS (EFIAPI *EC_TURBOCTRL_TESTMODE)(
143 UINT8 Enable,
144 UINT8 ACBrickCap,
145 UINT8 ECPollPeriod,
146 UINT8 ECGuardBandValue,
147 UINT8 ECAlgorithmSel
148 );
149
150 typedef
151 EFI_STATUS (EFIAPI *EC_GET_SWITCH_STATUS)(
152 UINT8 *Data
153 );
154
155 typedef
156 EFI_STATUS (EFIAPI *EC_FAIL_SAFE_FAN_CTRL)(
157 UINT8 CpuTemp,
158 UINT8 CpuFanSpeed
159 );
160 typedef struct _EFI_EC_ACCESS_PROTOCOL {
161 EFI_HANDLE Handle;
162 EC_QUERY_COMMAND QuerryCmd;
163 EC_WRITE_CMD WriteCmd;
164 EC_WRITE_DATA WriteData;
165 EC_READ_DATA ReadData;
166 EC_READ_MEM ReadMem;
167 EC_WRITE_MEM WriteMem;
168 EC_ACPI_ENABLE AcpiEnable;
169 EC_ACPI_DISABLE AcpiDisable;
170 EC_SMI_NOTIFY_ENABLE SMINotifyEnable;
171 EC_SMI_NOTIFY_DISABLE SMINotifyDisable;
172 EC_SHUTDOWN_SYSTEM ShutDownSystem;
173 EC_GET_MOTHER_BOARD_ID GetMotherBoardID;
174 EC_GET_EC_VERSION GetECVersion;
175 EC_ENABLE_LAN EnableLan;
176 EC_DISABLE_LAN DisableLan;
177 EC_DEEPSX_CONFIG DeepSxConfig;
178 EC_TURBOCTRL_TESTMODE TurboCtrlMode;
179 EC_GET_SWITCH_STATUS GetSwitchStatus;
180 EC_FAIL_SAFE_FAN_CTRL FailSafeFanCtrl;
181 } EFI_EC_ACCESS_PROTOCOL;
182
183 #endif
184
185
186
187
188
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcCommands.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcCommands.h File Reference
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Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcCommands.h.


AlderLake Platform Sample Code: EcCommands.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcCommands.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef EC_COMMANDS_H_
36 #define EC_COMMANDS_H_
37
38 //
39 // Timeout if EC command/data fails
40 //
41 #define EC_TIME_OUT 0x20000
42
43 //
44 // The EC implements an embedded controller interface at ports 0x60/0x64 and a ACPI compliant
45 // system management controller at ports 0x62/0x66. Port 0x66 is the command and status port,
46 // port 0x62 is the data port.
47 //
48 #define EC_D_PORT 0x62
49 #define EC_C_PORT 0x66
50
51 //
52 // Status Port 0x62
53 //
54 #define EC_S_OVR_TMP 0x80 // Current CPU temperature exceeds the threshold
55 #define EC_S_SMI_EVT 0x40 // SMI event is pending
56 #define EC_S_SCI_EVT 0x20 // SCI event is pending
57 #define EC_S_BURST 0x10 // EC is in burst mode or normal mode
58 #define EC_S_CMD 0x08 // Byte in data register is command/data
59 #define EC_S_IGN 0x04 // Ignored
60 #define EC_S_IBF 0x02 // Input buffer is full/empty
61 #define EC_S_OBF 0x01 // Output buffer is full/empty
62
63 //
64 // EC commands that are issued to the EC through the command port (0x66).
65 // New commands and command parameters should only be written by the host when IBF=0.
66 // Data read from the EC data port is valid only when OBF=1.
67 //
68 #define EC_C_SMI_NOTIFY_ENABLE 0x04 // Enable SMI notifications to the host
69 #define EC_C_SMI_NOTIFY_DISABLE 0x05 // SMI notifications are disabled and pending notifications cleared
70 #define EC_C_QUERY_SYS_STATUS 0x06 // Returns 1 byte of information about the system status
71 #define EC_C_QUERY_BOARD_ID_BIT 0x0A // Board Id 8 or 16 bit
72 #define EC_C_QUERY_BOARD_BUTTON_BITS 0x0A // Get board button status
73 #define EC_C_SMC_GET_MODE 0x09 // Command to detect EC
74 #define EC_C_RESET 0x0B // EC reset
75 #define EC_C_FAB_ID 0x0D // Get the board fab ID in the lower 3 bits
76 #define EC_C_PLN_ENABLE 0x0F // Enable or disable PLN
77 #define EC_C_SET_CHARGING_METHOD 0x13 // Command to specify charging method. (Normal charging or Fast charging (DFCT))
78 #define EC_C_GET_PMIC_VENDOR_ID 0x1B // Command to detect the Vendor ID of the PMIC
79 #define EC_C_SLP_S0_VOLTAGE 0x1C // Command to set/reset the bits of register V085ACNT[7:6]
80 #define EC_C_USBC_RETIMER 0x1F // notify EC of Retimer compliance mode enablement status
81 #define EC_C_SYSTEM_POWER_OFF 0x22 // Turn off the system power
82 #define EC_C_ENABLE_POWER_BTN 0x23 // Disable power button functionality
83 #define EC_C_DISABLE_POWER_BTN 0x24 // Enable power button functionality
84 #define EC_C_LOW_POWER_ENTRY 0x2C // Enter Low Power Mode
85 #define EC_C_LOW_POWER_EXIT 0x2D // Exit Low Power Mode
86 #define EC_C_UPDATE_EC 0x2E // Update Device Power
87 #define EC_C_PMIC_VOLTAGE 0x2F // Command to set the VCC and VDDQ Voltage Levels
88 #define EC_C_FAIL_SAFE_FAN_CTRL 0x39 // Set Fail safe FAN speed for given Cpu temp
89 #define EC_C_SET_PECI_MODE 0x3C // Switch PECI mode between Legacy and eSPI mode
90 #define EC_C_LAN_ON 0x46 // Turn on the power to LAN through EC
91 #define EC_C_LAN_OFF 0x47 // Turn off the power to LAN through EC
92 #define EC_C_DIS_PCH_DTS_READ 0x4E // Disable PCH DTS reading
93 #define EC_C_SET_CTEMP 0x58 // The next byte written to the data port will be the shutdown temperature
94 #define EC_C_EN_DTEMP 0x5E // Commands EC to begin reading Thermal Diode and comparing to Critical Temperature
95 #define EC_C_DIS_DTEMP 0x5F // Commands EC to stop reading Thermal Diode
96 #define EC_C_PCH_SMBUS_EN 0x60 // EC PCH SMBus thermal monitoring Enable cmd
97 #define EC_C_PCH_SMBUS_DIS 0x61 // EC PCH SMBus thermal monitoring Disable cmd
98 #define EC_C_PCH_SMBUS_WRITE_EN 0x68 // EC PCH SMBus Write Enable cmd
99 #define EC_C_PCH_SMBUS_WRITE_DIS 0x69 // EC PCH SMBus Write Disable cmd
100 #define EC_C_TS_ON_DIMM_EN 0x6B // TS-on-DIMM thermal monitoring enable command
101 #define EC_C_TS_ON_DIMM_DIS 0x6C // TS-on-DIMM thermal monitoring disable command
102 #define EC_C_PCH_SMBUS_MSG_LENGTH 0x6D // PCH SMBus block read buffer length
103 #define EC_C_PCH_SMBUS_PEC_EN 0x6E // PCH SMBus Packet Error Checking (PEC) Enable command.
104 #define EC_C_PCH_SMBUS_PEC_DIS 0x76 // PCH SMBus Packet Error Checking (PEC) Disable command.
105 #define EC_C_SMBUS_HIGH_SPEED 0x75 // EC SMBus high speed mode command
106 #define EC_C_SMI_QUERY 0x70 // The host reads the data port to retrieve the notifications
107 #define EC_C_SMI_TIMER 0x71 // Commands the EC to generate a periodic SMI to the host
108 #define EC_C_SMI_HOTKEY 0x72 // Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
109 #define EC_C_READ_MEM 0x80 // Read the EC memory
110 #define EC_C_WRITE_MEM 0x81 // Write the EC memory
111 #define EC_C_DOCK_STATUS 0x8A // Get the dock status
112 #define EC_C_EC_REVISION 0x90 // Get the revision for the EC
113 #define EC_C_UPDATE_PWM 0x1A // Update the FAN Speed
114 #define EC_C_SET_PD_FW_UPDATE_MODE 0x1D // Commands EC to enter or exit Retimer FW Update Mode for ALL PD controller
115 #define EC_C_GET_PD_FW_UPDATE_MODE 0x1E // Commands EC to get Status of ALL PD controller Retimer FW Update Mode
116 #define EC_C_ACPI_ENABLE 0xAA // Enable ACPI mode
117 #define EC_C_ACPI_DISABLE 0xAB // Disable ACPI mode
118 #define EC_C_SMI_INJECT 0xBA // The next byte written to the data port will generate an immediate SMI
119 #define EC_C_SMI_DISABLE 0xBC // SMI generation by the EC is disabled
120 #define EC_C_SMI_ENABLE 0xBD // SMI generation by the EC is enabled
121 #define EC_C_USBC_SX_ENTRY_WAIT 0xE2 // Send this command from SMM and wait for response
122 #define EC_C_USBC_SX_EXIT_WAIT 0xE3 // Send this command during boot and wait for response
123 #define EC_C_WDT_WRITE 0xE4 // write command to EC WDT through 0x66 EC_C_PORT
124 #define EC_C_WDT_READ 0xE5 // read command to EC WDT through 0x66 EC_C_PORT
125 #define EC_C_USBC_IOM_READY_NOTIFY 0xE4 // Send this command during boot/resume when IOM is ready
126 #define EC_C_USBC_GET_USB_CONN_STATUS 0xE5 // Send this command during boot before USB enumeration and wait for response
127 #define EC_C_SET_G3TOS5 0xF3 // Set KSC Misc Flags BIT0(G3ToS5)
128 #define EC_C_USBC_PD_STATUS 0xFF // Get PD status from EC RAM
129
130 //
131 // @todo Those definitions need to be reviewed and cleaned up.
132 //
133 #define EC_B_BOARD_ID 0x0F // Board ID = [3:0]
134 #define EC_B_BOARD_ID_BIT_16 0x80 // Bit7 = 1 means 16 bit implementation
135 #define EC_B_SYS_STATUS_AC 0x10 // AC power status (Bit 4 = 1, AC powered)
136 #define EC_B_SYS_STATUS_THERMAL 0x0F // CPU thermal state (0 ~ 9)
137 #define EC_B_SYS_STATUS_FAN 0x40 // Fan status (Bit 6 = 1, Fan on)
138 #define EC_B_LID_STATUS_OPEN 0x40 // Lid status (Bit 6 = 1, Lid open)
139 #define EC_B_SYS_STATUS_DOCK 0x20 // Dock status (Bit 5 = 1, Docked)
140 #define EC_B_DOCK_STATUS_ATTACH 0x01 // Dock status (Bit 0 = 1, Attach)
141
142 #define EC_D_LID_STATE 0x03 // Get Lid State (EC RAM offset 0x03 bit6)
143 #define EC_D_FORCE_RESET 0x78 // Enable/Disable ForceResetAfterAcRemoval (EC RAM offset 0x78 bit2)
144 #define EC_D_TEN_SEC_MODE 0x78 // Enable/Disable 10sec Power button Override (EC RAM offset 0x78 bit1)
145 #define EC_D_SATA2_POWER 0xC8 // Enable/Disable SATA port2 power (EC RAM offset 0xC8 bit0)
146 #define EC_D_NORMAL_CHARGING 0x01 // Select normal charging method
147 #define EC_D_FAST_CHARGING 0x02 // Select fast charging (DFCT) method
148
149 //
150 // EC commands that are only valid if the EC has ACPI mode enabled.
151 // Note that capacity and voltage are 16 bit values, thus you need to read them from
152 // ACPI space with two reads (little Endian).
153 //
154 #define EC_VIRTUAL_BAT_STATUS 48 // Status of the virtual battery (present)
155 #define EC_VIRTUAL_BAT_PRESENT_MASK 0x10 // Bit 4 is the indicator
156
157 #define EC_REAL_BAT1_STATUS 50 // Status of the first real battery (present, charging)
158 #define EC_REAL_BAT1_REMAINING_PERCENT 52 // Remaining capacity in percentage
159 #define EC_REAL_BAT1_REMAINING_CAPACITY 89 // Remaining capacity in mWh
160 #define EC_REAL_BAT1_RESOLUTION_VOLTAGE 93 // Full resolution voltage in mV
161
162 #define EC_REAL_BAT2_STATUS 54 // Status of the second real battery (present, charging)
163 #define EC_REAL_BAT2_REMAINING_PERCENT 56 // Remaining capacity in percentage
164 #define EC_REAL_BAT2_REMAINING_CAPACITY 99 // Remaining capacity in mWh
165 #define EC_REAL_BAT2_RESOLUTION_VOLTAGE 103 // Full resolution voltage in mV
166
167 #define EC_REAL_BAT_PRESENT_MASK 0x8 // Bit 3 is the indicator
168 #define EC_REAL_BAT_CHARGING_MASK 0x1 // Bit 1 is the indicator
169
170 //
171 // SMI notification code table, read through command EC_C_SMI_QUERY
172 //
173 #define EC_N_SMI_NULL 0x00 // Null marks the end of the SMI notification queue
174 #define EC_N_SMI_HOTKEY 0x20 // Hotkey pressed SMI
175 #define EC_N_SMI_ACINSERTION 0x30 // AC insertion SMI
176 #define EC_N_SMI_ACREMOVAL 0x31 // AC removal SMI
177 #define EC_N_SMI_PWRSW 0x32 // Power switch press SMI
178 #define EC_N_SMI_LID 0x33 // Lid switch change SMI
179 #define EC_N_SMI_VB 0x34 // Virtual battery switch change SMI
180 #define EC_N_SMI_THERM_0 0x60 // Thermal state 0 SMI
181 #define EC_N_SMI_THERM_1 0x61 // Thermal state 1 SMI
182 #define EC_N_SMI_THERM_2 0x62 // Thermal state 2 SMI
183 #define EC_N_SMI_THERM_3 0x63 // Thermal state 3 SMI
184 #define EC_N_SMI_THERM_4 0x64 // Thermal state 4 SMI
185 #define EC_N_SMI_THERM_5 0x65 // Thermal state 5 SMI
186 #define EC_N_SMI_THERM_6 0x66 // Thermal state 6 SMI
187 #define EC_N_SMI_THERM_7 0x67 // Thermal state 7 SMI
188 #define EC_N_SMI_THERM_8 0x68 // Thermal state 8 SMI
189 #define EC_N_SMI_DOCKED 0x70 // Dock complete SMI
190 #define EC_N_SMI_UNDOCKED 0x71 // Undock complete SMI
191 #define EC_N_SMI_UNDOCKREQUEST 0x72 // Undocking request SMI
192 #define EC_N_SMI_TIMER 0x80 // Timer wakeup SMI
193
194 //
195 // Hotkey scan code (CTRL + ALT + SHIFT + key)
196 //
197 #define EC_HK_ESC 0x01 // ESC
198 #define EC_HK_1 0x02 // 1 !
199 #define EC_HK_2 0x03 // 2 @
200 #define EC_HK_3 0x04 // 3 #
201 #define EC_HK_4 0x05 // 4 $
202 #define EC_HK_5 0x06 // 5 %
203 #define EC_HK_6 0x07 // 6 ^
204 #define EC_HK_7 0x08 // 7 &
205 #define EC_HK_8 0x09 // 8 *
206 #define EC_HK_9 0x0A // 9 (
207 #define EC_HK_0 0x0B // 0 )
208 #define EC_HK_MINUS 0x0C // - _
209 #define EC_HK_ADD 0x0D // = +
210 #define EC_HK_F1 0x3B // F1
211 #define EC_HK_F2 0x3C // F2
212 #define EC_HK_F3 0x3D // F3
213 #define EC_HK_F4 0x3E // F4
214 #define EC_HK_F5 0x3F // F5
215 #define EC_HK_F6 0x40 // F6
216 #define EC_HK_F7 0x41 // F7
217 #define EC_HK_F8 0x42 // F8
218 #define EC_HK_F9 0x43 // F9
219 #define EC_HK_F10 0x44 // F10
220 #define EC_HK_F11 0x57 // F11
221 #define EC_HK_F12 0x58 // F12
222
223 //
224 // EC WDT timeout definition
225 //
226 #define EC_WDT_FIRST_BOOT 0xFF // 255 second for the first release boot
227 #define EC_WDT_TIMEOUT 0x80 // 128 second for normal boot
228 #define EC_WDT_ENABLE 0x02 // 10=ARM WDT
229 #define EC_WDT_DISABLE 0x01 // 01=Disarm WDT
230
231 //
232 // For notify EC to PD firmware to Enable/Disable USB or PCIe.
233 //
234 #define USBC_MISC_VPRO_EN_DIS 0x02
235 #define USBC_MISC_PCIE_EN_DIS 0x03
236 #define SMCHOST_USBC_MISC_CMD_HANDLER 0xE3
237
238 //
239 // BoardId format definition (Data came from EC_C_FAB_ID command)
240 //
241 // @todo Instead of Build Flag, we could have maintained a generic structure called RvpFields and create TglRvpFields structure by including RvpFields
242 typedef union {
243 UINT16 Raw;
244 struct {
245 UINT16 BoardId :6; // [5:0] - BOARD_IDx
246 UINT16 BomId :3; // [8:6] - BOM_IDx
247 UINT16 FabId :2; // [10:9] - REV_FAB_IDx
248 UINT16 SpdPresent :1; // [11] - SPD_PRSNT
249 UINT16 DdiAConfig :1; // [12] - DDI_A_CONFIG 0: EDP, 1: MIPI
250 UINT16 DdiBConfig :1; // [13] - DDI_B_CONFIG 0: EDP, 1: MIPI
251 UINT16 DdiBDisplay :1; // [14] - DDI_B_DISPLAY 0: INTERNAL, 1: EXTERNAL
252 UINT16 Reserved :1; // [15] - RESERVED
253 } TglRvpFields;
254 } BOARD_ID_INFO;
255
256 typedef union {
257 UINT16 EcWdtWrite;
258 struct {
259 UINT16 Upgrade :1; // [0] - 1=Initiate upgrade/0=Default
260 UINT16 WdtStatus :2; // [2:1] - 11=Reserved/10=ARM WDT/01=Disarm WDT/00=Disarm WDT,Assert Reset without TopSwap
261 UINT16 WdtMode :2; // [4:3] - 00=Successful completion/NOP/01=Signature verification failure/10=Entry/Exit into/from debug mode/11=Entry/Exit into/from setup mode
262 UINT16 BiosStatus :2; // [6:5] - Current BIOS state/00=default state after reset/01=BIOS message received from PEI/10=BIOS message received from DXE
263 UINT16 Reserved :1; // [7] - reserved
264 UINT16 WdtTimer :8; // [15:8] - 2 seconds set the value to 02h
265 } Bits;
266 } EC_WDT_W_PARAMETER;
267 typedef union {
268 UINT8 EcWdtRead;
269 struct {
270 UINT8 Recovery :1; // [0] - 1 = Recovery Initiated/0 = Default
271 UINT8 Upgrade :1; // [1] - 1 = Initiate upgrade/0 = Default
272 UINT8 WdtStatus :1; // [2] - 0 = wdt disarmed, 1 = wdt armed
273 UINT8 WdtMode :2; // [4:3] - 00=Successful completion/NOP/01=Signature verification failure/10=Entry/Exit into/from debug mode/11=Entry/Exit into/from setup mode
274 UINT8 BiosStatus :2; // [6:5] - Current BIOS state/00=default state after reset/01=BIOS message received from PEI/10=BIOS message received from DXE
275 UINT8 Reserved :1; // [7] - reserved
276 } Bits;
277 } EC_WDT_R_PARAMETER;
278 #endif // EC_COMMANDS_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcHwLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcHwLib.h File Reference

EC hardware library functions and definitions. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcCommands.h>
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This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

EC hardware library functions and definitions.

This library provides basic Embedded Controller Hardware interface. It is keeped simple enough and used by other BaseEc libraries to abstacrt the usage

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcHwLib.h.


AlderLake Platform Sample Code: EcHwLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcHwLib.h
Go to the documentation of this file.
1 /** @file
2 EC hardware library functions and definitions.
3
4 This library provides basic Embedded Controller Hardware interface.
5 It is keeped simple enough and used by other BaseEc libraries to abstacrt the usage
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2014 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains 'Framework Code' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may not be
33 modified, except as allowed by additional terms of your license agreement.
34
35 @par Specification Reference:
36 **/
37
38
39 #ifndef _BASE_EC_HW_LIB_H_
40 #define _BASE_EC_HW_LIB_H_
41
42 #include <Base.h>
43 #include <Uefi.h>
44 #include <Library/EcCommands.h>
45
46 typedef enum {
47 LpcInterface = 0,
48 SpiInterface,
49 EspiInterface,
50 I2cInterface,
51 EcInterfaceMax
52 } EC_INTERFACE_TYPE;
53
54 typedef enum {
55 EcId0 = 0,
56 EcIdMax
57 } EC_ID;
58
59 #endif
EcCommands.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
EcLib.h File Reference

EC library functions and definitions. More...

#include <Base.h>
#include <Uefi.h>
#include "EcCommands.h"
#include <Library/EcHwLib.h>
Include dependency graph for EcLib.h:
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Go to the source code of this file.

Functions

BOOLEAN | DetectEc (OUT UINT8 *EcMajorRevision, OUT UINT8 *EcMinorRevision)
Detect EC. More...
EFI_STATUS | LpcEcResetEcInNormalMode (VOID)
Initiate EC reset sequence. More...
EFI_STATUS | SendEcCommand (IN UINT8 Command)
Send a command to the Keyboard System Controller. More...
EFI_STATUS | SendEcData (IN UINT8 Data)
Sends data to Keyboard System Controller. More...
EFI_STATUS | ReceiveEcData (OUT UINT8 *Data)
Receives data from Keyboard System Controller. More...
EFI_STATUS | ReceiveEcStatus (OUT UINT8 *EcStatus)
Receives status from Keyboard System Controller. More...
EFI_STATUS | EcInterface (IN EC_ID EcId, IN UINT8 Command, IN OUT UINT8 *DataSize, IN OUT UINT8 *DataBuffer)
Sends data to the Embedded Controler. More...
EFI_STATUS | GetPDInformation (IN UINT8 PDIndex, IN OUT UINT8 *Data)
Get PD Information. More...

Detailed Description

EC library functions and definitions.

This library provides basic EC interface.

There may be different libraries for different environments (PEI, BS, RT, SMM). Make sure you meet the requirements for the library (protocol dependencies, use restrictions, etc).

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcLib.h.

Function Documentation

◆ DetectEc()

BOOLEAN DetectEc | ( | OUT UINT8 * | EcMajorRevision,
 |  | OUT UINT8 * | EcMinorRevision
 | ) |  |

Detect EC.

Parameters
[out] | EcMajorRevision
[out] | EcMinorRevision
Return values
TRUE | EC is present on the system.
FALSE | EC is NOT present on the system.

◆ EcInterface()

EFI_STATUS EcInterface | ( | IN EC_ID | EcId,
 |  | IN UINT8 | Command,
 |  | IN OUT UINT8 * | DataSize,
 |  | IN OUT UINT8 * | DataBuffer
 | ) |  |

Sends data to the Embedded Controler.

Four use-cases: 1.Send command to EC (DataSize and DataBuffer can be NULL) 2.Send command to EC and send data to EC 3.Send command to EC and receive data from EC 4.Send command to EC, send data to EC and receive data from EC

Parameters
[in] | EcId | Embedded Controller identification - in case there is more then one.
[in] | Interface | Interface used to access the EC HW
[in] | Command | Command value to send to the EC
[in]

◆ GetPDInformation()

EFI_STATUS GetPDInformation | ( | IN UINT8 | PDIndex,
 |  | IN OUT UINT8 * | Data
 | ) |  |

Get PD Information.

Parameters
[in] PDIndex PD Index
[in]

◆ LpcEcResetEcInNormalMode()

EFI_STATUS LpcEcResetEcInNormalMode ( VOID )

Initiate EC reset sequence.

EC is in Normal Mode.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ ReceiveEcData()

EFI_STATUS ReceiveEcData ( OUT UINT8 * Data )

Receives data from Keyboard System Controller.

Parameters
[out] Data Data byte received
Return values
EFI_SUCCESS | Read success
EFI_TIMEOUT | Read timeout
Other | Read failed

◆ ReceiveEcStatus()

EFI_STATUS ReceiveEcStatus ( OUT UINT8 * EcStatus )

Receives status from Keyboard System Controller.

Parameters
[out] Status Status byte to receive
Return values
EFI_SUCCESS | Success
Other | Failed

◆ SendEcCommand()

EFI_STATUS SendEcCommand ( IN UINT8 Command )

Send a command to the Keyboard System Controller.

Parameters
[in] Command Command byte to send
Return values
EFI_SUCCESS | Command success
EFI_TIMEOUT | Command timeout
Other | Command failed

◆ SendEcData()

EFI_STATUS SendEcData ( IN UINT8 Data )

Sends data to Keyboard System Controller.

Parameters
[in] Data Data byte to send
Return values
EFI_SUCCESS | Success
EFI_TIMEOUT | Timeout
Other | Failed


AlderLake Platform Sample Code: EcLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcLib.h
Go to the documentation of this file.
1 /** @file
2 EC library functions and definitions.
3
4 This library provides basic EC interface.
5
6 There may be different libraries for different environments (PEI, BS, RT, SMM).
7 Make sure you meet the requirements for the library (protocol dependencies, use
8 restrictions, etc).
9
10 @copyright
11 INTEL CONFIDENTIAL
12 Copyright 1999 - 2019 Intel Corporation.
13
14 The source code contained or described herein and all documents related to the
15 source code ("Material") are owned by Intel Corporation or its suppliers or
16 licensors. Title to the Material remains with Intel Corporation or its suppliers
17 and licensors. The Material may contain trade secrets and proprietary and
18 confidential information of Intel Corporation and its suppliers and licensors,
19 and is protected by worldwide copyright and trade secret laws and treaty
20 provisions. No part of the Material may be used, copied, reproduced, modified,
21 published, uploaded, posted, transmitted, distributed, or disclosed in any way
22 without Intel's prior express written permission.
23
24 No license under any patent, copyright, trade secret or other intellectual
25 property right is granted to or conferred upon you by disclosure or delivery
26 of the Materials, either expressly, by implication, inducement, estoppel or
27 otherwise. Any license under such intellectual property rights must be
28 express and approved by Intel in writing.
29
30 Unless otherwise agreed by Intel in writing, you may not remove or alter
31 this notice or any other notice embedded in Materials by Intel or
32 Intel's suppliers or licensors in any way.
33
34 This file contains 'Framework Code' and is licensed as such under the terms
35 of your license agreement with Intel or your vendor. This file may not be
36 modified, except as allowed by additional terms of your license agreement.
37
38 @par Specification Reference:
39 **/
40
41
42 #ifndef _BASE_EC_LIB_H_
43 #define _BASE_EC_LIB_H_
44
45 //
46 // Include files
47 //
48 #include <Base.h>
49 #include <Uefi.h>
50 #include "EcCommands.h"
51 #include <Library/EcHwLib.h>
52
53 //
54 // PD Information data len
55 //
56 #define PD_INFORMATION_LEN 4
57 #define PD_VERSION_INFO_CMD 0xDF
58 //
59 // Function declarations
60 //
61 /**
62 Detect EC
63
64 @param[out] EcMajorRevision
65 @param[out] EcMinorRevision
66
67 @retval TRUE EC is present on the system.
68 @retval FALSE EC is NOT present on the system.
69 **/
70
71 BOOLEAN
72 DetectEc (
73 OUT UINT8 *EcMajorRevision,
74 OUT UINT8 *EcMinorRevision
75 );
76
77 /**
78
79 Initiate EC reset sequence. EC is in Normal Mode.
80
81 @retval EFI_SUCCESS Command success
82 @retval EFI_DEVICE_ERROR Command error
83 **/
84
85 EFI_STATUS
86 LpcEcResetEcInNormalMode (
87 VOID
88 );
89
90 /**
91 Send a command to the Keyboard System Controller.
92
93 @param[in] Command Command byte to send
94
95 @retval EFI_SUCCESS Command success
96 @retval EFI_TIMEOUT Command timeout
97 @retval Other Command failed
98 **/
99 EFI_STATUS
100 SendEcCommand (
101 IN UINT8 Command
102 );
103
104
105 /**
106 Sends data to Keyboard System Controller.
107
108 @param[in] Data Data byte to send
109
110 @retval EFI_SUCCESS Success
111 @retval EFI_TIMEOUT Timeout
112 @retval Other Failed
113 **/
114 EFI_STATUS
115 SendEcData (
116 IN UINT8 Data
117 );
118
119
120 /**
121 Receives data from Keyboard System Controller.
122
123 @param[out] Data Data byte received
124
125 @retval EFI_SUCCESS Read success
126 @retval EFI_TIMEOUT Read timeout
127 @retval Other Read failed
128 **/
129 EFI_STATUS
130 ReceiveEcData (
131 OUT UINT8 *Data
132 );
133
134
135 /**
136 Receives status from Keyboard System Controller.
137
138 @param[out] Status Status byte to receive
139
140 @retval EFI_SUCCESS Success
141 @retval Other Failed
142 **/
143 EFI_STATUS
144 ReceiveEcStatus (
145 OUT UINT8 *EcStatus
146 );
147
148 /**
149 Sends data to the Embedded Controler.
150 Four use-cases:
151 1.Send command to EC (DataSize and DataBuffer can be NULL)
152 2.Send command to EC and send data to EC
153 3.Send command to EC and receive data from EC
154 4.Send command to EC, send data to EC and receive data from EC
155
156 @param[in] EcId Embedded Controller identification - in case there is more then one.
157 @param[in] Interface Interface used to access the EC HW
158 @param[in] Command Command value to send to the EC
159 @param[in][out] DataSize Size of data to send to the EC.
160 If the command retuned data - size of buffer returned by the EC.
161 Be aware of the DataSize must euqal to size of DataBuffer and cannot smaller
162 than number of send data or number of receive data, whichever is the grater.
163 @param[in][out] DataBuffer Pointer to the data buffer including data to be sent to the EC.
164 If the command returned data - pointer to the buffer including the data.
165 The buffer size should be the max of receive and transmit data.
166
167 @retval EFI_SUCCESS Success
168 @retval Other Failed - EFI_TIMEOUT, EFI_INVALID_PARAMETER, EFI_UNSUPPORTED,
169 EFI_BUFFER_TOO_SMALL, etc.
170 **/
171 EFI_STATUS
172 EcInterface (
173 IN EC_ID EcId,
174 IN UINT8 Command,
175 IN OUT UINT8 *DataSize,
176 IN OUT UINT8 *DataBuffer
177 );
178
179 /**
180 Get PD Information
181
182 @param[in] PDIndex PD Index
183 @param[in][out] *Data PD information
184
185 @retval EFI_SUCCESS Success Get PD information success
186 @retval Other Get PD information fail
187 **/
188 EFI_STATUS
189 GetPDInformation (
190 IN UINT8 PDIndex,
191 IN OUT UINT8 *Data
192 );
193
194 #endif
SendEcData
EFI_STATUS SendEcData(IN UINT8 Data)
Sends data to Keyboard System Controller.
ReceiveEcData
EFI_STATUS ReceiveEcData(OUT UINT8 *Data)
Receives data from Keyboard System Controller.
GetPDInformation
EFI_STATUS GetPDInformation(IN UINT8 PDIndex, IN OUT UINT8 *Data)
Get PD Information.
EcCommands.h
ReceiveEcStatus
EFI_STATUS ReceiveEcStatus(OUT UINT8 *EcStatus)
Receives status from Keyboard System Controller.
EcInterface
EFI_STATUS EcInterface(IN EC_ID EcId, IN UINT8 Command, IN OUT UINT8 *DataSize, IN OUT UINT8 *DataBuffer)
Sends data to the Embedded Controler.
LpcEcResetEcInNormalMode
EFI_STATUS LpcEcResetEcInNormalMode(VOID)
Initiate EC reset sequence.
SendEcCommand
EFI_STATUS SendEcCommand(IN UINT8 Command)
Send a command to the Keyboard System Controller.
EcHwLib.h
EC hardware library functions and definitions.
DetectEc
BOOLEAN DetectEc(OUT UINT8 *EcMajorRevision, OUT UINT8 *EcMinorRevision)
Detect EC.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcMiscLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
EcMiscLib.h File Reference

EC miscellaneous library functions. More...

#include <Base.h>
#include <Uefi.h>
#include "EcCommands.h"
#include <Library/EcLib.h>
Include dependency graph for EcMiscLib.h:
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Functions

EFI_STATUS | EnableEcAcpiMode (IN BOOLEAN Enable)
Send enable ACPI mode command to EC. More...
EFI_STATUS | DisableEcSmiMode (VOID)
Send disable SMI mode command to EC. More...
EFI_STATUS | SetEcCriticalShutdownTemperature (IN UINT8 DataBuffer)
Set EC critical shutdown temperature. More...
BOOLEAN | PowerStateIsAc (VOID)
Get power state from EC. More...
EFI_STATUS | EcReset (VOID)
Do EC reset. More...
EFI_STATUS | EcResetEcInNormalMode (VOID)
Initiate EC reset sequence. More...
EFI_STATUS | EnableLanPower (IN BOOLEAN Enable)
Enable LAN power. More...
EFI_STATUS | QuerySmiEvent (OUT UINT8 *DataBuffer)
Query SMI event. More...
EFI_STATUS | GetHotkeyScanCode (OUT UINT8 *DataBuffer)
Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key) More...
EFI_STATUS | GetBatteryNumber (OUT UINT8 *DataBuffer)
Get the number of battery. More...
EFI_STATUS | GetPcieDockStatus (OUT UINT8 *DataBuffer)
Get PCIe dock status. More...
VOID | ClearTenSecPwrButtonMode (VOID)
Clear ten second power button mode.
VOID | EnableSataPort2Power (VOID)
Enable SATA port2 power.
EFI_STATUS | SetSlpS0Voltage (IN UINT8 EcDataV085ACNT)
Set SLP_S0 Voltage. More...
EFI_STATUS | DetectPmicVendorID (OUT UINT8 *DataBuffer)
Detect Pmic Vendor ID. More...
EFI_STATUS | SetPmicVoltage (IN UINT8 EcDataVcc, IN UINT8 EcDataVddq)
Set Pmic Voltage. More...
EFI_STATUS | ReadEcRam (IN OUT UINT8 *DataBuffer)
Read data from EC RAM. More...
EFI_STATUS | WriteEcRam (IN OUT UINT8 *DataBuffer)
Write data to EC RAM. More...
EFI_STATUS | UpdateDevicePower (VOID)
Update Device Power. More...
EFI_STATUS | QuerySysStatus (OUT UINT8 *DataBuffer)
Query system status. More...
EFI_STATUS | GetBoardInfo (OUT UINT16 *BoardFabId)
Get board fab ID. More...
EFI_STATUS | ExitLowPowerMode (VOID)
Send Exit Low Power Mode command to EC. More...
EFI_STATUS | SystemPowerOff (VOID)
System power off. More...
EFI_STATUS | DetectEcSupport (OUT UINT8 *DataBuffer)
Detect EC support. More...
EFI_STATUS | DetectEcRevision (OUT UINT8 *DataBuffer)
Detect EC revision. More...
EFI_STATUS | DisablePchDtsReading (IN UINT8 Disable)
Disable PCH DTS reading on SMLink 1. More...
EFI_STATUS | WakeUpEc (VOID)
Wake up EC. More...
EFI_STATUS | UpdatePwm (VOID)
Send Update PWM command to EC. More...
EFI_STATUS | GetFanSpeed (IN UINT8 Pwmvalue, OUT UINT16 *Speed)
Updates the PWM to the given value and returns the Fan speed. More...
EFI_STATUS | DfctFastChargingMode (IN BOOLEAN Enable)
Select charging method. More...
VOID | EcForceResetAfterAcRemoval (IN UINT8 ForceResetAfterAcRemovalVar)
EcForceResetAfterAcRemoval. More...
EFI_STATUS | SetFailSafeFanCtrl (UINT8 CpuTemp, UINT8 CpuFanSpeed)
Allow EC to control Fail Safe Fan control to avoid silicon burnout after hung state. More...
EFI_STATUS | BiosEcWdtReadCommand (IN OUT UINT8 *DataBuffer)
ec wdt read command More...
EFI_STATUS | BiosEcWdtWriteCommand (IN UINT8 *DataBuffer)
ec wdt write command More...
EFI_STATUS | ArmEcWdtWithTimeOut (IN UINT8 TimeOut)
Arm ec wdt with specific timeout. More...
EFI_STATUS | DisArmEcWdt (VOID)
Dis arm ec wdt. More...
VOID | NotifyEcToPdForPcieTunnel (IN UINT8 PcieTunneling)
Notify Ec To Pd firmware for enabling or disabling Pcie. More...
VOID | NotifyEcToPdForVpro (VOID)
Notify Ec To Pd firmware for enabling Vpro.

Detailed Description

EC miscellaneous library functions.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcMiscLib.h.

Function Documentation

◆ ArmEcWdtWithTimeOut()

EFI_STATUS ArmEcWdtWithTimeOut ( IN UINT8 TimeOut )

Arm ec wdt with specific timeout.

Parameters
[in] timeout value
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ BiosEcWdtReadCommand()

EFI_STATUS BiosEcWdtReadCommand ( IN OUT UINT8 * DataBuffer )

ec wdt read command

Parameters
[in] DataBuffer,1 byte will be read through 0x66
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ BiosEcWdtWriteCommand()

EFI_STATUS BiosEcWdtWriteCommand ( IN UINT8 * DataBuffer )

ec wdt write command

Parameters
[in] DataBuffer,2 bytes write for ECWDT through 0x66
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DetectEcRevision()

EFI_STATUS DetectEcRevision ( OUT UINT8 * DataBuffer )

Detect EC revision.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DetectEcSupport()

EFI_STATUS DetectEcSupport ( OUT UINT8 * DataBuffer )

Detect EC support.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DetectPmicVendorID()

EFI_STATUS DetectPmicVendorID ( OUT UINT8 * DataBuffer )

Detect Pmic Vendor ID.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DfctFastChargingMode()

EFI_STATUS DfctFastChargingMode ( IN BOOLEAN Enable )

Select charging method.

Parameters
[in] Enable TURE - Fast charging (DFCT) FALSE - Normal charging
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DisableEcSmiMode()

EFI_STATUS DisableEcSmiMode ( VOID )

Send disable SMI mode command to EC.

Parameters
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DisablePchDtsReading()

EFI_STATUS DisablePchDtsReading ( IN UINT8 Disable )

Disable PCH DTS reading on SMLink 1.

Parameters
[in] Disable 0: Enable PCH DTS reading 1: Disable PCH DTS reading
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ DisArmEcWdt()

EFI_STATUS DisArmEcWdt ( VOID )

Dis arm ec wdt.

Parameters
[in] timeout value
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ EcForceResetAfterAcRemoval()

VOID EcForceResetAfterAcRemoval ( IN UINT8 ForceResetAfterAcRemovalVar )

EcForceResetAfterAcRemoval.

Parameters
[in] ForceResetAfterAcRemovalVar 0 : Clear AC Removal reset bit in EC 1 : Set AC Removal reset bit in EC

◆ EcReset()

EFI_STATUS EcReset ( VOID )

Do EC reset.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ EcResetEcInNormalMode()

EFI_STATUS EcResetEcInNormalMode ( VOID )

Initiate EC reset sequence.

EC is in Normal Mode.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ EnableEcAcpiMode()

EFI_STATUS EnableEcAcpiMode ( IN BOOLEAN Enable )

Send enable ACPI mode command to EC.

Parameters
[in] Enable TURE - Enable EC ACPI mode FALSE - Disable EC ACPI mode
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ EnableLanPower()

EFI_STATUS EnableLanPower ( IN BOOLEAN Enable )

Enable LAN power.

Parameters
[in] Enable TURE - Enable LAN power FALSE - Disable LAN power
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ ExitLowPowerMode()

EFI_STATUS ExitLowPowerMode ( VOID )

Send Exit Low Power Mode command to EC.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ GetBatteryNumber()

EFI_STATUS GetBatteryNumber ( OUT UINT8 * DataBuffer )

Get the number of battery.

Parameters
[out] DataBuffer The number of battery
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ GetBoardInfo()

EFI_STATUS GetBoardInfo ( OUT UINT16 * BoardFabId )

Get board fab ID.

Parameters
[out] BoardFabId
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ GetFanSpeed()

EFI_STATUS GetFanSpeed | ( | IN UINT8 | Pwmvalue,
 |  | OUT UINT16 * | Speed
 | ) |  |

Updates the PWM to the given value and returns the Fan speed.

Parameters
Pwmvalue | Pwm ending value
Speed | Updates the Speed
Return values
EFI_SUCCESS | when successfully able to get the nominal data.
ERROR | Error if anything went wrong.

◆ GetHotkeyScanCode()

EFI_STATUS GetHotkeyScanCode ( OUT UINT8 * DataBuffer )

Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)

Parameters
[out] DataBuffer Scan code of hotkey
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ GetPcieDockStatus()

EFI_STATUS GetPcieDockStatus ( OUT UINT8 * DataBuffer )

Get PCIe dock status.

Parameters
[out] DataBuffer PCIe dock status
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ NotifyEcToPdForPcieTunnel()

VOID NotifyEcToPdForPcieTunnel ( IN UINT8 PcieTunneling )

Notify Ec To Pd firmware for enabling or disabling Pcie.

Parameters
[in] PcieTunneling a switch to enable or disable Pcie

◆ PowerStateIsAc()

BOOLEAN PowerStateIsAc ( VOID )

Get power state from EC.

If power state cannot be determined, battery powered is assumed.

Parameters
TRUE | AC powered
FALSE | Battery powered

◆ QuerySmiEvent()

EFI_STATUS QuerySmiEvent ( OUT UINT8 * DataBuffer )

Query SMI event.

Parameters
[out] DataBuffer SMI event
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ QuerySysStatus()

EFI_STATUS QuerySysStatus ( OUT UINT8 * DataBuffer )

Query system status.

Parameters
[out] DataBuffer
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ ReadEcRam()

EFI_STATUS ReadEcRam ( IN OUT UINT8 * DataBuffer )

Read data from EC RAM.

Parameters
[in]

◆ SetEcCriticalShutdownTemperature()

EFI_STATUS SetEcCriticalShutdownTemperature ( IN UINT8 DataBuffer )

Set EC critical shutdown temperature.

Parameters
[in] DataBuffer Shutdown temperature
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ SetFailSafeFanCtrl()

EFI_STATUS SetFailSafeFanCtrl | ( | UINT8 | CpuTemp,
 |  | UINT8 | CpuFanSpeed
 | ) |  |

Allow EC to control Fail Safe Fan control to avoid silicon burnout after hung state.

It is effective after CpuTemp is reached by running Fan at specified PWM

Parameters
[in] | CpuTemp
[in] | CpuFanSpeed
Return values
EFI_SUCCESS Function successfully executed.

◆ SetPmicVoltage()

EFI_STATUS SetPmicVoltage | ( | IN UINT8 | EcDataVcc,
 |  | IN UINT8 | EcDataVddq
 | ) |  |

Set Pmic Voltage.

Parameters
[in] | EcDataVcc
[in] | EcDataVddq
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ SetSlpS0Voltage()

EFI_STATUS SetSlpS0Voltage ( IN UINT8 EcDataV085ACNT )

Set SLP_S0 Voltage.

Parameters
[in] EcDataV085ACNT
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ SystemPowerOff()

EFI_STATUS SystemPowerOff ( VOID )

System power off.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ UpdateDevicePower()

EFI_STATUS UpdateDevicePower ( VOID )

Update Device Power.

Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ UpdatePwm()

EFI_STATUS UpdatePwm ( VOID )

Send Update PWM command to EC.

Parameters
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error

◆ WakeUpEc()

EFI_STATUS WakeUpEc ( VOID )

Wake up EC.

Return values
TRUE | EC wake up successfully.
FALSE | Fail to wake up EC.

◆ WriteEcRam()

EFI_STATUS WriteEcRam ( IN OUT UINT8 * DataBuffer )

Write data to EC RAM.

Parameters
[in]


AlderLake Platform Sample Code: EcMiscLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcMiscLib.h
Go to the documentation of this file.
1 /** @file
2 EC miscellaneous library functions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _BASE_EC_MISC_LIB_H_
36 #define _BASE_EC_MISC_LIB_H_
37
38 //
39 // Include files
40 //
41 #include <Base.h>
42 #include <Uefi.h>
43 #include "EcCommands.h"
44 #include <Library/EcLib.h>
45
46 /**
47 Send enable ACPI mode command to EC
48
49 @param[in] Enable TURE - Enable EC ACPI mode
50 FALSE - Disable EC ACPI mode
51 @retval EFI_SUCCESS Command success
52 @retval EFI_DEVICE_ERROR Command error
53 **/
54 EFI_STATUS
55 EnableEcAcpiMode (
56 IN BOOLEAN Enable
57 );
58
59
60 /**
61 Send disable SMI mode command to EC
62
63 @param EFI_SUCCESS Command success
64 @param EFI_DEVICE_ERROR Command error
65 **/
66 EFI_STATUS
67 DisableEcSmiMode (
68 VOID
69 );
70
71
72 /**
73 Set EC critical shutdown temperature
74
75 @param[in] DataBuffer Shutdown temperature
76 @retval EFI_SUCCESS Command success
77 @retval EFI_DEVICE_ERROR Command error
78 **/
79 EFI_STATUS
80 SetEcCriticalShutdownTemperature (
81 IN UINT8 DataBuffer
82 );
83
84
85 /**
86 Get power state from EC. If power state cannot be determined,
87 battery powered is assumed.
88
89 @param TRUE AC powered
90 @param FALSE Battery powered
91 **/
92 BOOLEAN
93 PowerStateIsAc (
94 VOID
95 );
96
97
98 /**
99 Do EC reset
100
101 @retval EFI_SUCCESS Command success
102 @retval EFI_DEVICE_ERROR Command error
103 **/
104 EFI_STATUS
105 EcReset (
106 VOID
107 );
108
109
110 /**
111 Initiate EC reset sequence. EC is in Normal Mode.
112
113 @retval EFI_SUCCESS Command success
114 @retval EFI_DEVICE_ERROR Command error
115 **/
116 EFI_STATUS
117 EcResetEcInNormalMode (
118 VOID
119 );
120
121 /**
122 Enable LAN power
123
124 @param[in] Enable TURE - Enable LAN power
125 FALSE - Disable LAN power
126
127 @retval EFI_SUCCESS Command success
128 @retval EFI_DEVICE_ERROR Command error
129 **/
130 EFI_STATUS
131 EnableLanPower (
132 IN BOOLEAN Enable
133 );
134
135
136 /**
137 Query SMI event
138
139 @param[out] DataBuffer SMI event
140
141 @retval EFI_SUCCESS Command success
142 @retval EFI_DEVICE_ERROR Command error
143 **/
144 EFI_STATUS
145 QuerySmiEvent (
146 OUT UINT8 *DataBuffer
147 );
148
149
150 /**
151 Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
152
153 @param[out] DataBuffer Scan code of hotkey
154
155 @retval EFI_SUCCESS Command success
156 @retval EFI_DEVICE_ERROR Command error
157 **/
158 EFI_STATUS
159 GetHotkeyScanCode (
160 OUT UINT8 *DataBuffer
161 );
162
163
164 /**
165 Get the number of battery
166
167 @param[out] DataBuffer The number of battery
168
169 @retval EFI_SUCCESS Command success
170 @retval EFI_DEVICE_ERROR Command error
171 **/
172 EFI_STATUS
173 GetBatteryNumber (
174 OUT UINT8 *DataBuffer
175 );
176
177
178 /**
179 Get PCIe dock status
180
181 @param[out] DataBuffer PCIe dock status
182
183 @retval EFI_SUCCESS Command success
184 @retval EFI_DEVICE_ERROR Command error
185 **/
186 EFI_STATUS
187 GetPcieDockStatus (
188 OUT UINT8 *DataBuffer
189 );
190
191
192 /**
193 Clear ten second power button mode
194
195 **/
196 VOID
197 ClearTenSecPwrButtonMode (
198 VOID
199 );
200
201
202 /**
203 Enable SATA port2 power
204
205 **/
206 VOID
207 EnableSataPort2Power (
208 VOID
209 );
210
211 /**
212 Set SLP_S0 Voltage
213
214 @param[in] EcDataV085ACNT
215 @retval EFI_SUCCESS Command success
216 @retval EFI_DEVICE_ERROR Command error
217 **/
218 EFI_STATUS
219 SetSlpS0Voltage (
220 IN UINT8 EcDataV085ACNT
221 );
222
223 /**
224 Detect Pmic Vendor ID
225 @param[out] DataBuffer
226
227 @retval EFI_SUCCESS Command success
228 @retval EFI_DEVICE_ERROR Command error
229 **/
230 EFI_STATUS
231 DetectPmicVendorID (
232 OUT UINT8 *DataBuffer
233 );
234
235 /**
236 Set Pmic Voltage
237
238 @param[in] EcDataVcc
239 @param[in] EcDataVddq
240
241 @retval EFI_SUCCESS Command success
242 @retval EFI_DEVICE_ERROR Command error
243 **/
244 EFI_STATUS
245 SetPmicVoltage (
246 IN UINT8 EcDataVcc,
247 IN UINT8 EcDataVddq
248 );
249
250
251 /**
252 Read data from EC RAM
253
254 @param[in][out] DataBuffer
255
256 @retval EFI_SUCCESS Command success
257 @retval EFI_DEVICE_ERROR Command error
258 **/
259 EFI_STATUS
260 ReadEcRam (
261 IN OUT UINT8 *DataBuffer
262 );
263
264
265 /**
266 Write data to EC RAM
267
268 @param[in][out] DataBuffer
269
270 @retval EFI_SUCCESS Command success
271 @retval EFI_DEVICE_ERROR Command error
272 **/
273 EFI_STATUS
274 WriteEcRam (
275 IN OUT UINT8 *DataBuffer
276 );
277
278
279 /**
280 Update Device Power
281
282 @retval EFI_SUCCESS Command success
283 @retval EFI_DEVICE_ERROR Command error
284 **/
285 EFI_STATUS
286 UpdateDevicePower (
287 VOID
288 );
289
290
291 /**
292 Query system status
293
294 @param[out] DataBuffer
295
296 @retval EFI_SUCCESS Command success
297 @retval EFI_DEVICE_ERROR Command error
298 **/
299 EFI_STATUS
300 QuerySysStatus (
301 OUT UINT8 *DataBuffer
302 );
303
304
305 /**
306 Get board fab ID
307
308 @param[out] BoardFabId
309
310 @retval EFI_SUCCESS Command success
311 @retval EFI_DEVICE_ERROR Command error
312 **/
313 EFI_STATUS
314 GetBoardInfo (
315 OUT UINT16 *BoardFabId
316 );
317
318
319 /**
320 Send Exit Low Power Mode command to EC
321
322 @retval EFI_SUCCESS Command success
323 @retval EFI_DEVICE_ERROR Command error
324 **/
325 EFI_STATUS
326 ExitLowPowerMode (
327 VOID
328 );
329
330
331 /**
332 System power off
333
334 @retval EFI_SUCCESS Command success
335 @retval EFI_DEVICE_ERROR Command error
336 **/
337 EFI_STATUS
338 SystemPowerOff (
339 VOID
340 );
341
342
343 /**
344 Detect EC support
345
346 @param[out] DataBuffer
347
348 @retval EFI_SUCCESS Command success
349 @retval EFI_DEVICE_ERROR Command error
350 **/
351 EFI_STATUS
352 DetectEcSupport (
353 OUT UINT8 *DataBuffer
354 );
355
356 /**
357 Detect EC revision
358
359 @param[out] DataBuffer
360
361 @retval EFI_SUCCESS Command success
362 @retval EFI_DEVICE_ERROR Command error
363 **/
364 EFI_STATUS
365 DetectEcRevision (
366 OUT UINT8 *DataBuffer
367 );
368
369
370 /**
371 Disable PCH DTS reading on SMLink 1
372
373 @param[in] Disable 0: Enable PCH DTS reading
374 1: Disable PCH DTS reading
375
376 @retval EFI_SUCCESS Command success
377 @retval EFI_DEVICE_ERROR Command error
378 **/
379 EFI_STATUS
380 DisablePchDtsReading (
381 IN UINT8 Disable
382 );
383
384 /**
385 Wake up EC
386
387 @retval TRUE EC wake up successfully.
388 @retval FALSE Fail to wake up EC.
389 **/
390 EFI_STATUS
391 WakeUpEc (
392 VOID
393 );
394
395 /**
396 Send Update PWM command to EC
397
398 @param EFI_SUCCESS Command success
399 @param EFI_DEVICE_ERROR Command error
400 **/
401 EFI_STATUS
402 UpdatePwm (
403 VOID
404 );
405
406 /**
407 Updates the PWM to the given value and returns the Fan speed.
408 @param Pwmvalue Pwm ending value
409 @param Speed Updates the Speed
410
411 @retval EFI_SUCCESS when successfully able to get the nominal data.
412 @retval ERROR Error if anything went wrong.
413
414 **/
415 EFI_STATUS
416 GetFanSpeed(
417 IN UINT8 Pwmvalue,
418 OUT UINT16 *Speed
419 );
420
421
422 /**
423 Select charging method
424
425 @param[in] Enable TURE - Fast charging (DFCT)
426 FALSE - Normal charging
427
428 @retval EFI_SUCCESS Command success
429 @retval EFI_DEVICE_ERROR Command error
430 **/
431 EFI_STATUS
432 DfctFastChargingMode (
433 IN BOOLEAN Enable
434 );
435
436 /**
437 EcForceResetAfterAcRemoval
438
439 @param[in] ForceResetAfterAcRemovalVar 0 : Clear AC Removal reset bit in EC
440 1 : Set AC Removal reset bit in EC
441 **/
442 VOID
443 EcForceResetAfterAcRemoval (
444 IN UINT8 ForceResetAfterAcRemovalVar
445 );
446
447 /**
448 Allow EC to control Fail Safe Fan control to avoid silicon burnout after hung state.
449 It is effective after CpuTemp is reached by running Fan at specified PWM
450
451 @param[in] CpuTemp
452 @param[in] CpuFanSpeed
453
454 @retval EFI_SUCCESS Function successfully executed.
455 **/
456 EFI_STATUS
457 SetFailSafeFanCtrl (
458 UINT8 CpuTemp,
459 UINT8 CpuFanSpeed
460 );
461
462 /**
463 ec wdt read command
464
465 @param[in] DataBuffer, 1 byte will be read through 0x66
466
467 @retval EFI_SUCCESS Command success
468 @retval EFI_DEVICE_ERROR Command error
469 **/
470 EFI_STATUS
471 BiosEcWdtReadCommand (
472 IN OUT UINT8 *DataBuffer
473 );
474
475 /**
476 ec wdt write command
477
478 @param[in] DataBuffer, 2 bytes write for ECWDT through 0x66
479
480 @retval EFI_SUCCESS Command success
481 @retval EFI_DEVICE_ERROR Command error
482 **/
483 EFI_STATUS
484 BiosEcWdtWriteCommand (
485 IN UINT8 *DataBuffer
486 );
487
488 /**
489 Arm ec wdt with specific timeout
490
491 @param[in] timeout value
492
493 @retval EFI_SUCCESS Command success
494 @retval EFI_DEVICE_ERROR Command error
495 **/
496 EFI_STATUS
497 ArmEcWdtWithTimeOut (
498 IN UINT8 TimeOut
499 );
500
501 /**
502 Dis arm ec wdt
503
504 @param[in] timeout value
505
506 @retval EFI_SUCCESS Command success
507 @retval EFI_DEVICE_ERROR Command error
508 **/
509 EFI_STATUS
510 DisArmEcWdt (
511 VOID
512 );
513
514 /**
515 Notify Ec To Pd firmware for enabling or disabling Pcie.
516
517 @param[in] PcieTunneling a switch to enable or disable Pcie
518 **/
519 VOID
520 NotifyEcToPdForPcieTunnel (
521 IN UINT8 PcieTunneling
522 );
523
524
525 /**
526 Notify Ec To Pd firmware for enabling Vpro.
527 **/
528 VOID
529 NotifyEcToPdForVpro (
530 VOID
531 );
532 #endif
EnableLanPower
EFI_STATUS EnableLanPower(IN BOOLEAN Enable)
Enable LAN power.
EnableSataPort2Power
VOID EnableSataPort2Power(VOID)
Enable SATA port2 power.
EnableEcAcpiMode
EFI_STATUS EnableEcAcpiMode(IN BOOLEAN Enable)
Send enable ACPI mode command to EC.
SetFailSafeFanCtrl
EFI_STATUS SetFailSafeFanCtrl(UINT8 CpuTemp, UINT8 CpuFanSpeed)
Allow EC to control Fail Safe Fan control to avoid silicon burnout after hung state.
QuerySmiEvent
EFI_STATUS QuerySmiEvent(OUT UINT8 *DataBuffer)
Query SMI event.
BiosEcWdtReadCommand
EFI_STATUS BiosEcWdtReadCommand(IN OUT UINT8 *DataBuffer)
ec wdt read command
GetBatteryNumber
EFI_STATUS GetBatteryNumber(OUT UINT8 *DataBuffer)
Get the number of battery.
NotifyEcToPdForPcieTunnel
VOID NotifyEcToPdForPcieTunnel(IN UINT8 PcieTunneling)
Notify Ec To Pd firmware for enabling or disabling Pcie.
NotifyEcToPdForVpro
VOID NotifyEcToPdForVpro(VOID)
Notify Ec To Pd firmware for enabling Vpro.
EcCommands.h
DisableEcSmiMode
EFI_STATUS DisableEcSmiMode(VOID)
Send disable SMI mode command to EC.
QuerySysStatus
EFI_STATUS QuerySysStatus(OUT UINT8 *DataBuffer)
Query system status.
DisArmEcWdt
EFI_STATUS DisArmEcWdt(VOID)
Dis arm ec wdt.
PowerStateIsAc
BOOLEAN PowerStateIsAc(VOID)
Get power state from EC.
ClearTenSecPwrButtonMode
VOID ClearTenSecPwrButtonMode(VOID)
Clear ten second power button mode.
WriteEcRam
EFI_STATUS WriteEcRam(IN OUT UINT8 *DataBuffer)
Write data to EC RAM.
ArmEcWdtWithTimeOut
EFI_STATUS ArmEcWdtWithTimeOut(IN UINT8 TimeOut)
Arm ec wdt with specific timeout.
DetectPmicVendorID
EFI_STATUS DetectPmicVendorID(OUT UINT8 *DataBuffer)
Detect Pmic Vendor ID.
DetectEcSupport
EFI_STATUS DetectEcSupport(OUT UINT8 *DataBuffer)
Detect EC support.
DisablePchDtsReading
EFI_STATUS DisablePchDtsReading(IN UINT8 Disable)
Disable PCH DTS reading on SMLink 1.
SetPmicVoltage
EFI_STATUS SetPmicVoltage(IN UINT8 EcDataVcc, IN UINT8 EcDataVddq)
Set Pmic Voltage.
GetFanSpeed
EFI_STATUS GetFanSpeed(IN UINT8 Pwmvalue, OUT UINT16 *Speed)
Updates the PWM to the given value and returns the Fan speed.
ReadEcRam
EFI_STATUS ReadEcRam(IN OUT UINT8 *DataBuffer)
Read data from EC RAM.
SystemPowerOff
EFI_STATUS SystemPowerOff(VOID)
System power off.
DfctFastChargingMode
EFI_STATUS DfctFastChargingMode(IN BOOLEAN Enable)
Select charging method.
EcForceResetAfterAcRemoval
VOID EcForceResetAfterAcRemoval(IN UINT8 ForceResetAfterAcRemovalVar)
EcForceResetAfterAcRemoval.
GetHotkeyScanCode
EFI_STATUS GetHotkeyScanCode(OUT UINT8 *DataBuffer)
Get the scan code of hotkey pressed (CTRL + ALT + SHIFT + key)
WakeUpEc
EFI_STATUS WakeUpEc(VOID)
Wake up EC.
SetSlpS0Voltage
EFI_STATUS SetSlpS0Voltage(IN UINT8 EcDataV085ACNT)
Set SLP_S0 Voltage.
GetPcieDockStatus
EFI_STATUS GetPcieDockStatus(OUT UINT8 *DataBuffer)
Get PCIe dock status.
GetBoardInfo
EFI_STATUS GetBoardInfo(OUT UINT16 *BoardFabId)
Get board fab ID.
EcReset
EFI_STATUS EcReset(VOID)
Do EC reset.
BiosEcWdtWriteCommand
EFI_STATUS BiosEcWdtWriteCommand(IN UINT8 *DataBuffer)
ec wdt write command
SetEcCriticalShutdownTemperature
EFI_STATUS SetEcCriticalShutdownTemperature(IN UINT8 DataBuffer)
Set EC critical shutdown temperature.
EcResetEcInNormalMode
EFI_STATUS EcResetEcInNormalMode(VOID)
Initiate EC reset sequence.
ExitLowPowerMode
EFI_STATUS ExitLowPowerMode(VOID)
Send Exit Low Power Mode command to EC.
EcLib.h
EC library functions and definitions.
DetectEcRevision
EFI_STATUS DetectEcRevision(OUT UINT8 *DataBuffer)
Detect EC revision.
UpdateDevicePower
EFI_STATUS UpdateDevicePower(VOID)
Update Device Power.
UpdatePwm
EFI_STATUS UpdatePwm(VOID)
Send Update PWM command to EC.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcSmi.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
Functions
EcSmi.c File Reference

This file processes hotkey dispatch and callback event. More...

#include "PlatformInitAdvancedSmm.h"
#include <Library/EcLib.h>
#include <Library/EcMiscLib.h>
#include <Library/EcCommands.h>
Include dependency graph for EcSmi.c:

Go to the source code of this file.

Functions

VOID eSpiEcSmiCallback (IN EFI_HANDLE DispatchHandle)
eSPI EC SMI callback function. More...

Detailed Description

This file processes hotkey dispatch and callback event.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EcSmi.c.

Function Documentation

◆ eSpiEcSmiCallback()

VOID eSpiEcSmiCallback ( IN EFI_HANDLE DispatchHandle )

eSPI EC SMI callback function.

Parameters
[in] DispatchHandle Not used

Definition at line 52 of file EcSmi.c.


AlderLake Platform Sample Code: EcSmi.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
EcSmi.c
Go to the documentation of this file.
1 /** @file
2 This file processes hotkey dispatch and callback event.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include "PlatformInitAdvancedSmm.h"
36 #include <Library/EcLib.h>
37 #include <Library/EcMiscLib.h>
38 #include <Library/EcCommands.h>
39
40 //
41 // Internal functions
42 //
43
44 /**
45 eSPI EC SMI callback function.
46
47 @param[in] DispatchHandle Not used
48
49 **/
50 VOID
51 EFIAPI
52 eSpiEcSmiCallback (
53 IN EFI_HANDLE DispatchHandle
54 )
55 {
56 //
57 // This is a dummy handling routine.
58 //
59 IoWrite8 (EC_C_PORT, EC_C_SMI_QUERY);
60 IoRead8 (EC_D_PORT);
61 }
EcCommands.h
PlatformInitAdvancedSmm.h
Header file for the Platform Advanced SMM Driver.
EcMiscLib.h
EC miscellaneous library functions.
eSpiEcSmiCallback
VOID eSpiEcSmiCallback(IN EFI_HANDLE DispatchHandle)
eSPI EC SMI callback function.
Definition: EcSmi.c:52
EcLib.h
EC library functions and definitions.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcSmi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
EcSmi.h File Reference

Header file for EC SMI handlers. More...

#include <Library/EcLib.h>
Include dependency graph for EcSmi.h:

Go to the source code of this file.

Detailed Description

Header file for EC SMI handlers.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file EcSmi.h.


AlderLake Platform Sample Code: EcSmi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
EcSmi.h
Go to the documentation of this file.
1 /** @file
2 Header file for EC SMI handlers.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _EC_SMI_H_
36 #define _EC_SMI_H_
37
38 //
39 // Include files
40 //
41 #include <Library/EcLib.h>
42
43 #endif
EcLib.h
EC library functions and definitions.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EcTcssLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
EcTcssLib.h File Reference

EC TCSS library functions. More...

#include <Base.h>
#include <Uefi.h>
#include <Library/EcCommands.h>
#include <Library/EcLib.h>
Include dependency graph for EcTcssLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | UsbcRetimerCompliancePDMessage (IN OUT UINT8 *DataBuffer)
Usbc Retimer Compliance Mode. More...
EFI_STATUS | UsbcIomReadyNotify (IN OUT UINT8 *DataBuffer)
USBC IOM Ready Notify. More...
EFI_STATUS | UsbcGetUsbConnStatus (IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Entry Wait. More...
EFI_STATUS | UsbcSxEntry (IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
Send enable ACPI mode command to EC. More...
EFI_STATUS | UsbcSxExit (OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Exit Wait. More...
EFI_STATUS | SetPdControllerMode (IN UINT8 PdControllerMode, IN UINT8 PdControllerNumber)
Set PD Controller Mode. More...
EFI_STATUS | GetPdControllerMode (OUT UINT8 *PdControllerModeBuffer, IN UINT8 PdControllerNumber, IN UINT32 TotalCountOfPdController)
Get PD Controller Mode. More...

Detailed Description

EC TCSS library functions.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file EcTcssLib.h.

Function Documentation

◆ GetPdControllerMode()

EFI_STATUS GetPdControllerMode | ( | OUT UINT8 * | PdControllerModeBuffer,
 |  | IN UINT8 | PdControllerNumber,
 |  | IN UINT32 | TotalCountOfPdController
 | ) |  |

Get PD Controller Mode.

Parameters
[out] | *PdControllerModeBuffer
[in] | PdControllerNumber
[in] | TotalCountOfPdController
Return values
EFI_SUCCESS | Command success
EFI_TIMEOUT | Command timeout
EFI_DEVICE_ERROR | Command error
EFI_INVALID_PARAMETER | Command usage error.

◆ SetPdControllerMode()

EFI_STATUS SetPdControllerMode | ( | IN UINT8 | PdControllerMode,
 |  | IN UINT8 | PdControllerNumber
 | ) |  |

Set PD Controller Mode.

Parameters
[in] | PdControllerMode
[in] | PdControllerNumber
Return values
EFI_SUCCESS | Command success
EFI_TIMEOUT | Command timeout
EFI_DEVICE_ERROR | Command error
EFI_INVALID_PARAMETER | Command usage error.

◆ UsbcGetUsbConnStatus()

EFI_STATUS UsbcGetUsbConnStatus | ( | IN OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

USBC Sx Entry Wait.

Parameters
[in]

◆ UsbcIomReadyNotify()

EFI_STATUS UsbcIomReadyNotify ( IN OUT UINT8 * DataBuffer )

USBC IOM Ready Notify.

Parameters
[in]

◆ UsbcRetimerCompliancePDMessage()

EFI_STATUS UsbcRetimerCompliancePDMessage ( IN OUT UINT8 * DataBuffer )

Usbc Retimer Compliance Mode.

Parameters
[in]

◆ UsbcSxEntry()

EFI_STATUS UsbcSxEntry | ( | IN OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

Send enable ACPI mode command to EC.

Parameters
[in]

◆ UsbcSxExit()

EFI_STATUS UsbcSxExit | ( | OUT UINT8 * | DataBuffer,
 |  | IN UINT32 | Timeout
 | ) |  |

USBC Sx Exit Wait.

Parameters
[out] | DataBuffer
[in] | Timeout
Return values
EFI_SUCCESS | Command success
EFI_DEVICE_ERROR | Command error


AlderLake Platform Sample Code: EcTcssLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
EcTcssLib.h
Go to the documentation of this file.
1 /** @file
2 EC TCSS library functions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _BASE_EC_TCSS_LIB_H_
36 #define _BASE_EC_TCSS_LIB_H_
37
38 //
39 // Include files
40 //
41 #include <Base.h>
42 #include <Uefi.h>
43 #include <Library/EcCommands.h>
44 #include <Library/EcLib.h>
45
46 //
47 // Retry time in milli-seconds for EC-TCSS commands with Timeout
48 //
49 #define EC_TCSS_RETRY_TIME_GET_USB_CONN_STATUS 10
50 #define EC_TCSS_RETRY_TIME_SX_ENTRY_WAIT 100
51 #define EC_TCSS_RETRY_TIME_SX_EXIT_WAIT 100
52
53 //
54 // Bitmasks for USBC IOM Ready Notify message request byte
55 //
56 #define EC_TCSS_BITMASK_REPLAY_MESSAGES 0x01
57 #define EC_TCSS_BITMASK_VCCST_ON 0x02
58
59 //
60 // Define all PD Mode supported by EC
61 //
62 typedef enum {
63 RetimerFirmWareUpdateDisableMode = 0,
64 RetimerFirmWareUpdateEnableMode = 1,
65 InvalidRetimerFirmWareUpdateMode
66 } EC_C_PD_RETIMER_FW_UPDATE_MODE;
67
68 #define EC_SET_PD_MODE_WAIT_TIME_IN_FACTOR_OF_50_MS 10 // EC Wait time after Sending SET PD MODE command in Factor of 50 MiliSec
69 #define EC_C_ALL_PD_CONTROLLER_INDEX 0xFE // PD Controller Index to SET mode of all PD Controller
70
71 //
72 // Currently EC is supporting 2 PD controller and following BIT MAP for each
73 // controller.
74 // BIT0 - 1 - PD0 I2C cmd successful ( 0 - fail )
75 // BIT1 - 1 - PD0 in FORCE TBT Mode (0 - not in force tbt mode)
76 // BIT2-BIT3 - Reserved
77 // BIT4 - 1 - PD1 I2C cmd successful(0 - fail)
78 // BIT5 - 1 - PD1 in FORCE TBT Mode (0 - not in force tbt mode)
79 // BIT6-BIT7 - Reserved
80 // So currently EC is using 4 BIT for EACH Controller and 8 BIT in total.
81 //
82 #define GET_PD_MODE_STATUS_BIT_WIDTH_TOTAL 8
83 #define GET_PD_MODE_STATUS_BIT_WIDTH_PER_CONTROLLER 4
84 #define I2C_COMMAND_SUCCESSFUL BIT0 // I2C cmd successful ( 0 - fail )
85 #define RETIMER_FW_UPDATE_MODE BIT1 // FORCE TBT Mode (0 - not in force tbt mode)
86
87 /**
88 Usbc Retimer Compliance Mode
89
90 @param[in][out] DataBuffer
91
92 @retval EFI_SUCCESS Command success
93 @retval EFI_DEVICE_ERROR Command error
94 **/
95 EFI_STATUS
96 UsbcRetimerCompliancePDMessage (
97 IN OUT UINT8 *DataBuffer
98 );
99
100 /**
101 USBC IOM Ready Notify
102
103 @param[in][out] DataBuffer
104
105 @retval EFI_SUCCESS Command success
106 @retval EFI_DEVICE_ERROR Command error
107 **/
108 EFI_STATUS
109 UsbcIomReadyNotify (
110 IN OUT UINT8 *DataBuffer
111 );
112
113 /**
114 USBC Sx Entry Wait
115
116 @param[in][out] DataBuffer
117 @param[in] Timeout
118
119 @retval EFI_SUCCESS Command success
120 @retval EFI_DEVICE_ERROR Command error
121 **/
122 EFI_STATUS
123 UsbcGetUsbConnStatus (
124 IN OUT UINT8 *DataBuffer,
125 IN UINT32 Timeout
126 );
127
128 /**
129 Send enable ACPI mode command to EC
130
131 @param[in][out] DataBuffer
132 @param[in] Timeout
133
134 @retval EFI_SUCCESS Command success
135 @retval EFI_DEVICE_ERROR Command error
136 **/
137 EFI_STATUS
138 UsbcSxEntry (
139 IN OUT UINT8 *DataBuffer
140 , IN UINT32 Timeout
141 );
142
143 /**
144 USBC Sx Exit Wait
145
146 @param[out] DataBuffer
147 @param[in] Timeout
148
149 @retval EFI_SUCCESS Command success
150 @retval EFI_DEVICE_ERROR Command error
151 **/
152 EFI_STATUS
153 UsbcSxExit (
154 OUT UINT8 *DataBuffer
155 , IN UINT32 Timeout
156 );
157
158 /**
159 Set PD Controller Mode
160
161 @param[in] PdControllerMode
162 @param[in] PdControllerNumber
163
164 @retval EFI_SUCCESS Command success
165 @retval EFI_TIMEOUT Command timeout
166 @retval EFI_DEVICE_ERROR Command error
167 @retval EFI_INVALID_PARAMETER Command usage error.
168 **/
169 EFI_STATUS
170 SetPdControllerMode (
171 IN UINT8 PdControllerMode,
172 IN UINT8 PdControllerNumber
173 );
174
175 /**
176 Get PD Controller Mode
177
178 @param[out] *PdControllerModeBuffer
179 @param[in] PdControllerNumber
180 @param[in] TotalCountOfPdController
181
182 @retval EFI_SUCCESS Command success
183 @retval EFI_TIMEOUT Command timeout
184 @retval EFI_DEVICE_ERROR Command error
185 @retval EFI_INVALID_PARAMETER Command usage error.
186 **/
187 EFI_STATUS
188 GetPdControllerMode (
189 OUT UINT8 *PdControllerModeBuffer,
190 IN UINT8 PdControllerNumber,
191 IN UINT32 TotalCountOfPdController
192 );
193 #endif // _BASE_EC_TCSS_LIB_H_
UsbcSxExit
EFI_STATUS UsbcSxExit(OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Exit Wait.
UsbcRetimerCompliancePDMessage
EFI_STATUS UsbcRetimerCompliancePDMessage(IN OUT UINT8 *DataBuffer)
Usbc Retimer Compliance Mode.
SetPdControllerMode
EFI_STATUS SetPdControllerMode(IN UINT8 PdControllerMode, IN UINT8 PdControllerNumber)
Set PD Controller Mode.
EcCommands.h
UsbcSxEntry
EFI_STATUS UsbcSxEntry(IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
Send enable ACPI mode command to EC.
UsbcGetUsbConnStatus
EFI_STATUS UsbcGetUsbConnStatus(IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
USBC Sx Entry Wait.
GetPdControllerMode
EFI_STATUS GetPdControllerMode(OUT UINT8 *PdControllerModeBuffer, IN UINT8 PdControllerNumber, IN UINT32 TotalCountOfPdController)
Get PD Controller Mode.
EcLib.h
EC library functions and definitions.
UsbcIomReadyNotify
EFI_STATUS UsbcIomReadyNotify(IN OUT UINT8 *DataBuffer)
USBC IOM Ready Notify.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Efi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Efi.h File Reference
#include "Tiano.h"
Include dependency graph for Efi.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Efi.h.


AlderLake Platform Sample Code: Efi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Efi.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _EFI_H_
35 #define _EFI_H_
36
37 #include "Tiano.h"
38
39 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: EfiUsbFnIo.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Classes | Typedefs
EfiUsbFnIo.h File Reference

EFI USB function IO Protocol This protocol supports Usb Function IO API. More...

#include <IndustryStandard/Usb.h>
Include dependency graph for EfiUsbFnIo.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct EFI_USB_INTERFACE_INFO
USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR are already defined in UEFI spec 2.3, as par USB 2.0 spec. More...

Typedefs

typedef EFI_STATUS(* | EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)
Allocates transfer buffer of the specified size that satisfies controller requirements. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN VOID *Buffer)
Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
typedef EFI_STATUS(* | EFI_USBFN_IO_DETECT_PORT) (IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_PORT_TYPE *PortType)
Returns information about what type of device was attached.
typedef EFI_STATUS(* | EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo)
Configure endpoints based on supplied device and configuration descriptors.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_ENDPOINT_TYPE EndpointType, IN EFI_USB_BUS_SPEED BusSpeed, OUT UINT16 *MaxPacketSize)
Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (IN EFI_USBFN_IO_PROTOCOL *This, OUT UINTN *MaxTransferSize)
Returns the maximum supported transfer size.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_DEVICE_INFO) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USBFN_DEVICE_INFO_ID Id, IN OUT UINTN *BufferSize, OUT VOID *Buffer OPTIONAL)
Returns device specific information based on the supplied identifier as a Unicode string.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (IN EFI_USBFN_IO_PROTOCOL *This, OUT UINT16 *Vid, OUT UINT16 *Pid)
Returns vendor-id and product-id of the device.
typedef EFI_STATUS(* | EFI_USBFN_IO_ABORT_TRANSFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction)
Aborts transfer on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT BOOLEAN *State)
Returns the stall state on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN BOOLEAN State)
Sets or clears the stall state on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_EVENTHANDLER) (IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_MESSAGE *Message, IN OUT UINTN *PayloadSize, OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload)
This function is called repeatedly to receive updates on USB bus states, receive, transmit status changes on endpoints and setup packet on endpoint 0.
typedef EFI_STATUS(* | EFI_USBFN_IO_TRANSFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
Primary function to handle transfer in either direction based on specified direction and on the specified endpoint.
typedef EFI_STATUS(* | EFI_USBFN_IO_START_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)
This function supplies power to the USB controller if needed, initialize hardware and internal data structures, and then return. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_STOP_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)
This function disables the hardware device by resetting the run/stop bit and power off the USB controller if needed.
typedef EFI_STATUS(* | EFI_USBFN_IO_SET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)
This function sets the configuration policy for the specified non-control endpoint. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_GET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
This function retrieves the configuration policy for the specified non-control endpoint. More...
typedef EFI_STATUS(* | EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo, IN EFI_USB_SUPERSPEED_DEVICE_INFO *SSDeviceInfo)
This function configures endpoints based on supplied list of device and configuration descriptors. More...

Detailed Description

EFI USB function IO Protocol This protocol supports Usb Function IO API.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file EfiUsbFnIo.h.

Typedef Documentation

◆ EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER

typedef EFI_STATUS( * EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)

Allocates transfer buffer of the specified size that satisfies controller requirements.

The AllocateTransferBuffer function allocates a memory region of Size bytes and returns the address of the allocated memory that satisfies underlying controller requirements in the location referenced by Buffer.

Definition at line 259 of file EfiUsbFnIo.h.

◆ EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX

typedef EFI_STATUS( * EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX) (IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo, IN EFI_USB_SUPERSPEED_DEVICE_INFO *SSDeviceInfo)

This function configures endpoints based on supplied list of device and configuration descriptors.

There are no associated calling restrictions for this function.

Definition at line 469 of file EfiUsbFnIo.h.

◆ EFI_USBFN_IO_GET_ENDPOINT_POLICY

typedef EFI_STATUS( * EFI_USBFN_IO_GET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)

This function retrieves the configuration policy for the specified non-control endpoint.

There are no associated calling restrictions for this function.

Definition at line 453 of file EfiUsbFnIo.h.

◆ EFI_USBFN_IO_SET_ENDPOINT_POLICY

typedef EFI_STATUS( * EFI_USBFN_IO_SET_ENDPOINT_POLICY) (IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)

This function sets the configuration policy for the specified non-control endpoint.

Refer to the description for calling restrictions.

Definition at line 437 of file EfiUsbFnIo.h.

◆ EFI_USBFN_IO_START_CONTROLLER

typedef EFI_STATUS( * EFI_USBFN_IO_START_CONTROLLER) (IN EFI_USBFN_IO_PROTOCOL *This)

This function supplies power to the USB controller if needed, initialize hardware and internal data structures, and then return.

The port must not be activated by this function.

Definition at line 416 of file EfiUsbFnIo.h.


AlderLake Platform Sample Code: EfiUsbFnIo.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
EfiUsbFnIo.h
Go to the documentation of this file.
1 /** @file
2 EFI USB function IO Protocol
3 This protocol supports Usb Function IO API.
4
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2015 - 2020 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification
35 **/
36
37 #ifndef __EFI_USB_FUNC_IO_H__
38 #define __EFI_USB_FUNC_IO_H__
39
40 #include <IndustryStandard/Usb.h>
41
42 #define EFI_USBFN_IO_PROTOCOL_REVISION 0x00010002
43
44 /* //{32D2963A-FE5D-4f30-B633-6E5DC55803CC}
45 #define EFI_USBFN_IO_PROTOCOL_GUID \
46 {0x32d2963a, 0xfe5d, 0x4f30, 0xb6, 0x33, 0x6e, 0x5d, 0xc5, \
47 0x58, 0x3, 0xcc };
48 */
49
50 typedef struct _EFI_USBFN_IO_PROTOCOL EFI_USBFN_IO_PROTOCOL;
51
52 //
53 // USB standard descriptors and reqeust
54 //
55 typedef USB_DEVICE_REQUEST EFI_USB_DEVICE_REQUEST;
56 typedef USB_DEVICE_DESCRIPTOR EFI_USB_DEVICE_DESCRIPTOR;
57 typedef USB_CONFIG_DESCRIPTOR EFI_USB_CONFIG_DESCRIPTOR;
58 typedef USB_INTERFACE_DESCRIPTOR EFI_USB_INTERFACE_DESCRIPTOR;
59 typedef USB_ENDPOINT_DESCRIPTOR EFI_USB_ENDPOINT_DESCRIPTOR;
60
61 typedef enum _EFI_USBFN_PORT_TYPE {
62 EfiUsbUnknownPort = 0,
63 EfiUsbStandardDownstreamPort,
64 EfiUsbChargingDownstreamPort,
65 EfiUsbDedicatedChargingPort,
66 EfiUsbInvalidDedicatedChargingPort
67 } EFI_USBFN_PORT_TYPE;
68
69 /**
70 USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and
71 USB_ENDPOINT_DESCRIPTOR are already defined
72 in UEFI spec 2.3, as par USB 2.0 spec.
73 **/
74
75 typedef struct {
76 EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;
77 EFI_USB_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;
78 } EFI_USB_INTERFACE_INFO;
79
80 typedef struct {
81 EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;
82 EFI_USB_INTERFACE_INFO **InterfaceInfoTable;
83 } EFI_USB_CONFIG_INFO;
84
85 typedef struct {
86 EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;
87 EFI_USB_CONFIG_INFO **ConfigInfoTable;
88 } EFI_USB_DEVICE_INFO;
89
90 typedef struct {
91 UINT8 Length;
92 UINT8 DescriptorType;
93 UINT16 TotalLength;
94 UINT8 NumDeviceCaps;
95 } EFI_USB_BOS_DESCRIPTOR;
96
97 typedef struct
98 {
99 UINT8 Length;
100 UINT8 DescriptorType;
101 UINT8 MaxBurst;
102 UINT8 Attributes;
103 UINT16 BytesPerInterval;
104 } EFI_USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR;
105
106 typedef struct
107 {
108 EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDescriptor;
109 EFI_USB_SUPERSPEED_ENDPOINT_COMPANION_DESCRIPTOR *EndpointCompanionDescriptor;
110 } EFI_USB_SUPERSPEED_ENDPOINT_DESCRIPTOR;
111
112 typedef struct
113 {
114 EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDescriptor;
115 EFI_USB_SUPERSPEED_ENDPOINT_DESCRIPTOR **EndpointDescriptorTable;
116 } EFI_USB_SUPERSPEED_INTERFACE_INFO;
117
118 typedef struct
119 {
120 EFI_USB_CONFIG_DESCRIPTOR *ConfigDescriptor;
121 EFI_USB_SUPERSPEED_INTERFACE_INFO **InterfaceInfoTable;
122 } EFI_USB_SUPERSPEED_CONFIG_INFO;
123
124 typedef struct {
125 EFI_USB_DEVICE_DESCRIPTOR *DeviceDescriptor;
126 EFI_USB_SUPERSPEED_CONFIG_INFO **ConfigInfoTable;
127 EFI_USB_BOS_DESCRIPTOR *BosDescriptor;
128 } EFI_USB_SUPERSPEED_DEVICE_INFO;
129
130 typedef enum _EFI_USB_ENDPOINT_TYPE {
131 UsbEndpointControl = 0x00,
132 UsbEndpointIsochronous = 0x01,
133 UsbEndpointBulk = 0x02,
134 UsbEndpointInterrupt = 0x03
135 } EFI_USB_ENDPOINT_TYPE;
136
137
138 typedef enum _EFI_USBFN_DEVICE_INFO_ID {
139 EfiUsbDeviceInfoUnknown = 0,
140 EfiUsbDeviceInfoSerialNumber,
141 EfiUsbDeviceInfoManufacturerName,
142 EfiUsbDeviceInfoProductName
143 } EFI_USBFN_DEVICE_INFO_ID;
144
145
146 typedef enum _EFI_USBFN_ENDPOINT_DIRECTION {
147 EfiUsbEndpointDirectionHostOut = 0,
148 EfiUsbEndpointDirectionHostIn,
149 EfiUsbEndpointDirectionDeviceTx = EfiUsbEndpointDirectionHostIn,
150 EfiUsbEndpointDirectionDeviceRx = EfiUsbEndpointDirectionHostOut
151 } EFI_USBFN_ENDPOINT_DIRECTION;
152
153
154 typedef enum _EFI_USBFN_MESSAGE {
155 //
156 // Nothing
157 //
158 EfiUsbMsgNone = 0,
159 //
160 // SETUP packet is received, returned Buffer contains
161 // EFI_USB_DEVICE_REQUEST struct
162 //
163 EfiUsbMsgSetupPacket,
164 //
165 // Indicates that some of the requested data has been received from the
166 // host. It is the responsibility of the class driver to determine if it
167 // needs to wait for any remaining data. Returned Buffer contains
168 // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
169 // status and count of bytes received.
170 //
171 EfiUsbMsgEndpointStatusChangedRx,
172 //
173 // Indicates that some of the requested data has been transmitted to the
174 // host. It is the responsibility of the class driver to determine if any
175 // remaining data needs to be resent. Returned Buffer contains
176 // EFI_USBFN_TRANSFER_RESULT struct containing endpoint number, transfer
177 // status and count of bytes sent.
178 //
179 EfiUsbMsgEndpointStatusChangedTx,
180 //
181 // DETACH bus event signaled
182 //
183 EfiUsbMsgBusEventDetach,
184 //
185 // ATTACH bus event signaled
186 //
187 EfiUsbMsgBusEventAttach,
188 //
189 // RESET bus event signaled
190 //
191 EfiUsbMsgBusEventReset,
192 //
193 // SUSPEND bus event signaled
194 //
195 EfiUsbMsgBusEventSuspend,
196 //
197 // RESUME bus event signaled
198 //
199 EfiUsbMsgBusEventResume,
200 //
201 // Bus speed updated, returned buffer indicated bus speed using
202 // following enumeration named EFI_USB_BUS_SPEED
203 //
204 EfiUsbMsgBusEventSpeed
205 } EFI_USBFN_MESSAGE;
206
207
208 typedef enum _EFI_USBFN_TRANSFER_STATUS {
209 UsbTransferStatusUnknown = 0,
210 UsbTransferStatusComplete,
211 UsbTransferStatusAborted,
212 UsbTransferStatusActive,
213 UsbTransferStatusNone
214 } EFI_USBFN_TRANSFER_STATUS;
215
216
217 typedef struct _EFI_USBFN_TRANSFER_RESULT {
218 UINTN BytesTransferred;
219 EFI_USBFN_TRANSFER_STATUS TransferStatus;
220 UINT8 EndpointIndex;
221 EFI_USBFN_ENDPOINT_DIRECTION Direction;
222 VOID *Buffer;
223 } EFI_USBFN_TRANSFER_RESULT;
224
225 typedef enum _EFI_USB_BUS_SPEED {
226 UsbBusSpeedUnknown = 0,
227 UsbBusSpeedLow,
228 UsbBusSpeedFull,
229 UsbBusSpeedHigh,
230 UsbBusSpeedSuper,
231 UsbBusSpeedMaximum = UsbBusSpeedSuper
232 } EFI_USB_BUS_SPEED;
233
234 typedef union _EFI_USBFN_MESSAGE_PAYLOAD {
235 EFI_USB_DEVICE_REQUEST udr;
236 EFI_USBFN_TRANSFER_RESULT utr;
237 EFI_USB_BUS_SPEED ubs;
238 } EFI_USBFN_MESSAGE_PAYLOAD;
239
240 typedef enum _EFI_USBFN_POLICY_TYPE {
241 EfiUsbPolicyUndefined = 0,
242 EfiUsbPolicyMaxTransactionSize,
243 EfiUsbPolicyZeroLengthTerminationSupport,
244 EfiUsbPolicyZeroLengthTermination
245 } EFI_USBFN_POLICY_TYPE;
246
247
248 /**
249
250 Allocates transfer buffer of the specified size that satisfies
251 controller requirements.
252
253 The AllocateTransferBuffer function allocates a memory region of Size bytes and
254 returns the address of the allocated memory that satisfies underlying
255 controller requirements in the location referenced by Buffer.
256
257 **/
258 typedef
259 EFI_STATUS
260 (EFIAPI * EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER) (
261 IN EFI_USBFN_IO_PROTOCOL *This,
262 IN UINTN Size,
263 OUT VOID **Buffer
264 );
265
266 /**
267
268 Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
269
270 **/
271 typedef
272 EFI_STATUS
273 (EFIAPI * EFI_USBFN_IO_FREE_TRANSFER_BUFFER) (
274 IN EFI_USBFN_IO_PROTOCOL *This,
275 IN VOID *Buffer
276 );
277
278 /**
279 Returns information about what type of device was attached.
280
281 **/
282 typedef
283 EFI_STATUS
284 (EFIAPI * EFI_USBFN_IO_DETECT_PORT) (
285 IN EFI_USBFN_IO_PROTOCOL *This,
286 OUT EFI_USBFN_PORT_TYPE *PortType
287 );
288
289 /**
290 Configure endpoints based on supplied device and configuration descriptors.
291 **/
292 typedef
293 EFI_STATUS
294 (EFIAPI * EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS) (
295 IN EFI_USBFN_IO_PROTOCOL *This,
296 IN EFI_USB_DEVICE_INFO *DeviceInfo
297 );
298
299
300 /**
301 Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
302 **/
303 typedef
304 EFI_STATUS
305 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE) (
306 IN EFI_USBFN_IO_PROTOCOL *This,
307 IN EFI_USB_ENDPOINT_TYPE EndpointType,
308 IN EFI_USB_BUS_SPEED BusSpeed,
309 OUT UINT16 *MaxPacketSize
310 );
311
312 /**
313 Returns the maximum supported transfer size.
314 **/
315 typedef
316 EFI_STATUS
317 (EFIAPI * EFI_USBFN_IO_GET_MAXTRANSFER_SIZE) (
318 IN EFI_USBFN_IO_PROTOCOL *This,
319 OUT UINTN *MaxTransferSize
320 );
321
322 /**
323 Returns device specific information based on the supplied identifier as a
324 Unicode string.
325 **/
326 typedef
327 EFI_STATUS
328 (EFIAPI * EFI_USBFN_IO_GET_DEVICE_INFO) (
329 IN EFI_USBFN_IO_PROTOCOL *This,
330 IN EFI_USBFN_DEVICE_INFO_ID Id,
331 IN OUT UINTN *BufferSize,
332 OUT VOID *Buffer OPTIONAL
333 );
334
335 /**
336 Returns vendor-id and product-id of the device.
337 **/
338 typedef
339 EFI_STATUS
340 (EFIAPI * EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID) (
341 IN EFI_USBFN_IO_PROTOCOL *This,
342 OUT UINT16 *Vid,
343 OUT UINT16 *Pid
344 );
345
346 /**
347 Aborts transfer on the specified endpoint.
348 **/
349 typedef
350 EFI_STATUS
351 (EFIAPI * EFI_USBFN_IO_ABORT_TRANSFER) (
352 IN EFI_USBFN_IO_PROTOCOL *This,
353 IN UINT8 EndpointIndex,
354 IN EFI_USBFN_ENDPOINT_DIRECTION Direction
355 );
356
357 /**
358 Returns the stall state on the specified endpoint.
359 **/
360 typedef
361 EFI_STATUS
362 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE) (
363 IN EFI_USBFN_IO_PROTOCOL *This,
364 IN UINT8 EndpointIndex,
365 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
366 IN OUT BOOLEAN *State
367 );
368
369 /**
370 Sets or clears the stall state on the specified endpoint.
371 **/
372 typedef
373 EFI_STATUS
374 (EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE) (
375 IN EFI_USBFN_IO_PROTOCOL *This,
376 IN UINT8 EndpointIndex,
377 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
378 IN BOOLEAN State
379 );
380
381
382 /**
383 This function is called repeatedly to receive updates on USB bus states,
384 receive, transmit status changes on endpoints and setup packet on endpoint 0.
385 **/
386 typedef
387 EFI_STATUS
388 (EFIAPI * EFI_USBFN_IO_EVENTHANDLER) (
389 IN EFI_USBFN_IO_PROTOCOL *This,
390 OUT EFI_USBFN_MESSAGE *Message,
391 IN OUT UINTN *PayloadSize,
392 OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload
393 );
394
395 /**
396 Primary function to handle transfer in either direction based on specified
397 direction and on the specified endpoint.
398 **/
399 typedef
400 EFI_STATUS
401 (EFIAPI *EFI_USBFN_IO_TRANSFER) (
402 IN EFI_USBFN_IO_PROTOCOL *This,
403 IN UINT8 EndpointIndex,
404 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
405 IN OUT UINTN *BufferSize,
406 IN OUT VOID *Buffer
407 );
408
409 /**
410 This function supplies power to the USB controller if needed,
411 initialize hardware and internal data structures, and then return.
412
413 The port must not be activated by this function.
414 **/
415 typedef
416 EFI_STATUS
417 (EFIAPI * EFI_USBFN_IO_START_CONTROLLER) (
418 IN EFI_USBFN_IO_PROTOCOL *This
419 );
420
421 /**
422 This function disables the hardware device by resetting the run/stop bit and
423 power off the USB controller if needed.
424 **/
425 typedef
426 EFI_STATUS
427 (EFIAPI * EFI_USBFN_IO_STOP_CONTROLLER) (
428 IN EFI_USBFN_IO_PROTOCOL *This
429 );
430
431 /**
432 This function sets the configuration policy for the specified non-control endpoint.
433
434 Refer to the description for calling restrictions.
435 **/
436 typedef
437 EFI_STATUS
438 (EFIAPI * EFI_USBFN_IO_SET_ENDPOINT_POLICY) (
439 IN EFI_USBFN_IO_PROTOCOL *This,
440 IN UINT8 EndpointIndex,
441 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
442 IN EFI_USBFN_POLICY_TYPE PolicyType,
443 IN UINTN BufferSize,
444 IN VOID *Buffer
445 );
446
447 /**
448 This function retrieves the configuration policy for the specified non-control endpoint.
449
450 There are no associated calling restrictions for this function.
451 **/
452 typedef
453 EFI_STATUS
454 (EFIAPI * EFI_USBFN_IO_GET_ENDPOINT_POLICY) (
455 IN EFI_USBFN_IO_PROTOCOL *This,
456 IN UINT8 EndpointIndex,
457 IN EFI_USBFN_ENDPOINT_DIRECTION Direction,
458 IN EFI_USBFN_POLICY_TYPE PolicyType,
459 IN OUT UINTN *BufferSize,
460 IN OUT VOID *Buffer
461 );
462
463 /**
464 This function configures endpoints based on supplied list of device and configuration descriptors.
465
466 There are no associated calling restrictions for this function.
467 **/
468 typedef
469 EFI_STATUS
470 (EFIAPI * EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX) (
471 IN EFI_USBFN_IO_PROTOCOL *This,
472 IN EFI_USB_DEVICE_INFO *DeviceInfo,
473 IN EFI_USB_SUPERSPEED_DEVICE_INFO *SSDeviceInfo
474 );
475
476
477 struct _EFI_USBFN_IO_PROTOCOL {
478 UINT32 Revision;
479 EFI_USBFN_IO_DETECT_PORT DetectPort;
480 EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS ConfigureEnableEndpoints;
481 EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE GetEndpointMaxPacketSize;
482 EFI_USBFN_IO_GET_DEVICE_INFO GetDeviceInfo;
483 EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID GetVendorIdProductId;
484 EFI_USBFN_IO_ABORT_TRANSFER AbortTransfer;
485 EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE GetEndpointStallState;
486 EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE SetEndpointStallState;
487 EFI_USBFN_IO_EVENTHANDLER EventHandler;
488 EFI_USBFN_IO_TRANSFER Transfer;
489 EFI_USBFN_IO_GET_MAXTRANSFER_SIZE GetMaxTransferSize;
490 EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER AllocateTransferBuffer;
491 EFI_USBFN_IO_FREE_TRANSFER_BUFFER FreeTransferBuffer;
492
493 /// Valid for version EFI_USBFN_IO_PROTOCOL_REVISION2 and above
494 EFI_USBFN_IO_START_CONTROLLER StartController;
495 EFI_USBFN_IO_STOP_CONTROLLER StopController;
496 EFI_USBFN_IO_SET_ENDPOINT_POLICY SetEndpointPolicy;
497 EFI_USBFN_IO_GET_ENDPOINT_POLICY GetEndpointPolicy;
498 EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX ConfigureEnableEndpointsEx;
499 };
500
501
502 extern EFI_GUID gUsbFnIoProtocolGuid;
503 #endif
EFI_USBFN_IO_GET_ENDPOINT_POLICY
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_POLICY)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
This function retrieves the configuration policy for the specified non-control endpoint.
Definition: EfiUsbFnIo.h:454
EFI_USBFN_IO_FREE_TRANSFER_BUFFER
EFI_STATUS(* EFI_USBFN_IO_FREE_TRANSFER_BUFFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN VOID *Buffer)
Deallocates the memory allocated for the transfer buffer by AllocateTransferBuffer function.
Definition: EfiUsbFnIo.h:273
EFI_USBFN_IO_GET_DEVICE_INFO
EFI_STATUS(* EFI_USBFN_IO_GET_DEVICE_INFO)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USBFN_DEVICE_INFO_ID Id, IN OUT UINTN *BufferSize, OUT VOID *Buffer OPTIONAL)
Returns device specific information based on the supplied identifier as a Unicode string.
Definition: EfiUsbFnIo.h:328
EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS
EFI_STATUS(* EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo)
Configure endpoints based on supplied device and configuration descriptors.
Definition: EfiUsbFnIo.h:294
EFI_USBFN_IO_DETECT_PORT
EFI_STATUS(* EFI_USBFN_IO_DETECT_PORT)(IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_PORT_TYPE *PortType)
Returns information about what type of device was attached.
Definition: EfiUsbFnIo.h:284
EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID
EFI_STATUS(* EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID)(IN EFI_USBFN_IO_PROTOCOL *This, OUT UINT16 *Vid, OUT UINT16 *Pid)
Returns vendor-id and product-id of the device.
Definition: EfiUsbFnIo.h:340
EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE
EFI_STATUS(* EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN BOOLEAN State)
Sets or clears the stall state on the specified endpoint.
Definition: EfiUsbFnIo.h:374
EFI_USBFN_IO_GET_MAXTRANSFER_SIZE
EFI_STATUS(* EFI_USBFN_IO_GET_MAXTRANSFER_SIZE)(IN EFI_USBFN_IO_PROTOCOL *This, OUT UINTN *MaxTransferSize)
Returns the maximum supported transfer size.
Definition: EfiUsbFnIo.h:317
EFI_USBFN_IO_ABORT_TRANSFER
EFI_STATUS(* EFI_USBFN_IO_ABORT_TRANSFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction)
Aborts transfer on the specified endpoint.
Definition: EfiUsbFnIo.h:351
EFI_USBFN_IO_TRANSFER
EFI_STATUS(* EFI_USBFN_IO_TRANSFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT UINTN *BufferSize, IN OUT VOID *Buffer)
Primary function to handle transfer in either direction based on specified direction and on the speci...
Definition: EfiUsbFnIo.h:401
EFI_USB_INTERFACE_INFO
USB_DEVICE_DESCRIPTOR, USB_CONFIG_DESCRIPTOR, USB_INTERFACE_DESCRIPTOR, and USB_ENDPOINT_DESCRIPTOR a...
Definition: EfiUsbFnIo.h:75
EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_ENDPOINT_TYPE EndpointType, IN EFI_USB_BUS_SPEED BusSpeed, OUT UINT16 *MaxPacketSize)
Returns the maximum packet size of the specified endpoint type for the supplied bus speed.
Definition: EfiUsbFnIo.h:305
EFI_USBFN_IO_EVENTHANDLER
EFI_STATUS(* EFI_USBFN_IO_EVENTHANDLER)(IN EFI_USBFN_IO_PROTOCOL *This, OUT EFI_USBFN_MESSAGE *Message, IN OUT UINTN *PayloadSize, OUT EFI_USBFN_MESSAGE_PAYLOAD *Payload)
This function is called repeatedly to receive updates on USB bus states, receive, transmit status cha...
Definition: EfiUsbFnIo.h:388
EFI_USBFN_IO_START_CONTROLLER
EFI_STATUS(* EFI_USBFN_IO_START_CONTROLLER)(IN EFI_USBFN_IO_PROTOCOL *This)
This function supplies power to the USB controller if needed, initialize hardware and internal data s...
Definition: EfiUsbFnIo.h:417
EFI_USBFN_IO_SET_ENDPOINT_POLICY
EFI_STATUS(* EFI_USBFN_IO_SET_ENDPOINT_POLICY)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN EFI_USBFN_POLICY_TYPE PolicyType, IN UINTN BufferSize, IN VOID *Buffer)
This function sets the configuration policy for the specified non-control endpoint.
Definition: EfiUsbFnIo.h:438
EFI_USBFN_IO_STOP_CONTROLLER
EFI_STATUS(* EFI_USBFN_IO_STOP_CONTROLLER)(IN EFI_USBFN_IO_PROTOCOL *This)
This function disables the hardware device by resetting the run/stop bit and power off the USB contro...
Definition: EfiUsbFnIo.h:427
EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX
EFI_STATUS(* EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX)(IN EFI_USBFN_IO_PROTOCOL *This, IN EFI_USB_DEVICE_INFO *DeviceInfo, IN EFI_USB_SUPERSPEED_DEVICE_INFO *SSDeviceInfo)
This function configures endpoints based on supplied list of device and configuration descriptors.
Definition: EfiUsbFnIo.h:470
EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER
EFI_STATUS(* EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINTN Size, OUT VOID **Buffer)
Allocates transfer buffer of the specified size that satisfies controller requirements.
Definition: EfiUsbFnIo.h:260
EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE
EFI_STATUS(* EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE)(IN EFI_USBFN_IO_PROTOCOL *This, IN UINT8 EndpointIndex, IN EFI_USBFN_ENDPOINT_DIRECTION Direction, IN OUT BOOLEAN *State)
Returns the stall state on the specified endpoint.
Definition: EfiUsbFnIo.h:362
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: FastBootDataDef.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootDataDef.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file FastBootDataDef.h.


AlderLake Platform Sample Code: FastBootDataDef.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootDataDef.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __FAST_BOOT_DATA_DEF_H__
35 #define __FAST_BOOT_DATA_DEF_H__
36
37 #define FAST_BOOT_WDT_RESET_SIGNATURE 0xFB
38
39 typedef enum {
40 NoException = 0,
41 ExceptionType1,
42 ExceptionType2,
43 ExceptionType3A,
44 ExceptionType3B,
45 ExceptionTypeMax
46 } FAST_BOOT_EXCEPTION_TYPE;
47
48 typedef enum {
49 NoExceptionCategory = 0,
50 FastBootDisabled,
51 FastBootOverridden,
52 FastBootBreakByUser,
53 FirstBoot,
54 BootFailure,
55 FirmwareUpdate,
56 HardwareChanged,
57 SetupConfigurationChanged,
58 ConsoleDeviceChanged,
59 BootDeviceChanged,
60 ContentLost,
61 PowerFailure,
62 HardwareError,
63 SpecialBoot,
64 AnyOfOtherCategories,
65 ExceptionCategoryMax
66 } FAST_BOOT_EXCEPTION_CATEGORY;
67
68 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: FastBootException.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
FastBootException.h File Reference
#include <FastBootDataDef.h>
Include dependency graph for FastBootException.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file FastBootException.h.


AlderLake Platform Sample Code: FastBootException.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
FastBootException.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __FAST_BOOT_EXCEPTION_H__
35 #define __FAST_BOOT_EXCEPTION_H__
36
37 #include <FastBootDataDef.h>
38
39 //
40 // Forward reference for pure ANSI compatability
41 //
42
43 typedef struct _FAST_BOOT_EXCEPTION_PROTOCOL {
44 FAST_BOOT_EXCEPTION_TYPE FbExceptionType;
45 FAST_BOOT_EXCEPTION_CATEGORY FbExceptionCategory;
46 } FAST_BOOT_EXCEPTION_PROTOCOL;
47
48 #endif
FastBootDataDef.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: FastBootExceptionInfoHob.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootExceptionInfoHob.h File Reference
#include <Pi/PiHob.h>
#include <FastBootDataDef.h>
Include dependency graph for FastBootExceptionInfoHob.h:
This graph shows which files directly or indirectly include this file:

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Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file FastBootExceptionInfoHob.h.


AlderLake Platform Sample Code: FastBootExceptionInfoHob.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootExceptionInfoHob.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32
33 **/
34
35 #ifndef __FAST_BOOT_EXCEPTION_INFO_HOB_H__
36 #define __FAST_BOOT_EXCEPTION_INFO_HOB_H__
37
38 #include <Pi/PiHob.h>
39 #include <FastBootDataDef.h>
40
41 typedef struct _FAST_BOOT_EXCEPTION_INFO_HOB {
42 EFI_HOB_GUID_TYPE Header;
43 EFI_GUID GuidName;
44 FAST_BOOT_EXCEPTION_TYPE FbExceptionType;
45 FAST_BOOT_EXCEPTION_CATEGORY FbExceptionCategory;
46 } FAST_BOOT_EXCEPTION_INFO_HOB;
47
48 #endif // __FAST_BOOT_EXCEPTION_INFO_HOB_H__
FastBootDataDef.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: FastBootFunctionEnabledHob.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootFunctionEnabledHob.h File Reference

This file defines the HOB data structure to indicate that Fast Boot function is enabled in PEI phase, which may be used by some DXE phase drivers as well. More...

#include <Pi/PiHob.h>
Include dependency graph for FastBootFunctionEnabledHob.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This file defines the HOB data structure to indicate that Fast Boot function is enabled in PEI phase, which may be used by some DXE phase drivers as well.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file FastBootFunctionEnabledHob.h.


AlderLake Platform Sample Code: FastBootFunctionEnabledHob.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FastBootFunctionEnabledHob.h
Go to the documentation of this file.
1 /** @file
2 This file defines the HOB data structure to indicate that Fast Boot function
3 is enabled in PEI phase, which may be used by some DXE phase drivers as well.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains 'Framework Code' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may not be
31 modified, except as allowed by additional terms of your license agreement.
32
33 @par Specification Reference:
34
35 **/
36
37 #ifndef _FAST_BOOT_FUNCTION_ENABLED_HOB_H_
38 #define _FAST_BOOT_FUNCTION_ENABLED_HOB_H_
39
40 #include <Pi/PiHob.h>
41
42 typedef struct _FAST_BOOT_FUNCTION_ENABLED_HOB {
43 EFI_HOB_GUID_TYPE Header;
44 BOOLEAN FastBootEnabled;
45 } FAST_BOOT_FUNCTION_ENABLED_HOB;
46
47 #endif // _FAST_BOOT_FUNCTION_ENABLED_HOB_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: FirwmareConfigurations.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FirwmareConfigurations.h File Reference

This header file provides definitions of firmware configuration. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This header file provides definitions of firmware configuration.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file FirwmareConfigurations.h.


AlderLake Platform Sample Code: FirwmareConfigurations.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
FirwmareConfigurations.h
Go to the documentation of this file.
1 /** @file
2 This header file provides definitions of firmware configuration.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _FIRMWARE_CONFIGURATION_H_
36 #define _FIRMWARE_CONFIGURATION_H_
37
38 typedef enum {
39 FwConfigDefault = 0,
40 FwConfigProduction,
41 FwConfigTest,
42 FwConfigMax
43 } FW_CONFIG;
44
45 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: GfxInt15Interface.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
Functions
GfxInt15Interface.c File Reference

This is a driver to produce Int15 hook. More...

#include "PlatformInitAdvancedDxe.h"
#include <Uefi/UefiBaseType.h>
#include <Protocol/FirmwareVolume2.h>
Include dependency graph for GfxInt15Interface.c:

Go to the source code of this file.

Functions

EFI_STATUS LoadRealModeFile (EFI_GUID *Guid, VOID **Buffer, UINTN *BufferSize)
Loads real mode file form the FV. More...

Detailed Description

This is a driver to produce Int15 hook.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GfxInt15Interface.c.

Function Documentation

◆ LoadRealModeFile()

EFI_STATUS LoadRealModeFile | ( | EFI_GUID * | Guid,
 |  | VOID ** | Buffer,
 |  | UINTN * | BufferSize
 | ) |  |

Loads real mode file form the FV.

Parameters
[in] | Guid
[in] | Buffer
[in] | BufferSize
Return values
EFI_SUCCESS Function has completed successfully.

Definition at line 53 of file GfxInt15Interface.c.


AlderLake Platform Sample Code: GfxInt15Interface.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
GfxInt15Interface.c
Go to the documentation of this file.
1 /** @file
2 This is a driver to produce Int15 hook.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 //
36 // Module specific Includes
37 //
38 #include "PlatformInitAdvancedDxe.h"
39 #include <Uefi/UefiBaseType.h>
40 #include <Protocol/FirmwareVolume2.h>
41
42
43 /**
44 Loads real mode file form the FV
45
46 @param[in] Guid
47 @param[in] Buffer
48 @param[in] BufferSize
49
50 @retval EFI_SUCCESS Function has completed successfully.
51 **/
52 EFI_STATUS
53 LoadRealModeFile (
54 EFI_GUID *Guid,
55 VOID **Buffer,
56 UINTN *BufferSize
57 )
58 {
59 EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
60 UINT32 Authentication;
61 EFI_STATUS Status;
62 UINTN NumHandles;
63 EFI_HANDLE *HandleBuffer;
64 UINTN Index;
65
66 *Buffer = NULL;
67 *BufferSize = 0;
68 Fv = NULL;
69
70 Status = gBS->LocateHandleBuffer (
71 ByProtocol,
72 &gEfiFirmwareVolume2ProtocolGuid,
73 NULL,
74 &NumHandles,
75 &HandleBuffer
76 );
77 if (EFI_ERROR(Status)) return Status;
78
79 for (Index = 0; Index < NumHandles; ++Index) {
80 Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiFirmwareVolume2ProtocolGuid, (VOID **) &Fv);
81 if (EFI_ERROR(Status)) continue;
82
83 Status = Fv->ReadSection(Fv,
84 Guid,
85 EFI_SECTION_RAW,
86 0, //Instance
87 Buffer,
88 BufferSize,
89 &Authentication);
90
91 if (Status == EFI_SUCCESS) break;
92 }
93
94 (gBS->FreePool)(HandleBuffer);
95 return Status;
96 }
97
PlatformInitAdvancedDxe.h
Header file for Platform Init Advanced Dxe Driver.
LoadRealModeFile
EFI_STATUS LoadRealModeFile(EFI_GUID *Guid, VOID **Buffer, UINTN *BufferSize)
Loads real mode file form the FV.
Definition: GfxInt15Interface.c:53
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: GopPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
GopPolicyInitDxe.c File Reference

This file initialises and Installs GopPolicy Protocol. More...

#include "GopPolicyInitDxe.h"
#include <Protocol/GopPolicy.h>
Include dependency graph for GopPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | GetPlatformLidStatus (OUT LID_STATUS *CurrentLidStatus)
EFI_STATUS | GetPlatformDockStatus (OUT DOCK_STATUS *CurrentDockStatus)
EFI_STATUS | GetVbtData (OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
EFI_STATUS | GopPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy. More...

Detailed Description

This file initialises and Installs GopPolicy Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GopPolicyInitDxe.c.

Function Documentation

◆ GetPlatformDockStatus()

EFI_STATUS GetPlatformDockStatus ( OUT DOCK_STATUS * CurrentDockStatus )
Parameters
[out] CurrentDockStatus
Return values
EFI_SUCCESS
EFI_UNSUPPORTED

Definition at line 97 of file GopPolicyInitDxe.c.

◆ GetPlatformLidStatus()

EFI_STATUS GetPlatformLidStatus ( OUT LID_STATUS * CurrentLidStatus )
Parameters
[out] CurrentLidStatus
Return values
EFI_SUCCESS
EFI_UNSUPPORTED

Definition at line 55 of file GopPolicyInitDxe.c.

◆ GetVbtData()

EFI_STATUS GetVbtData | ( | OUT EFI_PHYSICAL_ADDRESS * | VbtAddress,
 |  | OUT UINT32 * | VbtSize
 | ) |  |
Parameters
[out] | VbtAddress
[out] | VbtSize
Return values
EFI_SUCCESS
EFI_NOT_FOUND

Definition at line 115 of file GopPolicyInitDxe.c.

◆ GopPolicyInitDxe()

EFI_STATUS GopPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize GOP DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 219 of file GopPolicyInitDxe.c.


AlderLake Platform Sample Code: GopPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
GopPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file initialises and Installs GopPolicy Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include "GopPolicyInitDxe.h"
36 #include <Protocol/GopPolicy.h>
37
38 GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;
39 GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize = 0;
40 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress = 0;
41
42 //
43 // Function implementations
44 //
45
46 /**
47
48 @param[out] CurrentLidStatus
49
50 @retval EFI_SUCCESS
51 @retval EFI_UNSUPPORTED
52 **/
53 EFI_STATUS
54 EFIAPI
55 GetPlatformLidStatus (
56 OUT LID_STATUS *CurrentLidStatus
57 )
58 {
59 EFI_STATUS Status;
60 UINT8 PortDataOut;
61 UINT8 DataBuffer[1];
62
63 //
64 // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
65 //
66 if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
67 DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
68 return EFI_UNSUPPORTED;
69 }
70
71
72 if (PcdGetBool (PcdEcPresent)) {
73 DataBuffer[0] = EC_D_LID_STATE;
74 Status = ReadEcRam (DataBuffer);
75 if (Status == EFI_SUCCESS) {
76 PortDataOut = DataBuffer[0];
77 if ((PortDataOut & EC_B_LID_STATUS_OPEN) == EC_B_LID_STATUS_OPEN) {
78 *CurrentLidStatus = LidOpen;
79 } else {
80 *CurrentLidStatus = LidClosed;
81 }
82 return EFI_SUCCESS;
83 }
84 }
85
86 return EFI_UNSUPPORTED;
87 }
88 /**
89
90 @param[out] CurrentDockStatus
91
92 @retval EFI_SUCCESS
93 @retval EFI_UNSUPPORTED
94 **/
95 EFI_STATUS
96 EFIAPI
97 GetPlatformDockStatus (
98 OUT DOCK_STATUS *CurrentDockStatus
99 )
100 {
101 return EFI_UNSUPPORTED;
102 }
103
104
105 /**
106
107 @param[out] VbtAddress
108 @param[out] VbtSize
109
110 @retval EFI_SUCCESS
111 @retval EFI_NOT_FOUND
112 **/
113 EFI_STATUS
114 EFIAPI
115 GetVbtData (
116 OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
117 OUT UINT32 *VbtSize
118 )
119 {
120 EFI_GUID BmpImageGuid;
121 EFI_STATUS Status;
122 UINTN FvProtocolCount;
123 EFI_HANDLE *FvHandles;
124 EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
125 UINTN Index;
126 UINT32 AuthenticationStatus;
127 UINT8 *Buffer;
128 UINTN VbtBufferSize;
129 UINTN VariableSize;
130 SA_SETUP SaSetup;
131
132
133 Status = EFI_NOT_FOUND;
134 if (mVbtAddress == 0) {
135 Fv = NULL;
136 VariableSize = sizeof (SA_SETUP);
137 //
138 // Get setup variable
139 //
140 Status = gRT->GetVariable (
141 L"SaSetup",
142 &gSaSetupVariableGuid,
143 NULL,
144 &VariableSize,
145 &SaSetup
146 );
147 ASSERT_EFI_ERROR(Status);
148
149 if (SaSetup.VbtSelect == VBT_SELECT_MIPI) {
150 CopyMem (&BmpImageGuid, PcdGetPtr (PcdVbtMipiGuid), sizeof (BmpImageGuid));
151 } else {
152 CopyMem (&BmpImageGuid, PcdGetPtr (PcdIntelGraphicsVbtFileGuid), sizeof (BmpImageGuid));
153 }
154 Buffer = 0;
155 FvHandles = NULL;
156 Status = gBS->LocateHandleBuffer (
157 ByProtocol,
158 &gEfiFirmwareVolume2ProtocolGuid,
159 NULL,
160 &FvProtocolCount,
161 &FvHandles
162 );
163 if (!EFI_ERROR (Status)) {
164 for (Index = 0; Index < FvProtocolCount; Index++) {
165 Status = gBS->HandleProtocol (
166 FvHandles[Index],
167 &gEfiFirmwareVolume2ProtocolGuid,
168 (VOID **) &Fv
169 );
170 VbtBufferSize = 0;
171 Status = Fv->ReadSection (
172 Fv,
173 &BmpImageGuid,
174 EFI_SECTION_RAW,
175 0,
176 (VOID **) &Buffer,
177 &VbtBufferSize,
178 &AuthenticationStatus
179 );
180 if (!EFI_ERROR (Status)) {
181 *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer;
182 *VbtSize = (UINT32)VbtBufferSize;
183 mVbtAddress = *VbtAddress;
184 mVbtSize = *VbtSize;
185 Status = EFI_SUCCESS;
186 break;
187 }
188 }
189 } else {
190 Status = EFI_NOT_FOUND;
191 }
192
193 if (FvHandles != NULL) {
194 FreePool (FvHandles);
195 FvHandles = NULL;
196 }
197 } else {
198 *VbtAddress = mVbtAddress;
199 *VbtSize = mVbtSize;
200 Status = EFI_SUCCESS;
201 }
202
203 return Status;
204 }
205
206 /**
207 Initialize GOP DXE Policy
208
209 @param[in] ImageHandle Image handle of this driver.
210
211 @retval EFI_SUCCESS Initialization complete.
212 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
213 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
214 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
215 **/
216
217 EFI_STATUS
218 EFIAPI
219 GopPolicyInitDxe (
220 IN EFI_HANDLE ImageHandle
221 )
222 {
223 EFI_STATUS Status;
224
225 //
226 // Initialize the EFI Driver Library
227 //
228 SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);
229
230 mGOPPolicy.Revision = GOP_POLICY_PROTOCOL_REVISION_03;
231 mGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus;
232 mGOPPolicy.GetVbtData = GetVbtData;
233 mGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus;
234
235 //
236 // Install protocol to allow access to this Policy.
237 //
238 Status = gBS->InstallMultipleProtocolInterfaces (
239 &ImageHandle,
240 &gGopPolicyProtocolGuid,
241 &mGOPPolicy,
242 NULL
243 );
244
245 return Status;
246 }
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:219
GetPlatformLidStatus
EFI_STATUS GetPlatformLidStatus(OUT LID_STATUS *CurrentLidStatus)
Definition: GopPolicyInitDxe.c:55
GetPlatformDockStatus
EFI_STATUS GetPlatformDockStatus(OUT DOCK_STATUS *CurrentDockStatus)
Definition: GopPolicyInitDxe.c:97
GetVbtData
EFI_STATUS GetVbtData(OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
Definition: GopPolicyInitDxe.c:115
ReadEcRam
EFI_STATUS ReadEcRam(IN OUT UINT8 *DataBuffer)
Read data from EC RAM.
GopPolicyInitDxe.h
Header file for the GopPolicyInitDxe Driver.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: GopPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
GopPolicyInitDxe.h File Reference

Header file for the GopPolicyInitDxe Driver. More...

#include <Protocol/FirmwareVolume2.h>
#include <SetupVariable.h>
#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/EcMiscLib.h>
#include <PlatformBoardId.h>
#include <Library/PcdLib.h>
Include dependency graph for GopPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS GopPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy. More...

Detailed Description

Header file for the GopPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file GopPolicyInitDxe.h.

Function Documentation

◆ GopPolicyInitDxe()

EFI_STATUS GopPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize GOP DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 219 of file GopPolicyInitDxe.c.


AlderLake Platform Sample Code: GopPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
GopPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the GopPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _GOP_POLICY_INIT_DXE_H_
35 #define _GOP_POLICY_INIT_DXE_H_
36
37 #include <Protocol/FirmwareVolume2.h>
38 #include <SetupVariable.h>
39 #include <Library/UefiLib.h>
40 #include <Library/BaseLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Library/DxeServicesTableLib.h>
43 #include <Library/UefiBootServicesTableLib.h>
44 #include <Library/UefiRuntimeServicesTableLib.h>
45 #include <Library/BaseMemoryLib.h>
46 #include <Library/DebugLib.h>
47 #include <Library/EcMiscLib.h>
48 #include <PlatformBoardId.h>
49 #include <Library/PcdLib.h>
50
51 /**
52 Initialize GOP DXE Policy
53
54 @param[in] ImageHandle Image handle of this driver.
55
56 @retval EFI_SUCCESS Initialization complete.
57 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
58 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
59 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
60 **/
61 EFI_STATUS
62 EFIAPI
63 GopPolicyInitDxe (
64 IN EFI_HANDLE ImageHandle
65 );
66
67 #endif
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:219
EcMiscLib.h
EC miscellaneous library functions.
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: HidI2cPlatformSupportLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
HidI2cPlatformSupportLib.h File Reference

Support for IO expander TCA6424. More...

#include <Uefi.h>
Include dependency graph for HidI2cPlatformSupportLib.h:

Go to the source code of this file.

Detailed Description

Support for IO expander TCA6424.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file HidI2cPlatformSupportLib.h.


AlderLake Platform Sample Code: HidI2cPlatformSupportLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
HidI2cPlatformSupportLib.h
Go to the documentation of this file.
1 /** @file
2 Support for IO expander TCA6424.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Uefi.h>
36
37 //
38 // There's no decision yet if the 3 functions below should be a lib or protocol
39 //
40
41 EFI_STATUS EFIAPI HidI2cInitialize ( IN EFI_HANDLE Handle);
42 BOOLEAN EFIAPI HidI2cCheckInterrupt ( IN EFI_HANDLE Handle);
43 UINT16 EFIAPI HidI2cGetHidRegisterAddress ( IN EFI_HANDLE Handle);
44
45 typedef
46 UINT16
47 (EFIAPI *HID_I2C_GET_HID_REGISTER_ADDRESS)(
48 IN EFI_HANDLE Device
49 );
50 typedef
51 BOOLEAN
52 (EFIAPI *HID_I2C_CHECK_INTERRUPT)(
53 IN EFI_HANDLE Device
54 );
55 typedef
56 EFI_STATUS
57 (EFIAPI *HID_I2C_INITIALIZE)(
58 IN EFI_HANDLE Device
59 );
60
61 typedef struct {
62 HID_I2C_GET_HID_REGISTER_ADDRESS GetHidRegisterAddress;
63 HID_I2C_CHECK_INTERRUPT CheckInterrupt;
64 HID_I2C_INITIALIZE Initialize;
65 } HID_I2C_PLATFORM_SUPPORT;
66
67
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: HstiFeatureBit_1_1a.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
HstiFeatureBit_1_1a.h File Reference

This file contains various definitions for IHV HSTI implementation including STATUS string definitions. More...

Go to the source code of this file.

Detailed Description

This file contains various definitions for IHV HSTI implementation including STATUS string definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification

Definition in file HstiFeatureBit_1_1a.h.


AlderLake Platform Sample Code: HstiFeatureBit_1_1a.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
HstiFeatureBit_1_1a.h
Go to the documentation of this file.
1 /** @file
2 This file contains various definitions for IHV HSTI implementation
3 including STATUS string definitions
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains 'Framework Code' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may not be
31 modified, except as allowed by additional terms of your license agreement.
32
33 @par Specification
34 **/
35
36 #ifndef __HSTI_FEATURE_BIT_1_1A_H__
37 #define __HSTI_FEATURE_BIT_1_1A_H__
38
39 #define HSTI_SECURITY_FEATURE_SIZE 3
40
41 typedef enum {
42 P2sbEpMask5RemAccMaskBits29To26UnexpSts = BIT0,
43 P2sbEpMask7RemAccMaskBits31To30UnexpSts = BIT1,
44 P2sbLockMaskBitUnexpSts = BIT2
45 } SMM_HSTI_UNEXP_STATUS_DATA;
46
47 #define HSTI_STATUS L" Status "
48 #define HSTI_UNEXP_STATUS L" Unexpected Status "
49 #define HSTI_PLATFORM_SECURITY_SPECIFICATION L" Platform Security Specification"
50 #define HSTI_BOOTGUARD_CONFIGURATION L" - Boot Guard Configuration -"
51 #define HSTI_SPI_FLASH_CONFIGURATION L" - SPI Flash Configuration -"
52 #define HSTI_PCH_SECURITY_CONFIGURATION L" - PCH Security Configuration -"
53 #define HSTI_BIOS_GUARD_SECURITY_CONFIGURATION L" - BIOS Guard Security Configuration -"
54 #define HSTI_MEASURED_BOOT_CONFIGURATION L" - Measured Boot Configuration -"
55 #define HSTI_INTEGRATED_DEVICE_DMA_PROTECTION L" - Integrated Device DMA Protection -"
56 #define HSTI_DEBUG_INTERFACE_SECURITY_CONFIGURATION L" - Debug Interface Security Configuration -"
57 #define HSTI_CPU_SECURITY_CONFIGURATION L" - CPU Security Configuration -"
58 #define HSTI_MEMORY_MAP_SECURITY_CONFIGURATION L" - Memory Map Security Configuration -"
59 #define HSTI_PROCESSOR_GRAPHICS_SECURITY_CONFIGURATION L" - Processor Graphics Security Configuration -"
60 #define HSTI_PROCESSOR_SPD_SECURITY_CONFIGURATION L" - SPD Security Configuration -"
61 #define HSTI_PCH_SMM_SECURITY_CONFIGURATION L" - Secure PCH SMM Security Configuration - "
62
63 #define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY BIT0
64 #define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_UNEXP_STATUS_CODE_1 L"0x00000001"
65 #define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_UNEXP_STATUS_STRING_1 L" Boot Guard configured without Verified Boot\r\n"
66 #define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_UNEXP_STATUS_CODE_2 L"0x00000002"
67 #define HSTI_BYTE0_HARDWARE_ROOTED_BOOT_INTEGRITY_UNEXP_STATUS_STRING_2 L" Boot Guard disabled\r\n"
68
69 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION BIT1
70 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_1 L"0x00010001"
71 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_1 L" SPI Flash not write protected\r\n"
72 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_2 L"0x00010002"
73 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_2 L" SPI Flash descriptor overridden\r\n"
74 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_3 L"0x00010003"
75 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_3 L" SPI Controller configuration unlocked\r\n"
76 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_4 L"0x00010004"
77 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_4 L" SPI Controller BIOS Interface unlocked\r\n"
78 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_5 L"0x00010005"
79 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_5 L" Top Swap enabled\r\n"
80 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_6 L"0x00010006"
81 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_6 L" SPI Vendor Specific Component Capabilities unlocked\r\n"
82 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_8 L"0x00010008"
83 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_8 L" ME FW not in Normal Working State\r\n"
84 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_9 L"0x00010009"
85 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_9 L" Flash Descriptor Invalid\r\n"
86 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_A L"0x0001000A"
87 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_A L" SPI Region Access Rights Invalid\r\n"
88 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_D L"0x0001000D"
89 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_D L" Global SMI not enabled and locked\r\n"
90 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_E L"0x0001000E"
91 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_E L" TCO SMI not enabled and locked\r\n"
92 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_F L"0x0001000F"
93 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_F L" Allowed WriteStatus SPI OPCODE configuration incorrect\r\n"
94 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_10 L"0x00010010"
95 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_10 L" Extended BIOS Decode Region is incorrectly Configured\r\n"
96 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_11 L"0x00010011"
97 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_11 L" Extended BIOS Decode Region limit is unlocked\r\n"
98 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_CODE_12 L"0x00010012"
99 #define HSTI_BYTE0_BOOT_FIRMWARE_MEDIA_PROTECTION_UNEXP_STATUS_STRING_12 L" Extended BIOS Decode Region base is unlocked\r\n"
100
101 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE BIT2
102 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_CODE_1 L"0x00020001"
103 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_STRING_1 L" BIOS Guard unsupported\r\n"
104 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_CODE_2 L"0x00020002"
105 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_STRING_2 L" BIOS Guard configuration unlocked\r\n"
106 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_CODE_3 L"0x00020001"
107 #define HSTI_BYTE0_SIGNED_FIRMWARE_UPDATE_UNEXP_STATUS_STRING_3 L" BIOS Guard disabled\r\n"
108
109 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT BIT3
110 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_1 L"0x00030001"
111 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_1 L" Chipset supports FW TPM, however no TPM enabled\r\n"
112 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_2 L"0x00030002"
113 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_2 L" PCR[7] is not initialized\r\n"
114 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_3 L"0x00030003"
115 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_3 L" Event Log is not published or invalid\r\n"
116 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_4 L"0x00030004"
117 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_4 L" Platform Auth accessible via 0x00000000\r\n"
118 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_5 L"0x00030005"
119 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_5 L" Unable to test Platform Auth accessible via 0x00000000 - Authorization Size = 0\r\n"
120 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_CODE_6 L"0x00030006"
121 #define HSTI_BYTE0_MEASURED_BOOT_ENFORCEMENT_UNEXP_STATUS_STRING_6 L" PCR(s) not found - no Event Log(s) published\r\n"
122
123 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION BIT4
124 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_1 L"0x00040001"
125 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_1 L" Bus Mastering Enabled for non-boot, integrated device - VTd Feature is not enabled in the CPU SKU\r\n"
126 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_2 L"0x00040002"
127 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_2 L" Bus Mastering Enabled for non-boot, integrated device - VTd1 is not enabled\r\n"
128 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_3 L"0x00040003"
129 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_3 L" Bus Mastering Enabled for non-boot, integrated device - VTd1 Region Address is not configured\r\n"
130 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_4 L"0x00040004"
131 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_4 L" Bus Mastering Enabled for non-boot, integrated device - VTd2 is not enabled\r\n"
132 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_5 L"0x00040005"
133 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_5 L" Bus Mastering Enabled for non-boot, integrated device - VTd2 Region Address is not configured\r\n"
134 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_6 L"0x00040006"
135 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_6 L" Bus Mastering Enabled for non-boot, integrated device - VTd3 is not enabled \r\n"
136 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_7 L"0x00040007"
137 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_7 L" Bus Mastering Enabled for non-boot, integrated device - VTd3 Region Address is not configured\r\n"
138 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_8 L"0x00040008"
139 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_8 L" Bus Mastering Enabled for non-boot, integrated device - VTd4 is not enabled \r\n"
140 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_9 L"0x00040009"
141 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_9 L" Bus Mastering Enabled for non-boot, integrated device - VTd4 Region Address is not configured\r\n"
142 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_A L"0x0004000A"
143 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_A L" Bus Mastering Enabled for non-boot, integrated device - VTd5 is not enabled\r\n"
144 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_B L"0x0004000B"
145 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_B L" Bus Mastering Enabled for non-boot, integrated device - VTd5 Region Address is not configured\r\n"
146 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_C L"0x0004000C"
147 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_C L" Bus Mastering Enabled for non-boot, integrated device - VTd6 is not enabled\r\n"
148 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_D L"0x0004000D"
149 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_D L" Bus Mastering Enabled for non-boot, integrated device - VTd6 Region Address is not configured\r\n"
150 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_12 L"0x00040012"
151 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_12 L" Bus Mastering Enabled for non-boot, integrated device - VTd9 is not enabled\r\n"
152 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_13 L"0x00040013"
153 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_13 L" Bus Mastering Enabled for non-boot, integrated device - VTd9 Region Address is not configured\r\n"
154 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_CODE_10 L"0x00040010"
155 #define HSTI_BYTE0_INTEGRATED_DEVICE_DMA_PROTECTION_UNEXP_STATUS_STRING_10 L" Bus Mastering Enabled for non-boot, integrated device - VTd Feature is enabled in the CPU SKU but disabled in the Platform\r\n"
156
157 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_CONFIGURATION BIT5
158 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_CODE_1 L"0x00050001"
159 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_STRING_1 L" Debug MSR enabled\r\n"
160 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_CODE_2 L"0x00050002"
161 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_STRING_2 L" Debug interface unlocked\r\n"
162 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_CODE_3 L"0x00050003"
163 #define HSTI_BYTE0_DEBUG_INTERFACE_SECURITY_UNEXP_STATUS_STRING_3 L" OPI Debug interface unlocked\r\n"
164
165 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION BIT6
166 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_1 L"0x00060001"
167 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_1 L" Minimum uCode patch revision not met\r\n"
168 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_2 L"0x00060002"
169 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_2 L" Pre-production silicon in use\r\n"
170 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_3 L"0x00060003"
171 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_3 L" VMX & Senter feature configuration unlocked\r\n"
172 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_4 L"0x00060004"
173 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_4 L" SMM Code Fetch feature configuration unlocked\r\n"
174 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_5 L"0x00060005"
175 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_5 L" AES-NI Feature configuration unlocked\r\n"
176 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_6 L"0x00060006"
177 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_6 L" FIT table not present\r\n"
178 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_7 L"0x00060007"
179 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_7 L" Microcode Range Registers improperly configured or unlocked\r\n"
180 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_8 L"0x00060008"
181 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_8 L" SMM Configuration Unlocked\r\n"
182 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_9 L"0x00060009"
183 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_9 L" TSEG not naturally aligned\r\n"
184 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_A L"0x0006000A"
185 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_A L" Improper SMRR configuration\r\n"
186 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_B L"0x0006000B"
187 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_B L" SMM Code Fetch outside SMRAM detection feature is disabled\r\n"
188 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_C L"0x0006000C"
189 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_C L" BIOS DONE MSR is not set\r\n"
190 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_D L"0x0006000D"
191 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_D L" Intel TXT configuration unlocked\r\n"
192 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_E L"0x0006000E"
193 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_E L" Processor Reserved Memory Range Register is Supported but Disabled\r\n"
194 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_F L"0x0006000F"
195 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_F L" Volume Management Device is Unlocked\r\n"
196 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_CODE_10 L"0x00060010"
197 #define HSTI_BYTE0_SECURE_CPU_CONFIGURATION_UNEXP_STATUS_STRING_10 L" TME bit is Unlocked\r\n"
198
199 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION BIT0
200 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_CODE_1 L"0x00080001"
201 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_STRING_1 L" Memory BAR configuration unlocked\r\n"
202 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_CODE_2 L"0x00080002"
203 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_STRING_2 L" Fixed MMIO regions overlap\r\n"
204 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_CODE_3 L"0x00080003"
205 #define HSTI_BYTE1_SECURE_MEMORY_MAP_CONFIGURATION_UNEXP_STATUS_STRING_3 L" Non lockable MMIO ranges overlap other critical regions\r\n"
206
207 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION BIT1
208 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_1 L"0x00090001"
209 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_1 L" Graphics configuration unlocked\r\n"
210 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_2 L"0x00090002"
211 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_2 L" Invalid Graphics Memory Alignment\r\n"
212 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_3 L"0x00090003"
213 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_3 L" Reserved Check failed\r\n"
214 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_4 L"0x00090004"
215 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_4 L" WOPCM BASE Consistency Check failed\r\n"
216 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_5 L"0x00090005"
217 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_5 L" DSM Consistency Check failed\r\n"
218 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_6 L"0x00090006"
219 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_6 L" GSM Consistency Check failed\r\n"
220 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_7 L"0x00090007"
221 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_7 L" GGC Consistency Check failed\r\n"
222 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_8 L"0x00090008"
223 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_8 L" TOLUD Consistency Check failed\r\n"
224 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_9 L"0x00090009"
225 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_9 L" TOUUD Consistency Check failed\r\n"
226 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_A L"0x0009000A"
227 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_A L" TSEG Consistency Check failed\r\n"
228 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_B L"0x0009000B"
229 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_B L" PAVP Lock bit is not Locked\r\n"
230 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_C L"0x0009000C"
231 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_C L" DSM Lock bit is not Locked\r\n"
232 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_D L"0x0009000D"
233 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_D L" GSM Lock bit is not Locked\r\n"
234 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_E L"0x0009000E"
235 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_E L" GGC Lock bit is not Locked\r\n"
236 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_F L"0x0009000F"
237 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_F L" TOLUD Lock bit is not Locked\r\n"
238 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_10 L"0x00090010"
239 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_10 L" TOUUD Lock bit is not Locked\r\n"
240 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_11 L"0x00090011"
241 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_11 L" TSEG Lock bit is not Locked\r\n"
242 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_12 L"0x00090012"
243 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_12 L" RC6 Lock bit is not Locked\r\n"
244 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_13 L"0x00090013"
245 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_13 L" DSM Valid bit is not set\r\n"
246 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_14 L"0x00090014"
247 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_14 L" GSM Valid bit is not set\r\n"
248 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_15 L"0x00090015"
249 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_15 L" WOPCM Range Valid bits are not set\r\n"
250 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_16 L"0x00090016"
251 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_16 L" RC6 Range Valid bits are not set\r\n"
252 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_CODE_17 L"0x00090017"
253 #define HSTI_BYTE1_SECURE_INTEGRATED_GRAPHICS_CONFIGURATION_UNEXP_STATUS_STRING_17 L" Doorbell Range Valid bits are not set\r\n"
254
255 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION BIT2
256 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_1 L"0x000A0001"
257 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_1 L" Thermal Configuration unlocked\r\n"
258 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_2 L"0x000A0002"
259 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_2 L" BAR's unlocked\r\n"
260 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_3 L"0x000A0003"
261 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_3 L" Reserved Check failure\r\n"
262 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_4 L"0x000A0004"
263 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_4 L" SPD not write protected\r\n"
264 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_5 L"0x000A0005"
265 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_5 L" ACS ECH Root Port is not Configured\r\n"
266 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_CODE_6 L"0x000A0006"
267 #define HSTI_BYTE1_SECURE_PCH_CONFIGURATION_UNEXP_STATUS_STRING_6 L" VR CONFIG Bit is Unlocked\r\n"
268 // HSTI IHV PCH P2SB SMM
269 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_CODE_1 L"0x000A0010"
270 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_STRING_1 L" P2SB EPMASK5 Remove Access Mask is not Configured\r\n"
271 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_CODE_2 L"0x000A0020"
272 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_STRING_2 L" P2SB EPMASK7 Remove Access Mask is not Configured\r\n"
273 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_CODE_3 L"0x000A0030"
274 #define HSTI_BYTE1_SECURE_PCH_SMM_CONFIGURATION_UNEXP_STATUS_STRING_3 L" P2SB Mask Bit is Unlocked\r\n"
275
276
277 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: HstiIbvFeatureBit.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
HstiIbvFeatureBit.h File Reference

This file contains various definitions for IHV HSTI implementation including error string definitions. More...

Go to the source code of this file.

Detailed Description

This file contains various definitions for IHV HSTI implementation including error string definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file HstiIbvFeatureBit.h.


AlderLake Platform Sample Code: HstiIbvFeatureBit.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
HstiIbvFeatureBit.h
Go to the documentation of this file.
1 /** @file
2 This file contains various definitions for IHV HSTI implementation
3 including error string definitions
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 **/
35
36 #ifndef __HSTI_FEATURE_BIT_H__
37 #define __HSTI_FEATURE_BIT_H__
38
39 #define HSTI_IMPLEMENTATION_ID_BROADWELL L"Intel(R) 9-Series v1"
40
41 #define HSTI_SECURITY_FEATURE_SIZE 3
42
43 #define HSTI_ERROR L"Error "
44 #define HSTI_PLATFORM_SECURITY_SPECIFICATION L" Platform Security Specification"
45
46 #define HSTI_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH L" - Firmware Trust Continuation Crypto Strength - "
47 #define HSTI_NO_TEST_KEY_VERIFICATION L" - No Test Key Verification - "
48 #define HSTI_FIRMWARE_VERSION_ROLLBACK_PROTECTION L" - Firmware Version Rollback Protection - "
49 #define HSTI_SECUREBOOT_BYPASS_CHECKING L" - SecureBoot Bypass Checking - "
50 #define HSTI_EXTERNAL_DEVICE_DMA_PROTECTION L" - External Device DMA Protection - "
51 #define HSTI_MOR_SUPPORT L" - MOR Support - "
52
53 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH BIT0
54 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH_ERROR_CODE_1 L"0x00100001"
55 #define HSTI_BYTE2_FIRMWARE_TRUSTED_CONTINUATION_CRYPTO_STRENGTH_ERROR_STRING_1 L"SHA1\r\n"
56
57 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION BIT1
58 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION_ERROR_CODE_1 L"0x00110001"
59 #define HSTI_BYTE2_NO_TEST_KEY_VERIFICATION_ERROR_STRING_1 L"fail\r\n"
60
61 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION BIT2
62 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION_ERROR_CODE_1 L"0x00120001"
63 #define HSTI_BYTE2_FIRMWARE_VERSION_ROLLBACK_PROTECTION_ERROR_STRING_1 L"fail\r\n"
64
65 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING BIT3
66 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING_ERROR_CODE_1 L"0x00130001"
67 #define HSTI_BYTE2_SECUREBOOT_BYPASS_CHECKING_ERROR_STRING_1 L"fail\r\n"
68
69
70 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION BIT4
71 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION_ERROR_CODE_1 L"0x00140001"
72 #define HSTI_BYTE2_EXTERNAL_DEVICE_DMA_PROTECTION_ERROR_STRING_1 L"unsupported\r\n"
73
74
75 #define HSTI_BYTE2_MOR_SUPPORT BIT5
76 #define HSTI_BYTE2_MOR_SUPPORT_ERROR_CODE_1 L"0x00150001"
77 #define HSTI_BYTE2_MOR_SUPPORT_ERROR_STRING_1 L"unsupported\r\n"
78
79
80 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: I2cBusConfigurationManagement.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Classes | Typedefs
I2cBusConfigurationManagement.h File Reference

I2C bus configuration management interface. More...

#include <Protocol/I2cMaster.h>
Include dependency graph for I2cBusConfigurationManagement.h:

Go to the source code of this file.

Classes

struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol. More...

Typedefs

typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL | EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol. More...
typedef EFI_STATUS(* | EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)
Enable access to an I2C bus configuration. More...

Detailed Description

I2C bus configuration management interface.

The I2C host driver uses this API to configure the switches and multiplexers in the I2C bus to gain access to the desired I2C device at its maximum clock frequency.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cBusConfigurationManagement.h.

Typedef Documentation

◆ EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION

typedef EFI_STATUS( * EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)

Enable access to an I2C bus configuration.

This routine must be called at or below TPL_NOTIFY. For synchronous requests this routine must be called at or below TPL_CALLBACK.

Reconfigure the switches and multiplexers in the I2C bus to enable access to a specific I2C bus configuration. Also select the maximum clock frequency for this I2C bus configuration.

This routine uses the I2cMaster protocol when the platform routine needs to perform I2C operations on the local bus. This eliminates any recursion in the I2C stack for configuration operations on the local bus. This works because the local I2C bus is idle while the I2C bus configuration is being enabled.

The platform layer must perform I2C operations on other I2C busses by using the EFI_I2C_HOST_PROTOCOL or third party driver interface for the specific device. This requirement is because the I2C host driver controls the flow of requests to the I2C conroller. Use the EFI_I2C_HOST_PROTOCOL when the device is not defined in the platform's ACPI tables. Use the third party driver when it is available or EFI_I2C_BUS_PROTOCOL when the thrid party driver is not available but the device is defined in the platform's ACPI tables.

Parameters
[in] | This | Address of an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL structure
[in] | I2cBusConfiguration | Index into a list or array of I2C bus configurations.
[in] | I2cMaster | Address of an EFI_I2C_MASTER_PROTOCOL structure. This protocol may only be used for this specific operation and should not be referenced after this operation completes!
[in] | Event | Event to set when the operation is complete.
[out] | Status | Buffer to receive the operation status.
Return values
EFI_SUCCESS | The operation completed successfully.
EFI_DEVICE_ERROR | There was an I2C error (NACK) during the operation. This could indicate the peripheral device is not present.
EFI_INVALID_PARAMETER | I2cMaster is NULL
EFI_INVALID_PARAMETER | TPL is too high
EFI_NO_MAPPING | Invalid I2cBusConfiguration value
EFI_NO_RESPONSE | The I2C device is not responding to the peripheral address. EFI_DEVICE_ERROR may also be returned if the controller can not distinguish when the NACK occurred.
EFI_NOT_FOUND | I2C peripheral address exceeds maximum address
EFI_NOT_READY | I2C bus is busy or operation pending, wait for the event and then read status.
EFI_OUT_OF_RESOURCES | Insufficient memory for I2C operation
EFI_TIMEOUT | The transaction did not complete within an internally specified timeout period.

Definition at line 165 of file I2cBusConfigurationManagement.h.

◆ EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL

I2C bus configuration management protocol.

The I2C driver stack uses the concept of an I2C bus configuration as a way to describe a particular state of the switches and multiplexers in the I2C bus.

A simple I2C bus does not have any multiplexers or switches is described to the I2C driver stack with a single I2C bus configuration.

An I2C bus with switches and multiplexers use an I2C bus configuration to describe each of the unique settings for the switches and multiplexers. However the I2C platform driver only needs to define the I2C bus configurations that the software uses, which is a subset of the total.

The I2C bus configuration description includes a list of I2C devices which may be accessed when this I2C bus configuration is enabled. I2C devices before a switch or multiplexer should be included in one I2C bus configuration while I2C devices after a switch or multiplexer should be on another I2C bus configuration.

The I2C bus configuration management protocol is an optional protocol provided by the I2C platform driver. When the I2C bus configuration protocol is not defined the host driver assumes a single I2C bus configuration and operates the I2C bus at 100 KHz. When the I2C bus configuration protocol is available, the I2C host driver uses the I2C bus configuration protocol to call into the I2C platform driver to set the switches and multiplexers and set the maximum I2C bus frequency.

The platform designers determine the maximum I2C bus frequency by selecting a frequency which supports all of the I2C devices on the I2C bus for the setting of switches and multiplexers. The platform designers must validate this against the I2C device data sheets and any limits of the I2C controller or bus length.

The I2C host driver uses an index into a list or array of I2C bus configurations to keep the platform implementation hidden from the rest of the I2C stack. The protocol exposes BusConfigurationCount to enable the I2C host driver to perform bounds checking on the I2C bus configuration value supplied by the upper layers. The I2C bus layer also is told during the I2C device enumeration which I2C bus configuration is in use for each of the I2C devices. While this is hidden from the upper layers the I2C bus configuration is provided to the I2C host driver when performing I2C requests.

When the I2C bus configuration protocol is available, the I2C host driver calls EnableBusConfiguration to enable access to the necessary I2C bus configuration. This host driver may optimize calls to EnableBusConfiguration by only calling the routine only when the I2C bus configuration value changes between I2C requests.

When I2C operations are necessary on the same I2C bus to change I2C GPIO devices, multiplexers or switches, the I2C platform layer uses the I2C controller protocol to perform the necessary I2C operations.

It is up to the I2C platform driver to choose the proper I2C bus configuration when ExitBootServices is called.

Definition at line 1 of file I2cBusConfigurationManagement.h.


AlderLake Platform Sample Code: I2cBusConfigurationManagement.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
I2cBusConfigurationManagement.h
Go to the documentation of this file.
1 /** @file
2 I2C bus configuration management interface
3
4 The I2C host driver uses this API to configure the
5 switches and multiplexers in the I2C bus to gain access
6 to the desired I2C device at its maximum clock frequency.
7
8 @copyright
9 INTEL CONFIDENTIAL
10 Copyright 2012 - 2021 Intel Corporation.
11
12 The source code contained or described herein and all documents related to the
13 source code ("Material") are owned by Intel Corporation or its suppliers or
14 licensors. Title to the Material remains with Intel Corporation or its suppliers
15 and licensors. The Material may contain trade secrets and proprietary and
16 confidential information of Intel Corporation and its suppliers and licensors,
17 and is protected by worldwide copyright and trade secret laws and treaty
18 provisions. No part of the Material may be used, copied, reproduced, modified,
19 published, uploaded, posted, transmitted, distributed, or disclosed in any way
20 without Intel's prior express written permission.
21
22 No license under any patent, copyright, trade secret or other intellectual
23 property right is granted to or conferred upon you by disclosure or delivery
24 of the Materials, either expressly, by implication, inducement, estoppel or
25 otherwise. Any license under such intellectual property rights must be
26 express and approved by Intel in writing.
27
28 Unless otherwise agreed by Intel in writing, you may not remove or alter
29 this notice or any other notice embedded in Materials by Intel or
30 Intel's suppliers or licensors in any way.
31
32 This file contains a 'Sample Driver' and is licensed as such under the terms
33 of your license agreement with Intel or your vendor. This file may be modified
34 by the user, subject to the additional terms of the license agreement.
35
36 @par Specification Reference:
37
38 **/
39
40 #ifndef __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
41 #define __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
42
43 #include <Protocol/I2cMaster.h>
44
45 ///
46 /// I2C bus configuration management protocol
47 ///
48 /// The I2C driver stack uses the concept of an I2C bus configuration
49 /// as a way to describe a particular state of the switches and
50 /// multiplexers in the I2C bus.
51 ///
52 /// A simple I2C bus does not have any multiplexers or switches is
53 /// described to the I2C driver stack with a single I2C bus configuration.
54 ///
55 /// An I2C bus with switches and multiplexers use an I2C bus configuration
56 /// to describe each of the unique settings for the switches and multiplexers.
57 /// However the I2C platform driver only needs to define the I2C bus
58 /// configurations that the software uses, which is a subset of the
59 /// total.
60 ///
61 /// The I2C bus configuration description includes a list of I2C devices
62 /// which may be accessed when this I2C bus configuration is enabled.
63 /// I2C devices before a switch or multiplexer should be included in one
64 /// I2C bus configuration while I2C devices after a switch or multiplexer
65 /// should be on another I2C bus configuration.
66 ///
67 /// The I2C bus configuration management protocol is an optional
68 /// protocol provided by the I2C platform driver. When the I2C bus
69 /// configuration protocol is not defined the host driver assumes a
70 /// single I2C bus configuration and operates the I2C bus at 100 KHz.
71 /// When the I2C bus configuration protocol is available, the I2C host
72 /// driver uses the I2C bus configuration protocol to call into the
73 /// I2C platform driver to set the switches and multiplexers and set
74 /// the maximum I2C bus frequency.
75 ///
76 /// The platform designers determine the maximum I2C bus frequency by
77 /// selecting a frequency which supports all of the I2C devices on the
78 /// I2C bus for the setting of switches and multiplexers. The platform
79 /// designers must validate this against the I2C device data sheets and
80 /// any limits of the I2C controller or bus length.
81 ///
82 /// The I2C host driver uses an index into a list or array of I2C bus
83 /// configurations to keep the platform implementation hidden from the
84 /// rest of the I2C stack. The protocol exposes BusConfigurationCount
85 /// to enable the I2C host driver to perform bounds checking on the I2C
86 /// bus configuration value supplied by the upper layers. The I2C bus
87 /// layer also is told during the I2C device enumeration which I2C bus
88 /// configuration is in use for each of the I2C devices. While this
89 /// is hidden from the upper layers the I2C bus configuration is
90 /// provided to the I2C host driver when performing I2C requests.
91 ///
92 /// When the I2C bus configuration protocol is available, the I2C host
93 /// driver calls EnableBusConfiguration to enable access to the necessary
94 /// I2C bus configuration. This host driver may optimize calls to
95 /// EnableBusConfiguration by only calling the routine only when the I2C
96 /// bus configuration value changes between I2C requests.
97 ///
98 /// When I2C operations are necessary on the same I2C bus to change I2C
99 /// GPIO devices, multiplexers or switches, the I2C platform layer uses
100 /// the I2C controller protocol to perform the necessary I2C operations.
101 ///
102 /// It is up to the I2C platform driver to choose the proper I2C bus
103 /// configuration when ExitBootServices is called.
104 ///
105 typedef struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL;
106
107
108 /**
109 Enable access to an I2C bus configuration.
110
111 This routine must be called at or below TPL_NOTIFY. For synchronous
112 requests this routine must be called at or below TPL_CALLBACK.
113
114 Reconfigure the switches and multiplexers in the I2C bus to enable
115 access to a specific I2C bus configuration. Also select the maximum
116 clock frequency for this I2C bus configuration.
117
118 This routine uses the I2cMaster protocol when the platform routine
119 needs to perform I2C operations on the local bus. This eliminates
120 any recursion in the I2C stack for configuration operations on the
121 local bus. This works because the local I2C bus is idle while the
122 I2C bus configuration is being enabled.
123
124 The platform layer must perform I2C operations on other I2C busses
125 by using the EFI_I2C_HOST_PROTOCOL or third party driver interface
126 for the specific device. This requirement is because the I2C host
127 driver controls the flow of requests to the I2C conroller. Use the
128 EFI_I2C_HOST_PROTOCOL when the device is not defined in the platform's
129 ACPI tables. Use the third party driver when it is available or
130 EFI_I2C_BUS_PROTOCOL when the thrid party driver is not available
131 but the device is defined in the platform's ACPI tables.
132
133 @param[in] This Address of an EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
134 structure
135 @param[in] I2cBusConfiguration Index into a list or array of I2C bus
136 configurations.
137 @param[in] I2cMaster Address of an EFI_I2C_MASTER_PROTOCOL
138 structure. This protocol may only be used
139 for this specific operation and should not
140 be referenced after this operation completes!
141 @param[in] Event Event to set when the operation is
142 complete.
143 @param[out] Status Buffer to receive the operation
144 status.
145
146 @retval EFI_SUCCESS The operation completed successfully.
147 @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
148 This could indicate the peripheral device is not present.
149 @retval EFI_INVALID_PARAMETER I2cMaster is NULL
150 @retval EFI_INVALID_PARAMETER TPL is too high
151 @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value
152 @retval EFI_NO_RESPONSE The I2C device is not responding to the
153 peripheral address. EFI_DEVICE_ERROR may also be
154 returned if the controller can not distinguish
155 when the NACK occurred.
156 @retval EFI_NOT_FOUND I2C peripheral address exceeds maximum address
157 @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
158 the event and then read status.
159 @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
160 @retval EFI_TIMEOUT The transaction did not complete within an internally
161 specified timeout period.
162
163 **/
164 typedef
165 EFI_STATUS
166 (EFIAPI *EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION) (
167 IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This,
168 IN UINTN I2cBusConfiguration,
169 IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster,
170 IN EFI_EVENT Event OPTIONAL,
171 IN EFI_STATUS *Status OPTIONAL
172 );
173
174
175 ///
176 /// I2C bus configuration management protocol
177 ///
178 struct _EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL {
179 ///
180 /// Enable an I2C bus configuration for use
181 ///
182 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration;
183
184 ///
185 /// Number of switch and multiplexer configurations for this
186 /// I2C bus.
187 ///
188 UINTN I2cBusConfigurationCount;
189 };
190
191 #endif // __I2C_BUS_CONFIGURATION_MANAGEMENT_H__
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL::I2cBusConfigurationCount
UINTN I2cBusConfigurationCount
Number of switch and multiplexer configurations for this I2C bus.
Definition: I2cBusConfigurationManagement.h:188
I2cMaster.h
I2C Master interface.
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL::EnableI2cBusConfiguration
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION EnableI2cBusConfiguration
Enable an I2C bus configuration for use.
Definition: I2cBusConfigurationManagement.h:182
_EFI_I2C_MASTER_PROTOCOL
I2C controller mode protocol.
Definition: I2cMaster.h:511
_EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL
I2C bus configuration management protocol.
Definition: I2cBusConfigurationManagement.h:178
EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION
EFI_STATUS(* EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION)(IN CONST EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL *This, IN UINTN I2cBusConfiguration, IN CONST EFI_I2C_MASTER_PROTOCOL *I2cMaster, IN EFI_EVENT Event OPTIONAL, IN EFI_STATUS *Status OPTIONAL)
Enable access to an I2C bus configuration.
Definition: I2cBusConfigurationManagement.h:166
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: I2cMaster.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Classes | Typedefs
I2cMaster.h File Reference

I2C Master interface. More...

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Go to the source code of this file.

Classes

struct | EFI_I2C_REQUEST_PACKET
I2C device operation. More...
struct | _EFI_I2C_MASTER_PROTOCOL
I2C controller mode protocol. More...

Typedefs

typedef struct _EFI_I2C_MASTER_PROTOCOL | EFI_I2C_MASTER_PROTOCOL
Declare the forward references. More...
typedef EFI_STATUS(* | EFI_I2C_MASTER_BUS_FREQUENCY_SET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)
Set the I2C controller bus clock frequency. More...
typedef VOID(* | EFI_I2C_MASTER_RESET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This)
Reset the I2C controller and configure it for use. More...
typedef EFI_STATUS(* | EFI_I2C_MASTER_START_REQUEST) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)
Start an I2C operation on the host controller. More...

Detailed Description

I2C Master interface.

A driver or application uses the I2C controller protocol to manage the controller mode of an I2C controller. Note that access is restricted to the current configuration of the I2C bus.

I2C Driver Stack

The following is a representation of the I2C (I2C) driver stack and an I2C bus layout.

                 +-----------------+
                 |   Application   |
                 +-----------------+
                          |
                          | Third Party or UEFI
                          |
                          V
     +----------+   +-----------------+
     |Peripheral|   |   Third Party   |
     |  Driver  |   |   I2C Device    |
     |          |   |     Driver      |
     +----------+   +-----------------+
            |             |
            |         BUS |
            |             |
            |             V
            |    +-----------------+
            |    | I2C Bus Driver  |------------------.
            |    +-----------------+                  |
            |             |                           |
            |        HOST |          BUS              |
            |             |          CONFIGURATION    |
 PERIPHERAL |             V          MANAGEMENT       | ACPI
            |    +-----------------+                  |
            |    | I2C Host Driver |----------.       |
            |    +-----------------+          |       |
            |             |                   |       |
            |  Controller |                   V       V
            |             |               +-------=-------------+
            |             V               | I2C Platform Driver |
            |    +-----------------+      +---------------------+
            `--->| I2C Port Driver |               |      |
                 +-----------------+               |      |
                          |                        |      |
               Software   |                        |      |
               --------------------------------------------------
               Hardware   |                        |      |
                          |                        |      |
                          V                        |      |
                 +-----------------+               |      |
                 | I2C Controller  |               |      |
                 +-----------------+               |      |
                          |                        |      |
               -----------------------             |      |
               I2C Bus    |                        |      |
                          |    +------------+      |      |
                          +----| High speed |      |      |
                          |    | I2C device |      |      |
                          |    |    0x01    |      |      |
                          |    +------------+      |      |
                          |                        |      |
                     +---------+  0                |      |
                     | Switch  |<------------------`      |
                     +---------+  1                       |
                          |                               |
                          |    +------------+             |
                          +----| Fast speed |             |
                          |    | I2C device |             |
                          |    |    0x02    |             |
                          |    +------------+             |
                          |                               |
                   +-------------+                        |
                   | Multiplexer |<-----------------------`
                   +-------------+
                    0 |       | 1
                      |       |
                      |       |
                      |       |    +-------------+
                      |       +----| Third Party |
                      |       |    | I2C Device  |
                      |       |    |  0x03, 0x04 |
                      |       |    +-------------+
                      |       |
                      |
                      |            +-------------+
                      +------------| Third Party |
                      |            | I2C Device  |
                      |            |  0x03, 0x04 |
                      |            +-------------+
                      |

The platform hardware designer chooses the bus layout based upon the platform, I2C chip and software requirements. The design uses switches to truncate the bus to enable higher speed operation for a subset of devices which are placed closer to the controller. When the switch is on, the extended bus must operate at a lower speed. The design uses multiplexer to create separate address spaces enabling the use of multiple devices which would otherwise have conflicting addresses. See the I2C Specification for more details.

N.B. Some operating systems may prohibit the changing of switches and multiplexers in the I2C bus. In this case the platform hardware and software designers must select a single I2C bus configuration consisting of constant input values for the switches and multiplexers. The platform software designer must then ensure that this I2C bus configuration is enabled prior to passing control to the operating system.

The platform hardware designer needs to provide the platform software designer the following data for each I2C bus:

  1. Which controller controls this bus

  2. A list of logic blocks contained in one or more I2C devices:

    a. I2C device which contains this logic block

    b. Logic block peripheral address

    c. Logic block name

  3. For each configuration of the switches and multiplexer

    a. What is the maximum speed of operation

    b. What devices are accessible

  4. The settings for the switches and multiplexers when control is given to the operating system.

Third Party I2C Drivers

This layer is I2C chip specific but platform and host controller independent.

Third party I2C driver writers, typically silicon vendors, need to provide:

  1. The device path node data that is used to select their driver.
  2. The order for the blocks of logic that get referenced by the entries in the peripheral address array.
  3. The hardware version of the I2C device, this value is passed to the third party I2C driver to enable it to perform work arounds for the specific hardware version. This value should match the value in the ACPI _HRV tag.

The third party I2C driver uses relative addressing to abstract the platform specific details of the I2C device. Using an example I2C device containing an accelerometer and a magnetometer which consumes two peripheral addresses, one for each logic block. The third party I2C driver writer may choose to write two drivers, one for each block of logic, in which case each driver refers to the single I2C peripheral address using the relative value of zero (0). However if the third party I2C driver writer chooses to write a single driver which consumes multiple peripheral addresses then the third party I2C driver writer needs to convey the order of the I2C peripheral address entries in the peripheral address array to the platform software designer. For the example:

0: Accelerometer

1: Magnetometer

The platform hardware designer picks the actual peripheral addresses from the I2C device's data sheet and provides this information to the platform software designer. The platform software designer then places the peripheral addresses into the peripheral address array in the order specified by the third party I2C driver writer. The third party driver I2C writer then indirectly references this array by specifying the index value as the relative peripheral address. The relative value always starts at zero (0) and its maximum value is the number of entries in peripheral address array minus one.

The peripheral address is specified as a 32-bit integer to allow room for future peripheral address expansion. Only the port driver knows the maximum peripheral address value. All other drivers and applications must look for the EFI_NOT_FOUND status for the indication that the maximum peripheral address was exceeded.

I2C Bus Driver

This layer is platform, host controller, and I2C chip independent.

The I2C bus driver creates a handle for each of the I2C devices described within the platform driver. The I2C controller's device path is extended with the device path node provided by the platform driver and attached to the handle. The third party I2C device driver uses the device path to determine if it may connect. For ACPI nodes, the third party I2C driver should use the CID or CidString value.

The I2C bus driver validates the relative address for the I2C device and then converts the relative value to an actual I2C peripheral address. The request is then passed to the I2C host driver.

I2C Host Driver

This layer is platform, host controller, and I2C chip independent.

N.B. For proper operation of the I2C bus, only the I2C bus driver and the I2C test application should connect to the I2C host driver via the EFI_I2C_HOST_DRIVER_PROTOCOL.

The I2C host driver may access any device on the I2C bus. The I2C host driver has the following responsibilities:

  1. Limits the number of requests to the I2C port driver to one. The I2C host driver holds on to additional requests until the I2C port driver is available to process the request. The I2C requests are issued in FIFO order to the I2C port driver.
  2. Enable the proper I2C bus configuration before starting the I2C request on the I2C port driver

I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress. I2C bus configuration zero (0) is the portion of the I2C bus that connects to the host controller. The bus configuration specifies the control values for the switches and multiplexers in the I2C bus. After the switches and multiplexers are properly configured, the I2C controller uses the peripheral address to access the requested I2C device.

Since the I2C driver stack supports asynchronous operations this layer maintains a queue of I2C requests until the I2C controller is available them. When a request reaches the head of the queue the necessary bus configuration is enabled and then the request is sent to the I2C port driver.

I2C Port Driver

This layer is I2C controller specific but platform independent.

This layer manipulates the I2C controller to perform an operation on the I2C bus. This layer does not configure the I2C bus so it is up to the caller to ensure that the I2C bus is in the proper configuration before issuing the I2C request.

This layer typically needs the following information:

  1. Host controller address
  2. Controller's input clock frequency

Depending upon the I2C controller, more data may be necessary. This layer may use any method to get these values: hard coded values, PCD values, or may choose to communicate with the platform layer using an undefined mechanism to get these values.

If the I2C port driver requires data from the platform driver then the I2C port driver writer needs to provide the platform interface details to the platform software designer.

I2C Platform Driver

When enabling access to I2C devices within UEFI, this driver installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device descriptions to the I2C bus driver using the EFI_I2C_DEVICE structure. These descriptions include the bus configuration number required for the I2C device, the peripheral address array and the device path.

The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional. This protocol needs to be specified under the following conditions:

  1. The I2C bus must operate at a frequency greater than 100 KHz
  2. The I2C bus contains switches or multiplexers.

The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the I2C host driver to call into the I2C platform driver to enable a specific I2C bus configuration and set its maximum clock speed.

The platform software designer collects the data requirements from third party I2C driver writers, the I2C controller driver writer, the EFI_I2C_ACPI_PROTOCOL and EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform software designer gets the necessary data from the platform hardware designer. The platform software designer then builds the data structures and implements the necessary routines to construct the I2C platform driver.

Switches and Multiplexers

There are some I2C switches and I2C multiplexers where the control is done via I2C commands. When the control inputs come via the same I2C bus that is being configured then the platform driver must use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform driver. While the I2C host driver makes the call to the I2C platform driver to configure the bus, the host driver keeps the I2C port driver idle, to allow the I2C platform driver preform the necessary configuration operations.

If however the configuration control is done via and I2C device connected to a different I2C bus (host controller), then it is possible for the platform software designer may choose between the following:

  1. Call into a third party I2C driver to manipulate the I2C bus control device.
  2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C driver exists for the I2C bus control device
  3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does not expose the I2C bus control device.
Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file I2cMaster.h.

Typedef Documentation

◆ EFI_I2C_MASTER_BUS_FREQUENCY_SET

typedef EFI_STATUS( * EFI_I2C_MASTER_BUS_FREQUENCY_SET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)

Set the I2C controller bus clock frequency.

This routine must be called at or below TPL_NOTIFY.

The software and controller do a best case effort of using the specified frequency for the I2C bus. If the frequency does not match exactly then the controller will use a slightly lower frequency to avoid exceeding the operating conditions for any of the I2C devices on the bus. For example if 400 KHz was specified and the controller's divide network only supports 402 KHz or 398 KHz then the controller would be set to 398 KHz. However if the desired frequency is 400 KHz and the controller only supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.

Parameters
[in] | This | Address of an EFI_I2C_MASTER_PROTOCOL structure
[in] | BusClockHertz | New I2C bus clock frequency in Hertz
Return values
EFI_SUCCESS | The bus frequency was set successfully.
EFI_UNSUPPORTED | The controller does not support this frequency.

Definition at line 414 of file I2cMaster.h.

◆ EFI_I2C_MASTER_PROTOCOL

typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL

Declare the forward references.

I2C controller protocol

Definition at line 1 of file I2cMaster.h.

◆ EFI_I2C_MASTER_RESET

typedef VOID( * EFI_I2C_MASTER_RESET) (IN CONST EFI_I2C_MASTER_PROTOCOL *This)

Reset the I2C controller and configure it for use.

This routine must be called at or below TPL_NOTIFY.

The I2C controller is reset and the I2C bus frequency is set to 100 KHz.

Parameters
[in] This Address of an EFI_I2C_MASTER_PROTOCOL structure

Definition at line 432 of file I2cMaster.h.

◆ EFI_I2C_MASTER_START_REQUEST

typedef EFI_STATUS( * EFI_I2C_MASTER_START_REQUEST) (IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)

Start an I2C operation on the host controller.

This routine must be called at or below TPL_NOTIFY. For synchronous requests this routine must be called at or below TPL_CALLBACK.

This function initiates an I2C operation on the controller.

The operation is performed by selecting the I2C device with its peripheral address and then sending all write data to the I2C device. If read data is requested, a restart is sent followed by the peripheral address and then the read data is clocked into the I2C controller and placed in the read buffer. When the operation completes, the status value is returned and then the event is set.

N.B. The typical consumer of this API is the I2C host driver. Extreme care must be taken by other consumers of this API to prevent confusing the third party I2C drivers due to a state change at the I2C device which the third party I2C drivers did not initiate. I2C platform drivers may use this API within these guidelines.

N.B. This API supports only one operation, no queuing support exists at this layer. This API assumes that the I2C bus is in the correct configuration for the I2C request.

Parameters
[in] | This | Address of an EFI_I2C_MASTER_PROTOCOL structure
[in] | SlaveAddress | Address of the device on the I2C bus.
[in] | Event | Event to set for asynchronous operations, NULL for synchronous operations
[in] | RequestPacket | Address of an EFI_I2C_REQUEST_PACKET structure describing the I2C operation
[out] | I2cStatus | Optional buffer to receive the I2C operation completion status
Return values
EFI_SUCCESS | The operation completed successfully.
EFI_ABORTED | The request did not complete because the driver was shutdown.
EFI_BAD_BUFFER_SIZE | The WriteBytes or ReadBytes buffer size is too large.
EFI_DEVICE_ERROR | There was an I2C error (NACK) during the operation. This could indicate the peripheral device is not present.
EFI_INVALID_PARAMETER | RequestPacket is NULL
EFI_INVALID_PARAMETER | TPL is too high
EFI_NOT_FOUND | SlaveAddress exceeds maximum address
EFI_NOT_READY | I2C bus is busy or operation pending, wait for the event and then read status pointed to by the request packet.
EFI_NO_RESPONSE | The I2C device is not responding to the peripheral address. EFI_DEVICE_ERROR may also be returned if the controller cannot distinguish when the NACK occurred.
EFI_OUT_OF_RESOURCES | Insufficient memory for I2C operation
EFI_TIMEOUT | The transaction did not complete within an internally specified timeout period.

Definition at line 495 of file I2cMaster.h.


AlderLake Platform Sample Code: I2cMaster.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
I2cMaster.h
Go to the documentation of this file.
1 /** @file
2 I2C Master interface
3
4 A driver or application uses the I2C controller protocol to
5 manage the controller mode of an I2C controller. Note that
6 access is restricted to the current configuration of the I2C
7 bus.
8
9 \section I2cDriverStack I2C Driver Stack
10
11 The following is a representation of the I<sup>2</sup>C (I2C)
12 driver stack and an I2C bus layout.
13
14 <code><pre>
15 +-----------------+
16 | Application |
17 +-----------------+
18 |
19 | Third Party or UEFI
20 |
21 V
22 +----------+ +-----------------+
23 |Peripheral| | Third Party |
24 | Driver | | I2C Device |
25 | | | Driver |
26 +----------+ +-----------------+
27 | |
28 | BUS |
29 | |
30 | V
31 | +-----------------+
32 | | I2C Bus Driver |------------------.
33 | +-----------------+ |
34 | | |
35 | HOST | BUS |
36 | | CONFIGURATION |
37 PERIPHERAL | V MANAGEMENT | ACPI
38 | +-----------------+ |
39 | | I2C Host Driver |----------. |
40 | +-----------------+ | |
41 | | | |
42 | Controller | V V
43 | | +-------=-------------+
44 | V | I2C Platform Driver |
45 | +-----------------+ +---------------------+
46 `--->| I2C Port Driver | | |
47 +-----------------+ | |
48 | | |
49 Software | | |
50 --------------------------------------------------
51 Hardware | | |
52 | | |
53 V | |
54 +-----------------+ | |
55 | I2C Controller | | |
56 +-----------------+ | |
57 | | |
58 ----------------------- | |
59 I2C Bus | | |
60 | +------------+ | |
61 +----| High speed | | |
62 | | I2C device | | |
63 | | 0x01 | | |
64 | +------------+ | |
65 | | |
66 +---------+ 0 | |
67 | Switch |<------------------` |
68 +---------+ 1 |
69 | |
70 | +------------+ |
71 +----| Fast speed | |
72 | | I2C device | |
73 | | 0x02 | |
74 | +------------+ |
75 | |
76 +-------------+ |
77 | Multiplexer |<-----------------------`
78 +-------------+
79 0 | | 1
80 | |
81 | |
82 | | +-------------+
83 | +----| Third Party |
84 | | | I2C Device |
85 | | | 0x03, 0x04 |
86 | | +-------------+
87 | |
88 |
89 | +-------------+
90 +------------| Third Party |
91 | | I2C Device |
92 | | 0x03, 0x04 |
93 | +-------------+
94 |
95 </pre></code>
96
97 The platform hardware designer chooses the bus layout based upon
98 the platform, I2C chip and software requirements. The design uses
99 switches to truncate the bus to enable higher speed operation for a
100 subset of devices which are placed closer to the controller. When the
101 switch is on, the extended bus must operate at a lower speed. The
102 design uses multiplexer to create separate address spaces enabling
103 the use of multiple devices which would otherwise have conflicting
104 addresses. See the
105 <a href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I<sup>2</sup>C
106 Specification</a> for more details.
107
108 N.B. Some operating systems may prohibit the changing of switches
109 and multiplexers in the I2C bus. In this case the platform hardware
110 and software designers must select a single I2C bus configuration
111 consisting of constant input values for the switches and multiplexers.
112 The platform software designer must then ensure that this I2C bus
113 configuration is enabled prior to passing control to the operating
114 system.
115
116 The platform hardware designer needs to provide the platform software
117 designer the following data for each I2C bus:
118
119 1. Which controller controls this bus
120
121 2. A list of logic blocks contained in one or more I2C devices:
122
123 a. I2C device which contains this logic block
124
125 b. Logic block peripheral address
126
127 c. Logic block name
128
129 3. For each configuration of the switches and multiplexer
130
131 a. What is the maximum speed of operation
132
133 b. What devices are accessible
134
135 4. The settings for the switches and multiplexers when control is
136 given to the operating system.
137
138 \section ThirdPartyI2cDrivers Third Party I2C Drivers
139
140 This layer is I2C chip specific but platform and host controller
141 independent.
142
143 Third party I2C driver writers, typically silicon vendors, need
144 to provide:
145
146 1. The device path node data that is used to select their
147 driver.
148
149 2. The order for the blocks of logic that get referenced
150 by the entries in the peripheral address array.
151
152 3. The hardware version of the I2C device, this value is passed
153 to the third party I2C driver to enable it to perform work
154 arounds for the specific hardware version. This value should
155 match the value in the ACPI _HRV tag.
156
157 The third party I2C driver uses relative addressing to abstract
158 the platform specific details of the I2C device. Using an
159 example I2C device containing an accelerometer and a magnetometer
160 which consumes two peripheral addresses, one for each logic block. The
161 third party I2C driver writer may choose to write two drivers, one
162 for each block of logic, in which case each driver refers to the
163 single I2C peripheral address using the relative value of zero (0).
164 However if the third party I2C driver writer chooses to write a
165 single driver which consumes multiple peripheral addresses then the
166 third party I2C driver writer needs to convey the order of the
167 I2C peripheral address entries in the peripheral address array to the
168 platform software designer. For the example:
169
170 0: Accelerometer
171
172 1: Magnetometer
173
174 The platform hardware designer picks the actual peripheral addresses
175 from the I2C device's data sheet and provides this information
176 to the platform software designer. The platform software designer
177 then places the peripheral addresses into the peripheral address array in the
178 order specified by the third party I2C driver writer. The third
179 party driver I2C writer then indirectly references this array by
180 specifying the index value as the relative peripheral address. The
181 relative value always starts at zero (0) and its maximum value is
182 the number of entries in peripheral address array minus one.
183
184 The peripheral address is specified as a 32-bit integer to allow room
185 for future peripheral address expansion. Only the port driver knows
186 the maximum peripheral address value. All other drivers and
187 applications must look for the EFI_NOT_FOUND status for the
188 indication that the maximum peripheral address was exceeded.
189
190 \section I2cBusDriver I2C Bus Driver
191
192 This layer is platform, host controller, and I2C chip independent.
193
194 The I2C bus driver creates a handle for each of the I2C devices
195 described within the platform driver. The I2C controller's device
196 path is extended with the device path node provided by the platform
197 driver and attached to the handle. The third party I2C device driver
198 uses the device path to determine if it may connect. For ACPI nodes,
199 the third party I2C driver should use the CID or CidString value.
200
201 The I2C bus driver validates the relative address for the I2C device
202 and then converts the relative value to an actual I2C peripheral address.
203 The request is then passed to the I2C host driver.
204
205 \section I2cHostDriver I2C Host Driver
206
207 This layer is platform, host controller, and I2C chip independent.
208
209 N.B. For proper operation of the I2C bus, only the I2C bus driver
210 and the I2C test application should connect to the I2C host driver
211 via the EFI_I2C_HOST_DRIVER_PROTOCOL.
212
213 The I2C host driver may access any device on the I2C bus. The I2C
214 host driver has the following responsibilities:
215
216 1. Limits the number of requests to the I2C port driver to one.
217 The I2C host driver holds on to additional requests until the
218 I2C port driver is available to process the request. The I2C
219 requests are issued in FIFO order to the I2C port driver.
220
221 2. Enable the proper I2C bus configuration before starting the
222 I2C request on the I2C port driver
223
224 I2C devices are addressed as the tuple: BusConfiguration:SlaveAddress.
225 I2C bus configuration zero (0) is the portion of the I2C bus that
226 connects to the host controller. The bus configuration specifies
227 the control values for the switches and multiplexers in the I2C bus.
228 After the switches and multiplexers are properly configured, the I2C
229 controller uses the peripheral address to access the requested I2C device.
230
231 Since the I2C driver stack supports asynchronous operations this
232 layer maintains a queue of I2C requests until the I2C controller
233 is available them. When a request reaches the head of the queue
234 the necessary bus configuration is enabled and then the request
235 is sent to the I2C port driver.
236
237 \section I2cPortDriver I2C Port Driver
238
239 This layer is I2C controller specific but platform independent.
240
241 This layer manipulates the I2C controller to perform an operation
242 on the I2C bus. This layer does not configure the I2C bus so it
243 is up to the caller to ensure that the I2C bus is in the proper
244 configuration before issuing the I2C request.
245
246 This layer typically needs the following information:
247
248 1. Host controller address
249 2. Controller's input clock frequency
250
251 Depending upon the I2C controller, more data may be necessary.
252 This layer may use any method to get these values: hard coded
253 values, PCD values, or may choose to communicate with the platform
254 layer using an undefined mechanism to get these values.
255
256 If the I2C port driver requires data from the platform driver then
257 the I2C port driver writer needs to provide the platform interface
258 details to the platform software designer.
259
260 \section I2cPlatformDriver I2C Platform Driver
261
262 When enabling access to I2C devices within UEFI, this driver
263 installs the EFI_I2C_ACPI_PROTOCOL to provide the I2C device
264 descriptions to the I2C bus driver using the EFI_I2C_DEVICE
265 structure. These descriptions include the bus configuration
266 number required for the I2C device, the peripheral address array
267 and the device path.
268
269 The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol is optional.
270 This protocol needs to be specified under the following conditions:
271
272 1. The I2C bus must operate at a frequency greater than 100 KHz
273 2. The I2C bus contains switches or multiplexers.
274
275 The EFI_I2C_BUS_CONFIGURATION_MANAGEMENT protocol enables the
276 I2C host driver to call into the I2C platform driver to enable
277 a specific I2C bus configuration and set its maximum clock speed.
278
279 The platform software designer collects the data requirements
280 from third party I2C driver writers, the I2C controller
281 driver writer, the EFI_I2C_ACPI_PROTOCOL and
282 EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL. The platform
283 software designer gets the necessary data from the platform
284 hardware designer. The platform software designer then builds
285 the data structures and implements the necessary routines to
286 construct the I2C platform driver.
287
288 \section I2cSwitches Switches and Multiplexers
289
290 There are some I2C switches and I2C multiplexers where the control
291 is done via I2C commands. When the control inputs come via the
292 same I2C bus that is being configured then the platform driver must
293 use the EFI_I2C_MASTER_PROTOCOL that is passed to the platform
294 driver. While the I2C host driver makes the call to the I2C
295 platform driver to configure the bus, the host driver keeps the
296 I2C port driver idle, to allow the I2C platform driver preform
297 the necessary configuration operations.
298
299 If however the configuration control is done via and I2C device
300 connected to a different I2C bus (host controller), then it is
301 possible for the platform software designer may choose between
302 the following:
303
304 1. Call into a third party I2C driver to manipulate the I2C
305 bus control device.
306 2. Call into the EFI_I2C_BUS_PROTOCOL if no third party I2C
307 driver exists for the I2C bus control device
308 3. Call into the EFI_I2C_HOST_PROTOCOL if the platform does
309 not expose the I2C bus control device.
310
311 @copyright
312 INTEL CONFIDENTIAL
313 Copyright 2012 - 2021 Intel Corporation.
314
315 The source code contained or described herein and all documents related to the
316 source code ("Material") are owned by Intel Corporation or its suppliers or
317 licensors. Title to the Material remains with Intel Corporation or its suppliers
318 and licensors. The Material may contain trade secrets and proprietary and
319 confidential information of Intel Corporation and its suppliers and licensors,
320 and is protected by worldwide copyright and trade secret laws and treaty
321 provisions. No part of the Material may be used, copied, reproduced, modified,
322 published, uploaded, posted, transmitted, distributed, or disclosed in any way
323 without Intel's prior express written permission.
324
325 No license under any patent, copyright, trade secret or other intellectual
326 property right is granted to or conferred upon you by disclosure or delivery
327 of the Materials, either expressly, by implication, inducement, estoppel or
328 otherwise. Any license under such intellectual property rights must be
329 express and approved by Intel in writing.
330
331 Unless otherwise agreed by Intel in writing, you may not remove or alter
332 this notice or any other notice embedded in Materials by Intel or
333 Intel's suppliers or licensors in any way.
334
335 This file contains a 'Sample Driver' and is licensed as such under the terms
336 of your license agreement with Intel or your vendor. This file may be modified
337 by the user, subject to the additional terms of the license agreement.
338
339 @par Specification Reference:
340
341 **/
342
343 #ifndef __I2C_MASTER_H__
344 #define __I2C_MASTER_H__
345
346 // @todo: do the integration with the I2cMaster.h from MdePkg.
347
348 /**
349 Declare the forward references
350
351 **/
352 typedef struct _EFI_I2C_MASTER_PROTOCOL EFI_I2C_MASTER_PROTOCOL; ///< I2C controller protocol
353
354 ///
355 /// I2C device operation
356 ///
357 /// This structure provides the information necessary for an operation
358 /// on an I2C device
359 ///
360 typedef struct {
361 ///
362 /// Number of bytes to send to the I2C device
363 ///
364 UINT32 WriteBytes;
365
366 ///
367 /// Number of bytes to read, set to zero for write only operations
368 ///
369 UINT32 ReadBytes;
370
371 ///
372 /// Address of the buffer containing the data to send to the I2C device.
373 /// The WriteBuffer must be at least WriteBytes in length.
374 ///
375 UINT8 *WriteBuffer;
376
377 ///
378 /// Address of the buffer to receive data from the I2C device. Use NULL
379 /// for write only operations. The ReadBuffer must be at least ReadBytes
380 /// in length.
381 ///
382 UINT8 *ReadBuffer;
383
384 ///
385 /// Timeout for the I2C operation in 100 ns units
386 ///
387 UINT32 Timeout;
388 } EFI_I2C_REQUEST_PACKET;
389
390
391 /**
392 Set the I2C controller bus clock frequency.
393
394 This routine must be called at or below TPL_NOTIFY.
395
396 The software and controller do a best case effort of using the specified
397 frequency for the I2C bus. If the frequency does not match exactly then
398 the controller will use a slightly lower frequency to avoid
399 exceeding the operating conditions for any of the I2C devices on the bus.
400 For example if 400 KHz was specified and the controller's divide network
401 only supports 402 KHz or 398 KHz then the controller would be set to 398
402 KHz. However if the desired frequency is 400 KHz and the controller only
403 supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTED.
404
405 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
406 structure
407 @param[in] BusClockHertz New I2C bus clock frequency in Hertz
408
409 @retval EFI_SUCCESS The bus frequency was set successfully.
410 @retval EFI_UNSUPPORTED The controller does not support this frequency.
411
412 **/
413 typedef
414 EFI_STATUS
415 (EFIAPI *EFI_I2C_MASTER_BUS_FREQUENCY_SET) (
416 IN CONST EFI_I2C_MASTER_PROTOCOL *This,
417 IN UINTN BusClockHertz
418 );
419
420 /**
421 Reset the I2C controller and configure it for use
422
423 This routine must be called at or below TPL_NOTIFY.
424
425 The I2C controller is reset and the I2C bus frequency is set to 100 KHz.
426
427 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
428 structure
429
430 **/
431 typedef
432 VOID
433 (EFIAPI *EFI_I2C_MASTER_RESET) (
434 IN CONST EFI_I2C_MASTER_PROTOCOL *This
435 );
436
437 /**
438 Start an I2C operation on the host controller
439
440 This routine must be called at or below TPL_NOTIFY. For synchronous
441 requests this routine must be called at or below TPL_CALLBACK.
442
443 This function initiates an I2C operation on the controller.
444
445 The operation is performed by selecting the I2C device with its peripheral
446 address and then sending all write data to the I2C device. If read data
447 is requested, a restart is sent followed by the peripheral address and then
448 the read data is clocked into the I2C controller and placed in the read
449 buffer. When the operation completes, the status value is returned and
450 then the event is set.
451
452 N.B. The typical consumer of this API is the I2C host driver.
453 Extreme care must be taken by other consumers of this API to
454 prevent confusing the third party I2C drivers due to a state
455 change at the I2C device which the third party I2C drivers did
456 not initiate. I2C platform drivers may use this API within
457 these guidelines.
458
459 N.B. This API supports only one operation, no queuing support
460 exists at this layer. This API assumes that the I2C bus is in
461 the correct configuration for the I2C request.
462
463 @param[in] This Address of an EFI_I2C_MASTER_PROTOCOL
464 structure
465 @param[in] SlaveAddress Address of the device on the I2C bus.
466 @param[in] Event Event to set for asynchronous operations,
467 NULL for synchronous operations
468 @param[in] RequestPacket Address of an EFI_I2C_REQUEST_PACKET
469 structure describing the I2C operation
470 @param[out] I2cStatus Optional buffer to receive the I2C operation
471 completion status
472
473 @retval EFI_SUCCESS The operation completed successfully.
474 @retval EFI_ABORTED The request did not complete because the driver
475 was shutdown.
476 @retval EFI_BAD_BUFFER_SIZE The WriteBytes or ReadBytes buffer size is too large.
477 @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the operation.
478 This could indicate the peripheral device is not present.
479 @retval EFI_INVALID_PARAMETER RequestPacket is NULL
480 @retval EFI_INVALID_PARAMETER TPL is too high
481 @retval EFI_NOT_FOUND SlaveAddress exceeds maximum address
482 @retval EFI_NOT_READY I2C bus is busy or operation pending, wait for
483 the event and then read status pointed to by
484 the request packet.
485 @retval EFI_NO_RESPONSE The I2C device is not responding to the
486 peripheral address. EFI_DEVICE_ERROR may also be
487 returned if the controller cannot distinguish
488 when the NACK occurred.
489 @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C operation
490 @retval EFI_TIMEOUT The transaction did not complete within an internally
491 specified timeout period.
492
493 **/
494 typedef
495 EFI_STATUS
496 (EFIAPI *EFI_I2C_MASTER_START_REQUEST) (
497 IN CONST EFI_I2C_MASTER_PROTOCOL *This,
498 IN UINTN SlaveAddress,
499 IN EFI_EVENT Event OPTIONAL,
500 IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket,
501 OUT EFI_STATUS *I2cStatus OPTIONAL
502 );
503
504 ///
505 /// I2C controller mode protocol
506 ///
507 /// This protocol manipulates the I2C host controller to perform transactions as a
508 /// controller on the I2C bus using the current state of any switches or multiplexers
509 /// in the I2C bus.
510 ///
511 struct _EFI_I2C_MASTER_PROTOCOL {
512 ///
513 /// Set the clock frequency for the I2C bus
514 ///
515 EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet;
516
517 ///
518 /// Reset the I2C host controller
519 ///
520 EFI_I2C_MASTER_RESET Reset;
521
522 ///
523 /// Start an I2C transaction in controller mode on the host controller
524 ///
525 EFI_I2C_MASTER_START_REQUEST StartRequest;
526
527 ///
528 /// The maximum number of bytes the I2C host controller
529 /// is able to receive from the I2C bus.
530 ///
531 UINT32 MaximumReceiveBytes;
532
533 ///
534 /// The maximum number of bytes the I2C host controller
535 /// is able to send on the I2C bus.
536 ///
537 UINT32 MaximumTransmitBytes;
538
539 ///
540 /// The maximum number of bytes in the I2C bus transaction.
541 ///
542 UINT32 MaximumTotalBytes;
543 };
544
545 #endif // __I2C_MASTER_H__
_EFI_I2C_MASTER_PROTOCOL::MaximumReceiveBytes
UINT32 MaximumReceiveBytes
The maximum number of bytes the I2C host controller is able to receive from the I2C bus.
Definition: I2cMaster.h:531
EFI_I2C_REQUEST_PACKET::ReadBuffer
UINT8 * ReadBuffer
Address of the buffer to receive data from the I2C device.
Definition: I2cMaster.h:382
EFI_I2C_REQUEST_PACKET::WriteBytes
UINT32 WriteBytes
Number of bytes to send to the I2C device.
Definition: I2cMaster.h:364
_EFI_I2C_MASTER_PROTOCOL::MaximumTotalBytes
UINT32 MaximumTotalBytes
The maximum number of bytes in the I2C bus transaction.
Definition: I2cMaster.h:542
_EFI_I2C_MASTER_PROTOCOL::Reset
EFI_I2C_MASTER_RESET Reset
Reset the I2C host controller.
Definition: I2cMaster.h:520
EFI_I2C_MASTER_START_REQUEST
EFI_STATUS(* EFI_I2C_MASTER_START_REQUEST)(IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN SlaveAddress, IN EFI_EVENT Event OPTIONAL, IN CONST EFI_I2C_REQUEST_PACKET *RequestPacket, OUT EFI_STATUS *I2cStatus OPTIONAL)
Start an I2C operation on the host controller.
Definition: I2cMaster.h:496
EFI_I2C_MASTER_BUS_FREQUENCY_SET
EFI_STATUS(* EFI_I2C_MASTER_BUS_FREQUENCY_SET)(IN CONST EFI_I2C_MASTER_PROTOCOL *This, IN UINTN BusClockHertz)
Set the I2C controller bus clock frequency.
Definition: I2cMaster.h:415
EFI_I2C_REQUEST_PACKET::Timeout
UINT32 Timeout
Timeout for the I2C operation in 100 ns units.
Definition: I2cMaster.h:387
EFI_I2C_REQUEST_PACKET
I2C device operation.
Definition: I2cMaster.h:360
_EFI_I2C_MASTER_PROTOCOL
I2C controller mode protocol.
Definition: I2cMaster.h:511
_EFI_I2C_MASTER_PROTOCOL::MaximumTransmitBytes
UINT32 MaximumTransmitBytes
The maximum number of bytes the I2C host controller is able to send on the I2C bus.
Definition: I2cMaster.h:537
EFI_I2C_REQUEST_PACKET::WriteBuffer
UINT8 * WriteBuffer
Address of the buffer containing the data to send to the I2C device.
Definition: I2cMaster.h:375
_EFI_I2C_MASTER_PROTOCOL::StartRequest
EFI_I2C_MASTER_START_REQUEST StartRequest
Start an I2C transaction in controller mode on the host controller.
Definition: I2cMaster.h:525
_EFI_I2C_MASTER_PROTOCOL::BusFrequencySet
EFI_I2C_MASTER_BUS_FREQUENCY_SET BusFrequencySet
Set the clock frequency for the I2C bus.
Definition: I2cMaster.h:515
EFI_I2C_MASTER_RESET
VOID(* EFI_I2C_MASTER_RESET)(IN CONST EFI_I2C_MASTER_PROTOCOL *This)
Reset the I2C controller and configure it for use.
Definition: I2cMaster.h:433
EFI_I2C_REQUEST_PACKET::ReadBytes
UINT32 ReadBytes
Number of bytes to read, set to zero for write only operations.
Definition: I2cMaster.h:369
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: IccSetupData.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
IccSetupData.h File Reference

Go to the source code of this file.

Macros

#define ICC_SETUP_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file IccSetupData.h.


AlderLake Platform Sample Code: IccSetupData.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
IccSetupData.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _ICC_SETUP_DATA_H_
35 #define _ICC_SETUP_DATA_H_
36
37 #define MAX_UI_CLOCKS 2
38
39 #define CLOCK1 1
40
41 #define INTEL_ICC_GUID \
42 {0x64192dca, 0xd034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 }}
43
44 #define DONT_DISPLAY 0
45 #define DISPLAY 1
46
47 #define OPTION_DISABLED 0
48 #define OPTION_ENABLED 1
49
50 #define OPTION_LOCK_DEFAULT 0
51 #define OPTION_LOCK_ALL 1
52 #define OPTION_UNLOCK_ALL 2
53
54 #define ICC_SSC_NONE 0
55 #define ICC_SSC_UP 1
56 #define ICC_SSC_CENTER 2
57 #define ICC_SSC_DOWN 4
58
59 #define ICC_BCLK_REAL_TIME 0
60 #define ICC_BCLK_PERM_NO_WR 1
61
62 #define ICC_SETUP_DATA_C_NAME L"IccAdvancedSetupDataVar"
63
64 //
65 // Ensure proper structure formats
66 //
67 #pragma pack(1)
68
69 /**
70 Making any setup structure change after code frozen
71 will need to maintain backward compatibility, bump up
72 structure revision and update below history table\n
73 <b>Revision 1</b>: - Initial version.
74 **/
75 #define ICC_SETUP_DATA_REVISION 1
76
77 typedef struct _ICC_SETUP_DATA {
78 UINT16 Frequency;
79 UINT8 Spread;
80 UINT8 ShowFrequency;
81 UINT8 ShowSpread;
82 UINT8 ShowProfile;
83 UINT8 Profile;
84 UINT8 AllowAdvancedOptions;
85 } ICC_SETUP_DATA;
86
87 #pragma pack()
88
89 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: LifeCycleState.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Typedefs | Functions
LifeCycleState.h File Reference

Go to the source code of this file.

Typedefs

typedef EFI_STATUS(* GET_LIFE_CYCLE_STATE) (IN LIFE_CYCLE_STATE_PROTOCOL *This, OUT LIFE_CYCLE_STATE *LifeCycleState)
Retrieves life cycle state. More...

Functions

EFI_STATUS GetLifeCycleState (IN LIFE_CYCLE_STATE_PROTOCOL *This, OUT LIFE_CYCLE_STATE *LifeCycleState)
Retrieves life cycle state. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file LifeCycleState.h.

Typedef Documentation

◆ GET_LIFE_CYCLE_STATE

typedef EFI_STATUS( * GET_LIFE_CYCLE_STATE) (IN LIFE_CYCLE_STATE_PROTOCOL *This, OUT LIFE_CYCLE_STATE *LifeCycleState)

Retrieves life cycle state.

Parameters
[in] | This | Protocol instance pointer.
[out] | LifeCycleState | The life cycle state read from ME FW status.
Return values
EFI_SUCCESS The state was successfully retrived.

Definition at line 64 of file LifeCycleState.h.

Function Documentation

◆ GetLifeCycleState()

EFI_STATUS GetLifeCycleState | ( | IN LIFE_CYCLE_STATE_PROTOCOL * | This,
 |  | OUT LIFE_CYCLE_STATE * | LifeCycleState
 | ) |  |

Retrieves life cycle state.

Parameters
[in] | This | Protocol instance pointer.
[out] | LifeCycleState | The life cycle state read from ME FW status.
Return values
EFI_SUCCESS The state was successfully retrived.


AlderLake Platform Sample Code: LifeCycleState.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
LifeCycleState.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2016 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef LIFE_CYCLE_STATE_H_
35 #define LIFE_CYCLE_STATE_H_
36
37 #define LIFE_CYCLE_STATE_PROTOCOL_GUID \
38 { 0xf3c1138e, 0xcd89, 0x4e20, { 0x9e, 0x68, 0x25, 0xa6, 0x76, 0x95, 0xa5, 0x6a } }
39
40 #define LIFE_CYCLE_STATE_PROTOCOL_REVISION1 0x00000001
41
42 //*******************************************************
43 // LIFE_CYCLE_STATE
44 //*******************************************************
45 typedef enum {
46 StateManufacturing,
47 StateEndUser,
48 StateRnD,
49 StateCare
50 } LIFE_CYCLE_STATE;
51
52 typedef struct _LIFE_CYCLE_STATE_PROTOCOL LIFE_CYCLE_STATE_PROTOCOL;
53
54 /**
55 Retrieves life cycle state
56
57 @param[in] This Protocol instance pointer.
58 @param[out] LifeCycleState The life cycle state read from ME FW status.
59
60 @retval EFI_SUCCESS The state was successfully retrived.
61
62 **/
63 typedef
64 EFI_STATUS
65 (EFIAPI * GET_LIFE_CYCLE_STATE) (
66 IN LIFE_CYCLE_STATE_PROTOCOL *This,
67 OUT LIFE_CYCLE_STATE *LifeCycleState
68 );
69
70 #pragma pack(1)
71 struct _LIFE_CYCLE_STATE_PROTOCOL {
72 UINT32 Revision;
73 GET_LIFE_CYCLE_STATE GetLifeCycleState;
74 };
75 #pragma pack()
76
77 /**
78 Retrieves life cycle state
79
80 @param[in] This Protocol instance pointer.
81 @param[out] LifeCycleState The life cycle state read from ME FW status.
82
83 @retval EFI_SUCCESS The state was successfully retrived.
84
85 **/
86 EFI_STATUS
87 GetLifeCycleState (
88 IN LIFE_CYCLE_STATE_PROTOCOL *This,
89 OUT LIFE_CYCLE_STATE *LifeCycleState
90 );
91
92 extern EFI_GUID gLifeCycleStateProtocolGuid;
93
94 #endif
GetLifeCycleState
EFI_STATUS GetLifeCycleState(IN LIFE_CYCLE_STATE_PROTOCOL *This, OUT LIFE_CYCLE_STATE *LifeCycleState)
Retrieves life cycle state.
GET_LIFE_CYCLE_STATE
EFI_STATUS(* GET_LIFE_CYCLE_STATE)(IN LIFE_CYCLE_STATE_PROTOCOL *This, OUT LIFE_CYCLE_STATE *LifeCycleState)
Retrieves life cycle state.
Definition: LifeCycleState.h:65
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: MePolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
MePolicyInitDxe.c File Reference

This file is SampleCode for Intel ME DXE Policy initialization. More...

#include "MePolicyInitDxe.h"
Include dependency graph for MePolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS MePolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy. More...

Detailed Description

This file is SampleCode for Intel ME DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyInitDxe.c.

Function Documentation

◆ MePolicyInitDxe()

EFI_STATUS MePolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize ME DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file MePolicyInitDxe.c.

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AlderLake Platform Sample Code: MePolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
MePolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel ME DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "MePolicyInitDxe.h"
35
36 /**
37 Initialize ME DXE Policy
38
39 @param[in] ImageHandle Image handle of this driver.
40
41 @retval EFI_SUCCESS Initialization complete.
42 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
43 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
44 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
45 **/
46 EFI_STATUS
47 EFIAPI
48 MePolicyInitDxe (
49 IN EFI_HANDLE ImageHandle
50 )
51 {
52 EFI_STATUS Status;
53 ME_POLICY_PROTOCOL *MePolicyProtocol;
54
55 DEBUG ((DEBUG_INFO, "MePolicyInitDxe\n"));
56 //
57 // Call MeCreatePolicyDefaults to initialize platform policy structure
58 // and get all default policy settings.
59 //
60 Status = MeCreatePolicyDefaults (&MePolicyProtocol);
61 ASSERT_EFI_ERROR (Status);
62 if (EFI_ERROR (Status)) {
63 return Status;
64 }
65
66 UpdateDxeMePolicyBoardConfig (MePolicyProtocol);
67
68 if (mFirmwareConfiguration != FwConfigDefault) {
69 UpdateDxeMePolicy (MePolicyProtocol);
70 }
71 //
72 // Install MeInstallPolicyProtocol.
73 // While installed, RC assumes the Policy is ready and finalized. So please
74 // update and override any setting before calling this function.
75 //
76 Status = MeInstallPolicyProtocol (ImageHandle, MePolicyProtocol);
77 ASSERT_EFI_ERROR (Status);
78
79 return Status;
80 }
81
MePolicyInitDxe.h
Header file for the MePolicyInitDxe Driver.
UpdateDxeMePolicyBoardConfig
EFI_STATUS UpdateDxeMePolicyBoardConfig(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
This function performs DXE ME Policy update by board configuration.
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
UpdateDxeMePolicy
EFI_STATUS UpdateDxeMePolicy(IN OUT ME_POLICY_PROTOCOL *DxeMePolicy)
Update the ME Policy Library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: MePolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
MePolicyInitDxe.h File Reference

Header file for the MePolicyInitDxe Driver. More...

#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/MePolicy.h>
#include <Library/DxeMePolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeMePolicyUpdateLib.h>
Include dependency graph for MePolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | MePolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy. More...
VOID | HeciPlatformDebugCapabilityMsgCallback (IN EFI_EVENT Event, IN VOID *Context)
Checkes the HECI protocol and send MEI message. More...

Detailed Description

Header file for the MePolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyInitDxe.h.

Function Documentation

◆ HeciPlatformDebugCapabilityMsgCallback()

VOID HeciPlatformDebugCapabilityMsgCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Checkes the HECI protocol and send MEI message.

Parameters
[in] | Event | Event objext
[in] | *Context | VOID Pointer

◆ MePolicyInitDxe()

EFI_STATUS MePolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize ME DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 48 of file MePolicyInitDxe.c.

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AlderLake Platform Sample Code: MePolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
MePolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the MePolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _ME_POLICY_INIT_DXE_H_
35 #define _ME_POLICY_INIT_DXE_H_
36
37 #include <Library/IoLib.h>
38 #include <Library/PcdLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42
43 #include <Protocol/MePolicy.h>
44 #include <Library/DxeMePolicyLib.h>
45 #include <Library/DxePolicyBoardConfigLib.h>
46 #include <Library/DxeMePolicyUpdateLib.h>
47
48 extern UINT8 mFirmwareConfiguration;
49
50 /**
51 Initialize ME DXE Policy
52
53 @param[in] ImageHandle Image handle of this driver.
54
55 @retval EFI_SUCCESS Initialization complete.
56 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
57 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
58 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
59 **/
60 EFI_STATUS
61 EFIAPI
62 MePolicyInitDxe (
63 IN EFI_HANDLE ImageHandle
64 )
65 ;
66
67 /**
68 Checkes the HECI protocol and send MEI message
69
70 @param[in] Event Event objext
71 @param[in] *Context VOID Pointer
72
73 **/
74 VOID
75 EFIAPI
76 HeciPlatformDebugCapabilityMsgCallback (
77 IN EFI_EVENT Event,
78 IN VOID *Context
79 )
80 ;
81 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxeMePolicyUpdateLib.h
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
HeciPlatformDebugCapabilityMsgCallback
VOID HeciPlatformDebugCapabilityMsgCallback(IN EFI_EVENT Event, IN VOID *Context)
Checkes the HECI protocol and send MEI message.
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: MultiPlatSupport.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Classes | Macros | Enumerations
MultiPlatSupport.h File Reference

Go to the source code of this file.

Classes

struct | VARIABLE_STORE_HEADER
Variable Store region header. More...
struct | VARIABLE_HEADER
Single Variable Data Header Structure. More...
struct | AUTHENTICATED_VARIABLE_HEADER
Single Variable Data Header Structure for Auth variable. More...

Macros

#define | ALIGNMENT 1
Alignment of variable name and data, according to the architecture: More...
#define | HEADER_ALIGNMENT 4
Alignment of Variable Data Header in Variable Store region.
#define | VARIABLE_STORE_FORMATTED 0x5a
Variable Store Header Format and State.
#define | VARIABLE_DATA 0x55AA
Variable data start flag.
#define | VAR_IN_DELETED_TRANSITION 0xfe
Variable State flags. More...
#define | VAR_DELETED 0xfd
Variable is obsolete.
#define | VAR_HEADER_VALID_ONLY 0x7f
Variable header has been valid.
#define | VAR_ADDED 0x3f
Variable has been completely added.

Enumerations

enum VARIABLE_STORE_STATUS
Status of Variable Store Region.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file MultiPlatSupport.h.

Macro Definition Documentation

◆ ALIGNMENT

#define ALIGNMENT 1

Alignment of variable name and data, according to the architecture:

  • For IA-32 and Intel(R) 64 architectures: 1.
  • For IA-64 architecture: 8.

Definition at line 45 of file MultiPlatSupport.h.

◆ VAR_IN_DELETED_TRANSITION

#define VAR_IN_DELETED_TRANSITION 0xfe

Variable State flags.

Variable is in obsolete transition.

Definition at line 114 of file MultiPlatSupport.h.


AlderLake Platform Sample Code: MultiPlatSupport.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
MultiPlatSupport.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2013 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __MULTI_PLATFORM_SUPPORT_H__
35 #define __MULTI_PLATFORM_SUPPORT_H__
36
37 ///
38 /// Alignment of variable name and data, according to the architecture:
39 /// * For IA-32 and Intel(R) 64 architectures: 1.
40 /// * For IA-64 architecture: 8.
41 ///
42 #if defined (MDE_CPU_IPF)
43 #define ALIGNMENT 8
44 #else
45 #define ALIGNMENT 1
46 #endif
47
48 //
49 // GET_PAD_SIZE calculates the miminal pad bytes needed to make the current pad size satisfy the alignment requirement.
50 //
51 #if (ALIGNMENT == 1)
52 #define GET_PAD_SIZE(a) (0)
53 #else
54 #define GET_PAD_SIZE(a) (((~a) + 1) & (ALIGNMENT - 1))
55 #endif
56
57 ///
58 /// Alignment of Variable Data Header in Variable Store region.
59 ///
60 #define HEADER_ALIGNMENT 4
61 #define HEADER_ALIGN(Header) (((UINTN) (Header) + HEADER_ALIGNMENT - 1) & (~(HEADER_ALIGNMENT - 1)))
62
63 ///
64 /// Status of Variable Store Region.
65 ///
66 typedef enum {
67 EfiRaw,
68 EfiValid,
69 EfiInvalid,
70 EfiUnknown
71 } VARIABLE_STORE_STATUS;
72
73 #pragma pack(1)
74
75 ///
76 /// Variable Store Header Format and State.
77 ///
78 #define VARIABLE_STORE_FORMATTED 0x5a
79 #define VARIABLE_STORE_HEALTHY 0xfe
80
81 ///
82 /// Variable Store region header.
83 ///
84 typedef struct {
85 ///
86 /// Variable store region signature.
87 ///
88 EFI_GUID Signature;
89 ///
90 /// Size of entire variable store,
91 /// including size of variable store header but not including the size of FvHeader.
92 ///
93 UINT32 Size;
94 ///
95 /// Variable region format state.
96 ///
97 UINT8 Format;
98 ///
99 /// Variable region healthy state.
100 ///
101 UINT8 State;
102 UINT16 Reserved;
103 UINT32 Reserved1;
104 } VARIABLE_STORE_HEADER;
105
106 ///
107 /// Variable data start flag.
108 ///
109 #define VARIABLE_DATA 0x55AA
110
111 ///
112 /// Variable State flags.
113 ///
114 #define VAR_IN_DELETED_TRANSITION 0xfe ///< Variable is in obsolete transition.
115 #define VAR_DELETED 0xfd ///< Variable is obsolete.
116 #define VAR_HEADER_VALID_ONLY 0x7f ///< Variable header has been valid.
117 #define VAR_ADDED 0x3f ///< Variable has been completely added.
118
119 ///
120 /// Single Variable Data Header Structure.
121 ///
122 typedef struct {
123 ///
124 /// Variable Data Start Flag.
125 ///
126 UINT16 StartId;
127 ///
128 /// Variable State defined above.
129 ///
130 UINT8 State;
131 UINT8 Reserved;
132 ///
133 /// Attributes of variable defined in UEFI specification.
134 ///
135 UINT32 Attributes;
136 ///
137 /// Size of variable null-terminated Unicode string name.
138 ///
139 UINT32 NameSize;
140 ///
141 /// Size of the variable data without this header.
142 ///
143 UINT32 DataSize;
144 ///
145 /// A unique identifier for the vendor that produces and consumes this varaible.
146 ///
147 EFI_GUID VendorGuid;
148 } VARIABLE_HEADER;
149
150 ///
151 /// Single Variable Data Header Structure for Auth variable.
152 ///
153 typedef struct {
154 ///
155 /// Variable Data Start Flag.
156 ///
157 UINT16 StartId;
158 ///
159 /// Variable State defined above.
160 ///
161 UINT8 State;
162 UINT8 Reserved;
163 ///
164 /// Attributes of variable defined in UEFI specification.
165 ///
166 UINT32 Attributes;
167 ///
168 /// Associated monotonic count value against replay attack.
169 ///
170 UINT64 MonotonicCount;
171 ///
172 /// Associated TimeStamp value against replay attack.
173 ///
174 EFI_TIME TimeStamp;
175 ///
176 /// Index of associated public key in database.
177 ///
178 UINT32 PubKeyIndex;
179 ///
180 /// Size of variable null-terminated Unicode string name.
181 ///
182 UINT32 NameSize;
183 ///
184 /// Size of the variable data without this header.
185 ///
186 UINT32 DataSize;
187 ///
188 /// A unique identifier for the vendor that produces and consumes this varaible.
189 ///
190 EFI_GUID VendorGuid;
191 } AUTHENTICATED_VARIABLE_HEADER;
192
193 typedef struct {
194 UINT16 DefaultId;
195 UINT16 BoardId;
196 } DEFAULT_INFO;
197
198 typedef struct {
199 UINT16 Offset;
200 UINT8 Value;
201 } DATA_DELTA;
202
203 typedef struct {
204 //
205 // HeaderSize includes HeaderSize fields and DefaultInfo arrays
206 //
207 UINT16 HeaderSize;
208 //
209 // DefaultInfo arrays those have the same default setting.
210 //
211 DEFAULT_INFO DefaultInfo[1];
212 //
213 // Default data is stored as variable storage or the array of DATA_DELTA.
214 //
215 } DEFAULT_DATA;
216
217 #pragma pack()
218
219 #endif
VARIABLE_STORE_STATUS
VARIABLE_STORE_STATUS
Status of Variable Store Region.
Definition: MultiPlatSupport.h:66
VARIABLE_HEADER::DataSize
UINT32 DataSize
Size of the variable data without this header.
Definition: MultiPlatSupport.h:143
VARIABLE_HEADER::Attributes
UINT32 Attributes
Attributes of variable defined in UEFI specification.
Definition: MultiPlatSupport.h:135
AUTHENTICATED_VARIABLE_HEADER::StartId
UINT16 StartId
Variable Data Start Flag.
Definition: MultiPlatSupport.h:157
AUTHENTICATED_VARIABLE_HEADER
Single Variable Data Header Structure for Auth variable.
Definition: MultiPlatSupport.h:153
VARIABLE_STORE_HEADER::Format
UINT8 Format
Variable region format state.
Definition: MultiPlatSupport.h:97
VARIABLE_HEADER::State
UINT8 State
Variable State defined above.
Definition: MultiPlatSupport.h:130
VARIABLE_STORE_HEADER
Variable Store region header.
Definition: MultiPlatSupport.h:84
AUTHENTICATED_VARIABLE_HEADER::TimeStamp
EFI_TIME TimeStamp
Associated TimeStamp value against replay attack.
Definition: MultiPlatSupport.h:174
AUTHENTICATED_VARIABLE_HEADER::Attributes
UINT32 Attributes
Attributes of variable defined in UEFI specification.
Definition: MultiPlatSupport.h:166
AUTHENTICATED_VARIABLE_HEADER::DataSize
UINT32 DataSize
Size of the variable data without this header.
Definition: MultiPlatSupport.h:186
VARIABLE_STORE_HEADER::Size
UINT32 Size
Size of entire variable store, including size of variable store header but not including the size of ...
Definition: MultiPlatSupport.h:93
VARIABLE_HEADER::NameSize
UINT32 NameSize
Size of variable null-terminated Unicode string name.
Definition: MultiPlatSupport.h:139
VARIABLE_HEADER::StartId
UINT16 StartId
Variable Data Start Flag.
Definition: MultiPlatSupport.h:126
VARIABLE_STORE_HEADER::Signature
EFI_GUID Signature
Variable store region signature.
Definition: MultiPlatSupport.h:88
VARIABLE_HEADER
Single Variable Data Header Structure.
Definition: MultiPlatSupport.h:122
VARIABLE_HEADER::VendorGuid
EFI_GUID VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.
Definition: MultiPlatSupport.h:147
AUTHENTICATED_VARIABLE_HEADER::NameSize
UINT32 NameSize
Size of variable null-terminated Unicode string name.
Definition: MultiPlatSupport.h:182
AUTHENTICATED_VARIABLE_HEADER::VendorGuid
EFI_GUID VendorGuid
A unique identifier for the vendor that produces and consumes this varaible.
Definition: MultiPlatSupport.h:190
AUTHENTICATED_VARIABLE_HEADER::MonotonicCount
UINT64 MonotonicCount
Associated monotonic count value against replay attack.
Definition: MultiPlatSupport.h:170
VARIABLE_STORE_HEADER::State
UINT8 State
Variable region healthy state.
Definition: MultiPlatSupport.h:101
AUTHENTICATED_VARIABLE_HEADER::State
UINT8 State
Variable State defined above.
Definition: MultiPlatSupport.h:161
AUTHENTICATED_VARIABLE_HEADER::PubKeyIndex
UINT32 PubKeyIndex
Index of associated public key in database.
Definition: MultiPlatSupport.h:178
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: MultiPlatSupportLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
MultiPlatSupportLib.h File Reference

Go to the source code of this file.

Functions

EFI_STATUS | GetVariableFromHob (IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, OUT UINT32 *Attributes, OPTIONAL IN OUT UINTN *DataSize, OUT VOID *Data)
Get variable from default variable HOB. More...
EFI_STATUS | SetVariableToHob (IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, IN UINT32 *Attributes, OPTIONAL IN UINTN DataSize, IN VOID *Data)
Set variable to default variable HOB. More...
EFI_STATUS | CreateDefaultVariableHob (IN UINT16 DefaultId)
This function finds the matched default data and create GUID hob for it. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file MultiPlatSupportLib.h.

Function Documentation

◆ CreateDefaultVariableHob()

EFI_STATUS CreateDefaultVariableHob ( IN UINT16 DefaultId )

This function finds the matched default data and create GUID hob for it.

Parameters
[in] DefaultId - Specifies the type of defaults to retrieve.
Returns
EFI_SUCCESS - The matched default data is found.
EFI_NOT_FOUND - The matched default data is not found.
EFI_OUT_OF_RESOURCES - No enough resource to create HOB.

◆ GetVariableFromHob()

EFI_STATUS GetVariableFromHob | ( | IN CHAR16 * | VariableName,
 |  | IN EFI_GUID * | VendorGuid,
 |  | OUT UINT32 * | Attributes,
 |  | OPTIONAL IN OUT UINTN * | DataSize,
 |  | OUT VOID * | Data
 | ) |  |

Get variable from default variable HOB.

Parameters
[in] | VariableName | A Null-terminated string that is the name of the vendor's variable.
[in] | VendorGuid | A unique identifier for the vendor.
[out] | Attributes | If not NULL, a pointer to the memory location to return the attributes bitmask for the variable.
[in,out] | DataSize | On input, the size in bytes of the return Data buffer. On output the size of data returned in Data.
[out] | Data | The buffer to return the contents of the variable.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The variable was not found.
EFI_BUFFER_TOO_SMALL | The DataSize is too small for the result.
EFI_INVALID_PARAMETER | VariableName is NULL.
EFI_INVALID_PARAMETER | VendorGuid is NULL.
EFI_INVALID_PARAMETER | DataSize is NULL.
EFI_INVALID_PARAMETER | The DataSize is not too small and Data is NULL.

◆ SetVariableToHob()

EFI_STATUS SetVariableToHob | ( | IN CHAR16 * | VariableName,
 |  | IN EFI_GUID * | VendorGuid,
 |  | IN UINT32 * | Attributes,
 |  | OPTIONAL IN UINTN | DataSize,
 |  | IN VOID * | Data
 | ) |  |

Set variable to default variable HOB.

Parameters
[in] | VariableName | A Null-terminated string that is the name of the vendor's variable.
[in] | VendorGuid | A unique identifier for the vendor.
[in] | Attributes | If not NULL, a pointer to the memory location to set the attributes bitmask for the variable.
[in] | DataSize | On input, the size in bytes of the return Data buffer. On output the size of data returned in Data.
[in] | Data | The buffer to return the contents of the variable.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | The variable was not found.
EFI_INVALID_PARAMETER | VariableName is NULL.
EFI_INVALID_PARAMETER | VendorGuid is NULL.
EFI_INVALID_PARAMETER | Attributes is not NULL, but attributes value is 0.
EFI_INVALID_PARAMETER | DataSize is not equal to the variable data size.
EFI_INVALID_PARAMETER | The DataSize is equal to the variable data size, but Data is NULL.


AlderLake Platform Sample Code: MultiPlatSupportLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
MultiPlatSupportLib.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2012 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _MULTI_PLATFORM_SUPPORT_LIB_H_
35 #define _MULTI_PLATFORM_SUPPORT_LIB_H_
36
37 /**
38 Get variable from default variable HOB.
39
40 @param[in] VariableName A Null-terminated string that is the name of the vendor's
41 variable.
42 @param[in] VendorGuid A unique identifier for the vendor.
43 @param[out] Attributes If not NULL, a pointer to the memory location to return the
44 attributes bitmask for the variable.
45 @param[in, out] DataSize On input, the size in bytes of the return Data buffer.
46 On output the size of data returned in Data.
47 @param[out] Data The buffer to return the contents of the variable.
48
49 @retval EFI_SUCCESS The function completed successfully.
50 @retval EFI_NOT_FOUND The variable was not found.
51 @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result.
52 @retval EFI_INVALID_PARAMETER VariableName is NULL.
53 @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
54 @retval EFI_INVALID_PARAMETER DataSize is NULL.
55 @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL.
56
57 **/
58 EFI_STATUS
59 EFIAPI
60 GetVariableFromHob (
61 IN CHAR16 *VariableName,
62 IN EFI_GUID *VendorGuid,
63 OUT UINT32 *Attributes, OPTIONAL
64 IN OUT UINTN *DataSize,
65 OUT VOID *Data
66 );
67
68 /**
69 Set variable to default variable HOB.
70
71 @param[in] VariableName A Null-terminated string that is the name of the vendor's
72 variable.
73 @param[in] VendorGuid A unique identifier for the vendor.
74 @param[in] Attributes If not NULL, a pointer to the memory location to set the
75 attributes bitmask for the variable.
76 @param[in] DataSize On input, the size in bytes of the return Data buffer.
77 On output the size of data returned in Data.
78 @param[in] Data The buffer to return the contents of the variable.
79
80 @retval EFI_SUCCESS The function completed successfully.
81 @retval EFI_NOT_FOUND The variable was not found.
82 @retval EFI_INVALID_PARAMETER VariableName is NULL.
83 @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
84 @retval EFI_INVALID_PARAMETER Attributes is not NULL, but attributes value is 0.
85 @retval EFI_INVALID_PARAMETER DataSize is not equal to the variable data size.
86 @retval EFI_INVALID_PARAMETER The DataSize is equal to the variable data size, but Data is NULL.
87
88 **/
89 EFI_STATUS
90 EFIAPI
91 SetVariableToHob (
92 IN CHAR16 *VariableName,
93 IN EFI_GUID *VendorGuid,
94 IN UINT32 *Attributes, OPTIONAL
95 IN UINTN DataSize,
96 IN VOID *Data
97 );
98
99 /**
100 This function finds the matched default data and create GUID hob for it.
101
102 @param[in] DefaultId - Specifies the type of defaults to retrieve.
103
104 @return EFI_SUCCESS - The matched default data is found.
105 @return EFI_NOT_FOUND - The matched default data is not found.
106 @return EFI_OUT_OF_RESOURCES - No enough resource to create HOB.
107
108 **/
109 EFI_STATUS
110 EFIAPI
111 CreateDefaultVariableHob (
112 IN UINT16 DefaultId
113 );
114
115 #endif
CreateDefaultVariableHob
EFI_STATUS CreateDefaultVariableHob(IN UINT16 DefaultId)
This function finds the matched default data and create GUID hob for it.
GetVariableFromHob
EFI_STATUS GetVariableFromHob(IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, OUT UINT32 *Attributes, OPTIONAL IN OUT UINTN *DataSize, OUT VOID *Data)
Get variable from default variable HOB.
SetVariableToHob
EFI_STATUS SetVariableToHob(IN CHAR16 *VariableName, IN EFI_GUID *VendorGuid, IN UINT32 *Attributes, OPTIONAL IN UINTN DataSize, IN VOID *Data)
Set variable to default variable HOB.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: OemSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
OemSetup.h File Reference

OEM Specific Setup Variables and Structures. More...

#include <PchLimits.h>
#include <CpuPcieInfo.h>
Include dependency graph for OemSetup.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | SETUP_VOLATILE_DATA_REVISION 11
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | SETUP_CPU_FEATURES_REVISION 7
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | OS_PROFILE_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

OEM Specific Setup Variables and Structures.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OemSetup.h.

Macro Definition Documentation

◆ SETUP_CPU_FEATURES_REVISION

#define SETUP_CPU_FEATURES_REVISION 7

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Removed SgxSupported Revision 3: - Add NumSmallCores support Revision 4: - Added PerCore HT Disable Revision 5: - Added TmeSupported support Revision 6: - Added GT Unslice supported Revision 7: - Added IsFastMsrHwpSupport

Definition at line 152 of file OemSetup.h.

◆ SETUP_VOLATILE_DATA_REVISION

#define SETUP_VOLATILE_DATA_REVISION 11

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Remove Item EnableDebugSerialIoUartNumber Revision 3: - Added Item PSOnSupported Revision 4: - Move Board related variables to SETUP_DATA Revision 5: - Added OcrBootHttpsSupported, OcrBootPbaSupported, OcrBootWinReSupported, and OcrAmtDisSecBootSupported Revision 6: - Deprecate TbtVtdBaseSecurityGrayOut. Revision 7: - Added TcssPdType Revision 8: - Added TotalNumberOfTypeCPortsSupported Revision 9: - Added MobileOcUnSupport Revision 10: - Added AudioDspFusedOut Revision 11: - Added UsbcEcPdNegotiation

Definition at line 89 of file OemSetup.h.


AlderLake Platform Sample Code: OemSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
OemSetup.h
Go to the documentation of this file.
1 /** @file
2 OEM Specific Setup Variables and Structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _OEMSETUP_H_
36 #define _OEMSETUP_H_
37
38 #include <PchLimits.h>
39 #include <CpuPcieInfo.h>
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 // OS profile
46 #define OS_PROFILE_GUID \
47 { 0xE59376D7, 0x2DD9, 0x42A3, { 0x9E, 0xC8, 0x1D, 0x71, 0xD5, 0xE3, 0xC1, 0xEC }}
48
49 // Currently enumerated OSes
50 #define OsNone 0x00
51 #define OsAndroid 0x01
52 #define OsWinCs 0x02
53 #define OsWinNonCs 0x03
54 #define OsMax 0x04
55
56 #define PCH_MOBILE_SKU 0
57 #define PCH_DESKTOP_SKU 1
58 #define PCH_SERVER_SKU 2
59
60 #define PCH_RP_AVAILABLE 0
61 #define PCH_RP_FUSED_OFF 1
62 #define PCH_RP_MERGED 2
63 #define PCH_RP_DIFFERENT_BUS 3
64 #define PCH_RP_NOT_IMPLEMENTED 5
65
66 #define CPU_PCIE_RP_AVAILABLE 0
67 #define CPU_PCIE_RP_FUSED_OFF 1
68 #define PCH_TSN_GBE_LANE6 6
69 #define PCH_TSN_GBE_LANE7 7
70 #pragma pack(1)
71
72 /**
73 Making any setup structure change after code frozen
74 will need to maintain backward compatibility, bump up
75 structure revision and update below history table\n
76 Revision 1: - Initial version.
77 <b>Revision 2</b>: - Remove Item EnableDebugSerialIoUartNumber
78 <b>Revision 3</b>: - Added Item PSOnSupported
79 <b>Revision 4</b>: - Move Board related variables to SETUP_DATA
80 <b>Revision 5</b>: - Added OcrBootHttpsSupported, OcrBootPbaSupported, OcrBootWinReSupported, and OcrAmtDisSecBootSupported
81 <b>Revision 6</b>: - Deprecate TbtVtdBaseSecurityGrayOut.
82 <b>Revision 7</b>: - Added TcssPdType
83 <b>Revision 8</b>: - Added TotalNumberOfTypeCPortsSupported
84 <b>Revision 9</b>: - Added MobileOcUnSupport
85 <b>Revision 10</b>: - Added AudioDspFusedOut
86 <b>Revision 11</b>: - Added UsbcEcPdNegotiation
87 **/
88
89 #define SETUP_VOLATILE_DATA_REVISION 11
90
91
92 typedef struct _SETUP_VOLATILE_DATA
93 {
94 UINT16 PlatId;
95 UINT8 PlatformFlavor;
96 UINT8 PlatformType;
97 UINT8 BoardType;
98 UINT8 VTdAvailable;
99 UINT8 PchGeneration;
100 UINT8 GbeSupportByPch; // Gbe is supported on current PCH
101 UINT8 GbeAvailable; // Gbe is configured and usable
102 UINT8 ThcSupported;
103 UINT8 ThcAvailable;
104 UINT8 IshAvailable;
105 UINT8 DimmPresent[16];
106 UINT8 MemoryType; // 0 - DDR4, 1 - DDR5, 2 - LPDDR5, 3 - LPDDR4, 4 - UnKnown
107 UINT8 PciePortCfg[PCH_MAX_PCIE_ROOT_PORTS];
108 UINT8 PchUsb2PortCount;
109 UINT8 PchUsb3PortCount;
110 UINT8 CpuPciePortCfg[CPU_PCIE_MAX_ROOT_PORTS];
111 UINT8 EmmcSupported;
112 UINT8 UfsSupported[PCH_MAX_UFS_DEV_NUM];
113 UINT32 AcpiDebugAddress;
114 UINT8 SataMpsPresent[8];
115 UINT8 DockAttached;
116 UINT8 AudioHdaLinkSupported;
117 UINT8 AudioDmicLinkSupported[PCH_MAX_HDA_DMIC_LINK_NUM];
118 UINT8 AudioSspLinkSupported[PCH_MAX_HDA_SSP_LINK_NUM];
119 UINT8 AudioSndwLinkSupported[PCH_MAX_HDA_SNDW_LINK_NUM];
120 UINT8 PchCridSupport;
121 UINT8 IpuSupport;
122 UINT8 TbtVtdBaseSecurityGrayOut; // Deprecated from Revision 6.
123 UINT8 CdClockSelector;
124 UINT8 TsnSupportByPch;
125 UINT8 TsnAvailable;
126 UINT8 PSOnSupported;
127 UINT8 TsnGbeLaneNum;
128 UINT8 OcrBootHttpsSupported;
129 UINT8 OcrBootPbaSupported;
130 UINT8 OcrBootWinReSupported;
131 UINT8 OcrAmtDisSecBootSupported;
132 UINT8 TcssPdType;
133 UINT8 TotalNumberOfTypeCPortsSupported;
134 UINT8 MobileOcUnSupport;
135 UINT8 AudioDspFusedOut;
136 UINT8 UsbcEcPdNegotiation;
137 } SETUP_VOLATILE_DATA;
138
139 /**
140 Making any setup structure change after code frozen
141 will need to maintain backward compatibility, bump up
142 structure revision and update below history table\n
143 <b>Revision 1</b>: - Initial version.
144 <b>Revision 2</b>: - Removed SgxSupported
145 <b>Revision 3</b>: - Add NumSmallCores support
146 <b>Revision 4</b>: - Added PerCore HT Disable
147 <b>Revision 5</b>: - Added TmeSupported support
148 <b>Revision 6</b>: - Added GT Unslice supported
149 <b>Revision 7</b>: - Added IsFastMsrHwpSupport
150 **/
151
152 #define SETUP_CPU_FEATURES_REVISION 7
153
154 //This structure is used for setup.
155 typedef struct {
156 UINT8 XDBitAvailable;
157 UINT8 TurboModeAvailable;
158 UINT8 XETdcTdpLimitAvailable;
159 UINT8 CoreRatioLimitAvailable;
160 UINT8 HTAvailable;
161 UINT8 MultiCoreAvailable;
162 UINT8 VTAvailable;
163 UINT8 AESAvailable;
164 UINT8 TXTAvailable;
165 UINT8 CxAvailable;
166 UINT8 C1Available;
167 UINT8 C1EAvailable;
168 UINT8 C3Available;
169 UINT8 C6Available;
170 UINT8 C7Available;
171 UINT8 C8Available;
172 UINT8 C9Available;
173 UINT8 C10Available;
174 UINT8 EISTAvailable;
175 UINT8 HwpAvailable;
176 UINT8 ItbmAvailable;
177 UINT8 NumCores;
178 UINT8 MultiSocketAvailable;
179 UINT8 MultiSocketPopulated;
180 UINT8 LocalX2ApicAvailable;
181 UINT8 EnergyEfficientTurboAvailable;
182 UINT8 Reserved;
183 UINT8 C6DramSupported;
184 UINT8 ApicIdFlag;
185 UINT8 ConfigTdpAvailable;
186 UINT8 PpinFeatureAvailable;
187 UINT8 LpmAvailable;
188 UINT8 TimedMwaitSupported;
189 UINT8 DebugInterfaceSupported;
190 UINT8 ProcTraceSupported;
191 UINT8 SmmEnhancementSupported;
192 UINT8 SmmTargetedSmiAvailable;
193 UINT8 SmmCpuSvrstrAvailable;
194 UINT8 SmmLongFlowAvailable;
195 UINT8 HdcSupported;
196 UINT8 HwpInterruptSupported;
197 UINT8 CtdpDownSupported;
198 UINT8 CtdpUpSupported;
199 UINT8 FivrSupported;
200 UINT8 FclkSupported;
201 UINT8 NumSmallCores;
202 UINT8 PerCoreHtDisableSupported;
203 UINT8 GtUnsliceSupported;
204 UINT8 CpuSkuOcSupported;
205 UINT8 TmeSupported;
206 BOOLEAN SaVrSupport;
207 UINT8 IsFastMsrHwpSupport;
208 } SETUP_CPU_FEATURES;
209
210 /**
211 Making any setup structure change after code frozen
212 will need to maintain backward compatibility, bump up
213 structure revision and update below history table\n
214 <b>Revision 1</b>: - Initial version.
215 **/
216 #define OS_PROFILE_REVISION 1
217
218 typedef struct {
219 UINT8 OsProfile;
220 UINT8 PrevOs;
221 } OS_PROFILE;
222
223 #pragma pack()
224
225 /****** DO NOT WRITE BELOW THIS LINE *******/
226 #ifdef __cplusplus
227 }
228 #endif
229 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: OverClockPpi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
OverClockPpi.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OverClockPpi.h.


AlderLake Platform Sample Code: OverClockPpi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
OverClockPpi.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2010 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PEI_OVERCLOCKING_PPI_H
35 #define _PEI_OVERCLOCKING_PPI_H
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #ifdef __cplusplus
41 }
42 #endif
43 #endif
44
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PchPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
PchPolicyInitDxe.c File Reference

This file is SampleCode for PCH DXE Policy initialization. More...

#include "PchPolicyInitDxe.h"
Include dependency graph for PchPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS PchPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy. More...

Detailed Description

This file is SampleCode for PCH DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicyInitDxe.c.

Function Documentation

◆ PchPolicyInitDxe()

EFI_STATUS PchPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize PCH DXE Policy.

PCH DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 51 of file PchPolicyInitDxe.c.


AlderLake Platform Sample Code: PchPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
PchPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for PCH DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PchPolicyInitDxe.h"
35
36 //
37 // Function implementations
38 //
39
40 /**
41 Initialize PCH DXE Policy
42
43 @param[in] ImageHandle Image handle of this driver.
44
45 @retval EFI_SUCCESS Initialization complete.
46 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
47 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
48 **/
49 EFI_STATUS
50 EFIAPI
51 PchPolicyInitDxe (
52 IN EFI_HANDLE ImageHandle
53 )
54 {
55 EFI_STATUS Status;
56 PCH_POLICY_PROTOCOL *PchPolicy;
57
58 //
59 // Call CreatePchDxeConfigBlocks to create & initialize platform policy structure
60 // and get all Intel default policy settings.
61 //
62 Status = CreatePchDxeConfigBlocks (&PchPolicy);
63 DEBUG ((DEBUG_INFO, "PchPolicy->TableHeader.NumberOfBlocks = 0x%x\n", PchPolicy->TableHeader.NumberOfBlocks));
64 ASSERT_EFI_ERROR (Status);
65
66 if (mFirmwareConfiguration != FwConfigDefault) {
67 UpdateDxePchPolicy (PchPolicy);
68 }
69
70 //
71 // Install PchInstallPolicyProtocol.
72 // While installed, RC assumes the Policy is ready and finalized. So please
73 // update and override any setting before calling this function.
74 //
75 Status = PchInstallPolicyProtocol (ImageHandle, PchPolicy);
76 ASSERT_EFI_ERROR (Status);
77
78 return Status;
79 }
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy.
Definition: PchPolicyInitDxe.c:51
PchPolicyInitDxe.h
Header file for the PchPolicyInitDxe Driver.
UpdateDxePchPolicy
EFI_STATUS UpdateDxePchPolicy(IN OUT PCH_POLICY_PROTOCOL *PchPolicy)
Get data for platform policy from setup options.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PchPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
PchPolicyInitDxe.h File Reference

Header file for the PchPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/PchPolicy.h>
#include <Library/DxePchPolicyLib.h>
#include <Library/DxePchPolicyUpdateLib.h>
Include dependency graph for PchPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS PchPolicyInitDxe (IN EFI_HANDLE ImageHandle)
PCH DXE Policy Driver Entry Point
More...

Detailed Description

Header file for the PchPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicyInitDxe.h.

Function Documentation

◆ PchPolicyInitDxe()

EFI_STATUS PchPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

PCH DXE Policy Driver Entry Point

  • Introduction
    Pch DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to PCH initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

PCH DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS | Initialization complete.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 51 of file PchPolicyInitDxe.c.


AlderLake Platform Sample Code: PchPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
PchPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PchPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PCH_POLICY_INIT_DXE_H_
35 #define _PCH_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/PchPolicy.h>
43 #include <Library/DxePchPolicyLib.h>
44 #include <Library/DxePchPolicyUpdateLib.h>
45
46 extern UINT8 mFirmwareConfiguration;
47
48 /**
49 <b>PCH DXE Policy Driver Entry Point</b> \n
50 - <b>Introduction</b> \n
51 Pch DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
52 Platform policy Protocol is initialized with default settings in this funciton.
53 This policy Protocol has to be initialized prior to PCH initialization DXE drivers execution.
54
55 - @pre
56 - Runtime variable service should be ready if policy initialization required.
57
58 - @result
59 PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch reference code use.
60
61 - <b>Porting Recommendations</b> \n
62 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
63
64 @param[in] ImageHandle - Image handle of this driver.
65
66 @retval EFI_SUCCESS Initialization complete.
67 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
68 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
69 **/
70 EFI_STATUS
71 EFIAPI
72 PchPolicyInitDxe (
73 IN EFI_HANDLE ImageHandle
74 );
75
76 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxePchPolicyUpdateLib.h
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
PCH DXE Policy Driver Entry Point
Definition: PchPolicyInitDxe.c:51
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PciBusSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
PciBusSetup.h File Reference

Go to the source code of this file.

Macros

#define PCI_BUS_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PciBusSetup.h.


AlderLake Platform Sample Code: PciBusSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PciBusSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PCI_BUS_SETUP_H_
35 #define _PCI_BUS_SETUP_H_
36
37 #pragma pack(1)
38
39 #define PCI_BUS_SETUP_VARSTORE\
40 efivarstore PCI_BUS_SETUP, \
41 attribute = 0x7, \
42 name = PciBusSetup, \
43 guid = SETUP_GUID;
44
45 /**
46 Making any setup structure change after code frozen
47 will need to maintain backward compatibility, bump up
48 structure revision and update below history table\n
49 <b>Revision 1</b>: - Initial version.
50 **/
51 #define PCI_BUS_SETUP_REVISION 1
52
53 typedef struct {
54 UINT8 InstallExtOpRom;
55 } PCI_BUS_SETUP;
56 #endif
57
58
59 #pragma pack()
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PcieDockSmi.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PcieDockSmi.c File Reference
#include <Library/IoLib.h>
#include <Library/PciSegmentLib.h>
#include "PlatformInitAdvancedSmm.h"
#include "PcieDockSmi.h"
Include dependency graph for PcieDockSmi.c:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PcieDockSmi.c.


AlderLake Platform Sample Code: PcieDockSmi.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PcieDockSmi.c
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2018 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #include <Library/IoLib.h>
35 #include <Library/PciSegmentLib.h>
36 #include "PlatformInitAdvancedSmm.h"
37 #include "PcieDockSmi.h"
38
39 //Assign resources to saddlestring downstream bridges
40 VOID
41 AssignSaddleStringResources (
42 VOID
43 )
44 {
45
46 UINT32 VenDev_id1;
47 UINT32 VenDev_id2;
48 UINT16 IoBaseLimit;
49 UINT16 BaseLimit16;
50 UINT32 MemBaseLimit;
51 UINT32 PfmBaseLimit;
52 UINT32 BaseLimit32;
53 UINT32 PfmBaseLimit32;
54 UINT32 BusNumber32;
55 UINT32 SecBusNum;
56 UINT32 SecBusNum1;
57 UINT32 SecBusNum2;
58 UINT32 EndBusNum;
59 UINT32 EndBusNum2;
60 UINTN DevIndex;
61 UINT8 Command8;
62 UINT8 BusWidth8;
63 UINT16 Dev_id;
64 UINT32 i;
65 UINT64 PCIControlBase;
66
67 BusWidth8 = 1;
68
69 //
70 // Check if PEG (0,1,0) is populated
71 //
72 VenDev_id2 = 0;
73 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1, 0, 0)) != 0xFFFF) {
74 //
75 // Checking for the Turbo dock. Turbo dock has PLX 8547 for the PEG. 8547 sits on the Bus 0, dev1, fun 0.
76 //
77 BusNumber32 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1, 0, 0x18));
78
79 SecBusNum1 = (BusNumber32 >> 8) & 0xFF; // Get Secondary Bus Number
80
81 // Read the vendor id to check for the PLX8547 on Secbusnum, dev 0 and func 0
82 VenDev_id2 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum1, 0, 0, 0));
83
84
85 // Read the bus numbers for the PLX8547 device
86 BusNumber32 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum1, 0, 0, 0x18));
87 SecBusNum2 = (BusNumber32 >> 8) & 0xFF; // Get Secondary Bus Number
88 EndBusNum2 = (BusNumber32 >> 16) & 0xFF; // Get Subordinary Bus Number
89
90 // Fix for the PLX8547 NVidia.
91 // Enable only VC0 in the PCI reg 0x114 if NVidia card.
92 if (VenDev_id2 == TURBODOCK_PLX_DEVID) { //if there is Turbo dock device
93 for (i=SecBusNum2; i<=EndBusNum2; i++) {
94 Dev_id = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, i, 0, 0, 2));
95 if (Dev_id == 0x0191) { //If dev id is for NVidia card.
96 PCIControlBase = PCI_SEGMENT_LIB_ADDRESS (0, i, 0, 0, 0x114);
97 PciSegmentWrite32 (PCIControlBase, 0x80000001);
98 }
99 }
100 }
101 }
102
103 //
104 // Get PCIe Root Port 7 Bus Number Register
105 //
106 BusNumber32 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1C, 6, 0x18));
107
108 SecBusNum = (BusNumber32 >> 8) & 0xFF; // Get Secondary Bus Number
109 EndBusNum = (BusNumber32 >> 16) & 0xFF; // Get Subordinary Bus Number
110
111 // Turbo dock - 7 or more buses will execute resource allocation
112 if(VenDev_id2 == TURBODOCK_PLX_DEVID) {
113 if (EndBusNum - SecBusNum < 7) { // If bus width not enough
114 return; // Skip Resource Setting
115 }
116 } else { // Saddle string - 6 or more buses will execute resource allocation
117 if (EndBusNum - SecBusNum < 6) { // If bus width not enough
118 return; // Skip Resource Setting
119 }
120 }
121
122 VenDev_id1 = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0));
123
124 if ((VenDev_id1 != SADDLESTRINGS_PLX_DEVID) && (VenDev_id2 != TURBODOCK_PLX_DEVID)) { //if there is no saddlestring or Turbo dock device, return
125 return;
126 }
127
128 //
129 // Set PCIe dock first level Bridge Bus Number Register
130 //
131 BusNumber32 = SecBusNum + ((SecBusNum + 1) << 8) + (EndBusNum << 16);
132 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x18), 0, BusNumber32);
133
134 //
135 // Get PCIe Root Port 7 I/O Base & Limit Register
136 //
137 IoBaseLimit = PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1C, 6, 0x1C));
138
139 //
140 // Set PCIe dock first level Bridge I/O Base & Limit Register
141 //
142 PciSegmentAndThenOr16 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x1C), 0, IoBaseLimit);
143 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x30), 0, 0); // I/O Base/Limit Upper 16 Bits Regs
144
145 //
146 // Get PCIe Root Port 7 MEM Base & Limit Register
147 //
148 MemBaseLimit = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1C, 6, 0x20));
149
150 //
151 // Set PCIe dock first level Bridge MEM BAR0
152 //
153 BaseLimit32 = (MemBaseLimit & 0xFFFF0000); // Set top 1M MEM for BAR0
154 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x10), 0, BaseLimit32);
155
156 //
157 // Set PCIe dock first level Bridge MEM Base & Limit Register
158 //
159 MemBaseLimit -= 0x100000; // Exclude the top 1M MEM Range
160 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x20), 0, MemBaseLimit);
161
162 //
163 // Get PCIe Root Port 7 Prefetchable MEM Base & Limit Register
164 //
165 PfmBaseLimit = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (0, 0, 0x1C, 6, 0x24));
166
167 //
168 // Set PCIe dock first level Bridge Prefetchable MEM Base & Limit Register
169 //
170 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x24), 0, PfmBaseLimit);
171
172 //
173 // Set PCIe dock first level Bridge Command Register
174 //
175 Command8 = 7;
176 PciSegmentAndThenOr8 (PCI_SEGMENT_LIB_ADDRESS (0, SecBusNum, 0, 0, 0x04), 0, Command8);
177
178 //
179 // Set resource for PCIe dock 2nd level Bridge
180 //
181 if(VenDev_id2 == TURBODOCK_PLX_DEVID) {
182 //
183 // Turbo dock dev 1 & dev 2 has 2 buses each.
184 //
185 BusNumber32 = (BusNumber32 & 0xFFFF) + 0x0001 + ((SecBusNum + 2) << 16);
186 BusWidth8 = 2;
187 } else if ((VenDev_id2 != TURBODOCK_PLX_DEVID) && (VenDev_id1 == SADDLESTRINGS_PLX_DEVID)) {
188 BusNumber32 = (BusNumber32 & 0xFFFF) + 0x0001 + ((SecBusNum + 1) << 16);
189 BusWidth8 = 1;
190 }
191
192 BaseLimit16 = IoBaseLimit & 0x00FF; // Get RP1 I/O Base Register
193 BaseLimit16 += BaseLimit16 << 8; // Set first 4K I/O Range
194
195 BaseLimit32 = MemBaseLimit & 0x0000FFFF; // Get RP1 MEM Base Register
196 BaseLimit32 += (BaseLimit32 << 16) + 0x300000; // Set first 4M MEM Range
197
198 PfmBaseLimit32 = PfmBaseLimit & 0x0000FFFF; // Get RP1 Prefetchable MEM Base Register
199 PfmBaseLimit32 += (PfmBaseLimit32 << 16) + 0x300000; // Set first 4M Prefetchable MEM Range
200
201 for (DevIndex = 0; DevIndex <= 9; DevIndex ++) {
202 //
203 // Check if the 2nd level Bridges exist
204 //
205 if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x00)) != 0xFFFF) {
206 //
207 // I/O Base & Limit Register
208 //
209 PciSegmentAndThenOr16 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x1C), 0, BaseLimit16);
210 //
211 // I/O Base/Limit Upper 16 Bits Register
212 //
213 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x30), 0, 0);
214 //
215 // Set next 4K I/O Range
216 //
217 if (BaseLimit16 < IoBaseLimit) {
218 BaseLimit16 += 0x01010;
219 }
220
221 //
222 // MEM Base & Limit Register
223 //
224 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x20), 0, BaseLimit32);
225 //
226 // Set next 4M MEM Range
227 //
228 if (BaseLimit32 + 0x400000 < MemBaseLimit) {
229 BaseLimit32 += 0x00400040;
230 } else {
231 //
232 // Last remained MEM Range
233 //
234 BaseLimit32 = ((BaseLimit32 + 0x40) & 0xFFFF) + (MemBaseLimit & 0xFFFF0000);
235 }
236
237 //
238 // Prefetchable MEM Base & Limit register
239 //
240 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x24), 0, PfmBaseLimit32);
241 //
242 // Set next 4M Prefetchable MEM Range
243 //
244 if (PfmBaseLimit32 + 0x400000 < PfmBaseLimit) {
245 PfmBaseLimit32 += 0x00400040;
246 } else {
247 //
248 // Last remained MEM Range
249 //
250 PfmBaseLimit32 = ((BaseLimit32 + 0x40) & 0xFFFF) + (PfmBaseLimit & 0xFFFF0000);
251 }
252
253 //
254 // Secondary Bus Range
255 //
256 BusNumber32 += (BusWidth8 << 8);
257 if (VenDev_id2 == TURBODOCK_PLX_DEVID) {
258 //
259 // in case of turbo dock, device 1& 2 has 2 buses
260 //
261 BusWidth8 = (DevIndex >= 2)? 1 : 2;
262 } else if ((VenDev_id2 != TURBODOCK_PLX_DEVID) && (VenDev_id1 == SADDLESTRINGS_PLX_DEVID)) {
263 //
264 // in case of Saddle string, Only 3rd downstream gets 2
265 //
266 BusWidth8 = (DevIndex == 7)? 2 : 1;
267 }
268 //
269 // Set Subordinate Bus Number
270 //
271 BusNumber32 += (BusWidth8 << 16);
272 //
273 // Set Bus Number Register
274 //
275 PciSegmentAndThenOr32 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x18), 0, BusNumber32);
276
277 //
278 // Set Command Register
279 //
280 PciSegmentAndThenOr8 (PCI_SEGMENT_LIB_ADDRESS (0, (SecBusNum + 1), (UINT32)DevIndex, 0, 0x04), 0, Command8);
281 }
282 }
283
284 IoWrite32 (0x80, 0x4DCE); // Display port 80h with value 4DCEh
285 }
286
287 EFI_STATUS
288 EFIAPI
289 PcieDockSmiCallback (
290 IN EFI_HANDLE DispatchHandle,
291 IN CONST VOID *DispatchContext,
292 IN OUT VOID *CommBuffer OPTIONAL,
293 IN UINTN *CommBufferSize OPTIONAL
294 )
295 /*++
296
297 Routine Description:
298
299 Dispatch function for a PCIe Dock Bridge Resource Patch SMI handler.
300
301 Arguments:
302
303 DispatchHandle - Handle of this dispatch function
304 DispatchContext - Pointer to the dispatch function's context.
305 The DispatchContext fields are filled in by the dispatching driver
306 prior to invoke this dispatch function
307
308 Returns:
309
310 None
311
312 --*/
313 {
314 AssignSaddleStringResources();
315
316 return EFI_SUCCESS;
317 }
PlatformInitAdvancedSmm.h
Header file for the Platform Advanced SMM Driver.
PcieDockSmi.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PcieDockSmi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PcieDockSmi.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PcieDockSmi.h.


AlderLake Platform Sample Code: PcieDockSmi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PcieDockSmi.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PCIE_DOCK_SMI_H_
35 #define _PCIE_DOCK_SMI_H_
36
37 #define SADDLESTRINGS_PLX_DEVID 0x860610B5
38 #define TURBODOCK_PLX_DEVID 0x854710B5
39
40 EFI_STATUS
41 EFIAPI
42 PcieDockSmiCallback (
43 IN EFI_HANDLE DispatchHandle,
44 IN CONST VOID *DispatchContext,
45 IN OUT VOID *CommBuffer OPTIONAL,
46 IN UINTN *CommBufferSize OPTIONAL
47 );
48
49 VOID
50 AssignSaddleStringResources (
51 VOID
52 );
53
54 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PcieWorkaroundOnPolicy.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PcieWorkaroundOnPolicy.h File Reference

Header file for the PCIE Workaround on Policy. More...

#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Ppi/SiPolicy.h>
#include <CpuRegs.h>
#include <Library/TimerLib.h>
#include <Library/GpioLib.h>
#include <HybridGraphicsInfo.h>
Include dependency graph for PcieWorkaroundOnPolicy.h:

Go to the source code of this file.

Functions

EFI_STATUS PcieCardResetWorkAround (VOID)
PcieCardResetWorkAround performs PCIe Card reset on root port. More...

Detailed Description

Header file for the PCIE Workaround on Policy.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PcieWorkaroundOnPolicy.h.

Function Documentation

◆ PcieCardResetWorkAround()

EFI_STATUS PcieCardResetWorkAround ( VOID )

PcieCardResetWorkAround performs PCIe Card reset on root port.

Parameters
[in,out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI
Return values
EFI_SUCCESS The policy is installed and initialized.


AlderLake Platform Sample Code: PcieWorkaroundOnPolicy.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PcieWorkaroundOnPolicy.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PCIE Workaround on Policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PCIE_WORKAROUND_ON_POLICY_PEI_H_
35 #define _PCIE_WORKAROUND_ON_POLICY_PEI_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/DebugLib.h>
39 #include <Library/MemoryAllocationLib.h>
40 #include <Library/PcdLib.h>
41 #include <Library/PeiServicesLib.h>
42 #include <Library/PeiSaPolicyLib.h>
43 #include <Ppi/SiPolicy.h>
44 #include <CpuRegs.h>
45 #include <Library/TimerLib.h>
46 #include <Library/GpioLib.h>
47
48 #include <HybridGraphicsInfo.h>
49
50 //
51 // Functions
52 //
53
54 /**
55 PcieCardResetWorkAround performs PCIe Card reset on root port
56
57 @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI
58
59 @retval EFI_SUCCESS The policy is installed and initialized.
60 **/
61 EFI_STATUS
62 EFIAPI
63 PcieCardResetWorkAround (
64 VOID
65 );
66 #endif
PcieCardResetWorkAround
EFI_STATUS PcieCardResetWorkAround(VOID)
PcieCardResetWorkAround performs PCIe Card reset on root port.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PdtUpdateLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PdtUpdateLib.h File Reference
#include <Uefi.h>
#include <PiDxe.h>
#include <Library/UefiLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/IoLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DxeMeLib.h>
Include dependency graph for PdtUpdateLib.h:

Go to the source code of this file.

Functions

EFI_STATUS PdtUpdate (IN UINT32 SensorBomId, IN UINT8 *FileBuffer, IN UINT32 MultiPdtSize)
API to Update new PDT file by sending it to ME. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PdtUpdateLib.h.

Function Documentation

◆ PdtUpdate()

EFI_STATUS PdtUpdate | ( | IN UINT32 | SensorBomId,
 |  | IN UINT8 * | FileBuffer,
 |  | IN UINT32 | MultiPdtSize
 | ) |  |

API to Update new PDT file by sending it to ME.

Parameters
[in] | SensorBomId | SensorBomId to be matched to in MultiPDT package
[in] | FileBuffer | The pointer to MultiPdt file
[in] | MultiPdtSize | MultiPDT file size
Return values
EFI_SUCCESS Bios2Ish file send complete.


AlderLake Platform Sample Code: PdtUpdateLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PdtUpdateLib.h
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32 **/
33
34 #ifndef _PDT_UPDATE_LIB_H_
35 #define _PDT_UPDATE_LIB_H_
36
37 #include <Uefi.h>
38 #include <PiDxe.h>
39 #include <Library/UefiLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/MemoryAllocationLib.h>
42 #include <Library/BaseLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/IoLib.h>
45 #include <Library/UefiBootServicesTableLib.h>
46 #include <Library/UefiRuntimeServicesTableLib.h>
47 #include <Library/DxeMeLib.h>
48
49 /**
50 API to Update new PDT file by sending it to ME
51
52 @param[in] SensorBomId SensorBomId to be matched to in MultiPDT package
53 @param[in] FileBuffer The pointer to MultiPdt file
54 @param[in] MultiPdtSize MultiPDT file size
55
56 @retval EFI_SUCCESS Bios2Ish file send complete.
57
58 **/
59
60 EFI_STATUS
61 PdtUpdate (
62 IN UINT32 SensorBomId,
63 IN UINT8 *FileBuffer,
64 IN UINT32 MultiPdtSize
65 );
66
67 #endif
PdtUpdate
EFI_STATUS PdtUpdate(IN UINT32 SensorBomId, IN UINT8 *FileBuffer, IN UINT32 MultiPdtSize)
API to Update new PDT file by sending it to ME.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiBootGuardEventLogLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiBootGuardEventLogLib.h File Reference

This file contains functions for creating TPM Event Log. More...

#include <Protocol/Tcg2Protocol.h>
Include dependency graph for PeiBootGuardEventLogLib.h:

Go to the source code of this file.

Functions

EFI_STATUS CreateBootguardEventLogEntries (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN VOID *InvokePpi)
This is the library's callback entry point that will handle the TCG event logging depending on the Boot Guard configuration. More...

Detailed Description

This file contains functions for creating TPM Event Log.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PeiBootGuardEventLogLib.h.

Function Documentation

◆ CreateBootguardEventLogEntries()

EFI_STATUS CreateBootguardEventLogEntries | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDesc,
 |  | IN VOID * | InvokePpi
 | ) |  |

This is the library's callback entry point that will handle the TCG event logging depending on the Boot Guard configuration.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS | The function completes successfully
Others | Bootguard not supported


AlderLake Platform Sample Code: PeiBootGuardEventLogLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiBootGuardEventLogLib.h
Go to the documentation of this file.
1 /** @file
2 This file contains functions for creating TPM Event Log
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #include <Protocol/Tcg2Protocol.h>
36
37 //
38 // Data structure definitions
39 //
40 #pragma pack (1)
41
42 //
43 // ACM definition
44 //
45 #define ACM_MODULE_TYPE_CHIPSET_ACM 2
46 #define ACM_MODULE_SUBTYPE_CAPABLE_OF_EXECUTE_AT_RESET 0x1
47 #define ACM_MODULE_SUBTYPE_ANC_MODULE 0x2
48 #define ACM_HEADER_FLAG_DEBUG_SIGNED BIT15
49 #define ACM_NPW_SVN 0x2
50
51 typedef struct {
52 UINT16 ModuleType;
53 UINT16 ModuleSubType;
54 UINT32 HeaderLen;
55 UINT32 HeaderVersion;
56 UINT16 ChipsetId;
57 UINT16 Flags;
58 UINT32 ModuleVendor;
59 UINT32 Date;
60 UINT32 Size;
61 UINT16 AcmSvn;
62 UINT16 SeAcmSvn;
63 UINT32 CodeControl;
64 UINT32 ErrorEntryPoint;
65 UINT32 GdtLimit;
66 UINT32 GdtBasePtr;
67 UINT32 SegSel;
68 UINT32 EntryPoint;
69 UINT8 Rsvd2[64];
70 UINT32 KeySize; // 64 DWORDS in the Key
71 UINT32 ScratchSize;
72 UINT8 Rsa2048PubKey[256];
73 UINT32 RsaPubExp;
74 UINT8 Rsa2048Sig[256];
75 UINT8 Scratch[572]; // 143 DWORDS = 572 BYTES Scratch Size
76 } ACM_HEADER;
77
78 typedef struct {
79 UINT16 ModuleType;
80 UINT16 ModuleSubType;
81 UINT32 HeaderLen;
82 UINT32 HeaderVersion;
83 UINT16 ChipsetId;
84 UINT16 Flags;
85 UINT32 ModuleVendor;
86 UINT32 Date;
87 UINT32 Size;
88 UINT16 AcmSvn;
89 UINT16 SeAcmSvn;
90 UINT32 CodeControl;
91 UINT32 ErrorEntryPoint;
92 UINT32 GdtLimit;
93 UINT32 GdtBasePtr;
94 UINT32 SegSel;
95 UINT32 EntryPoint;
96 UINT8 Rsvd2[64];
97 UINT32 KeySize; // 96 DWORDS in the Key
98 UINT32 ScratchSize;
99 UINT8 Rsa3072PubKey[384];
100 UINT8 Rsa3072Sig[384];
101 UINT8 Scratch[832]; // 208 DWORDS = 832 BYTES Scratch Size
102 } ACM_HEADER_3;
103
104 //
105 // BPM Policy:
106 // FIT record type 12 points to Boot Policy Manifest.
107 // FIT record type 11 points to Key Manifest.
108 //
109
110 #define RSA_KEY_SIZE_1K SIZE_1KB
111 #define RSA_KEY_SIZE_2K SIZE_2KB
112 #define RSA_KEY_SIZE_3K (SIZE_1KB + SIZE_2KB)
113 #define PKCS_1_5_RSA_SHA1_SIGNATURE_SIZE (RSA_KEY_SIZE_1K / 8)
114 #define PKCS_1_5_RSA_SHA256_SIGNATURE_SIZE (RSA_KEY_SIZE_2K / 8)
115 #define PKCS_1_5_RSA_SHA384_SIGNATURE_SIZE (RSA_KEY_SIZE_3K / 8)
116 #define SHA1_DIGEST_SIZE 20
117 #define SHA256_DIGEST_SIZE 32
118 #define SHA384_DIGEST_SIZE 48
119 #define SM3_256_DIGEST_SIZE 32
120
121 typedef union {
122 UINT8 digest8[SHA1_DIGEST_SIZE];
123 UINT32 digest32[SHA1_DIGEST_SIZE / 4];
124 } BtgSha1Digest_u;
125
126 typedef union {
127 UINT8 digest8[SHA256_DIGEST_SIZE];
128 UINT32 digest32[SHA256_DIGEST_SIZE / 4];
129 UINT64 digest64[SHA256_DIGEST_SIZE / 8];
130 } BtgSha256Digest_u;
131
132 typedef union {
133 UINT8 digest8[SHA384_DIGEST_SIZE];
134 UINT32 digest32[SHA384_DIGEST_SIZE / 4];
135 UINT64 digest64[SHA384_DIGEST_SIZE / 8];
136 } BtgSha384Digest_u;
137
138 //
139 // Hash structure
140 //
141 typedef struct {
142 UINT16 HashAlg;
143 UINT16 Size;
144 BtgSha1Digest_u HashBuffer;
145 } SHA1_HASH_STRUCTURE;
146
147 typedef struct {
148 UINT16 HashAlg;
149 UINT16 Size;
150 BtgSha256Digest_u HashBuffer;
151 } SHA256_HASH_STRUCTURE;
152
153 typedef struct {
154 UINT16 HashAlg;
155 UINT16 Size;
156 BtgSha384Digest_u HashBuffer;
157 } SHA384_HASH_STRUCTURE;
158
159 typedef struct {
160 UINT16 HashAlg;
161 UINT16 Size;
162 UINT8 HashBuffer[];
163 } SHAX_HASH_STRUCTURE;
164
165 typedef struct {
166 UINT16 Size; //Total number of bytes of HASH_LIST structure
167 UINT16 Count; //Number of Digest elements
168 } HASH_LIST;
169
170 typedef struct {
171 UINT16 Size; //Total number of bytes of HASH_LIST structure
172 UINT16 Count; //Number of Digest elements
173 SHA1_HASH_STRUCTURE Sha1Digest; //Array of digests {AlgID, Size, HashValue; ...}
174 SHA256_HASH_STRUCTURE Sha256Digest; //Array of digests {AlgID, Size, HashValue; ...}
175 SHA256_HASH_STRUCTURE ShaSm3Digest; //Array of digests {AlgID, Size, HashValue; ...}
176 SHA384_HASH_STRUCTURE Sha384Digest; //Array of digests {AlgID, Size, HashValue; ...}
177 } MAX_HASH_LIST;
178
179 struct {
180 UINT64 Usage; // Bit mask of usages
181 SHAX_HASH_STRUCTURE Digest; // Standard BtG hash structure primitive
182 } SHAX_KMHASH_STRUCT;
183
184
185 #define ALG_RSA 0x1
186 #define ALG_RSASSA 0x14
187
188 #define RSA_PUBLIC_KEY_STRUCT_VERSION_1_0 0x10
189 #define RSA_PUBLIC_KEY_STRUCT_KEY_EXPONENT_DEFAULT 0x11 // NOT 0x10001
190
191 typedef struct {
192 UINT8 Version; // 0x10
193 UINT16 KeySizeBits; // 1024 or 2048 or 3072 bits
194 } KEY_STRUCT_HEADER;
195
196 typedef struct {
197 UINT8 Version; // 0x10
198 UINT16 KeySizeBits; // Number of bits in the modulus.
199 UINT32 Exponent; // The public exponent (must be RSA_KEY_EXPONENT_VALUE)
200 UINT8 Modulus[RSA_KEY_SIZE_2K/8]; // The modulus in LSB format (256 bytes)
201 } RSA2K_PUBLIC_KEY_STRUCT;
202
203 typedef struct {
204 UINT8 Version; // 0x10
205 UINT16 KeySizeBits; // Number of bits in the modulus.
206 UINT32 Exponent; // The public exponent (must be RSA_KEY_EXPONENT_VALUE)
207 UINT8 Modulus[RSA_KEY_SIZE_3K/8]; // The modulus in LSB format (384 bytes)
208 } RSA3K_PUBLIC_KEY_STRUCT;
209
210 typedef struct {
211 UINT8 Version; // 0x10
212 UINT16 KeySizeBits; // 1024 or 2048 or 3072 bits
213 UINT32 Exponent; // The public exponent
214 UINT8 Modulus[1]; // The modulus in LSB format
215 } RSA_PUBLIC_KEY_STRUCT;
216
217 #define ECC_PUBLIC_KEY_STRUCT_VERSION_1_0 0x10
218 #define ECC_PUBLIC_KEY_STRUCT_KEY_SIZE_DEFAULT 256
219 #define ECC_PUBLIC_KEY_STRUCT_KEY_LEN_DEFAULT (ECC_PUBLIC_KEY_STRUCT_KEY_SIZE_DEFAULT/8)
220 typedef struct {
221 UINT8 Version; // 0x10
222 UINT16 KeySizeBits; // 256 - Number of bits in key. Fixed for SM2
223 UINT8 Qx[ECC_PUBLIC_KEY_STRUCT_KEY_LEN_DEFAULT]; // X component. Fixed size for SM2
224 UINT8 Qy[ECC_PUBLIC_KEY_STRUCT_KEY_LEN_DEFAULT]; // Y component. Fixed size for SM2
225 } ECC_PUBLIC_KEY_STRUCT;
226
227 #define RSASSA_SIGNATURE_STRUCT_VERSION_1_0 0x10
228
229 typedef struct {
230 UINT8 Version;
231 UINT16 SigSizeBits; // 2048 or 3072 bits
232 } SIGNATURE_STRUCT_HEADER;
233
234 typedef struct {
235 UINT8 Version;
236 UINT16 KeySizeBits; // 2048 or 3072 bits
237 UINT16 HashAlg;
238 UINT8 Signature[];
239 } RSASSA_SIGNATURE_STRUCT;
240
241 #define ECC_SIGNATURE_STRUCT_VERSION_1_0 0x10
242 typedef struct {
243 UINT8 Version;
244 UINT16 KeySizeBits; // 256 or 384 bits
245 UINT16 HashAlg;
246 } ECC_SIGNATURE_STRUCT;
247
248 #define KEY_SIGNATURE_STRUCT_VERSION_1_0 0x10
249 typedef struct {
250 UINT8 Version;
251 UINT16 KeyAlg; // TPM_ALG_RSA=0x1 or TPM_ALG_ECC=0x23
252 } KEY_AND_SIGNATURE_STRUCT_HEADER;
253 typedef struct {
254 UINT8 Version;
255 UINT16 KeyAlg; // TPM_ALG_RSA=0x1 or TPM_ALG_ECC=0x23
256 union { // Based on KeyAlg
257 RSA_PUBLIC_KEY_STRUCT RsaKey;
258 ECC_PUBLIC_KEY_STRUCT EccKey;
259 } Key;
260 UINT16 SigScheme; // TPM_ALG_RSASSA=0x14 or TPM_ALG_RSAPSS=0x15 or TPM_ALG_SM2=0x1B
261 union { // Based on KeyAlg
262 RSASSA_SIGNATURE_STRUCT SignatureRsa;
263 ECC_SIGNATURE_STRUCT SignatureEcc;
264 } Sig;
265 } KEY_AND_SIGNATURE_STRUCT;
266
267 #define BP_KEY_TYPE_BOOT_POLICY_MANIFEST 0
268 #define BP_KEY_TYPE_KEY_MANIFEST 1
269
270 #define BOOT_POLICY_MANIFEST_HEADER_STRUCTURE_ID (*(UINT64 *)"__ACBP__")
271 #define BOOT_POLICY_MANIFEST_HEADER_VERSION_2_1 0x21
272 typedef struct {
273 UINT8 StructureId[8];
274 UINT8 StructVersion; // 0x21
275 UINT8 HdrStructVersion; // 0x20
276 UINT16 HdrSize; // total number of bytes in Header (i.e., offset to first element)
277 UINT16 KeySignatureOffset; // Offset from start of Bpm to KeySignature field of Signature Element
278 UINT8 BpmRevision;
279 UINT8 BpmRevocation;
280 UINT8 AcmRevocation;
281 UINT8 Reserved;
282 UINT16 NemPages;
283 } BOOT_POLICY_MANIFEST_HEADER;
284
285 #define IBB_SEGMENT_FLAG_IBB 0x0
286 #define IBB_SEGMENT_FLAG_NON_IBB 0x1
287 typedef struct {
288 UINT16 Reserved; // Alignment
289 UINT16 Flags; // Control flags
290 UINT32 Base; // Segment base
291 UINT32 Size; // Segment size
292 } IBB_SEGMENT;
293
294 #define BOOT_POLICY_MANIFEST_IBB_ELEMENT_STRUCTURE_ID (*(UINT64 *)"__IBBS__")
295 #define BOOT_POLICY_MANIFEST_IBB_ELEMENT_DIGEST_ID (*(UINT64 *)"__DIGE__")
296
297 #define BOOT_POLICY_MANIFEST_IBB_ELEMENT_VERSION_2_0 0x20
298 #define IBB_FLAG_INITIAL_MEASURE_LOC3 0x2
299 #define IBB_FLAG_AUTHORITY_MEASURE 0x4
300 //
301 // BIT7 will be used to control the stability of PCR[0] by masking out mutable policies from
302 // ACM_BIOS_POLICY_STS (0xfed30378) which is part of extend value into PCR[0]
303 //
304 #define IBB_FLAG_SRTM_AC 0x80 //Bit 7
305 #define SRTM_AC_MASK 0x20FFF
306
307 typedef struct {
308 UINT8 StructureId[8];
309 UINT8 StructVersion; // 0x20
310 UINT8 Reserved0;
311 UINT16 ElementSize; // Total number of bytes in the element
312 UINT8 Reserved1;
313 UINT8 SetType;
314 UINT8 Reserved;
315 UINT8 PbetValue;
316 UINT32 Flags;
317 UINT64 IbbMchBar;
318 UINT64 VtdBar;
319 UINT32 DmaProtBase0;
320 UINT32 DmaProtLimit0;
321 UINT64 DmaProtBase1;
322 UINT64 DmaProtLimit1;
323 SHAX_HASH_STRUCTURE PostIbbHash;
324 } IBB_ELEMENT;
325
326 #define BOOT_POLICY_MANIFEST_TXT_ELEMENT_STRUCTURE_ID (*(UINT64 *)"__TXTS__")
327 #define BOOT_POLICY_MANIFEST_TXT_ELEMENT_VERSION_2_0 0x20
328 typedef struct {
329 UINT8 StructureId[8];
330 UINT8 StructVersion; // 0x20
331 UINT8 Reserved0;
332 UINT16 ElementSize; // Total number of bytes in the element
333 UINT8 Reserved1;
334 UINT8 SetType;
335 UINT16 Reserved;
336 UINT32 Flags;
337 UINT16 PwrDownInterval;
338 UINT8 PttCmosOffset0;
339 UINT8 PttCmosOffset1;
340 UINT16 AcpiBaseOffset;
341 UINT16 Reserved2;
342 UINT32 PrwmBaseOffset;
343 HASH_LIST DigestList;
344 UINT8 Reserved3[3];
345 UINT8 SegmentCount;
346 IBB_SEGMENT* TxtSegment; // TxtSegment[SegmentCount]
347 } TXT_ELEMENT;
348
349 #define BOOT_POLICY_MANIFEST_PLATFORM_CONFIG_DATA_ELEMENT_STRUCTURE_ID (*(UINT64 *)"__PCDS__")
350 #define BOOT_POLICY_MANIFEST_PLATFORM_CONFIG_DATA_ELEMENT_VERSION_2_0 0x20
351 typedef struct {
352 UINT8 StructureId[8];
353 UINT8 StructVersion; // 0x20
354 UINT8 Reserved0;
355 UINT16 ElementSize; // Total number of bytes in the element
356 UINT16 Reserved1;
357 UINT16 SizeOfData;
358 UINT8* Data; //Data[SizeofData] // Any data but starts from PDRS
359 } PLATFORM_CONFIG_DATA_ELEMENT;
360
361 #define BOOT_POLICY_MANIFEST_PLATFORM_MANUFACTURER_ELEMENT_STRUCTURE_ID (*(UINT64 *)"__PMDA__")
362 #define BOOT_POLICY_MANIFEST_PLATFORM_MANUFACTURER_ELEMENT_VERSION_2_0 0x20
363 typedef struct {
364 UINT8 StructureId[8];
365 UINT8 StructVersion; // 0x20
366 UINT8 Reserved0;
367 UINT16 ElementSize; // Total number of bytes in the element
368 UINT16 Reserved1;
369 UINT16 PmDataSize; // required to be 4 byte multiple
370 UINT8* PmData; // PmData[PmDataSize]
371 } PLATFORM_MANUFACTURER_ELEMENT;
372
373 #define BOOT_POLICY_MANIFEST_SIGNATURE_ELEMENT_STRUCTURE_ID (*(UINT64 *)"__PMSG__")
374 #define BOOT_POLICY_MANIFEST_SIGNATURE_ELEMENT_VERSION_1_0 0x10
375 typedef struct {
376 UINT8 StructureId[8];
377 UINT8 StructVersion; // 0x20
378 UINT8 Reserved[3]; // KeySignature must be DWORD aligned
379 KEY_AND_SIGNATURE_STRUCT KeySignature; // this is now a variable Size
380 } BOOT_POLICY_MANIFEST_SIGNATURE_ELEMENT;
381
382 #define KEY_MANIFEST_STRUCTURE_ID (*(UINT64 *)"__KEYM__")
383 #define KEY_MANIFEST_STRUCTURE_VERSION_2_1 0x21
384 typedef struct {
385 UINT8 StructureId[8];
386 UINT8 StructVersion; // 0x21
387 UINT8 reserved[3]; // 3 bytes to make KeySignatureOffset same offset as for BPM
388 UINT16 KeySignatureOffset; // Offset from start of KM to KeyManifestSignature
389 UINT8 Reserved2[3]; // Alignment
390 UINT8 KeyManifestRevision;
391 UINT8 KmSvn;
392 UINT8 KeyManifestId;
393 UINT16 KmPubKeyHashAlg;
394 UINT16 KeyCount;
395 } KEY_MANIFEST_STRUCTURE;
396
397 //
398 // Detail PCR data
399 //
400 typedef struct {
401 UINT64 AcmPolicySts;
402 UINT16 AcmSvn; // ACM_SVN from ACM Header
403 UINT8 AcmRsaSignature[]; // copy from ACM.HEADER.RSASIG
404 } DETAIL_PCR_DATA;
405
406 typedef struct {
407 UINT64 AcmPolicySts; // lower 8 bits of the BP.RSTR
408 UINT16 AcmSvn; // ACM_SVN from ACM Header
409 UINT8 buffer[RSA_KEY_SIZE_3K/8 + RSA_KEY_SIZE_3K/8 + RSA_KEY_SIZE_3K/8 + SHA384_DIGEST_SIZE ] ;
410 } MAX_DETAIL_PCR_DATA;
411
412 //
413 // Authority PCR data
414 //
415 typedef struct {
416 UINT64 AcmPolicySts;
417 UINT16 AcmSvn; // ACM_SVN from ACM Header
418 UINT8 AcmKeyHash[]; // The hash of the key used to verify the ACM (SHAxxx)
419 } AUTHORITY_PCR_DATA;
420
421 typedef struct {
422 UINT64 AcmPolicySts;
423 UINT16 AcmSvn; // ACM_SVN from ACM Header
424 UINT8 AcmKeyHash[SHA384_DIGEST_SIZE]; // The hash of the key used to verify the ACM (SHAxxx)
425 UINT8 BpKeyHash[SHA384_DIGEST_SIZE]; // The hash of the key used to verify the Key Manifest (SHAxxx)
426 UINT8 BpmKeyHashFromKm[SHA384_DIGEST_SIZE]; // The hash of the key used to verify the Boot Policy Manifest (SHAxxx)
427 } MAX_AUTHORITY_PCR_DATA;
428
429 //
430 // Efi Startup Locality Event Data
431 //
432 typedef struct {
433 UINT8 Signature[16];
434 UINT8 StartupLocality;
435 } TCG_EFI_STARTUP_LOCALITY_EVENT;
436
437 typedef struct {
438 EFI_GUID *EventGuid;
439 EFI_TCG2_EVENT_LOG_FORMAT LogFormat;
440 } EFI_TCG2_EVENT_INFO_STRUCT;
441
442 typedef union {
443 struct {
444 UINT64 KmId : 4; // 0-3 Key Manifest ID used for verified Key Manifest
445 UINT64 MeasuredBoot : 1; // 4 perform measured boot
446 UINT64 VerifiedBoot : 1; // 5 perform verified boot
447 UINT64 HAP : 1; // 6 high assurance platform
448 UINT64 TxtSupported : 1; // 7 txt supported
449 UINT64 BootMedia : 1; // 8 Boot media
450 UINT64 DCD : 1; // 9 disable CPU debug
451 UINT64 DBI : 1; // 10 disable BSP init
452 UINT64 PBE : 1; // 11 protect BIOS environment
453 UINT64 BBP : 1; // 12 bypass boot policy - fast S3 resume
454 UINT64 TpmType : 2; // 13-14 TPM Type
455 UINT64 TpmSuccess : 1; // 15 TPM Success
456 UINT64 Reserved1 : 1; // 16
457 UINT64 BootPolicies : 1; // 17 PFR supported
458 UINT64 BackupActions : 2; // 18-19 Backup actions
459 UINT64 TxtProfile : 5; // 20-24 TXT profile selection
460 UINT64 MemScrubPolicy : 2; // 25-26 Memory scrubbing policy
461 UINT64 Reserved2 : 2; // 27-28
462 UINT64 DmaProtection : 1; // 29 DMA Protection
463 UINT64 Reserved3 : 2; // 30-31
464 UINT64 SCrtmStatus : 3; // 32-34 S-CRTM status
465 UINT64 Cosign : 1; // 35 CPU co-signing
466 UINT64 TpmStartupLocality : 1; // 36 TPM startup locality.
467 UINT64 Reserved :27; // 37-63
468 } Bits;
469 UINT64 Data;
470 } ACM_BIOS_POLICY;
471
472 #pragma pack ()
473
474 /**
475 This is the library's callback entry point that will handle the TCG event logging
476 depending on the Boot Guard configuration.
477
478 @param[in] PeiServices Pointer to PEI Services Table.
479 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
480 caused this function to execute.
481 @param[in] Ppi Pointer to the PPI data associated with this function.
482
483 @retval EFI_SUCCESS The function completes successfully
484 @retval Others Bootguard not supported
485 **/
486 EFI_STATUS
487 EFIAPI
488 CreateBootguardEventLogEntries (
489 IN EFI_PEI_SERVICES **PeiServices,
490 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
491 IN VOID *InvokePpi
492 );
CreateBootguardEventLogEntries
EFI_STATUS CreateBootguardEventLogEntries(IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN VOID *InvokePpi)
This is the library's callback entry point that will handle the TCG event logging depending on the Bo...
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiCpuPolicyDebugLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiCpuPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel CPU PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiCpuPolicyDebugPreMem (VOID)
This function performs CPU PEI Debug Policy initialization. More...
EFI_STATUS | UpdatePeiCpuPolicyDebug (VOID)
This function performs CPU PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiCpuPolicyDebugLib.h.

Function Documentation

◆ UpdatePeiCpuPolicyDebug()

EFI_STATUS UpdatePeiCpuPolicyDebug ( VOID )

This function performs CPU PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.

◆ UpdatePeiCpuPolicyDebugPreMem()

EFI_STATUS UpdatePeiCpuPolicyDebugPreMem ( VOID )

This function performs CPU PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


AlderLake Platform Sample Code: PeiCpuPolicyDebugLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiCpuPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_CPU_POLICY_DEBUG_LIB_H_
35 #define _PEI_CPU_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs CPU PEI Debug Policy initialization.
40
41 @retval EFI_SUCCESS The PPI is installed and initialized.
42 @retval EFI ERRORS The PPI is not successfully installed.
43 **/
44 EFI_STATUS
45 EFIAPI
46 UpdatePeiCpuPolicyDebugPreMem (
47 VOID
48 );
49
50
51 /**
52 This function performs CPU PEI Debug Policy initialization.
53
54 @retval EFI_SUCCESS The PPI is installed and initialized.
55 @retval EFI ERRORS The PPI is not successfully installed.
56 **/
57 EFI_STATUS
58 EFIAPI
59 UpdatePeiCpuPolicyDebug (
60 VOID
61 );
62 #endif
UpdatePeiCpuPolicyDebugPreMem
EFI_STATUS UpdatePeiCpuPolicyDebugPreMem(VOID)
This function performs CPU PEI Debug Policy initialization.
UpdatePeiCpuPolicyDebug
EFI_STATUS UpdatePeiCpuPolicyDebug(VOID)
This function performs CPU PEI Debug Policy initialization.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiGetFvInfoLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiGetFvInfoLib.h File Reference

Header file for PeiGetFvInfoLib. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS PeiGetSectionFromFv (IN CONST EFI_GUID NameGuid, OUT VOID **Address, OUT UINT32 *Size)
PeiGetSectionFromFv finds the file in FV and gets file Address and Size. More...

Detailed Description

Header file for PeiGetFvInfoLib.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiGetFvInfoLib.h.

Function Documentation

◆ PeiGetSectionFromFv()

EFI_STATUS PeiGetSectionFromFv | ( | IN CONST EFI_GUID | NameGuid,
 |  | OUT VOID ** | Address,
 |  | OUT UINT32 * | Size
 | ) |  |

PeiGetSectionFromFv finds the file in FV and gets file Address and Size.

Parameters
[in] | NameGuid | - File GUID
[out] | Address | - Pointer to the File Address
[out] | Size | - Pointer to File Size
Return values
EFI_SUCCESS Successfull in reading the section from FV


AlderLake Platform Sample Code: PeiGetFvInfoLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiGetFvInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PeiGetFvInfoLib..
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PEI_GET_FV_INFO_LIB_H_
36 #define _PEI_GET_FV_INFO_LIB_H_
37
38 /**
39 PeiGetSectionFromFv finds the file in FV and gets file Address and Size
40
41 @param[in] NameGuid - File GUID
42 @param[out] Address - Pointer to the File Address
43 @param[out] Size - Pointer to File Size
44
45 @retval EFI_SUCCESS Successfull in reading the section from FV
46 **/
47 EFI_STATUS
48 EFIAPI
49 PeiGetSectionFromFv (
50 IN CONST EFI_GUID NameGuid,
51 OUT VOID **Address,
52 OUT UINT32 *Size
53 );
54
55 #endif
PeiGetSectionFromFv
EFI_STATUS PeiGetSectionFromFv(IN CONST EFI_GUID NameGuid, OUT VOID **Address, OUT UINT32 *Size)
PeiGetSectionFromFv finds the file in FV and gets file Address and Size.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiPchPolicyDebugLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiPchPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel PCH PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiPchPolicyDebug (VOID)
This function performs PCH PEI Debug Policy initialization. More...
EFI_STATUS | UpdatePeiPchPolicyDebugPreMem (VOID)
This function performs PCH PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPchPolicyDebugLib.h.

Function Documentation

◆ UpdatePeiPchPolicyDebug()

EFI_STATUS UpdatePeiPchPolicyDebug ( VOID )

This function performs PCH PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.

◆ UpdatePeiPchPolicyDebugPreMem()

EFI_STATUS UpdatePeiPchPolicyDebugPreMem ( VOID )

This function performs PCH PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


AlderLake Platform Sample Code: PeiPchPolicyDebugLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiPchPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_PCH_POLICY_DEBUG_LIB_H_
35 #define _PEI_PCH_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs PCH PEI Debug Policy initialization.
40
41 @retval EFI_SUCCESS The PPI is installed and initialized.
42 @retval EFI ERRORS The PPI is not successfully installed.
43 **/
44 EFI_STATUS
45 EFIAPI
46 UpdatePeiPchPolicyDebug (
47 VOID
48 );
49
50 /**
51 This function performs PCH PEI Debug Policy initialization.
52
53 @retval EFI_SUCCESS The PPI is installed and initialized.
54 @retval EFI ERRORS The PPI is not successfully installed.
55 **/
56 EFI_STATUS
57 EFIAPI
58 UpdatePeiPchPolicyDebugPreMem (
59 VOID
60 );
61 #endif
UpdatePeiPchPolicyDebug
EFI_STATUS UpdatePeiPchPolicyDebug(VOID)
This function performs PCH PEI Debug Policy initialization.
UpdatePeiPchPolicyDebugPreMem
EFI_STATUS UpdatePeiPchPolicyDebugPreMem(VOID)
This function performs PCH PEI Debug Policy initialization.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiPlatformLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiPlatformLib.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPlatformLib.h.


AlderLake Platform Sample Code: PeiPlatformLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiPlatformLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_PLATFORM_LIB_H_
35 #define _PEI_PLATFORM_LIB_H_
36
37
38
39 #define PEI_DEVICE_DISABLED 0
40 #define PEI_DEVICE_ENABLED 1
41
42 typedef struct {
43 UINT8 Register;
44 UINT32 Value;
45 } PCH_GPIO_DEV;
46
47 //
48 // GPIO Initialization Data Structure
49 //
50 typedef struct{
51 PCH_GPIO_DEV Use_Sel;
52 PCH_GPIO_DEV Use_Sel2;
53 PCH_GPIO_DEV Use_Sel3;
54 PCH_GPIO_DEV Io_Sel;
55 PCH_GPIO_DEV Io_Sel2;
56 PCH_GPIO_DEV Io_Sel3;
57 PCH_GPIO_DEV Lvl;
58 PCH_GPIO_DEV Lvl2;
59 PCH_GPIO_DEV Lvl3;
60 PCH_GPIO_DEV Inv;
61 PCH_GPIO_DEV Blink;
62 PCH_GPIO_DEV Rst_Sel;
63 PCH_GPIO_DEV Rst_Sel2;
64 } GPIO_INIT_STRUCT;
65
66 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiPlatformRecoveryLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiPlatformRecoveryLib.h File Reference

This library provides platform recovery module. More...

Go to the source code of this file.

Functions

EFI_STATUS InitializeRecovery (VOID)
Provide the functionality of the recovery module. More...

Detailed Description

This library provides platform recovery module.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiPlatformRecoveryLib.h.

Function Documentation

◆ InitializeRecovery()

EFI_STATUS InitializeRecovery ( VOID )

Provide the functionality of the recovery module.

Return values
EFI_SUCCESS The function completed successfully.


AlderLake Platform Sample Code: PeiPlatformRecoveryLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiPlatformRecoveryLib.h
Go to the documentation of this file.
1 /** @file
2 This library provides platform recovery module.
3
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_PLATFORM_RECOVERY_LIB_H_
37 #define _PEI_PLATFORM_RECOVERY_LIB_H_
38
39
40 /**
41 Provide the functionality of the recovery module.
42
43 @retval EFI_SUCCESS The function completed successfully.
44 **/
45 EFI_STATUS
46 EFIAPI
47 InitializeRecovery (
48 VOID
49 );
50 #endif
InitializeRecovery
EFI_STATUS InitializeRecovery(VOID)
Provide the functionality of the recovery module.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiReadWriteVariableLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiReadWriteVariableLib.h File Reference

Go to the source code of this file.

Functions

EFI_STATUS PeiReadWriteVariableInit (VOID)
Initialize PEI read write Variable PPI. More...

Detailed Description

Todo:
ADD DESCRIPTION
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiReadWriteVariableLib.h.

Function Documentation

◆ PeiReadWriteVariableInit()

EFI_STATUS PeiReadWriteVariableInit ( VOID )

Initialize PEI read write Variable PPI.

Return values
Status
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiReadWriteVariableLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiReadWriteVariableLib.h
Go to the documentation of this file.
1 /** @file
2 @todo ADD DESCRIPTION
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_READ_WRITE_VARIABLE_LIB_H_
35 #define _PEI_READ_WRITE_VARIABLE_LIB_H_
36
37 /**
38 Initialize PEI read write Variable PPI.
39
40 @retval Status
41 **/
42 EFI_STATUS
43 PeiReadWriteVariableInit (
44 VOID
45 );
46
47 #endif
PeiReadWriteVariableInit
EFI_STATUS PeiReadWriteVariableInit(VOID)
Initialize PEI read write Variable PPI.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiSaPolicyDebugLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiSaPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel SA PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS | UpdatePeiSaPolicyDebugPreMem (VOID)
This function performs SA PEI Debug PreMem Policy initialization. More...
EFI_STATUS | UpdatePeiSaPolicyDebug (VOID)
This function performs SA PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel SA PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSaPolicyDebugLib.h.

Function Documentation

◆ UpdatePeiSaPolicyDebug()

EFI_STATUS UpdatePeiSaPolicyDebug ( VOID )

This function performs SA PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.

◆ UpdatePeiSaPolicyDebugPreMem()

EFI_STATUS UpdatePeiSaPolicyDebugPreMem ( VOID )

This function performs SA PEI Debug PreMem Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


AlderLake Platform Sample Code: PeiSaPolicyDebugLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiSaPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel SA PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_SA_POLICY_DEBUG_LIB_H_
35 #define _PEI_SA_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs SA PEI Debug PreMem Policy initialization.
40
41 @retval EFI_SUCCESS The PPI is installed and initialized.
42 @retval EFI ERRORS The PPI is not successfully installed.
43 **/
44 EFI_STATUS
45 EFIAPI
46 UpdatePeiSaPolicyDebugPreMem (
47 VOID
48 );
49
50 /**
51 This function performs SA PEI Debug Policy initialization.
52
53 @retval EFI_SUCCESS The PPI is installed and initialized.
54 @retval EFI ERRORS The PPI is not successfully installed.
55 **/
56 EFI_STATUS
57 EFIAPI
58 UpdatePeiSaPolicyDebug (
59 VOID
60 );
61 #endif
UpdatePeiSaPolicyDebugPreMem
EFI_STATUS UpdatePeiSaPolicyDebugPreMem(VOID)
This function performs SA PEI Debug PreMem Policy initialization.
UpdatePeiSaPolicyDebug
EFI_STATUS UpdatePeiSaPolicyDebug(VOID)
This function performs SA PEI Debug Policy initialization.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiSiPolicyDebugLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiSiPolicyDebugLib.h File Reference

SampleCode header file of the library for Intel SI PEI Debug Policy initialization. More...

Go to the source code of this file.

Functions

EFI_STATUS UpdatePeiSiPolicyDebug (VOID)
This function performs SI PEI Debug Policy initialization. More...

Detailed Description

SampleCode header file of the library for Intel SI PEI Debug Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiPolicyDebugLib.h.

Function Documentation

◆ UpdatePeiSiPolicyDebug()

EFI_STATUS UpdatePeiSiPolicyDebug ( VOID )

This function performs SI PEI Debug Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.


AlderLake Platform Sample Code: PeiSiPolicyDebugLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiSiPolicyDebugLib.h
Go to the documentation of this file.
1 /** @file
2 SampleCode header file of the library for Intel SI PEI Debug Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _PEI_SI_POLICY_DEBUG_LIB_H_
35 #define _PEI_SI_POLICY_DEBUG_LIB_H_
36
37
38 /**
39 This function performs SI PEI Debug Policy initialization.
40
41 @retval EFI_SUCCESS The PPI is installed and initialized.
42 @retval EFI ERRORS The PPI is not successfully installed.
43 **/
44 EFI_STATUS
45 UpdatePeiSiPolicyDebug (
46 VOID
47 );
48
49 #endif
UpdatePeiSiPolicyDebug
EFI_STATUS UpdatePeiSiPolicyDebug(VOID)
This function performs SI PEI Debug Policy initialization.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiSubRegionLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiSubRegionLib.h File Reference

Header file for PeiSubRegionLib. More...

Go to the source code of this file.

Functions

BOOLEAN | IsBiosSubRegionFmpGuid (IN EFI_GUID *ImageGuid)
Return if input ImageGuid belongs to a Sub Region FMP. More...
EFI_STATUS | ReadSectionInformationFromFv (IN CONST EFI_GUID *NameGuid, IN EFI_SECTION_TYPE SectionType, OUT VOID **Buffer, OUT UINTN *Size)
Searches all the available firmware volumes and returns the first matching FFS section. More...

Detailed Description

Header file for PeiSubRegionLib.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSubRegionLib.h.

Function Documentation

◆ IsBiosSubRegionFmpGuid()

BOOLEAN IsBiosSubRegionFmpGuid ( IN EFI_GUID * ImageGuid )

Return if input ImageGuid belongs to a Sub Region FMP.

Parameters
[in] ImageGuid A pointer to GUID
Return values
TRUE | ImageGuid belongs to a Sub Region FMP
FALSE | ImageGuid does not belong to a Sub Region FMP

◆ ReadSectionInformationFromFv()

EFI_STATUS ReadSectionInformationFromFv | ( | IN CONST EFI_GUID * | NameGuid,
 |  | IN EFI_SECTION_TYPE | SectionType,
 |  | OUT VOID ** | Buffer,
 |  | OUT UINTN * | Size
 | ) |  |

Searches all the available firmware volumes and returns the first matching FFS section.

This function searches all the firmware volumes for FFS files with an FFS filename specified by NameGuid. The order in which the firmware volumes are searched is not deterministic. For each FFS file found, a search is made for FFS sections of type SectionType. If the FFS file contains at least SectionInstance instances of the FFS section specified by SectionType, then the SectionInstance instance is returned in Buffer. Buffer is allocated using AllocatePool(), and the size of the allocated buffer is returned in Size.

If SectionType is EFI_SECTION_TE, and the search with an FFS file fails, the search will be retried with a section type of EFI_SECTION_PE32.

If NameGuid is NULL, then ASSERT(). If Buffer is NULL, then ASSERT(). If Size is NULL, then ASSERT().

Parameters
NameGuid | A pointer to to the FFS filename GUID to search for within any of the firmware volumes in the platform.
SectionType | Indicates the FFS section type to search for within the FFS file specified by NameGuid.
Buffer | On output, a pointer to a buffer containing the FFS file section that was found.
Size | On output, a pointer to the size, in bytes, of Buffer.
Return values
EFI_SUCCESS | The specified FFS section was returned.
EFI_NOT_FOUND | The specified FFS section could not be found.
EFI_OUT_OF_RESOURCES | There are not enough resources available to retrieve the matching FFS section.
EFI_DEVICE_ERROR | The FFS section could not be retrieves due to a device error.
EFI_ACCESS_DENIED | The FFS section could not be retrieves because the firmware volume that contains the matching FFS section does not allow reads.


AlderLake Platform Sample Code: PeiSubRegionLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiSubRegionLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PeiSubRegionLib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PEI_SUB_REGION_LIB_H_
36 #define _PEI_SUB_REGION_LIB_H_
37
38 /**
39 Return if input ImageGuid belongs to a Sub Region FMP
40
41 @param[in] ImageGuid A pointer to GUID
42
43 @retval TRUE ImageGuid belongs to a Sub Region FMP
44 @retval FALSE ImageGuid does not belong to a Sub Region FMP
45
46 **/
47 BOOLEAN
48 IsBiosSubRegionFmpGuid (
49 IN EFI_GUID *ImageGuid
50 );
51
52 /**
53 Searches all the available firmware volumes and returns the first matching FFS section.
54
55 This function searches all the firmware volumes for FFS files with an FFS filename
56 specified by NameGuid. The order in which the firmware volumes are searched is not
57 deterministic. For each FFS file found, a search is made for FFS sections of type
58 SectionType. If the FFS file contains at least SectionInstance instances of the FFS
59 section specified by SectionType, then the SectionInstance instance is returned in
60 Buffer. Buffer is allocated using AllocatePool(), and the size of the allocated buffer
61 is returned in Size.
62
63 If SectionType is EFI_SECTION_TE, and the search with an FFS file fails,
64 the search will be retried with a section type of EFI_SECTION_PE32.
65
66 If NameGuid is NULL, then ASSERT().
67 If Buffer is NULL, then ASSERT().
68 If Size is NULL, then ASSERT().
69
70
71 @param NameGuid A pointer to to the FFS filename GUID to search for
72 within any of the firmware volumes in the platform.
73 @param SectionType Indicates the FFS section type to search for within
74 the FFS file specified by NameGuid.
75 @param Buffer On output, a pointer to a buffer
76 containing the FFS file section that was found.
77 @param Size On output, a pointer to the size, in bytes, of Buffer.
78
79 @retval EFI_SUCCESS The specified FFS section was returned.
80 @retval EFI_NOT_FOUND The specified FFS section could not be found.
81 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to retrieve
82 the matching FFS section.
83 @retval EFI_DEVICE_ERROR The FFS section could not be retrieves due to a
84 device error.
85 @retval EFI_ACCESS_DENIED The FFS section could not be retrieves because the
86 firmware volume that contains the matching FFS
87 section does not allow reads.
88 **/
89 EFI_STATUS
90 EFIAPI
91 ReadSectionInformationFromFv (
92 IN CONST EFI_GUID *NameGuid,
93 IN EFI_SECTION_TYPE SectionType,
94 OUT VOID **Buffer,
95 OUT UINTN *Size
96 );
97
98 #endif
ReadSectionInformationFromFv
EFI_STATUS ReadSectionInformationFromFv(IN CONST EFI_GUID *NameGuid, IN EFI_SECTION_TYPE SectionType, OUT VOID **Buffer, OUT UINTN *Size)
Searches all the available firmware volumes and returns the first matching FFS section.
IsBiosSubRegionFmpGuid
BOOLEAN IsBiosSubRegionFmpGuid(IN EFI_GUID *ImageGuid)
Return if input ImageGuid belongs to a Sub Region FMP.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiSwbpeLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiSwbpeLib.h File Reference
#include <DsAllocation.h>
#include <DsConfig.h>
#include <Swbpe.h>
Include dependency graph for PeiSwbpeLib.h:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiSwbpeLib.h.


AlderLake Platform Sample Code: PeiSwbpeLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiSwbpeLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _PEI_SWBPE_LIB_H_
36 #define _PEI_SWBPE_LIB_H_
37
38 #include <DsAllocation.h>
39 #include <DsConfig.h>
40 #include <Swbpe.h>
41
42 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiTsnFvLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiTsnFvLib.h File Reference

Header file for PeiTsnFvFile. More...

Go to the source code of this file.

Functions

EFI_STATUS | InstallTsnFv (VOID)
Install Base and Size Info Ppi for Siip Firmware Volume. More...
EFI_STATUS | LoadFlashTsnFv (VOID)
Install Base and Size Info Ppi for TSN Firmware Volume. More...

Detailed Description

Header file for PeiTsnFvFile.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiTsnFvLib.h.

Function Documentation

◆ InstallTsnFv()

EFI_STATUS InstallTsnFv ( VOID )

Install Base and Size Info Ppi for Siip Firmware Volume.

Return values
EFI_SUCCESS Always returns success.

◆ LoadFlashTsnFv()

EFI_STATUS LoadFlashTsnFv ( VOID )

Install Base and Size Info Ppi for TSN Firmware Volume.

Return values
EFI_SUCCESS Always returns success.


AlderLake Platform Sample Code: PeiTsnFvLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiTsnFvLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PeiTsnFvFile
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PEI_TSN_FV_LIB_H_
36 #define _PEI_TSN_FV_LIB_H_
37
38 typedef struct {
39 UINT32 Type;
40 UINT32 Version;
41 UINT64 DataOffset;
42 UINT32 DataSize;
43 UINT64 SignatureOffset;
44 UINT32 SignatureType;
45 } TSN_SUB_REGION_HEADER;
46
47 typedef struct {
48 UINT32 Seg : 8;
49 UINT32 Bus : 8;
50 UINT32 Dev : 5;
51 UINT32 Func : 3;
52 UINT32 PcieCap : 8;
53 } SBDF;
54
55 typedef struct {
56 SBDF Bdf;
57 UINT32 PortLength;
58 UINT32 MacAddressHigh;
59 UINT32 MacAddressLow;
60 } PCH_TSN_SUB_REGION_PORT;
61
62 typedef struct {
63 PCH_TSN_SUB_REGION_PORT Port;
64 UINT32 Signature;
65 } TSN_SUB_REGION;
66
67 /**
68 Install Base and Size Info Ppi for Siip Firmware Volume.
69
70 @retval EFI_SUCCESS Always returns success.
71
72 **/
73 EFI_STATUS
74 EFIAPI
75 InstallTsnFv (
76 VOID
77 );
78
79 /**
80 Install Base and Size Info Ppi for TSN Firmware Volume.
81
82 @retval EFI_SUCCESS Always returns success.
83
84 **/
85 EFI_STATUS
86 EFIAPI
87 LoadFlashTsnFv (
88 VOID
89 );
90
91 /*
92 Reads TSN Sub region.
93
94 Reads TSN sub region data from FV. Returns pointer to data.
95
96 @param[out] SubRegion Pointer to sub region data.
97
98 @retval EFI_SUCCESS Function has completed successfully.
99 @retval Others TSN region was not found
100 */
101 EFI_STATUS
102 GetTsnSubRegion (
103 OUT TSN_SUB_REGION** SubRegion
104 );
105
106 #endif
InstallTsnFv
EFI_STATUS InstallTsnFv(VOID)
Install Base and Size Info Ppi for Siip Firmware Volume.
LoadFlashTsnFv
EFI_STATUS LoadFlashTsnFv(VOID)
Install Base and Size Info Ppi for TSN Firmware Volume.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiWdtAppLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PeiWdtAppLib.h File Reference

PEI WDT App library definitions. More...

#include <Base.h>
#include <Uefi.h>
#include <Ppi/Wdt.h>
#include <Library/DebugLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Library/PeiServicesLib.h>
#include <WdtAppVariable.h>
Include dependency graph for PeiWdtAppLib.h:
This graph shows which files directly or indirectly include this file:

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Functions

EFI_STATUS PeiWdtApp (IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT status) and BIOS modules (through flash variable) More...

Detailed Description

PEI WDT App library definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PeiWdtAppLib.h.

Function Documentation

◆ PeiWdtApp()

EFI_STATUS PeiWdtApp ( IN WDT_PPI * WdtPei )

turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT status) and BIOS modules (through flash variable)

Parameters
[in] WdtPei
Return values
EFI_SUCCESS
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PeiWdtAppLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PeiWdtAppLib.h
Go to the documentation of this file.
1 /** @file
2 PEI WDT App library definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PEI_WDT_APP_LIB_H_
36 #define _PEI_WDT_APP_LIB_H_
37
38 #include <Base.h>
39 #include <Uefi.h>
40 #include <Ppi/Wdt.h>
41 #include <Library/DebugLib.h>
42 #include <Ppi/ReadOnlyVariable2.h>
43 #include <Library/PeiServicesLib.h>
44 #include <WdtAppVariable.h>
45
46
47 /**
48 turns on WDT during PEI phase according to requests made by
49 OS overclocking application (through WDT status) and BIOS modules (through flash variable)
50
51 @param[in] WdtPei
52
53 @retval EFI_SUCCESS
54 **/
55 EFI_STATUS
56 PeiWdtApp (
57 IN WDT_PPI *WdtPei
58 );
59
60 #endif
PeiWdtApp
EFI_STATUS PeiWdtApp(IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT ...
WdtAppVariable.h
Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Platform.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Platform.h File Reference

This header file provides platform specific definitions used by other modules for platform specific initialization. More...

#include "CommonDefinitions.h"
Include dependency graph for Platform.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This header file provides platform specific definitions used by other modules for platform specific initialization.

This is not suitable for consumption by ASL or VRF files.

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Platform.h.


AlderLake Platform Sample Code: Platform.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Platform.h
Go to the documentation of this file.
1 /** @file
2 This header file provides platform specific definitions used
3 by other modules for platform specific initialization.
4 This is not suitable for consumption by ASL or VRF files.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2004 - 2019 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PLATFORM_H_
38 #define _PLATFORM_H_
39
40 #include "CommonDefinitions.h"
41
42 //
43 // Need minimum of 48MB during PEI phase for IAG and some buffer for boot.
44 //
45 #define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
46 #define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
47
48 #define FLASH_BLOCK_SIZE 0x10000
49
50 #define CPU_EXTERNAL_CLOCK_FREQ 0x64
51 #define CPU_FREQUENCY_MODE_100 0x64
52 #define FREQUENCY_RESOLUTION_3182 0xc6e
53 #define NDIVIDER_BASE_VALUE 0x19d
54 #define MDIVIDER_VALUE_13 0xd
55
56 #endif
CommonDefinitions.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformBoardType.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformBoardType.h File Reference

BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file PlatformBoardType.h.


AlderLake Platform Sample Code: PlatformBoardType.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformBoardType.h
Go to the documentation of this file.
1 /** @file
2 BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_BOARD_TYPE_H_
36 #define _PLATFORM_BOARD_TYPE_H_
37
38 #define BoardTypeRvp 0x00 // Reference Validation Platform
39 #define BoardTypeRvpSthi 0x01 // Boards with Special Test Hooks
40 #define BoardTypeRvpPpv 0x02 // Boards used for Processor Platform Validation
41 #define BoardTypeFfrd 0x03 // Form factor reference design Boards
42 #define BoardTypeRvpErb 0x04 // ERB Boards
43 #define BoardTypeRvpCpv 0x05 // Boards used for Chipset Platform Validation
44 #define BoardTypeSv 0x06 // Boards used for Silicon Validation
45 #define BoardTypeUpServer 0x07 // Server Boards
46 #define BoardTypeFfvs 0x08 // Form factor Validation system
47 #define BoardTypeTdv 0x09 // Technology Development Vehicle
48 #define BoardTypeMax 0x0A
49
50 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformClock.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformClock.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformClock.h.


AlderLake Platform Sample Code: PlatformClock.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformClock.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _PLATFORM_DEFINITIONS_CLOCK_H_
35 #define _PLATFORM_DEFINITIONS_CLOCK_H_
36
37 //
38 // Clock controller SMBUS address
39 //
40 #define CLOCK_CONTROLLER_SMBUS_ADDRESS 0xD2
41
42 //
43 // Redfort platform CK505 configuration bytes 0~12
44 // (Reference: Table 21, CK505 Clock Synthesizer Specification Revision 1.0
45 // October 2006 Intel)
46 //
47 // BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
48 // =================================================================================
49 // Byte 0
50 // ------
51 // FSC(r) FSB(r) FSA(r) MT_EN Reserved SRC_MAIN SATA_SEL PD_RESTORE
52 // _SEL
53 // 0 0 0 0 0 1 0 1
54 //
55 // Byte 1
56 // ------
57 // SRC0_SEL PLL1_SSC PLL3_SSC PLL3_CFB3 PLL3_CFB2 PLL3_CFB1 PLL3_CFB0 PCI_SEL
58 // _DC _DC
59 // 1 0 0 0 0 0 1 1
60 //
61 // Byte 2
62 // ------
63 // REF_OE USB_OE PCIF5_OE PCI4_OE PCI3_OE PCI2_OE PCI1_OE PCI0_OE
64 // 1 0 0 0 0 0 0 0
65 //
66 // Byte 3
67 // ------
68 // SRC11_OE SRC10_OE SRC9_OE SRC8/ITP SRC7_OE SRC6_OE SRC5_OE SRC4_OE
69 // _OE
70 // 0 0 0 0 0 0 0 0
71 //
72 // Byte 4
73 // ------
74 // SRC3_OE SATA/SRC2 SRC1_OE SRC0 CPU1_OE CPU0_OE PLL1_SSC PLL3_SSC_EN
75 // _OE /DOT96_OE _EN
76 // 0 1 1 1 0 1 0 0
77 //
78 // Byte 5
79 // ------
80 // CR#_A_EN CR#_A_SEL CR#_B_EN CR#_B_SEL CR#_C_EN CR#_C_SEL CR#_D_EN CR#_D_SEL
81 // 0 0 0 0 0 0 0 0
82 //
83 // Byte 6
84 // ------
85 // CR#_E_EN CR#_F_EN CR#_G_EN CR#_H_EN Reserved Reserved SSCD_STP SRC_STP_CRTL
86 // _CRTL
87 // 0 0 0 0 0 0 0 0
88 //
89 // Byte 7
90 // ------
91 // RC Bit3(r) RC Bit2(r) RC Bit1(r) RC Bit0(r) VID Bit3(r)VID Bit2(r)VID Bit1(r)VID Bit0(r)
92 // 0 0 0 0 0 0 0 0
93 //
94 // Byte 8
95 // ------
96 // DID3(r) DID2(r) DID1(r) DID0(r) Reserved Reserved SE1_OE SE2_OE
97 // 0 0 0 0 0 0 0 0
98 //
99 // Byte 9
100 // ------
101 // PCIF5_STP TME_STRAP REF_DRIVE TEST_MODE TEST_MODE IO_VOUT2 IO_VOUT1 IO_VOUT0
102 // _CTRL (r) _SEL _ENTRY
103 // 0 0 1 0 0 1 0 1
104 //
105 // Byte 10
106 // -------
107 // SRC5_EN PLL3_EN PLL2_EN SRC_DIV_EN PCI_DIV_EN CPU_DIV_EN CPU1_STOP CPU0_STOP
108 // _STRAP(r) _EN _EN
109 // 1 1 1 0 0 0 0 0
110 //
111 // Byte 11
112 // -------
113 // PCI3_CFG1 PCI3_CFG0 25MHZ_EN PLL4_EN CPU2_AMT CPU1_AMT PCI-E_GEN2 CPU2_STOP
114 // (r) (r) _SE1 _EN _EN (r) _EN
115 // 0 1 0 1 0 0 1 0
116 //
117 // Byte 12
118 // -------
119 // Reserved Reserved BC5 BC4 BC3 BC2 BC1 BC0
120 // 0 0 0 0 1 1 0 1
121 //
122
123 #define MOBILE_CLOCK_CONTROLLER_SETTINGS {0x05, 0x83, 0x80, 0, 0x77, 0x00, 0x0, 0x00, 0, 0x25, 0xe0, 0x52, 0xd}
124 #define DESKTOP_CLOCK_CONTROLLER_SETTINGS {0x35, 0x83, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x26, 0x03, 0x25, 0xFD, 0x56}
125
126 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformConfigurationChangeVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformConfigurationChangeVariable.h File Reference

Platform configuration change variable definitions. More...

Go to the source code of this file.

Detailed Description

Platform configuration change variable definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformConfigurationChangeVariable.h.


AlderLake Platform Sample Code: PlatformConfigurationChangeVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformConfigurationChangeVariable.h
Go to the documentation of this file.
1 /** @file
2 Platform configuration change variable definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_CONFIGURATION_CHANGE_VARIABLE_H__
36 #define __PLATFORM_CONFIGURATION_CHANGE_VARIABLE_H__
37
38 #define PLATFORM_CONFIGURATION_CHANGE_VARIABLE_GUID \
39 { \
40 0xe3cacf62, 0x3062, 0x4e1d, { 0x97, 0x8e, 0x46, 0x80, 0x7a, 0xb9, 0x74, 0x7d }\
41 }
42
43 #define PLATFORM_CONFIGURATION_CHANGE L"PlatformConfigurationChange"
44
45 #define NO_CONFIG_CHANGE 0x00000000
46 #define FIRST_BOOT 0x00000001
47 #define SETUP_OPTION_CHANGE 0x00000002
48
49 typedef struct {
50 UINT32 ConfigChangeType; /// Significant change from previous boot
51 } CONFIGURATION_CHANGE;
52
53 #endif
54
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformGlobalVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PlatformGlobalVariable.h File Reference

GUID for Platform (NVRAM) Variables. More...

Go to the source code of this file.

Detailed Description

GUID for Platform (NVRAM) Variables.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformGlobalVariable.h.


AlderLake Platform Sample Code: PlatformGlobalVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PlatformGlobalVariable.h
Go to the documentation of this file.
1 /** @file
2 GUID for Platform (NVRAM) Variables.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_GLOBAL_VARIABLE_GUID_H__
36 #define __PLATFORM_GLOBAL_VARIABLE_GUID_H__
37
38 #define PLATFORM_GLOBAL_VARIABLE \
39 { \
40 0xa5dabcf0, 0xc7a1, 0x4370, { 0x8c, 0x21, 0xfa, 0x50, 0xd3, 0x22, 0xa4, 0x3e } \
41 }
42
43 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInfo.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Typedefs
PlatformInfo.h File Reference

GUID used for Platform Info Data entries in the HOB list. More...

#include <PlatformBoardType.h>
Include dependency graph for PlatformInfo.h:

Go to the source code of this file.

Typedefs

typedef UINT32 PCH_GPIO_PAD
PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h.

Detailed Description

GUID used for Platform Info Data entries in the HOB list.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file PlatformInfo.h.


AlderLake Platform Sample Code: PlatformInfo.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformInfo.h
Go to the documentation of this file.
1 /** @file
2 GUID used for Platform Info Data entries in the HOB list.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _PLATFORM_INFO_H_
37 #define _PLATFORM_INFO_H_
38
39 #include <PlatformBoardType.h>
40
41 #pragma pack(1)
42
43 ///
44 /// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h
45 ///
46 typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it based on include)
47
48 typedef struct {
49 UINT8 Expander;
50 UINT8 Pin;
51 UINT16 Reserved; // Reserved for future use
52 } IO_EXPANDER_PAD;
53
54 typedef union {
55 PCH_GPIO_PAD PchGpio;
56 IO_EXPANDER_PAD IoExpGpio;
57 } GPIO_PAD_CONFIG;
58
59 typedef struct {
60 UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH, 2: I/O Expander
61 UINT8 Reserved[3]; // Reserved for future use
62 GPIO_PAD_CONFIG GpioData;
63 } PACKED_GPIO_CONFIG;
64
65 typedef union {
66 PACKED_GPIO_CONFIG PackedGpio;
67 UINT64 Data64;
68 } COMMON_GPIO_CONFIG;
69
70 #pragma pack()
71
72 #endif
PCH_GPIO_PAD
UINT32 PCH_GPIO_PAD
PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h.
Definition: PlatformInfo.h:46
PlatformBoardType.h
BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
Functions
PlatformInitAdvancedDxe.c File Reference

Source code file for the Platform Init Advanced DXE module. More...

#include "PlatformInitAdvancedDxe.h"
#include <CpuRegs.h>
#include <Guid/EventGroup.h>
#include <Library/BootGuardLibVer1.h>
#include <Protocol/CpuInfo.h>
#include <Protocol/PlatformNvsArea.h>
#include <Protocol/VariableLock.h>
#include <Library/CpuPlatformLib.h>
#include <Library/SmbiosProcessorLib.h>
#include <Guid/TpmInstance.h>
#include <Library/Tpm2CommandLib.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Register/Cpuid.h>
#include <Register/PmcRegs.h>
#include <Protocol/Tcg2Protocol.h>
#include <Library/TpmMeasurementLib.h>
#include <Library/UefiLib.h>
#include <Protocol/ResetNotification.h>
#include <Library/CpuPcieRpLib.h>
#include <Register/CommonMsr.h>
#include <Register/AdlMsr.h>
#include <Library/DxeServicesTableLib.h>
#include <Library/MtrrLib.h>
#include <Library/SiMtrrLib.h>
#include <Protocol/MpService.h>
#include <PlatformBoardId.h>
#include <Library/DccProgramLib.h>
#include <Pi/PiStatusCode.h>
#include <Library/ReportStatusCodeLib.h>
Include dependency graph for PlatformInitAdvancedDxe.c:

Go to the source code of this file.

Functions

VOID | PlatformResetNotificationCallback (IN EFI_RESET_TYPE ResetType, IN EFI_STATUS ResetStatus, IN UINTN DataSize, IN VOID *ResetData OPTIONAL)
Call back function for reset notification. More...
VOID | EndofDxeCallback (IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInit task at the end of DXE. More...
VOID | RegisterEndOfDxeCallbacks (VOID)
Registers callback for.PlatformInitEndOfDxe. More...
VOID | SetMtrrsFromBuffer (IN VOID *Buffer)
A minimal wrapper function that allows MtrrSetAllMtrrs () to be passed to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs () as Procedure. More...
VOID | PlatformDxeReadyToBootCallback (IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInitDxe task at the ready to boot. More...
VOID | RegisterReadyToBootCallback (VOID)
Registers callback for PlatformDxeReadyToBoot.
VOID | OnResetNotifyInstall (IN EFI_EVENT Event, IN VOID *Context)
Hook to reset notification protocol to properly reset function with TPM. More...
VOID | ExtendPCR7CallBack (IN EFI_EVENT Event, IN VOID *Context)
Security EndOfDxe CallBack Function If the firmware/BIOS has an option to enable and disable DMA protections via a VT-d switch in BIOS options, then the shipping configuration must be with VT-d protection enabled. More...
VOID | RegisterExtendPCR7CallBack (VOID)
Register an End of DXE event for extended a TPM log to PCR[7] when vtd is disable This feature is introduced by TBT Security requirment.
EFI_STATUS | AllocateMemoryBelow4G (IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address. More...
EFI_STATUS | ReadLowPowerModeRequirementReg (VOID)
Read And load the LPM register in NVS area.
EFI_STATUS | UpdateMemorySpaceAttributes ()
Update memory space attributes.
UINT16 | GetDccCurrentFreq (IN UINT16 Integer, IN UINT32 Fractional)
Get DCC current frequencies. More...
EFI_STATUS | PlatformInitAdvancedDxeEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point for the driver. More...

Detailed Description

Source code file for the Platform Init Advanced DXE module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedDxe.c.

Function Documentation

◆ AllocateMemoryBelow4G()

EFI_STATUS AllocateMemoryBelow4G | ( | IN EFI_MEMORY_TYPE | MemoryType,
 |  | IN UINTN | Size,
 |  | OUT VOID ** | Buffer
 | ) |  |

Allocate MemoryType below 4G memory address.

Parameters
[in] | MemoryType | The type of memory to allocate
[in] | Size | Size of memory to allocate.
[OUT] | Buffer Allocated address for output.
Return values
EFI_SUCCESS | Memory successfully allocated.
Other | Other errors occur.

Definition at line 588 of file PlatformInitAdvancedDxe.c.

◆ EndofDxeCallback()

VOID EndofDxeCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function handles PlatformInit task at the end of DXE.

Parameters
[in] | Event | The Event this notify function registered to.
[in] | Context | Pointer to the context data registered to the Event.

Verify if Boot Guard is supported

Identify if Revocation is requested by Boot Guard ACM

Definition at line 91 of file PlatformInitAdvancedDxe.c.

◆ ExtendPCR7CallBack()

VOID ExtendPCR7CallBack | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Security EndOfDxe CallBack Function If the firmware/BIOS has an option to enable and disable DMA protections via a VT-d switch in BIOS options, then the shipping configuration must be with VT-d protection enabled.

On every boot where VT-d/DMA protection is disabled, or will be disabled, or configured to a lower security state, and a platform has a TPM enabled, then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data. Measure and log launch of TBT Security, and extend the measurement result into a specific PCR. Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data.

Parameters
[in] | Event | - A pointer to the Event that triggered the callback.
[in] | Context | - A pointer to private data registered with the callback function.

Definition at line 381 of file PlatformInitAdvancedDxe.c.

◆ GetDccCurrentFreq()

UINT16 GetDccCurrentFreq | ( | IN UINT16 | Integer,
 |  | IN UINT32 | Fractional
 | ) |  |

Get DCC current frequencies.

Parameters
[in] | Integer | The integer parts of divider register.
[in] | Fractional | The fractional parts of divider register.
Return values
Frequency Discrete Clock frequency.

Definition at line 705 of file PlatformInitAdvancedDxe.c.

◆ OnResetNotifyInstall()

VOID OnResetNotifyInstall | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Hook to reset notification protocol to properly reset function with TPM.

Parameters
[in] | Event | Event whose notification function is being invoked
[in] | Context | Pointer to the notification function's context

Definition at line 350 of file PlatformInitAdvancedDxe.c.

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◆ PlatformDxeReadyToBootCallback()

VOID PlatformDxeReadyToBootCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function handles PlatformInitDxe task at the ready to boot.

Parameters
[in] | Event | The Event this notify function registered to.
[in] | Context | Pointer to the context data registered to the Event.

Definition at line 203 of file PlatformInitAdvancedDxe.c.

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◆ PlatformInitAdvancedDxeEntryPoint()

EFI_STATUS PlatformInitAdvancedDxeEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Entry point for the driver.

Parameters
[in] | ImageHandle | Image Handle.
[in] | SystemTable | EFI System Table.
Return values
EFI_SUCCESS | Function has completed successfully.
Others | All other error conditions encountered result in an ASSERT.

Definition at line 735 of file PlatformInitAdvancedDxe.c.

◆ PlatformResetNotificationCallback()

VOID PlatformResetNotificationCallback | ( | IN EFI_RESET_TYPE | ResetType,
 |  | IN EFI_STATUS | ResetStatus,
 |  | IN UINTN | DataSize,
 |  | IN VOID *ResetData | OPTIONAL
 | ) |  |

Call back function for reset notification.

Parameters
[in] | ResetType | UEFI defined reset type.
[in] | ResetStatus | The status code for the reset.
[in] | DataSize | The size of ResetData in bytes.
[in] | ResetData | Optional element used to introduce a platform specific reset. The exact type of the reset is defined by the EFI_GUID that follows the Null-terminated Unicode string.

Definition at line 325 of file PlatformInitAdvancedDxe.c.

◆ RegisterEndOfDxeCallbacks()

VOID RegisterEndOfDxeCallbacks ( VOID )

Registers callback for.PlatformInitEndOfDxe.

Performing PlatformInitEndOfDxe after the gEfiEndOfDxeEventGroup is signaled.

Definition at line 156 of file PlatformInitAdvancedDxe.c.

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◆ SetMtrrsFromBuffer()

VOID SetMtrrsFromBuffer ( IN VOID * Buffer )

A minimal wrapper function that allows MtrrSetAllMtrrs () to be passed to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs () as Procedure.

Parameters
[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to MtrrSetAllMtrrs ().

Definition at line 187 of file PlatformInitAdvancedDxe.c.


AlderLake Platform Sample Code: PlatformInitAdvancedDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
PlatformInitAdvancedDxe.c
Go to the documentation of this file.
1 /** @file
2 Source code file for the Platform Init Advanced DXE module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PlatformInitAdvancedDxe.h"
35 #include <CpuRegs.h>
36 #include <Guid/EventGroup.h>
37 #include <Library/BootGuardLibVer1.h>
38 #include <Protocol/CpuInfo.h>
39 #include <Protocol/PlatformNvsArea.h>
40 #include <Protocol/VariableLock.h>
41 #include <Library/CpuPlatformLib.h>
42 #include <Library/SmbiosProcessorLib.h>
43 #include <Guid/TpmInstance.h>
44 #include <Library/Tpm2CommandLib.h>
45 #include <Library/PostCodeLib.h>
46 #include <PlatformPostCode.h>
47 #include <Register/Cpuid.h>
48 #include <Register/PmcRegs.h>
49 #include <Protocol/Tcg2Protocol.h>
50 #include <Library/TpmMeasurementLib.h>
51 #include <Library/UefiLib.h>
52 #include <Protocol/ResetNotification.h>
53 #if FixedPcdGetBool (PcdDTbtEnable) == 1
54 #include <DTbtInfoHob.h>
55 #include <Library/DxeTbtSecurityLib.h>
56 #endif
57 #include <Library/CpuPcieRpLib.h>
58 #include <Register/CommonMsr.h>
59 #include <Register/AdlMsr.h>
60 #include <Library/DxeServicesTableLib.h>
61 #include <Library/MtrrLib.h>
62 #include <Library/SiMtrrLib.h>
63 #include <Protocol/MpService.h>
64 #include <PlatformBoardId.h>
65 #include <Library/DccProgramLib.h>
66 #include <Pi/PiStatusCode.h>
67 #include <Library/ReportStatusCodeLib.h>
68
69
70 GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT EndOfDxeEvent;
71 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL *mPlatformNvsAreaProtocol;
72 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA *mPlatformNvsAreaPtr;
73 VOID
74 EFIAPI
75 PlatformResetNotificationCallback (
76 IN EFI_RESET_TYPE ResetType,
77 IN EFI_STATUS ResetStatus,
78 IN UINTN DataSize,
79 IN VOID *ResetData OPTIONAL
80 );
81
82 /**
83 This function handles PlatformInit task at the end of DXE
84
85 @param[in] Event The Event this notify function registered to.
86 @param[in] Context Pointer to the context data registered to the
87 Event.
88 **/
89 VOID
90 EFIAPI
91 EndofDxeCallback (
92 IN EFI_EVENT Event,
93 IN VOID *Context
94 )
95 {
96 MSR_ANC_SACM_INFO_REGISTER AncSacmInfoMsr;
97 static BOOLEAN S3DataSaved = FALSE;
98 UINT16 ABase;
99 UINT32 SmiEn;
100 UINT16 Pm1Sts;
101
102 gBS->CloseEvent (Event);
103
104 if (S3DataSaved) {
105 return ;
106 }
107
108 ABase = PmcGetAcpiBase ();
109 SmiEn = IoRead32 (ABase + R_ACPI_IO_SMI_EN);
110 //
111 // Disabled Legacy USB Logic that generates SMI, during S3 Resume.
112 //
113 SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB | B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_PERIODIC | B_ACPI_IO_SMI_EN_SWSMI_TMR);
114
115 S3BootScriptSaveIoWrite (
116 S3BootScriptWidthUint32,
117 (UINTN) (ABase + R_ACPI_IO_SMI_EN),
118 1,
119 &SmiEn
120 );
121 //
122 // Clear bust master status bit on S3 resume
123 //
124 Pm1Sts = B_ACPI_IO_PM1_STS_BM;
125
126 S3BootScriptSaveIoWrite (
127 S3BootScriptWidthUint16,
128 (UINTN) (ABase + R_ACPI_IO_PM1_STS),
129 1,
130 &Pm1Sts
131 );
132
133 S3DataSaved = TRUE;
134
135
136 ///
137 /// Verify if Boot Guard is supported
138 ///
139 if (IsBootGuardSupported ()) {
140 AncSacmInfoMsr.Uint64 = AsmReadMsr64 (MSR_ANC_SACM_INFO);
141 ///
142 /// Identify if Revocation is requested by Boot Guard ACM
143 ///
144 if (AncSacmInfoMsr.Bits.SacmData & BIT7) {
145 BootGuardOemRevocationHook ();
146 }
147 }
148
149 }
150
151 /**
152 Registers callback for.PlatformInitEndOfDxe
153
154 **/
155 VOID
156 RegisterEndOfDxeCallbacks (
157 VOID
158 )
159 {
160 EFI_STATUS Status;
161
162 ///
163 /// Performing PlatformInitEndOfDxe after the gEfiEndOfDxeEventGroup is signaled.
164 ///
165 Status = gBS->CreateEventEx (
166 EVT_NOTIFY_SIGNAL,
167 TPL_CALLBACK,
168 EndofDxeCallback,
169 NULL,
170 &gEfiEndOfDxeEventGroupGuid,
171 &EndOfDxeEvent
172 );
173 ASSERT_EFI_ERROR (Status);
174
175 }
176
177
178 /**
179 A minimal wrapper function that allows MtrrSetAllMtrrs () to be passed to
180 EFI_MP_SERVICES_PROTOCOL.StartupAllAPs () as Procedure.
181
182 @param[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to
183 MtrrSetAllMtrrs ().
184 **/
185 VOID
186 EFIAPI
187 SetMtrrsFromBuffer (
188 IN VOID *Buffer
189 )
190 {
191 MtrrSetAllMtrrs (Buffer);
192 }
193
194
195 /**
196 This function handles PlatformInitDxe task at the ready to boot
197
198 @param[in] Event The Event this notify function registered to.
199 @param[in] Context Pointer to the context data registered to the Event.
200 **/
201 VOID
202 EFIAPI
203 PlatformDxeReadyToBootCallback (
204 IN EFI_EVENT Event,
205 IN VOID *Context
206 )
207 {
208 EFI_STATUS Status;
209 MTRR_SETTINGS MtrrSetting;
210 EFI_MP_SERVICES_PROTOCOL *MpService;
211
212 DEBUG ((DEBUG_INFO, "PlatformDxeReadyToBootCallback start\n"));
213
214 Status = MtrrTransfer2DefaultWB (&MtrrSetting);
215 if (EFI_ERROR (Status)) {
216 return;
217 }
218
219 #if FixedPcdGetBool(PcdExtendedBiosRegionSupport) == 1
220 DEBUG ((DEBUG_INFO, "[BIOS] PlatformDxeReadyToBootCallback\n"));
221 UINT32 ExtendedBiosRegionBaseAddress;
222 UINT32 ExtendedBiosRegionSize;
223 MTRR_SETTINGS ExtendedBiosRegionUCMtrrSetting;
224
225 ExtendedBiosRegionBaseAddress = 0xF8000000;
226 ExtendedBiosRegionSize = SIZE_32MB;
227 ///
228 /// Reset all MTRR setting.
229 ///
230 ZeroMem (&ExtendedBiosRegionUCMtrrSetting, sizeof (MTRR_SETTINGS));
231
232 //
233 // Get the Current MTRR Settings
234 //
235 MtrrGetAllMtrrs (&ExtendedBiosRegionUCMtrrSetting);
236
237 Status = MtrrSetMemoryAttributeInMtrrSettings (
238 &ExtendedBiosRegionUCMtrrSetting,
239 ExtendedBiosRegionBaseAddress,
240 ExtendedBiosRegionSize,
241 CacheUncacheable
242 );
243
244 if (EFI_ERROR (Status)) {
245 REPORT_STATUS_CODE_EX (
246 (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED),
247 (EFI_COMPUTING_UNIT_HOST_PROCESSOR|EFI_CU_HP_EC_CACHE),
248 0,
249 &gCpuFspErrorTypeCallerId,
250 NULL,
251 NULL,
252 0
253 );
254 }
255
256 ///
257 /// Update MTRR setting from MTRR buffer
258 ///
259 MtrrSetAllMtrrs (&ExtendedBiosRegionUCMtrrSetting);
260 MtrrDebugPrintAllMtrrs ();
261 #endif
262
263 //
264 // Synchronize the update with all APs
265 //
266 Status = gBS->LocateProtocol (
267 &gEfiMpServiceProtocolGuid,
268 NULL,
269 (VOID **)&MpService
270 );
271 if (!EFI_ERROR (Status)) {
272 MtrrGetAllMtrrs (&MtrrSetting);
273 MpService->StartupAllAPs (
274 MpService, // This
275 SetMtrrsFromBuffer, // Procedure
276 FALSE, // SingleThread
277 NULL, // WaitEvent
278 0, // TimeoutInMicrosecsond
279 &MtrrSetting, // ProcedureArgument
280 NULL // FailedCpuList
281 );
282 }
283
284 DEBUG ((DEBUG_INFO, "PlatformDxeReadyToBootCallback end\n"));
285
286 gBS->CloseEvent (Event);
287
288 return;
289 }
290
291 /**
292 Registers callback for PlatformDxeReadyToBoot
293
294 **/
295 VOID
296 RegisterReadyToBootCallback (
297 VOID
298 )
299 {
300 EFI_STATUS Status;
301 EFI_EVENT Event;
302
303 Status = EfiCreateEventReadyToBootEx (
304 TPL_CALLBACK,
305 PlatformDxeReadyToBootCallback,
306 NULL,
307 &Event
308 );
309
310 ASSERT_EFI_ERROR (Status);
311 }
312
313 /**
314 Call back function for reset notification.
315
316 @param[in] ResetType UEFI defined reset type.
317 @param[in] ResetStatus The status code for the reset.
318 @param[in] DataSize The size of ResetData in bytes.
319 @param[in] ResetData Optional element used to introduce a platform specific reset.
320 The exact type of the reset is defined by the EFI_GUID that follows
321 the Null-terminated Unicode string.
322 **/
323 VOID
324 EFIAPI
325 PlatformResetNotificationCallback (
326 IN EFI_RESET_TYPE ResetType,
327 IN EFI_STATUS ResetStatus,
328 IN UINTN DataSize,
329 IN VOID *ResetData OPTIONAL
330 )
331 {
332 EFI_STATUS Status;
333
334 DEBUG ((DEBUG_INFO, "PlatformResetNotificationCallback\n"));
335
336 Status = Tpm2Shutdown (TPM_SU_CLEAR);
337 if (EFI_ERROR (Status)) {
338 DEBUG ((DEBUG_ERROR, "Tpm2Shutdown (TPM_SU_CLEAR) failed: %r\n", Status));
339 }
340 }
341
342
343 /**
344 Hook to reset notification protocol to properly reset function with TPM.
345 @param[in] Event Event whose notification function is being invoked
346 @param[in] Context Pointer to the notification function's context
347 **/
348 VOID
349 EFIAPI
350 OnResetNotifyInstall (
351 IN EFI_EVENT Event,
352 IN VOID *Context
353 )
354 {
355
356 EFI_STATUS Status;
357 EFI_RESET_NOTIFICATION_PROTOCOL *ResetNotify;
358
359 Status = gBS->LocateProtocol (&gEfiResetNotificationProtocolGuid, NULL, (VOID **) &ResetNotify);
360 if (!EFI_ERROR (Status)) {
361 ResetNotify->RegisterResetNotify (ResetNotify, PlatformResetNotificationCallback);
362 if(Event) gBS->CloseEvent (Event);
363 }
364 }
365
366 /**
367 Security EndOfDxe CallBack Function
368 If the firmware/BIOS has an option to enable and disable DMA protections via a VT-d switch in BIOS options, then the shipping configuration must be with VT-d protection enabled.
369 On every boot where VT-d/DMA protection is disabled, or will be disabled, or configured to a lower security state, and a platform has a TPM enabled, then the platform SHALL
370 extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA
371 The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data.
372 Measure and log launch of TBT Security, and extend the measurement result into a specific PCR.
373 Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement
374 in the event log using the string "DMA Protection Disabled" for the Event Data.
375
376 @param[in] Event - A pointer to the Event that triggered the callback.
377 @param[in] Context - A pointer to private data registered with the callback function.
378 **/
379 VOID
380 EFIAPI
381 ExtendPCR7CallBack (
382 IN EFI_EVENT Event,
383 IN VOID *Context
384 )
385 {
386 UINTN Status;
387 UINT64 HashDataLen;
388 PCR7_DATA *PCR7DataPtr;
389
390 DEBUG ((DEBUG_INFO, "ExtendPCR7CallBack START\n"));
391
392 if (Context == NULL) {
393 DEBUG ((DEBUG_INFO, "ExtendPCR7CallBack function ERROR\n"));
394 return;
395 }
396
397 PCR7DataPtr = (PCR7_DATA*) Context;
398
399 if (PCR7DataPtr->EnableVtd == FALSE) {
400 //
401 // When VT-d/DMA protection is disabled and a platform has a TPM enabled,
402 // the platform SHALL extend an EV_EFI_ACTION event into PCR[7]
403 //
404 HashDataLen = SECURITY_EVENT_STRING_LEN;
405
406 Status = TpmMeasureAndLogData (
407 7,
408 EV_EFI_ACTION,
409 SECURITY_EVENT_STRING,
410 (UINT32) HashDataLen,
411 SECURITY_EVENT_STRING,
412 HashDataLen
413 );
414 if (EFI_ERROR(Status)) {
415 DEBUG ((DEBUG_ERROR, "VT-d TpmMeasureAndLogData Status: %d\n", Status));
416 } else {
417 DEBUG ((DEBUG_INFO, "VT-d TpmMeasureAndLogData Successfully\n"));
418 }
419 }
420
421 #if FixedPcdGetBool (PcdDTbtEnable) == 1
422 if (PCR7DataPtr->SLDowngrade == TRUE) {
423 //
424 // When TBT security mode downgrade to 0 and a platform has a TPM enabled,
425 // the platform SHALL extend an EV_EFI_ACTION event into PCR[7]
426 //
427 HashDataLen = TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN;
428
429 Status = TpmMeasureAndLogData (
430 7,
431 EV_EFI_ACTION,
432 TBT_SECURITY_LEVEL_DOWNGRADED_STRING,
433 (UINT32)HashDataLen,
434 TBT_SECURITY_LEVEL_DOWNGRADED_STRING,
435 HashDataLen
436 );
437 if (EFI_ERROR (Status)) {
438 DEBUG ((DEBUG_ERROR, "TBT SL downgrade to 0, TpmMeasureAndLogData Status: %d\n", Status));
439 }
440 else {
441 DEBUG ((DEBUG_INFO, "TBT SL downgrade to 0,TpmMeasureAndLogData Successfully\n"));
442 }
443 }
444 #endif
445 if (PCR7DataPtr != NULL) {
446 FreePool(PCR7DataPtr);
447 }
448
449 DEBUG ((DEBUG_INFO, "ExtendPCR7CallBack END\n"));
450 }
451
452 /**
453 Register an End of DXE event for extended a TPM log to PCR[7] when vtd is disable
454 This feature is introduced by TBT Security requirment
455 **/
456 VOID
457 RegisterExtendPCR7CallBack (
458 VOID
459 )
460 {
461 EFI_STATUS Status;
462 UINTN DataSize;
463 SA_SETUP *SaSetup;
464 BOOLEAN SLDowngrade;
465 #if FixedPcdGetBool (PcdDTbtEnable) == 1
466 UINT8 Index;
467 UINT8 DTbtController[MAX_DTBT_CONTROLLER_NUMBER];
468 #endif
469 PCR7_DATA *PCR7DataPtr;
470 #if FixedPcdGetBool (PcdDTbtEnable) == 1
471 DTBT_INFO_HOB *DTbtInfoHob;
472 UINT8 CurrentSecurityMode;
473 #endif
474
475 Status = EFI_SUCCESS;
476 SaSetup = NULL;
477 DataSize = 0;
478 SLDowngrade = FALSE;
479 PCR7DataPtr = NULL;
480 #if FixedPcdGetBool (PcdDTbtEnable) == 1
481 DTbtInfoHob = NULL;
482 #endif
483
484 DataSize = sizeof (SA_SETUP);
485 SaSetup = AllocateZeroPool (DataSize);
486 if (SaSetup == NULL) {
487 DEBUG ((DEBUG_ERROR, "Failed to allocate SaSetup size\n"));
488 Status = EFI_OUT_OF_RESOURCES;
489 goto Exit;
490 }
491
492 Status = gRT->GetVariable (
493 L"SaSetup",
494 &gSaSetupVariableGuid,
495 NULL,
496 &DataSize,
497 SaSetup
498 );
499 if (EFI_ERROR (Status)) {
500 DEBUG ((DEBUG_ERROR, "Get SaSetup Status: %d\n", Status));
501 goto Exit;
502 }
503
504 #if FixedPcdGetBool (PcdDTbtEnable) == 1
505
506 //
507 // Get TBT INFO HOB
508 //
509 DTbtInfoHob = (DTBT_INFO_HOB *) GetFirstGuidHob (&gDTbtInfoHobGuid);
510 if (DTbtInfoHob != NULL) {
511 if (DTbtInfoHob->DTbtControllerConfig[0].DTbtControllerEn == 1 || DTbtInfoHob->DTbtControllerConfig[1].DTbtControllerEn == 1) {
512 for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
513 DTbtController[Index] = DTbtInfoHob->DTbtControllerConfig[Index].DTbtControllerEn;
514 }
515 //
516 // Check current security mode
517 //
518 CurrentSecurityMode = GetSetSecurityMode (
519 0,
520 DTbtController,
521 MAX_DTBT_CONTROLLER_NUMBER,
522 GET_TBT_SECURITY_MODE
523 );
524
525 if ((CurrentSecurityMode != 0) && (CurrentSecurityMode != 5)) {
526 // Code shouldn't run to here
527 DEBUG ((DEBUG_ERROR, "Code shouldn't run to here, it means security level got changed unintentionaly\n"));
528 SLDowngrade = TRUE;
529 }
530 }
531
532 }
533 #endif
534 if ((SaSetup->EnableVtd == FALSE) || (SLDowngrade == TRUE)) {
535 DataSize = sizeof (PCR7_DATA);
536 PCR7DataPtr = AllocateZeroPool (DataSize);
537 if (PCR7DataPtr == NULL) {
538 DEBUG ((DEBUG_ERROR, "Failed to allocate PCR7 data size\n"));
539 Status = EFI_OUT_OF_RESOURCES;
540 goto Exit;
541 }
542
543 PCR7DataPtr->EnableVtd = SaSetup->EnableVtd;
544 PCR7DataPtr->SLDowngrade = SLDowngrade;
545
546 //
547 // Register an End of DXE event for extended a TPM log to PCR[7]
548 //
549 DEBUG ((DEBUG_ERROR, "Register an End of DXE event for extended a TPM log to PCR[7] when Vtd is disable\n"));
550 Status = gBS->CreateEventEx (
551 EVT_NOTIFY_SIGNAL,
552 TPL_CALLBACK,
553 ExtendPCR7CallBack,
554 PCR7DataPtr,
555 &gEfiEndOfDxeEventGroupGuid,
556 &EndOfDxeEvent
557 );
558 if (EFI_ERROR (Status)) {
559 DEBUG ((DEBUG_ERROR, "Failed to register an End of DXE event for extended a TPM log to PCR[7], Status: %d\n", Status));
560 gBS->CloseEvent (EndOfDxeEvent);
561 goto Exit;
562 }
563 }
564
565 Exit:
566 if (SaSetup != NULL) {
567 FreePool (SaSetup);
568 }
569
570 if (EFI_ERROR (Status)) {
571 if (PCR7DataPtr != NULL) {
572 FreePool (PCR7DataPtr);
573 }
574 }
575 }
576
577 /**
578 Allocate MemoryType below 4G memory address.
579
580 @param[in] MemoryType The type of memory to allocate
581 @param[in] Size Size of memory to allocate.
582 @param[OUT] Buffer Allocated address for output.
583
584 @retval EFI_SUCCESS Memory successfully allocated.
585 @retval Other Other errors occur.
586 **/
587 EFI_STATUS
588 AllocateMemoryBelow4G(
589 IN EFI_MEMORY_TYPE MemoryType,
590 IN UINTN Size,
591 OUT VOID **Buffer
592 )
593 {
594 UINTN Pages;
595 EFI_PHYSICAL_ADDRESS Address;
596 EFI_STATUS Status;
597
598 Pages = EFI_SIZE_TO_PAGES(Size);
599 Address = 0xffffffff;
600
601 Status = (gBS->AllocatePages) (
602 AllocateMaxAddress,
603 MemoryType,
604 Pages,
605 &Address
606 );
607 DEBUG((DEBUG_INFO, "AllocateMemoryBelow4G: %r\n", Status));
608 *Buffer = (VOID *)(UINTN)Address;
609
610 return Status;
611 };
612
613 /**
614 Read And load the LPM register in NVS area
615 **/
616 EFI_STATUS
617 ReadLowPowerModeRequirementReg(
618 VOID
619 )
620 {
621 EFI_STATUS Status;
622 UINT32 *LpmData;
623 UINT32 LpmDataLen;
624
625 Status = gBS->LocateProtocol (
626 &gPlatformNvsAreaProtocolGuid,
627 NULL,
628 (VOID **)&mPlatformNvsAreaProtocol
629 );
630 DEBUG ((DEBUG_ERROR, "mPlatformNvsAreaProtocol: %r\n", Status));
631 ASSERT_EFI_ERROR (Status);
632 if (EFI_ERROR (Status)) {
633 return Status;
634 }
635
636 mPlatformNvsAreaPtr = mPlatformNvsAreaProtocol->Area;
637
638 LpmDataLen = V_PMC_PWRM_LPM_REQ_DATA_LEN; //LPM register counter is 48, so length is 192 byte
639
640 // Allocate memory in ACPI NVS
641 //
642 Status = AllocateMemoryBelow4G (EfiACPIMemoryNVS, LpmDataLen, (VOID **)&LpmData);
643 ASSERT_EFI_ERROR (Status);
644 if (EFI_ERROR (Status)) {
645 return Status;
646 }
647
648 ZeroMem (LpmData, LpmDataLen);
649
650 //
651 // Read out LPM requiremetn register data
652 //
653 Status = PmcReadLpmReqData (LpmData, LpmDataLen);
654 if (EFI_ERROR (Status)) {
655 return Status;
656 }
657
658 mPlatformNvsAreaPtr->LpmReqRegAddr = (UINT32) (UINTN) LpmData;
659
660 return Status;
661 }
662
663 /**
664 Update memory space attributes.
665 **/
666 EFI_STATUS
667 EFIAPI
668 UpdateMemorySpaceAttributes (
669 )
670 {
671 EFI_STATUS Status;
672 EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;
673 EFI_PHYSICAL_ADDRESS BaseAddress;
674 UINT64 Length;
675
676 BaseAddress = PcdGet64 (PcdPciExpressBaseAddress);;
677 Length = PcdGet32 (PcdPciExpressRegionLength);
678
679 Status = gDS->GetMemorySpaceDescriptor (BaseAddress, &GcdDescriptor);
680 if (EFI_ERROR (Status)) {
681 DEBUG ((DEBUG_ERROR, "UpdateMemorySpaceAttributes failed to get memory space descriptor.\n"));
682 } else {
683 Status = gDS->SetMemorySpaceAttributes (
684 BaseAddress,
685 Length,
686 GcdDescriptor.Attributes | EFI_MEMORY_RUNTIME
687 );
688 if (EFI_ERROR (Status)) {
689 DEBUG ((DEBUG_ERROR, "UpdateMemorySpaceAttributes failed to add EFI_MEMORY_RUNTIME attribute.\n"));
690 }
691 }
692
693 return Status;
694 }
695
696 /**
697 Get DCC current frequencies.
698
699 @param[in] Integer The integer parts of divider register.
700 @param[in] Fractional The fractional parts of divider register.
701
702 @retval Frequency Discrete Clock frequency.
703 **/
704 UINT16
705 GetDccCurrentFreq (
706 IN UINT16 Integer,
707 IN UINT32 Fractional
708 )
709 {
710 UINT64 DividerValue;
711 UINT64 DefualtFreq;
712
713 DividerValue = (Integer % BIT9);// The RC260x chip only provide [8:0] for integer register
714 DividerValue = LShiftU64 (DividerValue, 28);
715 DividerValue += (Fractional % BIT28); // The RC260x chip only provide [27:0] for fraction register
716
717 DefualtFreq = RENESAS_260X_CHIP_FREQUENCY;
718 DefualtFreq = LShiftU64 (DefualtFreq, 28);
719
720 return (DividerValue == 0)? 0 : (UINT16)(DefualtFreq / DividerValue);
721 }
722
723
724 /**
725 Entry point for the driver.
726
727 @param[in] ImageHandle Image Handle.
728 @param[in] SystemTable EFI System Table.
729
730 @retval EFI_SUCCESS Function has completed successfully.
731 @retval Others All other error conditions encountered result in an ASSERT.
732 **/
733 EFI_STATUS
734 EFIAPI
735 PlatformInitAdvancedDxeEntryPoint (
736 IN EFI_HANDLE ImageHandle,
737 IN EFI_SYSTEM_TABLE *SystemTable
738 )
739 {
740 EFI_STATUS Status;
741 SETUP_DATA SetupData;
742 UINTN VariableSize;
743 UINT32 VariableAttr;
744 UINT8 *SecureBootState;
745 VOID *Registration;
746 REGISTER_INTEGER Integer;
747 REGISTER_FRACTIONAL Fractional;
748 PostCode (PLATFORM_INIT_DXE_ENTRY);
749 Status = EFI_SUCCESS;
750
751 #if FixedPcdGetBool (PcdSinitAcmBinEnable) == 1
752 Status = TxtSinitAcmLoad ();
753 if (Status == EFI_SUCCESS) {
754 DEBUG ((DEBUG_INFO, "TXTDXE: Found SINIT ACM In FV\n"));
755 } else {
756 DEBUG ((DEBUG_INFO, "TXTDXE: Error finding SINIT binary in FVs\n"));
757 }
758 #endif
759
760 SecureBootState = NULL;
761 GetVariable2 (L"SecureBootEnable", &gEfiSecureBootEnableDisableGuid, (VOID**)&SecureBootState, NULL);
762
763 //
764 // Set CsmControl Setup variable reflecting Secure boot status. Whenever Secure boot is enabled, CSM must be turned off.
765 //
766 VariableSize = sizeof (SETUP_DATA);
767 Status = gRT->GetVariable (
768 L"Setup",
769 &gSetupVariableGuid,
770 &VariableAttr,
771 &VariableSize,
772 &SetupData
773 );
774 ASSERT_EFI_ERROR (Status);
775
776 SetupData.OpRomPost = OPROM_EFI;
777
778 if ((SecureBootState != NULL) && (*SecureBootState)) {
779 if (!EFI_ERROR (Status)) {
780 SetupData.OpRomPost = OPROM_EFI;
781 }
782 }
783
784 //
785 // Update Cpu BCLK & PEG/DMI Freq.
786 //
787 if (PcdGetBool (PcdDiscreteClockOcSupport) == TRUE) {
788 if (SetupData.DccClkCtrl == 1) {
789 GetCurrentDividerSettings (CPU_BCLK_OC_FOD, &Integer, &Fractional);
790 SetupData.CurrentCpuBclkFreq = GetDccCurrentFreq (Integer.Uint16, Fractional.Uint32);
791
792 GetCurrentDividerSettings (PEG_DMI_CLK_FOD, &Integer, &Fractional);
793 SetupData.CurrentPegDmiClkFreq = GetDccCurrentFreq (Integer.Uint16, Fractional.Uint32);
794 }
795 }
796 Status = gRT->SetVariable (
797 L"Setup",
798 &gSetupVariableGuid,
799 VariableAttr,
800 VariableSize,
801 &SetupData
802 );
803 ASSERT_EFI_ERROR (Status);
804
805 if (SecureBootState != NULL) {
806 FreePool (SecureBootState);
807 }
808
809
810 //
811 // Initialize System Agent platform settings
812 //
813 SaPlatformInitDxe ();
814
815 //
816 // Update DIMM funtionalities for desktop and server boards
817 //
818 UpdateDimmPopulation ();
819
820 ReadLowPowerModeRequirementReg ();
821
822 RegisterEndOfDxeCallbacks ();
823 RegisterReadyToBootCallback ();
824
825 //
826 // Add Smbios type 4 and type 7 table.
827 //
828 AddSmbiosProcessorAndCacheTables ();
829
830 //
831 // Check if TPM2.0 exist.
832 //
833 if (CompareGuid (PcdGetPtr (PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceNoneGuid)) {
834 } else if (CompareGuid (PcdGetPtr (PcdTpmInstanceGuid), &gEfiTpmDeviceInstanceTpm12Guid)) {
835 } else {
836 //
837 // Register Pch reset callback to shutdown TPM
838 //
839 EfiCreateProtocolNotifyEvent (
840 &gEfiResetNotificationProtocolGuid,
841 TPL_CALLBACK,
842 OnResetNotifyInstall,
843 NULL,
844 &Registration
845 );
846
847 }
848
849 //
850 // Inform OS by TPM PCR7 when Vtd is disable
851 //
852 RegisterExtendPCR7CallBack ();
853
854 UpdateMemorySpaceAttributes();
855
856
857 PostCode (PLATFORM_INIT_DXE_EXIT);
858
859 return Status;
860 }
861
862 #if FixedPcdGetBool(PcdSinitAcmBinEnable) == 1
863 /**
864
865 This function looks for SINIT ACM in FVs and updates TXT HOB
866 with SINIT ACM Base and Size.
867
868 @retval EFI_SUCCESS - SINIT ACM found and copied.
869 @retval EFI_NOT_FOUND - If TxtInfoHob is not found
870 @retval EFI_UNSUPPORTED - TXT Device memory not available.
871
872 **/
873 EFI_STATUS
874 TxtSinitAcmLoad (
875 VOID
876 )
877 {
878 EFI_STATUS Status;
879 TXT_INFO_HOB *HobList;
880 TXT_INFO_DATA *TxtInfoData;
881 EFI_HANDLE *HandleBuffer;
882 UINTN NumberOfHandles;
883 EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
884 UINTN Size;
885 EFI_FV_FILETYPE FileType;
886 UINT32 FvStatus;
887 EFI_FV_FILE_ATTRIBUTES Attributes;
888 UINT64 TxtHeapMemoryBase;
889 UINT64 TxtSinitMemoryBase;
890 UINT64 *Ptr64;
891 EFI_PHYSICAL_ADDRESS TopAddr;
892 BIOS_OS_DATA_REGION *BiosOsDataRegion;
893
894 HandleBuffer = NULL;
895 NumberOfHandles = 0;
896 FwVol = NULL;
897 FileType = 0;
898 Attributes = 0;
899 BiosOsDataRegion = NULL;
900
901 ///
902 /// Find TXT HOB
903 ///
904 HobList = (TXT_INFO_HOB *) GetFirstGuidHob (&gTxtInfoHobGuid);
905 if (HobList == NULL) {
906 return EFI_NOT_FOUND;
907 }
908
909 TxtInfoData = &HobList->Data;
910 ///
911 /// Check TXT mode
912 ///
913 if (TxtInfoData->TxtMode == 0) {
914 return EFI_UNSUPPORTED;
915 }
916
917 if ((TxtInfoData == 0) ||
918 (TxtInfoData->TxtDprMemoryBase == 0) ||
919 (TxtInfoData->TxtDprMemorySize == 0) ||
920 (TxtInfoData->TxtHeapMemorySize == 0) ||
921 (TxtInfoData->SinitMemorySize == 0)
922 ) {
923 return EFI_UNSUPPORTED;
924 } else {
925 ///
926 /// Use address passed from PEI
927 ///
928 TopAddr = TxtInfoData->TxtDprMemoryBase + TxtInfoData->TxtDprMemorySize;
929
930 TxtHeapMemoryBase = (UINT64) (TopAddr - TxtInfoData->TxtHeapMemorySize);
931
932 TxtSinitMemoryBase = TxtHeapMemoryBase - TxtInfoData->SinitMemorySize;
933 }
934 ///
935 /// Start looking for SINIT ACM in FVs
936 ///
937 DEBUG ((DEBUG_INFO, "TXTDXE: Looking for SINIT ACM in FVs\n"));
938
939 Status = gBS->LocateHandleBuffer (
940 ByProtocol,
941 &gEfiFirmwareVolume2ProtocolGuid,
942 NULL,
943 &NumberOfHandles,
944 &HandleBuffer
945 );
946 ASSERT_EFI_ERROR (Status);
947 ///
948 /// Looking for FV with SinitAC binary
949 ///
950 for (UINTN i = 0; i < NumberOfHandles; i++) {
951 ///
952 /// Get the protocol on this handle
953 ///
954 Status = gBS->HandleProtocol (
955 HandleBuffer[i],
956 &gEfiFirmwareVolume2ProtocolGuid,
957 &FwVol
958 );
959 ASSERT_EFI_ERROR (Status);
960 ///
961 /// See if it has the SinitACM file
962 ///
963 Size = 0;
964 FvStatus = 0;
965 Status = FwVol->ReadFile (
966 FwVol,
967 &gSinitModuleGuid,
968 NULL,
969 &Size,
970 &FileType,
971 &Attributes,
972 &FvStatus
973 );
974 ///
975 /// If the binary was located, then break
976 ///
977 if (Status == EFI_SUCCESS) {
978 DEBUG ((DEBUG_INFO, "TXTDXE: Found SINIT ACM In FV\n"));
979 break;
980 }
981 }
982 FreePool (HandleBuffer);
983 ///
984 /// Sanity check
985 ///
986 if ( !(FwVol == NULL || Status != EFI_SUCCESS || Size >= TxtInfoData->SinitMemorySize ) ) {
987 ///
988 /// Read Sinit ACM from the storage file.
989 ///
990 Ptr64 = (UINT64 *)TxtSinitMemoryBase;
991 Status = FwVol->ReadFile (
992 FwVol,
993 &gSinitModuleGuid,
994 &Ptr64,
995 &Size,
996 &FileType,
997 &Attributes,
998 &FvStatus
999 );
1000 ASSERT_EFI_ERROR (Status);
1001 TxtInfoData->SinitAcmSize = (UINT64) Size;
1002
1003 Ptr64 = (UINT64 *) TxtHeapMemoryBase;
1004 ///
1005 /// BiosOsDataSize plus size of data size field itself
1006 ///
1007 BiosOsDataRegion = (BIOS_OS_DATA_REGION *) (Ptr64 + 1);
1008 BiosOsDataRegion->BiosSinitSize = (UINT32) TxtInfoData->SinitAcmSize;
1009 DEBUG ((DEBUG_INFO, "TXTDXE: Copy SINIT ACM Done\n"));
1010 }
1011 return Status;
1012 }
1013 #endif
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
PlatformInitAdvancedDxe.h
Header file for Platform Init Advanced Dxe Driver.
PlatformInitAdvancedDxeEntryPoint
EFI_STATUS PlatformInitAdvancedDxeEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Entry point for the driver.
Definition: PlatformInitAdvancedDxe.c:735
RegisterEndOfDxeCallbacks
VOID RegisterEndOfDxeCallbacks(VOID)
Registers callback for.PlatformInitEndOfDxe.
Definition: PlatformInitAdvancedDxe.c:156
GetDccCurrentFreq
UINT16 GetDccCurrentFreq(IN UINT16 Integer, IN UINT32 Fractional)
Get DCC current frequencies.
Definition: PlatformInitAdvancedDxe.c:705
OnResetNotifyInstall
VOID OnResetNotifyInstall(IN EFI_EVENT Event, IN VOID *Context)
Hook to reset notification protocol to properly reset function with TPM.
Definition: PlatformInitAdvancedDxe.c:350
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitAdvancedDxe.c:241
ExtendPCR7CallBack
VOID ExtendPCR7CallBack(IN EFI_EVENT Event, IN VOID *Context)
Security EndOfDxe CallBack Function If the firmware/BIOS has an option to enable and disable DMA prot...
Definition: PlatformInitAdvancedDxe.c:381
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitAdvancedDxe.c:347
EndofDxeCallback
VOID EndofDxeCallback(IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInit task at the end of DXE.
Definition: PlatformInitAdvancedDxe.c:91
PlatformPostCode.h
BootGuardOemRevocationHook
VOID BootGuardOemRevocationHook(VOID)
Provide a hook for OEM to deal with Boot Guard revocation flow.
PlatformDxeReadyToBootCallback
VOID PlatformDxeReadyToBootCallback(IN EFI_EVENT Event, IN VOID *Context)
This function handles PlatformInitDxe task at the ready to boot.
Definition: PlatformInitAdvancedDxe.c:203
UpdateMemorySpaceAttributes
EFI_STATUS UpdateMemorySpaceAttributes()
Update memory space attributes.
Definition: PlatformInitAdvancedDxe.c:668
RegisterExtendPCR7CallBack
VOID RegisterExtendPCR7CallBack(VOID)
Register an End of DXE event for extended a TPM log to PCR[7] when vtd is disable This feature is int...
Definition: PlatformInitAdvancedDxe.c:457
AllocateMemoryBelow4G
EFI_STATUS AllocateMemoryBelow4G(IN EFI_MEMORY_TYPE MemoryType, IN UINTN Size, OUT VOID **Buffer)
Allocate MemoryType below 4G memory address.
Definition: PlatformInitAdvancedDxe.c:588
RegisterReadyToBootCallback
VOID RegisterReadyToBootCallback(VOID)
Registers callback for PlatformDxeReadyToBoot.
Definition: PlatformInitAdvancedDxe.c:296
PlatformResetNotificationCallback
VOID PlatformResetNotificationCallback(IN EFI_RESET_TYPE ResetType, IN EFI_STATUS ResetStatus, IN UINTN DataSize, IN VOID *ResetData OPTIONAL)
Call back function for reset notification.
Definition: PlatformInitAdvancedDxe.c:325
SetMtrrsFromBuffer
VOID SetMtrrsFromBuffer(IN VOID *Buffer)
A minimal wrapper function that allows MtrrSetAllMtrrs () to be passed to EFI_MP_SERVICES_PROTOCOL....
Definition: PlatformInitAdvancedDxe.c:187
ReadLowPowerModeRequirementReg
EFI_STATUS ReadLowPowerModeRequirementReg(VOID)
Read And load the LPM register in NVS area.
Definition: PlatformInitAdvancedDxe.c:617
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
Functions
PlatformInitAdvancedDxe.h File Reference

Header file for Platform Init Advanced Dxe Driver. More...

#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/HobLib.h>
#include <SetupVariable.h>
#include <Library/DebugLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/BootGuardRevocationLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/PrintLib.h>
#include <Library/UefiLib.h>
#include <Uefi/UefiBaseType.h>
#include <OemSetup.h>
#include <MemInfoHob.h>
#include <Library/PmcLib.h>
#include <Library/PciSegmentLib.h>
#include <Register/PmcRegs.h>
Include dependency graph for PlatformInitAdvancedDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

VOID | SaPlatformInitDxe (VOID)
System Agent platform Initialization.
VOID | UpdateDimmPopulation (VOID)
Updates DIMM slots status for Desktop,server and workstation boards.

Detailed Description

Header file for Platform Init Advanced Dxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedDxe.h.


AlderLake Platform Sample Code: PlatformInitAdvancedDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
PlatformInitAdvancedDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for Platform Init Advanced Dxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_INIT_ADVANCED_DXE_H_
36 #define _PLATFORM_INIT_ADVANCED_DXE_H_
37
38 #include <Library/IoLib.h>
39 #include <Library/PcdLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <Library/UefiRuntimeServicesTableLib.h>
42 #include <Library/HobLib.h>
43 #include <SetupVariable.h>
44 #include <Library/DebugLib.h>
45 #include <Library/S3BootScriptLib.h>
46 #include <Library/BootGuardRevocationLib.h>
47 #include <Library/BaseMemoryLib.h>
48 #include <Library/MemoryAllocationLib.h>
49 #include <Library/PrintLib.h>
50 #include <Library/UefiLib.h>
51 #include <Uefi/UefiBaseType.h>
52 #include <OemSetup.h>
53 #include <MemInfoHob.h>
54 #include <Library/PmcLib.h>
55 #include <Library/PciSegmentLib.h>
56 #include <Register/PmcRegs.h>
57 #if FixedPcdGetBool(PcdSinitAcmBinEnable) == 1
58 #include <TxtInfoHob.h>
59 #include <Txt.h>
60 #include <Protocol/FirmwareVolume2.h>
61 #endif
62
63 #define SECURITY_EVENT_STRING "DMA Protection Disabled"
64 #define SECURITY_EVENT_STRING_LEN (sizeof (SECURITY_EVENT_STRING) - 1)
65 #if FixedPcdGetBool (PcdDTbtEnable) == 1
66 #define TBT_SECURITY_LEVEL_DOWNGRADED_STRING "Security Level is Downgraded to 0"
67 #define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN (sizeof (TBT_SECURITY_LEVEL_DOWNGRADED_STRING) - 1)
68 #endif
69
70 typedef struct {
71 UINT8 EnableVtd;
72 BOOLEAN SLDowngrade;
73 } PCR7_DATA;
74
75 //----------------------------------------------------------------------------
76 // VT-d Engine Configuration Register Details
77 //----------------------------------------------------------------------------
78 #define SA_VTD_RMRR_USB_LENGTH 0x20000
79
80 VOID
81 SaPlatformInitDxe (
82 VOID
83 );
84
85 VOID
86 UpdateDimmPopulation (
87 VOID
88 );
89
90
91 #if FixedPcdGetBool (PcdSinitAcmBinEnable) == 1
92 /**
93
94 This function looks for SINIT ACM in FVs and updates TXT HOB
95 with SINIT ACM Base and Size.
96
97 @retval EFI_SUCCESS - SINIT ACM found and copied.
98 @retval EFI_NOT_FOUND - If TxtInfoHob is not found
99 @retval EFI_UNSUPPORTED - TXT Device memory not available.
100
101 **/
102 EFI_STATUS
103 TxtSinitAcmLoad (
104 VOID
105 );
106 #endif
107
108 #endif
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitAdvancedDxe.c:241
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitAdvancedDxe.c:347
OemSetup.h
OEM Specific Setup Variables and Structures.
BootGuardRevocationLib.h
Header file for Boot Guard revocation notification.
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedPostMem.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei
Functions
PlatformInitAdvancedPostMem.c File Reference

Source code file for Platform Init PEI module. More...

#include <Register/Msr.h>
#include <CpuRegs.h>
#include <SetupVariable.h>
#include <Library/IoLib.h>
#include <Library/HobLib.h>
#include <Library/DebugLib.h>
#include <Library/PchInfoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/PmcLib.h>
#include <Library/GpioLib.h>
#include <Library/GpioNativeLib.h>
#include <Ppi/EndOfPeiPhase.h>
#include <Library/MtrrLib.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Guid/SmramMemoryReserve.h>
#include <Library/ConfigBlockLib.h>
#include <Ppi/SiPolicy.h>
#include <PchPolicyCommon.h>
#include <Library/SiPolicyLib.h>
#include <Guid/FirmwareFileSystem2.h>
#include <Protocol/FirmwareVolumeBlock.h>
#include <Guid/SystemNvDataGuid.h>
#include <Library/CnviLib.h>
#include <Library/EcLib.h>
#include <Library/EcMiscLib.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Library/EcTcssLib.h>
#include <Register/ArchMsr.h>
#include <Register/AdlMsr.h>
#include <Library/ItbtPcieRpLib.h>
#include <Ppi/Spi.h>
#include <Register/MeRegs.h>
#include <Register/HeciRegs.h>
#include <Library/PciSegmentLib.h>
#include <Register/PchRegs.h>
#include <Register/PmcRegs.h>
#include <Register/TelemetryRegs.h>
#include <Library/TelemetryLib.h>
#include <Guid/CrashLog.h>
#include <AttemptUsbFirst.h>
#include <PlatformBoardId.h>
#include <Core/Pei/PeiMain.h>
#include <Library/PchPciBdfLib.h>
#include <Ppi/GraphicsPlatformPolicyPpi.h>
#include <Library/PeiGetFvInfoLib.h>
Include dependency graph for PlatformInitAdvancedPostMem.c:

Go to the source code of this file.

Functions

VOID | MtrrLibInitializeMtrrMask (OUT UINT64 *MtrrValidBitsMask, OUT UINT64 *MtrrValidAddressMask)
Initializes the valid bits mask and valid address mask for MTRRs. More...
UINT32 | MtrrLibGetRawVariableRanges (IN MTRR_VARIABLE_SETTINGS *VariableSettings, IN UINTN VariableMtrrCount, IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT MTRR_MEMORY_RANGE *VariableMtrr)
Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array. More...
RETURN_STATUS | MtrrLibApplyVariableMtrrs (IN CONST MTRR_MEMORY_RANGE *VariableMtrr, IN UINT32 VariableMtrrCount, IN OUT MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCapacity, IN OUT UINTN *RangeCount)
Apply the variable MTRR settings to memory range array. More...
EFI_STATUS | EOPSetMemoryAttributesInMtrrSettings (IN OUT MTRR_SETTINGS *MtrrSetting, IN MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount)
This function attempts to set the attributes into MTRR setting buffer. More...
EFI_STATUS | PlatformDebugStateChecksCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This callback function checks the debug state of the platform and sets the PcdFirmwareDebuggerInitialized value accordingly. More...
EFI_STATUS | PlatformInitAdvancedEndOfPei (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task at the end of PEI. More...
EFI_STATUS | PeiGraphicsPlatformInit (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function will pass data to Pei graphics PEIM. More...
EFI_STATUS | GetPeiPlatformLidStatus (OUT LID_STATUS *CurrentLidStatus)
This function will return Lid Status in PEI phase. More...
EFI_STATUS | SetCacheMtrrAfterEndOfPei (VOID)
Update MTRR setting in EndOfPei phase. More...
BOOLEAN | IsPremiumPmicPresent (VOID)
Checks if Premium PMIC present (VendorID == 1Fh) More...
VOID | PremiumPmicEnableSlpS0Voltage (VOID)
Pmic Programming to Enable Voltage Margining.
VOID | ConfigurePciHostBridgePcds (VOID)
Configure PciHostBridge related PCDs.
BOOLEAN | PlatformDebugStateChecks (VOID)
Returns whether the platform is in a debug state, by checking if any of the following conditions is true: More...
EFI_STATUS | CreateAttemptUsbFirstHotkeyInfoHob (VOID)
Create the HOB for hotkey status for 'Attempt USB First' feature. More...
UINT32 | GetPmcCrashLogDescriptTblAddr (IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get address of PMC crash log record from descriptor table. More...
UINT32 | GetPmcCrashLogAmount (IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get how many PMC crash log records. More...
UINT32 | GetPmcCrashLogRecord (IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer, IN UINT32 Offset)
Get offset and log size from PMC crash records. More...
BOOLEAN | GetPmcValidRecord (IN UINT32 PmcCrashLogAddr)
Consider the PMC crash log data is valid or invalid. More...
BOOLEAN | GetPmcCrashLogSupport (IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get PMC crash log supported or not. More...
BOOLEAN | GetCpuReArmSupport (IN CPU_CRASHLOG_HEADER *CrashlogHeader)
Get re-arm supported or not. More...
BOOLEAN | GetPmcReArmSupport (IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get re-arm supported or not. More...
VOID | CrashLogCollectDataFromPmcSSRAM (VOID)
Collect PCH CrashLog data from Pmc SSRAM and store in HOB .
VOID | CpuCrashLogCollectDataFromTelemetrySRAM (VOID)
Collect CPU CrashLog data from Telemetry SRAM and store in HOB .
VOID | ConfigureGpio (IN GPIO_INIT_CONFIG *GpioDefinition, IN UINT16 GpioTableCount)
Configures GPIO. More...
VOID | FoxvilleLanGpioInit (VOID)
Configure GPIO pads for Foxville I225 Lan based on the Setup Option.
VOID | TouchPanelGpioInit (VOID)
Configure GPIO pads for TouchPanels use.
VOID | CvfGpioInit (VOID)
Configure GPIO pads for CVF use.
VOID | GpioInitAdvanced (VOID)
Configure advanced GPIO.
EFI_STATUS | PlatformInitAdvancedPostMemEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init PEI module entry point. More...

Detailed Description

Source code file for Platform Init PEI module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedPostMem.c.

Function Documentation

◆ ConfigureGpio()

VOID ConfigureGpio | ( | IN GPIO_INIT_CONFIG * | GpioDefinition,
 |  | IN UINT16 | GpioTableCount
 | ) |  |

Configures GPIO.

Parameters
[in] | GpioTable | Point to Platform Gpio table
[in] | GpioTableCount | Number of Gpio table entries

Definition at line 1693 of file PlatformInitAdvancedPostMem.c.

◆ CreateAttemptUsbFirstHotkeyInfoHob()

EFI_STATUS CreateAttemptUsbFirstHotkeyInfoHob ( VOID )

Create the HOB for hotkey status for 'Attempt USB First' feature.

Return values
EFI_SUCCESS | HOB Creating successful.
Others | HOB Creating failed.

Build HOB for Attempt USB First feature

Definition at line 902 of file PlatformInitAdvancedPostMem.c.

◆ EOPSetMemoryAttributesInMtrrSettings()

EFI_STATUS EOPSetMemoryAttributesInMtrrSettings | ( | IN OUT MTRR_SETTINGS * | MtrrSetting,
 |  | IN MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount
 | ) |  |

This function attempts to set the attributes into MTRR setting buffer.

Parameters
[in,out] | MtrrSetting | - A buffer holding all MTRRs content.
[in] | Ranges | - Array holding memory type settings.
[in] | RangeCount | - Memory range count in the array.
Return values
Count of used variable Mtrrs

Definition at line 163 of file PlatformInitAdvancedPostMem.c.

◆ GetCpuReArmSupport()

BOOLEAN GetCpuReArmSupport ( IN CPU_CRASHLOG_HEADER * CrashlogHeader )

Get re-arm supported or not.

Parameters
[in] CrashlogHeader CPU Crashlog header structure
Return values
TRUE | PMC Re-arm command support
FALSE | PMC Re-arm command not support

Definition at line 1093 of file PlatformInitAdvancedPostMem.c.

◆ GetPeiPlatformLidStatus()

EFI_STATUS GetPeiPlatformLidStatus ( OUT LID_STATUS * CurrentLidStatus )

This function will return Lid Status in PEI phase.

Parameters
[out] CurrentLidStatus
Return values
EFI_SUCCESS
EFI_UNSUPPORTED

Definition at line 420 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcCrashLogAmount()

UINT32 GetPmcCrashLogAmount ( IN PMC_IPC_DISCOVERY_BUF * DiscoveryBuffer )

Get how many PMC crash log records.

Parameters
[in] DiscoveryBuffer PMC IPC discover buffer
Return values
UINT32 Amounts of PMC crash log.

Definition at line 954 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcCrashLogDescriptTblAddr()

UINT32 GetPmcCrashLogDescriptTblAddr ( IN PMC_IPC_DISCOVERY_BUF * DiscoveryBuffer )

Get address of PMC crash log record from descriptor table.

Parameters
[in] DiscoveryBuffer PMC IPC discover buffer
Return values
UINT32 An address of PMC crash log record.

Definition at line 939 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcCrashLogRecord()

UINT32 GetPmcCrashLogRecord | ( | IN PMC_IPC_DISCOVERY_BUF * | DiscoveryBuffer,
 |  | IN UINT32 | Offset
 | ) |  |

Get offset and log size from PMC crash records.

Parameters
[in] | DiscoveryBuffer | PMC IPC discover buffer
[in] | Offset | PMC records of region offset
Return values
UINT32 PMC crash record

Definition at line 980 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcCrashLogSupport()

BOOLEAN GetPmcCrashLogSupport ( IN PMC_IPC_DISCOVERY_BUF * DiscoveryBuffer )

Get PMC crash log supported or not.

Parameters
[in] DiscoveryBuffer PMC IPC discover buffer
Return values
TRUE | PMC crash log support
FALSE | PMC crash log not support

Definition at line 1057 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcReArmSupport()

BOOLEAN GetPmcReArmSupport ( IN PMC_IPC_DISCOVERY_BUF * DiscoveryBuffer )

Get re-arm supported or not.

Parameters
[in] DiscoveryBuffer PMC IPC discover buffer
Return values
TRUE | PMC Re-arm command support
FALSE | PMC Re-arm command not support

Definition at line 1148 of file PlatformInitAdvancedPostMem.c.

◆ GetPmcValidRecord()

BOOLEAN GetPmcValidRecord ( IN UINT32 PmcCrashLogAddr )

Consider the PMC crash log data is valid or invalid.

Parameters
[in] PmcCrashLogAddr Crash log data of memory address
Return values
TRUE | Data is valid
FALSE | Data is invalid

Definition at line 1029 of file PlatformInitAdvancedPostMem.c.

◆ IsPremiumPmicPresent()

BOOLEAN IsPremiumPmicPresent ( VOID )

Checks if Premium PMIC present (VendorID == 1Fh)

Return values
TRUE | if present
FALSE | it discrete/other PMIC

Definition at line 610 of file PlatformInitAdvancedPostMem.c.

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◆ MtrrLibApplyVariableMtrrs()

RETURN_STATUS MtrrLibApplyVariableMtrrs | ( | IN CONST MTRR_MEMORY_RANGE * | VariableMtrr,
 |  | IN UINT32 | VariableMtrrCount,
 |  | IN OUT MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCapacity,
 |  | IN OUT UINTN * | RangeCount
 | ) |  |

Apply the variable MTRR settings to memory range array.

Parameters
[in] | VariableMtrr | The variable MTRR array.
[in] | VariableMtrrCount | The count of variable MTRRs.
[in,out] | Ranges | Return the memory range array with new MTRR settings applied.
[in] | RangeCapacity | The capacity of memory range array.
[in,out] | RangeCount | Return the count of memory range.
Return values
RETURN_SUCCESS | The memory range array is returned successfully.
RETURN_OUT_OF_RESOURCES | The count of memory ranges exceeds capacity.

◆ MtrrLibGetRawVariableRanges()

UINT32 MtrrLibGetRawVariableRanges | ( | IN MTRR_VARIABLE_SETTINGS * | VariableSettings,
 |  | IN UINTN | VariableMtrrCount,
 |  | IN UINT64 | MtrrValidBitsMask,
 |  | IN UINT64 | MtrrValidAddressMask,
 |  | OUT MTRR_MEMORY_RANGE * | VariableMtrr
 | ) |  |

Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.

One MTRR_MEMORY_RANGE element is created for each MTRR setting. The routine doesn't remove the overlap or combine the near-by region.

Parameters
[in] | VariableSettings | The variable MTRR values to shadow
[in] | VariableMtrrCount | The number of variable MTRRs
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
Number of MTRRs which has been used.

◆ MtrrLibInitializeMtrrMask()

VOID MtrrLibInitializeMtrrMask | ( | OUT UINT64 * | MtrrValidBitsMask,
 |  | OUT UINT64 * | MtrrValidAddressMask
 | ) |  |

Initializes the valid bits mask and valid address mask for MTRRs.

This function initializes the valid bits mask and valid address mask for MTRRs.

Parameters
[out] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[out] | MtrrValidAddressMask | The valid address mask for the MTRR

◆ PeiGraphicsPlatformInit()

EFI_STATUS PeiGraphicsPlatformInit | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This function will pass data to Pei graphics PEIM.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Locate GfxPlatformPolicyPpi

Definition at line 378 of file PlatformInitAdvancedPostMem.c.

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◆ PlatformDebugStateChecks()

BOOLEAN PlatformDebugStateChecks ( VOID )

Returns whether the platform is in a debug state, by checking if any of the following conditions is true:

  • Using a sample part
  • Feature Control MSR lock is not set
  • Debug interface is enabled
  • SOC Configuration lock is not set (manufacturing mode)
Return values
TRUE | Platform is in a debug state.
FALSE | Platform is NOT in a debug state.

Definition at line 761 of file PlatformInitAdvancedPostMem.c.

◆ PlatformDebugStateChecksCallback()

EFI_STATUS PlatformDebugStateChecksCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This callback function checks the debug state of the platform and sets the PcdFirmwareDebuggerInitialized value accordingly.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Definition at line 831 of file PlatformInitAdvancedPostMem.c.

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◆ PlatformInitAdvancedEndOfPei()

EFI_STATUS PlatformInitAdvancedEndOfPei | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This function handles PlatformInit task at the end of PEI.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

Definition at line 863 of file PlatformInitAdvancedPostMem.c.

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◆ PlatformInitAdvancedPostMemEntryPoint()

EFI_STATUS PlatformInitAdvancedPostMemEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Platform Init PEI module entry point.

Parameters
[in] | FileHandle | Not used.
[in] | PeiServices | General purpose services available to every PEIM.
Return values
EFI_SUCCESS | The function completes successfully
EFI_OUT_OF_RESOURCES | Insufficient resources to create database

Definition at line 2234 of file PlatformInitAdvancedPostMem.c.

◆ SetCacheMtrrAfterEndOfPei()

EFI_STATUS SetCacheMtrrAfterEndOfPei ( VOID )

Update MTRR setting in EndOfPei phase.

Return values
EFI_SUCCESS | The function completes successfully.
Others | Some error occurs.

Definition at line 524 of file PlatformInitAdvancedPostMem.c.

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AlderLake Platform Sample Code: PlatformInitAdvancedPostMem.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei
PlatformInitAdvancedPostMem.c
Go to the documentation of this file.
1 /** @file
2 Source code file for Platform Init PEI module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include <Register/Msr.h>
36 #include <CpuRegs.h>
37 #include <SetupVariable.h>
38 #include <Library/IoLib.h>
39 #include <Library/HobLib.h>
40 #include <Library/DebugLib.h>
41 #include <Library/PchInfoLib.h>
42 #include <Library/BaseMemoryLib.h>
43 #include <Library/PeiServicesLib.h>
44 #include <Library/PmcLib.h>
45 #include <Library/GpioLib.h>
46 #include <Library/GpioNativeLib.h>
47 #include <Ppi/EndOfPeiPhase.h>
48 #include <Library/MtrrLib.h>
49 #include <Ppi/ReadOnlyVariable2.h>
50 #include <Guid/SmramMemoryReserve.h>
51 #include <Library/ConfigBlockLib.h>
52 #include <Ppi/SiPolicy.h>
53 #include <PchPolicyCommon.h>
54 #include <Library/SiPolicyLib.h>
55
56 #include <Guid/FirmwareFileSystem2.h>
57 #include <Protocol/FirmwareVolumeBlock.h>
58 #include <Guid/SystemNvDataGuid.h>
59
60 #include <Library/CnviLib.h>
61 #include <Library/EcLib.h>
62 #include <Library/EcMiscLib.h>
63 #include <Library/PostCodeLib.h>
64 #include <PlatformPostCode.h>
65 #include <Library/EcTcssLib.h>
66 #include <Register/ArchMsr.h>
67 #include <Register/AdlMsr.h>
68 #if FixedPcdGetBool(PcdITbtEnable) == 1
69 #include <TcssDataHob.h>
70 #endif
71 #include <Library/ItbtPcieRpLib.h>
72 #include <Ppi/Spi.h>
73 #include <Register/MeRegs.h>
74 #include <Register/HeciRegs.h>
75 #include <Library/MtrrLib.h>
76 #include <Library/PciSegmentLib.h>
77 #if FixedPcdGetBool (PcdDTbtEnable) == 1
78 #include <Ppi/PeiDTbtPolicy.h>
79 #include <Library/PeiTbtTaskDispatchLib.h>
80 #include <Private/Library/PeiDTbtInitLib.h>
81 #endif
82 #include <Register/PchRegs.h>
83 #include <Register/PmcRegs.h>
84 #include <Register/TelemetryRegs.h>
85 #include <Library/TelemetryLib.h>
86 #include <Guid/CrashLog.h>
87 #include <AttemptUsbFirst.h>
88 #include <PlatformBoardId.h>
89 #include <Core/Pei/PeiMain.h>
90 #include <Library/PchPciBdfLib.h>
91 #include <Ppi/GraphicsPlatformPolicyPpi.h>
92 #include <Library/PeiGetFvInfoLib.h>
93 /**
94 Initializes the valid bits mask and valid address mask for MTRRs.
95
96 This function initializes the valid bits mask and valid address mask for MTRRs.
97
98 @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR
99 @param[out] MtrrValidAddressMask The valid address mask for the MTRR
100
101 **/
102 VOID
103 MtrrLibInitializeMtrrMask (
104 OUT UINT64 *MtrrValidBitsMask,
105 OUT UINT64 *MtrrValidAddressMask
106 );
107
108 /**
109 Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
110 One MTRR_MEMORY_RANGE element is created for each MTRR setting.
111 The routine doesn't remove the overlap or combine the near-by region.
112
113 @param[in] VariableSettings The variable MTRR values to shadow
114 @param[in] VariableMtrrCount The number of variable MTRRs
115 @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
116 @param[in] MtrrValidAddressMask The valid address mask for MTRR
117 @param[out] VariableMtrr The array to shadow variable MTRRs content
118
119 @return Number of MTRRs which has been used.
120
121 **/
122 UINT32
123 MtrrLibGetRawVariableRanges (
124 IN MTRR_VARIABLE_SETTINGS *VariableSettings,
125 IN UINTN VariableMtrrCount,
126 IN UINT64 MtrrValidBitsMask,
127 IN UINT64 MtrrValidAddressMask,
128 OUT MTRR_MEMORY_RANGE *VariableMtrr
129 );
130
131 /**
132 Apply the variable MTRR settings to memory range array.
133
134 @param[in] VariableMtrr The variable MTRR array.
135 @param[in] VariableMtrrCount The count of variable MTRRs.
136 @param[in, out] Ranges Return the memory range array with new MTRR settings applied.
137 @param[in] RangeCapacity The capacity of memory range array.
138 @param[in, out] RangeCount Return the count of memory range.
139
140 @retval RETURN_SUCCESS The memory range array is returned successfully.
141 @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
142 **/
143 RETURN_STATUS
144 MtrrLibApplyVariableMtrrs (
145 IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
146 IN UINT32 VariableMtrrCount,
147 IN OUT MTRR_MEMORY_RANGE *Ranges,
148 IN UINTN RangeCapacity,
149 IN OUT UINTN *RangeCount
150 );
151
152 /**
153 This function attempts to set the attributes into MTRR setting buffer.
154
155 @param[in, out] MtrrSetting - A buffer holding all MTRRs content.
156 @param[in] Ranges - Array holding memory type settings.
157 @param[in] RangeCount - Memory range count in the array.
158
159 @retval Count of used variable Mtrrs
160 **/
161 EFI_STATUS
162 EFIAPI
163 EOPSetMemoryAttributesInMtrrSettings (
164 IN OUT MTRR_SETTINGS *MtrrSetting,
165 IN MTRR_MEMORY_RANGE *Ranges,
166 IN UINTN RangeCount
167 )
168 {
169 EFI_STATUS Status;
170 UINTN Index;
171 UINTN HighIndex;
172 UINT64 TopHighMemory;
173
174 Status = EFI_NOT_FOUND;
175
176 for (Index = 0, HighIndex = 0xFF; Index < RangeCount; Index++) {
177 //
178 // Set Mtrr variables from 1M.
179 //
180 if (Ranges[Index].BaseAddress < 0x100000) {
181 Ranges[Index].Length -= 0x100000;
182 Ranges[Index].BaseAddress = 0x100000;
183 }
184 if ((Ranges[Index].BaseAddress >= SIZE_4GB) && (Ranges[Index].Type == CacheWriteBack)) {
185 HighIndex = Index; // Set above 4G attributes at the latest step.
186 } else {
187 Status = MtrrSetMemoryAttributeInMtrrSettings (
188 MtrrSetting,
189 Ranges[Index].BaseAddress,
190 Ranges[Index].Length,
191 Ranges[Index].Type
192 );
193 ASSERT_EFI_ERROR (Status);
194 }
195 }
196 if (HighIndex != 0xFF) {
197 TopHighMemory = Ranges[HighIndex].BaseAddress + Ranges[HighIndex].Length;
198 //
199 // Try to cover memory as mmuch as we can.
200 // In later phase boot loader code can re-configure MTRR to exclude flash region and get back above 4GB coverage.
201 //
202 do {
203 Status = MtrrSetMemoryAttributeInMtrrSettings (
204 MtrrSetting,
205 SIZE_4GB,
206 TopHighMemory - SIZE_4GB,
207 CacheWriteBack
208 );
209 if (TopHighMemory > SIZE_4GB) {
210 TopHighMemory = RShiftU64 (TopHighMemory, 1);
211 }
212 } while ((EFI_SUCCESS != Status) && (TopHighMemory > SIZE_4GB));
213 }
214
215 return Status;
216 }
217
218
219 EFI_STATUS
220 EFIAPI
221 PlatformDebugStateChecksCallback (
222 IN CONST EFI_PEI_SERVICES **PeiServices,
223 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
224 IN VOID *Ppi
225 );
226
227 #if FixedPcdGetBool(PcdFspModeSelection) == 1
228 static EFI_PEI_NOTIFY_DESCRIPTOR mPlatformDebugStateChecksNotifyList = {
229 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
230 &gFspSiliconInitDonePpiGuid,
231 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformDebugStateChecksCallback
232 };
233 #else
234 static EFI_PEI_NOTIFY_DESCRIPTOR mPlatformDebugStateChecksNotifyList = {
235 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
236 &gEfiEndOfPeiSignalPpiGuid,
237 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformDebugStateChecksCallback
238 };
239 #endif
240
241 EFI_STATUS
242 EFIAPI
243 PlatformInitAdvancedEndOfPei (
244 IN CONST EFI_PEI_SERVICES **PeiServices,
245 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
246 IN VOID *Ppi
247 );
248
249 static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
250 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
251 &gEfiEndOfPeiSignalPpiGuid,
252 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitAdvancedEndOfPei
253 };
254
255 #if FixedPcdGetBool(PcdAdlLpSupport) == 1
256 EFI_STATUS
257 EFIAPI
258 GetPeiPlatformLidStatus (
259 OUT LID_STATUS *CurrentLidStatus
260 );
261
262 EFI_STATUS
263 EFIAPI
264 GetVbtData (
265 OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
266 OUT UINT32 *VbtSize
267 );
268
269 PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
270 PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
271 GetPeiPlatformLidStatus,
272 GetVbtData
273 };
274
275 EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
276 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
277 &gPeiGraphicsPlatformPpiGuid,
278 &PeiGraphicsPlatform
279 };
280
281 EFI_STATUS
282 EFIAPI
283 GetVbtData (
284 OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
285 OUT UINT32 *VbtSize
286 )
287 {
288 EFI_STATUS Status;
289 EFI_STATUS Status1;
290 SA_SETUP SaSetup;
291 UINTN VarSize;
292 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
293 EFI_GUID FileGuid;
294 EFI_GUID BmpImageGuid;
295 VOID *Buffer;
296 UINT32 Size;
297
298 Size = 0;
299 Buffer = NULL;
300 VarSize = sizeof (SA_SETUP);
301
302 //
303 // Locate system configuration variable
304 //
305 Status1 = PeiServicesLocatePpi (
306 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
307 0, // INSTANCE
308 NULL, // EFI_PEI_PPI_DESCRIPTOR
309 (VOID **) &VariableServices // PPI
310 );
311 ASSERT_EFI_ERROR (Status1);
312 Status = VariableServices->GetVariable(
313 VariableServices,
314 L"SaSetup",
315 &gSaSetupVariableGuid,
316 NULL,
317 &VarSize,
318 &SaSetup
319 );
320 ASSERT_EFI_ERROR(Status);
321
322 DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
323
324 if (SaSetup.VbtSelect == VBT_SELECT_MIPI) {
325 CopyMem (&BmpImageGuid, PcdGetPtr(PcdVbtMipiGuid), sizeof(BmpImageGuid));
326 } else {
327 CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
328 }
329
330 CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
331 PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
332 if (Buffer == NULL) {
333 DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
334 } else {
335 DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
336 DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
337 *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
338 *VbtSize = Size;
339 }
340 DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
341
342 return EFI_SUCCESS;
343 }
344 #else
345 EFI_STATUS
346 EFIAPI
347 PeiGraphicsPlatformInit (
348 IN CONST EFI_PEI_SERVICES **PeiServices,
349 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
350 IN VOID *Ppi
351 );
352
353 EFI_STATUS
354 EFIAPI
355 GetPeiPlatformLidStatus (
356 OUT LID_STATUS *CurrentLidStatus
357 );
358
359 static EFI_PEI_NOTIFY_DESCRIPTOR mPeiGraphicsPlatformNotifyList = {
360 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
361 &gPeiGraphicsPlatformPpiGuid,
362 (EFI_PEIM_NOTIFY_ENTRY_POINT) PeiGraphicsPlatformInit
363 };
364
365 /**
366 This function will pass data to Pei graphics PEIM.
367
368 @param[in] PeiServices Pointer to PEI Services Table.
369 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
370 caused this function to execute.
371 @param[in] Ppi Pointer to the PPI data associated with this function.
372
373 @retval EFI_SUCCESS The function completes successfully
374 @retval others
375 **/
376 EFI_STATUS
377 EFIAPI
378 PeiGraphicsPlatformInit (
379 IN CONST EFI_PEI_SERVICES **PeiServices,
380 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
381 IN VOID *Ppi
382 )
383 {
384 EFI_STATUS Status;
385 PEI_GRAPHICS_PLATFORM_POLICY_PPI *GfxPlatformPolicyPpi;
386
387 DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformInit: Begin \n"));
388
389 Status = EFI_SUCCESS;
390 ///
391 /// Locate GfxPlatformPolicyPpi
392 ///
393 Status = PeiServicesLocatePpi (&gPeiGraphicsPlatformPpiGuid, 0, NULL, (VOID *) &GfxPlatformPolicyPpi);
394 if (EFI_ERROR (Status)) {
395 DEBUG ((DEBUG_WARN, "Failed to locate Ppi GfxPlatformPolicyPpi.\n"));
396 return Status;
397 }
398
399 GfxPlatformPolicyPpi->Revision = PEI_GRAPHICS_PLATFORM_POLICY_REVISION;
400 GfxPlatformPolicyPpi->GetPlatformLidStatus = (GET_PLATFORM_LID_STATUS) GetPeiPlatformLidStatus;
401
402 DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformInit: End \n"));
403
404 return Status;
405 }
406
407 #endif
408
409 /**
410 This function will return Lid Status in PEI phase.
411
412 @param[out] CurrentLidStatus
413
414 @retval EFI_SUCCESS
415 @retval EFI_UNSUPPORTED
416 **/
417
418 EFI_STATUS
419 EFIAPI
420 GetPeiPlatformLidStatus (
421 OUT LID_STATUS *CurrentLidStatus
422 )
423 {
424 EFI_STATUS Status;
425 UINT8 PortDataOut;
426 UINT8 DataBuffer[1];
427
428 DEBUG ((DEBUG_INFO, "LidStatus Entry\n"));
429 //
430 // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
431 //
432 if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
433 DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
434 return EFI_UNSUPPORTED;
435 }
436 if (PcdGetBool (PcdEcPresent)) {
437 DataBuffer[0] = EC_D_LID_STATE;
438 Status = ReadEcRam (DataBuffer);
439 if (Status == EFI_SUCCESS) {
440 PortDataOut = DataBuffer[0];
441 if ((PortDataOut & EC_B_LID_STATUS_OPEN) == EC_B_LID_STATUS_OPEN) {
442 *CurrentLidStatus = LidOpen;
443 } else {
444 *CurrentLidStatus = LidClosed;
445 }
446 DEBUG ((DEBUG_INFO, "LidStatus Exit\n"));
447 return EFI_SUCCESS;
448 }
449 }
450
451 DEBUG ((DEBUG_INFO, "LidStatus UnSupported\n"));
452 return EFI_UNSUPPORTED;
453 }
454
455 #if FixedPcdGetBool (PcdDTbtEnable) == 1
456 /**
457 This function handles TbtInit task at the end of PEI
458
459 @param[in] PeiServices Pointer to PEI Services Table.
460 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
461 caused this function to execute.
462 @param[in] Ppi Pointer to the PPI data associated with this function.
463
464 @retval EFI_SUCCESS The function completes successfully
465 @retval RETURN_UNSUPPORTED DTBT is not supported
466 **/
467 EFI_STATUS
468 EFIAPI
469 DTbtInitEndOfPei (
470 VOID
471 )
472 {
473 EFI_STATUS Status;
474 UINT8 Index;
475 BOOLEAN DTbtExisted;
476 PEI_DTBT_POLICY *PeiDTbtConfig;
477
478 DEBUG ((DEBUG_INFO, "DTbtInitEndOfPei Entry\n"));
479
480 Status = EFI_SUCCESS;
481 PeiDTbtConfig = NULL;
482 Index = 0;
483 DTbtExisted = FALSE;
484
485 Status = PeiServicesLocatePpi (
486 &gPeiDTbtPolicyPpiGuid,
487 0,
488 NULL,
489 (VOID **) &PeiDTbtConfig
490 );
491 if (EFI_ERROR(Status)) {
492 DEBUG ((DEBUG_ERROR, " gPeiDTbtPolicyPpiGuid Not installed!!!\n"));
493 return RETURN_UNSUPPORTED;
494 }
495
496 if (PeiDTbtConfig != NULL) {
497 for (Index = 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) {
498 if (PeiDTbtConfig->DTbtControllerConfig[Index].DTbtControllerEn == 1) {
499 DTbtExisted = TRUE;
500 break;
501 }
502 }
503
504 if (DTbtExisted == TRUE) {
505 //
506 // Dispatch DTBT task table
507 //
508 TbtTaskDistpach (DTbtCallTable, (VOID *) PeiDTbtConfig);
509 }
510 }
511
512 return EFI_SUCCESS;
513 }
514 #endif
515
516 /**
517 Update MTRR setting in EndOfPei phase.
518
519 @retval EFI_SUCCESS The function completes successfully.
520 @retval Others Some error occurs.
521 **/
522 EFI_STATUS
523 EFIAPI
524 SetCacheMtrrAfterEndOfPei (
525 VOID
526 )
527 {
528 EFI_STATUS Status;
529 EFI_PEI_HOB_POINTERS Hob;
530 UINTN Index;
531 UINT64 SmramSize;
532 UINT64 SmramBase;
533 EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
534 MTRR_SETTINGS MtrrSetting;
535 UINTN RangeCount;
536 UINT32 VariableMtrrCount;
537 UINT64 MtrrValidBitsMask;
538 UINT64 MtrrValidAddressMask;
539 MTRR_MEMORY_RANGE RawVariableRanges[MTRR_NUMBER_OF_VARIABLE_MTRR];
540 MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR];
541 MTRR_SETTINGS UCMtrrSetting;
542 //
543 // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
544 // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
545 //
546 SmramSize = 0;
547 SmramBase = 0;
548 Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
549 while (!END_OF_HOB_LIST (Hob)) {
550 if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
551 if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
552 SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
553 for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
554 if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
555 SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
556 if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
557 SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
558 }
559 }
560 }
561 break;
562 }
563 }
564 Hob.Raw = GET_NEXT_HOB (Hob);
565 }
566
567 MtrrGetAllMtrrs (&MtrrSetting);
568 VariableMtrrCount = GetVariableMtrrCount ();
569 MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
570
571 Ranges[0].BaseAddress = 0;
572 Ranges[0].Length = MtrrValidBitsMask + 1;
573 Ranges[0].Type = (MTRR_MEMORY_CACHE_TYPE)(MtrrSetting.MtrrDefType & 0x07); //[Bits 2:0] Default Memory Type.
574 RangeCount = 1;
575
576 MtrrLibGetRawVariableRanges (
577 &MtrrSetting.Variables, VariableMtrrCount,
578 MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
579 );
580
581 MtrrLibApplyVariableMtrrs (
582 RawVariableRanges, VariableMtrrCount,
583 Ranges, ARRAY_SIZE (Ranges), &RangeCount
584 );
585
586 //
587 // Set SMRAM as CacheWriteBack for performance.
588 //
589 Ranges[RangeCount].BaseAddress = SmramBase;
590 Ranges[RangeCount].Length = SmramSize;
591 Ranges[RangeCount].Type = CacheWriteBack;
592 RangeCount++;
593
594 ZeroMem (&UCMtrrSetting, sizeof (MTRR_SETTINGS));
595 UCMtrrSetting.MtrrDefType = MtrrSetting.MtrrDefType;
596 Status = EOPSetMemoryAttributesInMtrrSettings (&UCMtrrSetting, Ranges, RangeCount);
597
598 CopyMem (&MtrrSetting.Variables, &UCMtrrSetting.Variables, sizeof (MTRR_VARIABLE_SETTINGS));
599 MtrrSetting.MtrrDefType = UCMtrrSetting.MtrrDefType;
600 return Status;
601 }
602
603 /**
604 Checks if Premium PMIC present (VendorID == 1Fh)
605
606 @retval TRUE if present
607 @retval FALSE it discrete/other PMIC
608 **/
609 BOOLEAN
610 IsPremiumPmicPresent (
611 VOID
612 )
613 {
614 UINT8 PmicVendorID;
615
616 PmicVendorID = 0;
617 //Send KSC Command to detect vendor ID of PMIC is present on the system(Applicable only for ULT/ULX Platforms)
618 DetectPmicVendorID (&PmicVendorID);
619 DEBUG((DEBUG_INFO, "Vendor ID of the Pmic Present on the system is: %x\n", PmicVendorID));
620
621 if (PmicVendorID == 0x1F) {
622 return TRUE;
623 }
624
625 return FALSE;
626 }
627
628 /**
629 Pmic Programming to Enable Voltage Margining
630 **/
631 VOID
632 PremiumPmicEnableSlpS0Voltage (
633 VOID
634 )
635 {
636 EFI_STATUS Status;
637 UINT8 EcDataV085ACNT;
638 UINT64 HdaPciBase;
639 BOOLEAN PremiumPmicPresent;
640
641 HdaPciBase = HdaPciCfgBase ();
642 PremiumPmicPresent = IsPremiumPmicPresent();
643 if ((PciSegmentRead16(HdaPciBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) && (PremiumPmicPresent == TRUE)) { // If HDA Device is not detected & Premium PMIC is present
644 DEBUG((DEBUG_INFO, "Enable VM in case Premium PMIC is Detected and HDA Disabled\n"));
645 EcDataV085ACNT = 0x7A; //Enable Voltage Margining in case HDA is disabled
646 Status = SetSlpS0Voltage(EcDataV085ACNT);
647 ASSERT_EFI_ERROR(Status);
648 }
649 }
650
651 /**
652 Configure PciHostBridge related PCDs
653 **/
654 VOID
655 ConfigurePciHostBridgePcds (
656 VOID
657 )
658 {
659 EFI_STATUS Status;
660 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
661 EFI_PHYSICAL_ADDRESS PciBaseAddress;
662 UINT32 Tolud;
663 UINT64 Length;
664 UINT64 McD0BaseAddress;
665 UINTN ResMemLimit1;
666 UINTN SaSetupSize;
667 SA_SETUP SaSetup;
668 #if FixedPcdGetBool(PcdITbtEnable) == 1
669 TCSS_DATA_HOB *TcssHob;
670
671 TcssHob = NULL;
672 #endif
673 Status = PeiServicesLocatePpi (
674 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
675 0, // INSTANCE
676 NULL, // EFI_PEI_PPI_DESCRIPTOR
677 (VOID **) &VariableServices // PPI
678 );
679 if (EFI_ERROR (Status)) {
680 DEBUG ((DEBUG_ERROR, "ConfigurePciHostBridgePcds: PeiServicesLocatePpi failed\n"));
681 return;
682 }
683 #if FixedPcdGetBool(PcdITbtEnable) == 1
684 //
685 // Get Tcss Data HOB
686 //
687 TcssHob = (TCSS_DATA_HOB *) GetFirstGuidHob (&gTcssHobGuid);
688 if (TcssHob != NULL) {
689 if (TcssHob->TcssData.PcieMultipleSegmentEnabled) {
690 PcdSet8S (PcdPciSegmentCount, 2);
691 }
692 }
693 #endif
694 //
695 // Allocate 56 KB of I/O space [0x2000..0xFFFF]
696 //
697 DEBUG ((DEBUG_INFO, " Assign IO resource for PCI_ROOT_BRIDGE from 0x%X to 0x%X\n", PcdGet16 (PcdPciReservedIobase) ,PcdGet16 (PcdPciReservedIoLimit)));
698
699 //
700 // Read memory map registers
701 //
702 McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
703 Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
704 PciBaseAddress = Tolud;
705
706 ResMemLimit1 = PcdGet32 (PcdPciReservedMemLimit);
707 if (ResMemLimit1 == 0) {
708 ResMemLimit1 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
709 }
710
711 Length = ResMemLimit1 - PciBaseAddress;
712
713 if (Length != 0) {
714 PcdSet32S (PcdPciReservedMemBase, (UINT32) PciBaseAddress);
715 PcdSet32S (PcdPciReservedMemLimit, (UINT32) (PciBaseAddress + Length - 1));
716 DEBUG ((DEBUG_INFO, " Assign Memory Resource for PCI_ROOT_BRIDGE from 0x%X", PcdGet32 (PcdPciReservedMemBase)));
717 DEBUG ((DEBUG_INFO, " to 0x%X\n", PcdGet32 (PcdPciReservedMemLimit)));
718 }
719
720 //
721 // Check Enable Above 4GB MMIO or not
722 //
723 SaSetupSize = sizeof (SA_SETUP);
724 Status = VariableServices->GetVariable (
725 VariableServices,
726 L"SaSetup",
727 &gSaSetupVariableGuid,
728 NULL,
729 &SaSetupSize,
730 &SaSetup
731 );
732 if (!EFI_ERROR(Status)) {
733 if (SaSetup.EnableAbove4GBMmio == 1 || SaSetup.ApertureSize == 15) {
734 //
735 // Provide 256GB available above 4GB MMIO resource
736 // limited to use single variable MTRR to cover this above 4GB MMIO region.
737 //
738 PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
739 PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);
740 if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
741 DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
742 DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
743 }
744 }
745 }
746 }
747
748 /**
749 Returns whether the platform is in a debug state, by checking if any of the
750 following conditions is true:
751
752 - Using a sample part
753 - Feature Control MSR lock is not set
754 - Debug interface is enabled
755 - SOC Configuration lock is not set (manufacturing mode)
756
757 @retval TRUE Platform is in a debug state.
758 @retval FALSE Platform is NOT in a debug state.
759 **/
760 BOOLEAN
761 PlatformDebugStateChecks (
762 VOID
763 )
764 {
765 ADL_MSR_PLATFORM_INFO_REGISTER PlatformInfoMsr;
766 MSR_IA32_FEATURE_CONTROL_REGISTER Ia32FeatureControlMsr;
767 MSR_IA32_DEBUG_INTERFACE_REGISTER DebugInterfaceMsr;
768 HECI_FW_STS6_REGISTER MeFirmwareStatus;
769
770 BOOLEAN DebugState = FALSE;
771
772 DEBUG ((DEBUG_INFO, "PlatformDebugStateChecks\n"));
773
774 //
775 // Check for sample part
776 //
777 PlatformInfoMsr.Uint64 = AsmReadMsr64 (ADL_MSR_PLATFORM_INFO);
778 DEBUG ((DEBUG_INFO, " PlatformInfoMsr = 0x%x\n", PlatformInfoMsr.Uint64));
779 if (PlatformInfoMsr.Bits.SamplePart) {
780 DEBUG ((DEBUG_WARN, " Sample part detected!\n"));
781 DebugState = TRUE;
782 }
783
784 //
785 // Check for MSR Feature Control lock
786 //
787 Ia32FeatureControlMsr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
788 DEBUG ((DEBUG_INFO, " Ia32FeatureControlMsr.Uint64 = 0x%x\n", Ia32FeatureControlMsr.Uint64));
789 if (Ia32FeatureControlMsr.Bits.Lock == 0) {
790 DEBUG ((DEBUG_WARN, " MSR Feature Control MSR lock is not set!\n"));
791 DebugState = TRUE;
792 }
793
794 //
795 // Check for Debug interface
796 //
797 DebugInterfaceMsr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
798 DEBUG ((DEBUG_INFO, " DebugInterfaceMsr.Uint64 = 0x%x\n", DebugInterfaceMsr.Uint64));
799 if (DebugInterfaceMsr.Bits.Enable) {
800 DEBUG ((DEBUG_WARN, " Debug interface is enabled!\n"));
801 DebugState = TRUE;
802 }
803
804 //
805 // Check for Manufacturing Mode
806 //
807 MeFirmwareStatus.ul = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (ME_SEGMENT, ME_BUS, ME_DEVICE_NUMBER, HECI_FUNCTION_NUMBER, R_ME_HFS_6));
808 DEBUG ((DEBUG_INFO, " MeFirmwareStatus.ul = 0x%x\n", MeFirmwareStatus.ul));
809 if (MeFirmwareStatus.r.FpfSocConfigLock == 0) {
810 DEBUG ((DEBUG_WARN, " SOC Configuration Lock is not set!\n"));
811 DebugState = TRUE;
812 }
813
814 return DebugState;
815 }
816
817 /**
818 This callback function checks the debug state of the platform and
819 sets the PcdFirmwareDebuggerInitialized value accordingly.
820
821 @param[in] PeiServices Pointer to PEI Services Table.
822 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
823 caused this function to execute.
824 @param[in] Ppi Pointer to the PPI data associated with this function.
825
826 @retval EFI_SUCCESS The function completes successfully
827 @retval others
828 **/
829 EFI_STATUS
830 EFIAPI
831 PlatformDebugStateChecksCallback (
832 IN CONST EFI_PEI_SERVICES **PeiServices,
833 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
834 IN VOID *Ppi
835 )
836 {
837 //
838 // Check Platform debug state
839 //
840 if (PlatformDebugStateChecks () == TRUE) {
841 //
842 // Extend platform state into TPM PCR[7]
843 //
844 PcdSetBoolS (PcdFirmwareDebuggerInitialized, TRUE);
845 }
846 DEBUG ((DEBUG_INFO, "PcdFirmwareDebuggerInitialized = %x\n", PcdGetBool (PcdFirmwareDebuggerInitialized)));
847 return EFI_SUCCESS;
848 }
849
850 /**
851 This function handles PlatformInit task at the end of PEI
852
853 @param[in] PeiServices Pointer to PEI Services Table.
854 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
855 caused this function to execute.
856 @param[in] Ppi Pointer to the PPI data associated with this function.
857
858 @retval EFI_SUCCESS The function completes successfully
859 @retval others
860 **/
861 EFI_STATUS
862 EFIAPI
863 PlatformInitAdvancedEndOfPei (
864 IN CONST EFI_PEI_SERVICES **PeiServices,
865 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
866 IN VOID *Ppi
867 )
868 {
869 EFI_STATUS Status;
870
871 Status = SetCacheMtrrAfterEndOfPei ();
872 ASSERT_EFI_ERROR (Status);
873
874 //
875 // Function to enable VM in case HD Audio is Disabled
876 //
877 PremiumPmicEnableSlpS0Voltage ();
878
879 #if FixedPcdGetBool (PcdDTbtEnable) == 1
880 //
881 // Perform DTBT init
882 //
883 Status = DTbtInitEndOfPei ();
884 #endif
885
886 //
887 // Configure PciHostBridge related PCDs before DXE phase
888 //
889 ConfigurePciHostBridgePcds ();
890
891 return Status;
892 }
893
894 //@todo Review this functionality and if it is required for SKL SDS
895 /**
896 Create the HOB for hotkey status for 'Attempt USB First' feature
897
898 @retval EFI_SUCCESS HOB Creating successful.
899 @retval Others HOB Creating failed.
900 **/
901 EFI_STATUS
902 CreateAttemptUsbFirstHotkeyInfoHob (
903 VOID
904 )
905 {
906 EFI_STATUS Status;
907 ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
908
909 Status = EFI_SUCCESS;
910
911 ZeroMem (
912 &AttemptUsbFirstHotkeyInfo,
913 sizeof (AttemptUsbFirstHotkeyInfo)
914 );
915
916 AttemptUsbFirstHotkeyInfo.RevisonId = 0;
917 AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
918
919 ///
920 /// Build HOB for Attempt USB First feature
921 ///
922 BuildGuidDataHob (
923 &gAttemptUsbFirstHotkeyInfoHobGuid,
924 &(AttemptUsbFirstHotkeyInfo),
925 sizeof (ATTEMPT_USB_FIRST_HOTKEY_INFO)
926 );
927
928 return Status;
929 }
930
931 /**
932 Get address of PMC crash log record from descriptor table
933
934 @param[in] DiscoveryBuffer PMC IPC discover buffer
935
936 @retval UINT32 An address of PMC crash log record.
937 **/
938 UINT32
939 GetPmcCrashLogDescriptTblAddr (
940 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
941 )
942 {
943 return PcdGet32 (PcdSiliconInitTempMemBaseAddr) + DiscoveryBuffer->Bits64.DesTableOffset;
944 }
945
946 /**
947 Get how many PMC crash log records.
948
949 @param[in] DiscoveryBuffer PMC IPC discover buffer
950
951 @retval UINT32 Amounts of PMC crash log.
952 **/
953 UINT32
954 GetPmcCrashLogAmount (
955 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
956 )
957 {
958 UINT32 NumberOfRegionsAddress;
959
960 switch (DiscoveryBuffer->Bits64.Mech) {
961 case CRASHLOG_MECH_LEGACY:
962 return 1;
963 case CRASHLOG_MECH_DESCRIPTOR_TABLE:
964 NumberOfRegionsAddress = GetPmcCrashLogDescriptTblAddr (DiscoveryBuffer);
965 return MmioRead32 (NumberOfRegionsAddress);
966 default:
967 return 0;
968 }
969 }
970
971 /**
972 Get offset and log size from PMC crash records.
973
974 @param[in] DiscoveryBuffer PMC IPC discover buffer
975 @param[in] Offset PMC records of region offset
976
977 @retval UINT32 PMC crash record
978 **/
979 UINT32
980 GetPmcCrashLogRecord (
981 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer,
982 IN UINT32 Offset
983 )
984 {
985 PMC_CRASHLOG_RECORDS Record;
986 UINT32 PmcCrashRecordAddr;
987
988 switch (DiscoveryBuffer->Bits64.Mech) {
989 case CRASHLOG_MECH_LEGACY:
990 //
991 // Legacy Mechanism uses Baseoffset as PmcCrashLogAddr.
992 // The BaseOffset is returned from PMC discovery buffer.
993 //
994 Record.Info.Offset = DiscoveryBuffer->Bits.BaseOffset;
995 Record.Info.Size = (DiscoveryBuffer->Bits.Size != 0) ? DiscoveryBuffer->Bits.Size : 0x300;
996 break;
997 case CRASHLOG_MECH_DESCRIPTOR_TABLE:
998 // Descritpor Table Mechanism
999 //---------------------------------
1000 // Number of records | 4 bytes
1001 // 1 record offset | 2 bytes
1002 // 1 record size | 2 bytes
1003 // 2 record offset | 2 bytes
1004 // 2 record size | 2 bytes
1005 //---------------------------------
1006 PmcCrashRecordAddr = GetPmcCrashLogDescriptTblAddr (DiscoveryBuffer) + (4 * Offset);
1007 Record.Uint32 = MmioRead32 (PmcCrashRecordAddr);
1008 break;
1009 default:
1010 return 0;
1011 }
1012
1013 //
1014 // PMC crash log size is number of DWORDs.
1015 //
1016 Record.Info.Size *= sizeof (UINT32);
1017 return Record.Uint32;
1018 }
1019
1020 /**
1021 Consider the PMC crash log data is valid or invalid.
1022
1023 @param[in] PmcCrashLogAddr Crash log data of memory address
1024
1025 @retval TRUE Data is valid
1026 @retval FALSE Data is invalid
1027 **/
1028 BOOLEAN
1029 GetPmcValidRecord (
1030 IN UINT32 PmcCrashLogAddr
1031 )
1032 {
1033 CRASHLOG_VERSION *PmcCrashLogVersion;
1034
1035 PmcCrashLogVersion = (CRASHLOG_VERSION *) PmcCrashLogAddr;
1036
1037 if (PmcCrashLogVersion->Uint32 == 0) {
1038 return FALSE;
1039 }
1040
1041 if (PmcCrashLogVersion->Bits.Consumed == 1) {
1042 return FALSE;
1043 }
1044
1045 return TRUE;
1046 }
1047
1048 /**
1049 Get PMC crash log supported or not.
1050
1051 @param[in] DiscoveryBuffer PMC IPC discover buffer
1052
1053 @retval TRUE PMC crash log support
1054 @retval FALSE PMC crash log not support
1055 **/
1056 BOOLEAN
1057 GetPmcCrashLogSupport (
1058 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
1059 )
1060 {
1061
1062 if (DiscoveryBuffer->Bits.Avail != 1) {
1063 return FALSE;
1064 }
1065
1066 switch (DiscoveryBuffer->Bits64.Mech) {
1067 case CRASHLOG_MECH_LEGACY:
1068 if (DiscoveryBuffer->Bits.Dis == 1) {
1069 return FALSE;
1070 }
1071 break;
1072 case CRASHLOG_MECH_DESCRIPTOR_TABLE:
1073 if (DiscoveryBuffer->Bits64.CrashDisSts) {
1074 return FALSE;
1075 }
1076 break;
1077 default:
1078 return FALSE;
1079 }
1080
1081 return TRUE;
1082 }
1083
1084 /**
1085 Get re-arm supported or not.
1086
1087 @param[in] CrashlogHeader CPU Crashlog header structure
1088
1089 @retval TRUE PMC Re-arm command support
1090 @retval FALSE PMC Re-arm command not support
1091 **/
1092 BOOLEAN
1093 GetCpuReArmSupport (
1094 IN CPU_CRASHLOG_HEADER *CrashlogHeader
1095 )
1096 {
1097 EFI_STATUS Status;
1098 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1099 SETUP_DATA SetupData;
1100 UINTN VariableSize;
1101
1102 if (CrashlogHeader == NULL) {
1103 return FALSE;
1104 }
1105
1106 if (CrashlogHeader->CrashlogCapability.Fields.ReArmSupported == 0) {
1107 return FALSE;
1108 }
1109
1110 Status = PeiServicesLocatePpi (
1111 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
1112 0, // INSTANCE
1113 NULL, // EFI_PEI_PPI_DESCRIPTOR
1114 (VOID **) &VariableServices // PPI
1115 );
1116 ASSERT_EFI_ERROR (Status);
1117 if (EFI_ERROR (Status)) {
1118 DEBUG ((DEBUG_ERROR, "%a: Failed to locate gEfiPeiReadOnlyVariable2Ppi.\n", __FUNCTION__));
1119 return FALSE;
1120 }
1121
1122 VariableSize = sizeof (SETUP_DATA);
1123 Status = VariableServices->GetVariable (
1124 VariableServices,
1125 PLATFORM_SETUP_VARIABLE_NAME,
1126 &gSetupVariableGuid,
1127 NULL,
1128 &VariableSize,
1129 &SetupData
1130 );
1131 if (EFI_ERROR (Status)) {
1132 DEBUG ((DEBUG_ERROR, "%a: Failed to GetVariable (%r).\n", __FUNCTION__, Status));
1133 return FALSE;
1134 }
1135
1136 return (BOOLEAN)(SetupData.CrashLogRearmEnable);
1137 }
1138
1139 /**
1140 Get re-arm supported or not.
1141
1142 @param[in] DiscoveryBuffer PMC IPC discover buffer
1143
1144 @retval TRUE PMC Re-arm command support
1145 @retval FALSE PMC Re-arm command not support
1146 **/
1147 BOOLEAN
1148 GetPmcReArmSupport (
1149 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
1150 )
1151 {
1152 EFI_STATUS Status;
1153 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1154 SETUP_DATA SetupData;
1155 UINTN VariableSize;
1156
1157 if (DiscoveryBuffer == NULL) {
1158 return FALSE;
1159 }
1160
1161 if (DiscoveryBuffer->Bits64.Mech == CRASHLOG_MECH_DESCRIPTOR_TABLE) {
1162 if (DiscoveryBuffer->Bits64.ReArm == 0) {
1163 return FALSE;
1164 }
1165 } else {
1166 return FALSE;
1167 }
1168
1169 Status = PeiServicesLocatePpi (
1170 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
1171 0, // INSTANCE
1172 NULL, // EFI_PEI_PPI_DESCRIPTOR
1173 (VOID **) &VariableServices // PPI
1174 );
1175 ASSERT_EFI_ERROR (Status);
1176 if (EFI_ERROR (Status)) {
1177 DEBUG ((DEBUG_ERROR, "%a: Failed to locate gEfiPeiReadOnlyVariable2Ppi.\n", __FUNCTION__));
1178 return FALSE;
1179 }
1180
1181 VariableSize = sizeof (SETUP_DATA);
1182 Status = VariableServices->GetVariable (
1183 VariableServices,
1184 PLATFORM_SETUP_VARIABLE_NAME,
1185 &gSetupVariableGuid,
1186 NULL,
1187 &VariableSize,
1188 &SetupData
1189 );
1190 if (EFI_ERROR (Status)) {
1191 DEBUG ((DEBUG_ERROR, "%a: Failed to GetVariable (%r).\n", __FUNCTION__, Status));
1192 return FALSE;
1193 }
1194
1195 return (BOOLEAN)(SetupData.CrashLogRearmEnable);
1196 }
1197
1198 /*
1199 Get pmc crash log clear enable or not.
1200
1201 @param[in] DiscoveryBuffer PMC IPC discover buffer
1202
1203 @retval TRUE PMC crash log clear
1204 @retval FALSE PMC crash log do not clear
1205 */
1206 BOOLEAN
1207 GetPmcClearSupport (
1208 IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
1209 )
1210 {
1211 EFI_STATUS Status;
1212 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1213 SETUP_DATA SetupData;
1214 UINTN VariableSize;
1215
1216 if (DiscoveryBuffer->Bits64.Mech == CRASHLOG_MECH_DESCRIPTOR_TABLE) {
1217 if (DiscoveryBuffer->Bits64.Clr == 0) {
1218 return FALSE;
1219 }
1220 }
1221
1222 Status = PeiServicesLocatePpi (
1223 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
1224 0, // INSTANCE
1225 NULL, // EFI_PEI_PPI_DESCRIPTOR
1226 (VOID **) &VariableServices // PPI
1227 );
1228 ASSERT_EFI_ERROR (Status);
1229
1230 VariableSize = sizeof (SETUP_DATA);
1231 Status = VariableServices->GetVariable (
1232 VariableServices,
1233 PLATFORM_SETUP_VARIABLE_NAME,
1234 &gSetupVariableGuid,
1235 NULL,
1236 &VariableSize,
1237 &SetupData
1238 );
1239
1240 return (BOOLEAN)(SetupData.CrashLogClearEnable);
1241 }
1242
1243 /**
1244 Collect PCH CrashLog data from Pmc SSRAM and store in HOB .
1245
1246 **/
1247 VOID
1248 CrashLogCollectDataFromPmcSSRAM (
1249 VOID
1250 )
1251 {
1252 EFI_STATUS Status;
1253 PMC_IPC_DISCOVERY_BUF DiscoveryBuffer;
1254 UINT64 PmcSsramBaseAddress;
1255 UINT32 PmcSsramBar0;
1256 PMC_CRASHLOG_LINK *PmcCrashLog;
1257 PMC_CRASHLOG_LINK *PmcCrashLogList;
1258 PMC_CRASHLOG_LINK *TempPmcCrashLog;
1259 CRASHLOG_HOB *PmcCrashLogHob;
1260 UINT32 Index;
1261 UINT32 NumberOfRegions = 0;
1262 UINT32 ValidRecords;
1263 UINT32 PmcCrashLogAddr;
1264 UINT32 *Destination = NULL;
1265 UINT32 CopiedSize = 0;
1266
1267 DEBUG ((DEBUG_INFO, "CrashLogCollectDataFromPmcSSRAM - start\n"));
1268
1269 //
1270 // Check for the availability of CrashLog feature
1271 //
1272 ZeroMem (&DiscoveryBuffer, sizeof (PMC_IPC_DISCOVERY_BUF));
1273
1274 Status = PmcCrashLogDiscovery (&DiscoveryBuffer);
1275
1276 if (EFI_ERROR (Status) || (GetPmcCrashLogSupport (&DiscoveryBuffer) == FALSE)) {
1277 DEBUG ((DEBUG_INFO, "PCH CrashLog feature is not supported\n"));
1278 return;
1279 }
1280
1281 //
1282 // Start to access PMC SSRAM MMIO
1283 //
1284 PmcSsramBaseAddress = PmcSsramPciCfgBase ();
1285
1286 if (PciSegmentRead16 (PmcSsramBaseAddress + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
1287 DEBUG ((DEBUG_ERROR, "PMC SSRAM PCI device is disabled\n"));
1288 return;
1289 }
1290
1291 //
1292 // Program BAR 0 and enable command register memory space decoding
1293 //
1294 PmcSsramBar0 = PcdGet32 (PcdSiliconInitTempMemBaseAddr);
1295 PciSegmentWrite32 (PmcSsramBaseAddress + PCI_BASE_ADDRESSREG_OFFSET, PmcSsramBar0);
1296 PciSegmentOr16 (PmcSsramBaseAddress + PCI_COMMAND_OFFSET, (UINT16) (EFI_PCI_COMMAND_MEMORY_SPACE));
1297
1298 NumberOfRegions = GetPmcCrashLogAmount (&DiscoveryBuffer);
1299 PmcCrashLogList = NULL;
1300
1301 for (Index = 1, ValidRecords = 0; Index <= NumberOfRegions; Index++) {
1302 PmcCrashLog = AllocateZeroPool (sizeof (PMC_CRASHLOG_LINK));
1303 if (PmcCrashLog == NULL) {
1304 DEBUG((DEBUG_ERROR, "CrashLogCollectDataFromPmcSSRAM : buffer allocation failure\n"));
1305 Status = RETURN_OUT_OF_RESOURCES;
1306 ASSERT_EFI_ERROR(Status);
1307 return;
1308 }
1309 PmcCrashLog->Record.Uint32 = GetPmcCrashLogRecord (&DiscoveryBuffer, Index);
1310 DEBUG ((DEBUG_INFO, "%d.Crashlog record = 0x%08x\n", Index, PmcCrashLog->Record.Uint32));
1311
1312 //
1313 // Check all records' data are valid or invalid, if not, skip the record.
1314 //
1315 PmcCrashLogAddr = PmcSsramBar0 + PmcCrashLog->Record.Info.Offset;
1316 DEBUG ((DEBUG_INFO, "%d.MmioRead32 (0x%08x) = 0x%08x\n", Index, PmcCrashLogAddr, MmioRead32 (PmcCrashLogAddr)));
1317 if (GetPmcValidRecord (PmcCrashLogAddr) == FALSE) {
1318 //
1319 // Invalid record. Skip this record and check the next.
1320 //
1321 FreePool (PmcCrashLog);
1322 continue;
1323 }
1324
1325 //
1326 // Valid record, prepare memory space for this address of record.
1327 //
1328 Status = PeiServicesAllocatePages (
1329 EfiBootServicesData,
1330 EFI_SIZE_TO_PAGES (PmcCrashLog->Record.Info.Size),
1331 &(PmcCrashLog->AllocateAddress)
1332 );
1333
1334 if (EFI_ERROR (Status)) {
1335 DEBUG ((DEBUG_ERROR, "Memory out of resource\n"));
1336 goto Exit;
1337 }
1338
1339 ValidRecords++;
1340 PmcCrashLog->Next = NULL;
1341 TempPmcCrashLog = PmcCrashLogList;
1342
1343 //
1344 // Link every valid records to PmcCrashLogList
1345 //
1346 if (PmcCrashLogList == NULL) {
1347 PmcCrashLogList = PmcCrashLog;
1348 } else {
1349 while (TempPmcCrashLog->Next != NULL) {
1350 TempPmcCrashLog = TempPmcCrashLog->Next;
1351 }
1352 TempPmcCrashLog->Next = PmcCrashLog;
1353 }
1354 }
1355
1356 //
1357 // If none valid records, exit.
1358 //
1359 if (ValidRecords == 0) {
1360 goto Exit;
1361 }
1362
1363 //
1364 // Build of location for Crash log in Hob
1365 //
1366 PmcCrashLogHob = (CRASHLOG_HOB *) BuildGuidHob (
1367 &gPmcCrashLogDataBufferHobGuid,
1368 sizeof (CRASHLOG_HOB) * ValidRecords
1369 );
1370 DEBUG ((DEBUG_INFO, "CrashLogDataBuffer = 0x%08x\n", PmcCrashLogHob));
1371 if (PmcCrashLogHob == NULL) {
1372 //
1373 // No enough hob resource.
1374 //
1375 return;
1376 }
1377
1378 for (Index = 0, TempPmcCrashLog = PmcCrashLogList; TempPmcCrashLog != NULL; Index++) {
1379 //
1380 // Fill allocate memory address and record size to Hob.
1381 //
1382 PmcCrashLogHob[Index].AllocateAddress = TempPmcCrashLog->AllocateAddress;
1383 PmcCrashLogHob[Index].Size = TempPmcCrashLog->Record.Info.Size;
1384 DEBUG ((DEBUG_INFO, "%d.CrashLogHob->AllocateAddress = 0x%08x\n", Index, PmcCrashLogHob[Index].AllocateAddress));
1385 DEBUG ((DEBUG_INFO, "%d.CrashLogHob->Size = 0x%x\n", Index, PmcCrashLogHob[Index].Size));
1386
1387 //
1388 // Initial pointers for copy crash log data.
1389 //
1390 Destination = (UINT32 *)(UINTN) TempPmcCrashLog->AllocateAddress;
1391 PmcCrashLogAddr = PmcSsramBar0 + TempPmcCrashLog->Record.Info.Offset;
1392 CopiedSize = 0;
1393
1394 //
1395 // Copy CrashLog data from SSRAM to allocated memory buffer
1396 //
1397 while (CopiedSize < TempPmcCrashLog->Record.Info.Size) {
1398 *Destination = MmioRead32 (PmcCrashLogAddr); // Byte access is not allowed to PMC SSRAM, hence copying DW by DW
1399 Destination++;
1400 PmcCrashLogAddr += 4;
1401 CopiedSize += 4;
1402 }
1403
1404 //
1405 // Point to next PmcCrashLog
1406 //
1407 TempPmcCrashLog = TempPmcCrashLog->Next;
1408 }
1409
1410 if (GetPmcReArmSupport (&DiscoveryBuffer) == TRUE) {
1411 //
1412 // Trigger re-arm command.
1413 //
1414 Status = PmcCrashLogReArm ();
1415 DEBUG ((DEBUG_INFO, "Re-arm Status = %r\n", Status));
1416 }
1417
1418 if (GetPmcClearSupport (&DiscoveryBuffer) == TRUE) {
1419 //
1420 // Clear the SSRAM region after copying the error log
1421 //
1422 Status = PmcCrashLogClear ();
1423 DEBUG ((DEBUG_INFO, "Clear CrashLog Status = %r\n", Status));
1424 }
1425
1426 Exit:
1427 //
1428 // Disable PMC SSRAM MMIO
1429 //
1430 PciSegmentAnd16 (PmcSsramBaseAddress + PCI_COMMAND_OFFSET, (UINT16) ~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE));
1431 PciSegmentWrite32 (PmcSsramBaseAddress + PCI_BASE_ADDRESSREG_OFFSET, 0);
1432 DEBUG ((DEBUG_INFO, "CrashLogCollectDataFromPmcSSRAM - end\n"));
1433
1434 return;
1435 }
1436
1437 /**
1438 Collect CPU CrashLog data from Telemetry SRAM and store in HOB .
1439
1440 **/
1441 VOID
1442 CpuCrashLogCollectDataFromTelemetrySRAM (
1443 VOID
1444 )
1445 {
1446 EFI_STATUS Status;
1447 TEL_CRASHLOG_DEVSC_CAP CrashLogDevscCap;
1448 UINT64 TelemetryPciDeviceBaseAddr;
1449 UINT32 TempBarAddr;
1450 EFI_PHYSICAL_ADDRESS MainLogAllocateAddress;
1451 EFI_PHYSICAL_ADDRESS TelemetryAllocateAddress;
1452 EFI_PHYSICAL_ADDRESS TraceAllocateAddress;
1453 UINT32 MainLogSize = 0;
1454 UINT32 TelemetrySize = 0;
1455 UINT32 TraceSize = 0;
1456 UINT32 CpuCrashLogAddr;
1457 CPU_CRASHLOG_STRUCT CpuCrashLogStruct;
1458 CPU_CRASHLOG_HOB CpuCrashLogHob;
1459 UINT32 *Destination = NULL;
1460 UINT32 CopiedSize = 0;
1461 UINT32 BaseAddress;
1462 CPU_CRASHLOG_HEADER CrashlogHeader;
1463 UINT32 Data32;
1464
1465 DEBUG ((DEBUG_INFO, "CpuCrashLogCollectDataFromTelemetrySRAM - start\n"));
1466
1467 //
1468 // Check for the availability of CPU CrashLog feature
1469 //
1470 ZeroMem (&CrashLogDevscCap, sizeof (TEL_CRASHLOG_DEVSC_CAP));
1471
1472 Status = GetCpuCrashLogCapability (&CrashLogDevscCap);
1473
1474 if (EFI_ERROR (Status)) {
1475 DEBUG ((DEBUG_INFO, "CPU CrashLog feature is not supported\n"));
1476 return;
1477 }
1478
1479 //
1480 // Start to access Telemetry MMIO
1481 //
1482 TelemetryPciDeviceBaseAddr = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, TEL_BUS_NUM, TEL_DEV_NUM, TEL_FUN_NUM, 0);
1483 DEBUG ((DEBUG_INFO, "TelemetryPciDeviceBaseAddr = 0x%X\n", TelemetryPciDeviceBaseAddr));
1484
1485 //
1486 // Program BAR address and enable command register memory space decoding
1487 //
1488 TempBarAddr = PcdGet32 (PcdSiliconInitTempMemBaseAddr);
1489 DEBUG ((DEBUG_INFO, "TempBarAddr = 0x%X\n", TempBarAddr));
1490 if (CrashLogDevscCap.DiscoveryData.Fields.TBir == V_TEL_DVSEC_TBIR_BAR0) {
1491 PciSegmentWrite32 (TelemetryPciDeviceBaseAddr + R_TEL_CFG_BAR0, TempBarAddr);
1492 } else if (CrashLogDevscCap.DiscoveryData.Fields.TBir == V_TEL_DVSEC_TBIR_BAR1) {
1493 PciSegmentWrite32 (TelemetryPciDeviceBaseAddr + R_TEL_CFG_BAR1, TempBarAddr);
1494 }
1495 PciSegmentOr16 (TelemetryPciDeviceBaseAddr + PCI_COMMAND_OFFSET, (UINT16) (EFI_PCI_COMMAND_MEMORY_SPACE));
1496
1497 ZeroMem (&CpuCrashLogStruct, sizeof (CPU_CRASHLOG_STRUCT));
1498
1499 Status = CpuCrashLogDiscovery (&CpuCrashLogStruct);
1500
1501 MainLogSize = CpuCrashLogStruct.MainBuffer.Fields.DataBuffSize * 4;
1502 TelemetrySize = CpuCrashLogStruct.TelemetryBuffer.Fields.DataBuffSize * 4;
1503 TraceSize = CpuCrashLogStruct.TraceBuffer.Fields.DataBuffSize * 4;
1504
1505 DEBUG ((DEBUG_INFO, "Use MainLog Size as 0x%X \n", MainLogSize));
1506 DEBUG ((DEBUG_INFO, "Use Telemetry Size as 0x%X \n", TelemetrySize));
1507 DEBUG ((DEBUG_INFO, "Use Trace Size as 0x%X \n", TraceSize));
1508
1509 if (MainLogSize == 0) {
1510 DEBUG ((DEBUG_INFO, "MainLog is not present \n"));
1511 goto Exit;
1512 }
1513
1514 //
1515 // Check if the first DW of CPU crashlog is valid
1516 //
1517 CpuCrashLogAddr = (UINT32) TempBarAddr + CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress;
1518 Data32 = MmioRead32 (CpuCrashLogAddr);
1519 if (Data32 == 0) {
1520 DEBUG ((DEBUG_INFO, "Cpu MainLog is invalid \n"));
1521 goto Exit;
1522 }
1523
1524 if (TelemetrySize == 0) {
1525 DEBUG ((DEBUG_INFO, "TelemetryLog is not present \n"));
1526 }
1527
1528 if (TraceSize == 0) {
1529 DEBUG ((DEBUG_INFO, "TraceLog is not present \n"));
1530 }
1531
1532 //
1533 // Allocate memory buffer for MainLog data
1534 //
1535 Status = PeiServicesAllocatePages (
1536 EfiBootServicesData,
1537 EFI_SIZE_TO_PAGES (MainLogSize),
1538 &MainLogAllocateAddress
1539 );
1540 DEBUG ((DEBUG_INFO, "MainLogAllocateAddress : 0x%X \n", MainLogAllocateAddress));
1541
1542 if (EFI_ERROR (Status)) {
1543 DEBUG ((DEBUG_ERROR, "Memory out of resource\n"));
1544 goto Exit;
1545 }
1546
1547 //
1548 // Allocate memory buffer for Telemetry data
1549 //
1550 Status = PeiServicesAllocatePages (
1551 EfiBootServicesData,
1552 EFI_SIZE_TO_PAGES (TelemetrySize),
1553 &TelemetryAllocateAddress
1554 );
1555 DEBUG ((DEBUG_INFO, "TelemetryAllocateAddress : 0x%X \n", TelemetryAllocateAddress));
1556
1557 if (EFI_ERROR (Status)) {
1558 DEBUG ((DEBUG_ERROR, "Memory out of resource\n"));
1559 goto Exit;
1560 }
1561
1562 //
1563 // Allocate memory buffer for Trace data
1564 //
1565 Status = PeiServicesAllocatePages (
1566 EfiBootServicesData,
1567 EFI_SIZE_TO_PAGES (TraceSize),
1568 &TraceAllocateAddress
1569 );
1570 DEBUG ((DEBUG_INFO, "TraceAllocateAddress : 0x%X \n", TraceAllocateAddress));
1571
1572 if (EFI_ERROR (Status)) {
1573 DEBUG ((DEBUG_ERROR, "Memory out of resource\n"));
1574 goto Exit;
1575 }
1576
1577
1578 CpuCrashLogHob.Main.AllocateAddress = (UINTN) MainLogAllocateAddress;
1579 CpuCrashLogHob.Main.Size = MainLogSize;
1580
1581 CpuCrashLogHob.Telemetry.AllocateAddress = (UINTN) TelemetryAllocateAddress;
1582 CpuCrashLogHob.Telemetry.Size = TelemetrySize;
1583
1584 CpuCrashLogHob.Trace.AllocateAddress = (UINTN) TraceAllocateAddress;
1585 CpuCrashLogHob.Trace.Size = TraceSize;
1586
1587 //
1588 // Build of location for Crash log in Hob
1589 //
1590 BuildGuidDataHob (
1591 &gCpuCrashLogDataBufferHobGuid,
1592 &CpuCrashLogHob,
1593 sizeof (CPU_CRASHLOG_HOB)
1594 );
1595 DEBUG ((DEBUG_INFO, "CpuCrashLogHob = 0x%X, sizeof (CPU_CRASHLOG_HOB) : 0x%X \n", CpuCrashLogHob, sizeof (CPU_CRASHLOG_HOB)));
1596
1597 ZeroMem ((VOID *) (UINTN) MainLogAllocateAddress, EFI_SIZE_TO_PAGES (MainLogSize) * EFI_PAGE_SIZE);
1598 ZeroMem ((VOID *) (UINTN) TelemetryAllocateAddress, EFI_SIZE_TO_PAGES (TelemetrySize) * EFI_PAGE_SIZE);
1599 ZeroMem ((VOID *) (UINTN) TraceAllocateAddress, EFI_SIZE_TO_PAGES (TraceSize) * EFI_PAGE_SIZE);
1600
1601 //
1602 // copy Main pointer crashlog data
1603 //
1604 // CopyMem ((UINT8 *)(UINTN) MainLogAllocateAddress, &(TelemetryBaseAddress + CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress), (CpuCrashLogStruct.MainBuffer.Fields.DataBuffSize) * 4);
1605 CpuCrashLogAddr = (UINT32) TempBarAddr + CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress;
1606 Destination = (UINT32 *)(UINTN) MainLogAllocateAddress;
1607 while (CopiedSize < MainLogSize) {
1608 *Destination = MmioRead32 (CpuCrashLogAddr); // Byte access is not allowed to PMC SSRAM, hence copying DW by DW
1609 if (CopiedSize < CRASHLOG_SIZE_DEBUG_PURPOSE) { // Dumping only few bytes to help debug
1610 DEBUG ((DEBUG_INFO, "Main CrashData = 0x%x\n", *Destination));
1611 }
1612 Destination++;
1613 CpuCrashLogAddr += 4;
1614 CopiedSize += 4;
1615 }
1616 CpuCrashLogAddr = (UINT32) TempBarAddr + CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress;
1617 DEBUG ((DEBUG_INFO, "TempBarAddr = 0x%x, CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress = 0x%x, MainLogCrashLogAddr = 0x%x\n", TempBarAddr, CpuCrashLogStruct.MainBuffer.Fields.DataBuffAddress, CpuCrashLogAddr));
1618
1619 //
1620 // copy Telemetry pointer crashlog data
1621 //
1622 // CopyMem ((UINT8 *)(UINTN) TelemetryAllocateAddress, &(TelemetryBaseAddress + CpuCrashLogStruct.TelemetryBuffer.Fields.DataBuffAddress), (CpuCrashLogStruct.TelemetryBuffer.Fields.DataBuffSize) * 4);
1623 CpuCrashLogAddr = (UINT32) TempBarAddr + CpuCrashLogStruct.TelemetryBuffer.Fields.DataBuffAddress;
1624 DEBUG ((DEBUG_INFO, "TempBarAddr = 0x%x, TelemetryBuffer.Fields.DataBuffAddress = 0x%x, TelemetryCrashLogAddr = 0x%x\n", TempBarAddr, CpuCrashLogStruct.TelemetryBuffer.Fields.DataBuffAddress, CpuCrashLogAddr));
1625 Destination = (UINT32 *)(UINTN) TelemetryAllocateAddress;
1626 CopiedSize = 0;
1627 while (CopiedSize < TelemetrySize) {
1628 *Destination = MmioRead32 (CpuCrashLogAddr); // Byte access is not allowed to PMC SSRAM, hence copying DW by DW
1629 if (CopiedSize < CRASHLOG_SIZE_DEBUG_PURPOSE) { // Dumping only few bytes to help debug
1630 DEBUG ((DEBUG_INFO, "Telemetry CrashData = 0x%x\n", *Destination));
1631 }
1632 Destination++;
1633 CpuCrashLogAddr += 4;
1634 CopiedSize += 4;
1635 }
1636 //
1637 // copy Trace pointer crashlog data
1638 //
1639 // CopyMem ((UINT8 *)(UINTN) TraceAllocateAddress, &(TelemetryBaseAddress + CpuCrashLogStruct.TraceBuffer.Fields.DataBuffAddress), (CpuCrashLogStruct.TraceBuffer.Fields.DataBuffSize) * 4);
1640 CpuCrashLogAddr = (UINT32) TempBarAddr + CpuCrashLogStruct.TraceBuffer.Fields.DataBuffAddress;
1641 DEBUG ((DEBUG_INFO, "TempBarAddr = 0x%x, TraceBuffer.Fields.DataBuffAddress = 0x%x, TraceCrashLogAddr = 0x%x\n", TempBarAddr, CpuCrashLogStruct.TraceBuffer.Fields.DataBuffAddress, CpuCrashLogAddr));
1642 Destination = (UINT32 *)(UINTN) TraceAllocateAddress;
1643 CopiedSize = 0;
1644 while (CopiedSize < TraceSize) {
1645 *Destination = MmioRead32 (CpuCrashLogAddr); // Byte access is not allowed to PMC SSRAM, hence copying DW by DW
1646 if (CopiedSize < CRASHLOG_SIZE_DEBUG_PURPOSE) { // Dumping only few bytes to help debug
1647 DEBUG ((DEBUG_INFO, "Trace CrashData = 0x%x\n", *Destination));
1648 }
1649 Destination++;
1650 CpuCrashLogAddr += 4;
1651 CopiedSize += 4;
1652 }
1653
1654 BaseAddress = GetCpuCrashLogBarAddress (&CrashLogDevscCap);
1655 GetCrashLogHeader (BaseAddress, &CrashlogHeader);
1656
1657 //
1658 // Clear the Telemetry SRAM region after copying the error log
1659 //
1660 CpuCrashLogClear ();
1661
1662 //
1663 // Send re-arm command
1664 //
1665 if (GetCpuReArmSupport (&CrashlogHeader) == TRUE) {
1666 CpuCrashLogReArm ();
1667 DEBUG ((DEBUG_INFO, "Re-arm Status = %r\n", Status));
1668 }
1669
1670 Exit:
1671 //
1672 // Disable Telemetry SRAM MMIO
1673 //
1674 PciSegmentAnd16 (TelemetryPciDeviceBaseAddr + PCI_COMMAND_OFFSET, (UINT16) ~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE));
1675 if (CrashLogDevscCap.DiscoveryData.Fields.TBir == V_TEL_DVSEC_TBIR_BAR0) {
1676 PciSegmentWrite32 (TelemetryPciDeviceBaseAddr + R_TEL_CFG_BAR0, 0);
1677 } else if (CrashLogDevscCap.DiscoveryData.Fields.TBir == V_TEL_DVSEC_TBIR_BAR1) {
1678 PciSegmentWrite32 (TelemetryPciDeviceBaseAddr + R_TEL_CFG_BAR1, 0);
1679 }
1680 DEBUG ((DEBUG_INFO, "CpuCrashLogCollectDataFromTelemetrySRAM - end\n"));
1681
1682 return;
1683 }
1684
1685 /**
1686 Configures GPIO
1687
1688 @param[in] GpioTable Point to Platform Gpio table
1689 @param[in] GpioTableCount Number of Gpio table entries
1690
1691 **/
1692 VOID
1693 ConfigureGpio (
1694 IN GPIO_INIT_CONFIG *GpioDefinition,
1695 IN UINT16 GpioTableCount
1696 )
1697 {
1698 EFI_STATUS Status;
1699
1700 DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
1701
1702 Status = GpioConfigurePads (GpioTableCount, GpioDefinition);
1703 ASSERT_EFI_ERROR (Status);
1704
1705 DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
1706 }
1707
1708 /**
1709 Configure GPIO pads for Foxville I225 Lan based on the Setup Option
1710 **/
1711 VOID
1712 FoxvilleLanGpioInit (
1713 VOID
1714 )
1715 {
1716 EFI_STATUS Status;
1717 PCH_SETUP PchSetup;
1718 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1719 UINTN VarSize;
1720 GPIO_PAD FoxLanEnablePad;
1721 GPIO_PAD FoxLanWakePad;
1722 GPIO_CONFIG FoxLanEnablePadConfig;
1723 GPIO_CONFIG FoxLanWakePadConfig;
1724
1725 if ((PcdGet32 (PcdFoxLanEnableGpio) != 0) && (PcdGet32 (PcdFoxLanWakeGpio) != 0)) {
1726 DEBUG ((DEBUG_INFO, "FoxvilleLanGpioInit Start\n"));
1727
1728 //
1729 // Locate Setup variables
1730 //
1731 Status = PeiServicesLocatePpi (
1732 &gEfiPeiReadOnlyVariable2PpiGuid,
1733 0,
1734 NULL,
1735 (VOID **) &VariableServices
1736 );
1737
1738 if (EFI_ERROR (Status)) {
1739 DEBUG ((DEBUG_ERROR, "FoxvilleLanGpioInit: PeiServicesLocatePpi failed\n"));
1740 return;
1741 }
1742
1743 VarSize = sizeof (PCH_SETUP);
1744 Status = VariableServices-> GetVariable (
1745 VariableServices,
1746 L"PchSetup",
1747 &gPchSetupVariableGuid,
1748 NULL,
1749 &VarSize,
1750 &PchSetup
1751 );
1752 if (EFI_ERROR (Status)) {
1753 DEBUG ((DEBUG_ERROR, "FoxvilleLanGpioInit: GetVariable (PchSetup) failed\n"));
1754 return;
1755 }
1756
1757 if (PchSetup.FoxvilleLanSupport) {
1758 DEBUG ((DEBUG_INFO, "Setting Foxville Lan Support Gpio\n"));
1759 FoxLanEnablePad = PcdGet32 (PcdFoxLanEnableGpio);
1760 ZeroMem (&FoxLanEnablePadConfig, sizeof (FoxLanEnablePadConfig));
1761 FoxLanEnablePadConfig.Direction = GpioDirOut;
1762 FoxLanEnablePadConfig.OutputState = GpioOutHigh;
1763 Status = GpioSetPadConfig (FoxLanEnablePad, &FoxLanEnablePadConfig); // Setting FOXVILLE_LAN_EN Output High
1764
1765 if (PchSetup.FoxvilleWakeOnLan) {
1766 DEBUG ((DEBUG_INFO, "Setting Foxville Lan Wake Gpio\n"));
1767 FoxLanWakePad = PcdGet32 (PcdFoxLanWakeGpio);
1768 ZeroMem (&FoxLanWakePadConfig, sizeof (FoxLanWakePadConfig));
1769 FoxLanWakePadConfig.Direction = GpioDirInInv;
1770 FoxLanWakePadConfig.InterruptConfig = GpioIntEdge|GpioIntSci;
1771 FoxLanWakePadConfig.LockConfig = GpioPadConfigUnlock;
1772 Status = GpioSetPadConfig (FoxLanWakePad, &FoxLanWakePadConfig); // Setting FOX_WAKE_N interrupt as SCI
1773 }
1774
1775 if (EFI_ERROR (Status)) {
1776 DEBUG ((DEBUG_ERROR, "FoxvilleLanGpioInit: GpioSetPadConfig failed\n"));
1777 return;
1778 }
1779 }
1780 DEBUG ((DEBUG_INFO, "FoxvilleLanGpioInit End\n"));
1781 } else {
1782 DEBUG ((DEBUG_INFO, "FoxvilleLanGpioInit Skipped\n"));
1783 }
1784 }
1785
1786 /**
1787 Configure GPIO pads for TouchPanels use
1788 **/
1789 VOID
1790 TouchPanelGpioInit (
1791 VOID
1792 )
1793 {
1794 EFI_STATUS Status;
1795 PCH_SETUP PchSetup;
1796 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1797 UINTN VarSize;
1798 UINT16 BoardId;
1799 SETUP_DATA Setup;
1800
1801 DEBUG ((DEBUG_INFO, "TouchPanelGpioInit Start\n"));
1802
1803 //
1804 // Locate Setup variables
1805 //
1806 Status = PeiServicesLocatePpi (
1807 &gEfiPeiReadOnlyVariable2PpiGuid,
1808 0,
1809 NULL,
1810 (VOID **) &VariableServices
1811 );
1812 if (EFI_ERROR (Status)) {
1813 DEBUG ((DEBUG_ERROR, "TouchPanelGpioInit: PeiServicesLocatePpi failed\n"));
1814 return;
1815 }
1816
1817 VarSize = sizeof (PCH_SETUP);
1818 Status = VariableServices->GetVariable (
1819 VariableServices,
1820 L"PchSetup",
1821 &gPchSetupVariableGuid,
1822 NULL,
1823 &VarSize,
1824 &PchSetup
1825 );
1826 if (EFI_ERROR (Status)) {
1827 DEBUG ((DEBUG_ERROR, "TouchPanelGpioInit: GetVariable (PchSetup) failed\n"));
1828 return;
1829 }
1830
1831 VarSize = sizeof (SETUP_DATA);
1832 Status = VariableServices->GetVariable (
1833 VariableServices,
1834 L"Setup",
1835 &gSetupVariableGuid,
1836 NULL,
1837 &VarSize,
1838 &Setup
1839 );
1840 if (EFI_ERROR (Status)) {
1841 DEBUG ((DEBUG_ERROR, "TouchPanelGpioInit: GetVariable (Setup) failed\n"));
1842 return;
1843 }
1844
1845 BoardId = PcdGet16(PcdBoardId);
1846
1847 switch (BoardId) {
1848 case BoardIdAdlPLp4Bep:
1849 case BoardIdAdlPLp5Rvp:
1850 case BoardIdAdlPT3Lp5Rvp:
1851 case BoardIdAdlPLp4Rvp:
1852 case BoardIdAdlPDdr5MRRvp:
1853 case BoardIdAdlPDdr5Rvp:
1854 case BoardIdAdlPDdr4Rvp:
1855 case BoardIdAdlPSimics:
1856 case BoardIdAdlPDdr5Dg384Aep:
1857 case BoardIdAdlPLp5Aep:
1858 case BoardIdAdlMLp4Rvp:
1859 case BoardIdAdlMLp5Rvp:
1860 case BoardIdAdlMLp5Rvp2a:
1861 case BoardIdAdlMLp5PmicRvp:
1862 case BoardIdAdlMLp5Aep:
1863 case BoardIdAdlPLp5Dg128Aep:
1864 case BoardIdAdlPLp5Gcs:
1865 //
1866 // Verify if THC0 or THC1 panels are enabled before changing GPIO configuration
1867 //
1868 if (PchSetup.ThcPort0Assignment == ThcAssignmentNone && (Setup.PchI2cTouchPanelType != 0)) {
1869 DEBUG ((DEBUG_INFO, "THC0 Disabled. Configuring GPIO Touch Panel 1 set for other controller use\n"));
1870 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel1), (UINTN) PcdGet16 (PcdBoardGpioTableTouchPanel1Size));
1871 }
1872 break;
1873 }
1874 DEBUG ((DEBUG_INFO, "TouchPanelGpioInit End\n"));
1875 }
1876
1877
1878 /**
1879 Configure GPIO pads for CVF use
1880 **/
1881 VOID
1882 CvfGpioInit (
1883 VOID
1884 )
1885 {
1886 EFI_STATUS Status;
1887 SETUP_DATA SetupData;
1888 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1889 UINTN VarSize;
1890
1891 DEBUG ((DEBUG_INFO, "CvfGpioInit Start\n"));
1892
1893 //
1894 // Locate Setup variables
1895 //
1896 Status = PeiServicesLocatePpi (
1897 &gEfiPeiReadOnlyVariable2PpiGuid,
1898 0,
1899 NULL,
1900 (VOID **) &VariableServices
1901 );
1902 if (EFI_ERROR (Status)) {
1903 DEBUG ((DEBUG_ERROR, "CvfGpioInit: PeiServicesLocatePpi failed\n"));
1904 return;
1905 }
1906
1907 VarSize = sizeof (SETUP_DATA);
1908 Status = VariableServices->GetVariable (
1909 VariableServices,
1910 L"Setup",
1911 &gSetupVariableGuid,
1912 NULL,
1913 &VarSize,
1914 &SetupData
1915 );
1916 if (EFI_ERROR (Status)) {
1917 DEBUG ((DEBUG_ERROR, "CvfGpioInit: GetVariable (Setup) failed\n"));
1918 return;
1919 }
1920
1921 //
1922 // Configure CVF GPIO only when its enabled in setup as NIO or USB Bridge.
1923 //
1924 if ((SetupData.CvfSupport > 0x00) && (SetupData.CvfSupport <3 )) {
1925 DEBUG ((DEBUG_INFO, "Configure CVF gpio\n"));
1926 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableCvf), (UINTN) PcdGet16 (PcdBoardGpioTableCvfSize));
1927 }
1928 DEBUG ((DEBUG_INFO, "CvfGpioInit End\n"));
1929 }
1930
1931 VOID
1932 ConnectivityGpioInit (
1933 VOID
1934 )
1935 {
1936 EFI_STATUS Status;
1937 PCH_SETUP PchSetup;
1938 SETUP_DATA SetupData;
1939 UINTN VarSize;
1940 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1941
1942 //
1943 // Locate Setup variables
1944 //
1945 Status = PeiServicesLocatePpi (
1946 &gEfiPeiReadOnlyVariable2PpiGuid,
1947 0,
1948 NULL,
1949 (VOID **) &VariableServices
1950 );
1951 if (EFI_ERROR (Status)) {
1952 DEBUG ((DEBUG_ERROR, "ConnectivityGpioInit: PeiServicesLocatePpi failed\n"));
1953 return;
1954 }
1955
1956 VarSize = sizeof (PCH_SETUP);
1957 Status = VariableServices->GetVariable (
1958 VariableServices,
1959 L"PchSetup",
1960 &gPchSetupVariableGuid,
1961 NULL,
1962 &VarSize,
1963 &PchSetup
1964 );
1965 if (EFI_ERROR (Status)) {
1966 DEBUG ((DEBUG_ERROR, "ConnectivityGpioInit: GetVariable (PchSetup) failed\n"));
1967 return;
1968 }
1969
1970 VarSize = sizeof (SETUP_DATA);
1971 Status = VariableServices->GetVariable (
1972 VariableServices,
1973 L"Setup",
1974 &gSetupVariableGuid,
1975 NULL,
1976 &VarSize,
1977 &SetupData
1978 );
1979 if (EFI_ERROR(Status)) {
1980 DEBUG((DEBUG_ERROR, "ConnectivityGpioInit: GetVariable (SetupData) failed\n"));
1981 return;
1982 }
1983 if (!CnviIsPresent () || (PchSetup.CnviMode == CnviModeDisabled)) {
1984 //
1985 // Discrete BT Module Selection as Disabled, Over USB or UART
1986 //
1987 PcdSet8S (PcdDiscreteBtModule, SetupData.DiscreteBtModule);
1988 }
1989 if (!CnviIsPresent () && PcdGet32 (PcdBoardGpioTableCnvd) != 0 && PcdGet16 (PcdBoardGpioTableCnvdSize) != 0) {
1990 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableCnvd), (UINTN) PcdGet16 (PcdBoardGpioTableCnvdSize));
1991 }
1992 }
1993
1994 VOID
1995 MipiCamConfigureGpio (
1996 IN GPIO_CONFIG *GpioConfig
1997 )
1998 {
1999 ZeroMem(GpioConfig, sizeof(GPIO_CONFIG));
2000 GpioConfig->PadMode = GpioPadModeGpio;
2001 GpioConfig->HostSoftPadOwn = GpioHostOwnGpio;
2002 GpioConfig->Direction = GpioDirOut;
2003 GpioConfig->OutputState = GpioOutDefault;
2004 GpioConfig->InterruptConfig = GpioIntDis;
2005 GpioConfig->PowerConfig = GpioPlatformReset;
2006 GpioConfig->ElectricalConfig = GpioTermNone;
2007 }
2008
2009 VOID
2010 MipiCamGpioInit (
2011 VOID
2012 )
2013 {
2014 PCH_SETUP PchSetup;
2015 SETUP_DATA SetupData;
2016 UINTN VarSize;
2017 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
2018 EFI_STATUS Status;
2019 GPIO_CONFIG GpioConfig;
2020 GPIO_PAD GpioPad;
2021 UINT8 GpioPin;
2022
2023 //
2024 // Locate Setup variables
2025 //
2026 Status = PeiServicesLocatePpi (
2027 &gEfiPeiReadOnlyVariable2PpiGuid,
2028 0,
2029 NULL,
2030 (VOID **) &VariableServices
2031 );
2032 if (EFI_ERROR(Status)) {
2033 DEBUG((DEBUG_ERROR, "MipiCamGpioInit: PeiServicesLocatePpi failed\n"));
2034 return;
2035 }
2036
2037 VarSize = sizeof (PCH_SETUP);
2038 Status = VariableServices->GetVariable (
2039 VariableServices,
2040 L"PchSetup",
2041 &gPchSetupVariableGuid,
2042 NULL,
2043 &VarSize,
2044 &PchSetup
2045 );
2046 if (EFI_ERROR(Status)) {
2047 DEBUG((DEBUG_ERROR, "MipiCamGpioInit: GetVariable (PchSetup) failed\n"));
2048 return;
2049 }
2050
2051 VarSize = sizeof (SETUP_DATA);
2052 Status = VariableServices->GetVariable (
2053 VariableServices,
2054 L"Setup",
2055 &gSetupVariableGuid,
2056 NULL,
2057 &VarSize,
2058 &SetupData
2059 );
2060 if (EFI_ERROR(Status)) {
2061 DEBUG((DEBUG_ERROR, "MipiCamGpioInit: GetVariable (SetupData) failed\n"));
2062 return;
2063 }
2064 if (SetupData.MipiCam_ControlLogic0) {
2065 DEBUG((DEBUG_INFO, "MipiCamGpioInit ControlLogic0\n =%X",SetupData.MipiCam_ControlLogic0_Type));
2066 MipiCamConfigureGpio (&GpioConfig);
2067 //
2068 // If PMIC based control logic, configure gpio with TX state high to avoid PMIC goes into reset.
2069 //
2070 if((SetupData.MipiCam_ControlLogic0_Type == 2) || (SetupData.MipiCam_ControlLogic0_Type == 3)) {
2071 GpioConfig.OutputState = GpioOutHigh;
2072 }
2073 for (GpioPin = 0; GpioPin < SetupData.MipiCam_ControlLogic0_GpioPinsEnabled; GpioPin ++) {
2074 GpioPad = GpioGetGpioPadFromGroupIndexAndPadNumber (
2075 (UINT32)SetupData.MipiCam_ControlLogic0_GpioGroupNumber[GpioPin],
2076 (UINT32)SetupData.MipiCam_ControlLogic0_GpioGroupPadNumber[GpioPin]);
2077 DEBUG((DEBUG_INFO, "MipiCamGpioInit GpioPad 0x%x\n", GpioPad));
2078 GpioSetPadConfig (GpioPad, &GpioConfig);
2079 }
2080 }
2081 if (SetupData.MipiCam_ControlLogic1) {
2082 DEBUG((DEBUG_INFO, "MipiCamGpioInit ControlLogic1 =%X\n",SetupData.MipiCam_ControlLogic1_Type));
2083 MipiCamConfigureGpio (&GpioConfig);
2084 //
2085 // If PMIC based control logic, configure gpio with TX state high to avoid PMIC goes into reset.
2086 //
2087 if((SetupData.MipiCam_ControlLogic1_Type == 2) || (SetupData.MipiCam_ControlLogic1_Type == 3)) {
2088 GpioConfig.OutputState = GpioOutHigh;
2089 }
2090 for (GpioPin = 0; GpioPin < SetupData.MipiCam_ControlLogic1_GpioPinsEnabled; GpioPin ++) {
2091 GpioPad = GpioGetGpioPadFromGroupIndexAndPadNumber (
2092 (UINT32)SetupData.MipiCam_ControlLogic1_GpioGroupNumber[GpioPin],
2093 (UINT32)SetupData.MipiCam_ControlLogic1_GpioGroupPadNumber[GpioPin]);
2094 DEBUG((DEBUG_INFO, "MipiCamGpioInit GpioPad 0x%x\n", GpioPad));
2095 GpioSetPadConfig (GpioPad, &GpioConfig);
2096 }
2097 }
2098 if (SetupData.MipiCam_ControlLogic2) {
2099 DEBUG((DEBUG_INFO, "MipiCamGpioInit ControlLogic2 Type = %X\n",SetupData.MipiCam_ControlLogic2_Type));
2100 MipiCamConfigureGpio (&GpioConfig);
2101 //
2102 // If PMIC based control logic, configure gpio with TX state high to avoid PMIC goes into reset.
2103 //
2104 if((SetupData.MipiCam_ControlLogic2_Type == 2) || (SetupData.MipiCam_ControlLogic2_Type == 3)) {
2105 GpioConfig.OutputState = GpioOutHigh;
2106 }
2107 for (GpioPin = 0; GpioPin < SetupData.MipiCam_ControlLogic2_GpioPinsEnabled; GpioPin ++) {
2108 GpioPad = GpioGetGpioPadFromGroupIndexAndPadNumber (
2109 (UINT32)SetupData.MipiCam_ControlLogic2_GpioGroupNumber[GpioPin],
2110 (UINT32)SetupData.MipiCam_ControlLogic2_GpioGroupPadNumber[GpioPin]);
2111 DEBUG((DEBUG_INFO, "MipiCamGpioInit GpioPad 0x%x\n", GpioPad));
2112 GpioSetPadConfig (GpioPad, &GpioConfig);
2113 }
2114 }
2115 if (SetupData.MipiCam_ControlLogic3) {
2116 DEBUG((DEBUG_INFO, "MipiCamGpioInit ControlLogic3 Type = %X\n",SetupData.MipiCam_ControlLogic3_Type));
2117 MipiCamConfigureGpio (&GpioConfig);
2118 //
2119 // If PMIC based control logic, configure gpio with TX state high to avoid PMIC goes into reset.
2120 //
2121 if((SetupData.MipiCam_ControlLogic3_Type == 2) || (SetupData.MipiCam_ControlLogic3_Type == 3)) {
2122 GpioConfig.OutputState = GpioOutHigh;
2123 }
2124 for (GpioPin = 0; GpioPin < SetupData.MipiCam_ControlLogic3_GpioPinsEnabled; GpioPin ++) {
2125 GpioPad = GpioGetGpioPadFromGroupIndexAndPadNumber (
2126 (UINT32)SetupData.MipiCam_ControlLogic3_GpioGroupNumber[GpioPin],
2127 (UINT32)SetupData.MipiCam_ControlLogic3_GpioGroupPadNumber[GpioPin]);
2128 DEBUG((DEBUG_INFO, "MipiCamGpioInit GpioPad 0x%x\n", GpioPad));
2129 GpioSetPadConfig (GpioPad, &GpioConfig);
2130 }
2131 }
2132 return;
2133 }
2134
2135
2136 VOID
2137 TsnDeviceGpioInit (
2138 VOID
2139 )
2140 {
2141 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
2142 EFI_STATUS Status;
2143 PCH_SETUP PchSetup;
2144 UINTN VarSize;
2145 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
2146
2147 DEBUG ((DEBUG_INFO, "TsnDeviceGpioInit() Start\n"));
2148
2149 //
2150 // Locate Setup variables
2151 //
2152 Status = PeiServicesLocatePpi (
2153 &gEfiPeiReadOnlyVariable2PpiGuid,
2154 0,
2155 NULL,
2156 (VOID **) &VariableServices
2157 );
2158 if (EFI_ERROR (Status)) {
2159 DEBUG ((DEBUG_ERROR, "TsnGpioInit: PeiServicesLocatePpi failed\n"));
2160 return;
2161 }
2162
2163 VarSize = sizeof (PCH_SETUP);
2164 Status = VariableServices->GetVariable (
2165 VariableServices,
2166 L"PchSetup",
2167 &gPchSetupVariableGuid,
2168 NULL,
2169 &VarSize,
2170 &PchSetup
2171 );
2172 if (EFI_ERROR (Status)) {
2173 DEBUG ((DEBUG_ERROR, "TsnGpioInit: GetVariable (PchSetup) failed\n"));
2174 return;
2175 }
2176
2177 if (PchSetup.PchTsnEnable == 1) {
2178 DEBUG ((DEBUG_INFO, "TSN Device GpioInit\n"));
2179 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTsnDevice), (UINTN) PcdGet16 (PcdBoardGpioTableTsnDeviceSize));
2180 } else {
2181 //
2182 // Disable Tsn Pcs if TsnEnable feature not available
2183 //
2184 PchSetup.TsnPcsEnabled = 0;
2185 }
2186 DEBUG ((DEBUG_INFO, "TsnDeviceGpioInit() End\n"));
2187 #endif
2188 }
2189
2190 /**
2191 Configure advanced GPIO
2192
2193 **/
2194 VOID
2195 GpioInitAdvanced (
2196 VOID
2197 )
2198 {
2199 FoxvilleLanGpioInit ();
2200 TouchPanelGpioInit ();
2201
2202 // Configure Connectivity options
2203 ConnectivityGpioInit();
2204 if (PcdGetBool (PcdMipiCamGpioEnable)) {
2205 DEBUG ((DEBUG_INFO, "\nMIPI Camera GpioInit\n"));
2206 MipiCamGpioInit();
2207 DEBUG ((DEBUG_INFO, "\nCVF GpioInit\n"));
2208 CvfGpioInit();
2209 }
2210
2211
2212 TsnDeviceGpioInit ();
2213
2214 //
2215 // Lock pads after initializing platform GPIO.
2216 // Pads which were requested to be unlocked during configuration
2217 // will not be locked.
2218 //
2219 GpioLockPads ();
2220
2221 return;
2222 }
2223 /**
2224 Platform Init PEI module entry point
2225
2226 @param[in] FileHandle Not used.
2227 @param[in] PeiServices General purpose services available to every PEIM.
2228
2229 @retval EFI_SUCCESS The function completes successfully
2230 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
2231 **/
2232 EFI_STATUS
2233 EFIAPI
2234 PlatformInitAdvancedPostMemEntryPoint (
2235 IN EFI_PEI_FILE_HANDLE FileHandle,
2236 IN CONST EFI_PEI_SERVICES **PeiServices
2237 )
2238 {
2239 EFI_STATUS Status;
2240 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
2241 SETUP_DATA SetupData;
2242 UINTN VariableSize;
2243 UINT8 CrashLogCollect;
2244 PEI_CORE_INSTANCE *PrivateData;
2245 UINTN CurrentFv;
2246 PEI_CORE_FV_HANDLE *CoreFvHandle;
2247 VOID *HobData;
2248
2249 PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
2250
2251 Status = PeiServicesLocatePpi (
2252 &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
2253 0, // INSTANCE
2254 NULL, // EFI_PEI_PPI_DESCRIPTOR
2255 (VOID **) &VariableServices // PPI
2256 );
2257 ASSERT_EFI_ERROR (Status);
2258
2259 VariableSize = sizeof (SETUP_DATA);
2260 Status = VariableServices->GetVariable (
2261 VariableServices,
2262 PLATFORM_SETUP_VARIABLE_NAME,
2263 &gSetupVariableGuid,
2264 NULL,
2265 &VariableSize,
2266 &SetupData
2267 );
2268 if (EFI_ERROR (Status)) {
2269 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
2270 CrashLogCollect = 1;
2271 } else {
2272 CrashLogCollect = SetupData.EnableCrashLog;
2273 }
2274 //
2275 // BIOS shall extract Crash records from PMC SSRAM after memory init
2276 // and before enabling the Energy Reporting feature
2277 //
2278 if (CrashLogCollect == 1) {
2279 CrashLogCollectDataFromPmcSSRAM ();
2280 CpuCrashLogCollectDataFromTelemetrySRAM ();
2281 }
2282 GpioInitAdvanced();
2283 //
2284 // Build a HOB to show current FV location for SA policy update code to consume.
2285 //
2286 PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
2287 CurrentFv = PrivateData->CurrentPeimFvCount;
2288 CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
2289
2290 HobData = BuildGuidHob (
2291 &gPlatformInitFvLocationGuid,
2292 sizeof (VOID *)
2293 );
2294 ASSERT (HobData != NULL);
2295 CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
2296
2297 //
2298 // Create USB Boot First hotkey information HOB
2299 //
2300 CreateAttemptUsbFirstHotkeyInfoHob ();
2301
2302 #if FixedPcdGetBool(PcdAdlLpSupport) == 1
2303 //
2304 // Install mPeiGraphicsPlatformPpi
2305 //
2306 DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));
2307 Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
2308 #else
2309 //
2310 // Notify mPeiGraphicsPlatformNotifyList
2311 //
2312 DEBUG ((DEBUG_INFO, "Notify mPeiGraphicsPlatformNotifyList \n"));
2313 Status = PeiServicesNotifyPpi (&mPeiGraphicsPlatformNotifyList);
2314 #endif
2315
2316 Status = PeiServicesNotifyPpi (&mPlatformDebugStateChecksNotifyList);
2317
2318 //
2319 // Performing PlatformInitEndOfPei after EndOfPei PPI produced
2320 //
2321 Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
2322 PostCode (PLATFORM_INIT_POSTMEM_EXIT);
2323
2324 return Status;
2325 }
SystemNvDataGuid.h
CvfGpioInit
VOID CvfGpioInit(VOID)
Configure GPIO pads for CVF use.
Definition: PlatformInitAdvancedPostMem.c:1882
PeiGetSectionFromFv
EFI_STATUS PeiGetSectionFromFv(IN CONST EFI_GUID NameGuid, OUT VOID **Address, OUT UINT32 *Size)
PeiGetSectionFromFv finds the file in FV and gets file Address and Size.
MtrrLibInitializeMtrrMask
VOID MtrrLibInitializeMtrrMask(OUT UINT64 *MtrrValidBitsMask, OUT UINT64 *MtrrValidAddressMask)
Initializes the valid bits mask and valid address mask for MTRRs.
PremiumPmicEnableSlpS0Voltage
VOID PremiumPmicEnableSlpS0Voltage(VOID)
Pmic Programming to Enable Voltage Margining.
Definition: PlatformInitAdvancedPostMem.c:632
GetPmcCrashLogRecord
UINT32 GetPmcCrashLogRecord(IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer, IN UINT32 Offset)
Get offset and log size from PMC crash records.
Definition: PlatformInitAdvancedPostMem.c:980
PlatformDebugStateChecks
BOOLEAN PlatformDebugStateChecks(VOID)
Returns whether the platform is in a debug state, by checking if any of the following conditions is t...
Definition: PlatformInitAdvancedPostMem.c:761
GpioInitAdvanced
VOID GpioInitAdvanced(VOID)
Configure advanced GPIO.
Definition: PlatformInitAdvancedPostMem.c:2195
PeiGraphicsPlatformInit
EFI_STATUS PeiGraphicsPlatformInit(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function will pass data to Pei graphics PEIM.
Definition: PlatformInitAdvancedPostMem.c:378
GetPmcCrashLogSupport
BOOLEAN GetPmcCrashLogSupport(IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get PMC crash log supported or not.
Definition: PlatformInitAdvancedPostMem.c:1057
GetPmcCrashLogAmount
UINT32 GetPmcCrashLogAmount(IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get how many PMC crash log records.
Definition: PlatformInitAdvancedPostMem.c:954
CreateAttemptUsbFirstHotkeyInfoHob
EFI_STATUS CreateAttemptUsbFirstHotkeyInfoHob(VOID)
Create the HOB for hotkey status for 'Attempt USB First' feature.
Definition: PlatformInitAdvancedPostMem.c:902
CrashLogCollectDataFromPmcSSRAM
VOID CrashLogCollectDataFromPmcSSRAM(VOID)
Collect PCH CrashLog data from Pmc SSRAM and store in HOB .
Definition: PlatformInitAdvancedPostMem.c:1248
CpuCrashLogCollectDataFromTelemetrySRAM
VOID CpuCrashLogCollectDataFromTelemetrySRAM(VOID)
Collect CPU CrashLog data from Telemetry SRAM and store in HOB .
Definition: PlatformInitAdvancedPostMem.c:1442
DetectPmicVendorID
EFI_STATUS DetectPmicVendorID(OUT UINT8 *DataBuffer)
Detect Pmic Vendor ID.
GetVbtData
EFI_STATUS GetVbtData(OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
Definition: GopPolicyInitDxe.c:115
GetPeiPlatformLidStatus
EFI_STATUS GetPeiPlatformLidStatus(OUT LID_STATUS *CurrentLidStatus)
This function will return Lid Status in PEI phase.
Definition: PlatformInitAdvancedPostMem.c:420
FoxvilleLanGpioInit
VOID FoxvilleLanGpioInit(VOID)
Configure GPIO pads for Foxville I225 Lan based on the Setup Option.
Definition: PlatformInitAdvancedPostMem.c:1712
SetCacheMtrrAfterEndOfPei
EFI_STATUS SetCacheMtrrAfterEndOfPei(VOID)
Update MTRR setting in EndOfPei phase.
Definition: PlatformInitAdvancedPostMem.c:524
PeiGetFvInfoLib.h
Header file for PeiGetFvInfoLib.
MtrrLibApplyVariableMtrrs
RETURN_STATUS MtrrLibApplyVariableMtrrs(IN CONST MTRR_MEMORY_RANGE *VariableMtrr, IN UINT32 VariableMtrrCount, IN OUT MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCapacity, IN OUT UINTN *RangeCount)
Apply the variable MTRR settings to memory range array.
ReadEcRam
EFI_STATUS ReadEcRam(IN OUT UINT8 *DataBuffer)
Read data from EC RAM.
EcMiscLib.h
EC miscellaneous library functions.
PlatformPostCode.h
GetPmcValidRecord
BOOLEAN GetPmcValidRecord(IN UINT32 PmcCrashLogAddr)
Consider the PMC crash log data is valid or invalid.
Definition: PlatformInitAdvancedPostMem.c:1029
PlatformInitAdvancedEndOfPei
EFI_STATUS PlatformInitAdvancedEndOfPei(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task at the end of PEI.
Definition: PlatformInitAdvancedPostMem.c:863
GetCpuReArmSupport
BOOLEAN GetCpuReArmSupport(IN CPU_CRASHLOG_HEADER *CrashlogHeader)
Get re-arm supported or not.
Definition: PlatformInitAdvancedPostMem.c:1093
SetSlpS0Voltage
EFI_STATUS SetSlpS0Voltage(IN UINT8 EcDataV085ACNT)
Set SLP_S0 Voltage.
MtrrLibGetRawVariableRanges
UINT32 MtrrLibGetRawVariableRanges(IN MTRR_VARIABLE_SETTINGS *VariableSettings, IN UINTN VariableMtrrCount, IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT MTRR_MEMORY_RANGE *VariableMtrr)
Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
IsPremiumPmicPresent
BOOLEAN IsPremiumPmicPresent(VOID)
Checks if Premium PMIC present (VendorID == 1Fh)
Definition: PlatformInitAdvancedPostMem.c:610
CrashLog.h
GetPmcReArmSupport
BOOLEAN GetPmcReArmSupport(IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get re-arm supported or not.
Definition: PlatformInitAdvancedPostMem.c:1148
TouchPanelGpioInit
VOID TouchPanelGpioInit(VOID)
Configure GPIO pads for TouchPanels use.
Definition: PlatformInitAdvancedPostMem.c:1790
EcTcssLib.h
EC TCSS library functions.
ConfigurePciHostBridgePcds
VOID ConfigurePciHostBridgePcds(VOID)
Configure PciHostBridge related PCDs.
Definition: PlatformInitAdvancedPostMem.c:655
ConfigureGpio
VOID ConfigureGpio(IN GPIO_INIT_CONFIG *GpioDefinition, IN UINT16 GpioTableCount)
Configures GPIO.
Definition: PlatformInitAdvancedPostMem.c:1693
PlatformDebugStateChecksCallback
EFI_STATUS PlatformDebugStateChecksCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This callback function checks the debug state of the platform and sets the PcdFirmwareDebuggerInitial...
Definition: PlatformInitAdvancedPostMem.c:831
AttemptUsbFirst.h
GetPmcCrashLogDescriptTblAddr
UINT32 GetPmcCrashLogDescriptTblAddr(IN PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
Get address of PMC crash log record from descriptor table.
Definition: PlatformInitAdvancedPostMem.c:939
EOPSetMemoryAttributesInMtrrSettings
EFI_STATUS EOPSetMemoryAttributesInMtrrSettings(IN OUT MTRR_SETTINGS *MtrrSetting, IN MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount)
This function attempts to set the attributes into MTRR setting buffer.
Definition: PlatformInitAdvancedPostMem.c:163
SetupVariable.h
EcLib.h
EC library functions and definitions.
PlatformInitAdvancedPostMemEntryPoint
EFI_STATUS PlatformInitAdvancedPostMemEntryPoint(IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init PEI module entry point.
Definition: PlatformInitAdvancedPostMem.c:2234
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedPreMem.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei
Macros | Functions
PlatformInitAdvancedPreMem.c File Reference

Source code file for Platform Init Advanced Pre-Memory PEI module. More...

#include <PiPei.h>
#include <Ppi/Reset.h>
#include <Ppi/ReadOnlyVariable2.h>
#include <Guid/GlobalVariable.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/HobLib.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/PciSegmentLib.h>
#include <Library/PostCodeLib.h>
#include <Library/TimerLib.h>
#include <Library/EcTcssLib.h>
#include <Ppi/Wdt.h>
#include <Guid/TcoWdtHob.h>
#include <Library/PmcLib.h>
#include <Library/TcoLib.h>
#include <Library/PchCycleDecodingLib.h>
#include <PlatformNvRamHookLib.h>
#include <Library/BiosIdLib.h>
#include <Library/EcMiscLib.h>
#include <Library/PeiWdtAppLib.h>
#include <Register/SaRegsHostBridge.h>
#include <Register/PmcRegs.h>
#include <Register/PchRegs.h>
#include <Register/PchRegsSmbus.h>
#include <PchBdfAssignment.h>
#include <SetupVariable.h>
#include <FastBootFunctionEnabledHob.h>
#include <FastBootExceptionInfoHob.h>
#include <CustomOptionControl.h>
#include <Setup.h>
#include <PlatformPostCode.h>
#include <FirwmareConfigurations.h>
#include <Library/GpioLib.h>
#include <Library/PeiPlatformLib.h>
#include <PlatformBoardId.h>
#include <Library/PeiMeLib.h>
#include <Ppi/Smbus2.h>
#include <Library/SmbusLib.h>
#include <Library/SpiAccessLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Ppi/HeciPpi.h>
#include <PcieRegs.h>
#include <Register/HeciRegs.h>
#include <Register/PttPtpRegs.h>
#include <MeDisabledEventHob.h>
#include <Library/BootGuardLibVer1.h>
#include <CpuRegs.h>
Include dependency graph for PlatformInitAdvancedPreMem.c:

Go to the source code of this file.

Macros

#define | RESET_GENERATOR_PORT 0xCF9
Reset Generator I/O Port.
#define | VCCIN_AUX_SECONDARY_ADDRESS 0x26
VCCIN_AUX Secondary address.
#define | RICHTEK_VR_SECONDARY_ADDRESS 0x40
Richtek VR from I2C.

Functions

EFI_STATUS | PlatformInitPreMem (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced. More...
EFI_STATUS | MemoryDiscoveredPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Callback once there is main memory. More...
EFI_STATUS | SiPreMemPolicyPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after SaPolicy PPI to be installed. More...
EFI_STATUS | WdtAppPpiNotifyCallback (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after Wdt PPI to be installed. More...
EFI_STATUS | PlatformVoltageInit (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Platform Voltage Init - Programs platform voltages over SMBUS. More...
EFI_STATUS | PchReset (IN CONST EFI_PEI_SERVICES **PeiServices)
Provide hard reset PPI service. More...
EFI_STATUS | PeiExtendMeMeasuredBootNotifyCallback (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Callback function to install and update CSME Measurements HOB before DID in case of CSME in Disabled mode. More...
VOID | ConfigureGpio (IN GPIO_INIT_CONFIG *GpioDefinition, IN UINT16 GpioTableCount)
Configures GPIO. More...
VOID | USBCRetimerComplianceModePreMem (VOID)
Configure TypeC Retimer FP pin for USB compliance mode function.
BOOLEAN | IsOverclockingEnabled (VOID)
Check to see the overclocking is enabled or not. More...
BOOLEAN | IsFastBootEnabled (VOID)
Check fast boot is enabled or not. More...
EFI_STATUS | CreateFastBootHob (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Create Fast Boot HOB. More...
VOID | EarlyPlatformPchInit (VOID)
Early Platform PCH initialization. More...
VOID | SetTheStateToGoAfterG3 (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Set the state to go after G3. More...
VOID | PlatformPchInit (IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers. More...
VOID | EcInit (IN UINT8 PchLan, IN EFI_BOOT_MODE BootMode)
Configure EC for specific devices. More...
EFI_STATUS | PlatformSpecificInitPreMem (VOID)
Do platform specific programming. More...
EFI_STATUS | ProgramVcc1p8Override (IN UINT16 Voltage)
Programs the overrides for Vcc1p8 voltage which are controlled by UP1816 chip using SVID/PMBUS interface. More...
EFI_STATUS | ProgramVcc1p05Override (IN UINT16 Voltage)
Programs the overrides for Vcc1p05 voltage which are controlled by UP1816 chip using SVID/PMBUS interface. More...
EFI_STATUS | ProgramVccDd2Override (IN UINT16 Voltage)
Programs the overrides for VccDd2 voltage which are controlled by UP1816 chip using SVID/PMBUS interface. More...
EFI_STATUS | ProgramVccInAuxOverride (IN UINT16 Voltage)
Programs the overrides for VCCIN_AUX_CPU voltage which are controlled by PCA9555 (IO Port expander). More...
EFI_STATUS | ProgramRichtekVccIaOverride (IN UINT8 VidModeEn, IN UINT16 Voltage)
Programs the overrides for Richtek VccIa voltage which are controlled by Richtek VR (External VR). More...
EFI_STATUS | ProgramRichtekVccGtOverride (IN UINT8 VidModeEn, IN UINT16 Voltage)
Programs the overrides for Richtek VccGt voltage which are controlled by Richtek VR (External VR). More...
VOID | ProgramVoltageOverrides (IN CPU_SETUP *CpuSetup)
Check and apply the override knobs for external voltage rails based on board design. More...
VOID | BuildDebugConfigDataHob (IN DEBUG_CONFIG_DATA *DebugConfigData)
Build a HOB for debug configure data. More...
VOID | GpioInitEarlyWwanPreMem (VOID)
Basic GPIO configuration before memory is ready.
VOID | UpdateDebugConfigPcds (IN DEBUG_CONFIG_DATA *DebugConfigData)
Update PCDs for debug configure data. More...
EFI_STATUS | PlatformInitAdvancedPreMemEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init before memory PEI module entry point. More...

Detailed Description

Source code file for Platform Init Advanced Pre-Memory PEI module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedPreMem.c.

Function Documentation

◆ BuildDebugConfigDataHob()

VOID BuildDebugConfigDataHob ( IN DEBUG_CONFIG_DATA * DebugConfigData )

Build a HOB for debug configure data.

The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and PeiDxeSmmSerialPortParameterLib library instances.

Parameters
[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.

Definition at line 1686 of file PlatformInitAdvancedPreMem.c.

◆ ConfigureGpio()

VOID ConfigureGpio | ( | IN GPIO_INIT_CONFIG * | GpioDefinition,
 |  | IN UINT16 | GpioTableCount
 | ) |  |

Configures GPIO.

Parameters
[in] | GpioTable | Point to Platform Gpio table
[in] | GpioTableCount | Number of Gpio table entries

Definition at line 361 of file PlatformInitAdvancedPreMem.c.

◆ CreateFastBootHob()

EFI_STATUS CreateFastBootHob ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Create Fast Boot HOB.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
Return values
EFI_SUCCESS The function completes successfully
others

If Fast Boot is enabled, create the FAST_BOOT_FUNCTION_ENABLED_HOB for other modules' reference.

When RTC battery is drained (RTC power loss) or Secondary NvRam content is cleared (via jumper short), this bit will get set. This is the Fast Boot Exception Type 2.

Check the EFI Globally-Defined variable which is nonexistent right after updating BIOS, to determine if BIOS was just updated.

If overclocking is enabled, then BIOS shall switch back to Full Boot mode

Definition at line 624 of file PlatformInitAdvancedPreMem.c.

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◆ EarlyPlatformPchInit()

VOID EarlyPlatformPchInit ( VOID )

Early Platform PCH initialization.

Create HOB

Definition at line 746 of file PlatformInitAdvancedPreMem.c.

◆ EcInit()

VOID EcInit | ( | IN UINT8 | PchLan,
 |  | IN EFI_BOOT_MODE | BootMode
 | ) |  |

Configure EC for specific devices.

Parameters
[in] | PchLan | - The PchLan of PCH_SETUP variable.
[in] | BootMode | - The current boot mode.

Definition at line 888 of file PlatformInitAdvancedPreMem.c.

◆ IsFastBootEnabled()

BOOLEAN IsFastBootEnabled ( VOID )

Check fast boot is enabled or not.

Return values
FastBootEnabledStatus TRUE means fast boot is enabled FALSE means fast boot is disabled

Definition at line 577 of file PlatformInitAdvancedPreMem.c.

◆ IsOverclockingEnabled()

BOOLEAN IsOverclockingEnabled ( VOID )

Check to see the overclocking is enabled or not.

Return values
OverclockingEnabledStatus TRUE means overclocking is enabled FALSE means overclocking is disabled

Definition at line 531 of file PlatformInitAdvancedPreMem.c.

◆ MemoryDiscoveredPpiNotifyCallback()

EFI_STATUS MemoryDiscoveredPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Callback once there is main memory.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Definition at line 482 of file PlatformInitAdvancedPreMem.c.

◆ PchReset()

EFI_STATUS PchReset ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Provide hard reset PPI service.

To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).

Parameters
[in] PeiServices General purpose services available to every PEIM.
Return values
Not | return System reset occured.
EFI_DEVICE_ERROR | Device error, could not reset the system.

System reset occured, should never reach at this line.

Definition at line 724 of file PlatformInitAdvancedPreMem.c.

◆ PeiExtendMeMeasuredBootNotifyCallback()

EFI_STATUS PeiExtendMeMeasuredBootNotifyCallback | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Callback function to install and update CSME Measurements HOB before DID in case of CSME in Disabled mode.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | The typedef structure of the notification descriptor. Not used in this function.
[in] | Ppi | The typedef structure of the PPI descriptor. Not used in this function.
Return values
EFI_SUCCESS The function completed successfully

Definition at line 217 of file PlatformInitAdvancedPreMem.c.

◆ PlatformInitAdvancedPreMemEntryPoint()

EFI_STATUS PlatformInitAdvancedPreMemEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Platform Init before memory PEI module entry point.

Parameters
[in] | FileHandle | Not used.
[in] | PeiServices | General purpose services available to every PEIM.
Return values
EFI_SUCCESS | The function completes successfully
EFI_OUT_OF_RESOURCES | Insufficient resources to create database

Initialize Nvram to default when checksum computation is failed

Todo:
it should be moved to Si Pkg.

Do Early PCH init

Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced

After code reorangized, memorycallback will run because the PPI is already installed when code run to here, it is supposed that the InstallEfiMemory is done before.

Definition at line 2111 of file PlatformInitAdvancedPreMem.c.

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◆ PlatformInitPreMem()

EFI_STATUS PlatformInitPreMem | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced.

Parameters
[in] | PeiServices | Pointer to PEI Services Table.
[in] | NotifyDesc | Pointer to the descriptor for the Notification event that caused this function to execute.
[in] | Ppi | Pointer to the PPI data associated with this function.
Return values
EFI_SUCCESS The function completes successfully
others

EDK/FSP dispatch mode switches PcdAcpiS3Enable dynamically on gSiPkgTokenSpaceGuid.PcdS3Enable setting. FSP API mode has a default PcdAcpiS3Enable setting but does not turn the PCD on/off here.

Do basic PCH init

Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state)

Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.

BIOS should check the wake status before memory initialization to determine if ME has reset the system while the host was in a sleep state. If platform was not in a sleep state, BIOS should ensure a non-sleep exit path is taken by forcing an s5 exit.

Install Pre Memory PPIs

Definition at line 1838 of file PlatformInitAdvancedPreMem.c.

◆ PlatformPchInit()

VOID PlatformPchInit ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.

Enable the LPC I/O decoding for 0x6A0~0x6A7 as EC's extra I/O port, where 0x6A0 is the Data port and 0x6A4 is the Command/Status port.

Definition at line 860 of file PlatformInitAdvancedPreMem.c.

◆ PlatformSpecificInitPreMem()

EFI_STATUS PlatformSpecificInitPreMem ( VOID )

Do platform specific programming.

For example, EC init, Chipset programming

Return values
EFI_SUCCESS The function completed successfully.

Definition at line 915 of file PlatformInitAdvancedPreMem.c.

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◆ PlatformVoltageInit()

EFI_STATUS PlatformVoltageInit | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Platform Voltage Init - Programs platform voltages over SMBUS.

Run this function after Smbus2Ppi is installed.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

External Voltage rails control

  • Check if we need to override the voltages of the different VRMs using the SVID or PMBUS interfaces

Set SMBus PCI 0x64 = 0x0A0A0000

Definition at line 1563 of file PlatformInitAdvancedPreMem.c.

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◆ ProgramRichtekVccGtOverride()

EFI_STATUS ProgramRichtekVccGtOverride | ( | IN UINT8 | VidModeEn,
 |  | IN UINT16 | Voltage
 | ) |  |

Programs the overrides for Richtek VccGt voltage which are controlled by Richtek VR (External VR).

Parameters
[in] | VidModeEn | Enabled/ Disable VCC VID Mode
[in] | Voltage | Voltage target in mV
Return values
EFI_SUCCESS | The function completes successfully
EFI_STATUS | Fail status return from SmBusWriteDataWord ()

Definition at line 1382 of file PlatformInitAdvancedPreMem.c.

◆ ProgramRichtekVccIaOverride()

EFI_STATUS ProgramRichtekVccIaOverride | ( | IN UINT8 | VidModeEn,
 |  | IN UINT16 | Voltage
 | ) |  |

Programs the overrides for Richtek VccIa voltage which are controlled by Richtek VR (External VR).

Parameters
[in] | VidModeEn | Enabled/ Disable VCC VID Mode
[in] | Voltage | Voltage target in mV
Return values
EFI_SUCCESS | The function completes successfully
EFI_STATUS | Fail status return from SmBusWriteDataWord ()

Definition at line 1313 of file PlatformInitAdvancedPreMem.c.

◆ ProgramVcc1p05Override()

EFI_STATUS ProgramVcc1p05Override ( IN UINT16 Voltage )

Programs the overrides for Vcc1p05 voltage which are controlled by UP1816 chip using SVID/PMBUS interface.

Parameters
[in] Voltage Voltage target in mV
Return values
EFI_SUCCESS Successful to override voltage.

Definition at line 1135 of file PlatformInitAdvancedPreMem.c.

◆ ProgramVcc1p8Override()

EFI_STATUS ProgramVcc1p8Override ( IN UINT16 Voltage )

Programs the overrides for Vcc1p8 voltage which are controlled by UP1816 chip using SVID/PMBUS interface.

Parameters
[in] Voltage Voltage target in mV
Return values
EFI_SUCCESS Successful to override voltage.

Definition at line 1075 of file PlatformInitAdvancedPreMem.c.

◆ ProgramVccDd2Override()

EFI_STATUS ProgramVccDd2Override ( IN UINT16 Voltage )

Programs the overrides for VccDd2 voltage which are controlled by UP1816 chip using SVID/PMBUS interface.

Parameters
[in] Voltage Voltage target in mV
Return values
EFI_SUCCESS Successful to override voltage.

Definition at line 1195 of file PlatformInitAdvancedPreMem.c.

◆ ProgramVccInAuxOverride()

EFI_STATUS ProgramVccInAuxOverride ( IN UINT16 Voltage )

Programs the overrides for VCCIN_AUX_CPU voltage which are controlled by PCA9555 (IO Port expander).

Parameters
[in] Voltage Voltage target in mV
Return values
EFI_SUCCESS | The function completes successfully
EFI_STATUS | Fail status return from SmBusWriteDataWord ()

Definition at line 1256 of file PlatformInitAdvancedPreMem.c.

◆ ProgramVoltageOverrides()

VOID ProgramVoltageOverrides ( IN CPU_SETUP * CpuSetup )

Check and apply the override knobs for external voltage rails based on board design.

Parameters
[in] CpuSetup Setup variables under CPU Setup

Definition at line 1447 of file PlatformInitAdvancedPreMem.c.

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◆ SetTheStateToGoAfterG3()

VOID SetTheStateToGoAfterG3 ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI * VariableServices )

Set the state to go after G3.

Parameters
[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.

Definition at line 817 of file PlatformInitAdvancedPreMem.c.

◆ SiPreMemPolicyPpiNotifyCallback()

EFI_STATUS SiPreMemPolicyPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Run this function after SaPolicy PPI to be installed.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Platform specific programming. It may have Chipset, EC or some platform specific programming here.

Definition at line 1020 of file PlatformInitAdvancedPreMem.c.

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◆ UpdateDebugConfigPcds()

VOID UpdateDebugConfigPcds ( IN DEBUG_CONFIG_DATA * DebugConfigData )

Update PCDs for debug configure data.

The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and PeiDxeSmmSerialPortParameterLib library instances.

Parameters
[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.

Definition at line 1816 of file PlatformInitAdvancedPreMem.c.

◆ WdtAppPpiNotifyCallback()

EFI_STATUS WdtAppPpiNotifyCallback | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Run this function after Wdt PPI to be installed.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | Notify that this module published.
[in] | Ppi | PPI that was installed.
Return values
EFI_SUCCESS The function completed successfully.

Definition at line 1049 of file PlatformInitAdvancedPreMem.c.

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AlderLake Platform Sample Code: PlatformInitAdvancedPreMem.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei
PlatformInitAdvancedPreMem.c
Go to the documentation of this file.
1 /** @file
2 Source code file for Platform Init Advanced Pre-Memory PEI module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #include <PiPei.h>
37 #include <Ppi/Reset.h>
38 #include <Ppi/ReadOnlyVariable2.h>
39 #include <Guid/GlobalVariable.h>
40 #include <Library/BaseMemoryLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/HobLib.h>
43 #include <Library/IoLib.h>
44 #include <Library/PcdLib.h>
45 #include <Library/PciSegmentLib.h>
46 #include <Library/PostCodeLib.h>
47 #include <Library/TimerLib.h>
48 #include <Library/EcTcssLib.h>
49 #include <Ppi/Wdt.h>
50 #include <Guid/TcoWdtHob.h>
51 #include <Library/PmcLib.h>
52 #include <Library/TcoLib.h>
53 #include <Library/PchCycleDecodingLib.h>
54 #include <PlatformNvRamHookLib.h>
55 #include <Library/BiosIdLib.h>
56 #include <Library/EcMiscLib.h>
57 #include <Library/PeiWdtAppLib.h>
58 #if FixedPcdGetBool (PcdDTbtEnable) == 1
59 #include <Library/PeiDTbtPolicyLib.h>
60 #endif
61 #include <Register/SaRegsHostBridge.h>
62 #include <Register/PmcRegs.h>
63 #include <Register/PchRegs.h>
64 #include <Register/PchRegsSmbus.h>
65 #include <PchBdfAssignment.h>
66 #include <SetupVariable.h>
67 #include <FastBootFunctionEnabledHob.h>
68 #include <FastBootExceptionInfoHob.h>
69 #include <CustomOptionControl.h>
70 #include <Setup.h>
71 #include <PlatformPostCode.h>
72 #include <FirwmareConfigurations.h>
73 #include <Library/GpioLib.h>
74 #include <Library/PeiPlatformLib.h>
75 #include <PlatformBoardId.h>
76 #include <Library/PeiMeLib.h>
77 #include <Ppi/Smbus2.h>
78 #include <Library/SmbusLib.h>
79 #include <Library/SpiAccessLib.h>
80 #include <Library/MemoryAllocationLib.h>
81 #include <Ppi/HeciPpi.h>
82 #include <PcieRegs.h>
83 #include <Register/HeciRegs.h>
84 #include <Register/PttPtpRegs.h>
85 #include <MeDisabledEventHob.h>
86 #include <Library/BootGuardLibVer1.h>
87 #include <CpuRegs.h>
88
89
90 ///
91 /// Reset Generator I/O Port
92 ///
93 #define RESET_GENERATOR_PORT 0xCF9
94
95 ///
96 /// VCCIN_AUX Secondary address
97 ///
98 #define VCCIN_AUX_SECONDARY_ADDRESS 0x26
99
100 ///
101 /// Richtek VR from I2C
102 ///
103 #define RICHTEK_VR_SECONDARY_ADDRESS 0x40
104 #define RICHTEK_VFIX_LSB_CORE_MASK 0x00FF
105 #define RICHTEK_VFIX_MSB_CORE_MASK 0x0100
106
107 EFI_STATUS
108 EFIAPI
109 PlatformInitPreMem (
110 IN CONST EFI_PEI_SERVICES **PeiServices,
111 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
112 IN VOID *Ppi
113 );
114
115 EFI_STATUS
116 EFIAPI
117 MemoryDiscoveredPpiNotifyCallback (
118 IN CONST EFI_PEI_SERVICES **PeiServices,
119 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
120 IN VOID *Ppi
121 );
122
123 EFI_STATUS
124 EFIAPI
125 SiPreMemPolicyPpiNotifyCallback (
126 IN CONST EFI_PEI_SERVICES **PeiServices,
127 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
128 IN VOID *Ppi
129 );
130
131 EFI_STATUS
132 EFIAPI
133 WdtAppPpiNotifyCallback (
134 IN CONST EFI_PEI_SERVICES **PeiServices,
135 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
136 IN VOID *Ppi
137 );
138
139 EFI_STATUS
140 EFIAPI
141 PlatformVoltageInit (
142 IN CONST EFI_PEI_SERVICES **PeiServices,
143 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
144 IN VOID *Ppi
145 );
146
147 EFI_STATUS
148 EFIAPI
149 PchReset (
150 IN CONST EFI_PEI_SERVICES **PeiServices
151 );
152
153 static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
154 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
155 &gEfiPeiReadOnlyVariable2PpiGuid,
156 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMem
157 };
158
159 static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
160 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
161 &gEfiPeiMemoryDiscoveredPpiGuid,
162 (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
163 };
164
165 // @todo: FvCallBack.c needs to align with MinPlatform FV layout.
166 //static EFI_PEI_NOTIFY_DESCRIPTOR mGetFvNotifyList = {
167 // (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_DISPATCH | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
168 // &gEfiPeiVirtualBlockIoPpiGuid,
169 // (EFI_PEIM_NOTIFY_ENTRY_POINT) GetFvNotifyCallback
170 //};
171
172 static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyNotifyList = {
173 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
174 &gSiPreMemPolicyReadyPpiGuid,
175 (EFI_PEIM_NOTIFY_ENTRY_POINT) SiPreMemPolicyPpiNotifyCallback
176 };
177
178 static EFI_PEI_NOTIFY_DESCRIPTOR mWdtPpiNotifyList = {
179 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
180 &gWdtPpiGuid,
181 (EFI_PEIM_NOTIFY_ENTRY_POINT) WdtAppPpiNotifyCallback
182 };
183
184 static EFI_PEI_NOTIFY_DESCRIPTOR mPlatformVoltageInitOnMemoryNotifyList = {
185 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
186 &gEfiPeiMasterBootModePpiGuid,
187 (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformVoltageInit
188 };
189
190 static EFI_PEI_RESET_PPI mResetPpi = {
191 PchReset
192 };
193
194 static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
195 {
196 (EFI_PEI_PPI_DESCRIPTOR_PPI| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
197 &gEfiPeiResetPpiGuid,
198 &mResetPpi
199 }
200 };
201
202
203 /**
204 Callback function to install and update CSME Measurements HOB before DID in case of CSME in Disabled mode.
205
206 @param[in] PeiServices General purpose services available to every PEIM.
207 @param[in] NotifyDescriptor The typedef structure of the notification
208 descriptor. Not used in this function.
209 @param[in] Ppi The typedef structure of the PPI descriptor.
210 Not used in this function.
211
212 @retval EFI_SUCCESS The function completed successfully
213
214 **/
215 EFI_STATUS
216 EFIAPI
217 PeiExtendMeMeasuredBootNotifyCallback (
218 IN EFI_PEI_SERVICES **PeiServices,
219 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
220 IN VOID *Ppi
221 )
222 {
223 EFI_STATUS Status;
224 UINT32 RemainingBufSize;
225 UINT32 ReceivedLogSize;
226 UINT8 LogEntryIndex;
227 UINT8 RemainingEntries;
228 UINT8 *TempEvent;
229 UINT8 Events [MAX_EVENTLOG_SIZE];
230 UINT32 EventLogSize;
231 UINT64 HeciBaseAddress;
232 UINT32 *HerValue;
233 UINT8 HerMaxRegCount;
234 UINTN HeciMemBar;
235 UINT32 HerOffset;
236 UINT8 Index;
237 HECI_FWS_REGISTER MeFwsts1;
238 HECI_GS_SHDW_REGISTER MeFwsts2;
239 ME_DISABLED_EVENT_HOB *MeDisabledHob;
240
241 Status = EFI_SUCCESS;
242 // Get HECI Device MMIO address
243 HeciBaseAddress = PCI_SEGMENT_LIB_ADDRESS (ME_SEGMENT, ME_BUS, ME_DEVICE_NUMBER, HECI_FUNCTION_NUMBER, 0);
244 if (PciSegmentRead16 (HeciBaseAddress + PCI_DEVICE_ID_OFFSET) == 0xFFFF) {
245 DEBUG ((DEBUG_WARN, "HECI device is disabled\n"));
246 return EFI_UNSUPPORTED;
247 }
248
249 // Read ME status and check for CSME operation mode
250 MeFwsts1.ul = PciSegmentRead32 (HeciBaseAddress + R_ME_HFS);
251 MeFwsts2.ul = PciSegmentRead32 (HeciBaseAddress + R_ME_HFS_2);
252
253 // Check whether CSME is in Disabled mode
254 if ((MeFwsts1.r.MeOperationMode != ME_OPERATION_MODE_NORMAL) || (MeFwsts2.r.CseToDisabled == 1)) {
255 EventLogSize = 0;
256 RemainingBufSize = MAX_EVENTLOG_SIZE;
257 ReceivedLogSize = 0;
258 LogEntryIndex = 0;
259 TempEvent = Events;
260
261 // Create MeDisabledHob
262 Status = PeiServicesCreateHob (
263 EFI_HOB_TYPE_GUID_EXTENSION,
264 sizeof (ME_DISABLED_EVENT_HOB),
265 (VOID **) &MeDisabledHob
266 );
267 if (EFI_ERROR (Status)) {
268 DEBUG ((DEBUG_ERROR, "MeExtMeasurement: Failed to create MeDisabledHob\n"));
269 ASSERT_EFI_ERROR (Status);
270 return Status;
271 }
272 DEBUG ((DEBUG_INFO, "MeExtMeasurement: MeDisabledHob Created\n"));
273
274 MeDisabledHob->EfiHobGuidType.Name = gMeDisabledEventHobGuid;
275
276 // Read HER Status register value
277 MeDisabledHob->Hers = PciSegmentRead32 (HeciBaseAddress + R_ME_HERS);
278
279 HeciMemBar = PciSegmentRead32 (HeciBaseAddress + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFFFF0;
280 if ((PciSegmentRead32 (HeciBaseAddress + PCI_BASE_ADDRESSREG_OFFSET) & B_PCI_BAR_MEMORY_TYPE_MASK) == B_PCI_BAR_MEMORY_TYPE_64) {
281 HeciMemBar += (UINT64) PciSegmentRead32 (HeciBaseAddress + (PCI_BASE_ADDRESSREG_OFFSET + 4)) << 32;
282 }
283
284 if (HeciMemBar == 0) {
285 DEBUG ((DEBUG_WARN, "MMIO Bar for HECI device isn't programmed\n"));
286 return EFI_UNSUPPORTED;
287 }
288
289 // Enable HECI MSE
290 PciSegmentOr8 (HeciBaseAddress + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
291
292 MeDisabledHob->Enh_Hers= MmioRead32 (HeciMemBar + R_HERS);
293
294 ZeroMem (&MeDisabledHob->Her, sizeof (MeDisabledHob->Her));
295 HerMaxRegCount = HER_REG_COUNT_SHA384;
296 HerOffset = (UINT32) R_ME_HER1;
297 HerOffset += R_HER_BASE;
298 HerValue = MeDisabledHob->Her;
299 // Read HER data from MMIO space
300 for (Index = 0; Index < HerMaxRegCount; Index++) {
301 *HerValue = MmioRead32 (HeciMemBar + (HerOffset + (Index * sizeof (UINT32))));
302 HerValue++;
303 }
304
305 MeDisabledHob->LogUnavailable = FALSE;
306 TempEvent = MeDisabledHob->Events;
307
308 do {
309 RemainingEntries = 0;
310 Status = PeiHeciGetErLog (
311 TempEvent,
312 RemainingBufSize,
313 &ReceivedLogSize,
314 &LogEntryIndex,
315 &RemainingEntries
316 );
317 if (EFI_ERROR (Status)) {
318 DEBUG((DEBUG_INFO, "Failed to get ER Log data\n"));
319 MeDisabledHob->LogUnavailable = TRUE;
320 } else {
321 EventLogSize += ReceivedLogSize;
322 if (RemainingEntries) {
323 if (EventLogSize >= MAX_EVENTLOG_SIZE) {
324 DEBUG((DEBUG_INFO, "Event Log is exceeding the Maximum allocated buffer\n"));
325 return EFI_BUFFER_TOO_SMALL;
326 }
327 TempEvent += ReceivedLogSize;
328 RemainingBufSize = MAX_EVENTLOG_SIZE - EventLogSize;
329 }
330 }
331 } while (RemainingEntries != 0);
332
333 MeDisabledHob->EventLogSize = EventLogSize;
334 }
335
336 return Status;
337 }
338
339 static EFI_PEI_NOTIFY_DESCRIPTOR mPeiExtendMeMeasuredBootNotifyList = {
340 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
341 &gMeBeforeDidSentPpiGuid,
342 (EFI_PEIM_NOTIFY_ENTRY_POINT) PeiExtendMeMeasuredBootNotifyCallback
343 };
344
345
346
347 EFI_STATUS
348 EFIAPI
349 PeiGuidForward (
350 VOID
351 );
352
353 /**
354 Configures GPIO
355
356 @param[in] GpioTable Point to Platform Gpio table
357 @param[in] GpioTableCount Number of Gpio table entries
358
359 **/
360 VOID
361 ConfigureGpio (
362 IN GPIO_INIT_CONFIG *GpioDefinition,
363 IN UINT16 GpioTableCount
364 )
365 {
366 DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
367
368 GpioConfigurePads (GpioTableCount, GpioDefinition);
369
370 DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
371 }
372
373 /**
374 Configure TypeC Retimer FP pin for USB compliance mode function.
375 **/
376 VOID
377 USBCRetimerComplianceModePreMem (
378 VOID
379 )
380 {
381 GPIO_CONFIG GpioConfig;
382 GPIO_PAD GpioPad;
383 EFI_STATUS Status;
384 SETUP_DATA SetupData;
385 UINTN VarSize;
386 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
387 UINT8 EcDataBuffer;
388
389 DEBUG ((DEBUG_INFO, "USBCRetimerComplianceModePreMem: Start\n"));
390 EcDataBuffer = 0;
391
392 //
393 // Locate Setup variables
394 //
395 Status = PeiServicesLocatePpi (
396 &gEfiPeiReadOnlyVariable2PpiGuid,
397 0,
398 NULL,
399 (VOID **) &VariableServices
400 );
401 if (EFI_ERROR(Status)) {
402 DEBUG((DEBUG_ERROR, "PeiServicesLocatePpi failed\n"));
403 return;
404 }
405
406 VarSize = sizeof (SETUP_DATA);
407 Status = VariableServices->GetVariable (
408 VariableServices,
409 L"Setup",
410 &gSetupVariableGuid,
411 NULL,
412 &VarSize,
413 &SetupData
414 );
415 if (EFI_ERROR(Status)) {
416 DEBUG((DEBUG_ERROR, "GetVariable (SetupData) failed\n"));
417 return;
418 }
419 GpioPad = PcdGet32 (PcdBoardRetimerForcePwrGpio);
420 DEBUG((DEBUG_INFO, "Retimer Force Power Gpio is : 0x%08x\n", GpioPad));
421
422 if (GpioPad != 0) {
423 GpioGetPadConfig (GpioPad, &GpioConfig);
424 GpioConfig.PadMode = GpioPadModeGpio;
425 GpioConfig.HostSoftPadOwn = GpioHostOwnAcpi;
426 GpioConfig.Direction = GpioDirOut;
427 GpioConfig.InterruptConfig = GpioIntDis;
428 GpioConfig.PowerConfig = GpioPlatformReset;
429 GpioConfig.ElectricalConfig = GpioTermNone;
430 GpioConfig.LockConfig = GpioOutputStateUnlock;
431
432 if (SetupData.TypecRetimerTxComplianceModeEn != 0) {
433 if (SetupData.TypecRetimerPD0 == 1) { //PD 0 Retimer enable
434 EcDataBuffer |= BIT0;
435 } else {
436 EcDataBuffer &= ~BIT0;
437 }
438
439 if (SetupData.TypecRetimerPD1 == 1) { //PD 1 Retimer enable
440 EcDataBuffer |= BIT1;
441 } else {
442 EcDataBuffer &= ~BIT1;
443 }
444
445 if (SetupData.TypecRetimerPD2 == 1) { //PD 2 Retimer enable
446 EcDataBuffer |= BIT2;
447 } else {
448 EcDataBuffer &= ~BIT2;
449 }
450
451 if (SetupData.TypecRetimerPD3 == 1) { //PD 3 Retimer enable
452 EcDataBuffer |= BIT3;
453 } else {
454 EcDataBuffer &= ~BIT3;
455 }
456
457 GpioConfig.OutputState = GpioOutHigh;
458 GpioSetPadConfig (GpioPad, &GpioConfig);
459 UsbcRetimerCompliancePDMessage (&EcDataBuffer);
460 DEBUG((DEBUG_INFO, "Compliance Mode: Enable\nAssert Retimer FP Pin\n"));
461 } else {
462 EcDataBuffer = 0;
463 DEBUG((DEBUG_INFO, "TCompliance Mode: Disable\nNo Action\n"));
464 }
465
466 }
467
468 DEBUG ((DEBUG_INFO, "USBCRetimerComplianceModePreMem: End\n"));
469 }
470
471 /**
472 Callback once there is main memory
473
474 @param[in] PeiServices General purpose services available to every PEIM.
475 @param[in] NotifyDescriptor Notify that this module published.
476 @param[in] Ppi PPI that was installed.
477
478 @retval EFI_SUCCESS The function completed successfully.
479 **/
480 EFI_STATUS
481 EFIAPI
482 MemoryDiscoveredPpiNotifyCallback (
483 IN CONST EFI_PEI_SERVICES **PeiServices,
484 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
485 IN VOID *Ppi
486 )
487 {
488 EFI_STATUS Status;
489 DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
490 EFI_PEI_HOB_POINTERS Hob;
491 DEBUG_CONFIG_DATA DebugConfigData;
492 UINTN DebugConfigDataSize;
493 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VarPpi;
494
495 Status = EFI_SUCCESS;
496
497 Hob.Guid = GetFirstGuidHob (&gDebugConfigHobGuid);
498 if (Hob.Guid != NULL) {
499 Status = PeiServicesLocatePpi (
500 &gEfiPeiReadOnlyVariable2PpiGuid,
501 0,
502 NULL,
503 (VOID **) &VarPpi
504 );
505 ASSERT_EFI_ERROR (Status);
506 DebugConfigDataSize = sizeof (DEBUG_CONFIG_DATA);
507 Status = VarPpi->GetVariable (
508 VarPpi,
509 L"DebugConfigData",
510 &gDebugConfigVariableGuid,
511 NULL,
512 &DebugConfigDataSize,
513 &DebugConfigData
514 );
515 ASSERT_EFI_ERROR (Status);
516 DebugConfigDataHob = (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA (Hob.Guid);
517 DebugConfigDataHob->RamDebugInterface = (DebugConfigData.RamDebugInterface == 1 && FeaturePcdGet (PcdRamDebugEnable)) ? 1 : 0;
518 }
519
520 return Status;
521 }
522
523 /**
524 Check to see the overclocking is enabled or not
525
526 @retval OverclockingEnabledStatus TRUE means overclocking is enabled
527 FALSE means overclocking is disabled
528 **/
529 BOOLEAN
530 EFIAPI
531 IsOverclockingEnabled (
532 VOID
533 )
534 {
535 EFI_STATUS Status;
536 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
537 UINTN VarSize;
538 CPU_SETUP CpuSetup;
539 BOOLEAN OverclockingEnabledStatus;
540
541 OverclockingEnabledStatus = FALSE;
542
543 Status = PeiServicesLocatePpi (
544 &gEfiPeiReadOnlyVariable2PpiGuid,
545 0,
546 NULL,
547 (VOID **) &PeiReadOnlyVarPpi
548 );
549 if (Status == EFI_SUCCESS) {
550 VarSize = sizeof (CPU_SETUP);
551 Status = PeiReadOnlyVarPpi->GetVariable (
552 PeiReadOnlyVarPpi,
553 L"CpuSetup",
554 &gCpuSetupVariableGuid,
555 NULL,
556 &VarSize,
557 &CpuSetup
558 );
559 if (Status == EFI_SUCCESS) {
560 if (CpuSetup.OverclockingSupport != 0) {
561 OverclockingEnabledStatus = TRUE;
562 }
563 }
564 }
565
566 return OverclockingEnabledStatus;
567 }
568
569 /**
570 Check fast boot is enabled or not
571
572 @retval FastBootEnabledStatus TRUE means fast boot is enabled
573 FALSE means fast boot is disabled
574 **/
575 BOOLEAN
576 EFIAPI
577 IsFastBootEnabled (
578 VOID
579 )
580 {
581 EFI_STATUS Status;
582 EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiReadOnlyVarPpi;
583 UINTN VarSize;
584 SETUP_DATA SystemConfiguration;
585 BOOLEAN FastBootEnabledStatus;
586
587 FastBootEnabledStatus = FALSE;
588 Status = PeiServicesLocatePpi (
589 &gEfiPeiReadOnlyVariable2PpiGuid,
590 0,
591 NULL,
592 (VOID **) &PeiReadOnlyVarPpi
593 );
594 if (Status == EFI_SUCCESS) {
595 VarSize = sizeof (SETUP_DATA);
596 Status = PeiReadOnlyVarPpi->GetVariable (
597 PeiReadOnlyVarPpi,
598 L"Setup",
599 &gSetupVariableGuid,
600 NULL,
601 &VarSize,
602 &SystemConfiguration
603 );
604 if (Status == EFI_SUCCESS) {
605 if (SystemConfiguration.FastBoot != 0) {
606 FastBootEnabledStatus = TRUE;
607 }
608 }
609 }
610
611 return FastBootEnabledStatus;
612 }
613
614 /**
615 Create Fast Boot HOB
616
617 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
618
619 @retval EFI_SUCCESS The function completes successfully
620 @retval others
621 **/
622 EFI_STATUS
623 EFIAPI
624 CreateFastBootHob (
625 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
626 )
627 {
628 EFI_STATUS Status;
629 UINTN VarSize;
630 FAST_BOOT_FUNCTION_ENABLED_HOB *FastBootFunctionEnabledHob;
631 FAST_BOOT_EXCEPTION_INFO_HOB *FastBootExceptionInfoHob;
632
633 if (IsFastBootEnabled ()) {
634 ///
635 /// If Fast Boot is enabled, create the FAST_BOOT_FUNCTION_ENABLED_HOB for other modules' reference.
636 ///
637 Status = PeiServicesCreateHob (
638 EFI_HOB_TYPE_GUID_EXTENSION,
639 sizeof (FAST_BOOT_FUNCTION_ENABLED_HOB),
640 (VOID **) &FastBootFunctionEnabledHob
641 );
642 if (!EFI_ERROR (Status)) {
643 FastBootFunctionEnabledHob->Header.Name = gFastBootFunctionEnabledHobGuid;
644 FastBootFunctionEnabledHob->FastBootEnabled = TRUE;
645 } else {
646 return Status;
647 }
648 ///
649 /// When RTC battery is drained (RTC power loss) or Secondary NvRam content is cleared (via jumper short), this bit will get set.
650 /// This is the Fast Boot Exception Type 2.
651 ///
652 if (!PmcIsRtcBatteryGood ()) {
653 Status = PeiServicesCreateHob (
654 EFI_HOB_TYPE_GUID_EXTENSION,
655 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
656 (VOID **) &FastBootExceptionInfoHob
657 );
658 if (!EFI_ERROR (Status)) {
659 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
660 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
661 FastBootExceptionInfoHob->FbExceptionCategory = ContentLost;
662 } else {
663 return Status;
664 }
665 }
666 ///
667 /// Check the EFI Globally-Defined variable which is nonexistent right after updating BIOS, to determine if BIOS was just updated.
668 ///
669 Status = VariableServices->GetVariable (
670 VariableServices,
671 L"ConOut",
672 &gEfiGlobalVariableGuid,
673 NULL,
674 &VarSize,
675 NULL
676 );
677 if (Status == EFI_NOT_FOUND) {
678 Status = PeiServicesCreateHob (
679 EFI_HOB_TYPE_GUID_EXTENSION,
680 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
681 (VOID **) &FastBootExceptionInfoHob
682 );
683 if (!EFI_ERROR (Status)) {
684 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
685 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
686 FastBootExceptionInfoHob->FbExceptionCategory = FirmwareUpdate;
687 } else {
688 return Status;
689 }
690 }
691 ///
692 /// If overclocking is enabled, then BIOS shall switch back to Full Boot mode
693 ///
694 if (IsOverclockingEnabled ()) {
695 Status = PeiServicesCreateHob (
696 EFI_HOB_TYPE_GUID_EXTENSION,
697 sizeof (FAST_BOOT_EXCEPTION_INFO_HOB),
698 (VOID **) &FastBootExceptionInfoHob
699 );
700 if (!EFI_ERROR (Status)) {
701 FastBootExceptionInfoHob->Header.Name = gFastBootExceptionInfoHobGuid;
702 FastBootExceptionInfoHob->FbExceptionType = ExceptionType2;
703 FastBootExceptionInfoHob->FbExceptionCategory = SpecialBoot;
704 } else {
705 return Status;
706 }
707 }
708 }
709 return EFI_SUCCESS;
710 }
711
712 //@todo it should be performed in Si Pkg.
713 /**
714 Provide hard reset PPI service.
715 To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
716
717 @param[in] PeiServices General purpose services available to every PEIM.
718
719 @retval Not return System reset occured.
720 @retval EFI_DEVICE_ERROR Device error, could not reset the system.
721 **/
722 EFI_STATUS
723 EFIAPI
724 PchReset (
725 IN CONST EFI_PEI_SERVICES **PeiServices
726 )
727 {
728 DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
729 IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
730
731 CpuDeadLoop ();
732
733 ///
734 /// System reset occured, should never reach at this line.
735 ///
736 ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
737
738 return EFI_DEVICE_ERROR;
739 }
740
741 /**
742 Early Platform PCH initialization
743 **/
744 VOID
745 EFIAPI
746 EarlyPlatformPchInit (
747 VOID
748 )
749 {
750 UINT8 TcoRebootHappened;
751 TCO_WDT_HOB *TcoWdtHobPtr;
752 EFI_STATUS Status;
753
754 if (TcoSecondToHappened ()) {
755 TcoRebootHappened = 1;
756 DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
757 } else {
758 TcoRebootHappened = 0;
759 }
760
761 ///
762 /// Create HOB
763 ///
764 Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (TCO_WDT_HOB), (VOID **) &TcoWdtHobPtr);
765 if (!EFI_ERROR (Status)) {
766 TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
767 TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
768 }
769
770 TcoClearSecondToStatus ();
771 }
772
773 /**
774 Set the state to go after G3
775
776 @dot
777 digraph G {
778 subgraph cluster_c0 {
779 node [shape = box];
780 b1[label="EcForceResetAfterAcRemoval ()" fontsize=12 style=filled color=lightblue];
781 b2[label="Force S5" fontsize=12 style=filled color=lightblue];
782 b3[label="Force S0" fontsize=12 style=filled color=lightblue];
783
784 node [shape = ellipse];
785 e1[label="Start" fontsize=12 style=filled color=lightblue];
786 e2[label="End" fontsize=12 style=filled color=lightblue];
787
788 node [shape = diamond,style=filled,color=lightblue];
789 d1[label="GetVariable\nFroceResetAfterAcRemoval" fontsize=12];
790 d2[label="EcPresent" fontsize=12];
791 d3[label="ForceResetAfterAcRemoval" fontsize=12];
792 d4[label="GetVariable\nStateAfterG3" fontsize=12];
793 d5[label="StateAfterG3" fontsize=12];
794
795 label = "SetTheStateToGoAfterG3 Flow"; fontsize=15; fontcolor=black; color=lightblue;
796 e1 -> d1
797 d1 -> d2 [label="Success" fontsize=9]
798 d1 -> d4 [label="Fail" fontsize=9]
799 d2 -> b1 [label="Yes" fontsize=9]
800 b1 -> d3
801 d2 -> d3 [label="No" fontsize=9]
802 d3 -> b3 [label="Yes" fontsize=9]
803 d3 -> d4 [label="No" fontsize=9]
804 d4 -> d5 [label="Success" fontsize=9]
805 d4 -> b3 [label="Fail" fontsize=9]
806 d5 -> b2 [label="Set" fontsize=9]
807 d5 -> b3 [label="Clear" fontsize=9]
808 b3 -> e2
809 }
810 }
811 @enddot
812
813 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
814 **/
815 VOID
816 EFIAPI
817 SetTheStateToGoAfterG3 (
818 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
819 )
820 {
821 EFI_STATUS Status;
822 UINTN VariableSize;
823 UINT8 ForceResetAfterAcRemovalVar;
824 UINT8 StateAfterG3;
825 PCH_SETUP PchSetup;
826
827 ForceResetAfterAcRemovalVar = 0;
828 StateAfterG3 = 0;
829
830
831 VariableSize = sizeof (PCH_SETUP);
832 Status = VariableServices->GetVariable (
833 VariableServices,
834 L"PchSetup",
835 &gPchSetupVariableGuid,
836 NULL,
837 &VariableSize,
838 &PchSetup
839 );
840 if (!EFI_ERROR(Status)) {
841 StateAfterG3 = PchSetup.StateAfterG3;
842 }
843
844 if ((StateAfterG3 == 1) && (ForceResetAfterAcRemovalVar == 0)) {
845 PmcSetPlatformStateAfterPowerFailure (1); // AfterG3 = S5
846 } else {
847 PmcSetPlatformStateAfterPowerFailure (0); // AfterG3 = S0
848 }
849 }
850
851
852 // @todo: It should be moved Policy Init.
853 /**
854 Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers
855
856 @param[in] VariableServices A pointer to this instance of the EFI_PEI_READ_ONLY_VARIABLE2_PPI.
857 **/
858 VOID
859 EFIAPI
860 PlatformPchInit (
861 IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices
862 )
863 {
864
865 ///
866 /// Enable the LPC I/O decoding for 0x6A0~0x6A7 as EC's extra I/O port, where 0x6A0 is the Data port
867 /// and 0x6A4 is the Command/Status port.
868 ///
869 if (PcdGetBool (PcdEcPresent)) {
870 PchLpcGenIoRangeSet (PcdGet16 (PcdEcExtraIoBase), 0x10); //PTLMOD+
871 }
872 #if FixedPcdGetBool(PcdNct677FPresent) == 1
873 else {
874 /// Added Nuvoton HW monitor IO address.
875 PchLpcGenIoRangeSet (PcdGet16 (PcdNct6776fHwMonBase), 0x10);
876 }
877 #endif
878
879 }
880
881 /**
882 Configure EC for specific devices
883
884 @param[in] PchLan - The PchLan of PCH_SETUP variable.
885 @param[in] BootMode - The current boot mode.
886 **/
887 VOID
888 EcInit (
889 IN UINT8 PchLan,
890 IN EFI_BOOT_MODE BootMode
891 )
892 {
893 EFI_STATUS Status;
894
895 Status = EFI_SUCCESS;
896 if (PchLan != PEI_DEVICE_DISABLED) {
897 Status = EnableLanPower (TRUE);
898 } else {
899 Status = EnableLanPower (FALSE);
900 }
901 ASSERT_EFI_ERROR (Status);
902
903 //
904 // Clear 10sec PB Override mode in EC so that Power button is always available during POST.
905 //
906 ClearTenSecPwrButtonMode ();
907 }
908
909 /**
910 Do platform specific programming. For example, EC init, Chipset programming
911
912 @retval EFI_SUCCESS The function completed successfully.
913 **/
914 EFI_STATUS
915 PlatformSpecificInitPreMem (
916 VOID
917 )
918 {
919 EFI_STATUS Status;
920 EFI_BOOT_MODE BootMode;
921 SA_SETUP SaSetup;
922 PCH_SETUP PchSetup;
923 SETUP_DATA SystemConfiguration;
924 UINTN VarSize;
925 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
926
927 Status = PeiServicesGetBootMode (&BootMode);
928 ASSERT_EFI_ERROR (Status);
929
930 //
931 // Locate Setup variables
932 //
933 Status = PeiServicesLocatePpi (
934 &gEfiPeiReadOnlyVariable2PpiGuid,
935 0,
936 NULL,
937 (VOID **) &VariableServices
938 );
939 ASSERT_EFI_ERROR (Status);
940
941 VarSize = sizeof (PCH_SETUP);
942 Status = VariableServices->GetVariable (
943 VariableServices,
944 L"PchSetup",
945 &gPchSetupVariableGuid,
946 NULL,
947 &VarSize,
948 &PchSetup
949 );
950
951 if (!EFI_ERROR(Status) && PcdGetBool (PcdEcPresent)) {
952 EcInit (PchSetup.PchLan, BootMode);
953 }
954
955 VarSize = sizeof (SETUP_DATA);
956 Status = VariableServices->GetVariable (
957 VariableServices,
958 L"Setup",
959 &gSetupVariableGuid,
960 NULL,
961 &VarSize,
962 &SystemConfiguration
963 );
964 if (!EFI_ERROR(Status)) {
965 //
966 // Selecting charging method
967 //
968 if (PcdGetBool (PcdEcPresent)) {
969 if (SystemConfiguration.EcChargingMethod == 1) {
970 //
971 // Fast charging
972 //
973 DfctFastChargingMode (TRUE);
974 } else {
975 //
976 // Normal charging
977 //
978 DfctFastChargingMode (FALSE);
979 }
980 }
981
982 VarSize = sizeof (SA_SETUP);
983 Status = VariableServices->GetVariable (
984 VariableServices,
985 L"SaSetup",
986 &gSaSetupVariableGuid,
987 NULL,
988 &VarSize,
989 &SaSetup
990 );
991 if (!EFI_ERROR(Status)) {
992 if (PcdGet8 (PcdPlatformType) == TypeUltUlx) {
993 // Force Valid Sensor Settings depending on the Option selected in Sensor Hub Type Setup Option.
994 if(SystemConfiguration.SensorHubType == 0) {
995 SystemConfiguration.UsbSensorHub = 0;
996 } else if (SystemConfiguration.SensorHubType == 1) {
997 SaSetup.AlsEnable = 0;
998 SystemConfiguration.UsbSensorHub = 0;
999 } else {
1000 SaSetup.AlsEnable = 0;
1001 SystemConfiguration.UsbSensorHub = 1;
1002 }
1003 }
1004 }
1005 }
1006 return EFI_SUCCESS;
1007 }
1008
1009 /**
1010 Run this function after SaPolicy PPI to be installed.
1011
1012 @param[in] PeiServices General purpose services available to every PEIM.
1013 @param[in] NotifyDescriptor Notify that this module published.
1014 @param[in] Ppi PPI that was installed.
1015
1016 @retval EFI_SUCCESS The function completed successfully.
1017 **/
1018 EFI_STATUS
1019 EFIAPI
1020 SiPreMemPolicyPpiNotifyCallback (
1021 IN CONST EFI_PEI_SERVICES **PeiServices,
1022 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1023 IN VOID *Ppi
1024 )
1025 {
1026 EFI_STATUS Status;
1027
1028 ///
1029 /// Platform specific programming. It may have Chipset, EC or some platform specific
1030 /// programming here.
1031 ///
1032 Status = PlatformSpecificInitPreMem ();
1033 ASSERT_EFI_ERROR (Status);
1034
1035 return Status;
1036 }
1037
1038 /**
1039 Run this function after Wdt PPI to be installed.
1040
1041 @param[in] PeiServices General purpose services available to every PEIM.
1042 @param[in] NotifyDescriptor Notify that this module published.
1043 @param[in] Ppi PPI that was installed.
1044
1045 @retval EFI_SUCCESS The function completed successfully.
1046 **/
1047 EFI_STATUS
1048 EFIAPI
1049 WdtAppPpiNotifyCallback (
1050 IN CONST EFI_PEI_SERVICES **PeiServices,
1051 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1052 IN VOID *Ppi
1053 )
1054 {
1055 EFI_STATUS Status;
1056 WDT_PPI *WdtPei;
1057
1058 WdtPei = (WDT_PPI *) Ppi;
1059
1060 Status = PeiWdtApp (WdtPei);
1061 ASSERT_EFI_ERROR (Status);
1062
1063 return Status;
1064 }
1065
1066 /**
1067 Programs the overrides for Vcc1p8 voltage which are controlled by UP1816
1068 chip using SVID/PMBUS interface.
1069
1070 @param[in] Voltage Voltage target in mV
1071
1072 @retval EFI_SUCCESS Successful to override voltage.
1073 **/
1074 EFI_STATUS
1075 ProgramVcc1p8Override (
1076 IN UINT16 Voltage
1077 )
1078 {
1079 EFI_STATUS Status;
1080 EFI_SMBUS_DEVICE_ADDRESS SlaveAddr;
1081 UINT8 DeviceCommand;
1082 UINT8 Data;
1083 UINT8 Prefix;
1084 UINT8 CurrentData;
1085
1086 //
1087 // Target address 0x2A
1088 //
1089 SlaveAddr.SmbusDeviceAddress = (0x2A >> 1);
1090
1091 //
1092 // Device Command and set Byte write
1093 //
1094 DeviceCommand = 0x2; // VREF2
1095
1096 //
1097 // Data = 0 is 1800 mV
1098 //
1099 Prefix = 0;
1100 if (Voltage >= 1800) {
1101 Data = (UINT8) (((Voltage - 1800) / 10) | (Prefix << 7));
1102 } else {
1103 Prefix = 1;
1104 Data = (UINT8) (((1800 - Voltage) / 10) | (Prefix << 7));
1105 }
1106
1107 CurrentData = SmBusReadDataByte (
1108 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1109 &Status
1110 );
1111
1112 DEBUG ((DEBUG_INFO, "SMBUS transaction request Vcc1p8: Addr=0x%08X Command=0x%08X CurrentData=0x%08X Data=0x%08X\n",
1113 SlaveAddr.SmbusDeviceAddress, DeviceCommand, CurrentData, Data));
1114
1115 SmBusWriteDataByte (
1116 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1117 Data,
1118 &Status
1119 );
1120
1121 DEBUG ((DEBUG_INFO, "SMBUS transaction result : Status=0x%08X\n", Status));
1122
1123 return Status;
1124 }
1125
1126 /**
1127 Programs the overrides for Vcc1p05 voltage which are controlled by UP1816
1128 chip using SVID/PMBUS interface.
1129
1130 @param[in] Voltage Voltage target in mV
1131
1132 @retval EFI_SUCCESS Successful to override voltage.
1133 **/
1134 EFI_STATUS
1135 ProgramVcc1p05Override (
1136 IN UINT16 Voltage
1137 )
1138 {
1139 EFI_STATUS Status;
1140 EFI_SMBUS_DEVICE_ADDRESS SlaveAddr;
1141 UINT8 Data;
1142 UINT8 DeviceCommand;
1143 UINT8 Prefix;
1144 UINT8 CurrentData;
1145
1146 //
1147 // Target address 0x2A
1148 //
1149 SlaveAddr.SmbusDeviceAddress = (0x2A >> 1);
1150
1151 //
1152 // Device Command and set Byte write
1153 //
1154 DeviceCommand = 0x1; // VREF1
1155
1156 //
1157 // Data = 0 is 1050 mV
1158 //
1159 Prefix = 0;
1160 if (Voltage >= 1050) {
1161 Data = (UINT8) (((Voltage - 1050) / 10) | (Prefix << 7));
1162 } else {
1163 Prefix = 1;
1164 Data = (UINT8) (((1050 - Voltage) / 10) | (Prefix << 7));
1165 }
1166
1167 CurrentData = SmBusReadDataByte (
1168 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1169 &Status
1170 );
1171
1172 DEBUG ((DEBUG_INFO, "SMBUS transaction request Vcc1p05: Addr=0x%08X Command=0x%08X CurrentData=0x%08X Data=0x%08X\n",
1173 SlaveAddr.SmbusDeviceAddress, DeviceCommand, CurrentData, Data));
1174
1175 SmBusWriteDataByte (
1176 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1177 Data,
1178 &Status
1179 );
1180
1181 DEBUG ((DEBUG_INFO, "SMBUS transaction result : Status=0x%08X\n", Status));
1182
1183 return Status;
1184 }
1185
1186 /**
1187 Programs the overrides for VccDd2 voltage which are controlled by UP1816
1188 chip using SVID/PMBUS interface.
1189
1190 @param[in] Voltage Voltage target in mV
1191
1192 @retval EFI_SUCCESS Successful to override voltage.
1193 **/
1194 EFI_STATUS
1195 ProgramVccDd2Override (
1196 IN UINT16 Voltage
1197 )
1198 {
1199 EFI_STATUS Status;
1200 EFI_SMBUS_DEVICE_ADDRESS SlaveAddr;
1201 UINT8 DeviceCommand;
1202 UINT8 Data;
1203 UINT8 Prefix;
1204 UINT8 CurrentData;
1205
1206 //
1207 // Target address 0x28
1208 //
1209 SlaveAddr.SmbusDeviceAddress = (0x28 >> 1);
1210
1211 //
1212 // Device Command and set Byte write
1213 //
1214 DeviceCommand = 0x1; // VREF1
1215
1216 //
1217 // Data = 0 is 1100 mV
1218 //
1219
1220 Prefix = 0;
1221 if (Voltage >= 1100) {
1222 Data = (UINT8) (((Voltage - 1100) / 10) | (Prefix << 7));
1223 } else {
1224 Prefix = 1;
1225 Data = (UINT8) (((1100 - Voltage) / 10) | (Prefix << 7));
1226 }
1227
1228 CurrentData = SmBusReadDataByte (
1229 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1230 &Status
1231 );
1232
1233 DEBUG ((DEBUG_INFO, "SMBUS transaction request VccDD2: Addr=0x%08X Command=0x%08X CurrentData=0x%08X Data=0x%08X\n",
1234 SlaveAddr.SmbusDeviceAddress, DeviceCommand, CurrentData, Data));
1235
1236 SmBusWriteDataByte (
1237 SMBUS_LIB_ADDRESS (SlaveAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1238 Data,
1239 &Status
1240 );
1241
1242 DEBUG ((DEBUG_INFO, "SMBUS transaction result : Status=0x%08X\n", Status));
1243
1244 return Status;
1245 }
1246
1247 /**
1248 Programs the overrides for VCCIN_AUX_CPU voltage which are controlled by PCA9555 (IO Port expander).
1249
1250 @param[in] Voltage Voltage target in mV
1251
1252 @retval EFI_SUCCESS The function completes successfully
1253 @retval EFI_STATUS Fail status return from SmBusWriteDataWord ()
1254 **/
1255 EFI_STATUS
1256 ProgramVccInAuxOverride (
1257 IN UINT16 Voltage
1258 )
1259 {
1260 EFI_STATUS Status;
1261 EFI_SMBUS_DEVICE_ADDRESS SecondaryAddr;
1262 UINT8 DeviceCommand;
1263 UINT16 InputVid;
1264 UINT16 Vid1620mV;
1265 UINT16 CurrentData;
1266
1267 Vid1620mV = (UINT16) 0x1E8F;
1268
1269 //
1270 // Secondary address 0x26 based on board design
1271 //
1272 SecondaryAddr.SmbusDeviceAddress = (VCCIN_AUX_SECONDARY_ADDRESS >> 1);
1273
1274 //
1275 // Device Command and set Word write
1276 //
1277 DeviceCommand = 0x21; // VCCIN AUX
1278
1279 //
1280 // Send the voltage
1281 //
1282 InputVid = (UINT16) (Vid1620mV + ((Voltage - 1620) / 10));
1283
1284 CurrentData = SmBusReadDataWord (
1285 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1286 &Status
1287 );
1288
1289 DEBUG ((DEBUG_INFO, "SMBUS transaction request VccCore: Addr=0x%08X Command=0x%08X CurrentData=0x%08X Data=0x%08X\n",
1290 SecondaryAddr.SmbusDeviceAddress, DeviceCommand, CurrentData, InputVid));
1291
1292 SmBusWriteDataWord (
1293 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1294 InputVid,
1295 &Status
1296 );
1297
1298 DEBUG ((DEBUG_INFO, "SMBUS transaction Status=0x%08X\n", Status));
1299
1300 return Status;
1301 }
1302
1303 /**
1304 Programs the overrides for Richtek VccIa voltage which are controlled by Richtek VR (External VR).
1305
1306 @param[in] VidModeEn Enabled/ Disable VCC VID Mode
1307 @param[in] Voltage Voltage target in mV
1308
1309 @retval EFI_SUCCESS The function completes successfully
1310 @retval EFI_STATUS Fail status return from SmBusWriteDataWord ()
1311 **/
1312 EFI_STATUS
1313 ProgramRichtekVccIaOverride (
1314 IN UINT8 VidModeEn,
1315 IN UINT16 Voltage
1316 )
1317 {
1318 EFI_STATUS Status;
1319 EFI_SMBUS_DEVICE_ADDRESS SecondaryAddr;
1320 UINT8 DeviceCommand;
1321 UINT16 InputVid;
1322 UINT8 MsbVid;
1323 UINT8 LsbVid;
1324
1325 //
1326 // Secondary address 0x20 based on board design
1327 //
1328 SecondaryAddr.SmbusDeviceAddress = (RICHTEK_VR_SECONDARY_ADDRESS >> 1);
1329
1330 //
1331 // Enable / Disable Fixed VID mode of Core Rail
1332 //
1333 DeviceCommand = 0x24; // EN_VFIX_CORE for IA
1334
1335 SmBusWriteDataByte (
1336 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1337 VidModeEn,
1338 &Status
1339 );
1340 DEBUG ((DEBUG_INFO, "SMBUS transaction result : Status=0x%08X\n", Status));
1341
1342 if (VidModeEn) {
1343 //
1344 // Calculate request VID (voltage)
1345 //
1346 InputVid = (UINT16) ((Voltage - 245) / 5);
1347 MsbVid = (InputVid & RICHTEK_VFIX_MSB_CORE_MASK)? 0x01 : 0x00;
1348 LsbVid = (UINT8) (InputVid & RICHTEK_VFIX_LSB_CORE_MASK);
1349
1350 DEBUG ((DEBUG_INFO, "SMBUS transaction request VccIA: Addr=0x%08X Command=0x%08X Data=0x%08X\n",
1351 SecondaryAddr.SmbusDeviceAddress, DeviceCommand, InputVid));
1352
1353 DeviceCommand = 0x25; // VFIX_LSB_CORE
1354 SmBusWriteDataByte (
1355 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1356 LsbVid,
1357 &Status
1358 );
1359 DEBUG ((DEBUG_INFO, "SMBUS transaction LSB Status=0x%08X\n", Status));
1360
1361 DeviceCommand = 0x26; // VFIX_MSB_CORE
1362 SmBusWriteDataByte (
1363 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1364 MsbVid,
1365 &Status
1366 );
1367 DEBUG ((DEBUG_INFO, "SMBUS transaction MSB Status=0x%08X\n", Status));
1368 }
1369 return Status;
1370 }
1371
1372 /**
1373 Programs the overrides for Richtek VccGt voltage which are controlled by Richtek VR (External VR).
1374
1375 @param[in] VidModeEn Enabled/ Disable VCC VID Mode
1376 @param[in] Voltage Voltage target in mV
1377
1378 @retval EFI_SUCCESS The function completes successfully
1379 @retval EFI_STATUS Fail status return from SmBusWriteDataWord ()
1380 **/
1381 EFI_STATUS
1382 ProgramRichtekVccGtOverride (
1383 IN UINT8 VidModeEn,
1384 IN UINT16 Voltage
1385 )
1386 {
1387 EFI_STATUS Status;
1388 EFI_SMBUS_DEVICE_ADDRESS SecondaryAddr;
1389 UINT8 DeviceCommand;
1390 UINT16 InputVid;
1391 UINT8 MsbVid;
1392 UINT8 LsbVid;
1393
1394 //
1395 // Secondary address 0x20 based on board design
1396 //
1397 SecondaryAddr.SmbusDeviceAddress = (RICHTEK_VR_SECONDARY_ADDRESS >> 1);
1398
1399 //
1400 // Enable / Disable Fixed VID mode of Core Rail
1401 //
1402 DeviceCommand = 0x44; // EN_VFIX_CORE for GT
1403
1404 SmBusWriteDataByte (
1405 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1406 VidModeEn,
1407 &Status
1408 );
1409 DEBUG ((DEBUG_INFO, "SMBUS transaction result : Status=0x%08X\n", Status));
1410
1411 if (VidModeEn) {
1412 //
1413 // Calculate request VID (voltage)
1414 //
1415 InputVid = (UINT16) ((Voltage - 245) / 5);
1416 MsbVid = (InputVid & RICHTEK_VFIX_MSB_CORE_MASK)? 0x01 : 0x00;
1417 LsbVid = (UINT8) (InputVid & RICHTEK_VFIX_LSB_CORE_MASK);
1418
1419 DEBUG ((DEBUG_INFO, "SMBUS transaction request VccGt: Addr=0x%08X Command=0x%08X Data=0x%08X\n",
1420 SecondaryAddr.SmbusDeviceAddress, DeviceCommand, InputVid));
1421
1422 DeviceCommand = 0x45; // VFIX_LSB_CORE
1423 SmBusWriteDataByte (
1424 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1425 LsbVid,
1426 &Status
1427 );
1428 DEBUG ((DEBUG_INFO, "SMBUS transaction LSB Status=0x%08X\n", Status));
1429
1430 DeviceCommand = 0x46; // VFIX_MSB_CORE
1431 SmBusWriteDataByte (
1432 SMBUS_LIB_ADDRESS (SecondaryAddr.SmbusDeviceAddress, DeviceCommand, 0, FALSE),
1433 MsbVid,
1434 &Status
1435 );
1436 DEBUG ((DEBUG_INFO, "SMBUS transaction MSB Status=0x%08X\n", Status));
1437 }
1438 return Status;
1439 }
1440
1441 /**
1442 Check and apply the override knobs for external voltage rails based on board design
1443
1444 @param[in] CpuSetup Setup variables under CPU Setup
1445 **/
1446 VOID
1447 ProgramVoltageOverrides (
1448 IN CPU_SETUP *CpuSetup
1449 )
1450 {
1451 EFI_STATUS Status = 0x0;
1452
1453 //
1454 // Check for Vcc1p8 voltage override
1455 //
1456 if (CpuSetup->Vcc1p8OverrideEnable == 0) {
1457 DEBUG ((DEBUG_INFO, "Default Vcc1p8 selected. No action required for voltage programming.\n"));
1458 } else {
1459 DEBUG ((DEBUG_INFO, "(OCVR) Programming Vcc1p8 Override = %d\n", CpuSetup->Vcc1p8OverrideVoltage));
1460 Status = ProgramVcc1p8Override (CpuSetup->Vcc1p8OverrideVoltage);
1461
1462 if (EFI_ERROR (Status)) {
1463 DEBUG ((DEBUG_INFO, "Vcc1p8 programming failed. Status = %r\n", Status));
1464 } else {
1465 DEBUG ((DEBUG_INFO, "Vcc1p8 programming successful. Status = %r\n", Status));
1466 }
1467 }
1468
1469 //
1470 // Check for Vcc1p05 voltage override
1471 //
1472 if (CpuSetup->Vcc1p05OverrideEnable == 0) {
1473 DEBUG ((DEBUG_INFO, "Default Vcc1p05 selected. No action required for voltage programming.\n"));
1474 } else {
1475 DEBUG ((DEBUG_INFO, "(OCVR) Programming Vcc1p05 Override = %d\n", CpuSetup->Vcc1p05OverrideVoltage));
1476 Status = ProgramVcc1p05Override (CpuSetup->Vcc1p05OverrideVoltage);
1477
1478 if (EFI_ERROR (Status)) {
1479 DEBUG ((DEBUG_INFO, "Vcc1p05 programming failed. Status = %r\n", Status));
1480 } else {
1481 DEBUG ((DEBUG_INFO, "Vcc1p05 programming successful. Status = %r\n", Status));
1482 }
1483 }
1484
1485 //
1486 // Check for VccDD2 voltage override
1487 //
1488 if (CpuSetup->VccDd2OverrideEnable == 0) {
1489 DEBUG ((DEBUG_INFO, "Default VccDD2 selected. No action required for voltage programming.\n"));
1490 } else {
1491 DEBUG ((DEBUG_INFO, "(OCVR) Programming VccDD2 Override = %d\n", CpuSetup->VccDd2OverrideVoltage));
1492 Status = ProgramVccDd2Override (CpuSetup->VccDd2OverrideVoltage);
1493
1494 if (EFI_ERROR (Status)) {
1495 DEBUG ((DEBUG_INFO, "VccDD2 programming failed. Status = %r\n", Status));
1496 } else {
1497 DEBUG ((DEBUG_INFO, "VccDD2 programming successful. Status = %r\n", Status));
1498 }
1499 }
1500
1501 //
1502 // Check for VCCIN AUX CPU voltage override
1503 //
1504 if (CpuSetup->VccInAuxEnable == 0) {
1505 DEBUG ((DEBUG_INFO, "Default VCCIN AUX CPU selected. No action required for voltage programming.\n"));
1506 } else {
1507 DEBUG ((DEBUG_INFO, "(OCVR) Programming VCCIN AUX CPU Override = %d\n", CpuSetup->VccInAuxVoltage));
1508 Status = ProgramVccInAuxOverride (CpuSetup->VccInAuxVoltage);
1509
1510 if (EFI_ERROR (Status)) {
1511 DEBUG ((DEBUG_INFO, "VCCIN AUX programming failed. Status = %r\n", Status));
1512 } else {
1513 DEBUG ((DEBUG_INFO, "VCCIN AUX programming successful. Status = %r\n", Status));
1514 }
1515 } // VccInAux override
1516
1517 //
1518 // Check for RichTek VccIA voltage override
1519 //
1520 if (CpuSetup->RichtekVccIaEnable == 0) {
1521 DEBUG ((DEBUG_INFO, "Default RichTek VccIA selected. No action required for voltage programming.\n"));
1522 } else {
1523 DEBUG ((DEBUG_INFO, "(OCVR) Programming RichTek VccIA Override = %d\n", CpuSetup->RichtekVccIaVoltage));
1524 Status = ProgramRichtekVccIaOverride (CpuSetup->RichtekVccIaFixedVidMode, CpuSetup->RichtekVccIaVoltage);
1525
1526 if (EFI_ERROR (Status)) {
1527 DEBUG ((DEBUG_INFO, "RichTek VccIA programming failed. Status = %r\n", Status));
1528 } else {
1529 DEBUG ((DEBUG_INFO, "RichTek VccIA programming successful. Status = %r\n", Status));
1530 }
1531 } // RichTek VccIA override
1532
1533
1534 //
1535 // Check for RichTek VccGT voltage override
1536 //
1537 if (CpuSetup->RichtekVccGtEnable == 0) {
1538 DEBUG ((DEBUG_INFO, "Default RichTek VccGT selected. No action required for voltage programming.\n"));
1539 } else {
1540 DEBUG ((DEBUG_INFO, "(OCVR) Programming RichTek VccGT Override = %d\n", CpuSetup->RichtekVccGtVoltage));
1541 Status = ProgramRichtekVccGtOverride (CpuSetup->RichtekVccGtFixedVidMode, CpuSetup->RichtekVccGtVoltage);
1542
1543 if (EFI_ERROR (Status)) {
1544 DEBUG ((DEBUG_INFO, "RichTek VccGT programming failed. Status = %r\n", Status));
1545 } else {
1546 DEBUG ((DEBUG_INFO, "RichTek VccGT programming successful. Status = %r\n", Status));
1547 }
1548 } // RichTek VccGT override
1549 }
1550
1551 /**
1552 Platform Voltage Init - Programs platform voltages over SMBUS.
1553 Run this function after Smbus2Ppi is installed.
1554
1555 @param[in] PeiServices General purpose services available to every PEIM.
1556 @param[in] NotifyDescriptor Notify that this module published.
1557 @param[in] Ppi PPI that was installed.
1558
1559 @retval EFI_SUCCESS The function completed successfully.
1560 **/
1561 EFI_STATUS
1562 EFIAPI
1563 PlatformVoltageInit (
1564 IN CONST EFI_PEI_SERVICES **PeiServices,
1565 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1566 IN VOID *Ppi
1567 )
1568 {
1569 EFI_STATUS Status;
1570 CPU_SETUP CpuSetup;
1571 EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable;
1572 UINTN VariableSize;
1573 WDT_PPI *gWdtPei;
1574 UINTN SmbusPciBase;
1575 UINT16 SmbusIoBar;
1576
1577 DEBUG ((DEBUG_INFO, "(OC) Platform Voltage Init\n"));
1578
1579 Status = PeiServicesLocatePpi (
1580 &gEfiPeiReadOnlyVariable2PpiGuid,
1581 0,
1582 NULL,
1583 (VOID **) &ReadOnlyVariable
1584 );
1585 ASSERT_EFI_ERROR (Status);
1586
1587 //
1588 // Locate WDT_PPI (ICC WDT PPI)
1589 //
1590 gWdtPei = NULL;
1591 Status = PeiServicesLocatePpi (
1592 &gWdtPpiGuid,
1593 0,
1594 NULL,
1595 (VOID **) &gWdtPei
1596 );
1597
1598 VariableSize = sizeof (CPU_SETUP);
1599 Status = ReadOnlyVariable->GetVariable (
1600 ReadOnlyVariable,
1601 L"CpuSetup",
1602 &gCpuSetupVariableGuid,
1603 NULL,
1604 &VariableSize,
1605 &CpuSetup
1606 );
1607
1608 if (EFI_ERROR (Status)) {
1609 //
1610 // If GetVariable fails.
1611 //
1612 DEBUG ((DEBUG_INFO, "(OC) Failed to read Setup Data\n"));
1613 return EFI_SUCCESS;
1614 }
1615
1616 if (CpuSetup.OverclockingSupport == 0) {
1617 DEBUG ((DEBUG_INFO, "(OC) Skipping Platform Voltage Init, overclocking is not enabled in BIOS setup.\n"));
1618 return EFI_SUCCESS;
1619 }
1620
1621 ///
1622 /// External Voltage rails control
1623 /// - Check if we need to override the voltages of the different VRMs using the SVID or PMBUS interfaces
1624 ///
1625 if (CpuSetup.OverclockingSupport != 0) {
1626 //
1627 // Initial SMBUS
1628 //
1629 SmbusIoBar = 0xEFA0;
1630
1631 //
1632 // Temporary initialize SMBUS
1633 //
1634 SmbusPciBase = PCI_SEGMENT_LIB_ADDRESS (
1635 DEFAULT_PCI_SEGMENT_NUMBER_PCH,
1636 DEFAULT_PCI_BUS_NUMBER_PCH,
1637 PCI_DEVICE_NUMBER_PCH_SMBUS,
1638 PCI_FUNCTION_NUMBER_PCH_SMBUS,
1639 0
1640 );
1641
1642 DEBUG ((DEBUG_INFO, "SmbusPciBase = %x\n", SmbusPciBase));
1643 ///
1644 /// Set SMBus PCI 0x64 = 0x0A0A0000
1645 ///
1646 PciSegmentWrite32 (SmbusPciBase + R_SMBUS_CFG_64, 0x0A0A0000);
1647
1648 //
1649 // Initialize I/O BAR
1650 //
1651 PciSegmentAndThenOr32 (SmbusPciBase + R_SMBUS_CFG_BASE, B_SMBUS_CFG_BASE_BAR, SmbusIoBar);
1652
1653 //
1654 // Enable the Smbus I/O Enable
1655 //
1656 PciSegmentOr8 (SmbusPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPACE);
1657
1658 //
1659 // Enable the SMBUS Controller
1660 //
1661 PciSegmentOr8 (SmbusPciBase + R_SMBUS_CFG_HOSTC, B_SMBUS_CFG_HOSTC_SSRESET);
1662
1663 PciSegmentAndThenOr8 (
1664 SmbusPciBase + R_SMBUS_CFG_HOSTC,
1665 (UINT8) (~(B_SMBUS_CFG_HOSTC_SMI_EN | B_SMBUS_CFG_HOSTC_I2C_EN)),
1666 B_SMBUS_CFG_HOSTC_HST_EN
1667 );
1668
1669 ProgramVoltageOverrides (&CpuSetup);
1670 }
1671
1672 return Status;
1673 }
1674
1675 /**
1676 Build a HOB for debug configure data.
1677
1678 The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and
1679 PeiDxeSmmSerialPortParameterLib library instances.
1680
1681 @param[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.
1682
1683 **/
1684 VOID
1685 EFIAPI
1686 BuildDebugConfigDataHob (
1687 IN DEBUG_CONFIG_DATA *DebugConfigData
1688 )
1689 {
1690 DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
1691
1692 DebugConfigDataHob = BuildGuidHob (&gDebugConfigHobGuid, sizeof (DEBUG_CONFIG_DATA_HOB));
1693 ASSERT (DebugConfigDataHob != NULL);
1694 if (DebugConfigDataHob == NULL) {
1695 DEBUG ((DEBUG_ERROR, "Build Debug Config Hob failed!\n"));
1696 return;
1697 }
1698
1699 DebugConfigDataHob->SerialDebugMrcLevel = DebugConfigData->SerialDebugMrcLevel;
1700 DebugConfigDataHob->SerialDebug = DebugConfigData->SerialDebug;
1701 DebugConfigDataHob->SerialDebugBaudRate = DebugConfigData->SerialDebugBaudRate;
1702 DebugConfigDataHob->RamDebugInterface = 0;
1703 DebugConfigDataHob->UartDebugInterface = (DebugConfigData->UartDebugInterface == 1 && FeaturePcdGet (PcdSerialPortEnable)) ? 1 : 0;
1704 DebugConfigDataHob->Usb3DebugInterface = (DebugConfigData->Usb3DebugInterface == 1 && FeaturePcdGet (PcdUsb3SerialStatusCodeEnable)) ? 1 : 0;
1705 DebugConfigDataHob->TraceHubDebugInterface = (DebugConfigData->TraceHubDebugInterface == 1) ? 1 : 0;
1706
1707 DebugConfigDataHob->SerialIoDebugInterface = (DebugConfigData->SerialIoDebugInterface == 1 && FeaturePcdGet (PcdSerialIoUartEnable)) ? 1 : 0;
1708 DebugConfigDataHob->SerialIoUartDebugControllerNumber = DebugConfigData->SerialIoUartDebugControllerNumber;
1709 DebugConfigDataHob->SerialIoUartDebugBaudRate = DebugConfigData->SerialIoUartDebugBaudRate;
1710 DebugConfigDataHob->SerialIoUartDebugStopBits = DebugConfigData->SerialIoUartDebugStopBits;
1711 DebugConfigDataHob->SerialIoUartDebugParity = DebugConfigData->SerialIoUartDebugParity;
1712 DebugConfigDataHob->SerialIoUartDebugFlowControl = DebugConfigData->SerialIoUartDebugFlowControl;
1713 DebugConfigDataHob->SerialIoUartDebugDataBits = DebugConfigData->SerialIoUartDebugDataBits;
1714 }
1715
1716 /**
1717 Basic GPIO configuration before memory is ready
1718
1719 **/
1720 VOID
1721 GpioInitEarlyWwanPreMem (
1722 VOID
1723 )
1724 {
1725 GPIO_CONFIG BbrstConfig;
1726 UINT32 WwanBbrstGpio;
1727 UINT32 WwanPerstGpio;
1728 UINT32 WwanFcpoGpio;
1729
1730 WwanFcpoGpio = PcdGet32 (PcdWwanFullCardPowerOffGpio);
1731 WwanBbrstGpio = PcdGet32 (PcdWwanBbrstGpio);
1732 WwanPerstGpio = PcdGet32 (PcdWwanPerstGpio);
1733
1734 if (WwanBbrstGpio) {
1735 //
1736 // BIOS needs to reset modem if modem RESET# is not asserted via PLTRST# in the previous sleep state
1737 //
1738 GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig);
1739 if ((PcdGet8 (PcdPcieWwanEnable) == 0) ||
1740 ((PcdGetBool (PcdWwanResetWorkaround) == TRUE) &&
1741 (BbrstConfig.Direction == GpioDirOut) &&
1742 (BbrstConfig.OutputState == GpioOutHigh))) {
1743 //
1744 // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs
1745 //
1746 if (PcdGet8 (PcdPcieWwanEnable) == 1) { // Turn off 4G modem
1747 if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize) != 0) {
1748 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize));
1749 }
1750 MicroSecondDelay (1 * 1000); // Delay by 1ms
1751 } else {
1752 if (PcdGet8 (PcdPcieWwanEnable) == 2) { // Turn off 5G modem
1753 if (WwanPerstGpio) {
1754 GpioSetOutputValue (WwanPerstGpio, PcdGetBool (PcdWwanPerstGpioPolarity));
1755 MicroSecondDelay ((UINTN) PcdGet16 (PcdBoardWwanTPer2ResDelayMs) * 1000);
1756 }
1757 if (WwanBbrstGpio) {
1758 GpioSetOutputValue (WwanBbrstGpio, 0);
1759 MicroSecondDelay ((UINTN) PcdGet16 (PcdBoardWwanTRes2OffDelayMs) * 1000);
1760 }
1761 if (WwanFcpoGpio) {
1762 GpioSetOutputValue (WwanFcpoGpio, PcdGetBool (PcdWwanPerstGpioPolarity));
1763 MicroSecondDelay ((UINTN) PcdGet16 (PcdBoardWwanTOffDisDelayMs) * 1000);
1764 }
1765 }
1766 }
1767 DEBUG((DEBUG_INFO, "Put modem in OFF state\n"));
1768 }
1769
1770 if (PcdGet8 (PcdPcieWwanEnable) == 1) { // 4G - Intel Modem 7360/7560
1771 if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize) != 0) {
1772 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize));
1773 }
1774 } else if (PcdGet8 (PcdPcieWwanEnable) == 2) { // 5G - Mediatek Modem M80
1775 if (PcdGet32 (PcdBoardGpioTableM80WwanOnEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableM80WwanOnEarlyPreMemSize) != 0) {
1776 DEBUG((DEBUG_INFO, "5G M80 Modem: Power On Sequnce Start\n"));
1777 //
1778 // 1. Turn on EN_V3.3A_WWAN_LS, Turn off WWAN_RST_N & WWAN_PERST
1779 //
1780 ConfigureGpio ((VOID *) (UINTN) PcdGet32(PcdBoardGpioTableM80WwanOnEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableM80WwanOnEarlyPreMemSize));
1781 MicroSecondDelay ((UINTN) PcdGet16 (PcdBoardWwanTOn2ResDelayMs) * 1000);
1782 //
1783 // 2. De-asserting WWAN_RST_N
1784 //
1785 if (WwanBbrstGpio) {
1786 GpioSetOutputValue (WwanBbrstGpio, 1);
1787 MicroSecondDelay ((UINTN) PcdGet16 (PcdBoardWwanTOnRes2PerDelayMs) * 1000);
1788 }
1789 //
1790 // 3. De-asserting WWAN_PERST
1791 //
1792 if (WwanPerstGpio) {
1793 GpioSetOutputValue (WwanPerstGpio, (~(PcdGetBool (PcdWwanPerstGpioPolarity))) & BIT0);
1794 }
1795 DEBUG((DEBUG_INFO, "5G M80 Modem: Power On Sequnce End\n"));
1796 }
1797 }
1798 } else if(PcdGetBool (PcdPcieDeviceOnWwanSlot) == TRUE) {
1799 if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize) != 0) {
1800 ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize));
1801 }
1802 }
1803 }
1804
1805 /**
1806 Update PCDs for debug configure data.
1807
1808 The DebugConfigHob is built by platform code and consumed by PeiDxeSmmDebugPrintErrorLevelLib and
1809 PeiDxeSmmSerialPortParameterLib library instances.
1810
1811 @param[in] DebugConfigData A pointer to the DEBUG_CONFIG_DATA.
1812
1813 **/
1814 VOID
1815 EFIAPI
1816 UpdateDebugConfigPcds (
1817 IN DEBUG_CONFIG_DATA *DebugConfigData
1818 )
1819 {
1820 PcdSetBoolS (PcdStatusCodeUseSerial, DebugConfigData->UartDebugInterface == 1 && FeaturePcdGet(PcdSerialPortEnable) ? TRUE : FALSE);
1821
1822 return ;
1823 }
1824
1825 /**
1826 This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
1827
1828 @param[in] PeiServices Pointer to PEI Services Table.
1829 @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
1830 caused this function to execute.
1831 @param[in] Ppi Pointer to the PPI data associated with this function.
1832
1833 @retval EFI_SUCCESS The function completes successfully
1834 @retval others
1835 **/
1836 EFI_STATUS
1837 EFIAPI
1838 PlatformInitPreMem (
1839 IN CONST EFI_PEI_SERVICES **PeiServices,
1840 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
1841 IN VOID *Ppi
1842 )
1843 {
1844 EFI_STATUS Status;
1845 EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
1846 EFI_BOOT_MODE BootMode;
1847 UINT64 McD0BaseAddress;
1848 UINT16 ABase;
1849 SETUP_DATA SystemConfiguration;
1850 UINTN VariableSize;
1851 CHAR16 BiosVersion[40];
1852 CHAR16 ReleaseDate[20];
1853 CHAR16 ReleaseTime[20];
1854 UINTN Size;
1855 DEBUG_CONFIG_DATA DebugConfigData;
1856 ME_SETUP MeSetup;
1857 UINT32 PttFtifReg;
1858 UINT8 TpmInterfaceId;
1859 #if (FixedPcdGetBool (PcdBootGuardEnable) == 1) || (FixedPcdGetBool (PcdTxtEnable) == 1)
1860 BOOT_GUARD_INFO BootGuardInfo;
1861 #endif // (FixedPcdGetBool (PcdBootGuardEnable) == 1) || (FixedPcdGetBool (PcdTxtEnable) == 1)
1862
1863 PostCode(PLATFORM_INIT_PREMEM_ENTRY);
1864
1865 if (PcdGetBool (PcdPlatformInitPreMem)) {
1866 return EFI_SUCCESS;
1867 } else {
1868 Status = PcdSetBoolS (PcdPlatformInitPreMem, TRUE);
1869 ASSERT_EFI_ERROR (Status);
1870 }
1871
1872 VariableServices = (EFI_PEI_READ_ONLY_VARIABLE2_PPI *) Ppi;
1873
1874 Status = GetBiosVersionDateTime (BiosVersion, ReleaseDate, ReleaseTime);
1875 Size = sizeof (BiosVersion);
1876 PcdSetPtrS (PcdBiosVersion, &Size, &BiosVersion);
1877 Size = sizeof (ReleaseDate);
1878 PcdSetPtrS (PcdReleaseDate, &Size, &ReleaseDate);
1879 Size = sizeof (ReleaseTime);
1880 PcdSetPtrS (PcdReleaseTime, &Size, &ReleaseTime);
1881
1882 ///
1883 /// EDK/FSP dispatch mode switches PcdAcpiS3Enable dynamically on gSiPkgTokenSpaceGuid.PcdS3Enable setting.
1884 /// FSP API mode has a default PcdAcpiS3Enable setting but does not turn the PCD on/off here.
1885 ///
1886 #if FixedPcdGetBool (PcdFspModeSelection) == 0
1887 #if FixedPcdGetBool (PcdS3Enable) == 1
1888 PcdSetBoolS (PcdAcpiS3Enable, TRUE);
1889 #else
1890 PcdSetBoolS (PcdAcpiS3Enable, FALSE);
1891 #endif
1892 #endif
1893
1894 PeiServicesGetBootMode (&BootMode);
1895
1896 //
1897 // Set FailSafe Critical Temp & Fan Speed setting
1898 //
1899 Status = SetFailSafeFanCtrl (
1900 PcdGet8(PcdEcFailSafeActionCpuTemp),
1901 PcdGet8(PcdEcFailSafeActionFanPwm)
1902 );
1903 DEBUG ((DEBUG_INFO, " EC FailSafe (CpuTemp,Fan) set to (%d,%d), Status = %r\n",\
1904 PcdGet8(PcdEcFailSafeActionCpuTemp),PcdGet8(PcdEcFailSafeActionFanPwm), Status));
1905
1906 //
1907 // Set FailSafe Critical Temp & Fan Speed setting
1908 //
1909 Status = SetFailSafeFanCtrl (
1910 PcdGet8(PcdEcFailSafeActionCpuTemp),
1911 PcdGet8(PcdEcFailSafeActionFanPwm)
1912 );
1913 DEBUG ((DEBUG_INFO, " EC FailSafe (CpuTemp,Fan) set to (%d,%d), Status = %r\n",\
1914 PcdGet8(PcdEcFailSafeActionCpuTemp),PcdGet8(PcdEcFailSafeActionFanPwm), Status));
1915
1916 VariableSize = sizeof (SETUP_DATA);
1917 Status = VariableServices->GetVariable (
1918 VariableServices,
1919 L"Setup",
1920 &gSetupVariableGuid,
1921 NULL,
1922 &VariableSize,
1923 &SystemConfiguration
1924 );
1925 if (EFI_ERROR (Status)) {
1926 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration and set the configuration to production mode!\n"));
1927 PcdSet8S (PcdPcieWwanEnable, 0);
1928 PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
1929 } else {
1930 PcdSet8S (PcdPcieWwanEnable, SystemConfiguration.WwanEnable);
1931 PcdSetBoolS (PcdWwanResetWorkaround, SystemConfiguration.WwanResetWorkaround);
1932 DEBUG((DEBUG_INFO, "WwanEnable: %d\n", PcdGet8 (PcdPcieWwanEnable)));
1933 DEBUG((DEBUG_INFO, "WwanTOn2ResDelayMs: %d\n", PcdGet16 (PcdBoardWwanTOn2ResDelayMs)));
1934 DEBUG((DEBUG_INFO, "WwanTOnRes2PerDelayMs: %d\n", PcdGet16 (PcdBoardWwanTOnRes2PerDelayMs)));
1935 DEBUG((DEBUG_INFO, "WwanTOnPer2PdsDelayMs: %d\n", PcdGet16 (PcdBoardWwanTOnPer2PdsDelayMs)));
1936 DEBUG((DEBUG_INFO, "WwanTPer2ResDelayMs: %d\n", PcdGet16 (PcdBoardWwanTRes2OffDelayMs)));
1937 DEBUG((DEBUG_INFO, "WwanTRes2OffDelayMs: %d\n", PcdGet16 (PcdBoardWwanTRes2OffDelayMs)));
1938 DEBUG((DEBUG_INFO, "WwanTOffDisDelayMs: %d\n", PcdGet16 (PcdBoardWwanTOffDisDelayMs)));
1939 DEBUG((DEBUG_INFO, "WwanTResTogDelayMs: %d\n", PcdGet16 (PcdBoardWwanTResTogDelayMs)));
1940 DEBUG((DEBUG_INFO, "WwanTRes2PdsDelayMs: %d\n", PcdGet16 (PcdBoardWwanTRes2PdsDelayMs)));
1941 }
1942
1943 GpioInitEarlyWwanPreMem();
1944 USBCRetimerComplianceModePreMem();
1945
1946 #if FixedPcdGetBool(PcdDTbtEnable) == 1
1947 if (SystemConfiguration.DiscreteTbtSupport) {
1948 InstallPeiDTbtPolicy ();
1949 }
1950 #endif
1951
1952
1953 DEBUG_CODE_BEGIN();
1954 VariableSize = sizeof (DEBUG_CONFIG_DATA);
1955 Status = VariableServices->GetVariable (
1956 VariableServices,
1957 L"DebugConfigData",
1958 &gDebugConfigVariableGuid,
1959 NULL,
1960 &VariableSize,
1961 &DebugConfigData
1962 );
1963 if (EFI_ERROR (Status)) {
1964 DEBUG ((DEBUG_ERROR, "Failed to get Debug Configuration data variable!\n"));
1965 } else {
1966 BuildDebugConfigDataHob (&DebugConfigData);
1967 UpdateDebugConfigPcds (&DebugConfigData);
1968 }
1969 DEBUG_CODE_END();
1970
1971 ///
1972 ///
1973 ///
1974 ///
1975
1976 Status = CreateFastBootHob (VariableServices);
1977 ASSERT_EFI_ERROR (Status);
1978
1979 Status = PeiServicesNotifyPpi (&mWdtPpiNotifyList);
1980 ASSERT_EFI_ERROR (Status);
1981
1982 Status = PeiServicesNotifyPpi (&mSiPreMemPolicyNotifyList);
1983 ASSERT_EFI_ERROR (Status);
1984
1985 #if FixedPcdGetBool (PcdOverclockEnable) == 1
1986 Status = PeiServicesNotifyPpi (&mPlatformVoltageInitOnMemoryNotifyList);
1987 ASSERT_EFI_ERROR (Status);
1988 #endif
1989 ///
1990 /// Do basic PCH init
1991 ///
1992 PlatformPchInit (VariableServices);
1993
1994 ///
1995 /// Set what state (S0/S5) to go to when power is re-applied after a power failure (G3 state)
1996 ///
1997 SetTheStateToGoAfterG3 (VariableServices);
1998
1999 ABase = PmcGetAcpiBase ();
2000
2001 ///
2002 /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
2003 ///
2004 IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
2005 IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
2006 ///----------------------------------------------------------------------------------
2007 ///
2008 /// BIOS should check the wake status before memory initialization to determine
2009 /// if ME has reset the system while the host was in a sleep state. If platform was not in a sleep state,
2010 /// BIOS should ensure a non-sleep exit path is taken by forcing an s5 exit.
2011 ///
2012 if (PmcGetSleepTypeAfterWake () == PmcNotASleepState) {
2013 PmcSetSleepState (PmcS5SleepState);
2014 }
2015
2016 if (BootMode == BOOT_ON_S3_RESUME) {
2017 //
2018 // A platform PEIM should enable R/W access to E/F segment in the S3 boot path
2019 // otherwise, this AP wakeup buffer can't be accessed during CPU S3 operation.
2020 //
2021 McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, 0);
2022 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM0, 0x30);
2023 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM5, 0x33);
2024 PciSegmentWrite8 (McD0BaseAddress + R_SA_PAM6, 0x33);
2025 }
2026
2027 #if (FixedPcdGetBool (PcdBootGuardEnable) == 1) || (FixedPcdGetBool (PcdTxtEnable) == 1)
2028 //
2029 // TPM Initialized by Boot Guard
2030 //
2031 if (IsBootGuardSupported ()) {
2032 GetBootGuardInfo (&BootGuardInfo);
2033 DEBUG ((DEBUG_INFO, "PlatformInitAdvancedPreMem: BootGuard supported\n"));
2034 if (BootGuardInfo.BypassTpmInit == TRUE) {
2035 DEBUG ((DEBUG_INFO, "PlatformInitAdvancedPreMem: Bypass TPM init\n"));
2036 PcdSet8S (PcdTpm2InitializationPolicy, 0);
2037 }
2038 }
2039 #endif // (FixedPcdGetBool (PcdBootGuardEnable) == 1) || (FixedPcdGetBool (PcdTxtEnable) == 1)
2040
2041 //
2042 // If PTT presence detected, disable TPM self test policy
2043 //
2044 TpmInterfaceId = MmioRead8 ((UINTN)PcdGet64 (PcdTpmBaseAddress) + 0x30);
2045 PttFtifReg = MmioRead32 (R_PTT_TXT_STS_FTIF);
2046
2047 if ((TpmInterfaceId != 0xFF) &&
2048 ((PttFtifReg & V_FTIF_FTPM_PRESENT) == V_FTIF_FTPM_PRESENT)) {
2049
2050 DEBUG ((DEBUG_INFO, "PttFtifReg: %x\n", PttFtifReg));
2051 DEBUG ((DEBUG_INFO, "PTT detected\n"));
2052 DEBUG ((DEBUG_INFO, "PlatformInitAdvancedPreMem: Disabling TPM Self Test policy for PTT\n"));
2053 PcdSet8S (PcdTpm2SelfTestPolicy, 0);
2054
2055 }
2056
2057 if (BootMode == BOOT_ON_S3_RESUME) {
2058 PcdSet8S (PcdCRBIdleByPass, 0x0);
2059 }
2060
2061 VariableSize = sizeof (ME_SETUP);
2062 Status = VariableServices->GetVariable (
2063 VariableServices,
2064 L"MeSetup",
2065 &gMeSetupVariableGuid,
2066 NULL,
2067 &VariableSize,
2068 &MeSetup
2069 );
2070 ASSERT_EFI_ERROR (Status);
2071 if ((BootMode != BOOT_ON_S3_RESUME) && (MeSetup.ExtendMeMeasuredBoot == TRUE)) {
2072 PeiServicesNotifyPpi (&mPeiExtendMeMeasuredBootNotifyList);
2073 }
2074
2075 ///
2076 /// Install Pre Memory PPIs
2077 ///
2078 Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
2079 ASSERT_EFI_ERROR (Status);
2080
2081 PostCode(PLATFORM_INIT_PREMEM_EXIT);
2082
2083 DisArmEcWdt ();
2084 DEBUG ((DEBUG_INFO, "Disarm EC WDT\n"));
2085
2086 #if FixedPcdGetBool(PcdResiliencyEnable) == 1
2087 #ifdef MDEPKG_NDEBUG
2088 if (BootMode != BOOT_ON_S3_RESUME) {
2089 //
2090 // Arm EC WDT with a max timeout value (255s) to monitor system boot in release build.
2091 //
2092 ArmEcWdtWithTimeOut (0xFF);
2093 }
2094 #endif
2095 #endif
2096
2097 return Status;
2098 }
2099
2100 /**
2101 Platform Init before memory PEI module entry point
2102
2103 @param[in] FileHandle Not used.
2104 @param[in] PeiServices General purpose services available to every PEIM.
2105
2106 @retval EFI_SUCCESS The function completes successfully
2107 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
2108 **/
2109 EFI_STATUS
2110 EFIAPI
2111 PlatformInitAdvancedPreMemEntryPoint (
2112 IN EFI_PEI_FILE_HANDLE FileHandle,
2113 IN CONST EFI_PEI_SERVICES **PeiServices
2114 )
2115 {
2116 EFI_STATUS Status;
2117 BIOS_ID_IMAGE BiosIdImage;
2118
2119 Status = GetBiosId (&BiosIdImage);
2120
2121 if (Status == EFI_SUCCESS) {
2122 DEBUG ((DEBUG_INFO, "+==================================================+\n"));
2123 DEBUG ((DEBUG_INFO, "| BIOS version [%s] |\n", &BiosIdImage.BiosIdString));
2124 DEBUG ((DEBUG_INFO, "+==================================================+\n"));
2125 }
2126
2127 ///
2128 /// Initialize Nvram to default when checksum computation is failed
2129 ///
2130 SecondaryNvRamInit ();
2131
2132 ///@todo it should be moved to Si Pkg.
2133 ///
2134 /// Do Early PCH init
2135 ///
2136 EarlyPlatformPchInit ();
2137
2138 //
2139 // Install ME reset call back function.
2140 //
2141 RegisterMeReset ();
2142
2143 ///
2144 /// Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced
2145 ///
2146 Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
2147
2148 ///
2149 /// After code reorangized, memorycallback will run because the PPI is already
2150 /// installed when code run to here, it is supposed that the InstallEfiMemory is
2151 /// done before.
2152 ///
2153 Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
2154
2155 return Status;
2156 }
EnableLanPower
EFI_STATUS EnableLanPower(IN BOOLEAN Enable)
Enable LAN power.
TcoWdtHob.h
IsFastBootEnabled
BOOLEAN IsFastBootEnabled(VOID)
Check fast boot is enabled or not.
Definition: PlatformInitAdvancedPreMem.c:577
USBCRetimerComplianceModePreMem
VOID USBCRetimerComplianceModePreMem(VOID)
Configure TypeC Retimer FP pin for USB compliance mode function.
Definition: PlatformInitAdvancedPreMem.c:377
RICHTEK_VR_SECONDARY_ADDRESS
#define RICHTEK_VR_SECONDARY_ADDRESS
Richtek VR from I2C.
Definition: PlatformInitAdvancedPreMem.c:103
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
SetFailSafeFanCtrl
EFI_STATUS SetFailSafeFanCtrl(UINT8 CpuTemp, UINT8 CpuFanSpeed)
Allow EC to control Fail Safe Fan control to avoid silicon burnout after hung state.
UpdateDebugConfigPcds
VOID UpdateDebugConfigPcds(IN DEBUG_CONFIG_DATA *DebugConfigData)
Update PCDs for debug configure data.
Definition: PlatformInitAdvancedPreMem.c:1816
ProgramVccDd2Override
EFI_STATUS ProgramVccDd2Override(IN UINT16 Voltage)
Programs the overrides for VccDd2 voltage which are controlled by UP1816 chip using SVID/PMBUS interf...
Definition: PlatformInitAdvancedPreMem.c:1195
PeiWdtAppLib.h
PEI WDT App library definitions.
CustomOptionControl.h
UsbcRetimerCompliancePDMessage
EFI_STATUS UsbcRetimerCompliancePDMessage(IN OUT UINT8 *DataBuffer)
Usbc Retimer Compliance Mode.
BuildDebugConfigDataHob
VOID BuildDebugConfigDataHob(IN DEBUG_CONFIG_DATA *DebugConfigData)
Build a HOB for debug configure data.
Definition: PlatformInitAdvancedPreMem.c:1686
CreateFastBootHob
EFI_STATUS CreateFastBootHob(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Create Fast Boot HOB.
Definition: PlatformInitAdvancedPreMem.c:624
ConfigureGpio
VOID ConfigureGpio(IN GPIO_INIT_CONFIG *GpioDefinition, IN UINT16 GpioTableCount)
Configures GPIO.
Definition: PlatformInitAdvancedPreMem.c:361
PchReset
EFI_STATUS PchReset(IN CONST EFI_PEI_SERVICES **PeiServices)
Provide hard reset PPI service.
Definition: PlatformInitAdvancedPreMem.c:724
EcInit
VOID EcInit(IN UINT8 PchLan, IN EFI_BOOT_MODE BootMode)
Configure EC for specific devices.
Definition: PlatformInitAdvancedPreMem.c:888
SetTheStateToGoAfterG3
VOID SetTheStateToGoAfterG3(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Set the state to go after G3.
Definition: PlatformInitAdvancedPreMem.c:817
FastBootFunctionEnabledHob.h
This file defines the HOB data structure to indicate that Fast Boot function is enabled in PEI phase,...
SiPreMemPolicyPpiNotifyCallback
EFI_STATUS SiPreMemPolicyPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after SaPolicy PPI to be installed.
Definition: PlatformInitAdvancedPreMem.c:1020
DisArmEcWdt
EFI_STATUS DisArmEcWdt(VOID)
Dis arm ec wdt.
PeiExtendMeMeasuredBootNotifyCallback
EFI_STATUS PeiExtendMeMeasuredBootNotifyCallback(IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Callback function to install and update CSME Measurements HOB before DID in case of CSME in Disabled ...
Definition: PlatformInitAdvancedPreMem.c:217
ClearTenSecPwrButtonMode
VOID ClearTenSecPwrButtonMode(VOID)
Clear ten second power button mode.
SecondaryNvRamInit
VOID SecondaryNvRamInit(VOID)
Load CMOS default on RTC battery failure.
PlatformInitAdvancedPreMemEntryPoint
EFI_STATUS PlatformInitAdvancedPreMemEntryPoint(IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)
Platform Init before memory PEI module entry point.
Definition: PlatformInitAdvancedPreMem.c:2111
Setup.h
ArmEcWdtWithTimeOut
EFI_STATUS ArmEcWdtWithTimeOut(IN UINT8 TimeOut)
Arm ec wdt with specific timeout.
VCCIN_AUX_SECONDARY_ADDRESS
#define VCCIN_AUX_SECONDARY_ADDRESS
VCCIN_AUX Secondary address.
Definition: PlatformInitAdvancedPreMem.c:98
PeiWdtApp
EFI_STATUS PeiWdtApp(IN WDT_PPI *WdtPei)
turns on WDT during PEI phase according to requests made by OS overclocking application (through WDT ...
ProgramVccInAuxOverride
EFI_STATUS ProgramVccInAuxOverride(IN UINT16 Voltage)
Programs the overrides for VCCIN_AUX_CPU voltage which are controlled by PCA9555 (IO Port expander).
Definition: PlatformInitAdvancedPreMem.c:1256
ProgramVoltageOverrides
VOID ProgramVoltageOverrides(IN CPU_SETUP *CpuSetup)
Check and apply the override knobs for external voltage rails based on board design.
Definition: PlatformInitAdvancedPreMem.c:1447
PlatformSpecificInitPreMem
EFI_STATUS PlatformSpecificInitPreMem(VOID)
Do platform specific programming.
Definition: PlatformInitAdvancedPreMem.c:915
MemoryDiscoveredPpiNotifyCallback
EFI_STATUS MemoryDiscoveredPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Callback once there is main memory.
Definition: PlatformInitAdvancedPreMem.c:482
PlatformNvRamHookLib.h
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NV...
WdtAppPpiNotifyCallback
EFI_STATUS WdtAppPpiNotifyCallback(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Run this function after Wdt PPI to be installed.
Definition: PlatformInitAdvancedPreMem.c:1049
PlatformInitPreMem
EFI_STATUS PlatformInitPreMem(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced.
Definition: PlatformInitAdvancedPreMem.c:1838
IsOverclockingEnabled
BOOLEAN IsOverclockingEnabled(VOID)
Check to see the overclocking is enabled or not.
Definition: PlatformInitAdvancedPreMem.c:531
EcMiscLib.h
EC miscellaneous library functions.
PlatformPostCode.h
DfctFastChargingMode
EFI_STATUS DfctFastChargingMode(IN BOOLEAN Enable)
Select charging method.
RESET_GENERATOR_PORT
#define RESET_GENERATOR_PORT
Reset Generator I/O Port.
Definition: PlatformInitAdvancedPreMem.c:93
ProgramVcc1p05Override
EFI_STATUS ProgramVcc1p05Override(IN UINT16 Voltage)
Programs the overrides for Vcc1p05 voltage which are controlled by UP1816 chip using SVID/PMBUS inter...
Definition: PlatformInitAdvancedPreMem.c:1135
GpioInitEarlyWwanPreMem
VOID GpioInitEarlyWwanPreMem(VOID)
Basic GPIO configuration before memory is ready.
Definition: PlatformInitAdvancedPreMem.c:1721
PeiPlatformLib.h
PlatformVoltageInit
EFI_STATUS PlatformVoltageInit(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Platform Voltage Init - Programs platform voltages over SMBUS.
Definition: PlatformInitAdvancedPreMem.c:1563
EcTcssLib.h
EC TCSS library functions.
ProgramVcc1p8Override
EFI_STATUS ProgramVcc1p8Override(IN UINT16 Voltage)
Programs the overrides for Vcc1p8 voltage which are controlled by UP1816 chip using SVID/PMBUS interf...
Definition: PlatformInitAdvancedPreMem.c:1075
ProgramRichtekVccIaOverride
EFI_STATUS ProgramRichtekVccIaOverride(IN UINT8 VidModeEn, IN UINT16 Voltage)
Programs the overrides for Richtek VccIa voltage which are controlled by Richtek VR (External VR).
Definition: PlatformInitAdvancedPreMem.c:1313
ProgramRichtekVccGtOverride
EFI_STATUS ProgramRichtekVccGtOverride(IN UINT8 VidModeEn, IN UINT16 Voltage)
Programs the overrides for Richtek VccGt voltage which are controlled by Richtek VR (External VR).
Definition: PlatformInitAdvancedPreMem.c:1382
EarlyPlatformPchInit
VOID EarlyPlatformPchInit(VOID)
Early Platform PCH initialization.
Definition: PlatformInitAdvancedPreMem.c:746
FastBootExceptionInfoHob.h
SetupVariable.h
PlatformPchInit
VOID PlatformPchInit(IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices)
Initialize the GPIO IO selection, GPIO USE selection, and GPIO signal inversion registers.
Definition: PlatformInitAdvancedPreMem.c:860
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedSmm.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
Functions
PlatformInitAdvancedSmm.c File Reference

Platform Advanced SMM Driver. More...

#include "PlatformInitAdvancedSmm.h"
#include <OemSetup.h>
#include <CpuRegs.h>
#include <PchPolicyCommon.h>
#include "PcieDockSmi.h"
#include "PlatformBoardId.h"
#include "AcpiCommon.h"
#include <Library/PmcLib.h>
#include <Library/PciSegmentLib.h>
#include <Library/GpioLib.h>
#include <Library/ItssLib.h>
#include <Library/TimerLib.h>
#include <Register/MeRegs.h>
#include <Register/HeciRegs.h>
#include <Protocol/PchTcoSmiDispatch.h>
#include <Protocol/SmmVariable.h>
#include <Protocol/SmmCpu.h>
#include <Library/PostCodeLib.h>
#include <PlatformPostCode.h>
#include <Register/PchRegs.h>
#include <Register/PchRegsLpc.h>
#include <Register/PmcRegs.h>
#include <Register/RtcRegs.h>
#include <Library/PchPciBdfLib.h>
#include <Register/CommonMsr.h>
Include dependency graph for PlatformInitAdvancedSmm.c:

Go to the source code of this file.

Functions

EFI_STATUS | EnableAcpiCallback (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN OUT UINTN *CommBufferSize OPTIONAL)
Clear Port 80h. More...
EFI_STATUS | DisableAcpiCallback (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
Disable SCI. More...
UINT8 | DecToBCD (UINT8 Dec)
Converts Decimal to BCD Only for 2 digit BCD. More...
UINT8 | BCDToDec (UINT8 BCD)
Converts BCD to Dec number Only for 2 digit BCD. More...
UINT8 | ReadRtcIndex (IN UINT8 Index)
Reads the RTC Index register. More...
VOID | WriteRtcIndex (IN UINT8 Index, IN UINT8 Value)
Writes to an RTC Index register. More...
VOID | InitRtcWakeup (VOID)
Disable RTC alarm and clear RTC PM1 status.
EFI_STATUS | EnablePchTier2GpioWakeSupport (VOID)
Enable wake capability for that wake delivered via tier2 GPIO. More...
VOID | EnablePchPcieWakeSupport (VOID)
If PCIe native mode is disabled through BIOS setup options, Windows ACPI driver initializes the PM1 enable bits with PCIEXP_WAKE_DIS bit set to 1 provided the flag PCI_EXP_WAK is set in FADT. More...
VOID | EnableFingerPrintSensorWakeSupport (VOID)
Enable FInger Print Sensor Wake Support Default GPIO is configured as GPIO Driver Mode where FPS driver will take care in OS Environment. More...
VOID | OverwriteCpuWakeEnValue (VOID)
Check GPE0_EN_127_96_CPU_WAKE_EN value (bit19 of General Purpose Event 0 Status [127:96] Register), and overwrite it by the value which was saved in platform NVS when OS called Method(_PTS). More...
VOID | WakeOnRTCS5 (VOID)
Enables RTC Wake from S5 and fast startup flow. More...
EFI_STATUS | S3SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S3 Sleep Entry Call Back. More...
EFI_STATUS | S4SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S4 Sleep Entry Call Back. More...
EFI_STATUS | S5SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S5 Sleep Entry Call Back. More...
EFI_STATUS | PowerButtonCallback (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
When a power button event happens, it shuts off the machine. More...
VOID | PchTcoTimeoutCallback (IN EFI_HANDLE DispatchHandle)
This hardware SMI handler will be run every time the BIOS Write Enable bit is set. More...
EFI_STATUS | RegisterTcoTimeoutHandler (VOID)
Register a SMI handler for Tco timeout event. More...
EFI_STATUS | InitializePlatformSmm (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initializes the SMM Platform Driver. More...

Detailed Description

Platform Advanced SMM Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedSmm.c.

Function Documentation

◆ BCDToDec()

UINT8 BCDToDec ( UINT8 BCD )

Converts BCD to Dec number Only for 2 digit BCD.

Parameters
[in] BCD - BCD number which needs to be converted to Dec
Return values
Dec value for given BCD

Definition at line 328 of file PlatformInitAdvancedSmm.c.

◆ DecToBCD()

UINT8 DecToBCD ( UINT8 Dec )

Converts Decimal to BCD Only for 2 digit BCD.

Parameters
[in] Dec - Decimal value to be converted to BCD
Return values
BCD for Dec number

Definition at line 306 of file PlatformInitAdvancedSmm.c.

◆ DisableAcpiCallback()

EFI_STATUS DisableAcpiCallback | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

Disable SCI.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.

Definition at line 267 of file PlatformInitAdvancedSmm.c.

◆ EnableAcpiCallback()

EFI_STATUS EnableAcpiCallback | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN OUT UINTN *CommBufferSize | OPTIONAL
 | ) |  |

Clear Port 80h.

SMI handler to enable ACPI mode

Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI

Disables the SW SMI Timer. ACPI events are disabled and ACPI event status is cleared. SCI mode is then enabled.

Clear SLP SMI status Enable SLP SMI

Disable SW SMI Timer

Clear all ACPI event status and disable all ACPI events

Disable PM sources except power button Clear status bits

Disable GPE0 sources Clear status bits

Disable GPE1 sources Clear status bits

Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)

Enable SCI

Set 8254 timer clock gate enable if it's not set in early phase

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.

Definition at line 142 of file PlatformInitAdvancedSmm.c.

◆ EnableFingerPrintSensorWakeSupport()

VOID EnableFingerPrintSensorWakeSupport ( VOID )

Enable FInger Print Sensor Wake Support Default GPIO is configured as GPIO Driver Mode where FPS driver will take care in OS Environment.

Here Enable Wake support by reconfiguring the GPIO with SCI Capability

Parameters
[in] VOID
Return values
VOID

Definition at line 570 of file PlatformInitAdvancedSmm.c.

◆ EnablePchPcieWakeSupport()

VOID EnablePchPcieWakeSupport ( VOID )

If PCIe native mode is disabled through BIOS setup options, Windows ACPI driver initializes the PM1 enable bits with PCIEXP_WAKE_DIS bit set to 1 provided the flag PCI_EXP_WAK is set in FADT.

If the FADT flag is not set then Windows will not set the PCIEXP_WAKE_DIS bit.

In summary OS is setting PCIEXP_WAKE_DIS if native PCIe support is disabled.

To mitigate the wake issue bios will clear this bit in case of Sx entry which will allow system to detect any wake event from Add in card."

Parameters
[in] VOID
Return values
VOID

Definition at line 532 of file PlatformInitAdvancedSmm.c.

◆ EnablePchTier2GpioWakeSupport()

EFI_STATUS EnablePchTier2GpioWakeSupport ( VOID )

Enable wake capability for that wake delivered via tier2 GPIO.

Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 485 of file PlatformInitAdvancedSmm.c.

◆ InitializePlatformSmm()

EFI_STATUS InitializePlatformSmm | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initializes the SMM Platform Driver.

Parameters
[in] | ImageHandle | - Pointer to the loaded image protocol for this driver
[in] | SystemTable | - Pointer to the EFI System Table
Return values
Status - EFI_SUCCESS
Assert,otherwise.

Definition at line 1207 of file PlatformInitAdvancedSmm.c.

◆ OverwriteCpuWakeEnValue()

VOID OverwriteCpuWakeEnValue ( VOID )

Check GPE0_EN_127_96_CPU_WAKE_EN value (bit19 of General Purpose Event 0 Status [127:96] Register), and overwrite it by the value which was saved in platform NVS when OS called Method(_PTS).

Parameters
[in] VOID
Return values
VOID

Definition at line 609 of file PlatformInitAdvancedSmm.c.

◆ PchTcoTimeoutCallback()

VOID PchTcoTimeoutCallback ( IN EFI_HANDLE DispatchHandle )

This hardware SMI handler will be run every time the BIOS Write Enable bit is set.

Parameters
[in] DispatchHandle Not used

Definition at line 974 of file PlatformInitAdvancedSmm.c.

◆ PowerButtonCallback()

EFI_STATUS PowerButtonCallback | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

When a power button event happens, it shuts off the machine.

Parameters
[in] | DispatchHandle | - Handle of this dispatch function
[in] | DispatchContext | - Pointer to the dispatch function's context
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 907 of file PlatformInitAdvancedSmm.c.

◆ ReadRtcIndex()

UINT8 ReadRtcIndex ( IN UINT8 Index )

Reads the RTC Index register.

Parameters
[in] Index - Index register
Return values
Value in Index register

Definition at line 348 of file PlatformInitAdvancedSmm.c.

◆ RegisterTcoTimeoutHandler()

EFI_STATUS RegisterTcoTimeoutHandler ( VOID )

Register a SMI handler for Tco timeout event.

Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid pointer passed.

Definition at line 1006 of file PlatformInitAdvancedSmm.c.

◆ S3SleepEntryCallBack()

EFI_STATUS S3SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S3 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 702 of file PlatformInitAdvancedSmm.c.

◆ S4SleepEntryCallBack()

EFI_STATUS S4SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S4 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 770 of file PlatformInitAdvancedSmm.c.

◆ S5SleepEntryCallBack()

EFI_STATUS S5SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S5 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 832 of file PlatformInitAdvancedSmm.c.

◆ WakeOnRTCS5()

VOID WakeOnRTCS5 ( VOID )

Enables RTC Wake from S5 and fast startup flow.

Parameters
[in] VOID
Return values
VOID

Definition at line 643 of file PlatformInitAdvancedSmm.c.

Here is the call graph for this function:

◆ WriteRtcIndex()

VOID WriteRtcIndex | ( | IN UINT8 | Index,
 |  | IN UINT8 | Value
 | ) |  |

Writes to an RTC Index register.

Parameters
[in] | Index | - Index to be written
[in] | Value | - Value to be written to Index register

Definition at line 414 of file PlatformInitAdvancedSmm.c.


AlderLake Platform Sample Code: PlatformInitAdvancedSmm.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PlatformInitAdvancedSmm.c
Go to the documentation of this file.
1 /** @file
2 Platform Advanced SMM Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #include "PlatformInitAdvancedSmm.h"
36 #include <OemSetup.h>
37 #include <CpuRegs.h>
38 #include <PchPolicyCommon.h>
39 #include "PcieDockSmi.h"
40 #include "PlatformBoardId.h"
41 #include "AcpiCommon.h"
42
43 #include <Library/PmcLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <Library/GpioLib.h>
46 #include <Library/ItssLib.h>
47 #include <Library/TimerLib.h>
48 #include <Register/MeRegs.h>
49 #include <Register/HeciRegs.h>
50 #include <Protocol/PchTcoSmiDispatch.h>
51 #include <Protocol/SmmVariable.h>
52 #include <Protocol/SmmCpu.h>
53 #include <Library/PostCodeLib.h>
54 #include <PlatformPostCode.h>
55 #include <Register/PchRegs.h>
56 #include <Register/PchRegsLpc.h>
57 #include <Register/PmcRegs.h>
58 #include <Register/RtcRegs.h>
59 #include <Library/PchPciBdfLib.h>
60 #include <Register/CommonMsr.h>
61 #if FixedPcdGetBool(PcdCapsuleEnable) == 1
62 #include <Library/HobLib.h>
63 #include <Library/TopSwapLib.h>
64 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
65 #include <SiConfigHob.h>
66 #endif
67 #endif
68
69
70 //
71 // Global variables
72 //
73 GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
74
75 GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
76 GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA *mPlatformNvsAreaPtr = 0;
77 GLOBAL_REMOVE_IF_UNREFERENCED EFI_ACPI_SMM_DEV mAcpiSmm;
78 //
79 // Setup variables
80 //
81 GLOBAL_REMOVE_IF_UNREFERENCED SETUP_DATA mSystemConfiguration;
82 GLOBAL_REMOVE_IF_UNREFERENCED PCH_SETUP mPchSetup;
83 //
84 // HMRFPO lock output parameters
85 //
86
87 GLOBAL_REMOVE_IF_UNREFERENCED EFI_EC_ACCESS_PROTOCOL *mEcAccess = NULL;
88
89 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPlatformFlavor;
90 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mBoardType;
91 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mEcPresent;
92 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mEcHandshakeEnable;
93 GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpu;
94
95 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mEctoPdControllerNegotiationInSx = 0;
96 GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mFpsWakeGpio = 0;
97 GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mGpioTier2WakeSupport;
98 #if FixedPcdGetBool(PcdCapsuleEnable) == 1
99 GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mEndOfDxe = FALSE;
100 #endif
101 /**
102 Clear Port 80h
103
104 SMI handler to enable ACPI mode
105
106 Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
107
108 Disables the SW SMI Timer.
109 ACPI events are disabled and ACPI event status is cleared.
110 SCI mode is then enabled.
111
112 Clear SLP SMI status
113 Enable SLP SMI
114
115 Disable SW SMI Timer
116
117 Clear all ACPI event status and disable all ACPI events
118
119 Disable PM sources except power button
120 Clear status bits
121
122 Disable GPE0 sources
123 Clear status bits
124
125 Disable GPE1 sources
126 Clear status bits
127
128 Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
129
130 Enable SCI
131
132 Set 8254 timer clock gate enable if it's not set in early phase
133
134 @param[in] DispatchHandle - The handle of this callback, obtained when registering
135 @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
136 @param[in] CommBuffer - A pointer to a collection of data in memory that will
137 be conveyed from a non-SMM environment into an SMM environment.
138 @param[in] CommBufferSize - The size of the CommBuffer.
139 **/
140 EFI_STATUS
141 EFIAPI
142 EnableAcpiCallback (
143 IN EFI_HANDLE DispatchHandle,
144 IN CONST VOID *DispatchContext,
145 IN OUT VOID *CommBuffer OPTIONAL,
146 IN OUT UINTN *CommBufferSize OPTIONAL
147 )
148 {
149 UINT32 OutputValue;
150 UINT32 Pm1Cnt;
151 EFI_STATUS Status;
152
153 Status = EFI_SUCCESS;
154 //
155 // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
156 // OS in order to prevent the host from issuing global resets and resetting ME
157 //
158 // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
159 // MmioWrite32 (
160 // PmcBaseAddress + R_PCH_PMC_ETR3),
161 // PmInit);
162
163 //
164 // Clear Port 80h
165 //
166 OutputValue = 0;
167 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
168
169 //
170 // Disable PM sources except power button
171 //
172 OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
173 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
174 //
175 // Clear PM status except Power Button status for RapidStart Resume
176 //
177 // OutputValue = 0xFFFF;
178 OutputValue = 0xFEFF;
179 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
180
181 //
182 // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
183 //
184 OutputValue = R_RTC_IO_REGD;
185 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
186 OutputValue = 0x0;
187 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
188
189 //
190 // Enable SCI
191 //
192 mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
193 Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
194 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
195
196 if (mEcPresent == 1) {
197 //
198 // Check the power state from EC and update it to global NVS area
199 //
200 if (PowerStateIsAc ()) {
201 mPlatformNvsAreaPtr->PowerState = 1;
202 } else {
203 mPlatformNvsAreaPtr->PowerState = 0;
204 }
205
206 //
207 // Disable SMI mode
208 //
209 Status = DisableEcSmiMode ();
210 ASSERT_EFI_ERROR (Status);
211
212 //
213 // Commands EC to begin reading Thermal Diode and comparing to Critical Temperature.
214 // Shutdown will occur when current temp equals or exceeds Critical temperature.
215 //
216 Status = EnableEcAcpiMode (TRUE);
217 ASSERT_EFI_ERROR (Status);
218
219 //
220 // send command to EC to enable/disable ALS
221 //
222 if (mEcAccess != NULL) {
223 mEcAccess->SMINotifyDisable ();
224 mEcAccess->AcpiEnable ();
225 }
226 }
227
228 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
229 //
230 // Enable embedded specific stuff
231 //
232 if (mPlatformFlavor == FlavorEmbedded) {
233 mPlatformNvsAreaPtr->PowerState = 0;
234 }
235 #endif
236 PlatformSpecificAcpiEnableHook ();
237 //
238 // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
239 //
240 OutputValue = 0;
241 mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
242 OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
243 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
244
245 //
246 // Set 8254 timer clock gate enable if it's not set in early phase
247 //
248 if ((mPchSetup.Enable8254ClockGating != 1) && (mPchSetup.PchLegacyIoLowLatency != 1)) {
249 Status = ItssSet8254ClockGateState (TRUE);
250 ASSERT_EFI_ERROR (Status);
251 }
252
253 return Status;
254 }
255
256 /**
257 Disable SCI
258
259 @param[in] DispatchHandle - The handle of this callback, obtained when registering
260 @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
261 @param[in] CommBuffer - A pointer to a collection of data in memory that will
262 be conveyed from a non-SMM environment into an SMM environment.
263 @param[in] CommBufferSize - The size of the CommBuffer.
264 **/
265 EFI_STATUS
266 EFIAPI
267 DisableAcpiCallback (
268 IN EFI_HANDLE DispatchHandle,
269 IN CONST VOID *DispatchContext,
270 IN OUT VOID *CommBuffer OPTIONAL,
271 IN UINTN *CommBufferSize OPTIONAL
272 )
273 {
274 UINT32 Pm1Cnt;
275 EFI_STATUS Status;
276
277 //
278 // Disable SCI
279 //
280 mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
281 Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
282 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
283
284 //
285 // Disable mobile specific stuff
286 //
287 PlatformSpecificAcpiDisableHook ();
288 //
289 // Take EC out of ACPI Mode.
290 //
291 Status = EnableEcAcpiMode (FALSE);
292 ASSERT_EFI_ERROR (Status);
293
294 return Status;
295 }
296
297 /**
298 Converts Decimal to BCD
299 Only for 2 digit BCD.
300
301 @param[in] Dec - Decimal value to be converted to BCD
302
303 @retval BCD for Dec number
304 **/
305 UINT8
306 DecToBCD (
307 UINT8 Dec
308 )
309 {
310 UINT8 FirstDigit;
311 UINT8 SecondDigit;
312
313 FirstDigit = Dec % 10;
314 SecondDigit = Dec / 10;
315
316 return (SecondDigit << 4) + FirstDigit;
317 }
318
319 /**
320 Converts BCD to Dec number
321 Only for 2 digit BCD.
322
323 @param[in] BCD - BCD number which needs to be converted to Dec
324
325 @retval Dec value for given BCD
326 **/
327 UINT8
328 BCDToDec (
329 UINT8 BCD
330 )
331 {
332 UINT8 FirstDigit;
333 UINT8 SecondDigit;
334 FirstDigit = BCD & 0xf;
335 SecondDigit = BCD >> 4;
336
337 return SecondDigit * 10 + FirstDigit;
338 }
339
340 /**
341 Reads the RTC Index register
342
343 @param[in] Index - Index register
344
345 @retval Value in Index register
346 **/
347 UINT8
348 ReadRtcIndex (
349 IN UINT8 Index
350 )
351 {
352 UINT8 Value;
353 UINT8 Addr;
354
355 //
356 // Use port RTC alternative ports 74h/75h to prevent from breaking NMI setting
357 //
358
359 //
360 // Check if Data Time is valid
361 //
362 if (Index <= 9) {
363 do {
364 Addr = 0x0A;
365 mSmst->SmmIo.Io.Write (
366 &mSmst->SmmIo,
367 SMM_IO_UINT8,
368 R_RTC_IO_INDEX_ALT,
369 1,
370 &Addr
371 );
372 mSmst->SmmIo.Io.Read (
373 &mSmst->SmmIo,
374 SMM_IO_UINT8,
375 R_RTC_IO_TARGET_ALT,
376 1,
377 &Value
378 );
379 } while (Value & 0x80);
380 }
381
382 Addr = Index;
383 mSmst->SmmIo.Io.Write (
384 &mSmst->SmmIo,
385 SMM_IO_UINT8,
386 R_RTC_IO_INDEX_ALT,
387 1,
388 &Addr
389 );
390 //
391 // Read register.
392 //
393 mSmst->SmmIo.Io.Read (
394 &mSmst->SmmIo,
395 SMM_IO_UINT8,
396 R_RTC_IO_TARGET_ALT,
397 1,
398 &Value
399 );
400 if (Index <= 9) {
401 Value = BCDToDec (Value);
402 }
403
404 return (UINT8) Value;
405 }
406
407 /**
408 Writes to an RTC Index register
409
410 @param[in] Index - Index to be written
411 @param[in] Value - Value to be written to Index register
412 **/
413 VOID
414 WriteRtcIndex (
415 IN UINT8 Index,
416 IN UINT8 Value
417 )
418 {
419 UINT8 Addr;
420
421 //
422 // Use port RTC alternative ports 74h/75h to prevent from breaking NMI setting
423 //
424
425 Addr = Index;
426 mSmst->SmmIo.Io.Write (
427 &mSmst->SmmIo,
428 SMM_IO_UINT8,
429 R_RTC_IO_INDEX_ALT,
430 1,
431 &Addr
432 );
433 if (Index <= 9) {
434 Value = DecToBCD (Value);
435 }
436 //
437 // Write Register.
438 //
439 mSmst->SmmIo.Io.Write (
440 &mSmst->SmmIo,
441 SMM_IO_UINT8,
442 R_RTC_IO_TARGET_ALT,
443 1,
444 &Value
445 );
446 }
447
448 /**
449 Disable RTC alarm and clear RTC PM1 status.
450
451 **/
452 VOID
453 InitRtcWakeup (
454 VOID
455 )
456 {
457 UINT16 Data16;
458
459 //
460 // Clear Alarm Flag (AF) by reading RTC Reg C
461 //
462 mSmst->SmmIo.Io.Read (
463 &mSmst->SmmIo,
464 SMM_IO_UINT16,
465 mAcpiBaseAddr + R_ACPI_IO_PM1_STS,
466 1,
467 &Data16
468 );
469 Data16 = Data16 | B_ACPI_IO_PM1_STS_RTC;
470 mSmst->SmmIo.Io.Write (
471 &mSmst->SmmIo,
472 SMM_IO_UINT16,
473 mAcpiBaseAddr + R_ACPI_IO_PM1_STS,
474 1,
475 &Data16
476 );
477 }
478
479 /**
480 Enable wake capability for that wake delivered via tier2 GPIO
481
482 @retval EFI_SUCCESS - Operation successfully performed
483 **/
484 EFI_STATUS
485 EnablePchTier2GpioWakeSupport (
486 VOID
487 )
488 {
489
490 UINT16 Data16;
491
492 if (!mGpioTier2WakeSupport) {
493 return EFI_UNSUPPORTED;
494 }
495
496 //
497 // Enable wake capability when device is present
498 //
499 mSmst->SmmIo.Io.Read (
500 &mSmst->SmmIo,
501 SMM_IO_UINT16,
502 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
503 1,
504 &Data16
505 );
506 Data16 = Data16 | B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2;
507 mSmst->SmmIo.Io.Write (
508 &mSmst->SmmIo,
509 SMM_IO_UINT16,
510 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
511 1,
512 &Data16
513 );
514
515 return EFI_SUCCESS;
516 }
517
518 /**
519 If PCIe native mode is disabled through BIOS setup options,
520 Windows ACPI driver initializes the PM1 enable bits with PCIEXP_WAKE_DIS bit set to 1 provided the flag PCI_EXP_WAK is set in FADT.
521 If the FADT flag is not set then Windows will not set the PCIEXP_WAKE_DIS bit.
522
523 In summary OS is setting PCIEXP_WAKE_DIS if native PCIe support is disabled.
524
525 To mitigate the wake issue bios will clear this bit in case of Sx entry which will allow system to detect any wake event from Add in card."
526
527 @param[in] VOID
528
529 @retval VOID
530 **/
531 VOID
532 EnablePchPcieWakeSupport (
533 VOID
534 )
535 {
536
537 UINT16 Data16;
538
539 if (!(mSystemConfiguration.PciExpNative)) {
540 mSmst->SmmIo.Io.Read (
541 &mSmst->SmmIo,
542 SMM_IO_UINT16,
543 mAcpiBaseAddr + R_ACPI_IO_PM1_EN,
544 1,
545 &Data16
546 );
547 Data16 = Data16 & (UINT16)~BIT14;
548 mSmst->SmmIo.Io.Write (
549 &mSmst->SmmIo,
550 SMM_IO_UINT16,
551 mAcpiBaseAddr + R_ACPI_IO_PM1_EN,
552 1,
553 &Data16
554 );
555 }
556 }
557
558 #define FPS_FPC1021 06
559
560 /**
561 Enable FInger Print Sensor Wake Support
562 Default GPIO is configured as GPIO Driver Mode where FPS driver will take care in OS Environment.
563 Here Enable Wake support by reconfiguring the GPIO with SCI Capability
564
565 @param[in] VOID
566
567 @retval VOID
568 **/
569 VOID
570 EnableFingerPrintSensorWakeSupport (
571 VOID
572 )
573 {
574 UINT32 Data32;
575 GPIO_CONFIG FpsDevicereadypin = { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone };
576 if ((mSystemConfiguration.PchSpiFingerPrintType == FPS_FPC1021) && (mFpsWakeGpio)) {
577 //
578 // Enable GPIO Tier 2 SCI Before entering into Sx (incase if not enabled already)
579 //
580 mSmst->SmmIo.Io.Read (
581 &mSmst->SmmIo,
582 SMM_IO_UINT32,
583 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
584 1,
585 &Data32
586 );
587 Data32 = Data32 | (UINT32) (BIT15);
588 mSmst->SmmIo.Io.Write (
589 &mSmst->SmmIo,
590 SMM_IO_UINT32,
591 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
592 1,
593 &Data32
594 );
595 GpioSetPadConfig (mFpsWakeGpio, &FpsDevicereadypin);
596 }
597 }
598 #define DDR3_STANDBY_PWR_GPIO_PIN 0 // Platform specific @ TBD
599
600 /**
601 Check GPE0_EN_127_96_CPU_WAKE_EN value (bit19 of General Purpose Event 0 Status [127:96] Register),
602 and overwrite it by the value which was saved in platform NVS when OS called Method(_PTS).
603
604 @param[in] VOID
605
606 @retval VOID
607 **/
608 VOID
609 OverwriteCpuWakeEnValue (
610 VOID
611 )
612 {
613 UINT32 WakeRegU32 = 0;
614 UINT32 NvsCpuWakeEnValue = 0;
615
616 DEBUG ((DEBUG_INFO, "[SMM_SLEEP]OverwriteCpuWakeEnValue()\n"));
617
618 mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96, 1, &WakeRegU32);
619 DEBUG ((DEBUG_INFO, " mAcpiBaseAddr[0x%X]+GPE0_EN_127_96[0x%X] = 0x%08X\n", mAcpiBaseAddr, R_ACPI_IO_GPE0_EN_127_96, WakeRegU32));
620
621 NvsCpuWakeEnValue = (mPlatformNvsAreaPtr->CpuWakeEnFlag) << 19;
622 DEBUG ((DEBUG_INFO, " CpuWakeEn saved in NVS = 0x%X\n", mPlatformNvsAreaPtr->CpuWakeEnFlag));
623
624 while ((WakeRegU32 & B_ACPI_IO_GPE0_STS_127_96_CPU_WAKE_EN) != NvsCpuWakeEnValue) {
625 DEBUG ((DEBUG_INFO, "Overwrite CpuWakeEn value.\n"));
626 WakeRegU32 = (WakeRegU32 & ~B_ACPI_IO_GPE0_STS_127_96_CPU_WAKE_EN) | NvsCpuWakeEnValue;
627 mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96, 1, &WakeRegU32);
628 DEBUG ((DEBUG_INFO, " Write mAcpiBaseAddr + GPE0_EN_127_96 = 0x%08X\n", WakeRegU32));
629
630 mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96, 1, &WakeRegU32);
631 DEBUG ((DEBUG_INFO, " Read mAcpiBaseAddr + GPE0_EN_127_96 = 0x%08X\n", WakeRegU32));
632 }
633 }
634
635 /**
636 Enables RTC Wake from S5 and fast startup flow.
637
638 @param[in] VOID
639
640 @retval VOID
641 **/
642 VOID
643 WakeOnRTCS5 (
644 VOID
645 )
646 {
647 UINT16 Data16;
648 UINT8 RtcInterruptBit;
649 RtcInterruptBit = ReadRtcIndex(0x0B) & BIT5;
650 if (mSystemConfiguration.WakeOnRTCS5 == 1 && RtcInterruptBit) {
651 //
652 // Clear RTC PM1 status
653 //
654 mSmst->SmmIo.Io.Read (
655 &mSmst->SmmIo,
656 SMM_IO_UINT16,
657 mAcpiBaseAddr + R_ACPI_IO_PM1_STS,
658 1,
659 &Data16
660 );
661 Data16 = Data16 | B_ACPI_IO_PM1_STS_RTC;
662 mSmst->SmmIo.Io.Write (
663 &mSmst->SmmIo,
664 SMM_IO_UINT16,
665 mAcpiBaseAddr + R_ACPI_IO_PM1_STS,
666 1,
667 &Data16
668 );
669 //
670 // set RTC_EN bit in PM1_EN to wake up from the alarm
671 //
672 mSmst->SmmIo.Io.Read (
673 &mSmst->SmmIo,
674 SMM_IO_UINT16,
675 mAcpiBaseAddr + R_ACPI_IO_PM1_EN,
676 1,
677 &Data16
678 );
679 Data16 = Data16 | B_ACPI_IO_PM1_EN_RTC;
680 mSmst->SmmIo.Io.Write (
681 &mSmst->SmmIo,
682 SMM_IO_UINT16,
683 mAcpiBaseAddr + R_ACPI_IO_PM1_EN,
684 1,
685 &Data16
686 );
687 }
688 }
689 /**
690 S3 Sleep Entry Call Back.
691
692 @param[in] DispatchHandle - The handle of this callback, obtained when registering
693 @param[in] DispatchContext - The predefined context which contained sleep type and phase
694 @param[in] CommBuffer - A pointer to a collection of data in memory that will
695 be conveyed from a non-SMM environment into an SMM environment.
696 @param[in] CommBufferSize - The size of the CommBuffer.
697
698 @retval EFI_SUCCESS - Operation successfully performed
699 **/
700 EFI_STATUS
701 EFIAPI
702 S3SleepEntryCallBack (
703 IN EFI_HANDLE DispatchHandle,
704 IN CONST VOID *DispatchContext,
705 IN OUT VOID *CommBuffer OPTIONAL,
706 IN UINTN *CommBufferSize OPTIONAL
707 )
708 {
709 UINT8 EcDataBuffer;
710 UINT32 Timeout;
711
712 PostCode (BIOS_S3_ENTRY);
713
714 EcDataBuffer = 0x03; // Input: 0x03 S3, 0x04 S4, 0x05S5
715 if (mEctoPdControllerNegotiationInSx) {
716 //
717 // Send this EC command from SMM to notify EC and wait for response (EC_C_USBC_SX_ENTRY_WAIT for Sx Entry)
718 //
719 if (mPlatformFlavor == FlavorDesktop && mEcHandshakeEnable == 1) {
720 Timeout = mSystemConfiguration.UsbcSxEntryTimeout;
721 UsbcSxEntry (&EcDataBuffer, Timeout);
722 }
723 }
724 //
725 // Enable Wakesupport for PCIE Add-on Cards when Native support is disabled
726 //
727 EnablePchPcieWakeSupport ();
728
729 //
730 // Enable Finger Print Sensor Wake support
731 //
732 EnableFingerPrintSensorWakeSupport ();
733
734 if ((mPlatformFlavor == FlavorMobile) || (mPlatformFlavor == FlavorEmbedded)) {
735 //
736 // This GPIO operation is designed to take care of DDR3 Standby Power Reduction
737 // PullDown GPIO
738 //
739 //GpioSetPadElectricalConfig (DDR3_STANDBY_PWR_GPIO_PIN, GpioTermNone); //@todo, uncomment when DDR3_STANDBY_PWR_GPIO_PIN has been assigned correct GpioPad
740 }
741
742 //
743 // Enable Tier2 GPIO Wake support
744 //
745 EnablePchTier2GpioWakeSupport ();
746 #if FixedPcdGetBool(PcdITbtEnable) == 1
747 OverwriteCpuWakeEnValue ();
748 #endif
749
750 //
751 // WARNING!!! Please do not modify GP_LVL register after this point
752 //
753
754 return EFI_SUCCESS;
755 }
756
757 /**
758 S4 Sleep Entry Call Back.
759
760 @param[in] DispatchHandle - The handle of this callback, obtained when registering
761 @param[in] DispatchContext - The predefined context which contained sleep type and phase
762 @param[in] CommBuffer - A pointer to a collection of data in memory that will
763 be conveyed from a non-SMM environment into an SMM environment.
764 @param[in] CommBufferSize - The size of the CommBuffer.
765
766 @retval EFI_SUCCESS - Operation successfully performed
767 **/
768 EFI_STATUS
769 EFIAPI
770 S4SleepEntryCallBack (
771 IN EFI_HANDLE DispatchHandle,
772 IN CONST VOID *DispatchContext,
773 IN OUT VOID *CommBuffer OPTIONAL,
774 IN UINTN *CommBufferSize OPTIONAL
775 )
776 {
777 UINT8 EcDataBuffer;
778 UINT32 Timeout;
779
780 PostCode (BIOS_S4_ENTRY);
781
782 //
783 // Put EC in non-ACPI mode. This ensures EC takes over FAN control from now on till actual shutdown.
784 //
785 EnableEcAcpiMode (FALSE);
786 if (mEctoPdControllerNegotiationInSx) {
787
788 EcDataBuffer = 0x04; // Input: 0x03 S3, 0x04 S4, 0x05 S5
789 //
790 // Send this EC command from SMM to notify EC and wait for response (EC_C_USBC_SX_ENTRY_WAIT for Sx Entry)
791 //
792 if (mPlatformFlavor == FlavorDesktop && mEcHandshakeEnable == 1) {
793 Timeout = mSystemConfiguration.UsbcSxEntryTimeout;
794 UsbcSxEntry (&EcDataBuffer, Timeout);
795 }
796 }
797 //
798 // Enable Wakesupport for PCIE Add-on Cards when Native support is disabled
799 //
800 EnablePchPcieWakeSupport ();
801 //
802 // WARNING!!! Please do not modify GP_LVL register after this point
803 //
804
805 //
806 // Enable Tier2 GPIO Wake support
807 //
808 EnablePchTier2GpioWakeSupport ();
809
810 WakeOnRTCS5();
811
812 #if FixedPcdGetBool(PcdITbtEnable) == 1
813 OverwriteCpuWakeEnValue ();
814 #endif
815
816 return EFI_SUCCESS;
817 }
818
819 /**
820 S5 Sleep Entry Call Back.
821
822 @param[in] DispatchHandle - The handle of this callback, obtained when registering
823 @param[in] DispatchContext - The predefined context which contained sleep type and phase
824 @param[in] CommBuffer - A pointer to a collection of data in memory that will
825 be conveyed from a non-SMM environment into an SMM environment.
826 @param[in] CommBufferSize - The size of the CommBuffer.
827
828 @retval EFI_SUCCESS - Operation successfully performed
829 **/
830 EFI_STATUS
831 EFIAPI
832 S5SleepEntryCallBack (
833 IN EFI_HANDLE DispatchHandle,
834 IN CONST VOID *DispatchContext,
835 IN OUT VOID *CommBuffer OPTIONAL,
836 IN UINTN *CommBufferSize OPTIONAL
837 )
838 {
839 UINT32 Data32;
840 UINT8 EcDataBuffer;
841 UINT32 Timeout;
842
843 PostCode (BIOS_S5_ENTRY);
844
845 //
846 // Put EC in non-ACPI mode. This ensures EC takes over FAN control from now on till actual shutdown.
847 //
848 EnableEcAcpiMode (FALSE);
849
850 EcDataBuffer = 0x05; // Input: 0x03 S3, 0x04 S4, 0x05 S5
851 if (mEctoPdControllerNegotiationInSx) {
852 //
853 // Send this EC command from SMM to notify EC and wait for response (EC_C_USBC_SX_ENTRY_WAIT for Sx Entry)
854 //
855
856 if (mPlatformFlavor == FlavorDesktop && mEcHandshakeEnable == 1) {
857 Timeout = mSystemConfiguration.UsbcSxEntryTimeout;
858 UsbcSxEntry (&EcDataBuffer, Timeout);
859 }
860 }
861 //
862 // Enable Wakesupport for PCIE Add-on Cards when Native support is disabled
863 //
864 EnablePchPcieWakeSupport ();
865
866 WakeOnRTCS5();
867 //
868 // Read GPE0 enable register and set PME_B0 enable (bit 13) to enable
869 // WOL from S5 state.
870 //
871 mSmst->SmmIo.Io.Read (
872 &mSmst->SmmIo,
873 SMM_IO_UINT32,
874 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
875 1,
876 &Data32
877 );
878 Data32 |= BIT13;
879 mSmst->SmmIo.Io.Write (
880 &mSmst->SmmIo,
881 SMM_IO_UINT32,
882 mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96,
883 1,
884 &Data32
885 );
886
887 //
888 // WARNING!!! Please do not modify GP_LVL register after this point
889 //
890
891 return EFI_SUCCESS;
892 }
893
894 /**
895 When a power button event happens, it shuts off the machine
896
897 @param[in] DispatchHandle - Handle of this dispatch function
898 @param[in] DispatchContext - Pointer to the dispatch function's context
899 @param[in] CommBuffer - A pointer to a collection of data in memory that will
900 be conveyed from a non-SMM environment into an SMM environment.
901 @param[in] CommBufferSize - The size of the CommBuffer.
902
903 @retval EFI_SUCCESS - Operation successfully performed
904 **/
905 EFI_STATUS
906 EFIAPI
907 PowerButtonCallback (
908 IN EFI_HANDLE DispatchHandle,
909 IN CONST VOID *DispatchContext,
910 IN OUT VOID *CommBuffer OPTIONAL,
911 IN UINTN *CommBufferSize OPTIONAL
912 )
913 {
914 UINT32 Buffer;
915 UINT16 Data16;
916
917 //
918 // Clear Power Button Status
919 //
920 Data16 = B_ACPI_IO_PM1_STS_PWRBTN;
921 mSmst->SmmIo.Io.Write (
922 &mSmst->SmmIo,
923 SMM_IO_UINT16,
924 mAcpiBaseAddr + R_ACPI_IO_PM1_STS,
925 1,
926 &Data16
927 );
928
929 //
930 // Shut it off now
931 //
932 mSmst->SmmIo.Io.Read (
933 &mSmst->SmmIo,
934 SMM_IO_UINT32,
935 mAcpiBaseAddr + R_ACPI_IO_PM1_CNT,
936 1,
937 &Buffer
938 );
939 Buffer &= ~(B_ACPI_IO_PM1_CNT_SLP_EN | B_ACPI_IO_PM1_CNT_SLP_TYP);
940
941 Buffer |= V_ACPI_IO_PM1_CNT_S5;
942
943 mSmst->SmmIo.Io.Write (
944 &mSmst->SmmIo,
945 SMM_IO_UINT32,
946 mAcpiBaseAddr + R_ACPI_IO_PM1_CNT,
947 1,
948 &Buffer
949 );
950
951
952 Buffer |= B_ACPI_IO_PM1_CNT_SLP_EN;
953
954 mSmst->SmmIo.Io.Write (
955 &mSmst->SmmIo,
956 SMM_IO_UINT32,
957 mAcpiBaseAddr + R_ACPI_IO_PM1_CNT,
958 1,
959 &Buffer
960 );
961
962 return EFI_SUCCESS;
963 }
964
965
966 /**
967 This hardware SMI handler will be run every time the BIOS Write Enable bit is set.
968
969 @param[in] DispatchHandle Not used
970
971 **/
972 VOID
973 EFIAPI
974 PchTcoTimeoutCallback (
975 IN EFI_HANDLE DispatchHandle
976 )
977 {
978
979 DEBUG((DEBUG_INFO, "PchTcoTimeoutCallback entry\n"));
980
981
982 //
983 // Stall for 3 seconds to trigger the second timeout.
984 //
985 MicroSecondDelay (3000 * 1000);
986
987 //
988 // A catastrophic crash happened (causing TCO timeout) when we reach here
989 // Directly trigger a warm reboot here
990 //
991 IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET);
992
993 CpuDeadLoop ();
994
995 return;
996 }
997
998 /**
999 Register a SMI handler for Tco timeout event.
1000
1001 @retval EFI_SUCCESS Successfully completed.
1002 @retval EFI_INVALID_PARAMETER Invalid pointer passed.
1003 **/
1004 EFI_STATUS
1005 EFIAPI
1006 RegisterTcoTimeoutHandler (
1007 VOID
1008 )
1009 {
1010 EFI_STATUS Status;
1011 PCH_TCO_SMI_DISPATCH_PROTOCOL *mPchTcoSmiDispatchProtocol;
1012 EFI_HANDLE Handle;
1013
1014 Status = mSmst->SmmLocateProtocol (&gPchTcoSmiDispatchProtocolGuid, NULL, (VOID **) &mPchTcoSmiDispatchProtocol);
1015
1016 Handle = NULL;
1017 Status = mPchTcoSmiDispatchProtocol->TcoTimeoutRegister (
1018 mPchTcoSmiDispatchProtocol,
1019 PchTcoTimeoutCallback,
1020 &Handle
1021 );
1022 DEBUG((DEBUG_INFO, "RegisterTcoTimeoutHandler status = %x\n", Status));
1023
1024 return Status;
1025 }
1026
1027 #if FixedPcdGetBool(PcdCapsuleEnable) == 1
1028 /**
1029 SMM END_OF_DXE protocol notification event handler.
1030
1031 @param Protocol Points to the protocol's unique identifier
1032 @param Interface Points to the interface instance
1033 @param Handle The handle on which the interface was installed
1034
1035 @retval EFI_SUCCESS SmmEndOfDxeCallback runs successfully
1036
1037 **/
1038 EFI_STATUS
1039 EFIAPI
1040 SmmEndOfDxeCallback (
1041 IN CONST EFI_GUID *Protocol,
1042 IN VOID *Interface,
1043 IN EFI_HANDLE Handle
1044 )
1045 {
1046 DEBUG ((DEBUG_INFO, "[SmmPlatform]SMM_END_OF_DXE is signaled\n"));
1047 mEndOfDxe = TRUE;
1048
1049 return EFI_SUCCESS;
1050 }
1051
1052 /**
1053 Software SMI callback to set TopSwap bit. Only allowed to access TopSwap bit before EndOfDxe.
1054
1055 @param[in] DispatchHandle The unique handle assigned to this handler by SmiHandlerRegister().
1056 @param[in] DispatchContext Points to an optional handler context which was specified when the
1057 handler was registered.
1058 @param[in, out] CommBuffer A pointer to a collection of data in memory that will
1059 be conveyed from a non-SMM environment into an SMM environment.
1060 @param[in, out] CommBufferSize The size of the CommBuffer.
1061
1062 @retval EFI_SUCCESS The interrupt was handled successfully.
1063
1064 **/
1065 EFI_STATUS
1066 EFIAPI
1067 EnableTopSwapCallback (
1068 IN EFI_HANDLE DispatchHandle,
1069 IN CONST VOID *DispatchContext,
1070 IN OUT VOID *CommBuffer OPTIONAL,
1071 IN OUT UINTN *CommBufferSize OPTIONAL
1072 )
1073 {
1074 if (!mEndOfDxe) {
1075 TopSwapSet (TRUE);
1076 }
1077
1078 return EFI_SUCCESS;
1079 }
1080
1081 /**
1082 Software SMI callback to clear TopSwap bit. Only allowed to access TopSwap bit before EndOfDxe.
1083
1084 @param[in] DispatchHandle The unique handle assigned to this handler by SmiHandlerRegister().
1085 @param[in] DispatchContext Points to an optional handler context which was specified when the
1086 handler was registered.
1087 @param[in, out] CommBuffer A pointer to a collection of data in memory that will
1088 be conveyed from a non-SMM environment into an SMM environment.
1089 @param[in, out] CommBufferSize The size of the CommBuffer.
1090
1091 @retval EFI_SUCCESS The interrupt was handled successfully.
1092
1093 **/
1094 EFI_STATUS
1095 EFIAPI
1096 DisableTopSwapCallback (
1097 IN EFI_HANDLE DispatchHandle,
1098 IN CONST VOID *DispatchContext,
1099 IN OUT VOID *CommBuffer OPTIONAL,
1100 IN OUT UINTN *CommBufferSize OPTIONAL
1101 )
1102 {
1103 if (!mEndOfDxe) {
1104 TopSwapSet (FALSE);
1105 }
1106
1107 return EFI_SUCCESS;
1108 }
1109
1110 /**
1111 Register a SMI handler to set/clear TopSwap bit.
1112
1113 @retval EFI_SUCCESS Successfully completed.
1114 @retval Other SMI handler is not registered.
1115 **/
1116 EFI_STATUS
1117 RegisterTopSwapSwSmiHandler (
1118 VOID
1119 )
1120 {
1121 EFI_STATUS Status;
1122 VOID *SmmEndOfDxeRegistration;
1123 EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
1124 EFI_HANDLE SwHandle;
1125 EFI_SMM_SW_REGISTER_CONTEXT SwContext;
1126 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
1127 SI_CONFIG_HOB_DATA *SiConfigHobData;
1128 EFI_PEI_HOB_POINTERS HobPtr;
1129 #endif
1130
1131 DEBUG((DEBUG_INFO, "RegisterTopSwapSwSmiHandler entry\n"));
1132
1133 #if FixedPcdGet8(PcdEmbeddedEnable) == 0x1
1134 HobPtr.Guid = GetFirstGuidHob (&gSiConfigHobGuid);
1135 ASSERT (HobPtr.Guid != NULL);
1136 SiConfigHobData = (SI_CONFIG_HOB_DATA *)GET_GUID_HOB_DATA (HobPtr.Guid);
1137 if (SiConfigHobData->SkipBiosDoneWhenFwUpdate == 1) {
1138 DEBUG ((DEBUG_INFO, "BIOS_DONE programming is skipped at EndOfPei, skip to register TopSwap SMI callback\n"));
1139 return EFI_SUCCESS;
1140 }
1141 #endif
1142
1143 //
1144 // Register EFI_SMM_END_OF_DXE_PROTOCOL_GUID notify function.
1145 //
1146 Status = gSmst->SmmRegisterProtocolNotify (
1147 &gEfiSmmEndOfDxeProtocolGuid,
1148 SmmEndOfDxeCallback,
1149 &SmmEndOfDxeRegistration
1150 );
1151 ASSERT_EFI_ERROR (Status);
1152 if (EFI_ERROR (Status)) {
1153 return EFI_NOT_READY;
1154 }
1155
1156 Status = mSmst->SmmLocateProtocol (&gEfiSmmSwDispatch2ProtocolGuid, NULL, (VOID**)&SwDispatch);
1157 ASSERT_EFI_ERROR (Status);
1158 if (EFI_ERROR (Status)) {
1159 return EFI_NOT_READY;
1160 }
1161
1162 //
1163 // Register TopSwap enable/disable handler
1164 //
1165 SwContext.SwSmiInputValue = (UINTN) -1;
1166 Status = SwDispatch->Register (
1167 SwDispatch,
1168 EnableTopSwapCallback,
1169 &SwContext,
1170 &SwHandle
1171 );
1172 ASSERT_EFI_ERROR (Status);
1173 if (Status == EFI_SUCCESS) {
1174 PcdSet8S (PcdTopSwapEnableSwSmi, (UINT8) SwContext.SwSmiInputValue);
1175 }
1176
1177 SwContext.SwSmiInputValue = (UINTN) -1;;
1178 Status = SwDispatch->Register (
1179 SwDispatch,
1180 DisableTopSwapCallback,
1181 &SwContext,
1182 &SwHandle
1183 );
1184 ASSERT_EFI_ERROR (Status);
1185 if (Status == EFI_SUCCESS) {
1186 PcdSet8S (PcdTopSwapDisableSwSmi, (UINT8) SwContext.SwSmiInputValue);
1187 }
1188
1189 DEBUG((DEBUG_INFO, "RegisterTopSwapSwSmiHandler Done!\n"));
1190
1191 return EFI_SUCCESS;
1192 }
1193 #endif
1194
1195 /**
1196 Initializes the SMM Platform Driver
1197
1198 @param[in] ImageHandle - Pointer to the loaded image protocol for this driver
1199 @param[in] SystemTable - Pointer to the EFI System Table
1200
1201 @retval Status - EFI_SUCCESS
1202 @retval Assert, otherwise.
1203
1204 **/
1205 EFI_STATUS
1206 EFIAPI
1207 InitializePlatformSmm (
1208 IN EFI_HANDLE ImageHandle,
1209 IN EFI_SYSTEM_TABLE *SystemTable
1210 )
1211 {
1212 EFI_STATUS Status;
1213 EFI_HANDLE Handle;
1214 EFI_HANDLE PowerButtonHandle;
1215 EFI_HANDLE SwHandle;
1216 EFI_HANDLE S4SleepEntryHandle;
1217 EFI_HANDLE S5SleepEntryHandle;
1218 #if FixedPcdGetBool (PcdS3Enable) == 1
1219 EFI_HANDLE S3SleepEntryHandle;
1220 #endif
1221
1222 EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL *PowerButtonDispatch;
1223 EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
1224 EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT PowerButtonContext;
1225 EFI_SMM_SW_REGISTER_CONTEXT SwContext;
1226 EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatch;
1227 EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext;
1228 PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
1229 UINTN DataSize;
1230
1231 SETUP_CPU_FEATURES SetupCpuFeatures;
1232 UINT8 TargetedSmiAvailable;
1233 UINT8 CpuSvrstrAvailable;
1234 UINT8 LongFlowAvailable;
1235 UINT8 SmmEnhancementSupported;
1236 UINT32 VariableAttr;
1237 PCH_ESPI_SMI_DISPATCH_PROTOCOL *PchEspiSmiDispatchProtocol;
1238 MSR_SMM_MCA_CAP_REGISTER SmmMcaCapMsr;
1239 #if FixedPcdGetBool (PcdAdlLpSupport) == 0
1240 CPU_SETUP CpuSetup;
1241 UINTN VariableSize;
1242 #endif
1243
1244 Handle = NULL;
1245 PowerButtonHandle = NULL;
1246 SwHandle = NULL;
1247 TargetedSmiAvailable = 0;
1248 CpuSvrstrAvailable = 0;
1249 LongFlowAvailable = 0;
1250 SmmEnhancementSupported = 0;
1251
1252 PostCode (PLATFORM_SMM_INIT_ENTRY);
1253
1254 //
1255 // Great! We're now in SMM!
1256 //
1257 mEctoPdControllerNegotiationInSx = PcdGetBool (PcdUsbcEcPdNegotiation) ? 1 : 0;
1258 mFpsWakeGpio = PcdGet32(PcdFingerPrintIrqGpio);
1259 //
1260 // Locate Platform Info Protocol.
1261 //
1262 mPlatformFlavor = PcdGet8 (PcdPlatformFlavor);
1263 mEcPresent = PcdGetBool (PcdEcPresent);
1264 mGpioTier2WakeSupport = PcdGetBool (PcdGpioTier2WakeEnable);
1265
1266 //
1267 // Initialize global variables
1268 //
1269 mSmst = gSmst;
1270
1271 //
1272 // Locate setup variable
1273 // We assert if it is not found because we have a dependency on AcpiPlatform which is
1274 // dependent on protocols the setup driver produces.
1275 //
1276 DataSize = sizeof (SETUP_DATA);
1277 Status = gRT->GetVariable (
1278 L"Setup",
1279 &gSetupVariableGuid,
1280 NULL,
1281 &DataSize,
1282 &mSystemConfiguration
1283 );
1284 // ASSERT_EFI_ERROR (Status);
1285
1286 //
1287 // Determine if EC TCSS handshake is enabled
1288 //
1289 mEcHandshakeEnable = 0;
1290 if ((mSystemConfiguration.UsbcBiosTcssHandshake == 1) && (!PcdGetBool(PcdBoardPmcPdEnable))) {
1291 mEcHandshakeEnable = 1;
1292 }
1293
1294 DataSize = sizeof (PCH_SETUP);
1295 Status = gRT->GetVariable (
1296 L"PchSetup",
1297 &gPchSetupVariableGuid,
1298 NULL,
1299 &DataSize,
1300 &mPchSetup
1301 );
1302 //
1303 // Get the ACPI Base Address
1304 //
1305 mAcpiBaseAddr = PmcGetAcpiBase ();
1306
1307 //
1308 // Disable RTC alarm and clear RTC PM1 status
1309 //
1310 InitRtcWakeup();
1311
1312 //
1313 // Locate the ICH SMM Power Button dispatch protocol
1314 //
1315 Status = mSmst->SmmLocateProtocol (&gEfiSmmPowerButtonDispatch2ProtocolGuid, NULL, (VOID**)&PowerButtonDispatch);
1316 ASSERT_EFI_ERROR (Status);
1317
1318 //
1319 // Register the power button SMM event
1320 //
1321 PowerButtonContext.Phase = EfiPowerButtonEntry;
1322 Status = PowerButtonDispatch->Register (
1323 PowerButtonDispatch,
1324 PowerButtonCallback,
1325 &PowerButtonContext,
1326 &PowerButtonHandle
1327 );
1328 ASSERT_EFI_ERROR (Status);
1329
1330 //
1331 // Locate the ICH SMM SW dispatch protocol
1332 //
1333 Status = mSmst->SmmLocateProtocol (&gEfiSmmSwDispatch2ProtocolGuid, NULL, (VOID**)&SwDispatch);
1334 ASSERT_EFI_ERROR (Status);
1335
1336 //
1337 // Locate our shared data area
1338 //
1339 Status = gBS->LocateProtocol (&gPlatformNvsAreaProtocolGuid, NULL, (VOID **) &PlatformNvsAreaProtocol);
1340 ASSERT_EFI_ERROR (Status);
1341 mPlatformNvsAreaPtr = PlatformNvsAreaProtocol->Area;
1342
1343 //
1344 // Register ACPI enable handler
1345 //
1346 SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiEnableSwSmi);
1347 Status = SwDispatch->Register (
1348 SwDispatch,
1349 EnableAcpiCallback,
1350 &SwContext,
1351 &SwHandle
1352 );
1353 ASSERT_EFI_ERROR (Status);
1354
1355 //
1356 // Register ACPI disable handler
1357 //
1358 SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiDisableSwSmi);
1359 Status = SwDispatch->Register (
1360 SwDispatch,
1361 DisableAcpiCallback,
1362 &SwContext,
1363 &SwHandle
1364 );
1365 ASSERT_EFI_ERROR (Status);
1366
1367 #ifdef DOCK_ENABLE
1368 //
1369 // Register PCIe Dock Bridges IO MEM Base Limit Patch Handler
1370 //
1371 SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdPcieDockBridgeResourcePatchSmi);
1372 Status = SwDispatch->Register (
1373 SwDispatch,
1374 PcieDockSmiCallback,
1375 &SwContext,
1376 &SwHandle
1377 );
1378 ASSERT_EFI_ERROR (Status);
1379 #endif
1380
1381 //
1382 // Locate the SmmSxDispatch protocol
1383 //
1384 Status = mSmst->SmmLocateProtocol (&gEfiSmmSxDispatch2ProtocolGuid, NULL, (VOID**)&SxDispatch);
1385 if (EFI_ERROR (Status)) {
1386 return Status;
1387 }
1388
1389 #if FixedPcdGetBool (PcdS3Enable) == 1
1390 //
1391 // Register S3 entry phase call back function
1392 //
1393 EntryDispatchContext.Type = SxS3;
1394 EntryDispatchContext.Phase = SxEntry;
1395 Status = SxDispatch->Register (
1396 SxDispatch,
1397 S3SleepEntryCallBack,
1398 &EntryDispatchContext,
1399 &S3SleepEntryHandle
1400 );
1401 #endif
1402 //
1403 // Register S4-Entry phase callback function
1404 //
1405 EntryDispatchContext.Type = SxS4;
1406 EntryDispatchContext.Phase = SxEntry;
1407 Status = SxDispatch->Register (
1408 SxDispatch,
1409 S4SleepEntryCallBack,
1410 &EntryDispatchContext,
1411 &S4SleepEntryHandle
1412 );
1413 //
1414 // Register S5 entry phase call back function
1415 //
1416 EntryDispatchContext.Type = SxS5;
1417 EntryDispatchContext.Phase = SxEntry;
1418 Status = SxDispatch->Register (
1419 SxDispatch,
1420 S5SleepEntryCallBack,
1421 &EntryDispatchContext,
1422 &S5SleepEntryHandle
1423 );
1424
1425 //
1426 // Check MSR SMM_MCA_CAP(0x17D) whether supports CPU SMM Enhancement Feature
1427 //
1428 DataSize = sizeof (SETUP_CPU_FEATURES);
1429 Status = gRT->GetVariable (
1430 L"SetupCpuFeatures",
1431 &gSetupVariableGuid,
1432 &VariableAttr,
1433 &DataSize,
1434 &SetupCpuFeatures
1435 );
1436 if (EFI_ERROR(Status)) {
1437 DEBUG((DEBUG_ERROR, "Get CPU Feature variable failure \n"));
1438 }
1439
1440 SmmMcaCapMsr.Uint64 = AsmReadMsr64 (MSR_SMM_MCA_CAP);
1441 if (SmmMcaCapMsr.Bits.TargetedSmi ||
1442 SmmMcaCapMsr.Bits.SmmCpuSvrstr ||
1443 SmmMcaCapMsr.Bits.SmmCodeAccessChk ||
1444 SmmMcaCapMsr.Bits.LongFlowIndication) {
1445 SmmEnhancementSupported = 1;
1446 TargetedSmiAvailable = (UINT8) SmmMcaCapMsr.Bits.TargetedSmi;
1447 CpuSvrstrAvailable = (UINT8) SmmMcaCapMsr.Bits.SmmCpuSvrstr;
1448 LongFlowAvailable = (UINT8) SmmMcaCapMsr.Bits.LongFlowIndication;
1449 }
1450
1451 //
1452 // Update SetupCpuFeature variable if not equal
1453 //
1454 if (EFI_ERROR(Status) || ((SmmEnhancementSupported != SetupCpuFeatures.SmmEnhancementSupported) || (TargetedSmiAvailable != SetupCpuFeatures.SmmTargetedSmiAvailable) || (CpuSvrstrAvailable != SetupCpuFeatures.SmmCpuSvrstrAvailable) || (LongFlowAvailable != SetupCpuFeatures.SmmLongFlowAvailable))) {
1455 SetupCpuFeatures.SmmEnhancementSupported = SmmEnhancementSupported;
1456 SetupCpuFeatures.SmmTargetedSmiAvailable = TargetedSmiAvailable;
1457 SetupCpuFeatures.SmmCpuSvrstrAvailable = CpuSvrstrAvailable;
1458 SetupCpuFeatures.SmmLongFlowAvailable = LongFlowAvailable;
1459
1460 Status = gRT->SetVariable (
1461 L"SetupCpuFeatures",
1462 &gSetupVariableGuid,
1463 VariableAttr,
1464 DataSize,
1465 &SetupCpuFeatures
1466 );
1467 if (EFI_ERROR(Status)) {
1468 DEBUG ((DEBUG_ERROR, "Set CPU Feature variable failure \n"));
1469 }
1470 }
1471
1472 #if FixedPcdGetBool(PcdS3Enable) == 1
1473 //
1474 // Initialize RuntimeScriptTable base address
1475 //
1476 Status = InitializeSmmScriptLib (SystemTable, 2, &(mAcpiSmm.RuntimeScriptTableBase));
1477 DEBUG((DEBUG_INFO, "RuntimeScriptTableBase is 0x%x\n", mAcpiSmm.RuntimeScriptTableBase));
1478 ASSERT_EFI_ERROR (Status);
1479 #endif
1480
1481 //
1482 // Lock HMRFPO
1483 // Output parameters are stored in global variables that can be used in subsequent calls in SMM
1484 // call back functions, e.g., HMRFPO Enable
1485 //
1486
1487 //
1488 // Locate the PCH eSPI SMI dispatch protocol.
1489 //
1490 PchEspiSmiDispatchProtocol = NULL;
1491 Status = mSmst->SmmLocateProtocol (&gPchEspiSmiDispatchProtocolGuid, NULL, (VOID **) &PchEspiSmiDispatchProtocol);
1492 if (EFI_ERROR(Status)) {
1493 DEBUG((DEBUG_ERROR, "Locate the PCH eSPI SMI dispatch protocol failure\n"));
1494 } else {
1495
1496 //
1497 // Register an eSPI EC SMI callback function.
1498 //
1499 Handle = NULL;
1500 Status = PchEspiSmiDispatchProtocol->EspiSlaveSmiRegister (
1501 PchEspiSmiDispatchProtocol,
1502 eSpiEcSmiCallback,
1503 &Handle
1504 );
1505 if (EFI_ERROR(Status)) {
1506 DEBUG((DEBUG_ERROR, "Register eSPI EC SMI callback function failure\n"));
1507 }
1508 }
1509
1510 //
1511 // Register TCO timeout SMI handler
1512 //
1513 Status = RegisterTcoTimeoutHandler ();
1514
1515 #if FixedPcdGetBool(PcdCapsuleEnable) == 1
1516 //
1517 // TopSwap Manipulation SMI handler
1518 //
1519 Status = RegisterTopSwapSwSmiHandler ();
1520 #endif
1521 #if FixedPcdGetBool (PcdAdlLpSupport) == 0
1522 VariableSize = sizeof(CPU_SETUP);
1523 Status = gRT->GetVariable(
1524 (CHAR16 *)L"CpuSetup",
1525 &gCpuSetupVariableGuid,
1526 (UINT32 *)NULL,
1527 &VariableSize,
1528 &CpuSetup
1529 );
1530 if (EFI_ERROR(Status)) {
1531 DEBUG((DEBUG_ERROR, "CpuSetup Status %r\n", Status));
1532 }
1533 else {
1534 //
1535 // Scroll Lock hot key IO Trap for Game compatibility Mode to Toggle Performance Core/Efficient Core Hints to Pcode.
1536 //
1537 if (CpuSetup.GameCompatibilityMode) {
1538 SetupPs2IoTrap();
1539 }
1540 }
1541 #endif
1542 PostCode(PLATFORM_SMM_INIT_EXIT);
1543
1544 return EFI_SUCCESS;
1545 }
EnableAcpiCallback
EFI_STATUS EnableAcpiCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN OUT UINTN *CommBufferSize OPTIONAL)
Clear Port 80h.
Definition: PlatformInitAdvancedSmm.c:142
S3SleepEntryCallBack
EFI_STATUS S3SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S3 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:702
InitializePlatformSmm
EFI_STATUS InitializePlatformSmm(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initializes the SMM Platform Driver.
Definition: PlatformInitAdvancedSmm.c:1207
EnableEcAcpiMode
EFI_STATUS EnableEcAcpiMode(IN BOOLEAN Enable)
Send enable ACPI mode command to EC.
BCDToDec
UINT8 BCDToDec(UINT8 BCD)
Converts BCD to Dec number Only for 2 digit BCD.
Definition: PlatformInitAdvancedSmm.c:328
WakeOnRTCS5
VOID WakeOnRTCS5(VOID)
Enables RTC Wake from S5 and fast startup flow.
Definition: PlatformInitAdvancedSmm.c:643
EnableFingerPrintSensorWakeSupport
VOID EnableFingerPrintSensorWakeSupport(VOID)
Enable FInger Print Sensor Wake Support Default GPIO is configured as GPIO Driver Mode where FPS driv...
Definition: PlatformInitAdvancedSmm.c:570
DisableEcSmiMode
EFI_STATUS DisableEcSmiMode(VOID)
Send disable SMI mode command to EC.
PowerStateIsAc
BOOLEAN PowerStateIsAc(VOID)
Get power state from EC.
DecToBCD
UINT8 DecToBCD(UINT8 Dec)
Converts Decimal to BCD Only for 2 digit BCD.
Definition: PlatformInitAdvancedSmm.c:306
S4SleepEntryCallBack
EFI_STATUS S4SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S4 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:770
UsbcSxEntry
EFI_STATUS UsbcSxEntry(IN OUT UINT8 *DataBuffer, IN UINT32 Timeout)
Send enable ACPI mode command to EC.
InitRtcWakeup
VOID InitRtcWakeup(VOID)
Disable RTC alarm and clear RTC PM1 status.
Definition: PlatformInitAdvancedSmm.c:453
EnablePchPcieWakeSupport
VOID EnablePchPcieWakeSupport(VOID)
If PCIe native mode is disabled through BIOS setup options, Windows ACPI driver initializes the PM1 e...
Definition: PlatformInitAdvancedSmm.c:532
WriteRtcIndex
VOID WriteRtcIndex(IN UINT8 Index, IN UINT8 Value)
Writes to an RTC Index register.
Definition: PlatformInitAdvancedSmm.c:414
PlatformInitAdvancedSmm.h
Header file for the Platform Advanced SMM Driver.
DisableAcpiCallback
EFI_STATUS DisableAcpiCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
Disable SCI.
Definition: PlatformInitAdvancedSmm.c:267
S5SleepEntryCallBack
EFI_STATUS S5SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S5 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:832
EnablePchTier2GpioWakeSupport
EFI_STATUS EnablePchTier2GpioWakeSupport(VOID)
Enable wake capability for that wake delivered via tier2 GPIO.
Definition: PlatformInitAdvancedSmm.c:485
SetupPs2IoTrap
EFI_STATUS SetupPs2IoTrap(VOID)
Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.
Definition: Ps2IoTrapHandler.c:264
ReadRtcIndex
UINT8 ReadRtcIndex(IN UINT8 Index)
Reads the RTC Index register.
Definition: PlatformInitAdvancedSmm.c:348
PlatformPostCode.h
RegisterTcoTimeoutHandler
EFI_STATUS RegisterTcoTimeoutHandler(VOID)
Register a SMI handler for Tco timeout event.
Definition: PlatformInitAdvancedSmm.c:1006
PcieDockSmi.h
PchTcoTimeoutCallback
VOID PchTcoTimeoutCallback(IN EFI_HANDLE DispatchHandle)
This hardware SMI handler will be run every time the BIOS Write Enable bit is set.
Definition: PlatformInitAdvancedSmm.c:974
OverwriteCpuWakeEnValue
VOID OverwriteCpuWakeEnValue(VOID)
Check GPE0_EN_127_96_CPU_WAKE_EN value (bit19 of General Purpose Event 0 Status [127:96] Register),...
Definition: PlatformInitAdvancedSmm.c:609
OemSetup.h
OEM Specific Setup Variables and Structures.
eSpiEcSmiCallback
VOID eSpiEcSmiCallback(IN EFI_HANDLE DispatchHandle)
eSPI EC SMI callback function.
Definition: EcSmi.c:52
PowerButtonCallback
EFI_STATUS PowerButtonCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
When a power button event happens, it shuts off the machine.
Definition: PlatformInitAdvancedSmm.c:907
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvancedSmm.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
Functions
PlatformInitAdvancedSmm.h File Reference

Header file for the Platform Advanced SMM Driver. More...

#include "Platform.h"
#include <SetupVariable.h>
#include <Uefi/UefiBaseType.h>
#include <Library/IoLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/S3BootScriptLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/DxeSmmScriptLib/DxeSmmScriptLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Protocol/EcAccess.h>
#include <PlatformBoardType.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/SmmBase2.h>
#include <Protocol/SmmPowerButtonDispatch2.h>
#include <Protocol/SmmSxDispatch2.h>
#include <Protocol/SmmSwDispatch2.h>
#include <Protocol/SmmIoTrapDispatch2.h>
#include <Protocol/SmmUsbDispatch2.h>
#include <Library/EcMiscLib.h>
#include "Library/DxeSmmAcpiCustomLib.h"
#include <Protocol/PlatformNvsArea.h>
#include <IndustryStandard/Pci30.h>
#include <Protocol/PchEspiSmiDispatch.h>
#include <Library/EcTcssLib.h>
Include dependency graph for PlatformInitAdvancedSmm.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | DisableAcpiCallback (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
Disable SCI. More...
EFI_STATUS | PowerButtonCallback (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
When a power button event happens, it shuts off the machine. More...
EFI_STATUS | S3SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S3 Sleep Entry Call Back. More...
EFI_STATUS | S4SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S4 Sleep Entry Call Back. More...
EFI_STATUS | S5SleepEntryCallBack (IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S5 Sleep Entry Call Back. More...
VOID | eSpiEcSmiCallback (IN EFI_HANDLE DispatchHandle)
eSPI EC SMI callback function. More...
VOID | WakeOnRTCS5 (VOID)
Enables RTC Wake from S5 and fast startup flow. More...
EFI_STATUS | SetupPs2IoTrap (VOID)
Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses. More...

Detailed Description

Header file for the Platform Advanced SMM Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitAdvancedSmm.h.

Function Documentation

◆ DisableAcpiCallback()

EFI_STATUS DisableAcpiCallback | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

Disable SCI.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.

Definition at line 267 of file PlatformInitAdvancedSmm.c.

◆ eSpiEcSmiCallback()

VOID eSpiEcSmiCallback ( IN EFI_HANDLE DispatchHandle )

eSPI EC SMI callback function.

Parameters
[in] DispatchHandle Not used

Definition at line 52 of file EcSmi.c.

◆ PowerButtonCallback()

EFI_STATUS PowerButtonCallback | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

When a power button event happens, it shuts off the machine.

Parameters
[in] | DispatchHandle | - Handle of this dispatch function
[in] | DispatchContext | - Pointer to the dispatch function's context
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 907 of file PlatformInitAdvancedSmm.c.

◆ S3SleepEntryCallBack()

EFI_STATUS S3SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S3 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 702 of file PlatformInitAdvancedSmm.c.

◆ S4SleepEntryCallBack()

EFI_STATUS S4SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S4 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 770 of file PlatformInitAdvancedSmm.c.

◆ S5SleepEntryCallBack()

EFI_STATUS S5SleepEntryCallBack | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID * | DispatchContext,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN UINTN *CommBufferSize | OPTIONAL
 | ) |  |

S5 Sleep Entry Call Back.

Parameters
[in] | DispatchHandle | - The handle of this callback, obtained when registering
[in] | DispatchContext | - The predefined context which contained sleep type and phase
[in] | CommBuffer | - A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
[in] | CommBufferSize | - The size of the CommBuffer.
Return values
EFI_SUCCESS - Operation successfully performed

Definition at line 832 of file PlatformInitAdvancedSmm.c.

◆ SetupPs2IoTrap()

EFI_STATUS SetupPs2IoTrap ( VOID )

Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.

Return values
EFI_SUCCESS Function successfully executed.

Definition at line 264 of file Ps2IoTrapHandler.c.

◆ WakeOnRTCS5()

VOID WakeOnRTCS5 ( VOID )

Enables RTC Wake from S5 and fast startup flow.

Parameters
[in] VOID
Return values
VOID

Definition at line 643 of file PlatformInitAdvancedSmm.c.

Here is the call graph for this function:


AlderLake Platform Sample Code: PlatformInitAdvancedSmm.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PlatformInitAdvancedSmm.h
Go to the documentation of this file.
1 /** @file
2 Header file for the Platform Advanced SMM Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_INIT_ADVANCED_SMM_H_
36 #define _PLATFORM_INIT_ADVANCED_SMM_H_
37
38 #include "Platform.h"
39 #include <SetupVariable.h>
40 #include <Uefi/UefiBaseType.h>
41 #include <Library/IoLib.h>
42 #include <Library/PcdLib.h>
43 #include <Library/DebugLib.h>
44 #include <Library/S3BootScriptLib.h>
45 #include <Library/SmmServicesTableLib.h>
46 #include <Library/DxeSmmScriptLib/DxeSmmScriptLib.h>
47 #include <Library/ReportStatusCodeLib.h>
48 #include <Library/UefiBootServicesTableLib.h>
49 #include <Library/UefiRuntimeServicesTableLib.h>
50 #include <Protocol/EcAccess.h>
51 #include <PlatformBoardType.h>
52 #include <Protocol/LoadedImage.h>
53 #include <Protocol/PciRootBridgeIo.h>
54 #include <Protocol/SmmBase2.h>
55 #include <Protocol/SmmPowerButtonDispatch2.h>
56 #include <Protocol/SmmSxDispatch2.h>
57 #include <Protocol/SmmSwDispatch2.h>
58 #include <Protocol/SmmIoTrapDispatch2.h>
59 #include <Protocol/SmmUsbDispatch2.h>
60 #include <Library/EcMiscLib.h>
61 #include "Library/DxeSmmAcpiCustomLib.h"
62 #include <Protocol/PlatformNvsArea.h>
63 #include <IndustryStandard/Pci30.h>
64 #include <Protocol/PchEspiSmiDispatch.h>
65 #include <Library/EcTcssLib.h>
66
67 //
68 // Related data structures definition
69 //
70 typedef struct _EFI_ACPI_SMM_DEV {
71 EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
72 UINT32 BootScriptSaved;
73 } EFI_ACPI_SMM_DEV;
74
75
76 //
77 // Callback function prototypes
78 //
79 EFI_STATUS
80 EFIAPI
81 EnableAcpiCallback (
82 IN EFI_HANDLE DispatchHandle,
83 IN CONST VOID *DispatchContext,
84 IN OUT VOID *CommBuffer OPTIONAL,
85 IN UINTN *CommBufferSize OPTIONAL
86 );
87
88 EFI_STATUS
89 EFIAPI
90 DisableAcpiCallback (
91 IN EFI_HANDLE DispatchHandle,
92 IN CONST VOID *DispatchContext,
93 IN OUT VOID *CommBuffer OPTIONAL,
94 IN UINTN *CommBufferSize OPTIONAL
95 );
96
97 EFI_STATUS
98 EFIAPI
99 PowerButtonCallback (
100 IN EFI_HANDLE DispatchHandle,
101 IN CONST VOID *DispatchContext,
102 IN OUT VOID *CommBuffer OPTIONAL,
103 IN UINTN *CommBufferSize OPTIONAL
104 );
105
106 EFI_STATUS
107 EFIAPI
108 S3SleepEntryCallBack (
109 IN EFI_HANDLE DispatchHandle,
110 IN CONST VOID *DispatchContext,
111 IN OUT VOID *CommBuffer OPTIONAL,
112 IN UINTN *CommBufferSize OPTIONAL
113 );
114
115 EFI_STATUS
116 EFIAPI
117 S4SleepEntryCallBack (
118 IN EFI_HANDLE DispatchHandle,
119 IN CONST VOID *DispatchContext,
120 IN OUT VOID *CommBuffer OPTIONAL,
121 IN UINTN *CommBufferSize OPTIONAL
122 );
123
124 EFI_STATUS
125 EFIAPI
126 S5SleepEntryCallBack (
127 IN EFI_HANDLE DispatchHandle,
128 IN CONST VOID *DispatchContext,
129 IN OUT VOID *CommBuffer OPTIONAL,
130 IN UINTN *CommBufferSize OPTIONAL
131 );
132
133 EFI_STATUS
134 IntelUsb20SmiHandler (
135 IN EFI_HANDLE DispatchHandle,
136 IN EFI_SMM_USB_REGISTER_CONTEXT *DispatchContext
137 );
138
139 VOID
140 EFIAPI
141 eSpiEcSmiCallback (
142 IN EFI_HANDLE DispatchHandle
143 );
144
145 VOID
146 WakeOnRTCS5 (
147 VOID
148 );
149
150 #if FixedPcdGetBool (PcdAdlLpSupport) == 0
151 EFI_STATUS
152 SetupPs2IoTrap(
153 VOID
154 );
155 #endif
156
157 #endif
158
PlatformNvsArea.h
This file defines the Platform NVS Area Protocol.
EnableAcpiCallback
EFI_STATUS EnableAcpiCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN OUT UINTN *CommBufferSize OPTIONAL)
Clear Port 80h.
Definition: PlatformInitAdvancedSmm.c:142
WakeOnRTCS5
VOID WakeOnRTCS5(VOID)
Enables RTC Wake from S5 and fast startup flow.
Definition: PlatformInitAdvancedSmm.c:643
DisableAcpiCallback
EFI_STATUS DisableAcpiCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
Disable SCI.
Definition: PlatformInitAdvancedSmm.c:267
DxeSmmAcpiCustomLib.h
This header file provides platform specific definitions used by other modules for platform specific i...
Platform.h
This header file provides platform specific definitions used by other modules for platform specific i...
PowerButtonCallback
EFI_STATUS PowerButtonCallback(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
When a power button event happens, it shuts off the machine.
Definition: PlatformInitAdvancedSmm.c:907
eSpiEcSmiCallback
VOID eSpiEcSmiCallback(IN EFI_HANDLE DispatchHandle)
eSPI EC SMI callback function.
Definition: EcSmi.c:52
SetupPs2IoTrap
EFI_STATUS SetupPs2IoTrap(VOID)
Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.
Definition: Ps2IoTrapHandler.c:264
EcMiscLib.h
EC miscellaneous library functions.
S4SleepEntryCallBack
EFI_STATUS S4SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S4 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:770
EcAccess.h
S5SleepEntryCallBack
EFI_STATUS S5SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S5 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:832
S3SleepEntryCallBack
EFI_STATUS S3SleepEntryCallBack(IN EFI_HANDLE DispatchHandle, IN CONST VOID *DispatchContext, IN OUT VOID *CommBuffer OPTIONAL, IN UINTN *CommBufferSize OPTIONAL)
S3 Sleep Entry Call Back.
Definition: PlatformInitAdvancedSmm.c:702
EcTcssLib.h
EC TCSS library functions.
SetupVariable.h
PlatformBoardType.h
BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PlatformInitLib.h File Reference

Function prototype of PlatformInitLib. More...

Go to the source code of this file.

Detailed Description

Function prototype of PlatformInitLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformInitLib.h.


AlderLake Platform Sample Code: PlatformInitLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PlatformInitLib.h
Go to the documentation of this file.
1 /** @file
2 Function prototype of PlatformInitLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_INIT_LIB_H_
36 #define _PLATFORM_INIT_LIB_H_
37
38 VOID
39 PlatformLateInit (
40 VOID
41 );
42
43 VOID
44 InitSerialPort (
45 VOID
46 );
47
48 #endif // _PLATFORM_INIT_LIB_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformNvRamHookLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Functions
PlatformNvRamHookLib.h File Reference

Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

BOOLEAN | IsChecksumBad (VOID)
Test to see if Checksum is bad. More...
VOID | ClearDiagnosticStatus (VOID)
Clear Diagnostic Status.
BOOLEAN | NeedResetBoardDefaultVariableHob (VOID)
Check to reset setup variable and Clear CMOS 0E when CMOS content is bad. More...
VOID | SecondaryNvRamInit (VOID)
Load CMOS default on RTC battery failure.
UINT8 | GetFastBootFlagStatus (VOID)
Get Boot Flag Status. More...
VOID | UpdateFastBootFlagStatus (UINT8 BootStatus)
Update Boot Flag Status. More...
UINT8 | GetRtc3Address (VOID)
Get RTC 3 Address. More...
VOID | GetPostCodeBreak (UINT8 *Port80, UINT8 *Port81)
Get Post Code Break for Port 80 and 81. More...
UINT8 | GetTxtAliasCheckAndReset (VOID)
Get TXT Alias Check Request and Reset it. More...
VOID | SaveTxtAliasCheck (UINT8 ACheckRequest)
Save the TXT Alias Check Request. More...
VOID | SaveCpuRatio (UINT8 CpuRatio)
Save the CPU Ratio. More...
VOID | SetBclkRampFlag (UINT8 BclkRampFlag)
Set the BCLK Ramp Flag. More...
UINT8 | GetTbtHostRouterStatus (VOID)
Get TBT Host Router Status. More...
VOID | SaveTbtHostRouterStatus (UINT8 TbtHrStatus)
Save TBT Host Router Status. More...

Detailed Description

Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformNvRamHookLib.h.

Function Documentation

◆ GetFastBootFlagStatus()

UINT8 GetFastBootFlagStatus ( VOID )

Get Boot Flag Status.

Return values
Value of current boot status

◆ GetPostCodeBreak()

VOID GetPostCodeBreak | ( | UINT8 * | Port80,
 |  | UINT8 * | Port81
 | ) |  |

Get Post Code Break for Port 80 and 81.

Parameters
[out] | *Port80 | Pointer to return value of post code 80
[out] | *Port81 | Pointer to return value of post code 81

◆ GetRtc3Address()

UINT8 GetRtc3Address ( VOID )

Get RTC 3 Address.

Return values
Current value of RTC 3 Address

◆ GetTbtHostRouterStatus()

UINT8 GetTbtHostRouterStatus ( VOID )

Get TBT Host Router Status.

CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)

Return values
Current value of TBT Host Router Status

◆ GetTxtAliasCheckAndReset()

UINT8 GetTxtAliasCheckAndReset ( VOID )

Get TXT Alias Check Request and Reset it.

Return values
TXT Alias Check Request

◆ IsChecksumBad()

BOOLEAN IsChecksumBad ( VOID )

Test to see if Checksum is bad.

Return values
TRUE - Checksum content is bad FALSE - Checksum content is good

◆ NeedResetBoardDefaultVariableHob()

BOOLEAN NeedResetBoardDefaultVariableHob ( VOID )

Check to reset setup variable and Clear CMOS 0E when CMOS content is bad.

Return values
Flag to Reset Setup variable : TRUE - When CMOS content is bad FALSE - Otherwise

◆ SaveCpuRatio()

VOID SaveCpuRatio ( UINT8 CpuRatio )

Save the CPU Ratio.

Parameters
[in] CpuRatio The Cpu ratio value to be saved.

◆ SaveTbtHostRouterStatus()

VOID SaveTbtHostRouterStatus ( UINT8 TbtHrStatus )

Save TBT Host Router Status.

CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)

Parameters
[in] TbtHrStatus The TBT Host Router Status to be udpated.

◆ SaveTxtAliasCheck()

VOID SaveTxtAliasCheck ( UINT8 ACheckRequest )

Save the TXT Alias Check Request.

Parameters
[in] ACheckRequest Request of TXT Alias Check.

◆ SetBclkRampFlag()

VOID SetBclkRampFlag ( UINT8 BclkRampFlag )

Set the BCLK Ramp Flag.

Parameters
[in] BclkRampFlag The BCLK Ramp Flag to be set.

◆ UpdateFastBootFlagStatus()

VOID UpdateFastBootFlagStatus ( UINT8 BootStatus )

Update Boot Flag Status.

Parameters
[in] BootStatus Current Boot value which to be updated.


AlderLake Platform Sample Code: PlatformNvRamHookLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformNvRamHookLib.h
Go to the documentation of this file.
1 /** @file
2
3 Platform Nv RAM Hook Library Header Definition which will oprovide the absraction
4 to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains a 'Sample Driver' and is licensed as such under the terms
31 of your license agreement with Intel or your vendor. This file may be modified
32 by the user, subject to the additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PLATFORM_NVRAM_HOOK_LIB_H_
38 #define _PLATFORM_NVRAM_HOOK_LIB_H_
39
40 #ifndef DEFAULT_VALUE
41 #define DEFAULT_VALUE 0
42 #endif
43
44 /**
45 Test to see if Checksum is bad.
46
47 @retval TRUE - Checksum content is bad
48 FALSE - Checksum content is good
49 **/
50 BOOLEAN
51 IsChecksumBad (
52 VOID
53 );
54
55 /**
56 Clear Diagnostic Status.
57 **/
58 VOID
59 ClearDiagnosticStatus (
60 VOID
61 );
62
63 /**
64 Check to reset setup variable and Clear CMOS 0E when CMOS content is bad
65
66 @retval Flag to Reset Setup variable : TRUE - When CMOS content is bad
67 FALSE - Otherwise
68 **/
69 BOOLEAN
70 NeedResetBoardDefaultVariableHob(
71 VOID
72 );
73
74 /**
75 Load CMOS default on RTC battery failure.
76 **/
77 VOID
78 SecondaryNvRamInit(
79 VOID
80 );
81
82 /**
83 Get Boot Flag Status.
84
85 @retval Value of current boot status
86 **/
87 UINT8
88 GetFastBootFlagStatus(
89 VOID
90 );
91
92 /**
93 Update Boot Flag Status.
94
95 @param [in] BootStatus Current Boot value which to be updated.
96 **/
97 VOID
98 UpdateFastBootFlagStatus(
99 UINT8 BootStatus
100 );
101
102 /**
103 Get RTC 3 Address.
104
105 @retval Current value of RTC 3 Address
106 **/
107 UINT8
108 GetRtc3Address(
109 VOID
110 );
111 /**
112 Get Post Code Break for Port 80 and 81
113
114 @param [out] *Port80 Pointer to return value of post code 80
115
116 @param [out] *Port81 Pointer to return value of post code 81
117 **/
118 VOID
119 GetPostCodeBreak(
120 UINT8 *Port80,
121 UINT8 *Port81
122 );
123
124 /**
125 Get TXT Alias Check Request and Reset it.
126
127 @retval TXT Alias Check Request
128 **/
129 UINT8
130 GetTxtAliasCheckAndReset(
131 VOID
132 );
133
134 /**
135 Save the TXT Alias Check Request.
136
137 @param [in] ACheckRequest Request of TXT Alias Check.
138 **/
139 VOID
140 SaveTxtAliasCheck(
141 UINT8 ACheckRequest
142 );
143
144 /**
145 Save the CPU Ratio.
146
147 @param [in] CpuRatio The Cpu ratio value to be saved.
148 **/
149 VOID
150 SaveCpuRatio(
151 UINT8 CpuRatio
152 );
153
154 /**
155 Set the BCLK Ramp Flag.
156
157 @param [in] BclkRampFlag The BCLK Ramp Flag to be set.
158 **/
159 VOID
160 SetBclkRampFlag(
161 UINT8 BclkRampFlag
162 );
163
164
165 /**
166 Get TBT Host Router Status.
167
168 CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
169
170 @retval Current value of TBT Host Router Status
171 **/
172 UINT8
173 GetTbtHostRouterStatus(
174 VOID
175 );
176
177 /**
178 Save TBT Host Router Status.
179
180 CMOS_TBTHR_PRESENT_ON_RESUME: Bits 0-3 is for DTBT and Bits 4-7 is for ITBT (HIA0/1/2/Reserved)
181
182 @param [in] TbtHrStatus The TBT Host Router Status to be udpated.
183 **/
184 VOID
185 SaveTbtHostRouterStatus(
186 UINT8 TbtHrStatus
187 );
188 #endif // _PLATFORM_NVRAM_HOOK_LIB_H_
GetTbtHostRouterStatus
UINT8 GetTbtHostRouterStatus(VOID)
Get TBT Host Router Status.
GetTxtAliasCheckAndReset
UINT8 GetTxtAliasCheckAndReset(VOID)
Get TXT Alias Check Request and Reset it.
NeedResetBoardDefaultVariableHob
BOOLEAN NeedResetBoardDefaultVariableHob(VOID)
Check to reset setup variable and Clear CMOS 0E when CMOS content is bad.
GetRtc3Address
UINT8 GetRtc3Address(VOID)
Get RTC 3 Address.
SaveTxtAliasCheck
VOID SaveTxtAliasCheck(UINT8 ACheckRequest)
Save the TXT Alias Check Request.
GetFastBootFlagStatus
UINT8 GetFastBootFlagStatus(VOID)
Get Boot Flag Status.
GetPostCodeBreak
VOID GetPostCodeBreak(UINT8 *Port80, UINT8 *Port81)
Get Post Code Break for Port 80 and 81.
ClearDiagnosticStatus
VOID ClearDiagnosticStatus(VOID)
Clear Diagnostic Status.
SecondaryNvRamInit
VOID SecondaryNvRamInit(VOID)
Load CMOS default on RTC battery failure.
SaveCpuRatio
VOID SaveCpuRatio(UINT8 CpuRatio)
Save the CPU Ratio.
SaveTbtHostRouterStatus
VOID SaveTbtHostRouterStatus(UINT8 TbtHrStatus)
Save TBT Host Router Status.
SetBclkRampFlag
VOID SetBclkRampFlag(UINT8 BclkRampFlag)
Set the BCLK Ramp Flag.
UpdateFastBootFlagStatus
VOID UpdateFastBootFlagStatus(UINT8 BootStatus)
Update Boot Flag Status.
IsChecksumBad
BOOLEAN IsChecksumBad(VOID)
Test to see if Checksum is bad.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformNvsArea.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
PlatformNvsArea.h File Reference

This file defines the Platform NVS Area Protocol. More...

#include <PlatformNvsAreaDef.h>
Include dependency graph for PlatformNvsArea.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This file defines the Platform NVS Area Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformNvsArea.h.


AlderLake Platform Sample Code: PlatformNvsArea.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
PlatformNvsArea.h
Go to the documentation of this file.
1 /** @file
2 This file defines the Platform NVS Area Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _PLATFORM_NVS_AREA_H_
36 #define _PLATFORM_NVS_AREA_H_
37
38 //
39 // Platform NVS Area definition
40 //
41 #include <PlatformNvsAreaDef.h>
42
43 //
44 // Includes
45 //
46 #define PLATFORM_NVS_DEVICE_ENABLE 1
47 #define PLATFORM_NVS_DEVICE_DISABLE 0
48
49 //
50 // Forward reference for pure ANSI compatibility
51 //
52 typedef struct _PLATFORM_NVS_AREA_PROTOCOL PLATFORM_NVS_AREA_PROTOCOL;
53
54 //
55 // Platform NVS Area Protocol GUID
56 //
57 #define PLATFORM_NVS_AREA_PROTOCOL_GUID \
58 { 0xc77ae556,0x40a3, 0x41c0, 0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71 }
59
60 #define PLATFORM_NVS_AREA_REVISION_1 1
61
62 //
63 // Platform NVS Area Protocol
64 //
65 typedef struct _PLATFORM_NVS_AREA_PROTOCOL {
66 PLATFORM_NVS_AREA *Area;
67 } PLATFORM_NVS_AREA_PROTOCOL;
68
69 #endif // _PLATFORM_NVS_AREA_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformOpRomTable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • MultiPlatform
PlatformOpRomTable.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformOpRomTable.h.


AlderLake Platform Sample Code: PlatformOpRomTable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • MultiPlatform
PlatformOpRomTable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 //
35 // Automatically generated by ACE ver 1.63 PIRQTRANS
36 // Please DO NOT modify !!!
37 //
38
39
40 //
41 // Global variables for Option Roms
42 //
43 #define NULL_ROM_FILE_GUID \
44 { \
45 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } \
46 }
47
48 //
49 // {6A5F1EF9-C478-42ba-A4DB-C7846CC7DB57}
50 //
51 #define MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID \
52 { \
53 0x6A5F1EF9, 0xC478, 0x42ba, { 0xA4, 0xDB, 0xC7, 0x84, 0x6C, 0xC7, 0xDB, 0x57 } \
54 }
55
56 //
57 // {2BB1381D-AE4F-4b37-B999-812F93811282}
58 //
59 #define RAID_OPTION_ROM_FILE_GUID \
60 { \
61 0x2BB1381D, 0xAE4F, 0x4b37, { 0xB9, 0x99, 0x81, 0x2F, 0x93, 0x81, 0x12, 0x82 } \
62 }
63
64 //
65 // {BF3CE2C0-FCEE-11E1-A21F-0800200C9A66}
66 //
67 #define RSTE_OPTION_ROM_FILE_GUID \
68 { \
69 0xBF3CE2C0, 0xFCEE, 0x11E1, { 0xA2, 0x1F, 0x08, 0x00, 0x20, 0x0C, 0x9A, 0x66 } \
70 }
71
72 //
73 // {58531F11-5C10-4dea-A54C-0A017FA03425}
74 //
75 #define PXE_OPTION_ROM_FILE_GUID \
76 { \
77 0x58531F11, 0x5C10, 0x4dea , { 0xA5, 0x4C, 0x0A, 0x01, 0x7F, 0xA0, 0x34, 0x25 } \
78 }
79
80 #define MAX_ROM_NUMBER 4
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformOptionRomTable_Default.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • MultiPlatform
PlatformOptionRomTable_Default.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformOptionRomTable_Default.h.


AlderLake Platform Sample Code: PlatformOptionRomTable_Default.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • MultiPlatform
PlatformOptionRomTable_Default.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2017 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 //
35 // Automatically generated by ACE ver 1.63 PIRQTRANS
36 // Please DO NOT modify !!!
37 //
38
39
40 PCI_OPTION_ROM_TABLE mPciOptionRomTable_Default[] = {
41 //
42 // Option Rom for
43 //
44 {
45 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
46 0x0, // Segment
47 0x0, // Bus Number
48 0x2, // Device Number
49 0x0, // Function Number
50 0x8086, // Vendor ID
51 0xff05, // Device ID
52 },
53 //
54 // Option Rom for
55 //
56 {
57 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
58 0x0, // Segment
59 0x0, // Bus Number
60 0x2, // Device Number
61 0x0, // Function Number
62 0x8086, // Vendor ID
63 0x8a51, // Device ID
64 },
65 //
66 // Option Rom for
67 //
68 {
69 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
70 0x0, // Segment
71 0x0, // Bus Number
72 0x2, // Device Number
73 0x0, // Function Number
74 0x8086, // Vendor ID
75 0x8a52, // Device ID
76 },
77 //
78 // Option Rom for
79 //
80 {
81 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
82 0x0, // Segment
83 0x0, // Bus Number
84 0x2, // Device Number
85 0x0, // Function Number
86 0x8086, // Vendor ID
87 0x8a70, // Device ID
88 },
89 //
90 // Option Rom for
91 //
92 {
93 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
94 0x0, // Segment
95 0x0, // Bus Number
96 0x2, // Device Number
97 0x0, // Function Number
98 0x8086, // Vendor ID
99 0x1906, // Device ID
100 },
101 //
102 // Option Rom for
103 //
104 {
105 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
106 0x0, // Segment
107 0x0, // Bus Number
108 0x2, // Device Number
109 0x0, // Function Number
110 0x8086, // Vendor ID
111 0x1913, // Device ID
112 },
113 //
114 // Option Rom for
115 //
116 {
117 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
118 0x0, // Segment
119 0x0, // Bus Number
120 0x2, // Device Number
121 0x0, // Function Number
122 0x8086, // Vendor ID
123 0x1916, // Device ID
124 },
125 //
126 // Option Rom for
127 //
128 {
129 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
130 0x0, // Segment
131 0x0, // Bus Number
132 0x2, // Device Number
133 0x0, // Function Number
134 0x8086, // Vendor ID
135 0x1921, // Device ID
136 },
137 //
138 // Option Rom for
139 //
140 {
141 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
142 0x0, // Segment
143 0x0, // Bus Number
144 0x2, // Device Number
145 0x0, // Function Number
146 0x8086, // Vendor ID
147 0x1926, // Device ID
148 },
149 //
150 // Option Rom for
151 //
152 {
153 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
154 0x0, // Segment
155 0x0, // Bus Number
156 0x2, // Device Number
157 0x0, // Function Number
158 0x8086, // Vendor ID
159 0x190b, // Device ID
160 },
161 //
162 // Option Rom for
163 //
164 {
165 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
166 0x0, // Segment
167 0x0, // Bus Number
168 0x2, // Device Number
169 0x0, // Function Number
170 0x8086, // Vendor ID
171 0x191b, // Device ID
172 },
173 //
174 // Option Rom for
175 //
176 {
177 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
178 0x0, // Segment
179 0x0, // Bus Number
180 0x2, // Device Number
181 0x0, // Function Number
182 0x8086, // Vendor ID
183 0x192b, // Device ID
184 },
185 //
186 // Option Rom for
187 //
188 {
189 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
190 0x0, // Segment
191 0x0, // Bus Number
192 0x2, // Device Number
193 0x0, // Function Number
194 0x8086, // Vendor ID
195 0x193b, // Device ID
196 },
197 //
198 // Option Rom for
199 //
200 {
201 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
202 0x0, // Segment
203 0x0, // Bus Number
204 0x2, // Device Number
205 0x0, // Function Number
206 0x8086, // Vendor ID
207 0x192d, // Device ID
208 },
209 //
210 // Option Rom for
211 //
212 {
213 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
214 0x0, // Segment
215 0x0, // Bus Number
216 0x2, // Device Number
217 0x0, // Function Number
218 0x8086, // Vendor ID
219 0x193d, // Device ID
220 },
221 //
222 // Option Rom for
223 //
224 {
225 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
226 0x0, // Segment
227 0x0, // Bus Number
228 0x2, // Device Number
229 0x0, // Function Number
230 0x8086, // Vendor ID
231 0x190e, // Device ID
232 },
233 //
234 // Option Rom for
235 //
236 {
237 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
238 0x0, // Segment
239 0x0, // Bus Number
240 0x2, // Device Number
241 0x0, // Function Number
242 0x8086, // Vendor ID
243 0x1915, // Device ID
244 },
245 //
246 // Option Rom for
247 //
248 {
249 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
250 0x0, // Segment
251 0x0, // Bus Number
252 0x2, // Device Number
253 0x0, // Function Number
254 0x8086, // Vendor ID
255 0x191e, // Device ID
256 },
257 //
258 // Option Rom for
259 //
260 {
261 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
262 0x0, // Segment
263 0x0, // Bus Number
264 0x2, // Device Number
265 0x0, // Function Number
266 0x8086, // Vendor ID
267 0x190a, // Device ID
268 },
269 //
270 // Option Rom for
271 //
272 {
273 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
274 0x0, // Segment
275 0x0, // Bus Number
276 0x2, // Device Number
277 0x0, // Function Number
278 0x8086, // Vendor ID
279 0x191a, // Device ID
280 },
281 //
282 // Option Rom for
283 //
284 {
285 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
286 0x0, // Segment
287 0x0, // Bus Number
288 0x2, // Device Number
289 0x0, // Function Number
290 0x8086, // Vendor ID
291 0x192a, // Device ID
292 },
293 //
294 // Option Rom for
295 //
296 {
297 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
298 0x0, // Segment
299 0x0, // Bus Number
300 0x2, // Device Number
301 0x0, // Function Number
302 0x8086, // Vendor ID
303 0x193a, // Device ID
304 },
305 //
306 // Option Rom for
307 //
308 {
309 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
310 0x0, // Segment
311 0x0, // Bus Number
312 0x2, // Device Number
313 0x0, // Function Number
314 0x8086, // Vendor ID
315 0x1902, // Device ID
316 },
317 //
318 // Option Rom for
319 //
320 {
321 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
322 0x0, // Segment
323 0x0, // Bus Number
324 0x2, // Device Number
325 0x0, // Function Number
326 0x8086, // Vendor ID
327 0x1912, // Device ID
328 },
329 //
330 // Option Rom for
331 //
332 {
333 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
334 0x0, // Segment
335 0x0, // Bus Number
336 0x2, // Device Number
337 0x0, // Function Number
338 0x8086, // Vendor ID
339 0x1917, // Device ID
340 },
341 //
342 // Option Rom for
343 //
344 {
345 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
346 0x0, // Segment
347 0x0, // Bus Number
348 0x2, // Device Number
349 0x0, // Function Number
350 0x8086, // Vendor ID
351 0x1932, // Device ID
352 },
353 //
354 // Option Rom for
355 //
356 {
357 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
358 0x0, // Segment
359 0x0, // Bus Number
360 0x2, // Device Number
361 0x0, // Function Number
362 0x8086, // Vendor ID
363 0x191d, // Device ID
364 },
365 //
366 // Option Rom for
367 //
368 {
369 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
370 0x0, // Segment
371 0x0, // Bus Number
372 0x2, // Device Number
373 0x0, // Function Number
374 0x8086, // Vendor ID
375 0x5906, // Device ID
376 },
377 //
378 // Option Rom for
379 //
380 {
381 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
382 0x0, // Segment
383 0x0, // Bus Number
384 0x2, // Device Number
385 0x0, // Function Number
386 0x8086, // Vendor ID
387 0x5913, // Device ID
388 },
389 //
390 // Option Rom for
391 //
392 {
393 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
394 0x0, // Segment
395 0x0, // Bus Number
396 0x2, // Device Number
397 0x0, // Function Number
398 0x8086, // Vendor ID
399 0x5916, // Device ID
400 },
401 //
402 // Option Rom for
403 //
404 {
405 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
406 0x0, // Segment
407 0x0, // Bus Number
408 0x2, // Device Number
409 0x0, // Function Number
410 0x8086, // Vendor ID
411 0x5921, // Device ID
412 },
413 //
414 // Option Rom for
415 //
416 {
417 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
418 0x0, // Segment
419 0x0, // Bus Number
420 0x2, // Device Number
421 0x0, // Function Number
422 0x8086, // Vendor ID
423 0x5926, // Device ID
424 },
425 //
426 // Option Rom for
427 //
428 {
429 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
430 0x0, // Segment
431 0x0, // Bus Number
432 0x2, // Device Number
433 0x0, // Function Number
434 0x8086, // Vendor ID
435 0x590b, // Device ID
436 },
437 //
438 // Option Rom for
439 //
440 {
441 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
442 0x0, // Segment
443 0x0, // Bus Number
444 0x2, // Device Number
445 0x0, // Function Number
446 0x8086, // Vendor ID
447 0x591b, // Device ID
448 },
449 //
450 // Option Rom for
451 //
452 {
453 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
454 0x0, // Segment
455 0x0, // Bus Number
456 0x2, // Device Number
457 0x0, // Function Number
458 0x8086, // Vendor ID
459 0x592b, // Device ID
460 },
461 //
462 // Option Rom for
463 //
464 {
465 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
466 0x0, // Segment
467 0x0, // Bus Number
468 0x2, // Device Number
469 0x0, // Function Number
470 0x8086, // Vendor ID
471 0x593b, // Device ID
472 },
473 //
474 // Option Rom for
475 //
476 {
477 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
478 0x0, // Segment
479 0x0, // Bus Number
480 0x2, // Device Number
481 0x0, // Function Number
482 0x8086, // Vendor ID
483 0x590e, // Device ID
484 },
485 //
486 // Option Rom for
487 //
488 {
489 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
490 0x0, // Segment
491 0x0, // Bus Number
492 0x2, // Device Number
493 0x0, // Function Number
494 0x8086, // Vendor ID
495 0x5915, // Device ID
496 },
497 //
498 // Option Rom for
499 //
500 {
501 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
502 0x0, // Segment
503 0x0, // Bus Number
504 0x2, // Device Number
505 0x0, // Function Number
506 0x8086, // Vendor ID
507 0x591e, // Device ID
508 },
509 //
510 // Option Rom for
511 //
512 {
513 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
514 0x0, // Segment
515 0x0, // Bus Number
516 0x2, // Device Number
517 0x0, // Function Number
518 0x8086, // Vendor ID
519 0x590a, // Device ID
520 },
521 //
522 // Option Rom for
523 //
524 {
525 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
526 0x0, // Segment
527 0x0, // Bus Number
528 0x2, // Device Number
529 0x0, // Function Number
530 0x8086, // Vendor ID
531 0x591a, // Device ID
532 },
533 //
534 // Option Rom for
535 //
536 {
537 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
538 0x0, // Segment
539 0x0, // Bus Number
540 0x2, // Device Number
541 0x0, // Function Number
542 0x8086, // Vendor ID
543 0x592a, // Device ID
544 },
545 //
546 // Option Rom for
547 //
548 {
549 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
550 0x0, // Segment
551 0x0, // Bus Number
552 0x2, // Device Number
553 0x0, // Function Number
554 0x8086, // Vendor ID
555 0x593a, // Device ID
556 },
557 //
558 // Option Rom for
559 //
560 {
561 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
562 0x0, // Segment
563 0x0, // Bus Number
564 0x2, // Device Number
565 0x0, // Function Number
566 0x8086, // Vendor ID
567 0x5902, // Device ID
568 },
569 //
570 // Option Rom for
571 //
572 {
573 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
574 0x0, // Segment
575 0x0, // Bus Number
576 0x2, // Device Number
577 0x0, // Function Number
578 0x8086, // Vendor ID
579 0x5912, // Device ID
580 },
581 //
582 // Option Rom for
583 //
584 {
585 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
586 0x0, // Segment
587 0x0, // Bus Number
588 0x2, // Device Number
589 0x0, // Function Number
590 0x8086, // Vendor ID
591 0x5917, // Device ID
592 },
593 //
594 // Option Rom for
595 //
596 {
597 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
598 0x0, // Segment
599 0x0, // Bus Number
600 0x2, // Device Number
601 0x0, // Function Number
602 0x8086, // Vendor ID
603 0x5932, // Device ID
604 },
605 //
606 // Option Rom for
607 //
608 {
609 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
610 0x0, // Segment
611 0x0, // Bus Number
612 0x2, // Device Number
613 0x0, // Function Number
614 0x8086, // Vendor ID
615 0x591d, // Device ID
616 },
617 //
618 // Option Rom for
619 //
620 {
621 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
622 0x0, // Segment
623 0x0, // Bus Number
624 0x2, // Device Number
625 0x0, // Function Number
626 0x8086, // Vendor ID
627 0x593d, // Device ID
628 },
629 //
630 // Option Rom for
631 //
632 {
633 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
634 0x0, // Segment
635 0x0, // Bus Number
636 0x2, // Device Number
637 0x0, // Function Number
638 0x8086, // Vendor ID
639 0x2a42, // Device ID
640 },
641 //
642 // Option Rom for
643 //
644 {
645 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
646 0x0, // Segment
647 0x0, // Bus Number
648 0x2, // Device Number
649 0x0, // Function Number
650 0x8086, // Vendor ID
651 0x106, // Device ID
652 },
653 //
654 // Option Rom for
655 //
656 {
657 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
658 0x0, // Segment
659 0x0, // Bus Number
660 0x2, // Device Number
661 0x0, // Function Number
662 0x8086, // Vendor ID
663 0x116, // Device ID
664 },
665 //
666 // Option Rom for
667 //
668 {
669 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
670 0x0, // Segment
671 0x0, // Bus Number
672 0x2, // Device Number
673 0x0, // Function Number
674 0x8086, // Vendor ID
675 0x126, // Device ID
676 },
677 //
678 // Option Rom for
679 //
680 {
681 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
682 0x0, // Segment
683 0x0, // Bus Number
684 0x2, // Device Number
685 0x0, // Function Number
686 0x8086, // Vendor ID
687 0xa02, // Device ID
688 },
689 //
690 // Option Rom for
691 //
692 {
693 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
694 0x0, // Segment
695 0x0, // Bus Number
696 0x2, // Device Number
697 0x0, // Function Number
698 0x8086, // Vendor ID
699 0x102, // Device ID
700 },
701 //
702 // Option Rom for
703 //
704 {
705 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
706 0x0, // Segment
707 0x0, // Bus Number
708 0x2, // Device Number
709 0x0, // Function Number
710 0x8086, // Vendor ID
711 0x112, // Device ID
712 },
713 //
714 // Option Rom for
715 //
716 {
717 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
718 0x0, // Segment
719 0x0, // Bus Number
720 0x2, // Device Number
721 0x0, // Function Number
722 0x8086, // Vendor ID
723 0x122, // Device ID
724 },
725 //
726 // Option Rom for
727 //
728 {
729 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
730 0x0, // Segment
731 0x0, // Bus Number
732 0x2, // Device Number
733 0x0, // Function Number
734 0x8086, // Vendor ID
735 0x10a, // Device ID
736 },
737 //
738 // Option Rom for
739 //
740 {
741 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
742 0x0, // Segment
743 0x0, // Bus Number
744 0x2, // Device Number
745 0x0, // Function Number
746 0x8086, // Vendor ID
747 0x5a51, // Device ID
748 },
749 //
750 // Option Rom for
751 //
752 {
753 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
754 0x0, // Segment
755 0x0, // Bus Number
756 0x2, // Device Number
757 0x0, // Function Number
758 0x8086, // Vendor ID
759 0x5a52, // Device ID
760 },
761 //
762 // Option Rom for
763 //
764 {
765 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
766 0x0, // Segment
767 0x0, // Bus Number
768 0x2, // Device Number
769 0x0, // Function Number
770 0x8086, // Vendor ID
771 0x5a5a, // Device ID
772 },
773 //
774 // Option Rom for
775 //
776 {
777 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
778 0x0, // Segment
779 0x0, // Bus Number
780 0x2, // Device Number
781 0x0, // Function Number
782 0x8086, // Vendor ID
783 0x5a42, // Device ID
784 },
785 //
786 // Option Rom for
787 //
788 {
789 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
790 0x0, // Segment
791 0x0, // Bus Number
792 0x2, // Device Number
793 0x0, // Function Number
794 0x8086, // Vendor ID
795 0x5a4a, // Device ID
796 },
797 //
798 // Option Rom for
799 //
800 {
801 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
802 0x0, // Segment
803 0x0, // Bus Number
804 0x2, // Device Number
805 0x0, // Function Number
806 0x8086, // Vendor ID
807 0x5a62, // Device ID
808 },
809 //
810 // Option Rom for
811 //
812 {
813 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
814 0x0, // Segment
815 0x0, // Bus Number
816 0x2, // Device Number
817 0x0, // Function Number
818 0x8086, // Vendor ID
819 0x5a54, // Device ID
820 },
821 //
822 // Option Rom for
823 //
824 {
825 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
826 0x0, // Segment
827 0x0, // Bus Number
828 0x2, // Device Number
829 0x0, // Function Number
830 0x8086, // Vendor ID
831 0x5a44, // Device ID
832 },
833 //
834 // Option Rom for
835 //
836 {
837 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
838 0x0, // Segment
839 0x0, // Bus Number
840 0x2, // Device Number
841 0x0, // Function Number
842 0x8086, // Vendor ID
843 0x5a55, // Device ID
844 },
845 //
846 // Option Rom for
847 //
848 {
849 MOBILE_ONBOARD_VIDEO_OPTION_ROM_FILE_GUID, // Guid
850 0x0, // Segment
851 0x0, // Bus Number
852 0x2, // Device Number
853 0x0, // Function Number
854 0x8086, // Vendor ID
855 0x5a45, // Device ID
856 },
857 //
858 // Option Rom for
859 //
860 {
861 RAID_OPTION_ROM_FILE_GUID, // Guid
862 0x0, // Segment
863 0x0, // Bus Number
864 0x17, // Device Number
865 0x0, // Function Number
866 0x8086, // Vendor ID
867 0x282a, // Device ID
868 },
869 //
870 // Option Rom for
871 //
872 {
873 RAID_OPTION_ROM_FILE_GUID, // Guid
874 0x0, // Segment
875 0x0, // Bus Number
876 0x17, // Device Number
877 0x0, // Function Number
878 0x8086, // Vendor ID
879 0x2822, // Device ID
880 },
881 //
882 // Option Rom for
883 //
884 {
885 RSTE_OPTION_ROM_FILE_GUID, // Guid
886 0x0, // Segment
887 0x0, // Bus Number
888 0x17, // Device Number
889 0x0, // Function Number
890 0x8086, // Vendor ID
891 0x2826, // Device ID
892 },
893 //
894 // Option Rom for
895 //
896 {
897 PXE_OPTION_ROM_FILE_GUID, // Guid
898 0x0, // Segment
899 0x0, // Bus Number
900 0x1f, // Device Number
901 0x6, // Function Number
902 0xffff, // Vendor ID
903 0xffff, // Device ID
904 },
905 //
906 // End of OptionRom Entries
907 //
908 {
909 NULL_ROM_FILE_GUID, // Guid
910 0, // Segment
911 0, // Bus Number
912 0, // Device Number
913 0, // Function Number
914 0xffff, // Vendor ID
915 0xffff, // Device ID
916 }
917 };
918
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformPostCode.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
PlatformPostCode.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define BOARD_INIT_PREMEM_ENTRY 0xD500
[definition] PostCode = XYZZ X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver, "5"=board driver ZZ - "00"=entry, "7F"=exit More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright (c) 2016-2020 Intel Corporation. All rights reserved

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformPostCode.h.

Macro Definition Documentation

◆ BOARD_INIT_PREMEM_ENTRY

#define BOARD_INIT_PREMEM_ENTRY 0xD500

[definition] PostCode = XYZZ X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE Y - "6"=platform driver, "5"=board driver ZZ - "00"=entry, "7F"=exit

  • 1 - board init premem: entry/exit (0xD500/0xD57F)
  • 2 - platform init premem: entry/exit (0xD600/0xD67F)
  • 3 - board init postmem: entry/exit (0x9500/0x957F)
  • 4 - platform init postmem: entry/exit (0x9600/0x967F)
  • 5 - board init DXE: entry/exit (0x7500/0x757F)
  • 6 - platform init DXE: entry/exit (0x7600/0x767F)
  • 7 - platform SMM init: entry/exit (0x8600/0x867F)
  • 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
  • 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
  • 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC

Definition at line 58 of file PlatformPostCode.h.


AlderLake Platform Sample Code: PlatformPostCode.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PlatformPostCode.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright (c) 2016-2020 Intel Corporation. All rights reserved
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33 #ifndef _PLATFORMPOSTCODE_H_
34 #define _PLATFORMPOSTCODE_H_
35
36 //
37 // GENERAL USAGE GUIDELINES
38 //
39
40 /**
41 [definition]
42 PostCode = XYZZ
43 X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE
44 Y - "6"=platform driver, "5"=board driver
45 ZZ - "00"=entry, "7F"=exit
46 - 1 - board init premem: entry/exit (0xD500/0xD57F)
47 - 2 - platform init premem: entry/exit (0xD600/0xD67F)
48 - 3 - board init postmem: entry/exit (0x9500/0x957F)
49 - 4 - platform init postmem: entry/exit (0x9600/0x967F)
50 - 5 - board init DXE: entry/exit (0x7500/0x757F)
51 - 6 - platform init DXE: entry/exit (0x7600/0x767F)
52 - 7 - platform SMM init: entry/exit (0x8600/0x867F)
53 - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
54 - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
55 - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC
56 */
57
58 #define BOARD_INIT_PREMEM_ENTRY 0xD500
59 #define BOARD_INIT_PREMEM_EXIT 0xD57F
60 #define PLATFORM_INIT_PREMEM_ENTRY 0xD600
61 #define PLATFORM_INIT_PREMEM_EXIT 0xD67F
62 #define BOARD_INIT_POSTMEM_ENTRY 0x9500
63 #define BOARD_INIT_POSTMEM_EXIT 0x957F
64 #define PLATFORM_INIT_POSTMEM_ENTRY 0x9600
65 #define PLATFORM_INIT_POSTMEM_EXIT 0x967F
66 #define BOARD_INIT_DXE_ENTRY 0x7500
67 #define BOARD_INIT_DXE_EXIT 0x757F
68 #define PLATFORM_INIT_DXE_ENTRY 0x7600
69 #define PLATFORM_INIT_DXE_EXIT 0x767F
70 #define PLATFORM_SMM_INIT_ENTRY 0x8600
71 #define PLATFORM_SMM_INIT_EXIT 0x867F
72 #define BIOS_S3_ENTRY 0xB503
73 #define BIOS_S4_ENTRY 0xB504
74 #define BIOS_S5_ENTRY 0xB505
75 #define GET_SET_TBT_SEC_LEVEL_ENTRY 0x7680
76 #define GET_SET_TBT_SEC_LEVEL_EXIT 0x7681
77
78 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformSecureLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PlatformSecureLib.h File Reference

Provides a secure platform-specific method to detect physically present user. More...

Go to the source code of this file.

Functions

EFI_STATUS PlatformSecureLibTestConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) BOOLEAN UserPhysicalPresent(VOID)
Constructor function for Platform Security library. More...

Detailed Description

Provides a secure platform-specific method to detect physically present user.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PlatformSecureLib.h.

Function Documentation

◆ PlatformSecureLibTestConstructor()

EFI_STATUS PlatformSecureLibTestConstructor | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Constructor function for Platform Security library.

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS When this function completed. This function provides a platform-specific method to detect whether the platform is operating by a physically present user.

Programmatic changing of platform security policy (such as disable Secure Boot, or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during Boot Services or after exiting EFI Boot Services. Only a physically present user is allowed to perform these operations.

NOTE THAT: This function cannot depend on any EFI Variable Service since they are not available when this function is called in AuthenticateVariable driver.

Return values
TRUE | The platform is operated by a physically present user.
FALSE | The platform is NOT operated by a physically present user.


AlderLake Platform Sample Code: PlatformSecureLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PlatformSecureLib.h
Go to the documentation of this file.
1 /** @file
2 Provides a secure platform-specific method to detect physically present user.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PLATFORM_SECURE_LIB_H__
36 #define __PLATFORM_SECURE_LIB_H__
37
38
39 /**
40 Constructor function for Platform Security library.
41
42 @param[in] ImageHandle The firmware allocated handle for the EFI image.
43 @param[in] SystemTable A pointer to the EFI System Table.
44
45 @retval EFI_SUCCESS When this function completed.
46
47 **/
48 EFI_STATUS
49 EFIAPI
50 PlatformSecureLibTestConstructor (
51 IN EFI_HANDLE ImageHandle,
52 IN EFI_SYSTEM_TABLE *SystemTable
53 )
54
55
56 /**
57
58 This function provides a platform-specific method to detect whether the platform
59 is operating by a physically present user.
60
61 Programmatic changing of platform security policy (such as disable Secure Boot,
62 or switch between Standard/Custom Secure Boot mode) MUST NOT be possible during
63 Boot Services or after exiting EFI Boot Services. Only a physically present user
64 is allowed to perform these operations.
65
66 NOTE THAT: This function cannot depend on any EFI Variable Service since they are
67 not available when this function is called in AuthenticateVariable driver.
68
69 @retval TRUE The platform is operated by a physically present user.
70 @retval FALSE The platform is NOT operated by a physically present user.
71
72 **/
73 BOOLEAN
74 EFIAPI
75 UserPhysicalPresent (
76 VOID
77 );
78
79 #endif
PlatformSecureLibTestConstructor
EFI_STATUS PlatformSecureLibTestConstructor(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable) BOOLEAN UserPhysicalPresent(VOID)
Constructor function for Platform Security library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformTelemetryLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PlatformTelemetryLib.h File Reference

Save LastUpdateTime to variable by different ImageTypeID. More...

Go to the source code of this file.

Functions

VOID SetLastUpdateTimeInVariable (EFI_GUID *ImageTypeGuid)
Saves the last update time value of the most recent FMP capsule update to a UEFI variable. More...

Detailed Description

Save LastUpdateTime to variable by different ImageTypeID.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PlatformTelemetryLib.h.

Function Documentation

◆ SetLastUpdateTimeInVariable()

VOID SetLastUpdateTimeInVariable ( EFI_GUID * ImageTypeGuid )

Saves the last update time value of the most recent FMP capsule update to a UEFI variable.

UEFI Variable accessed: GUID = gEfiCallerIdGuid, Name = L"LastUpdateTime"


AlderLake Platform Sample Code: PlatformTelemetryLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PlatformTelemetryLib.h
Go to the documentation of this file.
1 /** @file
2 Save LastUpdateTime to variable by different ImageTypeID.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __PLATFORM_TELEMETRY_LIB__
36 #define __PLATFORM_TELEMETRY_LIB__
37
38 /**
39 Saves the last update time value of the most recent FMP capsule update to
40 a UEFI variable.
41
42 UEFI Variable accessed: GUID = gEfiCallerIdGuid, Name = L"LastUpdateTime"
43
44 **/
45 VOID
46 SetLastUpdateTimeInVariable (
47 EFI_GUID *ImageTypeGuid
48 );
49
50 #endif
SetLastUpdateTimeInVariable
VOID SetLastUpdateTimeInVariable(EFI_GUID *ImageTypeGuid)
Saves the last update time value of the most recent FMP capsule update to a UEFI variable.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PolicyInitAdvancedDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
PolicyInitAdvancedDxe.c File Reference

This file is a wrapper for Platform Policy Advanced driver. More...

#include "PolicyInitAdvancedDxe.h"
#include <Library/PreSiliconEnvDetectLib.h>
Include dependency graph for PolicyInitAdvancedDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS PolicyInitAdvancedDxeEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy. More...

Detailed Description

This file is a wrapper for Platform Policy Advanced driver.

Get Setup Value to initialize Intel DXE Platform Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PolicyInitAdvancedDxe.c.

Function Documentation

◆ PolicyInitAdvancedDxeEntryPoint()

EFI_STATUS PolicyInitAdvancedDxeEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initialize DXE Platform Policy.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SystemTable | Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 54 of file PolicyInitAdvancedDxe.c.


AlderLake Platform Sample Code: PolicyInitAdvancedDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
PolicyInitAdvancedDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is a wrapper for Platform Policy Advanced driver. Get Setup
3 Value to initialize Intel DXE Platform Policy.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2013 - 2020 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #include "PolicyInitAdvancedDxe.h"
37 #include <Library/PreSiliconEnvDetectLib.h>
38
39 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFirmwareConfiguration = 0;
40
41 /**
42 Initialize DXE Platform Policy
43
44 @param[in] ImageHandle Image handle of this driver.
45 @param[in] SystemTable Global system service table.
46
47 @retval EFI_SUCCESS Initialization complete.
48 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
49 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
50 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
51 **/
52 EFI_STATUS
53 EFIAPI
54 PolicyInitAdvancedDxeEntryPoint (
55 IN EFI_HANDLE ImageHandle,
56 IN EFI_SYSTEM_TABLE *SystemTable
57 )
58 {
59 EFI_STATUS Status;
60 UINTN VarDataSize;
61 SETUP_DATA *SystemConfiguration = NULL;
62
63 Status = EFI_SUCCESS;
64
65 if (IsSimicsEnvironment()) {
66 Status = PcdSetBoolS (PcdResetOnMemoryTypeInformationChange, FALSE);
67 } else {
68 Status = PcdSetBoolS (PcdResetOnMemoryTypeInformationChange, TRUE);
69 }
70
71 if (EFI_ERROR (Status)) {
72 DEBUG ((DEBUG_ERROR, "Error: PcdSetBoolS failed @ line %d\n",__LINE__));
73 ASSERT_EFI_ERROR (Status);
74 } else {
75 DEBUG ((DEBUG_INFO, "Info: PcdResetOnMemoryTypeInformationChange is now False\n"));
76 }
77
78 VarDataSize = sizeof (SETUP_DATA);
79
80 SystemConfiguration = (SETUP_DATA *) AllocateZeroPool (VarDataSize);
81
82 mFirmwareConfiguration = 0;
83 if (SystemConfiguration == NULL) {
84 DEBUG ((DEBUG_ERROR, "Fail to allocate memory to get System Configuration!\n"));
85 ASSERT_EFI_ERROR (EFI_OUT_OF_RESOURCES);
86 return EFI_OUT_OF_RESOURCES;
87 } else {
88 Status = gRT->GetVariable (
89 L"Setup",
90 &gSetupVariableGuid,
91 NULL,
92 &VarDataSize,
93 SystemConfiguration
94 );
95
96 if (EFI_ERROR (Status)) {
97 DEBUG ((DEBUG_ERROR, "Fail to get System Configuration to identify the initial policy mode!\n"));
98 } else {
99 mFirmwareConfiguration = SystemConfiguration->FirmwareConfiguration;
100 }
101 }
102 //
103 // SystemAgent Dxe Platform Policy Initialization
104 //
105 Status = SaPolicyInitDxe (ImageHandle);
106 DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
107 ASSERT_EFI_ERROR (Status);
108
109 //
110 // PCH Dxe Platform Policy Initialization
111 //
112 Status = PchPolicyInitDxe (ImageHandle);
113 DEBUG ((DEBUG_INFO, "PCH Dxe Platform Policy Initialization status: %r\n", Status));
114 ASSERT_EFI_ERROR (Status);
115
116 //
117 // ME DXE Policy Initialization
118 //
119 Status = MePolicyInitDxe (ImageHandle);
120 DEBUG ((DEBUG_INFO, "ME DXE Policy Initialization status: %r\n", Status));
121 ASSERT_EFI_ERROR (Status);
122
123 //
124 // AMT DXE Policy Initialization
125 //
126 #if FixedPcdGetBool (PcdAmtEnable) == 1
127 Status = AmtPolicyInitDxe (ImageHandle);
128 DEBUG ((DEBUG_INFO, "AMT DXE Policy Initialization status: %r\n", Status));
129 #endif
130
131 //
132 // Silicon Dxe Platform Policy Initialization
133 //
134 Status = SiliconPolicyInitDxe (ImageHandle);
135 DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization status: %r\n", Status));
136 ASSERT_EFI_ERROR (Status);
137
138 //
139 // CPU DXE Platform Policy Initialization
140 //
141 Status = CpuPolicyInitDxe (ImageHandle);
142 DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization status: %r\n", Status));
143 ASSERT_EFI_ERROR (Status);
144
145
146 if (PcdGetBool (PcdIntelGopEnable)) {
147 //
148 // GOP Dxe Policy Initialization
149 //
150 Status = GopPolicyInitDxe (ImageHandle);
151 DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization status: %r\n", Status));
152 ASSERT_EFI_ERROR (Status);
153 }
154
155 //
156 // TBT Dxe Platform Policy Initialization
157 //
158 Status = TbtPolicyInitDxe (ImageHandle);
159 DEBUG((DEBUG_INFO, "TBT Dxe Platform Policy Initialization status: %r\n", Status));
160 ASSERT_EFI_ERROR (Status);
161
162 return EFI_SUCCESS;
163 }
CpuPolicyInitDxe
EFI_STATUS CpuPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Platform Policy.
Definition: CpuPolicyInitDxe.c:50
PolicyInitAdvancedDxeEntryPoint
EFI_STATUS PolicyInitAdvancedDxeEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy.
Definition: PolicyInitAdvancedDxe.c:54
GopPolicyInitDxe
EFI_STATUS GopPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize GOP DXE Policy.
Definition: GopPolicyInitDxe.c:219
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy.
Definition: SiliconPolicyInitDxe.c:51
AmtPolicyInitDxe
EFI_STATUS AmtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize Intel AMT DXE Policy.
Definition: AmtPolicyInitDxe.c:48
PolicyInitAdvancedDxe.h
Header file for the PolicyInitAdvancedDxe Driver.
MePolicyInitDxe
EFI_STATUS MePolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize ME DXE Policy.
Definition: MePolicyInitDxe.c:48
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy.
Definition: SaPolicyInitDxe.c:54
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy.
Definition: TbtPolicyInitDxe.c:53
PchPolicyInitDxe
EFI_STATUS PchPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize PCH DXE Policy.
Definition: PchPolicyInitDxe.c:51
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PolicyInitAdvancedDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
PolicyInitAdvancedDxe.h File Reference

Header file for the PolicyInitAdvancedDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
#include <Library/DebugLib.h>
#include <SetupVariable.h>
#include "AmtPolicyInitDxe.h"
#include "MePolicyInitDxe.h"
#include "SaPolicyInitDxe.h"
#include "PchPolicyInitDxe.h"
#include "SiliconPolicyInitDxe.h"
#include "GopPolicyInitDxe.h"
#include "CpuPolicyInitDxe.h"
#include "TbtPolicyInitDxe.h"
Include dependency graph for PolicyInitAdvancedDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS PolicyInitAdvancedDxeEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy. More...

Detailed Description

Header file for the PolicyInitAdvancedDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PolicyInitAdvancedDxe.h.

Function Documentation

◆ PolicyInitAdvancedDxeEntryPoint()

EFI_STATUS PolicyInitAdvancedDxeEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initialize DXE Platform Policy.

Parameters
[in] | ImageHandle | - Image handle of this driver.
[in] | SystemTable | - Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SystemTable | Global system service table.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 54 of file PolicyInitAdvancedDxe.c.


AlderLake Platform Sample Code: PolicyInitAdvancedDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
PolicyInitAdvancedDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PolicyInitAdvancedDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _POLICY_INIT_ADVANCED_DXE_H_
35 #define _POLICY_INIT_ADVANCED_DXE_H_
36
37
38 #include <Library/BaseMemoryLib.h>
39 #include <Library/UefiBootServicesTableLib.h>
40 #include <Library/UefiRuntimeServicesTableLib.h>
41 #include <Library/DebugLib.h>
42 #include <SetupVariable.h>
43
44 #include "AmtPolicyInitDxe.h"
45 #include "MePolicyInitDxe.h"
46 #include "SaPolicyInitDxe.h"
47 #include "PchPolicyInitDxe.h"
48 #include "SiliconPolicyInitDxe.h"
49 #include "GopPolicyInitDxe.h"
50 #include "CpuPolicyInitDxe.h"
51 #include "TbtPolicyInitDxe.h"
52
53 //#include <Library/DxeTbtPolicyLib.h>
54 /**
55 Initialize DXE Platform Policy
56
57 @param[in] ImageHandle - Image handle of this driver.
58 @param[in] SystemTable - Global system service table.
59
60 @retval EFI_SUCCESS Initialization complete.
61 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
62 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
63 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
64 **/
65
66 EFI_STATUS
67 EFIAPI
68 PolicyInitAdvancedDxeEntryPoint (
69 IN EFI_HANDLE ImageHandle,
70 IN EFI_SYSTEM_TABLE *SystemTable
71 );
72
73 #endif
MePolicyInitDxe.h
Header file for the MePolicyInitDxe Driver.
SaPolicyInitDxe.h
Header file for the SaPolicyInitDxe Driver.
AmtPolicyInitDxe.h
Header file for the AmtPolicyInitDxe Driver.
SiliconPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
GopPolicyInitDxe.h
Header file for the GopPolicyInitDxe Driver.
PchPolicyInitDxe.h
Header file for the PchPolicyInitDxe Driver.
TbtPolicyInitDxe.h
Header file for the TbtPolicyInitDxe Driver.
PolicyInitAdvancedDxeEntryPoint
EFI_STATUS PolicyInitAdvancedDxeEntryPoint(IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
Initialize DXE Platform Policy.
Definition: PolicyInitAdvancedDxe.c:54
CpuPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PolicyUpdateMacro.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PolicyUpdateMacro.h File Reference

Macros for platform to update different types of policy. More...

Go to the source code of this file.

Detailed Description

Macros for platform to update different types of policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file PolicyUpdateMacro.h.


AlderLake Platform Sample Code: PolicyUpdateMacro.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
PolicyUpdateMacro.h
Go to the documentation of this file.
1
2 /** @file
3 Macros for platform to update different types of policy.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 - 2020 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains 'Framework Code' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may not be
31 modified, except as allowed by additional terms of your license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _POLICY_UPDATE_MACRO_H_
37 #define _POLICY_UPDATE_MACRO_H_
38
39 #ifdef UPDATE_POLICY
40 #undef UPDATE_POLICY
41 #endif
42
43 #ifdef COPY_POLICY
44 #undef COPY_POLICY
45 #endif
46
47 #ifdef GET_POLICY
48 #undef GET_POLICY
49 #endif
50
51 #ifdef AND_POLICY
52 #undef AND_POLICY
53 #endif
54
55 #ifdef OR_POLICY
56 #undef OR_POLICY
57 #endif
58
59 #define NullIndex -1
60 #define POLICY_DEBUG_WARNING(ConfigField, SetupField, ArrayIndex) {\
61 DEBUG ((DEBUG_INFO, "Policy Default Mismatch With Setup Default\n"));\
62 DEBUG ((DEBUG_INFO, "ConfigBlock : " #ConfigField " = 0x%x\n", ConfigField));\
63 DEBUG ((DEBUG_INFO, "Setup : " #SetupField " = 0x%x\n", SetupField));\
64 if (ArrayIndex != NullIndex) {\
65 DEBUG ((DEBUG_INFO, "ArrayIndex : " #ArrayIndex " = 0x%x\n", ArrayIndex));\
66 }\
67 }
68
69 #if FixedPcdGet8(PcdFspModeSelection) == 1
70 //
71 // MACROS for platform code use
72 //
73 #define UPDATE_POLICY(UpdField, ConfigField, Value) UpdField = Value;
74 #define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (UpdField, Value, Size);
75 #define GET_POLICY(UpdField, ConfigField, Value) Value = UpdField;
76 #define AND_POLICY(UpdField, ConfigField, Value) UpdField &= Value;
77 #define OR_POLICY(UpdField, ConfigField, Value) UpdField |= Value;
78 //
79 // Compare Policy Default and Setup Default not support for API mode yet
80 //
81 #define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value, ArrayIndex) UPDATE_POLICY(UpdField, ConfigField, Value);
82 #else
83 #define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField = Value;
84 #define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (ConfigField, Value, Size);
85 #define GET_POLICY(UpdField, ConfigField, Value) Value = ConfigField;
86 #define AND_POLICY(UpdField, ConfigField, Value) ConfigField &= Value;
87 #define OR_POLICY(UpdField, ConfigField, Value) ConfigField |= Value;
88 //
89 // Compare Policy Default and Setup Default when FirstBoot and RvpSupport
90 //
91 #define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value, ArrayIndex) {\
92 if ((ConfigField != Value) && (IsPolicyDefaultCheckRequired())) {\
93 POLICY_DEBUG_WARNING(ConfigField, Value, ArrayIndex);\
94 }\
95 UPDATE_POLICY(UpdField, ConfigField, Value);\
96 }
97 #endif
98
99
100 #endif //_POLICY_UPDATE_MACRO_H_
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Ps2IoTrapHandler.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
Functions
Ps2IoTrapHandler.c File Reference
#include <Library/DebugLib.h>
#include <Library/SmmServicesTableLib.h>
#include <Library/IoLib.h>
#include <Library/BaseLib.h>
#include <Protocol/SmmIoTrapDispatch2.h>
#include <Protocol/PchSmmIoTrapControl.h>
#include <Protocol/SmmCpu.h>
#include <Library/CpuMailboxLib.h>
#include <Register/SaRegsHostBridge.h>
#include <Library/PciSegmentLib.h>
#include <Library/TimerLib.h>
#include <Protocol/MmMp.h>
#include <Library/SynchronizationLib.h>
#include <Register/Cpuid.h>
Include dependency graph for Ps2IoTrapHandler.c:

Go to the source code of this file.

Functions

EFI_STATUS | DttMailboxCoreParkHint (IN BOOLEAN ParkEnable)
Write to pCode DTT Mailbox to enable/disable core parking. More...
VOID | Ps2IoTrapHandler (IN EFI_HANDLE DispatchHandle, IN CONST EFI_SMM_IO_TRAP_CONTEXT *DispatchContext, IN OUT VOID *CommBuffer, IN OUT UINTN *CommBufferSize)
Traps on writes to IO port 60 and when a write occurs, the funtion will check for the Scroll lock LED command and then perform core parking when the LED is ON and remove parking when the LED is OFF. More...
VOID | GetCppIndexCoreInformation (VOID)
Get the CPP Inex information for all the Efficient Cores.
EFI_STATUS | SetupPs2IoTrap (VOID)
Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Ps2IoTrapHandler.c.

Function Documentation

◆ DttMailboxCoreParkHint()

EFI_STATUS DttMailboxCoreParkHint ( IN BOOLEAN ParkEnable )

Write to pCode DTT Mailbox to enable/disable core parking.

Parameters
[in] BOOLEAN ParkEnable - boolean indicating core parlking to be enabled or disabled.
Return values
EFI_SUCCESS Function successfully executed.

Definition at line 82 of file Ps2IoTrapHandler.c.

◆ Ps2IoTrapHandler()

VOID Ps2IoTrapHandler | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST EFI_SMM_IO_TRAP_CONTEXT * | DispatchContext,
 |  | IN OUT VOID * | CommBuffer,
 |  | IN OUT UINTN * | CommBufferSize
 | ) |  |

Traps on writes to IO port 60 and when a write occurs, the funtion will check for the Scroll lock LED command and then perform core parking when the LED is ON and remove parking when the LED is OFF.

Parameters
[in] | DispatchHandle | - Handle of this dispatch function
[in] | DispatchContext | - Pointer to the dispatch function's context. The DispatchContext fields are filled in by the dispatching driver prior to invoke this dispatch function
[in] | CommBuffer | - Point to the CommBuffer structure
[in] | CommBufferSize | - Point to the Size of CommBuffer structure

Definition at line 140 of file Ps2IoTrapHandler.c.

◆ SetupPs2IoTrap()

EFI_STATUS SetupPs2IoTrap ( VOID )

Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.

Return values
EFI_SUCCESS Function successfully executed.

Definition at line 264 of file Ps2IoTrapHandler.c.


AlderLake Platform Sample Code: Ps2IoTrapHandler.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
Ps2IoTrapHandler.c
Go to the documentation of this file.
1 /**@file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 //
36 // Module specific Includes
37 //
38 #include <Library/DebugLib.h>
39 #include <Library/SmmServicesTableLib.h>
40 #include <Library/IoLib.h>
41 #include <Library/BaseLib.h>
42 #include <Protocol/SmmIoTrapDispatch2.h>
43 #include <Protocol/PchSmmIoTrapControl.h>
44 #include <Protocol/SmmCpu.h>
45 #include <Library/CpuMailboxLib.h>
46 #include <Register/SaRegsHostBridge.h>
47 #include <Library/PciSegmentLib.h>
48 #include <Library/TimerLib.h>
49 #include <Protocol/MmMp.h>
50 #include <Library/SynchronizationLib.h>
51
52 #include <Register/Cpuid.h>
53
54 #if FixedPcdGetBool (PcdAdlLpSupport) == 0
55
56 //
57 // Global variables
58 //
59 GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mSmmIoTrapDispatch;
60 GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *mPchSmmIoTrapControl;
61 GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_IO_TRAP_REGISTER_CONTEXT mPs2IoTrapContext64;
62 GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mPs2IoTrapHandle64;
63
64 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gSmmState; // Track State Machine for SMM IO Trap
65 GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gSmmLedState; // Track State Machine for SMM IO Trap
66 GLOBAL_REMOVE_IF_UNREFERENCED volatile UINT32 mEfficientCoreCount; //Track the number Efficient Cores Found
67 GLOBAL_REMOVE_IF_UNREFERENCED volatile UINT32 mEfficientCoreModuleIndexMap; //Track the CCP Index. Bitwise map. Bits set for all Efficient Core CPP Index.
68
69 #define SMM_MP_DEF_TIMEOUT_US 000
70
71 #define DTT_MAILBOX_INTERFACE_OFFSET 0x5818 // Offset 0x5818 DTT mailbox command/status port
72 #define DTT_MAILBOX_DATA_OFFSET 0x5810 // Offset 0x5810 DTT mailbox data port
73 #define MAX_CPP_INDEX 32 // Maximum number of Bits we can hold in mEfficientCoreModuleIndexMap
74
75 /**
76 Write to pCode DTT Mailbox to enable/disable core parking
77
78 @param[in] BOOLEAN ParkEnable - boolean indicating core parlking to be enabled or disabled.
79
80 @retval EFI_SUCCESS Function successfully executed.
81 **/
82 EFI_STATUS DttMailboxCoreParkHint (
83 IN BOOLEAN ParkEnable
84 )
85 {
86 UINT32 MchBar;
87 UINT16 StallCount;
88 UINT8 CPPIndex;
89
90 StallCount = 0;
91
92 MchBar = PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MCHBAR)) & ~BIT0;
93
94 //
95 // Check for BIT31 (run busy bit) to be cleared before writing
96 //
97 for (CPPIndex = 0; CPPIndex < MAX_CPP_INDEX; CPPIndex++) {
98 if ((mEfficientCoreModuleIndexMap & (1 << CPPIndex)) != 0) {
99
100 while ((MmioRead32(MchBar + DTT_MAILBOX_INTERFACE_OFFSET) & BIT31) && ((StallCount < MAILBOX_WAIT_TIMEOUT))) {
101 //
102 // Wait for 1us
103 //
104 MicroSecondDelay(MAILBOX_WAIT_STALL);
105 StallCount++;
106 }
107 if (StallCount >= MAILBOX_WAIT_TIMEOUT) {
108 return EFI_TIMEOUT;
109 }
110 //
111 //Set data port with Mailbox data to indicate Core Parking
112 //
113 if (ParkEnable) {
114 MmioWrite32(MchBar + DTT_MAILBOX_DATA_OFFSET, 0xC0000000);
115 }
116 else {
117 MmioWrite32(MchBar + DTT_MAILBOX_DATA_OFFSET, 0x00000000);
118 }
119 //
120 //Set Command Port with Bit[31](trigger execution of command), Bit[23:16](0x0F), Bit[15:8](CCP index-core/module number), Bit[7:0] (0x1b to park)
121 //
122 MmioWrite32(MchBar + DTT_MAILBOX_INTERFACE_OFFSET, 0x800F001B | (CPPIndex << 8));
123 }
124 }
125 return EFI_SUCCESS;
126 }
127
128 /**
129 Traps on writes to IO port 60 and when a write occurs, the funtion will check for the Scroll lock LED command
130 and then perform core parking when the LED is ON and remove parking when the LED is OFF.
131
132 @param[in] DispatchHandle - Handle of this dispatch function
133 @param[in] DispatchContext - Pointer to the dispatch function's context.
134 The DispatchContext fields are filled in by the dispatching driver
135 prior to invoke this dispatch function
136 @param[in] CommBuffer - Point to the CommBuffer structure
137 @param[in] CommBufferSize - Point to the Size of CommBuffer structure
138 **/
139 VOID
140 Ps2IoTrapHandler (
141 IN EFI_HANDLE DispatchHandle,
142 IN CONST EFI_SMM_IO_TRAP_CONTEXT *DispatchContext,
143 IN OUT VOID *CommBuffer,
144 IN OUT UINTN *CommBufferSize
145 )
146 {
147 UINT8 IoPortValue;
148 EFI_STATUS Status;
149
150 //
151 // write back this port value in the port 60 (get the unmodified port value again)
152 //
153
154 IoPortValue = (UINT8)DispatchContext->WriteData;
155
156 Status = mPchSmmIoTrapControl->Pause(
157 mPchSmmIoTrapControl,
158 mPs2IoTrapHandle64
159 );
160 DEBUG((DEBUG_INFO, " SetupPs2IoTrap->Pause returned %r\n", Status));
161
162 gSmst->SmmIo.Io.Write(&gSmst->SmmIo,
163 SMM_IO_UINT8,
164 0x60,
165 1,
166 &IoPortValue);
167 Status = mPchSmmIoTrapControl->Resume(
168 mPchSmmIoTrapControl,
169 mPs2IoTrapHandle64
170 );
171 DEBUG((DEBUG_INFO, "SetupPs2IoTrap->Resume returned %r\n", Status));
172
173 switch (gSmmState) {
174 case 0x1:
175 //
176 // looking for LED command (0xED)
177 //
178 if (IoPortValue == 0xED) { //0xED SET LED Command
179 //
180 //Move to State 2 for Next
181 //
182 gSmmState = 0x2;
183
184 }
185 break;
186 case 0x2:
187 //
188 // is it scroll lock on or off?
189 //
190 IoPortValue = IoPortValue & 0x1;
191 if (IoPortValue == 0x1 && gSmmLedState == 0) { //BIT0 is Scroll Lock. Value 0x1 mean to Send pCode Hint
192 //
193 //Send command to pCode (Core Parking Enabled for Efficient Cores)
194 //
195 DEBUG((DEBUG_INFO, "Scroll Lock Set ON \n"));
196 //
197 // enable core parking
198 //
199 DttMailboxCoreParkHint(TRUE);
200 gSmmLedState = 1;
201 } else if (IoPortValue == 0x0 && gSmmLedState != 0) {
202 //
203 //Send command to pCode (Core Parking Disabled for Efficient Cores)
204 //
205 DEBUG((DEBUG_INFO, "Scroll Lock Set OFF \n"));
206 //
207 // disable core parking
208 //
209 DttMailboxCoreParkHint(FALSE);
210 gSmmLedState = 0;
211 }
212 //
213 // move state back to waiting on LED command
214 //
215 gSmmState = 0x1;
216 break;
217 }
218
219 return;
220 }
221
222 /**
223 Get the CPP Inex information for all the Efficient Cores
224 **/
225 VOID
226 GetCppIndexCoreInformation (
227 VOID
228 )
229 {
230 UINT8 CoreType;
231 UINT32 Eax;
232 UINT32 Edx;
233 UINT32 CppIndex;
234 UINT32 Value;
235
236 //
237 // Check which is the running core by reading CPUID.(EAX=1AH, ECX=00H):EAX
238 //
239 AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL);
240 CoreType = (UINT8)((Eax & 0xFF000000) >> 24);
241 if (CoreType == 0x20) { // Efficient Core
242 InterlockedIncrement (&mEfficientCoreCount);
243 AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, NULL, NULL, NULL, &Edx);
244 //
245 // Get CCP Index from Edx[31:16]
246 //
247 CppIndex = ((Edx & 0xFFFF0000) >> 16);
248 do {
249 Value = mEfficientCoreModuleIndexMap;
250 } while (InterlockedCompareExchange32 (
251 &mEfficientCoreModuleIndexMap,
252 Value,
253 Value | (1 << CppIndex)
254 ) != Value);
255 }
256 }
257
258 /**
259 Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.
260
261 @retval EFI_SUCCESS Function successfully executed.
262 **/
263 EFI_STATUS
264 SetupPs2IoTrap (
265 VOID
266 )
267 {
268 EFI_STATUS Status;
269 EFI_MM_MP_PROTOCOL *mSmmMp;
270
271 //
272 // Register SMM IO Trap
273 //
274 Status = gSmst->SmmLocateProtocol(&gEfiSmmIoTrapDispatch2ProtocolGuid, NULL, (VOID **)&mSmmIoTrapDispatch);
275 if (EFI_ERROR(Status)) {
276 DEBUG((DEBUG_ERROR, "Locate IoTrap Protocol returned %r\n", Status));
277 return Status;
278 }
279
280 //
281 // Register PS2 IO Trap Handler
282 //
283 DEBUG ((DEBUG_INFO, "Installing SetupPs2IoTrap Handler \n"));
284 mPs2IoTrapContext64.Type = WriteTrap;//ReadTrap;
285 mPs2IoTrapContext64.Length = 1;
286 mPs2IoTrapContext64.Address = 0x60; //PS2 Keyboard Data Port
287
288 Status = mSmmIoTrapDispatch->Register (
289 mSmmIoTrapDispatch,
290 (EFI_SMM_HANDLER_ENTRY_POINT2)Ps2IoTrapHandler,
291 &mPs2IoTrapContext64,
292 &mPs2IoTrapHandle64
293 );
294 DEBUG ((DEBUG_INFO, " Ps2 IoTrap register Status: %r\n", Status));
295
296 Status = gSmst->SmmLocateProtocol(&gEfiMmMpProtocolGuid, NULL, (VOID**)&mSmmMp);
297 if (EFI_ERROR (Status)) {
298 ASSERT_EFI_ERROR (Status);
299 return Status;
300 }
301
302 gSmmState = 0x1; //Start State is 1
303 gSmmLedState = 0; // starting LED state is off
304
305 mEfficientCoreCount = 0;
306 mEfficientCoreModuleIndexMap = 0;
307
308 GetCppIndexCoreInformation();
309 mSmmMp->BroadcastProcedure(
310 mSmmMp,
311 (EFI_AP_PROCEDURE2)GetCppIndexCoreInformation,
312 SMM_MP_DEF_TIMEOUT_US,
313 NULL,
314 NULL,
315 NULL
316 );
317
318 DEBUG ((DEBUG_INFO, " mEfficientCoreModuleIndexMap %x, Efficient Core - %x\n", mEfficientCoreModuleIndexMap, mEfficientCoreCount));
319 //
320 // Initialize global variable mPchSmmIoTrapControl to pause or resume the trap handler
321 //
322 Status = gSmst->SmmLocateProtocol (&gPchSmmIoTrapControlGuid, NULL, (VOID **) &mPchSmmIoTrapControl);
323 if (EFI_ERROR (Status)) {
324 ASSERT_EFI_ERROR (Status);
325 return Status;
326 }
327
328 return Status;
329 }
330 #endif
331
Ps2IoTrapHandler
VOID Ps2IoTrapHandler(IN EFI_HANDLE DispatchHandle, IN CONST EFI_SMM_IO_TRAP_CONTEXT *DispatchContext, IN OUT VOID *CommBuffer, IN OUT UINTN *CommBufferSize)
Traps on writes to IO port 60 and when a write occurs, the funtion will check for the Scroll lock LED...
Definition: Ps2IoTrapHandler.c:140
DttMailboxCoreParkHint
EFI_STATUS DttMailboxCoreParkHint(IN BOOLEAN ParkEnable)
Write to pCode DTT Mailbox to enable/disable core parking.
Definition: Ps2IoTrapHandler.c:82
SetupPs2IoTrap
EFI_STATUS SetupPs2IoTrap(VOID)
Initialize and register for the IO Trap SMI Handler to deal with Scroll lock presses.
Definition: Ps2IoTrapHandler.c:264
GetCppIndexCoreInformation
VOID GetCppIndexCoreInformation(VOID)
Get the CPP Inex information for all the Efficient Cores.
Definition: Ps2IoTrapHandler.c:226
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PssLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
PssLib.h File Reference

PSS(Processor Secured Storage) Chip Operation Library Header. More...

Go to the source code of this file.

Functions

EFI_STATUS | ReadPssData (UINT8 *Buffer, UINT32 Address, UINT32 Size)
Read data from PSS chip. More...
EFI_STATUS | WritePssData (UINT8 *Buffer, UINT32 Address, UINTN Size)
Write data to PSS chip. More...
EFI_STATUS | PssDetect (VOID)
Check PSS chip status. More...
EFI_STATUS | PssGetSerialNumber (UINT8 *Buffer, UINT32 Size)
Get 16 bytes Serial Number from PSS chip. More...

Detailed Description

PSS(Processor Secured Storage) Chip Operation Library Header.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PssLib.h.

Function Documentation

◆ PssDetect()

EFI_STATUS PssDetect ( VOID )

Check PSS chip status.

Parameters
[in] none
Return values
EFI_STATUS

◆ PssGetSerialNumber()

EFI_STATUS PssGetSerialNumber | ( | UINT8 * | Buffer,
 |  | UINT32 | Size
 | ) |  |

Get 16 bytes Serial Number from PSS chip.

Parameters
[in] | Buffer
[in] | Size
Return values
EFI_STATUS

◆ ReadPssData()

EFI_STATUS ReadPssData | ( | UINT8 * | Buffer,
 |  | UINT32 | Address,
 |  | UINT32 | Size
 | ) |  |

Read data from PSS chip.

Parameters
[out] | Buffer
[in] | Address
[in] | Size
Return values
EFI_STATUS

◆ WritePssData()

EFI_STATUS WritePssData | ( | UINT8 * | Buffer,
 |  | UINT32 | Address,
 |  | UINTN | Size
 | ) |  |

Write data to PSS chip.

Parameters
[in] | Buffer
[in] | Address
[in] | Size
Return values
EFI_STATUS
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PssLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
PssLib.h
Go to the documentation of this file.
1 /** @file
2 PSS(Processor Secured Storage) Chip Operation Library Header
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __PSS_LIB_H__
36 #define __PSS_LIB_H__
37
38 //
39 // Monza X-8K PSS Chip Memory Map
40 //
41 #define MONZAX_SIZE_RESERVED 22
42 #define MONZAX_SIZE_EPC 18
43 #define MONZAX_SIZE_TID 24
44 #define MONZAX_SIZE_USER 1024
45
46 #define PSS_BASE_ADDR_RESERVED 0x00
47 #define PSS_BASE_ADDR_EPC 0x16
48 #define PSS_BASE_ADDR_TID 0x28
49 #define PSS_BASE_ADDR_CLASSID 0x28
50 #define PSS_BASE_ADDR_USER 0x40
51 #define PSS_BASE_ADDR_MAX 0x43F // 0 ~ 0x43F
52
53 #define PSS_CHIP_TID_LENGTH 12
54
55 #define PSS_SN_LENGTH 16
56
57 //
58 // Intel PSS Chip Memory Layout Definition - Start
59 // Base address is BASE_ADDRESS_USER(0x40)
60 //
61 #define PSS_CHIP_BLOCK_0_START (0)
62 #define PSS_CHIP_BLOCK_1_START (PSS_CHIP_BLOCK_0_START + 64) // 0x40
63 #define PSS_CHIP_BLOCK_2_START (PSS_CHIP_BLOCK_1_START + 64) // 0x80
64 #define PSS_CHIP_BLOCK_3_START (PSS_CHIP_BLOCK_2_START + 64) // 0xC0
65 #define PSS_CHIP_BLOCK_4_START (PSS_CHIP_BLOCK_3_START + 64) // 0x100
66
67 #define PSS_CHIP_REWORK_OFFSET (PSS_CHIP_BLOCK_0_START) // 0x00
68 #define PSS_CHIP_REWORK_LENGTH (12) // Bytes
69 #define PSS_CHIP_STATUS_OFFSET (PSS_CHIP_REWORK_OFFSET + PSS_CHIP_REWORK_LENGTH) // 0x0C
70 #define PSS_CHIP_STATUS_LENGTH (12)
71 #define PSS_CHIP_LAST_PSS_UPDATE_OFFSET (PSS_CHIP_STATUS_OFFSET + PSS_CHIP_STATUS_LENGTH) // 0x18
72 #define PSS_CHIP_LAST_PSS_UPDATE_LENGTH (10)
73 #define PSS_CHIP_PMIC_VERSION_OFFSET (PSS_CHIP_LAST_PSS_UPDATE_OFFSET + PSS_CHIP_LAST_PSS_UPDATE_LENGTH) // 0x22
74 #define PSS_CHIP_PMIC_VERSION_LENGTH (6)
75 #define PSS_CHIP_ASSIGNED_USER_OFFSET (PSS_CHIP_PMIC_VERSION_OFFSET + PSS_CHIP_PMIC_VERSION_LENGTH) // 0x28
76 #define PSS_CHIP_ASSIGNED_USER_LENGTH (8)
77 #define PSS_CHIP_LOCATION_OFFSET (PSS_CHIP_ASSIGNED_USER_OFFSET + PSS_CHIP_ASSIGNED_USER_LENGTH) // 0x30
78 #define PSS_CHIP_LOCATION_LENGTH (16)
79
80 #define PSS_CHIP_BOARD_SERIAL_NUMBER_OFFSET (PSS_CHIP_BLOCK_1_START) // 0x40
81 #define PSS_CHIP_BOARD_SERIAL_NUMBER_LENGTH (16)
82 #define PSS_CHIP_WORK_ORDER_NUMBER_OFFSET (PSS_CHIP_BOARD_SERIAL_NUMBER_OFFSET + PSS_CHIP_BOARD_SERIAL_NUMBER_LENGTH) // 0x50
83 #define PSS_CHIP_WORK_ORDER_NUMBER_LENGTH (16)
84 #define PSS_CHIP_INTEL_PART_NUMBER_OFFSET (PSS_CHIP_WORK_ORDER_NUMBER_OFFSET + PSS_CHIP_WORK_ORDER_NUMBER_LENGTH) // 0x60
85 #define PSS_CHIP_INTEL_PART_NUMBER_LENGTH (12)
86 #define PSS_CHIP_PRODUCT_FAMILY_OFFSET (PSS_CHIP_INTEL_PART_NUMBER_OFFSET + PSS_CHIP_INTEL_PART_NUMBER_LENGTH) // 0x6C
87 #define PSS_CHIP_PRODUCT_FAMILY_LENGTH (20)
88
89 #define PSS_CHIP_LAST_RFID_SYNC_OFFSET (PSS_CHIP_BLOCK_2_START) // 0x80
90 #define PSS_CHIP_LAST_RFID_SYNC_LENGTH (10)
91 #define PSS_CHIP_DATE_SHIPPED_OFFSET (PSS_CHIP_LAST_RFID_SYNC_OFFSET + PSS_CHIP_LAST_RFID_SYNC_LENGTH) // 0x8A
92 #define PSS_CHIP_DATE_SHIPPED_LENGTH (10)
93 #define PSS_CHIP_SPECIAL_INSTRUCTIONS_OFFSET (PSS_CHIP_DATE_SHIPPED_OFFSET + PSS_CHIP_DATE_SHIPPED_LENGTH) // 0x94
94 #define PSS_CHIP_SPECIAL_INSTRUCTIONS_LENGTH (32)
95 #define PSS_CHIP_RECALL_OFFSET (PSS_CHIP_SPECIAL_INSTRUCTIONS_OFFSET + PSS_CHIP_SPECIAL_INSTRUCTIONS_LENGTH) // 0xB4
96 #define PSS_CHIP_RECALL_LENGTH (1)
97 #define PSS_CHIP_CONSUMPTION_METER_OFFSET (PSS_CHIP_RECALL_OFFSET + PSS_CHIP_RECALL_LENGTH) // 0xB5
98 #define PSS_CHIP_CONSUMPTION_METER_LENGTH (7)
99 #define PSS_CHIP_BOOT_COUNT_OFFSET (PSS_CHIP_CONSUMPTION_METER_OFFSET + PSS_CHIP_CONSUMPTION_METER_LENGTH) // 0xBC
100 #define PSS_CHIP_BOOT_COUNT_LENGTH (4)
101
102 #define PSS_CHIP_SOC_VERSION_OFFSET (PSS_CHIP_BLOCK_3_START) // 0xC0
103 #define PSS_CHIP_SOC_VERSION_LENGTH (8)
104 #define PSS_CHIP_BKC_VERSION_OFFSET (PSS_CHIP_SOC_VERSION_OFFSET + PSS_CHIP_SOC_VERSION_LENGTH) // 0xC8
105 #define PSS_CHIP_BKC_VERSION_LENGTH (16)
106 #define PSS_CHIP_OS_OFFSET (PSS_CHIP_BKC_VERSION_OFFSET + PSS_CHIP_BKC_VERSION_LENGTH) // 0xD8
107 #define PSS_CHIP_OS_LENGTH (16)
108 #define PSS_CHIP_IFWI_OFFSET (PSS_CHIP_OS_OFFSET + PSS_CHIP_OS_LENGTH) // 0xE8
109 #define PSS_CHIP_IFWI_LENGTH (24)
110
111 #define PSS_CHIP_LATITUDE_OFFSET (PSS_CHIP_BLOCK_4_START) // 0x100
112 #define PSS_CHIP_LATITUDE_LENGTH (8)
113 #define PSS_CHIP_LONGITUDE_OFFSET (PSS_CHIP_LATITUDE_OFFSET + PSS_CHIP_LATITUDE_LENGTH) // 0x108
114 #define PSS_CHIP_LONGITUDE_LENGTH (8)
115
116 #define PSS_CHIP_CLASS_ID 0xE2 // TID Offset 0 CLASS_ID[7:0] = 11100010b
117 #define PSS_CHIP_TID_DESIGNER_LOW 0x01 // TID Offset 2 Bit 4-7 TID_DESIGNER [3:0] = 0000b
118 #define PSS_CHIP_TID_MODEL_HIGH 0x01 // TID Offset 2 Bit 0-3 TID_MODEL [11:8] = 0001b
119 #define PSS_CHIP_TID_MODEL_LOW 0x50 // TID Offset 3 Bit 0-7 TID_MODEL [7:0] = 01010000b
120 //
121 // Intel PSS Chip Memory Layout Definition - End
122 //
123
124 #define IsLeap(y) (((y) % 4) == 0 && (((y) % 100) != 0 || ((y) % 400) == 0))
125 #define SECSPERMIN (60)
126 #define SECSPERHOUR (60 * 60)
127 #define SECSPERDAY (24 * SECSPERHOUR)
128
129 #pragma pack (1)
130 typedef struct _PSS_CHIP_STRING
131 {
132 UINT16 Offset;
133 UINT8 Length;
134 EFI_STRING_ID StringToken;
135 }PSS_CHIP_STRING;
136 #pragma pack ()
137
138 extern UINTN CumulativeDays[2][14];
139 extern CHAR8 *WeekDayName[];
140 extern CHAR8 *MonthName[];
141
142 /**
143 Read data from PSS chip.
144
145 @param[out] Buffer
146 @param[in] Address
147 @param[in] Size
148
149 @retval EFI_STATUS
150 **/
151 EFI_STATUS
152 EFIAPI
153 ReadPssData (
154 UINT8 *Buffer,
155 UINT32 Address,
156 UINT32 Size
157 );
158
159 /**
160 Write data to PSS chip.
161
162 @param[in] Buffer
163 @param[in] Address
164 @param[in] Size
165
166 @retval EFI_STATUS
167 **/
168 EFI_STATUS
169 EFIAPI
170 WritePssData (
171 UINT8 *Buffer,
172 UINT32 Address,
173 UINTN Size
174 );
175
176 /**
177 Check PSS chip status.
178
179 @param[in] none
180
181 @retval EFI_STATUS
182 **/
183 EFI_STATUS
184 EFIAPI
185 PssDetect (
186 VOID
187 );
188
189 /**
190 Get 16 bytes Serial Number from PSS chip.
191
192 @param[in] Buffer
193 @param[in] Size
194
195 @retval EFI_STATUS
196 **/
197 EFI_STATUS
198 EFIAPI
199 PssGetSerialNumber (
200 UINT8 *Buffer,
201 UINT32 Size
202 );
203
204 #endif
PssDetect
EFI_STATUS PssDetect(VOID)
Check PSS chip status.
WritePssData
EFI_STATUS WritePssData(UINT8 *Buffer, UINT32 Address, UINTN Size)
Write data to PSS chip.
ReadPssData
EFI_STATUS ReadPssData(UINT8 *Buffer, UINT32 Address, UINT32 Size)
Read data from PSS chip.
PssGetSerialNumber
EFI_STATUS PssGetSerialNumber(UINT8 *Buffer, UINT32 Size)
Get 16 bytes Serial Number from PSS chip.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PttInstance.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PttInstance.h File Reference

GUID definition for the PTT device instance. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

GUID definition for the PTT device instance.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file PttInstance.h.


AlderLake Platform Sample Code: PttInstance.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PttInstance.h
Go to the documentation of this file.
1 /** @file
2 GUID definition for the PTT device instance
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __PTT_INSTANCE_GUID_H__
36 #define __PTT_INSTANCE_GUID_H__
37
38 #define TPM_DEVICE_INTERFACE_TPM20_PTT \
39 { 0x72cd3a7b, 0xfea5, 0x4f5e, { 0x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13 } }
40
41 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PttPTPInstanceGuid.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PttPTPInstanceGuid.h File Reference

GUID definition for the PTT device instance. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

GUID definition for the PTT device instance.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file PttPTPInstanceGuid.h.


AlderLake Platform Sample Code: PttPTPInstanceGuid.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
PttPTPInstanceGuid.h
Go to the documentation of this file.
1 /** @file
2 GUID definition for the PTT device instance
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __PTT_PTP_INSTANCE_GUID_H__
36 #define __PTT_PTP_INSTANCE_GUID_H__
37
38 #define TPM_DEVICE_INTERFACE_TPM20_PTT_PTP \
39 { 0x93d66f66, 0x55da, 0x4f03, { 0x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a } }
40
41 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: RetimerCapsuleUpdate.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Macros | Typedefs
RetimerCapsuleUpdate.h File Reference

RetimerCapsuleUpdate driver definitions. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <PiDxe.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/EcTcssLib.h>
#include <Guid/SystemResourceTable.h>
#include <Protocol/EsrtManagement.h>
#include <Library/GpioLib.h>
#include <Library/GpioConfig.h>
Include dependency graph for RetimerCapsuleUpdate.h:

Go to the source code of this file.

Macros

#define TCSS_RETIMER_PROTOCOL_GUID
Global ID for the ESRT_MANAGEMENT_PROTOCOL.

Typedefs

typedef struct _TCSS_RETIMER_PROTOCOL | TCSS_RETIMER_PROTOCOL
Forward declaration for the _TCSS_RETIMER_PROTOCOL.
typedef EFI_STATUS(* | TCSS_RETIMER_INFO) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid, OUT TCSS_RETIMER_PROTOCOL_CAPABILITY *RetimerInfo)
Get TCSS Retimer Controller info and Capability. More...
typedef EFI_STATUS(* | FW_UPDATE_MODE_ENTRY) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)
Drive TCSS Retimer Controller into FW Update Mode. More...
typedef EFI_STATUS(* | FW_UPDATE_MODE_EXIT) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)
Restore TBT PD Controller into original mode. More...

Detailed Description

RetimerCapsuleUpdate driver definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file RetimerCapsuleUpdate.h.

Typedef Documentation

◆ FW_UPDATE_MODE_ENTRY

typedef EFI_STATUS( * FW_UPDATE_MODE_ENTRY) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)

Drive TCSS Retimer Controller into FW Update Mode.

Parameters
[in] | This | The TCSS RETIMER PROTOCOL Instance.
[in] | RetimerGuid | GUID from ESRT ACPI Table.
[out] | *RetimerInfo | Out buffer containing Retimer info of guid passed.
Return values
EFI_SUCCESS | Successfully Mode is Changed to FW Update Mode.
EFI_INVALID_PARAMETER | Invalid GUID from ESRT Table is Passed.
EFI_UNSUPPORTED | This driver does not support.
EFI_DEVICE_ERROR | This driver cannot be started due to device Error.
EFI_ALREADY_STARTED | This driver has been started.
EFI_TIMEOUT | DriveToFwUpdateMode Command timeout Happen.

Definition at line 138 of file RetimerCapsuleUpdate.h.

◆ FW_UPDATE_MODE_EXIT

typedef EFI_STATUS( * FW_UPDATE_MODE_EXIT) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)

Restore TBT PD Controller into original mode.

Parameters
[in] | This | The TCSS RETIMER PROTOCOL Instance.
[in] | RetimerGuid | GUID from ESRT ACPI Table.
Return values
EFI_SUCCESS | Successfully Mode is Restore.
EFI_INVALID_PARAMETER | Invalid GUID from ESRT Table is Passed.
EFI_UNSUPPORTED | This driver does not support.
EFI_DEVICE_ERROR | This driver cannot be started due to device Error.
EFI_NOT_STARTED | This driver has not been started.
EFI_TIMEOUT | RestoreToOriginalMode Command timeout Happen.

Definition at line 159 of file RetimerCapsuleUpdate.h.

◆ TCSS_RETIMER_INFO

typedef EFI_STATUS( * TCSS_RETIMER_INFO) (IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid, OUT TCSS_RETIMER_PROTOCOL_CAPABILITY *RetimerInfo)

Get TCSS Retimer Controller info and Capability.

Parameters
[in] | This | The TCSS RETIMER PROTOCOL Instance.
[in] | RetimerGuid | GUID from ESRT ACPI Table.
Return values
EFI_SUCCESS | Successfully Mode is Changed to FW Update Mode.
EFI_INVALID_PARAMETER | Invalid GUID from ESRT Table is Passed.
EFI_UNSUPPORTED | This driver does not support.
EFI_DEVICE_ERROR | This driver cannot be started due to device Error.
EFI_ALREADY_STARTED | This driver has been started.
EFI_TIMEOUT | Tcss Command timeout Happen.

Definition at line 114 of file RetimerCapsuleUpdate.h.


AlderLake Platform Sample Code: RetimerCapsuleUpdate.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
RetimerCapsuleUpdate.h
Go to the documentation of this file.
1 /** @file
2 RetimerCapsuleUpdate driver definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _RETIMER_CAPSULE_UPDATE_H_
36 #define _RETIMER_CAPSULE_UPDATE_H_
37
38 #include <Uefi.h>
39 #include <Library/BaseLib.h>
40 #include <Library/PcdLib.h>
41 #include <PiDxe.h>
42 #include <Library/DebugLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/UefiBootServicesTableLib.h>
45 #include <Library/EcTcssLib.h>
46 #include <Guid/SystemResourceTable.h>
47 #include <Protocol/EsrtManagement.h>
48 #include <Library/GpioLib.h>
49 #include <Library/GpioConfig.h>
50
51
52 // Macro Defination
53 #define RETIMER_TO_PD_MAPPING_PCD_TOTAL_WIDTH 32
54 #define RETIMER_TO_PD_MAPPING_PER_DEVICE_WIDTH 4
55 //
56 // Make Sure MAX_TBT_RETIMER_DEVICE must be equal to
57 // RETIMER_TO_PD_MAPPING_PCD_TOTAL_WIDTH / RETIMER_TO_PD_MAPPING_PER_DEVICE_WIDTH value.
58 // In this case it is 32/4 = 8.
59 //
60 #define MAX_TBT_RETIMER_DEVICE 8
61 #define INVALID_DEVICE_MODE 0xFF
62 #define INVALID_PD_CONTROLLER_INDEX 0xFF
63 #define ALL_PD_CONTROLLER 0xFE
64 #define RETIMER_DEVICE_AVAILABLE_BIT BIT3
65 #define PD_CONTROLLER_INDEX_BIT_MASK (BIT0 | BIT1 | BIT2)
66
67 #define NO_VALID_GUID_FOUND 0x00
68 #define TBT_RETIMER_VALID_GUID_FOUND BIT0
69 #define NON_TBT_I2C_RETIMER_VALID_GUID_FOUND BIT1
70
71 #define INVALID_I2C_RETIMER_INDEX 0xFF
72 #define ALL_I2C_RETIMER_SLAVE_DEVICE 0xFE
73 #define I2C_RETIMER_BUS_CONFIG_0_400_KHZ 400
74 #define I2C_RETIMER_HW_CONFIG_VERSION_1 1
75
76 #define INVALID_RETIMER_INDEX 0xFF
77 #define ALL_RETIMER_DEVICE 0xFE
78
79 ///
80 /// Forward declaration for the _TCSS_RETIMER_PROTOCOL.
81 ///
82 typedef struct _TCSS_RETIMER_PROTOCOL TCSS_RETIMER_PROTOCOL;
83 typedef struct _TCSS_RETIMER_PROTOCOL_CAPABILITY TCSS_RETIMER_PROTOCOL_CAPABILITY;
84
85 ///
86 /// Global ID for the ESRT_MANAGEMENT_PROTOCOL.
87 ///
88 // {B9AC2BD1-D450-4BEC-BD5B-192601119B84}
89 #define TCSS_RETIMER_PROTOCOL_GUID \
90 { \
91 0xB9AC2BD1, 0xD450, 0x4BEC, { 0xBD, 0x5B, 0x19, 0x26, 0x1, 0x11, 0x9B, 0x84 } \
92 }
93 //EFI_GUID gTcssRetimerProtocolGuid = { 0xB9AC2BD1, 0xD450, 0x4BEC, { 0xBD, 0x5B, 0x19, 0x26, 0x1, 0x11, 0x9B, 0x84 } };
94
95 extern EFI_GUID gTcssRetimerProtocolGuid;
96
97 // Structure Declaration
98
99 /**
100 Get TCSS Retimer Controller info and Capability.
101
102 @param[in] This The TCSS RETIMER PROTOCOL Instance.
103 @param[in] RetimerGuid GUID from ESRT ACPI Table.
104
105 @retval EFI_SUCCESS Successfully Mode is Changed to FW Update Mode.
106 @retval EFI_INVALID_PARAMETER Invalid GUID from ESRT Table is Passed.
107 @retval EFI_UNSUPPORTED This driver does not support.
108 @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error.
109 @retval EFI_ALREADY_STARTED This driver has been started.
110 @retval EFI_TIMEOUT Tcss Command timeout Happen.
111
112 **/
113 typedef
114 EFI_STATUS
115 (EFIAPI *TCSS_RETIMER_INFO)(
116 IN TCSS_RETIMER_PROTOCOL *This,
117 IN EFI_GUID RetimerGuid, ///< GUID from ESRT ACPI Table
118 OUT TCSS_RETIMER_PROTOCOL_CAPABILITY *RetimerInfo
119 );
120
121 /**
122 Drive TCSS Retimer Controller into FW Update Mode.
123
124 @param[in] This The TCSS RETIMER PROTOCOL Instance.
125 @param[in] RetimerGuid GUID from ESRT ACPI Table.
126
127 @param[out] *RetimerInfo Out buffer containing Retimer info of guid passed.
128
129 @retval EFI_SUCCESS Successfully Mode is Changed to FW Update Mode.
130 @retval EFI_INVALID_PARAMETER Invalid GUID from ESRT Table is Passed.
131 @retval EFI_UNSUPPORTED This driver does not support.
132 @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error.
133 @retval EFI_ALREADY_STARTED This driver has been started.
134 @retval EFI_TIMEOUT DriveToFwUpdateMode Command timeout Happen.
135
136 **/
137 typedef
138 EFI_STATUS
139 (EFIAPI *FW_UPDATE_MODE_ENTRY)(
140 IN TCSS_RETIMER_PROTOCOL *This,
141 IN EFI_GUID RetimerGuid ///< GUID from ESRT ACPI Table
142 );
143
144 /**
145 Restore TBT PD Controller into original mode.
146
147 @param[in] This The TCSS RETIMER PROTOCOL Instance.
148 @param[in] RetimerGuid GUID from ESRT ACPI Table.
149
150 @retval EFI_SUCCESS Successfully Mode is Restore.
151 @retval EFI_INVALID_PARAMETER Invalid GUID from ESRT Table is Passed.
152 @retval EFI_UNSUPPORTED This driver does not support.
153 @retval EFI_DEVICE_ERROR This driver cannot be started due to device Error.
154 @retval EFI_NOT_STARTED This driver has not been started.
155 @retval EFI_TIMEOUT RestoreToOriginalMode Command timeout Happen.
156
157 **/
158 typedef
159 EFI_STATUS
160 (EFIAPI *FW_UPDATE_MODE_EXIT)(
161 IN TCSS_RETIMER_PROTOCOL *This,
162 IN EFI_GUID RetimerGuid ///< GUID from ESRT ACPI Table
163 );
164
165 #pragma pack (push,1)
166 //
167 // Interface structure for the TBT retimer Protocol
168 //
169 struct _TCSS_RETIMER_PROTOCOL {
170 TCSS_RETIMER_INFO GetRetimerInfo; ///< Get TCSS Retimer Device info
171 FW_UPDATE_MODE_ENTRY Drive; ///< Drive TCSS retimer device into FW Update mode.
172 FW_UPDATE_MODE_EXIT Restore; ///< Restore TCSS retimer device into original mode.
173 };
174
175 struct _TCSS_RETIMER_PROTOCOL_CAPABILITY {
176 UINT8 RetimerType;
177 UINT8 RetimerDeviceCount;
178 UINT16 RetimerDeviceIndexBitMap;
179 UINT8 Reserved[12];
180 };
181
182 //
183 // Defining the Retimer Device Type Enum Variable
184 //
185 typedef enum {
186 TbtPdRetimerType =0,
187 NonTbtI2cRetimerType,
188 // Include New Retimer Device type only above this line
189 MaxRetimerDeviceType,
190 AllRetimerDeviceType = 0xFE,
191 InvalidRetimerDeviceType = 0xFF
192 } RETIMER_TYPE;
193
194 //
195 // Platform Data structure for the TBT PD Retimer Device
196 //
197 typedef struct {
198 RETIMER_TYPE RetimerType;
199 BOOLEAN RetimerDevicePresent;
200 UINT8 RetimerDeviceIndex;
201 UINT8 PdControllerIndex : 4;
202 UINT8 Reserved4Bits: 4;
203 UINT8 Reserved_Uint8; ///< Reserved for DWORD alignment
204 UINT32 Reserved_Uint32; ///< Reserved for DWORD alignment
205 UINT64 Reserved_Uint64; ///< Reserved for DWORD alignment
206 } TBT_PD_RETIMER_PLATFORM_DATA;
207
208 //
209 // Platform Data structure for the Non TBT I2C Retimer Device
210 //
211 typedef struct {
212 RETIMER_TYPE RetimerType;
213 BOOLEAN RetimerDevicePresent;
214 UINT8 RetimerDeviceIndex;
215 UINT8 PdControllerIndex : 4;
216 UINT8 I2cControllerIndex: 4;
217 BOOLEAN ForcePowerGpioLevel; ///< 0 = Active Low; 1 = Active High
218 GPIO_PAD ForcePowerGpioPad; ///< GPIO Pad Number
219 UINT16 RetimerBusConfig;
220 UINT8 RetimerHardwareConfig;
221 UINT8 RetimerDeviceUid;
222 UINT32 RetimerDeviceSlaveAddress;
223 } NON_TBT_I2C_RETIMER_PLATFORM_DATA;
224
225 //
226 // Platform Data Union structure for the Retimer Device
227 //
228 typedef union {
229 RETIMER_TYPE RetimerType;
230 TBT_PD_RETIMER_PLATFORM_DATA TbtPdRetimerData;
231 NON_TBT_I2C_RETIMER_PLATFORM_DATA NonTbtI2cRetimerData;
232 } RETIMER_PLATFORM_DATA;
233
234 #pragma pack (pop)
235
236 #endif
FW_UPDATE_MODE_EXIT
EFI_STATUS(* FW_UPDATE_MODE_EXIT)(IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)
Restore TBT PD Controller into original mode.
Definition: RetimerCapsuleUpdate.h:160
FW_UPDATE_MODE_ENTRY
EFI_STATUS(* FW_UPDATE_MODE_ENTRY)(IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid)
Drive TCSS Retimer Controller into FW Update Mode.
Definition: RetimerCapsuleUpdate.h:139
TCSS_RETIMER_PROTOCOL
struct _TCSS_RETIMER_PROTOCOL TCSS_RETIMER_PROTOCOL
Forward declaration for the _TCSS_RETIMER_PROTOCOL.
Definition: RetimerCapsuleUpdate.h:82
TCSS_RETIMER_INFO
EFI_STATUS(* TCSS_RETIMER_INFO)(IN TCSS_RETIMER_PROTOCOL *This, IN EFI_GUID RetimerGuid, OUT TCSS_RETIMER_PROTOCOL_CAPABILITY *RetimerInfo)
Get TCSS Retimer Controller info and Capability.
Definition: RetimerCapsuleUpdate.h:115
EcTcssLib.h
EC TCSS library functions.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: RstConfigPpi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
RstConfigPpi.h File Reference

This file contains RST related PPI definitions. More...

Go to the source code of this file.

Detailed Description

This file contains RST related PPI definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file RstConfigPpi.h.


AlderLake Platform Sample Code: RstConfigPpi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
RstConfigPpi.h
Go to the documentation of this file.
1 /** @file
2
3 This file contains RST related PPI definitions.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 - 2020 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36
37 #ifndef __PEI_RST_CONFIG_PPI_H__
38 #define __PEI_RST_CONFIG_PPI_H__
39
40 //
41 // This PPI is installed by AhciHc driver when AHCI controller is RAID mode.
42 // RST driver will consume this PPI to produce passthru PPI/ SSCP interface of RST version.
43 //
44 #define RST_RAID_CONTROLLER_PPI_GUID \
45 { \
46 0x62f52aed, 0xf299, 0x4167, { 0x8e, 0x94, 0xea, 0x61, 0x9f, 0x5, 0x12, 0xad } \
47 }
48
49 extern EFI_GUID gRstRaidControllerPpiGuid;
50
51 //
52 // This PPI is installed by NvmeHc driver when NVMe device is hybrid device.
53 // RST driver will consume this PPI to produce passthru PPI/ SSCP interface of RST version.
54 //
55 #define HYBRID_NVME_EXPRESS_HOST_CONTROLLER_PPI_GUID \
56 { \
57 0x5da70373, 0xd684, 0x4b95, { 0x9a, 0xae, 0x72, 0x6d, 0xa3, 0xfd, 0x47, 0xcb } \
58 }
59
60 extern EFI_GUID gPeiHybridNvmExpressHostControllerPpiGuid;
61
62 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: RstConfigSpaceAccess.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Macros | Typedefs
RstConfigSpaceAccess.h File Reference

RST config space access protocol for bios. More...

Go to the source code of this file.

Macros

#define | EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_VERSION 0x0001
Version of EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL.
#define | EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_GUID
Global ID for the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL.

Typedefs

typedef EFI_STATUS(* | EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS) (IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT EFI_PHYSICAL_ADDRESS *ConfigSpaceAddress)
Retrieves the address of PCIe Config Space of device (specified by NamespaceId value) managed by VMD controller. More...
typedef EFI_STATUS(* | EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF) (IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT UINTN *BusNumber, OUT UINTN *DeviceNumber, OUT UINTN *FunctionNumber)
Retrieves the PCI bus/device/function number of the root port before device managed by VMD controller. More...

Detailed Description

RST config space access protocol for bios.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file RstConfigSpaceAccess.h.

Typedef Documentation

◆ EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS

typedef EFI_STATUS( * EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS) (IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT EFI_PHYSICAL_ADDRESS *ConfigSpaceAddress)

Retrieves the address of PCIe Config Space of device (specified by NamespaceId value) managed by VMD controller.

Parameters
This | A pointer to the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL instance.
NamespaceId | A NamespaceId value returned by GetNextNamespaced function of NVMe Pass Thru protocol.
ConfigSpaceAddress | An address of PCIe Config Space of device managed by VMD controller.
Return values
EFI_SUCCESS | The PCIe Config Space address of the device has been retrived with success.
EFI_NOT_FOUND | The device specified by NamespaceId couldn't be found.
EFI_INVALID_PARAMETER | ConfigSpaceAdddress buffer is NULL or invalid NamespaceId requested.

Definition at line 65 of file RstConfigSpaceAccess.h.

◆ EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF

typedef EFI_STATUS( * EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF) (IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT UINTN *BusNumber, OUT UINTN *DeviceNumber, OUT UINTN *FunctionNumber)

Retrieves the PCI bus/device/function number of the root port before device managed by VMD controller.

Parameters
This | A pointer to the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL instance.
NamespaceId | A NamespaceId value returned by GetNextNamespaced function of NVMe Pass Thru protocol.
BusNumber | PCI bus number of root port
DeviceNumber | PCI device number of root port
FunctionNumber | PCI function number of root port
Return values
EFI_SUCCESS | The BusNumber, DeviceNumber and FunctionNumber of the device has been retrived with success.
EFI_NOT_FOUND | The device specified by NamespaceId couldn't be found.
EFI_INVALID_PARAMETER | BusNumber, DeviceNumber or FunctionNumber is NULL or invalid NamespaceId requested.

Definition at line 87 of file RstConfigSpaceAccess.h.


AlderLake Platform Sample Code: RstConfigSpaceAccess.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
RstConfigSpaceAccess.h
Go to the documentation of this file.
1 /**@file
2 RST config space access protocol for bios.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _RST_CONFIG_SPACE_ACCESS_H
36 #define _RST_CONFIG_SPACE_ACCESS_H
37
38 /// Version of EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL
39 #define EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_VERSION 0x0001
40
41 ///
42 /// Global ID for the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL
43 ///
44 #define EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_GUID \
45 { \
46 0x32370e89, 0x5f4a, 0x4ef0, 0xa5, 0x58, 0xce, 0x76, 0xfe, 0xff, 0x2b, 0xbe } \
47 }
48
49 typedef struct _EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL;
50
51 /**
52 Retrieves the address of PCIe Config Space of device (specified by NamespaceId value) managed by VMD controller.
53
54 @param This A pointer to the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL instance.
55 @param NamespaceId A NamespaceId value returned by GetNextNamespaced function of NVMe Pass Thru protocol.
56 @param ConfigSpaceAddress An address of PCIe Config Space of device managed by VMD controller.
57
58
59 @retval EFI_SUCCESS The PCIe Config Space address of the device has been retrived with success.
60 @retval EFI_NOT_FOUND The device specified by NamespaceId couldn't be found.
61 @retval EFI_INVALID_PARAMETER ConfigSpaceAdddress buffer is NULL or invalid NamespaceId requested.
62
63 **/
64 typedef
65 EFI_STATUS
66 (EFIAPI *EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS) (
67 IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This,
68 IN UINT32 NamespaceId,
69 OUT EFI_PHYSICAL_ADDRESS *ConfigSpaceAddress
70 );
71
72 /**
73 Retrieves the PCI bus/device/function number of the root port before device managed by VMD controller.
74
75 @param This A pointer to the EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL instance.
76 @param NamespaceId A NamespaceId value returned by GetNextNamespaced function of NVMe Pass Thru protocol.
77 @param BusNumber PCI bus number of root port
78 @param DeviceNumber PCI device number of root port
79 @param FunctionNumber PCI function number of root port
80
81 @retval EFI_SUCCESS The BusNumber, DeviceNumber and FunctionNumber of the device has been retrived with success.
82 @retval EFI_NOT_FOUND The device specified by NamespaceId couldn't be found.
83 @retval EFI_INVALID_PARAMETER BusNumber, DeviceNumber or FunctionNumber is NULL or invalid NamespaceId requested.
84
85 **/
86 typedef
87 EFI_STATUS
88 (EFIAPI *EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF)(
89 IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This,
90 IN UINT32 NamespaceId,
91 OUT UINTN *BusNumber,
92 OUT UINTN *DeviceNumber,
93 OUT UINTN *FunctionNumber
94 );
95
96
97 struct _EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL {
98 UINT8 Version;
99 EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS GetAddress;
100 EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF GetBDF;
101 };
102
103 extern EFI_GUID gRSTConfigSpaceAccessGuid;
104
105 #endif // _RST_CONFIG_SPACE_ACCESS_H
EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF
EFI_STATUS(* EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF)(IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT UINTN *BusNumber, OUT UINTN *DeviceNumber, OUT UINTN *FunctionNumber)
Retrieves the PCI bus/device/function number of the root port before device managed by VMD controller...
Definition: RstConfigSpaceAccess.h:88
EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS
EFI_STATUS(* EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS)(IN EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL *This, IN UINT32 NamespaceId, OUT EFI_PHYSICAL_ADDRESS *ConfigSpaceAddress)
Retrieves the address of PCIe Config Space of device (specified by NamespaceId value) managed by VMD ...
Definition: RstConfigSpaceAccess.h:66
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: RstFeaturesVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Classes
RstFeaturesVariable.h File Reference

RST Features variable definition. More...

Go to the source code of this file.

Classes

struct EFI_RST_FEATURE_DATA
This variable is needed for VMD to know what Rst features are enabled on platform. More...

Detailed Description

RST Features variable definition.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file RstFeaturesVariable.h.


AlderLake Platform Sample Code: RstFeaturesVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
RstFeaturesVariable.h
Go to the documentation of this file.
1 /** @file
2 RST Features variable definition
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __RST_FEATURES_VARIABLE_H_
36 #define __RST_FEATURES_VARIABLE_H_
37
38 #define EFI_RST_FEATURE_VARIABLE_REVISION_ID 1
39 #define EFI_RST_FEATURE_VARIABLE_NAME L"IntelRstFeatures"
40
41 extern EFI_GUID gRstFeaturesVariableGuid;
42
43 /**
44 This variable is needed for VMD to know what Rst features are enabled on platform.
45 Feature enable values are set up in SA SETUP
46 **/
47 typedef struct {
48 UINT32 RevisionId;
49 UINT32 Raid0 : 1;
50 UINT32 Raid1 : 1;
51 UINT32 Raid5 : 1;
52 UINT32 Raid10 : 1;
53 UINT32 Rrt : 1;
54 UINT32 RrtOnlyEsata : 1;
55 UINT32 Optane : 1;
56 UINT32 RsvdBits0 : 25;
57 } EFI_RST_FEATURE_DATA;
58
59 #endif
EFI_RST_FEATURE_DATA
This variable is needed for VMD to know what Rst features are enabled on platform.
Definition: RstFeaturesVariable.h:47
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: RstLegacyBootDisabledProtocol.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
RstLegacyBootDisabledProtocol.h File Reference

RST legacy boot disabled protocol. More...

Go to the source code of this file.

Detailed Description

RST legacy boot disabled protocol.

This protocol is used to tell RST that UEFI driver should dispatch and take control of all supported drives. The presence of the protocol is enough for RST driver dispatch. The protocol itself is empty.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file RstLegacyBootDisabledProtocol.h.


AlderLake Platform Sample Code: RstLegacyBootDisabledProtocol.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
RstLegacyBootDisabledProtocol.h
Go to the documentation of this file.
1 /** @file
2 RST legacy boot disabled protocol. This protocol is used to tell RST that
3 UEFI driver should dispatch and take control of all supported drives.
4 The presence of the protocol is enough for RST driver dispatch. The protocol
5 itself is empty.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2018 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37
38 #ifndef _RST_LEGACY_BOOT_DISABLED_PROTOCOL_H_
39 #define _RST_LEGACY_BOOT_DISABLED_PROTOCOL_H_
40
41 extern EFI_GUID gRstLegacyBootDisabledProtocolGuid;
42
43 #endif
44
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: S3MemoryVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
S3MemoryVariable.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file S3MemoryVariable.h.


AlderLake Platform Sample Code: S3MemoryVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
S3MemoryVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains 'Framework Code' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may not be
29 modified, except as allowed by additional terms of your license agreement.
30
31 @par Specification Reference:
32
33 **/
34
35
36 #ifndef _S3_MEMORY_VARIABLE_H_
37 #define _S3_MEMORY_VARIABLE_H_
38 #define S3_MEMORY_VARIABLE_NAME L"S3MemoryVariable"
39
40 typedef struct {
41 EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
42 UINT32 AcpiReservedMemorySize;
43 UINT64 SystemMemoryLength;
44 } S3_MEMORY_VARIABLE;
45
46 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SaPlatformInitAdvancedDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
Functions
SaPlatformInitAdvancedDxe.c File Reference

Source code file for the SA Platform Init DXE module. More...

#include "PlatformInitAdvancedDxe.h"
#include <Protocol/BlockIo.h>
#include <Protocol/GopPolicy.h>
#include <Protocol/SaPolicy.h>
#include <Library/DebugLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/PciEnumerationComplete.h>
#include <PlatformNvRamHookLib.h>
#include <ITbtInfoHob.h>
#include <SaDataHob.h>
#include <Library/GraphicsInfoLib.h>
#include <HostBridgeDataLib.h>
#include <Library/CmosAccessLib.h>
#include <CmosMap.h>
#include <TcssDataHob.h>
Include dependency graph for SaPlatformInitAdvancedDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | RegisterDisplayDimmPopulationErrMsg (VOID)
Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation. More...
VOID | DisplayDimmPopulationErrMsg (IN EFI_EVENT Event, IN VOID *Context)
Display DIMM population error message, while Wrong DIMM Population is found. More...
VOID | UpdateGmAdrRegionToWriteCombine (VOID)
This function will update the GT Aperture Region to Write Combining. More...
VOID | PciEnumCompleteCallback (IN EFI_EVENT Event, IN VOID *Context)
This function gets registered as a callback to perform SA functions after PCI enumeration completes. More...
VOID | UpdateItbtDmaUuidVariable (VOID)
Update Setup variable for keep DMA UUID. More...
VOID | SyncItbtVariables (VOID)
Sync ITBT Variables.
VOID | UpdateDimmPopulation (VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
VOID | SaPlatformInitDxe (VOID)
System Agent platform Initialization.

Detailed Description

Source code file for the SA Platform Init DXE module.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPlatformInitAdvancedDxe.c.

Function Documentation

◆ DisplayDimmPopulationErrMsg()

VOID DisplayDimmPopulationErrMsg | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Display DIMM population error message, while Wrong DIMM Population is found.

Parameters
[in] | Event | A pointer to the Event that triggered the callback
[in] | Context | A pointer to private data registered with the callback function.
Return values
EFI_SUCCESS If Successfully exectuted else returns the error status

Definition at line 297 of file SaPlatformInitAdvancedDxe.c.

◆ PciEnumCompleteCallback()

VOID PciEnumCompleteCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

This function gets registered as a callback to perform SA functions after PCI enumeration completes.

Parameters
[in] | Event | - A pointer to the Event that triggered the callback.
[in] | Context | - A pointer to private data registered with the callback function.

Check if this is first time called by EfiCreateProtocolNotifyEvent() or not, if it is, we will skip it until real event is triggered

If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.

Definition at line 399 of file SaPlatformInitAdvancedDxe.c.

◆ RegisterDisplayDimmPopulationErrMsg()

EFI_STATUS RegisterDisplayDimmPopulationErrMsg ( VOID )

Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.

Parameters
[in] SystemTable Pointer to the System Table
Return values
EFI_SUCCESS return EFI_STATUS as success

Definition at line 259 of file SaPlatformInitAdvancedDxe.c.

Here is the call graph for this function:

◆ UpdateGmAdrRegionToWriteCombine()

VOID UpdateGmAdrRegionToWriteCombine ( VOID )

This function will update the GT Aperture Region to Write Combining.

Create PCI Enumeration Completed callback

Definition at line 371 of file SaPlatformInitAdvancedDxe.c.

Here is the call graph for this function:

◆ UpdateItbtDmaUuidVariable()

VOID UpdateItbtDmaUuidVariable ( VOID )

Update Setup variable for keep DMA UUID.

Get ITBT DMA UUID value from HOB of gTcssHobGuid

Set ITBT DMA UUID to Setup Data variable with updated values

Definition at line 84 of file SaPlatformInitAdvancedDxe.c.


AlderLake Platform Sample Code: SaPlatformInitAdvancedDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
SaPlatformInitAdvancedDxe.c
Go to the documentation of this file.
1 /** @file
2 Source code file for the SA Platform Init DXE module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "PlatformInitAdvancedDxe.h"
35 #include <Protocol/BlockIo.h>
36 #include <Protocol/GopPolicy.h>
37 #include <Protocol/SaPolicy.h>
38 #include <Library/DebugLib.h>
39 #include <Protocol/Cpu.h>
40 #include <Protocol/PciEnumerationComplete.h>
41 #include <PlatformNvRamHookLib.h>
42 #include <ITbtInfoHob.h>
43 #include <SaDataHob.h>
44 #include <Library/GraphicsInfoLib.h>
45 #include <HostBridgeDataLib.h>
46 #include <Library/CmosAccessLib.h>
47 #include <CmosMap.h>
48 #include <TcssDataHob.h>
49
50 GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mAddress;
51 GLOBAL_REMOVE_IF_UNREFERENCED UINTN mSize;
52
53 #define EFI_MAX_ADDRESS 0xFFFFFFFF
54
55 EFI_STATUS
56 EFIAPI
57 RegisterDisplayDimmPopulationErrMsg (
58 VOID
59 );
60
61 VOID
62 EFIAPI
63 DisplayDimmPopulationErrMsg (
64 IN EFI_EVENT Event,
65 IN VOID *Context
66 );
67
68 VOID
69 UpdateGmAdrRegionToWriteCombine (
70 VOID
71 );
72
73 VOID
74 EFIAPI
75 PciEnumCompleteCallback (
76 IN EFI_EVENT Event,
77 IN VOID *Context
78 );
79
80 /**
81 Update Setup variable for keep DMA UUID
82 **/
83 VOID
84 UpdateItbtDmaUuidVariable (
85 VOID
86 )
87 {
88 UINTN VarSize;
89 UINT32 VariableAttr;
90 ITBT_INFO_HOB *ITbtInfoHobPtr;
91 SETUP_DATA SystemConfiguration;
92 EFI_STATUS Status;
93
94 DEBUG ((DEBUG_INFO, "UpdateItbtDmaUuidVariable - Start\n"));
95 //
96 // Get Setup Data for update ITBT DMA UUID
97 //
98 VarSize = sizeof (SETUP_DATA);
99 Status = gRT->GetVariable (
100 PLATFORM_SETUP_VARIABLE_NAME,
101 &gSetupVariableGuid,
102 &VariableAttr,
103 &VarSize,
104 &SystemConfiguration
105 );
106 ASSERT_EFI_ERROR (Status);
107
108 if (EFI_ERROR(Status)){
109 DEBUG ((DEBUG_ERROR, "Platform Setup data was not found.\n"));
110 return;
111 }
112
113 ///
114 /// Get ITBT DMA UUID value from HOB of gTcssHobGuid
115 ///
116 ITbtInfoHobPtr = (ITBT_INFO_HOB *) GetFirstGuidHob (&gITbtInfoHobGuid);
117
118 if (ITbtInfoHobPtr == NULL) {
119 DEBUG ((DEBUG_ERROR, "TcssHobPtr is NULL.\n"));
120 return;
121 }
122
123 ///
124 /// Set ITBT DMA UUID to Setup Data variable with updated values
125 ///
126 Status = gRT->SetVariable (
127 PLATFORM_SETUP_VARIABLE_NAME,
128 &gSetupVariableGuid,
129 VariableAttr,
130 VarSize,
131 &SystemConfiguration
132 );
133 ASSERT_EFI_ERROR (Status);
134 DEBUG ((DEBUG_INFO, "UpdateItbtDmaUuidVariable - End\n"));
135 }
136
137 /**
138 Sync ITBT Variables
139 **/
140 VOID
141 SyncItbtVariables (
142 VOID
143 )
144 {
145 SA_SETUP SaSetup;
146 UINTN SaSetupVariableSize;
147 UINT32 SaVariableAttributes;
148 EFI_STATUS Status;
149 SETUP_DATA SetupData;
150 UINTN SetupDataVariableSize;
151 UINT32 SetupDataVariableAttributes;
152 UINT8 CmosUsb4CmModeValue;
153 UINT8 EnableSyncSetupData;
154 UINT8 TempITbtRtd3;
155
156 DEBUG ((DEBUG_INFO, "SyncItbtVariables Entry\n"));
157
158 EnableSyncSetupData = 0;
159
160 SetupDataVariableAttributes = 0;
161 SetupDataVariableSize = sizeof (SETUP_DATA);
162 Status = gRT->GetVariable (
163 PLATFORM_SETUP_VARIABLE_NAME,
164 &gSetupVariableGuid,
165 &SetupDataVariableAttributes,
166 &SetupDataVariableSize,
167 &SetupData);
168 if (EFI_ERROR (Status)) {
169 DEBUG ((DEBUG_ERROR, "Get Setup variable fail.\n"));
170 return;
171 }
172
173 SaVariableAttributes = 0;
174 SaSetupVariableSize = sizeof (SA_SETUP);
175 Status = gRT->GetVariable (
176 L"SaSetup",
177 &gSaSetupVariableGuid,
178 &SaVariableAttributes,
179 &SaSetupVariableSize,
180 &SaSetup
181 );
182 if (EFI_ERROR (Status)) {
183 DEBUG ((DEBUG_ERROR, "Get SaSetup variable fail.\n"));
184 return;
185 }
186
187 CmosUsb4CmModeValue = CmosRead8 (CMOS_USB4_CM_MODE_REG);
188 if ((SetupData.Usb4CmMode == SETUP_OPTION_USB4_CM_MODE_FW) ||
189 ((SetupData.Usb4CmMode == SETUP_OPTION_USB4_CM_MODE_OS) && (CmosUsb4CmModeValue == USB4_CM_MODE_FW_CM))) {
190 TempITbtRtd3 = SetupData.ITbtRtd3;
191 } else {
192 TempITbtRtd3 = 1;
193 }
194
195 if (SetupData.ITbtRtd3 != TempITbtRtd3) {
196 DEBUG ((DEBUG_INFO, "Sync ITbtRtd3 Variables\n"));
197 SetupData.ITbtRtd3 = TempITbtRtd3;
198 EnableSyncSetupData = 1;
199 }
200
201 if (EnableSyncSetupData == 1) {
202 Status = gRT->SetVariable (
203 PLATFORM_SETUP_VARIABLE_NAME,
204 &gSetupVariableGuid,
205 SetupDataVariableAttributes,
206 SetupDataVariableSize,
207 &SetupData);
208 if (EFI_ERROR (Status)) {
209 DEBUG ((DEBUG_ERROR, "Save SetupData variables fail.\n"));
210 }
211 }
212
213 //
214 // Wake Capability is S3
215 //
216 if (SetupData.DeepestUSBSleepWakeCapability == 3) {
217 if (SaSetup.TcssVccstStatus != 0) {
218 DEBUG ((DEBUG_INFO, "Sync TcssIomVccSt Variables\n"));
219 SaSetup.TcssVccstStatus = 0;
220 Status = gRT->SetVariable (
221 L"SaSetup",
222 &gSaSetupVariableGuid,
223 SaVariableAttributes,
224 SaSetupVariableSize,
225 &SaSetup
226 );
227 if (EFI_ERROR (Status)) {
228 DEBUG ((DEBUG_ERROR, "Save SaSetup variables fail.\n"));
229 }
230 }
231 }
232
233 DEBUG ((DEBUG_INFO, "SyncItbtVariables Exit\n"));
234 }
235
236 /**
237 Updates DIMM slots status for Desktop,server and workstation boards
238
239 **/
240 VOID
241 UpdateDimmPopulation(
242 VOID
243 )
244 {
245 if (PcdGetBool (PcdDimmPopulationError)) {
246 RegisterDisplayDimmPopulationErrMsg ();
247 }
248 }
249
250 /**
251 Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.
252
253 @param[in] SystemTable Pointer to the System Table
254
255 @retval EFI_SUCCESS return EFI_STATUS as success
256 **/
257 EFI_STATUS
258 EFIAPI
259 RegisterDisplayDimmPopulationErrMsg (
260 VOID
261 )
262 {
263 EFI_EVENT DimmPopultionErrMsgEvent;
264 VOID *Registration;
265
266 DimmPopultionErrMsgEvent = NULL;
267
268 //
269 // Create event for SimpleInProtocol Callback notification
270 //
271 gBS->CreateEvent (
272 EVT_NOTIFY_SIGNAL,
273 TPL_CALLBACK,
274 DisplayDimmPopulationErrMsg,
275 NULL,
276 &DimmPopultionErrMsgEvent
277 );
278 gBS->RegisterProtocolNotify (
279 &gBdsAllDriversConnectedProtocolGuid,
280 DimmPopultionErrMsgEvent,
281 &Registration
282 );
283
284 return EFI_SUCCESS;
285 }
286
287 /**
288 Display DIMM population error message, while Wrong DIMM Population is found.
289
290 @param[in] Event A pointer to the Event that triggered the callback
291 @param[in] Context A pointer to private data registered with the callback function.
292
293 @retval EFI_SUCCESS If Successfully exectuted else returns the error status
294 **/
295 VOID
296 EFIAPI
297 DisplayDimmPopulationErrMsg (
298 IN EFI_EVENT Event,
299 IN VOID *Context
300 )
301 {
302 EFI_STATUS Status;
303 EFI_INPUT_KEY Key;
304
305 DEBUG ((DEBUG_ERROR, "\n DIMMPopulation Error msg\n"));
306
307 if (gST->ConOut != NULL && gST->ConIn != NULL) {
308 if (Event != NULL) {
309 gBS->CloseEvent (Event);
310 }
311 //
312 // Display the Error Message
313 //
314 gST->ConOut->OutputString (gST->ConOut, L"");
315
316 gST->ConOut->OutputString (gST->ConOut, L"Error...! Invalid DIMM Population.");
317
318 gST->ConOut->OutputString (gST->ConOut, L"Slot 0 can't be populated when Slot 1 is not populated on the same channel");
319
320 gST->ConOut->OutputString (gST->ConOut, L"Press <Y> to Continue. <N> to Shutdown");
321
322 //
323 // Wait for User Input
324 //
325 do {
326 Status = gBS->CheckEvent (gST->ConIn->WaitForKey);
327 if (!EFI_ERROR (Status)) {
328 Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);
329 if (Key.UnicodeChar == L'Y' || Key.UnicodeChar == L'y') {
330 DEBUG ((DEBUG_INFO, " Boot Continue\n"));
331 break;
332 } else if (Key.UnicodeChar == L'N' || Key.UnicodeChar == L'n') {
333 DEBUG ((DEBUG_ERROR, " System shutdown\n"));
334 gRT->ResetSystem (EfiResetShutdown, EFI_SUCCESS, 0, NULL);
335 }
336 }
337 } while (1);
338 }
339 }
340
341
342 /**
343 System Agent platform Initialization
344
345 **/
346 VOID
347 SaPlatformInitDxe (
348 VOID
349 )
350 {
351
352 //
353 // Update GT Aperture region memory type as Write Combine.
354 //
355 UpdateGmAdrRegionToWriteCombine();
356
357 #if FixedPcdGetBool (PcdITbtEnable) == 1
358 //
359 // Save Itbt Dma UUID Data
360 //
361 UpdateItbtDmaUuidVariable ();
362 SyncItbtVariables ();
363 #endif
364 }
365
366 /**
367 This function will update the GT Aperture Region to Write Combining.
368
369 **/
370 VOID
371 UpdateGmAdrRegionToWriteCombine (
372 VOID
373 )
374 {
375 VOID *Registration;
376
377 DEBUG ((DEBUG_INFO, "Call backs to update GmAdr region as write combine\n"));
378
379 ///
380 /// Create PCI Enumeration Completed callback
381 ///
382 EfiCreateProtocolNotifyEvent (
383 &gEfiPciEnumerationCompleteProtocolGuid,
384 TPL_NOTIFY,
385 PciEnumCompleteCallback,
386 NULL,
387 &Registration
388 );
389 }
390
391 /**
392 This function gets registered as a callback to perform SA functions after PCI enumeration completes.
393
394 @param[in] Event - A pointer to the Event that triggered the callback.
395 @param[in] Context - A pointer to private data registered with the callback function.
396 **/
397 VOID
398 EFIAPI
399 PciEnumCompleteCallback (
400 IN EFI_EVENT Event,
401 IN VOID *Context
402 )
403 {
404 EFI_STATUS Status;
405 VOID *ProtocolPointer;
406 UINT32 Msac;
407 UINT64 McD2BaseAddress;
408 UINT64 GtApertureSize;
409 UINT64 GtApertureAdr;
410 EFI_CPU_ARCH_PROTOCOL *CpuArch;
411
412 DEBUG ((DEBUG_INFO, "SA Platform PciEnumCompleteCallback Start\n"));
413
414 Msac = 0;
415 GtApertureAdr = 0;
416 GtApertureSize = 0;
417
418 ///
419 /// Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
420 /// if it is, we will skip it until real event is triggered
421 ///
422 Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) &ProtocolPointer);
423 if (EFI_SUCCESS != Status) {
424 return;
425 }
426
427 gBS->CloseEvent (Event);
428
429 McD2BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, GetIgdBusNumber(), GetIgdDevNumber(), GetIgdFuncNumber(), 0);
430 ///
431 /// If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.
432 ///
433 if ((PciSegmentRead16 (McD2BaseAddress + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) {
434 Msac = PciSegmentRead32 (McD2BaseAddress + GetIgdMsacOffset());
435 GtApertureSize = ((((Msac & (BIT20 | BIT19 | BIT18 | BIT17 | BIT16))) >> 16) + 1) * SIZE_128MB;
436
437 PciSegmentReadBuffer (McD2BaseAddress + GetGmAdrOffset(), sizeof (UINT64), &GtApertureAdr);
438 GtApertureAdr &= 0xFFFFFFFFFFFFFFF0;
439
440 Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **) &CpuArch);
441 ASSERT_EFI_ERROR (Status);
442
443 //
444 // Check Enable Above 4GB MMIO or not
445 //
446 if (IsAbove4GBMmioEnabled ()) {
447 //
448 // WORKAROUND for MTRR above 4G issue
449 //
450 GtApertureSize = SIZE_128GB;
451 }
452
453 Status = CpuArch->SetMemoryAttributes (
454 CpuArch,
455 GtApertureAdr,
456 GtApertureSize,
457 EFI_MEMORY_WC
458 );
459 if (EFI_SUCCESS != Status) {
460 DEBUG((DEBUG_INFO, "Setting GmAdr Memory as WriteCombine failed! Cache the Flash area as UC to release MTRR. \n"));
461 Status = CpuArch->SetMemoryAttributes (
462 CpuArch,
463 0xff000000,
464 0x01000000,
465 EFI_MEMORY_UC
466 );
467 DEBUG((DEBUG_INFO, "Setting Flash Memory as UnCacheable %r\n", Status));
468 ASSERT_EFI_ERROR (Status);
469 Status = CpuArch->SetMemoryAttributes (
470 CpuArch,
471 GtApertureAdr,
472 GtApertureSize,
473 EFI_MEMORY_WC
474 );
475 DEBUG((DEBUG_INFO, "Setting GmAdr Memory as WriteCombine %r\n", Status));
476 ASSERT_EFI_ERROR (Status);
477 }
478 }
479
480 DEBUG ((DEBUG_INFO, "SA Platform PciEnumCompleteCallback End\n"));
481
482 return;
483 }
PlatformInitAdvancedDxe.h
Header file for Platform Init Advanced Dxe Driver.
SyncItbtVariables
VOID SyncItbtVariables(VOID)
Sync ITBT Variables.
Definition: SaPlatformInitAdvancedDxe.c:141
UpdateItbtDmaUuidVariable
VOID UpdateItbtDmaUuidVariable(VOID)
Update Setup variable for keep DMA UUID.
Definition: SaPlatformInitAdvancedDxe.c:84
UpdateGmAdrRegionToWriteCombine
VOID UpdateGmAdrRegionToWriteCombine(VOID)
This function will update the GT Aperture Region to Write Combining.
Definition: SaPlatformInitAdvancedDxe.c:371
DisplayDimmPopulationErrMsg
VOID DisplayDimmPopulationErrMsg(IN EFI_EVENT Event, IN VOID *Context)
Display DIMM population error message, while Wrong DIMM Population is found.
Definition: SaPlatformInitAdvancedDxe.c:297
PlatformNvRamHookLib.h
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NV...
PciEnumCompleteCallback
VOID PciEnumCompleteCallback(IN EFI_EVENT Event, IN VOID *Context)
This function gets registered as a callback to perform SA functions after PCI enumeration completes.
Definition: SaPlatformInitAdvancedDxe.c:399
UpdateDimmPopulation
VOID UpdateDimmPopulation(VOID)
Updates DIMM slots status for Desktop,server and workstation boards.
Definition: SaPlatformInitAdvancedDxe.c:241
RegisterDisplayDimmPopulationErrMsg
EFI_STATUS RegisterDisplayDimmPopulationErrMsg(VOID)
Register DisplayDIMMPopulationErrMsg Notification function on SimpleIn protocol Installation.
Definition: SaPlatformInitAdvancedDxe.c:259
SaPlatformInitDxe
VOID SaPlatformInitDxe(VOID)
System Agent platform Initialization.
Definition: SaPlatformInitAdvancedDxe.c:347
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SaPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
SaPolicyInitDxe.c File Reference

This file is SampleCode for SA DXE Policy initialization. More...

#include "SaPolicyInitDxe.h"
#include <Library/GraphicsInfoLib.h>
Include dependency graph for SaPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS | SaPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy. More...
EFI_STATUS | GetGopVbtData (VOID)
Function to register call back event to get GOP VBT data. More...
VOID | UpdateSaPolicyGopVbtPointer (IN EFI_EVENT Event, IN VOID *Context)
Callback function to Update SaPolicyGopVbtPointer and Size. More...

Detailed Description

This file is SampleCode for SA DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPolicyInitDxe.c.

Function Documentation

◆ GetGopVbtData()

EFI_STATUS GetGopVbtData ( VOID )

Function to register call back event to get GOP VBT data.

Return values
EFI_SUCCESS | Call back registered successfully.
EFI_UNSUPPORTED | Call back registration fails.

If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.

Definition at line 96 of file SaPolicyInitDxe.c.

Here is the call graph for this function:

◆ SaPolicyInitDxe()

EFI_STATUS SaPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize SA DXE Policy.

SA DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 54 of file SaPolicyInitDxe.c.

Here is the call graph for this function:

◆ UpdateSaPolicyGopVbtPointer()

VOID UpdateSaPolicyGopVbtPointer | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Callback function to Update SaPolicyGopVbtPointer and Size.

Parameters
[in] | Event | - The triggered event.
[in] | Context | - Context for this event.

Locate the GOP Policy Protocol.

Get VBT data

Definition at line 147 of file SaPolicyInitDxe.c.


AlderLake Platform Sample Code: SaPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
SaPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for SA DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "SaPolicyInitDxe.h"
35 #include <Library/GraphicsInfoLib.h>
36
37
38 //
39 // Function implementations
40 //
41
42 /**
43 Initialize SA DXE Policy
44
45 @param[in] ImageHandle Image handle of this driver.
46
47 @retval EFI_SUCCESS Initialization complete.
48 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
49 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
50 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
51 **/
52 EFI_STATUS
53 EFIAPI
54 SaPolicyInitDxe (
55 IN EFI_HANDLE ImageHandle
56 )
57 {
58 EFI_STATUS Status;
59 SA_POLICY_PROTOCOL *SaPolicy;
60
61 //
62 // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
63 // and get all Intel default policy settings.
64 //
65 Status = CreateSaDxeConfigBlocks (&SaPolicy);
66 DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
67 ASSERT_EFI_ERROR (Status);
68
69 UpdateDxeSaPolicyBoardConfig (SaPolicy);
70
71 if (mFirmwareConfiguration != FwConfigDefault) {
72
73 UpdateDxeSaPolicy (SaPolicy);
74 GetGopVbtData();
75 }
76
77 //
78 // Install SaInstallPolicyProtocol.
79 // While installed, RC assumes the Policy is ready and finalized. So please
80 // update and override any setting before calling this function.
81 //
82 Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
83 ASSERT_EFI_ERROR (Status);
84
85 return Status;
86 }
87
88 /**
89 Function to register call back event to get GOP VBT data.
90
91 @retval EFI_SUCCESS Call back registered successfully.
92 @retval EFI_UNSUPPORTED: Call back registration fails.
93
94 **/
95 EFI_STATUS
96 GetGopVbtData (
97 VOID
98 )
99 {
100 EFI_STATUS Status;
101 VOID *Registration;
102 EFI_EVENT Event;
103 GOP_POLICY_PROTOCOL *GopPolicy;
104 UINT64 McD2BaseAddress;
105
106 McD2BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, GetIgdBusNumber(), GetIgdDevNumber(), GetIgdFuncNumber(), 0);
107 ///
108 /// If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.
109 ///
110 if ((PciSegmentRead16 (McD2BaseAddress + PCI_VENDOR_ID_OFFSET) == 0xFFFF)) {
111 DEBUG((DEBUG_INFO, "IGD is not present, skip GetGopVbtData ()\n"));
112 return EFI_SUCCESS;
113 }
114
115 Status = gBS->LocateProtocol (&gGopPolicyProtocolGuid, NULL, (VOID **) &GopPolicy);
116 if (Status == EFI_NOT_FOUND) {
117 Status = gBS->CreateEvent (
118 EVT_NOTIFY_SIGNAL,
119 TPL_CALLBACK,
120 (EFI_EVENT_NOTIFY) UpdateSaPolicyGopVbtPointer,
121 NULL,
122 &Event
123 );
124 ASSERT_EFI_ERROR (Status);
125 Status = gBS->RegisterProtocolNotify (
126 &gGopPolicyProtocolGuid,
127 Event,
128 &Registration
129 );
130 ASSERT_EFI_ERROR (Status);
131 } else {
132 UpdateSaPolicyGopVbtPointer (NULL, NULL);
133 }
134
135 return EFI_SUCCESS;
136 }
137
138
139 /**
140 Callback function to Update SaPolicyGopVbtPointer and Size.
141
142 @param[in] Event - The triggered event.
143 @param[in] Context - Context for this event.
144
145 **/
146 VOID
147 UpdateSaPolicyGopVbtPointer (
148 IN EFI_EVENT Event,
149 IN VOID *Context
150 )
151 {
152 EFI_STATUS Status;
153 SA_POLICY_PROTOCOL *SaPolicy;
154 GOP_POLICY_PROTOCOL *GopPolicy;
155 EFI_PHYSICAL_ADDRESS VbtAddress;
156 UINT32 Size;
157 GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
158
159 Status = gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) &SaPolicy);
160 if (EFI_ERROR (Status)) {
161 return;
162 }
163
164 Status = GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
165 ASSERT_EFI_ERROR (Status);
166
167 DEBUG ((DEBUG_INFO, "Locate GopPolicy and GetVbtData\n"));
168 ///
169 /// Locate the GOP Policy Protocol.
170 ///
171 GopPolicy = NULL;
172 Status = gBS->LocateProtocol (&gGopPolicyProtocolGuid, NULL, (VOID **) &GopPolicy);
173 ASSERT (GopPolicy != NULL);
174 if (EFI_ERROR (Status) || (GopPolicy == NULL)) {
175 return;
176 }
177
178 ///
179 /// Get VBT data
180 ///
181 VbtAddress = 0;
182 Size = 0;
183 DEBUG ((DEBUG_INFO, "GetVbtData\n"));
184 Status = GopPolicy->GetVbtData (&VbtAddress, &Size);
185 ASSERT_EFI_ERROR(Status);
186
187 GraphicsDxeConfig->VbtAddress = VbtAddress;
188 GraphicsDxeConfig->Size = Size;
189
190 return;
191 }
SaPolicyInitDxe.h
Header file for the SaPolicyInitDxe Driver.
UpdateSaPolicyGopVbtPointer
VOID UpdateSaPolicyGopVbtPointer(IN EFI_EVENT Event, IN VOID *Context)
Callback function to Update SaPolicyGopVbtPointer and Size.
Definition: SaPolicyInitDxe.c:147
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize SA DXE Policy.
Definition: SaPolicyInitDxe.c:54
GetGopVbtData
EFI_STATUS GetGopVbtData(VOID)
Function to register call back event to get GOP VBT data.
Definition: SaPolicyInitDxe.c:96
UpdateDxeSaPolicy
EFI_STATUS UpdateDxeSaPolicy(IN OUT SA_POLICY_PROTOCOL *SaPolicy)
Get data for platform policy from setup options.
UpdateDxeSaPolicyBoardConfig
EFI_STATUS UpdateDxeSaPolicyBoardConfig(IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy)
This function performs DXE SA Policy update by board configuration.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SaPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
SaPolicyInitDxe.h File Reference

Header file for the SaPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/SaPolicy.h>
#include <Protocol/GopPolicy.h>
#include <Library/DxeSaPolicyLib.h>
#include <Library/DxePolicyBoardConfigLib.h>
#include <Library/DxeSaPolicyUpdateLib.h>
Include dependency graph for SaPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | SaPolicyInitDxe (IN EFI_HANDLE ImageHandle)
SA DXE Policy Driver Entry Point
More...
EFI_STATUS | GetGopVbtData (VOID)
Function to register call back event to get GOP VBT data. More...
VOID | UpdateSaPolicyGopVbtPointer (IN EFI_EVENT Event, IN VOID *Context)
Callback function to Update SaPolicyGopVbtPointer and Size. More...

Detailed Description

Header file for the SaPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SaPolicyInitDxe.h.

Function Documentation

◆ GetGopVbtData()

EFI_STATUS GetGopVbtData ( VOID )

Function to register call back event to get GOP VBT data.

Return values
EFI_SUCCESS | Call back registered successfully.
EFI_UNSUPPORTED | Call back registration fails.

If device 0:2:0 (Internal Graphics Device, or GT) is not present, skip it.

Definition at line 96 of file SaPolicyInitDxe.c.

Here is the call graph for this function:

◆ SaPolicyInitDxe()

EFI_STATUS SaPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

SA DXE Policy Driver Entry Point

  • Introduction
    System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

SA DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 54 of file SaPolicyInitDxe.c.

Here is the call graph for this function:

◆ UpdateSaPolicyGopVbtPointer()

VOID UpdateSaPolicyGopVbtPointer | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Callback function to Update SaPolicyGopVbtPointer and Size.

Parameters
[in] | Event | - The triggered event.
[in] | Context | - Context for this event.

Locate the GOP Policy Protocol.

Get VBT data

Definition at line 147 of file SaPolicyInitDxe.c.


AlderLake Platform Sample Code: SaPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
SaPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SaPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _SA_POLICY_INIT_DXE_H_
35 #define _SA_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/SaPolicy.h>
43 #include <Protocol/GopPolicy.h>
44 #include <Library/DxeSaPolicyLib.h>
45 #include <Library/DxePolicyBoardConfigLib.h>
46 #include <Library/DxeSaPolicyUpdateLib.h>
47
48
49 extern UINT8 mFirmwareConfiguration;
50
51 /**
52 <b>SA DXE Policy Driver Entry Point</b> \n
53 - <b>Introduction</b> \n
54 System Agent DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
55 Platform policy Protocol is initialized with default settings in this funciton.
56 This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
57
58 - @pre
59 - Runtime variable service should be ready if policy initialization required.
60
61 - @result
62 SA_POLICY_PROTOCOL will be installed successfully and ready for System Agent reference code use.
63
64 - <b>Porting Recommendations</b> \n
65 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
66
67 @param[in] ImageHandle - Image handle of this driver.
68
69 @retval EFI_SUCCESS Initialization complete.
70 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
71 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
72 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
73 **/
74 EFI_STATUS
75 EFIAPI
76 SaPolicyInitDxe (
77 IN EFI_HANDLE ImageHandle
78 );
79
80 /**
81 Function to register call back event to get GOP VBT data.
82
83 @retval EFI_SUCCESS Call back registered successfully.
84 @retval EFI_UNSUPPORTED: Call back registration fails.
85
86 **/
87 EFI_STATUS
88 GetGopVbtData (
89 VOID
90 );
91
92 /**
93 Callback function to Update SaPolicyGopVbtPointer and Size.
94
95 @param[in] Event - The triggered event.
96 @param[in] Context - Context for this event.
97
98 **/
99 VOID
100 UpdateSaPolicyGopVbtPointer (
101 IN EFI_EVENT Event,
102 IN VOID *Context
103 );
104
105 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxeSaPolicyUpdateLib.h
UpdateSaPolicyGopVbtPointer
VOID UpdateSaPolicyGopVbtPointer(IN EFI_EVENT Event, IN VOID *Context)
Callback function to Update SaPolicyGopVbtPointer and Size.
Definition: SaPolicyInitDxe.c:147
GetGopVbtData
EFI_STATUS GetGopVbtData(VOID)
Function to register call back event to get GOP VBT data.
Definition: SaPolicyInitDxe.c:96
SaPolicyInitDxe
EFI_STATUS SaPolicyInitDxe(IN EFI_HANDLE ImageHandle)
SA DXE Policy Driver Entry Point
Definition: SaPolicyInitDxe.c:54
DxePolicyBoardConfigLib.h
Header file for the DxePolicyBoardConfig Library.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SecureBootSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
SecureBootSetup.h File Reference

Go to the source code of this file.

Macros

#define SECURE_BOOT_VARIABLE_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SecureBootSetup.h.


AlderLake Platform Sample Code: SecureBootSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SecureBootSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SECURE_BOOT_SETUP_H_
35 #define _SECURE_BOOT_SETUP_H_
36
37 #pragma pack(1)
38
39 #define SECURE_BOOT_VARIABLE_KEY 4363
40
41 #define SECURE_BOOT_SETUP_VARSTORE\
42 varstore SECURE_BOOT_VARIABLE, \
43 varid = SECURE_BOOT_VARIABLE_KEY, \
44 name = SecureBoot, \
45 guid = EFI_GLOBAL_VARIABLE;
46
47
48 /**
49 Making any setup structure change after code frozen
50 will need to maintain backward compatibility, bump up
51 structure revision and update below history table\n
52 <b>Revision 1</b>: - Initial version.
53 **/
54 #define SECURE_BOOT_VARIABLE_REVISION 1
55
56 typedef struct{
57 UINT8 SecureBoot;
58 } SECURE_BOOT_VARIABLE;
59
60 #pragma pack()
61 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SecurePreMemoryDataLoadLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
SecurePreMemoryDataLoadLib.h File Reference

PEI Secure Pre-Memory Data Load Library. More...

#include <SecurePreMemoryData.h>
Include dependency graph for SecurePreMemoryDataLoadLib.h:

Go to the source code of this file.

Functions

EFI_STATUS LoadSecurePreMemoryData (VOID)
Loads the Secure Pre-Memory Data (SPMD) from the CSE Shared SRAM on a block media boot. More...

Detailed Description

PEI Secure Pre-Memory Data Load Library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SecurePreMemoryDataLoadLib.h.

Function Documentation

◆ LoadSecurePreMemoryData()

EFI_STATUS LoadSecurePreMemoryData ( VOID )

Loads the Secure Pre-Memory Data (SPMD) from the CSE Shared SRAM on a block media boot.

This data will contain a UEFI variable store that serves read requests in PEI on a block media boot.

Parameters
None
Return values
EFI_SUCCESS | The secure pre-memory data was loaded successfully.
EFI_NOT_FOUND | The secure pre-memory data was not found.


AlderLake Platform Sample Code: SecurePreMemoryDataLoadLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
SecurePreMemoryDataLoadLib.h
Go to the documentation of this file.
1 /** @file
2 PEI Secure Pre-Memory Data Load Library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SECURE_PRE_MEMORY_DATA_LOAD_LIB_H_
36 #define _SECURE_PRE_MEMORY_DATA_LOAD_LIB_H_
37
38 #include <SecurePreMemoryData.h>
39
40 /**
41 Loads the Secure Pre-Memory Data (SPMD) from the CSE Shared SRAM on a block media boot. This data will contain
42 a UEFI variable store that serves read requests in PEI on a block media boot.
43
44 @param None
45
46 @retval EFI_SUCCESS The secure pre-memory data was loaded successfully.
47 @retval EFI_NOT_FOUND The secure pre-memory data was not found.
48 */
49 EFI_STATUS
50 EFIAPI
51 LoadSecurePreMemoryData (
52 VOID
53 );
54
55 #endif
LoadSecurePreMemoryData
EFI_STATUS LoadSecurePreMemoryData(VOID)
Loads the Secure Pre-Memory Data (SPMD) from the CSE Shared SRAM on a block media boot.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SerialIoUartDebugHelperLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
SerialIoUartDebugHelperLib.h File Reference

Go to the source code of this file.

Functions

VOID | SerialIoUartDebugInit (VOID)
Initialize SerialIo UART for debug.
UINTN | SerialIoUartDebugWrite (IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data to serial device. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file SerialIoUartDebugHelperLib.h.

Function Documentation

◆ SerialIoUartDebugWrite()

UINTN SerialIoUartDebugWrite | ( | IN UINT8 * | Buffer,
 |  | IN UINTN | NumberOfBytes
 | ) |  |

Write data to serial device.

If the buffer is NULL, then return 0; if NumberOfBytes is zero, then return 0.

Parameters
[in] | Buffer | Data pointer
[in] | NumberOfBytes | Number of output bytes which are cached in Buffer.
Return values
Actual number of bytes written to serial device.


AlderLake Platform Sample Code: SerialIoUartDebugHelperLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
SerialIoUartDebugHelperLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2019 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification
32
33 **/
34
35 #ifndef __SERIAL_IO_UART_DEBUG_HELPER_LIB_H__
36 #define __SERIAL_IO_UART_DEBUG_HELPER_LIB_H__
37
38 /**
39 Initialize SerialIo UART for debug.
40
41 **/
42 VOID
43 EFIAPI
44 SerialIoUartDebugInit (
45 VOID
46 );
47
48 /**
49 Write data to serial device.
50
51 If the buffer is NULL, then return 0;
52 if NumberOfBytes is zero, then return 0.
53
54 @param[in] Buffer Data pointer
55 @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
56
57 @retval Actual number of bytes written to serial device.
58 **/
59 UINTN
60 EFIAPI
61 SerialIoUartDebugWrite (
62 IN UINT8 *Buffer,
63 IN UINTN NumberOfBytes
64 );
65
66 #endif // __SERIAL_IO_UART_DEBUG_HELPER_LIB_H__
SerialIoUartDebugWrite
UINTN SerialIoUartDebugWrite(IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data to serial device.
SerialIoUartDebugInit
VOID SerialIoUartDebugInit(VOID)
Initialize SerialIo UART for debug.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SerialIoUartDebugPropertyLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
SerialIoUartDebugPropertyLib.h File Reference
#include <SerialIoDevices.h>
Include dependency graph for SerialIoUartDebugPropertyLib.h:

Go to the source code of this file.

Functions

VOID | SerialIoUartDebugGetAttributes (IN OUT SERIAL_IO_UART_ATTRIBUTES *UartAttributes)
Returns UART's attributes. More...
UINT8 | SerialIoUartDebugGetControllerNumber (VOID)
Returns Serial Io UART Controller Number used in Debug mode. More...
UINT32 | SerialIoUartDebugGetPciDefaultMmioBase (VOID)
Returns Serial Io UART MMIO Base Address. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoUartDebugPropertyLib.h.

Function Documentation

◆ SerialIoUartDebugGetAttributes()

VOID SerialIoUartDebugGetAttributes ( IN OUT SERIAL_IO_UART_ATTRIBUTES * UartAttributes )

Returns UART's attributes.

Parameters
[in,out] UartAttributes Uart Attributes

◆ SerialIoUartDebugGetControllerNumber()

UINT8 SerialIoUartDebugGetControllerNumber ( VOID )

Returns Serial Io UART Controller Number used in Debug mode.

Return values
ControllerNumber UART Controller Number

◆ SerialIoUartDebugGetPciDefaultMmioBase()

UINT32 SerialIoUartDebugGetPciDefaultMmioBase ( VOID )

Returns Serial Io UART MMIO Base Address.

Return values
MMIO Base Address by default in PCI Mode
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SerialIoUartDebugPropertyLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
SerialIoUartDebugPropertyLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2019 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SERAIL_IO_DEBUG_PROPERTY_LIB_H_
35 #define _SERAIL_IO_DEBUG_PROPERTY_LIB_H_
36
37 #include <SerialIoDevices.h>
38
39 /**
40 Returns UART's attributes
41
42 @param[in,out] UartAttributes Uart Attributes
43 **/
44 VOID
45 SerialIoUartDebugGetAttributes (
46 IN OUT SERIAL_IO_UART_ATTRIBUTES *UartAttributes
47 );
48
49 /**
50 Returns Serial Io UART Controller Number used in Debug mode
51
52 @retval ControllerNumber UART Controller Number
53 **/
54 UINT8
55 SerialIoUartDebugGetControllerNumber (
56 VOID
57 );
58
59 /**
60 Returns Serial Io UART MMIO Base Address
61
62 @retval MMIO Base Address by default in PCI Mode
63 **/
64 UINT32
65 SerialIoUartDebugGetPciDefaultMmioBase (
66 VOID
67 );
68
69 #endif //_SERAIL_IO_DEBUG_PROPERTY_LIB_H_
SerialIoUartDebugGetAttributes
VOID SerialIoUartDebugGetAttributes(IN OUT SERIAL_IO_UART_ATTRIBUTES *UartAttributes)
Returns UART's attributes.
SerialIoUartDebugGetPciDefaultMmioBase
UINT32 SerialIoUartDebugGetPciDefaultMmioBase(VOID)
Returns Serial Io UART MMIO Base Address.
SerialIoUartDebugGetControllerNumber
UINT8 SerialIoUartDebugGetControllerNumber(VOID)
Returns Serial Io UART Controller Number used in Debug mode.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SerialPortParameterLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
SerialPortParameterLib.h File Reference

This library class provides capability to get/set serial port baud rate. More...

Go to the source code of this file.

Functions

UINT32 | GetSerialPortBaudRate (VOID)
Returns the serial port baud rate. More...
BOOLEAN | SetSerialPortBaudRate (UINT32 BaudRate)
Sets the serial port baud rate value. More...
UINT8 | GetDebugInterface (VOID)
Returns enabled debug interfaces. More...
VOID | SetDebugInterface (UINT8 DebugInterface)
Sets debug interfaces. More...

Detailed Description

This library class provides capability to get/set serial port baud rate.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file SerialPortParameterLib.h.

Function Documentation

◆ GetDebugInterface()

UINT8 GetDebugInterface ( VOID )

Returns enabled debug interfaces.

Return values
Enabled debug interfaces bitmask.

◆ GetSerialPortBaudRate()

UINT32 GetSerialPortBaudRate ( VOID )

Returns the serial port baud rate.

Returns
Baud rate of serial port.

◆ SetDebugInterface()

VOID SetDebugInterface ( UINT8 DebugInterface )

Sets debug interfaces.

Parameters
[in] DebugInterface Debug interfaces to be set.

◆ SetSerialPortBaudRate()

BOOLEAN SetSerialPortBaudRate ( UINT32 BaudRate )

Sets the serial port baud rate value.

Parameters
[in] BaudRate Baud rate value to be set.
Return values
TRUE | The baud rate of serial port was sucessfully set.
FALSE | The baud rate of serial port could not be set.


AlderLake Platform Sample Code: SerialPortParameterLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
SerialPortParameterLib.h
Go to the documentation of this file.
1 /** @file
2 This library class provides capability to get/set serial port baud rate.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef __SERIAL_PORT_PARAMETER_LIB__
36 #define __SERIAL_PORT_PARAMETER_LIB__
37
38 #define STATUS_CODE_USE_RAM BIT0
39 #define STATUS_CODE_USE_ISA_SERIAL BIT1
40 #define STATUS_CODE_USE_USB BIT2
41 #define STATUS_CODE_USE_USB3 BIT3
42 #define STATUS_CODE_USE_SERIALIO BIT4
43 #define STATUS_CODE_USE_TRACEHUB BIT5
44 #define STATUS_CODE_CMOS_INVALID BIT6
45 #define STATUS_CODE_CMOS_VALID BIT7
46
47
48 /**
49 Returns the serial port baud rate.
50
51 @return Baud rate of serial port.
52
53 **/
54 UINT32
55 EFIAPI
56 GetSerialPortBaudRate (
57 VOID
58 );
59
60 /**
61 Sets the serial port baud rate value.
62
63 @param[in] BaudRate Baud rate value to be set.
64
65 @retval TRUE The baud rate of serial port was sucessfully set.
66 @retval FALSE The baud rate of serial port could not be set.
67
68 **/
69 BOOLEAN
70 EFIAPI
71 SetSerialPortBaudRate (
72 UINT32 BaudRate
73 );
74
75 /**
76 Returns enabled debug interfaces.
77
78 @retval Enabled debug interfaces bitmask.
79
80 **/
81 UINT8
82 GetDebugInterface (
83 VOID
84 );
85
86 /**
87 Sets debug interfaces.
88
89 @param[in] DebugInterface Debug interfaces to be set.
90
91 **/
92 VOID
93 SetDebugInterface (
94 UINT8 DebugInterface
95 );
96
97
98 #endif
GetDebugInterface
UINT8 GetDebugInterface(VOID)
Returns enabled debug interfaces.
SetDebugInterface
VOID SetDebugInterface(UINT8 DebugInterface)
Sets debug interfaces.
GetSerialPortBaudRate
UINT32 GetSerialPortBaudRate(VOID)
Returns the serial port baud rate.
SetSerialPortBaudRate
BOOLEAN SetSerialPortBaudRate(UINT32 BaudRate)
Sets the serial port baud rate value.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Setup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
Setup.h File Reference
#include "SetupConfiguration.h"
#include "SetupVariable.h"
Include dependency graph for Setup.h:
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Macros

#define | SYSTEM_ACCESS_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | EFI_PASSWORD_STATUS_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | DEBUG_CONFIG_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Setup.h.


AlderLake Platform Sample Code: Setup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Setup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2009 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __SETUP__H__
35 #define __SETUP__H__
36
37 #include "SetupConfiguration.h"
38 #include "SetupVariable.h"
39
40 #ifndef MDEPKG_NDEBUG
41 #define DEBUG_INTERFACE_FORM_ENABLE
42 #endif // MDEPKG_NDEBUG
43 //
44 // Form class guid for the forms those will be showed on first front page.
45 //
46 #define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a, 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } }
47 //
48 // Form class guid for the forms those will be showed on boot maintenance manager menu.
49 //
50 #define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a, 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } }
51
52 // VFR common Definitions
53 #define INVENTORY(Name,Value) \
54 text \
55 help = STRING_TOKEN(STR_EMPTY), \
56 text = Name, \
57 text = Value, \
58 flags = 0, \
59 key = 0;
60
61 #define SUBTITLE(Text) subtitle text = Text;
62 #define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY))
63
64 #define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\
65 grayoutif TRUE;\
66 oneof varid = SETUP_DATA.InteractiveText,\
67 questionid = Key,\
68 prompt = CaptionToken,\
69 help = HelpToken,\
70 option text = ValueToken, value = 0, flags = INTERACTIVE | DEFAULT;\
71 refresh interval = 1 \
72 endoneof;\
73 endif;
74
75 #define SUPPRESS_GRAYOUT_ENDIF endif; endif;
76 #define DEFAULT_FLAG
77
78 #define SYSTEM_ACCESS_KEY_ID 0xF000
79 //
80 // System Access defintions.
81 //
82 #define SYSTEM_ACCESS_GUID \
83 { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE, 0xAC }}
84
85 #define SYSTEM_PASSWORD_ADMIN 0
86 #define SYSTEM_PASSWORD_USER 1
87 #define ADMIN_PW_CLEAR 0
88 #define ADMIN_PW_SET 1
89
90 /**
91 Making any setup structure change after code frozen
92 will need to maintain backward compatibility, bump up
93 structure revision and update below history table\n
94 <b>Revision 1</b>: - Initial version.
95 **/
96 #define SYSTEM_ACCESS_REVISION 1
97
98 typedef struct _SYSTEM_ACCESS
99 {
100 //
101 // Passwords
102 //
103 UINT8 Access;
104 } SYSTEM_ACCESS;
105
106 /**
107 Making any setup structure change after code frozen
108 will need to maintain backward compatibility, bump up
109 structure revision and update below history table\n
110 <b>Revision 1</b>: - Initial version.
111 **/
112 #define EFI_PASSWORD_STATUS_REVISION 1
113
114 //
115 // Record the password status.
116 //
117 typedef struct {
118 UINT8 AdminName;
119 UINT8 UserName;
120 } EFI_PASSWORD_STATUS;
121
122 #pragma pack(1)
123
124 /**
125 Making any setup structure change after code frozen
126 will need to maintain backward compatibility, bump up
127 structure revision and update below history table\n
128 <b>Revision 1</b>: - Initial version.
129 **/
130 #define DEBUG_CONFIG_DATA_REVISION 1
131 //
132 // Config Data
133 //
134 typedef struct {
135 UINT8 SerialDebugMrcLevel;
136 UINT8 SerialDebug;
137 UINT8 SerialDebugBaudRate;
138 UINT8 RamDebugInterface;
139 UINT8 UartDebugInterface;
140 UINT8 Usb3DebugInterface;
141 UINT8 SerialIoDebugInterface;
142 UINT8 TraceHubDebugInterface;
143 // SerialIouartDebug Configuration
144 UINT8 SerialIoUartDebugControllerNumber;
145 UINT32 SerialIoUartDebugBaudRate;
146 UINT8 SerialIoUartDebugStopBits;
147 UINT8 SerialIoUartDebugParity;
148 UINT8 SerialIoUartDebugFlowControl;
149 UINT8 SerialIoUartDebugDataBits;
150 } DEBUG_CONFIG_DATA;
151
152 //
153 // Config Data Hob
154 //
155 #define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA
156
157 #pragma pack()
158
159 //
160 // Varstore statement
161 // Setup is EfiVarStore that is related to EFI variable with attribute 0x07
162 // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS)
163 //
164 #define SETUP_DATA_VARSTORE\
165 efivarstore SETUP_DATA, varid = 1,\
166 attribute = 0x7, name = Setup, guid = SETUP_GUID;
167 #define SA_SETUP_VARSTORE\
168 efivarstore SA_SETUP, varid = 2,\
169 attribute = 0x7, name = SaSetup, guid = SA_SETUP_GUID;
170 #define CPU_SETUP_VARSTORE\
171 efivarstore CPU_SETUP, varid = 3,\
172 attribute = 0x7, name = CpuSetup, guid = CPU_SETUP_GUID;
173 #define ME_SETUP_VARSTORE\
174 efivarstore ME_SETUP, varid = 4,\
175 attribute = 0x7, name = MeSetup, guid = ME_SETUP_GUID;
176 #define PCH_SETUP_VARSTORE\
177 efivarstore PCH_SETUP, varid = 5,\
178 attribute = 0x7, name = PchSetup, guid = PCH_SETUP_GUID;
179 #define SI_SETUP_VARSTORE\
180 efivarstore SI_SETUP, varid = 6,\
181 attribute = 0x7, name = SiSetup, guid = SI_SETUP_GUID;
182 #define BOARD_INFO_SETUP_VARSTORE\
183 efivarstore BOARD_INFO_SETUP, varid = 7,\
184 attribute = 0x7, name = BoardInfoSetup, guid = BOARD_INFO_SETUP_GUID;
185 #ifdef DEBUG_INTERFACE_FORM_ENABLE
186 #define DEBUG_CONFIG_DATA_ID 0xF001
187 #define DEBUG_CONFIG_DATA_VARSTORE\
188 efivarstore DEBUG_CONFIG_DATA, varid = DEBUG_CONFIG_DATA_ID,\
189 attribute = 0x7, name = DebugConfigData, guid = DEBUG_CONFIG_GUID;
190 #endif // DEBUG_INTERFACE_FORM_ENABLE
191 #define SYSTEM_ACCESS_VARSTORE\
192 varstore SYSTEM_ACCESS, varid = SYSTEM_ACCESS_KEY_ID,\
193 name = SystemAccess, guid = SYSTEM_ACCESS_GUID;
194 #define SYSTEM_PASSWORD_VARSTORE\
195 varstore EFI_PASSWORD_STATUS,\
196 name = PasswordStatus, guid = SYSTEM_ACCESS_GUID;
197
198 #define BOOT_FLOW_CONDITION_RECOVERY 2
199 #define BOOT_FLOW_CONDITION_FIRST_BOOT 4
200
201 #endif
SetupConfiguration.h
Default platform setup configuration settings.
SetupVariable.h
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SetupConfiguration.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SetupConfiguration.h File Reference

Default platform setup configuration settings. More...

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Go to the source code of this file.

Detailed Description

Default platform setup configuration settings.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SetupConfiguration.h.


AlderLake Platform Sample Code: SetupConfiguration.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SetupConfiguration.h
Go to the documentation of this file.
1 /** @file
2 Default platform setup configuration settings.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SETUP_CONFIGURATION_H_
36 #define _SETUP_CONFIGURATION_H_
37
38 #define SERIAL_SETUP_OPTION 1
39 #define TOTAL_SIO_SERIAL_PORTS 0x4
40 #define TOTAL_PCI_SERIAL_PORTS 0x1
41 #define TOTAL_SERIAL_PORTS 0x5
42 #define MAX_SIO_SERIAL_PORTS 0x4
43 #define MAX_PCI_SERIAL_PORTS 0x4
44
45 #define DEFAULT_CONSOLE_REDIRECTION_ENABLE 1
46 #define DEFAULT_ACPI_SPCR_COM_PORT 0x0
47 #define DEFAULT_TERMINAL_TYPE 0x3
48 #define DEFAULT_RESOLUTION_TYPE 0x0
49 #define DEFAULT_ACPI_SPCR_CONSOLE_REDIRECTION_ENABLE 1
50 #define DEFAULT_ACPI_SPCR_TABLE_TERMINAL_TYPE 0x2
51 #define HARDWARE_FLOW_CONTROL_SETUP_OPTION 0x1
52 #define SOFTWARE_FLOW_CONTROL_SETUP_OPTION 0x2
53 #define TIMEOUT_FOR_DETERMINING_LONE_ESC_CHAR 0xf4240
54
55 #define DEFAULT_BOOT_TIMEOUT 0x1
56 #define DEFAULT_FAST_BOOT 0
57 #define DEFAULT_QUIET_BOOT 0
58 #define FORCE_USER_TO_SETUP_ON_FIRST_BOOT 0
59 #define SHOW_ADVANCED_FORMSET 1
60 #define FORCE_USER_TO_SETUP_IF_BOOT_WITH_DEFAULT 0
61 #define LOAD_DEFAULTS_IF_SECONDARY_NVRAM_INIT 1
62
63 #define UART_SERIAL_PORT_0_INDEX 0x0
64 #define UART_SERIAL_PORT_1_INDEX 0x1
65 #define UART_SERIAL_PORT_2_INDEX 0x2
66 #define UART_SERIAL_PORT_3_INDEX 0x3
67 #define PCI_SERIAL_PORT_0_INDEX 0x4
68 #define PCI_SERIAL_PORT_1_INDEX 0x5
69 #define PCI_SERIAL_PORT_2_INDEX 0x6
70 #define PCI_SERIAL_PORT_3_INDEX 0x7
71
72 #define OFFSET_0 0x0
73 #define OFFSET_1 0x1
74 #define OFFSET_2 0x2
75 #define OFFSET_3 0x3
76 #define OFFSET_4 0x4
77 #define OFFSET_5 0x5
78 #define OFFSET_6 0x6
79 #define OFFSET_7 0x7
80 #define OFFSET_8 0x8
81 #define OFFSET_9 0x9
82 #define OFFSET_10 0xa
83 #define OFFSET_11 0xb
84 #define OFFSET_12 0xc
85 #define OFFSET_13 0xd
86 #define OFFSET_14 0xe
87 #define OFFSET_15 0xf
88 #define OFFSET_16 0x10
89 #define OFFSET_17 0x11
90 #define OFFSET_18 0x12
91 #define OFFSET_19 0x13
92 #define OFFSET_20 0x14
93 #define OFFSET_21 0x15
94 #define OFFSET_22 0x16
95 #define OFFSET_23 0x17
96 #define OFFSET_24 0x18
97 #define OFFSET_25 0x19
98 #define OFFSET_26 0x1a
99 #define OFFSET_27 0x1b
100 #define OFFSET_28 0x1c
101 #define OFFSET_29 0x1d
102 #define OFFSET_30 0x1e
103 #define OFFSET_31 0x1f
104 #define OFFSET_32 0x20
105 #define OFFSET_33 0x21
106 #define OFFSET_34 0x22
107 #define OFFSET_35 0x23
108 #define OFFSET_36 0x24
109 #define OFFSET_37 0x25
110 #define OFFSET_38 0x26
111 #define OFFSET_39 0x27
112 #define ENGLISH en-US
113
114 #endif
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SetupVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
SetupVariable.h File Reference
#include <PchLimits.h>
#include <CpuPcieInfo.h>
#include <TcssInfo.h>
#include <CpuLimits.h>
Include dependency graph for SetupVariable.h:
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Macros

#define | SETUP_DATA_REVISION 63
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | CPU_SETUP_REVISION 65
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | CPU_SETUP_VOLATILE_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | TBT_SETUP_VOLATILE_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.
#define | ME_SETUP_REVISION 5
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | SA_SETUP_REVISION 43
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | PCH_SETUP_REVISION 14
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
. More...
#define | SI_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table. More...
#define | DEBUG_SETUP_VOLATILE_DATA_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SetupVariable.h.

Macro Definition Documentation

◆ CPU_SETUP_REVISION

#define CPU_SETUP_REVISION 65

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Updated VR related setup options. Revision 3: - Removed Voltage Optimization Feature as not a POR. Revision 4: - Deprecate BiosGuard enabling support Revision 5: - Added PsysOffsetPrefix. Revision 6: - Deprecate Vr Voltage Limit support Revision 7: - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor Revision 8: - Add ApplyConfigTdp. Revision 9: - Added Hwp Lock support. Revision 10: - Add SmmMsrSaveStateEnable, SmmUseDelayIndication, SmmUseBlockIndication, SmmUseSmmEnableIndication, SmmProcTraceEnable. Revision 11: - Added number of active small core support. Revision 12: - Add PerCoreHtDisable. Revision 13: - Add VF Point Offset Mode support. Revision 14: - Updated the VR Topology data. Revision 15: - Add irms support Revision 16: - Add Per-core VF curve support. Revision 17: - Add AllSmallCoreCount/AllBigCoreCount. Revision 18: - Deprecate SmmSpsEnable enabling DGR support. Revision 19: - Add RatioLimitRatioDefault, RatioLimitRatio, RatioLimitNumCoreDefault, RatioLimitNumCore, AtomRatioLimitRatioDefault, AtomRatioLimitRatio, AtomRatioLimitNumCoreDefault and AtomRatioLimitNumCore to replace RatioLimitXDefault and RatioLimitX. Correct IsTurboRatioDefaultsInitalized to IsTurboRatioDefaultsInitialized. Revision 20: - Add DualTauBoost Revision 21: - Add AtomL2MaxOcRatio and AtomL2MaxOcRatioDefault Revision 22: - Add PerCoreRatioOverride and PerCoreRatio for Per Core Ratio override Revision 23: - Add support for Platform Voltage control Revision 24: - Add PreWake, RampUp and RampDown for Acoustic Noise Mitigation DPA tuning. Revision 25: - Add UnlimitedIccMax Revision 26: - Removed EnableItbmDriver. Revision 27: - Add IntelSpeedOptimizer. Revision 28: - Add AtomL2Voltage related setup variables. Revision 29: - Add Avx disable support. Revision 30: - Add SA/Uncore voltage configurations Revision 31: - add CrashLogGprs. Revision 32: - Add TvbRatioClipping, TvbVoltageOptimization Revision 33: - Add Vr Voltage Limit Revision 34: - Add VF Point Offset Mode support for Ring. Revision 35: - Add VccInAux IMON support Revision 36: - Add FIVR Spread Spectrum Enable. Revision 37: - Add CpuBclkOcFrequency Revision 38: - Add processor disable control support to indicate which core/atom should be disabled. Revision 39: - Add VR Power Delivery design Revision 40: - Add Core Ratio Extension Mode support. Revision 41: - Deprecate SGx. Revision 42: - Add Pvd Ratio Threshold. Revision 43: - Add per Atom Cluster VF support. Revision 44: - Add new external voltage rails overrides and deprecated some others unused voltage rails based on ADL OC RVP design. Revision 45: - Add VR Fast Vmode ICC Limit support. Revision 46: - Add CEP enable/disable support for IA/GT. Revision 47: - Add AtomPllVoltageOffset. Revision 48: - Removed FivrFaults, FivrEfficiency. Revision 49: - Add VCCIN_AUX and Richtek VccIA and VccGT voltage override support Revision 50: - Add DlvrBypassModeEnable support. Revision 51: - Deprecated AtomL2MaxOcRatio Revision 52: - Deprecated Avx3Disable Revision 53: - Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset Revision 54: - Add SaPllFreqOverride support. Revision 55: - Add PllMaxBandingRatio Revision 56: - Add TscDisableHwFixup Revision 57: - Add IaIccMax, IaIccUnlimitedMode, GtIccMax, GtIccUnlimitedMode, deprecated UnlimitedIccMax Revision 58: - Add PerCoreDisableConfiguration Revision 59: - Add TvbDownBinsTempThreshold0, TvbTempThreshold0, TvbTempThreshold1, TvbDownBinsTempThreshold1 Revision 60: - Add GameComptibilityMode Revision 61: - Deprecated SafModeDisableBiosGuard Revision 62: - Deprecated PllMaxBandingRatio Revision 63: - Add FllOcModeEn, FllOverclockMode Revision 64: - Added PerCoreDisable1, PerCoreDisableOriMask and Deprecated PerCoreDisable, PerAtomDisable. Revision 65: - Add Etvb

Definition at line 1801 of file SetupVariable.h.

◆ ME_SETUP_REVISION

#define ME_SETUP_REVISION 5

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Add MacPassThrough Revision 3: - Add One Click Recovery setup variables Revision 4: - Add Remote Platform Erase setup variables Revision 5: - Add Cse Data Resilience setup variables

Definition at line 2350 of file SetupVariable.h.

◆ PCH_SETUP_REVISION

#define PCH_SETUP_REVISION 14

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
.

Revision 1: - Initial version. Revision 2: - Added PchXhciUaol to control UAOL feature enable status Revision 3: - Added Foxville LAN support Revision 4: - Deprecated DciModphyPg Revision 5: - Added Serial Io Debug Uart Power Gating support for Kernel Debug Revision 6: - Added CpuRootportUsedForHybridStorage and PchRootportUsedForCpuAttach to control Hybrid storage when it iss used with cpu root ports Revision 7: - Added FUSA IOP config support Revision 8: - Added AcpiL6dPmeHandling for _L6D. BIOS-ACPI can verify PMEENABLE and PMESTATUS of each device that requires GPE related wake Revision 9: - Added CpuHybridStorageConnected to store the status of the hybrid device connected to CPU PCIE slot. Revision 10: - Added PchScsEmmcEnabled, PchScsEmmcHs400Enabled, PchScsEmmcHs400DriverStrength, PchScsEmmcHs400SoftwareTuning for eMMC. Revision 11: - Added PchSkipVccInConfig. Revision 12: - Added PchHdaAlc245DmicConfiguration. Revision 13: - Added Hid Over Spi support for THC. Revision 14: - Add PchXhciHsiiEnable.

Definition at line 3111 of file SetupVariable.h.

◆ SA_SETUP_REVISION

#define SA_SETUP_REVISION 43

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Adding PEG RTD3 Support Setup Variable Revision 3: - Remove IedMemEnable. Revision 4: - Added VmdGlobalMapping Revision 5: - Added TCSS Tc C-State Limit. Revision 6: - Adding support for TCSS CPU XHCI Port Disable Override. Revision 7: - Added DisplayAudioLink Revision 8: - Added PPR Enable Type Revision 9: - Added LpddrRttWr and LpddrRttCa Revision 10: - Added MemoryVddqVoltage, MemoryVppVoltage Revision 11: - DisableDimmMcXChY changed to DisableMcXChY Revision 12: - Added PcieRootPortNewFom and DmiNewFom Revision 13: - Added DmiCdrRelock and PcieRootPortCdrRelock. Revision 14: - Added DIMMDFE Revision 15: - Added ExtendedBankHashing Revision 16: - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount Revision 17: - Deprecated DdrOddRatioMode Revision 18: - Added DynamicMemoryBoost Revision 19: - Added HgSupport Revision 20: - Added Config Fusa Revision 21: - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm Revision 22: - Deprecated RpFunctionSwap Revision 23: - Added PcieFunc0LinkDisable Revision 24: - Added DebugValue Revision 25: - Added PcieResizableBarSupport Revision 26: - Added McRefreshRate; Deprecated McRefresh2X Revision 27: - Added RealtimeMemoryFrequency Revision 28: - Added PeriodicDcc and LpMode Revision 29: - Added TcColdPowerSavingFactorSwitch, IomStayInTCColdSeconds and IomBeforeEnteringTCColdSeconds Revision 30: - Added TX DQS DCC Revision 31: - Added Timing parameters, tRFCpb, tRFC2, ..., tWTR_S Revision 32: - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount Revision 33: - Added FreqLimitMixedConfig and FirstDimmBitMask Revision 34: - Added SAGV SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsUpControl, SagvHeuristicsDownControl Revision 35: - Added DRAMDCA Revision 36: - Added DynamicMemoryBoostTrainingFailed Revision 37: - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R Revision 38: - Deprecated IgdDvmt50TotalAlloc Revision 39: - Added LctCmdEyeWidth Revision 40: - FirstDimmBitMaskEcc Revision 41: - Lp5BankMode Revision 43: - WRDS

Definition at line 2505 of file SetupVariable.h.

◆ SETUP_DATA_REVISION

#define SETUP_DATA_REVISION 63

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Added PepVmd Revision 3: - Added CnvExtClock Revision 4: - Added PPAG support Revision 5: - Added FlashMode Revision 6: - Cpu Pciexpress Gen3 Compatability Revision 7: - Added DeepestUSBSleepWakeCapability Revision 8: - Add PEP constraint support on SATA ports Revision 9: - Added PepHeci3 Revision 10: - Added 11ax R2 support and UHB channel support Revision 11: - Deprecate IccPllShutdownEnabled Revision 12: - Deprecated TR A0 workaround setup options Revision 13: - Deprecated MipiCam_LanesClkDiv and Added MipiCam_Link(X)_LanesClkDiv for all 6(0-5) Links. Revision 14: - Added Fan 2, Fan 3 and dGPU paticipant, AdlSAepBoard setup variable Revision 15: - Added WiFi Time Average SAR support Revision 16: - Added PLN support Revision 17: - Deprecated TbtSkipPciOprom Revision 18: - TcssPdPsOnEnable Revision 19: - Adding PepPcieLan,PepPcieWlan,PepPcieGfx and PepPcieOther for PCIe root port constraint configuration. Revision 20: - Adding AuxRailBudget Revision 21: - Added CVF Support Revision 22: - Deprecated CurrentSecurityMode, using EnablePcieTunnelingOverUsb4 to represent security level Revision 23: - Added WiFi Time Average SAR support Revision 24: - Added DTbt Off Method Delay optimization. Revision 25: - Replace TbtVtdBaseSecurity with DisableTbtPcieTreeBme. Revision 26: - Added StorageRtd3Support; Revision 27: - Adding PMAX device settings Revision 28: - Deprecated Gpio3ForcePwrDly Revision 29: - Added MPdt Support Revision 30: - Add DiscreteTbtPlatformConfigurationSupport Setup variable. Revision 31: - Deprecated ITbtPcieTunnelingForUsb4 Revision 32: - Added DtbtCmSupport and Usb4CmMode Revision 33: - Added PepUfs0 and PepUfs1 Revision 34: - Added TestEnableTcssCovTypeA[MAX_TCSS_USB3_PORTS] and TestDisableTcssPortUcxxSupport[10] Revision 35: - Deprecated TbtUsbOn Revision 36: - Depricated SecondConfigReworkOption. Revision 37: - DpInExternalEn Revision 38: - Deprecated TestEnableTcssCovTypeA[MAX_TCSS_USB3_PORTS]. Revision 39: - Added CpuBclkFreq, PegDmiClkFreq, and DccClkCtrl Revision 40: - Added UsbcDataRoleSwapPlatformDisable Revision 41: - Added TwoMapleRidgeBoard Revision 42: - Added FlashID Support for link 0-5 Revision 43: - Added SerialIoTiming Parameters and PEP Constraint for I2C6 and I2C7 Revision 44: - Deprecated TwoMapleRidgeBoard add DTbtDpInSupport Revision 45: - XmlCli Related Knobs are now removed and reserved bytes added for offset consistency Revision 46: - Deprecated WPFC (WiFi Phy Filter Configuration) Revision 47: - Added WwanTPer2ResDelayMs Revision 48: - Added WwanOemSvid and WwanSvidTimeout Revision 49: - Updated BT Tile to Rev 1 (Ring My PC) Revision 50: - Added WifiRegulatoryConfigurations, WifiUartConfigurations, WifiUnii4 and WifiIndoorControl Revision 51: - Added pep constraint support for EMMC Revision 52: - Deprecated PPR interface for MipiCamera Revision 53: - Deprecated SdCard D3 Cold Support Revision 54: - Added WirelessCnvConfigDevice to enable/disable WCCD Revision 55: - Add CurrentCpuBclkFreq, CurrentPegDmiClkFreq for DCC OC Revision 56: - Added WLAN/WWAN Antenna Isolation support for WiFi Revision 57: - Deprecated SGOM variables. Revision 58: - Add WgdsWiFiSarDeltaGroup and more WgdsWifiSarDeltaGroup elements for WGDS revision 3 Revisiom 59: - RP08 Wake Rework Done Revision 60: - Rp08 D3 cold Support Revision 61: - Add WifiTASSelectionValue for RPL (WTSY revision 1) Revision 62: - Added RplSAepBoard setup variable Revision 63: - Added DMI Policies

Definition at line 324 of file SetupVariable.h.

◆ SI_SETUP_REVISION

#define SI_SETUP_REVISION 1

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table.

Revision 1: - Initial version.

Definition at line 3590 of file SetupVariable.h.


AlderLake Platform Sample Code: SetupVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SetupVariable.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SETUP_VARIABLE_H_
35 #define _SETUP_VARIABLE_H_
36
37 #include <PchLimits.h>
38 #include <CpuPcieInfo.h>
39 #include <TcssInfo.h>
40 #include <CpuLimits.h>
41
42 #define VMD_MAX_DEVICES 31
43 #ifndef MAX_CUSTOM_P_STATES
44 #define MAX_CUSTOM_P_STATES 40
45 #endif // MAX_CUSTOM_P_STATES
46 #ifndef MAX_16_CUSTOM_P_STATES
47 #define MAX_16_CUSTOM_P_STATES 16
48 #endif // MAX_16_CUSTOM_P_STATES
49
50 #define MAX_IIO_PCI_EXPRESS_ROOT_PORTS 4
51 #define MAX_PCI_ROOT_BRIDGES 1
52 #define SATA_MODE_AHCI 0
53 #define SATA_MODE_RAID 1
54 #define SATA_TEST_MODE_ENABLE 1
55 #define NON_CS_DEVICES 9
56 #define I2C0_SENSOR_DEVICES 7
57 #define I2C1_SENSOR_DEVICES 13
58 #define SERIAL_IO_I2C0 0x0
59 #define SERIAL_IO_I2C1 0x1
60 #define SERIAL_IO_I2C2 0x2
61 #define SERIAL_IO_I2C3 0x3
62 #define SERIAL_IO_I2C4 0x4
63 #define SERIAL_IO_I2C5 0x5
64 #define SERIAL_IO_I2C6 0x6
65 #define SERIAL_IO_I2C7 0x7
66
67 #define SERIAL_IO_SPI0 0x0
68 #define SERIAL_IO_SPI1 0x1
69 #define SERIAL_IO_SPI2 0x2
70 #define SERIAL_IO_SPI3 0x3
71 #define SERIAL_IO_SPI4 0x4
72 #define SERIAL_IO_SPI5 0x5
73 #define SERIAL_IO_SPI6 0x6
74
75 #define SERIAL_IO_UART0 0x0
76 #define SERIAL_IO_UART1 0x1
77 #define SERIAL_IO_UART2 0x2
78 #define SERIAL_IO_UART3 0x3
79 #define SERIAL_IO_UART4 0x4
80 #define SERIAL_IO_UART5 0x5
81 #define SERIAL_IO_UART6 0x6
82
83 //
84 // This is 8 Bits Map of I2C Devices for combined use in BoardConfigPatchTable.h and in PchSetup.hfr
85 //
86 #define SERIAL_IO_I2C_TOUCHPAD 0x1
87 #define SERIAL_IO_I2C_TOUCHPANEL 0x2
88 #define SERIAL_IO_I2C_UCMC 0x4
89 #define SERIAL_IO_I2C_PD02 0x8
90 //#define 5TH_SERIAL_IO_I2C_DEVICE 0x10
91 //#define 6TH_SERIAL_IO_I2C_DEVICE 0x20
92 //#define 7TH_SERIAL_IO_I2C_DEVICE 0x40
93 //#define 8TH_SERIAL_IO_I2C_DEVICE 0x80
94
95 //
96 // This is 8 Bits Map of SPI Devices for combined use in BoardConfigPatchTable.h and in PchSetup.hfr
97 //
98 #define SERIAL_IO_SPI_FINGERPRINT 0x1
99 //#define 2nd_SERIAL_IO_SPI_DEVICE 0x02
100 //#define 3rd_SERIAL_IO_SPI_DEVICE 0x04
101 //#define 4TH_SERIAL_IO_SPI_DEVICE 0x08
102 //#define 5TH_SERIAL_IO_SPI_DEVICE 0x10
103 //#define 6TH_SERIAL_IO_SPI_DEVICE 0x20
104 //#define 7TH_SERIAL_IO_SPI_DEVICE 0x40
105 //#define 8TH_SERIAL_IO_SPI_DEVICE 0x80
106
107 #define HDAUDIO_FEATURES 9
108 #define HDAUDIO_PP_MODULES 32
109
110 #define HDAUDIO_DMIC_CLOCK_SELECT_BOTH 0
111 #define HDAUDIO_DMIC_CLOCK_SELECT_CLKA 1
112 #define HDAUDIO_DMIC_CLOCK_SELECT_CLKB 2
113
114 #define GUID_CHARS_NUMBER 37 // 36 GUID chars + null termination
115 #define FIVR_RAIL_S0IX_SX_STATES_MAX 6 // Number of availabe S0ix/Sx policy bits in FIVR Rail configuration
116 #define FIVR_RAIL_EXT_VOLTAGE_STATES_MAX 4 // Number of supported voltage settings for FIVR Rail configuration
117
118 #define SETUP_MAX_USB2_PORTS 16
119 #define SETUP_MAX_USB3_PORTS 10
120
121 // DTT EC supported Fans & Sensors
122 #define MAX_EC_SENSORS 5
123 #define MAX_EC_FANS 3
124 #define VBT_SELECT_EDP 0x0
125 #define VBT_SELECT_MIPI 0x1
126
127 #define OPROM_EFI 1
128 #define OPROM_LEGACY 0
129
130 #define MIPICAM_I2C_DEVICES_COUNT 12
131 #define MIPICAM_GPIO_COUNT 6
132 #define MIPICAM_MODULE_NAME_LENGTH 16
133 #define MIPICAM_HID_MIN_LENGTH 6
134 #define MIPICAM_HID_LENGTH 20
135 #define DTBT_CONTROLLER_SUPPORTED 2
136 #define ITBT_ROOT_PORTS_SUPPORTED 6
137 #define ITBT_HOST_DMA_SUPPORTED 3
138 #define CPU_FM_TGL_ULT_ULX 0x000006C0
139 #define CPU_FM_ADL_ULT_ULX 0x000006A0
140 #define CPU_FM_ADL_DT_HALO 0x00000670
141 #define CPU_STEPPING_ADL_A0 0
142
143 #define IBECC_REGIONS_MAX 8
144
145 //
146 // Max number of VF point offset
147 //
148 #ifndef CPU_OC_MAX_VF_POINTS
149 #define CPU_OC_MAX_VF_POINTS 0xF
150 #endif
151
152 #define MAX_VR_NUM 5
153
154 #ifndef TURBO_RATIO_LIMIT_ARRAY_SIZE
155 #define TURBO_RATIO_LIMIT_ARRAY_SIZE 8
156 #endif
157
158 #ifndef BIT0
159 #define BIT0 0x00000001
160 #endif
161 #ifndef BIT1
162 #define BIT1 0x00000002
163 #endif
164 #ifndef BIT2
165 #define BIT2 0x00000004
166 #endif
167 #ifndef BIT3
168 #define BIT3 0x00000008
169 #endif
170 #ifndef BIT4
171 #define BIT4 0x00000010
172 #endif
173 #ifndef BIT5
174 #define BIT5 0x00000020
175 #endif
176 #ifndef BIT6
177 #define BIT6 0x00000040
178 #endif
179 #ifndef BIT7
180 #define BIT7 0x00000080
181 #endif
182 #ifndef BIT8
183 #define BIT8 0x00000100
184 #endif
185 #ifndef BIT9
186 #define BIT9 0x00000200
187 #endif
188 #ifndef BIT10
189 #define BIT10 0x00000400
190 #endif
191 #ifndef BIT11
192 #define BIT11 0x00000800
193 #endif
194 #ifndef BIT12
195 #define BIT12 0x00001000
196 #endif
197 #ifndef BIT13
198 #define BIT13 0x00002000
199 #endif
200 #ifndef BIT14
201 #define BIT14 0x00004000
202 #endif
203 #ifndef BIT15
204 #define BIT15 0x00008000
205 #endif
206 #ifndef BIT16
207 #define BIT16 0x00010000
208 #endif
209 #ifndef BIT17
210 #define BIT17 0x00020000
211 #endif
212 #ifndef BIT18
213 #define BIT18 0x00040000
214 #endif
215 #ifndef BIT19
216 #define BIT19 0x00080000
217 #endif
218 #ifndef BIT20
219 #define BIT20 0x00100000
220 #endif
221 #ifndef BIT21
222 #define BIT21 0x00200000
223 #endif
224 #ifndef BIT22
225 #define BIT22 0x00400000
226 #endif
227 #ifndef BIT23
228 #define BIT23 0x00800000
229 #endif
230 #ifndef BIT24
231 #define BIT24 0x01000000
232 #endif
233 #ifndef BIT25
234 #define BIT25 0x02000000
235 #endif
236 #ifndef BIT26
237 #define BIT26 0x04000000
238 #endif
239 #ifndef BIT27
240 #define BIT27 0x08000000
241 #endif
242 #ifndef BIT28
243 #define BIT28 0x10000000
244 #endif
245 #ifndef BIT29
246 #define BIT29 0x20000000
247 #endif
248 #ifndef BIT30
249 #define BIT30 0x40000000
250 #endif
251 #ifndef BIT31
252 #define BIT31 0x80000000
253 #endif
254 #pragma pack(1)
255 /**
256 Making any setup structure change after code frozen
257 will need to maintain backward compatibility, bump up
258 structure revision and update below history table\n
259 <b>Revision 1</b>: - Initial version.
260 <b>Revision 2</b>: - Added PepVmd
261 <b>Revision 3</b>: - Added CnvExtClock
262 <b>Revision 4</b>: - Added PPAG support
263 <b>Revision 5</b>: - Added FlashMode
264 <b>Revision 6</b>: - Cpu Pciexpress Gen3 Compatability
265 <b>Revision 7</b>: - Added DeepestUSBSleepWakeCapability
266 <b>Revision 8</b>: - Add PEP constraint support on SATA ports
267 <b>Revision 9</b>: - Added PepHeci3
268 <b>Revision 10</b>: - Added 11ax R2 support and UHB channel support
269 <b>Revision 11</b>: - Deprecate IccPllShutdownEnabled
270 <b>Revision 12</b>: - Deprecated TR A0 workaround setup options
271 <b>Revision 13</b>: - Deprecated MipiCam_LanesClkDiv and Added MipiCam_Link(X)_LanesClkDiv for all 6(0-5) Links.
272 <b>Revision 14</b>: - Added Fan 2, Fan 3 and dGPU paticipant, AdlSAepBoard setup variable
273 <b>Revision 15</b>: - Added WiFi Time Average SAR support
274 <b>Revision 16</b>: - Added PLN support
275 <b>Revision 17</b>: - Deprecated TbtSkipPciOprom
276 <b>Revision 18</b>: - TcssPdPsOnEnable
277 <b>Revision 19</b>: - Adding PepPcieLan,PepPcieWlan,PepPcieGfx and PepPcieOther for PCIe root port constraint configuration.
278 <b>Revision 20</b>: - Adding AuxRailBudget
279 <b>Revision 21</b>: - Added CVF Support
280 <b>Revision 22</b>: - Deprecated CurrentSecurityMode, using EnablePcieTunnelingOverUsb4 to represent security level
281 <b>Revision 23</b>: - Added WiFi Time Average SAR support
282 <b>Revision 24</b>: - Added DTbt Off Method Delay optimization.
283 <b>Revision 25</b>: - Replace TbtVtdBaseSecurity with DisableTbtPcieTreeBme.
284 <b>Revision 26</b>: - Added StorageRtd3Support;
285 <b>Revision 27</b>: - Adding PMAX device settings
286 <b>Revision 28</b>: - Deprecated Gpio3ForcePwrDly
287 <b>Revision 29</b>: - Added MPdt Support
288 <b>Revision 30</b>: - Add DiscreteTbtPlatformConfigurationSupport Setup variable.
289 <b>Revision 31</b>: - Deprecated ITbtPcieTunnelingForUsb4
290 <b>Revision 32</b>: - Added DtbtCmSupport and Usb4CmMode
291 <b>Revision 33</b>: - Added PepUfs0 and PepUfs1
292 <b>Revision 34</b>: - Added TestEnableTcssCovTypeA[MAX_TCSS_USB3_PORTS] and TestDisableTcssPortUcxxSupport[10]
293 <b>Revision 35</b>: - Deprecated TbtUsbOn
294 <b>Revision 36</b>: - Depricated SecondConfigReworkOption.
295 <b>Revision 37</b>: - DpInExternalEn
296 <b>Revision 38</b>: - Deprecated TestEnableTcssCovTypeA[MAX_TCSS_USB3_PORTS].
297 <b>Revision 39</b>: - Added CpuBclkFreq, PegDmiClkFreq, and DccClkCtrl
298 <b>Revision 40</b>: - Added UsbcDataRoleSwapPlatformDisable
299 <b>Revision 41</b>: - Added TwoMapleRidgeBoard
300 <b>Revision 42</b>: - Added FlashID Support for link 0-5
301 <b>Revision 43</b>: - Added SerialIoTiming Parameters and PEP Constraint for I2C6 and I2C7
302 <b>Revision 44</b>: - Deprecated TwoMapleRidgeBoard add DTbtDpInSupport
303 <b>Revision 45</b>: - XmlCli Related Knobs are now removed and reserved bytes added for offset consistency
304 <b>Revision 46</b>: - Deprecated WPFC (WiFi Phy Filter Configuration)
305 <b>Revision 47</b>: - Added WwanTPer2ResDelayMs
306 <b>Revision 48</b>: - Added WwanOemSvid and WwanSvidTimeout
307 <b>Revision 49</b>: - Updated BT Tile to Rev 1 (Ring My PC)
308 <b>Revision 50</b>: - Added WifiRegulatoryConfigurations, WifiUartConfigurations, WifiUnii4 and WifiIndoorControl
309 <b>Revision 51</b>: - Added pep constraint support for EMMC
310 <b>Revision 52</b>: - Deprecated PPR interface for MipiCamera
311 <b>Revision 53</b>: - Deprecated SdCard D3 Cold Support
312 <b>Revision 54</b>: - Added WirelessCnvConfigDevice to enable/disable WCCD
313 <b>Revision 55</b>: - Add CurrentCpuBclkFreq, CurrentPegDmiClkFreq for DCC OC
314 <b>Revision 56</b>: - Added WLAN/WWAN Antenna Isolation support for WiFi
315 <b>Revision 57</b>: - Deprecated SGOM variables.
316 <b>Revision 58</b>: - Add WgdsWiFiSarDeltaGroup and more WgdsWifiSarDeltaGroup elements for WGDS revision 3
317 <b>Revisiom 59</b>: - RP08 Wake Rework Done
318 <b>Revision 60</b>: - Rp08 D3 cold Support
319 <b>Revision 61</b>: - Add WifiTASSelectionValue for RPL (WTSY revision 1)
320 <b>Revision 62</b>: - Added RplSAepBoard setup variable
321 <b>Revision 63</b>: - Added DMI Policies
322 **/
323
324 #define SETUP_DATA_REVISION 63
325
326 typedef struct {
327 UINT8 Revision;
328 UINT8 FastBoot;
329 UINT8 FastBootWdt;
330 UINT8 SkipHIIUpdate;
331 UINT8 ConInBehavior;
332 UINT8 DisplayBootMode;
333 UINT8 Numlock;
334 UINT8 InteractiveText;
335 UINT8 LazyConIn;
336 UINT8 VirtualKeyboard;
337 UINT8 FirmwareConfiguration;
338 UINT8 OpRomPost; // [Legacy] \ EFI Compatible
339 // General PCI Settings: [] - default
340 UINT8 PciLatency; //[32]\ 64 \ 96 \ 128 \ 160 \ 192 \ 224 \ 248
341 UINT8 AcpiAuto;
342 UINT8 AcpiSleepState;
343 UINT8 AcpiHibernate;
344 UINT8 AcpiTableRevision;
345 UINT8 PciExpNative;
346 UINT8 NativeAspmEnable;
347 UINT8 PtidSupport;
348 // AcpiDebug Setup Options
349 UINT8 AcpiDebug;
350 UINT32 AcpiDebugAddress;
351 UINT8 PciDelayOptimizationEcr;
352 // S5 RTC wakeup setup options
353 UINT8 WakeOnRTCS5;
354 UINT8 PeciAccessMethod;
355 UINT8 LowPowerS0Idle;
356 UINT8 PepCpu;
357 UINT8 PepGfx;
358 UINT8 PepSataContraints;
359 UINT8 PepUart;
360 UINT8 PepI2c0;
361 UINT8 PepI2c1;
362 UINT8 PepI2c2;
363 UINT8 PepI2c3;
364 UINT8 PepI2c4;
365 UINT8 PepI2c5;
366 UINT8 PepSpi;
367 UINT8 PepXhci;
368 UINT8 PepAudio;
369 UINT8 PepIpu;
370 UINT8 PepGna;
371 UINT8 PepCsme;
372 UINT8 PepGbe;
373 UINT8 PepThc0;
374 UINT8 PepThc1;
375 UINT8 PepTcss;
376 UINT8 CSNotifyEC;
377 UINT8 CSDebugLightEC;
378 UINT8 EcLowPowerMode;
379 UINT8 EcPeciModeUnsupport;
380 UINT8 EcPeciMode;
381 UINT8 EcDebugLed;
382 UINT8 ECBaseCsPwrPolicy;
383 UINT8 SensorStandby;
384 UINT8 PL1LimitCS;
385 UINT16 PL1LimitCSValue;
386 UINT8 TenSecondPowerButtonSupport;
387 UINT8 TenSecondPowerButtonEnable;
388 UINT8 LpitResidencyCounter;
389 UINT8 PseudoG3State;
390 // Reading SSDT table from file
391 UINT8 LoadSSDTFromFile;
392 //
393 // On Screen Branding
394 //
395 UINT16 OperatingSystem;
396 UINT16 OemBadgingBrand;
397 UINT8 BootFirstToShell;
398
399 UINT8 SensorHubType;
400 UINT8 DebugUsbUartSupport;
401 UINT8 DebugUsbUart;
402 UINT8 EfiNetworkSupport;
403 UINT8 Reserved; // Get rid of "EnableClockSpreadSpec"
404 UINT8 UsbSensorHub;
405
406 UINT8 HddAcousticPowerManagement;
407 UINT8 HddAcousticMode;
408
409 //
410 // Recovery Configuration
411 //
412 UINT8 IsRecoveryJumper;
413
414 //
415 // MipiCam sensor configuration menu
416 //
417 UINT8 MipiCam_ControlLogic0; // None/discrete/PMIC
418 UINT8 MipiCam_ControlLogic1; // None/discrete/PMIC
419 UINT8 MipiCam_ControlLogic2; // None/discrete/PMIC
420 UINT8 MipiCam_ControlLogic3; // None/discrete/PMIC
421 UINT8 MipiCam_ControlLogic4; // None/discrete/PMIC
422 UINT8 MipiCam_ControlLogic5; // None/discrete/PMIC
423
424 UINT8 MipiCam_Link0; // Enabled / Disabled
425 UINT8 MipiCam_Link1; // Enabled / Disabled
426 UINT8 MipiCam_Link2; // Enabled / Disabled
427 UINT8 MipiCam_Link3; // Enabled / Disabled
428 UINT8 MipiCam_Link4; // Enabled / Disabled
429 UINT8 MipiCam_Link5; // Enabled / Disabled
430
431 UINT8 MipiCam4Enable; // Enable 5th camera
432 UINT8 MipiCam5Enable; // Enable 6th camera
433
434 UINT8 MipiCam_LanesClkDiv; // This member is deprecated and should be deleted in next generation
435
436 UINT8 MipiCam_ControlLogic0_Type;
437 UINT8 MipiCam_ControlLogic0_CrdVersion;
438 UINT32 MipiCam_ControlLogic0_InputClock;
439 UINT8 MipiCam_ControlLogic0_PchClockSource;
440 UINT8 MipiCam_ControlLogic0_GpioPinsEnabled;
441 UINT8 MipiCam_ControlLogic0_I2cChannel;
442 UINT16 MipiCam_ControlLogic0_I2cAddress;
443 UINT8 MipiCam_ControlLogic0_Pld;
444 UINT8 MipiCam_ControlLogic0_Wled1FlashMaxCurrent;
445 UINT8 MipiCam_ControlLogic0_Wled1TorchMaxCurrent;
446 UINT8 MipiCam_ControlLogic0_Wled2FlashMaxCurrent;
447 UINT8 MipiCam_ControlLogic0_Wled2TorchMaxCurrent;
448 UINT8 MipiCam_ControlLogic0_SubPlatformId;
449 UINT8 MipiCam_ControlLogic0_Wled1Type;
450 UINT8 MipiCam_ControlLogic0_Wled2Type;
451 UINT8 MipiCam_ControlLogic0_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
452 UINT8 MipiCam_ControlLogic0_GpioGroupNumber[MIPICAM_GPIO_COUNT];
453 UINT8 MipiCam_ControlLogic0_GpioFunction[MIPICAM_GPIO_COUNT];
454 UINT8 MipiCam_ControlLogic0_GpioActiveValue[MIPICAM_GPIO_COUNT];
455 UINT8 MipiCam_ControlLogic0_GpioInitialValue[MIPICAM_GPIO_COUNT];
456
457 UINT8 MipiCam_ControlLogic1_Type;
458 UINT8 MipiCam_ControlLogic1_CrdVersion;
459 UINT32 MipiCam_ControlLogic1_InputClock;
460 UINT8 MipiCam_ControlLogic1_PchClockSource;
461 UINT8 MipiCam_ControlLogic1_GpioPinsEnabled;
462 UINT8 MipiCam_ControlLogic1_I2cChannel;
463 UINT16 MipiCam_ControlLogic1_I2cAddress;
464 UINT8 MipiCam_ControlLogic1_Pld;
465 UINT8 MipiCam_ControlLogic1_Wled1FlashMaxCurrent;
466 UINT8 MipiCam_ControlLogic1_Wled1TorchMaxCurrent;
467 UINT8 MipiCam_ControlLogic1_Wled2FlashMaxCurrent;
468 UINT8 MipiCam_ControlLogic1_Wled2TorchMaxCurrent;
469 UINT8 MipiCam_ControlLogic1_SubPlatformId;
470 UINT8 MipiCam_ControlLogic1_Wled1Type;
471 UINT8 MipiCam_ControlLogic1_Wled2Type;
472 UINT8 MipiCam_ControlLogic1_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
473 UINT8 MipiCam_ControlLogic1_GpioGroupNumber[MIPICAM_GPIO_COUNT];
474 UINT8 MipiCam_ControlLogic1_GpioFunction[MIPICAM_GPIO_COUNT];
475 UINT8 MipiCam_ControlLogic1_GpioActiveValue[MIPICAM_GPIO_COUNT];
476 UINT8 MipiCam_ControlLogic1_GpioInitialValue[MIPICAM_GPIO_COUNT];
477
478 UINT8 MipiCam_ControlLogic2_Type;
479 UINT8 MipiCam_ControlLogic2_CrdVersion;
480 UINT32 MipiCam_ControlLogic2_InputClock;
481 UINT8 MipiCam_ControlLogic2_PchClockSource;
482 UINT8 MipiCam_ControlLogic2_GpioPinsEnabled;
483 UINT8 MipiCam_ControlLogic2_I2cChannel;
484 UINT16 MipiCam_ControlLogic2_I2cAddress;
485 UINT8 MipiCam_ControlLogic2_Pld;
486 UINT8 MipiCam_ControlLogic2_Wled1FlashMaxCurrent;
487 UINT8 MipiCam_ControlLogic2_Wled1TorchMaxCurrent;
488 UINT8 MipiCam_ControlLogic2_Wled2FlashMaxCurrent;
489 UINT8 MipiCam_ControlLogic2_Wled2TorchMaxCurrent;
490 UINT8 MipiCam_ControlLogic2_SubPlatformId;
491 UINT8 MipiCam_ControlLogic2_Wled1Type;
492 UINT8 MipiCam_ControlLogic2_Wled2Type;
493 UINT8 MipiCam_ControlLogic2_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
494 UINT8 MipiCam_ControlLogic2_GpioGroupNumber[MIPICAM_GPIO_COUNT];
495 UINT8 MipiCam_ControlLogic2_GpioFunction[MIPICAM_GPIO_COUNT];
496 UINT8 MipiCam_ControlLogic2_GpioActiveValue[MIPICAM_GPIO_COUNT];
497 UINT8 MipiCam_ControlLogic2_GpioInitialValue[MIPICAM_GPIO_COUNT];
498
499 UINT8 MipiCam_ControlLogic3_Type;
500 UINT8 MipiCam_ControlLogic3_CrdVersion;
501 UINT32 MipiCam_ControlLogic3_InputClock;
502 UINT8 MipiCam_ControlLogic3_PchClockSource;
503 UINT8 MipiCam_ControlLogic3_GpioPinsEnabled;
504 UINT8 MipiCam_ControlLogic3_I2cChannel;
505 UINT16 MipiCam_ControlLogic3_I2cAddress;
506 UINT8 MipiCam_ControlLogic3_Pld;
507 UINT8 MipiCam_ControlLogic3_Wled1FlashMaxCurrent;
508 UINT8 MipiCam_ControlLogic3_Wled1TorchMaxCurrent;
509 UINT8 MipiCam_ControlLogic3_Wled2FlashMaxCurrent;
510 UINT8 MipiCam_ControlLogic3_Wled2TorchMaxCurrent;
511 UINT8 MipiCam_ControlLogic3_SubPlatformId;
512 UINT8 MipiCam_ControlLogic3_Wled1Type;
513 UINT8 MipiCam_ControlLogic3_Wled2Type;
514 UINT8 MipiCam_ControlLogic3_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
515 UINT8 MipiCam_ControlLogic3_GpioGroupNumber[MIPICAM_GPIO_COUNT];
516 UINT8 MipiCam_ControlLogic3_GpioFunction[MIPICAM_GPIO_COUNT];
517 UINT8 MipiCam_ControlLogic3_GpioActiveValue[MIPICAM_GPIO_COUNT];
518 UINT8 MipiCam_ControlLogic3_GpioInitialValue[MIPICAM_GPIO_COUNT];
519
520 UINT8 MipiCam_ControlLogic4_Type;
521 UINT8 MipiCam_ControlLogic4_CrdVersion;
522 UINT32 MipiCam_ControlLogic4_InputClock;
523 UINT8 MipiCam_ControlLogic4_PchClockSource;
524 UINT8 MipiCam_ControlLogic4_GpioPinsEnabled;
525 UINT8 MipiCam_ControlLogic4_I2cChannel;
526 UINT16 MipiCam_ControlLogic4_I2cAddress;
527 UINT8 MipiCam_ControlLogic4_Pld;
528 UINT8 MipiCam_ControlLogic4_Wled1FlashMaxCurrent;
529 UINT8 MipiCam_ControlLogic4_Wled1TorchMaxCurrent;
530 UINT8 MipiCam_ControlLogic4_Wled2FlashMaxCurrent;
531 UINT8 MipiCam_ControlLogic4_Wled2TorchMaxCurrent;
532 UINT8 MipiCam_ControlLogic4_SubPlatformId;
533 UINT8 MipiCam_ControlLogic4_Wled1Type;
534 UINT8 MipiCam_ControlLogic4_Wled2Type;
535 UINT8 MipiCam_ControlLogic4_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
536 UINT8 MipiCam_ControlLogic4_GpioGroupNumber[MIPICAM_GPIO_COUNT];
537 UINT8 MipiCam_ControlLogic4_GpioFunction[MIPICAM_GPIO_COUNT];
538 UINT8 MipiCam_ControlLogic4_GpioActiveValue[MIPICAM_GPIO_COUNT];
539 UINT8 MipiCam_ControlLogic4_GpioInitialValue[MIPICAM_GPIO_COUNT];
540
541 UINT8 MipiCam_ControlLogic5_Type;
542 UINT8 MipiCam_ControlLogic5_CrdVersion;
543 UINT32 MipiCam_ControlLogic5_InputClock;
544 UINT8 MipiCam_ControlLogic5_PchClockSource;
545 UINT8 MipiCam_ControlLogic5_GpioPinsEnabled;
546 UINT8 MipiCam_ControlLogic5_I2cChannel;
547 UINT16 MipiCam_ControlLogic5_I2cAddress;
548 UINT8 MipiCam_ControlLogic5_Pld;
549 UINT8 MipiCam_ControlLogic5_Wled1FlashMaxCurrent;
550 UINT8 MipiCam_ControlLogic5_Wled1TorchMaxCurrent;
551 UINT8 MipiCam_ControlLogic5_Wled2FlashMaxCurrent;
552 UINT8 MipiCam_ControlLogic5_Wled2TorchMaxCurrent;
553 UINT8 MipiCam_ControlLogic5_SubPlatformId;
554 UINT8 MipiCam_ControlLogic5_Wled1Type;
555 UINT8 MipiCam_ControlLogic5_Wled2Type;
556 UINT8 MipiCam_ControlLogic5_GpioGroupPadNumber[MIPICAM_GPIO_COUNT];
557 UINT8 MipiCam_ControlLogic5_GpioGroupNumber[MIPICAM_GPIO_COUNT];
558 UINT8 MipiCam_ControlLogic5_GpioFunction[MIPICAM_GPIO_COUNT];
559 UINT8 MipiCam_ControlLogic5_GpioActiveValue[MIPICAM_GPIO_COUNT];
560 UINT8 MipiCam_ControlLogic5_GpioInitialValue[MIPICAM_GPIO_COUNT];
561
562 UINT8 MipiCam_Link0_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User0
563 UINT16 MipiCam_Link0_UserHid[MIPICAM_HID_LENGTH];
564 UINT8 MipiCam_Link0_CameraPhysicalLocation;
565 UINT16 MipiCam_Link0_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
566 UINT8 MipiCam_Link0_I2cDevicesEnabled; // number of I2C devices defined for this link
567 UINT8 MipiCam_Link0_I2cChannel;
568 UINT16 MipiCam_Link0_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
569 UINT8 MipiCam_Link0_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
570 UINT8 MipiCam_Link0_DriverData_Version;
571 UINT8 MipiCam_Link0_DriverData_CrdVersion;
572 UINT8 MipiCam_Link0_DriverData_LinkUsed;
573 UINT8 MipiCam_Link0_DriverData_LaneUsed;
574 UINT8 MipiCam_Link0_DriverData_CsiSpeed;
575 UINT8 MipiCam_Link0_DriverData_EepromType;
576 UINT8 MipiCam_Link0_DriverData_VcmType;
577 UINT8 MipiCam_Link0_DriverData_CustomData[4];
578 UINT32 MipiCam_Link0_DriverData_Mclk;
579 UINT8 MipiCam_Link0_DriverData_ControlLogic;
580 UINT8 MipiCam_Link0_DriverData_FlashSupport;
581 UINT8 MipiCam_Link0_DriverData_PrivacyLed;
582 UINT8 MipiCam_Link0_DriverData_Degree;
583 UINT8 MipiCam_Link0_DriverData_PmicPosition;
584 UINT8 MipiCam_Link0_DriverData_VoltageRail;
585 UINT8 MipiCam_Link0_DriverData_PprValue; // Deprecated from Revision 52
586 UINT8 MipiCam_Link0_DriverData_PprUnit; // Deprecated from Revision 52
587 UINT8 MipiCam_Link0_FlashDriverSelection;
588
589 UINT8 MipiCam_Link1_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User1
590 UINT16 MipiCam_Link1_UserHid[MIPICAM_HID_LENGTH];
591 UINT8 MipiCam_Link1_CameraPhysicalLocation;
592 UINT16 MipiCam_Link1_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
593 UINT8 MipiCam_Link1_I2cDevicesEnabled; // number of I2C devices defined for this link
594 UINT8 MipiCam_Link1_I2cChannel;
595 UINT16 MipiCam_Link1_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
596 UINT8 MipiCam_Link1_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
597 UINT8 MipiCam_Link1_DriverData_Version;
598 UINT8 MipiCam_Link1_DriverData_LinkUsed;
599 UINT8 MipiCam_Link1_DriverData_CrdVersion;
600 UINT8 MipiCam_Link1_DriverData_LaneUsed;
601 UINT8 MipiCam_Link1_DriverData_CsiSpeed;
602 UINT8 MipiCam_Link1_DriverData_EepromType;
603 UINT8 MipiCam_Link1_DriverData_VcmType;
604 UINT8 MipiCam_Link1_DriverData_CustomData[4];
605 UINT32 MipiCam_Link1_DriverData_Mclk;
606 UINT8 MipiCam_Link1_DriverData_ControlLogic;
607 UINT8 MipiCam_Link1_DriverData_FlashSupport;
608 UINT8 MipiCam_Link1_DriverData_PrivacyLed;
609 UINT8 MipiCam_Link1_DriverData_Degree;
610 UINT8 MipiCam_Link1_DriverData_PmicPosition;
611 UINT8 MipiCam_Link1_DriverData_VoltageRail;
612 UINT8 MipiCam_Link1_DriverData_PprValue; // Deprecated from Revision 52
613 UINT8 MipiCam_Link1_DriverData_PprUnit; // Deprecated from Revision 52
614 UINT8 MipiCam_Link1_FlashDriverSelection;
615
616 UINT8 MipiCam_Link2_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User2
617 UINT16 MipiCam_Link2_UserHid[MIPICAM_HID_LENGTH];
618 UINT8 MipiCam_Link2_CameraPhysicalLocation;
619 UINT16 MipiCam_Link2_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
620 UINT8 MipiCam_Link2_I2cDevicesEnabled; // number of I2C devices defined for this link
621 UINT8 MipiCam_Link2_I2cChannel;
622 UINT16 MipiCam_Link2_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
623 UINT8 MipiCam_Link2_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
624 UINT8 MipiCam_Link2_DriverData_Version;
625 UINT8 MipiCam_Link2_DriverData_CrdVersion;
626 UINT8 MipiCam_Link2_DriverData_LinkUsed;
627 UINT8 MipiCam_Link2_DriverData_LaneUsed;
628 UINT8 MipiCam_Link2_DriverData_CsiSpeed;
629 UINT8 MipiCam_Link2_DriverData_EepromType;
630 UINT8 MipiCam_Link2_DriverData_VcmType;
631 UINT8 MipiCam_Link2_DriverData_CustomData[4];
632 UINT32 MipiCam_Link2_DriverData_Mclk;
633 UINT8 MipiCam_Link2_DriverData_ControlLogic;
634 UINT8 MipiCam_Link2_DriverData_FlashSupport;
635 UINT8 MipiCam_Link2_DriverData_PrivacyLed;
636 UINT8 MipiCam_Link2_DriverData_Degree;
637 UINT8 MipiCam_Link2_DriverData_PmicPosition;
638 UINT8 MipiCam_Link2_DriverData_VoltageRail;
639 UINT8 MipiCam_Link2_DriverData_PprValue; // Deprecated from Revision 52
640 UINT8 MipiCam_Link2_DriverData_PprUnit; // Deprecated from Revision 52
641 UINT8 MipiCam_Link2_FlashDriverSelection;
642
643 UINT8 MipiCam_Link3_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User3
644 UINT16 MipiCam_Link3_UserHid[MIPICAM_HID_LENGTH];
645 UINT8 MipiCam_Link3_CameraPhysicalLocation;
646 UINT16 MipiCam_Link3_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
647 UINT8 MipiCam_Link3_I2cDevicesEnabled; // number of I2C devices defined for this link
648 UINT8 MipiCam_Link3_I2cChannel;
649 UINT16 MipiCam_Link3_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
650 UINT8 MipiCam_Link3_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
651 UINT8 MipiCam_Link3_DriverData_Version;
652 UINT8 MipiCam_Link3_DriverData_CrdVersion;
653 UINT8 MipiCam_Link3_DriverData_LinkUsed;
654 UINT8 MipiCam_Link3_DriverData_LaneUsed;
655 UINT8 MipiCam_Link3_DriverData_CsiSpeed;
656 UINT8 MipiCam_Link3_DriverData_EepromType;
657 UINT8 MipiCam_Link3_DriverData_VcmType;
658 UINT8 MipiCam_Link3_DriverData_CustomData[4];
659 UINT32 MipiCam_Link3_DriverData_Mclk;
660 UINT8 MipiCam_Link3_DriverData_ControlLogic;
661 UINT8 MipiCam_Link3_DriverData_FlashSupport;
662 UINT8 MipiCam_Link3_DriverData_PrivacyLed;
663 UINT8 MipiCam_Link3_DriverData_Degree;
664 UINT8 MipiCam_Link3_DriverData_PmicPosition;
665 UINT8 MipiCam_Link3_DriverData_VoltageRail;
666 UINT8 MipiCam_Link3_DriverData_PprValue; // Deprecated from Revision 52
667 UINT8 MipiCam_Link3_DriverData_PprUnit; // Deprecated from Revision 52
668 UINT8 MipiCam_Link3_FlashDriverSelection;
669
670 UINT8 MipiCam_Link4_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User3
671 UINT16 MipiCam_Link4_UserHid[MIPICAM_HID_LENGTH];
672 UINT8 MipiCam_Link4_CameraPhysicalLocation;
673 UINT16 MipiCam_Link4_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
674 UINT8 MipiCam_Link4_I2cDevicesEnabled; // number of I2C devices defined for this link
675 UINT8 MipiCam_Link4_I2cChannel;
676 UINT16 MipiCam_Link4_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
677 UINT8 MipiCam_Link4_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
678 UINT8 MipiCam_Link4_DriverData_Version;
679 UINT8 MipiCam_Link4_DriverData_CrdVersion;
680 UINT8 MipiCam_Link4_DriverData_LinkUsed;
681 UINT8 MipiCam_Link4_DriverData_LaneUsed;
682 UINT8 MipiCam_Link4_DriverData_CsiSpeed;
683 UINT8 MipiCam_Link4_DriverData_EepromType;
684 UINT8 MipiCam_Link4_DriverData_VcmType;
685 UINT8 MipiCam_Link4_DriverData_CustomData[4];
686 UINT32 MipiCam_Link4_DriverData_Mclk;
687 UINT8 MipiCam_Link4_DriverData_ControlLogic;
688 UINT8 MipiCam_Link4_DriverData_FlashSupport;
689 UINT8 MipiCam_Link4_DriverData_PrivacyLed;
690 UINT8 MipiCam_Link4_DriverData_Degree;
691 UINT8 MipiCam_Link4_DriverData_PmicPosition;
692 UINT8 MipiCam_Link4_DriverData_VoltageRail;
693 UINT8 MipiCam_Link4_DriverData_PprValue; // Deprecated from Revision 52
694 UINT8 MipiCam_Link4_DriverData_PprUnit; // Deprecated from Revision 52
695 UINT8 MipiCam_Link4_FlashDriverSelection;
696
697 UINT8 MipiCam_Link5_SensorModel; // IMX135 / OV5693 / IMX179 / OV8858 / OV2740-IVCAM / IMX208 / OV9728 / IMX188 / User3
698 UINT16 MipiCam_Link5_UserHid[MIPICAM_HID_LENGTH];
699 UINT8 MipiCam_Link5_CameraPhysicalLocation;
700 UINT16 MipiCam_Link5_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
701 UINT8 MipiCam_Link5_I2cDevicesEnabled; // number of I2C devices defined for this link
702 UINT8 MipiCam_Link5_I2cChannel;
703 UINT16 MipiCam_Link5_I2cAddress[MIPICAM_I2C_DEVICES_COUNT];
704 UINT8 MipiCam_Link5_I2cDeviceType[MIPICAM_I2C_DEVICES_COUNT];
705 UINT8 MipiCam_Link5_DriverData_Version;
706 UINT8 MipiCam_Link5_DriverData_CrdVersion;
707 UINT8 MipiCam_Link5_DriverData_LinkUsed;
708 UINT8 MipiCam_Link5_DriverData_LaneUsed;
709 UINT8 MipiCam_Link5_DriverData_CsiSpeed;
710 UINT8 MipiCam_Link5_DriverData_EepromType;
711 UINT8 MipiCam_Link5_DriverData_VcmType;
712 UINT8 MipiCam_Link5_DriverData_CustomData[4];
713 UINT32 MipiCam_Link5_DriverData_Mclk;
714 UINT8 MipiCam_Link5_DriverData_ControlLogic;
715 UINT8 MipiCam_Link5_DriverData_FlashSupport;
716 UINT8 MipiCam_Link5_DriverData_PrivacyLed;
717 UINT8 MipiCam_Link5_DriverData_Degree;
718 UINT8 MipiCam_Link5_DriverData_PmicPosition;
719 UINT8 MipiCam_Link5_DriverData_VoltageRail;
720 UINT8 MipiCam_Link5_DriverData_PprValue; // Deprecated from Revision 52
721 UINT8 MipiCam_Link5_DriverData_PprUnit; // Deprecated from Revision 52
722 UINT8 MipiCam_Link5_FlashDriverSelection;
723
724 UINT8 MipiCam_Flash0_Model; // LM3643 / Internal PMIC - WRC
725 UINT16 MipiCam_Flash0_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
726 UINT8 MipiCam_Flash0_I2cChannel;
727 UINT16 MipiCam_Flash0_I2cAddress;
728 UINT8 MipiCam_Flash0_GpioGroupPadNumber;
729 UINT16 MipiCam_Flash0_GpioGroupNumber;
730 UINT8 MipiCam_Flash0_GpioActiveValue;
731 UINT8 MipiCam_Flash0_GpioInitialValue;
732 UINT8 MipiCam_Flash0_OperatingMode;
733
734 UINT8 MipiCam_Flash1_Model; // LM3643 / Internal PMIC - WRC
735 UINT16 MipiCam_Flash1_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
736 UINT8 MipiCam_Flash1_I2cChannel;
737 UINT16 MipiCam_Flash1_I2cAddress;
738 UINT8 MipiCam_Flash1_GpioGroupPadNumber;
739 UINT16 MipiCam_Flash1_GpioGroupNumber;
740 UINT8 MipiCam_Flash1_GpioActiveValue;
741 UINT8 MipiCam_Flash1_GpioInitialValue;
742 UINT8 MipiCam_Flash1_OperatingMode;
743
744 UINT8 MipiCam_Flash2_Model; // LM3643 / Internal PMIC - WRC
745 UINT16 MipiCam_Flash2_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
746 UINT8 MipiCam_Flash2_I2cChannel;
747 UINT16 MipiCam_Flash2_I2cAddress;
748 UINT8 MipiCam_Flash2_GpioGroupPadNumber;
749 UINT16 MipiCam_Flash2_GpioGroupNumber;
750 UINT8 MipiCam_Flash2_GpioActiveValue;
751 UINT8 MipiCam_Flash2_GpioInitialValue;
752 UINT8 MipiCam_Flash2_OperatingMode;
753
754 UINT8 MipiCam_Flash3_Model; // LM3643 / Internal PMIC - WRC
755 UINT16 MipiCam_Flash3_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
756 UINT8 MipiCam_Flash3_I2cChannel;
757 UINT16 MipiCam_Flash3_I2cAddress;
758 UINT8 MipiCam_Flash3_GpioGroupPadNumber;
759 UINT16 MipiCam_Flash3_GpioGroupNumber;
760 UINT8 MipiCam_Flash3_GpioActiveValue;
761 UINT8 MipiCam_Flash3_GpioInitialValue;
762 UINT8 MipiCam_Flash3_OperatingMode;
763
764 UINT8 MipiCam_Flash4_Model; // LM3643 / Internal PMIC - WRC
765 UINT16 MipiCam_Flash4_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
766 UINT8 MipiCam_Flash4_I2cChannel;
767 UINT16 MipiCam_Flash4_I2cAddress;
768 UINT8 MipiCam_Flash4_GpioGroupPadNumber;
769 UINT16 MipiCam_Flash4_GpioGroupNumber;
770 UINT8 MipiCam_Flash4_GpioActiveValue;
771 UINT8 MipiCam_Flash4_GpioInitialValue;
772 UINT8 MipiCam_Flash4_OperatingMode;
773
774 UINT8 MipiCam_Flash5_Model; // LM3643 / Internal PMIC - WRC
775 UINT16 MipiCam_Flash5_ModuleName[MIPICAM_MODULE_NAME_LENGTH];
776 UINT8 MipiCam_Flash5_I2cChannel;
777 UINT16 MipiCam_Flash5_I2cAddress;
778 UINT8 MipiCam_Flash5_GpioGroupPadNumber;
779 UINT16 MipiCam_Flash5_GpioGroupNumber;
780 UINT8 MipiCam_Flash5_GpioActiveValue;
781 UINT8 MipiCam_Flash5_GpioInitialValue;
782 UINT8 MipiCam_Flash5_OperatingMode;
783
784 UINT8 PchI2cSensorDevicePort[PCH_MAX_SERIALIO_I2C_CONTROLLERS];
785
786 UINT8 PchI2cTouchPadType;
787 UINT8 PchI2cTouchPadIrqMode;
788 UINT8 PchI2cTouchPadBusAddress;
789 UINT16 PchI2cTouchPadHidAddress;
790 UINT8 PchI2cTouchPadSpeed;
791
792 UINT8 PchI2cTouchPanelType;
793 UINT8 PchI2cTouchPanelIrqMode;
794 UINT8 PchI2cTouchPanelBusAddress;
795 UINT16 PchI2cTouchPanelHidAddress;
796 UINT8 PchI2cTouchPanelSpeed;
797
798 UINT8 PchSpiSensorDevicePort[PCH_MAX_SERIALIO_SPI_CONTROLLERS];
799 UINT8 PchSpiFingerPrintType;
800 UINT8 PchSpiSensorIrqMode;
801
802 UINT8 PchUart1SensorDevice;
803 UINT8 PchUart2SensorDevice;
804 UINT8 PchI2cWittDevice;
805 UINT8 PchI2cWittVersion;
806 UINT8 PchUartUtkDevice;
807 UINT8 DiscreteBtModule;
808 UINT8 DiscreteBtModuleIrqMode;
809
810 UINT8 PchSerialIoUseTimingParameters;
811
812 UINT16 PchSerialIoTimingSSH0; // [SSH0] SSCN-HIGH for I2C0
813 UINT16 PchSerialIoTimingSSL0; // [SSL0] SSCN-LOW for I2C0
814 UINT16 PchSerialIoTimingSSD0; // [SSD0] SSCN-HOLD for I2C0
815 UINT16 PchSerialIoTimingFMH0; // [FMH0] FMCN-HIGH for I2C0
816 UINT16 PchSerialIoTimingFML0; // [FML0] FMCN-LOW for I2C0
817 UINT16 PchSerialIoTimingFMD0; // [FMD0] FMCN-HOLD for I2C0
818 UINT16 PchSerialIoTimingFPH0; // [FPH0] FPCN-HIGH for I2C0
819 UINT16 PchSerialIoTimingFPL0; // [FPL0] FPCN-LOW for I2C0
820 UINT16 PchSerialIoTimingFPD0; // [FPD0] FPCN-HOLD for I2C0
821 UINT16 PchSerialIoTimingHSH0; // [HSH0] HSCN-HIGH for I2C0
822 UINT16 PchSerialIoTimingHSL0; // [HSL0] HSCN-LOW for I2C0
823 UINT16 PchSerialIoTimingHSD0; // [HSD0] HSCN-HOLD for I2C0
824
825 UINT16 PchSerialIoTimingSSH1; // [SSH1] SSCN-HIGH for I2C1
826 UINT16 PchSerialIoTimingSSL1; // [SSL1] SSCN-LOW for I2C1
827 UINT16 PchSerialIoTimingSSD1; // [SSD1] SSCN-HOLD for I2C1
828 UINT16 PchSerialIoTimingFMH1; // [FMH1] FMCN-HIGH for I2C1
829 UINT16 PchSerialIoTimingFML1; // [FML1] FMCN-LOW for I2C1
830 UINT16 PchSerialIoTimingFMD1; // [FMD1] FMCN-HOLD for I2C1
831 UINT16 PchSerialIoTimingFPH1; // [FPH1] FPCN-HIGH for I2C1
832 UINT16 PchSerialIoTimingFPL1; // [FPL1] FPCN-LOW for I2C1
833 UINT16 PchSerialIoTimingFPD1; // [FPD1] FPCN-HOLD for I2C1
834 UINT16 PchSerialIoTimingHSH1; // [HSH1] HSCN-HIGH for I2C1
835 UINT16 PchSerialIoTimingHSL1; // [HSL1] HSCN-LOW for I2C1
836 UINT16 PchSerialIoTimingHSD1; // [HSD1] HSCN-HOLD for I2C1
837
838 UINT16 PchSerialIoTimingSSH2; // [SSH2] SSCN-HIGH for I2C2
839 UINT16 PchSerialIoTimingSSL2; // [SSL2] SSCN-LOW for I2C2
840 UINT16 PchSerialIoTimingSSD2; // [SSD2] SSCN-HOLD for I2C2
841 UINT16 PchSerialIoTimingFMH2; // [FMH2] FMCN-HIGH for I2C2
842 UINT16 PchSerialIoTimingFML2; // [FML2] FMCN-LOW for I2C2
843 UINT16 PchSerialIoTimingFMD2; // [FMD2] FMCN-HOLD for I2C2
844 UINT16 PchSerialIoTimingFPH2; // [FPH2] FPCN-HIGH for I2C2
845 UINT16 PchSerialIoTimingFPL2; // [FPL2] FPCN-LOW for I2C2
846 UINT16 PchSerialIoTimingFPD2; // [FPD2] FPCN-HOLD for I2C2
847 UINT16 PchSerialIoTimingHSH2; // [HSH2] HSCN-HIGH for I2C2
848 UINT16 PchSerialIoTimingHSL2; // [HSL2] HSCN-LOW for I2C2
849 UINT16 PchSerialIoTimingHSD2; // [HSD2] HSCN-HOLD for I2C2
850
851 UINT16 PchSerialIoTimingSSH3; // [SSH3] SSCN-HIGH for I2C3
852 UINT16 PchSerialIoTimingSSL3; // [SSL3] SSCN-LOW for I2C3
853 UINT16 PchSerialIoTimingSSD3; // [SSD3] SSCN-HOLD for I2C3
854 UINT16 PchSerialIoTimingFMH3; // [FMH3] FMCN-HIGH for I2C3
855 UINT16 PchSerialIoTimingFML3; // [FML3] FMCN-LOW for I2C3
856 UINT16 PchSerialIoTimingFMD3; // [FMD3] FMCN-HOLD for I2C3
857 UINT16 PchSerialIoTimingFPH3; // [FPH3] FPCN-HIGH for I2C3
858 UINT16 PchSerialIoTimingFPL3; // [FPL3] FPCN-LOW for I2C3
859 UINT16 PchSerialIoTimingFPD3; // [FPD3] FPCN-HOLD for I2C3
860 UINT16 PchSerialIoTimingHSH3; // [HSH3] HSCN-HIGH for I2C3
861 UINT16 PchSerialIoTimingHSL3; // [HSL3] HSCN-LOW for I2C3
862 UINT16 PchSerialIoTimingHSD3; // [HSD3] HSCN-HOLD for I2C3
863
864 UINT16 PchSerialIoTimingSSH4; // [SSH4] SSCN-HIGH for I2C4
865 UINT16 PchSerialIoTimingSSL4; // [SSL4] SSCN-LOW for I2C4
866 UINT16 PchSerialIoTimingSSD4; // [SSD4] SSCN-HOLD for I2C4
867 UINT16 PchSerialIoTimingFMH4; // [FMH4] FMCN-HIGH for I2C4
868 UINT16 PchSerialIoTimingFML4; // [FML4] FMCN-LOW for I2C4
869 UINT16 PchSerialIoTimingFMD4; // [FMD4] FMCN-HOLD for I2C4
870 UINT16 PchSerialIoTimingFPH4; // [FPH4] FPCN-HIGH for I2C4
871 UINT16 PchSerialIoTimingFPL4; // [FPL4] FPCN-LOW for I2C4
872 UINT16 PchSerialIoTimingFPD4; // [FPD4] FPCN-HOLD for I2C4
873 UINT16 PchSerialIoTimingHSH4; // [HSH4] HSCN-HIGH for I2C4
874 UINT16 PchSerialIoTimingHSL4; // [HSL4] HSCN-LOW for I2C4
875 UINT16 PchSerialIoTimingHSD4; // [HSD4] HSCN-HOLD for I2C4
876
877 UINT16 PchSerialIoTimingSSH5; // [SSH5] SSCN-HIGH for I2C5
878 UINT16 PchSerialIoTimingSSL5; // [SSL5] SSCN-LOW for I2C5
879 UINT16 PchSerialIoTimingSSD5; // [SSD5] SSCN-HOLD for I2C5
880 UINT16 PchSerialIoTimingFMH5; // [FMH5] FMCN-HIGH for I2C5
881 UINT16 PchSerialIoTimingFML5; // [FML5] FMCN-LOW for I2C5
882 UINT16 PchSerialIoTimingFMD5; // [FMD5] FMCN-HOLD for I2C5
883 UINT16 PchSerialIoTimingFPH5; // [FPH5] FPCN-HIGH for I2C5
884 UINT16 PchSerialIoTimingFPL5; // [FPL5] FPCN-LOW for I2C5
885 UINT16 PchSerialIoTimingFPD5; // [FPD5] FPCN-HOLD for I2C5
886 UINT16 PchSerialIoTimingHSH5; // [HSH5] HSCN-HIGH for I2C5
887 UINT16 PchSerialIoTimingHSL5; // [HSL5] HSCN-LOW for I2C5
888 UINT16 PchSerialIoTimingHSD5; // [HSD5] HSCN-HOLD for I2C5
889
890 UINT16 PchSerialIoTimingM0C0; // [M0C0] M0D3 for I2C0
891 UINT16 PchSerialIoTimingM1C0; // [M1C0] M1D3 for I2C0
892 UINT16 PchSerialIoTimingM0C1; // [M0C1] M0D3 for I2C1
893 UINT16 PchSerialIoTimingM1C1; // [M1C1] M1D3 for I2C1
894 UINT16 PchSerialIoTimingM0C2; // [M0C2] M0D3 for I2C2
895 UINT16 PchSerialIoTimingM1C2; // [M1C2] M1D3 for I2C2
896 UINT16 PchSerialIoTimingM0C3; // [M0C3] M0D3 for I2C3
897 UINT16 PchSerialIoTimingM1C3; // [M1C3] M1D3 for I2C3
898 UINT16 PchSerialIoTimingM0C4; // [M0C4] M0D3 for I2C4
899 UINT16 PchSerialIoTimingM1C4; // [M1C4] M1D3 for I2C4
900 UINT16 PchSerialIoTimingM0C5; // [M0C5] M0D3 for I2C5
901 UINT16 PchSerialIoTimingM1C5; // [M1C5] M1D3 for I2C5
902 UINT16 PchSerialIoTimingM0C6; // [M0C6] M0D3 for SPI0
903 UINT16 PchSerialIoTimingM1C6; // [M1C6] M1D3 for SPI0
904 UINT16 PchSerialIoTimingM0C7; // [M0C7] M0D3 for SPI1
905 UINT16 PchSerialIoTimingM1C7; // [M1C7] M1D3 for SPI1
906 UINT16 PchSerialIoTimingM0C8; // [M0C8] M0D3 for SPI2
907 UINT16 PchSerialIoTimingM1C8; // [M1C8] M1D3 for SPI2
908 UINT16 PchSerialIoTimingM0C9; // [M0C9] M0D3 for UART0
909 UINT16 PchSerialIoTimingM1C9; // [M1C9] M1D3 for UART0
910 UINT16 PchSerialIoTimingM0CA; // [M0CA] M0D3 for UART1
911 UINT16 PchSerialIoTimingM1CA; // [M1CA] M1D3 for UART1
912 UINT16 PchSerialIoTimingM0CB; // [M0CB] M0D3 for UART2
913 UINT16 PchSerialIoTimingM1CB; // [M1CB] M1D3 for UART2
914
915 UINT8 Ps2KbMsEnable;
916 UINT8 TouchPanelMuxSelector;
917
918 UINT8 Ac1TripPoint;
919 UINT8 Ac0TripPoint;
920 UINT8 Ac1FanSpeed;
921 UINT8 Ac0FanSpeed;
922 UINT8 PassiveThermalTripPoint;
923 UINT8 CriticalThermalTripPoint;
924 UINT8 PassiveTc1Value;
925 UINT8 PassiveTc2Value;
926 UINT8 PassiveTspValue;
927 UINT8 DisableActiveTripPoints;
928 UINT8 DisablePassiveTripPoints;
929 UINT8 DisableCriticalTripPoints;
930 UINT8 PmicVccLevel;
931 UINT8 PmicVddqLevel;
932 UINT8 TwoComponents;
933 UINT8 CrcPmicNvmUpdateEnable;
934 UINT8 CrcPmicCustomizationNvmUpdateEnable;
935 UINT8 PmicNvmWriteLockEnable;
936
937 UINT8 CPUTempReadEnable;
938 UINT8 CPUEnergyReadEnable;
939 UINT8 PCHTempReadEnable;
940 UINT8 AlertEnableLock;
941 UINT8 PchAlert;
942 UINT8 DimmAlert;
943 UINT8 CpuTemp;
944 UINT8 CpuFanSpeed;
945
946 //
947 // Intel(R) Dynamic Tuning Technology SETUP items begin
948 //
949 UINT8 EnableDptf;
950 UINT8 EnableDCFG;
951
952 UINT8 EnableSaDevice;
953 UINT32 PpccStepSize;
954
955 UINT8 DetectEcFan[MAX_EC_FANS];
956 UINT8 EnableFan1Device;
957
958 UINT8 EnableChargerParticipant;
959 UINT8 EnablePowerParticipant;
960 UINT16 PowerParticipantPollingRate;
961
962 UINT8 EnableBatteryParticipant;
963 UINT8 EnableInt3400Device;
964
965 UINT8 EnableSen1ParticipantSupport; // @deprecated - No longer needed DetectEcSensors[0] is used instead
966 UINT8 DetectEcSensors[MAX_EC_SENSORS];
967 UINT8 EnableSen1Participant;
968 UINT8 EnableSen2Participant;
969 UINT8 EnableSen3Participant;
970 UINT8 EnableSen4Participant;
971 UINT8 EnableSen5Participant;
972
973 UINT8 EnablePchFivrParticipant;
974
975 UINT8 PpccObject;
976 UINT8 ArtgObject;
977 UINT8 PmaxObject;
978 UINT8 Tmp1Object;
979 UINT8 Tmp2Object;
980 UINT8 Tmp3Object;
981 UINT8 Tmp4Object;
982 UINT8 Tmp5Object;
983 UINT8 Tmp6Object;
984 UINT8 Tmp7Object;
985 UINT8 Tmp8Object;
986 UINT8 OptionalObjects;
987
988 UINT8 OemDesignVariable0;
989 UINT8 OemDesignVariable1;
990 UINT8 OemDesignVariable2;
991 UINT8 OemDesignVariable3;
992 UINT8 OemDesignVariable4;
993 UINT8 OemDesignVariable5;
994
995 //
996 // Intel(R) Dynamic Tuning Technology SETUP items end
997 //
998 UINT8 Rtd3Support;
999 UINT8 Rtd3P0dl;
1000 UINT8 Rtd3UsbPt1;
1001 UINT8 Rtd3UsbPt2;
1002 UINT16 Rtd3AudioDelay;
1003 UINT16 Rtd3TouchPadDelay;
1004 UINT16 Rtd3TouchPanelDelay;
1005 UINT16 Rtd3SensorHub;
1006 UINT16 VRRampUpDelay;
1007 UINT8 PstateCapping;
1008 UINT8 Rtd3ZpoddSupport;
1009 UINT8 Rtd3Zpodd;
1010 UINT8 Rtd3WWAN;
1011 UINT8 Rtd3SataPort0;
1012 UINT8 Rtd3SataPort1;
1013 UINT8 Rtd3SataPort2;
1014 UINT8 Rtd3SataPort3;
1015 UINT8 Rtd3SataPort4;
1016 UINT8 Rtd3SataPort5;
1017 UINT8 Rtd3SataPort6;
1018 UINT8 Rtd3SataPort7;
1019 UINT8 Rtd3WaGpio;
1020 UINT8 Rtd3RemapCR1;
1021 UINT8 Rtd3RemapCR2;
1022 UINT8 Rtd3RemapCR3;
1023 UINT8 Rtd3I2CTouchPanel;
1024
1025 UINT8 PowerSharingManagerEnable;
1026 UINT8 PsmSplcDomainType1;
1027 UINT32 PsmSplcPowerLimit1;
1028 UINT32 PsmSplcTimeWindow1;
1029
1030 UINT8 PsmDplcDomainType1;
1031 UINT8 PsmDplcDomainPreference1;
1032 UINT16 PsmDplcPowerLimitIndex1;
1033 UINT16 PsmDplcDefaultPowerLimit1;
1034 UINT32 PsmDplcDefaultTimeWindow1;
1035 UINT16 PsmDplcMinimumPowerLimit1;
1036 UINT16 PsmDplcMaximumPowerLimit1;
1037 UINT16 PsmDplcMaximumTimeWindow1;
1038
1039 UINT8 WifiEnable;
1040 UINT8 WifiDomainType1;
1041 UINT16 WifiPowerLimit1;
1042 UINT32 WifiTimeWindow1;
1043 UINT8 TRxDelay0;
1044 UINT8 TRxCableLength0;
1045 UINT8 TRxDelay1;
1046 UINT8 TRxCableLength1;
1047 UINT8 WrddDomainType1;
1048 UINT16 WrddCountryIndentifier1;
1049 UINT8 WrddDomainType2;
1050 UINT16 WrddCountryIndentifier2;
1051 UINT8 WrdsWiFiSarEnable;
1052 UINT8 WrdsWiFiSarTxPowerSet1Limit1;
1053 UINT8 WrdsWiFiSarTxPowerSet1Limit2;
1054 UINT8 WrdsWiFiSarTxPowerSet1Limit3;
1055 UINT8 WrdsWiFiSarTxPowerSet1Limit4;
1056 UINT8 WrdsWiFiSarTxPowerSet1Limit5;
1057 UINT8 WrdsWiFiSarTxPowerSet1Limit6;
1058 UINT8 WrdsWiFiSarTxPowerSet1Limit7;
1059 UINT8 WrdsWiFiSarTxPowerSet1Limit8;
1060 UINT8 WrdsWiFiSarTxPowerSet1Limit9;
1061 UINT8 WrdsWiFiSarTxPowerSet1Limit10;
1062
1063 UINT8 EwrdWiFiDynamicSarEnable;
1064 UINT8 EwrdWiFiDynamicSarRangeSets;
1065 UINT8 EwrdWiFiSarTxPowerSet2Limit1;
1066 UINT8 EwrdWiFiSarTxPowerSet2Limit2;
1067 UINT8 EwrdWiFiSarTxPowerSet2Limit3;
1068 UINT8 EwrdWiFiSarTxPowerSet2Limit4;
1069 UINT8 EwrdWiFiSarTxPowerSet2Limit5;
1070 UINT8 EwrdWiFiSarTxPowerSet2Limit6;
1071 UINT8 EwrdWiFiSarTxPowerSet2Limit7;
1072 UINT8 EwrdWiFiSarTxPowerSet2Limit8;
1073 UINT8 EwrdWiFiSarTxPowerSet2Limit9;
1074 UINT8 EwrdWiFiSarTxPowerSet2Limit10;
1075 UINT8 EwrdWiFiSarTxPowerSet3Limit1;
1076 UINT8 EwrdWiFiSarTxPowerSet3Limit2;
1077 UINT8 EwrdWiFiSarTxPowerSet3Limit3;
1078 UINT8 EwrdWiFiSarTxPowerSet3Limit4;
1079 UINT8 EwrdWiFiSarTxPowerSet3Limit5;
1080 UINT8 EwrdWiFiSarTxPowerSet3Limit6;
1081 UINT8 EwrdWiFiSarTxPowerSet3Limit7;
1082 UINT8 EwrdWiFiSarTxPowerSet3Limit8;
1083 UINT8 EwrdWiFiSarTxPowerSet3Limit9;
1084 UINT8 EwrdWiFiSarTxPowerSet3Limit10;
1085 UINT8 EwrdWiFiSarTxPowerSet4Limit1;
1086 UINT8 EwrdWiFiSarTxPowerSet4Limit2;
1087 UINT8 EwrdWiFiSarTxPowerSet4Limit3;
1088 UINT8 EwrdWiFiSarTxPowerSet4Limit4;
1089 UINT8 EwrdWiFiSarTxPowerSet4Limit5;
1090 UINT8 EwrdWiFiSarTxPowerSet4Limit6;
1091 UINT8 EwrdWiFiSarTxPowerSet4Limit7;
1092 UINT8 EwrdWiFiSarTxPowerSet4Limit8;
1093 UINT8 EwrdWiFiSarTxPowerSet4Limit9;
1094 UINT8 EwrdWiFiSarTxPowerSet4Limit10;
1095 UINT8 WgdsWiFiSarDeltaGroup1PowerMax1;
1096 UINT8 WgdsWiFiSarDeltaGroup1PowerChainA1;
1097 UINT8 WgdsWiFiSarDeltaGroup1PowerChainB1;
1098 UINT8 WgdsWiFiSarDeltaGroup1PowerMax2;
1099 UINT8 WgdsWiFiSarDeltaGroup1PowerChainA2;
1100 UINT8 WgdsWiFiSarDeltaGroup1PowerChainB2;
1101 UINT8 WgdsWiFiSarDeltaGroup2PowerMax1;
1102 UINT8 WgdsWiFiSarDeltaGroup2PowerChainA1;
1103 UINT8 WgdsWiFiSarDeltaGroup2PowerChainB1;
1104 UINT8 WgdsWiFiSarDeltaGroup2PowerMax2;
1105 UINT8 WgdsWiFiSarDeltaGroup2PowerChainA2;
1106 UINT8 WgdsWiFiSarDeltaGroup2PowerChainB2;
1107 UINT8 WgdsWiFiSarDeltaGroup3PowerMax1;
1108 UINT8 WgdsWiFiSarDeltaGroup3PowerChainA1;
1109 UINT8 WgdsWiFiSarDeltaGroup3PowerChainB1;
1110 UINT8 WgdsWiFiSarDeltaGroup3PowerMax2;
1111 UINT8 WgdsWiFiSarDeltaGroup3PowerChainA2;
1112 UINT8 WgdsWiFiSarDeltaGroup3PowerChainB2;
1113 UINT8 WiFiDynamicSarAntennaACurrentSet;
1114 UINT8 WiFiDynamicSarAntennaBCurrentSet;
1115
1116 UINT8 BluetoothSar;
1117 UINT8 BluetoothSarBr;
1118 UINT8 BluetoothSarEdr2;
1119 UINT8 BluetoothSarEdr3;
1120 UINT8 BluetoothSarLe;
1121 UINT8 BluetoothSarLe2Mhz;
1122 UINT8 BluetoothSarLeLr;
1123
1124 UINT8 AntennaDiversity;
1125 UINT8 CoExistenceManager;
1126 UINT8 PrebootBleEnable;
1127 UINT8 UsbFnEnable;
1128
1129 UINT8 FanControl;
1130 UINT8 CpuFanControl;
1131 UINT8 LowestFanSpeed;
1132
1133 //
1134 // Thunderbolt(TM)
1135 //
1136 UINT8 TbtSetupFormSupport;
1137 UINT8 TbtSetupDTbtPegTypeSupport;
1138 UINT8 DiscreteTbtSupport;
1139 UINT8 IntegratedTbtSupport;
1140 UINT8 TbtPcieSupport;
1141 UINT8 TbtUsbOn; // Deprecated
1142 UINT8 TbtBootOn;
1143 UINT8 TbtWakeupSupport;
1144 UINT8 Gpio3ForcePwr;
1145 UINT16 Gpio3ForcePwrDly; // Deprecated
1146 UINT8 CallSmiBeforeBoot;
1147 UINT8 Gpio5Filter;
1148 UINT8 TBTHotNotify;
1149 UINT8 EnableMsiInFadt;
1150 UINT8 DTbtController[DTBT_CONTROLLER_SUPPORTED];
1151 UINT8 DTbtControllerType[DTBT_CONTROLLER_SUPPORTED];
1152 UINT8 TBTSetClkReq;
1153 UINT8 TbtAspm;
1154 UINT8 TbtLtr;
1155 UINT8 DTbthostRouterPortNumber[DTBT_CONTROLLER_SUPPORTED];
1156 UINT8 DTbtPcieExtraBusRsvd[DTBT_CONTROLLER_SUPPORTED];
1157 UINT16 DTbtPcieMemRsvd[DTBT_CONTROLLER_SUPPORTED];
1158 UINT8 DTbtPcieIoRsvd[DTBT_CONTROLLER_SUPPORTED];
1159 UINT8 DTbtPcieMemAddrRngMax[DTBT_CONTROLLER_SUPPORTED];
1160 UINT16 DTbtPciePMemRsvd[DTBT_CONTROLLER_SUPPORTED];
1161 UINT8 DTbtPciePMemAddrRngMax[DTBT_CONTROLLER_SUPPORTED];
1162 UINT8 Win10Support;
1163 UINT8 TrOsup; // Deprecated from Revision 12
1164 UINT8 TbtL1SubStates;
1165 UINT8 TbtPtm;
1166 UINT8 OsNativeResourceBalance;
1167 UINT8 TbtAcDcSwitch; // Deprecated from Revision 12
1168 UINT8 TbtLegacyModeSupport;
1169 // ITBT Specific Setup Options
1170 UINT8 ITbtPcieRootPortSupported[ITBT_ROOT_PORTS_SUPPORTED];
1171 UINT8 ITbtRootPort[ITBT_ROOT_PORTS_SUPPORTED];
1172 UINT8 ITbtPcieExtraBusRsvd[ITBT_ROOT_PORTS_SUPPORTED];
1173 UINT16 ITbtPcieMemRsvd[ITBT_ROOT_PORTS_SUPPORTED];
1174 UINT8 ITbtPcieMemAddrRngMax[ITBT_ROOT_PORTS_SUPPORTED];
1175 UINT16 ITbtPciePMemRsvd[ITBT_ROOT_PORTS_SUPPORTED];
1176 UINT8 ITbtPciePMemAddrRngMax[ITBT_ROOT_PORTS_SUPPORTED];
1177 UINT16 ITbtForcePowerOnTimeoutInMs;
1178 UINT16 ITbtConnectTopologyTimeoutInMs;
1179 UINT16 ReserveMemoryPerSlot;
1180 UINT16 ReservePMemoryPerSlot;
1181 UINT8 ReserveIoPerSlot;
1182 UINT8 ITbtPcieTunnelingForUsb4; // Deprecated from Revision 31
1183 UINT8 TbtSkipPciOprom; // Deprecated from Revision 17
1184 UINT8 TbtAcpiRemovalSupport;
1185
1186 UINT8 OcWdtEnabled;
1187 UINT8 IccLockRegisters;
1188 UINT8 IccProfile;
1189 UINT8 ShowProfile;
1190 UINT8 NumProfiles;
1191
1192 UINT8 CsModeFirst;
1193 UINT8 CsMode;
1194 UINT8 CsModeChanged;
1195
1196 UINT8 PlatformUnstable;
1197 UINT8 IsOcDefaultsInitalized;
1198
1199 UINT8 SecureEraseModeRealMode;
1200 UINT8 ForceSecureErase;
1201
1202 UINT8 HidEventFilterDriverEnable;
1203
1204
1205 UINT8 PmicSlpS0VmSupport;
1206 UINT8 HebcValueSupport;
1207 UINT32 HebcValue;
1208
1209 UINT8 I2cSarResetDelay;
1210
1211 UINT8 WwanEnable;
1212
1213 UINT8 UsbcBiosTcssHandshake;
1214 // EC - BIOS handshake timeouts
1215 UINT32 UsbConnStatusTimeout;
1216 UINT32 UsbcSxEntryTimeout;
1217 UINT32 UsbcSxExitTimeout;
1218
1219
1220 UINT8 VtioSupport;
1221 UINT8 SdevCio2Entry;
1222 UINT8 SdevIspEntry;
1223 UINT8 SdevHeciEntry;
1224 UINT8 SdevSpi1Entry;
1225 UINT8 SdevSpi2Entry;
1226 UINT8 SdevXhciEntry;
1227 UINT16 SdevNumberOfSensors[5];
1228 UINT16 SdevSensorEntry1[5];
1229 UINT16 SdevSensorEntry2[5];
1230
1231 UINT8 EcChargingMethod;
1232 UINT8 AlternateModeSynchDelay;
1233 UINT8 WakeOnWiGigSupport;
1234
1235 UINT8 SystemTimeAndAlarmSource; // Select source for system time and alarm
1236
1237 UINT8 TrustedDeviceSetupBoot;
1238 UINT8 TestUsbUnlockForNoa;
1239
1240 UINT8 EnableCrashLog;
1241 UINT8 CrashLogOnAllReset;
1242 UINT8 CrashLogClearEnable;
1243 UINT8 CrashLogRearmEnable;
1244
1245 UINT8 SysFwUpdateLoadDefault;
1246 UINT8 SysFwUpdateSkipPowerCheck;
1247
1248 UINT8 BoardReworkComplainceEnable;
1249 UINT8 ItpxdpMuxSupport;
1250 UINT8 ItpxdpMux;
1251
1252
1253 UINT8 OsDnx;
1254
1255 UINT8 PepPeg0;
1256 // Option to slect UCMC/UCSI device
1257 UINT8 TcssUcmDevice;
1258 UINT8 PepPcieStorage;
1259 UINT8 TbtVtdBaseSecurity; // Deprecated from Revision 25
1260 UINT8 KernelDebugPatch;
1261 UINT8 ITbtRtd3;
1262 UINT16 ITbtRtd3ExitDelay;
1263 UINT8 AuxOriOverrideSupport;
1264 UINT8 AuxOriOverride;
1265 UINT8 TccMode;
1266
1267 UINT8 BclkSource;
1268 UINT8 PowermeterDeviceEnable; // powermeter enabling
1269 UINT8 WwanResetWorkaround;
1270 UINT8 PuisEnable;
1271 UINT8 SdevXhciNumberOfDevices;
1272 UINT8 SdevXhciDeviceAttributes[2];
1273 UINT8 SdevXhciRootPortNumber[2];
1274 UINT16 SdevXhciVendorId[2];
1275 UINT16 SdevXhciProductId[2];
1276 UINT16 SdevXhciRevision[2];
1277 UINT8 SdevXhciInterfaceNumber[2];
1278 UINT8 SdevXhciClass[2];
1279 UINT8 SdevXhciSubClass[2];
1280 UINT8 SdevXhciProtocol[2];
1281 UINT16 SdevXhciAcpiPathStringOffset[2];
1282 UINT16 SdevXhciAcpiPathStringLength[2];
1283 UINT64 SdevXhciFirmwareHashDevice1[4];
1284 UINT64 SdevXhciFirmwareHashDevice2[4];
1285 UINT16 SdevXhciAcpiPathNameDevice1[49]; // 48 characters + NULL termination
1286 UINT16 SdevXhciAcpiPathNameDevice2[49]; // 48 characters + NULL termination
1287
1288 UINT8 CurrentSecurityMode;// Deprecated
1289
1290 UINT8 ControlIommu;
1291
1292 UINT8 SdevFlags[5];
1293 UINT8 SdevXhciFlags;
1294 UINT8 DevicePasswordSupport;
1295 UINT8 PepVmd;
1296 UINT8 DTbtRtd3;
1297 UINT16 DTbtRtd3OffDelay;
1298 UINT32 DTbtRtd3ClkReq;
1299 UINT16 DTbtRtd3ClkReqDelay;
1300 UINT8 DTbtGo2SxCommand;
1301 UINT8 EnablePcieTunnelingOverUsb4;
1302 UINT8 CnvExtClock;
1303
1304 UINT8 WifiAntGainEnale;
1305 UINT8 WifiAntGain2400ChainA;
1306 UINT8 WifiAntGain5150ChainA;
1307 UINT8 WifiAntGain5350ChainA;
1308 UINT8 WifiAntGain5470ChainA;
1309 UINT8 WifiAntGain5725ChainA;
1310 UINT8 WifiAntGain2400ChainB;
1311 UINT8 WifiAntGain5150ChainB;
1312 UINT8 WifiAntGain5350ChainB;
1313 UINT8 WifiAntGain5470ChainB;
1314 UINT8 WifiAntGain5725ChainB;
1315
1316 UINT8 WifiSarGeoMappingMode; // Deprecated
1317 UINT8 WifiSarGeoDefault; // Deprecated
1318 UINT8 WifiSarGeoFcc; // Deprecated
1319 UINT8 WifiSarGeoTwalike; // Deprecated
1320 UINT8 WifiSarGeoCanadaIsed; // Deprecated
1321 UINT8 WifiSarGeoEtsi5G8Srd; // Deprecated
1322 UINT8 WifiSarGeoEtsi5G8Med; // Deprecated
1323 UINT8 WifiSarGeoJapan; // Deprecated
1324 UINT8 WifiSarGeoBrazil; // Deprecated
1325 UINT8 WifiSarGeoEtsi5G8Fcc; // Deprecated
1326 UINT8 WifiSarGeoIndonesia; // Deprecated
1327 UINT8 WifiSarGeoSouthKorea; // Deprecated
1328 UINT8 WifiSarGeoChile; // Deprecated
1329 UINT8 WifiSarGeoEtsi5G8Pass; // Deprecated
1330 UINT8 WifiSarGeoPakistan; // Deprecated
1331 UINT8 WifiSarGeoEgypt; // Deprecated
1332 UINT8 WifiSarGeoTunisia; // Deprecated
1333 UINT8 WifiSarGeoChinaBios; // Deprecated
1334 UINT8 WifiSarGeoRussia; // Deprecated
1335 UINT8 WifiSarGeoEuEtsi5G8Srd; // Deprecated
1336 UINT8 WifiSarGeoUsaOnly; // Deprecated
1337 UINT8 WifiSarGeoEuEtsi5G8Dfs; // Deprecated
1338 UINT8 WifiSarGeoQatar; // Deprecated
1339
1340 UINT8 MipiCam_Flash0_Mode;
1341 UINT8 MipiCam_Flash1_Mode;
1342 UINT8 MipiCam_Flash2_Mode;
1343 UINT8 MipiCam_Flash3_Mode;
1344 UINT8 MipiCam_Flash4_Mode;
1345 UINT8 MipiCam_Flash5_Mode;
1346 UINT8 TypecRetimerTxComplianceModeEn;
1347 UINT8 TypecRetimerPD0;
1348 UINT8 TypecRetimerPD1;
1349 UINT8 TypecRetimerPD2;
1350 UINT8 TypecRetimerPD3;
1351 UINT8 WifiActiveChannelSrd;
1352 UINT8 WifiIndonesia5GhzSupport;
1353 UINT8 CvfSupport;
1354 UINT8 DeepestUSBSleepWakeCapability;
1355
1356 UINT8 PepSataEnumeration;
1357 UINT8 PepHeci3;
1358
1359
1360 UINT32 WifiUltraHighBandSupport;
1361 UINT8 WrdsWiFiSarTxPowerSet1Limit11;
1362 UINT8 WrdsWiFiSarTxPowerSet1Limit12;
1363 UINT8 WrdsWiFiSarTxPowerSet1Limit13;
1364 UINT8 WrdsWiFiSarTxPowerSet1Limit14;
1365 UINT8 WrdsWiFiSarTxPowerSet1Limit15;
1366 UINT8 WrdsWiFiSarTxPowerSet1Limit16;
1367 UINT8 WrdsWiFiSarTxPowerSet1Limit17;
1368 UINT8 WrdsWiFiSarTxPowerSet1Limit18;
1369 UINT8 WrdsWiFiSarTxPowerSet1Limit19;
1370 UINT8 WrdsWiFiSarTxPowerSet1Limit20;
1371 UINT8 WrdsWiFiSarTxPowerSet1Limit21;
1372 UINT8 WrdsWiFiSarTxPowerSet1Limit22;
1373 UINT8 EwrdWiFiSarTxPowerSet2Limit11;
1374 UINT8 EwrdWiFiSarTxPowerSet2Limit12;
1375 UINT8 EwrdWiFiSarTxPowerSet2Limit13;
1376 UINT8 EwrdWiFiSarTxPowerSet2Limit14;
1377 UINT8 EwrdWiFiSarTxPowerSet2Limit15;
1378 UINT8 EwrdWiFiSarTxPowerSet2Limit16;
1379 UINT8 EwrdWiFiSarTxPowerSet2Limit17;
1380 UINT8 EwrdWiFiSarTxPowerSet2Limit18;
1381 UINT8 EwrdWiFiSarTxPowerSet2Limit19;
1382 UINT8 EwrdWiFiSarTxPowerSet2Limit20;
1383 UINT8 EwrdWiFiSarTxPowerSet2Limit21;
1384 UINT8 EwrdWiFiSarTxPowerSet2Limit22;
1385 UINT8 EwrdWiFiSarTxPowerSet3Limit11;
1386 UINT8 EwrdWiFiSarTxPowerSet3Limit12;
1387 UINT8 EwrdWiFiSarTxPowerSet3Limit13;
1388 UINT8 EwrdWiFiSarTxPowerSet3Limit14;
1389 UINT8 EwrdWiFiSarTxPowerSet3Limit15;
1390 UINT8 EwrdWiFiSarTxPowerSet3Limit16;
1391 UINT8 EwrdWiFiSarTxPowerSet3Limit17;
1392 UINT8 EwrdWiFiSarTxPowerSet3Limit18;
1393 UINT8 EwrdWiFiSarTxPowerSet3Limit19;
1394 UINT8 EwrdWiFiSarTxPowerSet3Limit20;
1395 UINT8 EwrdWiFiSarTxPowerSet3Limit21;
1396 UINT8 EwrdWiFiSarTxPowerSet3Limit22;
1397 UINT8 EwrdWiFiSarTxPowerSet4Limit11;
1398 UINT8 EwrdWiFiSarTxPowerSet4Limit12;
1399 UINT8 EwrdWiFiSarTxPowerSet4Limit13;
1400 UINT8 EwrdWiFiSarTxPowerSet4Limit14;
1401 UINT8 EwrdWiFiSarTxPowerSet4Limit15;
1402 UINT8 EwrdWiFiSarTxPowerSet4Limit16;
1403 UINT8 EwrdWiFiSarTxPowerSet4Limit17;
1404 UINT8 EwrdWiFiSarTxPowerSet4Limit18;
1405 UINT8 EwrdWiFiSarTxPowerSet4Limit19;
1406 UINT8 EwrdWiFiSarTxPowerSet4Limit20;
1407 UINT8 EwrdWiFiSarTxPowerSet4Limit21;
1408 UINT8 EwrdWiFiSarTxPowerSet4Limit22;
1409
1410 UINT8 WifiAntGain5945ChainA;
1411 UINT8 WifiAntGain6165ChainA;
1412 UINT8 WifiAntGain6405ChainA;
1413 UINT8 WifiAntGain6525ChainA;
1414 UINT8 WifiAntGain6705ChainA;
1415 UINT8 WifiAntGain6865ChainA;
1416 UINT8 WifiAntGain5945ChainB;
1417 UINT8 WifiAntGain6165ChainB;
1418 UINT8 WifiAntGain6405ChainB;
1419 UINT8 WifiAntGain6525ChainB;
1420 UINT8 WifiAntGain6705ChainB;
1421 UINT8 WifiAntGain6865ChainB;
1422 UINT8 AxSettingUkraine;
1423 UINT8 AxModeUkraine;
1424 UINT8 AxSettingRussia;
1425 UINT8 AxModeRussia;
1426
1427 UINT8 WgdsWiFiSarDeltaGroup1PowerMax3;
1428 UINT8 WgdsWiFiSarDeltaGroup1PowerChainA3;
1429 UINT8 WgdsWiFiSarDeltaGroup1PowerChainB3;
1430 UINT8 WgdsWiFiSarDeltaGroup2PowerMax3;
1431 UINT8 WgdsWiFiSarDeltaGroup2PowerChainA3;
1432 UINT8 WgdsWiFiSarDeltaGroup2PowerChainB3;
1433 UINT8 WgdsWiFiSarDeltaGroup3PowerMax3;
1434 UINT8 WgdsWiFiSarDeltaGroup3PowerChainA3;
1435 UINT8 WgdsWiFiSarDeltaGroup3PowerChainB3;
1436
1437 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit1;
1438 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit2;
1439 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit3;
1440 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit4;
1441 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit5;
1442 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit6;
1443 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit7;
1444 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit8;
1445 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit9;
1446 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit10;
1447 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit11;
1448 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit12;
1449 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit13;
1450 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit14;
1451 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit15;
1452 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit16;
1453 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit17;
1454 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit18;
1455 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit19;
1456 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit20;
1457 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit21;
1458 UINT8 WrdsCdbWiFiSarTxPowerSet1Limit22;
1459
1460 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit1;
1461 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit2;
1462 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit3;
1463 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit4;
1464 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit5;
1465 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit6;
1466 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit7;
1467 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit8;
1468 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit9;
1469 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit10;
1470 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit11;
1471 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit12;
1472 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit13;
1473 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit14;
1474 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit15;
1475 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit16;
1476 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit17;
1477 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit18;
1478 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit19;
1479 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit20;
1480 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit21;
1481 UINT8 EwrdCdbWiFiSarTxPowerSet2Limit22;
1482
1483 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit1;
1484 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit2;
1485 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit3;
1486 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit4;
1487 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit5;
1488 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit6;
1489 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit7;
1490 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit8;
1491 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit9;
1492 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit10;
1493 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit11;
1494 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit12;
1495 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit13;
1496 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit14;
1497 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit15;
1498 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit16;
1499 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit17;
1500 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit18;
1501 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit19;
1502 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit20;
1503 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit21;
1504 UINT8 EwrdCdbWiFiSarTxPowerSet3Limit22;
1505
1506 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit1;
1507 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit2;
1508 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit3;
1509 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit4;
1510 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit5;
1511 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit6;
1512 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit7;
1513 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit8;
1514 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit9;
1515 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit10;
1516 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit11;
1517 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit12;
1518 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit13;
1519 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit14;
1520 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit15;
1521 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit16;
1522 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit17;
1523 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit18;
1524 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit19;
1525 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit20;
1526 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit21;
1527 UINT8 EwrdCdbWiFiSarTxPowerSet4Limit22;
1528
1529 UINT32 WifiPhyFilterConfigA; // Deprecated
1530 UINT32 WifiPhyFilterConfigB; // Deprecated
1531 UINT32 WifiPhyFilterConfigC; // Deprecated
1532 UINT32 WifiPhyFilterConfigD; // Deprecated
1533
1534 UINT8 MipiCam_Link0_LanesClkDiv;
1535 UINT8 MipiCam_Link1_LanesClkDiv;
1536 UINT8 MipiCam_Link2_LanesClkDiv;
1537 UINT8 MipiCam_Link3_LanesClkDiv;
1538 UINT8 MipiCam_Link4_LanesClkDiv;
1539 UINT8 MipiCam_Link5_LanesClkDiv;
1540 UINT8 EnableFan2Device;
1541 UINT8 EnableFan3Device;
1542 UINT8 EnableDgpuParticipant;
1543 UINT8 AdlSAepBoard;
1544
1545 UINT8 WifiTASSelection;
1546 UINT8 WifiTASListEntries;
1547 UINT8 PlnEnable;
1548
1549 // Option to enable/disable PD PS_ON feature
1550 UINT8 TcssPdPsOnEnable;
1551
1552 UINT8 PepPcieLan;
1553 UINT8 PepPcieWlan;
1554 UINT8 PepPcieGfx;
1555 UINT8 PepPcieOther;
1556 UINT8 AuxRailBudget;
1557 UINT8 PepPcieDg;
1558 UINT8 DgPlatformSupport;
1559 UINT16 WTASBlockedList[16];
1560 UINT8 DTbtRtd3OffDelayOptEn;
1561 // Disable TBT PCIE RP and child device Tree BME. It was earlier known as TbtVtdBaseSecurity
1562 UINT8 DisableTbtPcieTreeBme;
1563
1564 UINT8 BtTileMode;
1565 UINT8 TileS0;
1566 UINT8 TileS0ix;
1567 UINT8 TileS4;
1568 UINT8 TileS5;
1569 UINT8 SpecialLedConfig;
1570 UINT16 LedDuration;
1571 UINT8 AirplaneMode;
1572 UINT8 StorageRtd3Support;
1573 UINT8 PmaxDevice;
1574 UINT8 PmaxAudioCodec;
1575 UINT8 PmaxWfCamera;
1576 UINT8 PmaxUfCamera;
1577 UINT8 PmaxFlashDevice;
1578 UINT8 SecondConfigReworkOption; // Deprecated in revision 36
1579 UINT8 MPdtSupport;
1580 // Discrete TBT (DTBT) Setup Page Support.
1581 UINT8 DiscreteTbtPlatformConfigurationSupport;
1582 UINT8 WwanFwFlashDevice;
1583 UINT8 DtbtCmSupport;
1584 UINT8 Usb4CmMode;
1585 //
1586 // dTBT Dp-In Setup Option
1587 //
1588 UINT8 DpInExternalEn;
1589 UINT8 PepUfs0;
1590 UINT8 PepUfs1;
1591 UINT8 ClosedLidWovLightingSupport;
1592 //
1593 // TCSS CPU XHCI Enable Convert of Type-C to Type-A Port
1594 //
1595 UINT8 TestEnableTcssCovTypeA[MAX_TCSS_USB3_PORTS]; // Deprecated from Revision 38.
1596 //
1597 // TCSS Port Disable UCSI/UCMX Driver Support. 0: Platform POR (For EclessPd it is UCMX, For For EcPd it is USCI), 2: Force Disable the Driver support.
1598 //
1599 UINT8 TestDisableTcssPortUcxxSupport[10]; // MAX 10 Type-C Port. Reserve Extra also.
1600 UINT16 CpuBclkFreq;
1601 UINT8 PegDmiClkFreq;
1602 UINT8 DccClkCtrl;
1603 UINT8 UsbcDataRoleSwapPlatformDisable; // Platform Setup option to disable USBC DataRole Swap
1604 //
1605 // Dual Maple Ridge Platfrom.
1606 //
1607 UINT8 TwoMapleRidgeBoard;//Deprecated
1608 //
1609 // Flash ID support for Link 0-5
1610 //
1611 UINT8 MipiCam_Link0_DriverData_FlashID;
1612 UINT8 MipiCam_Link1_DriverData_FlashID;
1613 UINT8 MipiCam_Link2_DriverData_FlashID;
1614 UINT8 MipiCam_Link3_DriverData_FlashID;
1615 UINT8 MipiCam_Link4_DriverData_FlashID;
1616 UINT8 MipiCam_Link5_DriverData_FlashID;
1617
1618 UINT16 PchSerialIoTimingSSH6; // [SSH6] SSCN-HIGH for I2C6
1619 UINT16 PchSerialIoTimingSSL6; // [SSL6] SSCN-LOW for I2C6
1620 UINT16 PchSerialIoTimingSSD6; // [SSD6] SSCN-HOLD for I2C6
1621 UINT16 PchSerialIoTimingFMH6; // [FMH6] FMCN-HIGH for I2C6
1622 UINT16 PchSerialIoTimingFML6; // [FML6] FMCN-LOW for I2C6
1623 UINT16 PchSerialIoTimingFMD6; // [FMD6] FMCN-HOLD for I2C6
1624 UINT16 PchSerialIoTimingFPH6; // [FPH6] FPCN-HIGH for I2C6
1625 UINT16 PchSerialIoTimingFPL6; // [FPL6] FPCN-LOW for I2C6
1626 UINT16 PchSerialIoTimingFPD6; // [FPD6] FPCN-HOLD for I2C6
1627 UINT16 PchSerialIoTimingHSH6; // [HSH6] HSCN-HIGH for I2C6
1628 UINT16 PchSerialIoTimingHSL6; // [HSL6] HSCN-LOW for I2C6
1629 UINT16 PchSerialIoTimingHSD6; // [HSD6] HSCN-HOLD for I2C6
1630 UINT16 PchSerialIoTimingM0CC; // [M0CC] M0D3 for I2C6
1631 UINT16 PchSerialIoTimingM1CC; // [M1CC] M1D3 for I2C6
1632 UINT8 PepI2c6;
1633
1634 UINT16 PchSerialIoTimingSSH7; // [SSH7] SSCN-HIGH for I2C7
1635 UINT16 PchSerialIoTimingSSL7; // [SSL7] SSCN-LOW for I2C7
1636 UINT16 PchSerialIoTimingSSD7; // [SSD7] SSCN-HOLD for I2C7
1637 UINT16 PchSerialIoTimingFMH7; // [FMH7] FMCN-HIGH for I2C7
1638 UINT16 PchSerialIoTimingFML7; // [FML7] FMCN-LOW for I2C7
1639 UINT16 PchSerialIoTimingFMD7; // [FMD7] FMCN-HOLD for I2C7
1640 UINT16 PchSerialIoTimingFPH7; // [FPH7] FPCN-HIGH for I2C7
1641 UINT16 PchSerialIoTimingFPL7; // [FPL7] FPCN-LOW for I2C7
1642 UINT16 PchSerialIoTimingFPD7; // [FPD7] FPCN-HOLD for I2C7
1643 UINT16 PchSerialIoTimingHSH7; // [HSH7] HSCN-HIGH for I2C7
1644 UINT16 PchSerialIoTimingHSL7; // [HSL7] HSCN-LOW for I2C7
1645 UINT16 PchSerialIoTimingHSD7; // [HSD7] HSCN-HOLD for I2C7
1646 UINT16 PchSerialIoTimingM0CD; // [M0CD] M0D3 for I2C7
1647 UINT16 PchSerialIoTimingM1CD; // [M1CD] M1D3 for I2C7
1648 UINT8 PepI2c7;
1649 UINT8 DTbtDpInSupport;
1650 UINT16 WwanOemSvid;
1651 UINT16 WwanSvidTimeout;
1652 UINT8 BtLedConfig;
1653 UINT8 BtLedPulseDuration;
1654 UINT8 BtLedPulseInterval;
1655 UINT32 WifiRegulatoryConfigurations;
1656 UINT32 WifiUartConfigurations;
1657 UINT32 WifiUnii4;
1658 UINT32 WifiIndoorControl;
1659 UINT8 PepEmmc;
1660 UINT8 SdCardD3ColdDisable; //Deprecated SdCardD3ColdDisable
1661 UINT8 SDCardD3ColdSupport; // Deprecated SDCardD3ColdSupport
1662 UINT8 WirelessCnvConfigDevice;
1663 UINT16 CurrentCpuBclkFreq;
1664 UINT16 CurrentPegDmiClkFreq;
1665 UINT8 WirelessLowBandIsolation; // WLAN/WWAN Low Band Isolation
1666 UINT8 WirelessHighBandIsolation; // WLAN/WWAN High Band Isolation
1667 UINT8 WgdsWiFiSarDeltaGroupNumber;
1668 UINT8 WgdsWiFiSarDeltaGroup4PowerMax1;
1669 UINT8 WgdsWiFiSarDeltaGroup4PowerChainA1;
1670 UINT8 WgdsWiFiSarDeltaGroup4PowerChainB1;
1671 UINT8 WgdsWiFiSarDeltaGroup4PowerMax2;
1672 UINT8 WgdsWiFiSarDeltaGroup4PowerChainA2;
1673 UINT8 WgdsWiFiSarDeltaGroup4PowerChainB2;
1674 UINT8 WgdsWiFiSarDeltaGroup4PowerMax3;
1675 UINT8 WgdsWiFiSarDeltaGroup4PowerChainA3;
1676 UINT8 WgdsWiFiSarDeltaGroup4PowerChainB3;
1677 UINT8 WgdsWiFiSarDeltaGroup5PowerMax1;
1678 UINT8 WgdsWiFiSarDeltaGroup5PowerChainA1;
1679 UINT8 WgdsWiFiSarDeltaGroup5PowerChainB1;
1680 UINT8 WgdsWiFiSarDeltaGroup5PowerMax2;
1681 UINT8 WgdsWiFiSarDeltaGroup5PowerChainA2;
1682 UINT8 WgdsWiFiSarDeltaGroup5PowerChainB2;
1683 UINT8 WgdsWiFiSarDeltaGroup5PowerMax3;
1684 UINT8 WgdsWiFiSarDeltaGroup5PowerChainA3;
1685 UINT8 WgdsWiFiSarDeltaGroup5PowerChainB3;
1686 UINT8 WgdsWiFiSarDeltaGroup6PowerMax1;
1687 UINT8 WgdsWiFiSarDeltaGroup6PowerChainA1;
1688 UINT8 WgdsWiFiSarDeltaGroup6PowerChainB1;
1689 UINT8 WgdsWiFiSarDeltaGroup6PowerMax2;
1690 UINT8 WgdsWiFiSarDeltaGroup6PowerChainA2;
1691 UINT8 WgdsWiFiSarDeltaGroup6PowerChainB2;
1692 UINT8 WgdsWiFiSarDeltaGroup6PowerMax3;
1693 UINT8 WgdsWiFiSarDeltaGroup6PowerChainA3;
1694 UINT8 WgdsWiFiSarDeltaGroup6PowerChainB3;
1695 UINT8 WgdsWiFiSarDeltaGroup7PowerMax1;
1696 UINT8 WgdsWiFiSarDeltaGroup7PowerChainA1;
1697 UINT8 WgdsWiFiSarDeltaGroup7PowerChainB1;
1698 UINT8 WgdsWiFiSarDeltaGroup7PowerMax2;
1699 UINT8 WgdsWiFiSarDeltaGroup7PowerChainA2;
1700 UINT8 WgdsWiFiSarDeltaGroup7PowerChainB2;
1701 UINT8 WgdsWiFiSarDeltaGroup7PowerMax3;
1702 UINT8 WgdsWiFiSarDeltaGroup7PowerChainA3;
1703 UINT8 WgdsWiFiSarDeltaGroup7PowerChainB3;
1704 UINT8 WgdsWiFiSarDeltaGroup8PowerMax1;
1705 UINT8 WgdsWiFiSarDeltaGroup8PowerChainA1;
1706 UINT8 WgdsWiFiSarDeltaGroup8PowerChainB1;
1707 UINT8 WgdsWiFiSarDeltaGroup8PowerMax2;
1708 UINT8 WgdsWiFiSarDeltaGroup8PowerChainA2;
1709 UINT8 WgdsWiFiSarDeltaGroup8PowerChainB2;
1710 UINT8 WgdsWiFiSarDeltaGroup8PowerMax3;
1711 UINT8 WgdsWiFiSarDeltaGroup8PowerChainA3;
1712 UINT8 WgdsWiFiSarDeltaGroup8PowerChainB3;
1713 UINT8 Rp08D3ColdSupport;
1714 UINT8 Rp08D3ColdDisable;
1715 UINT8 Rp08WakeReworkDone;
1716
1717 UINT32 WifiTASSelectionValue;
1718 UINT8 RplSAepBoard;
1719 UINT8 PchDmiGen3RtcoCpre[PCH_MAX_DMI_LANES];
1720 UINT8 PchDmiGen3RtcoCpo[PCH_MAX_DMI_LANES];
1721 UINT8 DmiGen4RtcoCpre[8];
1722 UINT8 DmiGen4RtcoCpo[8];
1723 UINT8 DmiHweq;
1724 } SETUP_DATA;
1725
1726 /**
1727 Making any setup structure change after code frozen
1728 will need to maintain backward compatibility, bump up
1729 structure revision and update below history table\n
1730 <b>Revision 1</b>: - Initial version.
1731 <b>Revision 2</b>: - Updated VR related setup options.
1732 <b>Revision 3</b>: - Removed Voltage Optimization Feature as not a POR.
1733 <b>Revision 4</b>: - Deprecate BiosGuard enabling support
1734 <b>Revision 5</b>: - Added PsysOffsetPrefix.
1735 <b>Revision 6</b>: - Deprecate Vr Voltage Limit support
1736 <b>Revision 7</b>: - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor
1737 <b>Revision 8</b>: - Add ApplyConfigTdp.
1738 <b>Revision 9</b>: - Added Hwp Lock support.
1739 <b>Revision 10</b>: - Add SmmMsrSaveStateEnable, SmmUseDelayIndication,
1740 SmmUseBlockIndication, SmmUseSmmEnableIndication, SmmProcTraceEnable.
1741 <b>Revision 11</b>: - Added number of active small core support.
1742 <b>Revision 12</b>: - Add PerCoreHtDisable.
1743 <b>Revision 13</b>: - Add VF Point Offset Mode support.
1744 <b>Revision 14</b>: - Updated the VR Topology data.
1745 <b>Revision 15</b>: - Add irms support
1746 <b>Revision 16</b>: - Add Per-core VF curve support.
1747 <b>Revision 17</b>: - Add AllSmallCoreCount/AllBigCoreCount.
1748 <b>Revision 18</b>: - Deprecate SmmSpsEnable enabling DGR support.
1749 <b>Revision 19</b>: - Add RatioLimitRatioDefault, RatioLimitRatio, RatioLimitNumCoreDefault,
1750 RatioLimitNumCore, AtomRatioLimitRatioDefault, AtomRatioLimitRatio,
1751 AtomRatioLimitNumCoreDefault and AtomRatioLimitNumCore to replace
1752 RatioLimitXDefault and RatioLimitX.
1753 Correct IsTurboRatioDefaultsInitalized to IsTurboRatioDefaultsInitialized.
1754 <b>Revision 20</b>: - Add DualTauBoost
1755 <b>Revision 21</b>: - Add AtomL2MaxOcRatio and AtomL2MaxOcRatioDefault
1756 <b>Revision 22</b>: - Add PerCoreRatioOverride and PerCoreRatio for Per Core Ratio override
1757 <b>Revision 23</b>: - Add support for Platform Voltage control
1758 <b>Revision 24</b>: - Add PreWake, RampUp and RampDown for Acoustic Noise Mitigation DPA tuning.
1759 <b>Revision 25</b>: - Add UnlimitedIccMax
1760 <b>Revision 26</b>: - Removed EnableItbmDriver.
1761 <b>Revision 27</b>: - Add IntelSpeedOptimizer.
1762 <b>Revision 28</b>: - Add AtomL2Voltage related setup variables.
1763 <b>Revision 29</b>: - Add Avx disable support.
1764 <b>Revision 30</b>: - Add SA/Uncore voltage configurations
1765 <b>Revision 31</b>: - add CrashLogGprs.
1766 <b>Revision 32</b>: - Add TvbRatioClipping, TvbVoltageOptimization
1767 <b>Revision 33</b>: - Add Vr Voltage Limit
1768 <b>Revision 34</b>: - Add VF Point Offset Mode support for Ring.
1769 <b>Revision 35</b>: - Add VccInAux IMON support
1770 <b>Revision 36</b>: - Add FIVR Spread Spectrum Enable.
1771 <b>Revision 37</b>: - Add CpuBclkOcFrequency
1772 <b>Revision 38</b>: - Add processor disable control support to indicate which core/atom should be disabled.
1773 <b>Revision 39</b>: - Add VR Power Delivery design
1774 <b>Revision 40</b>: - Add Core Ratio Extension Mode support.
1775 <b>Revision 41</b>: - Deprecate SGx.
1776 <b>Revision 42</b>: - Add Pvd Ratio Threshold.
1777 <b>Revision 43</b>: - Add per Atom Cluster VF support.
1778 <b>Revision 44</b>: - Add new external voltage rails overrides and deprecated some others unused voltage rails based on ADL OC RVP design.
1779 <b>Revision 45</b>: - Add VR Fast Vmode ICC Limit support.
1780 <b>Revision 46</b>: - Add CEP enable/disable support for IA/GT.
1781 <b>Revision 47</b>: - Add AtomPllVoltageOffset.
1782 <b>Revision 48</b>: - Removed FivrFaults, FivrEfficiency.
1783 <b>Revision 49</b>: - Add VCCIN_AUX and Richtek VccIA and VccGT voltage override support
1784 <b>Revision 50</b>: - Add DlvrBypassModeEnable support.
1785 <b>Revision 51</b>: - Deprecated AtomL2MaxOcRatio
1786 <b>Revision 52</b>: - Deprecated Avx3Disable
1787 <b>Revision 53</b>: - Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset
1788 <b>Revision 54</b>: - Add SaPllFreqOverride support.
1789 <b>Revision 55</b>: - Add PllMaxBandingRatio
1790 <b>Revision 56</b>: - Add TscDisableHwFixup
1791 <b>Revision 57</b>: - Add IaIccMax, IaIccUnlimitedMode, GtIccMax, GtIccUnlimitedMode, deprecated UnlimitedIccMax
1792 <b>Revision 58</b>: - Add PerCoreDisableConfiguration
1793 <b>Revision 59</b>: - Add TvbDownBinsTempThreshold0, TvbTempThreshold0, TvbTempThreshold1, TvbDownBinsTempThreshold1
1794 <b>Revision 60</b>: - Add GameComptibilityMode
1795 <b>Revision 61</b>: - Deprecated SafModeDisableBiosGuard
1796 <b>Revision 62</b>: - Deprecated PllMaxBandingRatio
1797 <b>Revision 63</b>: - Add FllOcModeEn, FllOverclockMode
1798 <b>Revision 64</b>: - Added PerCoreDisable1, PerCoreDisableOriMask and Deprecated PerCoreDisable, PerAtomDisable.
1799 <b>Revision 65</b>: - Add Etvb
1800 **/
1801 #define CPU_SETUP_REVISION 65
1802
1803 typedef struct {
1804 UINT8 Revision;
1805 UINT8 CpuRatio;
1806 UINT8 CpuDefaultRatio;
1807 UINT8 CpuRatioOverride;
1808 UINT8 Peci;
1809 UINT8 HyperThreading;
1810 //
1811 // CPU: Number of active Big core.
1812 //
1813 UINT8 ActiveCoreCount;
1814 UINT8 BistOnReset;
1815 UINT8 JtagC10PowerGateDisable;
1816 UINT8 EnableGv;
1817 UINT8 RaceToHalt;
1818 UINT8 EnableHwp;
1819 UINT8 EnableItbm;
1820 UINT8 Reserved;
1821
1822 UINT8 EnablePerCorePState;
1823 UINT8 EnableHwpAutoPerCorePstate;
1824 UINT8 EnableHwpAutoEppGrouping;
1825 UINT8 EnableEpbPeciOverride;
1826 UINT8 EnableFastMsrHwpReq;
1827
1828 UINT8 BootFrequency;
1829 UINT8 EnableCx;
1830 UINT8 EnableC1e;
1831 UINT8 TurboMode;
1832 UINT32 PowerLimit1;
1833 UINT8 LongDurationPwrLimitOverride;
1834 UINT8 PowerLimit1Time;
1835 UINT8 PowerLimit2;
1836 UINT32 PowerLimit2Power;
1837 UINT8 PowerLimit3Override;
1838 UINT32 PowerLimit3;
1839 UINT8 PowerLimit3Time;
1840 UINT8 PowerLimit3DutyCycle;
1841 UINT8 PowerLimit3Lock;
1842 UINT8 PowerLimit4Override;
1843 UINT32 PowerLimit4;
1844 UINT8 PowerLimit4Lock;
1845 UINT8 TurboPowerLimitLock;
1846 UINT8 PlatformPowerLimit1Enable;
1847 UINT32 PlatformPowerLimit1Power;
1848 UINT8 PlatformPowerLimit1Time;
1849 UINT8 PlatformPowerLimit2Enable;
1850 UINT32 PlatformPowerLimit2Power;
1851 UINT8 EnergyEfficientPState;
1852 UINT8 CStatePreWake;
1853 UINT8 CStateAutoDemotion;
1854 UINT8 CStateUnDemotion;
1855 UINT8 PkgCStateDemotion;
1856 UINT8 PkgCStateUnDemotion;
1857 UINT8 EnableThermalMonitor;
1858 UINT8 PmgCstCfgCtrlLock;
1859 UINT8 ConfigTdpLevel;
1860 UINT8 ConfigTdpLock;
1861 UINT8 ConfigTdpBios;
1862 UINT8 TimedMwait;
1863 UINT8 PmgCstCfgCtrIoMwaitRedirection;
1864 UINT8 InterruptRedirectMode;
1865
1866 UINT8 HdcControl;
1867 UINT8 PkgCStateLimit;
1868 UINT8 CstateLatencyControl1TimeUnit;
1869 UINT8 CstateLatencyControl2TimeUnit;
1870 UINT8 CstateLatencyControl3TimeUnit;
1871 UINT8 CstateLatencyControl4TimeUnit;
1872 UINT8 CstateLatencyControl5TimeUnit;
1873 UINT16 CstateLatencyControl1Irtl;
1874 UINT16 CstateLatencyControl2Irtl;
1875 UINT16 CstateLatencyControl3Irtl;
1876 UINT16 CstateLatencyControl4Irtl;
1877 UINT16 CstateLatencyControl5Irtl;
1878
1879 UINT32 Custom1PowerLimit1Power;
1880 UINT32 Custom1PowerLimit2Power;
1881 UINT8 Custom1PowerLimit1Time;
1882 UINT8 Custom1TurboActivationRatio;
1883 UINT32 Custom2PowerLimit1Power;
1884 UINT32 Custom2PowerLimit2Power;
1885 UINT8 Custom2PowerLimit1Time;
1886 UINT8 Custom2TurboActivationRatio;
1887 UINT32 Custom3PowerLimit1Power;
1888 UINT32 Custom3PowerLimit2Power;
1889 UINT8 Custom3PowerLimit1Time;
1890 UINT8 Custom3TurboActivationRatio;
1891 UINT8 TStatesEnable;
1892 UINT8 EnableProcHot;
1893 UINT8 DisableProcHotOut;
1894 UINT8 DisableVrThermalAlert;
1895 UINT8 ProcHotLock;
1896 UINT8 ProcHotResponse;
1897 UINT8 TCCActivationOffset;
1898 UINT8 NumOfCustomPStates;
1899 UINT8 StateRatio[MAX_CUSTOM_P_STATES];
1900 UINT8 StateRatioMax16[MAX_16_CUSTOM_P_STATES];
1901 UINT8 VT;
1902 UINT8 AES;
1903 UINT8 MachineCheck;
1904 UINT8 MonitorMwait;
1905 UINT16 DprSize;
1906 UINT8 HwPrefetcher;
1907 UINT8 AclPrefetch;
1908 UINT8 Txt;
1909 UINT8 LtDprProgramming;
1910 UINT8 ResetAux;
1911 UINT8 AcheckRequest;
1912 UINT8 MsegOpt;
1913 UINT8 MsegSize;
1914
1915 UINT8 EcTurboControlMode;
1916 UINT8 AcBrickCapacity;
1917 UINT8 EcPollingPeriod;
1918 UINT8 EcGuardBandValue;
1919 UINT8 EcAlgorithmSel;
1920
1921 UINT8 IsTurboRatioDefaultsInitialized;
1922 UINT8 FlexRatioOverrideDefault;
1923 UINT8 RatioLimitRatioDefault[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1924 UINT8 RatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1925 UINT8 RatioLimitNumCoreDefault[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1926 UINT8 RatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1927 UINT8 AtomRatioLimitRatioDefault[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1928 UINT8 AtomRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1929 UINT8 AtomRatioLimitNumCoreDefault[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1930 UINT8 AtomRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
1931 UINT8 OverclockingLock;
1932
1933 UINT8 Reserved1;
1934 UINT8 BiosGuardToolsInterface;
1935
1936 UINT8 DebugInterfaceEnable;
1937 UINT8 DebugInterfaceLockEnable;
1938 UINT8 DebugCpuDisabled;
1939
1940 UINT8 EnableC6Dram;
1941 UINT8 EnableSgx; // Deprecated from Revision 41
1942 UINT8 EpochUpdate; // Deprecated from Revision 41
1943 UINT8 ShowEpoch; // Deprecated from Revision 41
1944 UINT32 MaxPrmrrSize; // Deprecated from Revision 41
1945 UINT32 PrmrrSize; // Deprecated from Revision 41
1946 UINT8 ApIdleManner;
1947
1948 UINT8 ProcessorTraceOutputScheme;
1949 UINT8 ProcessorTraceMemSize;
1950 UINT8 ProcessorTraceEnable;
1951
1952 UINT8 SkipStopPbet;
1953 UINT8 ThreeStrikeCounterDisable;
1954 UINT8 EpocFclkFreq;
1955
1956 //
1957 // VR Config. IA = 0, GT =1
1958 //
1959 UINT8 PsysSlope;
1960 UINT16 PsysOffset;
1961 UINT8 PsysOffsetPrefix;
1962 UINT16 PsysPmax;
1963 UINT8 VrConfigEnable[MAX_VR_NUM];
1964 UINT16 AcLoadline[MAX_VR_NUM];
1965 UINT16 DcLoadline[MAX_VR_NUM];
1966 UINT16 Psi1Threshold[MAX_VR_NUM];
1967 UINT16 Psi2Threshold[MAX_VR_NUM];
1968 UINT16 Psi3Threshold[MAX_VR_NUM];
1969 UINT8 Psi3Enable[MAX_VR_NUM];
1970 UINT8 Psi4Enable[MAX_VR_NUM];
1971 UINT16 ImonSlope[MAX_VR_NUM];
1972 UINT16 ImonOffset[MAX_VR_NUM];
1973 UINT8 ImonOffsetPrefix[MAX_VR_NUM];
1974 UINT16 IccMax[MAX_VR_NUM];
1975 UINT16 TdcCurrentLimit[MAX_VR_NUM];
1976 UINT8 TdcEnable[MAX_VR_NUM];
1977 UINT32 TdcTimeWindow[MAX_VR_NUM];
1978 UINT8 TdcLock[MAX_VR_NUM];
1979 UINT8 Irms[MAX_VR_NUM];
1980 UINT16 VrVoltageLimit[MAX_VR_NUM];
1981 UINT32 TccOffsetTimeWindow;
1982 UINT8 TccOffsetClamp;
1983 UINT8 TccOffsetLock;
1984
1985 //
1986 // CPU related
1987 //
1988 UINT8 FlexOverrideEnable;
1989 UINT8 MaxEfficiencyRatio;
1990 UINT8 MaxNonTurboRatio;
1991 UINT8 FlexRatioOverride;
1992
1993 UINT8 BusSpeedEnable;
1994 UINT8 ProcessorBusSpeedOverride;
1995
1996 UINT8 PciePll;
1997 UINT8 EnergyEfficientTurbo;
1998
1999 UINT8 WDTSupportforNextOSBoot;
2000 UINT16 TimeforNextOSBoot;
2001
2002 //
2003 // OverClocking setup options
2004 //
2005 UINT8 OverclockingSupport;
2006
2007 UINT8 CoreRatioExtensionMode;
2008 UINT8 CoreMaxOcRatio;
2009 UINT8 PvdRatioThreshold;
2010 UINT8 CoreVoltageMode;
2011 UINT16 CoreVoltageOverride;
2012 UINT16 CoreVoltageOffset;
2013 UINT8 CoreVoltageOffsetPrefix;
2014 UINT16 CoreExtraTurboVoltage;
2015 UINT8 Avx2RatioOffset;
2016 UINT8 Avx3RatioOffset; // Deprecated from Revision 53
2017 UINT8 RingMaxOcRatio;
2018 UINT8 RingDownBin;
2019 UINT8 RingVoltageMode;
2020 UINT16 RingVoltageOverride;
2021 UINT16 RingVoltageOffset;
2022 UINT8 RingVoltageOffsetPrefix;
2023 UINT16 RingExtraTurboVoltage;
2024
2025 UINT8 EnableAllThermalFunctions;
2026 UINT8 CorePllVoltageOffset;
2027 UINT8 GtPllVoltageOffset;
2028 UINT8 RingPllVoltageOffset;
2029 UINT8 SaPllVoltageOffset;
2030 UINT8 AtomPllVoltageOffset;
2031 UINT8 McPllVoltageOffset;
2032 UINT8 TjMaxOffset;
2033
2034 //
2035 // RFI Setup Options
2036 //
2037 UINT16 FivrRfiFrequency;
2038 UINT8 FivrSpreadSpectrum;
2039
2040 //
2041 // Acoustic Noise Mitigation
2042 //
2043 UINT8 AcousticNoiseMitigation;
2044 UINT8 FastPkgCRampDisable[MAX_VR_NUM];
2045 UINT8 SlowSlewRate[MAX_VR_NUM];
2046 UINT8 EnableMinVoltageOverride;
2047 UINT16 MinVoltageRuntime;
2048 UINT16 MinVoltageC8;
2049
2050 UINT8 HwpInterruptControl;
2051 UINT8 BclkAdaptiveVoltageEnable;
2052
2053 UINT8 PpinSupport;
2054 UINT8 PpinEnableMode;
2055
2056 UINT8 MinRingRatioLimit;
2057 UINT8 MaxRingRatioLimit;
2058
2059 UINT8 SafModeDisableBiosGuard; // Deprecated from Revision 61
2060 // Bclk RFI Frequency for each SAGV point in 10KHz units.
2061 UINT32 BclkRfi10KhzFreq[4];
2062 UINT8 CpuBclkSpread;
2063
2064 UINT8 AcSplitLock;
2065 UINT8 Avx2VoltageScaleFactor;
2066 UINT8 Avx512VoltageScaleFactor; // Deprecated from Revision 53
2067 UINT8 ApplyConfigTdp;
2068 UINT8 HwpLock;
2069 UINT8 TmeEnable;
2070 UINT8 SmmMsrSaveStateEnable;
2071 UINT8 SmmUseDelayIndication;
2072 UINT8 SmmUseBlockIndication;
2073 UINT8 SmmUseSmmEnableIndication;
2074 UINT8 SmmProcTraceEnable;
2075 //
2076 // CPU: Number of active small core.
2077 //
2078 UINT8 ActiveSmallCoreCount;
2079 //
2080 // HyerThreading Disable
2081 //
2082 UINT16 PerCoreHtDisable;
2083 //
2084 // Core VF Offset Support
2085 //
2086 UINT8 CoreVfPointOffsetMode;
2087 UINT8 CoreVfPointCount;
2088 UINT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
2089 UINT8 CoreVfPointOffsetPrefix[CPU_OC_MAX_VF_POINTS];
2090
2091 UINT8 CoreVfConfigScope;
2092 UINT16 PerCoreVoltageOffset[CPU_MAX_BIG_CORES];
2093 UINT8 PerCoreVoltageOffsetPrefix[CPU_MAX_BIG_CORES];
2094 UINT8 Reserved2[2];
2095
2096 //
2097 // Ring VF Offset Support
2098 //
2099 UINT8 RingVfPointOffsetMode;
2100 UINT8 RingVfPointCount;
2101 UINT16 RingVfPointOffset[CPU_OC_MAX_VF_POINTS];
2102 UINT8 RingVfPointOffsetPrefix[CPU_OC_MAX_VF_POINTS];
2103
2104 //
2105 // CPU: Record number of all cores including enabled & disabled.
2106 //
2107 UINT8 AllSmallCoreCount;
2108 UINT8 AllBigCoreCount;
2109
2110 UINT8 DualTauBoost;
2111 //
2112 // ATOM Overclocking
2113 //
2114 UINT8 AtomL2MaxOcRatio; ///<Deprecated from revision 51
2115
2116 UINT8 AtomL2VoltageMode;
2117
2118 UINT16 AtomL2VoltageOverride;
2119
2120 UINT16 AtomL2VoltageOffset;
2121
2122 UINT8 AtomL2VoltageOffsetPrefix;
2123
2124 UINT16 AtomL2ExtraTurboVoltage;
2125
2126 UINT8 AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS];
2127
2128 UINT8 PerCoreRatioOverride;
2129 UINT8 PerCoreRatio[CPU_MAX_BIG_CORES];
2130 //
2131 // Unlimited ICCMAX
2132 //
2133 UINT8 UnlimitedIccMax; // Deprecated from Revision 57
2134
2135 //
2136 // Platform Voltage Override setup options
2137 //
2138 UINT8 VccCoreOverrideEnable; // Deprecated from Revision 44
2139 UINT16 VccCoreOverrideVoltage; // Deprecated from Revision 44
2140 UINT8 VccStOverrideEnable; // Deprecated from Revision 44
2141 UINT16 VccStOverrideVoltage; // Deprecated from Revision 44
2142 UINT8 VccSaOverrideEnable; // Deprecated from Revision 44
2143 UINT16 VccSaOverrideVoltage; // Deprecated from Revision 44
2144 UINT8 VccSfrOcOverrideEnable; // Deprecated from Revision 44
2145 UINT16 VccSfrOcOverrideVoltage; // Deprecated from Revision 44
2146 UINT8 VccSfrOverrideEnable; // Deprecated from Revision 44
2147 UINT16 VccSfrOverrideVoltage; // Deprecated from Revision 44
2148 UINT8 VccIoOverrideEnable; // Deprecated from Revision 44
2149 UINT16 VccIoOverrideVoltage; // Deprecated from Revision 44
2150
2151 //
2152 // VR Core Load Line override
2153 //
2154 UINT8 CoreVrDcLLOverrideEnable;
2155 UINT8 CoreDcLoadline;
2156
2157 //
2158 // Acoustic Noise Mitigation Range for Dynamic Periodicity Alteration (DPA)Tuning
2159 //
2160 UINT8 PreWake;
2161 UINT8 RampUp;
2162 UINT8 RampDown;
2163
2164 UINT8 AvxDisable;
2165 UINT8 Avx3Disable; ///<Deprecated from revision 52
2166 //
2167 // SA/Uncore voltage configurations
2168 //
2169 UINT8 SaVoltageMode;
2170 UINT16 SaVoltageOverride;
2171 UINT16 SaExtraTurboVoltage;
2172
2173 //
2174 // Thermal Velocity Boost options
2175 //
2176 UINT8 TvbRatioClipping;
2177 UINT8 TvbVoltageOptimization;
2178 UINT8 Reserved4[3];
2179
2180 //
2181 // VccIn AUX IMON
2182 //
2183 UINT16 VccInAuxImonIccImax;
2184 UINT16 VccInAuxImonSlope;
2185 UINT16 VccInAuxImonOffset;
2186 UINT8 VccInAuxImonOffsetPrefix;
2187
2188 //
2189 // Vsys
2190 //
2191 UINT8 EnableVsysCritical;
2192 UINT8 VsysFullScale;
2193 UINT8 VsysCriticalThreshold;
2194 UINT8 VsysAssertionDeglitchMantissa;
2195 UINT8 VsysAssertionDeglitchExponent;
2196 UINT8 VsysDeassertionDeglitchMantissa;
2197 UINT8 VsysDeassertionDeglitchExponent;
2198
2199 //
2200 // FIVR SSC Enable
2201 //
2202 UINT8 FivrSpectrumEnable;
2203 //
2204 // CPU BCLK OC Frequency
2205 //
2206 UINT32 CpuBclkOcFrequency;
2207
2208 //
2209 // Processor Disable control
2210 //
2211 UINT8 PerCoreDisable[CPU_MAX_BIG_CORES]; // Deprecated from version 64
2212 UINT8 PerAtomDisable[CPU_MAX_ATOM_CORES]; // Deprecated from version 64
2213
2214 ///
2215 /// VR Power Delivery Design
2216 ///
2217 UINT8 VrPowerDeliveryDesign;
2218
2219 UINT8 CrashLogGprs;
2220
2221 UINT16 PerAtomClusterVoltageOffset[CPU_MAX_ATOM_CLUSTERS];
2222 UINT8 PerAtomClusterVoltageOffsetPrefix[CPU_MAX_ATOM_CLUSTERS];
2223
2224 //
2225 // External voltage rails overrides
2226 //
2227 UINT8 Vcc1p8OverrideEnable;
2228 UINT16 Vcc1p8OverrideVoltage;
2229 UINT8 Vcc1p05OverrideEnable;
2230 UINT16 Vcc1p05OverrideVoltage;
2231 UINT8 VccDd2OverrideEnable;
2232 UINT16 VccDd2OverrideVoltage;
2233 UINT16 IccLimit[MAX_VR_NUM];
2234
2235 //
2236 // IA/GT CEP (Current Excursion Protection) Enable
2237 //
2238 UINT8 IaCepEnable;
2239 UINT8 GtCepEnable;
2240
2241 UINT8 VccInAuxEnable;
2242 UINT16 VccInAuxVoltage;
2243 UINT8 RichtekVccIaEnable;
2244 UINT8 RichtekVccGtEnable;
2245 UINT8 RichtekVccIaFixedVidMode;
2246 UINT8 RichtekVccGtFixedVidMode;
2247 UINT16 RichtekVccIaVoltage;
2248 UINT16 RichtekVccGtVoltage;
2249
2250 //
2251 // CPU DLVR bypass mode Enable/Disable
2252 //
2253 UINT8 DlvrBypassModeEnable;
2254
2255 //
2256 // Sa PLL Frequency Configuration
2257 //
2258 UINT8 SaPllFreqOverride;
2259
2260 //
2261 // PLL Max Banding Ratio overrides.
2262 //
2263 UINT8 PllMaxBandingRatio; // Deprecated from Revision 62
2264
2265 //
2266 // TSC HW Fixup disable
2267 //
2268 UINT8 TscDisableHwFixup;
2269 UINT8 Reserved5[1];
2270
2271 //
2272 // IA/GT ICC MAX settings
2273 //
2274 UINT8 IaIccUnlimitedMode;
2275 UINT16 IaIccMax;
2276 UINT8 GtIccUnlimitedMode;
2277 UINT16 GtIccMax;
2278 UINT8 PerCoreDisableConfiguration;
2279 //
2280 // Legacy Game Compatibility Mode
2281 //
2282 UINT8 GameCompatibilityMode;
2283 //
2284 // TVB controls for Down Bins and Temperature Thresholds
2285 //
2286 UINT8 TvbDownBinsTempThreshold0;
2287 UINT8 TvbTempThreshold0;
2288 UINT8 TvbTempThreshold1;
2289 UINT8 TvbDownBinsTempThreshold1;
2290 UINT8 FllOcModeEn;
2291 UINT8 FllOverclockMode;
2292
2293 UINT32 PerCoreDisableOriMask;
2294 UINT8 PerCoreDisable1[32];
2295 UINT8 Etvb;
2296
2297
2298
2299 } CPU_SETUP;
2300
2301 /**
2302 Making any setup structure change after code frozen
2303 will need to maintain backward compatibility, bump up
2304 structure revision and update below history table\n
2305 <b>Revision 1</b>: - Initial version.
2306 **/
2307 #define CPU_SETUP_VOLATILE_DATA_REVISION 1
2308
2309 typedef struct {
2310 UINT16 CpuFamilyModel;
2311 UINT16 CpuExtendedFamilyModel;
2312 UINT8 CpuStepping;
2313 UINT8 EdramSupported;
2314
2315 //
2316 // Vr Topology
2317 //
2318 UINT8 CoreVrLocked;
2319 UINT8 GtVrLocked;
2320 UINT8 SaVrLocked;
2321 UINT8 TccSupported;
2322 } CPU_SETUP_VOLATILE_DATA;
2323
2324
2325 /**
2326 Making any setup structure change after code frozen
2327 will need to maintain backward compatibility, bump up
2328 structure revision and update below history table\n
2329 <b>Revision 1</b>: - Initial version.
2330 **/
2331 #define TBT_SETUP_VOLATILE_DATA_REVISION 1
2332
2333 typedef struct {
2334 UINT8 DTbtContollersNumber;
2335 UINT8 ITbtRootPortsNumber;
2336 UINT8 TcssCpuXhciPortSupport[MAX_TCSS_USB3_PORTS];
2337 } TBT_SETUP_VOLATILE_DATA;
2338
2339 /**
2340 Making any setup structure change after code frozen
2341 will need to maintain backward compatibility, bump up
2342 structure revision and update below history table\n
2343 <b>Revision 1</b>: - Initial version.
2344 <b>Revision 2</b>: - Add MacPassThrough
2345 <b>Revision 3</b>: - Add One Click Recovery setup variables
2346 <b>Revision 4</b>: - Add Remote Platform Erase setup variables
2347 <b>Revision 5</b>: - Add Cse Data Resilience setup variables
2348 **/
2349
2350 #define ME_SETUP_REVISION 5
2351
2352 typedef struct {
2353 UINT8 Revision;
2354 //
2355 // Intel ME
2356 //
2357 UINT8 MeFirmwareInfo;
2358 UINT8 MeImageType;
2359 UINT8 MeFwDowngrade;
2360 UINT8 CommsHubEnable;
2361
2362 UINT8 HeciTimeouts;
2363 UINT8 DidInitStat;
2364 UINT8 DisableCpuReplacedPolling;
2365 UINT8 DisableMessageCheck;
2366 UINT8 SkipMbpHob;
2367 UINT8 HeciCommunication2;
2368 UINT8 KtDeviceEnable;
2369 UINT8 DisableD0I3SettingForHeci;
2370 UINT8 MctpBroadcastCycle;
2371
2372 UINT8 ChangeEps;
2373 UINT8 UnconfigOnRtcAvailable;
2374 UINT8 MeUnconfigOnRtcClear;
2375 UINT8 CoreBiosDoneEnabled;
2376 UINT8 EndOfPostMessage;
2377 UINT8 MeJhiSupport;
2378
2379 //
2380 // Intel AMT
2381 //
2382 UINT8 Amt;
2383 UINT8 AmtbxHotKeyPressed; ///< @deprecated
2384 UINT8 AmtbxSelectionScreen; ///< @deprecated
2385 UINT8 HideUnConfigureMeConfirm; ///< @deprecated
2386 UINT8 MebxDebugMsg; ///< @deprecated
2387 UINT8 UnConfigureMe;
2388 UINT8 AmtCiraRequest;
2389 UINT8 AmtCiraTimeout; ///< @deprecated
2390 UINT8 UsbProvision;
2391 UINT8 FwProgress;
2392
2393 //
2394 // ASF
2395 //
2396 UINT8 AsfSensorsTable;
2397
2398 //
2399 // WatchDog
2400 //
2401 UINT8 WatchDogEnabled;
2402 UINT16 WatchDogTimerOs;
2403 UINT16 WatchDogTimerBios;
2404
2405 //
2406 // MEBx resolution settings
2407 //
2408 UINT8 MebxNonUiTextMode; ///< @deprecated
2409 UINT8 MebxUiTextMode; ///< @deprecated
2410 UINT8 MebxGraphicsMode; ///< @deprecated
2411
2412 //
2413 // Extend ME/CSME Measurements to TPM-PCR
2414 //
2415 UINT8 ExtendMeMeasuredBoot;
2416
2417 //
2418 // Anti-Rollback SVN
2419 //
2420 UINT8 AutoArbSvnCommit;
2421
2422 //
2423 // ME-SMBIOS 130 capabilities
2424 //
2425 UINT8 BiosReflash;
2426 UINT8 BiosSetup;
2427 UINT8 BiosPause;
2428 UINT8 SecureBootExposureToFw;
2429 UINT8 vProTbtDock;
2430
2431 //
2432 // MAC Pass Through
2433 //
2434 UINT8 MacPassThrough;
2435
2436 //
2437 // One Click Recovery
2438 //
2439 UINT8 OcrBootHttps;
2440 UINT8 OcrBootPba;
2441 UINT8 OcrBootWinRe;
2442 UINT8 OcrAmtDisSecBoot;
2443
2444 //
2445 // Remote Platform Erase
2446 //
2447 UINT8 EnableRpe;
2448 UINT8 RpeSsdEraseRealMode;
2449
2450 // CSE Data Resilience
2451 UINT8 CseDataResilience;
2452
2453 } ME_SETUP;
2454
2455
2456
2457 /**
2458 Making any setup structure change after code frozen
2459 will need to maintain backward compatibility, bump up
2460 structure revision and update below history table\n
2461 <b>Revision 1</b>: - Initial version.
2462 <b>Revision 2</b>: - Adding PEG RTD3 Support Setup Variable
2463 <b>Revision 3</b>: - Remove IedMemEnable.
2464 <b>Revision 4</b>: - Added VmdGlobalMapping
2465 <b>Revision 5</b>: - Added TCSS Tc C-State Limit.
2466 <b>Revision 6</b>: - Adding support for TCSS CPU XHCI Port Disable Override.
2467 <b>Revision 7</b>: - Added DisplayAudioLink
2468 <b>Revision 8</b>: - Added PPR Enable Type
2469 <b>Revision 9</b>: - Added LpddrRttWr and LpddrRttCa
2470 <b>Revision 10</b>: - Added MemoryVddqVoltage, MemoryVppVoltage
2471 <b>Revision 11</b>: - DisableDimmMcXChY changed to DisableMcXChY
2472 <b>Revision 12</b>: - Added PcieRootPortNewFom and DmiNewFom
2473 <b>Revision 13</b>: - Added DmiCdrRelock and PcieRootPortCdrRelock.
2474 <b>Revision 14</b>: - Added DIMMDFE
2475 <b>Revision 15</b>: - Added ExtendedBankHashing
2476 <b>Revision 16</b>: - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
2477 <b>Revision 17</b>: - Deprecated DdrOddRatioMode
2478 <b>Revision 18</b>: - Added DynamicMemoryBoost
2479 <b>Revision 19</b>: - Added HgSupport
2480 <b>Revision 20</b>: - Added Config Fusa
2481 <b>Revision 21</b>: - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
2482 <b>Revision 22</b>: - Deprecated RpFunctionSwap
2483 <b>Revision 23</b>: - Added PcieFunc0LinkDisable
2484 <b>Revision 24</b>: - Added DebugValue
2485 <b>Revision 25</b>: - Added PcieResizableBarSupport
2486 <b>Revision 26</b>: - Added McRefreshRate; Deprecated McRefresh2X
2487 <b>Revision 27</b>: - Added RealtimeMemoryFrequency
2488 <b>Revision 28</b>: - Added PeriodicDcc and LpMode
2489 <b>Revision 29</b>: - Added TcColdPowerSavingFactorSwitch, IomStayInTCColdSeconds and IomBeforeEnteringTCColdSeconds
2490 <b>Revision 30</b>: - Added TX DQS DCC
2491 <b>Revision 31</b>: - Added Timing parameters, tRFCpb, tRFC2, ..., tWTR_S
2492 <b>Revision 32</b>: - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
2493 <b>Revision 33</b>: - Added FreqLimitMixedConfig and FirstDimmBitMask
2494 <b>Revision 34</b>: - Added SAGV SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsUpControl, SagvHeuristicsDownControl
2495 <b>Revision 35</b>: - Added DRAMDCA
2496 <b>Revision 36</b>: - Added DynamicMemoryBoostTrainingFailed
2497 <b>Revision 37</b>: - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
2498 <b>Revision 38</b>: - Deprecated IgdDvmt50TotalAlloc
2499 <b>Revision 39</b>: - Added LctCmdEyeWidth
2500 <b>Revision 40</b>: - FirstDimmBitMaskEcc
2501 <b>Revision 41</b>: - Lp5BankMode
2502 <b>Revision 43</b>: - WRDS
2503 **/
2504
2505 #define SA_SETUP_REVISION 43
2506
2507 typedef struct {
2508 UINT8 Revision;
2509 UINT8 BdatEnable;
2510
2511 //
2512 // Memory related
2513 //
2514 UINT8 XmpProfileEnable;
2515 UINT16 MemoryVoltage;
2516 //
2517 // Memory timing override (these options are used for Custom/User Profile)
2518 //
2519 UINT8 DdrRefClk;
2520 UINT8 DdrRatio;
2521 UINT8 DdrOddRatioMode; // Deprecated from revision 18
2522 UINT8 tCL;
2523 UINT8 tCWL;
2524 UINT16 tFAW;
2525 UINT16 tRAS;
2526 UINT8 tRCDtRP;
2527 UINT16 tREFI;
2528 UINT16 tRFC;
2529 UINT8 tRRD;
2530 UINT8 tRTP;
2531 UINT8 tWR;
2532 UINT8 tWTR;
2533 UINT8 NModeSupport;
2534 //
2535 // Default values to restore memory timings to in case of Platform instability
2536 //
2537 UINT8 tCLDefault;
2538 UINT8 tCWLDefault;
2539 UINT16 tFAWDefault;
2540 UINT16 tRASDefault;
2541 UINT8 tRCDtRPDefault;
2542 UINT16 tREFIDefault;
2543 UINT16 tRFCDefault;
2544 UINT8 tRRDDefault;
2545 UINT8 tRTPDefault;
2546 UINT8 tWRDefault;
2547 UINT8 tWTRDefault;
2548 UINT8 NModeDefault;
2549
2550 UINT16 GtDid; // not a SETUP item, used by BIOS to pass GT SKU DID to SETUP items
2551 UINT8 IgdBootType;
2552 UINT8 DisplayPipeB;
2553 UINT8 LcdPanelType;
2554
2555 UINT8 LcdPanelScaling;
2556
2557 UINT8 EnableRenderStandby;
2558 UINT8 IgdLcdBlc;
2559 UINT8 AlsEnable;
2560 UINT8 ActiveLFP;
2561 UINT8 LfpColorDepth;
2562 UINT8 GTTSize;
2563 UINT8 ApertureSize;
2564 UINT8 GtPsmiSupport;
2565 UINT8 GtPsmiRegionSize;
2566 UINT8 PanelPowerEnable;
2567 UINT8 PmSupport;
2568 UINT8 PeiGraphicsPeimInit;
2569 UINT8 PavpEnable;
2570 UINT8 VbtSelect;
2571 UINT8 VbiosBrightness;
2572 UINT8 CdynmaxClampEnable;
2573 UINT8 CdClock;
2574 UINT8 GtFreqMax;
2575 UINT8 DisableTurboGt;
2576 UINT8 SkipCdClockInit;
2577 UINT8 RC1pFreqEnable;
2578 //
2579 // ICC Related
2580 //
2581 UINT8 BclkOverride;
2582 UINT32 BclkFrequency;
2583
2584 //
2585 // PEG
2586 //
2587 UINT8 PegAspm[4];
2588 UINT8 Peg0Enable;
2589 UINT8 Peg1Enable;
2590 UINT8 Peg2Enable;
2591 UINT8 Peg3Enable;
2592 UINT8 Peg0PowerDownUnusedLanes;
2593 UINT8 Peg1PowerDownUnusedLanes;
2594 UINT8 Peg2PowerDownUnusedLanes;
2595 UINT8 Peg3PowerDownUnusedLanes;
2596
2597
2598
2599 UINT8 PegMaxPayload[4];
2600 UINT8 Peg0LtrEnable;
2601 UINT8 Peg1LtrEnable;
2602 UINT8 Peg2LtrEnable;
2603 UINT8 Peg3LtrEnable;
2604 UINT8 Peg0ObffEnable;
2605 UINT8 Peg1ObffEnable;
2606 UINT8 Peg2ObffEnable;
2607 UINT8 Peg3ObffEnable;
2608 UINT8 InitAspmAfterOprom;
2609 UINT8 PegRootPortHPE[4];
2610
2611
2612
2613 //
2614 // PEG Hotplug Resources
2615 //
2616 UINT8 PegExtraBusRsvd[4];
2617 UINT16 PegMemRsvd[4];
2618 UINT8 PegIoRsvd[4];
2619
2620 UINT8 EpgEnable;
2621 UINT16 Idd3n;
2622 UINT16 Idd3p;
2623
2624 //
2625 // DVMT5.0 Graphic memory setting
2626 //
2627 UINT8 IgdDvmt50PreAlloc;
2628 UINT8 IgdDvmt50TotalAlloc; //Deprecated from revision 38
2629 //
2630 // SA Device Control
2631 //
2632 UINT8 SaDevice4;
2633 UINT8 EnableVtd;
2634 UINT8 EnableAbove4GBMmio;
2635 UINT8 GnaEnable;
2636 UINT8 SaIpuEnable;
2637 UINT8 SaIpuImrConfiguration;
2638 UINT8 EdramTestMode;
2639 UINT8 CpuTraceHubMode;
2640 UINT8 CpuTraceHubMemReg0Size;
2641 UINT8 CpuTraceHubMemReg1Size;
2642 //
2643 // VT-d
2644 //
2645 UINT8 X2ApicOptOut;
2646 UINT8 DmaControlGuarantee;
2647 UINT8 VtdIgdEnable;
2648 UINT8 VtdIpuEnable;
2649 UINT8 VtdIopEnable;
2650 //
2651 // DMI
2652 //
2653 UINT8 DmiMaxLinkSpeed;
2654
2655 UINT8 DmiDeEmphasis;
2656 UINT8 DmiGen3EqPh2Enable;
2657 UINT8 DmiGen3EqPh3Method;
2658 UINT8 DmiGen3ProgramStaticEq;
2659 UINT8 DmiGen3RootPortPreset[8];
2660 UINT8 DmiGen3EndPointPreset[8];
2661 UINT8 DmiGen3EndPointHint[8];
2662 UINT8 DmiGen3RxCtlePeaking[4];
2663 UINT8 DmiAspm;
2664 UINT8 DmiAspmCtrl;
2665 UINT8 DmiAspmL1ExitLatency;
2666 // Stop Grant
2667 UINT8 AutoNsg;
2668 UINT8 NumStopGrant;
2669 // Primary Display Select
2670 UINT8 PrimaryDisplay;
2671 UINT8 PcieCardSelect;
2672 UINT16 DelayAfterPwrEn;
2673 UINT16 DelayAfterHoldReset;
2674 UINT8 InternalGraphics;
2675 // Graphics Turbo IMON Current
2676 UINT8 GfxTurboIMON;
2677 UINT8 PcieMultipleSegmentEnabled;
2678 // TCSS
2679 UINT8 TcssItbtPcie0En;
2680 UINT8 TcssItbtPcie1En;
2681 UINT8 TcssItbtPcie2En;
2682 UINT8 TcssItbtPcie3En;
2683 UINT8 TcssXhciEn;
2684 UINT8 TcssXdciEn;
2685 UINT8 TcssDma0En;
2686 UINT8 TcssDma1En;
2687
2688 // VCCST Status
2689 UINT8 TcssVccstStatus;
2690 // USB Override for IOM
2691 UINT8 UsbOverride;
2692 //Enable D3 Cold in TCSS
2693 UINT8 D3ColdEnable;
2694 //Enable D3 hot in TCSS
2695 UINT8 D3HotEnable;
2696
2697 //Enable PTM in TCSS
2698 UINT8 PtmEnabled[MAX_ITBT_PCIE_PORT];
2699 //
2700 // PCIe LTR Configuration
2701 //
2702 UINT8 SaPcieItbtLtrEnable[MAX_ITBT_PCIE_PORT];
2703 UINT8 SaPcieItbtSnoopLatencyOverrideMode[MAX_ITBT_PCIE_PORT];
2704 UINT8 SaPcieItbtSnoopLatencyOverrideMultiplier[MAX_ITBT_PCIE_PORT];
2705 UINT16 SaPcieItbtSnoopLatencyOverrideValue[MAX_ITBT_PCIE_PORT];
2706 UINT8 SaPcieItbtNonSnoopLatencyOverrideMode[MAX_ITBT_PCIE_PORT];
2707 UINT8 SaPcieItbtNonSnoopLatencyOverrideMultiplier[MAX_ITBT_PCIE_PORT];
2708 UINT16 SaPcieItbtNonSnoopLatencyOverrideValue[MAX_ITBT_PCIE_PORT];
2709 UINT8 SaPcieItbtForceLtrOverride[MAX_ITBT_PCIE_PORT];
2710 UINT8 SaPcieItbtLtrConfigLock[MAX_ITBT_PCIE_PORT];
2711 //
2712 // Cpu Telemetry Aggregator (CrashLog)
2713 //
2714 UINT8 CpuCrashLogDevice;
2715
2716 //
2717 // VMD:Settings
2718 //
2719 UINT8 VmdSupported;
2720 UINT8 VmdEnable;
2721 UINT8 VmdPort[VMD_MAX_DEVICES];
2722 UINT8 VmdPortDev[VMD_MAX_DEVICES];
2723 UINT8 VmdPortFunc[VMD_MAX_DEVICES];
2724 UINT8 VmdPortPresent[VMD_MAX_DEVICES];
2725 UINT8 VmdCfgBarSize;
2726 UINT8 VmdCfgBarAttr;
2727 UINT8 VmdMemBarSize1;
2728 UINT8 VmdMemBar1Attr;
2729 UINT8 VmdMemBarSize2;
2730 UINT8 VmdMemBar2Attr;
2731 UINT8 VmdPortAPresent;
2732 UINT8 VmdPortBPresent;
2733 UINT8 VmdPortCPresent;
2734 UINT8 VmdPortDPresent;
2735 UINT8 RaidR0;
2736 UINT8 RaidR1;
2737 UINT8 RaidR10;
2738 UINT8 RaidR5;
2739 UINT8 Rrt;
2740 UINT8 RrtOnlyEsata;
2741 UINT8 OptaneMemory;
2742 UINT8 VmdRsvd[2];
2743 //
2744 // MRC settings
2745 //
2746 UINT8 HobBufferSize;
2747 UINT8 EccSupport;
2748 UINT8 MaxTolud;
2749 UINT16 DdrFreqLimit;
2750 UINT8 SpdProfileSelected;
2751 UINT8 MrcTimeMeasure;
2752 UINT8 MrcFastBoot;
2753 UINT8 RmtPerTask;
2754 UINT8 TrainTrace;
2755 UINT8 ChHashOverride;
2756 UINT8 ChHashEnable;
2757 UINT16 ChHashMask;
2758 UINT8 ChHashInterleaveBit;
2759 UINT8 PerBankRefresh;
2760 UINT8 Vc1ReadMeter;
2761 UINT8 StrongWkLeaker;
2762 UINT8 ForceSingleRank;
2763 UINT8 LpddrMemWriteLatencySet;
2764 UINT8 RetrainOnFastFail;
2765 UINT8 Ddr4OneDpc;
2766 UINT8 SafeMode;
2767 UINT8 BdatTestType;
2768 UINT8 RMTLoopCount;
2769 UINT8 MemTestOnWarmBoot;
2770 UINT8 PowerDownMode;
2771 UINT8 PwdwnIdleCounter;
2772 UINT8 DisPgCloseIdleTimeout;
2773 UINT8 Ibecc;
2774 UINT8 IbeccOperationMode;
2775 UINT8 IbeccProtectedRangeEnable[IBECC_REGIONS_MAX];
2776 UINT32 IbeccProtectedRangeBase[IBECC_REGIONS_MAX];
2777 UINT32 IbeccProtectedRangeMask[IBECC_REGIONS_MAX];
2778 UINT8 EccDftEn;
2779 UINT8 Write0;
2780
2781 UINT8 SaGv;
2782 UINT16 SaGvFreq[4];
2783 UINT8 SaGvGear[4];
2784 UINT8 GearRatio;
2785 //
2786 // MRC Training Algorithms
2787 //
2788 UINT8 ECT;
2789 UINT8 SOT;
2790 UINT8 ERDMPRTC2D;
2791 UINT8 RDMPRT;
2792 UINT8 RCVET;
2793 UINT8 JWRL;
2794 UINT8 EWRTC2D;
2795 UINT8 ERDTC2D;
2796 UINT8 WRTC1D;
2797 UINT8 WRVC1D;
2798 UINT8 RDTC1D;
2799 UINT8 DIMMODTT;
2800 UINT8 DIMMRONT;
2801 UINT8 WRDSEQT;
2802 UINT8 WRSRT;
2803 UINT8 RDODTT;
2804 UINT8 RDEQT;
2805 UINT8 RDAPT;
2806 UINT8 WRTC2D;
2807 UINT8 RDTC2D;
2808 UINT8 CMDVC;
2809 UINT8 WRVC2D;
2810 UINT8 RDVC2D;
2811 UINT8 LCT;
2812 UINT8 RTL;
2813 UINT8 TAT;
2814 UINT8 RMT;
2815 UINT8 MEMTST;
2816 UINT8 ALIASCHK;
2817 UINT8 RCVENC1D;
2818 UINT8 RMC;
2819 UINT8 WRDSUDT;
2820
2821 //
2822 // Power and Thermal Throttling Options
2823 //
2824 UINT8 EnablePwrDn;
2825 UINT8 EnablePwrDnLpddr;
2826 UINT8 Refresh2X;
2827 UINT8 LockPTMregs;
2828
2829 UINT8 SrefCfgEna;
2830 UINT16 SrefCfgIdleTmr;
2831 UINT8 ThrtCkeMinDefeat;
2832 UINT8 ThrtCkeMinTmr;
2833 UINT8 ThrtCkeMinDefeatLpddr;
2834 UINT8 ThrtCkeMinTmrLpddr;
2835 UINT8 AllowOppRefBelowWriteThrehold;
2836 UINT8 WriteThreshold;
2837
2838 UINT8 MemoryThermalManagement;
2839 UINT8 PeciInjectedTemp;
2840 UINT8 ExttsViaTsOnBoard;
2841 UINT8 ExttsViaTsOnDimm;
2842 UINT8 VirtualTempSensor;
2843 UINT8 ScramblerSupport;
2844 UINT8 ForceColdReset;
2845 UINT8 DisableMc0Ch0;
2846 UINT8 DisableMc0Ch1;
2847 UINT8 DisableMc0Ch2;
2848 UINT8 DisableMc0Ch3;
2849 UINT8 DisableMc1Ch0;
2850 UINT8 DisableMc1Ch1;
2851 UINT8 DisableMc1Ch2;
2852 UINT8 DisableMc1Ch3;
2853 UINT8 RemapEnable;
2854 UINT8 MrcSafeConfig;
2855 UINT8 LpDdrDqDqsReTraining;
2856 UINT8 RhSelect;
2857 UINT8 Lfsr0Mask;
2858 UINT8 Lfsr1Mask;
2859 UINT8 McRefresh2X; // Deprecated from revision 26, use McRefreshRate instead
2860 UINT8 RefreshPanicWm; // Deprecated from revision 22, use RefreshWm instead
2861 UINT8 RefreshHpWm; // Deprecated from revision 22, use RefreshWm instead
2862 UINT8 MaxRttWr;
2863 UINT8 ExitOnFailure;
2864 UINT8 NewFeatureEnable1;
2865 UINT8 NewFeatureEnable2;
2866 UINT8 RDVC1D;
2867 UINT8 TXTCO;
2868 UINT8 TXTCODQS;
2869 UINT8 VCCDLLBP;
2870 UINT8 CLKTCO;
2871 UINT8 CMDDSEQ;
2872 UINT8 CMDSR;
2873 UINT8 CMDDRUD;
2874 UINT8 DIMMODTCA;
2875 UINT8 PVTTDNLP;
2876 UINT8 RDVREFDC;
2877 UINT8 VDDQT;
2878 UINT8 DCC;
2879 UINT8 RMTBIT;
2880 UINT8 SkipExtGfxScan;
2881 //
2882 // CRID
2883 //
2884 UINT8 CridEnable;
2885
2886 UINT8 SlateIndicatorRT;
2887 UINT8 SlateIndicatorSx;
2888 UINT8 DockIndicatorRT;
2889 UINT8 DockIndicatorSx;
2890 UINT8 IuerButtonEnable;
2891 UINT8 IuerConvertibleEnable;
2892 UINT8 IuerDockEnable;
2893
2894 //
2895 // Uncore Related
2896 //
2897 UINT16 UncoreVoltageOffset;
2898 UINT8 UncoreVoltageOffsetPrefix;
2899
2900 //
2901 // GT related
2902 //
2903 UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override
2904 UINT8 GtVoltageMode; ///< Specifies whether GT voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
2905 UINT16 GtVoltageOffset; ///< The voltage offset applied to GT. Valid range from -1000mv to 1000mv
2906 UINT8 GtVoltageOffsetPrefix;
2907 UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies
2908 UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
2909 UINT8 GtusMaxOcRatio; ///< Maximum GT turbo ratio override
2910 UINT8 GtusVoltageMode; ///< Specifies whether GT unslice voltage is operating in Adaptive or Override mode - 0: Adaptive, 1: Override
2911 UINT16 GtusVoltageOffset; ///< The voltage offset applied to GT unslice. Valid range from -1000mv to 1000mv
2912 UINT8 GtusVoltageOffsetPrefix;
2913 UINT16 GtusVoltageOverride; ///< The GT unslice voltage override which is applied to the entire range of GT frequencies
2914 UINT16 GtusExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV
2915
2916 UINT8 RealtimeMemoryTiming; ///< Realtime memory timing will allow system to perform realtime memory timing changes.
2917 UINT8 BclkChangeWarmReset;
2918 UINT8 BclkChangeContinues;
2919
2920 UINT8 WrcFeatureEnable;
2921
2922 //
2923 // PCI_EXPRESS_CONFIG, MAX root ports
2924 //
2925 UINT8 PcieRootPortEn[CPU_PCIE_MAX_ROOT_PORTS];
2926 UINT8 PcieLaneCm[SA_PEG_MAX_LANE];
2927 UINT8 PcieLaneCp[SA_PEG_MAX_LANE];
2928 UINT8 PcieFiaProgramming;
2929 UINT8 PcieRootPortClockGating[CPU_PCIE_MAX_ROOT_PORTS];
2930 UINT8 PcieRootPortPowerGating[CPU_PCIE_MAX_ROOT_PORTS];
2931 UINT8 PcieComplianceTestMode;
2932 UINT8 RpFunctionSwap; //@deprecated
2933 UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE];
2934 UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE];
2935 UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE];
2936 UINT8 PegGen4RootPortPreset[SA_PEG_MAX_LANE];
2937 UINT8 PegGen4EndPointPreset[SA_PEG_MAX_LANE];
2938 UINT8 PegGen4EndPointHint[SA_PEG_MAX_LANE];
2939 UINT8 PcieRootPortLinkDownGpios;
2940 UINT8 PcieRootPortClockReqMsgEnable[CPU_PCIE_MAX_ROOT_PORTS];
2941 UINT8 PcieSlotSelection;
2942 UINT8 PcieRootPortHPE[CPU_PCIE_MAX_ROOT_PORTS];
2943 UINT8 PcieRootPortSI[CPU_PCIE_MAX_ROOT_PORTS];
2944 UINT8 PcieRootPortPMCE[CPU_PCIE_MAX_ROOT_PORTS];
2945 UINT8 PcieRootPortTHS[CPU_PCIE_MAX_ROOT_PORTS];
2946 UINT8 PcieRootPortACS[CPU_PCIE_MAX_ROOT_PORTS];
2947 UINT8 PcieRootPortAER[CPU_PCIE_MAX_ROOT_PORTS];
2948 UINT8 PcieRootPortURE[CPU_PCIE_MAX_ROOT_PORTS];
2949 UINT8 PcieRootPortFEE[CPU_PCIE_MAX_ROOT_PORTS];
2950 UINT8 PcieRootPortNFE[CPU_PCIE_MAX_ROOT_PORTS];
2951 UINT8 PcieRootPortCEE[CPU_PCIE_MAX_ROOT_PORTS];
2952 UINT8 PcieRootPortSFE[CPU_PCIE_MAX_ROOT_PORTS];
2953 UINT8 PcieRootPortSNE[CPU_PCIE_MAX_ROOT_PORTS];
2954 UINT8 PcieRootPortSCE[CPU_PCIE_MAX_ROOT_PORTS];
2955 UINT8 PcieRootPortDPC[CPU_PCIE_MAX_ROOT_PORTS];
2956 UINT8 PcieRootPortEDPC[CPU_PCIE_MAX_ROOT_PORTS];
2957 UINT8 PcieRootPortSpeed[CPU_PCIE_MAX_ROOT_PORTS];
2958 UINT8 PcieRootPortEqPh3Method[CPU_PCIE_MAX_ROOT_PORTS];
2959 UINT8 PcieRootPortGen4EqPh3Method[CPU_PCIE_MAX_ROOT_PORTS];
2960 UINT8 PcieRootPortGen5EqPh3Method[CPU_PCIE_MAX_ROOT_PORTS];
2961 UINT8 PcieRootPortAspm[CPU_PCIE_MAX_ROOT_PORTS];
2962 UINT8 PcieRootPortL1SubStates[CPU_PCIE_MAX_ROOT_PORTS];
2963 UINT8 PcieRootPortGen3Uptp[CPU_PCIE_MAX_ROOT_PORTS];
2964 UINT8 PcieRootPortGen3Dptp[CPU_PCIE_MAX_ROOT_PORTS];
2965 UINT8 PcieRootPortGen4Uptp[CPU_PCIE_MAX_ROOT_PORTS];
2966 UINT8 PcieRootPortGen4Dptp[CPU_PCIE_MAX_ROOT_PORTS];
2967 UINT8 PcieRootPortGen5Uptp[CPU_PCIE_MAX_ROOT_PORTS];
2968 UINT8 PcieRootPortGen5Dptp[CPU_PCIE_MAX_ROOT_PORTS];
2969 UINT8 PcieRootPortPTM[CPU_PCIE_MAX_ROOT_PORTS];
2970 UINT16 PcieDetectTimeoutMs[CPU_PCIE_MAX_ROOT_PORTS];
2971 UINT8 PcieRootPortMultiVc[CPU_PCIE_MAX_ROOT_PORTS];
2972 UINT8 PcieRootPortMultiVcSupported[CPU_PCIE_MAX_ROOT_PORTS];
2973 //
2974 // PCIe LTR Configuration
2975 //
2976 UINT8 CpuPcieLtrEnable[CPU_PCIE_MAX_ROOT_PORTS];
2977 UINT8 CpuPcieLtrConfigLock[CPU_PCIE_MAX_ROOT_PORTS];
2978 UINT8 CpuPcieSnoopLatencyOverrideMode[CPU_PCIE_MAX_ROOT_PORTS];
2979 UINT8 CpuPcieSnoopLatencyOverrideMultiplier[CPU_PCIE_MAX_ROOT_PORTS];
2980 UINT16 CpuPcieSnoopLatencyOverrideValue[CPU_PCIE_MAX_ROOT_PORTS];
2981 UINT8 CpuPcieNonSnoopLatencyOverrideMode[CPU_PCIE_MAX_ROOT_PORTS];
2982 UINT8 CpuPcieNonSnoopLatencyOverrideMultiplier[CPU_PCIE_MAX_ROOT_PORTS];
2983 UINT16 CpuPcieNonSnoopLatencyOverrideValue[CPU_PCIE_MAX_ROOT_PORTS];
2984 UINT8 CpuPcieForceLtrOverride[CPU_PCIE_MAX_ROOT_PORTS];
2985
2986 //
2987 // FUSA
2988 //
2989 UINT8 DisplayFusaConfigEnable;
2990 UINT8 GraphicFusaConfigEnable;
2991 UINT8 OpioFusaConfigEnable;
2992
2993 UINT8 GtClosEnable;
2994
2995 UINT8 CpuPcieFomsCp[CPU_PCIE_MAX_ROOT_PORTS];
2996 UINT8 DpmemSupport;
2997 UINT8 CpuPcieRootPortPeerToPeerMode[CPU_PCIE_MAX_ROOT_PORTS];
2998 UINT8 VmdGlobalMapping;
2999 //Tc C-State limit
3000 UINT8 TcStateLimit;
3001
3002 // Adding support for TCSS CPU XHCI Port Disable Override
3003 UINT8 CpuUsbPdoProgramming;
3004 UINT8 CpuUsbPortDisable;
3005 UINT8 CpuUsbSsPort[MAX_TCSS_USB3_PORTS];
3006
3007 UINT8 DisplayAudioLink;
3008
3009 // PPR Support
3010 UINT8 PprEnable;
3011 UINT8 MarginLimitCheck;
3012 UINT16 MarginLimitL2;
3013
3014 UINT8 LpddrRttWr;
3015 UINT8 LpddrRttCa;
3016
3017 UINT16 MemoryVddqVoltage;
3018 UINT16 MemoryVppVoltage;
3019 UINT8 PcieRootPortNewFom[CPU_PCIE_MAX_ROOT_PORTS];
3020 UINT8 DmiNewFom;
3021 UINT8 DmiCdrRelock;
3022 UINT8 PcieRootPortCdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
3023 UINT8 DIMMDFE; // MRC: DIMM DFE training
3024 UINT8 ExtendedBankHashing;
3025 UINT8 IbeccErrInjControl;
3026 UINT64 IbeccErrInjAddress;
3027 UINT64 IbeccErrInjMask;
3028 UINT32 IbeccErrInjCount;
3029 UINT8 DynamicMemoryBoost;
3030 UINT8 HgSupport;
3031
3032 //FUSA
3033 UINT8 FusaConfigEnable;
3034 UINT8 FusaRunStartupArrayBist;
3035 UINT8 FusaRunStartupScanBist;
3036 UINT8 FusaRunPeriodicScanBist;
3037 UINT8 Module0Lockstep;
3038 UINT8 Module1Lockstep;
3039 UINT8 RefreshWm;
3040 UINT8 PcieFunc0LinkDisable [CPU_PCIE_MAX_ROOT_PORTS];
3041 UINT32 DebugValue;
3042 UINT8 PcieResizableBarSupport;
3043 UINT8 McRefreshRate;
3044 UINT8 RealtimeMemoryFrequency;
3045 UINT8 PeriodicDcc;
3046 UINT8 LpMode;
3047 UINT8 TcColdPowerSavingFactorSwitch;
3048 UINT8 IomStayInTCColdSeconds;
3049 UINT8 IomBeforeEnteringTCColdSeconds;
3050 UINT8 TXDQSDCC; //MRC: TX DQS DCC Training
3051 UINT16 tRFCpb;
3052 UINT16 tRFC2;
3053 UINT16 tRFC4;
3054 UINT8 tRRD_L;
3055 UINT8 tRRD_S;
3056 UINT8 tWTR_L;
3057 UINT8 tCCD_L;
3058 UINT8 tWTR_S;
3059 UINT16 tRFCpbDefault;
3060 UINT16 tRFC2Default;
3061 UINT16 tRFC4Default;
3062 UINT8 tRRD_LDefault;
3063 UINT8 tRRD_SDefault;
3064 UINT8 tWTR_LDefault;
3065 UINT8 tCCD_LDefault;
3066 UINT8 tWTR_SDefault;
3067 UINT64 EccErrInjAddress;
3068 UINT64 EccErrInjMask;
3069 UINT32 EccErrInjCount;
3070 UINT16 FreqLimitMixedConfig;
3071 UINT8 FirstDimmBitMask;
3072 UINT8 SagvSwitchFactorIA;
3073 UINT8 SagvSwitchFactorGT;
3074 UINT8 SagvSwitchFactorIO;
3075 UINT8 SagvSwitchFactorStall;
3076 UINT8 SagvHeuristicsUpControl;
3077 UINT8 SagvHeuristicsDownControl;
3078 UINT8 DRAMDCA; // MRC: DRAM DCA training
3079 UINT8 DynamicMemoryBoostTrainingFailed;
3080 UINT16 FreqLimitMixedConfig_1R1R_8GB;
3081 UINT16 FreqLimitMixedConfig_1R1R_16GB;
3082 UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB;
3083 UINT16 FreqLimitMixedConfig_2R2R;
3084 UINT16 LctCmdEyeWidth;
3085 UINT8 FirstDimmBitMaskEcc;
3086 UINT8 Lp5BankMode; // MRC: LP5 Bank Mode
3087 UINT8 WRDS;
3088 } SA_SETUP;
3089
3090 /**
3091 Making any setup structure change after code frozen
3092 will need to maintain backward compatibility, bump up
3093 structure revision and update below history table\n
3094
3095 <b>Revision 1</b>: - Initial version.
3096 <b>Revision 2</b>: - Added PchXhciUaol to control UAOL feature enable status
3097 <b>Revision 3</b>: - Added Foxville LAN support
3098 <b>Revision 4</b>: - Deprecated DciModphyPg
3099 <b>Revision 5</b>: - Added Serial Io Debug Uart Power Gating support for Kernel Debug
3100 <b>Revision 6</b>: - Added CpuRootportUsedForHybridStorage and PchRootportUsedForCpuAttach to control Hybrid storage when it iss used with cpu root ports
3101 <b>Revision 7</b>: - Added FUSA IOP config support
3102 <b>Revision 8</b>: - Added AcpiL6dPmeHandling for _L6D. BIOS-ACPI can verify PMEENABLE and PMESTATUS of each device that requires GPE related wake
3103 <b>Revision 9</b>: - Added CpuHybridStorageConnected to store the status of the hybrid device connected to CPU PCIE slot.
3104 <b>Revision 10</b>: - Added PchScsEmmcEnabled, PchScsEmmcHs400Enabled, PchScsEmmcHs400DriverStrength, PchScsEmmcHs400SoftwareTuning for eMMC.
3105 <b>Revision 11</b>: - Added PchSkipVccInConfig.
3106 <b>Revision 12</b>: - Added PchHdaAlc245DmicConfiguration.
3107 <b>Revision 13</b>: - Added Hid Over Spi support for THC.
3108 <b>Revision 14</b>: - Add PchXhciHsiiEnable.
3109 **/
3110
3111 #define PCH_SETUP_REVISION 14
3112 typedef struct {
3113 UINT8 Revision;
3114 UINT8 ExternalDma;
3115 UINT16 RootPortDid; // not a SETUP item, used by BIOS to pass Root Port DID to SETUP items
3116
3117 UINT8 DeepSxMode;
3118 UINT8 LanWakeFromDeepSx;
3119 UINT8 DisableDsxAcPresentPulldown;
3120 UINT8 PmcReadDisable;
3121 UINT8 OsDebugPort;
3122 UINT8 PchLan;
3123 UINT8 DciUsb3TypecUfpDbg;
3124 UINT8 PchEnableDbcObs;
3125 UINT8 PchWakeOnLan;
3126 UINT8 SlpLanLowDc;
3127 UINT8 PchWakeOnWlan;
3128 UINT8 PchWakeOnWlanDeepSx;
3129 UINT8 PchEnergyReport;
3130 UINT8 EnableTcoTimer;
3131 UINT8 PchCrid;
3132 UINT8 PmcLpmS0i2p0En;
3133 UINT8 PmcLpmS0i2p1En;
3134 UINT8 PmcLpmS0i2p2En;
3135 UINT8 PmcLpmS0i3p0En;
3136 UINT8 PmcLpmS0i3p1En;
3137 UINT8 PmcLpmS0i3p2En;
3138 UINT8 PmcLpmS0i3p3En;
3139 UINT8 PmcLpmS0i3p4En;
3140
3141 UINT8 PchRtcMemoryLock;
3142 UINT8 PchBiosLock;
3143 UINT8 UnlockGpioPads;
3144 UINT8 PsOnEnable;
3145
3146 UINT8 Hpet;
3147 UINT8 StateAfterG3;
3148 UINT8 IchPort80Route;
3149 UINT8 EnhancePort8xhDecoding;
3150 UINT8 PciePllSsc;
3151 UINT8 WdtEnable;
3152 UINT8 PchS0ixAutoDemotion;
3153 UINT8 PchLatchEventsC10Exit;
3154 //
3155 // Usb Config
3156 //
3157 UINT8 PchUsbPortDisable;
3158 UINT8 PchUsbHsPort[SETUP_MAX_USB2_PORTS];
3159 UINT8 PchUsbSsPort[SETUP_MAX_USB3_PORTS];
3160 UINT8 PchUsbPdoProgramming;
3161 UINT8 PchUsbOverCurrentEnable;
3162 UINT8 PchXhciOcLock;
3163 UINT8 PchXhciAcLock;
3164 UINT8 PchUsb2SusWellPgEnable;
3165
3166 //
3167 // xDCI Config
3168 //
3169 UINT8 PchXdciSupport;
3170
3171 //
3172 // Sata CONFIG
3173 //
3174 UINT8 PchSata;
3175 UINT8 SataInterfaceMode;
3176 UINT8 SataPort[PCH_MAX_SATA_PORTS];
3177 UINT8 SataHotPlug[PCH_MAX_SATA_PORTS];
3178 UINT8 SataMechanicalSw[PCH_MAX_SATA_PORTS];
3179 UINT8 SataSpinUp[PCH_MAX_SATA_PORTS];
3180 UINT8 SataExternal[PCH_MAX_SATA_PORTS];
3181 UINT8 SataType[PCH_MAX_SATA_PORTS];
3182 UINT8 SataTopology[PCH_MAX_SATA_PORTS];
3183 UINT8 SataRaidR0;
3184 UINT8 SataRaidR1;
3185 UINT8 SataRaidR10;
3186 UINT8 SataRaidR5;
3187 UINT8 SataRaidIrrt;
3188 UINT8 SataRaidOub;
3189 UINT8 SataHddlk;
3190 UINT8 SataLedl;
3191 UINT8 SataRaidIooe;
3192 UINT8 SataRaidSrt;
3193 UINT8 SataRaidOromDelay;
3194 UINT8 SataRstForceForm;
3195 UINT8 SataLegacyOrom;
3196 UINT8 SataRstOptaneMemory;
3197 UINT8 SataRstCpuAttachedStorage;
3198 UINT8 RaidDeviceId;
3199 UINT8 SataSalp;
3200 UINT8 SataTestMode;
3201 UINT8 PxDevSlp[PCH_MAX_SATA_PORTS];
3202 UINT8 EnableDitoConfig[PCH_MAX_SATA_PORTS];
3203 UINT16 DitoVal[PCH_MAX_SATA_PORTS];
3204 UINT8 DmVal[PCH_MAX_SATA_PORTS];
3205
3206 //
3207 // PCI_EXPRESS_CONFIG, MAX 16 root ports
3208 //
3209 UINT8 PcieRootPort8xhDecode;
3210 UINT8 Pcie8xhDecodePortIndex;
3211 UINT8 PcieRootPortPeerMemoryWriteEnable[PCH_MAX_PCIE_ROOT_PORTS];
3212 UINT8 PcieComplianceTestMode;
3213
3214 // @TODO:
3215 // "GetPchMaxPcieClockNum(18)" is for ADL-S specific, and the value is larger than PCH_MAX_PCIE_CLOCKS(16)
3216 // For long term, we need to have a good way to deal with the condition.
3217 UINT8 PchPcieClockUsageOverride[18];
3218 UINT8 PchPcieClkReqSupport[18];
3219
3220 UINT8 PcieRootPortEn[PCH_MAX_PCIE_ROOT_PORTS];
3221 UINT8 PcieRootPortAspm[PCH_MAX_PCIE_ROOT_PORTS];
3222 UINT8 PcieRootPortURE[PCH_MAX_PCIE_ROOT_PORTS];
3223 UINT8 PcieRootPortFEE[PCH_MAX_PCIE_ROOT_PORTS];
3224 UINT8 PcieRootPortNFE[PCH_MAX_PCIE_ROOT_PORTS];
3225 UINT8 PcieRootPortCEE[PCH_MAX_PCIE_ROOT_PORTS];
3226 UINT8 PcieRootPortCTD[PCH_MAX_PCIE_ROOT_PORTS];
3227 UINT8 PcieRootPortPIE[PCH_MAX_PCIE_ROOT_PORTS];
3228 UINT8 PcieRootPortSFE[PCH_MAX_PCIE_ROOT_PORTS];
3229 UINT8 PcieRootPortSNE[PCH_MAX_PCIE_ROOT_PORTS];
3230 UINT8 PcieRootPortSCE[PCH_MAX_PCIE_ROOT_PORTS];
3231 UINT8 PcieRootPortPMCE[PCH_MAX_PCIE_ROOT_PORTS];
3232 UINT8 PcieRootPortHPE[PCH_MAX_PCIE_ROOT_PORTS];
3233 UINT8 PcieRootPortAER[PCH_MAX_PCIE_ROOT_PORTS];
3234 UINT8 PcieRootPortSpeed[PCH_MAX_PCIE_ROOT_PORTS];
3235 UINT8 PcieRootPortTHS[PCH_MAX_PCIE_ROOT_PORTS];
3236 UINT8 PcieRootPortL1SubStates[PCH_MAX_PCIE_ROOT_PORTS];
3237 UINT8 PcieRootPortL1Low[PCH_MAX_PCIE_ROOT_PORTS];
3238 UINT8 PcieRootPortACS[PCH_MAX_PCIE_ROOT_PORTS];
3239 UINT8 PcieRootPortPTM[PCH_MAX_PCIE_ROOT_PORTS];
3240 UINT8 PcieRootPortDPC[PCH_MAX_PCIE_ROOT_PORTS];
3241 UINT8 PcieRootPortEDPC[PCH_MAX_PCIE_ROOT_PORTS];
3242 UINT8 PcieRootPortSI[PCH_MAX_PCIE_ROOT_PORTS];
3243 UINT16 PcieDetectTimeoutMs[PCH_MAX_PCIE_ROOT_PORTS];
3244 UINT8 RpFunctionSwap;
3245
3246 //
3247 // PCIe EQ
3248 //
3249 UINT8 PcieEqOverrideDefault;
3250 UINT8 PcieEqMethod;
3251 UINT8 PcieEqMode;
3252 UINT8 PcieEqPh2LocalTransmitterOverrideEnable;
3253 UINT8 PcieEqPh1DownstreamPortTransmitterPreset;
3254 UINT8 PcieEqPh1UpstreamPortTransmitterPreset;
3255 UINT8 PcieEqPh3NumberOfPresetsOrCoefficients;
3256 UINT8 PcieEqPh3PreCursorList[10];
3257 UINT8 PcieEqPh3PostCursorList[10];
3258 UINT8 PcieEqPh3PresetList[11];
3259 UINT8 PcieEqPh2LocalTransmitterOverridePreset;
3260
3261 //
3262 // PCIe LTR Configuration
3263 //
3264 UINT8 PchPcieLtrEnable[PCH_MAX_PCIE_ROOT_PORTS];
3265 UINT8 PchPcieLtrConfigLock[PCH_MAX_PCIE_ROOT_PORTS];
3266 UINT8 PchPcieSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
3267 UINT8 PchPcieSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
3268 UINT8 PchPcieNonSnoopLatencyOverrideMode[PCH_MAX_PCIE_ROOT_PORTS];
3269 UINT8 PchPcieNonSnoopLatencyOverrideMultiplier[PCH_MAX_PCIE_ROOT_PORTS];
3270 UINT16 PchPcieSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
3271 UINT16 PchPcieNonSnoopLatencyOverrideValue[PCH_MAX_PCIE_ROOT_PORTS];
3272 UINT8 PchPcieForceLtrOverride[PCH_MAX_PCIE_ROOT_PORTS];
3273
3274 //
3275 // DMI Configuration
3276 //
3277 UINT8 PchDmiAspm;
3278
3279 //
3280 // THC Configuration
3281 //
3282 UINT8 ThcPort0Assignment;
3283 UINT8 ThcPort0Clock;
3284 UINT8 ThcPort0WakeOnTouch;
3285 UINT8 ThcPort1Assignment;
3286 UINT8 ThcPort1Clock;
3287 UINT8 ThcPort1WakeOnTouch;
3288
3289 //
3290 // IEH Configuration
3291 //
3292 UINT8 IehMode;
3293
3294 //
3295 // PCI Bridge Resources
3296 //
3297 UINT8 PcieExtraBusRsvd[PCH_MAX_PCIE_ROOT_PORTS];
3298 UINT16 PcieMemRsvd[PCH_MAX_PCIE_ROOT_PORTS];
3299 UINT8 PcieIoRsvd[PCH_MAX_PCIE_ROOT_PORTS];
3300
3301 //
3302 // HD-Audio Configuration
3303 //
3304 UINT8 PchHdAudio;
3305 UINT8 PchHdAudioDsp;
3306 UINT8 PchHdAudioDspUaaCompliance;
3307 UINT8 PchHdaIDisplayCodecDisconnect;
3308 UINT8 PchHdAudioPme;
3309 UINT8 PchHdAudioHdaLinkEnable;
3310 UINT8 PchHdAudioDmicLinkEnable[PCH_MAX_HDA_DMIC_LINK_NUM];
3311 UINT8 PchHdAudioDmicClockSelect[PCH_MAX_HDA_DMIC_LINK_NUM];
3312 UINT8 PchHdAudioSndwLinkEnable[PCH_MAX_HDA_SNDW_LINK_NUM];
3313 UINT8 PchHdAudioSspLinkEnable[PCH_MAX_HDA_SSP_LINK_NUM];
3314 UINT8 PchHdaHdAudioLinkFreq;
3315 UINT8 PchHdaIDisplayLinkFreq;
3316 UINT8 PchHdaIDisplayLinkTmode;
3317 UINT8 PchHdAudioCodecSxWakeCapability;
3318 UINT8 PchHdaAutonomousClockStopSndw[PCH_MAX_HDA_SNDW_LINK_NUM];
3319 UINT8 PchHdaDataOnActiveIntervalSelectSndw[PCH_MAX_HDA_SNDW_LINK_NUM];
3320 UINT8 PchHdaDataOnDelaySelectSndw[PCH_MAX_HDA_SNDW_LINK_NUM];
3321 UINT8 PchHdAudioI2sCodecSelect;
3322 UINT8 PchHdAudioI2sCodecBusNumber;
3323 UINT8 PchHdAudioFeature[HDAUDIO_FEATURES];
3324 UINT8 PchHdAudioPostProcessingMod[HDAUDIO_PP_MODULES];
3325 CHAR16 PchHdAudioPostProcessingModCustomGuid1[GUID_CHARS_NUMBER];
3326 CHAR16 PchHdAudioPostProcessingModCustomGuid2[GUID_CHARS_NUMBER];
3327 CHAR16 PchHdAudioPostProcessingModCustomGuid3[GUID_CHARS_NUMBER];
3328
3329 //
3330 // Interrupt Configuration
3331 //
3332 UINT8 PchIoApic24119Entries;
3333 UINT8 Enable8254ClockGating;
3334
3335 //
3336 // PCH Thermal Throttling
3337 //
3338 UINT8 PchCrossThrottling;
3339 //
3340 // SCS Configuration
3341 //
3342 UINT8 PchScsUfsEnable[PCH_MAX_UFS_DEV_NUM];
3343
3344 //
3345 // Integrated Sensor Hub (ISH) configuration
3346 //
3347 UINT8 PchIshEnable;
3348 UINT8 PchIshSpiEnable[PCH_MAX_ISH_SPI_CONTROLLERS];
3349 UINT8 PchIshSpiCs0Enable[PCH_MAX_ISH_SPI_CONTROLLERS];
3350 UINT8 PchIshUartEnable[PCH_MAX_ISH_UART_CONTROLLERS];
3351 UINT8 PchIshI2cEnable[PCH_MAX_ISH_I2C_CONTROLLERS];
3352 UINT8 PchIshGpEnable[PCH_MAX_ISH_GP_PINS];
3353 UINT8 PchIshPdtUnlock;
3354
3355 //
3356 // Pch Serial Io configuration
3357 //
3358 UINT8 PchSpiCsPolarity[14]; // [PCH_MAX_SERIALIO_SPI_CONTROLLERS * PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
3359 UINT8 PchSerialIoSpi[PCH_MAX_SERIALIO_SPI_CONTROLLERS];
3360 UINT8 PchSpiCsPolaritySelect[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS];
3361 UINT8 PchSerialIoUart[PCH_MAX_SERIALIO_UART_CONTROLLERS];
3362 UINT8 PchUartDmaEnable[PCH_MAX_SERIALIO_UART_CONTROLLERS];
3363 UINT8 PchUartHwFlowCtrl[PCH_MAX_SERIALIO_UART_CONTROLLERS];
3364 UINT8 PchUartPowerGating[PCH_MAX_SERIALIO_UART_CONTROLLERS];
3365 UINT8 PchSerialIoI2c[PCH_MAX_SERIALIO_I2C_CONTROLLERS];
3366 UINT8 PchSerialIoDeviceI2C4Support;
3367 UINT8 PchGpio;
3368 UINT8 PchGpioIrqRoute;
3369 UINT16 PchGpioDebounce;
3370 UINT8 PchGpioTestDevices;
3371 UINT8 PchAdditionalSerialIoDevices;
3372 //
3373 // TraceHub Setup Options
3374 //
3375 UINT8 PchTraceHubMode;
3376 UINT8 PchTraceHubMemReg0Size;
3377 UINT8 PchTraceHubMemReg1Size;
3378 //
3379 // Thermal Throttling Level options
3380 //
3381 UINT8 PchTtLevelSuggestSet;
3382 UINT16 PchThrmT0Level;
3383 UINT16 PchThrmT1Level;
3384 UINT16 PchThrmT2Level;
3385 UINT8 PchThrmTtEnable;
3386 UINT8 PchThrmTtState13Enable;
3387 UINT8 PchThrmTtLock;
3388
3389 //
3390 // DMI Thermal Throttling
3391 //
3392 UINT8 PchDmiTsSuggestSet;
3393 UINT8 PchTs0Width;
3394 UINT8 PchTs1Width;
3395 UINT8 PchTs2Width;
3396 UINT8 PchTs3Width;
3397 UINT8 PchDmiTsawEn;
3398 //
3399 // SATA Thermal Throttling
3400 //
3401 UINT8 PchSataTsSuggestSet;
3402 UINT8 PchP0T1M;
3403 UINT8 PchP0T2M;
3404 UINT8 PchP0T3M;
3405 UINT8 PchP0TDisp;
3406 UINT8 PchP0Tinact;
3407 UINT8 PchP0TDispFinit;
3408 UINT8 PchP1T1M;
3409 UINT8 PchP1T2M;
3410 UINT8 PchP1T3M;
3411 UINT8 PchP1TDisp;
3412 UINT8 PchP1Tinact;
3413 UINT8 PchP1TDispFinit;
3414 //
3415 // CNVi
3416 //
3417 UINT8 CnviMode;
3418 UINT8 CnviWifiCore;
3419 UINT8 CnviBtCore;
3420 UINT8 CnviBtAudioOffload;
3421 UINT8 CnviDdrRfim;
3422 //
3423 // eSPI Setup Options
3424 //
3425 UINT8 PchEspiLgmrEnable;
3426 UINT8 PchEspiHostC10ReportEnable;
3427
3428 //
3429 // SMBUS
3430 //
3431 UINT8 SmbusSpdWriteDisable;
3432 //
3433 // P2SB
3434 //
3435 UINT8 PchSidebandLock;
3436 //
3437 // Flash Protection configuration
3438 //
3439 UINT8 FprrEnable;
3440
3441 //
3442 // Debug Panel
3443 //
3444 UINT8 DciEn;
3445 UINT8 DciDbcMode;
3446 UINT8 DciModphyPg; // @deprecated - This policy is deprecated.
3447 UINT8 PmcDbgMsgEn;
3448
3449 //Hammock Harbor
3450 UINT8 EnableTimedGpio0;
3451 UINT8 EnableTimedGpio1;
3452
3453 //
3454 // FIVR Configuration;
3455 //
3456 UINT8 ExternalV1p05StateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
3457 UINT8 ExternalVnnStateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
3458 UINT8 ExternalVnnSxStateEnable[FIVR_RAIL_S0IX_SX_STATES_MAX];
3459 UINT8 ExternalV1p05SupportedVoltageStates[FIVR_RAIL_EXT_VOLTAGE_STATES_MAX];
3460 UINT8 ExternalVnnSupportedVoltageStates[FIVR_RAIL_EXT_VOLTAGE_STATES_MAX];
3461 UINT8 ExternalVnnSupportedVoltageConfigurations;
3462
3463 UINT8 ExternalV1p05IccMax; // @deprecated - This policy is deprecated, please use ExternalV1p05IccMaximum instead
3464 UINT16 ExternalV1p05Voltage;
3465 UINT8 ExternalVnnIccMax; // @deprecated - This policy is deprecated, please use ExternalVnnIccMaximum instead
3466 UINT16 ExternalVnnVoltage;
3467 UINT8 ExternalVnnSxIccMax; // @deprecated - This policy is deprecated, please use ExternalVnnSxIccMaximum instead
3468 UINT16 ExternalVnnSxVoltage;
3469
3470 UINT8 PchRetToLowCurModeVolTranTime;
3471 UINT8 PchRetToHighCurModeVolTranTime;
3472 UINT8 PchLowToHighCurModeVolTranTime;
3473 UINT16 PchOffToHighCurModeVolTranTime;
3474 UINT8 PchFivrDynPm;
3475
3476 //
3477 // OS IDLE MODE
3478 //
3479 UINT8 PchPmcOsIdleModeEnable;
3480 UINT8 PchLegacyIoLowLatency;
3481
3482 //
3483 // PSF
3484 //
3485 UINT8 PsfTccEnable;
3486
3487 //
3488 // TSN
3489 //
3490 UINT8 PchTsnEnable;
3491 UINT8 PchTsnLinkSpeed;
3492 UINT8 TsnPcsEnabled;
3493
3494 // FUSA
3495 //
3496 UINT8 PsfFusaConfigEnable;
3497
3498 //
3499 // Hybrid Storage
3500 //
3501 UINT8 HybridStorageMode;
3502
3503 UINT8 TsnMultiVcEnable;
3504
3505 UINT16 ExternalV1p05IccMaximum;
3506 UINT16 ExternalVnnIccMaximum;
3507 UINT16 ExternalVnnSxIccMaximum;
3508 UINT8 PmcC10DynamicThresholdAdjustment;
3509
3510 // Extended BIOS Decode Range
3511 UINT8 ExtendedBiosDecodeRangeEnable;
3512
3513 //
3514 // PMC configuration
3515 //
3516 UINT8 PmcAdrEn;
3517 UINT8 PmcAdrTimer1Val;
3518 UINT8 PmcAdrMultiplier1Val;
3519 UINT8 PmcAdrHostPartitionReset;
3520
3521 //
3522 // UAOL setup option
3523 //
3524 UINT8 PchXhciUaol;
3525
3526 //
3527 // Foxville LAN Config
3528 //
3529 UINT8 FoxvilleLanSupport;
3530 UINT8 FoxvilleWakeOnLan;
3531 //
3532 // Serial IO UART - Kernel support
3533 //
3534 UINT8 SerialIoDebugUartPowerGating;
3535
3536 //
3537 // Support for two lanes of Hybrid Storage connected to CPU
3538 //
3539 UINT8 CpuRootportUsedForHybridStorage;
3540 UINT8 PchRootportUsedForCpuAttach;
3541
3542 //
3543 // FUSA IOP config enable option
3544 //
3545 UINT8 IopFusaConfigEnable;
3546 //
3547 // ACPI L6D Handler option
3548 //
3549 UINT8 AcpiL6dPmeHandling;
3550 UINT8 CpuHybridStorageConnected;
3551 //
3552 // EMCC configurationn
3553 //
3554 UINT8 PchScsEmmcEnabled;
3555 UINT8 PchScsEmmcHs400Enabled;
3556 UINT8 PchScsEmmcHs400SoftwareTuning;
3557 UINT8 PchScsEmmcHs400DriverStrength;
3558
3559 UINT8 PchSkipVccInConfig;
3560 UINT8 PchHdaAlc245DmicConfiguration;
3561
3562 //
3563 // THC HidOver SPi
3564 //
3565 UINT8 ThcMode[PCH_MAX_THC_CONTROLLERS];
3566 UINT32 ThcActiveLtr[PCH_MAX_THC_CONTROLLERS];
3567 UINT32 ThcIdleLtr[PCH_MAX_THC_CONTROLLERS];
3568 UINT32 ThcLimitPacketSize[PCH_MAX_THC_CONTROLLERS];
3569 UINT32 ThcPerformanceLimitation[PCH_MAX_THC_CONTROLLERS];
3570 UINT32 ThcHidFlags[PCH_MAX_THC_CONTROLLERS];
3571 UINT32 ThcHidConnectionSpeed[PCH_MAX_THC_CONTROLLERS];
3572 UINT32 ThcHidInputReportBodyAddress[PCH_MAX_THC_CONTROLLERS];
3573 UINT32 ThcHidInputReportHeaderAddress[PCH_MAX_THC_CONTROLLERS];
3574 UINT32 ThcHidOutputReportAddress[PCH_MAX_THC_CONTROLLERS];
3575 UINT32 ThcHidReadOpcode[PCH_MAX_THC_CONTROLLERS];
3576 UINT32 ThcHidWriteOpcode[PCH_MAX_THC_CONTROLLERS];
3577 UINT32 ThcHidResetPadTrigger[PCH_MAX_THC_CONTROLLERS];
3578
3579 UINT8 PchXhciHsiiEnable;
3580 } PCH_SETUP;
3581
3582
3583 /**
3584 Making any setup structure change after code frozen
3585 will need to maintain backward compatibility, bump up
3586 structure revision and update below history table.\n
3587 <b>Revision 1</b>: - Initial version.
3588 **/
3589
3590 #define SI_SETUP_REVISION 1
3591
3592 typedef struct {
3593 UINT8 Revision;
3594 UINT8 PlatformDebugConsent;
3595 //
3596 // PCIe IMR
3597 //
3598 UINT8 PcieImrEnable;
3599 UINT16 PcieImrSize;
3600 UINT8 PcieImrRpLocation;
3601 UINT8 PcieImrRpSelection;
3602 } SI_SETUP;
3603
3604 /**
3605 Making any setup structure change after code frozen
3606 will need to maintain backward compatibility, bump up
3607 structure revision and update below history table\n
3608 <b>Revision 1</b>: - Initial version.
3609 **/
3610 #define DEBUG_SETUP_VOLATILE_DATA_REVISION 1
3611
3612 typedef struct {
3613 UINT8 StreamingTraceSink;
3614 UINT8 TraceHubForceOn;
3615 UINT8 JtagC10PgDis;
3616 UINT8 UsbOverCurrentOvrd;
3617 } DEBUG_SETUP_VOLATILE_DATA;
3618
3619 #define BOARD_INFO_SETUP_REVISION 2
3620
3621 typedef struct {
3622 // @todo decouple Board related variables from SETUP_DATA
3623 UINT16 FabId;
3624 UINT16 BoardBomId;
3625 // UINT8 PchGeneration;
3626 BOOLEAN EcPresent;
3627 UINT8 EcEspiFlashSharingMode;
3628 UINT8 EcMajorRevision;
3629 UINT8 EcMinorRevision;
3630 UINT16 BoardId;
3631 BOOLEAN SpdPresent;
3632 UINT8 PlatformGeneration;
3633 UINT16 DisplayId;
3634 UINT8 EcPeciMode;
3635 } BOARD_INFO_SETUP;
3636
3637 #pragma pack()
3638
3639 #ifndef PLATFORM_SETUP_VARIABLE_NAME
3640 #define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
3641 #endif
3642
3643 #define SETUP_GUID \
3644 { 0xEC87D643, 0xEBA4, 0x4BB5, { 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 } }
3645
3646 #define SA_SETUP_GUID \
3647 { 0x72c5e28c, 0x7783, 0x43a1, { 0x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4 } }
3648
3649 #define ME_SETUP_GUID \
3650 { 0x5432122d, 0xd034, 0x49d2, { 0xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74 } }
3651
3652 #define CPU_SETUP_GUID \
3653 { 0xb08f97ff, 0xe6e8, 0x4193, { 0xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32 } }
3654
3655 #define PCH_SETUP_GUID \
3656 { 0x4570b7f1, 0xade8, 0x4943, { 0x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84 } }
3657
3658 #define SI_SETUP_GUID \
3659 { 0xAAF8E719, 0x48F8, 0x4099, { 0xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D } }
3660
3661 #define DEBUG_CONFIG_GUID \
3662 { 0xDE0A5E74, 0x4E3E, 0x3D96, { 0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97 } }
3663
3664 #define BOARD_INFO_SETUP_GUID \
3665 { 0x1E785E1A, 0x8EC4, 0x49E4, { 0x82, 0x75, 0xFB, 0xBD, 0xED, 0xED, 0x18, 0xE7 } }
3666
3667 #endif
WakeOnRTCS5
VOID WakeOnRTCS5(VOID)
Enables RTC Wake from S5 and fast startup flow.
Definition: PlatformInitAdvancedSmm.c:643
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SiliconPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
SiliconPolicyInitDxe.c File Reference

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation. More...

#include <SiliconPolicyInitDxe.h>
#include <Library/BaseLib.h>
Include dependency graph for SiliconPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS SiliconPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy. More...

Detailed Description

This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file SiliconPolicyInitDxe.c.

Function Documentation

◆ SiliconPolicyInitDxe()

EFI_STATUS SiliconPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel Cpu DXE Platform Policy.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Install the DXE_SI_POLICY_PROTOCOL interface

Definition at line 51 of file SiliconPolicyInitDxe.c.


AlderLake Platform Sample Code: SiliconPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
SiliconPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #include <SiliconPolicyInitDxe.h>
35 #include <Library/BaseLib.h>
36
37 DXE_SI_POLICY_PROTOCOL mSiPolicyData = { 0 };
38
39 /**
40 Initilize Intel Cpu DXE Platform Policy
41
42 @param[in] ImageHandle Image handle of this driver.
43
44 @retval EFI_SUCCESS Initialization complete.
45 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
46 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
47 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
48 **/
49 EFI_STATUS
50 EFIAPI
51 SiliconPolicyInitDxe (
52 IN EFI_HANDLE ImageHandle
53 )
54 {
55 EFI_STATUS Status;
56
57 mSiPolicyData.Revision = DXE_SI_POLICY_PROTOCOL_REVISION;
58 mSiPolicyData.SmbiosOemTypeFirmwareVersionInfo = (UINT8) PcdGet8 (PcdSmbiosOemTypeFirmwareVersionInfo);
59 ///
60 /// Install the DXE_SI_POLICY_PROTOCOL interface
61 ///
62 Status = gBS->InstallMultipleProtocolInterfaces (
63 &ImageHandle,
64 &gDxeSiPolicyProtocolGuid,
65 &mSiPolicyData,
66 NULL
67 );
68 ASSERT_EFI_ERROR (Status);
69 return Status;
70 }
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel Cpu DXE Platform Policy.
Definition: SiliconPolicyInitDxe.c:51
SiliconPolicyInitDxe.h
Header file for the SiliconPolicyInitDxe Driver.
Generated on Wed Jan 5 2022 01:27:32 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SiliconPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
SiliconPolicyInitDxe.h File Reference

Header file for the SiliconPolicyInitDxe Driver. More...

#include <Protocol/FirmwareVolume2.h>
#include <Guid/StatusCodeDataTypeId.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DebugLib.h>
#include <Protocol/SiPolicyProtocol.h>
Include dependency graph for SiliconPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS SiliconPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy. More...

Detailed Description

Header file for the SiliconPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file SiliconPolicyInitDxe.h.

Function Documentation

◆ SiliconPolicyInitDxe()

EFI_STATUS SiliconPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Initilize Intel CPU DXE Policy.

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Install the DXE_SI_POLICY_PROTOCOL interface

Definition at line 51 of file SiliconPolicyInitDxe.c.


AlderLake Platform Sample Code: SiliconPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
SiliconPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the SiliconPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef _SILICON_POLICY_INIT_DXE_H_
36 #define _SILICON_POLICY_INIT_DXE_H_
37
38 #include <Protocol/FirmwareVolume2.h>
39 #include <Guid/StatusCodeDataTypeId.h>
40 #include <Library/MemoryAllocationLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Library/DebugLib.h>
43
44 #include <Protocol/SiPolicyProtocol.h>
45
46 /**
47 Initilize Intel CPU DXE Policy
48
49 @param[in] ImageHandle Image handle of this driver.
50
51 @retval EFI_SUCCESS Initialization complete.
52 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
53 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
54 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
55 **/
56 EFI_STATUS
57 EFIAPI
58 SiliconPolicyInitDxe (
59 IN EFI_HANDLE ImageHandle
60 );
61
62 #endif
SiliconPolicyInitDxe
EFI_STATUS SiliconPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initilize Intel CPU DXE Policy.
Definition: SiliconPolicyInitDxe.c:51
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SioRegs.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SioRegs.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SioRegs.h.


AlderLake Platform Sample Code: SioRegs.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SioRegs.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SIO_REG_H_
35 #define _SIO_REG_H_
36
37 #define REG_LOGICAL_DEVICE 0x07
38 #define ACTIVATE 0x30
39
40 #define BASE_ADDRESS_HIGH0 0x60
41 #define BASE_ADDRESS_LOW0 0x61
42 #define BASE_ADDRESS_HIGH1 0x62
43 #define BASE_ADDRESS_LOW1 0x63
44 #define BASE_ADDRESS_HIGH2 0x64
45 #define BASE_ADDRESS_LOW2 0x65
46 #define BASE_ADDRESS_HIGH3 0x66
47 #define BASE_ADDRESS_LOW3 0x67
48 #define PRIMARY_INTERRUPT_SELECT 0x70
49 #define WAKEUP_ON_IRQ_EN 0x70
50 #define INTERRUPT_TYPE 0x71
51 #define DMA_CHANNEL_SELECT0 0x74
52 #define DMA_CHANNEL_SELECT1 0x75
53
54
55
56 //
57 //Port address for PILOT - III
58 //
59 #define PILOTIII_CHIP_ID 0x03
60 #define PILOTIII_SIO_INDEX_PORT 0x04E
61 #define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1)
62
63 #define PILOTIII_UNLOCK 0x5A
64 #define PILOTIII_LOCK 0xA5
65
66 //
67 // logical device in PILOT-III
68 //
69 #define PILOTIII_SIO_PSR 0x00
70 #define PILOTIII_SIO_COM2 0x01
71 #define PILOTIII_SIO_COM1 0x02
72 #define PILOTIII_SIO_SWCP 0x03
73 #define PILOTIII_SIO_GPIO 0x04
74 #define PILOTIII_SIO_WDT 0x05
75 #define PILOTIII_SIO_KCS3 0x08
76 #define PILOTIII_SIO_KCS4 0x09
77 #define PILOTIII_SIO_KCS5 0x0A
78 #define PILOTIII_SIO_BT 0x0B
79 #define PILOTIII_SIO_SMIC 0x0C
80 #define PILOTIII_SIO_MAILBOX 0x0D
81 #define PILOTIII_SIO_RTC 0x0E
82 #define PILOTIII_SIO_SPI 0x0F
83 #define PILOTIII_SIO_TAP 0x10
84 //
85 // Regisgers for Pilot-III
86 //
87 #define PILOTIII_CHIP_ID_REG 0x20
88 #define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE
89 #define PILOTIII_ACTIVATE ACTIVATE
90 #define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
91 #define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
92 #define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1
93 #define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1
94 #define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
95
96 //
97 // Port address for PC8374
98 //
99 #define PC8374_SIO_INDEX_PORT 0x02E
100 #define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1)
101
102 //
103 // Logical device in PC8374
104 //
105 #define PC8374_SIO_FLOPPY 0x00
106 #define PC8374_SIO_PARA 0x01
107 #define PC8374_SIO_COM2 0x02
108 #define PC8374_SIO_COM1 0x03
109 #define PC8374_SIO_MOUSE 0x05
110 #define PC8374_SIO_KYBD 0x06
111 #define PC8374_SIO_GPIO 0x07
112
113 //
114 // Registers specific for PC8374
115 //
116 #define PC8374_CLOCK_SELECT 0x2D
117 #define PC8374_CLOCK_CONFIG 0x29
118
119 //
120 // Registers for PC8374
121 //
122 #define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE
123 #define PC8374_ACTIVATE ACTIVATE
124 #define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0
125 #define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0
126 #define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT
127 #define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0
128
129 #define PC87427_SERVERIO_CNF2 0x22
130
131
132 //
133 // Pilot III Mailbox Data Register definitions
134 //
135 #define MBDAT00_OFFSET 0x00
136 #define MBDAT01_OFFSET 0x01
137 #define MBDAT02_OFFSET 0x02
138 #define MBDAT03_OFFSET 0x03
139 #define MBDAT04_OFFSET 0x04
140 #define MBDAT05_OFFSET 0x05
141 #define MBDAT06_OFFSET 0x06
142 #define MBDAT07_OFFSET 0x07
143 #define MBDAT08_OFFSET 0x08
144 #define MBDAT09_OFFSET 0x09
145 #define MBDAT10_OFFSET 0x0A
146 #define MBDAT11_OFFSET 0x0B
147 #define MBDAT12_OFFSET 0x0C
148 #define MBDAT13_OFFSET 0x0D
149 #define MBDAT14_OFFSET 0x0E
150 #define MBDAT15_OFFSET 0x0F
151 #define MBST0_OFFSET 0x10
152 #define MBST1_OFFSET 0x11
153 #define MBBINT_OFFSET 0x12
154
155 //
156 // Mailbox Bit definitions...
157 //
158 #define MBBINT_MBBIST_BIT 0x80
159 // If both are there, use the default one
160 //
161 #define W83527_EXIST BIT2
162 #define PC8374_EXIST BIT1
163 #define PILOTIII_EXIST BIT0
164 #define DEFAULT_SIO PILOTIII_EXIST
165 #define DEFAULT_KDB PC8374_EXIST
166
167 #define IPMI_DEFAULT_SMM_IO_BASE 0xca2
168 //
169 // For Pilot III
170 //
171
172 #define PILOTIII_SWC_BASE_ADDRESS 0xA00
173 #define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80
174 #define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84
175 #define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86
176 #define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4
177 #define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5
178 #define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2
179 #define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3
180 #define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600
181 #define PILOTIII_MAILBOX_MASK 0xFFE0
182 #define BMC_KCS_BASE_ADDRESS 0x0CA0
183 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SmbiosPlatformInfoDefault.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
SmbiosPlatformInfoDefault.h File Reference

This file contains Default data for Platform SMBIOS tables. More...

#include <SmbiosPlatformInfoDefinition.h>
#include <../Features/Smbios/SmbiosMiscDxe/SmbiosMiscStrings.h>
Include dependency graph for SmbiosPlatformInfoDefault.h:

Go to the source code of this file.

Macros

#define | DEFAULT_BIOSVENDOR_CHARS { 0,0,0,0,0,0,1,0,0,0,1,1,0,0,1,1,0,0,1,0,0,0,0,0,0,1,1,1,1,0,0,0 }
MISC_BIOS_CHARACTERISTICS.BiosCharacteristics Bit0-1 Reserved1, Bit02 Unknown, Bit03 BiosCharacteristicsNotSupported, Bit04 IsaIsSupported, Bit05 McaIsSupported, Bit06 EisaIsSupported, Bit07 PciIsSupported, Bit08 PcmciaIsSupported, Bit09 PlugAndPlayIsSupported, Bit10 ApmIsSupported, Bit11 BiosIsUpgradable, Bit12 BiosShadowingAllowed, Bit13 VLVesaIsSupported, Bit14 EscdSupportIsAvailable, Bit15 BootFromCdIsSupported Bit16 SelectableBootIsSupported, Bit17 RomBiosIsSocketed, Bit18 BootFromPcmciaIsSupported, Bit19 EDDSpecificationIsSupported, Bit20 JapaneseNecFloppyIsSupported, Bit21 JapaneseToshibaFloppyIsSupported, Bit22 Floppy525_360IsSupported, Bit23 Floppy525_12IsSupported, Bit24 Floppy35_720IsSupported, Bit25 Floppy35_288IsSupported, Bit26 PrintScreenIsSupported, Bit27 Keyboard8042IsSupported, Bit28 SerialIsSupported, Bit29 PrinterIsSupported, Bit30 CgaMonoIsSupported, Bit31 NecPc98, Bit32-63 Reserved for BIOS/System Vendor.
#define | DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS (UINT8)(BIT0 | BIT1 | BIT4 | BIT5)
MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved Bit0 AcpiIsSupported, Bit1 UsbLegacyIsSupported, Bit2 AgpIsSupported, Bit3 I20BootIsSupported, Bit4 Ls120BootIsSupported, Bit5 AtapiZipDriveBootIsSupported, Bit6 Boot1394IsSupported, Bit7 SmartBatteryIsSupported.
#define | DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM (UINT8)(BIT0 | BIT1 | BIT2 | BIT3)
MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved Bit0 BiosBootSpecIsSupported, Bit1 FunctionKeyNetworkBootIsSupported, Bit2 TargetContentDistributionEnabled, Bit3 UefiSpecificationSupported, Bit4 VirtualMachineSupported, Bit5-7 ExtensionByte2Reserved.

Detailed Description

This file contains Default data for Platform SMBIOS tables.

This file should not be altered unless update in SMBIOS Specification.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file SmbiosPlatformInfoDefault.h.


AlderLake Platform Sample Code: SmbiosPlatformInfoDefault.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SmbiosPlatformInfoDefault.h
Go to the documentation of this file.
1 /** @file
2 This file contains Default data for Platform SMBIOS tables. This file should not
3 be altered unless update in SMBIOS Specification.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may not be
31 modified, except as allowed by additional terms of your license agreement.
32
33 @par Specification Reference:
34
35 **/
36
37 #ifndef _SMBIOS_PLATFORM_INFO_DEFAULT_H_
38 #define _SMBIOS_PLATFORM_INFO_DEFAULT_H_
39
40 #include <SmbiosPlatformInfoDefinition.h>
41 #include <../Features/Smbios/SmbiosMiscDxe/SmbiosMiscStrings.h>
42 //
43 // String Macro Definitions for Default Data
44 //
45 #define TO_BE_FILLED 0
46 #define DEFAULT_BIOSVENDOR_SEGMENT TO_BE_FILLED
47 #define DEFAULT_BIOSVENDOR_SIZE TO_BE_FILLED
48 /**
49 MISC_BIOS_CHARACTERISTICS.BiosCharacteristics
50 Bit0-1 Reserved1,
51 Bit02 Unknown,
52 Bit03 BiosCharacteristicsNotSupported,
53 Bit04 IsaIsSupported,
54 Bit05 McaIsSupported,
55 Bit06 EisaIsSupported,
56 Bit07 PciIsSupported,
57 Bit08 PcmciaIsSupported,
58 Bit09 PlugAndPlayIsSupported,
59 Bit10 ApmIsSupported,
60 Bit11 BiosIsUpgradable,
61 Bit12 BiosShadowingAllowed,
62 Bit13 VLVesaIsSupported,
63 Bit14 EscdSupportIsAvailable,
64 Bit15 BootFromCdIsSupported
65 Bit16 SelectableBootIsSupported,
66 Bit17 RomBiosIsSocketed,
67 Bit18 BootFromPcmciaIsSupported,
68 Bit19 EDDSpecificationIsSupported,
69 Bit20 JapaneseNecFloppyIsSupported,
70 Bit21 JapaneseToshibaFloppyIsSupported,
71 Bit22 Floppy525_360IsSupported,
72 Bit23 Floppy525_12IsSupported,
73 Bit24 Floppy35_720IsSupported,
74 Bit25 Floppy35_288IsSupported,
75 Bit26 PrintScreenIsSupported,
76 Bit27 Keyboard8042IsSupported,
77 Bit28 SerialIsSupported,
78 Bit29 PrinterIsSupported,
79 Bit30 CgaMonoIsSupported,
80 Bit31 NecPc98,
81 Bit32-63 Reserved for BIOS/System Vendor
82 **/
83 #define DEFAULT_BIOSVENDOR_CHARS { 0,0,0,0,0,0,1,0,0,0,1,1,0,0,1,1,0,0,1,0,0,0,0,0,0,1,1,1,1,0,0,0 }
84 /**
85 MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved
86 Bit0 AcpiIsSupported,
87 Bit1 UsbLegacyIsSupported,
88 Bit2 AgpIsSupported,
89 Bit3 I20BootIsSupported,
90 Bit4 Ls120BootIsSupported,
91 Bit5 AtapiZipDriveBootIsSupported,
92 Bit6 Boot1394IsSupported,
93 Bit7 SmartBatteryIsSupported
94 **/
95 #define DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS (UINT8)(BIT0 | BIT1 | BIT4 | BIT5)
96 /**
97 MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved
98 Bit0 BiosBootSpecIsSupported,
99 Bit1 FunctionKeyNetworkBootIsSupported,
100 Bit2 TargetContentDistributionEnabled,
101 Bit3 UefiSpecificationSupported,
102 Bit4 VirtualMachineSupported,
103 Bit5-7 ExtensionByte2Reserved
104 **/
105 #define DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM (UINT8)(BIT0 | BIT1 | BIT2 | BIT3)
106 #define DEFAULT_BIOSVENDOR_EC_RELEASE 0xFF
107 #define DEFAULT_SYSINFO_PRODUCTNAME L"Client Platform"
108 #define DEFAULT_SYSINFO_VERSION L"0.1"
109 #define DEFAULT_SYSINFO_FAMILY L"Client System"
110 #define DEFAULT_BOARDINFO_PRODUCTNAME L"RVP/SDS"
111 #define DEFAULT_BOARDINFO_MANUFACTURER L"Intel Corporation"
112 #define DEFAULT_BOARDINFO_VERSION L"FAB"
113 #define DEFAULT_BOARDINFO_FLAGS { 1,0,0,0,0,0 }
114 #define DEFAULT_BOARDINFO_CHASSIS L"Part Component"
115 #define DEFAULT_CHASSISINFO_MANUFACTURER L"Intel Corporation"
116 #define DEFAULT_CHASSISINFO_VERSION L"0.1"
117 #define DEFAULT_CHASSISINFO_OEM { 0,0,0,0 }
118 #define DEFAULT_CHASSISINFO_HEIGHT 0
119 #define DEFAULT_CHASSISINFO_POWER_CORDS_NUM 1
120 #define DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR L"None"
121 /* Default Port Info { IsPublishRequired, InternalDesignator, InternalConnectorType, ExternalDesignator, InternalConnectorType, PortType } */
122 #define DEFAULT_PORT_INFO { Required, DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR, PortConnectorTypeNone, DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR, PortConnectorTypeNone, PortTypeNone }
123 #define DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION L"To Be Filled by O.E.M."
124 #define DEFAULT_CONFIG_OPTIONS_STRING L"JUMPER:OPTIONS; NA:NA"
125 #define DEFAULT_BIOS_LANG_INFO_LANGUAGES { L"enUS" }
126 #define DEFAULT_BIOS_LANG_INFO_INSTALL_LANGUAGES MAX_LANGUAGES
127 #define DEFAULT_PORTABLE_BATTERY_LOCATION L"Battery Location"
128 #define DEFAULT_PORTABLE_BATTERY_MANUFACTURER L"Battery Manufacturer"
129 #define DEFAULT_PORTABLE_BATTERY_MANUFACTURER_DATE L"Battery Manufacture Date"
130 #define DEFAULT_PORTABLE_BATTERY_SERIAL_NUMBER L"Battery Serial Number"
131 #define DEFAULT_PORTABLE_BATTERY_DEVICE_NAME L"Battery"
132 /* Default Portable Battery Info { IsPublishRequired, BatteryType, Location, Manufacturer, ManufactureDate, SerialNumber, DevName, DevChemistry, DevCapacity, Voltage, SbdsVersion, MaxErrorInBatteryData, SbdsSerialNumber, SbdsManufactureDate, SbdsDeviceChemistry, CapacityMultiplier, Oem }*/
133 #define DEFAULT_PORTABLE_BATTERY_INFO { Required, Unknown, L"Battery Location", L"Battery Manufacturer", L"Battery Manufacture Date", L"Battery Serial Number", L"Battery", PortableBatteryDeviceChemistryUnknown, 0, 0, L"SBDS Version", 0, 0, 0, L"SBDS Device Chemistry", 1, 0, }
134 /* Default Cooling Device Info { IsPublishRequired, Type, Status, Group, Oem, Speed, Description } */
135 #define DEFAULT_COOLING_DEVICE_INFO { Required, CoolingDeviceTypeUnknown, CoolingDeviceStatusUnknown, 0x01, 0x0, 0x8000, L"Cooling Device" }
136 #define DEFAULT_COOLING_DEVICE_DESC L"Cooling Device"
137 #define TO_BE_FILLED_BY_OEM_STR L"To Be Filled by O.E.M."
138 #define DEFAULT_POWER_SUPPLY_INPUT_VOLT_PROBE 0
139 #define DEFAULT_POWER_SUPPLY_COOLING_DEVICE 0x0A
140 #define DEFAULT_POWER_SUPPLY_INPUT_CURR_PROBE 0
141 #define DEFAULT_POWER_SUPPLY_INFO_GROUP 0x1
142 #define DEFAULT_POWER_SUPPLY_INFO_POWER_CAPACITY 0x8000
143 /* Default Power Supply Characteristics { Bit0 HotReplaceable, Bit1 Present, Bit2 Unplugged, Bit3-6 InputVoltageRangeSwitch, Bit7-9 Status, Bit10-13 Type, Bit14-15 Reserved } */
144 #define DEFAULT_POWER_SUPPLY_INFO_CHARACTERISTICS { FALSE, TRUE, FALSE, InputVoltRangeSwitchUnknown, PowerSupplyStatusUnknown, PowerSupplyTypeUnknown, 0x0 }
145 /* Default OnBoard Device Extended Info { IsPublishRequired, Designation, DeviceType, DeviceStatus, DeviceInstance, Segment, Bus, DevFunc } */
146 #define DEFAULT_ONBOARD_DEV_EXT_INFO { Required, DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION, OnBoardDeviceExtendedTypeUnknown, Enabled, 0, 0xFF, 0xFF, 0xFF }
147 #define DEFAULT_SLOT_DESIGN L"PCI-Express #" // Slot Designation
148 #define DEFAULT_EXTENDED_BIOS_ROM_SIZE 0
149 #define DEFAULT_EXTENDED_BIOS_ROM_UNIT 0
150 //
151 // Default Bios Vendor Info for SMBIOS Type 0
152 //
153
154 SMBIOS_TABLE_TYPE0 mDefaultBiosVendorInfo = {
155 { // Hdr
156 SMBIOS_TYPE_BIOS_INFORMATION, /// Hdr.Type
157 sizeof (SMBIOS_TABLE_TYPE0), /// Hdr.Length
158 0 /// Hdr.Handle
159 },
160 SMBIOS_MISC_STRING_1, // Vendor
161 SMBIOS_MISC_STRING_2, // BiosVersion
162 DEFAULT_BIOSVENDOR_SEGMENT, // BiosSegment
163 SMBIOS_MISC_STRING_3, // BiosReleaseDate
164 DEFAULT_BIOSVENDOR_SEGMENT, // BiosSize = 64K *(n+1) where n=20 for 2MB
165 DEFAULT_BIOSVENDOR_CHARS, // BiosCharacteristics
166 { // BiosCharacteristicsExtensionBytes
167 DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS,
168 DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
169 },
170 0x0, // System BIOS Major Release
171 0x1, // System BIOS Minor Release
172 DEFAULT_BIOSVENDOR_EC_RELEASE, // Embedded controller firmware major Release
173 DEFAULT_BIOSVENDOR_EC_RELEASE, // Embedded controller firmware minor Release
174 { // Extended BIOS Rom Size
175 DEFAULT_EXTENDED_BIOS_ROM_SIZE,
176 DEFAULT_EXTENDED_BIOS_ROM_UNIT
177 }
178 };
179
180 SMBIOS_TABLE_TYPE00_STRINGS mDefaultBiosVendorStrings = {
181 SMBIOS_MISC_TYPE00_VENDOR,
182 SMBIOS_MISC_TYPE00_BIOS_VERSION,
183 SMBIOS_MISC_TYPE00_BIOS_RELEASE_DATE
184 };
185
186 //
187 // Default System Info for SMBIOS Type 1
188 //
189
190 SMBIOS_TABLE_TYPE1 mDefaultSysInfo = {
191 { // Hdr
192 SMBIOS_TYPE_SYSTEM_INFORMATION, /// Hdr.Type
193 sizeof (SMBIOS_TABLE_TYPE1), /// Hdr.Size
194 0 /// Hdr.Handle
195 },
196 SMBIOS_MISC_STRING_1, // SystemManufactrurer
197 SMBIOS_MISC_STRING_2, // SystemProductName
198 SMBIOS_MISC_STRING_3, // SystemVersion
199 SMBIOS_MISC_STRING_4, // SystemSerialNumber
200 { // SystemUuid
201 0x5e24fe9c, 0xc8d0, 0x45bd, { 0xa7, 0x9f, 0x54, 0xea, 0x5f, 0xbd, 0x3d, 0x97 }
202 },
203 SystemWakeupTypeOther, // SystemWakeupType
204 SMBIOS_MISC_STRING_5, // SystemSKUNumber
205 SMBIOS_MISC_STRING_6 // SystemFamily
206 };
207
208 SMBIOS_TABLE_TYPE01_STRINGS mDefaultSysStrings = {
209 SMBIOS_MISC_TYPE01_MANUFACTURER,
210 DEFAULT_SYSINFO_PRODUCTNAME,
211 DEFAULT_SYSINFO_VERSION,
212 SMBIOS_MISC_TYPE01_SERIAL_NUMBER,
213 SMBIOS_MISC_TYPE01_SKU_NUMBER,
214 DEFAULT_SYSINFO_FAMILY
215 };
216
217
218 //
219 // Default Base Board info for RVP Board data
220 //
221 #define DEFAULT_BASE_BOARD_INFO { DEFAULT_BOARDINFO_PRODUCTNAME, DEFAULT_BOARDINFO_MANUFACTURER, DEFAULT_BOARDINFO_VERSION, 0x1, BaseBoardTypeMotherBoard, DEFAULT_BOARDINFO_CHASSIS }
222 BASE_BOARD_INFO mDefaultBaseBoardInfo[] = {
223 DEFAULT_BASE_BOARD_INFO
224 };
225 //
226 // Default BaseBoard Info for SMBIOS Type 2
227 //
228 SMBIOS_TABLE_TYPE2 mDefaultBaseBoardsInfo = {
229 { // Hdr
230 SMBIOS_TYPE_BASEBOARD_INFORMATION, ///< Hdr.Type
231 sizeof (SMBIOS_TABLE_TYPE2), ///< Hdr.Length
232 0 ///< Hdr.Handle
233 },
234 SMBIOS_MISC_STRING_1, ///< Manufacturer
235 SMBIOS_MISC_STRING_2, ///< ProductName
236 SMBIOS_MISC_STRING_3, ///< Version
237 SMBIOS_MISC_STRING_4, ///< SerialNumber
238 SMBIOS_MISC_STRING_5, ///< AssetTag
239 { // FeatureFlags
240 1, ///< Bit0 Motherboard
241 0, ///< Bit1 RequiresDaughterCard
242 0, ///< Bit2 Removable
243 1, ///< Bit3 Replaceable,
244 0, ///< Bit4 HotSwappable
245 0, ///< Bit5-7 Reserved
246 },
247 SMBIOS_MISC_STRING_6, // LocationInChassis
248 0, // ChassisHandle
249 BaseBoardTypeMotherBoard, // BoardType
250 0, // NumberOfContainedObjectHandles
251 { 0 } // ContainedObjectHandles
252 };
253
254 SMBIOS_TABLE_TYPE02_STRINGS mDefaultBaseBoardsStrings = {
255 DEFAULT_BOARDINFO_MANUFACTURER, //Manufacturer
256 DEFAULT_BOARDINFO_PRODUCTNAME, //ProductName
257 DEFAULT_BOARDINFO_VERSION, //Version
258 SMBIOS_MISC_TYPE02_BOARD_SERIAL_NUMBER, //SerialNumber
259 SMBIOS_MISC_TYPE02_BOARD_ASSET_TAG, //AssetTag
260 DEFAULT_BOARDINFO_CHASSIS //LocationInChassis
261 };
262
263
264 //
265 // Default Chassis info for RVP Board data
266 //
267 #define DEFAULT_CHASSIS_INFO { DEFAULT_CHASSISINFO_MANUFACTURER, MiscChassisTypeOther, DEFAULT_CHASSISINFO_VERSION, ChassisStateSafe, ChassisStateSafe, ChassisStateOther, ChassisSecurityStatusOther, DEFAULT_CHASSISINFO_HEIGHT, DEFAULT_CHASSISINFO_POWER_CORDS_NUM }
268 CHASSIS_INFO mDefaultChssisInfo [] = {
269 DEFAULT_CHASSIS_INFO
270 };
271 //
272 // Default Chassis Info for SMBIOS Type 3
273 //
274 SMBIOS_TABLE_TYPE3 mDefaultChssisInfoInfo = {
275 { // Hdr
276 SMBIOS_TYPE_SYSTEM_ENCLOSURE, ///< Hdr.Type
277 sizeof(SMBIOS_TABLE_TYPE3), ///< Hdr.Length
278 0 ///< Hdr.Handle
279 },
280 SMBIOS_MISC_STRING_1, ///< Manufactrurer
281 0, ///< Type
282 SMBIOS_MISC_STRING_2, ///< Version
283 SMBIOS_MISC_STRING_3, ///< SerialNumber
284 SMBIOS_MISC_STRING_4, ///< AssetTag
285 ChassisStateSafe, ///< BootupState
286 ChassisStateSafe, ///< PowerSupplyState
287 ChassisStateOther, ///< ThermalState
288 ChassisSecurityStatusOther, ///< SecurityStatus
289 { // OemDefined[4]
290 0,
291 0,
292 0,
293 0
294 },
295 0, ///< Height
296 1, ///< NumberofPowerCords
297 0, ///< ContainedElementCount
298 0, ///< ContainedElementRecordLength
299 { // ContainedElements
300 {
301 0, ///< ContainedElementType
302 0, ///< ContainedElementMinimum
303 0 ///< ContainedElementMaximum
304 }
305 }
306 };
307
308 SMBIOS_TABLE_TYPE03_STRINGS mDefaultChssisInfoStrings = {
309 DEFAULT_CHASSISINFO_MANUFACTURER, //Manufacturer
310 DEFAULT_CHASSISINFO_VERSION, //Version
311 SMBIOS_MISC_CHASSIS_SERIAL_NUMBER, //SerialNumber
312 SMBIOS_MISC_CHASSIS_ASSET_TAG, //AssetTag
313 SMBIOS_MISC_CHASSIS_SKU_NUMBER //SkuNumber
314 };
315
316 //
317 // Default Port Info for SMBIOS Type 8
318 //
319
320 SMBIOS_TABLE_TYPE8 mDefaultPortConnectorsInfo = {
321 { // Hdr
322 SMBIOS_TYPE_PORT_CONNECTOR_INFORMATION, ///< Hdr.Type
323 sizeof(SMBIOS_TABLE_TYPE8), ///< Hdr.Length
324 0 ///< Hdr.Handle
325 },
326 SMBIOS_MISC_STRING_1, ///< InternalConnectorDesignator
327 PortConnectorTypeNone, ///< InternalConnectorType
328 SMBIOS_MISC_STRING_2, ///< ExternalConnectorDesignator
329 PortConnectorTypeNone, ///< ExternalConnectorType
330 PortTypeNone ///< PortType
331 };
332
333 SMBIOS_TABLE_TYPE8_STRINGS mDefaultPortConnectorsStrings = {
334 DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR,
335 DEFAULT_PORT_INFO_INT_EXT_DESIGNATOR
336 };
337
338 //
339 // Default Supported Port Connectors for RVP Board data
340 //
341 #define DEFAULT_PORT_CONNECTORS_SUPPORT 0x1FFFFFFFFFF // Set from Bit0 to Bit 40 in order to enable all port connectors by default.
342
343 //
344 // Default System Config for SMBIOS Type 12
345 //
346
347 SMBIOS_TABLE_TYPE12 mDefaultSysConfigInfo = {
348 {
349 SMBIOS_TYPE_SYSTEM_CONFIGURATION_OPTIONS,
350 sizeof(SMBIOS_TABLE_TYPE12),
351 0
352 },
353 SMBIOS_MISC_STRING_1
354 };
355
356 SMBIOS_TABLE_TYPE12_STRINGS mDefaultSysConfigStrings = {
357 DEFAULT_CONFIG_OPTIONS_STRING //StringCount
358 };
359 //
360 // Default Language Info for SMBIOS Type 13
361 //
362
363 SMBIOS_TABLE_TYPE13 mDefaultBiosLangInfo = {
364 { // Hdr
365 SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, ///< Hdr.Type
366 sizeof(SMBIOS_TABLE_TYPE13), ///< Hdr.Length
367 0 ///< Hdr.Handle
368 },
369 DEFAULT_BIOS_LANG_INFO_INSTALL_LANGUAGES, // NumberOfInstallableLanguages
370 Abbreviated, // LanguageFlags
371 { // Reserve[15]
372 0,
373 0,
374 0,
375 0,
376 0,
377 0,
378 0,
379 0,
380 0,
381 0,
382 0,
383 0,
384 0,
385 0,
386 0
387 },
388 SMBIOS_MISC_STRING_1, // CurrentLanguage
389 };
390 SMBIOS_TABLE_TYPE13_STRINGS mDefaultBiosLangStrings[] = {DEFAULT_BIOS_LANG_INFO_LANGUAGES}; //CurrentLanguages
391 //
392 // Default Portable Battery Info for SMBIOS Type 22
393 //
394
395 SMBIOS_TABLE_TYPE22 mDefaultPortableBatteryInfo = {
396 { // Hdr
397 SMBIOS_TYPE_PORTABLE_BATTERY, ///< Hdr.Type
398 sizeof(SMBIOS_TABLE_TYPE22), ///< Hdr.Length
399 0 ///< Hdr.Handle
400 },
401 SMBIOS_MISC_STRING_1, ///< Location
402 SMBIOS_MISC_STRING_2, ///< Manufacturer
403 SMBIOS_MISC_STRING_3, ///< ManufacturerDate
404 SMBIOS_MISC_STRING_4, ///< SerialNumber
405 SMBIOS_MISC_STRING_5, ///< DeviceName
406 PortableBatteryDeviceChemistryUnknown, ///< DeviceChemistry
407 0, ///< DeviceCapacity
408 0, ///< DeviceVoltage
409 SMBIOS_MISC_STRING_NULL, ///< SBDSVersionNumber
410 0xff, ///< MaximumErrorInBatteryData
411 0, ///< SBDSSerialNumber
412 0, ///< SBDSManufactureDate
413 SMBIOS_MISC_STRING_NULL, ///< SBDSDeviceChemistry
414 1, ///< DesignCapacityMultiplier
415 0 ///< OEMSpecific
416 };
417 SMBIOS_TABLE_TYPE22_STRINGS mDefaultPortableBatteryStrings = {
418 DEFAULT_PORTABLE_BATTERY_LOCATION, //Location;
419 DEFAULT_PORTABLE_BATTERY_MANUFACTURER, //Manufacturer;
420 DEFAULT_PORTABLE_BATTERY_MANUFACTURER_DATE, //ManufacturerDate;
421 DEFAULT_PORTABLE_BATTERY_SERIAL_NUMBER, //SerialNumber;
422 DEFAULT_PORTABLE_BATTERY_DEVICE_NAME //DeviceName;
423 };
424
425
426 //
427 // Default Cooling device info for RVP Board data
428 //
429 #define DEFAULT_COOLING_DEV_SUPPORT (BIT0 | BIT1)
430 #define DEFAULT_COOLING_DEV { CoolingDeviceTypeUnknown, L"Cooling Device" }
431
432 COOLING_DEV mDefaultCoolingDev [] = {
433 DEFAULT_COOLING_DEV
434 };
435 //
436 // Default Cooling Device Info for SMBIOS Type 27
437 //
438 SMBIOS_TABLE_TYPE27 mDefaultCoolingDeviceInfo = {
439 { // Hdr
440 SMBIOS_TYPE_COOLING_DEVICE, ///< Hdr.Type
441 sizeof(SMBIOS_TABLE_TYPE27), ///< Hdr.Length
442 0 ///< Hdr.Handle
443 },
444 SMBIOS_MISC_TEMP_PROBE_HANDLE, ///< TempratureProbeHandle
445 { // DeviceTypeAndStatus
446 CoolingDeviceTypeUnknown, ///< DeviceTypeAndStatus.CoolingDevice
447 CoolingDeviceStatusUnknown ///< DeviceTypeAndStatus.CoolingDeviceStatus
448 },
449 0x01, ///< CoolingUnitGroup
450 0, ///< OEMDefined
451 0x8000, ///< NominalSpeed
452 SMBIOS_MISC_STRING_1 ///< Description
453 };
454
455 SMBIOS_TABLE_TYPE27_STRINGS mDefaultCoolingDeviceStrings = {
456 DEFAULT_COOLING_DEVICE_DESC //Description
457 };
458
459 //
460 // Default Boot Info for SMBIOS Type 32
461 //
462
463 SMBIOS_TABLE_TYPE32 mDefaultBootInfo = {
464 { // Hdr
465 SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, ///< Hdr.Type
466 sizeof(SMBIOS_TABLE_TYPE32), ///< Hdr.Length
467 0 ///< Hdr.Handle
468 },
469 { // Reserved[6]
470 0,
471 0,
472 0,
473 0,
474 0,
475 0
476 },
477 BootInformationStatusNoError ///< BootStatus
478 };
479 //
480 // Default System Power Supply Info for SMBIOS Type 39
481 //
482
483 SMBIOS_TABLE_TYPE39 mDefaultPowerSupplyInfo = {
484 { // Hdr
485 SMBIOS_TYPE_SYSTEM_POWER_SUPPLY, ///< Hdr.Type
486 sizeof(SMBIOS_TABLE_TYPE39), ///< Hdr.Length
487 0 ///< Hdr.Handle
488 },
489 DEFAULT_POWER_SUPPLY_INFO_GROUP, ///< PowerUnitGroup
490 SMBIOS_MISC_STRING_1, ///< Location
491 SMBIOS_MISC_STRING_2, ///< DeviceName
492 SMBIOS_MISC_STRING_3, ///< Manufacturer
493 SMBIOS_MISC_STRING_4, ///< SerialNumber
494 SMBIOS_MISC_STRING_5, ///< AssertTagNumber
495 SMBIOS_MISC_STRING_6, ///< ModelPartNumber
496 SMBIOS_MISC_STRING_7, ///< RevisionLevel
497 DEFAULT_POWER_SUPPLY_INFO_POWER_CAPACITY, ///< MaxPowerCapacity
498 DEFAULT_POWER_SUPPLY_INFO_CHARACTERISTICS, // PowerSupplyCharacteristics
499 DEFAULT_POWER_SUPPLY_INPUT_VOLT_PROBE, ///< InputVoltageProbeHandle
500 DEFAULT_POWER_SUPPLY_COOLING_DEVICE, ///< CoolingDeviceHandle
501 DEFAULT_POWER_SUPPLY_INPUT_CURR_PROBE ///< InputCurrentProbeHandle
502 };
503
504 SMBIOS_TABLE_TYPE39_STRINGS mDefaultPowerSupplyStrings = {
505 TO_BE_FILLED_BY_OEM_STR, //Location
506 TO_BE_FILLED_BY_OEM_STR, //DeviceName
507 TO_BE_FILLED_BY_OEM_STR, //Manufacturer
508 TO_BE_FILLED_BY_OEM_STR, //SerialNumber
509 TO_BE_FILLED_BY_OEM_STR, //AssetTagNumber
510 TO_BE_FILLED_BY_OEM_STR, //ModelPartNumber
511 TO_BE_FILLED_BY_OEM_STR //RevisionLevel
512 };
513
514
515
516 //
517 // Default OnBoard Device info for RVP Board data
518 //
519 #define DEFAULT_ONBOARD_DEV_SUPPORT (BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) // Enable all bits to support all On-board devices
520 #define DEFAULT_ONBOARD_DEV_ADDR { 0, 0xFF, 0xFF, 0xFF }
521
522 ONBOARD_DEV_ADDR mDefaultOnboardDevAddr [] = {
523 DEFAULT_ONBOARD_DEV_ADDR
524 };
525 //
526 // Default OnBoard Device Extended Info for SMBIOS Type 41
527 //
528 SMBIOS_TABLE_TYPE41 mDefaultOnBoardDeviceExtendedRecord = {
529 { // Hdr
530 SMBIOS_TYPE_ONBOARD_DEVICES_EXTENDED_INFORMATION, ///< Hdr.Type
531 sizeof(SMBIOS_TABLE_TYPE41), ///< Hdr.Length
532 0 ///< Hdr.Handle
533 },
534 // Device
535 SMBIOS_MISC_STRING_1, ///< ReferenceDesignation
536 OnBoardDeviceExtendedTypeUnknown, ///< DeviceType
537 0, ///< DeviceTypeInstance
538 0, ///< SegmentGroupNum
539 0xFF, ///< BusNum
540 0xFF ///< DevFuncNum
541 };
542
543 SMBIOS_TABLE_TYPE41_STRINGS mDefaultOnBoardDeviceExtendedStrings = {
544 DEFAULT_ONBOARD_DEV_INFO_DESCRIPTION //Description String
545 };
546
547
548 //
549 // The contain of this Product ID info is just for Intel RVP. The table values can be modified
550 // accordingly to OEM/Customer product.
551 //
552 SMBIOS_TABLE_TYPE133_WWAN mDefaultOemType133Wwan = {
553 { // Hdr
554 SMBIOS_TYPE_OEM_133, ///< Hdr.Type
555 sizeof(SMBIOS_TABLE_TYPE133_WWAN), ///< Hdr.Length
556 0 ///< Hdr.Handle
557 },
558 { 0x7895b4f9, 0x924d, 0x410a, { 0x96, 0x39, 0x12, 0x38, 0x62, 0xb2, 0x8a, 0x63 } }, ///< TypeGuid
559 0, ///< Revision
560 0x8086, ///< OemId - same as Vendor ID
561 { 0x08, 0x16, 0x12, 0x20 }, ///< WwanModelId
562 0x80861226, ///< ProductId
563 { 1, 0, 0, 0, 0 }, ///< WwanSkuId
564 0x18577261, ///< ModelInfo
565 NUM_OF_DEV_MODE, ///< NumberOfDeviceMode
566 0 ///< Reserved
567 };
568
569 //
570 // Default OEM Type 136
571 //
572 SMBIOS_TABLE_TYPE136 mDefaultOemType136 = {
573 { // Hdr
574 SMBIOS_TYPE_OEM_136, ///< Hdr.Type
575 sizeof(SMBIOS_TABLE_TYPE136), ///< Hdr.Length
576 0 ///< Hdr.Handle
577 },
578 0, ///< RawData
579 0 ///< Zero
580 };
581
582 //
583 // Default System Slot Info for SMBIOS Type 9
584 //
585 SMBIOS_TABLE_TYPE9 mDefaultSystemSlotRecord = {
586 { // Hdr
587 SMBIOS_TYPE_SYSTEM_SLOTS, ///< Hdr.Type
588 sizeof(SMBIOS_TABLE_TYPE9), ///< Hdr.Length
589 0 ///< Hdr.Handle
590 },
591 SMBIOS_MISC_STRING_1, ///< SlotDesignation;
592 SlotTypePciExpress, ///< SlotType
593 SlotDataBusWidth1X, ///< SlotDataBusWidth;
594 SlotUsageAvailable, ///< CurrentUsage;
595 SlotLengthLong, ///< SlotLength;
596 0, ///< SlotID;
597 { ///< SlotCharacteristics1;
598 0, // Bit0 - CharacteristicsUnknown
599 0, // Bit1 - Provides 5.0 Volts
600 1, // Bit2 - Provides 3.3 Volts
601 0, // Bit3 - SharedSlot
602 0, // Bit4 - PcCard16Supported
603 0, // Bit5 - CardBusSupported
604 0, // Bit6 - ZoomVideoSupported
605 0 // Bit7 - ModemRingResumeSupported
606 },
607 { ///< SlotCharacteristics2;
608 1, // Bit0 - PmeSignalSupported
609 1, // Bit1 - HotPlugDevicesSupported
610 1, // Bit2 - SmbusSignalSupported
611 0 // Bit3-7 - Reserved
612 },
613 0x00, ///< SegmentGroupNum;
614 0xFF, ///< BusNum;
615 0xFF ///< DevFuncNum;
616 };
617
618 SMBIOS_TABLE_TYPE9_STRINGS mDefaultSystemSlotStrings = {
619 DEFAULT_SLOT_DESIGN //SlotDesignation
620 };
621
622 //
623 // Default Smbios Platform Info table
624 //
625 SMBIOS_PLATFORM_INFO mDefaultSmbiosPlatformInfo[] = {
626
627 { (VOID*)(&mDefaultBiosVendorInfo), (VOID*)(&mDefaultBiosVendorStrings), SIZEOF_SMBIOS_STRINGS(00), FALSE, 1 }, // SMBIOS Type 0 - BiosVendor
628
629 { (VOID*)(&mDefaultSysInfo), (VOID*)(&mDefaultSysStrings), SIZEOF_SMBIOS_STRINGS(01), FALSE, 1 }, // SMBIOS Type 1 - SystemManufacturer
630
631 { (VOID*)(&mDefaultBaseBoardsInfo), (VOID*)(&mDefaultBaseBoardsStrings), SIZEOF_SMBIOS_STRINGS(02), FALSE, 1 }, // SMBIOS Type 2 - BaseBoardManufacturer
632
633 { (VOID*)(&mDefaultChssisInfoInfo), (VOID*)(&mDefaultChssisInfoStrings), SIZEOF_SMBIOS_STRINGS(03), FALSE, 1 }, // SMBIOS Type 3 - ChassisManufacturer
634
635 { (VOID*)(&mDefaultBootInfo), NULL, 0, FALSE, 1 }, // SMBIOS Type 32 - BootInfoStatus
636
637 { (VOID*)(&mDefaultBiosLangInfo), (VOID*)(&mDefaultBiosLangStrings[0]), SIZEOF_SMBIOS_STRINGS(13), FALSE, 1 }, // SMBIOS Type 13 - BiosLanguagesInfo
638
639 { (VOID*)(&mDefaultSysConfigInfo), (VOID*)(&mDefaultSysConfigStrings), SIZEOF_SMBIOS_STRINGS(12), FALSE, 1 }, // SMBIOS Type 12 - SystemOptionString
640
641 { (VOID*)(&mDefaultPortConnectorsInfo), (VOID*)(&mDefaultPortConnectorsStrings), SIZEOF_SMBIOS_STRINGS(8), FALSE, 1 }, // SMBIOS Type 8 - PortConnectors
642
643
644 { (VOID*)(&mDefaultOemType133Wwan), NULL, 0, FALSE, 1 }, // SMBIOS Type 133 - OemType133
645
646 { (VOID*)(&mDefaultOemType136), NULL, 0, FALSE, 1 }, // SMBIOS Type 136 - OemType136
647
648 { (VOID*)(&mDefaultPortableBatteryInfo), (VOID*)(&mDefaultPortableBatteryStrings), SIZEOF_SMBIOS_STRINGS(22), FALSE, 1 }, // SMBIOS Type 22 - PortableBattery
649
650 { (VOID*)(&mDefaultCoolingDeviceInfo), (VOID*)(&mDefaultCoolingDeviceStrings), SIZEOF_SMBIOS_STRINGS(27), FALSE, 1 }, // SMBIOS Type 27 - CoolingDevice
651
652 { (VOID*)(&mDefaultPowerSupplyInfo), (VOID*)(&mDefaultPowerSupplyStrings), SIZEOF_SMBIOS_STRINGS(39), FALSE, 1 }, // SMBIOS Type 39 - SystemPowerSupply
653
654 { (VOID*)(&mDefaultOnBoardDeviceExtendedRecord), (VOID*)(&mDefaultOnBoardDeviceExtendedStrings), SIZEOF_SMBIOS_STRINGS(41), FALSE, 1 }, // SMBIOS Type 41 - OnBoardDeviceExtended
655
656 { (VOID*)(&mDefaultSystemSlotRecord), (VOID*)(&mDefaultSystemSlotStrings), SIZEOF_SMBIOS_STRINGS(9), FALSE, 1 } // SMBIOS Type 9 - SystemSlot
657
658 };
659 //
660 // Default Smbios Board info for RVP Board data
661 //
662 SMBIOS_PLATFORM_BOARD_INFO mDefaultSmbiosBoardInfo = {
663 DEFAULT_SYSINFO_PRODUCTNAME, //SystemProductName
664 DEFAULT_SYSINFO_VERSION, //SystemVersion
665 DEFAULT_SYSINFO_FAMILY, //SystemFamily
666 SystemWakeupTypeOther, //SystemWakeUpType
667 &mDefaultBaseBoardInfo[0], //BaseBoard
668 &mDefaultChssisInfo[0], //ChassisInfo
669 DEFAULT_PORT_CONNECTORS_SUPPORT, //SupportedPortConnectors
670 DEFAULT_CONFIG_OPTIONS_STRING, //SystemConfigOptions
671 &mDefaultCoolingDev[0], //CoolingDevCoolingDev
672 DEFAULT_ONBOARD_DEV_SUPPORT, //SupportedOnboardDev
673 &mDefaultOnboardDevAddr[0] //OnBoardDevAddr
674 };
675
676 #endif //_SMBIOS_PLATFORM_INFO_DEFAULT_H_
DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
#define DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM
MISC_BIOS_CHARACTERISTICS_EXTENSION.SystemReserved Bit0 BiosBootSpecIsSupported, Bit1 FunctionKeyNetw...
Definition: SmbiosPlatformInfoDefault.h:105
DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS
#define DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS
MISC_BIOS_CHARACTERISTICS_EXTENSION.BiosReserved Bit0 AcpiIsSupported, Bit1 UsbLegacyIsSupported,...
Definition: SmbiosPlatformInfoDefault.h:95
DEFAULT_BIOSVENDOR_CHARS
#define DEFAULT_BIOSVENDOR_CHARS
MISC_BIOS_CHARACTERISTICS.BiosCharacteristics Bit0-1 Reserved1, Bit02 Unknown, Bit03 BiosCharacterist...
Definition: SmbiosPlatformInfoDefault.h:83
SmbiosPlatformInfoDefinition.h
This file contains definition for Platform SMBIOS Info.


AlderLake Platform Sample Code: SmbiosPlatformInfoDefinition.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SmbiosPlatformInfoDefinition.h File Reference

This file contains definition for Platform SMBIOS Info. More...

#include <IndustryStandard/SmBios.h>
Include dependency graph for SmbiosPlatformInfoDefinition.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This file contains definition for Platform SMBIOS Info.

Revision Reference:
SMBIOS Specification version 3.0.0 from DMTF: http://www.dmtf.org/standards/smbios
Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file SmbiosPlatformInfoDefinition.h.


AlderLake Platform Sample Code: SmbiosPlatformInfoDefinition.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
SmbiosPlatformInfoDefinition.h
Go to the documentation of this file.
1 /** @file
2 This file contains definition for Platform SMBIOS Info.
3
4 @par Revision Reference:
5 SMBIOS Specification version 3.0.0 from DMTF: http://www.dmtf.org/standards/smbios
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 2017 - 2021 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains 'Framework Code' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may not be
33 modified, except as allowed by additional terms of your license agreement.
34
35 @par Specification Reference:
36
37 **/
38
39 #ifndef _SMBIOS_PLATFORM_INFO_DEFINITION_H_
40 #define _SMBIOS_PLATFORM_INFO_DEFINITION_H_
41
42 #include <IndustryStandard/SmBios.h>
43 //
44 // The below enumeration describes the order in which SMBIOS tables are published by SmbiosMiscDxe driver.
45 //
46 typedef enum{
47 BiosVendor = 0,
48 SystemManufacturer,
49 BaseBoardManufacturer,
50 ChassisManufacturer,
51 BootInfoStatus,
52 BiosLanguagesInfo,
53 SystemOptionString,
54 PortConnectors,
55 OemType133Wwan,
56 OemType136,
57 PortableBattery,
58 CoolingDevice,
59 SystemPowerSupply,
60 OnBoardDeviceExtended,
61 SystemSlot
62 }PLATFORM_SMBIOS_DATA_ORDER;
63
64 #define SIZEOF_SMBIOS_STRINGS(Type) (sizeof(SMBIOS_TABLE_TYPE ## Type ## _STRINGS) / sizeof (CHAR16*))
65
66 //
67 // Platform Info for Type 0 - BIOS Vendor
68 //
69 typedef struct {
70 UINT16 Segment;
71 UINT32 Size;
72 MISC_BIOS_CHARACTERISTICS Characteristics;
73 MISC_BIOS_CHARACTERISTICS_EXTENSION CharacteristicsExt;
74 UINT8 EcFwMajorRelease;
75 UINT8 EcFwMinorRelease;
76 }BIOS_VENDOR_INFO_TYPE0;
77
78 //
79 // Platform Info for Type 1 - System Info
80 //
81 typedef struct {
82 CHAR16 *ProductName;
83 CHAR16 *Version;
84 CHAR16 *Family;
85 UINT8 WakeUpType;
86 }SYSTEM_INFO_TYPE1;
87
88 //
89 // Platform Info For Type 2 - Base Board Info
90 //
91 typedef struct {
92 CHAR16 *ProductName;
93 CHAR16 *Manufacturer;
94 CHAR16 *Version;
95 BASE_BOARD_FEATURE_FLAGS FeatureFlags;
96 UINT8 BoardType;
97 CHAR16 *LocationInChassis;
98 }BASEBOARD_INFO_TYPE2;
99
100 //
101 // Platform Info For Type 3 - Chassis Info
102 //
103 typedef struct {
104 CHAR16 *Manufacturer;
105 MISC_CHASSIS_TYPE Type;
106 CHAR16 *Version;
107 MISC_CHASSIS_STATE Bootup;
108 MISC_CHASSIS_STATE PowerSupply;
109 MISC_CHASSIS_STATE Thermal;
110 MISC_CHASSIS_SECURITY_STATE Security;
111 UINT8 Oem[4];
112 UINT8 Height;
113 UINT8 NumberofPowerCords;
114 }CHASSIS_INFO_TYPE3;
115
116 //
117 // Platform Info For Type 8 - Port Connector Information
118 //
119 #define NUM_DEFINED_PORT_TYPES 41
120
121 typedef enum {
122 NotRequired = 0,
123 Required
124 }PUBLISH_REQ;
125
126 typedef struct {
127 PUBLISH_REQ IsPublishRequired;
128 CHAR16 *InternalDesignator;
129 MISC_PORT_CONNECTOR_TYPE InternalConnectorType;
130 CHAR16 *ExternalDesignator;
131 MISC_PORT_CONNECTOR_TYPE ExternalConnectorType;
132 MISC_PORT_TYPE PortType;
133 } PORT_INFO_TYPE8;
134
135 //
136 // Platform Info For Type 12 - System Config Options
137 //
138 typedef struct {
139 CHAR16 *ConfigOptions;
140 }SYSTEM_CONFIG_TYPE12;
141
142 //
143 // Platform Info For Type 13 - BIOS Language Information
144 //
145
146 typedef enum{
147 Long = 0,
148 Abbreviated
149 }LANGUAGES_FORMAT;
150
151 #define MAX_LANGUAGES 1 // TODO: it requires some investigation to update properly
152
153 typedef enum{
154 English = 1,
155 French,
156 Japanese
157 }CURRENT_LANGUAGES;
158
159 typedef struct {
160 CHAR16 *Language[MAX_LANGUAGES];
161 UINT8 InstallableLanguages;
162 LANGUAGES_FORMAT Flags;
163 CURRENT_LANGUAGES CurrentLanguage;
164 }BIOS_LANGUAGE_INFO_TYPE13;
165
166 //
167 // Platform Info For Type 22 - Portable Battery Info
168 //
169 #define NUM_PORTABLE_BATTERIES 3
170
171 typedef enum{
172 Unknown = 0,
173 Real1,
174 Real2,
175 Virtual
176 }BATTERY_TYPE;
177
178 typedef struct {
179 PUBLISH_REQ IsPublishRequired;
180 BATTERY_TYPE BatteryType;
181 CHAR16 *Location;
182 CHAR16 *Manufacturer;
183 CHAR16 *ManufactureDate;
184 CHAR16 *SerialNumber;
185 CHAR16 *DevName;
186 PORTABLE_BATTERY_DEVICE_CHEMISTRY DevChemistry;
187 UINT16 DevCapacity;
188 UINT16 Voltage;
189 CHAR16 *SbdsVersion;
190 UINT8 MaxErrorInBatteryData;
191 UINT16 SbdsSerialNumber;
192 UINT16 SbdsManufactureDate;
193 CHAR16 *SbdsDeviceChemistry;
194 UINT8 CapacityMultiplier;
195 UINT32 Oem;
196 } PORTABLE_BATTERY_INFO_TYPE22;
197
198 //
199 // Platform Info For Type 27 - Cooling Device Info
200 //
201
202 typedef enum{
203 CoolingDeviceTypeOther = 0x1,
204 CoolingDeviceTypeUnknown,
205 CoolingDeviceTypeFan,
206 CoolingDeviceTypeCentrifugalBlower,
207 CoolingDeviceTypeChipFan,
208 CoolingDeviceTypeCabinetFan,
209 CoolingDeviceTypePowerSupplyFan,
210 CoolingDeviceTypeHeatPipe,
211 CoolingDeviceTypeIntegratedRefrigeration,
212 CoolingDeviceTypeActiveCooling = 0x10,
213 CoolingDeviceTypePassiveCooling
214 }COOLING_DEVICE_TYPE;
215
216 typedef enum{
217 CoolingDeviceStatusOther = 1,
218 CoolingDeviceStatusUnknown,
219 CoolingDeviceStatusOk,
220 CoolingDeviceStatusNonCritical,
221 CoolingDeviceStatusCritical,
222 CoolingDeviceStatusNonRecoverable
223 }COOLING_DEVICE_STATUS;
224
225 typedef struct {
226 PUBLISH_REQ IsPublishRequired;
227 COOLING_DEVICE_TYPE Type;
228 COOLING_DEVICE_STATUS Status;
229 UINT8 Group;
230 UINT32 Oem;
231 UINT16 Speed;
232 CHAR16 *Description;
233 } COOLING_DEVICE_INFO_TYPE27;
234
235 //
236 // Platform Info For Type 32 - Boot Info Status
237 //
238 typedef struct {
239 MISC_BOOT_INFORMATION_STATUS_DATA_TYPE BootStatus;
240 }BOOT_INFO_TYPE32;
241
242 //
243 // Platform Info For Type 39 - System Power Supply
244 //
245 typedef enum{
246 InputVoltRangeSwitchOther = 1,
247 InputVoltRangeSwitchUnknown,
248 InputVoltRangeSwitchManual,
249 InputVoltRangeSwitchAutoSwitch,
250 InputVoltRangeSwitchWideRange,
251 InputVoltRangeSwitchNotApplicable,
252 InputVoltRangeSwitchNotReserved
253 }INPUT_VOLT_RANGE_SWITCH;
254
255 typedef enum{
256 PowerSupplyStatusOther = 1,
257 PowerSupplyStatusUnknown,
258 PowerSupplyStatusOk,
259 PowerSupplyStatusNonCritical,
260 PowerSupplyStatusCritical
261 }POWER_SUPPLY_STATUS;
262
263 typedef enum{
264 PowerSupplyTypeOther = 1,
265 PowerSupplyTypeUnknown,
266 PowerSupplyTypeLinear,
267 PowerSupplyTypeSwitching,
268 PowerSupplyTypeBattery,
269 PowerSupplyTypeUps,
270 PowerSupplyTypeConverter,
271 PowerSupplyTypeRegulator,
272 PowerSupplyTypeReserved
273 }POWER_SUPPLY_TYPE;
274
275 typedef struct {
276 UINT8 PowerUnitGroup;
277 CHAR16 *Location;
278 CHAR16 *DeviceName;
279 CHAR16 *Manufacturer;
280 CHAR16 *SerialNumber;
281 CHAR16 *AssetTagNumber;
282 CHAR16 *ModelPartNumber;
283 CHAR16 *RevisionLevel;
284 UINT16 MaxPowerCapacity;
285 SYS_POWER_SUPPLY_CHARACTERISTICS Characteristics;
286 }SYS_POWER_SUPPLY_INFO_TYPE39;
287
288 //
289 // Platform Info For Type 41 - OnBoard Device Extended Information
290 //
291
292 typedef enum {
293 Disabled = 0,
294 Enabled
295 } DEVICE_STATUS;
296
297 typedef struct {
298 PUBLISH_REQ IsPublishRequired;
299 CHAR16 *Designation;
300 ONBOARD_DEVICE_EXTENDED_INFO_TYPE DeviceType;
301 DEVICE_STATUS DeviceStatus;
302 UINT8 DeviceInstance;
303 UINT16 Segment;
304 UINT8 Bus;
305 UINT8 DevFunc;
306 } ONBOARD_DEV_EXT_INFO_TYPE41;
307
308 //
309 // OEM Type 133
310 //
311 #define NUM_OEM_TYPE_133 1
312 #define SMBIOS_TYPE_OEM_133 0x85
313
314
315 typedef struct{
316 UINT32 DeviceModel:8;
317 UINT32 SizeModel:8;
318 UINT32 PinModel:8;
319 UINT32 Reserved:8;
320 } WWAN_MODEL_ID;
321
322 typedef struct{
323 UINT32 Basic:1;
324 UINT32 Sku1:1;
325 UINT32 Sku2:1;
326 UINT32 Sku3:1;
327 UINT32 Reserved:28;
328 } WWAN_SKU_ID;
329
330 #define NUM_OF_DEV_MODE 3
331
332 #pragma pack(1)
333 //
334 // OEM Type 133 for WWAN
335 //
336 typedef struct {
337 SMBIOS_STRUCTURE Hdr;
338 EFI_GUID TypeGuid;
339 UINT8 Revision;
340 UINT16 OemId; // Same as Vendor ID
341 WWAN_MODEL_ID WwanModelId;
342 UINT32 ProductId;
343 WWAN_SKU_ID WwanSkuId;
344 UINT32 ModelInfo;
345 UINT8 NumberOfDeviceMode;
346 UINT32 Reserved;
347 } SMBIOS_TABLE_TYPE133_WWAN;
348 #pragma pack()
349
350 //
351 // OEM Type 136
352 //
353 #define NUM_OEM_TYPE_136 1
354 #define SMBIOS_TYPE_OEM_136 0x88
355
356 typedef struct {
357 SMBIOS_STRUCTURE Hdr;
358 UINT16 RawData;
359 UINT16 Zero; //terminator
360 } SMBIOS_TABLE_TYPE136;
361
362 //
363 // Smbios Platform Info table
364 //
365 typedef struct {
366 VOID *Info;
367 VOID *Strings;
368 UINTN StringCount;
369 BOOLEAN IsPoolAllocated;
370 UINTN NoOfInstances;
371 }SMBIOS_PLATFORM_INFO;
372
373
374 //
375 // Base Board info for RVP Board data
376 //
377 #define NUM_BASE_BOARDS 0x1
378 typedef struct{
379 CHAR16 *ProductName;
380 CHAR16 *Manufacturer;
381 CHAR16 *Version;
382 UINT8 FeatureFlags;
383 UINT8 BoardType;
384 CHAR16 *LocationInChassis;
385 } BASE_BOARD_INFO;
386 //
387 // Chassis info for RVP Board data
388 //
389 #define NUM_CHASSIS_INFO 0x1
390 typedef struct{
391 CHAR16 *Manufacturer;
392 UINT8 Type;
393 CHAR16 *Version;
394 UINT8 Bootup;
395 UINT8 PowerSupply;
396 UINT8 Thermal;
397 UINT8 Security;
398 UINT8 Height;
399 UINT8 NumberofPowerCords;
400 } CHASSIS_INFO;
401
402 /*
403 The SupportedPortConnectors is represented as below.
404
405 BIT0 Keyboard,
406 BIT1 Mouse,
407 BIT2 Com1,
408 BIT3 Video,
409 BIT4 Hdmi,
410 BIT5 Usb1,
411 BIT6 Usb2,
412 BIT7 Usb3,
413 BIT8 Usb4,
414 BIT9 Usb5,
415 BIT10 Usb201,
416 BIT11 Usb202,
417 BIT12 Network,
418 BIT13 Sata0,
419 BIT14 eSata4,
420 BIT15 eSata3,
421 BIT16 Sata2,
422 BIT17 Sata1,
423 BIT18 Acin,
424 BIT19 PchJtag,
425 BIT20 Port80,
426 BIT21 2X8Header,
427 BIT22 8PinHeader,
428 BIT23 HdaHdmi,
429 BIT24 Mkeyboard,
430 BIT25 Spi,
431 BIT26 LpcDocking,
432 BIT27 Sideband,
433 BIT28 LpcSlot,
434 BIT29 PchXdp,
435 BIT30 SataPower,
436 BIT31 FpHeader,
437 BIT32 AtxPower,
438 BIT33 Avmc,
439 BIT34 Battb,
440 BIT35 Batta,
441 BIT36 CpuFan,
442 BIT37 Xdp,
443 BIT38 Memory1,
444 BIT39 Memory2,
445 BIT40 FanPwr,
446 BIT41-63 Reserved
447 */
448
449 //
450 // Cooling info for RVP Board data
451 //
452 #define NUM_COOLING_DEVICES 2
453 typedef struct{
454 UINT8 Type;
455 CHAR16 *Description;
456 } COOLING_DEV;
457
458 /*
459 The SupportedOnboardDev is represented as below.
460
461 BIT0 Video,
462 BIT1 Ethernet,
463 BIT2 Sound,
464 BIT3 SataController,
465 BIT4 ScsiController,
466 BIT5 TokenRing,
467 BIT6 PataController,
468 BIT7 SasController
469
470 */
471 //
472 // OnBoard Device info for RVP Board data
473 //
474 #define NUM_ONBOARD_DEVICES_EXT 4
475 typedef struct{
476 UINT8 Seg;
477 UINT8 Bus;
478 UINT8 Dev;
479 UINT8 Func;
480 } ONBOARD_DEV_ADDR;
481
482 //
483 // Smbios Board info for RVP Board data
484 //
485 typedef struct {
486 /*System Info Type 1*/
487 CHAR16 *SystemProductName;
488 CHAR16 *SystemVersion;
489 CHAR16 *SystemFamily;
490 UINT8 SystemWakeUpType;
491 /*Base Board Info Type 2*/
492 BASE_BOARD_INFO *BaseBoard;
493 /*Chassis Info Type 3*/
494 CHASSIS_INFO *ChassisInfo;
495 /* Port Connector Info type 8 */
496 UINTN SupportedPortConnectors;
497 /*System Config Options Type 12*/
498 CHAR16 *SystemConfigOptions;
499 /*Cooling device Type 27*/
500 COOLING_DEV *CoolingDev;
501 /* Onboard Device Ext Type 41*/
502 UINT8 SupportedOnboardDev;
503 ONBOARD_DEV_ADDR *OnBoardDevAddr;
504 } SMBIOS_PLATFORM_BOARD_INFO;
505
506 //
507 // Smbios System Slot Board Info
508 //
509 #define MAX_SLOT_ENTRIES 20
510
511 typedef struct {
512 CHAR16 *SlotDesignation;
513 UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.
514 UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.
515 UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.
516 UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.
517 UINT16 SlotID;
518 MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;
519 MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;
520 UINT16 SegmentGroupNum; // Valid Only for PCIe Root Ports, Others 0xFF is expected
521 UINT8 BusNum;
522 UINT8 DevNum;
523 UINT8 FuncNum;
524 BOOLEAN Isvalid;
525 } SYSTEM_SLOT_INFO;
526
527 typedef struct {
528 UINT8 Numberofentries;
529 SYSTEM_SLOT_INFO Slotinfo[MAX_SLOT_ENTRIES];
530 }SYSTEM_SLOT_ENTRY;
531
532 #endif // _SMBIOS_PLATFORM_INFO_DEFINITION_H_


AlderLake Platform Sample Code: SmmCpuSaveState.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Classes
SmmCpuSaveState.h File Reference

This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors. More...

Go to the source code of this file.

Classes

struct | EFI_SMM_CPU_STATE32
CPU save-state strcuture for IA32 and X64. More...
struct | EFI_SMM_CPU_STATE64
This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. More...
union | EFI_SMM_CPU_STATE
Union of CPU save-state strcutures for IA32 and X64. More...
struct | _EFI_SMM_CPU_SAVE_STATE_PROTOCOL
Provides a programatic means to access SMM save state. More...

Detailed Description

This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification
This Protocol is defined in Framework of EFI SMM Core Interface Spec Version 0.91.

Definition in file SmmCpuSaveState.h.


AlderLake Platform Sample Code: SmmCpuSaveState.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
SmmCpuSaveState.h
Go to the documentation of this file.
1 /** @file
2 This file declares the SMM CPU Save State protocol, which provides the processor
3 save-state information for IA-32 and Itanium processors.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2010 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 This Protocol is defined in Framework of EFI SMM Core Interface Spec
35 Version 0.91.
36 **/
37
38 #ifndef _SMM_CPU_SAVE_STATE_H_
39 #define _SMM_CPU_SAVE_STATE_H_
40
41 #define EFI_SMM_CPU_SAVE_STATE_PROTOCOL_GUID \
42 { \
43 0x1413d458, 0x4e61, 0x9531, {0x1e, 0xf2, 0xfb, 0x89, 0x39, 0xa8, 0xa0, 0xea} \
44 }
45
46 typedef struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL EFI_SMM_CPU_SAVE_STATE_PROTOCOL;
47
48 #define EFI_SMM_MIN_REV_ID_x64 0x30006
49
50 #pragma pack (1)
51
52 ///
53 /// CPU save-state strcuture for IA32 and X64.
54 ///
55 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because the
56 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
57 /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
58 /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
59 /// the layout and also maintains source comaptibility for access of all fields in this
60 /// union.
61 ///
62 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
63 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
64 /// have been changed to use the base types defined in the UEFI Specification.
65 ///
66 typedef struct {
67 UINT8 Reserved[0x200];
68 UINT8 Reserved1[0xf8]; // fe00h
69 UINT32 SMBASE; // fef8h
70 UINT32 SMMRevId; // fefch
71 UINT16 IORestart; // ff00h
72 UINT16 AutoHALTRestart; // ff02h
73 UINT32 IEDBASE; // ff04h
74 UINT8 Reserved2[0x98]; // ff08h
75 UINT32 IOMemAddr; // ffa0h
76 UINT32 IOMisc; // ffa4h
77 UINT32 _ES;
78 UINT32 _CS;
79 UINT32 _SS;
80 UINT32 _DS;
81 UINT32 _FS;
82 UINT32 _GS;
83 UINT32 _LDTBase;
84 UINT32 _TR;
85 UINT32 _DR7;
86 UINT32 _DR6;
87 UINT32 _EAX;
88 UINT32 _ECX;
89 UINT32 _EDX;
90 UINT32 _EBX;
91 UINT32 _ESP;
92 UINT32 _EBP;
93 UINT32 _ESI;
94 UINT32 _EDI;
95 UINT32 _EIP;
96 UINT32 _EFLAGS;
97 UINT32 _CR3;
98 UINT32 _CR0;
99 } EFI_SMM_CPU_STATE32;
100
101 ///
102 /// This struct declaration does not exctly match the Framework SMM CIS 0.91 because
103 /// the Framework SMM CIS 0.91 uses ASM_XXX for base types in this structure. These
104 /// have been changed to use the base types defined in the UEFI Specification.
105 ///
106 typedef struct {
107 UINT8 Reserved1[0x1d0]; // fc00h
108 UINT32 GdtBaseHiDword; // fdd0h
109 UINT32 LdtBaseHiDword; // fdd4h
110 UINT32 IdtBaseHiDword; // fdd8h
111 UINT8 Reserved2[0xc]; // fddch
112 UINT64 IO_EIP; // fde8h
113 UINT8 Reserved3[0x50]; // fdf0h
114 UINT32 _CR4; // fe40h
115 UINT8 Reserved4[0x48]; // fe44h
116 UINT32 GdtBaseLoDword; // fe8ch
117 UINT32 GdtLimit; // fe90h
118 UINT32 IdtBaseLoDword; // fe94h
119 UINT32 IdtLimit; // fe98h
120 UINT32 LdtBaseLoDword; // fe9ch
121 UINT32 LdtLimit; // fea0h
122 UINT32 LdtInfo; // fea4h
123 UINT8 Reserved5[0x50]; // fea8h
124 UINT32 SMBASE; // fef8h
125 UINT32 SMMRevId; // fefch
126 UINT16 AutoHALTRestart; // ff00h
127 UINT16 IORestart; // ff02h
128 UINT32 IEDBASE; // ff04h
129 UINT8 Reserved6[0x14]; // ff08h
130 UINT64 _R15; // ff1ch
131 UINT64 _R14;
132 UINT64 _R13;
133 UINT64 _R12;
134 UINT64 _R11;
135 UINT64 _R10;
136 UINT64 _R9;
137 UINT64 _R8;
138 UINT64 _RAX; // ff5ch
139 UINT64 _RCX;
140 UINT64 _RDX;
141 UINT64 _RBX;
142 UINT64 _RSP;
143 UINT64 _RBP;
144 UINT64 _RSI;
145 UINT64 _RDI;
146 UINT64 IOMemAddr; // ff9ch
147 UINT32 IOMisc; // ffa4h
148 UINT32 _ES; // ffa8h
149 UINT32 _CS;
150 UINT32 _SS;
151 UINT32 _DS;
152 UINT32 _FS;
153 UINT32 _GS;
154 UINT32 _LDTR; // ffc0h
155 UINT32 _TR;
156 UINT64 _DR7; // ffc8h
157 UINT64 _DR6;
158 UINT64 _RIP; // ffd8h
159 UINT64 IA32_EFER; // ffe0h
160 UINT64 _RFLAGS; // ffe8h
161 UINT64 _CR3; // fff0h
162 UINT64 _CR0; // fff8h
163 } EFI_SMM_CPU_STATE64;
164
165 ///
166 /// Union of CPU save-state strcutures for IA32 and X64.
167 ///
168 /// This union declaration does not exctly match the Framework SMM CIS 0.91 because the
169 /// union in the Framework SMM CIS 0.91 contains an unnamed union member that causes build
170 /// breaks on many compilers with high warning levels. Instead, the UINT8 Reserved[0x200]
171 /// field has been moved into EFI_SMM_CPU_STATE32. This maintains binary compatibility for
172 /// the layout and also maintains source comaptibility for access of all fields in this
173 /// union.
174 ///
175 typedef union {
176 EFI_SMM_CPU_STATE32 x86;
177 EFI_SMM_CPU_STATE64 x64;
178 } EFI_SMM_CPU_STATE;
179
180 #pragma pack ()
181
182 ///
183 /// Provides a programatic means to access SMM save state.
184 ///
185 struct _EFI_SMM_CPU_SAVE_STATE_PROTOCOL {
186 ///
187 /// Reference to a list of save states.
188 ///
189 EFI_SMM_CPU_STATE **CpuSaveState;
190 };
191
192 #endif
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL
Provides a programatic means to access SMM save state.
Definition: SmmCpuSaveState.h:185
EFI_SMM_CPU_STATE64
This struct declaration does not exctly match the Framework SMM CIS 0.91 because the Framework SMM CI...
Definition: SmmCpuSaveState.h:106
EFI_SMM_CPU_STATE32
CPU save-state strcuture for IA32 and X64.
Definition: SmmCpuSaveState.h:66
EFI_SMM_CPU_STATE
Union of CPU save-state strcutures for IA32 and X64.
Definition: SmmCpuSaveState.h:175
_EFI_SMM_CPU_SAVE_STATE_PROTOCOL::CpuSaveState
EFI_SMM_CPU_STATE ** CpuSaveState
Reference to a list of save states.
Definition: SmmCpuSaveState.h:189
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SmmTxtResource.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Macros | Typedefs
SmmTxtResource.h File Reference

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM. More...

Go to the source code of this file.

Macros

#define END_OF_RESOURCES 0
Resource definitions.

Typedefs

typedef union _RESOURCE | RESOURCE
Resource database header.
typedef EFI_STATUS(* | STM_MAP_ADDRESS_RANGE) (STM_MAP_ADDRESS_RANGE_DESCRIPTOR *Buf)
Member functions.

Detailed Description

This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SmmTxtResource.h.


AlderLake Platform Sample Code: SmmTxtResource.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
SmmTxtResource.h
Go to the documentation of this file.
1 /** @file
2 This file contains function definitions that can determine
3 the TXT resource of a platform during SMM and perform
4 certain specific platform tasks that are required for TXT
5 during SMM.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright 1999 - 2016 Intel Corporation.
10
11 The source code contained or described herein and all documents related to the
12 source code ("Material") are owned by Intel Corporation or its suppliers or
13 licensors. Title to the Material remains with Intel Corporation or its suppliers
14 and licensors. The Material may contain trade secrets and proprietary and
15 confidential information of Intel Corporation and its suppliers and licensors,
16 and is protected by worldwide copyright and trade secret laws and treaty
17 provisions. No part of the Material may be used, copied, reproduced, modified,
18 published, uploaded, posted, transmitted, distributed, or disclosed in any way
19 without Intel's prior express written permission.
20
21 No license under any patent, copyright, trade secret or other intellectual
22 property right is granted to or conferred upon you by disclosure or delivery
23 of the Materials, either expressly, by implication, inducement, estoppel or
24 otherwise. Any license under such intellectual property rights must be
25 express and approved by Intel in writing.
26
27 Unless otherwise agreed by Intel in writing, you may not remove or alter
28 this notice or any other notice embedded in Materials by Intel or
29 Intel's suppliers or licensors in any way.
30
31 This file contains a 'Sample Driver' and is licensed as such under the terms
32 of your license agreement with Intel or your vendor. This file may be modified
33 by the user, subject to the additional terms of the license agreement.
34
35 @par Specification Reference:
36
37 **/
38 #ifndef _SMM_TXT_RESOURCE_PROTOCOL_H_
39 #define _SMM_TXT_RESOURCE_PROTOCOL_H_
40
41 ///
42 /// Resource database header
43 ///
44 #pragma pack(push, 1)
45 typedef union _RESOURCE RESOURCE;
46
47 typedef struct _RESOURCE_AREA RESOURCE_AREA;
48
49 struct _RESOURCE_AREA {
50 EFI_PHYSICAL_ADDRESS AreaAddress;
51 UINT32 AreaSize;
52 UINT32 FreeSize;
53 EFI_PHYSICAL_ADDRESS EndOfRscAddress;
54 EFI_PHYSICAL_ADDRESS FreeSpaceAddress;
55 };
56
57 #define MAX_AREAS 4
58 #define AREA_SIZE 0x1000
59 #define APPEND 0
60 #define START_OVER !0
61
62 typedef struct _STM_RESOURCE_HEADER STM_RESOURCE_HEADER;
63
64 struct _STM_RESOURCE_HEADER {
65 UINT32 NumAreas;
66 RESOURCE_AREA Area[MAX_AREAS];
67 };
68
69 ///
70 /// Resource definitions
71 ///
72 #define END_OF_RESOURCES 0
73 #define MEM_RANGE 1
74 #define IO_RANGE 2
75 #define MMIO_RANGE 3
76 #define MACHINE_SPECIFIC_REG 4
77 #define PCI_CFG_RANGE 5
78 #define TRAPPED_IO_RANGE 6
79 #define MAX_DESC_TYPE 6
80
81 #define RD_ACCS 1
82 #define WR_ACCS 2
83 #define EX_ACCS 4
84 #define RDWR_ACCS 3
85 #define FULL_ACCS 7
86
87 typedef struct {
88 UINT32 RscType;
89 UINT16 Length;
90 UINT16 ReturnStatus : 1;
91 UINT16 Res : 14;
92 UINT16 IgnoreResource : 1;
93 } STM_RSC_DESC_HEADER;
94
95 typedef struct {
96 STM_RSC_DESC_HEADER Hdr;
97 UINT64 ResourceListContinuation;
98 } STM_RSC_END;
99
100 typedef struct {
101 STM_RSC_DESC_HEADER Hdr;
102 UINT64 Base;
103 UINT64 Length;
104 UINT32 RWXAttributes;
105 UINT32 Reserved; /// must be 0
106 } STM_RSC_MEM_DESC;
107
108 typedef struct {
109 STM_RSC_DESC_HEADER Hdr;
110 UINT16 Base;
111 UINT16 Length;
112 UINT32 Reserved; /// must be 0
113 } STM_RSC_IO_DESC;
114
115 typedef struct {
116 STM_RSC_DESC_HEADER Hdr;
117 UINT64 Base;
118 UINT64 Length;
119 UINT32 RWXAttributes;
120 UINT32 Reserved; /// must be 0
121 } STM_RSC_MMIO_DESC;
122
123 #define MASK0 0
124 #define MASK64 0xFFFFFFFFFFFFFFFF
125 #define TABLE_END 0xFFFFFFFFFFFFFFFF
126
127 typedef struct {
128 STM_RSC_DESC_HEADER Hdr;
129 UINT64 MsrIndex;
130 UINT64 ReadMask;
131 UINT64 WriteMask;
132 } STM_RSC_MSR_DESC;
133
134 typedef struct {
135 UINT8 PciFunction;
136 UINT8 PciDevice;
137 } STM_PCI_DEVICE_PATH_NODE;
138
139 typedef struct {
140 STM_RSC_DESC_HEADER Hdr;
141 UINT16 RWAttributes;
142 UINT16 Base;
143 UINT16 Length;
144 UINT8 OriginatingBusNumber;
145 UINT8 LastNodeIndex;
146 UINT8 Reserved;
147 STM_PCI_DEVICE_PATH_NODE PciDevicePath[1];
148 } STM_RSC_PCI_CFG_DESC;
149
150 typedef struct {
151 STM_RSC_DESC_HEADER Hdr;
152 UINT16 Base;
153 UINT16 Length;
154 UINT16 In : 1;
155 UINT16 Out : 1;
156 UINT16 Api : 1;
157 UINT16 Reserved1 : 13;
158 UINT16 Reserved2; /// must be 0
159 } STM_RSC_TRAPPED_IO_DESC;
160
161 union _RESOURCE {
162 STM_RSC_DESC_HEADER hdr;
163 STM_RSC_MEM_DESC mem;
164 STM_RSC_IO_DESC io;
165 STM_RSC_MMIO_DESC mmio;
166 STM_RSC_MSR_DESC msr;
167 STM_RSC_PCI_CFG_DESC pci;
168 STM_RSC_TRAPPED_IO_DESC trapio;
169 STM_RSC_END eor;
170 };
171
172 #pragma pack(pop)
173
174 typedef struct _SMM_TXT_RESOURCE_PROTOCOL SMM_TXT_RESOURCE_PROTOCOL;
175 typedef struct _STM_MAP_ADDRESS_RANGE_DESCRIPTOR STM_MAP_ADDRESS_RANGE_DESCRIPTOR;
176 typedef struct _STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR;
177 typedef struct _STM_API_ADDRESS_LOOKUP_DESCRIPTOR STM_API_ADDRESS_LOOKUP_DESCRIPTOR;
178
179 ///
180 /// Member functions
181 ///
182 typedef
183 EFI_STATUS
184 (EFIAPI *STM_MAP_ADDRESS_RANGE) (
185 STM_MAP_ADDRESS_RANGE_DESCRIPTOR * Buf
186 );
187
188 typedef
189 EFI_STATUS
190 (EFIAPI *STM_UNMAP_ADDRESS_RANGE) (
191 STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR * Buf
192 );
193
194 typedef
195 EFI_STATUS
196 (EFIAPI *STM_API_ADDRESS_LOOKUP) (
197 STM_API_ADDRESS_LOOKUP_DESCRIPTOR * Buf
198 );
199
200 struct _SMM_TXT_RESOURCE_PROTOCOL {
201 STM_MAP_ADDRESS_RANGE StmMapAddressRange;
202 STM_UNMAP_ADDRESS_RANGE StmUnmapAddressRange;
203 STM_API_ADDRESS_LOOKUP StmApiAddressLookup;
204 };
205 #endif
STM_MAP_ADDRESS_RANGE
EFI_STATUS(* STM_MAP_ADDRESS_RANGE)(STM_MAP_ADDRESS_RANGE_DESCRIPTOR *Buf)
Member functions.
Definition: SmmTxtResource.h:184
RESOURCE
union _RESOURCE RESOURCE
Resource database header.
Definition: SmmTxtResource.h:45
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SpiFlashCommon.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
SpiFlashCommon.h File Reference

The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/PcdLib.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Spi.h>
Include dependency graph for SpiFlashCommon.h:

Go to the source code of this file.

Functions

EFI_STATUS | SpiFlashLock (VOID)
Enable block protection on the Serial Flash device. More...
EFI_STATUS | SpiFlashRead (IN UINTN Address, IN OUT UINT32 *NumBytes, OUT UINT8 *Buffer)
Read NumBytes bytes of data from the address specified by PAddress into Buffer. More...
EFI_STATUS | SpiFlashWrite (IN UINTN Address, IN OUT UINT32 *NumBytes, IN UINT8 *Buffer)
Write NumBytes bytes of data from Buffer to the address specified by PAddresss. More...
EFI_STATUS | SpiFlashBlockErase (IN UINTN Address, IN UINTN *NumBytes)
Erase the block starting at Address. More...

Detailed Description

The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SpiFlashCommon.h.

Function Documentation

◆ SpiFlashBlockErase()

EFI_STATUS SpiFlashBlockErase | ( | IN UINTN | Address,
 |  | IN UINTN * | NumBytes
 | ) |  |

Erase the block starting at Address.

Parameters
[in] | Address | The starting physical address of the block to be erased. This library assume that caller garantee that the PAddress is at the starting address of this block.
[in] | NumBytes | On input, the number of bytes of the logical block to be erased. On output, the actual number of bytes erased.
Return values
EFI_SUCCESS. | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.

◆ SpiFlashLock()

EFI_STATUS SpiFlashLock ( VOID )

Enable block protection on the Serial Flash device.

Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.

◆ SpiFlashRead()

EFI_STATUS SpiFlashRead | ( | IN UINTN | Address,
 |  | IN OUT UINT32 * | NumBytes,
 |  | OUT UINT8 * | Buffer
 | ) |  |

Read NumBytes bytes of data from the address specified by PAddress into Buffer.

Parameters
[in] | Address | The starting physical address of the read.
[in,out] | NumBytes | On input, the number of bytes to read. On output, the number of bytes actually read.
[out] | Buffer | The destination data buffer for the read.
Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.

◆ SpiFlashWrite()

EFI_STATUS SpiFlashWrite | ( | IN UINTN | Address,
 |  | IN OUT UINT32 * | NumBytes,
 |  | IN UINT8 * | Buffer
 | ) |  |

Write NumBytes bytes of data from Buffer to the address specified by PAddresss.

Parameters
[in] | Address | The starting physical address of the write.
[in,out] | NumBytes | On input, the number of bytes to write. On output, the actual number of bytes written.
[in] | Buffer | The source data buffer for the write.
Return values
EFI_SUCCESS | Opertion is successful.
EFI_DEVICE_ERROR | If there is any device errors.


AlderLake Platform Sample Code: SpiFlashCommon.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
SpiFlashCommon.h
Go to the documentation of this file.
1 /** @file
2 The header file includes the common header files, defines
3 internal structure and functions used by SpiFlashCommonLib.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2010 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __SPI_FLASH_COMMON_H__
37 #define __SPI_FLASH_COMMON_H__
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/PcdLib.h>
42 #include <Library/DebugLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/MemoryAllocationLib.h>
45 #include <Library/UefiDriverEntryPoint.h>
46 #include <Library/UefiBootServicesTableLib.h>
47 #include <Protocol/Spi.h>
48
49 #define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
50 /**
51 Enable block protection on the Serial Flash device.
52
53 @retval EFI_SUCCESS Opertion is successful.
54 @retval EFI_DEVICE_ERROR If there is any device errors.
55
56 **/
57 EFI_STATUS
58 EFIAPI
59 SpiFlashLock (
60 VOID
61 );
62
63 /**
64 Read NumBytes bytes of data from the address specified by
65 PAddress into Buffer.
66
67 @param[in] Address The starting physical address of the read.
68 @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
69 of bytes actually read.
70 @param[out] Buffer The destination data buffer for the read.
71
72 @retval EFI_SUCCESS Opertion is successful.
73 @retval EFI_DEVICE_ERROR If there is any device errors.
74
75 **/
76 EFI_STATUS
77 EFIAPI
78 SpiFlashRead (
79 IN UINTN Address,
80 IN OUT UINT32 *NumBytes,
81 OUT UINT8 *Buffer
82 );
83
84 /**
85 Write NumBytes bytes of data from Buffer to the address specified by
86 PAddresss.
87
88 @param[in] Address The starting physical address of the write.
89 @param[in,out] NumBytes On input, the number of bytes to write. On output,
90 the actual number of bytes written.
91 @param[in] Buffer The source data buffer for the write.
92
93 @retval EFI_SUCCESS Opertion is successful.
94 @retval EFI_DEVICE_ERROR If there is any device errors.
95
96 **/
97 EFI_STATUS
98 EFIAPI
99 SpiFlashWrite (
100 IN UINTN Address,
101 IN OUT UINT32 *NumBytes,
102 IN UINT8 *Buffer
103 );
104
105 /**
106 Erase the block starting at Address.
107
108 @param[in] Address The starting physical address of the block to be erased.
109 This library assume that caller garantee that the PAddress
110 is at the starting address of this block.
111 @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
112 On output, the actual number of bytes erased.
113
114 @retval EFI_SUCCESS. Opertion is successful.
115 @retval EFI_DEVICE_ERROR If there is any device errors.
116
117 **/
118 EFI_STATUS
119 EFIAPI
120 SpiFlashBlockErase (
121 IN UINTN Address,
122 IN UINTN *NumBytes
123 );
124
125 #endif
SpiFlashBlockErase
EFI_STATUS SpiFlashBlockErase(IN UINTN Address, IN UINTN *NumBytes)
Erase the block starting at Address.
SpiFlashRead
EFI_STATUS SpiFlashRead(IN UINTN Address, IN OUT UINT32 *NumBytes, OUT UINT8 *Buffer)
Read NumBytes bytes of data from the address specified by PAddress into Buffer.
SpiFlashLock
EFI_STATUS SpiFlashLock(VOID)
Enable block protection on the Serial Flash device.
SpiFlashWrite
EFI_STATUS SpiFlashWrite(IN UINTN Address, IN OUT UINT32 *NumBytes, IN UINT8 *Buffer)
Write NumBytes bytes of data from Buffer to the address specified by PAddresss.


AlderLake Platform Sample Code: SystemMonitor.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
SystemMonitor.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SystemMonitor.h.


AlderLake Platform Sample Code: SystemMonitor.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
SystemMonitor.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 1999 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _SYSTEM_MONITOR_H_
35 #define _SYSTEM_MONITOR_H_
36
37
38 // Device Types
39 #define HECETA6x 0x01
40
41 // Company IDs
42 #define NATIONAL 0x01
43 #define SMSC 0x5C
44 #define ADI 0x41
45
46 //Number of Monitor Device Supported
47 #define MAX_MONITOR_DEVICE 0x03
48
49 #define EC_REG_TSR1_LSB 145
50 #define EC_REG_TSR2_LSB 147
51 #define EC_REG_TSR3_LSB 149
52 #define EC_REG_TSR4_LSB 151
53 #define EC_REG_TSR5_LSB 153
54
55 #define EC_REG_CPU_FAN_SPEED 115
56 #define EC_REG_PCH_DTS_TEMP 129
57 #define EC_REG_TS_ON_DIMM0_TEMP 133
58 #define EC_REG_TS_ON_DIMM1_TEMP 134
59
60 // Structure used to return system status
61 // NOTE:
62 // All voltages have been multiplied by 1000 so that integer data
63 // types can be used. To find the actual voltage divide the voltage
64 // data member by 1000.
65 typedef struct {
66 UINTN V1_5;
67 UINTN Vccp;
68 UINTN V3_3;
69 UINTN V5;
70 UINTN V12;
71 INT8 ProcessorTemp;
72 INT8 InternalTemp;
73 INT8 RemoteTemp;
74 UINT16 Tach1;
75 UINT16 Tach2;
76 UINT16 Tach3;
77 UINT16 Tach4;
78 UINT8 CurrentPwm1;
79 UINT8 CurrentPwm2;
80 UINT8 CurrentPwm3;
81 } EFI_SYSTEM_MONITOR_INFO;
82
83 typedef struct {
84 INT16 EC_TSR1;
85 INT16 EC_TSR2;
86 INT16 EC_TSR3;
87 INT16 EC_TSR4;
88 INT16 EC_TSR5;
89 INT16 EC_TSR6;
90 INT16 EC_TSR7;
91 INT16 EC_TSR8;
92
93 INT16 CPUFanSpeed;
94 INT8 PCHDTSTemp;
95 INT8 TSonDimm0Temp;
96 INT8 TSonDimm1Temp;
97 } MOBILE_SYSTEM_MONITOR_INFO;
98
99 typedef struct {
100 UINT8 MonitorDeviceType;
101 UINT8 CompanyId;
102 UINT8 DeviceVersion;
103 UINT8 DeviceRevision;
104 UINT8 DeviceSmbusAddress;
105 } EFI_MONITOR_DEVICE_INFO;
106
107 // Protocol function prototypes
108 typedef
109 EFI_STATUS
110 (EFIAPI *EFI_GET_SYSTEM_MONITOR_VALUES) (
111 IN UINT8 DeviceSmbusAddress,
112 IN UINT16 KeyValue,
113 OUT EFI_SYSTEM_MONITOR_INFO* MonitorValues
114 );
115
116 typedef
117 EFI_STATUS
118 (EFIAPI *EFI_ACCURATE_TACH_SETTINGS) (
119 IN UINT8 DeviceSmbusAddress,
120 IN BOOLEAN EnablePws
121 );
122
123 // Protocol Definition
124 typedef struct {
125 UINT8 DeviceCount;
126 EFI_MONITOR_DEVICE_INFO DeviceInfoList[MAX_MONITOR_DEVICE];
127 EFI_GET_SYSTEM_MONITOR_VALUES GetMonitorValues;
128 EFI_ACCURATE_TACH_SETTINGS AccurateTachSettings;
129 } EFI_SYSTEM_MONITOR_PROTOCOL;
130
131 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: SystemNvDataGuid.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
SystemNvDataGuid.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SystemNvDataGuid.h.


AlderLake Platform Sample Code: SystemNvDataGuid.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
SystemNvDataGuid.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2004 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34
35 #ifndef _SYSTEM_NV_DATA_GUID_H_
36 #define _SYSTEM_NV_DATA_GUID_H_
37
38
39 typedef struct {
40 EFI_GUID SystemNvDataHobGuid;
41 EFI_GUID SystemNvDataFvGuid;
42 EFI_LBA StartLba;
43 UINTN StartLbaOffset;
44 EFI_LBA EndLba;
45 UINTN EndLbaOffset;
46 UINT32 DataTypeSignature;
47 } NV_SYSTEM_DATA_GUID_TYPE;
48
49 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: TbtPolicyInitDxe.c File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
TbtPolicyInitDxe.c File Reference

This file is SampleCode for TBT DXE Policy initialization. More...

#include "TbtPolicyInitDxe.h"
Include dependency graph for TbtPolicyInitDxe.c:

Go to the source code of this file.

Functions

EFI_STATUS TbtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy. More...

Detailed Description

This file is SampleCode for TBT DXE Policy initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TbtPolicyInitDxe.c.

Function Documentation

◆ TbtPolicyInitDxe()

EFI_STATUS TbtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

Initialize TBT DXE Policy.

TBT DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file TbtPolicyInitDxe.c.


AlderLake Platform Sample Code: TbtPolicyInitDxe.c Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
TbtPolicyInitDxe.c
Go to the documentation of this file.
1 /** @file
2 This file is SampleCode for TBT DXE Policy initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #include "TbtPolicyInitDxe.h"
35
36
37 //
38 // Function implementations
39 //
40
41 /**
42 Initialize TBT DXE Policy
43
44 @param[in] ImageHandle Image handle of this driver.
45
46 @retval EFI_SUCCESS Initialization complete.
47 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
48 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
49 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
50 **/
51 EFI_STATUS
52 EFIAPI
53 TbtPolicyInitDxe (
54 IN EFI_HANDLE ImageHandle
55 )
56 {
57 EFI_STATUS Status = EFI_SUCCESS;
58 ITBT_POLICY_PROTOCOL *ITbtPolicy;
59 ITbtPolicy = NULL;
60
61 //
62 // Call CreateITbtDxeConfigBlocks to create & initialize platform policy structure
63 // and get all Intel default policy settings.
64 //
65 Status = CreateITbtDxeConfigBlocks (&ITbtPolicy);
66 if ((Status == EFI_SUCCESS) && (ITbtPolicy != NULL)) {
67 DEBUG ((DEBUG_INFO, "ITbtPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", ITbtPolicy->TableHeader.NumberOfBlocks));
68 } else {
69 DEBUG ((DEBUG_INFO, "Create iTBT Dxe config block failed\n"));
70 }
71
72 #if FixedPcdGetBool (PcdDTbtEnable) == 1
73 //
74 // Install DTBT Policy
75 //
76 Status = DTbtInstallPolicyProtocol (ImageHandle);
77 if (!EFI_ERROR (Status)) {
78 DEBUG ((DEBUG_INFO, "Install DTbt Policy done\n"));
79 }
80
81 #endif
82
83 //
84 // For iTBT and DTBT
85 //
86 if (mFirmwareConfiguration != FwConfigDefault) {
87 UpdateDxeTbtPolicy (ITbtPolicy);
88 }
89
90 //
91 // Install ITbtInstallPolicyProtocol.
92 // While installed, RC assumes the Policy is ready and finalized. So please
93 // update and override any setting before calling this function.
94 //
95 if (ITbtPolicy != NULL) {
96 Status = ITbtInstallPolicyProtocol (ImageHandle, ITbtPolicy);
97 }
98 return Status;
99 }
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
Initialize TBT DXE Policy.
Definition: TbtPolicyInitDxe.c:53
UpdateDxeTbtPolicy
EFI_STATUS UpdateDxeTbtPolicy(IN OUT ITBT_POLICY_PROTOCOL *ITbtPolicy)
Get data for platform policy from setup options.
TbtPolicyInitDxe.h
Header file for the TbtPolicyInitDxe Driver.


AlderLake Platform Sample Code: TbtPolicyInitDxe.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
Functions
TbtPolicyInitDxe.h File Reference

Header file for the TbtPolicyInitDxe Driver. More...

#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <FirwmareConfigurations.h>
#include <Protocol/ITbtPolicy.h>
#include <Library/DxeITbtPolicyLib.h>
#include <Library/DxeTbtPolicyUpdateLib.h>
Include dependency graph for TbtPolicyInitDxe.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS TbtPolicyInitDxe (IN EFI_HANDLE ImageHandle)
TBT DXE Policy Driver Entry Point
More...

Detailed Description

Header file for the TbtPolicyInitDxe Driver.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TbtPolicyInitDxe.h.

Function Documentation

◆ TbtPolicyInitDxe()

EFI_STATUS TbtPolicyInitDxe ( IN EFI_HANDLE ImageHandle )

TBT DXE Policy Driver Entry Point

  • Introduction
    TBT DXE drivers behavior can be controlled by platform policy without modifying reference code directly. Platform policy Protocol is initialized with default settings in this funciton. This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
  • Precondition
    • Runtime variable service should be ready if policy initialization required.
  • Returns
    ITBT_POLICY_PROTOCOL will be installed successfully and ready for TBT reference code use.
  • Porting Recommendations
    Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
Parameters
[in] ImageHandle - Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

TBT DXE Policy Driver Entry Point

Parameters
[in] ImageHandle Image handle of this driver.
Return values
EFI_SUCCESS Initialization complete.
Exceptions
EFI_UNSUPPORTED The chipset is unsupported by this driver.
Return values
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

Definition at line 53 of file TbtPolicyInitDxe.c.


AlderLake Platform Sample Code: TbtPolicyInitDxe.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
TbtPolicyInitDxe.h
Go to the documentation of this file.
1 /** @file
2 Header file for the TbtPolicyInitDxe Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _TBT_POLICY_INIT_DXE_H_
35 #define _TBT_POLICY_INIT_DXE_H_
36
37 #include <Library/BaseMemoryLib.h>
38 #include <Library/MemoryAllocationLib.h>
39 #include <Library/DebugLib.h>
40 #include <Library/UefiBootServicesTableLib.h>
41 #include <FirwmareConfigurations.h>
42 #include <Protocol/ITbtPolicy.h>
43 #include <Library/DxeITbtPolicyLib.h>
44 #if FixedPcdGetBool (PcdDTbtEnable) == 1
45 #include <Library/DxeDTbtPolicyLib.h>
46 #endif
47 #include <Library/DxeTbtPolicyUpdateLib.h>
48
49 extern UINT8 mFirmwareConfiguration;
50
51 /**
52 <b>TBT DXE Policy Driver Entry Point</b> \n
53 - <b>Introduction</b> \n
54 TBT DXE drivers behavior can be controlled by platform policy without modifying reference code directly.
55 Platform policy Protocol is initialized with default settings in this funciton.
56 This policy Protocol has to be initialized prior to System Agent initialization DXE drivers execution.
57
58 - @pre
59 - Runtime variable service should be ready if policy initialization required.
60
61 - @result
62 ITBT_POLICY_PROTOCOL will be installed successfully and ready for TBT reference code use.
63
64 - <b>Porting Recommendations</b> \n
65 Policy should be initialized basing on platform design or user selection (like BIOS Setup Menu)
66
67 @param[in] ImageHandle - Image handle of this driver.
68
69 @retval EFI_SUCCESS Initialization complete.
70 @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
71 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
72 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
73 **/
74 EFI_STATUS
75 EFIAPI
76 TbtPolicyInitDxe (
77 IN EFI_HANDLE ImageHandle
78 );
79
80 #endif
FirwmareConfigurations.h
This header file provides definitions of firmware configuration.
DxeTbtPolicyUpdateLib.h
TbtPolicyInitDxe
EFI_STATUS TbtPolicyInitDxe(IN EFI_HANDLE ImageHandle)
TBT DXE Policy Driver Entry Point
Definition: TbtPolicyInitDxe.c:53
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Tcg.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Typedefs
Tcg.h File Reference

TCG defined values and structures used by the Tcg Core library. More...

#include <Base.h>
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Typedefs

typedef UINT64 TcgUid
UID in host native byte order.

Detailed Description

TCG defined values and structures used by the Tcg Core library.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file Tcg.h.


AlderLake Platform Sample Code: Tcg.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Tcg.h
Go to the documentation of this file.
1 /** @file
2 TCG defined values and structures used by the Tcg Core library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _TCG_H_
37 #define _TCG_H_
38
39 #include <Base.h>
40 #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1]
41
42 #ifdef __cplusplus
43 extern "C"
44 {
45 #endif
46
47 #ifdef _MSC_VER
48 #pragma warning(push)
49 #pragma warning(disable: 4200) // zero-sized array
50 #pragma warning(disable: 4201) // nameless struct/union
51 #pragma warning(disable: 4214) // bit field types other than int
52 #endif
53
54 #pragma pack(push, 1)
55
56 /// UID in host native byte order
57 typedef UINT64 TcgUid;
58
59 #define TCG_UID(b0, b1, b2, b3, b4, b5, b6, b7) (TcgUid)( \
60 (UINT64)(b0) | \
61 ((UINT64)(b1) << 8) | \
62 ((UINT64)(b2) << 16) | \
63 ((UINT64)(b3) << 24) | \
64 ((UINT64)(b4) << 32) | \
65 ((UINT64)(b5) << 40) | \
66 ((UINT64)(b6) << 48) | \
67 ((UINT64)(b7) << 56))
68
69 typedef struct _TcgComPacket {
70 UINT32 Reserved_BE;
71 UINT16 ComID_BE;
72 UINT16 ComIDExtension_BE;
73 UINT32 OutstandingData_BE;
74 UINT32 MinTransfer_BE;
75 UINT32 Length_BE;
76 UINT8 Payload[ 0 ];
77 } TcgComPacket;
78 C_ASSERT(sizeof(TcgComPacket) == 20);
79
80 typedef struct _TcgPacket {
81 UINT32 TperSessionNumber_BE;
82 UINT32 HostSessionNumber_BE;
83 UINT32 SequenceNumber_BE;
84 UINT16 Reserved_BE;
85 UINT16 AckType_BE;
86 UINT32 Acknowledgement_BE;
87 UINT32 Length_BE;
88 UINT8 Payload[ 0 ];
89 } TcgPacket;
90 C_ASSERT(sizeof(TcgPacket) == 24);
91
92 #define TCG_SUBPACKET_ALIGNMENT 4 // 4-byte alignment per spec
93 //TODO CP_Assert power of 2
94
95 typedef struct _TcgSubPacket {
96 UINT8 Reserved_BE[ 6 ];
97 UINT16 Kind_BE;
98 UINT32 Length_BE;
99 UINT8 Payload[ 0 ];
100 } TcgSubPacket;
101 C_ASSERT(sizeof(TcgSubPacket) == 12);
102
103 #define SUBPACKET_KIND_DATA 0x0000
104 #define SUBPACKET_KIND_CREDIT_CONTROL 0x8001
105
106 #define TCG_ATOM_TYPE_INTEGER 0x0
107 #define TCG_ATOM_TYPE_BYTE 0x1
108
109 typedef struct _TcgSimpleTokenTinyAtom {
110 union {
111 UINT8 raw;
112 struct {
113 UINT8 data : 6;
114 UINT8 sign : 1;
115 UINT8 isZero : 1;
116 };
117 };
118 } TcgSimpleTokenTinyAtom;
119 C_ASSERT(sizeof(TcgSimpleTokenTinyAtom) == 1);
120
121 typedef struct _TcgSimpleTokenShortAtom {
122 union {
123 UINT8 rawHeader;
124 struct {
125 UINT8 length : 4;
126 UINT8 signOrCont : 1;
127 UINT8 byteOrInt : 1;
128 UINT8 isZero : 1;
129 UINT8 isOne : 1;
130 };
131 };
132 } TcgSimpleTokenShortAtom;
133 C_ASSERT(sizeof(TcgSimpleTokenShortAtom) == 1);
134
135 #define TCG_MEDIUM_ATOM_LENGTH_HIGH_SHIFT 8
136 #define TCG_MEDIUM_ATOM_LENGTH_HIGH_MASK 0x7
137
138 typedef struct _TcgSimpleTokenMediumAtom {
139 union {
140 UINT16 rawHeader;
141 struct {
142 UINT8 lengthHigh : 3;
143 UINT8 signOrCont : 1;
144 UINT8 byteOrInt : 1;
145 UINT8 isZero : 1;
146 UINT8 isOne1 : 1;
147 UINT8 isOne2 : 1;
148 UINT8 lengthLow;
149 };
150 };
151 } TcgSimpleTokenMediumAtom;
152 C_ASSERT(sizeof(TcgSimpleTokenMediumAtom) == 2);
153
154 #define TCG_LONG_ATOM_LENGTH_HIGH_SHIFT 16
155 #define TCG_LONG_ATOM_LENGTH_MID_SHIFT 8
156
157 typedef struct _TcgSimpleTokenLongAtom {
158 union {
159 UINT32 rawHeader;
160 struct {
161 UINT8 signOrCont : 1;
162 UINT8 byteOrInt : 1;
163 UINT8 reserved : 2;
164 UINT8 isZero : 1;
165 UINT8 isOne1 : 1;
166 UINT8 isOne2 : 1;
167 UINT8 isOne3 : 1;
168 UINT8 lengthHigh;
169 UINT8 lengthMid;
170 UINT8 lengthLow;
171 };
172 };
173 } TcgSimpleTokenLongAtom;
174 C_ASSERT(sizeof(TcgSimpleTokenLongAtom) == 4);
175
176 // TCG Core Spec v2 - Table 04 - Token Types
177 typedef enum _TcgTokenType {
178 TcgTokenType_Reserved,
179 TcgTokenType_TinyAtom,
180 TcgTokenType_ShortAtom,
181 TcgTokenType_MediumAtom,
182 TcgTokenType_LongAtom,
183 TcgTokenType_StartList,
184 TcgTokenType_EndList,
185 TcgTokenType_StartName,
186 TcgTokenType_EndName,
187 TcgTokenType_Call,
188 TcgTokenType_EndOfData,
189 TcgTokenType_EndOfSession,
190 TcgTokenType_StartTransaction,
191 TcgTokenType_EndTransaction,
192 TcgTokenType_EmptyAtom,
193 } TcgTokenType;
194
195 #pragma pack(pop)
196
197 #define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F
198 #define TCG_TOKEN_SHORTATOM_MAX_BYTE_SIZE 0x0F
199 #define TCG_TOKEN_MEDIUMATOM_MAX_BYTE_SIZE 0x7FF
200 #define TCG_TOKEN_LONGATOM_MAX_BYTE_SIZE 0xFFFFFF
201
202 #define TCG_TOKEN_TINYATOM_UNSIGNED_MAX_VALUE 0x3F
203 #define TCG_TOKEN_TINYATOM_SIGNED_MAX_VALUE 0x1F
204 #define TCG_TOKEN_TINYATOM_SIGNED_MIN_VALUE -32
205
206 // TOKEN TYPES
207 #define TCG_TOKEN_TINYATOM 0x00
208 #define TCG_TOKEN_TINYSIGNEDATOM 0x40
209 #define TCG_TOKEN_SHORTATOM 0x80
210 #define TCG_TOKEN_SHORTSIGNEDATOM 0x90
211 #define TCG_TOKEN_SHORTBYTESATOM 0xA0
212 #define TCG_TOKEN_MEDIUMATOM 0xC0
213 #define TCG_TOKEN_MEDIUMSIGNEDATOM 0xC8
214 #define TCG_TOKEN_MEDIUMBYTESATOM 0xD0
215 #define TCG_TOKEN_LONGATOM 0xE0
216 #define TCG_TOKEN_LONGSIGNEDATOM 0xE1
217 #define TCG_TOKEN_LONGBYTESATOM 0xE2
218 #define TCG_TOKEN_STARTLIST 0xF0
219 #define TCG_TOKEN_ENDLIST 0xF1
220 #define TCG_TOKEN_STARTNAME 0xF2
221 #define TCG_TOKEN_ENDNAME 0xF3
222 // 0xF4 - 0xF7 TCG Reserved
223 #define TCG_TOKEN_CALL 0xF8
224 #define TCG_TOKEN_ENDDATA 0xF9
225 #define TCG_TOKEN_ENDSESSION 0xFA
226 #define TCG_TOKEN_STARTTRANSACTION 0xFB
227 #define TCG_TOKEN_ENDTRANSACTION 0xFC
228 // 0xFD - 0xFE TCG Reserved
229 #define TCG_TOKEN_EMPTY 0xFF
230
231 // CELLBLOCK reserved Names
232 #define TCG_CELL_BLOCK_TABLE_NAME (UINT8)0x00
233 #define TCG_CELL_BLOCK_START_ROW_NAME (UINT8)0x01
234 #define TCG_CELL_BLOCK_END_ROW_NAME (UINT8)0x02
235 #define TCG_CELL_BLOCK_START_COLUMN_NAME (UINT8)0x03
236 #define TCG_CELL_BLOCK_END_COLUMN_NAME (UINT8)0x04
237
238 // METHOD STATUS CODES
239 #define TCG_METHOD_STATUS_CODE_SUCCESS 0x00
240 #define TCG_METHOD_STATUS_CODE_NOT_AUTHORIZED 0x01
241 #define TCG_METHOD_STATUS_CODE_OBSOLETE 0x02
242 #define TCG_METHOD_STATUS_CODE_SP_BUSY 0x03
243 #define TCG_METHOD_STATUS_CODE_SP_FAILED 0x04
244 #define TCG_METHOD_STATUS_CODE_SP_DISABLED 0x05
245 #define TCG_METHOD_STATUS_CODE_SP_FROZEN 0x06
246 #define TCG_METHOD_STATUS_CODE_NO_SESSIONS_AVAILABLE 0x07
247 #define TCG_METHOD_STATUS_CODE_UNIQUENESS_CONFLICT 0x08
248 #define TCG_METHOD_STATUS_CODE_INSUFFICIENT_SPACE 0x09
249 #define TCG_METHOD_STATUS_CODE_INSUFFICIENT_ROWS 0x0A
250 #define TCG_METHOD_STATUS_CODE_INVALID_PARAMETER 0x0C
251 #define TCG_METHOD_STATUS_CODE_OBSOLETE2 0x0D
252 #define TCG_METHOD_STATUS_CODE_OBSOLETE3 0x0E
253 #define TCG_METHOD_STATUS_CODE_TPER_MALFUNCTION 0x0F
254 #define TCG_METHOD_STATUS_CODE_TRANSACTION_FAILURE 0x10
255 #define TCG_METHOD_STATUS_CODE_RESPONSE_OVERFLOW 0x11
256 #define TCG_METHOD_STATUS_CODE_AUTHORITY_LOCKED_OUT 0x12
257 #define TCG_METHOD_STATUS_CODE_FAIL 0x3F
258
259
260 // Feature Codes
261 #define TCG_FEATURE_INVALID (UINT16)0x0000
262 #define TCG_FEATURE_TPER (UINT16)0x0001
263 #define TCG_FEATURE_LOCKING (UINT16)0x0002
264 #define TCG_FEATURE_GEOMETRY_REPORTING (UINT16)0x0003
265 #define TCG_FEATURE_SINGLE_USER_MODE (UINT16)0x0201
266 #define TCG_FEATURE_DATASTORE_TABLE (UINT16)0x0202
267 #define TCG_FEATURE_OPAL_SSC_V1_0_0 (UINT16)0x0200
268 #define TCG_FEATURE_OPAL_SSC_V2_0_0 (UINT16)0x0203
269 #define TCG_FEATURE_OPAL_SSC_LITE (UINT16)0x0301
270 #define TCG_FEATURE_PYRITE_SSC (UINT16)0x0302
271
272 // ACE Expression values
273 #define TCG_ACE_EXPRESSION_AND 0x0
274 #define TCG_ACE_EXPRESSION_OR 0x1
275
276 /****************************************************************************
277 TRUSTED RECEIVE - supported security protocols list (SP_Specific = 0000h)
278 ATA 8 Rev6a Table 68 7.57.6.2
279 ****************************************************************************/
280 // Security Protocol IDs
281 #define SECURITY_PROTOCOL_INFO 0x00
282 #define OPAL_SECURITY_PROTOCOL_1 0x01
283 #define OPAL_SECURITY_PROTOCOL_2 0x02
284 #define SECURITY_PROTOCOL_TCG3 0x03
285 #define SECURITY_PROTOCOL_TCG4 0x04
286 #define SECURITY_PROTOCOL_TCG5 0x05
287 #define SECURITY_PROTOCOL_TCG6 0x06
288 #define SECURITY_PROTOCOL_CBCS 0x07
289 #define SECURITY_PROTOCOL_TAPE_DATA 0x20
290 #define SECURITY_PROTOCOL_DATA_ENCRYPT_CONFIG 0x21
291 #define SECURITY_PROTOCOL_SA_CREATION_CAPS 0x40
292 #define SECURITY_PROTOCOL_IKEV2_SCSI 0x41
293 #define SECURITY_PROTOCOL_JEDEC_UFS 0xEC
294 #define SECURITY_PROTOCOL_SDCARD_SECURITY 0xED
295 #define SECURITY_PROTOCOL_IEEE_1667 0xEE
296 #define SECURITY_PROTOCOL_ATA_DEVICE_SERVER_PASS 0xEF
297
298 // Security Protocol Specific IDs
299 #define TCG_SP_SPECIFIC_PROTOCOL_LIST 0x0000
300 #define TCG_SP_SPECIFIC_PROTOCOL_LEVEL0_DISCOVERY 0x0001
301
302 #define TCG_RESERVED_COMID 0x0000
303
304 #pragma pack(push, 1)
305 typedef struct _TCG_SUPPORTED_SECURITY_PROTOCOLS {
306 UINT8 reserved[6];
307 UINT16 listLength_BE; // 6 - 7
308 UINT8 list[504]; // 8...
309 } TCG_SUPPORTED_SECURITY_PROTOCOLS;
310 C_ASSERT(sizeof(TCG_SUPPORTED_SECURITY_PROTOCOLS) == 512);
311
312 // Level 0 Discovery
313 typedef struct _TCG_LEVEL0_DISCOVERY_HEADER {
314 UINT32 length_BE; // number of valid bytes in discovery response, not including length field
315 UINT16 verMajor_BE;
316 UINT16 verMinor_BE;
317 UINT8 reserved[8];
318 UINT8 vendorUnique[32];
319 } TCG_LEVEL0_DISCOVERY_HEADER;
320 C_ASSERT(sizeof(TCG_LEVEL0_DISCOVERY_HEADER) == 48);
321
322 typedef struct _TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER {
323 UINT16 featureCode_BE;
324 UINT8 reserved : 4;
325 UINT8 version : 4;
326 UINT8 length; // length of feature dependent data in bytes
327 } TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER;
328 C_ASSERT(sizeof(TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER) == 4);
329
330 typedef struct _TCG_LOCKING_FEATURE_DESCRIPTOR {
331 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER header;
332 UINT8 lockingSupported : 1;
333 UINT8 lockingEnabled : 1; // means the locking security provider (SP) is enabled
334 UINT8 locked : 1; // means at least 1 locking range is enabled
335 UINT8 mediaEncryption : 1;
336 UINT8 mbrEnabled : 1;
337 UINT8 mbrDone : 1;
338 UINT8 reserved : 2;
339 UINT8 reserved5_15[11];
340 } TCG_LOCKING_FEATURE_DESCRIPTOR;
341 C_ASSERT(sizeof(TCG_LOCKING_FEATURE_DESCRIPTOR) == 16);
342
343 typedef struct _TCG_TPER_FEATURE_DESCRIPTOR {
344 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER header;
345 UINT8 SyncSupported : 1;
346 UINT8 AsyncSupported : 1;
347 UINT8 AckNakSupported : 1;
348 UINT8 BufferMgmtSupported : 1;
349 UINT8 StreamingSupported : 1;
350 UINT8 Reserved4b5 : 1;
351 UINT8 ComIdMgmtSupported : 1;
352 UINT8 Reserved4b7 : 1;
353 UINT8 Reserved5_15[11];
354 } TCG_TPER_FEATURE_DESCRIPTOR;
355 C_ASSERT(sizeof(TCG_TPER_FEATURE_DESCRIPTOR) == 16);
356
357 #pragma pack(pop)
358
359
360 // Special Purpose UIDs
361 #define TCG_UID_NULL TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00)
362 #define TCG_UID_THIS_SP TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01)
363 #define TCG_UID_SMUID TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF)
364
365 // Session Manager Method UIDS
366 #define TCG_UID_SM_PROPERTIES TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x01)
367 #define TCG_UID_SM_START_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x02)
368 #define TCG_UID_SM_SYNC_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03)
369 #define TCG_UID_SM_START_TRUSTED_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x04)
370 #define TCG_UID_SM_SYNC_TRUSTED_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x05)
371 #define TCG_UID_SM_CLOSE_SESSION TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
372
373 // MethodID UIDs
374 #define TCG_UID_METHOD_DELETE_SP TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01)
375 #define TCG_UID_METHOD_CREATE_TABLE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x02)
376 #define TCG_UID_METHOD_DELETE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03)
377 #define TCG_UID_METHOD_CREATE_ROW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04)
378 #define TCG_UID_METHOD_DELETE_ROW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05)
379 #define TCG_UID_METHOD_NEXT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x08)
380 #define TCG_UID_METHOD_GET_FREE_SPACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x09)
381 #define TCG_UID_METHOD_GET_FREE_ROWS TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0A)
382 #define TCG_UID_METHOD_DELETE_METHOD TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0B)
383 #define TCG_UID_METHOD_GET_ACL TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0D)
384 #define TCG_UID_METHOD_ADD_ACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0E)
385 #define TCG_UID_METHOD_REMOVE_ACE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0F)
386 #define TCG_UID_METHOD_GEN_KEY TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x10)
387 #define TCG_UID_METHOD_GET_PACKAGE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x12)
388 #define TCG_UID_METHOD_SET_PACKAGE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x13)
389 #define TCG_UID_METHOD_GET TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x16)
390 #define TCG_UID_METHOD_SET TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x17)
391 #define TCG_UID_METHOD_AUTHENTICATE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x1C)
392 #define TCG_UID_METHOD_ISSUE_SP TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x02, 0x01)
393 #define TCG_UID_METHOD_GET_CLOCK TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x01)
394 #define TCG_UID_METHOD_RESET_CLOCK TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x02)
395 #define TCG_UID_METHOD_SET_CLOCK_HIGH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x03)
396 #define TCG_UID_METHOD_SET_LAG_HIGH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x04)
397 #define TCG_UID_METHOD_SET_CLOCK_LOW TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x05)
398 #define TCG_UID_METHOD_SET_LAG_LOW TCG_UID(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x06)
399 #define TCG_UID_METHOD_INCREMENT_COUNTER TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x04, 0x07)
400 #define TCG_UID_METHOD_RANDOM TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x01)
401 #define TCG_UID_METHOD_SALT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x02)
402 #define TCG_UID_METHOD_DECRYPT_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x03)
403 #define TCG_UID_METHOD_DECRYPT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x04)
404 #define TCG_UID_METHOD_DECRYPT_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x05)
405 #define TCG_UID_METHOD_ENCRYPT_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x06)
406 #define TCG_UID_METHOD_ENCRYPT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x07)
407 #define TCG_UID_METHOD_ENCRYPT_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x08)
408 #define TCG_UID_METHOD_HMAC_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x09)
409 #define TCG_UID_METHOD_HMAC TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0A)
410 #define TCG_UID_METHOD_HMAC_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0B)
411 #define TCG_UID_METHOD_HASH_INIT TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0C)
412 #define TCG_UID_METHOD_HASH TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0D)
413 #define TCG_UID_METHOD_HASH_FINALIZE TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0E)
414 #define TCG_UID_METHOD_SIGN TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x0F)
415 #define TCG_UID_METHOD_VERIFY TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x10)
416 #define TCG_UID_METHOD_XOR TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x06, 0x11)
417 #define TCG_UID_METHOD_ADD_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x01)
418 #define TCG_UID_METHOD_CREATE_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x02)
419 #define TCG_UID_METHOD_CLEAR_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x03)
420 #define TCG_UID_METHOD_FLUSH_LOG TCG_UID(0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x0A, 0x04)
421
422 #ifdef _MSC_VER
423 #pragma warning(pop)
424 #endif
425
426 #ifdef __cplusplus
427 }
428 #endif
429
430 #endif // TCG_H_
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Tcg2ConfigHii.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
Tcg2ConfigHii.h File Reference

GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2ConfigHii.h.


AlderLake Platform Sample Code: Tcg2ConfigHii.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
Tcg2ConfigHii.h
Go to the documentation of this file.
1 /** @file
2 GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __TCG2_CONFIG_HII_GUID_H__
36 #define __TCG2_CONFIG_HII_GUID_H__
37
38 #define TCG2_CONFIG_FORM_SET_GUID \
39 { \
40 0x6339d487, 0x26ba, 0x424b, { 0x9a, 0x5d, 0x68, 0x7e, 0x25, 0xd7, 0x40, 0xbc } \
41 }
42
43 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Tcg2ConfigNvData.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
Tcg2ConfigNvData.h File Reference

Header file for NV data structure definition. More...

#include <Guid/HiiPlatformSetupFormset.h>
#include <Guid/Tcg2ConfigHii.h>
#include <IndustryStandard/TcgPhysicalPresence.h>
#include <Guid/PttInstance.h>
#include <Guid/PttPTPInstanceGuid.h>
Include dependency graph for Tcg2ConfigNvData.h:

Go to the source code of this file.

Macros

#define TCG2_CONFIGURATION_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Header file for NV data structure definition.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2ConfigNvData.h.


AlderLake Platform Sample Code: Tcg2ConfigNvData.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Tcg2ConfigNvData.h
Go to the documentation of this file.
1 /** @file
2 Header file for NV data structure definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34
35 #ifndef __TCG2_CONFIG_NV_DATA_H__
36 #define __TCG2_CONFIG_NV_DATA_H__
37
38 #include <Guid/HiiPlatformSetupFormset.h>
39 #include <Guid/Tcg2ConfigHii.h>
40 #include <IndustryStandard/TcgPhysicalPresence.h>
41 #include <Guid/PttInstance.h>
42 #include <Guid/PttPTPInstanceGuid.h>
43
44 #define EFI_TCG2_EVENT_LOG_FORMAT_ALL (EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2 | EFI_TCG2_EVENT_LOG_FORMAT_TCG_2)
45
46 #define TCG2_CONFIGURATION_VARSTORE_ID 0x0002
47 #define TCG2_CONFIGURATION_FORM_ID 0x0001
48
49 #define KEY_TPM_DEVICE 0x2000
50 #define KEY_TPM2_OPERATION 0x2001
51 #define KEY_TPM2_OPERATION_PARAMETER 0x2002
52 #define KEY_TPM2_PCR_BANKS_REQUEST_0 0x2003
53 #define KEY_TPM2_PCR_BANKS_REQUEST_1 0x2004
54 #define KEY_TPM2_PCR_BANKS_REQUEST_2 0x2005
55 #define KEY_TPM2_PCR_BANKS_REQUEST_3 0x2006
56 #define KEY_TPM2_PCR_BANKS_REQUEST_4 0x2007
57
58 #define TPM_DEVICE_NULL 0
59 #define TPM_DEVICE_1_2 1
60 #define TPM_DEVICE_2_0_DTPM 2
61 #define TPM_DEVICE_MIN TPM_DEVICE_1_2
62 #define TPM_DEVICE_MAX TPM_DEVICE_2_0_DTPM
63 #define TPM_DEVICE_DEFAULT TPM_DEVICE_2_0_DTPM
64
65 #define TCG2_PROTOCOL_VERSION_DEFAULT 0x0001
66 #define EFI_TCG2_EVENT_LOG_FORMAT_DEFAULT EFI_TCG2_EVENT_LOG_FORMAT_TCG_1_2
67
68 /**
69 Making any setup structure change after code frozen
70 will need to maintain backward compatibility, bump up
71 structure revision and update below history table\n
72 <b>Revision 1</b>: - Initial version.
73 **/
74 #define TCG2_CONFIGURATION_REVISION 1
75
76 //
77 // Nv Data structure referenced by IFR, TPM device user desired
78 //
79 typedef struct {
80 UINT8 TpmDevice;
81 } TCG2_CONFIGURATION;
82
83 //
84 // Variable saved for S3, TPM detected, only valid in S3 path.
85 // This variable is ReadOnly.
86 //
87 typedef struct {
88 UINT8 TpmDeviceDetected;
89 } TCG2_DEVICE_DETECTION;
90
91 #define TCG2_STORAGE_NAME L"TCG2_CONFIGURATION"
92 #define TCG2_DEVICE_DETECTION_NAME L"TCG2_DEVICE_DETECTION"
93
94 #define TPM_INSTANCE_ID_LIST { \
95 {TPM_DEVICE_INTERFACE_NONE, TPM_DEVICE_NULL}, \
96 {TPM_DEVICE_INTERFACE_TPM12, TPM_DEVICE_1_2}, \
97 {TPM_DEVICE_INTERFACE_TPM20_DTPM, TPM_DEVICE_2_0_DTPM}, \
98 }
99
100 #endif
Tcg2ConfigHii.h
GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
PttInstance.h
GUID definition for the PTT device instance.
PttPTPInstanceGuid.h
GUID definition for the PTT device instance.


AlderLake Platform Sample Code: Tcg2PhysicalPresenceLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
Tcg2PhysicalPresenceLib.h File Reference

Ihis library is intended to be used by BDS modules. More...

#include <IndustryStandard/Tpm20.h>
#include <IndustryStandard/TcgPhysicalPresence.h>
#include <Protocol/Tcg2Protocol.h>
Include dependency graph for Tcg2PhysicalPresenceLib.h:

Go to the source code of this file.

Functions

VOID | Tcg2PhysicalPresenceLibProcessRequest (IN TPM2B_AUTH *PlatformAuth OPTIONAL)
Check and execute the pending TPM request. More...
BOOLEAN | Tcg2PhysicalPresenceLibNeedUserConfirm (VOID)
Check if the pending TPM request needs user input to confirm. More...
UINT32 | Tcg2PhysicalPresenceLibGetManagementFlags (VOID)
Return TPM2 ManagementFlags set by PP interface. More...
UINT32 | Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction (OUT UINT32 *MostRecentRequest, OUT UINT32 *Response)
The handler for TPM physical presence function: Return TPM Operation Response to OS Environment. More...
UINT32 | Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (IN UINT32 OperationRequest, IN UINT32 RequestParameter)
The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2. More...
UINT32 | Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction (IN UINT32 OperationRequest)
The handler for TPM physical presence function: Get User Confirmation Status for Operation. More...

Detailed Description

Ihis library is intended to be used by BDS modules.

This library will execute TPM2 request.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file Tcg2PhysicalPresenceLib.h.

Function Documentation

◆ Tcg2PhysicalPresenceLibGetManagementFlags()

UINT32 Tcg2PhysicalPresenceLibGetManagementFlags ( VOID )

Return TPM2 ManagementFlags set by PP interface.

Return values
ManagementFlags TPM2 Management Flags.

◆ Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction()

UINT32 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction ( IN UINT32 OperationRequest )

The handler for TPM physical presence function: Get User Confirmation Status for Operation.

This API should be invoked in OS runtime phase to interface with ACPI method.

Caution: This function may receive untrusted input.

Parameters
[in] OperationRequest TPM physical presence operation request.
Returns
Return Code for Get User Confirmation Status for Operation.

◆ Tcg2PhysicalPresenceLibNeedUserConfirm()

BOOLEAN Tcg2PhysicalPresenceLibNeedUserConfirm ( VOID )

Check if the pending TPM request needs user input to confirm.

The TPM request may come from OS. This API will check if TPM request exists and need user input to confirmation.

Return values
TRUE | TPM needs input to confirm user physical presence.
FALSE | TPM doesn't need input to confirm user physical presence.

◆ Tcg2PhysicalPresenceLibProcessRequest()

VOID Tcg2PhysicalPresenceLibProcessRequest ( IN TPM2B_AUTH *PlatformAuth OPTIONAL )

Check and execute the pending TPM request.

The TPM request may come from OS or BIOS. This API will display request information and wait for user confirmation if TPM request exists. The TPM request will be sent to TPM device after the TPM request is confirmed, and one or more reset may be required to make TPM request to take effect.

This API should be invoked after console in and console out are all ready as they are required to display request information and get user input to confirm the request.

Parameters
PlatformAuth platform auth value. NULL means no platform auth change.

◆ Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction()

UINT32 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction | ( | OUT UINT32 * | MostRecentRequest,
 |  | OUT UINT32 * | Response
 | ) |  |

The handler for TPM physical presence function: Return TPM Operation Response to OS Environment.

This API should be invoked in OS runtime phase to interface with ACPI method.

Parameters
[out] | MostRecentRequest | Most recent operation request.
[out] | Response | Response to the most recent operation request.
Returns
Return Code for Return TPM Operation Response to OS Environment.

◆ Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction()

UINT32 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction | ( | IN UINT32 | OperationRequest,
 |  | IN UINT32 | RequestParameter
 | ) |  |

The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2.

This API should be invoked in OS runtime phase to interface with ACPI method.

Caution: This function may receive untrusted input.

Parameters
[in] | OperationRequest | TPM physical presence operation request.
[in] | RequestParameter | TPM physical presence operation request parameter.
Returns
Return Code for Submit TPM Operation Request to Pre-OS Environment and Submit TPM Operation Request to Pre-OS Environment 2.


AlderLake Platform Sample Code: Tcg2PhysicalPresenceLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Tcg2PhysicalPresenceLib.h
Go to the documentation of this file.
1 /** @file
2 Ihis library is intended to be used by BDS modules.
3 This library will execute TPM2 request.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2015 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains a 'Sample Driver' and is licensed as such under the terms
30 of your license agreement with Intel or your vendor. This file may be modified
31 by the user, subject to the additional terms of the license agreement.
32
33 @par Specification
34 **/
35
36 #ifndef _TCG2_PHYSICAL_PRESENCE_LIB_H_
37 #define _TCG2_PHYSICAL_PRESENCE_LIB_H_
38
39 #include <IndustryStandard/Tpm20.h>
40 #include <IndustryStandard/TcgPhysicalPresence.h>
41 #include <Protocol/Tcg2Protocol.h>
42
43 //
44 // UEFI TCG2 library definition bit of the BIOS TPM Management Flags
45 //
46 // BIT0 is reserved
47 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CLEAR BIT1
48 // BIT2 is reserved
49 #define TCG2_LIB_PP_FLAG_RESET_TRACK BIT3
50 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_ON BIT4
51 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_OFF BIT5
52 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_EPS BIT6
53 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_PCRS BIT7
54
55 //
56 // UEFI TCG2 library definition bit of the BIOS Information Flags
57 //
58 #define TCG2_BIOS_INFORMATION_FLAG_HIERACHY_CONTROL_STORAGE_DISABLE BIT8
59 #define TCG2_BIOS_INFORMATION_FLAG_HIERACHY_CONTROL_ENDORSEMENT_DISABLE BIT9
60
61 //
62 // UEFI TCG2 library definition bit of the BIOS Storage Management Flags
63 //
64 #define TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_PP_REQUIRED_FOR_ENABLE_BLOCK_SID BIT16
65 #define TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_PP_REQUIRED_FOR_DISABLE_BLOCK_SID BIT17
66
67 //
68 // Default value
69 //
70 #define TCG2_BIOS_TPM_MANAGEMENT_FLAG_DEFAULT (TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_OFF | \
71 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CLEAR | \
72 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_EPS | \
73 TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_CHANGE_PCRS)
74
75 /**
76 Check and execute the pending TPM request.
77
78 The TPM request may come from OS or BIOS. This API will display request information and wait
79 for user confirmation if TPM request exists. The TPM request will be sent to TPM device after
80 the TPM request is confirmed, and one or more reset may be required to make TPM request to
81 take effect.
82
83 This API should be invoked after console in and console out are all ready as they are required
84 to display request information and get user input to confirm the request.
85
86 @param PlatformAuth platform auth value. NULL means no platform auth change.
87 **/
88 VOID
89 EFIAPI
90 Tcg2PhysicalPresenceLibProcessRequest (
91 IN TPM2B_AUTH *PlatformAuth OPTIONAL
92 );
93
94 /**
95 Check if the pending TPM request needs user input to confirm.
96
97 The TPM request may come from OS. This API will check if TPM request exists and need user
98 input to confirmation.
99
100 @retval TRUE TPM needs input to confirm user physical presence.
101 @retval FALSE TPM doesn't need input to confirm user physical presence.
102
103 **/
104 BOOLEAN
105 EFIAPI
106 Tcg2PhysicalPresenceLibNeedUserConfirm (
107 VOID
108 );
109
110 /**
111 Return TPM2 ManagementFlags set by PP interface.
112
113 @retval ManagementFlags TPM2 Management Flags.
114 **/
115 UINT32
116 EFIAPI
117 Tcg2PhysicalPresenceLibGetManagementFlags (
118 VOID
119 );
120
121 /**
122 The handler for TPM physical presence function:
123 Return TPM Operation Response to OS Environment.
124
125 This API should be invoked in OS runtime phase to interface with ACPI method.
126
127 @param[out] MostRecentRequest Most recent operation request.
128 @param[out] Response Response to the most recent operation request.
129
130 @return Return Code for Return TPM Operation Response to OS Environment.
131 **/
132 UINT32
133 EFIAPI
134 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction (
135 OUT UINT32 *MostRecentRequest,
136 OUT UINT32 *Response
137 );
138
139
140 /**
141 The handler for TPM physical presence function:
142 Submit TPM Operation Request to Pre-OS Environment and
143 Submit TPM Operation Request to Pre-OS Environment 2.
144
145 This API should be invoked in OS runtime phase to interface with ACPI method.
146
147 Caution: This function may receive untrusted input.
148
149 @param[in] OperationRequest TPM physical presence operation request.
150 @param[in] RequestParameter TPM physical presence operation request parameter.
151
152 @return Return Code for Submit TPM Operation Request to Pre-OS Environment and
153 Submit TPM Operation Request to Pre-OS Environment 2.
154 **/
155 UINT32
156 EFIAPI
157 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction (
158 IN UINT32 OperationRequest,
159 IN UINT32 RequestParameter
160 );
161
162 /**
163 The handler for TPM physical presence function:
164 Get User Confirmation Status for Operation.
165
166 This API should be invoked in OS runtime phase to interface with ACPI method.
167
168 Caution: This function may receive untrusted input.
169
170 @param[in] OperationRequest TPM physical presence operation request.
171
172 @return Return Code for Get User Confirmation Status for Operation.
173 **/
174 UINT32
175 EFIAPI
176 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction (
177 IN UINT32 OperationRequest
178 );
179
180 #endif
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction
UINT32 Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction(IN UINT32 OperationRequest, IN UINT32 RequestParameter)
The handler for TPM physical presence function: Submit TPM Operation Request to Pre-OS Environment an...
Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction
UINT32 Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction(OUT UINT32 *MostRecentRequest, OUT UINT32 *Response)
The handler for TPM physical presence function: Return TPM Operation Response to OS Environment.
Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction
UINT32 Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction(IN UINT32 OperationRequest)
The handler for TPM physical presence function: Get User Confirmation Status for Operation.
Tcg2PhysicalPresenceLibGetManagementFlags
UINT32 Tcg2PhysicalPresenceLibGetManagementFlags(VOID)
Return TPM2 ManagementFlags set by PP interface.
Tcg2PhysicalPresenceLibProcessRequest
VOID Tcg2PhysicalPresenceLibProcessRequest(IN TPM2B_AUTH *PlatformAuth OPTIONAL)
Check and execute the pending TPM request.
Tcg2PhysicalPresenceLibNeedUserConfirm
BOOLEAN Tcg2PhysicalPresenceLibNeedUserConfirm(VOID)
Check if the pending TPM request needs user input to confirm.


AlderLake Platform Sample Code: TcgCore.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Classes | Typedefs | Enumerations | Functions
TcgCore.h File Reference

Public API for the Tcg Core library to perform the lowest level TCG data encoding. More...

#include <Library/Tcg.h>
Include dependency graph for TcgCore.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...
struct | _TcgParseStruct
Structure that is used to parse the Tcg response received. More...
struct | _TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions. More...

Typedefs

typedef struct _TcgCreateStruct | TcgCreateStruct
Structure that is used to build the Tcg ComPacket. More...
typedef struct _TcgParseStruct | TcgParseStruct
Structure that is used to parse the Tcg response received. More...
typedef struct _TcgToken | TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.

Enumerations

enum TcgResult
Tcg result codes. More...

Functions

TcgResult TCG_CALL | tcgInitTcgCreateStruct (TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct. More...
TcgResult TCG_CALL | tcgStartComPacket (TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure. More...
TcgResult TCG_CALL | tcgStartPacket (TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure. More...
TcgResult TCG_CALL | tcgStartSubPacket (TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndSubPacket (TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure. More...
TcgResult TCG_CALL | tcgEndPacket (TcgCreateStruct *createStruct)
Ends the current Packet in the data structure. More...
TcgResult TCG_CALL | tcgEndComPacket (TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret. More...
TcgResult TCG_CALL | tcgAddRawByte (TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure. More...
TcgResult TCG_CALL | tcgAddByteSequence (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure. More...
TcgResult TCG_CALL | tcgAddInteger (TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT8 (TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT16 (TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT32 (TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddUINT64 (TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure. More...
TcgResult TCG_CALL | tcgAddBOOLEAN (TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure. More...
TcgResult TCG_CALL | tcgAddTcgUid (TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure. More...
TcgResult TCG_CALL | tcgAddStartList (TcgCreateStruct *createStruct)
Adds a Start List token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndList (TcgCreateStruct *createStruct)
Adds an End List token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartName (TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndName (TcgCreateStruct *createStruct)
Adds an End Name token to the data structure. More...
TcgResult TCG_CALL | tcgAddCall (TcgCreateStruct *createStruct)
Adds a Call token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfData (TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndOfSession (TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure. More...
TcgResult TCG_CALL | tcgAddStartTransaction (TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgAddEndTransaction (TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure. More...
TcgResult TCG_CALL | tcgInitTcgParseStruct (TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response. More...
TcgResult TCG_CALL | tcgGetNextToken (TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetNextTokenType (TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload. More...
TcgResult TCG_CALL | tcgGetAtomInfo (const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom. More...
const UINT8 *TCG_CALL | tcgGetTokenByteSequence (const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetTokenUINT64 (const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided. More...
TcgResult TCG_CALL | tcgGetNextUINT8 (TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT16 (TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT32 (TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextUINT64 (TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextBOOLEAN (TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextTcgUid (TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextByteSequence (TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndList (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndName (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextCall (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfData (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndOfSession (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextStartTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...
TcgResult TCG_CALL | tcgGetNextEndTransaction (TcgParseStruct *parseStruct)
Retrieves next token in the current payload. More...

Detailed Description

Public API for the Tcg Core library to perform the lowest level TCG data encoding.

TCG Core public interface header.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgCore.h.

Enumeration Type Documentation

◆ TcgResult

enum TcgResult

Tcg result codes.

The result code indicates if the Tcg function call was successful or not

Enumerator
TcgResult_Success

This is the return result upon successful completion of a Tcg function call.

TcgResult_Failure

This is the return "catchall" result for the failure of a Tcg function call.

TcgResult_Failure_NullPointer

This is the return result if a required parameter was Null for a Tcg function call.

TcgResult_Failure_ZeroSize

This is the return result if a required buffersize was 0 for a Tcg function call.

TcgResult_Failure_InvalidAction

This is the return result if a Tcg function call was executed out of order.

For instance, starting a Tcg subpacket before starting its Tcg packet.

TcgResult_Failure_BufferTooSmall

This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded item.

TcgResult_Failure_EndBuffer

This is the return result for a Tcg parse function if the end of the parsed buffer is reached, yet data is still attempted to be retrieved.

For instance, attempting to retrieve another Tcg token from the buffer after it has reached the end of the Tcg subpacket payload.

TcgResult_Failure_InvalidType

This is the return result for a Tcg parse function if the Tcg Token item requested is not the expected type.

For instance, the caller requested to receive an integer and the Tcg token was a byte sequence.

Definition at line 68 of file TcgCore.h.


AlderLake Platform Sample Code: TcgCore.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
TcgCore.h
Go to the documentation of this file.
1 /** @file
2 Public API for the Tcg Core library to perform the lowest level TCG data encoding.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 /**
37 * @file
38 * TCG Core public interface header
39 */
40
41 #ifndef _TCG_CORE_H_
42 #define _TCG_CORE_H_
43
44 #include <Library/Tcg.h>
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif
49
50 #ifdef _MSC_VER
51 #define TCG_CALL __stdcall
52 #else
53 #define TCG_CALL
54 #endif
55
56 #ifdef _MSC_VER
57 #pragma warning ( push )
58 #pragma warning(disable: 4200)
59 #endif
60
61 #pragma pack(push, 1)
62
63 /**
64 * Tcg result codes.
65 *
66 * The result code indicates if the Tcg function call was successful or not
67 */
68 typedef enum {
69 /**
70 * This is the return result upon successful completion of a Tcg function call
71 */
72 TcgResult_Success,
73
74 /**
75 * This is the return "catchall" result for the failure of a Tcg function call
76 */
77 TcgResult_Failure,
78
79 /**
80 * This is the return result if a required parameter was Null for a Tcg function call
81 */
82 TcgResult_Failure_NullPointer,
83
84 /**
85 * This is the return result if a required buffersize was 0 for a Tcg function call
86 */
87 TcgResult_Failure_ZeroSize,
88
89 /**
90 * This is the return result if a Tcg function call was executed out of order.
91 * For instance, starting a Tcg subpacket before starting its Tcg packet.
92 */
93 TcgResult_Failure_InvalidAction,
94
95 /**
96 * This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded item.
97 */
98 TcgResult_Failure_BufferTooSmall,
99
100 /**
101 * This is the return result for a Tcg parse function if the end of the parsed buffer is reached, yet data is still attempted to be retrieved.
102 * For instance, attempting to retrieve another Tcg token from the buffer after it has reached the end of the Tcg subpacket payload.
103 */
104 TcgResult_Failure_EndBuffer,
105
106 /**
107 * This is the return result for a Tcg parse function if the Tcg Token item requested is not the expected type.
108 * For instance, the caller requested to receive an integer and the Tcg token was a byte sequence.
109 */
110 TcgResult_Failure_InvalidType,
111 } TcgResult;
112
113
114 /**
115 * @defgroup create Create TCG ComPacket Functions
116 *
117 * These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
118 * as defined in the TCG Storage Architecture Core Specification.
119 *
120 * @{
121 */
122
123
124 /**
125 * Structure that is used to build the Tcg ComPacket. It contains the start buffer pointer and the current position of the
126 * Tcg ComPacket, current Tcg Packet and Tcg SubPacket. This structure must be initialized
127 * by calling tcgInitTcgCreateStruct before it is used as parameter to any other Tcg function.
128 * This structure should NOT be directly modified by the client of this library.
129 *
130 * NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
131 * INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
132 *
133 * @sa tcgInitTcgCreateStruct
134 */
135 typedef struct _TcgCreateStruct {
136 /**
137 * Buffer allocated and freed by the client of the Tcg library.
138 * This is the buffer that shall contain the final Tcg encoded compacket.
139 */
140 void* buffer;
141
142 /**
143 * Size of the buffer provided.
144 */
145 UINT32 bufferSize;
146
147 /**
148 * Pointer to the start of the Tcg ComPacket. It should point to a location within buffer.
149 */
150 TcgComPacket* comPacket;
151
152 /**
153 * Current Tcg Packet that is being created. It should point to a location within buffer.
154 */
155 TcgPacket* curPacket;
156
157 /**
158 * Current Tcg SubPacket that is being created. It should point to a location within buffer.
159 */
160 TcgSubPacket* curSubPacket;
161
162 /**
163 * Flag used to indicate if the buffer of the structure should be filled out.
164 * This is intended to be used to support a use-case where the client of library
165 * can perform all the desired tcg calls to determine what the actual size of the final compacket will be.
166 * Then the client can allocate the required buffer size and re-run the tcg calls.
167 * THIS MAY NOT BE IMPLEMENTED... REQUIRES MORE THOUGHT BECAUSE YOU CANNOT SOLVE ISSUE FOR RECEIVE
168 */
169 BOOLEAN dryRun;
170 } TcgCreateStruct;
171
172
173 /**
174 *
175 * Required to be called before calling any other Tcg functions with the TcgCreateStruct.
176 * Initializes the packet variables to NULL. Additionally, the buffer will be memset.
177 */
178 TcgResult TCG_CALL tcgInitTcgCreateStruct(
179
180 /**
181 * [in/out] Structure to initialize
182 */
183 TcgCreateStruct* createStruct,
184
185 /**
186 * [in] Buffer allocated by client of library. It will contain the Tcg encoded packet. This cannot be null.
187 */
188 void* buffer,
189
190 /**
191 * [in] Size of buffer provided. It cannot be 0.
192 */
193 UINT32 bufferSize
194 );
195
196
197 /**
198 *
199 * Encodes the ComPacket header to the data structure.
200 */
201 TcgResult TCG_CALL tcgStartComPacket(
202 /**
203 * [in/out] Structure used to build Tcg Compacket
204 */
205 TcgCreateStruct* createStruct,
206
207 /**
208 * [in] ComID of the Tcg ComPacket.
209 */
210 UINT16 comId,
211
212 /**
213 * [in] ComID Extension of the Tcg ComPacket.
214 */
215 UINT16 comIdExtension
216 );
217
218
219 /**
220 *
221 * Starts a new ComPacket in the data structure.
222 */
223 TcgResult TCG_CALL tcgStartPacket(
224 /**
225 * [in/out] Structure used to add Tcg Packet
226 */
227 TcgCreateStruct* createStruct,
228
229 /**
230 * [in] Packet Tper session number
231 */
232 UINT32 tsn,
233
234 /**
235 * [in] Packet Host session number
236 */
237 UINT32 hsn,
238
239 /**
240 * [in] Packet Sequence Number
241 */
242 UINT32 seqNumber,
243
244 /**
245 * [in] Packet Acknowledge Type
246 */
247 UINT16 ackType,
248
249 /**
250 * [in] Packet Acknowledge
251 */
252 UINT32 ack
253 );
254
255
256 /**
257 *
258 * Starts a new SubPacket in the data structure.
259 */
260 TcgResult TCG_CALL tcgStartSubPacket(
261 /**
262 * [in/out] Structure used to start Tcg SubPacket
263 */
264 TcgCreateStruct* createStruct,
265
266 /**
267 * [in] SubPacket kind
268 */
269 UINT16 kind
270 );
271
272
273 /**
274 *
275 * Ends the current SubPacket in the data structure. This function will also perform the 4-byte padding
276 * required for Subpackets.
277 */
278 TcgResult TCG_CALL tcgEndSubPacket(
279 /**
280 * [in/out] Structure used to end the current Tcg SubPacket
281 */
282 TcgCreateStruct* createStruct
283 );
284
285
286 /**
287 *
288 * Ends the current Packet in the data structure.
289 */
290 TcgResult TCG_CALL tcgEndPacket(
291 /**
292 * [in/out] Structure used to end the current Tcg Packet
293 */
294 TcgCreateStruct* createStruct
295 );
296
297
298 /**
299 *
300 * Ends the ComPacket in the data structure and ret
301 */
302 TcgResult TCG_CALL tcgEndComPacket(
303 /**
304 * [in/out] Structure used to end the Tcg ComPacket
305 */
306 TcgCreateStruct* createStruct,
307
308 /**
309 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
310 */
311 UINT32* size
312 );
313
314
315 /**
316 * @defgroup createSubPacket Create TCG SubPacket Functions
317 *
318 * These functions encode tokens contained in a SubPacket
319 * as defined in the TCG Storage Architecture Core Specification.
320 *
321 * @{
322 */
323
324
325
326 /**
327 * @defgroup createAtom Create TCG Atom Functions
328 *
329 * These functions encode simple atom tokens contained in a SubPacket
330 * as defined in the TCG Storage Architecture Core Specification.
331 *
332 * @{
333 */
334
335 /**
336 *
337 * Adds a single raw token byte to the data structure.
338 */
339 TcgResult TCG_CALL tcgAddRawByte(
340 /**
341 * [in/out] Structure used to add the byte
342 */
343 TcgCreateStruct* createStruct,
344
345 /**
346 * [in] Byte to add
347 */
348 UINT8 byte
349 );
350
351
352 /**
353 *
354 * Adds the data parameter as a byte sequence to the data structure.
355 */
356 TcgResult TCG_CALL tcgAddByteSequence(
357 /**
358 * [in/out] Structure used to add the byte sequence
359 */
360 TcgCreateStruct* createStruct,
361
362 /**
363 * [in] Byte sequence that will be encoded and copied into data structure
364 */
365 const void* data,
366
367 /**
368 * [in] Length of data provided
369 */
370 UINT32 dataSize,
371
372 /**
373 * [in] TRUE if byte sequence is continued or
374 * FALSE if the data contains the entire byte sequence to be encoded
375 */
376 BOOLEAN continued
377 );
378
379
380 /**
381 *
382 * Adds an arbitrary-length integer to the data structure.
383 *
384 * The integer will be encoded using the shortest possible atom.
385 */
386 TcgResult TCG_CALL tcgAddInteger(
387 /**
388 * [in/out] Structure used to add the integer
389 */
390 TcgCreateStruct* createStruct,
391
392 /**
393 * [in] Integer in host byte order that will be encoded and copied into data structure
394 */
395 const void* data,
396
397 /**
398 * [in] Length in bytes of the data provided
399 */
400 UINT32 dataSize,
401
402 /**
403 * [in] TRUE if the integer is signed or FALSE if the integer is unsigned
404 */
405 BOOLEAN signedInteger
406 );
407
408
409 /**
410 *
411 * Adds an 8-bit unsigned integer to the data structure.
412 */
413 TcgResult TCG_CALL tcgAddUINT8(
414 /**
415 * [in/out] Structure used to add the integer
416 */
417 TcgCreateStruct* createStruct,
418
419 /**
420 * [in] Integer value to add
421 */
422 UINT8 value
423 );
424
425
426 /**
427 *
428 * Adds a 16-bit unsigned integer to the data structure.
429 */
430 TcgResult TCG_CALL tcgAddUINT16(
431 /**
432 * [in/out] Structure used to add the integer
433 */
434 TcgCreateStruct* createStruct,
435
436 /**
437 * [in] Integer value to add
438 */
439 UINT16 value
440 );
441
442
443 /**
444 *
445 * Adds a 32-bit unsigned integer to the data structure.
446 */
447 TcgResult TCG_CALL tcgAddUINT32(
448 /**
449 * [in/out] Structure used to add the integer
450 */
451 TcgCreateStruct* createStruct,
452
453 /**
454 * [in] Integer value to add
455 */
456 UINT32 value
457 );
458
459
460 /**
461 *
462 * Adds a 64-bit unsigned integer to the data structure.
463 */
464 TcgResult TCG_CALL tcgAddUINT64(
465 /**
466 * [in/out] Structure used to add the integer
467 */
468 TcgCreateStruct* createStruct,
469
470 /**
471 * [in] Integer value to add
472 */
473 UINT64 value
474 );
475
476
477 /**
478 *
479 * Adds a BOOLEAN to the data structure.
480 */
481 TcgResult TCG_CALL tcgAddBOOLEAN(
482 /**
483 * [in/out] Structure used to add the integer
484 */
485 TcgCreateStruct* createStruct,
486
487 /**
488 * [in] BOOLEAN value to add
489 */
490 BOOLEAN value
491 );
492
493
494 /**
495 *
496 * Adds a TcgUid to the data structure.
497 */
498 TcgResult TCG_CALL tcgAddTcgUid(
499 /**
500 * [in/out] Structure used to add the TcgUid
501 */
502 TcgCreateStruct* createStruct,
503
504 /**
505 * [in] TcgUid value to add
506 */
507 TcgUid uid
508 );
509
510
511 /** @} */ // end of atom functions
512
513
514 /**
515 * @defgroup createSequenceTokens Create TCG Sequence Token Functions
516 *
517 * These functions encode sequence tokens contained in a SubPacket
518 * as defined in the TCG Storage Architecture Core Specification.
519 *
520 * @{
521 */
522
523 /**
524 *
525 * Adds a Start List token to the data structure.
526 */
527 TcgResult TCG_CALL tcgAddStartList(
528 /**
529 * [in/out] Structure used to add the token
530 */
531 TcgCreateStruct* createStruct
532 );
533
534
535 /**
536 *
537 * Adds an End List token to the data structure.
538 */
539 TcgResult TCG_CALL tcgAddEndList(
540 /**
541 * [in/out] Structure used to add the token
542 */
543 TcgCreateStruct* createStruct
544 );
545
546
547 /**
548 *
549 * Adds a Start Name token to the data structure.
550 */
551 TcgResult TCG_CALL tcgAddStartName(
552 /**
553 * [in/out] Structure used to add the token
554 */
555 TcgCreateStruct* createStruct
556 );
557
558
559 /**
560 *
561 * Adds an End Name token to the data structure.
562 */
563 TcgResult TCG_CALL tcgAddEndName(
564 /**
565 * [in/out] Structure used to add the token
566 */
567 TcgCreateStruct* createStruct
568 );
569
570
571 /** @} */ // end of sequence token functions
572
573
574 /**
575 * @defgroup createControlTokens Create TCG Control Token Functions
576 *
577 * These functions encode sequence tokens contained in a SubPacket
578 * as defined in the TCG Storage Architecture Core Specification.
579 *
580 * @{
581 */
582
583 /**
584 *
585 * Adds a Call token to the data structure.
586 */
587 TcgResult TCG_CALL tcgAddCall(
588 /**
589 * [in/out] Structure used to add the token
590 */
591 TcgCreateStruct* createStruct
592 );
593
594
595 /**
596 *
597 * Adds an End of Data token to the data structure.
598 */
599 TcgResult TCG_CALL tcgAddEndOfData(
600 /**
601 * [in/out] Structure used to add the token
602 */
603 TcgCreateStruct* createStruct
604 );
605
606
607 /**
608 *
609 * Adds an End of Session token to the data structure.
610 */
611 TcgResult TCG_CALL tcgAddEndOfSession(
612 /**
613 * [in/out] Structure used to add the token
614 */
615 TcgCreateStruct* createStruct
616 );
617
618
619 /**
620 *
621 * Adds a Start Transaction token to the data structure.
622 */
623 TcgResult TCG_CALL tcgAddStartTransaction(
624 /**
625 * [in/out] Structure used to add the token
626 */
627 TcgCreateStruct* createStruct
628 );
629
630
631 /**
632 *
633 * Adds an End Transaction token to the data structure.
634 */
635 TcgResult TCG_CALL tcgAddEndTransaction(
636 /**
637 * [in/out] Structure used to add the token
638 */
639 TcgCreateStruct* createStruct
640 );
641
642 /** @} */ // end of control token functions
643
644 /** @} */ // end of createSubPacket functions
645
646 /** @} */ // end of create functions
647
648
649
650 /**
651 * @defgroup parse Parse TCG ComPacket Functions
652 *
653 * These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
654 * as defined in the TCG Storage Architecture Core Specification.
655 *
656 * @{
657 */
658
659
660 /**
661 * Structure that is used to parse the Tcg response received. It contains the response buffer pointer
662 * and the current position of the Tcg ComPacket, current Tcg Packet and Tcg SubPacket being parsed.
663 * This structure must be initialized by calling tcgInitTcgParseStruct before it is used as parameter to any other Tcg parse function.
664 * This structure should NOT be directly modified by the client of this library.
665 *
666 * NOTE: WE MAY MAKE THIS AN ABSTRACT STRUCTURE WITH A DEFINED SIZE AND KEEP THE VARIABLES
667 * INTERNAL AND ONLY KNOWN TO THE TCG LIBRARY
668 *
669 * @sa tcgInitTcgParseStruct
670 */
671 typedef struct _TcgParseStruct {
672 /**
673 * Buffer allocated and freed by the client of the Tcg library.
674 * This is the buffer that contains the Tcg response to decode/parse.
675 */
676 const void* buffer;
677
678 /**
679 * Size of the buffer provided.
680 */
681 UINT32 bufferSize;
682
683 /**
684 * Pointer to the start of the Tcg ComPacket. It should point to a location within buffer.
685 */
686 const TcgComPacket* comPacket;
687
688 /**
689 * Current Tcg Packet that is being created. It should point to a location within buffer.
690 */
691 const TcgPacket* curPacket;
692
693 /**
694 * Current Tcg SubPacket that is being created. It should point to a location within buffer.
695 */
696 const TcgSubPacket* curSubPacket;
697
698 /**
699 * Current pointer within the current subpacket payload.
700 */
701 const UINT8* curPtr;
702 } TcgParseStruct;
703
704
705 /**
706 * Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
707 */
708 typedef struct _TcgToken {
709 /**
710 * Describes the type of Tcg token the hdr start points to.
711 */
712 TcgTokenType type;
713
714 /**
715 * Pointer to the beginning of the header of the Tcg token
716 */
717 const UINT8* hdrStart;
718 } TcgToken;
719
720
721 /**
722 *
723 * Intializes the parsing structure used to parse the Tcg response. This must be called before using the
724 * parseStruct with any other function.
725 */
726 TcgResult TCG_CALL tcgInitTcgParseStruct(
727 /**
728 * [in/out] Structure used to parse received TCG response
729 */
730 TcgParseStruct* parseStruct,
731
732 /**
733 * [in] Buffer containing TCG response
734 */
735 const void* buffer,
736
737 /**
738 * [in] Size of buffer containing TCG response
739 */
740 UINT32 bufferSize
741 );
742
743
744 /**
745 *
746 * Retrieves next Tcg Token from the current subpacket payload. The first time it is called on a parse structure
747 * it starts at the first Subpacket of the first Packet.
748 */
749 TcgResult TCG_CALL tcgGetNextToken(
750 /**
751 * [in/out] Structure used to parse received TCG response
752 */
753 TcgParseStruct* parseStruct,
754
755 /**
756 * [in/out] Tcg Token that was found. Buffer was verified to guarantee the entire Token can be accessed by caller.
757 */
758 TcgToken* tcgToken
759 );
760
761
762 /**
763 * Retrieves the next TCG token from the current subpacket payload.
764 * If the token is not of the specified type, an error is returned.
765 *
766 * This function is intended for use with sequence and control tokens that have no payload,
767 * since it does not return the token contents.
768 */
769 TcgResult TCG_CALL tcgGetNextTokenType(
770 /**
771 * [in/out] Structure used to parse received TCG response
772 */
773 TcgParseStruct* parseStruct,
774
775 /**
776 * [in] Expected TCG token type
777 */
778 TcgTokenType type
779 );
780
781
782 /**
783 *
784 * Retrieves information about a simple token containing an atom.
785 */
786 TcgResult TCG_CALL tcgGetAtomInfo(
787 /**
788 * [in/out] TCG token containing simple token atom to retrieve
789 */
790 const TcgToken* tcgToken,
791
792 /**
793 * [out] Length of token header.
794 *
795 * This is the number of bytes from the start of the token up to the beginning of the data.
796 */
797 UINT32* headerLength,
798
799 /**
800 * [out] Length of data.
801 *
802 * This is the size of the byte or integer data following the token header.
803 */
804 UINT32* dataLength,
805
806 /**
807 * [out] Flag indicating whether the atom is a byte sequence (TCG_ATOM_TYPE_BYTE) or integer (TCG_ATOM_TYPE_INTEGER).
808 */
809 UINT8* byteOrInt,
810
811 /**
812 * [out] Flag indicating whether an integer atom is a signed integer or whether a byte sequence atom is continued.
813 */
814 UINT8* signOrCont
815 );
816
817
818 /**
819 *
820 * Retrieves byte sequence from the Tcg Token provided.
821 *
822 * @return NULL if failure occurs, otherwise pointer to beginning of byte sequence.
823 */
824 const UINT8* TCG_CALL tcgGetTokenByteSequence(
825 /**
826 * [in/out] Tcg Token containing byte sequence value to retrieve
827 */
828 const TcgToken* tcgToken,
829
830 /**
831 * [out] Length of the byte sequence retrieved
832 */
833 UINT32* length
834 );
835
836
837 /**
838 *
839 * Retrieves Integer value up to 64-bits in size from the Tcg Token provided.
840 */
841 TcgResult TCG_CALL tcgGetTokenUINT64(
842 /**
843 * [in/out] Tcg Token containing integer value to retrieve
844 */
845 const TcgToken* tcgToken,
846
847 /**
848 * [in/out] Integer value retrieved
849 */
850 UINT64* value
851 );
852
853
854 /**
855 *
856 * Retrieves next token in the current payload. If it is not a UINT8 then a failure is reported.
857 */
858 TcgResult TCG_CALL tcgGetNextUINT8(
859 /**
860 * [in/out] Structure used to parse received TCG response
861 */
862 TcgParseStruct* parseStruct,
863
864 /**
865 * [in/out] UINT8 value retrieved from current payload
866 */
867 UINT8* value
868 );
869
870
871 /**
872 *
873 * Retrieves next token in the current payload. If it is not a UINT16 then a failure is reported.
874 */
875 TcgResult TCG_CALL tcgGetNextUINT16(
876 /**
877 * [in/out] Structure used to parse received TCG response
878 */
879 TcgParseStruct* parseStruct,
880
881 /**
882 * [in/out] UINT16 value retrieved from current payload
883 */
884 UINT16* value
885 );
886
887
888 /**
889 *
890 * Retrieves next token in the current payload. If it not a UINT32 then a failure is reported.
891 */
892 TcgResult TCG_CALL tcgGetNextUINT32(
893 /**
894 * [in/out] Structure used to parse received TCG response
895 */
896 TcgParseStruct* parseStruct,
897
898 /**
899 * [in/out] UINT32 value retrieved from current payload
900 */
901 UINT32* value
902 );
903
904
905 /**
906 *
907 * Retrieves next token in the current payload. If it is not a UINT64 then a failure is reported.
908 */
909 TcgResult TCG_CALL tcgGetNextUINT64(
910 /**
911 * [in/out] Structure used to parse received TCG response
912 */
913 TcgParseStruct* parseStruct,
914
915 /**
916 * [in/out] UINT64 value retrieved from current payload
917 */
918 UINT64* value
919 );
920
921
922 /**
923 *
924 * Retrieves next token in the current payload. If it not a BOOLEAN then a failure is reported.
925 */
926 TcgResult TCG_CALL tcgGetNextBOOLEAN(
927 /**
928 * [in/out] Structure used to parse received TCG response
929 */
930 TcgParseStruct* parseStruct,
931
932 /**
933 * [in/out] BOOLEAN value retrieved from current payload
934 */
935 BOOLEAN* value
936 );
937
938 /**
939 *
940 * Retrieves next token in the current payload. If it is not a TcgUid then a failure is reported.
941 */
942 TcgResult TCG_CALL tcgGetNextTcgUid(
943 /**
944 * [in/out] Structure used to parse received TCG response
945 */
946 TcgParseStruct* parseStruct,
947
948 /**
949 * [out] TcgUid value retrieved from current payload
950 */
951 TcgUid* uid
952 );
953
954
955 /**
956 *
957 * Retrieves next token in the current payload. If it is not a byte sequence, then a failure is reported.
958 */
959 TcgResult TCG_CALL tcgGetNextByteSequence(
960 /**
961 * [in/out] Structure used to parse received TCG response
962 */
963 TcgParseStruct* parseStruct,
964
965 /**
966 * [out] Pointer to the beginning of the byte sequence
967 */
968 const void** data,
969
970 /**
971 * [out] Length of the retrieved byte sequence in bytes
972 */
973 UINT32* length
974 );
975
976
977 /**
978 *
979 * Retrieves next token in the current payload. If it is not a Start List token, then a failure is reported.
980 */
981 TcgResult TCG_CALL tcgGetNextStartList(
982 /**
983 * [in/out] Structure used to parse received TCG response
984 */
985 TcgParseStruct* parseStruct
986 );
987
988
989 /**
990 *
991 * Retrieves next token in the current payload. If it is not an End List token, then a failure is reported.
992 */
993 TcgResult TCG_CALL tcgGetNextEndList(
994 /**
995 * [in/out] Structure used to parse received TCG response
996 */
997 TcgParseStruct* parseStruct
998 );
999
1000
1001 /**
1002 *
1003 * Retrieves next token in the current payload. If it is not a Start Name token, then a failure is reported.
1004 */
1005 TcgResult TCG_CALL tcgGetNextStartName(
1006 /**
1007 * [in/out] Structure used to parse received TCG response
1008 */
1009 TcgParseStruct* parseStruct
1010 );
1011
1012
1013 /**
1014 *
1015 * Retrieves next token in the current payload. If it is not an End Name token, then a failure is reported.
1016 */
1017 TcgResult TCG_CALL tcgGetNextEndName(
1018 /**
1019 * [in/out] Structure used to parse received TCG response
1020 */
1021 TcgParseStruct* parseStruct
1022 );
1023
1024
1025 /**
1026 *
1027 * Retrieves next token in the current payload. If it is not a Call token, then a failure is reported.
1028 */
1029 TcgResult TCG_CALL tcgGetNextCall(
1030 /**
1031 * [in/out] Structure used to parse received TCG response
1032 */
1033 TcgParseStruct* parseStruct
1034 );
1035
1036
1037 /**
1038 *
1039 * Retrieves next token in the current payload. If it is not an End of Data token, then a failure is reported.
1040 */
1041 TcgResult TCG_CALL tcgGetNextEndOfData(
1042 /**
1043 * [in/out] Structure used to parse received TCG response
1044 */
1045 TcgParseStruct* parseStruct
1046 );
1047
1048
1049 /**
1050 *
1051 * Retrieves next token in the current payload. If it is not an End of Session token, then a failure is reported.
1052 */
1053 TcgResult TCG_CALL tcgGetNextEndOfSession(
1054 /**
1055 * [in/out] Structure used to parse received TCG response
1056 */
1057 TcgParseStruct* parseStruct
1058 );
1059
1060
1061 /**
1062 *
1063 * Retrieves next token in the current payload. If it is not a Start Transaction token, then a failure is reported.
1064 */
1065 TcgResult TCG_CALL tcgGetNextStartTransaction(
1066 /**
1067 * [in/out] Structure used to parse received TCG response
1068 */
1069 TcgParseStruct* parseStruct
1070 );
1071
1072
1073 /**
1074 *
1075 * Retrieves next token in the current payload. If it is not an End Transaction token, then a failure is reported.
1076 */
1077 TcgResult TCG_CALL tcgGetNextEndTransaction(
1078 /**
1079 * [in/out] Structure used to parse received TCG response
1080 */
1081 TcgParseStruct* parseStruct
1082 );
1083
1084 /** @} */ // end of parse functions
1085
1086
1087 #pragma pack(pop)
1088 #ifdef _MSC_VER
1089 #pragma warning(pop) // C4200 zero-sized array
1090 #endif
1091
1092 #ifdef __cplusplus
1093 }
1094 #endif
1095
1096 #endif // _TCG_CORE_H_
tcgAddUINT32
TcgResult TCG_CALL tcgAddUINT32(TcgCreateStruct *createStruct, UINT32 value)
Adds a 32-bit unsigned integer to the data structure.
_TcgCreateStruct::buffer
void * buffer
Buffer allocated and freed by the client of the Tcg library.
Definition: TcgCore.h:140
tcgAddTcgUid
TcgResult TCG_CALL tcgAddTcgUid(TcgCreateStruct *createStruct, TcgUid uid)
Adds a TcgUid to the data structure.
tcgAddUINT8
TcgResult TCG_CALL tcgAddUINT8(TcgCreateStruct *createStruct, UINT8 value)
Adds an 8-bit unsigned integer to the data structure.
tcgGetNextStartList
TcgResult TCG_CALL tcgGetNextStartList(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgParseStruct::bufferSize
UINT32 bufferSize
Size of the buffer provided.
Definition: TcgCore.h:681
tcgAddEndOfSession
TcgResult TCG_CALL tcgAddEndOfSession(TcgCreateStruct *createStruct)
Adds an End of Session token to the data structure.
tcgGetNextEndName
TcgResult TCG_CALL tcgGetNextEndName(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
Definition: TcgCore.h:708
_TcgCreateStruct::comPacket
TcgComPacket * comPacket
Pointer to the start of the Tcg ComPacket.
Definition: TcgCore.h:150
tcgGetNextUINT8
TcgResult TCG_CALL tcgGetNextUINT8(TcgParseStruct *parseStruct, UINT8 *value)
Retrieves next token in the current payload.
tcgStartPacket
TcgResult TCG_CALL tcgStartPacket(TcgCreateStruct *createStruct, UINT32 tsn, UINT32 hsn, UINT32 seqNumber, UINT16 ackType, UINT32 ack)
Starts a new ComPacket in the data structure.
tcgAddStartName
TcgResult TCG_CALL tcgAddStartName(TcgCreateStruct *createStruct)
Adds a Start Name token to the data structure.
tcgAddUINT64
TcgResult TCG_CALL tcgAddUINT64(TcgCreateStruct *createStruct, UINT64 value)
Adds a 64-bit unsigned integer to the data structure.
tcgGetNextStartName
TcgResult TCG_CALL tcgGetNextStartName(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgGetNextTokenType
TcgResult TCG_CALL tcgGetNextTokenType(TcgParseStruct *parseStruct, TcgTokenType type)
Retrieves the next TCG token from the current subpacket payload.
Tcg.h
TCG defined values and structures used by the Tcg Core library.
_TcgCreateStruct::dryRun
BOOLEAN dryRun
Flag used to indicate if the buffer of the structure should be filled out.
Definition: TcgCore.h:169
tcgGetTokenUINT64
TcgResult TCG_CALL tcgGetTokenUINT64(const TcgToken *tcgToken, UINT64 *value)
Retrieves Integer value up to 64-bits in size from the Tcg Token provided.
tcgStartSubPacket
TcgResult TCG_CALL tcgStartSubPacket(TcgCreateStruct *createStruct, UINT16 kind)
Starts a new SubPacket in the data structure.
tcgGetNextEndList
TcgResult TCG_CALL tcgGetNextEndList(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
TcgResult_Failure_ZeroSize
@ TcgResult_Failure_ZeroSize
This is the return result if a required buffersize was 0 for a Tcg function call.
Definition: TcgCore.h:87
tcgGetNextUINT16
TcgResult TCG_CALL tcgGetNextUINT16(TcgParseStruct *parseStruct, UINT16 *value)
Retrieves next token in the current payload.
TcgResult
TcgResult
Tcg result codes.
Definition: TcgCore.h:68
tcgEndSubPacket
TcgResult TCG_CALL tcgEndSubPacket(TcgCreateStruct *createStruct)
Ends the current SubPacket in the data structure.
_TcgParseStruct::curPtr
const UINT8 * curPtr
Current pointer within the current subpacket payload.
Definition: TcgCore.h:701
TcgResult_Failure_InvalidType
@ TcgResult_Failure_InvalidType
This is the return result for a Tcg parse function if the Tcg Token item requested is not the expecte...
Definition: TcgCore.h:110
tcgGetNextStartTransaction
TcgResult TCG_CALL tcgGetNextStartTransaction(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
_TcgCreateStruct::curSubPacket
TcgSubPacket * curSubPacket
Current Tcg SubPacket that is being created.
Definition: TcgCore.h:160
tcgAddEndName
TcgResult TCG_CALL tcgAddEndName(TcgCreateStruct *createStruct)
Adds an End Name token to the data structure.
_TcgParseStruct::curPacket
const TcgPacket * curPacket
Current Tcg Packet that is being created.
Definition: TcgCore.h:691
_TcgToken::type
TcgTokenType type
Describes the type of Tcg token the hdr start points to.
Definition: TcgCore.h:712
tcgGetNextBOOLEAN
TcgResult TCG_CALL tcgGetNextBOOLEAN(TcgParseStruct *parseStruct, BOOLEAN *value)
Retrieves next token in the current payload.
tcgAddInteger
TcgResult TCG_CALL tcgAddInteger(TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN signedInteger)
Adds an arbitrary-length integer to the data structure.
tcgAddStartList
TcgResult TCG_CALL tcgAddStartList(TcgCreateStruct *createStruct)
Adds a Start List token to the data structure.
tcgGetAtomInfo
TcgResult TCG_CALL tcgGetAtomInfo(const TcgToken *tcgToken, UINT32 *headerLength, UINT32 *dataLength, UINT8 *byteOrInt, UINT8 *signOrCont)
Retrieves information about a simple token containing an atom.
tcgEndComPacket
TcgResult TCG_CALL tcgEndComPacket(TcgCreateStruct *createStruct, UINT32 *size)
Ends the ComPacket in the data structure and ret.
TcgResult_Failure_InvalidAction
@ TcgResult_Failure_InvalidAction
This is the return result if a Tcg function call was executed out of order.
Definition: TcgCore.h:93
_TcgParseStruct::curSubPacket
const TcgSubPacket * curSubPacket
Current Tcg SubPacket that is being created.
Definition: TcgCore.h:696
tcgGetNextTcgUid
TcgResult TCG_CALL tcgGetNextTcgUid(TcgParseStruct *parseStruct, TcgUid *uid)
Retrieves next token in the current payload.
tcgGetTokenByteSequence
const UINT8 *TCG_CALL tcgGetTokenByteSequence(const TcgToken *tcgToken, UINT32 *length)
Retrieves byte sequence from the Tcg Token provided.
tcgAddEndTransaction
TcgResult TCG_CALL tcgAddEndTransaction(TcgCreateStruct *createStruct)
Adds an End Transaction token to the data structure.
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
_TcgParseStruct::buffer
const void * buffer
Buffer allocated and freed by the client of the Tcg library.
Definition: TcgCore.h:676
TcgResult_Success
@ TcgResult_Success
This is the return result upon successful completion of a Tcg function call.
Definition: TcgCore.h:72
tcgGetNextUINT32
TcgResult TCG_CALL tcgGetNextUINT32(TcgParseStruct *parseStruct, UINT32 *value)
Retrieves next token in the current payload.
tcgAddCall
TcgResult TCG_CALL tcgAddCall(TcgCreateStruct *createStruct)
Adds a Call token to the data structure.
_TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
Definition: TcgCore.h:135
tcgInitTcgCreateStruct
TcgResult TCG_CALL tcgInitTcgCreateStruct(TcgCreateStruct *createStruct, void *buffer, UINT32 bufferSize)
Required to be called before calling any other Tcg functions with the TcgCreateStruct.
_TcgCreateStruct::bufferSize
UINT32 bufferSize
Size of the buffer provided.
Definition: TcgCore.h:145
tcgAddRawByte
TcgResult TCG_CALL tcgAddRawByte(TcgCreateStruct *createStruct, UINT8 byte)
Adds a single raw token byte to the data structure.
TcgResult_Failure_NullPointer
@ TcgResult_Failure_NullPointer
This is the return result if a required parameter was Null for a Tcg function call.
Definition: TcgCore.h:82
TcgResult_Failure
@ TcgResult_Failure
This is the return "catchall" result for the failure of a Tcg function call.
Definition: TcgCore.h:77
tcgGetNextEndTransaction
TcgResult TCG_CALL tcgGetNextEndTransaction(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgAddEndList
TcgResult TCG_CALL tcgAddEndList(TcgCreateStruct *createStruct)
Adds an End List token to the data structure.
_TcgCreateStruct::curPacket
TcgPacket * curPacket
Current Tcg Packet that is being created.
Definition: TcgCore.h:155
TcgCreateStruct
struct _TcgCreateStruct TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
tcgGetNextEndOfSession
TcgResult TCG_CALL tcgGetNextEndOfSession(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgAddStartTransaction
TcgResult TCG_CALL tcgAddStartTransaction(TcgCreateStruct *createStruct)
Adds a Start Transaction token to the data structure.
TcgParseStruct
struct _TcgParseStruct TcgParseStruct
Structure that is used to parse the Tcg response received.
_TcgParseStruct::comPacket
const TcgComPacket * comPacket
Pointer to the start of the Tcg ComPacket.
Definition: TcgCore.h:686
_TcgToken::hdrStart
const UINT8 * hdrStart
Pointer to the beginning of the header of the Tcg token.
Definition: TcgCore.h:717
tcgEndPacket
TcgResult TCG_CALL tcgEndPacket(TcgCreateStruct *createStruct)
Ends the current Packet in the data structure.
tcgGetNextUINT64
TcgResult TCG_CALL tcgGetNextUINT64(TcgParseStruct *parseStruct, UINT64 *value)
Retrieves next token in the current payload.
tcgAddBOOLEAN
TcgResult TCG_CALL tcgAddBOOLEAN(TcgCreateStruct *createStruct, BOOLEAN value)
Adds a BOOLEAN to the data structure.
_TcgParseStruct
Structure that is used to parse the Tcg response received.
Definition: TcgCore.h:671
TcgToken
struct _TcgToken TcgToken
Structure that is used to represent a Tcg Token that is retrieved by Tcg parse functions.
tcgInitTcgParseStruct
TcgResult TCG_CALL tcgInitTcgParseStruct(TcgParseStruct *parseStruct, const void *buffer, UINT32 bufferSize)
Intializes the parsing structure used to parse the Tcg response.
TcgResult_Failure_BufferTooSmall
@ TcgResult_Failure_BufferTooSmall
This is the return result if the buffersize provided is not big enough to add a requested Tcg encoded...
Definition: TcgCore.h:98
tcgGetNextByteSequence
TcgResult TCG_CALL tcgGetNextByteSequence(TcgParseStruct *parseStruct, const void **data, UINT32 *length)
Retrieves next token in the current payload.
tcgGetNextEndOfData
TcgResult TCG_CALL tcgGetNextEndOfData(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgAddUINT16
TcgResult TCG_CALL tcgAddUINT16(TcgCreateStruct *createStruct, UINT16 value)
Adds a 16-bit unsigned integer to the data structure.
tcgGetNextCall
TcgResult TCG_CALL tcgGetNextCall(TcgParseStruct *parseStruct)
Retrieves next token in the current payload.
tcgAddByteSequence
TcgResult TCG_CALL tcgAddByteSequence(TcgCreateStruct *createStruct, const void *data, UINT32 dataSize, BOOLEAN continued)
Adds the data parameter as a byte sequence to the data structure.
TcgResult_Failure_EndBuffer
@ TcgResult_Failure_EndBuffer
This is the return result for a Tcg parse function if the end of the parsed buffer is reached,...
Definition: TcgCore.h:104
tcgStartComPacket
TcgResult TCG_CALL tcgStartComPacket(TcgCreateStruct *createStruct, UINT16 comId, UINT16 comIdExtension)
Encodes the ComPacket header to the data structure.
tcgAddEndOfData
TcgResult TCG_CALL tcgAddEndOfData(TcgCreateStruct *createStruct)
Adds an End of Data token to the data structure.
tcgGetNextToken
TcgResult TCG_CALL tcgGetNextToken(TcgParseStruct *parseStruct, TcgToken *tcgToken)
Retrieves next Tcg Token from the current subpacket payload.


AlderLake Platform Sample Code: TcgSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros
TcgSetup.h File Reference

Go to the source code of this file.

Macros

#define TCG_SETUP_REVISION 1
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgSetup.h.


AlderLake Platform Sample Code: TcgSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
TcgSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2011 - 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _TCG_SETUP_H_
35 #define _TCG_SETUP_H_
36
37 #define TCG_SETUP_NAME L"TcgSetup"
38
39 #pragma pack(1)
40
41 /**
42 Making any setup structure change after code frozen
43 will need to maintain backward compatibility, bump up
44 structure revision and update below history table\n
45 <b>Revision 1</b>: - Initial version.
46 **/
47 #define TCG_SETUP_REVISION 1
48
49 typedef struct {
50 UINT8 dTpm12Present;
51 BOOLEAN HideTpm;
52 UINT8 TpmCurrentState;
53 BOOLEAN MorState;
54 UINT8 dTpm20Present;
55 UINT8 TpmOperation;
56 UINT8 PttPresent;
57 } TCG_SETUP;
58 #pragma pack()
59
60 #ifndef OFFSET_OF
61 #ifdef __GNUC__
62 #if __GNUC__ >= 4
63 #define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field))
64 #endif
65 #endif
66 #endif
67
68 #ifndef OFFSET_OF
69 #define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
70 #endif
71 #define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYPE##Field[(OFFSET_OF(TYPE, Field) == Offset) / (OFFSET_OF(TYPE, Field) == Offset)]
72
73 //
74 // If TpmSupport/MorStae isn't in this offset, build failure (0 size array or divided by 0) will be generated.
75 // Platform DSC file maps the two field to HII PCD so the offset value is critical.
76 //
77 VERIFY_OFFSET (TCG_SETUP, HideTpm, 0x1);
78 VERIFY_OFFSET (TCG_SETUP, MorState, 0x3);
79 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: TcgUtil.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Functions
TcgUtil.h File Reference

Provides TCG high-level API to perform common TCG actions on a TCG data packet. More...

#include <Library/TcgCore.h>
Include dependency graph for TcgUtil.h:

Go to the source code of this file.

Functions

TcgResult TCG_CALL | tcgStartMethodCall (TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided. More...
TcgResult TCG_CALL | tcgStartParameters (TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndParameters (TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure. More...
TcgResult TCG_CALL | tcgEndMethodCall (TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list. More...
TcgResult TCG_CALL | tcgCreateStartSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure. More...
TcgResult TCG_CALL | tcgCreateSetCPin (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified. More...
TcgResult TCG_CALL | tcgSetAuthorityEnabled (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified. More...
TcgResult TCG_CALL | tcgCreateEndSession (TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession. More...
const char *TCG_CALL | tcgTokenTypeString (TcgTokenType type)
Retrieves human-readable token type name. More...
TcgResult TCG_CALL | tcgGetMethodStatus (const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket. More...
const char *TCG_CALL | tcgMethodStatusString (UINT8 methodStatus)
Returns a human-readable string representing a method status return code. More...
TcgResult TCG_CALL | tcgGetComIds (const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response. More...
TcgResult TCG_CALL | tcgCheckComIds (const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values. More...
TcgResult TCG_CALL | tcgParseSyncSession (const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. More...
BOOLEAN TCG_CALL | tcgIsProtocolSupported (const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list. More...
BOOLEAN TCG_CALL | tcgIsLocked (const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response. More...

Detailed Description

Provides TCG high-level API to perform common TCG actions on a TCG data packet.

TCG Core utility public interface header.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcgUtil.h.


AlderLake Platform Sample Code: TcgUtil.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
TcgUtil.h
Go to the documentation of this file.
1 /** @file
2 Provides TCG high-level API to perform common TCG actions on a TCG data packet.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 /**
37 * @file
38 * TCG Core utility public interface header
39 */
40
41 #ifndef _TCG_UTIL_H_
42 #define _TCG_UTIL_H_
43
44 #include <Library/TcgCore.h>
45 #ifdef __cplusplus
46 extern "C"
47 {
48 #endif
49
50 #ifdef _MSC_VER
51 #pragma warning ( push )
52 #pragma warning(disable: 4200)
53 #endif
54
55 #pragma pack(push, 1)
56
57 /**
58 * @defgroup commonCreate Common Create TCG Utility Functions
59 *
60 * These functions encode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
61 * as defined in the TCG Storage Architecture Core Specification.
62 *
63 * @{
64 */
65
66 /**
67 *
68 * Adds start Method Call to the data structure using invoking id and method Id provided.
69 */
70 TcgResult TCG_CALL tcgStartMethodCall(
71 /**
72 * [in/out] Structure used to add the method call
73 */
74 TcgCreateStruct* createStruct,
75
76 /**
77 * [in] Invoking ID for the method call
78 */
79 TcgUid invokingId,
80
81 /**
82 * [in] Method ID for the method call
83 */
84 TcgUid methodId
85 );
86
87 /**
88 *
89 * Adds start parameters (STARTLIST) to the data structure.
90 */
91 TcgResult TCG_CALL tcgStartParameters(
92 /**
93 * [in/out] Structure used to add the start parameters
94 */
95 TcgCreateStruct* createStruct
96 );
97
98 /**
99 *
100 * Adds end parameters (ENDLIST) to the data structure.
101 */
102 TcgResult TCG_CALL tcgEndParameters(
103 /**
104 * [in/out] Structure used to add the end parameters
105 */
106 TcgCreateStruct* createStruct
107 );
108
109 /**
110 *
111 * Adds end method call (ENDDATA) to the data structure in addition to the method status list
112 */
113 TcgResult TCG_CALL tcgEndMethodCall(
114 /**
115 * [in/out] Structure used to add the method call
116 */
117 TcgCreateStruct* createStruct
118 );
119
120
121
122 /**
123 *
124 * Adds Start Session call to the data structure. This creates the entire ComPacket structure and
125 * returns the size of the entire compacket in the size parameter.
126 */
127 TcgResult TCG_CALL tcgCreateStartSession(
128 /**
129 * [in/out] Structure used to add the start session call
130 */
131 TcgCreateStruct* createStruct,
132
133 /**
134 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
135 */
136 UINT32* size,
137
138 /**
139 * [in] ComID for the ComPacket
140 */
141 UINT16 comId,
142
143 /**
144 * [in] Extended ComID for the ComPacket
145 */
146 UINT16 comIdExtension,
147
148 /**
149 * [in] Host Session ID
150 */
151 UINT32 hostSessionId,
152
153 /**
154 * [in] Security Provider to start session with
155 */
156 TcgUid spId,
157
158 /**
159 * [in] Write option for start session. TRUE = start session requests write access
160 */
161 BOOLEAN write,
162
163 /**
164 * [in] Length of the host challenge. Length should be 0 if hostChallenge is NULL
165 */
166 UINT32 hostChallengeLength,
167
168 /**
169 * [in] Host challenge for Host Signing Authority. If NULL, then no Host Challenge shall be sent.
170 */
171 const void* hostChallenge,
172
173 /**
174 * [in] Host Signing Authority used for start session. If NULL, then no Host Signing Authority shall be sent.
175 */
176 TcgUid HostSigningAuthority
177 );
178
179 /**
180 *
181 * Creates ComPacket with a Method call that sets the PIN column for the row specified.
182 * This assumes a start session has already been opened with the desired SP.
183 */
184 TcgResult TCG_CALL tcgCreateSetCPin(
185
186 /**
187 * [in/out] Structure used to add method call
188 */
189 TcgCreateStruct* createStruct,
190
191 /**
192 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
193 */
194 UINT32* size,
195
196 /**
197 * [in] ComID for the ComPacket
198 */
199 UINT16 comId,
200
201 /**
202 * [in] Extended ComID for the ComPacket
203 */
204 UINT16 comIdExtension,
205
206 /**
207 * [in] Tper Session ID for the Packet
208 */
209 UINT32 tperSession,
210
211 /**
212 * [in] Host Session ID for the Packet
213 */
214 UINT32 hostSession,
215
216 /**
217 * [in] UID of row of current SP to set PIN column
218 */
219 TcgUid sidRow,
220
221 /**
222 * [in] value of PIN to set
223 */
224 const void* password,
225
226 /**
227 * [in] Size of PIN
228 */
229 UINT32 passwordSize
230 );
231
232 /**
233 *
234 * Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the value specified.
235 * This assumes a start session has already been opened with the desired SP.
236 */
237 TcgResult TCG_CALL tcgSetAuthorityEnabled(
238
239 /**
240 * [in/out] Structure used to add method call
241 */
242 TcgCreateStruct* createStruct,
243
244 /**
245 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
246 */
247 UINT32* size,
248
249 /**
250 * [in] ComID for the ComPacket
251 */
252 UINT16 comId,
253
254 /**
255 * [in] Extended ComID for the ComPacket
256 */
257 UINT16 comIdExtension,
258
259 /**
260 * [in] Tper Session ID for the Packet
261 */
262 UINT32 tperSession,
263
264 /**
265 * [in] Host Session ID for the Packet
266 */
267 UINT32 hostSession,
268
269 /**
270 * [in] Authority UID to modify the "Enabled" column for
271 */
272 TcgUid authorityUid,
273
274 /**
275 * [in] Value to set the "Enabled" column to
276 */
277 BOOLEAN enabled
278 );
279
280 /**
281 *
282 * Creates ComPacket with EndSession.
283 * This assumes a start session has already been opened.
284 */
285 TcgResult TCG_CALL tcgCreateEndSession(
286 /**
287 * [in/out] Structure used to add Endsession
288 */
289 TcgCreateStruct* createStruct,
290
291 /**
292 * [in/out] Describes the size of the entire ComPacket (header and payload). Filled out by function.
293 */
294 UINT32* size,
295
296 /**
297 * [in] ComID for the ComPacket
298 */
299 UINT16 comId,
300
301 /**
302 * [in] Extended ComID for the ComPacket
303 */
304 UINT16 comIdExtension,
305
306 /**
307 * [in] Host Session ID for the Packet
308 */
309 UINT32 hostSession,
310
311 /**
312 * [in] Tper Session ID for the Packet
313 */
314 UINT32 tpSessionId
315 );
316
317
318
319 /** @} */ // end of createCommon
320
321
322 /**
323 * @defgroup parseCommon Parse TCG ComPacket Utility Functions
324 *
325 * These functions decode a data stream consisting of TCG ComPackets, Packets, SubPackets, and tokens
326 * as defined in the TCG Storage Architecture Core Specification.
327 *
328 * @{
329 */
330
331 /**
332 *
333 * Retrieves human-readable token type name.
334 */
335 const char* TCG_CALL tcgTokenTypeString(
336 /**
337 * [in] Token type to retrieve
338 */
339 TcgTokenType type
340 );
341
342
343 /**
344 *
345 * Returns the method status of the current subpacket. Does not affect the current position
346 * in the ComPacket. In other words, it can be called whenever you have a valid SubPacket.
347 */
348 TcgResult TCG_CALL tcgGetMethodStatus(
349 /**
350 * [in/out] Structure used to parse received TCG response
351 */
352 const TcgParseStruct* parseStruct,
353
354 /**
355 * [in/out] Method status retrieved of the current SubPacket
356 */
357 UINT8* methodStatus
358 );
359
360
361 /**
362 * Returns a human-readable string representing a method status return code.
363 */
364 const char* TCG_CALL tcgMethodStatusString(
365 /**
366 * [in] Method status to translate to a string
367 */
368 UINT8 methodStatus
369 );
370
371
372 /**
373 * Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
374 * It is intended to be used to confirm the received Tcg response is intended for user that received it.
375 */
376 TcgResult TCG_CALL tcgGetComIds(
377 /**
378 * [in] Structure used to parse received TCG response
379 */
380 const TcgParseStruct* parseStruct,
381
382 /**
383 * [in/out] comID retrieved from received ComPacket
384 */
385 UINT16* comId,
386
387 /**
388 * [in/out] Extended comID retrieved from received ComPacket
389 */
390 UINT16* comIdExtension
391 );
392
393
394 /**
395 * Checks if the ComIDs of the response match the expected values.
396 */
397 TcgResult TCG_CALL tcgCheckComIds(
398 /**
399 * [in] Structure used to parse received TCG response
400 */
401 const TcgParseStruct* parseStruct,
402
403 /**
404 * [in] Expected comID
405 */
406 UINT16 expectedComId,
407
408 /**
409 * [in] Expected extended comID
410 */
411 UINT16 expectedComIdExtension
412 );
413
414 /**
415 * Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID. If the Sync Session response
416 * parameters do not match the comID, extended ComID and host session ID then a failure is returned.
417 */
418 TcgResult TCG_CALL tcgParseSyncSession(
419 /**
420 * [in/out] Structure used to parse received TCG response, contains Sync Session response.
421 */
422 const TcgParseStruct* parseStruct,
423
424 /**
425 * [in] Expected ComID that is compared to actual ComID of response
426 */
427 UINT16 comId,
428
429 /**
430 * [in] Expected Extended ComID that is compared to actual Extended ComID of response
431 */
432 UINT16 comIdExtension,
433
434 /**
435 * [in] Expected Host Session ID that is compared to actual Host Session ID of response
436 */
437 UINT32 hostSessionId,
438
439 /**
440 * [in/out] Tper Session ID retrieved from the Sync Session response.
441 */
442 UINT32* tperSessionId
443 );
444
445
446 TcgResult TCG_CALL tcgCreateSetAce(
447 TcgCreateStruct* createStruct,
448 UINT32* size,
449 UINT16 comId,
450 UINT16 comIdExtension,
451 UINT32 tperSession,
452 UINT32 hostSession,
453 TcgUid aceRow,
454 TcgUid authority1,
455 BOOLEAN logicalOperator,
456 TcgUid authority2
457 );
458
459
460 typedef BOOLEAN(TCG_CALL* TcgLevel0EnumCallback)(
461 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
462 TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER* feature,
463 UINTN featureSize, // includes header
464 void* context
465 );
466
467 BOOLEAN TCG_CALL tcgEnumLevel0Discovery(
468 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
469 TcgLevel0EnumCallback callback,
470 void* context
471 );
472
473 const TCG_LEVEL0_FEATURE_DESCRIPTOR_HEADER* TCG_CALL tcgGetFeature(
474 const TCG_LEVEL0_DISCOVERY_HEADER* discoveryHeader,
475 UINT16 featureCode,
476 UINTN* featureSize
477 );
478
479 /**
480 *
481 * Determines if the protocol provided is part of the provided supported protocol list.
482 *
483 * @return TRUE = protocol is supported, FALSE = protocol is not supported
484 */
485 BOOLEAN TCG_CALL tcgIsProtocolSupported(
486 /**
487 * [in] Supported protocol list to investigate
488 */
489 const TCG_SUPPORTED_SECURITY_PROTOCOLS* protocolList,
490
491 /**
492 * [in] Protocol value to determine if supported
493 */
494 UINT16 protocol
495 );
496
497 /**
498 *
499 * Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response
500 *
501 * @return TRUE = Locked is set, FALSE = Locked is false
502 */
503 BOOLEAN TCG_CALL tcgIsLocked(
504
505 /**
506 * [in] Level 0 discovery response
507 */
508 const TCG_LEVEL0_DISCOVERY_HEADER* discovery
509 );
510
511 /** @} */ // end of parseCommon functions
512
513 #pragma pack(pop)
514
515 #ifdef _MSC_VER
516 #pragma warning(pop) // C4200 zero-sized array
517 #endif
518
519 #ifdef __cplusplus
520 }
521 #endif
522
523 #endif // _TCG_UTIL_H_
tcgParseSyncSession
TcgResult TCG_CALL tcgParseSyncSession(const TcgParseStruct *parseStruct, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, UINT32 *tperSessionId)
Parses the Sync Session response contained in the parseStruct to retrieve Tper session ID.
tcgGetComIds
TcgResult TCG_CALL tcgGetComIds(const TcgParseStruct *parseStruct, UINT16 *comId, UINT16 *comIdExtension)
Retrieves the comID and Extended comID of the ComPacket in the Tcg response.
tcgTokenTypeString
const char *TCG_CALL tcgTokenTypeString(TcgTokenType type)
Retrieves human-readable token type name.
tcgStartMethodCall
TcgResult TCG_CALL tcgStartMethodCall(TcgCreateStruct *createStruct, TcgUid invokingId, TcgUid methodId)
Adds start Method Call to the data structure using invoking id and method Id provided.
TcgResult
TcgResult
Tcg result codes.
Definition: TcgCore.h:68
tcgSetAuthorityEnabled
TcgResult TCG_CALL tcgSetAuthorityEnabled(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid authorityUid, BOOLEAN enabled)
Creates ComPacket with a Method call that sets the "Enabled" column for the row specified using the v...
tcgCheckComIds
TcgResult TCG_CALL tcgCheckComIds(const TcgParseStruct *parseStruct, UINT16 expectedComId, UINT16 expectedComIdExtension)
Checks if the ComIDs of the response match the expected values.
tcgMethodStatusString
const char *TCG_CALL tcgMethodStatusString(UINT8 methodStatus)
Returns a human-readable string representing a method status return code.
tcgIsLocked
BOOLEAN TCG_CALL tcgIsLocked(const TCG_LEVEL0_DISCOVERY_HEADER *discovery)
Determines if the Locking Feature "Locked" bit is set in the level 0 discovery response.
tcgIsProtocolSupported
BOOLEAN TCG_CALL tcgIsProtocolSupported(const TCG_SUPPORTED_SECURITY_PROTOCOLS *protocolList, UINT16 protocol)
Determines if the protocol provided is part of the provided supported protocol list.
tcgGetMethodStatus
TcgResult TCG_CALL tcgGetMethodStatus(const TcgParseStruct *parseStruct, UINT8 *methodStatus)
Returns the method status of the current subpacket.
TcgUid
UINT64 TcgUid
UID in host native byte order.
Definition: Tcg.h:57
tcgEndParameters
TcgResult TCG_CALL tcgEndParameters(TcgCreateStruct *createStruct)
Adds end parameters (ENDLIST) to the data structure.
_TcgCreateStruct
Structure that is used to build the Tcg ComPacket.
Definition: TcgCore.h:135
tcgCreateSetCPin
TcgResult TCG_CALL tcgCreateSetCPin(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 tperSession, UINT32 hostSession, TcgUid sidRow, const void *password, UINT32 passwordSize)
Creates ComPacket with a Method call that sets the PIN column for the row specified.
tcgCreateStartSession
TcgResult TCG_CALL tcgCreateStartSession(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSessionId, TcgUid spId, BOOLEAN write, UINT32 hostChallengeLength, const void *hostChallenge, TcgUid HostSigningAuthority)
Adds Start Session call to the data structure.
tcgEndMethodCall
TcgResult TCG_CALL tcgEndMethodCall(TcgCreateStruct *createStruct)
Adds end method call (ENDDATA) to the data structure in addition to the method status list.
_TcgParseStruct
Structure that is used to parse the Tcg response received.
Definition: TcgCore.h:671
tcgStartParameters
TcgResult TCG_CALL tcgStartParameters(TcgCreateStruct *createStruct)
Adds start parameters (STARTLIST) to the data structure.
tcgCreateEndSession
TcgResult TCG_CALL tcgCreateEndSession(TcgCreateStruct *createStruct, UINT32 *size, UINT16 comId, UINT16 comIdExtension, UINT32 hostSession, UINT32 tpSessionId)
Creates ComPacket with EndSession.
TcgCore.h
Public API for the Tcg Core library to perform the lowest level TCG data encoding.


AlderLake Platform Sample Code: TcoWdtHob.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
TcoWdtHob.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TcoWdtHob.h.


AlderLake Platform Sample Code: TcoWdtHob.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
TcoWdtHob.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2016 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef __TCO_WDT_HOB_H__
35 #define __TCO_WDT_HOB_H__
36
37 #define TCO_WDT_HOB_GUID \
38 { \
39 0x3e405418, 0xd8c, 0x4f1a, { 0xb0, 0x55, 0xbe, 0xf9, 0x8, 0x41, 0x46, 0x8d } \
40 }
41
42 #ifndef _PEI_HOB_H_
43 #ifndef __HOB__H__
44 #ifndef __PI_HOB_H__
45 typedef struct _EFI_HOB_GENERIC_HEADER {
46 UINT16 HobType;
47 UINT16 HobLength;
48 UINT32 Reserved;
49 } EFI_HOB_GENERIC_HEADER;
50
51 typedef struct _EFI_HOB_GUID_TYPE {
52 EFI_HOB_GENERIC_HEADER Header;
53 EFI_GUID Name;
54 //
55 // Guid specific data goes here
56 //
57 } EFI_HOB_GUID_TYPE;
58 #endif
59 #endif
60 #endif
61
62 typedef struct {
63 EFI_HOB_GUID_TYPE Header;
64 UINT8 TcoRebootHappened;
65 } TCO_WDT_HOB;
66
67 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: TPSxFwUpdateWrapperProtocol.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
TPSxFwUpdateWrapperProtocol.h File Reference

Protocol definitions for TPSxFwUpdateWrapper. More...

Go to the source code of this file.

Detailed Description

Protocol definitions for TPSxFwUpdateWrapper.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TPSxFwUpdateWrapperProtocol.h.


AlderLake Platform Sample Code: TPSxFwUpdateWrapperProtocol.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
TPSxFwUpdateWrapperProtocol.h
Go to the documentation of this file.
1 /** @file
2 Protocol definitions for TPSxFwUpdateWrapper
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef __TPSX_FW_UPDATE_WRAPPER_PROTOCOL_H___
35 #define __TPSX_FW_UPDATE_WRAPPER_PROTOCOL_H___
36
37 extern EFI_GUID gTPSxFwUpdateWrapperProtocolGuid;
38
39 //
40 // Used to indicate PD Firmware device
41 //
42 #define PD_FW_DEVICE_0 0
43 #define PD_FW_DEVICE_1 1
44
45 //
46 // FW Version Format
47 //
48 typedef struct {
49 UINT32 RomMajor0 : 8;
50 UINT32 RomMajor1 : 8;
51 UINT32 RomMinor : 8;
52 UINT32 Patch : 8;
53 } PD_FW_VERSION;
54
55 typedef
56 UINT16
57 (EFIAPI *TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_DEVSILICONID_FROM_IMAGE) (
58 IN UINT8 *FwImage,
59 IN UINTN ImageSize
60 );
61
62 typedef
63 UINT16
64 (EFIAPI *TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_DEVSILICONID_FROM_DEV) (
65 VOID
66 );
67
68 typedef
69 EFI_STATUS
70 (EFIAPI *TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_PDFWVERSION_FROM_DEV) (
71 IN UINT8 PdIndex,
72 IN OUT UINT8 *FwVersion
73 );
74
75 typedef
76 EFI_STATUS
77 (EFIAPI *TPSX_FW_UPDATE_WRAPPER_PROTOCOL_PERFORM_PDFWUPDATE) (
78 IN UINT8 PdIndex,
79 IN CONST VOID *FwImage,
80 IN UINTN ImageSize
81 );
82
83 typedef struct _TPSX_FW_UPDATE_WRAPPER_PROTOCOL {
84 TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_DEVSILICONID_FROM_IMAGE GetDevSiliconIdFromImage;
85 TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_DEVSILICONID_FROM_DEV GetDevSiliconIdFromDev;
86 TPSX_FW_UPDATE_WRAPPER_PROTOCOL_GET_PDFWVERSION_FROM_DEV GetPDFwVersionFromDev;
87 TPSX_FW_UPDATE_WRAPPER_PROTOCOL_PERFORM_PDFWUPDATE PerformPDFwUpdate;
88 } TPSX_FW_UPDATE_WRAPPER_PROTOCOL;
89
90 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: TrustedDeviceSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Macros | Functions
TrustedDeviceSetup.h File Reference

Intel Trusted Device Setup library services. More...

#include <Uefi.h>
Include dependency graph for TrustedDeviceSetup.h:

Go to the source code of this file.

Macros

#define | TRUSTED_DEVICE_SETUP_BOOT_ENABLE BIT6
0100 0000 - bit 6
#define | TRUSTED_DEVICE_SETUP_BOOT_LOCK BIT7
1000 0000 - bit 7

Functions

EFI_STATUS | TrustedDeviceSetupMain (IN UINT32 ExtensionFvBase, IN UINT32 ExtensionFvSize, IN UINT8 SpecialCommandParamHighByte, IN UINT8 TrustedDeviceSetupParam)
The Intel Trusted Device Setup main function. More...
BOOLEAN | IsTrustedDeviceSetupBoot (IN UINT8 SpecialCmdParamHighByte)
Function to check whether or not this is a Intel Trusted Device Setup boot. More...
BOOLEAN | IsTrustedDeviceSetupBootLock (IN UINT8 SpecialCmdParamHighByte)
Function to check if Intel Trusted Device Setup BootLock enabled. More...
VOID | UpdateSmbiosTrustedDeviceSetupCapabilities (IN OUT VOID *RecordData)
Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities. More...
BOOLEAN | TrustedDeviceSetupChassisIntrusionEnabled (VOID)
This function determines if chassis intrusion detection is enabled. More...
BOOLEAN | TrustedDeviceSetupChassisIntrusionDetected (VOID)
This function checks the status of the chassis intrusion detection pin. More...
EFI_STATUS | InstallTrustedDeviceSetupExtensionProtocol (VOID)
Installs the protocol provided for the PBA to determine chassis intrusion capability and status. More...
EFI_STATUS | SuppressUserInput (VOID)
Suppress user input by removing ConIn In order for this ConIn removal to correctly remove input, no ConIn variable shall be added after this function runs. More...
EFI_STATUS | TrustedDeviceSetupAddKeyboard (VOID)
Add Keyboard Function. More...
EFI_STATUS | TrustedDeviceSetupRemoveKeyboard (VOID)
Remove Keyboard Function. More...
EFI_STATUS | TrustedDeviceSetupSetDisplayResolution (VOID)
Set Display Resolution. More...
EFI_STATUS | SkipBootToFwUI (VOID)
This function skips booting to FW UI when EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit\ is set in OSIndication. More...
EFI_STATUS | ClearBootNext (VOID)
This function Clears the BootNext variable. More...

Detailed Description

Intel Trusted Device Setup library services.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TrustedDeviceSetup.h.

Function Documentation

◆ ClearBootNext()

EFI_STATUS ClearBootNext ( VOID )

This function Clears the BootNext variable.

Return values
EFI_SUCCESS | Cleared the BootNext Variable
Others | Unable to clear BootNext Variable

◆ InstallTrustedDeviceSetupExtensionProtocol()

EFI_STATUS InstallTrustedDeviceSetupExtensionProtocol ( VOID )

Installs the protocol provided for the PBA to determine chassis intrusion capability and status.

Return values
EFI_SUCCESS | The protocol has been successfully installed
Others | An error has occurred and the protocol was not published

◆ IsTrustedDeviceSetupBoot()

BOOLEAN IsTrustedDeviceSetupBoot ( IN UINT8 SpecialCmdParamHighByte )

Function to check whether or not this is a Intel Trusted Device Setup boot.

Parameters
[in] SpecialCmdParamHighByte BIT0 - Chassis Intrusion Status.
Return values
TRUE | This is a Trusted Device Setup Boot
FALSE | This is NOT a Trusted Device Setup Boot

◆ IsTrustedDeviceSetupBootLock()

BOOLEAN IsTrustedDeviceSetupBootLock ( IN UINT8 SpecialCmdParamHighByte )

Function to check if Intel Trusted Device Setup BootLock enabled.

Parameters
[in] SpecialCmdParamHighByte BIT1 - Boot_Lock.
Return values
TRUE | This is a Trusted Device Setup Boot
FALSE | This is NOT a Trusted Device Setup Boot

◆ SkipBootToFwUI()

EFI_STATUS SkipBootToFwUI ( VOID )

This function skips booting to FW UI when EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit\ is set in OSIndication.

Return values
EFI_SUCCESS | Cleared the EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit
EFI_NOT_FOUND | Unable to clear EFI_OS_INDICATIONS_BOOT_TO_FW_UI

◆ SuppressUserInput()

EFI_STATUS SuppressUserInput ( VOID )

Suppress user input by removing ConIn In order for this ConIn removal to correctly remove input, no ConIn variable shall be added after this function runs.

Return values
EFI_SUCCESS | ConIn has been set to NULL
Other | Error setting ConIn to NULL

◆ TrustedDeviceSetupAddKeyboard()

EFI_STATUS TrustedDeviceSetupAddKeyboard ( VOID )

Add Keyboard Function.

Return values
EFI_SUCCESS | Keyboard functionality has successfully been added.
EFI_UNSUPPORTED | Keyboard functionality addition is not supported
Others | Adding keyboard functionality has failed

◆ TrustedDeviceSetupChassisIntrusionDetected()

BOOLEAN TrustedDeviceSetupChassisIntrusionDetected ( VOID )

This function checks the status of the chassis intrusion detection pin.

Return values
TRUE | Chassis intrusion has been detected
FALSE | Chassis intrusion has not been detected

◆ TrustedDeviceSetupChassisIntrusionEnabled()

BOOLEAN TrustedDeviceSetupChassisIntrusionEnabled ( VOID )

This function determines if chassis intrusion detection is enabled.

Return values
TRUE | Chassis intrusion detection is enabled
FALSE | Chassis intrusion detection is not enabled

◆ TrustedDeviceSetupMain()

EFI_STATUS TrustedDeviceSetupMain | ( | IN UINT32 | ExtensionFvBase,
 |  | IN UINT32 | ExtensionFvSize,
 |  | IN UINT8 | SpecialCommandParamHighByte,
 |  | IN UINT8 | TrustedDeviceSetupParam
 | ) |  |

The Intel Trusted Device Setup main function.

The function does the necessary work for the Trusted Device Setup feature. This function shall be called from the right before ExitPmAuth () to ensure no ConIn variables are set after this runs.

Parameters
[in] | ExtensionFvBase | Starting Address of the Firmware Volume accommodate the Extension.
[in] | ExtensionFvSize | Size of the Firmware Volume
[in] | SpecialCommandParamHighByte | Special Command Parameter High Byte of ASF API.
[in] | TrustedDeviceSetupParam | Trusted Device Setup Parameter.
Return values
EFI_SUCCESS | It is a Trusted Device Setup boot and all tasks have been successfully completed.
EFI_UNSUPPORTED | It is not a Trusted Device Setup boot
EFI_ABORTED | Trusted Device Setup failed

◆ TrustedDeviceSetupRemoveKeyboard()

EFI_STATUS TrustedDeviceSetupRemoveKeyboard ( VOID )

Remove Keyboard Function.

Return values
EFI_SUCCESS | Keyboard functionality has successfully been removed.
EFI_UNSUPPORTED | Keyboard functionality removal is not supported
Others | Removing keyboard functionality has failed

◆ TrustedDeviceSetupSetDisplayResolution()

EFI_STATUS TrustedDeviceSetupSetDisplayResolution ( VOID )

Set Display Resolution.

Return values
EFI_SUCCESS | Display has been successfully changed
Others | Display change failed

◆ UpdateSmbiosTrustedDeviceSetupCapabilities()

VOID UpdateSmbiosTrustedDeviceSetupCapabilities ( IN OUT VOID * RecordData )

Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities.

Function sets whether BIOS supports the enhanced measured boot feature, the Trusted Device Setup boot and setup lock feature, and chassis intrusion detection.

Parameters
[in,out] RecordData Structure of SMBIOS record to be updated wtih Trusted Device Setup capabilities.


AlderLake Platform Sample Code: TrustedDeviceSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
TrustedDeviceSetup.h
Go to the documentation of this file.
1 /** @file
2 Intel Trusted Device Setup library services.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _TRUSTED_DEVICE_SETUP_H_
37 #define _TRUSTED_DEVICE_SETUP_H_
38
39 #include <Uefi.h>
40
41 //
42 // These define the BIOS Intel Trusted Device Setup Capabilities for SMBIOS table 131
43 //
44 #define TRUSTED_DEVICE_SETUP_MEASURED_BOOT_CAPABLE 1
45 #define TRUSTED_DEVICE_SETUP_BOOT_SETUP_LOCK_CAPABLE 1
46 #define TRUSTED_DEVICE_SETUP_CHASSIS_INTRUSION_CAPABLE 1
47
48 #define TRUSTED_DEVICE_SETUP_BOOT_ENABLE BIT6 ///< 0100 0000 - bit 6
49 #define TRUSTED_DEVICE_SETUP_BOOT_LOCK BIT7 ///< 1000 0000 - bit 7
50
51 /**
52 The Intel Trusted Device Setup main function.
53
54 The function does the necessary work for the Trusted Device Setup feature.
55 This function shall be called from the right before ExitPmAuth () to ensure no ConIn variables
56 are set after this runs.
57
58 @param[in] ExtensionFvBase Starting Address of the Firmware Volume accommodate the Extension.
59 @param[in] ExtensionFvSize Size of the Firmware Volume
60 @param[in] SpecialCommandParamHighByte Special Command Parameter High Byte of ASF API.
61 @param[in] TrustedDeviceSetupParam Trusted Device Setup Parameter.
62
63 @retval EFI_SUCCESS It is a Trusted Device Setup boot and all tasks have been successfully completed.
64 @retval EFI_UNSUPPORTED It is not a Trusted Device Setup boot
65 @retval EFI_ABORTED Trusted Device Setup failed
66 **/
67 EFI_STATUS
68 EFIAPI
69 TrustedDeviceSetupMain (
70 IN UINT32 ExtensionFvBase,
71 IN UINT32 ExtensionFvSize,
72 IN UINT8 SpecialCommandParamHighByte,
73 IN UINT8 TrustedDeviceSetupParam
74 );
75
76 /**
77 Function to check whether or not this is a Intel Trusted Device Setup boot
78
79 @param[in] SpecialCmdParamHighByte BIT0 - Chassis Intrusion Status.
80
81 @retval TRUE This is a Trusted Device Setup Boot
82 @retval FALSE This is NOT a Trusted Device Setup Boot
83 **/
84 BOOLEAN
85 IsTrustedDeviceSetupBoot (
86 IN UINT8 SpecialCmdParamHighByte
87 );
88
89 /**
90 Function to check if Intel Trusted Device Setup BootLock enabled
91
92 @param[in] SpecialCmdParamHighByte BIT1 - Boot_Lock.
93
94 @retval TRUE This is a Trusted Device Setup Boot
95 @retval FALSE This is NOT a Trusted Device Setup Boot
96 **/
97 BOOLEAN
98 IsTrustedDeviceSetupBootLock (
99 IN UINT8 SpecialCmdParamHighByte
100 );
101
102 /**
103 Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities
104
105 Function sets whether BIOS supports the enhanced measured boot feature,
106 the Trusted Device Setup boot and setup lock feature, and chassis intrusion detection.
107
108 @param[in, out] RecordData Structure of SMBIOS record to be updated wtih Trusted Device Setup capabilities.
109 **/
110 VOID
111 EFIAPI
112 UpdateSmbiosTrustedDeviceSetupCapabilities (
113 IN OUT VOID *RecordData
114 );
115
116 /**
117 This function determines if chassis intrusion detection is enabled
118
119 @retval TRUE Chassis intrusion detection is enabled
120 @retval FALSE Chassis intrusion detection is not enabled
121 **/
122 BOOLEAN
123 EFIAPI
124 TrustedDeviceSetupChassisIntrusionEnabled (
125 VOID
126 );
127
128 /**
129 This function checks the status of the chassis intrusion detection pin
130
131 @retval TRUE Chassis intrusion has been detected
132 @retval FALSE Chassis intrusion has not been detected
133 **/
134 BOOLEAN
135 EFIAPI
136 TrustedDeviceSetupChassisIntrusionDetected (
137 VOID
138 );
139
140 /**
141 Installs the protocol provided for the PBA to determine chassis intrusion capability and status
142
143 @retval EFI_SUCCESS The protocol has been successfully installed
144 @retval Others An error has occurred and the protocol was not published
145 **/
146 EFI_STATUS
147 EFIAPI
148 InstallTrustedDeviceSetupExtensionProtocol (
149 VOID
150 );
151
152 /**
153 Suppress user input by removing ConIn
154 In order for this ConIn removal to correctly remove input, no ConIn variable shall be added after this function runs.
155
156 @retval EFI_SUCCESS ConIn has been set to NULL
157 @retval Other Error setting ConIn to NULL
158 **/
159 EFI_STATUS
160 EFIAPI
161 SuppressUserInput (
162 VOID
163 );
164
165 /**
166 Add Keyboard Function
167
168 @retval EFI_SUCCESS Keyboard functionality has successfully been added.
169 @retval EFI_UNSUPPORTED Keyboard functionality addition is not supported
170 @retval Others Adding keyboard functionality has failed
171 **/
172 EFI_STATUS
173 EFIAPI
174 TrustedDeviceSetupAddKeyboard (
175 VOID
176 );
177
178 /**
179 Remove Keyboard Function
180
181 @retval EFI_SUCCESS Keyboard functionality has successfully been removed.
182 @retval EFI_UNSUPPORTED Keyboard functionality removal is not supported
183 @retval Others Removing keyboard functionality has failed
184 **/
185 EFI_STATUS
186 EFIAPI
187 TrustedDeviceSetupRemoveKeyboard (
188 VOID
189 );
190
191 /**
192 Set Display Resolution
193
194 @retval EFI_SUCCESS Display has been successfully changed
195 @retval Others Display change failed
196 **/
197 EFI_STATUS
198 EFIAPI
199 TrustedDeviceSetupSetDisplayResolution(
200 VOID
201 );
202
203 /**
204 This function skips booting to FW UI when EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit\
205 is set in OSIndication
206
207 @retval EFI_SUCCESS Cleared the EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit
208 @retval EFI_NOT_FOUND Unable to clear EFI_OS_INDICATIONS_BOOT_TO_FW_UI
209 **/
210 EFI_STATUS
211 EFIAPI
212 SkipBootToFwUI (
213 VOID
214 );
215
216 /**
217 This function Clears the BootNext variable
218
219 @retval EFI_SUCCESS Cleared the BootNext Variable
220 @retval Others Unable to clear BootNext Variable
221 **/
222 EFI_STATUS
223 EFIAPI
224 ClearBootNext (
225 VOID
226 );
227
228 #endif
TrustedDeviceSetupChassisIntrusionEnabled
BOOLEAN TrustedDeviceSetupChassisIntrusionEnabled(VOID)
This function determines if chassis intrusion detection is enabled.
IsTrustedDeviceSetupBootLock
BOOLEAN IsTrustedDeviceSetupBootLock(IN UINT8 SpecialCmdParamHighByte)
Function to check if Intel Trusted Device Setup BootLock enabled.
TrustedDeviceSetupAddKeyboard
EFI_STATUS TrustedDeviceSetupAddKeyboard(VOID)
Add Keyboard Function.
SkipBootToFwUI
EFI_STATUS SkipBootToFwUI(VOID)
This function skips booting to FW UI when EFI_OS_INDICATIONS_BOOT_TO_FW_UI bit\ is set in OSIndicatio...
TrustedDeviceSetupSetDisplayResolution
EFI_STATUS TrustedDeviceSetupSetDisplayResolution(VOID)
Set Display Resolution.
UpdateSmbiosTrustedDeviceSetupCapabilities
VOID UpdateSmbiosTrustedDeviceSetupCapabilities(IN OUT VOID *RecordData)
Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities.
SuppressUserInput
EFI_STATUS SuppressUserInput(VOID)
Suppress user input by removing ConIn In order for this ConIn removal to correctly remove input,...
TrustedDeviceSetupMain
EFI_STATUS TrustedDeviceSetupMain(IN UINT32 ExtensionFvBase, IN UINT32 ExtensionFvSize, IN UINT8 SpecialCommandParamHighByte, IN UINT8 TrustedDeviceSetupParam)
The Intel Trusted Device Setup main function.
TrustedDeviceSetupChassisIntrusionDetected
BOOLEAN TrustedDeviceSetupChassisIntrusionDetected(VOID)
This function checks the status of the chassis intrusion detection pin.
IsTrustedDeviceSetupBoot
BOOLEAN IsTrustedDeviceSetupBoot(IN UINT8 SpecialCmdParamHighByte)
Function to check whether or not this is a Intel Trusted Device Setup boot.
InstallTrustedDeviceSetupExtensionProtocol
EFI_STATUS InstallTrustedDeviceSetupExtensionProtocol(VOID)
Installs the protocol provided for the PBA to determine chassis intrusion capability and status.
ClearBootNext
EFI_STATUS ClearBootNext(VOID)
This function Clears the BootNext variable.
TrustedDeviceSetupRemoveKeyboard
EFI_STATUS TrustedDeviceSetupRemoveKeyboard(VOID)
Remove Keyboard Function.


AlderLake Platform Sample Code: TrustedDeviceSetupMainProtocol.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Macros | Typedefs
TrustedDeviceSetupMainProtocol.h File Reference

APIs for Intel Trusted Device Setup Main Protocol. More...

Go to the source code of this file.

Macros

#define TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION 1
Intel Trusted Device Setup Protocol revision number. More...

Typedefs

typedef EFI_STATUS(* | TRUSTED_DEVICE_SETUP_ENTRY) (IN UINT32 ExtensionFvBase, IN UINT32 ExtensionFvSize, IN UINT8 SpecialCommandParamHighByte, IN UINT8 TrustedDeviceSetupParam)
The Intel Trusted Device Setup Main protocol function. More...
typedef VOID(* | SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES) (IN OUT VOID *RecordData)
Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities. More...

Detailed Description

APIs for Intel Trusted Device Setup Main Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TrustedDeviceSetupMainProtocol.h.

Macro Definition Documentation

◆ TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION

#define TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION 1

Intel Trusted Device Setup Protocol revision number.

Revision 1: Initial version

Definition at line 101 of file TrustedDeviceSetupMainProtocol.h.

Typedef Documentation

◆ SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES

typedef VOID( * SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES) (IN OUT VOID *RecordData)

Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities.

Function sets whether BIOS supports the enhanced measured boot feature, the Trusted Device Setup boot and setup lock feature, and chassis intrusion detection.

Parameters
SMBIOS_STRUCTURE Structure of SMBIOS record to be udpated wtih Trusted Device Setup capablities.

Definition at line 81 of file TrustedDeviceSetupMainProtocol.h.

◆ TRUSTED_DEVICE_SETUP_ENTRY

typedef EFI_STATUS( * TRUSTED_DEVICE_SETUP_ENTRY) (IN UINT32 ExtensionFvBase, IN UINT32 ExtensionFvSize, IN UINT8 SpecialCommandParamHighByte, IN UINT8 TrustedDeviceSetupParam)

The Intel Trusted Device Setup Main protocol function.

The function does the necessary work for the Trusted Device Setup feature. This function shall be called from the PlatformBootManagerBeforeConsole () right before ExitPmAuth (). Ensure no ConIn variables are set after this runs.

Parameters
[in] | ExtensionFvBase | Starting Address of the Firmware Volume accommodate the Extension.
[un] | ExtensionFvSize Size of the Firmware Volume
[in] | SpecialCommandParamHighByte | Special Command Parameter High Byte of ASF API
[in] | TrustedDeviceSetupParam | Trusted Device Setup Parameter.
Return values
EFI_SUCCESS | It is a Trusted Device Setup boot and all tasks have been successfully completed.
EFI_UNSUPPORTED | It is not a Trusted Device Setup boot
EFI_ABORTED | Trusted Device Setup failed

Definition at line 64 of file TrustedDeviceSetupMainProtocol.h.


AlderLake Platform Sample Code: TrustedDeviceSetupMainProtocol.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
TrustedDeviceSetupMainProtocol.h
Go to the documentation of this file.
1 /** @file
2 APIs for Intel Trusted Device Setup Main Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _TRUSTED_DEVICE_SETUP_MAIN_PROTOCOL_H_
35 #define _TRUSTED_DEVICE_SETUP_MAIN_PROTOCOL_H_
36
37 //
38 // Extern the GUID for protocol users.
39 //
40 extern EFI_GUID gTrustedDeviceSetupMainProtocolGuid;
41
42 //
43 // Forward reference for ANSI C compatibility
44 //
45 typedef struct _TRUSTED_DEVICE_SETUP_MAIN_PROTOCOL TRUSTED_DEVICE_SETUP_MAIN_PROTOCOL;
46
47 /**
48 The Intel Trusted Device Setup Main protocol function.
49
50 The function does the necessary work for the Trusted Device Setup feature.
51 This function shall be called from the PlatformBootManagerBeforeConsole () right before ExitPmAuth ().
52 Ensure no ConIn variables are set after this runs.
53
54 @param[in] ExtensionFvBase Starting Address of the Firmware Volume accommodate the Extension.
55 @param[un] ExtensionFvSize Size of the Firmware Volume
56 @param[in] SpecialCommandParamHighByte Special Command Parameter High Byte of ASF API
57 @param[in] TrustedDeviceSetupParam Trusted Device Setup Parameter.
58
59 @retval EFI_SUCCESS It is a Trusted Device Setup boot and all tasks have been successfully completed.
60 @retval EFI_UNSUPPORTED It is not a Trusted Device Setup boot
61 @retval EFI_ABORTED Trusted Device Setup failed
62 **/
63 typedef
64 EFI_STATUS
65 (EFIAPI *TRUSTED_DEVICE_SETUP_ENTRY) (
66 IN UINT32 ExtensionFvBase,
67 IN UINT32 ExtensionFvSize,
68 IN UINT8 SpecialCommandParamHighByte,
69 IN UINT8 TrustedDeviceSetupParam
70 );
71
72 /**
73 Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities
74
75 Function sets whether BIOS supports the enhanced measured boot feature,
76 the Trusted Device Setup boot and setup lock feature, and chassis intrusion detection.
77
78 @param SMBIOS_STRUCTURE Structure of SMBIOS record to be udpated wtih Trusted Device Setup capablities.
79 **/
80 typedef
81 VOID
82 (EFIAPI *SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES) (
83 IN OUT VOID *RecordData
84 );
85
86 typedef struct _TRUSTED_DEVICE_SETUP_PROTOCOL {
87 /**
88 This member specifies the revision of this structure. This field is used to
89 indicate backwards compatible changes to the protocol.
90 **/
91 UINT8 Revision;
92 TRUSTED_DEVICE_SETUP_ENTRY TrustedDeviceSetupEntry;
93 SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES SmbiosTrustedDeviceSetupCapabilities;
94 } TRUSTED_DEVICE_SETUP_PROTOCOL;
95
96 /**
97 Intel Trusted Device Setup Protocol revision number
98
99 Revision 1: Initial version
100 **/
101 #define TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION 1
102
103 #endif
SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES
VOID(* SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES)(IN OUT VOID *RecordData)
Update SMBIOS table 131 with Intel Trusted Device Setup BIOS capabilities.
Definition: TrustedDeviceSetupMainProtocol.h:82
TRUSTED_DEVICE_SETUP_ENTRY
EFI_STATUS(* TRUSTED_DEVICE_SETUP_ENTRY)(IN UINT32 ExtensionFvBase, IN UINT32 ExtensionFvSize, IN UINT8 SpecialCommandParamHighByte, IN UINT8 TrustedDeviceSetupParam)
The Intel Trusted Device Setup Main protocol function.
Definition: TrustedDeviceSetupMainProtocol.h:65


AlderLake Platform Sample Code: TxtOneTouch.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
TxtOneTouch.h File Reference

This file contains definitions required for One-Touch function. More...

Go to the source code of this file.

Detailed Description

This file contains definitions required for One-Touch function.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TxtOneTouch.h.


AlderLake Platform Sample Code: TxtOneTouch.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
TxtOneTouch.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required for One-Touch function.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _TXT_ONE_TOUCH_H_
36 #define _TXT_ONE_TOUCH_H_
37
38 //
39 // Operation
40 //
41 #define ENABLE_VT 128
42 #define DISABLE_VT_TXT 129
43 #define ENABLE_VTD 130
44 #define DISABLE_VTD_TXT 131
45 #define ENABLE_ACTTPM_VT_VTD_TXT_DISABLE_STM 132
46 #define ENABLE_ACTTPM_VT_VTD_TXT_STM 133
47 #define DISABLE_STM 134
48 #define DISABLE_TXT_STM 135
49 #define DISABLE_SENTER_VMX 136
50 #define ENABLE_VMX_SMX_ONLY 137
51 #define ENABLE_VMX_OUTSIDE_SMX 138
52 #define ENABLE_VMX 139
53 #define ENABLE_SENTER_ONLY 140
54 #define ENABLE_SENTER_VMX_IN_SMX 141
55 #define ENABLE_SENTER_VMX_OUTSIDE_SMX 142
56 #define ENABLE_SENTER_VMX 143
57 #define SET_NO_TXT_MAINTENANCE_FALSE 159
58 #define SET_NO_TXT_MAINTENANCE_TRUE 160
59
60 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: TxtOneTouchOp.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Typedefs
TxtOneTouchOp.h File Reference

Txt specific PPI operation definition. More...

Go to the source code of this file.

Typedefs

typedef EFI_STATUS(* TXT_RESET_SYSTEM) (IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)
Reset system. More...

Detailed Description

Txt specific PPI operation definition.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file TxtOneTouchOp.h.

Typedef Documentation

◆ TXT_RESET_SYSTEM

typedef EFI_STATUS( * TXT_RESET_SYSTEM) (IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)

Reset system.

Parameters
[in] | This | - Point of TXT_ONE_TOUCH_OP_PROTOCOL
[in] | Command | - Operation value for TxT
Return values
EFI_SUCCESS - Always return EFI_SUCCESS

Definition at line 82 of file TxtOneTouchOp.h.


AlderLake Platform Sample Code: TxtOneTouchOp.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
TxtOneTouchOp.h
Go to the documentation of this file.
1 /** @file
2 Txt specific PPI operation definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _TXT_PPI_OPERATION_H_
37 #define _TXT_PPI_OPERATION_H_
38
39 typedef struct _TXT_ONE_TOUCH_OP_PROTOCOL TXT_ONE_TOUCH_OP_PROTOCOL;
40
41 //
42 // Member functions
43 //
44 /*
45 Extend PPI operation for TxT.
46
47 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
48 @param[in] Command - Operation value for TxT
49
50 */
51 typedef
52 EFI_STATUS
53 (EFIAPI *TXT_PPI_EXEC_OPERATION)(
54 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
55 IN UINT8 Command
56 );
57
58 /*
59 Confirmation dialog for TxT PPI
60
61 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
62 @param[in] Command - Operation value for TxT
63 @param[in] Confirm - User confirm
64 */
65 typedef
66 EFI_STATUS
67 (EFIAPI *TXT_CONFIRMATION_DIALOG)(
68 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
69 IN UINT8 Command,
70 IN OUT BOOLEAN *Confirm
71 );
72
73 /**
74 Reset system.
75
76 @param[in] This - Point of TXT_ONE_TOUCH_OP_PROTOCOL
77 @param[in] Command - Operation value for TxT
78
79 @retval EFI_SUCCESS - Always return EFI_SUCCESS
80 **/
81 typedef
82 EFI_STATUS
83 (EFIAPI *TXT_RESET_SYSTEM)(
84 IN TXT_ONE_TOUCH_OP_PROTOCOL *This,
85 IN UINT8 Command
86 );
87
88 struct _TXT_ONE_TOUCH_OP_PROTOCOL {
89 TXT_PPI_EXEC_OPERATION ExecuteOperation;
90 TXT_CONFIRMATION_DIALOG ConfirmationDialog;
91 TXT_RESET_SYSTEM ResetSystem;
92 };
93
94 #endif
TXT_RESET_SYSTEM
EFI_STATUS(* TXT_RESET_SYSTEM)(IN TXT_ONE_TOUCH_OP_PROTOCOL *This, IN UINT8 Command)
Reset system.
Definition: TxtOneTouchOp.h:83
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: UsbDeviceLib.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
UsbDeviceLib.h File Reference

Header file for USBFN library definition. More...

#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Protocol/UsbIo.h>
#include <Protocol/EfiUsbFnIo.h>
Include dependency graph for UsbDeviceLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Header file for USBFN library definition.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file UsbDeviceLib.h.


AlderLake Platform Sample Code: UsbDeviceLib.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
UsbDeviceLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for USBFN library definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #ifndef _EFI_XDCI_LIB_H_
35 #define _EFI_XDCI_LIB_H_
36
37 #include <Uefi.h>
38 #include <Library/DebugLib.h>
39 #include <Library/BaseMemoryLib.h>
40 #include <Library/MemoryAllocationLib.h>
41 #include <Library/UefiBootServicesTableLib.h>
42 #include <Protocol/UsbIo.h>
43 #include <Protocol/EfiUsbFnIo.h>
44
45 #define MAX_DESCRIPTOR_SIZE 64
46 #define STRING_ARR_SIZE (MAX_DESCRIPTOR_SIZE - 2)
47 #define USB_ADDRESS_TABLE_SIZE 16 //4
48
49 //
50 // Endpoint Zero
51 //
52 #define USB_EP0_MAX_PKT_SIZE_HS 0x40 // High Speed mode is explicitly set as 64 bytes
53 #define USB_EP0_MAX_PKT_SIZE_SS 0x9 // Must be 0x9 (2^9 = 512 Bytes) in SuperSpeed mode
54 #define USB_EPO_MAX_PKT_SIZE_ALL 512 // Overall max bytes for any type
55
56 //
57 // Bulk Endpoints
58 //
59 #define USB_BULK_EP_PKT_SIZE_HS 0x200 // Bulk-Endpoint HighSpeed
60 #define USB_BULK_EP_PKT_SIZE_SS 0x400 // Bulk-Endpoint SuperSpeed
61 #define USB_BULK_EP_PKT_SIZE_MAX USB_BULK_EP_PKT_SIZE_SS
62
63 //
64 // Transmit Direction Bits
65 //
66 #define USB_ENDPOINT_DIR_OUT 0x00
67
68 //
69 // Endpoint Companion Bulk Attributes
70 //
71 #define USB_EP_BULK_BM_ATTR_MASK 0x1F
72
73 //
74 // Configuration Modifiers (Attributes)
75 //
76 #define USB_BM_ATTR_RESERVED 0x80
77 #define USB_BM_ATTR_SELF_POWERED 0x40
78 #define USB_BM_ATTR_REMOTE_WAKE 0X20
79
80 //
81 // USB BCD version
82 //
83 #define USB_BCD_VERSION_LS 0x0110
84 #define USB_BCD_VERSION_HS 0x0200
85 #define USB_BCD_VERSION_SS 0x0300
86
87 //
88 // Device RequestType Flags
89 //
90 #define USB_RT_TX_DIR_H_TO_D (0x0) // Tx direction Host to Device
91 #define USB_RT_TX_DIR_D_TO_H (0x1 << 7) // Tx direction Device to Host
92 #define USB_RT_TX_DIR_MASK (0x80)
93
94 //
95 // USB request type
96 //
97 #define USB_REQ_TYPE_MASK (0x60)
98
99 //
100 // Usb control transfer target
101 //
102 #define USB_TARGET_MASK (0x1F)
103
104 //
105 // Device GetStatus bits
106 //
107 #define USB_STATUS_SELFPOWERED (0x01)
108 #define USB_STATUS_REMOTEWAKEUP (0x02)
109
110 //
111 // USB Device class identifiers
112 //
113 #define USB_DEVICE_MS_CLASS (0x08)
114 #define USB_DEVICE_VENDOR_CLASS (0xFF)
115
116 //
117 // USB Descriptor types
118 //
119 #define USB_DESC_TYPE_BOS 0x0F
120 #define USB_DESC_TYPE_DEVICE_CAPABILITY 0x10
121 #define USB_DESC_TYPE_SS_ENDPOINT_COMPANION 0x30
122
123 #ifdef SUPPORT_SUPER_SPEED
124 //
125 // USB device capability Type Codes
126 // USB3 Table 9-13
127 //
128 typedef enum {
129 WirelessUSB = 0x01,
130 USB2Extension,
131 SuperSpeedUSB,
132 ContainerID,
133 SuperSpeedPlusUSB = 0x0A
134 } USB_DEVICE_CAP_TYPE_CODE;
135 #endif
136
137
138 //
139 // USB device states from USB spec sec 9.1
140 //
141 typedef enum {
142 UsbDevStateOff = 0,
143 UsbDevStateInit,
144 UsbDevStateAttached,
145 UsbDevStatePowered,
146 UsbDevStateDefault,
147 UsbDevStateAddress,
148 UsbDevStateConfigured,
149 UsbDevStateSuspended,
150 UsbDevStateError
151 } USB_DEVICE_STATE;
152
153
154 //
155 // The following set of structs are used during USB data transaction
156 // operatitions, including requests and completion events.
157 //
158 #pragma pack(1)
159
160 typedef struct {
161 UINT32 EndpointNum;
162 UINT8 EndpointDir;
163 UINT8 EndpointType;
164 UINT32 Length;
165 VOID *Buffer;
166 } EFI_USB_DEVICE_XFER_INFO;
167
168 //
169 // SuperSpeed Endpoint companion descriptor
170 // USB3 table 9-22
171 //
172 typedef struct {
173 UINT8 Length;
174 UINT8 DescriptorType;
175 UINT8 MaxBurst;
176 UINT8 Attributes;
177 UINT16 BytesPerInterval;
178 } EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR;
179
180 typedef struct {
181 EFI_USB_ENDPOINT_DESCRIPTOR *EndpointDesc;
182 EFI_USB_ENDPOINT_COMPANION_DESCRIPTOR *EndpointCompDesc;
183 } USB_DEVICE_ENDPOINT_INFO, USB_DEVICE_ENDPOINT_OBJ;
184
185 typedef struct {
186 VOID *Buffer;
187 UINT32 Length;
188 } USB_DEVICE_IO_INFO;
189
190 typedef struct {
191 USB_DEVICE_IO_INFO IoInfo;
192 USB_DEVICE_ENDPOINT_INFO EndpointInfo;
193 } USB_DEVICE_IO_REQ;
194
195 //
196 // Optional string descriptor
197 //
198 typedef struct {
199 UINT8 Length;
200 UINT8 DescriptorType;
201 UINT16 LangID[STRING_ARR_SIZE];
202 } USB_STRING_DESCRIPTOR;
203
204
205 //
206 // The following structures abstract the device descriptors a class
207 // driver needs to provide to the USBD core.
208 // These structures are filled & owned by the class/function layer.
209 //
210 typedef struct {
211 EFI_USB_INTERFACE_DESCRIPTOR *InterfaceDesc;
212 USB_DEVICE_ENDPOINT_OBJ *EndpointObjs;
213 } USB_DEVICE_INTERFACE_OBJ;
214
215 typedef struct {
216 EFI_USB_CONFIG_DESCRIPTOR *ConfigDesc;
217 VOID *ConfigAll;
218 USB_DEVICE_INTERFACE_OBJ *InterfaceObjs;
219 } USB_DEVICE_CONFIG_OBJ;
220
221 #ifdef SUPPORT_SUPER_SPEED
222
223 //
224 // Generic Header of Device Capability descriptor
225 // USB3 9.6.2.2
226 //
227 typedef struct {
228 UINT8 Length;
229 UINT8 DescriptorType;
230 UINT8 DevCapabilityType;
231 UINT8 CapDependent;
232 } EFI_USB_SS_DEVICE_CAP_DESCRIPTOR;
233
234 //
235 // USB2.0 Extension descriptor
236 // USB3 Table 9-14
237 //
238 typedef struct {
239 UINT8 Length;
240 UINT8 DescriptorType;
241 UINT8 DeviceCapabilityType;
242 UINT32 Attributes;
243 } EFI_USB_USB2_EXT_CAP_DESCRIPTOR;
244
245
246 //
247 // SuperSpeed USB Device Capability descriptor
248 // USB3 Table 9-15
249 //
250 typedef struct {
251 UINT8 Length;
252 UINT8 DescriptorType;
253 UINT8 DeviceCapabilityType;
254 UINT8 Attributes;
255 UINT16 SpeedSupported;
256 UINT8 FunctionalitySupport;
257 UINT8 U1DevExitLat;
258 UINT16 U2DevExitLat;
259 } EFI_USB_SS_USB_DEV_CAP_DESCRIPTOR;
260
261 //
262 // Container ID descriptor
263 // USB3 Table 9-16
264 //
265 typedef struct {
266 UINT8 Length;
267 UINT8 DescriptorType;
268 UINT8 DeviceCapabilityType;
269 UINT8 Reserved;
270 UINT8 UUID[16];
271 } EFI_USB_CONTAINER_ID_DESCRIPTOR;
272
273 //
274 // Container ID descriptor
275 // USB3 Table 9-16
276 //
277 typedef struct {
278 UINT8 Length;
279 UINT8 DescriptorType;
280 UINT8 DeviceCapabilityType;
281 UINT8 ReservedByte;
282 UINT32 Attributes;
283 UINT16 FunctionalitySupport;
284 UINT16 ReservedWord;
285 UINT32 SublinkSpeedAttr[2];
286 } EFI_USB_SS_PLUS_USB_DEV_CAP_DESCRIPTOR;
287
288 #endif
289
290 typedef
291 EFI_STATUS
292 (EFIAPI *EFI_USB_CONFIG_CALLBACK) (
293 IN UINT8 CfgVal
294 );
295
296 typedef
297 EFI_STATUS
298 (EFIAPI *EFI_USB_SETUP_CALLBACK) (
299 IN EFI_USB_DEVICE_REQUEST *CtrlRequest,
300 IN USB_DEVICE_IO_INFO *IoInfo
301 );
302
303 typedef
304 EFI_STATUS
305 (EFIAPI *EFI_USB_DATA_CALLBACK) (
306 IN EFI_USB_DEVICE_XFER_INFO *XferInfo
307 );
308
309 typedef struct {
310 USB_DEVICE_DESCRIPTOR *DeviceDesc;
311 USB_DEVICE_CONFIG_OBJ *ConfigObjs;
312 USB_STRING_DESCRIPTOR *StringTable;
313 #ifdef SUPPORT_SUPER_SPEED
314 EFI_USB_BOS_DESCRIPTOR *BosDesc;
315 #endif
316 UINT8 StrTblEntries;
317 EFI_USB_CONFIG_CALLBACK ConfigCallback;
318 EFI_USB_SETUP_CALLBACK SetupCallback;
319 EFI_USB_DATA_CALLBACK DataCallback;
320 } USB_DEVICE_OBJ;
321
322
323 //
324 // Main USBD driver object structure containing all data necessary
325 // for USB device mode processing at this layer
326 //
327 typedef struct {
328 USB_DEVICE_OBJ *UsbdDevObj; /* pointer to a Device Object */
329 VOID *XdciDrvObj; /* Opaque handle to XDCI driver */
330 BOOLEAN XdciInitialized; /* flag to specify if the XDCI driver is initialized */
331 USB_DEVICE_CONFIG_OBJ *ActiveConfigObj; /* pointer to currently active configuraiton */
332 USB_DEVICE_STATE State; /* current state of the USB Device state machine */
333 UINT8 Address; /* configured device address */
334 } USB_DEVICE_DRIVER_OBJ;
335
336 #pragma pack()
337
338 #endif
EfiUsbFnIo.h
EFI USB function IO Protocol This protocol supports Usb Function IO API.


AlderLake Platform Sample Code: UsbDeviceModeProtocol.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Classes | Macros
UsbDeviceModeProtocol.h File Reference

Header file for definition of USBFN device mode protocol. More...

#include <Library/UsbDeviceLib.h>
Include dependency graph for UsbDeviceModeProtocol.h:

Go to the source code of this file.

Classes

struct _EFI_USB_DEVICE_MODE_PROTOCOL
Usb Device Mode Protocol Structure. More...

Macros

#define EFI_USB_DEVICE_MODE_PROTOCOL_GUID {0xC9923F7E, 0x1746, 0x4802, { 0x86, 0x2e, 0x1, 0x1c, 0x2c, 0x2d, 0x9d, 0x86 } }
UsbDeviceMode Protocol GUID.

Detailed Description

Header file for definition of USBFN device mode protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification

Definition in file UsbDeviceModeProtocol.h.


AlderLake Platform Sample Code: UsbDeviceModeProtocol.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
UsbDeviceModeProtocol.h
Go to the documentation of this file.
1 /**@file
2 Header file for definition of USBFN device mode protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification
33 **/
34 #ifndef _USB_DEVICE_MODE_PROTOCOL_H_
35 #define _USB_DEVICE_MODE_PROTOCOL_H_
36
37 #include <Library/UsbDeviceLib.h>
38
39 ///
40 /// UsbDeviceMode Protocol GUID.
41 ///
42 #define EFI_USB_DEVICE_MODE_PROTOCOL_GUID \
43 {0xC9923F7E, 0x1746, 0x4802, { 0x86, 0x2e, 0x1, 0x1c, 0x2c, 0x2d, 0x9d, 0x86 } }
44
45 typedef struct _EFI_USB_DEVICE_MODE_PROTOCOL EFI_USB_DEVICE_MODE_PROTOCOL;
46
47 typedef
48 EFI_STATUS
49 (EFIAPI *EFI_USB_DEVICE_MODE_INIT_XDCI) (
50 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
51 );
52
53 typedef
54 EFI_STATUS
55 (EFIAPI *EFI_USB_DEVICE_MODE_CONNECT) (
56 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
57 );
58
59 typedef
60 EFI_STATUS
61 (EFIAPI *EFI_USB_DEVICE_MODE_DISCONNECT) (
62 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
63 );
64
65 typedef
66 EFI_STATUS
67 (EFIAPI *EFI_USB_DEVICE_EP_TX_DATA) (
68 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
69 IN USB_DEVICE_IO_REQ *IoRequest
70 );
71
72 typedef
73 EFI_STATUS
74 (EFIAPI *EFI_USB_DEVICE_EP_RX_DATA) (
75 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
76 IN USB_DEVICE_IO_REQ *IoRequest
77 );
78
79 typedef
80 EFI_STATUS
81 (EFIAPI *EFI_USB_DEVICE_MODE_BIND) (
82 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
83 IN USB_DEVICE_OBJ *UsbdDevObj
84 );
85
86 typedef
87 EFI_STATUS
88 (EFIAPI *EFI_USB_DEVICE_MODE_UNBIND) (
89 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
90 );
91
92 typedef
93 EFI_STATUS
94 (EFIAPI *EFI_USB_DEVICE_MODE_STOP) (
95 IN EFI_USB_DEVICE_MODE_PROTOCOL *This
96 );
97
98 typedef
99 EFI_STATUS
100 (EFIAPI *EFI_USB_DEVICE_MODE_RUN) (
101 IN EFI_USB_DEVICE_MODE_PROTOCOL *This,
102 IN UINT32 TimeoutMs
103 );
104
105 ///
106 /// Usb Device Mode Protocol Structure.
107 ///
108 struct _EFI_USB_DEVICE_MODE_PROTOCOL {
109 EFI_USB_DEVICE_MODE_INIT_XDCI InitXdci;
110 EFI_USB_DEVICE_MODE_CONNECT Connect;
111 EFI_USB_DEVICE_MODE_DISCONNECT DisConnect;
112 EFI_USB_DEVICE_EP_TX_DATA EpTxData;
113 EFI_USB_DEVICE_EP_RX_DATA EpRxData;
114 EFI_USB_DEVICE_MODE_BIND Bind;
115 EFI_USB_DEVICE_MODE_UNBIND UnBind;
116 EFI_USB_DEVICE_MODE_RUN Run;
117 EFI_USB_DEVICE_MODE_STOP Stop;
118 };
119
120 #endif
_EFI_USB_DEVICE_MODE_PROTOCOL
Usb Device Mode Protocol Structure.
Definition: UsbDeviceModeProtocol.h:108
UsbDeviceLib.h
Header file for USBFN library definition.


AlderLake Platform Sample Code: VtdEnableDmaBufferPpi.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
VtdEnableDmaBufferPpi.h File Reference

The definition for the VTd Enable DMA Buffer PPI. More...

Go to the source code of this file.

Detailed Description

The definition for the VTd Enable DMA Buffer PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file VtdEnableDmaBufferPpi.h.


AlderLake Platform Sample Code: VtdEnableDmaBufferPpi.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
VtdEnableDmaBufferPpi.h
Go to the documentation of this file.
1 /** @file
2 The definition for the VTd Enable DMA Buffer PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 SPDX-License-Identifier: BSD-2-Clause-Patent
9
10 **/
11
12 #ifndef __VTD_ENABLE_DMA_BUFFER_PPI_H__
13 #define __VTD_ENABLE_DMA_BUFFER_PPI_H__
14
15 #define PLATFORM_VTD_ENABLE_DMA_BUFFER_PPI_GUID \
16 { \
17 0x2355a0a7, 0x4c52, 0x4b5b, { 0x96, 0xac 0xe5, 0x8e, 0x5e, 0xec, 0x79, 0xc8 } \
18 }
19
20 //
21 // Forward declaration for the VTd Enable DMA Buffer PPI.
22 //
23
24 /*
25 Enable DMA buffer in VTd
26
27 @param[in] VtdEngineIndex VTd engine index.
28
29 @retval EFI_SUCCESS Enable successfully.
30 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
31 @retval EFI_UNSUPPORTED VTd base is zero.
32 @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
33 */
34 typedef
35 EFI_STATUS
36 (EFIAPI *VTD_ENABLE_DMA_BUFFER) (
37 IN VTD_ENGINE_INDEX VtdEngineIndex
38 );
39
40 extern EFI_GUID gPlatformVTdEnableDmaBufferPpiGuid;
41
42 #endif
43


AlderLake Platform Sample Code: WdtAppVariable.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
WdtAppVariable.h File Reference

Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file WdtAppVariable.h.


AlderLake Platform Sample Code: WdtAppVariable.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
WdtAppVariable.h
Go to the documentation of this file.
1 /** @file
2 Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _WDT_APP_VARIABLE_H_
36 #define _WDT_APP_VARIABLE_H_
37
38 #define WDT_PERSISTENT_DATA_C_NAME L"WdtPersistentData"
39
40 typedef struct _WDT_PERSISTENT_DATA {
41 UINT8 Enable;
42 } WDT_PERSISTENT_DATA;
43
44 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: WheaSetup.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
WheaSetup.h File Reference

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file WheaSetup.h.


AlderLake Platform Sample Code: WheaSetup.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
WheaSetup.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2021 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26
27 This file contains a 'Sample Driver' and is licensed as such under the terms
28 of your license agreement with Intel or your vendor. This file may be modified
29 by the user, subject to the additional terms of the license agreement.
30
31 @par Specification Reference:
32 **/
33
34 #ifndef _WHEA_SETUP_H_
35 #define _WHEA_SETUP_H_
36
37 #ifdef WHEA_SUPPORT_FLAG
38
39 #pragma pack(1)
40 #define WHEA_SETUP_KEY 4105
41 #define WHEA_SETUP_VARSTORE\
42 varstore WHEA_SETUP, \
43 varid = WHEA_SETUP_KEY, \
44 name = WheaSetup, \
45 guid = SETUP_GUID;
46
47 /**
48 Making any setup structure change after code frozen
49 will need to maintain backward compatibility, bump up
50 structure revision and update below history table\n
51 <b>Revision 1</b>: - Initial version.
52 **/
53 #define WHEA_SETUP_REVISION 1
54
55 typedef struct{
56 UINT8 WheaSupport;
57 UINT8 LogErrors;
58 UINT8 ErrorGeneration;
59 UINT8 ProcessorErrors; // function not available
60 UINT8 SaErrors;
61 UINT8 PchErrors;
62 UINT8 PcieErrors;
63 UINT8 PlatformErrors;
64 UINT8 PropagateSerr;
65 UINT8 PropagatePerr;
66 UINT8 FatErr;
67 UINT8 UnCorRecErr;
68 UINT8 CorErr;
69 } WHEA_SETUP;
70
71 #pragma pack()
72 #endif // WHEA_SUPPORT_FLAG
73 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: WifiConnectionManagerConfigHii.h File Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
WifiConnectionManagerConfigHii.h File Reference

GUIDs used as HII FormSet and HII Package list GUID in WiFi Connection Manager. More...

Go to the source code of this file.

Detailed Description

GUIDs used as HII FormSet and HII Package list GUID in WiFi Connection Manager.

Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Definition in file WifiConnectionManagerConfigHii.h.


AlderLake Platform Sample Code: WifiConnectionManagerConfigHii.h Source File

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
WifiConnectionManagerConfigHii.h
Go to the documentation of this file.
1 /** @file
2 GUIDs used as HII FormSet and HII Package list GUID in WiFi Connection Manager.
3
4 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
6
7 **/
8
9 #ifndef __WIFI_CONNECTION_MANAGER_HII_GUID_H__
10 #define __WIFI_CONNECTION_MANAGER_HII_GUID_H__
11
12 #define WIFI_CONNECTION_MANAGER_CONFIG_GUID \
13 { \
14 0x9f94d327, 0x0b18, 0x4245, { 0x8f, 0xf2, 0x83, 0x2e, 0x30, 0xd, 0x2c, 0xef } \
15 }
16
17
18 #endif
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- a -

  • AcpiGnvsInit() : DxeAcpiGnvsInitLib.h
  • ALIGNMENT : MultiPlatSupport.h
  • AllocateMemoryBelow4G() : PlatformInitAdvancedDxe.c
  • AmtPolicyInitDxe() : AmtPolicyInitDxe.c , AmtPolicyInitDxe.h
  • ArmEcWdtWithTimeOut() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- b -

  • BCDToDec() : PlatformInitAdvancedSmm.c
  • BiosEcWdtReadCommand() : EcMiscLib.h
  • BiosEcWdtWriteCommand() : EcMiscLib.h
  • BOARD_INIT_PREMEM_ENTRY : PlatformPostCode.h
  • BootGuardOemRevocationHook() : BootGuardRevocationLib.h
  • BuildDebugConfigDataHob() : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- c -

  • CheckSataRaidMode() : BasePlatformVariableLib.h
  • ClearBootNext() : TrustedDeviceSetup.h
  • ClearDiagnosticStatus() : PlatformNvRamHookLib.h
  • ClearTenSecPwrButtonMode() : EcMiscLib.h
  • ConfigureGpio() : PlatformInitAdvancedPostMem.c , PlatformInitAdvancedPreMem.c
  • ConfigurePciHostBridgePcds() : PlatformInitAdvancedPostMem.c
  • CPU_SETUP_REVISION : SetupVariable.h
  • CPU_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h
  • CpuCrashLogCollectDataFromTelemetrySRAM() : PlatformInitAdvancedPostMem.c
  • CpuDxePrintPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuInstallPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuPolicyInitDxe() : CpuPolicyInitDxe.c , CpuPolicyInitDxe.h
  • CrashLogCollectDataFromPmcSSRAM() : PlatformInitAdvancedPostMem.c
  • CreateAttemptUsbFirstHotkeyInfoHob() : PlatformInitAdvancedPostMem.c
  • CreateBootguardEventLogEntries() : PeiBootGuardEventLogLib.h
  • CreateDefaultVariableHob() : MultiPlatSupportLib.h
  • CreateFastBootHob() : PlatformInitAdvancedPreMem.c
  • CvfGpioInit() : PlatformInitAdvancedPostMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- d -

  • DEBUG_CONFIG_DATA_REVISION : Setup.h
  • DEBUG_EVENT_HABDLER_PPI : DebugEventHandler.h
  • DEBUG_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h
  • DecToBCD() : PlatformInitAdvancedSmm.c
  • DEFAULT_BIOSVENDOR_CHARS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM : SmbiosPlatformInfoDefault.h
  • DetectEc() : EcLib.h
  • DetectEcRevision() : EcMiscLib.h
  • DetectEcSupport() : EcMiscLib.h
  • DetectPmicVendorID() : EcMiscLib.h
  • DevicePathToStr() : DxePlatformBootManagerLib.h
  • DfctFastChargingMode() : EcMiscLib.h
  • DisableAcpiCallback() : PlatformInitAdvancedSmm.h , PlatformInitAdvancedSmm.c
  • DisableEcSmiMode() : EcMiscLib.h
  • DisablePchDtsReading() : EcMiscLib.h
  • DisArmEcWdt() : EcMiscLib.h
  • DisplayDimmPopulationErrMsg() : SaPlatformInitAdvancedDxe.c
  • DttMailboxCoreParkHint() : Ps2IoTrapHandler.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- e -

  • EarlyPlatformPchInit() : PlatformInitAdvancedPreMem.c
  • EC_REAL_BAT1_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT1_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT1_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT1_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT2_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT2_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT_CHARGING_MASK : BaseEcFlashLib.h
  • EC_REAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_STATUS : BaseEcFlashLib.h
  • EcForceResetAfterAcRemoval() : EcMiscLib.h
  • EcInit() : PlatformInitAdvancedPreMem.c
  • EcInterface() : EcLib.h
  • EcReset() : EcMiscLib.h
  • EcResetEcInNormalMode() : EcMiscLib.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION : I2cBusConfigurationManagement.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL : I2cBusConfigurationManagement.h
  • EFI_I2C_MASTER_BUS_FREQUENCY_SET : I2cMaster.h
  • EFI_I2C_MASTER_PROTOCOL : I2cMaster.h
  • EFI_I2C_MASTER_RESET : I2cMaster.h
  • EFI_I2C_MASTER_START_REQUEST : I2cMaster.h
  • EFI_PASSWORD_STATUS_REVISION : Setup.h
  • EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS : RstConfigSpaceAccess.h
  • EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF : RstConfigSpaceAccess.h
  • EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_GUID : RstConfigSpaceAccess.h
  • EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_VERSION : RstConfigSpaceAccess.h
  • EFI_USB_DEVICE_MODE_PROTOCOL_GUID : UsbDeviceModeProtocol.h
  • EFI_USBFN_IO_ABORT_TRANSFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX : EfiUsbFnIo.h
  • EFI_USBFN_IO_DETECT_PORT : EfiUsbFnIo.h
  • EFI_USBFN_IO_EVENTHANDLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_FREE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_DEVICE_INFO : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_MAXTRANSFER_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_START_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_STOP_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_TRANSFER : EfiUsbFnIo.h
  • EnableAcpiCallback() : PlatformInitAdvancedSmm.c
  • EnableEcAcpiMode() : EcMiscLib.h
  • EnableFingerPrintSensorWakeSupport() : PlatformInitAdvancedSmm.c
  • EnableLanPower() : EcMiscLib.h
  • EnablePchPcieWakeSupport() : PlatformInitAdvancedSmm.c
  • EnablePchTier2GpioWakeSupport() : PlatformInitAdvancedSmm.c
  • EnableSataPort2Power() : EcMiscLib.h
  • END_OF_RESOURCES : SmmTxtResource.h
  • EndofDxeCallback() : PlatformInitAdvancedDxe.c
  • EOPSetMemoryAttributesInMtrrSettings() : PlatformInitAdvancedPostMem.c
  • eSpiEcSmiCallback() : EcSmi.c , PlatformInitAdvancedSmm.h
  • ExitLowPowerMode() : EcMiscLib.h
  • ExpandPartitionsDevPath() : DxePlatformBootManagerLib.h
  • ExtendPCR7CallBack() : PlatformInitAdvancedDxe.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- f -

  • FoxvilleLanGpioInit() : PlatformInitAdvancedPostMem.c
  • FW_UPDATE_MODE_ENTRY : RetimerCapsuleUpdate.h
  • FW_UPDATE_MODE_EXIT : RetimerCapsuleUpdate.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- g -

  • GET_LIFE_CYCLE_STATE : LifeCycleState.h
  • GetBatteryNumber() : EcMiscLib.h
  • GetBoardInfo() : EcMiscLib.h
  • GetBootStateAfterCapsule() : BootStateLib.h
  • GetCppIndexCoreInformation() : Ps2IoTrapHandler.c
  • GetCpuReArmSupport() : PlatformInitAdvancedPostMem.c
  • GetDccCurrentFreq() : PlatformInitAdvancedDxe.c
  • GetDebugInterface() : SerialPortParameterLib.h
  • GetFanSpeed() : EcMiscLib.h
  • GetFastBootFlagStatus() : PlatformNvRamHookLib.h
  • GetGopVbtData() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • GetHotkeyScanCode() : EcMiscLib.h
  • GetLifeCycleState() : LifeCycleState.h
  • GetPcieDockStatus() : EcMiscLib.h
  • GetPdControllerMode() : EcTcssLib.h
  • GetPDInformation() : EcLib.h
  • GetPeiPlatformLidStatus() : PlatformInitAdvancedPostMem.c
  • GetPlatformDockStatus() : GopPolicyInitDxe.c
  • GetPlatformLidStatus() : GopPolicyInitDxe.c
  • GetPmcCrashLogAmount() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogDescriptTblAddr() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogRecord() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogSupport() : PlatformInitAdvancedPostMem.c
  • GetPmcReArmSupport() : PlatformInitAdvancedPostMem.c
  • GetPmcValidRecord() : PlatformInitAdvancedPostMem.c
  • GetPostCodeBreak() : PlatformNvRamHookLib.h
  • GetRtc3Address() : PlatformNvRamHookLib.h
  • GetSerialPortBaudRate() : SerialPortParameterLib.h
  • GetTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • GetTxtAliasCheckAndReset() : PlatformNvRamHookLib.h
  • GetVariableFromHob() : MultiPlatSupportLib.h
  • GetVbtData() : GopPolicyInitDxe.c
  • GopPolicyInitDxe() : GopPolicyInitDxe.h , GopPolicyInitDxe.c
  • GpioInitAdvanced() : PlatformInitAdvancedPostMem.c
  • GpioInitEarlyWwanPreMem() : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- h -

  • HEADER_ALIGNMENT : MultiPlatSupport.h
  • HeciPlatformDebugCapabilityMsgCallback() : MePolicyInitDxe.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- i -

  • ICC_SETUP_DATA_REVISION : IccSetupData.h
  • InitializePlatformSmm() : PlatformInitAdvancedSmm.c
  • InitializeRecovery() : PeiPlatformRecoveryLib.h
  • InitRtcWakeup() : PlatformInitAdvancedSmm.c
  • InstallTrustedDeviceSetupExtensionProtocol() : TrustedDeviceSetup.h
  • InstallTsnFv() : PeiTsnFvLib.h
  • IsBiosSubRegionFmpGuid() : PeiSubRegionLib.h
  • IsBootStatePresent() : BootStateLib.h
  • IsChecksumBad() : PlatformNvRamHookLib.h
  • IsFastBootEnabled() : PlatformInitAdvancedPreMem.c
  • IsItPartitionsDevicePath() : DxePlatformBootManagerLib.h
  • IsOverclockingEnabled() : PlatformInitAdvancedPreMem.c
  • IsPremiumPmicPresent() : PlatformInitAdvancedPostMem.c
  • IsTrustedDeviceSetupBoot() : TrustedDeviceSetup.h
  • IsTrustedDeviceSetupBootLock() : TrustedDeviceSetup.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- l -

  • LoadFlashTsnFv() : PeiTsnFvLib.h
  • LoadRealModeFile() : GfxInt15Interface.c
  • LoadSecurePreMemoryData() : SecurePreMemoryDataLoadLib.h
  • LpcEcResetEcInNormalMode() : EcLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- m -

  • ME_SETUP_REVISION : SetupVariable.h
  • MemoryDiscoveredPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • MePolicyInitDxe() : MePolicyInitDxe.h , MePolicyInitDxe.c
  • MtrrLibApplyVariableMtrrs() : PlatformInitAdvancedPostMem.c
  • MtrrLibGetRawVariableRanges() : PlatformInitAdvancedPostMem.c
  • MtrrLibInitializeMtrrMask() : PlatformInitAdvancedPostMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- n -

  • NeedResetBoardDefaultVariableHob() : PlatformNvRamHookLib.h
  • NotifyEcToPdForPcieTunnel() : EcMiscLib.h
  • NotifyEcToPdForVpro() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- o -

  • OnResetNotifyInstall() : PlatformInitAdvancedDxe.c
  • OS_PROFILE_REVISION : OemSetup.h
  • OverwriteCpuWakeEnValue() : PlatformInitAdvancedSmm.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- p -

  • PCH_GPIO_PAD : PlatformInfo.h
  • PCH_SETUP_REVISION : SetupVariable.h
  • PchPolicyInitDxe() : PchPolicyInitDxe.h , PchPolicyInitDxe.c
  • PchReset() : PlatformInitAdvancedPreMem.c
  • PchTcoTimeoutCallback() : PlatformInitAdvancedSmm.c
  • PCI_BUS_SETUP_REVISION : PciBusSetup.h
  • PcieCardResetWorkAround() : PcieWorkaroundOnPolicy.h
  • PciEnumCompleteCallback() : SaPlatformInitAdvancedDxe.c
  • PdtUpdate() : PdtUpdateLib.h
  • PeiExtendMeMeasuredBootNotifyCallback() : PlatformInitAdvancedPreMem.c
  • PeiGetSectionFromFv() : PeiGetFvInfoLib.h
  • PeiGraphicsPlatformInit() : PlatformInitAdvancedPostMem.c
  • PeiReadWriteVariableInit() : PeiReadWriteVariableLib.h
  • PeiWdtApp() : PeiWdtAppLib.h
  • PlatformDebugStateChecks() : PlatformInitAdvancedPostMem.c
  • PlatformDebugStateChecksCallback() : PlatformInitAdvancedPostMem.c
  • PlatformDxeReadyToBootCallback() : PlatformInitAdvancedDxe.c
  • PlatformInitAdvancedDxeEntryPoint() : PlatformInitAdvancedDxe.c
  • PlatformInitAdvancedEndOfPei() : PlatformInitAdvancedPostMem.c
  • PlatformInitAdvancedPostMemEntryPoint() : PlatformInitAdvancedPostMem.c
  • PlatformInitAdvancedPreMemEntryPoint() : PlatformInitAdvancedPreMem.c
  • PlatformInitPreMem() : PlatformInitAdvancedPreMem.c
  • PlatformPchInit() : PlatformInitAdvancedPreMem.c
  • PlatformResetNotificationCallback() : PlatformInitAdvancedDxe.c
  • PlatformSecureLibTestConstructor() : PlatformSecureLib.h
  • PlatformSpecificInitPreMem() : PlatformInitAdvancedPreMem.c
  • PlatformVoltageInit() : PlatformInitAdvancedPreMem.c
  • PolicyInitAdvancedDxeEntryPoint() : PolicyInitAdvancedDxe.c , PolicyInitAdvancedDxe.h
  • PowerButtonCallback() : PlatformInitAdvancedSmm.h , PlatformInitAdvancedSmm.c
  • PowerStateIsAc() : EcMiscLib.h
  • PremiumPmicEnableSlpS0Voltage() : PlatformInitAdvancedPostMem.c
  • ProgramRichtekVccGtOverride() : PlatformInitAdvancedPreMem.c
  • ProgramRichtekVccIaOverride() : PlatformInitAdvancedPreMem.c
  • ProgramVcc1p05Override() : PlatformInitAdvancedPreMem.c
  • ProgramVcc1p8Override() : PlatformInitAdvancedPreMem.c
  • ProgramVccDd2Override() : PlatformInitAdvancedPreMem.c
  • ProgramVccInAuxOverride() : PlatformInitAdvancedPreMem.c
  • ProgramVoltageOverrides() : PlatformInitAdvancedPreMem.c
  • Ps2IoTrapHandler() : Ps2IoTrapHandler.c
  • PssDetect() : PssLib.h
  • PssGetSerialNumber() : PssLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- q -

  • QuerySmiEvent() : EcMiscLib.h
  • QuerySysStatus() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- r -

  • ReadEcRam() : EcMiscLib.h
  • ReadLowPowerModeRequirementReg() : PlatformInitAdvancedDxe.c
  • ReadPssData() : PssLib.h
  • ReadRtcIndex() : PlatformInitAdvancedSmm.c
  • ReadSectionInformationFromFv() : PeiSubRegionLib.h
  • ReceiveEcData() : EcLib.h
  • ReceiveEcStatus() : EcLib.h
  • RegisterDisplayDimmPopulationErrMsg() : SaPlatformInitAdvancedDxe.c
  • RegisterEndOfDxeCallbacks() : PlatformInitAdvancedDxe.c
  • RegisterExtendPCR7CallBack() : PlatformInitAdvancedDxe.c
  • RegisterReadyToBootCallback() : PlatformInitAdvancedDxe.c
  • RegisterTcoTimeoutHandler() : PlatformInitAdvancedSmm.c
  • RESET_GENERATOR_PORT : PlatformInitAdvancedPreMem.c
  • RESOURCE : SmmTxtResource.h
  • RICHTEK_VR_SECONDARY_ADDRESS : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- s -

  • S3SleepEntryCallBack() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • S4SleepEntryCallBack() : PlatformInitAdvancedSmm.h , PlatformInitAdvancedSmm.c
  • S5SleepEntryCallBack() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • SA_SETUP_REVISION : SetupVariable.h
  • SaPlatformInitDxe() : PlatformInitAdvancedDxe.h , SaPlatformInitAdvancedDxe.c
  • SaPolicyInitDxe() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • SaveCpuRatio() : PlatformNvRamHookLib.h
  • SaveTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • SaveTxtAliasCheck() : PlatformNvRamHookLib.h
  • SecondaryNvRamInit() : PlatformNvRamHookLib.h
  • SECURE_BOOT_VARIABLE_REVISION : SecureBootSetup.h
  • SendEcCommand() : EcLib.h
  • SendEcData() : EcLib.h
  • SerialIoUartDebugGetAttributes() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugGetControllerNumber() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugGetPciDefaultMmioBase() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugInit() : SerialIoUartDebugHelperLib.h
  • SerialIoUartDebugWrite() : SerialIoUartDebugHelperLib.h
  • SetBclkRampFlag() : PlatformNvRamHookLib.h
  • SetBootState() : BootStateLib.h
  • SetBootStateAfterCapsule() : BootStateLib.h
  • SetCacheMtrrAfterEndOfPei() : PlatformInitAdvancedPostMem.c
  • SetDebugInterface() : SerialPortParameterLib.h
  • SetEcCriticalShutdownTemperature() : EcMiscLib.h
  • SetFailSafeFanCtrl() : EcMiscLib.h
  • SetLastUpdateTimeInVariable() : PlatformTelemetryLib.h
  • SetMtrrsFromBuffer() : PlatformInitAdvancedDxe.c
  • SetPdControllerMode() : EcTcssLib.h
  • SetPmicVoltage() : EcMiscLib.h
  • SetSerialPortBaudRate() : SerialPortParameterLib.h
  • SetSlpS0Voltage() : EcMiscLib.h
  • SetTheStateToGoAfterG3() : PlatformInitAdvancedPreMem.c
  • SETUP_CPU_FEATURES_REVISION : OemSetup.h
  • SETUP_DATA_REVISION : SetupVariable.h
  • SETUP_VOLATILE_DATA_REVISION : OemSetup.h
  • SetupPs2IoTrap() : Ps2IoTrapHandler.c , PlatformInitAdvancedSmm.h
  • SetVariableToHob() : MultiPlatSupportLib.h
  • SI_SETUP_REVISION : SetupVariable.h
  • SiliconPolicyInitDxe() : SiliconPolicyInitDxe.c , SiliconPolicyInitDxe.h
  • SiPreMemPolicyPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • SkipBootToFwUI() : TrustedDeviceSetup.h
  • SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES : TrustedDeviceSetupMainProtocol.h
  • SpiFlashBlockErase() : SpiFlashCommon.h
  • SpiFlashLock() : SpiFlashCommon.h
  • SpiFlashRead() : SpiFlashCommon.h
  • SpiFlashWrite() : SpiFlashCommon.h
  • STM_MAP_ADDRESS_RANGE : SmmTxtResource.h
  • SuppressUserInput() : TrustedDeviceSetup.h
  • SyncItbtVariables() : SaPlatformInitAdvancedDxe.c
  • SYSTEM_ACCESS_REVISION : Setup.h
  • SystemPowerOff() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- t -

  • TBT_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h
  • TbtPolicyInitDxe() : TbtPolicyInitDxe.c , TbtPolicyInitDxe.h
  • TCG2_CONFIGURATION_REVISION : Tcg2ConfigNvData.h
  • Tcg2PhysicalPresenceLibGetManagementFlags() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibNeedUserConfirm() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibProcessRequest() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction() : Tcg2PhysicalPresenceLib.h
  • TCG_SETUP_REVISION : TcgSetup.h
  • tcgAddBOOLEAN() : TcgCore.h
  • tcgAddByteSequence() : TcgCore.h
  • tcgAddCall() : TcgCore.h
  • tcgAddEndList() : TcgCore.h
  • tcgAddEndName() : TcgCore.h
  • tcgAddEndOfData() : TcgCore.h
  • tcgAddEndOfSession() : TcgCore.h
  • tcgAddEndTransaction() : TcgCore.h
  • tcgAddInteger() : TcgCore.h
  • tcgAddRawByte() : TcgCore.h
  • tcgAddStartList() : TcgCore.h
  • tcgAddStartName() : TcgCore.h
  • tcgAddStartTransaction() : TcgCore.h
  • tcgAddTcgUid() : TcgCore.h
  • tcgAddUINT16() : TcgCore.h
  • tcgAddUINT32() : TcgCore.h
  • tcgAddUINT64() : TcgCore.h
  • tcgAddUINT8() : TcgCore.h
  • tcgCheckComIds() : TcgUtil.h
  • tcgCreateEndSession() : TcgUtil.h
  • tcgCreateSetCPin() : TcgUtil.h
  • tcgCreateStartSession() : TcgUtil.h
  • TcgCreateStruct : TcgCore.h
  • tcgEndComPacket() : TcgCore.h
  • tcgEndMethodCall() : TcgUtil.h
  • tcgEndPacket() : TcgCore.h
  • tcgEndParameters() : TcgUtil.h
  • tcgEndSubPacket() : TcgCore.h
  • tcgGetAtomInfo() : TcgCore.h
  • tcgGetComIds() : TcgUtil.h
  • tcgGetMethodStatus() : TcgUtil.h
  • tcgGetNextBOOLEAN() : TcgCore.h
  • tcgGetNextByteSequence() : TcgCore.h
  • tcgGetNextCall() : TcgCore.h
  • tcgGetNextEndList() : TcgCore.h
  • tcgGetNextEndName() : TcgCore.h
  • tcgGetNextEndOfData() : TcgCore.h
  • tcgGetNextEndOfSession() : TcgCore.h
  • tcgGetNextEndTransaction() : TcgCore.h
  • tcgGetNextStartList() : TcgCore.h
  • tcgGetNextStartName() : TcgCore.h
  • tcgGetNextStartTransaction() : TcgCore.h
  • tcgGetNextTcgUid() : TcgCore.h
  • tcgGetNextToken() : TcgCore.h
  • tcgGetNextTokenType() : TcgCore.h
  • tcgGetNextUINT16() : TcgCore.h
  • tcgGetNextUINT32() : TcgCore.h
  • tcgGetNextUINT64() : TcgCore.h
  • tcgGetNextUINT8() : TcgCore.h
  • tcgGetTokenByteSequence() : TcgCore.h
  • tcgGetTokenUINT64() : TcgCore.h
  • tcgInitTcgCreateStruct() : TcgCore.h
  • tcgInitTcgParseStruct() : TcgCore.h
  • tcgIsLocked() : TcgUtil.h
  • tcgIsProtocolSupported() : TcgUtil.h
  • tcgMethodStatusString() : TcgUtil.h
  • TcgParseStruct : TcgCore.h
  • tcgParseSyncSession() : TcgUtil.h
  • TcgResult : TcgCore.h
  • TcgResult_Failure : TcgCore.h
  • TcgResult_Failure_BufferTooSmall : TcgCore.h
  • TcgResult_Failure_EndBuffer : TcgCore.h
  • TcgResult_Failure_InvalidAction : TcgCore.h
  • TcgResult_Failure_InvalidType : TcgCore.h
  • TcgResult_Failure_NullPointer : TcgCore.h
  • TcgResult_Failure_ZeroSize : TcgCore.h
  • TcgResult_Success : TcgCore.h
  • tcgSetAuthorityEnabled() : TcgUtil.h
  • tcgStartComPacket() : TcgCore.h
  • tcgStartMethodCall() : TcgUtil.h
  • tcgStartPacket() : TcgCore.h
  • tcgStartParameters() : TcgUtil.h
  • tcgStartSubPacket() : TcgCore.h
  • TcgToken : TcgCore.h
  • tcgTokenTypeString() : TcgUtil.h
  • TcgUid : Tcg.h
  • TCSS_RETIMER_INFO : RetimerCapsuleUpdate.h
  • TCSS_RETIMER_PROTOCOL : RetimerCapsuleUpdate.h
  • TCSS_RETIMER_PROTOCOL_GUID : RetimerCapsuleUpdate.h
  • TIME_OUT_INFO_REVISION : BootMaintSetup.h
  • TOTAL_SERIAL_PORT_INFO_REVISION : BootMaintSetup.h
  • TouchPanelGpioInit() : PlatformInitAdvancedPostMem.c
  • TRUSTED_DEVICE_SETUP_BOOT_ENABLE : TrustedDeviceSetup.h
  • TRUSTED_DEVICE_SETUP_BOOT_LOCK : TrustedDeviceSetup.h
  • TRUSTED_DEVICE_SETUP_ENTRY : TrustedDeviceSetupMainProtocol.h
  • TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION : TrustedDeviceSetupMainProtocol.h
  • TrustedDeviceSetupAddKeyboard() : TrustedDeviceSetup.h
  • TrustedDeviceSetupChassisIntrusionDetected() : TrustedDeviceSetup.h
  • TrustedDeviceSetupChassisIntrusionEnabled() : TrustedDeviceSetup.h
  • TrustedDeviceSetupMain() : TrustedDeviceSetup.h
  • TrustedDeviceSetupRemoveKeyboard() : TrustedDeviceSetup.h
  • TrustedDeviceSetupSetDisplayResolution() : TrustedDeviceSetup.h
  • TXT_RESET_SYSTEM : TxtOneTouchOp.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- u -

  • UnsetBootState() : BootStateLib.h
  • UpdateDebugConfigPcds() : PlatformInitAdvancedPreMem.c
  • UpdateDevicePower() : EcMiscLib.h
  • UpdateDimmPopulation() : PlatformInitAdvancedDxe.h , SaPlatformInitAdvancedDxe.c
  • UpdateDxeAmtPolicy() : DxeAmtPolicyUpdateLib.h
  • UpdateDxeAmtPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeMePolicy() : DxeMePolicyUpdateLib.h
  • UpdateDxeMePolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxePchPolicy() : DxePchPolicyUpdateLib.h
  • UpdateDxeSaPolicy() : DxeSaPolicyUpdateLib.h
  • UpdateDxeSaPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeSiCpuPolicy() : DxeCpuPolicyUpdateLib.h
  • UpdateDxeTbtPolicy() : DxeTbtPolicyUpdateLib.h
  • UpdateFastBootFlagStatus() : PlatformNvRamHookLib.h
  • UpdateGmAdrRegionToWriteCombine() : SaPlatformInitAdvancedDxe.c
  • UpdateItbtDmaUuidVariable() : SaPlatformInitAdvancedDxe.c
  • UpdateMemorySpaceAttributes() : PlatformInitAdvancedDxe.c
  • UpdatePeiCpuPolicyDebug() : PeiCpuPolicyDebugLib.h
  • UpdatePeiCpuPolicyDebugPreMem() : PeiCpuPolicyDebugLib.h
  • UpdatePeiPchPolicyDebug() : PeiPchPolicyDebugLib.h
  • UpdatePeiPchPolicyDebugPreMem() : PeiPchPolicyDebugLib.h
  • UpdatePeiSaPolicyDebug() : PeiSaPolicyDebugLib.h
  • UpdatePeiSaPolicyDebugPreMem() : PeiSaPolicyDebugLib.h
  • UpdatePeiSiPolicyDebug() : PeiSiPolicyDebugLib.h
  • UpdatePwm() : EcMiscLib.h
  • UpdateSaPolicyGopVbtPointer() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • UpdateSmbiosTrustedDeviceSetupCapabilities() : TrustedDeviceSetup.h
  • UsbcGetUsbConnStatus() : EcTcssLib.h
  • UsbcIomReadyNotify() : EcTcssLib.h
  • USBCRetimerComplianceModePreMem() : PlatformInitAdvancedPreMem.c
  • UsbcRetimerCompliancePDMessage() : EcTcssLib.h
  • UsbcSxEntry() : EcTcssLib.h
  • UsbcSxExit() : EcTcssLib.h


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- v -

  • VAR_ADDED : MultiPlatSupport.h
  • VAR_DELETED : MultiPlatSupport.h
  • VAR_HEADER_VALID_ONLY : MultiPlatSupport.h
  • VAR_IN_DELETED_TRANSITION : MultiPlatSupport.h
  • VARIABLE_DATA : MultiPlatSupport.h
  • VARIABLE_STORE_FORMATTED : MultiPlatSupport.h
  • VARIABLE_STORE_STATUS : MultiPlatSupport.h
  • VCCIN_AUX_SECONDARY_ADDRESS : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

Here is a list of all documented file members with links to the documentation:

- w -

  • WakeOnRTCS5() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • WakeUpEc() : EcMiscLib.h
  • WdtAppPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • WriteEcRam() : EcMiscLib.h
  • WritePssData() : PssLib.h
  • WriteRtcIndex() : PlatformInitAdvancedSmm.c


AlderLake Platform Sample Code: File Members

- a -

  • AcpiGnvsInit() : DxeAcpiGnvsInitLib.h
  • AllocateMemoryBelow4G() : PlatformInitAdvancedDxe.c
  • AmtPolicyInitDxe() : AmtPolicyInitDxe.h , AmtPolicyInitDxe.c
  • ArmEcWdtWithTimeOut() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

- b -

  • BCDToDec() : PlatformInitAdvancedSmm.c
  • BiosEcWdtReadCommand() : EcMiscLib.h
  • BiosEcWdtWriteCommand() : EcMiscLib.h
  • BootGuardOemRevocationHook() : BootGuardRevocationLib.h
  • BuildDebugConfigDataHob() : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

- c -

  • CheckSataRaidMode() : BasePlatformVariableLib.h
  • ClearBootNext() : TrustedDeviceSetup.h
  • ClearDiagnosticStatus() : PlatformNvRamHookLib.h
  • ClearTenSecPwrButtonMode() : EcMiscLib.h
  • ConfigureGpio() : PlatformInitAdvancedPostMem.c , PlatformInitAdvancedPreMem.c
  • ConfigurePciHostBridgePcds() : PlatformInitAdvancedPostMem.c
  • CpuCrashLogCollectDataFromTelemetrySRAM() : PlatformInitAdvancedPostMem.c
  • CpuDxePrintPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuInstallPolicyProtocol() : DxeCpuPolicyUpdateLib.h
  • CpuPolicyInitDxe() : CpuPolicyInitDxe.c , CpuPolicyInitDxe.h
  • CrashLogCollectDataFromPmcSSRAM() : PlatformInitAdvancedPostMem.c
  • CreateAttemptUsbFirstHotkeyInfoHob() : PlatformInitAdvancedPostMem.c
  • CreateBootguardEventLogEntries() : PeiBootGuardEventLogLib.h
  • CreateDefaultVariableHob() : MultiPlatSupportLib.h
  • CreateFastBootHob() : PlatformInitAdvancedPreMem.c
  • CvfGpioInit() : PlatformInitAdvancedPostMem.c


AlderLake Platform Sample Code: File Members

- d -

  • DecToBCD() : PlatformInitAdvancedSmm.c
  • DetectEc() : EcLib.h
  • DetectEcRevision() : EcMiscLib.h
  • DetectEcSupport() : EcMiscLib.h
  • DetectPmicVendorID() : EcMiscLib.h
  • DevicePathToStr() : DxePlatformBootManagerLib.h
  • DfctFastChargingMode() : EcMiscLib.h
  • DisableAcpiCallback() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • DisableEcSmiMode() : EcMiscLib.h
  • DisablePchDtsReading() : EcMiscLib.h
  • DisArmEcWdt() : EcMiscLib.h
  • DisplayDimmPopulationErrMsg() : SaPlatformInitAdvancedDxe.c
  • DttMailboxCoreParkHint() : Ps2IoTrapHandler.c


AlderLake Platform Sample Code: File Members

- e -

  • EarlyPlatformPchInit() : PlatformInitAdvancedPreMem.c
  • EcForceResetAfterAcRemoval() : EcMiscLib.h
  • EcInit() : PlatformInitAdvancedPreMem.c
  • EcInterface() : EcLib.h
  • EcReset() : EcMiscLib.h
  • EcResetEcInNormalMode() : EcMiscLib.h
  • EnableAcpiCallback() : PlatformInitAdvancedSmm.c
  • EnableEcAcpiMode() : EcMiscLib.h
  • EnableFingerPrintSensorWakeSupport() : PlatformInitAdvancedSmm.c
  • EnableLanPower() : EcMiscLib.h
  • EnablePchPcieWakeSupport() : PlatformInitAdvancedSmm.c
  • EnablePchTier2GpioWakeSupport() : PlatformInitAdvancedSmm.c
  • EnableSataPort2Power() : EcMiscLib.h
  • EndofDxeCallback() : PlatformInitAdvancedDxe.c
  • EOPSetMemoryAttributesInMtrrSettings() : PlatformInitAdvancedPostMem.c
  • eSpiEcSmiCallback() : EcSmi.c , PlatformInitAdvancedSmm.h
  • ExitLowPowerMode() : EcMiscLib.h
  • ExpandPartitionsDevPath() : DxePlatformBootManagerLib.h
  • ExtendPCR7CallBack() : PlatformInitAdvancedDxe.c


AlderLake Platform Sample Code: File Members

- f -

  • FoxvilleLanGpioInit() : PlatformInitAdvancedPostMem.c


AlderLake Platform Sample Code: File Members

- g -

  • GetBatteryNumber() : EcMiscLib.h
  • GetBoardInfo() : EcMiscLib.h
  • GetBootStateAfterCapsule() : BootStateLib.h
  • GetCppIndexCoreInformation() : Ps2IoTrapHandler.c
  • GetCpuReArmSupport() : PlatformInitAdvancedPostMem.c
  • GetDccCurrentFreq() : PlatformInitAdvancedDxe.c
  • GetDebugInterface() : SerialPortParameterLib.h
  • GetFanSpeed() : EcMiscLib.h
  • GetFastBootFlagStatus() : PlatformNvRamHookLib.h
  • GetGopVbtData() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • GetHotkeyScanCode() : EcMiscLib.h
  • GetLifeCycleState() : LifeCycleState.h
  • GetPcieDockStatus() : EcMiscLib.h
  • GetPdControllerMode() : EcTcssLib.h
  • GetPDInformation() : EcLib.h
  • GetPeiPlatformLidStatus() : PlatformInitAdvancedPostMem.c
  • GetPlatformDockStatus() : GopPolicyInitDxe.c
  • GetPlatformLidStatus() : GopPolicyInitDxe.c
  • GetPmcCrashLogAmount() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogDescriptTblAddr() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogRecord() : PlatformInitAdvancedPostMem.c
  • GetPmcCrashLogSupport() : PlatformInitAdvancedPostMem.c
  • GetPmcReArmSupport() : PlatformInitAdvancedPostMem.c
  • GetPmcValidRecord() : PlatformInitAdvancedPostMem.c
  • GetPostCodeBreak() : PlatformNvRamHookLib.h
  • GetRtc3Address() : PlatformNvRamHookLib.h
  • GetSerialPortBaudRate() : SerialPortParameterLib.h
  • GetTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • GetTxtAliasCheckAndReset() : PlatformNvRamHookLib.h
  • GetVariableFromHob() : MultiPlatSupportLib.h
  • GetVbtData() : GopPolicyInitDxe.c
  • GopPolicyInitDxe() : GopPolicyInitDxe.h , GopPolicyInitDxe.c
  • GpioInitAdvanced() : PlatformInitAdvancedPostMem.c
  • GpioInitEarlyWwanPreMem() : PlatformInitAdvancedPreMem.c


AlderLake Platform Sample Code: File Members

- h -

  • HeciPlatformDebugCapabilityMsgCallback() : MePolicyInitDxe.h


AlderLake Platform Sample Code: File Members

- i -

  • InitializePlatformSmm() : PlatformInitAdvancedSmm.c
  • InitializeRecovery() : PeiPlatformRecoveryLib.h
  • InitRtcWakeup() : PlatformInitAdvancedSmm.c
  • InstallTrustedDeviceSetupExtensionProtocol() : TrustedDeviceSetup.h
  • InstallTsnFv() : PeiTsnFvLib.h
  • IsBiosSubRegionFmpGuid() : PeiSubRegionLib.h
  • IsBootStatePresent() : BootStateLib.h
  • IsChecksumBad() : PlatformNvRamHookLib.h
  • IsFastBootEnabled() : PlatformInitAdvancedPreMem.c
  • IsItPartitionsDevicePath() : DxePlatformBootManagerLib.h
  • IsOverclockingEnabled() : PlatformInitAdvancedPreMem.c
  • IsPremiumPmicPresent() : PlatformInitAdvancedPostMem.c
  • IsTrustedDeviceSetupBoot() : TrustedDeviceSetup.h
  • IsTrustedDeviceSetupBootLock() : TrustedDeviceSetup.h


AlderLake Platform Sample Code: File Members

- l -

  • LoadFlashTsnFv() : PeiTsnFvLib.h
  • LoadRealModeFile() : GfxInt15Interface.c
  • LoadSecurePreMemoryData() : SecurePreMemoryDataLoadLib.h
  • LpcEcResetEcInNormalMode() : EcLib.h


AlderLake Platform Sample Code: File Members

- m -

  • MemoryDiscoveredPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • MePolicyInitDxe() : MePolicyInitDxe.c , MePolicyInitDxe.h
  • MtrrLibApplyVariableMtrrs() : PlatformInitAdvancedPostMem.c
  • MtrrLibGetRawVariableRanges() : PlatformInitAdvancedPostMem.c
  • MtrrLibInitializeMtrrMask() : PlatformInitAdvancedPostMem.c


AlderLake Platform Sample Code: File Members

- n -

  • NeedResetBoardDefaultVariableHob() : PlatformNvRamHookLib.h
  • NotifyEcToPdForPcieTunnel() : EcMiscLib.h
  • NotifyEcToPdForVpro() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

- o -

  • OnResetNotifyInstall() : PlatformInitAdvancedDxe.c
  • OverwriteCpuWakeEnValue() : PlatformInitAdvancedSmm.c


AlderLake Platform Sample Code: File Members

- p -

  • PchPolicyInitDxe() : PchPolicyInitDxe.c , PchPolicyInitDxe.h
  • PchReset() : PlatformInitAdvancedPreMem.c
  • PchTcoTimeoutCallback() : PlatformInitAdvancedSmm.c
  • PcieCardResetWorkAround() : PcieWorkaroundOnPolicy.h
  • PciEnumCompleteCallback() : SaPlatformInitAdvancedDxe.c
  • PdtUpdate() : PdtUpdateLib.h
  • PeiExtendMeMeasuredBootNotifyCallback() : PlatformInitAdvancedPreMem.c
  • PeiGetSectionFromFv() : PeiGetFvInfoLib.h
  • PeiGraphicsPlatformInit() : PlatformInitAdvancedPostMem.c
  • PeiReadWriteVariableInit() : PeiReadWriteVariableLib.h
  • PeiWdtApp() : PeiWdtAppLib.h
  • PlatformDebugStateChecks() : PlatformInitAdvancedPostMem.c
  • PlatformDebugStateChecksCallback() : PlatformInitAdvancedPostMem.c
  • PlatformDxeReadyToBootCallback() : PlatformInitAdvancedDxe.c
  • PlatformInitAdvancedDxeEntryPoint() : PlatformInitAdvancedDxe.c
  • PlatformInitAdvancedEndOfPei() : PlatformInitAdvancedPostMem.c
  • PlatformInitAdvancedPostMemEntryPoint() : PlatformInitAdvancedPostMem.c
  • PlatformInitAdvancedPreMemEntryPoint() : PlatformInitAdvancedPreMem.c
  • PlatformInitPreMem() : PlatformInitAdvancedPreMem.c
  • PlatformPchInit() : PlatformInitAdvancedPreMem.c
  • PlatformResetNotificationCallback() : PlatformInitAdvancedDxe.c
  • PlatformSecureLibTestConstructor() : PlatformSecureLib.h
  • PlatformSpecificInitPreMem() : PlatformInitAdvancedPreMem.c
  • PlatformVoltageInit() : PlatformInitAdvancedPreMem.c
  • PolicyInitAdvancedDxeEntryPoint() : PolicyInitAdvancedDxe.h , PolicyInitAdvancedDxe.c
  • PowerButtonCallback() : PlatformInitAdvancedSmm.h , PlatformInitAdvancedSmm.c
  • PowerStateIsAc() : EcMiscLib.h
  • PremiumPmicEnableSlpS0Voltage() : PlatformInitAdvancedPostMem.c
  • ProgramRichtekVccGtOverride() : PlatformInitAdvancedPreMem.c
  • ProgramRichtekVccIaOverride() : PlatformInitAdvancedPreMem.c
  • ProgramVcc1p05Override() : PlatformInitAdvancedPreMem.c
  • ProgramVcc1p8Override() : PlatformInitAdvancedPreMem.c
  • ProgramVccDd2Override() : PlatformInitAdvancedPreMem.c
  • ProgramVccInAuxOverride() : PlatformInitAdvancedPreMem.c
  • ProgramVoltageOverrides() : PlatformInitAdvancedPreMem.c
  • Ps2IoTrapHandler() : Ps2IoTrapHandler.c
  • PssDetect() : PssLib.h
  • PssGetSerialNumber() : PssLib.h


AlderLake Platform Sample Code: File Members

- q -

  • QuerySmiEvent() : EcMiscLib.h
  • QuerySysStatus() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

- r -

  • ReadEcRam() : EcMiscLib.h
  • ReadLowPowerModeRequirementReg() : PlatformInitAdvancedDxe.c
  • ReadPssData() : PssLib.h
  • ReadRtcIndex() : PlatformInitAdvancedSmm.c
  • ReadSectionInformationFromFv() : PeiSubRegionLib.h
  • ReceiveEcData() : EcLib.h
  • ReceiveEcStatus() : EcLib.h
  • RegisterDisplayDimmPopulationErrMsg() : SaPlatformInitAdvancedDxe.c
  • RegisterEndOfDxeCallbacks() : PlatformInitAdvancedDxe.c
  • RegisterExtendPCR7CallBack() : PlatformInitAdvancedDxe.c
  • RegisterReadyToBootCallback() : PlatformInitAdvancedDxe.c
  • RegisterTcoTimeoutHandler() : PlatformInitAdvancedSmm.c


AlderLake Platform Sample Code: File Members

- s -

  • S3SleepEntryCallBack() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • S4SleepEntryCallBack() : PlatformInitAdvancedSmm.h , PlatformInitAdvancedSmm.c
  • S5SleepEntryCallBack() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • SaPlatformInitDxe() : SaPlatformInitAdvancedDxe.c , PlatformInitAdvancedDxe.h
  • SaPolicyInitDxe() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • SaveCpuRatio() : PlatformNvRamHookLib.h
  • SaveTbtHostRouterStatus() : PlatformNvRamHookLib.h
  • SaveTxtAliasCheck() : PlatformNvRamHookLib.h
  • SecondaryNvRamInit() : PlatformNvRamHookLib.h
  • SendEcCommand() : EcLib.h
  • SendEcData() : EcLib.h
  • SerialIoUartDebugGetAttributes() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugGetControllerNumber() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugGetPciDefaultMmioBase() : SerialIoUartDebugPropertyLib.h
  • SerialIoUartDebugInit() : SerialIoUartDebugHelperLib.h
  • SerialIoUartDebugWrite() : SerialIoUartDebugHelperLib.h
  • SetBclkRampFlag() : PlatformNvRamHookLib.h
  • SetBootState() : BootStateLib.h
  • SetBootStateAfterCapsule() : BootStateLib.h
  • SetCacheMtrrAfterEndOfPei() : PlatformInitAdvancedPostMem.c
  • SetDebugInterface() : SerialPortParameterLib.h
  • SetEcCriticalShutdownTemperature() : EcMiscLib.h
  • SetFailSafeFanCtrl() : EcMiscLib.h
  • SetLastUpdateTimeInVariable() : PlatformTelemetryLib.h
  • SetMtrrsFromBuffer() : PlatformInitAdvancedDxe.c
  • SetPdControllerMode() : EcTcssLib.h
  • SetPmicVoltage() : EcMiscLib.h
  • SetSerialPortBaudRate() : SerialPortParameterLib.h
  • SetSlpS0Voltage() : EcMiscLib.h
  • SetTheStateToGoAfterG3() : PlatformInitAdvancedPreMem.c
  • SetupPs2IoTrap() : PlatformInitAdvancedSmm.h , Ps2IoTrapHandler.c
  • SetVariableToHob() : MultiPlatSupportLib.h
  • SiliconPolicyInitDxe() : SiliconPolicyInitDxe.h , SiliconPolicyInitDxe.c
  • SiPreMemPolicyPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • SkipBootToFwUI() : TrustedDeviceSetup.h
  • SpiFlashBlockErase() : SpiFlashCommon.h
  • SpiFlashLock() : SpiFlashCommon.h
  • SpiFlashRead() : SpiFlashCommon.h
  • SpiFlashWrite() : SpiFlashCommon.h
  • SuppressUserInput() : TrustedDeviceSetup.h
  • SyncItbtVariables() : SaPlatformInitAdvancedDxe.c
  • SystemPowerOff() : EcMiscLib.h


AlderLake Platform Sample Code: File Members

- t -

  • TbtPolicyInitDxe() : TbtPolicyInitDxe.c , TbtPolicyInitDxe.h
  • Tcg2PhysicalPresenceLibGetManagementFlags() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibGetUserConfirmationStatusFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibNeedUserConfirm() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibProcessRequest() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibReturnOperationResponseToOsFunction() : Tcg2PhysicalPresenceLib.h
  • Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction() : Tcg2PhysicalPresenceLib.h
  • tcgAddBOOLEAN() : TcgCore.h
  • tcgAddByteSequence() : TcgCore.h
  • tcgAddCall() : TcgCore.h
  • tcgAddEndList() : TcgCore.h
  • tcgAddEndName() : TcgCore.h
  • tcgAddEndOfData() : TcgCore.h
  • tcgAddEndOfSession() : TcgCore.h
  • tcgAddEndTransaction() : TcgCore.h
  • tcgAddInteger() : TcgCore.h
  • tcgAddRawByte() : TcgCore.h
  • tcgAddStartList() : TcgCore.h
  • tcgAddStartName() : TcgCore.h
  • tcgAddStartTransaction() : TcgCore.h
  • tcgAddTcgUid() : TcgCore.h
  • tcgAddUINT16() : TcgCore.h
  • tcgAddUINT32() : TcgCore.h
  • tcgAddUINT64() : TcgCore.h
  • tcgAddUINT8() : TcgCore.h
  • tcgCheckComIds() : TcgUtil.h
  • tcgCreateEndSession() : TcgUtil.h
  • tcgCreateSetCPin() : TcgUtil.h
  • tcgCreateStartSession() : TcgUtil.h
  • tcgEndComPacket() : TcgCore.h
  • tcgEndMethodCall() : TcgUtil.h
  • tcgEndPacket() : TcgCore.h
  • tcgEndParameters() : TcgUtil.h
  • tcgEndSubPacket() : TcgCore.h
  • tcgGetAtomInfo() : TcgCore.h
  • tcgGetComIds() : TcgUtil.h
  • tcgGetMethodStatus() : TcgUtil.h
  • tcgGetNextBOOLEAN() : TcgCore.h
  • tcgGetNextByteSequence() : TcgCore.h
  • tcgGetNextCall() : TcgCore.h
  • tcgGetNextEndList() : TcgCore.h
  • tcgGetNextEndName() : TcgCore.h
  • tcgGetNextEndOfData() : TcgCore.h
  • tcgGetNextEndOfSession() : TcgCore.h
  • tcgGetNextEndTransaction() : TcgCore.h
  • tcgGetNextStartList() : TcgCore.h
  • tcgGetNextStartName() : TcgCore.h
  • tcgGetNextStartTransaction() : TcgCore.h
  • tcgGetNextTcgUid() : TcgCore.h
  • tcgGetNextToken() : TcgCore.h
  • tcgGetNextTokenType() : TcgCore.h
  • tcgGetNextUINT16() : TcgCore.h
  • tcgGetNextUINT32() : TcgCore.h
  • tcgGetNextUINT64() : TcgCore.h
  • tcgGetNextUINT8() : TcgCore.h
  • tcgGetTokenByteSequence() : TcgCore.h
  • tcgGetTokenUINT64() : TcgCore.h
  • tcgInitTcgCreateStruct() : TcgCore.h
  • tcgInitTcgParseStruct() : TcgCore.h
  • tcgIsLocked() : TcgUtil.h
  • tcgIsProtocolSupported() : TcgUtil.h
  • tcgMethodStatusString() : TcgUtil.h
  • tcgParseSyncSession() : TcgUtil.h
  • tcgSetAuthorityEnabled() : TcgUtil.h
  • tcgStartComPacket() : TcgCore.h
  • tcgStartMethodCall() : TcgUtil.h
  • tcgStartPacket() : TcgCore.h
  • tcgStartParameters() : TcgUtil.h
  • tcgStartSubPacket() : TcgCore.h
  • tcgTokenTypeString() : TcgUtil.h
  • TouchPanelGpioInit() : PlatformInitAdvancedPostMem.c
  • TrustedDeviceSetupAddKeyboard() : TrustedDeviceSetup.h
  • TrustedDeviceSetupChassisIntrusionDetected() : TrustedDeviceSetup.h
  • TrustedDeviceSetupChassisIntrusionEnabled() : TrustedDeviceSetup.h
  • TrustedDeviceSetupMain() : TrustedDeviceSetup.h
  • TrustedDeviceSetupRemoveKeyboard() : TrustedDeviceSetup.h
  • TrustedDeviceSetupSetDisplayResolution() : TrustedDeviceSetup.h


AlderLake Platform Sample Code: File Members

- u -

  • UnsetBootState() : BootStateLib.h
  • UpdateDebugConfigPcds() : PlatformInitAdvancedPreMem.c
  • UpdateDevicePower() : EcMiscLib.h
  • UpdateDimmPopulation() : PlatformInitAdvancedDxe.h , SaPlatformInitAdvancedDxe.c
  • UpdateDxeAmtPolicy() : DxeAmtPolicyUpdateLib.h
  • UpdateDxeAmtPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeMePolicy() : DxeMePolicyUpdateLib.h
  • UpdateDxeMePolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxePchPolicy() : DxePchPolicyUpdateLib.h
  • UpdateDxeSaPolicy() : DxeSaPolicyUpdateLib.h
  • UpdateDxeSaPolicyBoardConfig() : DxePolicyBoardConfigLib.h
  • UpdateDxeSiCpuPolicy() : DxeCpuPolicyUpdateLib.h
  • UpdateDxeTbtPolicy() : DxeTbtPolicyUpdateLib.h
  • UpdateFastBootFlagStatus() : PlatformNvRamHookLib.h
  • UpdateGmAdrRegionToWriteCombine() : SaPlatformInitAdvancedDxe.c
  • UpdateItbtDmaUuidVariable() : SaPlatformInitAdvancedDxe.c
  • UpdateMemorySpaceAttributes() : PlatformInitAdvancedDxe.c
  • UpdatePeiCpuPolicyDebug() : PeiCpuPolicyDebugLib.h
  • UpdatePeiCpuPolicyDebugPreMem() : PeiCpuPolicyDebugLib.h
  • UpdatePeiPchPolicyDebug() : PeiPchPolicyDebugLib.h
  • UpdatePeiPchPolicyDebugPreMem() : PeiPchPolicyDebugLib.h
  • UpdatePeiSaPolicyDebug() : PeiSaPolicyDebugLib.h
  • UpdatePeiSaPolicyDebugPreMem() : PeiSaPolicyDebugLib.h
  • UpdatePeiSiPolicyDebug() : PeiSiPolicyDebugLib.h
  • UpdatePwm() : EcMiscLib.h
  • UpdateSaPolicyGopVbtPointer() : SaPolicyInitDxe.c , SaPolicyInitDxe.h
  • UpdateSmbiosTrustedDeviceSetupCapabilities() : TrustedDeviceSetup.h
  • UsbcGetUsbConnStatus() : EcTcssLib.h
  • UsbcIomReadyNotify() : EcTcssLib.h
  • USBCRetimerComplianceModePreMem() : PlatformInitAdvancedPreMem.c
  • UsbcRetimerCompliancePDMessage() : EcTcssLib.h
  • UsbcSxEntry() : EcTcssLib.h
  • UsbcSxExit() : EcTcssLib.h


AlderLake Platform Sample Code: File Members

- w -

  • WakeOnRTCS5() : PlatformInitAdvancedSmm.c , PlatformInitAdvancedSmm.h
  • WakeUpEc() : EcMiscLib.h
  • WdtAppPpiNotifyCallback() : PlatformInitAdvancedPreMem.c
  • WriteEcRam() : EcMiscLib.h
  • WritePssData() : PssLib.h
  • WriteRtcIndex() : PlatformInitAdvancedSmm.c


AlderLake Platform Sample Code: File Members

- d -

  • DEBUG_EVENT_HABDLER_PPI : DebugEventHandler.h

- e -

  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_ENABLE_I2C_BUS_CONFIGURATION : I2cBusConfigurationManagement.h
  • EFI_I2C_BUS_CONFIGURATION_MANAGEMENT_PROTOCOL : I2cBusConfigurationManagement.h
  • EFI_I2C_MASTER_BUS_FREQUENCY_SET : I2cMaster.h
  • EFI_I2C_MASTER_PROTOCOL : I2cMaster.h
  • EFI_I2C_MASTER_RESET : I2cMaster.h
  • EFI_I2C_MASTER_START_REQUEST : I2cMaster.h
  • EFI_RST_CONFIG_SPACE_ACCESS_GET_ADDRESS : RstConfigSpaceAccess.h
  • EFI_RST_CONFIG_SPACE_ACCESS_GET_BDF : RstConfigSpaceAccess.h
  • EFI_USBFN_IO_ABORT_TRANSFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_ALLOCATE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS : EfiUsbFnIo.h
  • EFI_USBFN_IO_CONFIGURE_ENABLE_ENDPOINTS_EX : EfiUsbFnIo.h
  • EFI_USBFN_IO_DETECT_PORT : EfiUsbFnIo.h
  • EFI_USBFN_IO_EVENTHANDLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_FREE_TRANSFER_BUFFER : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_DEVICE_INFO : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_MAXPACKET_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_MAXTRANSFER_SIZE : EfiUsbFnIo.h
  • EFI_USBFN_IO_GET_VENDOR_ID_PRODUCT_ID : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_POLICY : EfiUsbFnIo.h
  • EFI_USBFN_IO_SET_ENDPOINT_STALL_STATE : EfiUsbFnIo.h
  • EFI_USBFN_IO_START_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_STOP_CONTROLLER : EfiUsbFnIo.h
  • EFI_USBFN_IO_TRANSFER : EfiUsbFnIo.h

- f -

  • FW_UPDATE_MODE_ENTRY : RetimerCapsuleUpdate.h
  • FW_UPDATE_MODE_EXIT : RetimerCapsuleUpdate.h

- g -

  • GET_LIFE_CYCLE_STATE : LifeCycleState.h

- p -

  • PCH_GPIO_PAD : PlatformInfo.h

- r -

  • RESOURCE : SmmTxtResource.h

- s -

  • SMBIOS_TRUSTED_DEVICE_SETUP_CAPABILITIES : TrustedDeviceSetupMainProtocol.h
  • STM_MAP_ADDRESS_RANGE : SmmTxtResource.h

- t -

  • TcgCreateStruct : TcgCore.h
  • TcgParseStruct : TcgCore.h
  • TcgToken : TcgCore.h
  • TcgUid : Tcg.h
  • TCSS_RETIMER_INFO : RetimerCapsuleUpdate.h
  • TCSS_RETIMER_PROTOCOL : RetimerCapsuleUpdate.h
  • TRUSTED_DEVICE_SETUP_ENTRY : TrustedDeviceSetupMainProtocol.h
  • TXT_RESET_SYSTEM : TxtOneTouchOp.h


AlderLake Platform Sample Code: File Members

  • TcgResult : TcgCore.h
  • VARIABLE_STORE_STATUS : MultiPlatSupport.h


AlderLake Platform Sample Code: File Members

  • TcgResult_Failure : TcgCore.h
  • TcgResult_Failure_BufferTooSmall : TcgCore.h
  • TcgResult_Failure_EndBuffer : TcgCore.h
  • TcgResult_Failure_InvalidAction : TcgCore.h
  • TcgResult_Failure_InvalidType : TcgCore.h
  • TcgResult_Failure_NullPointer : TcgCore.h
  • TcgResult_Failure_ZeroSize : TcgCore.h
  • TcgResult_Success : TcgCore.h


AlderLake Platform Sample Code: File Members

- a -

  • ALIGNMENT : MultiPlatSupport.h

- b -

  • BOARD_INIT_PREMEM_ENTRY : PlatformPostCode.h

- c -

  • CPU_SETUP_REVISION : SetupVariable.h
  • CPU_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h

- d -

  • DEBUG_CONFIG_DATA_REVISION : Setup.h
  • DEBUG_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h
  • DEFAULT_BIOSVENDOR_CHARS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_BIOS : SmbiosPlatformInfoDefault.h
  • DEFAULT_BIOSVENDOR_CHARS_EXT_SYSTEM : SmbiosPlatformInfoDefault.h

- e -

  • EC_REAL_BAT1_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT1_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT1_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT1_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_CAPACITY : BaseEcFlashLib.h
  • EC_REAL_BAT2_REMAINING_PERCENT : BaseEcFlashLib.h
  • EC_REAL_BAT2_RESOLUTION_VOLTAGE : BaseEcFlashLib.h
  • EC_REAL_BAT2_STATUS : BaseEcFlashLib.h
  • EC_REAL_BAT_CHARGING_MASK : BaseEcFlashLib.h
  • EC_REAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_PRESENT_MASK : BaseEcFlashLib.h
  • EC_VIRTUAL_BAT_STATUS : BaseEcFlashLib.h
  • EFI_PASSWORD_STATUS_REVISION : Setup.h
  • EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_GUID : RstConfigSpaceAccess.h
  • EFI_RST_CONFIG_SPACE_ACCESS_PROTOCOL_VERSION : RstConfigSpaceAccess.h
  • EFI_USB_DEVICE_MODE_PROTOCOL_GUID : UsbDeviceModeProtocol.h
  • END_OF_RESOURCES : SmmTxtResource.h

- h -

  • HEADER_ALIGNMENT : MultiPlatSupport.h

- i -

  • ICC_SETUP_DATA_REVISION : IccSetupData.h

- m -

  • ME_SETUP_REVISION : SetupVariable.h

- o -

  • OS_PROFILE_REVISION : OemSetup.h

- p -

  • PCH_SETUP_REVISION : SetupVariable.h
  • PCI_BUS_SETUP_REVISION : PciBusSetup.h

- r -

  • RESET_GENERATOR_PORT : PlatformInitAdvancedPreMem.c
  • RICHTEK_VR_SECONDARY_ADDRESS : PlatformInitAdvancedPreMem.c

- s -

  • SA_SETUP_REVISION : SetupVariable.h
  • SECURE_BOOT_VARIABLE_REVISION : SecureBootSetup.h
  • SETUP_CPU_FEATURES_REVISION : OemSetup.h
  • SETUP_DATA_REVISION : SetupVariable.h
  • SETUP_VOLATILE_DATA_REVISION : OemSetup.h
  • SI_SETUP_REVISION : SetupVariable.h
  • SYSTEM_ACCESS_REVISION : Setup.h

- t -

  • TBT_SETUP_VOLATILE_DATA_REVISION : SetupVariable.h
  • TCG2_CONFIGURATION_REVISION : Tcg2ConfigNvData.h
  • TCG_SETUP_REVISION : TcgSetup.h
  • TCSS_RETIMER_PROTOCOL_GUID : RetimerCapsuleUpdate.h
  • TIME_OUT_INFO_REVISION : BootMaintSetup.h
  • TOTAL_SERIAL_PORT_INFO_REVISION : BootMaintSetup.h
  • TRUSTED_DEVICE_SETUP_BOOT_ENABLE : TrustedDeviceSetup.h
  • TRUSTED_DEVICE_SETUP_BOOT_LOCK : TrustedDeviceSetup.h
  • TRUSTED_DEVICE_SETUP_PROTOCOL_REVISION : TrustedDeviceSetupMainProtocol.h

- v -

  • VAR_ADDED : MultiPlatSupport.h
  • VAR_DELETED : MultiPlatSupport.h
  • VAR_HEADER_VALID_ONLY : MultiPlatSupport.h
  • VAR_IN_DELETED_TRANSITION : MultiPlatSupport.h
  • VARIABLE_DATA : MultiPlatSupport.h
  • VARIABLE_STORE_FORMATTED : MultiPlatSupport.h
  • VCCIN_AUX_SECONDARY_ADDRESS : PlatformInitAdvancedPreMem.c
Generated on Wed Jan 5 2022 01:27:34 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: PlatformInitAdvanced Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
PlatformInitAdvanced Directory Reference
Directory dependency graph for PlatformInitAdvanced:

Directories

Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Include -> Guid Relation

  • Intel
  • AlderLakePlatSamplePkg
  • Include

Include → Guid Relation

File in Intel/AlderLakePlatSamplePkg/Include | Includes file in Intel/AlderLakePlatSamplePkg/Include/Guid
Tcg2ConfigNvData.h | PttInstance.h
Tcg2ConfigNvData.h | PttPTPInstanceGuid.h
Tcg2ConfigNvData.h | Tcg2ConfigHii.h


AlderLake Platform Sample Code: PlatformInitAdvanced -> Include Relation

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced

PlatformInitAdvanced → Include Relation

File in Intel/AlderLakePlatSamplePkg/PlatformInitAdvanced | Includes file in Intel/AlderLakePlatSamplePkg/Include
PlatformInitAdvancedDxe / PlatformInitAdvancedDxe.c | Protocol / PlatformNvsArea.h
PlatformInitAdvancedDxe / PlatformInitAdvancedDxe.c | PlatformPostCode.h
PlatformInitAdvancedDxe / PlatformInitAdvancedDxe.h | SetupVariable.h
PlatformInitAdvancedDxe / PlatformInitAdvancedDxe.h | Library / BootGuardRevocationLib.h
PlatformInitAdvancedDxe / PlatformInitAdvancedDxe.h | OemSetup.h
PlatformInitAdvancedDxe / SaPlatformInitAdvancedDxe.c | PlatformNvRamHookLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | SetupVariable.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Guid / SystemNvDataGuid.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Library / EcLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Library / EcMiscLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | PlatformPostCode.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Library / EcTcssLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Guid / CrashLog.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | AttemptUsbFirst.h
PlatformInitAdvancedPei / PlatformInitAdvancedPostMem.c | Library / PeiGetFvInfoLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Library / EcTcssLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Guid / TcoWdtHob.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | PlatformNvRamHookLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Library / EcMiscLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Library / PeiWdtAppLib.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | SetupVariable.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | FastBootFunctionEnabledHob.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | FastBootExceptionInfoHob.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | CustomOptionControl.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Setup.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | PlatformPostCode.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | FirwmareConfigurations.h
PlatformInitAdvancedPei / PlatformInitAdvancedPreMem.c | Library / PeiPlatformLib.h
PlatformInitAdvancedSmm / EcSmi.c | Library / EcLib.h
PlatformInitAdvancedSmm / EcSmi.c | Library / EcMiscLib.h
PlatformInitAdvancedSmm / EcSmi.c | Library / EcCommands.h
PlatformInitAdvancedSmm / EcSmi.h | Library / EcLib.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.c | OemSetup.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.c | PlatformPostCode.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Platform.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | SetupVariable.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Protocol / EcAccess.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | PlatformBoardType.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Library / EcMiscLib.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Library / DxeSmmAcpiCustomLib.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Protocol / PlatformNvsArea.h
PlatformInitAdvancedSmm / PlatformInitAdvancedSmm.h | Library / EcTcssLib.h
PolicyInitAdvancedDxe / AmtPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe / AmtPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
PolicyInitAdvancedDxe / AmtPolicyInitDxe.h | Library / DxeAmtPolicyUpdateLib.h
PolicyInitAdvancedDxe / CpuPolicyInitDxe.h | Library / DxeCpuPolicyUpdateLib.h
PolicyInitAdvancedDxe / GopPolicyInitDxe.h | SetupVariable.h
PolicyInitAdvancedDxe / GopPolicyInitDxe.h | Library / EcMiscLib.h
PolicyInitAdvancedDxe / MePolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe / MePolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
PolicyInitAdvancedDxe / MePolicyInitDxe.h | Library / DxeMePolicyUpdateLib.h
PolicyInitAdvancedDxe / PchPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe / PchPolicyInitDxe.h | Library / DxePchPolicyUpdateLib.h
PolicyInitAdvancedDxe / PolicyInitAdvancedDxe.h | SetupVariable.h
PolicyInitAdvancedDxe / SaPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe / SaPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
PolicyInitAdvancedDxe / SaPolicyInitDxe.h | Library / DxeSaPolicyUpdateLib.h
PolicyInitAdvancedDxe / TbtPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe / TbtPolicyInitDxe.h | Library / DxeTbtPolicyUpdateLib.h


AlderLake Platform Sample Code: PolicyInitAdvancedDxe -> Include Relation

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe

PolicyInitAdvancedDxe → Include Relation

File in Intel/AlderLakePlatSamplePkg/PlatformInitAdvanced/PolicyInitAdvancedDxe | Includes file in Intel/AlderLakePlatSamplePkg/Include
AmtPolicyInitDxe.h | Library / DxeAmtPolicyUpdateLib.h
AmtPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
AmtPolicyInitDxe.h | FirwmareConfigurations.h
CpuPolicyInitDxe.h | Library / DxeCpuPolicyUpdateLib.h
GopPolicyInitDxe.h | Library / EcMiscLib.h
GopPolicyInitDxe.h | SetupVariable.h
MePolicyInitDxe.h | Library / DxeMePolicyUpdateLib.h
MePolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
MePolicyInitDxe.h | FirwmareConfigurations.h
PchPolicyInitDxe.h | Library / DxePchPolicyUpdateLib.h
PchPolicyInitDxe.h | FirwmareConfigurations.h
PolicyInitAdvancedDxe.h | SetupVariable.h
SaPolicyInitDxe.h | Library / DxePolicyBoardConfigLib.h
SaPolicyInitDxe.h | Library / DxeSaPolicyUpdateLib.h
SaPolicyInitDxe.h | FirwmareConfigurations.h
TbtPolicyInitDxe.h | Library / DxeTbtPolicyUpdateLib.h
TbtPolicyInitDxe.h | FirwmareConfigurations.h


AlderLake Platform Sample Code: Library -> Protocol Relation

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library

Library → Protocol Relation

File in Intel/AlderLakePlatSamplePkg/Include/Library | Includes file in Intel/AlderLakePlatSamplePkg/Include/Protocol
DxeSmmAcpiCustomLib.h | PlatformNvsArea.h
UsbDeviceLib.h | EfiUsbFnIo.h


AlderLake Platform Sample Code: Protocol -> Library Relation

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol

Protocol → Library Relation

File in Intel/AlderLakePlatSamplePkg/Include/Protocol | Includes file in Intel/AlderLakePlatSamplePkg/Include/Library
RetimerCapsuleUpdate.h | EcTcssLib.h
UsbDeviceModeProtocol.h | UsbDeviceLib.h


AlderLake Platform Sample Code: PlatformInitAdvancedSmm -> Include Relation

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm

PlatformInitAdvancedSmm → Include Relation

File in Intel/AlderLakePlatSamplePkg/PlatformInitAdvanced/PlatformInitAdvancedSmm | Includes file in Intel/AlderLakePlatSamplePkg/Include
EcSmi.c | Library / EcCommands.h
EcSmi.c | Library / EcLib.h
EcSmi.c | Library / EcMiscLib.h
EcSmi.h | Library / EcLib.h
PlatformInitAdvancedSmm.c | OemSetup.h
PlatformInitAdvancedSmm.c | PlatformPostCode.h
PlatformInitAdvancedSmm.h | Library / DxeSmmAcpiCustomLib.h
PlatformInitAdvancedSmm.h | Protocol / EcAccess.h
PlatformInitAdvancedSmm.h | Library / EcMiscLib.h
PlatformInitAdvancedSmm.h | Library / EcTcssLib.h
PlatformInitAdvancedSmm.h | Platform.h
PlatformInitAdvancedSmm.h | PlatformBoardType.h
PlatformInitAdvancedSmm.h | Protocol / PlatformNvsArea.h
PlatformInitAdvancedSmm.h | SetupVariable.h


AlderLake Platform Sample Code: PlatformInitAdvancedDxe -> Include Relation

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe

PlatformInitAdvancedDxe → Include Relation

File in Intel/AlderLakePlatSamplePkg/PlatformInitAdvanced/PlatformInitAdvancedDxe | Includes file in Intel/AlderLakePlatSamplePkg/Include
PlatformInitAdvancedDxe.c | Protocol / PlatformNvsArea.h
PlatformInitAdvancedDxe.c | PlatformPostCode.h
PlatformInitAdvancedDxe.h | Library / BootGuardRevocationLib.h
PlatformInitAdvancedDxe.h | OemSetup.h
PlatformInitAdvancedDxe.h | SetupVariable.h
SaPlatformInitAdvancedDxe.c | PlatformNvRamHookLib.h


AlderLake Platform Sample Code: PlatformInitAdvancedPei -> Include Relation

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei

PlatformInitAdvancedPei → Include Relation

File in Intel/AlderLakePlatSamplePkg/PlatformInitAdvanced/PlatformInitAdvancedPei | Includes file in Intel/AlderLakePlatSamplePkg/Include
PlatformInitAdvancedPostMem.c | AttemptUsbFirst.h
PlatformInitAdvancedPostMem.c | Guid / CrashLog.h
PlatformInitAdvancedPostMem.c | Library / EcLib.h
PlatformInitAdvancedPostMem.c | Library / EcMiscLib.h
PlatformInitAdvancedPostMem.c | Library / EcTcssLib.h
PlatformInitAdvancedPostMem.c | Library / PeiGetFvInfoLib.h
PlatformInitAdvancedPostMem.c | PlatformPostCode.h
PlatformInitAdvancedPostMem.c | SetupVariable.h
PlatformInitAdvancedPostMem.c | Guid / SystemNvDataGuid.h
PlatformInitAdvancedPreMem.c | CustomOptionControl.h
PlatformInitAdvancedPreMem.c | Library / EcMiscLib.h
PlatformInitAdvancedPreMem.c | Library / EcTcssLib.h
PlatformInitAdvancedPreMem.c | FastBootExceptionInfoHob.h
PlatformInitAdvancedPreMem.c | FastBootFunctionEnabledHob.h
PlatformInitAdvancedPreMem.c | FirwmareConfigurations.h
PlatformInitAdvancedPreMem.c | Library / PeiPlatformLib.h
PlatformInitAdvancedPreMem.c | Library / PeiWdtAppLib.h
PlatformInitAdvancedPreMem.c | PlatformNvRamHookLib.h
PlatformInitAdvancedPreMem.c | PlatformPostCode.h
PlatformInitAdvancedPreMem.c | Setup.h
PlatformInitAdvancedPreMem.c | SetupVariable.h
PlatformInitAdvancedPreMem.c | Guid / TcoWdtHob.h


AlderLake Platform Sample Code: Library Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | BaseEcFlashLib.h [code]
file | BasePlatformVariableLib.h [code]
file | BootGuardRevocationLib.h [code]
Header file for Boot Guard revocation notification.
file | DxeAcpiGnvsInitLib.h [code]
Acpi Gnvs Init Library header file.
file | DxeAmtPolicyUpdateLib.h [code]
file | DxeCpuPolicyUpdateLib.h [code]
file | DxeFirmwareVersionInfoLib.h [code]
Private data structures.
file | DxeMePolicyUpdateLib.h [code]
file | DxeOpromPatchLib.h [code]
file | DxePchPolicyUpdateLib.h [code]
file | DxePlatformBootManagerLib.h [code]
Header file for DxePlatformBootManagerLib.
file | DxePolicyBoardConfigLib.h [code]
Header file for the DxePolicyBoardConfig Library.
file | DxeSaPolicyUpdateLib.h [code]
file | DxeSmmAcpiCustomLib.h [code]
This header file provides platform specific definitions used by other modules for platform specific initialization.
file | DxeTbtPolicyUpdateLib.h [code]
file | EcCommands.h [code]
file | EcHwLib.h [code]
EC hardware library functions and definitions.
file | EcLib.h [code]
EC library functions and definitions.
file | EcMiscLib.h [code]
EC miscellaneous library functions.
file | EcTcssLib.h [code]
EC TCSS library functions.
file | HidI2cPlatformSupportLib.h [code]
Support for IO expander TCA6424.
file | MultiPlatSupportLib.h [code]
file | PcieWorkaroundOnPolicy.h [code]
Header file for the PCIE Workaround on Policy.
file | PdtUpdateLib.h [code]
file | PeiBootGuardEventLogLib.h [code]
This file contains functions for creating TPM Event Log.
file | PeiCpuPolicyDebugLib.h [code]
SampleCode header file of the library for Intel CPU PEI Debug Policy initialization.
file | PeiGetFvInfoLib.h [code]
Header file for PeiGetFvInfoLib.
file | PeiPchPolicyDebugLib.h [code]
SampleCode header file of the library for Intel PCH PEI Debug Policy initialization.
file | PeiPlatformLib.h [code]
file | PeiPlatformRecoveryLib.h [code]
This library provides platform recovery module.
file | PeiReadWriteVariableLib.h [code]
file | PeiSaPolicyDebugLib.h [code]
SampleCode header file of the library for Intel SA PEI Debug Policy initialization.
file | PeiSiPolicyDebugLib.h [code]
SampleCode header file of the library for Intel SI PEI Debug Policy initialization.
file | PeiSubRegionLib.h [code]
Header file for PeiSubRegionLib.
file | PeiSwbpeLib.h [code]
file | PeiTsnFvLib.h [code]
Header file for PeiTsnFvFile.
file | PeiWdtAppLib.h [code]
PEI WDT App library definitions.
file | PlatformInitLib.h [code]
Function prototype of PlatformInitLib.
file | PlatformSecureLib.h [code]
Provides a secure platform-specific method to detect physically present user.
file | PlatformTelemetryLib.h [code]
Save LastUpdateTime to variable by different ImageTypeID.
file | PssLib.h [code]
PSS(Processor Secured Storage) Chip Operation Library Header.
file | SecurePreMemoryDataLoadLib.h [code]
PEI Secure Pre-Memory Data Load Library.
file | SerialIoUartDebugHelperLib.h [code]
file | SerialIoUartDebugPropertyLib.h [code]
file | SerialPortParameterLib.h [code]
This library class provides capability to get/set serial port baud rate.
file | SpiFlashCommon.h [code]
The header file includes the common header files, defines internal structure and functions used by SpiFlashCommonLib.
file | Tcg.h [code]
TCG defined values and structures used by the Tcg Core library.
file | Tcg2PhysicalPresenceLib.h [code]
Ihis library is intended to be used by BDS modules.
file | TcgCore.h [code]
Public API for the Tcg Core library to perform the lowest level TCG data encoding.
file | TcgUtil.h [code]
Provides TCG high-level API to perform common TCG actions on a TCG data packet.
file | UsbDeviceLib.h [code]
Header file for USBFN library definition.


AlderLake Platform Sample Code: DoxygenInternalOnly Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • DoxygenInternalOnly
DoxygenInternalOnly Directory Reference
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20


AlderLake Platform Sample Code: Guid Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Guid
Guid Directory Reference

Files

file | AcpiVariable.h [code]
file | CrashLog.h [code]
file | PlatformGlobalVariable.h [code]
GUID for Platform (NVRAM) Variables.
file | PttInstance.h [code]
GUID definition for the PTT device instance.
file | PttPTPInstanceGuid.h [code]
GUID definition for the PTT device instance.
file | S3MemoryVariable.h [code]
file | SystemNvDataGuid.h [code]
file | Tcg2ConfigHii.h [code]
GUIDs used as HII FormSet and HII Package list GUID in Tcg2Config driver.
file | TcoWdtHob.h [code]
file | TxtOneTouch.h [code]
This file contains definitions required for One-Touch function.
file | WifiConnectionManagerConfigHii.h [code]
GUIDs used as HII FormSet and HII Package list GUID in WiFi Connection Manager.


AlderLake Platform Sample Code: Protocol Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | DxePolicyUpdateProtocol.h [code]
file | EcAccess.h [code]
file | EfiUsbFnIo.h [code]
EFI USB function IO Protocol This protocol supports Usb Function IO API.
file | FastBootException.h [code]
file | I2cBusConfigurationManagement.h [code]
I2C bus configuration management interface.
file | I2cMaster.h [code]
I2C Master interface.
file | LifeCycleState.h [code]
file | PlatformNvsArea.h [code]
This file defines the Platform NVS Area Protocol.
file | RetimerCapsuleUpdate.h [code]
RetimerCapsuleUpdate driver definitions.
file | RstConfigSpaceAccess.h [code]
RST config space access protocol for bios.
file | RstLegacyBootDisabledProtocol.h [code]
RST legacy boot disabled protocol.
file | SmmCpuSaveState.h [code]
This file declares the SMM CPU Save State protocol, which provides the processor save-state information for IA-32 and Itanium processors.
file | SmmTxtResource.h [code]
This file contains function definitions that can determine the TXT resource of a platform during SMM and perform certain specific platform tasks that are required for TXT during SMM.
file | SystemMonitor.h [code]
file | TPSxFwUpdateWrapperProtocol.h [code]
Protocol definitions for TPSxFwUpdateWrapper.
file | TrustedDeviceSetupMainProtocol.h [code]
APIs for Intel Trusted Device Setup Main Protocol.
file | TxtOneTouchOp.h [code]
Txt specific PPI operation definition.
file | UsbDeviceModeProtocol.h [code]
Header file for definition of USBFN device mode protocol.


AlderLake Platform Sample Code: Intel Directory Reference

  • Intel
Intel Directory Reference
Directory dependency graph for Intel:


AlderLake Platform Sample Code: PlatformInitAdvancedPei Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedPei
PlatformInitAdvancedPei Directory Reference
Directory dependency graph for PlatformInitAdvancedPei:

Files

file | PlatformInitAdvancedPostMem.c [code]
Source code file for Platform Init PEI module.
file | PlatformInitAdvancedPreMem.c [code]
Source code file for Platform Init Advanced Pre-Memory PEI module.


AlderLake Platform Sample Code: PolicyInitAdvancedDxe Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PolicyInitAdvancedDxe
PolicyInitAdvancedDxe Directory Reference
Directory dependency graph for PolicyInitAdvancedDxe:

Files

file | AmtPolicyInitDxe.c [code]
This file is SampleCode for Intel AMT DXE Policy initialization.
file | AmtPolicyInitDxe.h [code]
Header file for the AmtPolicyInitDxe Driver.
file | CpuPolicyInitDxe.c [code]
This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
file | CpuPolicyInitDxe.h [code]
Header file for the SiliconPolicyInitDxe Driver.
file | GopPolicyInitDxe.c [code]
This file initialises and Installs GopPolicy Protocol.
file | GopPolicyInitDxe.h [code]
Header file for the GopPolicyInitDxe Driver.
file | MePolicyInitDxe.c [code]
This file is SampleCode for Intel ME DXE Policy initialization.
file | MePolicyInitDxe.h [code]
Header file for the MePolicyInitDxe Driver.
file | PchPolicyInitDxe.c [code]
This file is SampleCode for PCH DXE Policy initialization.
file | PchPolicyInitDxe.h [code]
Header file for the PchPolicyInitDxe Driver.
file | PolicyInitAdvancedDxe.c [code]
This file is a wrapper for Platform Policy Advanced driver.
file | PolicyInitAdvancedDxe.h [code]
Header file for the PolicyInitAdvancedDxe Driver.
file | SaPolicyInitDxe.c [code]
This file is SampleCode for SA DXE Policy initialization.
file | SaPolicyInitDxe.h [code]
Header file for the SaPolicyInitDxe Driver.
file | SiliconPolicyInitDxe.c [code]
This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
file | SiliconPolicyInitDxe.h [code]
Header file for the SiliconPolicyInitDxe Driver.
file | TbtPolicyInitDxe.c [code]
This file is SampleCode for TBT DXE Policy initialization.
file | TbtPolicyInitDxe.h [code]
Header file for the TbtPolicyInitDxe Driver.


AlderLake Platform Sample Code: Ppi Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • Ppi
Ppi Directory Reference

Files

file | DebugEventHandler.h [code]
file | OverClockPpi.h [code]
file | RstConfigPpi.h [code]
This file contains RST related PPI definitions.
file | VtdEnableDmaBufferPpi.h [code]
The definition for the VTd Enable DMA Buffer PPI.


AlderLake Platform Sample Code: PlatformInitAdvancedSmm Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedSmm
PlatformInitAdvancedSmm Directory Reference
Directory dependency graph for PlatformInitAdvancedSmm:

Files

file | EcSmi.c [code]
This file processes hotkey dispatch and callback event.
file | EcSmi.h [code]
Header file for EC SMI handlers.
file | PcieDockSmi.c [code]
file | PcieDockSmi.h [code]
file | PlatformInitAdvancedSmm.c [code]
Platform Advanced SMM Driver.
file | PlatformInitAdvancedSmm.h [code]
Header file for the Platform Advanced SMM Driver.
file | Ps2IoTrapHandler.c [code]


AlderLake Platform Sample Code: AlderLakePlatSamplePkg Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
AlderLakePlatSamplePkg Directory Reference
Directory dependency graph for AlderLakePlatSamplePkg:

Directories

directory | DoxygenInternalOnly
directory | PlatformInitAdvanced


AlderLake Platform Sample Code: PlatformInitAdvancedDxe Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • PlatformInitAdvanced
  • PlatformInitAdvancedDxe
PlatformInitAdvancedDxe Directory Reference
Directory dependency graph for PlatformInitAdvancedDxe:

Files

file | GfxInt15Interface.c [code]
This is a driver to produce Int15 hook.
file | PlatformInitAdvancedDxe.c [code]
Source code file for the Platform Init Advanced DXE module.
file | PlatformInitAdvancedDxe.h [code]
Header file for Platform Init Advanced Dxe Driver.
file | SaPlatformInitAdvancedDxe.c [code]
Source code file for the SA Platform Init DXE module.


AlderLake Platform Sample Code: MultiPlatform Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
  • MultiPlatform
MultiPlatform Directory Reference

Files

file | PlatformOpRomTable.h [code]
file | PlatformOptionRomTable_Default.h [code]


AlderLake Platform Sample Code: Include Directory Reference

  • Intel
  • AlderLakePlatSamplePkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | AttemptUsbFirst.h [code]
file | BootMaintSetup.h [code]
file | BootStateLib.h [code]
file | CastroCovePmicNvm.h [code]
This file is for CastroCove Pmic Nvm update.
file | ChassisIntrDetHob.h [code]
Chassis Intrusion Detection Status Structures.
file | CnvVariables.h [code]
Declaration of Intel Connectivity Variables Structures and guids for WLAN, BT and WIGIG.
file | CommonDefinitions.h [code]
file | CustomOptionControl.h [code]
file | DimmInfo.h [code]
This header file provides Dimm info definitions used by other modules for dimm info presentation.
file | Efi.h [code]
file | FastBootDataDef.h [code]
file | FastBootExceptionInfoHob.h [code]
file | FastBootFunctionEnabledHob.h [code]
This file defines the HOB data structure to indicate that Fast Boot function is enabled in PEI phase, which may be used by some DXE phase drivers as well.
file | FirwmareConfigurations.h [code]
This header file provides definitions of firmware configuration.
file | HstiFeatureBit_1_1a.h [code]
This file contains various definitions for IHV HSTI implementation including STATUS string definitions.
file | HstiIbvFeatureBit.h [code]
This file contains various definitions for IHV HSTI implementation including error string definitions.
file | IccSetupData.h [code]
file | MultiPlatSupport.h [code]
file | OemSetup.h [code]
OEM Specific Setup Variables and Structures.
file | PciBusSetup.h [code]
file | Platform.h [code]
This header file provides platform specific definitions used by other modules for platform specific initialization.
file | PlatformBoardType.h [code]
BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.
file | PlatformClock.h [code]
file | PlatformConfigurationChangeVariable.h [code]
Platform configuration change variable definitions.
file | PlatformInfo.h [code]
GUID used for Platform Info Data entries in the HOB list.
file | PlatformNvRamHookLib.h [code]
Platform Nv RAM Hook Library Header Definition which will oprovide the absraction to the different NVRAM types like eMMC, ECRAM, secondary SPI part etc.
file | PlatformPostCode.h [code]
file | PolicyUpdateMacro.h [code]
Macros for platform to update different types of policy.
file | RstFeaturesVariable.h [code]
RST Features variable definition.
file | SecureBootSetup.h [code]
file | Setup.h [code]
file | SetupConfiguration.h [code]
Default platform setup configuration settings.
file | SetupVariable.h [code]
file | SioRegs.h [code]
file | SmbiosPlatformInfoDefault.h [code]
This file contains Default data for Platform SMBIOS tables.
file | SmbiosPlatformInfoDefinition.h [code]
This file contains definition for Platform SMBIOS Info.
file | Tcg2ConfigNvData.h [code]
Header file for NV data structure definition.
file | TcgSetup.h [code]
file | TrustedDeviceSetup.h [code]
Intel Trusted Device Setup library services.
file | WdtAppVariable.h [code]
Definition of non-volatile EFI variable used by both PEI and DXE parts of WdtApp.
file | WheaSetup.h [code]


AlderLake Platform Sample Code: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labelled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labelled with the template parameters of the instance.


AlderLake Platform Sample Code: Related Pages

Related Pages
Here is a list of all related documentation pages:
Todo List
Generated on Wed Jan 5 2022 01:27:33 for AlderLake Platform Sample Code by doxygen 1.8.20