AlderLake Firmware Support Package (FSP): Deprecated List

AlderLake Firmware Support Package (FSP)
Deprecated List
Member AMT_PEI_CONFIG::ManageabilityMode
: Manageability Mode sync with Mebx, 0: Disabled; 1: AMT
Member AMT_PEI_CONFIG::RemoteAssistance
: Remote Assistance is enabled if platform is provisioned. 0: Disable, 1: Enable
Member AMT_PEI_CONFIG::AmtKvmEnabled
: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable
Member AMT_DXE_CONFIG::MebxDebugMsg
: OEMFlag Bit 14: Enable OEM debug menu in MEBx. 0: Disable; 1: Enable
Member AMT_DXE_CONFIG::HideUnConfigureMeConfirm
: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. 0: Don't hide; 1: Hide
Member AMT_DXE_CONFIG::AmtbxHotkeyPressed
: OEMFlag Bit 1: Enable automatic MEBx hotkey press. 0: Disable; 1: Enable
Member AMT_DXE_CONFIG::AmtbxSelectionScreen
Member AMT_DXE_CONFIG::CiraTimeout
Member AMT_DXE_CONFIG::CpuReplacementTimeout
Member AMT_DXE_CONFIG::MebxNonUiTextMode
: Resolution for non-UI text mode. 0: Auto; 1: 80x25; 2: 100x31
Member AMT_DXE_CONFIG::MebxUiTextMode
: Resolution for UI text mode. 0: Auto; 1: 80x25; 2: 100x31
Member AMT_DXE_CONFIG::MebxGraphicsMode
: Resolution for graphics mode. 0: Auto; 1: 640x480; 2: 800x600; 3: 1024x768
Member AMT_DXE_CONFIG::OemResolutionSettingsRsvd
: Reserved for future use & Config block alignment
Member CpuPcieEqDefault
since revision 3. Behaves as PchPcieEqHardware.
Member FIVR_EXT_RAIL_CONFIG::IccMax
THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD VR rail Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .
Member GRAPHICS_DXE_CONFIG::IgdDvmtMemSize
IGD DVMT Memory Size: 1=128MB, 2=256MB, 3=MAX
Member ME_PEI_CONFIG::Heci3Enabled
Member SI_CONFIG::CsmFlag
.
Member CPU_POWER_MGMT_VR_CONFIG::TdcTimeWindow [MAX_NUM_VRS]
. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default
Member SMBIOS_TABLE_TYPE131::MebxVersion
Member gAmtSaveMebxProtocolGuid
: please use gMebxConfigProtocolGuid instead
Member EnumMebx
: MEBx Version
Member CPU_CONFIG::Avx3Disable
Enable or Disable Avx3.
  • 1: Disable
  • 0: Enable
Member CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount
due to core active number limitaion.
Member CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset
no longer used.
Member CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver Enabling it will load the driver upon ACPI device with HID = INT3510. 0: Disable; 1: Enable;
Member CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
no longer used
Member CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
no longer used
Member CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
Move to premem phase.
Member CPU_SECURITY_PREMEM_CONFIG::EnableSgx
due to Non-POR feature.
Class SGX_INFO
due to Non-POR feature SGX Information
Member _CPU_INFO_PROTOCOL::SgxInfo
due to Non-POR feature.
Member SA_MISC_PEI_PREMEM_CONFIG::IedSize
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Todo List

Todo List
Member CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit
: The following enums have to be replaced with policies.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class List

Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
C _AMT_POLICY_PROTOCOL | AMT DXE Policy This protocol is initialized by Policy driver
C _AMT_READY_TO_BOOT_PROTOCOL | AMT Ready to Boot Protocol The interface functions are for Performing all Management Engine task
C _AMT_SAVE_MEBX_PROTOCOL | AMT Save Mebx Protocol The interface function is to save MEBX setting
C _BIOS_OS_DATA_REGION | TXT HEAP Memory: BIOS OS Data region definitions
C _BIOSGUARD_PROTOCOL | This protocol provides all the services required for flash writes/erases via BIOS Guard BIOS Guard Module can only be launched from SMM
C _CONFIG_BLOCK | Config Block
C _CONFIG_BLOCK_HEADER | Config Block Header
C _CONFIG_BLOCK_TABLE_STRUCT | Config Block Table Header
C _CPU_INFO_PROTOCOL | This protocol provides information about the common features available in this CPU
C _DXE_ITBT_CONFIG | ITBT DXE configuration Revision 1:
C _DXE_ITBT_GENERIC_CONFIG | ITBT Generic Data Structure to be used cross to RP and controller in DXE phase
C _EFI_SMM_VARIABLE_PROTOCOL | EFI SMM Variable Protocol is intended for use as a means to store data in the EFI SMM environment
C _FSP_TEMP_RAM_EXIT_PPI | This PPI provides function to program MTRR values
C _GOP_COMPONENT_NAME2_PROTOCOL | GOP Component protocol This protocol will be installed by GOP driver and can be used to retrieve GOP information
C _HEAP_BIOS_SPEC_VER_ELEMENT | TXT HEAP Memory: BIOS spec version element
C _HEAP_BIOSACM_ELEMENT | TXT HEAP Memory: BIOS ACM element
C _HEAP_EXT_DATA_ELEMENT | TXT HEAP Memory: Extended data elements
C _HECI_ACCESS_ | PPI/PROTOCOL for ME-UEFI FW HECI Access
C _HECI_CONTROL_ | EFI protocol for ME-UEFI FW communication over HECI
C _HECI_PPI | HECI PPI The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem in PEI phase
C _HECI_PROTOCOL | HECI protocol provided for DXE phase The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem
C _IO_TRAP_EX_DISPATCH_PROTOCOL | Interface structure for the IO trap Extention protocol
C _ITBT_GENERIC_CONFIG | ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
C _ITBT_ROOTPORT_CONFIG | ITBT RootPort Data Structure
C _ME_JHI_PROTOCOL | JHI protocol provided for DXE phase The interface functions are for JHI APIs to transfer data between host and Intel ME subsystem
C _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL | Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service is called
C _ME_POLICY_PROTOCOL | ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information
C _MEBX_CONFIG_PROTOCOL | AMT Mebx Config Protocol The interface function is to set/get MEBX settings
C _MEBX_DISPLAY_PROTOCOL | MEBx Display Protocol The interface functions are used for I/O operations related to screen
C _MEMORY_DXE_CONFIG | The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map
C _OC_MAILBOX_FULL | Consolidated OC mailbox command structure containing both data and interface information
C _OC_MAILBOX_INTERFACE | Expanded Overclocking Mailbox interface defintion, contains command id/completion code, input parameters and the run/busy bit
C _PCH_ACPI_SMI_DISPATCH_PROTOCOL | Interface structure for PCH ACPI SMIs Dispatch Protocol The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs
C _PCH_ESPI_SMI_DISPATCH_PROTOCOL | Interface structure for PCH eSPI SMIs Dispatch Protocol The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs
C _PCH_PCIE_SMI_DISPATCH_PROTOCOL | Interface structure for PCH PCIE SMIs Dispatch Protocol The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs
C _PCH_PREMEM_POLICY | PCH Policy PPI All PCH config block change history will be listed here
C _PCH_SMI_DISPATCH_PROTOCOL | Interface structure for PCH specific SMIs Dispatch Protocol The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs
C _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL | Interface structure for the SMM IO trap pause and resume protocol This protocol provides the functions to runtime control the IoTrap SMI enabled/disable
C _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL | Interface structure for the SMM PERIODIC TIMER pause and resume protocol This protocol provides the functions to runtime control the SM periodic timer enabled/disable
C _PCH_SPI_PROTOCOL | These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host Controller Interface
C _PCH_TCO_SMI_DISPATCH_PROTOCOL | Interface structure for PCH TCO SMIs Dispatch Protocol The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs
C _PCODE_MAILBOX_FULL | Consolidated Pcode mailbox command structure containing both data and interface information
C _PCODE_MAILBOX_INTERFACE | Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit
C _PEI_ITBT_CONFIG | ITBT PEI configuration Revision 1:
C _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _PEI_SI_DEFAULT_POLICY_INIT_PPI | This PPI provides function to install default silicon policy
C _PEI_SMM_CONTROL_PPI | PEI SMM Control PPI is used to initiate SMI/PMI activations
C _PLATFORM_ME_HOOK_PROTOCOL | Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM before perform reset command through Heci
C _PPM_CUSTOM_CTDP_TABLE | PPM Custom ConfigTdp Settings
C _SI_POLICY_STRUCT | SI Policy PPI All SI config block change history will be listed here
C _SI_PREMEM_POLICY_STRUCT | SI Policy PPI in Pre-Mem All SI config block change history will be listed here
C _THC_PROTOCOL | Protocol used by Thc Once installed allows to detect if it is already running on given device Also used for obtaining Thc context
C _TXT_INFO_DATA | TXT Info data
C _TXT_INFO_HOB | HOB to save TXT Info data
C _WDT_PROTOCOL | These protocols and PPI allow a platform module to perform watch dog timer operations through the Intel PCH LPC Host Controller Interface
C ADR_CONFIG | ADR Configuration Revision 1: - Initial version
C ADR_SOURCE_ENABLE | ADR Source Enable
C ALERT_STANDARD_FORMAT_PROTOCOL | Intel specific definitions end
C AMT_DXE_CONFIG | AMT Dxe Configuration Structure
C AMT_GET_ACTIVE_LAN_INTERFACE | Get Active LAN Interface Request Structure
C AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER | Get Active LAN Interface Union Buffer
C AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE | Get Active LAN Interface Response Structure
C AMT_PEI_CONFIG | AMT Pei Configuration Structure
C AMT_PET_QUEUE_HOB | Queue Hob
C AMT_QUERY_KVM | Query KVM Request Structure
C AMT_QUERY_KVM_BUFFER | Query KVM Union Buffer
C AMT_QUERY_KVM_RESPONSE | Query KVM Response Structure
C AMT_SCREEN_RESOLUTION | Get GFX UI Info/Fragment
C AMT_SET_ACTIVE_LAN_INTERFACE | Set Active LAN Interface Request Structure
C AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER | Set Active LAN Interface Union Buffer
C AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE | Set Active LAN Interface Response Structure
C AMT_SET_MAC_PASSTHROUGH_BUFFER | Set MAC Passthrough Buffer
C AMT_SET_MAC_PASSTHROUGH_RESPONSE | Set MAC Passthrough
C ARB_SVN_COMMIT | HW Anti-Rollback (ARB) Security Version Number Commit
C ARB_SVN_GET_INFO | HW Anti-Rollback (ARB) Security Version Number Get Info
C ASF_BOOT_OPTIONS | Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message
C ASF_DATA_HUB_MAP | Data Hub of ASF Progress Status
C ASF_FRAMEWORK_MESSAGE | ASF Framework Message
C ASF_MESSAGE | ASF Message
C ASF_MESSAGE_HEADER | Abstract ASF message header
C ASF_PROFILE_MESSAGE_HEADER | ASF Message header with profile name char array as data
C ASF_START_WDT | Start Watchdog Timer Message Structure
C ASF_STOP_WDT | Stop Watchdog Timer Message Structure
C BCLK_CONFIG | BCLK configuration
C BDAT_ACCESS_PROTOCOL | BDAT access protocol - For accessing some data generated by MRC or PCIe modules
C BDAT_SCHEMA_LIST_HOB | Not strictly part of the BDAT spec
C BGPDT | BIOS Guard Platform Data Table (BGPDT) Provides platform specific data required by BIOS Guard Module
C BGUP | BIOS Guard update package definition for BIOS SMM Initiated runtime calls
C BGUP_HEADER | BIOS Guard update Package Header
C BIOS_GUARD_CONFIG | BIOS Guard Configuration Structure
C BIOSGUARD_HOB | HOB used to pass data through every phase of BIOS Guard Bios
C BIOSGUARD_LOG | BIOS Guard Log The logging facility is used to communicate detailed information regarding the execution of a BIOS Guard script from the SMI handler which invoked the BIOS Guard module itself
C BIST_HOB_DATA | Store BIST data for BSP
C BOOT_GUARD_INFO | Information related to Boot Guard Configuration
C BOOT_OPTION_CAPS_STRUC | Boot Options/System Firmware Capabilities Bit Mask
C BUP_MPHY_READ_FROM_MPHY | MPHY group defines
C CACHE_DESCRIPTOR_INFO | Cache descriptor information
C CBM_RESET_ACK | Reset request MKHI ack message
C CBM_RESET_REQ | Reset request MKHI message
C CBM_RESET_REQ_DATA | Reset request message data
C CFG_COMPLETE_CONFIGURATION_REQUEST | Complete Configuration
C CFG_GET_FQDN_REQUEST | Get/Set Fqdn
C CFG_GET_IDLE_TIMEOUT_REQUEST | Get/Set Idle Timeout Request
C CFG_GET_INTERFACE_VERSION_RESPONSE | Get Interface Version
C CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE | Get OptIn Change Availability
C CFG_GET_PRIVACY_LEVEL_REQUEST | Get AMT Privacy Level
C CFG_GET_REDIRECTION_STATE_REQUEST | Get Redirection Features State
C CFG_GET_ZTC_ENABLED_STATUS_REQUEST | Get/Set ZTC Enabled Status
C CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST | Open/Close/Query User Initiatied Connection for CIRA
C CFG_SET_KVM_ENABLED_REQUEST | Get/Set KVM State
C CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST | Set Sol/Storage Redirection
C CFG_STOP_CONFIGURATION_REQUEST | Stop/Start Configuration
C CFG_UNPROVISION_REQUEST | Unprovision
C CHIPSET_INIT_INFO | Revision 1: - Initial version
C CLEAR_BOOT_OPTIONS | Clear Boot Options Message Structure
C CNVI_CONFIG | The CNVI_CONFIG block describes the expected configuration of the CNVi IP
C CNVI_PIN_MUX | CNVi signals pin muxing settings
C CNVI_PREMEM_CONFIG | The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP
C COMMIT_FILES | Commit Files
C CORE_BIOS_DONE | Core Bios Done - both GEN and MCA group definition
C CPU_CONFIG | CPU Configuration Structure
C CPU_CONFIG_LIB_PREMEM_CONFIG | CPU Config Library PreMemory Configuration Structure
C CPU_DATA_HOB | CPU Data Hob
C CPU_DMI_EQ_PARAM | Represent lane specific Dmi Gen3 equalization parameters
C CPU_DMI_HOB | The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi
C CPU_DMI_PREMEM_CONFIG | The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI
C CPU_INFO | Processor information
C CPU_PCIE_CONFIG | The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version
C CPU_PCIE_EQ_LANE_PARAM | Represent lane specific PCIe Gen3 equalization parameters
C CPU_PCIE_GPIO_INFO | CPU PCIe GPIO Data Structure
C CPU_PCIE_HOB | The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
C CPU_PCIE_PWR_OPT | PCIE Power Optimizer config
C CPU_PCIE_ROOT_PORT_CONFIG | The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port
C CPU_PCIE_RP_PREMEM_CONFIG | CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version
C CPU_PCIE_RTD3_GPIO | CPU PCIE RTD3 GPIO Data Structure
C CPU_POWER_MGMT_BASIC_CONFIG | CPU Power Management Basic Configuration Structure
C CPU_POWER_MGMT_CUSTOM_CONFIG | CPU Power Management Custom Configuration Structure
C CPU_POWER_MGMT_PSYS_CONFIG | CPU Power Management Psys(Platform) Configuration Structure
C CPU_POWER_MGMT_TEST_CONFIG | CPU Power Management Test Configuration Structure
C CPU_POWER_MGMT_VR_CONFIG | CPU Power Management VR Configuration Structure
C CPU_SECURITY_PREMEM_CONFIG | CPU Security PreMemory Configuration Structure
C CPU_TEST_CONFIG | CPU Test Configuration Structure
C CPU_TRACE_HUB_PREMEM_CONFIG | CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version
C CPU_TXT_PREMEM_CONFIG | CPU TXT PreMemory Configuration Structure
C DDI_CONFIGURATION | This structure configures the Native GPIOs for DDI port per VBT settings
C DIMM_INFO | Memory SMBIOS & OC Memory Data Hob
C DMI_HW_WIDTH_CONTROL | This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design
C DNX_REQ_CLEAR | DNX Request Clear
C DNX_REQ_SET | DNX Request Set
C DPIN_PREMEM_CONFIG | This configuration block describes DPIN settings
C DXE_CPU_POLICY_PROTOCOL | The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor in the DXE phase
C DXE_SI_POLICY_PROTOCOL | The protocol allows the platform code to publish a set of configuration information that the Silicon drivers will use to configure the processor in the DXE phase
C FIPS_VERSION | Get FIPS Mode
C FIVR_EXT_RAIL_CONFIG | Structure for V1p05/Vnn VR rail configuration
C FIVR_VCCIN_AUX_CONFIG | Structure for VCCIN_AUX voltage rail configuration
C FSP_ERROR_INFO_HOB | FSP Error Information Block
C FSPM_ARCH_CONFIG_PPI | This PPI provides FSP-M Arch Config PPI
C FUSA_CONFIG | The FUSA_CONFIG block describes the expected configuration of Functional Safety
C FVI_DATA | The string number for ComponentName and VersionString is always calculated dynamically
C FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA | FW Feature Shipment Time State Override
C FWSTS_SET_RECORD | FWSTS element structure
C FWSTS_SMBIOS_RECORD | FWSTS SMBIOS Record Structure
C GBE_CONFIG | PCH intergrated GBE controller configuration settings
C GEN_SEND_CPU_BRAND | Send CPU brand class fuse
C GET_BOOT_OPTIONS | Get Boot Options Request Structure
C GET_BOOT_OPTIONS_BUFFER | Get Boot Options Union Buffer
C GET_BOOT_OPTIONS_RESPONSE | Get Boot Options Response Structure
C GET_FEATURE_STATE_REQUEST | Get/Set Feature State
C GET_FEATURE_SUPPORT_REQUEST | Common Features Definitions
C GET_FW_VER | Get FW Version
C GET_IMR_CMD_REQ_DATA | Get IMR size message
C GET_MEASURED_BOOT | Get CSME Measured Boot
C GET_OS_CONTROL_FEATURE_STATE_REQUEST | Get/Set Os Control Feature State
C GET_PLATFORM_ID_REQUEST | Platform Id Feature Defintions
C GET_REFURBISH_COUNTER_REQUEST | Get Refurbish Counter
C GET_RPMC_STATUS | Get RPMC Status
C GET_RSE_PASSWORD | Get RSE Password Request Structure
C GET_RSE_PASSWORD_BUFFER | Get RSE Password Union Buffer
C GET_RSE_PASSWORD_RESPONSE | Get RSE Password Response Structure
C GET_WIFI_CLIENT_CERT_BUFFER | ASF buffer for Wifi profile client certificate
C GET_WIFI_CLIENT_KEY_BUFFER | ASF buffer for Wifi profile client key
C GET_WIFI_PROFILE_DATA_BUFFER | ASF buffer for Wifi profile data
C GET_WIFI_PROFILE_NAME_BUFFER | ASF buffer for Wifi profile name
C GET_WIFI_PROFILE_NAME_RESPONSE | Get Wifi profile name response from ASF
C GNA_CONFIG | GNA config block for configuring GNA
C GOP_POLICY_PROTOCOL | System Agent Graphics Output Protocol (GOP) - Policy Protocol Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization All functions in this protocol should be initialized by platform code basing on platform implementation
C GPIO_CONFIG | GPIO configuration structure used for pin programming
C GPIO_DXE_CONFIG | This structure contains the DXE policies which are related to GPIO device
C GRAPHICS_DXE_CONFIG | This configuration block is to configure IGD related variables used in DXE
C GRAPHICS_PEI_CONFIG | This configuration block is to configure IGD related variables used in PostMem PEI
C GRAPHICS_PEI_PREMEM_CONFIG | This Configuration block is to configure GT related PreMem data/variables
C HDA_LINK_DMIC | HD Audio DMIC Interface Policies
C HDA_LINK_HDA | HD Audio Link Policies
C HDA_LINK_SNDW | HD Audio SNDW Interface Policies
C HDA_LINK_SSP | HD Audio SSP Interface Policies
C HDA_VERB_TABLE_HEADER | Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands
C HDAUDIO_CONFIG | This structure contains the policies which are related to HD Audio device (cAVS)
C HDAUDIO_DXE_CONFIG | This structure contains the DXE policies which are related to HD Audio device (cAVS)
C HDAUDIO_PREMEM_CONFIG | This structure contains the premem policies which are related to HD Audio device (cAVS)
C HECI_ASF_PUSH_PROGRESS_CODE | ASF Push Progress Code
C HECI_CONTROL_STATUS_REGISTER | Register definitions
C HECI_FW_STS3_REGISTER | HFSTS3, offset 60h
C HECI_FW_STS4_REGISTER | HFSTS4, offset 64h
C HECI_FW_STS5_REGISTER | HFSTS5, offset 68h
C HECI_FW_STS6_REGISTER | HFSTS6, offset 6Ch
C HECI_FWS_REGISTER | HFSTS1, offset 40h
C HECI_GS_SHDW_REGISTER | HFSTS2, offset 48h
C HG_INFO | HG Info HOB
C HMRFPO_ENABLE | HMRFPO ENABLE
C HMRFPO_GET_STATUS | HMRFPO GET STATUS
C HMRFPO_LOCK | HMRFPO LOCK
C HOB_SAGV_INFO | This data structure contains SAGV config values that are considered output by the MRC
C HOB_SAGV_TIMING_OUT | This data structure contains per-SaGv timing values that are considered output by the MRC
C HOB_USAGE_DATA_HOB | Hob Usage Data Hob
C HOST_BRIDGE_PEI_CONFIG | This configuration block describes HostBridge settings in Post-Mem
C HOST_BRIDGE_PREMEM_CONFIG | This configuration block describes HostBridge settings in PreMem
C HR_NOTIFICATION_CMD | PM group defines
C HSIO_PARAMETERS | This structure describes USB3 Port N configuration parameters
C HWA_DATA | HWA AppId
C HWA_MESSAGE_HEADER | Definitions for Hardware Asset Header
C HWA_PUSH_TABLES_MSG | Asset Update Table Message
C HYBRID_GRAPHICS_CONFIG | This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port
C HYBRID_STORAGE_CONFIG | The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device
C I2C_PIN_MUX | I2C signals pin muxing settings
C ICC_CLOCK_MODE | Used for the Clock Mode parameter of Get/Set Clock Settings
C ICC_CLOCK_SETTINGS | Structure for Clock Settings
C ICC_CLOCK_SETTINGS_CURRENT_FLAGS | Used for the CURRENT FLAGS parameter of Get/Set Clock Settings
C ICC_CLOCK_SETTINGS_FLAGS | Get/Set Clock Settings
C ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS | Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings
C ICC_GET_CLK_CAPABILITIES_MESSAGE | Get/Set ICC Clock Capabilities
C ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ | Get Soft Strap Config
C ICC_GETSET_CLOCK_SETTINGS_REQRSP | Combined Request and Response structure for Get/Set Clock Settings
C ICC_MESSAGE_RESP_DATA | ICC group defines
C ICC_OVERRIDE_SOFT_STRAP_CMD_REQ | This is only a template
C IEH_CONFIG | The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler
C IGD_OPREGION_PROTOCOL | IGD OpRegion Protocol
C INVOCATION_CODE_BITS | MKHI_CBM_GROUP Definitions
C IO_TRAP_EX_REGISTER_CONTEXT | IO Trap Ex context structure containing information about the IO trap Ex event that should invoke the handler
C IOM_AUX_ORI_PAD_CONFIG | The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin
C IOM_INTERFACE_CONFIG | The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC
C IPU_DATA_HOB | This HOB is used to pass IPU related information to DXE phase
C IPU_PREMEM_CONFIG | IPU PreMem configuration Revision 1:
C ISH_CONFIG | The ISH_CONFIG block describes Integrated Sensor Hub device
C ISH_GP | Struct contains GPIO pins assigned and signal settings of GP
C ISH_GPIO_CONFIG | ISH GPIO settings
C ISH_I2C | Struct contains GPIO pins assigned and signal settings of I2C
C ISH_I2C_PIN_CONFIG | I2C signals settings
C ISH_I3C_CONFIG | The ISH_I3C_CONFIG block describes I3C in ISH device
C ISH_PREMEM_CONFIG | Premem Policy for Integrated Sensor Hub device
C ISH_SPI | Struct contains GPIO pins assigned and signal settings of SPI
C ISH_SPI_PIN_CONFIG | SPI signals settings
C ISH_UART | Struct contains GPIO pins assigned and signal settings of UART
C ISH_UART_PIN_CONFIG | UART signals settings
C ITBT_POLICY_PROTOCOL | ITBT DXE Policy
C MBP_FW_VERSION_NAME | MBP items
C MBP_HEADER | Common MBP types
C MBP_IFWI_DNX_REQUEST | MBP IFWI DNX request structure containing IFWI Dnx request data
C MBP_ITEM_HEADER | MBP items header
C MBP_MPHY_DATA | ICC AppId
C MBP_SENSITIVE_PPI | MBP SENSITIVE PPI Contains MBP sensitive data which should not be passed on to DXE as an HOB
C ME_BIOS_PAYLOAD | ME BIOS Payload structure containing insensitive data only
C ME_BIOS_PAYLOAD_SENSITIVE | All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below structure only
C ME_CAP | ME Platform Capabilities
C ME_DXE_CONFIG | ME Dxe Configuration Structure
C ME_PEI_CONFIG | ME Pei Post-Memory Configuration Structure
C ME_PEI_PREMEM_CONFIG | ME Pei Pre-Memory Configuration Structure
C ME_SMBIOS_TABLES_UPDATE_PROTOCOL | ME SMBIOS Tables update protocol The interface functions are to update SMBIOS type 130 (in case of AMT) and 131
C MEBX_PROTOCOL | MEBX protocol The interface for invoking MEBX binary
C MEFWCAPS_SKU | Get Firmware Capability
C MEI_DEV_STRING | MEI Device Structure
C MEM_INFO_PROTOCOL | Memory information Protocol definition
C MEMORY_CONFIG_NO_CRC | Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection
C MEMORY_CONFIGURATION | Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection
C MEMORY_INFO_DATA | Memory information Data Structure
C MEMORY_PLATFORM_DATA | Memory Platform Data Hob
C MEMORY_TIMING | Memory timing Structure
C MG_IMR_STATUS | Structure for MG image status from IMR
C MKHI_MESSAGE_HEADER | MKHI host message header
C MSR_TURBO_RATIO_LIMIT_REGISTER | MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT
C MUX_GPIO_PARAM | SD GPIO settings
C OVERCLOCKING_PREMEM_CONFIG | Overclocking Configuration Structure
C PCH_DCI_PREMEM_CONFIG | The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
C PCH_DEVICE_INTERRUPT_CONFIG | The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device
C PCH_DMI_CONFIG | The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI
C PCH_DMI_EQ_PARAM | Lane specific Dmi Gen3, Gen4 equalization parameters
C PCH_DMI_HOB | The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization
C PCH_ESPI_CONFIG | This structure contains the policies which are related to ESPI
C PCH_FIVR_CONFIG | The PCH_FIVR_CONFIG block describes FIVR settings
C PCH_FLASH_PROTECTION_CONFIG | The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled
C PCH_GENERAL_CONFIG | PCH General Configuration Revision 1: - Initial version
C PCH_GENERAL_PREMEM_CONFIG | PCH General Pre-Memory Configuration Revision 1: - Initial version
C PCH_HSIO_CONFIG | The PCH_HSIO_CONFIG block provides HSIO message related settings
C PCH_HSIO_PCIE_LANE_CONFIG | The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
C PCH_HSIO_PCIE_PREMEM_CONFIG | The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
C PCH_HSIO_PREMEM_CONFIG | The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings
C PCH_HSIO_SATA_PORT_LANE | The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
C PCH_HSIO_SATA_PREMEM_CONFIG | The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller
C PCH_INFO_HOB | This structure is used to provide the information of PCH controller
C PCH_INTERRUPT_CONFIG | The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH
C PCH_IOAPIC_CONFIG | The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE
C PCH_LOCK_DOWN_CONFIG | The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement
C PCH_LPC_GEN_IO_RANGE | Structure of LPC general IO range register It contains base address, address mask, and enable status
C PCH_LPC_GEN_IO_RANGE_LIST | Structure of LPC general IO range register list It lists all LPC general IO ran registers supported by PCH
C PCH_LPC_PREMEM_CONFIG | This structure contains the policies which are related to LPC
C PCH_MEMORY_THROTTLING | This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board)
C PCH_P2SB_CONFIG | This structure contains the policies which are related to P2SB device
C PCH_PCIE_CLOCK | PCH_PCIE_CLOCK describes PCIe source clock generated by PCH
C PCH_PCIE_CONFIG | The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:
C PCH_PCIE_ROOT_PORT_CONFIG | The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port
C PCH_PCIE_RP_PREMEM_CONFIG | The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:
C PCH_PM_CONFIG | The PCH_PM_CONFIG block describes expected miscellaneous power management settings
C PCH_POLICY_PROTOCOL | PCH DXE Policy
C PCH_SATA_PORT_CONFIG | This structure configures the features, property, and capability for each SATA port
C PCH_SMBUS_PREMEM_CONFIG | The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform
C PCH_TRACE_HUB_PREMEM_CONFIG | PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version
C PCH_WAKE_CONFIG | This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events
C PCH_WDT_PREMEM_CONFIG | This policy clears status bits and disable watchdog, then lock the WDT registers
C PCIE_COMMON_CONFIG | PCIe Common Config
C PCIE_DEVICE_OVERRIDE | PCIe device table entry entry
C PCIE_DXE_CONFIG | The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control for PEG ASPM
C PCIE_EQ_PARAM | Represent lane specific PCIe Gen3 equalization parameters
C PCIE_GPIO | SA GPIO Data Structure
C PCIE_IMR_CONFIG | PCIe IMR Config
C PCIE_LINK_EQ_PLATFORM_SETTINGS | PCIe Link EQ Platform Settings
C PCIE_PEI_CONFIG | PCI Express and DMI controller configuration - PostMem
C PCIE_PEI_PREMEM_CONFIG | PCI Express and DMI controller configuration
C PCIE_PEI_PREMEM_CONFIG_GEN3 | PCI Express and DMI controller configuration
C PCIE_PREMEM_CONFIG | PCIe Pre-Memory Configuration Revision 1: - Initial version
C PCIE_RP_DXE_CONFIG | The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
C PCIE_RTD3_GPIO | SA PCIE RTD3 GPIO Data Structure
C PEG_GPIO_DATA | SA Board PEG GPIO Info
C PET_ALERT | Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert
C PMC_GLOBAL_RESET_MASK | Description of Global Reset Trigger/Event Mask register
C PMC_INTERFACE_CONFIG | The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
C PMC_LPM_S0IX_SUB_STATE_EN | Low Power Mode Enable config
C PORT_INFO | PCIe device detection information
C PPM_CUSTOM_RATIO_TABLE | This structure is used to describe the custom processor ratio table desired by the platform
C PROTECTED_RANGE | Protected Flash Range
C PSF_CONFIG | The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric
C RC_VERSION | This structure contains the RC version details for FVI SMBIOS records
C READ_FILE | Read File, Ver3 API only
C READ_FILE_EX | Read File Ex
C REPORT_BIOS_STATUS | Report BIOS Status
C REQUEST_OWNERSHIP | Request Device Ownership
C RST_CONFIG | Rapid Storage Technology settings
C RST_HARDWARE_REMAPPED_STORAGE_CONFIG | This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required
C RTC_CONFIG | The RTC_CONFIG block describes the expected configuration of RTC configuration
C SA_ADDRESS_DECODE | SA memory address decode
C SA_DATA_HOB | System Agent Data Hob
C SA_FUNCTION_CALLS | Function calls into the SA
C SA_GPIO_INFO_PCIE | SA GPIO Data Structure
C SA_MEMORY_DQDQS_MAPPING | DqDqs Mapping
C SA_MEMORY_FUNCTIONS | Function calls into the MRC
C SA_MEMORY_RCOMP | Rcomp Policies
C SA_MISC_PEI_CONFIG | This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem
C SA_MISC_PEI_PREMEM_CONFIG | This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc
C SA_PEG_DATA | PEG data definition This structure can be saved in non-volatile memory to be re-used in the following boot
C SA_PEG_HOB | System Agent PEG NVS Hob
C SA_POLICY_PROTOCOL | SA DXE Policy
C SA_XDCI_IRQ_INT_CONFIG | The SA XDCI INT Pin and IRQ number
C SATA_CONFIG | The SATA_CONFIG block describes the expected configuration of the SATA controllers
C SATA_THERMAL_THROTTLING | This structure lists PCH supported SATA thermal throttling register setting for customization
C SCS_SD_DLL | This structre holds the DLL configuration register values that will be programmed by RC if EnableCustomDlls field is set to TRUE
C SERIAL_IO_CONFIG | The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
C SERIAL_IO_I2C_CONFIG | Serial IO I2C Controller Configuration
C SERIAL_IO_SPI_CONFIG | The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
C SERIAL_IO_UART_ATTRIBUTES | UART Settings
C SERIAL_IO_UART_CONFIG | Serial IO UART Controller Configuration
C SET_FILE | Set File, Ver3 API only
C SET_FILE_EX | Set File Ex
C SET_ME_RESET_HALT | Set Manufacturing ME Reset and Halt messages
C SET_MEASURED_BOOT | Set CSME Measured Boot
C SFAM_DATA | Signed Flash map descriptor definition
C SGX_INFO |
C SI_CONFIG | The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SI_PREMEM_CONFIG | The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware
C SMBIOS_CACHE_INFO | SMBIOS Cache Info HOB Structure
C SMBIOS_PROCESSOR_INFO | SMBIOS Processor Info HOB Structure
C SMBIOS_TABLE_TYPE130 | This is definition for SMBIOS Oem data type 130
C SMBIOS_TABLE_TYPE131 | This is definition for SMBIOS Oem data type 131
C SMM_RESOURCE_CONFIG_PROTOCOL | The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure IO ports & MSR registers access with in SMM
C SMRAM_CPU_INFO | This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA
C SPD_DATA_BUFFER | SPD Data Buffer
C SPD_OFFSET_TABLE | SPD Offset Table
C SPECIAL_COMMAND_CAPS_STRUC | Special Commands Bit Mask
C SPI_CONFIG | Basic configuration for option features of PCH SPI Flash controller
C SPI_PIN_MUX | SPI signals pin muxing settings
C SPS_RING3_EXCEPTION_HANDLER | The protocol allows to handle OEM Ring-3 Exceptions
C SVID_SID_VALUE | Subsystem Vendor ID / Subsystem ID
C SYSTEM_CAPS_STRUC | System Capabilities Bit Mask
C TBT_IMR_STATUS | Structure for Tbt firmware status from IMR
C TCSS_DATA | TCSS data definition
C TCSS_DATA_HOB | TCSS Data Hob
C TCSS_DATA_SSID_HOB | TCSS SSID Data Hob
C TCSS_DEVEN_PEI_PREMEM_CONFIG | The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS
C TCSS_IOM_ORI_OVERRIDE | The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS
C TCSS_IOM_PEI_CONFIG | The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS
C TCSS_MISC_PEI_CONFIG | The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS
C TCSS_MISC_PEI_PREMEM_CONFIG | The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS
C TCSS_PCIE_PEI_POLICY | TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS
C TCSS_PCIE_PORT_POLICY | The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS
C TCSS_PEI_CONFIG | The TCSS_PEI_CONFIG block describes TCSS settings for SA
C TCSS_PEI_PREMEM_CONFIG | This configuration block describes TCSS settings
C TCSS_USBTC_PEI_PERMEM_CONFIG | The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS
C TELEMETRY_PEI_CONFIG | This configuration block describes Telemetry settings in PostMem
C TELEMETRY_PEI_PREMEM_CONFIG | This configuration block describes Telemetry settings in PreMem
C THC_CONFIG | THC_CONFIG block provides the configurations forTouch Host Controllers
C THC_HID_OVER_SPI | THC Hid Over SPI mode related settings
C THC_PORT | Port Configuration structure required for each Port that THC might use
C THERMAL_CONFIG | The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block
C THERMAL_THROTTLE_LEVELS | This structure lists PCH supported throttling register setting for custimization
C TPM_STATE | Set ACM TPM
C TRACE_HUB_CONFIG | TRACE_HUB_CONFIG block describes TraceHub settings
C TRACEHUB_DATA_HOB | Trace Hub Data Hob
C TS_GPIO_PIN_SETTING | This structure configures PCH memory throttling thermal sensor GPIO PIN settings
C TSN_CONFIG | The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
C UART_PIN_MUX | UART signals pin muxing settings
C UPDATE_OEM_PLATFORM_ID_REQUEST | Update OEM Platform Id
C UPID_MESSAGE_HEADER | UPID (Unique Platform Id) Message Header
C USB2_PHY_CONFIG | This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
C USB2_PHY_PARAMETERS | This structure configures per USB2 AFE settings
C USB2_PORT_CONFIG | This structure configures per USB2.0 port settings like enabling and overcurrent protection
C USB3_HSIO_CONFIG | Structure for holding USB3 tuning parameters
C USB3_PORT_CONFIG | This structure configures per USB3.x port settings like enabling and overcurrent protection
C USB_CONFIG | This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field
C VMD_PEI_CONFIG | This configuration block is to configure VMD related variables used in PostMem PEI
C VTD_CONFIG | The data elements should be initialized by a Platform Module
C VTD_DXE_CONFIG | The data structure is for VT-d driver initialization in DXE Revision 1:
C WIFI_8021X_CLIENT_CERT | Get Wifi profile specific 8021X client certificate from ASF
C WIFI_8021X_CLIENT_KEY | Get Wifi profile specific 8021X client key from ASF
C WIFI_PROFILE_DATA | Get Wifi profile data response from ASF
C XDCI_CONFIG | The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _AMT_POLICY_PROTOCOL Struct Reference

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_AMT_POLICY_PROTOCOL Struct Reference

AMT DXE Policy This protocol is initialized by Policy driver. More...

#include <AmtPolicy.h>

Collaboration diagram for _AMT_POLICY_PROTOCOL:
[legend]

Detailed Description

AMT DXE Policy This protocol is initialized by Policy driver.

Other modules can locate this protocol to retrieve Intel AMT related setup options setting

Revision 1:

  • Initial version.

Definition at line 64 of file AmtPolicy.h.

The documentation for this struct was generated from the following file:
  • AmtPolicy.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_AMT_POLICY_PROTOCOL Member List

This is the complete list of members for _AMT_POLICY_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _AMT_READY_TO_BOOT_PROTOCOL Struct Reference

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_AMT_READY_TO_BOOT_PROTOCOL Struct Reference

AMT Ready to Boot Protocol The interface functions are for Performing all Management Engine task. More...

#include <AmtReadyToBoot.h>

Public Attributes

UINT8 Revision
Revision for the protocol structure.
AMT_READY_TO_BOOT_PROTOCOL_SIGNAL Signal
Performs all Management Engine task.

Detailed Description

AMT Ready to Boot Protocol The interface functions are for Performing all Management Engine task.

Definition at line 62 of file AmtReadyToBoot.h.

The documentation for this struct was generated from the following file:
  • AmtReadyToBoot.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_AMT_READY_TO_BOOT_PROTOCOL Member List

This is the complete list of members for _AMT_READY_TO_BOOT_PROTOCOL, including all inherited members.

Revision | _AMT_READY_TO_BOOT_PROTOCOL
Signal | _AMT_READY_TO_BOOT_PROTOCOL
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AlderLake Firmware Support Package (FSP): _AMT_SAVE_MEBX_PROTOCOL Struct Reference

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_AMT_SAVE_MEBX_PROTOCOL Struct Reference

AMT Save Mebx Protocol The interface function is to save MEBX setting. More...

#include <AmtSaveMebxProtocol.h>

Detailed Description

AMT Save Mebx Protocol The interface function is to save MEBX setting.

It is platform vendor's responsibility to implement the function instance.

Definition at line 68 of file AmtSaveMebxProtocol.h.

The documentation for this struct was generated from the following file:
  • AmtSaveMebxProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_AMT_SAVE_MEBX_PROTOCOL Member List

This is the complete list of members for _AMT_SAVE_MEBX_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _BIOS_OS_DATA_REGION Struct Reference

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_BIOS_OS_DATA_REGION Struct Reference

TXT HEAP Memory: BIOS OS Data region definitions. More...

#include <Txt.h>

Collaboration diagram for _BIOS_OS_DATA_REGION:
[legend]

Public Attributes

UINT32 | Version
Version number of the BIOS to OS data.
UINT32 | BiosSinitSize
This field indicates the size of the SINIT AC module stored in system firmware. More...
EFI_PHYSICAL_ADDRESS | LcpPdBase
Physical base address of the Platform Default Launch Control Policy structure. More...
UINT64 | LcpPdSize
Size of the Launch Control Policy Platform Default Policy Data. More...
UINT32 | NumOfLogicalProcessors
The total number of logical processors in the system. The minimum value in this register must be at least 0x01.
UINT64 | Flags
BIOS provided info for SINIT consumption.
HEAP_EXT_DATA_ELEMENT ExtData
Array/list of extended data element structures.

Detailed Description

TXT HEAP Memory: BIOS OS Data region definitions.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide

Definition at line 150 of file Txt.h.

Member Data Documentation

◆ BiosSinitSize

UINT32 _BIOS_OS_DATA_REGION::BiosSinitSize

This field indicates the size of the SINIT AC module stored in system firmware.

A value of 0 indicates the system firmware is not providing a SINIT module for OS use.

Definition at line 156 of file Txt.h.

◆ LcpPdBase

EFI_PHYSICAL_ADDRESS _BIOS_OS_DATA_REGION::LcpPdBase

Physical base address of the Platform Default Launch Control Policy structure.

If the Platform Default Policy does not require additional data this field should be set to 0x00 and will be ignored.

Definition at line 162 of file Txt.h.

◆ LcpPdSize

UINT64 _BIOS_OS_DATA_REGION::LcpPdSize

Size of the Launch Control Policy Platform Default Policy Data.

If the Platform Default Policy does not require additional data this field should be set to 0x00 and will be ignored.

Definition at line 168 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_BIOS_OS_DATA_REGION Member List

This is the complete list of members for _BIOS_OS_DATA_REGION, including all inherited members.

BiosSinitSize | _BIOS_OS_DATA_REGION
ExtData | _BIOS_OS_DATA_REGION
Flags | _BIOS_OS_DATA_REGION
LcpPdBase | _BIOS_OS_DATA_REGION
LcpPdSize | _BIOS_OS_DATA_REGION
NumOfLogicalProcessors | _BIOS_OS_DATA_REGION
Version | _BIOS_OS_DATA_REGION
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _BIOSGUARD_PROTOCOL Struct Reference

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_BIOSGUARD_PROTOCOL Struct Reference

This protocol provides all the services required for flash writes/erases via BIOS Guard BIOS Guard Module can only be launched from SMM. More...

#include <BiosGuard.h>

Collaboration diagram for _BIOSGUARD_PROTOCOL:
[legend]

Public Attributes

BIOSGUARD_WRITE Write
Invoked to fill up BIOS Guard script buffer for flash writes.
BIOSGUARD_ERASE Erase
Invoked to fill up BIOS Guard script buffer for flash erases.
BIOSGUARD_EXECUTE Execute
Will trigger invocation of BIOS Guard module.

Detailed Description

This protocol provides all the services required for flash writes/erases via BIOS Guard BIOS Guard Module can only be launched from SMM.

Warning
All flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL for installing BIOS Guard Protocol. Prior to BIOS Guard SMM Protocol being installed there should be no writes/erases to flash.

Definition at line 122 of file Protocol/BiosGuard.h.

The documentation for this struct was generated from the following file:
  • Protocol/BiosGuard.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_BIOSGUARD_PROTOCOL Member List

This is the complete list of members for _BIOSGUARD_PROTOCOL, including all inherited members.

Erase | _BIOSGUARD_PROTOCOL
Execute | _BIOSGUARD_PROTOCOL
Write | _BIOSGUARD_PROTOCOL
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AlderLake Firmware Support Package (FSP): _CONFIG_BLOCK Struct Reference

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_CONFIG_BLOCK Struct Reference

Config Block. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.

Detailed Description

Config Block.

Definition at line 40 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_CONFIG_BLOCK Member List

This is the complete list of members for _CONFIG_BLOCK, including all inherited members.

Header _CONFIG_BLOCK
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _CONFIG_BLOCK_HEADER Struct Reference

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_CONFIG_BLOCK_HEADER Struct Reference

Config Block Header. More...

#include <ConfigBlock.h>

Public Attributes

EFI_HOB_GUID_TYPE | GuidHob
Offset 0-23 GUID extension HOB header.
UINT8 | Revision
Offset 24 Revision of this config block.
UINT8 | Attributes
Offset 25 The main revision for config block.
UINT8 | Reserved [2]
Offset 26-27 Reserved for future use.

Detailed Description

Config Block Header.

Definition at line 30 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


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_CONFIG_BLOCK_HEADER Member List

This is the complete list of members for _CONFIG_BLOCK_HEADER, including all inherited members.

Attributes | _CONFIG_BLOCK_HEADER
GuidHob | _CONFIG_BLOCK_HEADER
Reserved | _CONFIG_BLOCK_HEADER
Revision | _CONFIG_BLOCK_HEADER
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _CONFIG_BLOCK_TABLE_STRUCT Struct Reference

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_CONFIG_BLOCK_TABLE_STRUCT Struct Reference

Config Block Table Header. More...

#include <ConfigBlock.h>

Collaboration diagram for _CONFIG_BLOCK_TABLE_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
UINT8 | Rsvd0 [2]
Offset 28-29 Reserved for future use.
UINT16 | NumberOfBlocks
Offset 30-31 Number of config blocks (N)
UINT32 | AvailableSize
Offset 32-35 Current config block table size.

Detailed Description

Config Block Table Header.

Definition at line 50 of file ConfigBlock.h.

The documentation for this struct was generated from the following file:
  • ConfigBlock.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_CONFIG_BLOCK_TABLE_STRUCT Member List

This is the complete list of members for _CONFIG_BLOCK_TABLE_STRUCT, including all inherited members.

AvailableSize | _CONFIG_BLOCK_TABLE_STRUCT
Header | _CONFIG_BLOCK_TABLE_STRUCT
NumberOfBlocks | _CONFIG_BLOCK_TABLE_STRUCT
Rsvd0 | _CONFIG_BLOCK_TABLE_STRUCT
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _CPU_INFO_PROTOCOL Struct Reference

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_CPU_INFO_PROTOCOL Struct Reference

This protocol provides information about the common features available in this CPU. More...

#include <CpuInfo.h>

Collaboration diagram for _CPU_INFO_PROTOCOL:
[legend]

Public Attributes

UINT8 | Revision
Revision for the protocol structure. More...
UINT64 | CpuCommonFeatures
CPU Supported Feature. More...
CPU_INFO * CpuInfo
Processor Basic Information Contains Big Core and Small Core.
SMRAM_CPU_INFO * SmramCpuInfo
SMRAM CPU Information.
SGX_INFO * SgxInfo

Detailed Description

This protocol provides information about the common features available in this CPU.

Definition at line 140 of file CpuInfo.h.

Member Data Documentation

◆ CpuCommonFeatures

UINT64 _CPU_INFO_PROTOCOL::CpuCommonFeatures

CPU Supported Feature.

  • BIT0: If set then processor supports TXT.
  • BIT1: If set then processor supports virtual mode extensions.
  • BIT2: If set then processor supports execute disable bit.
  • BIT3: If set then processor supports DCA.
  • BIT4: If set then processor supports X2APIC.
  • BIT5: If set then processor supports Advanced Encryption Standard.
  • BIT6: If set then processor supports hyperthreading.
  • BIT7: If set then processor supports debug interface.
  • BIT8: If set then processor supports debug interface lock.
  • BIT9: If set then processor supports processor trace.
  • BIT10: If Set then processor supports supports HDC.

Definition at line 176 of file CpuInfo.h.

◆ Revision

UINT8 _CPU_INFO_PROTOCOL::Revision

Revision for the protocol structure.

Any backwards compatible changes to this protocol will result in an update in the revision number. Major changes will require publication of a new protocol

Revision 1:

  • Initial version Revision 2:
  • Add number of enabled threads to CPU_INFO. Revision 3:
  • Extend CPU_INFO to support Small Core and Big Core. Revision 4:
  • Add Per Core PState OC supported New PerCoreRatioOverride and PerCoreRatio Revision 5:
  • Add Ring VF point support. New RingVfPointCount and Ring per VF Point Ratio. Revision 6:
  • Deprecated SGx

Definition at line 161 of file CpuInfo.h.

◆ SgxInfo

SGX_INFO* _CPU_INFO_PROTOCOL::SgxInfo
Deprecated:
due to Non-POR feature.

Definition at line 179 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_CPU_INFO_PROTOCOL Member List

This is the complete list of members for _CPU_INFO_PROTOCOL, including all inherited members.

CpuCommonFeatures | _CPU_INFO_PROTOCOL
CpuInfo | _CPU_INFO_PROTOCOL
Revision | _CPU_INFO_PROTOCOL
SgxInfo | _CPU_INFO_PROTOCOL
SmramCpuInfo | _CPU_INFO_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _DXE_ITBT_CONFIG Struct Reference

Public Attributes | List of all members
_DXE_ITBT_CONFIG Struct Reference

ITBT DXE configuration
Revision 1: More...

#include <DxeITbtConfig.h>

Collaboration diagram for _DXE_ITBT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TBT_COMMON_CONFIG | TbtCommonConfig
Tbt Common Information.
DXE_ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Generic Information.
TBT_RESOURCE_CONFIG | ITbtResourceConfig [MAX_ITBT_PCIE_PORT]
iTbt Resource Configuration

Detailed Description

ITBT DXE configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtVproDockSupport in DXE_ITBT_GENERIC_CONFIG structure.

Definition at line 63 of file DxeITbtConfig.h.

The documentation for this struct was generated from the following file:
  • DxeITbtConfig.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_DXE_ITBT_CONFIG Member List

This is the complete list of members for _DXE_ITBT_CONFIG, including all inherited members.

Header | _DXE_ITBT_CONFIG
ITbtGenericConfig | _DXE_ITBT_CONFIG
ITbtResourceConfig | _DXE_ITBT_CONFIG
TbtCommonConfig | _DXE_ITBT_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _DXE_ITBT_GENERIC_CONFIG Struct Reference

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_DXE_ITBT_GENERIC_CONFIG Struct Reference

ITBT Generic Data Structure to be used cross to RP and controller in DXE phase. More...

#include <DxeITbtConfig.h>

Public Attributes

UINT8 | ITbtRtd3
ITBT RTD3. - 0: Disable; 1: Enable.
UINT8 | ITbtVproDockSupport
ITBT vPro Dock support. - 0: not support; 1: supported.
UINT16 | ITbtRtd3ExitDelay
ITBT RTD3 delay before exit, unit is ms 0.

Detailed Description

ITBT Generic Data Structure to be used cross to RP and controller in DXE phase.

Definition at line 50 of file DxeITbtConfig.h.

The documentation for this struct was generated from the following file:
  • DxeITbtConfig.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_DXE_ITBT_GENERIC_CONFIG Member List

This is the complete list of members for _DXE_ITBT_GENERIC_CONFIG, including all inherited members.

ITbtRtd3 | _DXE_ITBT_GENERIC_CONFIG
ITbtRtd3ExitDelay | _DXE_ITBT_GENERIC_CONFIG
ITbtVproDockSupport | _DXE_ITBT_GENERIC_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _EFI_SMM_VARIABLE_PROTOCOL Struct Reference

List of all members
_EFI_SMM_VARIABLE_PROTOCOL Struct Reference

EFI SMM Variable Protocol is intended for use as a means to store data in the EFI SMM environment. More...

#include <SmmVariable.h>

Detailed Description

EFI SMM Variable Protocol is intended for use as a means to store data in the EFI SMM environment.

Definition at line 32 of file SmmVariable.h.

The documentation for this struct was generated from the following file:
  • SmmVariable.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_EFI_SMM_VARIABLE_PROTOCOL Member List

This is the complete list of members for _EFI_SMM_VARIABLE_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _FSP_TEMP_RAM_EXIT_PPI Struct Reference

List of all members
_FSP_TEMP_RAM_EXIT_PPI Struct Reference

This PPI provides function to program MTRR values. More...

#include <TempRamExitPpi.h>

Detailed Description

This PPI provides function to program MTRR values.

Definition at line 63 of file TempRamExitPpi.h.

The documentation for this struct was generated from the following file:
  • TempRamExitPpi.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_FSP_TEMP_RAM_EXIT_PPI Member List

This is the complete list of members for _FSP_TEMP_RAM_EXIT_PPI, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _GOP_COMPONENT_NAME2_PROTOCOL Struct Reference

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_GOP_COMPONENT_NAME2_PROTOCOL Struct Reference

GOP Component protocol
This protocol will be installed by GOP driver and can be used to retrieve GOP information. More...

#include <GopComponentName2.h>

Collaboration diagram for _GOP_COMPONENT_NAME2_PROTOCOL:
[legend]

Public Attributes

GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName
Protocol function to get driver name.
GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion
Protocol function to get driver version.
GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName
Protocol function to get controller name.
CHAR8 * SupportedLanguages
Number of Supported languages.

Detailed Description

GOP Component protocol
This protocol will be installed by GOP driver and can be used to retrieve GOP information.

Definition at line 80 of file GopComponentName2.h.

The documentation for this struct was generated from the following file:
  • GopComponentName2.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_GOP_COMPONENT_NAME2_PROTOCOL Member List

This is the complete list of members for _GOP_COMPONENT_NAME2_PROTOCOL, including all inherited members.

GetControllerName | _GOP_COMPONENT_NAME2_PROTOCOL
GetDriverName | _GOP_COMPONENT_NAME2_PROTOCOL
GetDriverVersion | _GOP_COMPONENT_NAME2_PROTOCOL
SupportedLanguages | _GOP_COMPONENT_NAME2_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HEAP_BIOS_SPEC_VER_ELEMENT Struct Reference

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_HEAP_BIOS_SPEC_VER_ELEMENT Struct Reference

TXT HEAP Memory: BIOS spec version element. More...

#include <Txt.h>

Collaboration diagram for _HEAP_BIOS_SPEC_VER_ELEMENT:
[legend]

Public Attributes

HEAP_EXT_DATA_ELEMENT Header
Header of HEAP extended data. Header.Type = 1.
UINT16 | SpecVerMajor
Major number of TXT BIOS spec version.
UINT16 | SpecVerMinor
Minor number of TXT BIOS spec version.
UINT16 | SpecVerRevision
Revision number of TXT BIOS spec version.

Detailed Description

TXT HEAP Memory: BIOS spec version element.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide

Definition at line 126 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HEAP_BIOS_SPEC_VER_ELEMENT Member List

This is the complete list of members for _HEAP_BIOS_SPEC_VER_ELEMENT, including all inherited members.

Header | _HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerMajor | _HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerMinor | _HEAP_BIOS_SPEC_VER_ELEMENT
SpecVerRevision | _HEAP_BIOS_SPEC_VER_ELEMENT
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HEAP_BIOSACM_ELEMENT Struct Reference

Public Attributes | List of all members
_HEAP_BIOSACM_ELEMENT Struct Reference

TXT HEAP Memory: BIOS ACM element. More...

#include <Txt.h>

Collaboration diagram for _HEAP_BIOSACM_ELEMENT:
[legend]

Public Attributes

HEAP_EXT_DATA_ELEMENT Header
Header of HEAP extended data. Header.Type = 2.
UINT32 NumAcms
Number of BIOS ACMs carried by BIOS.

Detailed Description

TXT HEAP Memory: BIOS ACM element.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide

Definition at line 139 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HEAP_BIOSACM_ELEMENT Member List

This is the complete list of members for _HEAP_BIOSACM_ELEMENT, including all inherited members.

Header | _HEAP_BIOSACM_ELEMENT
NumAcms | _HEAP_BIOSACM_ELEMENT
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HEAP_EXT_DATA_ELEMENT Struct Reference

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_HEAP_EXT_DATA_ELEMENT Struct Reference

TXT HEAP Memory: Extended data elements. More...

#include <Txt.h>

Public Attributes

UINT32 | Type
Type of HEAP extended data element.
UINT32 | Size
Size of HEAP extended data element.

Detailed Description

TXT HEAP Memory: Extended data elements.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide

Definition at line 115 of file Txt.h.

The documentation for this struct was generated from the following file:
  • Txt.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HEAP_EXT_DATA_ELEMENT Member List

This is the complete list of members for _HEAP_EXT_DATA_ELEMENT, including all inherited members.

Size | _HEAP_EXT_DATA_ELEMENT
Type | _HEAP_EXT_DATA_ELEMENT
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HECI_ACCESS_ Struct Reference

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_HECI_ACCESS_ Struct Reference

PPI/PROTOCOL for ME-UEFI FW HECI Access. More...

#include <HeciAccessProtocol.h>

Collaboration diagram for _HECI_ACCESS_:
[legend]

Public Attributes

HECI_ACCESS_GET_NEXT_HECI GetNextHeciAccess
< PciIo R/W HECI PCIe device
HECI_ACCESS_GET_PARAMETER GetHeciPch
< HECI access protocol walker
HECI_ACCESS_GET_PARAMETER GetHeciInterruptMode
< What PCH HECI belongs to

Detailed Description

PPI/PROTOCOL for ME-UEFI FW HECI Access.

This protocol defines operations for HECI (Host Embedded Controller Interface) hardware access.

Definition at line 70 of file HeciAccessProtocol.h.

The documentation for this struct was generated from the following file:
  • HeciAccessProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HECI_ACCESS_ Member List

This is the complete list of members for _HECI_ACCESS_, including all inherited members.

GetHeciInterruptMode | _HECI_ACCESS_
GetHeciPch | _HECI_ACCESS_
GetNextHeciAccess | _HECI_ACCESS_
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HECI_CONTROL_ Struct Reference

Public Attributes | List of all members
_HECI_CONTROL_ Struct Reference

EFI protocol for ME-UEFI FW communication over HECI. More...

#include <HeciControlProtocol.h>

Collaboration diagram for _HECI_CONTROL_:
[legend]

Public Attributes

HECI_CONTROL_SEND HeciSend
< Send HECI message and receive Ack
HECI_CONTROL_RECEIVE HeciReceive
< Send HECI message
HECI_CONTROL_RESET HeciReset
< Receive HECI message
HECI_CONTROL_READ_FIRMWARE_STATUS HeciFirmwareStatus
< Reset HECI interface

Detailed Description

EFI protocol for ME-UEFI FW communication over HECI.

This protocol defines operations for communication with ME using HECI (Host Embedded Controller Interface). There are more HECI functions in ME device on PCI. HECI is designated for ME-UEFI FW boot flow communication.

Definition at line 235 of file HeciControlProtocol.h.

The documentation for this struct was generated from the following file:
  • HeciControlProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HECI_CONTROL_ Member List

This is the complete list of members for _HECI_CONTROL_, including all inherited members.

HeciFirmwareStatus | _HECI_CONTROL_
HeciReceive | _HECI_CONTROL_
HeciReset | _HECI_CONTROL_
HeciSend | _HECI_CONTROL_
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HECI_PPI Struct Reference

Public Attributes | List of all members
_HECI_PPI Struct Reference

HECI PPI The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem in PEI phase. More...

#include <HeciPpi.h>

Public Attributes

HECI_SENDWACK SendwAck
Send HECI message and wait for respond.
HECI_READ_MESSAGE ReadMsg
Read message from HECI.
HECI_SEND_MESSAGE SendMsg
Send message to HECI.
HECI_INIT InitializeHeci
Init HECI.
HECI_GET_ME_STATUS GetMeStatus
Get Intel ME Status register.
HECI_GET_ME_MODE GetMeMode
Get Intel ME mode.

Detailed Description

HECI PPI The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem in PEI phase.

Definition at line 59 of file HeciPpi.h.

The documentation for this struct was generated from the following file:
  • HeciPpi.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HECI_PPI Member List

This is the complete list of members for _HECI_PPI, including all inherited members.

GetMeMode | _HECI_PPI
GetMeStatus | _HECI_PPI
InitializeHeci | _HECI_PPI
ReadMsg | _HECI_PPI
SendMsg | _HECI_PPI
SendwAck | _HECI_PPI
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _HECI_PROTOCOL Struct Reference

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_HECI_PROTOCOL Struct Reference

HECI protocol provided for DXE phase The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem. More...

#include <HeciProtocol.h>

Public Attributes

HECI_SENDWACK SendwAck
Send HECI message and wait for respond.
HECI_READ_MESSAGE ReadMsg
Receive HECI message.
HECI_SEND_MESSAGE SendMsg
Send HECI message.
HECI_RESET ResetHeci
Reset HECI device.
HECI_INIT InitHeci
Initialize HECI device.
HECI_RESET_WAIT MeResetWait
Intel ME Reset Wait Timer.
HECI_REINIT ReInitHeci
Re-initialize HECI.
HECI_GET_ME_STATUS GetMeStatus
Get Intel ME Status register.
HECI_GET_ME_MODE GetMeMode
Get Intel ME mode.

Detailed Description

HECI protocol provided for DXE phase The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem.

There is also support to control HECI Initialization and get Intel ME status.

Definition at line 243 of file HeciProtocol.h.

The documentation for this struct was generated from the following file:
  • HeciProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_HECI_PROTOCOL Member List

This is the complete list of members for _HECI_PROTOCOL, including all inherited members.

GetMeMode | _HECI_PROTOCOL
GetMeStatus | _HECI_PROTOCOL
InitHeci | _HECI_PROTOCOL
MeResetWait | _HECI_PROTOCOL
ReadMsg | _HECI_PROTOCOL
ReInitHeci | _HECI_PROTOCOL
ResetHeci | _HECI_PROTOCOL
SendMsg | _HECI_PROTOCOL
SendwAck | _HECI_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _IO_TRAP_EX_DISPATCH_PROTOCOL Struct Reference

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_IO_TRAP_EX_DISPATCH_PROTOCOL Struct Reference

Interface structure for the IO trap Extention protocol. More...

#include <IoTrapExDispatch.h>

Collaboration diagram for _IO_TRAP_EX_DISPATCH_PROTOCOL:
[legend]

Public Attributes

IO_TRAP_EX_DISPATCH_REGISTER Register
Register function for PCH IO TRAP EX DISPATCH PROTOCOL. More...
IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister
Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL.

Detailed Description

Interface structure for the IO trap Extention protocol.

This protocol exposes full IO TRAP capability for ByteEnable and ByteEnableMask setting. Platform code should fully control the ByteEnable and ByteEnableMake while using this protocol.

Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. This is the function to extend the IoTrap capability, and it's expected to handle the special ByteEnable and ByteEnableMask setting.

The protocol is low level, It returns PSTH trapped cycle. This might not be safe for multithread if more than one thread triggers the same IOTRAP at the same time.

Definition at line 190 of file IoTrapExDispatch.h.

Member Data Documentation

◆ Register

IO_TRAP_EX_DISPATCH_REGISTER _IO_TRAP_EX_DISPATCH_PROTOCOL::Register

Register function for PCH IO TRAP EX DISPATCH PROTOCOL.

The caller will provide information of IO trap setting via the context. Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. This is the function to extend the IoTrap capability, and it's expected to handle the special ByteEnable and ByteEnableMask setting. This register function will occupy one IoTrap register if possible. And it only support one handler for one IoTrap event. The Address of context MUST NOT be 0, and MUST be dword alignment. The Length of context MUST not less than 4, and MUST be power of 2. The ByteEnable and ByteEnableMask MUST not be zero at the same time. if the IO Trap handler is not used. It also enable the IO Trap Range to generate SMI.

Definition at line 205 of file IoTrapExDispatch.h.

The documentation for this struct was generated from the following file:
  • IoTrapExDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_IO_TRAP_EX_DISPATCH_PROTOCOL Member List

This is the complete list of members for _IO_TRAP_EX_DISPATCH_PROTOCOL, including all inherited members.

Register | _IO_TRAP_EX_DISPATCH_PROTOCOL
UnRegister | _IO_TRAP_EX_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _ITBT_GENERIC_CONFIG Struct Reference

Public Attributes | List of all members
_ITBT_GENERIC_CONFIG Struct Reference

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT16 | ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication. More...
UINT16 | ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available on PCIe before BIOS will enumerate them in BDS (Test) default is 5000 ms
UINT8 | ITbtSecurityLevel
iTbt Security Level Deprecated
UINT8 | ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
UINT8 | Usb4CmMode
USB4 CM mode.
UINT8 | Reserved [1]
Reserved for DWORD alignment.

Detailed Description

ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Definition at line 52 of file PeiITbtGenericStructure.h.

Member Data Documentation

◆ ITbtForcePowerOnTimeoutInMs

UINT16 _ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs

Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication.

After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication If TBT cable is disconnected, iTBT microcontrollers are in lower power state. To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or Force Power event. (Test) default is 500 ms

Definition at line 64 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_ITBT_GENERIC_CONFIG Member List

This is the complete list of members for _ITBT_GENERIC_CONFIG, including all inherited members.

ITbtConnectTopologyTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtForcePowerOnTimeoutInMs | _ITBT_GENERIC_CONFIG
ITbtPcieTunnelingForUsb4 | _ITBT_GENERIC_CONFIG
ITbtSecurityLevel | _ITBT_GENERIC_CONFIG
Reserved | _ITBT_GENERIC_CONFIG
Usb4CmMode | _ITBT_GENERIC_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _ITBT_ROOTPORT_CONFIG Struct Reference

Public Attributes | List of all members
_ITBT_ROOTPORT_CONFIG Struct Reference

iTBT RootPort Data Structure More...

#include <PeiITbtGenericStructure.h>

Public Attributes

UINT8 | ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
UINT8 | Reserved [3]
Reserved for DWORD alignment.

Detailed Description

iTBT RootPort Data Structure

Definition at line 44 of file PeiITbtGenericStructure.h.

The documentation for this struct was generated from the following file:
  • PeiITbtGenericStructure.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_ITBT_ROOTPORT_CONFIG Member List

This is the complete list of members for _ITBT_ROOTPORT_CONFIG, including all inherited members.

ITbtPcieRootPortEn | _ITBT_ROOTPORT_CONFIG
Reserved | _ITBT_ROOTPORT_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _ME_JHI_PROTOCOL Struct Reference

Public Attributes | List of all members
_ME_JHI_PROTOCOL Struct Reference

JHI protocol provided for DXE phase The interface functions are for JHI APIs to transfer data between host and Intel ME subsystem. More...

#include <JhiProtocol.h>

Public Attributes

UINT8 Revision
Structure revision number.
JHI_INITIALIZE Initialize
Initialize JHI DXE driver, allocate resource (JHI_Initialize)
JHI_UNINIT Uninit
Uninitialized JHI DXE driver, free resource (JHI_Deinit)
JHI_INSTALL_FILE InstallFile
Download an applet file into ME DAL VM (JHI_Install2)
JHI_INSTALL_CONTENT InstallContent
Download an applet content into ME DAL VM (JHI_Install3)
JHI_UNINSTALL Uninstall
Unload an applet from ME DAL VM (JHI_Uninstall)
JHI_GET_APPLET_PROPERTY GetAppletProperty
Get information of downloaded applets (JHI_GetAppletProperty)
JHI_CREATE_SESSION CreateSession
Create a session for a specific applet (JHI_CreateSession)
JHI_GET_SESSIONS_COUNT GetSessionsCount
Get count of total sessions (JHI_GetSessionsCount)
JHI_CLOSE_SESSION CloseSession
End a session for a specific applet (JHI_CloseSession)
JHI_GET_SESSION_INFO GetSessionInfo
Get information of specific session (JHI_GetSessionInfo)
JHI_GET_VERSION_INFO GetVersionInfo
Get information of JHI driver (JHI_GetVersionInfo)
JHI_SEND_ADN_RECEIVE SendAndReceive
Send/receive data to/from a specific applet (JHI_SendAndRecv2)

Detailed Description

JHI protocol provided for DXE phase The interface functions are for JHI APIs to transfer data between host and Intel ME subsystem.

Definition at line 621 of file JhiProtocol.h.

The documentation for this struct was generated from the following file:
  • JhiProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_ME_JHI_PROTOCOL Member List

This is the complete list of members for _ME_JHI_PROTOCOL, including all inherited members.

CloseSession | _ME_JHI_PROTOCOL
CreateSession | _ME_JHI_PROTOCOL
GetAppletProperty | _ME_JHI_PROTOCOL
GetSessionInfo | _ME_JHI_PROTOCOL
GetSessionsCount | _ME_JHI_PROTOCOL
GetVersionInfo | _ME_JHI_PROTOCOL
Initialize | _ME_JHI_PROTOCOL
InstallContent | _ME_JHI_PROTOCOL
InstallFile | _ME_JHI_PROTOCOL
Revision | _ME_JHI_PROTOCOL
SendAndReceive | _ME_JHI_PROTOCOL
Uninit | _ME_JHI_PROTOCOL
Uninstall | _ME_JHI_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL Struct Reference

List of all members
_ME_PLATFORM_GET_RESET_TYPE_PROTOCOL Struct Reference

Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service is called. More...

#include <MePlatformGetResetType.h>

Detailed Description

Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service is called.

Definition at line 69 of file MePlatformGetResetType.h.

The documentation for this struct was generated from the following file:
  • MePlatformGetResetType.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_ME_PLATFORM_GET_RESET_TYPE_PROTOCOL Member List

This is the complete list of members for _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _ME_POLICY_PROTOCOL Struct Reference

List of all members
_ME_POLICY_PROTOCOL Struct Reference

ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information. More...

#include <MePolicy.h>

Collaboration diagram for _ME_POLICY_PROTOCOL:
[legend]

Detailed Description

ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information.

Revision 1:

  • Initial version.

Definition at line 59 of file MePolicy.h.

The documentation for this struct was generated from the following file:
  • MePolicy.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_ME_POLICY_PROTOCOL Member List

This is the complete list of members for _ME_POLICY_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _MEBX_CONFIG_PROTOCOL Struct Reference

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_MEBX_CONFIG_PROTOCOL Struct Reference

AMT Mebx Config Protocol The interface function is to set/get MEBX settings. More...

#include <MebxConfigProtocol.h>

Detailed Description

AMT Mebx Config Protocol The interface function is to set/get MEBX settings.

It is platform vendor's responsibility to implement the function instances.

Revision 1:

  • Initial version.

Definition at line 89 of file MebxConfigProtocol.h.

The documentation for this struct was generated from the following file:
  • MebxConfigProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_MEBX_CONFIG_PROTOCOL Member List

This is the complete list of members for _MEBX_CONFIG_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _MEBX_DISPLAY_PROTOCOL Struct Reference

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_MEBX_DISPLAY_PROTOCOL Struct Reference

MEBx Display Protocol The interface functions are used for I/O operations related to screen. More...

#include <MebxDisplayProtocol.h>

Collaboration diagram for _MEBX_DISPLAY_PROTOCOL:
[legend]

Detailed Description

MEBx Display Protocol The interface functions are used for I/O operations related to screen.

It is platform vendor's responsibility to implement the function instance.

Definition at line 312 of file MebxDisplayProtocol.h.

The documentation for this struct was generated from the following file:
  • MebxDisplayProtocol.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_MEBX_DISPLAY_PROTOCOL Member List

This is the complete list of members for _MEBX_DISPLAY_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _MEMORY_DXE_CONFIG Struct Reference

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_MEMORY_DXE_CONFIG Struct Reference

The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map. More...

#include <MemoryDxeConfig.h>

Collaboration diagram for _MEMORY_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
UINT8 * | SpdAddressTable
Offset 28: Dimm SPD address Only Server support 2 channels * 3 slots per channel = 6 sockets totally The Desktop and mobile only support 2 channels * 2 slots per channel = 4 sockets totally So there is mapping rule here for Desktop and mobile that there are no more 4 DIMMS totally in a system: Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] Refer to SmbiosMemory.c for use If change the mapping rule, please update the Revision number.
UINT8 | ChannelASlotMap
Offset 36: ChannelASlotMap and ChannelBSlotMap change to use SlotMap as the DIMM slot map solution. More...
UINT8 | MrcTimeMeasure
Offset 38: MRC execution time measurement: 0=Disable, 1=Enable.
UINT8 | MrcFastBoot
Offset 39: Fast boot: 0=Disable, 1=Enable
MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString
Offset 40: Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.
MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString
Offset 48: Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.
UINT8 ** | SlotMap
Offset 56: Each DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ... More...

Detailed Description

The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map.

The data elements should be initialized by a Platform Module.
Revision 1:

  • Initial version.

Definition at line 100 of file MemoryDxeConfig.h.

Member Data Documentation

◆ ChannelASlotMap

UINT8 _MEMORY_DXE_CONFIG::ChannelASlotMap

Offset 36: ChannelASlotMap and ChannelBSlotMap change to use SlotMap as the DIMM slot map solution.

Reserve 2-bytes in order to comply with 4-bytes alignment and keep the offset of other members.

Definition at line 121 of file MemoryDxeConfig.h.

◆ SlotMap

UINT8** _MEMORY_DXE_CONFIG::SlotMap

Offset 56: Each DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ...

if the bit is 1, the related DIMM slot is present. E.g. if memory controller 0 channel 3 has 2 DIMMs, SlotMap[0][3] = 0x03; E.g. if memory controller 1 channel 2 has only 1 DIMMs, SlotMap[1][2] = 0x0;

Definition at line 150 of file MemoryDxeConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryDxeConfig.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_MEMORY_DXE_CONFIG Member List

This is the complete list of members for _MEMORY_DXE_CONFIG, including all inherited members.

ChannelASlotMap | _MEMORY_DXE_CONFIG
GetBankLocatorString | _MEMORY_DXE_CONFIG
GetDeviceLocatorString | _MEMORY_DXE_CONFIG
Header | _MEMORY_DXE_CONFIG
MrcFastBoot | _MEMORY_DXE_CONFIG
MrcTimeMeasure | _MEMORY_DXE_CONFIG
SlotMap | _MEMORY_DXE_CONFIG
SpdAddressTable | _MEMORY_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _OC_MAILBOX_FULL Struct Reference

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_OC_MAILBOX_FULL Struct Reference

Consolidated OC mailbox command structure containing both data and interface information. More...

#include <CpuMailboxLib.h>

Collaboration diagram for _OC_MAILBOX_FULL:
[legend]

Public Attributes

UINT32 Data
OC Mailbox read/write data.
OC_MAILBOX_INTERFACE Interface
OC mailbox interface.

Detailed Description

Consolidated OC mailbox command structure containing both data and interface information.

Definition at line 157 of file CpuMailboxLib.h.

The documentation for this struct was generated from the following file:
  • CpuMailboxLib.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_OC_MAILBOX_FULL Member List

This is the complete list of members for _OC_MAILBOX_FULL, including all inherited members.

Data | _OC_MAILBOX_FULL
Interface | _OC_MAILBOX_FULL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _OC_MAILBOX_INTERFACE Union Reference

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_OC_MAILBOX_INTERFACE Union Reference

Expanded Overclocking Mailbox interface defintion, contains command id/completion code, input parameters and the run/busy bit. More...

#include <CpuMailboxLib.h>

Public Attributes

UINT32 InterfaceData
All bit fields as a 32-bit value.
struct {
UINT8 CommandCompletion: 8
Command ID and completion code.
UINT8 Param1: 8
Parameter 1, generally used to specify the CPU Domain ID.
UINT8 Param2: 8
Parameter 2, only current usage is as a core index for ratio limits message.
UINT8 Reserved: 7
Reserved for future use.
UINT8 RunBusy: 1
Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
} Fields
Individual bit fields.

Detailed Description

Expanded Overclocking Mailbox interface defintion, contains command id/completion code, input parameters and the run/busy bit.

Definition at line 140 of file CpuMailboxLib.h.

The documentation for this union was generated from the following file:
  • CpuMailboxLib.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_OC_MAILBOX_INTERFACE Member List

This is the complete list of members for _OC_MAILBOX_INTERFACE, including all inherited members.

CommandCompletion | _OC_MAILBOX_INTERFACE
Fields | _OC_MAILBOX_INTERFACE
InterfaceData | _OC_MAILBOX_INTERFACE
Param1 | _OC_MAILBOX_INTERFACE
Param2 | _OC_MAILBOX_INTERFACE
Reserved | _OC_MAILBOX_INTERFACE
RunBusy | _OC_MAILBOX_INTERFACE
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_ACPI_SMI_DISPATCH_PROTOCOL Struct Reference

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_PCH_ACPI_SMI_DISPATCH_PROTOCOL Struct Reference

Interface structure for PCH ACPI SMIs Dispatch Protocol The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs. More...

#include <PchAcpiSmiDispatch.h>

Collaboration diagram for _PCH_ACPI_SMI_DISPATCH_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL.
PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister
Pme The event is triggered by hardware when the PME# signal goes active. More...
PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register
PmeB0 The event is triggered PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal. More...
PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister
RtcAlarm The event is triggered by hardware when the RTC generates an alarm (assertion of the IRQ8# signal).
PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister
TmrOverflow The event is triggered any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23). More...

Detailed Description

Interface structure for PCH ACPI SMIs Dispatch Protocol The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs.

It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow.

Definition at line 112 of file PchAcpiSmiDispatch.h.

Member Data Documentation

◆ PmeB0Register

PCH_ACPI_SMI_DISPATCH_REGISTER _PCH_ACPI_SMI_DISPATCH_PROTOCOL::PmeB0Register

PmeB0 The event is triggered PCH when any internal device with PCI Power Management capabilities on bus 0 asserts the equivalent of the PME# signal.

Additionally, the event is only triggered when SCI_EN is not set. The following are internal devices which can set this bit: Intel HD Audio, Intel Management Engine "maskable" wake events, Integrated LAN, SATA, xHCI, Intel SST

Definition at line 137 of file PchAcpiSmiDispatch.h.

◆ PmeRegister

PCH_ACPI_SMI_DISPATCH_REGISTER _PCH_ACPI_SMI_DISPATCH_PROTOCOL::PmeRegister

Pme The event is triggered by hardware when the PME# signal goes active.

Additionally, the event is only triggered when SCI_EN is not set.

Definition at line 127 of file PchAcpiSmiDispatch.h.

◆ Revision

UINT8 _PCH_ACPI_SMI_DISPATCH_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 117 of file PchAcpiSmiDispatch.h.

◆ TmrOverflowRegister

PCH_ACPI_SMI_DISPATCH_REGISTER _PCH_ACPI_SMI_DISPATCH_PROTOCOL::TmrOverflowRegister

TmrOverflow The event is triggered any time bit 22 of the 24-bit timer goes high (bits are numbered from 0 to 23).

This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 02h, bit 0) is set, then the setting of the TMROF_STS bit will additionally generate an SMI# Additionally, the event is only triggered when SCI_EN is not set.

Definition at line 152 of file PchAcpiSmiDispatch.h.

The documentation for this struct was generated from the following file:
  • PchAcpiSmiDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_ACPI_SMI_DISPATCH_PROTOCOL Member List

This is the complete list of members for _PCH_ACPI_SMI_DISPATCH_PROTOCOL, including all inherited members.

PmeB0Register | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
PmeRegister | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
Revision | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
RtcAlarmRegister | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
TmrOverflowRegister | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
UnRegister | _PCH_ACPI_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_ESPI_SMI_DISPATCH_PROTOCOL Struct Reference

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_PCH_ESPI_SMI_DISPATCH_PROTOCOL Struct Reference

Interface structure for PCH eSPI SMIs Dispatch Protocol The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs. More...

#include <PchEspiSmiDispatch.h>

Collaboration diagram for _PCH_ESPI_SMI_DISPATCH_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_ESPI_SMI_UNREGISTER UnRegister
Unregister eSPI SMI events.
PCH_ESPI_SMI_REGISTER BiosWrProtectRegister
Register a BIOS Write Protect event.
PCH_ESPI_SMI_REGISTER BiosWrReportRegister
Register a BIOS Write Report event.
PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister
Register a Peripheral Channel Non Fatal Error event.
PCH_ESPI_SMI_REGISTER PcErrFatalRegister
Register a Peripheral Channel Fatal Error event.
PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister
Register a Virtual Wire Non Fatal Error event.
PCH_ESPI_SMI_REGISTER VwErrFatalRegister
Register a Virtual Wire Fatal Error event.
PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister
Register a Flash Channel Non Fatal Error event.
PCH_ESPI_SMI_REGISTER FlashErrFatalRegister
Register a Flash Channel Fatal Error event.
PCH_ESPI_SMI_REGISTER LnkErrType1Register
Register a Link Error event.
PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister
Register a SMI handler for Espi slaver This routine will also lock down ESPI_SMI_LOCK bit after registration and prevent this handler from unregistration. More...

Detailed Description

Interface structure for PCH eSPI SMIs Dispatch Protocol The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs.

It contains SMI types of BiosWr, EcAssertedVw, and eSPI Initiator asserted SMIs

Definition at line 107 of file PchEspiSmiDispatch.h.

Member Data Documentation

◆ EspiSlaveSmiRegister

PCH_ESPI_SMI_REGISTER _PCH_ESPI_SMI_DISPATCH_PROTOCOL::EspiSlaveSmiRegister

Register a SMI handler for Espi slaver This routine will also lock down ESPI_SMI_LOCK bit after registration and prevent this handler from unregistration.

On platform that supports more than 1 device through another chip select (SPT-H), the SMI handler itself needs to inspect both the eSPI devices' interrupt status registers (implementation specific for each Slave) in order to identify and service the cause. After servicing it, it has to clear the Slaves' internal SMI# status registers

Definition at line 162 of file PchEspiSmiDispatch.h.

◆ Revision

UINT8 _PCH_ESPI_SMI_DISPATCH_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 112 of file PchEspiSmiDispatch.h.

The documentation for this struct was generated from the following file:
  • PchEspiSmiDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_ESPI_SMI_DISPATCH_PROTOCOL Member List

This is the complete list of members for _PCH_ESPI_SMI_DISPATCH_PROTOCOL, including all inherited members.

BiosWrProtectRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
BiosWrReportRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
EspiSlaveSmiRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
FlashErrFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
FlashErrNonFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
LnkErrType1Register | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
PcErrFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
PcErrNonFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
Revision | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
UnRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
VwErrFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
VwErrNonFatalRegister | _PCH_ESPI_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_PCIE_SMI_DISPATCH_PROTOCOL Struct Reference

Public Attributes | List of all members
_PCH_PCIE_SMI_DISPATCH_PROTOCOL Struct Reference

Interface structure for PCH PCIE SMIs Dispatch Protocol The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs. More...

#include <PchPcieSmiDispatch.h>

Collaboration diagram for _PCH_PCIE_SMI_DISPATCH_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.
PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister
PcieRpXHotPlug The event is triggered when PCIE root port Hot-Plug Presence Detect.
PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister
PcieRpXLinkActive The event is triggered when Hot-Plug Link Active State Changed.
PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister
PcieRpXLinkEq The event is triggered when Device Requests Software Link Equalization.

Detailed Description

Interface structure for PCH PCIE SMIs Dispatch Protocol The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs.

It contains SMI types of HotPlug, LinkActive, and Link EQ.

Definition at line 160 of file PchPcieSmiDispatch.h.

Member Data Documentation

◆ Revision

UINT8 _PCH_PCIE_SMI_DISPATCH_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 165 of file PchPcieSmiDispatch.h.

The documentation for this struct was generated from the following file:
  • PchPcieSmiDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_PCIE_SMI_DISPATCH_PROTOCOL Member List

This is the complete list of members for _PCH_PCIE_SMI_DISPATCH_PROTOCOL, including all inherited members.

HotPlugRegister | _PCH_PCIE_SMI_DISPATCH_PROTOCOL
LinkActiveRegister | _PCH_PCIE_SMI_DISPATCH_PROTOCOL
LinkEqRegister | _PCH_PCIE_SMI_DISPATCH_PROTOCOL
Revision | _PCH_PCIE_SMI_DISPATCH_PROTOCOL
UnRegister | _PCH_PCIE_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_PREMEM_POLICY Struct Reference

List of all members
_PCH_PREMEM_POLICY Struct Reference

PCH Policy PPI
All PCH config block change history will be listed here

. More...

#include <PchPreMemPolicyCommon.h>

Collaboration diagram for _PCH_PREMEM_POLICY:
[legend]

Detailed Description

PCH Policy PPI
All PCH config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 76 of file PchPreMemPolicyCommon.h.

The documentation for this struct was generated from the following file:
  • PchPreMemPolicyCommon.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_PREMEM_POLICY Member List

This is the complete list of members for _PCH_PREMEM_POLICY, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_SMI_DISPATCH_PROTOCOL Struct Reference

Public Attributes | List of all members
_PCH_SMI_DISPATCH_PROTOCOL Struct Reference

Interface structure for PCH specific SMIs Dispatch Protocol The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs. More...

#include <PchSmiDispatch.h>

Collaboration diagram for _PCH_SMI_DISPATCH_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH SMI DISPATCH PROTOCOL.
PCH_SMI_DISPATCH_REGISTER SerialIrqRegister
SerialIrq The event is triggered while the SMI# was caused by the SERIRQ decoder.
PCH_SMI_DISPATCH_REGISTER McSmiRegister
McSmi The event is triggered if there has been an access to the power management microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit in the LPC Bridge I/O Enables configuration register is 1 .
PCH_SMI_DISPATCH_REGISTER SmbusRegister
SmBus The event is triggered while the SMI# was caused by: More...
PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister
SPI Asynchronous When registered, the flash controller will generate an SMI when it blocks a BIOS write or erase.

Detailed Description

Interface structure for PCH specific SMIs Dispatch Protocol The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs.

It contains legacy SMIs and new PCH SMI types like: SerialIrq, McSmi, Smbus, ...

Definition at line 113 of file PchSmiDispatch.h.

Member Data Documentation

◆ Revision

UINT8 _PCH_SMI_DISPATCH_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 118 of file PchSmiDispatch.h.

◆ SmbusRegister

PCH_SMI_DISPATCH_REGISTER _PCH_SMI_DISPATCH_PROTOCOL::SmbusRegister

SmBus The event is triggered while the SMI# was caused by:

  1. The SMBus target receiving a message that an SMI# should be caused, or
  2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the SMBALERT_DIS bit is cleared, or
  3. The SMBus target receiving a Host Notify message and the HOST_NOTIFY_INTREN and the SMB_SMI_EN bits are set, or
  4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state.

Definition at line 145 of file PchSmiDispatch.h.

The documentation for this struct was generated from the following file:
  • PchSmiDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_SMI_DISPATCH_PROTOCOL Member List

This is the complete list of members for _PCH_SMI_DISPATCH_PROTOCOL, including all inherited members.

McSmiRegister | _PCH_SMI_DISPATCH_PROTOCOL
Revision | _PCH_SMI_DISPATCH_PROTOCOL
SerialIrqRegister | _PCH_SMI_DISPATCH_PROTOCOL
SmbusRegister | _PCH_SMI_DISPATCH_PROTOCOL
SpiAsyncRegister | _PCH_SMI_DISPATCH_PROTOCOL
UnRegister | _PCH_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL Struct Reference

Public Attributes | List of all members
_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL Struct Reference

Interface structure for the SMM IO trap pause and resume protocol This protocol provides the functions to runtime control the IoTrap SMI enabled/disable. More...

#include <PchSmmIoTrapControl.h>

Collaboration diagram for _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL:
[legend]

Public Attributes

PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause
This runtime pauses a registered IoTrap handler.
PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume
This runtime resumes a registered IoTrap handler.

Detailed Description

Interface structure for the SMM IO trap pause and resume protocol This protocol provides the functions to runtime control the IoTrap SMI enabled/disable.

This applys the capability to the DispatchHandle which returned by IoTrap callback registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0. Besides, when S3 resuem, it only restores the state of IoTrap callback registration. The Paused/Resume state won't be restored after S3 resume.

Definition at line 82 of file PchSmmIoTrapControl.h.

The documentation for this struct was generated from the following file:
  • PchSmmIoTrapControl.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL Member List

This is the complete list of members for _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL, including all inherited members.

Pause | _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL
Resume | _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL Struct Reference

Public Attributes | List of all members
_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL Struct Reference

Interface structure for the SMM PERIODIC TIMER pause and resume protocol This protocol provides the functions to runtime control the SM periodic timer enabled/disable. More...

#include <PchSmmPeriodicTimerControl.h>

Collaboration diagram for _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL:
[legend]

Public Attributes

PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause
This runtime pauses the registered periodic timer handler.
PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume
This runtime resumes the registered periodic timer handler.

Detailed Description

Interface structure for the SMM PERIODIC TIMER pause and resume protocol This protocol provides the functions to runtime control the SM periodic timer enabled/disable.

This applies the capability to the DispatchHandle which returned by SMM periodic timer callback registration. Besides, when S3 resume, it only restores the state of callback registration. The Paused/Resume state won't be restored after S3 resume.

Definition at line 82 of file PchSmmPeriodicTimerControl.h.

The documentation for this struct was generated from the following file:
  • PchSmmPeriodicTimerControl.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL Member List

This is the complete list of members for _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL, including all inherited members.

Pause | _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
Resume | _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_SPI_PROTOCOL Struct Reference

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_PCH_SPI_PROTOCOL Struct Reference

These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host Controller Interface. More...

#include <Spi.h>

Collaboration diagram for _PCH_SPI_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_SPI_FLASH_READ FlashRead
Read data from the flash part.
PCH_SPI_FLASH_WRITE FlashWrite
Write data to the flash part. Remark: Erase may be needed before write to the flash part.
PCH_SPI_FLASH_ERASE FlashErase
Erase some area on the flash part.
PCH_SPI_FLASH_READ_SFDP FlashReadSfdp
Read SFDP data from the flash part.
PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId
Read Jedec Id from the flash part.
PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus
Write the status register in the flash part.
PCH_SPI_FLASH_READ_STATUS FlashReadStatus
Read status register in the flash part.
PCH_SPI_GET_REGION_ADDRESS GetRegionAddress
Get the SPI region base and size.
PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap
Read PCH Soft Strap Values.
PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap
Read CPU Soft Strap Values.

Detailed Description

These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host Controller Interface.

Definition at line 349 of file Protocol/Spi.h.

Member Data Documentation

◆ Revision

UINT8 _PCH_SPI_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 354 of file Protocol/Spi.h.

The documentation for this struct was generated from the following file:
  • Protocol/Spi.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_SPI_PROTOCOL Member List

This is the complete list of members for _PCH_SPI_PROTOCOL, including all inherited members.

FlashErase | _PCH_SPI_PROTOCOL
FlashRead | _PCH_SPI_PROTOCOL
FlashReadJedecId | _PCH_SPI_PROTOCOL
FlashReadSfdp | _PCH_SPI_PROTOCOL
FlashReadStatus | _PCH_SPI_PROTOCOL
FlashWrite | _PCH_SPI_PROTOCOL
FlashWriteStatus | _PCH_SPI_PROTOCOL
GetRegionAddress | _PCH_SPI_PROTOCOL
ReadCpuSoftStrap | _PCH_SPI_PROTOCOL
ReadPchSoftStrap | _PCH_SPI_PROTOCOL
Revision | _PCH_SPI_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCH_TCO_SMI_DISPATCH_PROTOCOL Struct Reference

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_PCH_TCO_SMI_DISPATCH_PROTOCOL Struct Reference

Interface structure for PCH TCO SMIs Dispatch Protocol The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs. More...

#include <PchTcoSmiDispatch.h>

Collaboration diagram for _PCH_TCO_SMI_DISPATCH_PROTOCOL:
[legend]

Public Attributes

UINT8 Revision
This member specifies the revision of this structure. More...
PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL.
PCH_TCO_SMI_DISPATCH_REGISTER MchRegister
Mch The event is triggered when PCH received a DMI special cycle message using DMI indicating that it wants to cause an SMI. More...
PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister
TcoTimeout The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reaching 0.
PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister
OsTco The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h).
PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister
Nmi The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherwise have caused an NMI (because NMI2SMI_EN is set)
PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister
IntruderDectect The event is triggered by PCH to indicate that an intrusion was detected.
PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister
SpiBiosWp This event is triggered when SMI# was caused by the TCO logic and SPI flash controller asserted Synchronous SMI by BIOS lock enable set.
PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister
LpcBiosWp This event is triggered when SMI# was caused by the TCO logic and LPC/eSPI BIOS lock enable set.
PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister
NewCentury This event is triggered when SMI# was caused by the TCO logic and year of RTC date rolls over a century (99 to 00).

Detailed Description

Interface structure for PCH TCO SMIs Dispatch Protocol The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs.

It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, and BiowWp.

Definition at line 112 of file PchTcoSmiDispatch.h.

Member Data Documentation

◆ MchRegister

PCH_TCO_SMI_DISPATCH_REGISTER _PCH_TCO_SMI_DISPATCH_PROTOCOL::MchRegister

Mch The event is triggered when PCH received a DMI special cycle message using DMI indicating that it wants to cause an SMI.

The software must read the processor to determine the reason for the SMI.

Definition at line 128 of file PchTcoSmiDispatch.h.

◆ Revision

UINT8 _PCH_TCO_SMI_DISPATCH_PROTOCOL::Revision

This member specifies the revision of this structure.

This field is used to indicate backwards compatible changes to the protocol.

Definition at line 117 of file PchTcoSmiDispatch.h.

The documentation for this struct was generated from the following file:
  • PchTcoSmiDispatch.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCH_TCO_SMI_DISPATCH_PROTOCOL Member List

This is the complete list of members for _PCH_TCO_SMI_DISPATCH_PROTOCOL, including all inherited members.

IntruderDetRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
LpcBiosWpRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
MchRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
NewCenturyRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
NmiRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
OsTcoRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
Revision | _PCH_TCO_SMI_DISPATCH_PROTOCOL
SpiBiosWpRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
TcoTimeoutRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
UnRegister | _PCH_TCO_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCODE_MAILBOX_FULL Struct Reference

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_PCODE_MAILBOX_FULL Struct Reference

Consolidated Pcode mailbox command structure containing both data and interface information. More...

#include <CpuMailboxLib.h>

Collaboration diagram for _PCODE_MAILBOX_FULL:
[legend]

Public Attributes

PCODE_MAILBOX_INTERFACE Interface
Pcode mailbox interface.
UINT32 Data
Pcode mailbox read/write data.

Detailed Description

Consolidated Pcode mailbox command structure containing both data and interface information.

Definition at line 183 of file CpuMailboxLib.h.

The documentation for this struct was generated from the following file:
  • CpuMailboxLib.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCODE_MAILBOX_FULL Member List

This is the complete list of members for _PCODE_MAILBOX_FULL, including all inherited members.

Data | _PCODE_MAILBOX_FULL
Interface | _PCODE_MAILBOX_FULL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PCODE_MAILBOX_INTERFACE Union Reference

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_PCODE_MAILBOX_INTERFACE Union Reference

Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit. More...

#include <CpuMailboxLib.h>

Public Attributes

UINT32 InterfaceData
All bit fields as a 32-bit value.
struct {
UINT32 Command: 8
Pcode mailbox command.
UINT32 Param1: 8
This field contains parameter 1, used by sub-commands.
UINT32 Param2: 13
This field contains parameter 2.
UINT32 Reserved: 2
Reserved for future use.
UINT32 RunBusy: 1
Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
} Fields
Individual bit fields.

Detailed Description

Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit.

Definition at line 166 of file CpuMailboxLib.h.

The documentation for this union was generated from the following file:
  • CpuMailboxLib.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PCODE_MAILBOX_INTERFACE Member List

This is the complete list of members for _PCODE_MAILBOX_INTERFACE, including all inherited members.

Command | _PCODE_MAILBOX_INTERFACE
Fields | _PCODE_MAILBOX_INTERFACE
InterfaceData | _PCODE_MAILBOX_INTERFACE
Param1 | _PCODE_MAILBOX_INTERFACE
Param2 | _PCODE_MAILBOX_INTERFACE
Reserved | _PCODE_MAILBOX_INTERFACE
RunBusy | _PCODE_MAILBOX_INTERFACE
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PEI_ITBT_CONFIG Struct Reference

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_PEI_ITBT_CONFIG Struct Reference

ITBT PEI configuration
Revision 1: More...

#include <PeiITbtConfig.h>

Collaboration diagram for _PEI_ITBT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Common Configuration.
ITBT_ROOTPORT_CONFIG | ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]
iTbt Root Port Configuration
UINT16 | ITbtDmaLtr [MAX_HOST_ITBT_DMA_NUMBER]
iTbt Host controller DMA LTR value

Detailed Description

ITBT PEI configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.

Definition at line 53 of file PeiITbtConfig.h.

The documentation for this struct was generated from the following file:
  • PeiITbtConfig.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PEI_ITBT_CONFIG Member List

This is the complete list of members for _PEI_ITBT_CONFIG, including all inherited members.

Header | _PEI_ITBT_CONFIG
ITbtDmaLtr | _PEI_ITBT_CONFIG
ITbtGenericConfig | _PEI_ITBT_CONFIG
ITbtRootPortConfig | _PEI_ITBT_CONFIG
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiPreMemSiDefaultPolicy.h>

Public Attributes

PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiPreMemSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiPreMemSiDefaultPolicy.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI Member List

This is the complete list of members for _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI, including all inherited members.

PeiPreMemPolicyInit _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

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_PEI_SI_DEFAULT_POLICY_INIT_PPI Struct Reference

This PPI provides function to install default silicon policy. More...

#include <PeiSiDefaultPolicy.h>

Public Attributes

PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()

Detailed Description

This PPI provides function to install default silicon policy.

Definition at line 55 of file PeiSiDefaultPolicy.h.

The documentation for this struct was generated from the following file:
  • PeiSiDefaultPolicy.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PEI_SI_DEFAULT_POLICY_INIT_PPI Member List

This is the complete list of members for _PEI_SI_DEFAULT_POLICY_INIT_PPI, including all inherited members.

PeiPolicyInit _PEI_SI_DEFAULT_POLICY_INIT_PPI
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PEI_SMM_CONTROL_PPI Struct Reference

List of all members
_PEI_SMM_CONTROL_PPI Struct Reference

PEI SMM Control PPI is used to initiate SMI/PMI activations. More...

#include <SmmControl.h>

Collaboration diagram for _PEI_SMM_CONTROL_PPI:
[legend]

Detailed Description

PEI SMM Control PPI is used to initiate SMI/PMI activations.

This protocol could be published by either:

  • A processor driver to abstract the SMI/PMI IPI
  • The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an Intel chipset

Definition at line 91 of file SmmControl.h.

The documentation for this struct was generated from the following file:
  • SmmControl.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PEI_SMM_CONTROL_PPI Member List

This is the complete list of members for _PEI_SMM_CONTROL_PPI, including all inherited members.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PLATFORM_ME_HOOK_PROTOCOL Struct Reference

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_PLATFORM_ME_HOOK_PROTOCOL Struct Reference

Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM before perform reset command through Heci. More...

#include <PlatformMeHook.h>

Public Attributes

PLATFORM_ME_HOOK_PRE_GLOBAL_RESET PreGlobalReset
Function pointer for the hook called before BIOS sends Global Reset Heci Message to ME.

Detailed Description

Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM before perform reset command through Heci.

Definition at line 62 of file PlatformMeHook.h.

The documentation for this struct was generated from the following file:
  • PlatformMeHook.h
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PLATFORM_ME_HOOK_PROTOCOL Member List

This is the complete list of members for _PLATFORM_ME_HOOK_PROTOCOL, including all inherited members.

PreGlobalReset _PLATFORM_ME_HOOK_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _PPM_CUSTOM_CTDP_TABLE Struct Reference

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_PPM_CUSTOM_CTDP_TABLE Struct Reference

PPM Custom ConfigTdp Settings. More...

#include <CpuPowerMgmtCustomConfig.h>

Public Attributes

UINT32 | CustomPowerLimit1Time: 8
Short term Power Limit time window value for custom cTDP level.
UINT32 | CustomTurboActivationRatio: 8
Turbo Activation Ratio for custom cTDP level.
UINT32 | RsvdBits: 16
Bits reserved for DWORD alignment.
UINT16 | CustomPowerLimit1
Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | CustomPowerLimit2
Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Detailed Description

PPM Custom ConfigTdp Settings.

Definition at line 79 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_PPM_CUSTOM_CTDP_TABLE Member List

This is the complete list of members for _PPM_CUSTOM_CTDP_TABLE, including all inherited members.

CustomPowerLimit1 | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit1Time | _PPM_CUSTOM_CTDP_TABLE
CustomPowerLimit2 | _PPM_CUSTOM_CTDP_TABLE
CustomTurboActivationRatio | _PPM_CUSTOM_CTDP_TABLE
RsvdBits | _PPM_CUSTOM_CTDP_TABLE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _SI_POLICY_STRUCT Struct Reference

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_SI_POLICY_STRUCT Struct Reference

SI Policy PPI
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 85 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_SI_POLICY_STRUCT Member List

This is the complete list of members for _SI_POLICY_STRUCT, including all inherited members.

TableHeader _SI_POLICY_STRUCT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _SI_PREMEM_POLICY_STRUCT Struct Reference

Public Attributes | List of all members
_SI_PREMEM_POLICY_STRUCT Struct Reference

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...

#include <SiPolicyStruct.h>

Collaboration diagram for _SI_PREMEM_POLICY_STRUCT:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.

Detailed Description

SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

.

  • Revision 1:
    • Initial version.

Definition at line 71 of file SiPolicyStruct.h.

The documentation for this struct was generated from the following file:
  • SiPolicyStruct.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_SI_PREMEM_POLICY_STRUCT Member List

This is the complete list of members for _SI_PREMEM_POLICY_STRUCT, including all inherited members.

TableHeader _SI_PREMEM_POLICY_STRUCT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _THC_PROTOCOL Struct Reference

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_THC_PROTOCOL Struct Reference

Protocol used by Thc Once installed allows to detect if it is already running on given device Also used for obtaining Thc context. More...

#include <Thc.h>

Collaboration diagram for _THC_PROTOCOL:
[legend]

Public Attributes

EFI_STATUS DeviceStatus
Devices Status: EFI_NOT_READY - Thc initialization is still in progress EFI_DEVICE_ERROR - Thc Initialization failed EFI_SUCCESS - Thc is functional.

Detailed Description

Protocol used by Thc Once installed allows to detect if it is already running on given device Also used for obtaining Thc context.

Note
Designed to be backward compatible with previous versions.

Definition at line 124 of file Thc.h.

The documentation for this struct was generated from the following file:
  • Thc.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_THC_PROTOCOL Member List

This is the complete list of members for _THC_PROTOCOL, including all inherited members.

DeviceStatus _THC_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _TXT_INFO_DATA Struct Reference

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_TXT_INFO_DATA Struct Reference

TXT Info data. More...

#include <TxtInfoHob.h>

Public Attributes

UINT64 | SinitMemorySize
Size of memory reserved for placement of SINIT module. This memory is used by MLE.
UINT64 | TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
EFI_PHYSICAL_ADDRESS | TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
UINT64 | TxtDprMemorySize
Size of DPR protected memory reserved for TXT component.
EFI_PHYSICAL_ADDRESS | BiosAcmBase
Base address of BIOS ACM in system firmware.
UINT64 | BiosAcmSize
Size of BIOS ACM.
EFI_PHYSICAL_ADDRESS | SinitAcmBase
Base address of SINIT module if installed in system firmware. Zero otherwise.
UINT64 | SinitAcmSize
Size of SINIT module if installed in system firmware. Zero otherwise.
UINT64 | TgaSize
Size of Trusted Graphics Aperture if supported by chipset.
EFI_PHYSICAL_ADDRESS | TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
UINT64 | TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
UINT64 | Flags
Flags passed from BIOS to OS or MRC. More...
EFI_PHYSICAL_ADDRESS | ApStartupBase
Base address of AP Startup code.
EFI_PHYSICAL_ADDRESS | TsegBase
Physical base address of TSEG region.
UINT64 | TsegSize
Size of the entity at TSEG region.
EFI_PHYSICAL_ADDRESS | MsegBase
Physical base address of MSEG region.
UINT64 | MsegSize
Size of the entity at MSEG region.
UINT32 | AcpiBase:16
Address of PM1a_CNT_BLK register block. It is used by TXT PEIM to clean Sleep Type field of PM1a_CNT_BLK.S4 register before running of SCLEAN.
UINT32 | ChipsetIsTxtCapable:1
Value is set to 1 if chipset is Intel TXT capable.
UINT32 | TxtMode:1
Value is set to 1 if Intel TXT mode is enabled in BIOS Setup.
UINT32 | ResetAux:1
Value is set to 1 if reset Aux is enabled in BIOS Setup.
UINT32 | TxtAcheckRequest:1
Value is set to 1 if TXT Acheck Request is enabled in BIOS Setup.
UINT32 | ProcessorIsTxtCapable:1
Value is set to 1 if processor is Intel TXT capable.
UINT32 | Reserved:11
Reserved for future use.
UINT8 | AcmMajorVersion
BIOSACM binary major version.
UINT8 | AcmMinorVersion
BIOSACM binary minor version.
UINT8 | AcmRevision
BIOSACM binary revision.
UINT8 | Rsvd [1]
Reserved for config block alignment.

Detailed Description

TXT Info data.

The data that will be passed to DXE via TXT_INFO_HOB.

Definition at line 44 of file TxtInfoHob.h.

Member Data Documentation

◆ Flags

UINT64 _TXT_INFO_DATA::Flags

Flags passed from BIOS to OS or MRC.

  • BIT0: FLAGS0 for compatible definition.
  • BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
  • BIT2: TPM_INIT_FAILED for indicate TPM initiate status. If the bit set, ResetEstablishmentBit is skipped in Dxe driver.

Definition at line 62 of file TxtInfoHob.h.

The documentation for this struct was generated from the following file:
  • TxtInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_TXT_INFO_DATA Member List

This is the complete list of members for _TXT_INFO_DATA, including all inherited members.

AcmMajorVersion | _TXT_INFO_DATA
AcmMinorVersion | _TXT_INFO_DATA
AcmRevision | _TXT_INFO_DATA
AcpiBase | _TXT_INFO_DATA
ApStartupBase | _TXT_INFO_DATA
BiosAcmBase | _TXT_INFO_DATA
BiosAcmSize | _TXT_INFO_DATA
ChipsetIsTxtCapable | _TXT_INFO_DATA
Flags | _TXT_INFO_DATA
MsegBase | _TXT_INFO_DATA
MsegSize | _TXT_INFO_DATA
ProcessorIsTxtCapable | _TXT_INFO_DATA
Reserved | _TXT_INFO_DATA
ResetAux | _TXT_INFO_DATA
Rsvd | _TXT_INFO_DATA
SinitAcmBase | _TXT_INFO_DATA
SinitAcmSize | _TXT_INFO_DATA
SinitMemorySize | _TXT_INFO_DATA
TgaSize | _TXT_INFO_DATA
TsegBase | _TXT_INFO_DATA
TsegSize | _TXT_INFO_DATA
TxtAcheckRequest | _TXT_INFO_DATA
TxtDprMemoryBase | _TXT_INFO_DATA
TxtDprMemorySize | _TXT_INFO_DATA
TxtHeapMemorySize | _TXT_INFO_DATA
TxtLcpPdBase | _TXT_INFO_DATA
TxtLcpPdSize | _TXT_INFO_DATA
TxtMode | _TXT_INFO_DATA
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _TXT_INFO_HOB Struct Reference

Public Attributes | List of all members
_TXT_INFO_HOB Struct Reference

HOB to save TXT Info data. More...

#include <TxtInfoHob.h>

Collaboration diagram for _TXT_INFO_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE EfiHobGuidType
EFI Hob Guid Type.
TXT_INFO_DATA Data
TXT Info Data.

Detailed Description

HOB to save TXT Info data.

TXT Info HOB is used for passing Policy settings and CPU/chipset information within TXT modules.

Definition at line 97 of file TxtInfoHob.h.

The documentation for this struct was generated from the following file:
  • TxtInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_TXT_INFO_HOB Member List

This is the complete list of members for _TXT_INFO_HOB, including all inherited members.

Data | _TXT_INFO_HOB
EfiHobGuidType | _TXT_INFO_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): _WDT_PROTOCOL Struct Reference

Public Attributes | List of all members
_WDT_PROTOCOL Struct Reference

These protocols and PPI allow a platform module to perform watch dog timer operations through the Intel PCH LPC Host Controller Interface. More...

#include <Wdt.h>

Public Attributes

WDT_RELOAD_AND_START ReloadAndStart
Reloads WDT with new timeout value and starts it.
WDT_CHECK_STATUS CheckStatus
Returns WDT failure status.
WDT_DISABLE Disable
Disables WDT timer.
WDT_ALLOW_KNOWN_RESET AllowKnownReset
Perform expected reboots with WDT running, without being interpreted as failures.
IS_WDT_REQUIRED IsWdtRequired
Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
IS_WDT_ENABLED IsWdtEnabled
Returns WDT enabled/disabled status.

Detailed Description

These protocols and PPI allow a platform module to perform watch dog timer operations through the Intel PCH LPC Host Controller Interface.

The WDT protocol and WDT PPI implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively. WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they share the identical data structure.

Definition at line 130 of file Protocol/Wdt.h.

The documentation for this struct was generated from the following file:
  • Protocol/Wdt.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

_WDT_PROTOCOL Member List

This is the complete list of members for _WDT_PROTOCOL, including all inherited members.

AllowKnownReset | _WDT_PROTOCOL
CheckStatus | _WDT_PROTOCOL
Disable | _WDT_PROTOCOL
IsWdtEnabled | _WDT_PROTOCOL
IsWdtRequired | _WDT_PROTOCOL
ReloadAndStart | _WDT_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ADR_CONFIG Struct Reference

Public Attributes | List of all members
ADR_CONFIG Struct Reference

ADR Configuration Revision 1: - Initial version. More...

#include <AdrConfig.h>

Collaboration diagram for ADR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AdrEn: 2
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimerEn: 2
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrTimer1Val: 8
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
UINT32 | AdrMultiplier1Val: 3
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrTimer2Val: 8
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
UINT32 | AdrMultiplier2Val: 3
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values.
UINT32 | AdrHostPartitionReset: 2
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
UINT32 | AdrSrcOverride: 1
Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten.
UINT32 | AdrPlatAckEn: 2
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
ADR_SOURCE_ENABLE AdrSrcSel
Determine which ADR sources are enabled - 0: Enabled, 1: Disabled.

Detailed Description

ADR Configuration Revision 1: - Initial version.

Definition at line 97 of file AdrConfig.h.

The documentation for this struct was generated from the following file:
  • AdrConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ADR_CONFIG Member List

This is the complete list of members for ADR_CONFIG, including all inherited members.

AdrEn | ADR_CONFIG
AdrHostPartitionReset | ADR_CONFIG
AdrMultiplier1Val | ADR_CONFIG
AdrMultiplier2Val | ADR_CONFIG
AdrPlatAckEn | ADR_CONFIG
AdrSrcOverride | ADR_CONFIG
AdrSrcSel | ADR_CONFIG
AdrTimer1Val | ADR_CONFIG
AdrTimer2Val | ADR_CONFIG
AdrTimerEn | ADR_CONFIG
Header | ADR_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ADR_SOURCE_ENABLE Union Reference

List of all members
ADR_SOURCE_ENABLE Union Reference

ADR Source Enable. More...

#include <AdrConfig.h>

Detailed Description

ADR Source Enable.

Definition at line 59 of file AdrConfig.h.

The documentation for this union was generated from the following file:
  • AdrConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ADR_SOURCE_ENABLE Member List

This is the complete list of members for ADR_SOURCE_ENABLE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ALERT_STANDARD_FORMAT_PROTOCOL Struct Reference

List of all members
ALERT_STANDARD_FORMAT_PROTOCOL Struct Reference

Intel specific definitions end. More...

#include <AsfProtocol.h>

Collaboration diagram for ALERT_STANDARD_FORMAT_PROTOCOL:
[legend]

Detailed Description

Intel specific definitions end.

Alert Standard Format Protocol This protocol provides interfaces to get ASF Boot Options HECI protocol is consumed and used to send ASF messages and receive ASF Boot Options

Definition at line 116 of file AsfProtocol.h.

The documentation for this struct was generated from the following file:
  • AsfProtocol.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ALERT_STANDARD_FORMAT_PROTOCOL Member List

This is the complete list of members for ALERT_STANDARD_FORMAT_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_DXE_CONFIG Struct Reference

Public Attributes | List of all members
AMT_DXE_CONFIG Struct Reference

AMT Dxe Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | CiraRequest: 1
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
UINT32 | UnConfigureMe: 1
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME without password.
UINT32 | MebxDebugMsg: 1
UINT32 | HideUnConfigureMeConfirm: 1
UINT32 | UsbProvision: 1
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
UINT32 | AmtbxHotkeyPressed: 1
UINT32 | AmtbxSelectionScreen: 1
OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens Press 2 to initiate a remote connection. More...
UINT32 | RsvdBits: 25
Reserved for future use & Config block alignment.
UINT32 | CiraTimeout: 8
UINT32 | CpuReplacementTimeout: 8
CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay. More...
UINT32 | MebxNonUiTextMode: 4
UINT32 | MebxUiTextMode: 4
UINT32 | MebxGraphicsMode: 4
UINT32 | OemResolutionSettingsRsvd: 4
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.

Detailed Description

AMT Dxe Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 134 of file AmtConfig.h.

Member Data Documentation

◆ AmtbxHotkeyPressed

UINT32 AMT_DXE_CONFIG::AmtbxHotkeyPressed
Deprecated:
: OEMFlag Bit 1: Enable automatic MEBx hotkey press. 0: Disable; 1: Enable

Definition at line 141 of file AmtConfig.h.

◆ AmtbxSelectionScreen

UINT32 AMT_DXE_CONFIG::AmtbxSelectionScreen

OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens Press 2 to initiate a remote connection.

  • 0: Disabled
  • 1: Enabled
    Deprecated:

Definition at line 149 of file AmtConfig.h.

◆ CiraTimeout

UINT32 AMT_DXE_CONFIG::CiraTimeout
Deprecated:

Definition at line 151 of file AmtConfig.h.

◆ CpuReplacementTimeout

UINT32 AMT_DXE_CONFIG::CpuReplacementTimeout

CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay.

Deprecated:

Definition at line 160 of file AmtConfig.h.

◆ HideUnConfigureMeConfirm

UINT32 AMT_DXE_CONFIG::HideUnConfigureMeConfirm
Deprecated:
: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. 0: Don't hide; 1: Hide

Definition at line 139 of file AmtConfig.h.

◆ MebxDebugMsg

UINT32 AMT_DXE_CONFIG::MebxDebugMsg
Deprecated:
: OEMFlag Bit 14: Enable OEM debug menu in MEBx. 0: Disable; 1: Enable

Definition at line 138 of file AmtConfig.h.

◆ MebxGraphicsMode

UINT32 AMT_DXE_CONFIG::MebxGraphicsMode
Deprecated:
: Resolution for graphics mode. 0: Auto; 1: 640x480; 2: 800x600; 3: 1024x768

Definition at line 163 of file AmtConfig.h.

◆ MebxNonUiTextMode

UINT32 AMT_DXE_CONFIG::MebxNonUiTextMode
Deprecated:
: Resolution for non-UI text mode. 0: Auto; 1: 80x25; 2: 100x31

Definition at line 161 of file AmtConfig.h.

◆ MebxUiTextMode

UINT32 AMT_DXE_CONFIG::MebxUiTextMode
Deprecated:
: Resolution for UI text mode. 0: Auto; 1: 80x25; 2: 100x31

Definition at line 162 of file AmtConfig.h.

◆ OemResolutionSettingsRsvd

UINT32 AMT_DXE_CONFIG::OemResolutionSettingsRsvd
Deprecated:
: Reserved for future use & Config block alignment

Definition at line 164 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_DXE_CONFIG Member List

This is the complete list of members for AMT_DXE_CONFIG, including all inherited members.

AmtbxHotkeyPressed | AMT_DXE_CONFIG
AmtbxSelectionScreen | AMT_DXE_CONFIG
AmtReportError | AMT_DXE_CONFIG
CiraRequest | AMT_DXE_CONFIG
CiraTimeout | AMT_DXE_CONFIG
CpuReplacementTimeout | AMT_DXE_CONFIG
Header | AMT_DXE_CONFIG
HideUnConfigureMeConfirm | AMT_DXE_CONFIG
MebxDebugMsg | AMT_DXE_CONFIG
MebxGraphicsMode | AMT_DXE_CONFIG
MebxNonUiTextMode | AMT_DXE_CONFIG
MebxUiTextMode | AMT_DXE_CONFIG
OemResolutionSettingsRsvd | AMT_DXE_CONFIG
RsvdBits | AMT_DXE_CONFIG
UnConfigureMe | AMT_DXE_CONFIG
UsbProvision | AMT_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_GET_ACTIVE_LAN_INTERFACE Struct Reference

Public Attributes | List of all members
AMT_GET_ACTIVE_LAN_INTERFACE Struct Reference

Get Active LAN Interface Request Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_GET_ACTIVE_LAN_INTERFACE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Get Active LAN Interface Request Structure.

Definition at line 650 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_GET_ACTIVE_LAN_INTERFACE Member List

This is the complete list of members for AMT_GET_ACTIVE_LAN_INTERFACE, including all inherited members.

AsfHeader AMT_GET_ACTIVE_LAN_INTERFACE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER Union Reference

List of all members
AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER Union Reference

Get Active LAN Interface Union Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER:
[legend]

Detailed Description

Get Active LAN Interface Union Buffer.

Definition at line 667 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER Member List

This is the complete list of members for AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE Struct Reference

Public Attributes | List of all members
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE Struct Reference

Get Active LAN Interface Response Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT32 | Status
Response status.
UINT8 | ActiveInterface
0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.
UINT32 | Reserved [4]
Reserved for future use.

Detailed Description

Get Active LAN Interface Response Structure.

Definition at line 657 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE Member List

This is the complete list of members for AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE, including all inherited members.

ActiveInterface | AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
AsfHeader | AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
Reserved | AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
Status | AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_PEI_CONFIG Struct Reference

Public Attributes | List of all members
AMT_PEI_CONFIG Struct Reference

AMT Pei Configuration Structure. More...

#include <AmtConfig.h>

Collaboration diagram for AMT_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AmtEnabled: 1
Enable or Disable Intel Active Management Technology feature. More...
UINT32 | WatchDogEnabled: 1
ME WatchDog timer feature. More...
UINT32 | FwProgress: 1
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
UINT32 | ManageabilityMode: 1
UINT32 | AmtSolEnabled: 1
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable
UINT32 | RemoteAssistance: 1
UINT32 | AmtKvmEnabled: 1
UINT32 | ForcMebxSyncUp: 1
0: No; 1: Force MEBX execution
UINT32 | RsvdBits: 24
Reserved for future use & Config block alignment.
UINT16 | WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1. More...
UINT16 | WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1. More...

Detailed Description

AMT Pei Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 89 of file AmtConfig.h.

Member Data Documentation

◆ AmtEnabled

UINT32 AMT_PEI_CONFIG::AmtEnabled

Enable or Disable Intel Active Management Technology feature.

If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported. 0: Disable 1: Enable.

Definition at line 97 of file AmtConfig.h.

◆ AmtKvmEnabled

UINT32 AMT_PEI_CONFIG::AmtKvmEnabled
Deprecated:
: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, 1: Enable

Definition at line 109 of file AmtConfig.h.

◆ ManageabilityMode

UINT32 AMT_PEI_CONFIG::ManageabilityMode
Deprecated:
: Manageability Mode sync with Mebx, 0: Disabled; 1: AMT

Definition at line 106 of file AmtConfig.h.

◆ RemoteAssistance

UINT32 AMT_PEI_CONFIG::RemoteAssistance
Deprecated:
: Remote Assistance is enabled if platform is provisioned. 0: Disable, 1: Enable

Definition at line 108 of file AmtConfig.h.

◆ WatchDogEnabled

UINT32 AMT_PEI_CONFIG::WatchDogEnabled

ME WatchDog timer feature.

If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant. See WatchDogTimerOs and WatchDogTimerBios description. 0: Disable 1: Enable ME WDT if corresponding timer value is not zero.

Definition at line 104 of file AmtConfig.h.

◆ WatchDogTimerBios

UINT16 AMT_PEI_CONFIG::WatchDogTimerBios

BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.

Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.

Definition at line 124 of file AmtConfig.h.

◆ WatchDogTimerOs

UINT16 AMT_PEI_CONFIG::WatchDogTimerOs

OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.

Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set according to the value.

Definition at line 118 of file AmtConfig.h.

The documentation for this struct was generated from the following file:
  • AmtConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_PEI_CONFIG Member List

This is the complete list of members for AMT_PEI_CONFIG, including all inherited members.

AmtEnabled | AMT_PEI_CONFIG
AmtKvmEnabled | AMT_PEI_CONFIG
AmtSolEnabled | AMT_PEI_CONFIG
ForcMebxSyncUp | AMT_PEI_CONFIG
FwProgress | AMT_PEI_CONFIG
Header | AMT_PEI_CONFIG
ManageabilityMode | AMT_PEI_CONFIG
RemoteAssistance | AMT_PEI_CONFIG
RsvdBits | AMT_PEI_CONFIG
WatchDogEnabled | AMT_PEI_CONFIG
WatchDogTimerBios | AMT_PEI_CONFIG
WatchDogTimerOs | AMT_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_PET_QUEUE_HOB Struct Reference

Public Attributes | List of all members
AMT_PET_QUEUE_HOB Struct Reference

Queue Hob. More...

#include <AmtPetQueueHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
The GUID type hob header.
EFI_STATUS_CODE_VALUE | Value
Status code value.
EFI_STATUS_CODE_TYPE | Type
Status code type.

Detailed Description

Queue Hob.

This hob is used by PEI Status Code generic driver before Intel AMT PEI status code driver starts. 1) If AMT driver is not ready yet, StatusCode driver can save information to QueueHob. 2) If after AMT driver start, but ME is not ready, the AMT driver can also save information to QueueHob. Later, when ME is ready, AMT driver will send all the message in the QueueHob.

Definition at line 50 of file AmtPetQueueHob.h.

The documentation for this struct was generated from the following file:
  • AmtPetQueueHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_PET_QUEUE_HOB Member List

This is the complete list of members for AMT_PET_QUEUE_HOB, including all inherited members.

EfiHobGuidType | AMT_PET_QUEUE_HOB
Type | AMT_PET_QUEUE_HOB
Value | AMT_PET_QUEUE_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_QUERY_KVM Struct Reference

Public Attributes | List of all members
AMT_QUERY_KVM Struct Reference

Query KVM Request Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_QUERY_KVM:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT32 QueryType
KVM Session Query Type. More...

Detailed Description

Query KVM Request Structure.

Definition at line 715 of file AsfMsgs.h.

Member Data Documentation

◆ QueryType

UINT32 AMT_QUERY_KVM::QueryType

KVM Session Query Type.

0x00: Query the KVM session request 0x01: Cancel the KVM session request

Definition at line 722 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_QUERY_KVM Member List

This is the complete list of members for AMT_QUERY_KVM, including all inherited members.

AsfHeader | AMT_QUERY_KVM
QueryType | AMT_QUERY_KVM
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_QUERY_KVM_BUFFER Union Reference

List of all members
AMT_QUERY_KVM_BUFFER Union Reference

Query KVM Union Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_QUERY_KVM_BUFFER:
[legend]

Detailed Description

Query KVM Union Buffer.

Definition at line 728 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_QUERY_KVM_BUFFER Member List

This is the complete list of members for AMT_QUERY_KVM_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_QUERY_KVM_RESPONSE Struct Reference

Public Attributes | List of all members
AMT_QUERY_KVM_RESPONSE Struct Reference

Query KVM Response Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_QUERY_KVM_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT32 ResponseCode
Response Code of KVM Session Status. More...

Detailed Description

Query KVM Response Structure.

Definition at line 694 of file AsfMsgs.h.

Member Data Documentation

◆ ResponseCode

UINT32 AMT_QUERY_KVM_RESPONSE::ResponseCode

Response Code of KVM Session Status.

0x01: the KVM session established 0x02: the KVM session cancelled

Definition at line 701 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_QUERY_KVM_RESPONSE Member List

This is the complete list of members for AMT_QUERY_KVM_RESPONSE, including all inherited members.

AsfHeader | AMT_QUERY_KVM_RESPONSE
ResponseCode | AMT_QUERY_KVM_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SCREEN_RESOLUTION Struct Reference

List of all members
AMT_SCREEN_RESOLUTION Struct Reference

Get GFX UI Info/Fragment. More...

#include <AmthiMsgs.h>

Detailed Description

Get GFX UI Info/Fragment.

Definition at line 1107 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SCREEN_RESOLUTION Member List

This is the complete list of members for AMT_SCREEN_RESOLUTION, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SET_ACTIVE_LAN_INTERFACE Struct Reference

Public Attributes | List of all members
AMT_SET_ACTIVE_LAN_INTERFACE Struct Reference

Set Active LAN Interface Request Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_SET_ACTIVE_LAN_INTERFACE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT8 ActiveInterface
0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.

Detailed Description

Set Active LAN Interface Request Structure.

Definition at line 625 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SET_ACTIVE_LAN_INTERFACE Member List

This is the complete list of members for AMT_SET_ACTIVE_LAN_INTERFACE, including all inherited members.

ActiveInterface | AMT_SET_ACTIVE_LAN_INTERFACE
AsfHeader | AMT_SET_ACTIVE_LAN_INTERFACE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER Union Reference

List of all members
AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER Union Reference

Set Active LAN Interface Union Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER:
[legend]

Detailed Description

Set Active LAN Interface Union Buffer.

Definition at line 641 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER Member List

This is the complete list of members for AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE Struct Reference

Public Attributes | List of all members
AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE Struct Reference

Set Active LAN Interface Response Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT32 Status
Response status.

Detailed Description

Set Active LAN Interface Response Structure.

Definition at line 633 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE Member List

This is the complete list of members for AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE, including all inherited members.

AsfHeader | AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE
Status | AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SET_MAC_PASSTHROUGH_BUFFER Union Reference

List of all members
AMT_SET_MAC_PASSTHROUGH_BUFFER Union Reference

Set MAC Passthrough Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_SET_MAC_PASSTHROUGH_BUFFER:
[legend]

Detailed Description

Set MAC Passthrough Buffer.

Definition at line 756 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SET_MAC_PASSTHROUGH_BUFFER Member List

This is the complete list of members for AMT_SET_MAC_PASSTHROUGH_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AMT_SET_MAC_PASSTHROUGH_RESPONSE Struct Reference

Public Attributes | List of all members
AMT_SET_MAC_PASSTHROUGH_RESPONSE Struct Reference

Set MAC Passthrough. More...

#include <AsfMsgs.h>

Collaboration diagram for AMT_SET_MAC_PASSTHROUGH_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Set MAC Passthrough.

Definition at line 740 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

AMT_SET_MAC_PASSTHROUGH_RESPONSE Member List

This is the complete list of members for AMT_SET_MAC_PASSTHROUGH_RESPONSE, including all inherited members.

AsfHeader AMT_SET_MAC_PASSTHROUGH_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ARB_SVN_COMMIT Struct Reference

Public Attributes | List of all members
ARB_SVN_COMMIT Struct Reference

HW Anti-Rollback (ARB) Security Version Number Commit. More...

#include <MkhiMsgs.h>

Collaboration diagram for ARB_SVN_COMMIT:
[legend]

Public Attributes

UINT8 Reserved [3]
Reserved for future use, to allow specifying explicit usage to be committed.

Detailed Description

HW Anti-Rollback (ARB) Security Version Number Commit.

Definition at line 787 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ARB_SVN_COMMIT Member List

This is the complete list of members for ARB_SVN_COMMIT, including all inherited members.

Reserved ARB_SVN_COMMIT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ARB_SVN_GET_INFO Struct Reference

List of all members
ARB_SVN_GET_INFO Struct Reference

HW Anti-Rollback (ARB) Security Version Number Get Info. More...

#include <MkhiMsgs.h>

Collaboration diagram for ARB_SVN_GET_INFO:
[legend]

Detailed Description

HW Anti-Rollback (ARB) Security Version Number Get Info.

Definition at line 805 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ARB_SVN_GET_INFO Member List

This is the complete list of members for ARB_SVN_GET_INFO, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_BOOT_OPTIONS Struct Reference

Public Attributes | List of all members
ASF_BOOT_OPTIONS Struct Reference

Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message. More...

#include <AsfMsgs.h>

Public Attributes

UINT8 | SubCommand
ASF Message Sub-command. More...
UINT8 | Version
Default value is 0x10 to indicate ASF Specification Version.
UINT32 | IanaId
IANA-assigned Enterprise Number. More...
UINT8 | SpecialCommand
Defines commands to be processed by the managed client on the boot initiated by the ASF-RMCP message. More...
UINT8 | SpecialCommandParamHighByte
Defines a command parameter to augment the Special Command High Byte.
UINT8 | SpecialCommandParamLowByte
Defines a command parameter to augment the Special Command Low Byte.
UINT8 | BootOptionsMaskByte1
Defines a standard set of firmware operations.
UINT8 | BootOptionsMaskByte2
Defines a standard set of firmware operations.
UINT8 | OemParameterByte1
Defines parameters that further augment the Special Command definition.
UINT8 | OemParameterByte2
Defines parameters that further augment the Special Command definition.

Detailed Description

Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message.

Definition at line 136 of file AsfMsgs.h.

Member Data Documentation

◆ IanaId

UINT32 ASF_BOOT_OPTIONS::IanaId

IANA-assigned Enterprise Number.

0x000011BE: IANA Enterprise Number for ASF 0x00000157: IANA Enterprise Number for Intel

Definition at line 149 of file AsfMsgs.h.

◆ SpecialCommand

UINT8 ASF_BOOT_OPTIONS::SpecialCommand

Defines commands to be processed by the managed client on the boot initiated by the ASF-RMCP message.

0x00: NOP 0x01: Force PXE Boot 0x02: Force Hard-drive Boot 0x03: Force Hard-drive Safe Mode Boot 0x04: Force Diagnostic Boot 0x05: Force CD/DVD Boot 0x06-0xBF: Reserved 0xC0-0xFF: OEM special commands 0xC1: Intel special command

Definition at line 162 of file AsfMsgs.h.

◆ SubCommand

UINT8 ASF_BOOT_OPTIONS::SubCommand

ASF Message Sub-command.

0x16: Return boot option 0x17: No boot option

Definition at line 142 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_BOOT_OPTIONS Member List

This is the complete list of members for ASF_BOOT_OPTIONS, including all inherited members.

BootOptionsMaskByte1 | ASF_BOOT_OPTIONS
BootOptionsMaskByte2 | ASF_BOOT_OPTIONS
IanaId | ASF_BOOT_OPTIONS
OemParameterByte1 | ASF_BOOT_OPTIONS
OemParameterByte2 | ASF_BOOT_OPTIONS
SpecialCommand | ASF_BOOT_OPTIONS
SpecialCommandParamHighByte | ASF_BOOT_OPTIONS
SpecialCommandParamLowByte | ASF_BOOT_OPTIONS
SubCommand | ASF_BOOT_OPTIONS
Version | ASF_BOOT_OPTIONS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_DATA_HUB_MAP Struct Reference

Public Attributes | List of all members
ASF_DATA_HUB_MAP Struct Reference

Data Hub of ASF Progress Status. More...

#include <AsfMsgs.h>

Public Attributes

ASF_FRAMEWORK_MESSAGE_TYPE | MessageType
ASF Message Type.
EFI_STATUS_CODE_VALUE | StatusCodeValue
Platform Progress Status Code.

Detailed Description

Data Hub of ASF Progress Status.

Definition at line 503 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_DATA_HUB_MAP Member List

This is the complete list of members for ASF_DATA_HUB_MAP, including all inherited members.

MessageType | ASF_DATA_HUB_MAP
StatusCodeValue | ASF_DATA_HUB_MAP
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_FRAMEWORK_MESSAGE Struct Reference

Public Attributes | List of all members
ASF_FRAMEWORK_MESSAGE Struct Reference

ASF Framework Message. More...

#include <AsfMsgs.h>

Collaboration diagram for ASF_FRAMEWORK_MESSAGE:
[legend]

Public Attributes

ASF_FRAMEWORK_MESSAGE_TYPE MessageType
ASF Message Type.
ASF_MESSAGE Message
ASF Message Instance.

Detailed Description

ASF Framework Message.

Definition at line 495 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_FRAMEWORK_MESSAGE Member List

This is the complete list of members for ASF_FRAMEWORK_MESSAGE, including all inherited members.

Message | ASF_FRAMEWORK_MESSAGE
MessageType | ASF_FRAMEWORK_MESSAGE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_MESSAGE Struct Reference

Public Attributes | List of all members
ASF_MESSAGE Struct Reference

ASF Message. More...

#include <AsfMsgs.h>

Public Attributes

UINT8 | SubCommand
ASF Message Sub-command.
UINT8 | Version
ASF Specification Version.
UINT8 | EventSensorType
The Event Sensor Type field indicates what types of events the sensor is monitoring.
UINT8 | EventType
Code indicating what type of transition/state change triggered the trap.
UINT8 | EventOffset
Indicates which particular event occurred for a given Event Type.
UINT8 | EventSourceType
Class of device or type of software that originated the event.
UINT8 | EventSeverity
Severity of the event.
UINT8 | SensorDevice
Identifies the instance of the device that holds the sensor that generated the event.
UINT8 | SensorNumber
Identify a given instance of a sensor relative to the Sensor Device.
UINT8 | Entity
Indicates the platform entity the event is associated with.
UINT8 | EntityInstance
Indicates which instance of the Entity the event is for.
UINT8 | EventData1
Additional parametric data 1.
UINT8 | EventData2
Additional parametric data 2.

Detailed Description

ASF Message.

Definition at line 466 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_MESSAGE Member List

This is the complete list of members for ASF_MESSAGE, including all inherited members.

Entity | ASF_MESSAGE
EntityInstance | ASF_MESSAGE
EventData1 | ASF_MESSAGE
EventData2 | ASF_MESSAGE
EventOffset | ASF_MESSAGE
EventSensorType | ASF_MESSAGE
EventSeverity | ASF_MESSAGE
EventSourceType | ASF_MESSAGE
EventType | ASF_MESSAGE
SensorDevice | ASF_MESSAGE
SensorNumber | ASF_MESSAGE
SubCommand | ASF_MESSAGE
Version | ASF_MESSAGE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_MESSAGE_HEADER Union Reference

List of all members
ASF_MESSAGE_HEADER Union Reference

Abstract ASF message header. More...

#include <AsfMsgs.h>

Detailed Description

Abstract ASF message header.

This header is part of HECI message sent from BIOS to AMT/ASF ME Client

Definition at line 60 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_MESSAGE_HEADER Member List

This is the complete list of members for ASF_MESSAGE_HEADER, including all inherited members.

ByteCount | ASF_MESSAGE_HEADER
Command | ASF_MESSAGE_HEADER
SubCommand | ASF_MESSAGE_HEADER
VersionNumber | ASF_MESSAGE_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_PROFILE_MESSAGE_HEADER Struct Reference

Public Attributes | List of all members
ASF_PROFILE_MESSAGE_HEADER Struct Reference

ASF Message header with profile name char array as data. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for ASF_PROFILE_MESSAGE_HEADER:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
CHAR8 Data [PROFILE_NAME_SIZE]
ASF Data Request.

Detailed Description

ASF Message header with profile name char array as data.

Definition at line 61 of file WifiProfileSyncAsfMsgs.h.

The documentation for this struct was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_PROFILE_MESSAGE_HEADER Member List

This is the complete list of members for ASF_PROFILE_MESSAGE_HEADER, including all inherited members.

AsfHeader | ASF_PROFILE_MESSAGE_HEADER
Data | ASF_PROFILE_MESSAGE_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_START_WDT Struct Reference

Public Attributes | List of all members
ASF_START_WDT Struct Reference

Start Watchdog Timer Message Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for ASF_START_WDT:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT8 | TimeoutLow
Low byte of watchdog timeout value in seconds.
UINT8 | TimeoutHigh
High byte of watchdog timeout value in seconds.
UINT8 | EventSensorType
Default value is 0x23 to indicate it is for Watchdog 2.
UINT8 | EventType
Default value is 0x6F to indicate it is Sensor specific.
UINT8 | EventOffset
Default value is 0x00 to indicate it is for Timer expired.
UINT8 | EventSourceType
Class of device or type of software that originated the event. More...
UINT8 | EventSeverity
Default value is 0x10 to indicate it is Critical.
UINT8 | SensorDevice
Default value is 0xFF to indicate it is Unspecified.
UINT8 | SensorNumber
Default value is 0xFF to indicate it is Unspecified.
UINT8 | Entity
Default value is 0x00 to indicate it is Unspecified.
UINT8 | EntityInstance
Default value is 0x00 to indicate it is Unspecified.
UINT8 | EventData [5]
Additional parametric data byte. More...

Detailed Description

Start Watchdog Timer Message Structure.

This structure is only used for Starting Watchdog Timer Message. Elements' description is based on Start Watchdog Timer.

Definition at line 85 of file AsfMsgs.h.

Member Data Documentation

◆ EventData

UINT8 ASF_START_WDT::EventData[5]

Additional parametric data byte.

BYTE 0: 0x40 BYTE 1: 0x02, BIOS POST WDT Timeout 0x04, OS WDT Timeout BYTE 2-4: Not defined.

Definition at line 110 of file AsfMsgs.h.

◆ EventSourceType

UINT8 ASF_START_WDT::EventSourceType

Class of device or type of software that originated the event.

0x00: Platform firmware 0x48: OS vendor

Definition at line 97 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_START_WDT Member List

This is the complete list of members for ASF_START_WDT, including all inherited members.

AsfHeader | ASF_START_WDT
Entity | ASF_START_WDT
EntityInstance | ASF_START_WDT
EventData | ASF_START_WDT
EventOffset | ASF_START_WDT
EventSensorType | ASF_START_WDT
EventSeverity | ASF_START_WDT
EventSourceType | ASF_START_WDT
EventType | ASF_START_WDT
SensorDevice | ASF_START_WDT
SensorNumber | ASF_START_WDT
TimeoutHigh | ASF_START_WDT
TimeoutLow | ASF_START_WDT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ASF_STOP_WDT Struct Reference

Public Attributes | List of all members
ASF_STOP_WDT Struct Reference

Stop Watchdog Timer Message Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for ASF_STOP_WDT:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Stop Watchdog Timer Message Structure.

Definition at line 116 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ASF_STOP_WDT Member List

This is the complete list of members for ASF_STOP_WDT, including all inherited members.

AsfHeader ASF_STOP_WDT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BCLK_CONFIG Struct Reference

Public Attributes | List of all members
BCLK_CONFIG Struct Reference

BCLK configuration. More...

#include <PmConfig.h>

Collaboration diagram for BCLK_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | SocBclkPllOn
Controls enable status of SOC BCLK. More...
UINT8 | CpuBclkPllOn
Controls enable status of CPU BCLK. More...

Detailed Description

BCLK configuration.

Only available on projects with SOC and CPU BCLK supported.

Definition at line 468 of file PmConfig.h.

Member Data Documentation

◆ CpuBclkPllOn

UINT8 BCLK_CONFIG::CpuBclkPllOn

Controls enable status of CPU BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 480 of file PmConfig.h.

◆ SocBclkPllOn

UINT8 BCLK_CONFIG::SocBclkPllOn

Controls enable status of SOC BCLK.

0: HW default, 1: Force enable, 2: Force disable

Definition at line 475 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BCLK_CONFIG Member List

This is the complete list of members for BCLK_CONFIG, including all inherited members.

CpuBclkPllOn | BCLK_CONFIG
Header | BCLK_CONFIG
SocBclkPllOn | BCLK_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BDAT_ACCESS_PROTOCOL Struct Reference

List of all members
BDAT_ACCESS_PROTOCOL Struct Reference

BDAT access protocol - For accessing some data generated by MRC or PCIe modules. More...

#include <BdatAccess.h>

Detailed Description

BDAT access protocol - For accessing some data generated by MRC or PCIe modules.

Definition at line 41 of file BdatAccess.h.

The documentation for this struct was generated from the following file:
  • BdatAccess.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BDAT_ACCESS_PROTOCOL Member List

This is the complete list of members for BDAT_ACCESS_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BDAT_SCHEMA_LIST_HOB Struct Reference

Public Attributes | List of all members
BDAT_SCHEMA_LIST_HOB Struct Reference

Not strictly part of the BDAT spec. More...

#include <Bdat4.h>

Public Attributes

UINT16 | SchemaHobCount
SchemaHobCount : Number of HOBs that exist which contain data that should be copied to the BDAT structure.
EFI_GUID | SchemaHobGuids [MAX_SCHEMA_LIST_LENGTH]
SchemaHobGuids : Array of GUIDs which identify HOBs that contain data that should be copied into the BDAT structure. More...

Detailed Description

Not strictly part of the BDAT spec.

This HOB is used to identify which HOBs contain data that should be copied into the final BDAT structure as a schema

Definition at line 99 of file Bdat4.h.

Member Data Documentation

◆ SchemaHobGuids

EFI_GUID BDAT_SCHEMA_LIST_HOB::SchemaHobGuids[MAX_SCHEMA_LIST_LENGTH]

SchemaHobGuids : Array of GUIDs which identify HOBs that contain data that should be copied into the BDAT structure.

The contents of the HOB contains a schema. The GUID for the HOB is the same as the SchemaId GUID.

Definition at line 113 of file Bdat4.h.

The documentation for this struct was generated from the following file:
  • Bdat4.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BDAT_SCHEMA_LIST_HOB Member List

This is the complete list of members for BDAT_SCHEMA_LIST_HOB, including all inherited members.

SchemaHobCount | BDAT_SCHEMA_LIST_HOB
SchemaHobGuids | BDAT_SCHEMA_LIST_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BGPDT Struct Reference

Public Attributes | List of all members
BGPDT Struct Reference

BIOS Guard Platform Data Table (BGPDT) Provides platform specific data required by BIOS Guard Module. More...

#include <BiosGuard.h>

Collaboration diagram for BGPDT:
[legend]

Public Attributes

UINT32 | BgpdtSize
Size in bytes of BGPDT including SFAM.
UINT16 | BgpdtMajVer
Indicates major version of BGPDT.
UINT16 | BgpdtMinVer
Indicates minor version of BGPDT.
UINT8 | PlatId [16]
PLAT_ID used to be compared against the one found in the BGUP Header to prevent cross platform flashing.
UINT8 | PkeySlot0 [32]
SHA256 hash for BGUP verification key 0.
UINT8 | PkeySlot1 [32]
SHA256 hash for BGUP verification key 1.
UINT8 | PkeySlot2 [32]
SHA256 hash for BGUP verification key 2.
UINT32 | BgModSvn
BIOS Guard Module SVN.
UINT32 | BiosSvn
BIOS_SVN to prevent back-flashing.
UINT32 | ExecLim
Limit the number of opcodes that can be executed on any invocation of BIOS Guard.
UINT32 | BiosGuardAttr
Bitmap of Policy attributes. More...
UINT32 | EcCmd
Read/Write command sent to EC. More...
UINT32 | EcData
Data read or written to EC. More...
UINT32 | EcCmdGetSvn
EC command indicating a read of the current EC firmware SVN. More...
UINT32 | EcCmdOpen
EC command indicating begin of flash update session. More...
UINT32 | EcCmdClose
EC command indicating the termination of BIOS Guard protected session. More...
UINT32 | EcCmdPortTest
EC command used to verify connectivity between BIOS Guard and EC. More...
UINT8 | Reserved1 [4]
Reserved bits.
UINT8 | LastSfam
Defines number of elements in SFAM array. More...
UINT8 | Reserved2 [3]
Reserved 3 bits.
SFAM_DATA SfamData [MAX_SFAM_COUNT]
Array of flash address map descriptors. sizeof (SFAM_DATA) == 8.

Detailed Description

BIOS Guard Platform Data Table (BGPDT) Provides platform specific data required by BIOS Guard Module.

Definition at line 159 of file BiosGuard.h.

Member Data Documentation

◆ BiosGuardAttr

UINT32 BGPDT::BiosGuardAttr

Bitmap of Policy attributes.

  • BIT[0]: Reserved. Must be 0
  • BIT[2:1]: EC_PRESENT
    • 00b = EC does not exist in the system.
    • 01b = There exists an EC in the system, BIOS Guard does not extend any protection to the EC.
    • 11b = There exist an EC in the system, BIOS Guard extends protection to the EC.
    • 10b = Reserved. Must not be used.
  • BIT[3]: DESCRIPTOR_OVERRIDE_POLICY
    • 0b = Do not override BIOS Guard security policy.
    • 1b = Override BIOS Guard security policy.
  • BIT[4]: FLASH_WEAROUT_POLICY
    • 0b = Legacy BIOS Guard behavior.
    • 1b = Enable Flash Wear-Out Protection mitigation.
  • BIT[5]: FTU_ENABLE
    • 0b = Legacy BIOS Guard behavior.
    • 1b = Enable fault tolerant update.
  • BIT[23:6]: Reserved, must be 0
  • BIT[31:24]: Reserved for platform specific definition. Must be 0 if not defined.

Definition at line 190 of file BiosGuard.h.

◆ EcCmd

UINT32 BGPDT::EcCmd

Read/Write command sent to EC.

  • BIT[9:0]: 8 bit IO port used for sending EC commands (writes), and reading EC status (reads).
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:10]: Reserved. Must be 0.

Definition at line 198 of file BiosGuard.h.

◆ EcCmdClose

UINT32 BGPDT::EcCmdClose

EC command indicating the termination of BIOS Guard protected session.

  • BIT[7:0]: EC command indicating the termination of BIOS Guard protected session.
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:8]: Reserved. Must be 0.

Definition at line 230 of file BiosGuard.h.

◆ EcCmdGetSvn

UINT32 BGPDT::EcCmdGetSvn

EC command indicating a read of the current EC firmware SVN.

  • BIT[7:0]: EC command.
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:8]: Reserved. Must be 0.

Definition at line 214 of file BiosGuard.h.

◆ EcCmdOpen

UINT32 BGPDT::EcCmdOpen

EC command indicating begin of flash update session.

  • BIT[7:0]: EC command.
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:8]: Reserved. Must be 0.

Definition at line 222 of file BiosGuard.h.

◆ EcCmdPortTest

UINT32 BGPDT::EcCmdPortTest

EC command used to verify connectivity between BIOS Guard and EC.

  • BIT[7:0]: EC command.
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:8]: Reserved. Must be 0.

Definition at line 238 of file BiosGuard.h.

◆ EcData

UINT32 BGPDT::EcData

Data read or written to EC.

  • BIT[9:0]: 8 bit IO port used for reading and writing data to the EC based on a command issued to EC_CMD.
    • This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
    • This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
  • BIT[31:10]: Reserved. Must be 0

Definition at line 206 of file BiosGuard.h.

◆ LastSfam

UINT8 BGPDT::LastSfam

Defines number of elements in SFAM array.

  • BIT[5..0]: Index of the last SFAM element
  • BIT[7..6]: Reserved for future use. Must be 0

Definition at line 245 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BGPDT Member List

This is the complete list of members for BGPDT, including all inherited members.

BgModSvn | BGPDT
BgpdtMajVer | BGPDT
BgpdtMinVer | BGPDT
BgpdtSize | BGPDT
BiosGuardAttr | BGPDT
BiosSvn | BGPDT
EcCmd | BGPDT
EcCmdClose | BGPDT
EcCmdGetSvn | BGPDT
EcCmdOpen | BGPDT
EcCmdPortTest | BGPDT
EcData | BGPDT
ExecLim | BGPDT
LastSfam | BGPDT
PkeySlot0 | BGPDT
PkeySlot1 | BGPDT
PkeySlot2 | BGPDT
PlatId | BGPDT
Reserved1 | BGPDT
Reserved2 | BGPDT
SfamData | BGPDT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BGUP Struct Reference

Public Attributes | List of all members
BGUP Struct Reference

BIOS Guard update package definition for BIOS SMM Initiated runtime calls. More...

#include <BiosGuard.h>

Collaboration diagram for BGUP:
[legend]

Public Attributes

BGUP_HEADER BgupHeader
BIOS Guard update package header.
UINT64 BgupBuffer [BGUP_TSEG_BUFFER_SIZE/8]
BIOS Guard update buffer - Designed to contain the BIOS Guard Script followed immediately by the Update Data.

Detailed Description

BIOS Guard update package definition for BIOS SMM Initiated runtime calls.

Definition at line 290 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BGUP Member List

This is the complete list of members for BGUP, including all inherited members.

BgupBuffer | BGUP
BgupHeader | BGUP
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BGUP_HEADER Struct Reference

Public Attributes | List of all members
BGUP_HEADER Struct Reference

BIOS Guard update Package Header. More...

#include <BiosGuard.h>

Public Attributes

UINT16 | Version
Version of the update package header. Must be 0x0002.
UINT8 | Reserved3 [2]
Reserved bits.
UINT8 | PlatId [16]
PLAT_ID used to be compared against the one found in the BGPDT to prevent cross platform flashing.
UINT16 | PkgAttributes
If any bit set in this field then BGUP must be signed and valid BGUPC must be provided for BGUP to be processed. More...
UINT8 | Reserved4 [2]
Reserved bits.
UINT16 | PslMajorVer
Indicates the PSL major version. Must be 2.
UINT16 | PslMinorVer
Indicates the PSL minor version. Must be 0.
UINT32 | ScriptSectionSize
Size in bytes of the script.
UINT32 | DataSectionSize
Size of the data region in bytes.
UINT32 | BiosSvn
BIOS SVN.
UINT32 | EcSvn
EC SVN.
UINT32 | VendorSpecific
Vendor specific data.

Detailed Description

BIOS Guard update Package Header.

Definition at line 253 of file BiosGuard.h.

Member Data Documentation

◆ PkgAttributes

UINT16 BGUP_HEADER::PkgAttributes

If any bit set in this field then BGUP must be signed and valid BGUPC must be provided for BGUP to be processed.

  • BIT[0]: Indicates write/erase operations will be executed on protected flash area indicated in the BGPDT SFAM.
  • BIT[1]: Indicates protected EC operations included.

Definition at line 262 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BGUP_HEADER Member List

This is the complete list of members for BGUP_HEADER, including all inherited members.

BiosSvn | BGUP_HEADER
DataSectionSize | BGUP_HEADER
EcSvn | BGUP_HEADER
PkgAttributes | BGUP_HEADER
PlatId | BGUP_HEADER
PslMajorVer | BGUP_HEADER
PslMinorVer | BGUP_HEADER
Reserved3 | BGUP_HEADER
Reserved4 | BGUP_HEADER
ScriptSectionSize | BGUP_HEADER
VendorSpecific | BGUP_HEADER
Version | BGUP_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BIOS_GUARD_CONFIG Struct Reference

Public Attributes | List of all members
BIOS_GUARD_CONFIG Struct Reference

BIOS Guard Configuration Structure. More...

#include <BiosGuardConfig.h>

Collaboration diagram for BIOS_GUARD_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
BIOSGUARD_ATTRIBUTES BiosGuardAttr
BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy, BIT4 - Flash wearout protection, BIT5 - FTU enable.
UINT64 | BgpdtHash [4]
Hash of the BGPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
EFI_PHYSICAL_ADDRESS | BiosGuardModulePtr
Pointer to the BIOS Guard Module.
EFI_PHYSICAL_ADDRESS | SendEcCmd
Platform code can provide interface to communicate with EC through this function.
UINT8 | EcCmdProvisionEav
EC Command Provision Eav.
UINT8 | EcCmdLock
EC Command Lock.
UINT8 | Reserved [6]
Reserved for future use and config block alignment.

Detailed Description

BIOS Guard Configuration Structure.

Platform policies for BIOS Guard Configuration for all processor security features configuration. Platform code can pass relevant configuration data through this structure.

Note
Optional. These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> BiosGuard is disabled, or PeiBiosGuardLibNull is used.

Revision 1:

  • Initial version.

Definition at line 55 of file BiosGuardConfig.h.

The documentation for this struct was generated from the following file:
  • BiosGuardConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BIOS_GUARD_CONFIG Member List

This is the complete list of members for BIOS_GUARD_CONFIG, including all inherited members.

BgpdtHash | BIOS_GUARD_CONFIG
BiosGuardAttr | BIOS_GUARD_CONFIG
BiosGuardModulePtr | BIOS_GUARD_CONFIG
EcCmdLock | BIOS_GUARD_CONFIG
EcCmdProvisionEav | BIOS_GUARD_CONFIG
Header | BIOS_GUARD_CONFIG
Reserved | BIOS_GUARD_CONFIG
SendEcCmd | BIOS_GUARD_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BIOSGUARD_HOB Struct Reference

Public Attributes | List of all members
BIOSGUARD_HOB Struct Reference

HOB used to pass data through every phase of BIOS Guard Bios. More...

#include <BiosGuard.h>

Collaboration diagram for BIOSGUARD_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
GUID Hob type header.
BGPDT Bgpdt
BIOS Guard Platform Data Table.
BGUP_HEADER BgupHeader
BIOS Guard update package header, this header will be appended to all flash updates along with PSL script.
BIOSGUARD_LOG BiosGuardLog
Header for BIOS Guard Log Buffer.
EFI_PHYSICAL_ADDRESS | BiosGuardModulePtr
Pointer to the BIOS Guard Module.
UINT64 | BiosGuardMemAddress
BIOS Guard Memory Address for Tool Interface.
UINT8 | BiosGuardMemSize
BIOS Guard Memory Size for Tool Interface.
UINT8 | Reserved [3]
Reserved for alignment.
UINT16 | BiosGuardIoTrapAddress
BIOS Guard IoTrap Address for Tool Interface.
UINT16 | BiosGuardIoTrapLength
BIOS Guard IoTrap Length for Tool Interface.
UINT32 | BiosGuardModuleSize
BIOS Guard Module Size.

Detailed Description

HOB used to pass data through every phase of BIOS Guard Bios.

BIOS Guard BIOS code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase.

Definition at line 324 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BIOSGUARD_HOB Member List

This is the complete list of members for BIOSGUARD_HOB, including all inherited members.

Bgpdt | BIOSGUARD_HOB
BgupHeader | BIOSGUARD_HOB
BiosGuardIoTrapAddress | BIOSGUARD_HOB
BiosGuardIoTrapLength | BIOSGUARD_HOB
BiosGuardLog | BIOSGUARD_HOB
BiosGuardMemAddress | BIOSGUARD_HOB
BiosGuardMemSize | BIOSGUARD_HOB
BiosGuardModulePtr | BIOSGUARD_HOB
BiosGuardModuleSize | BIOSGUARD_HOB
EfiHobGuidType | BIOSGUARD_HOB
Reserved | BIOSGUARD_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BIOSGUARD_LOG Struct Reference

Public Attributes | List of all members
BIOSGUARD_LOG Struct Reference

BIOS Guard Log The logging facility is used to communicate detailed information regarding the execution of a BIOS Guard script from the SMI handler which invoked the BIOS Guard module itself. More...

#include <BiosGuard.h>

Public Attributes

UINT16 | Version
Indicates the version of the log. Must be 0x0001.
UINT16 | LastPage
Last valid page index for the log.
UINT32 | LoggingOptions
Bitmap indicating what events to log. More...
UINT8 | Reserved5 [8]
Reserved bits.
UINT32 | BgModSvn
Indicates a version number of the BIOS Guard module.
UINT32 | NumOfEntriesInLog
Total number of log entries that have been written to the log.

Detailed Description

BIOS Guard Log The logging facility is used to communicate detailed information regarding the execution of a BIOS Guard script from the SMI handler which invoked the BIOS Guard module itself.

Definition at line 300 of file BiosGuard.h.

Member Data Documentation

◆ LoggingOptions

UINT32 BIOSGUARD_LOG::LoggingOptions

Bitmap indicating what events to log.

  • BIT[0]: Step trace. This indicates a full execution trace. Each line is entered into the log with an EXECUTION_TRACE entry.
  • BIT[1]: Branch trace. All taken jumps are logged with a BRANCH_TRACE entry.
  • BIT[2]: Flash write All flash write operations are logged with a FLASH_WRITE entry.
  • BIT[3]: Flash erase All flash erase operations are logged with a FLASH_ERASE entry.
  • BIT[4]: Flash error. All error conditions from flash operations are logged with FLASH_ERROR entry.
  • BIT[5]: Debug. Log Debug opcode execution.
  • BIT[6]: BIOS Guard module debug message. Log implementation specific debug messages from debug module.
  • BIT[31:7]: Reserved. Must be 0. If any reserved bits are set in Header.LoggingOptions, the BIOS Guard module must disable the logging feature.

Definition at line 314 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BIOSGUARD_LOG Member List

This is the complete list of members for BIOSGUARD_LOG, including all inherited members.

BgModSvn | BIOSGUARD_LOG
LastPage | BIOSGUARD_LOG
LoggingOptions | BIOSGUARD_LOG
NumOfEntriesInLog | BIOSGUARD_LOG
Reserved5 | BIOSGUARD_LOG
Version | BIOSGUARD_LOG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BIST_HOB_DATA Struct Reference

Public Attributes | List of all members
BIST_HOB_DATA Struct Reference

Store BIST data for BSP. More...

#include <CpuDataStruct.h>

Public Attributes

UINT32 | ApicId
APIC ID.
UINT32 | Health
BIST result.

Detailed Description

Store BIST data for BSP.

Definition at line 43 of file CpuDataStruct.h.

The documentation for this struct was generated from the following file:
  • CpuDataStruct.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BIST_HOB_DATA Member List

This is the complete list of members for BIST_HOB_DATA, including all inherited members.

ApicId | BIST_HOB_DATA
Health | BIST_HOB_DATA
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BOOT_GUARD_INFO Struct Reference

Public Attributes | List of all members
BOOT_GUARD_INFO Struct Reference

Information related to Boot Guard Configuration. More...

#include <BootGuardLibVer1.h>

Public Attributes

BOOLEAN | MeasuredBoot
Report Measured Boot setting in Boot Guard profile. 0: Disable; 1: Enable.
BOOLEAN | BypassTpmInit
ByPassTpmInit is set to 1 if Boot Guard ACM does TPM initialization successfully. More...
TPM_TYPE TpmType
Report what TPM device is available on system.
BOOLEAN | BootGuardCapability
Value is set to 1 if chipset is Boot Guard capable.
BOOLEAN | DisconnectAllTpms
Value is set to 1 if microcode failed to load Boot Guard ACM or ENF Shutdown path is taken by ME FW. More...
BOOLEAN | ByPassTpmEventLog
It is indicated BIOS TPM code is not to create DetailPCR or AuthorityPCR event log if Sx resume type is S3, Deep-S3, or iFFS Resume. More...
BOOLEAN | TpmStartupFailureOnS3
This field indicates that the ACM's Tpm2Startup (State) command failed during S3 resume. More...

Detailed Description

Information related to Boot Guard Configuration.

Definition at line 53 of file BootGuardLibVer1.h.

Member Data Documentation

◆ ByPassTpmEventLog

BOOLEAN BOOT_GUARD_INFO::ByPassTpmEventLog

It is indicated BIOS TPM code is not to create DetailPCR or AuthorityPCR event log if Sx resume type is S3, Deep-S3, or iFFS Resume.

  • 0: Create TPM event log if not Sx Resume Type.
  • 1: Bypass TPM Event Log if Sx Resume Type is identified.

Definition at line 75 of file BootGuardLibVer1.h.

◆ BypassTpmInit

BOOLEAN BOOT_GUARD_INFO::BypassTpmInit

ByPassTpmInit is set to 1 if Boot Guard ACM does TPM initialization successfully.

  • 0: No TPM initialization happen in Boot Guard ACM.
  • 1: TPM initialization is done by Boot Guard ACM.

Definition at line 60 of file BootGuardLibVer1.h.

◆ DisconnectAllTpms

BOOLEAN BOOT_GUARD_INFO::DisconnectAllTpms

Value is set to 1 if microcode failed to load Boot Guard ACM or ENF Shutdown path is taken by ME FW.

  • 0: BIOS TPM code continue with TPM initization based on MeasuredBoot.
  • 1: BIOS TPM code is not to do any futher TPM initization and extends.

Definition at line 68 of file BootGuardLibVer1.h.

◆ TpmStartupFailureOnS3

BOOLEAN BOOT_GUARD_INFO::TpmStartupFailureOnS3

This field indicates that the ACM's Tpm2Startup (State) command failed during S3 resume.

  • 0: Successful Tpm2Startup (State)
  • 1: Failure during Tpm2Startup (State). BIOS will need to perform a cold reset to handle the error.

Definition at line 81 of file BootGuardLibVer1.h.

The documentation for this struct was generated from the following file:
  • BootGuardLibVer1.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BOOT_GUARD_INFO Member List

This is the complete list of members for BOOT_GUARD_INFO, including all inherited members.

BootGuardCapability | BOOT_GUARD_INFO
ByPassTpmEventLog | BOOT_GUARD_INFO
BypassTpmInit | BOOT_GUARD_INFO
DisconnectAllTpms | BOOT_GUARD_INFO
MeasuredBoot | BOOT_GUARD_INFO
TpmStartupFailureOnS3 | BOOT_GUARD_INFO
TpmType | BOOT_GUARD_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BOOT_OPTION_CAPS_STRUC Struct Reference

List of all members
BOOT_OPTION_CAPS_STRUC Struct Reference

Boot Options/System Firmware Capabilities Bit Mask. More...

#include <IndustryStandardAsf.h>

Detailed Description

Boot Options/System Firmware Capabilities Bit Mask.

Byte1: 7: Reserved for future definition by this specification 6: Supports Sleep Button Lock 5: Supports Lock Keyboard 4:3: Reserved for future definition by this specification 2: Supports Reset Button Lock 1: Supports Power Button Lock 0: Supports Firmware Verbosity/Screen Blank Byte2: 7: Supports Configuration Data Reset 6: Supports Firmware Verbosity/Quiet 5: Supports Firmware Verbosity/Verbose 4: Supports Forced Progress Events 3: Supports User Password Bypass 2:0: Reserved for future definition by this specification Byte3: 7:0: Reserved for future definition by this specification Byte4: 7:0: Reserved for future definition by this specification

Definition at line 380 of file IndustryStandardAsf.h.

The documentation for this struct was generated from the following file:
  • IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BOOT_OPTION_CAPS_STRUC Member List

This is the complete list of members for BOOT_OPTION_CAPS_STRUC, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BUP_MPHY_READ_FROM_MPHY Struct Reference

List of all members
BUP_MPHY_READ_FROM_MPHY Struct Reference

MPHY group defines. More...

#include <BupMsgs.h>

Collaboration diagram for BUP_MPHY_READ_FROM_MPHY:
[legend]

Detailed Description

MPHY group defines.

Definition at line 458 of file BupMsgs.h.

The documentation for this struct was generated from the following file:
  • BupMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

BUP_MPHY_READ_FROM_MPHY Member List

This is the complete list of members for BUP_MPHY_READ_FROM_MPHY, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CACHE_DESCRIPTOR_INFO Struct Reference

Public Attributes | List of all members
CACHE_DESCRIPTOR_INFO Struct Reference

Cache descriptor information. More...

#include <CpuInfo.h>

Public Attributes

UINT8 | Desc
Cache Descriptor.
UINT8 | Level
Cache Level.
UINT8 | Type
Cache Type. 0: Data, 1: Instruction, 3: Unified.
UINT32 | Size
Cache Size.
UINT16 | Associativity
Cache Ways of Associativity.

Detailed Description

Cache descriptor information.

Definition at line 83 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CACHE_DESCRIPTOR_INFO Member List

This is the complete list of members for CACHE_DESCRIPTOR_INFO, including all inherited members.

Associativity | CACHE_DESCRIPTOR_INFO
Desc | CACHE_DESCRIPTOR_INFO
Level | CACHE_DESCRIPTOR_INFO
Size | CACHE_DESCRIPTOR_INFO
Type | CACHE_DESCRIPTOR_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CBM_RESET_ACK Struct Reference

List of all members
CBM_RESET_ACK Struct Reference

Reset request MKHI ack message. More...

#include <CoreBiosMsg.h>

Collaboration diagram for CBM_RESET_ACK:
[legend]

Detailed Description

Reset request MKHI ack message.

Definition at line 93 of file CoreBiosMsg.h.

The documentation for this struct was generated from the following file:
  • CoreBiosMsg.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CBM_RESET_ACK Member List

This is the complete list of members for CBM_RESET_ACK, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CBM_RESET_REQ Struct Reference

List of all members
CBM_RESET_REQ Struct Reference

Reset request MKHI message. More...

#include <CoreBiosMsg.h>

Collaboration diagram for CBM_RESET_REQ:
[legend]

Detailed Description

Reset request MKHI message.

Definition at line 85 of file CoreBiosMsg.h.

The documentation for this struct was generated from the following file:
  • CoreBiosMsg.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CBM_RESET_REQ Member List

This is the complete list of members for CBM_RESET_REQ, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CBM_RESET_REQ_DATA Struct Reference

List of all members
CBM_RESET_REQ_DATA Struct Reference

Reset request message data. More...

#include <CoreBiosMsg.h>

Detailed Description

Reset request message data.

Definition at line 77 of file CoreBiosMsg.h.

The documentation for this struct was generated from the following file:
  • CoreBiosMsg.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CBM_RESET_REQ_DATA Member List

This is the complete list of members for CBM_RESET_REQ_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_COMPLETE_CONFIGURATION_REQUEST Struct Reference

List of all members
CFG_COMPLETE_CONFIGURATION_REQUEST Struct Reference

Complete Configuration. More...

#include <AmthiMsgs.h>

Detailed Description

Complete Configuration.

Definition at line 897 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_COMPLETE_CONFIGURATION_REQUEST Member List

This is the complete list of members for CFG_COMPLETE_CONFIGURATION_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_FQDN_REQUEST Struct Reference

List of all members
CFG_GET_FQDN_REQUEST Struct Reference

Get/Set Fqdn. More...

#include <AmthiMsgs.h>

Detailed Description

Get/Set Fqdn.

Definition at line 840 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_FQDN_REQUEST Member List

This is the complete list of members for CFG_GET_FQDN_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_IDLE_TIMEOUT_REQUEST Struct Reference

List of all members
CFG_GET_IDLE_TIMEOUT_REQUEST Struct Reference

Get/Set Idle Timeout Request. More...

#include <AmthiMsgs.h>

Detailed Description

Get/Set Idle Timeout Request.

Definition at line 538 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_IDLE_TIMEOUT_REQUEST Member List

This is the complete list of members for CFG_GET_IDLE_TIMEOUT_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_INTERFACE_VERSION_RESPONSE Struct Reference

List of all members
CFG_GET_INTERFACE_VERSION_RESPONSE Struct Reference

Get Interface Version. More...

#include <AmthiMsgs.h>

Detailed Description

Get Interface Version.

Definition at line 224 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_INTERFACE_VERSION_RESPONSE Member List

This is the complete list of members for CFG_GET_INTERFACE_VERSION_RESPONSE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE Struct Reference

List of all members
CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE Struct Reference

Get OptIn Change Availability. More...

#include <AmthiMsgs.h>

Detailed Description

Get OptIn Change Availability.

Definition at line 1063 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE Member List

This is the complete list of members for CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_PRIVACY_LEVEL_REQUEST Struct Reference

List of all members
CFG_GET_PRIVACY_LEVEL_REQUEST Struct Reference

Get AMT Privacy Level. More...

#include <AmthiMsgs.h>

Detailed Description

Get AMT Privacy Level.

Definition at line 1044 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_PRIVACY_LEVEL_REQUEST Member List

This is the complete list of members for CFG_GET_PRIVACY_LEVEL_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_REDIRECTION_STATE_REQUEST Struct Reference

List of all members
CFG_GET_REDIRECTION_STATE_REQUEST Struct Reference

Get Redirection Features State. More...

#include <AmthiMsgs.h>

Detailed Description

Get Redirection Features State.

Definition at line 877 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_REDIRECTION_STATE_REQUEST Member List

This is the complete list of members for CFG_GET_REDIRECTION_STATE_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_GET_ZTC_ENABLED_STATUS_REQUEST Struct Reference

List of all members
CFG_GET_ZTC_ENABLED_STATUS_REQUEST Struct Reference

Get/Set ZTC Enabled Status. More...

#include <AmthiMsgs.h>

Detailed Description

Get/Set ZTC Enabled Status.

Definition at line 510 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_GET_ZTC_ENABLED_STATUS_REQUEST Member List

This is the complete list of members for CFG_GET_ZTC_ENABLED_STATUS_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST Struct Reference

List of all members
CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST Struct Reference

Open/Close/Query User Initiatied Connection for CIRA. More...

#include <AmthiMsgs.h>

Detailed Description

Open/Close/Query User Initiatied Connection for CIRA.

Definition at line 561 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST Member List

This is the complete list of members for CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_SET_KVM_ENABLED_REQUEST Struct Reference

List of all members
CFG_SET_KVM_ENABLED_REQUEST Struct Reference

Get/Set KVM State. More...

#include <AmthiMsgs.h>

Detailed Description

Get/Set KVM State.

Definition at line 1021 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_SET_KVM_ENABLED_REQUEST Member List

This is the complete list of members for CFG_SET_KVM_ENABLED_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST Struct Reference

List of all members
CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST Struct Reference

Set Sol/Storage Redirection. More...

#include <AmthiMsgs.h>

Detailed Description

Set Sol/Storage Redirection.

Definition at line 329 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST Member List

This is the complete list of members for CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_STOP_CONFIGURATION_REQUEST Struct Reference

List of all members
CFG_STOP_CONFIGURATION_REQUEST Struct Reference

Stop/Start Configuration. More...

#include <AmthiMsgs.h>

Detailed Description

Stop/Start Configuration.

Definition at line 909 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_STOP_CONFIGURATION_REQUEST Member List

This is the complete list of members for CFG_STOP_CONFIGURATION_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CFG_UNPROVISION_REQUEST Struct Reference

List of all members
CFG_UNPROVISION_REQUEST Struct Reference

Unprovision. More...

#include <AmthiMsgs.h>

Detailed Description

Unprovision.

Definition at line 301 of file AmthiMsgs.h.

The documentation for this struct was generated from the following file:
  • AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CFG_UNPROVISION_REQUEST Member List

This is the complete list of members for CFG_UNPROVISION_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CHIPSET_INIT_INFO Struct Reference

List of all members
CHIPSET_INIT_INFO Struct Reference

Revision 1: - Initial version. More...

#include <ChipsetInfoHob.h>

Detailed Description

Revision 1: - Initial version.

Revision 2: - Added ChipsetInit version 3. The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.

Definition at line 43 of file ChipsetInfoHob.h.

The documentation for this struct was generated from the following file:
  • ChipsetInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CHIPSET_INIT_INFO Member List

This is the complete list of members for CHIPSET_INIT_INFO, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CLEAR_BOOT_OPTIONS Struct Reference

Public Attributes | List of all members
CLEAR_BOOT_OPTIONS Struct Reference

Clear Boot Options Message Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for CLEAR_BOOT_OPTIONS:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Clear Boot Options Message Structure.

Definition at line 128 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CLEAR_BOOT_OPTIONS Member List

This is the complete list of members for CLEAR_BOOT_OPTIONS, including all inherited members.

AsfHeader CLEAR_BOOT_OPTIONS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CNVI_CONFIG Struct Reference

Public Attributes | List of all members
CNVI_CONFIG Struct Reference

The CNVI_CONFIG block describes the expected configuration of the CNVi IP. More...

#include <CnviConfig.h>

Collaboration diagram for CNVI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Mode: 1
This option allows for automatic detection of Connectivity Solution. More...
UINT32 | BtCore: 1
The option to turn ON or OFF the BT Core. 0: Disabled, 1: Enabled
UINT32 | BtAudioOffload: 1
The option to enable or disable BT Audio Offload. More...
UINT32 | WifiCore: 1
The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, 1: Enabled
CNVI_PIN_MUX PinMux
CNVi PinMux Configuration RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.

Detailed Description

The CNVI_CONFIG block describes the expected configuration of the CNVi IP.

Revision 1: - Initial version. Revision 2: - Add DdrRfim. Revision 3: - Add WifiCore. Revision 4: - Move DdrRfim to Pre-Mem config.

Definition at line 73 of file CnviConfig.h.

Member Data Documentation

◆ BtAudioOffload

UINT32 CNVI_CONFIG::BtAudioOffload

The option to enable or disable BT Audio Offload.

0: Disabled, 1: Enabled

Note
This feature only support with Intel(R) Wireless-AX 22560

Definition at line 89 of file CnviConfig.h.

◆ Mode

UINT32 CNVI_CONFIG::Mode

This option allows for automatic detection of Connectivity Solution.

Auto Detection assumes that CNVi will be enabled when available; Disable allows for disabling CNVi. CnviModeDisabled = Disabled, CnviModeAuto = Auto Detection

Definition at line 82 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CNVI_CONFIG Member List

This is the complete list of members for CNVI_CONFIG, including all inherited members.

BtAudioOffload | CNVI_CONFIG
BtCore | CNVI_CONFIG
Header | CNVI_CONFIG
Mode | CNVI_CONFIG
PinMux | CNVI_CONFIG
WifiCore | CNVI_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CNVI_PIN_MUX Struct Reference

Public Attributes | List of all members
CNVI_PIN_MUX Struct Reference

CNVi signals pin muxing settings. More...

#include <CnviConfig.h>

Public Attributes

UINT32 | RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
UINT32 | Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.

Detailed Description

CNVi signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h for supported settings on a given platform

Definition at line 60 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CNVI_PIN_MUX Member List

This is the complete list of members for CNVI_PIN_MUX, including all inherited members.

Clkreq | CNVI_PIN_MUX
RfReset | CNVI_PIN_MUX
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CNVI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CNVI_PREMEM_CONFIG Struct Reference

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

#include <CnviConfig.h>

Collaboration diagram for CNVI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled

Detailed Description

The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.

Revision 1: - Initial version.

Definition at line 105 of file CnviConfig.h.

The documentation for this struct was generated from the following file:
  • CnviConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CNVI_PREMEM_CONFIG Member List

This is the complete list of members for CNVI_PREMEM_CONFIG, including all inherited members.

DdrRfim | CNVI_PREMEM_CONFIG
Header | CNVI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): COMMIT_FILES Struct Reference

List of all members
COMMIT_FILES Struct Reference

Commit Files. More...

#include <MkhiMsgs.h>

Collaboration diagram for COMMIT_FILES:
[legend]

Detailed Description

Commit Files.

Definition at line 674 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

COMMIT_FILES Member List

This is the complete list of members for COMMIT_FILES, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CORE_BIOS_DONE Struct Reference

List of all members
CORE_BIOS_DONE Struct Reference

Core Bios Done - both GEN and MCA group definition. More...

#include <MkhiMsgs.h>

Collaboration diagram for CORE_BIOS_DONE:
[legend]

Detailed Description

Core Bios Done - both GEN and MCA group definition.

Definition at line 681 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CORE_BIOS_DONE Member List

This is the complete list of members for CORE_BIOS_DONE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_CONFIG Struct Reference

Public Attributes | List of all members
CPU_CONFIG Struct Reference

CPU Configuration Structure. More...

#include <CpuConfig.h>

Collaboration diagram for CPU_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
EFI_PHYSICAL_ADDRESS | MicrocodePatchAddress
Pointer to microcode patch that is suitable for this processor.
UINT32 | AesEnable: 1
Enable or Disable Advanced Encryption Standard (AES) feature. More...
UINT32 | TxtEnable: 1
Enable or Disable Trusted Execution Technology (TXT) feature. More...
UINT32 | SkipMpInit: 1
For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
UINT32 | PpinSupport: 2
Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number. More...
UINT32 | AcSplitLock: 1
Enable or Disable #AC machine check on split lock. More...
UINT32 | AvxDisable: 1
Enable or Disable Avx. More...
UINT32 | Avx3Disable: 1
UINT32 | X2ApicSupport: 1
Enable or Disable X2APIC Support. More...
UINT32 | RsvdBits: 23
Reserved for future use.
UINT16 | SmbiosType4MaxSpeedOverride
Provide the option for platform to override the MaxSpeed field of Smbios Type 4. More...
UINT8 | Reserved0 [2]
Reserved for future use.

Detailed Description

CPU Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add SmbiosType4MaxSpeedOverride. Revision 3:
  • Add AvxDisable & Avx3Disable. Revision 4:
  • Add X2ApicSupport. Revision 5:
  • Deprecate Avx3Disable

Definition at line 58 of file CpuConfig.h.

Member Data Documentation

◆ AcSplitLock

UINT32 CPU_CONFIG::AcSplitLock

Enable or Disable #AC machine check on split lock.

  • 0: Disable
  • 1: Enable

Definition at line 88 of file CpuConfig.h.

◆ AesEnable

UINT32 CPU_CONFIG::AesEnable

Enable or Disable Advanced Encryption Standard (AES) feature.

For some countries, this should be disabled for legal reasons.

  • 0: Disable
  • 1: Enable

Definition at line 68 of file CpuConfig.h.

◆ Avx3Disable

UINT32 CPU_CONFIG::Avx3Disable
Deprecated:
Enable or Disable Avx3.
  • 1: Disable
  • 0: Enable

Definition at line 101 of file CpuConfig.h.

◆ AvxDisable

UINT32 CPU_CONFIG::AvxDisable

Enable or Disable Avx.

  • 1: Disable
  • 0: Enable

Definition at line 94 of file CpuConfig.h.

◆ PpinSupport

UINT32 CPU_CONFIG::PpinSupport

Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.

  • 0: Disable
  • 1: Enable
  • 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM is set, it is disabled.

Definition at line 82 of file CpuConfig.h.

◆ SmbiosType4MaxSpeedOverride

UINT16 CPU_CONFIG::SmbiosType4MaxSpeedOverride

Provide the option for platform to override the MaxSpeed field of Smbios Type 4.

Value 4000 means 4000MHz. If this value is not zero, it dominates the field. If this value is zero, CPU RC will update the field according to the max radio. default is 0.

Definition at line 116 of file CpuConfig.h.

◆ TxtEnable

UINT32 CPU_CONFIG::TxtEnable

Enable or Disable Trusted Execution Technology (TXT) feature.

  • 0: Disable
  • 1: Enable

Definition at line 74 of file CpuConfig.h.

◆ X2ApicSupport

UINT32 CPU_CONFIG::X2ApicSupport

Enable or Disable X2APIC Support.

  • 0: Disable
  • 1: Enable

Definition at line 107 of file CpuConfig.h.

The documentation for this struct was generated from the following file:
  • CpuConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_CONFIG Member List

This is the complete list of members for CPU_CONFIG, including all inherited members.

AcSplitLock | CPU_CONFIG
AesEnable | CPU_CONFIG
Avx3Disable | CPU_CONFIG
AvxDisable | CPU_CONFIG
Header | CPU_CONFIG
MicrocodePatchAddress | CPU_CONFIG
PpinSupport | CPU_CONFIG
Reserved0 | CPU_CONFIG
RsvdBits | CPU_CONFIG
SkipMpInit | CPU_CONFIG
SmbiosType4MaxSpeedOverride | CPU_CONFIG
TxtEnable | CPU_CONFIG
X2ApicSupport | CPU_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_CONFIG_LIB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_CONFIG_LIB_PREMEM_CONFIG Struct Reference

CPU Config Library PreMemory Configuration Structure. More...

#include <CpuConfigLibPreMemConfig.h>

Collaboration diagram for CPU_CONFIG_LIB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HyperThreading: 1
Enable or Disable Hyper Threading; 0: Disable; 1: Enable.
UINT32 | BootFrequency: 2
Sets the boot frequency starting from reset vector. More...
UINT32 | ActiveCoreCount: 3
Number of processor cores to enable. More...
UINT32 | JtagC10PowerGateDisable: 1
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. 0: False< >; 1: True.
UINT32 | BistOnReset: 1
(Test) Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
UINT32 | VmxEnable: 1
Enable or Disable Virtual Machine Extensions (VMX) feature. More...
UINT32 | FClkFrequency: 2
Processor Early Power On Configuration FCLK setting. More...
UINT32 | CrashLogEnable: 1
Enable or Disable CrashLog feature. More...
UINT32 | TmeEnable: 1
Enable or Disable Total Memory Encryption (TME) feature. More...
UINT32 | DebugInterfaceEnable: 2
Enable or Disable processor debug features; 0: Disable; 1: Enable; 2: No Change.
UINT32 | DebugInterfaceLockEnable: 1
Lock or Unlock debug interface features; 0: Disable; 1: Enable.
UINT32 | ActiveCoreCount1: 4
Number of big cores in processor to enable. More...
UINT32 | PeciSxReset: 1
Enables a mailbox command to resolve rare PECI related Sx issues. More...
UINT32 | PeciC10Reset: 1
Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit. More...
UINT32 | ActiveSmallCoreCount: 6
Number of small cores in processor to enable. More...
UINT32 | CrashLogGprs: 2
Enable or Disable CrashLog GPRs dump. More...
UINT32 | ComputeDieSscEnable: 1
Enable or Disable Compute Die SSC configuration. More...
UINT32 | SocDieSscEnable: 1
Enable or Disable Soc Die SSC configuration. More...
UINT8 | CpuRatio
CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio. More...
UINT8 | ActiveSocNorthAtomCoreCount
Number of enabled atom cores on SoC. More...
UINT8 | ComputeDieSscValue
SSC configuration value of Compute Die. More...
UINT8 | SocDieSscValue
SSC configuration value of Soc Die. More...
UINT32 | BclkSource: 2
Clock source of BCLK OC Frequency. More...
UINT8 | InfDfxPwrEnable
Determine whether to keep or shutdown INF_DFX power rail. More...
UINT8 | ConfigTdpLevel
Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up.

Detailed Description

CPU Config Library PreMemory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Expand the supported number of processor cores (ActiveCoreCount1). Revision 3:
  • Added PECI Sx and C10 Reset. Revision 4:
  • Added ActiveSmallCoreCount. Revision 5:
  • Added CrashLogGprs Revision 6:
  • Added ActiveSocNorthAtomCoreCount Revision 7:
  • Added ComputeDieSscEnable, SocDieSscEnable, ComputeDieSscValue, and SocDieSscValue Revision 8:
  • Added BclkSource. Revision 9:
  • Removed Elixir Springs Patch Revision 10
  • Add InfDfxPwrEnable Revision 11
  • Add ConfigTdpLevel, CustomPowerLimit1

Definition at line 61 of file CpuConfigLibPreMemConfig.h.

Member Data Documentation

◆ ActiveCoreCount

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount

Number of processor cores to enable.

  • 0: All cores
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores
    Deprecated:
    due to core active number limitaion.

Definition at line 79 of file CpuConfigLibPreMemConfig.h.

◆ ActiveCoreCount1

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount1

Number of big cores in processor to enable.

And support up to 15 cores.

  • 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 16).
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores

Definition at line 121 of file CpuConfigLibPreMemConfig.h.

◆ ActiveSmallCoreCount

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSmallCoreCount

Number of small cores in processor to enable.

And support up to 63 cores.

  • 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 64).
  • 1: 1 core
  • 2: 2 cores
  • 3: 3 cores

Definition at line 148 of file CpuConfigLibPreMemConfig.h.

◆ ActiveSocNorthAtomCoreCount

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSocNorthAtomCoreCount

Number of enabled atom cores on SoC.

Default is set to supported core number.

  • 0 - all core disabled
  • 1 - enable 1 core
  • 2 - enable 2 cores
  • others - reserved for future use

Definition at line 185 of file CpuConfigLibPreMemConfig.h.

◆ BclkSource

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::BclkSource

Clock source of BCLK OC Frequency.

  • 0: SOC
  • 1: CPU
  • 2: PCH
  • 3: Ext. Clock (optional)

Definition at line 214 of file CpuConfigLibPreMemConfig.h.

◆ BootFrequency

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::BootFrequency

Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.
  • 1: Maximum non-turbo performance -2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.

Definition at line 71 of file CpuConfigLibPreMemConfig.h.

◆ ComputeDieSscEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscEnable

Enable or Disable Compute Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 163 of file CpuConfigLibPreMemConfig.h.

◆ ComputeDieSscValue

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscValue

SSC configuration value of Compute Die.

SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.

  • 0 : invalid
  • 1 : 0.01%
  • 2 : 0.02%
  • 100 : 1%

Definition at line 195 of file CpuConfigLibPreMemConfig.h.

◆ CpuRatio

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::CpuRatio

CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.

0: Disabled If disabled, doesn't override max-non turbo ratio.

Definition at line 175 of file CpuConfigLibPreMemConfig.h.

◆ CrashLogEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogEnable

Enable or Disable CrashLog feature.

  • 0: Disable
  • 1: Enable

Definition at line 101 of file CpuConfigLibPreMemConfig.h.

◆ CrashLogGprs

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogGprs

Enable or Disable CrashLog GPRs dump.

  • 0: Disable
  • 1: Gprs Enabled, Smm Gprs Enabled 2: Gprs Enabled, Smm Gprs Disabled

Definition at line 156 of file CpuConfigLibPreMemConfig.h.

◆ FClkFrequency

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::FClkFrequency

Processor Early Power On Configuration FCLK setting.

  • 0: 800 MHz (ULT/ULX).
  • 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.
  • 2: 400 MHz.
  • 3: Reserved.

Definition at line 95 of file CpuConfigLibPreMemConfig.h.

◆ InfDfxPwrEnable

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::InfDfxPwrEnable

Determine whether to keep or shutdown INF_DFX power rail.

INF_DFX power is up from cold boot.

  • 0 : INF_DFX shutdown
  • 1 : INF_DFX power up

Definition at line 221 of file CpuConfigLibPreMemConfig.h.

◆ PeciC10Reset

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset

Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.

If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit. The default value 0: Disable for CPU's

  • 0: Disable
  • 1: Enable
    Deprecated:
    no longer used.

Definition at line 138 of file CpuConfigLibPreMemConfig.h.

◆ PeciSxReset

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::PeciSxReset

Enables a mailbox command to resolve rare PECI related Sx issues.

Note
This should only be used on systems that observe PECI Sx issues.
  • 0: Disable
  • 1: Enable

Definition at line 129 of file CpuConfigLibPreMemConfig.h.

◆ SocDieSscEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscEnable

Enable or Disable Soc Die SSC configuration.

  • 0: Disable
  • 1: Enable

Definition at line 170 of file CpuConfigLibPreMemConfig.h.

◆ SocDieSscValue

UINT8 CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscValue

SSC configuration value of Soc Die.

SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.

  • 0 : invalid
  • 1 : 0.01%
  • 2 : 0.02%
  • 100 : 1%

Definition at line 205 of file CpuConfigLibPreMemConfig.h.

◆ TmeEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::TmeEnable

Enable or Disable Total Memory Encryption (TME) feature.

  • 0: Disable
  • 1: Enable

Definition at line 108 of file CpuConfigLibPreMemConfig.h.

◆ VmxEnable

UINT32 CPU_CONFIG_LIB_PREMEM_CONFIG::VmxEnable

Enable or Disable Virtual Machine Extensions (VMX) feature.

  • 0: Disable
  • 1: Enable

Definition at line 87 of file CpuConfigLibPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuConfigLibPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_CONFIG_LIB_PREMEM_CONFIG Member List

This is the complete list of members for CPU_CONFIG_LIB_PREMEM_CONFIG, including all inherited members.

ActiveCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveCoreCount1 | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveSmallCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
ActiveSocNorthAtomCoreCount | CPU_CONFIG_LIB_PREMEM_CONFIG
BclkSource | CPU_CONFIG_LIB_PREMEM_CONFIG
BistOnReset | CPU_CONFIG_LIB_PREMEM_CONFIG
BootFrequency | CPU_CONFIG_LIB_PREMEM_CONFIG
ComputeDieSscEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
ComputeDieSscValue | CPU_CONFIG_LIB_PREMEM_CONFIG
ConfigTdpLevel | CPU_CONFIG_LIB_PREMEM_CONFIG
CpuRatio | CPU_CONFIG_LIB_PREMEM_CONFIG
CrashLogEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
CrashLogGprs | CPU_CONFIG_LIB_PREMEM_CONFIG
DebugInterfaceEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
DebugInterfaceLockEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
FClkFrequency | CPU_CONFIG_LIB_PREMEM_CONFIG
Header | CPU_CONFIG_LIB_PREMEM_CONFIG
HyperThreading | CPU_CONFIG_LIB_PREMEM_CONFIG
InfDfxPwrEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
JtagC10PowerGateDisable | CPU_CONFIG_LIB_PREMEM_CONFIG
PeciC10Reset | CPU_CONFIG_LIB_PREMEM_CONFIG
PeciSxReset | CPU_CONFIG_LIB_PREMEM_CONFIG
SocDieSscEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
SocDieSscValue | CPU_CONFIG_LIB_PREMEM_CONFIG
TmeEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
VmxEnable | CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_DATA_HOB Struct Reference

Public Attributes | List of all members
CPU_DATA_HOB Struct Reference

CPU Data Hob. More...

#include <CpuDataHob.h>

Public Attributes

UINT8 | SvidEnabled
Svid Enabled\Disabled according to various VR domains. Refer to the definition in Fru.
UINT8 | VrAddress [MAX_VR_INDEX]
VR address according to various VR domains.
UINT8 | Reserved1 [(4 -(MAX_VR_INDEX % 4)) % 4]
Padding for CPU Data Hon alignment.

Detailed Description

CPU Data Hob.

Definition at line 46 of file CpuDataHob.h.

The documentation for this struct was generated from the following file:
  • CpuDataHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_DATA_HOB Member List

This is the complete list of members for CPU_DATA_HOB, including all inherited members.

Reserved1 | CPU_DATA_HOB
SvidEnabled | CPU_DATA_HOB
VrAddress | CPU_DATA_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_DMI_EQ_PARAM Struct Reference

Public Attributes | List of all members
CPU_DMI_EQ_PARAM Struct Reference

Represent lane specific Dmi Gen3 equalization parameters. More...

#include <CpuDmiPreMemConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Represent lane specific Dmi Gen3 equalization parameters.

Definition at line 61 of file CpuDmiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuDmiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_DMI_EQ_PARAM Member List

This is the complete list of members for CPU_DMI_EQ_PARAM, including all inherited members.

Cm | CPU_DMI_EQ_PARAM
Cp | CPU_DMI_EQ_PARAM
Rsvd0 | CPU_DMI_EQ_PARAM
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_DMI_HOB Struct Reference

Public Attributes | List of all members
CPU_DMI_HOB Struct Reference

The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi. More...

#include <CpuDmiHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gCpuDmieHobGuid.
UINT8 | CmGen3 [CPU_DMI_HWEQ_COEFFS_MAX]
These members describe the configuration of each CPU Dmi root port. More...
UINT8 | CpGen3 [CPU_DMI_HWEQ_COEFFS_MAX]
Coefficient C+1 for Gen3.
UINT8 | CmGen4 [CPU_DMI_HWEQ_COEFFS_MAX]
Coefficient C-1 for Gen4.
UINT8 | CpGen4 [CPU_DMI_HWEQ_COEFFS_MAX]
Coefficient C+1 for Gen4.

Detailed Description

The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi.

Definition at line 48 of file CpuDmiHob.h.

Member Data Documentation

◆ CmGen3

UINT8 CPU_DMI_HOB::CmGen3[CPU_DMI_HWEQ_COEFFS_MAX]

These members describe the configuration of each CPU Dmi root port.

Coefficient C-1 for Gen3

Definition at line 54 of file CpuDmiHob.h.

The documentation for this struct was generated from the following file:
  • CpuDmiHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_DMI_HOB Member List

This is the complete list of members for CPU_DMI_HOB, including all inherited members.

CmGen3 | CPU_DMI_HOB
CmGen4 | CPU_DMI_HOB
CpGen3 | CPU_DMI_HOB
CpGen4 | CPU_DMI_HOB
EfiHobGuidType | CPU_DMI_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_DMI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_DMI_PREMEM_CONFIG Struct Reference

The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI. More...

#include <CpuDmiPreMemConfig.h>

Collaboration diagram for CPU_DMI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | DmiMaxLinkSpeed
UINT8 | DmiGen3EqPh2Enable
(Test) DMI Equalization Phase 2 Enable Control More...
UINT8 | DmiGen3EqPh3Method
(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI More...
UINT8 | DmiGen3ProgramStaticEq
(Test) Program DMI Gen3 EQ Phase1 Static Presets More...
UINT8 | DmiDeEmphasis
DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
UINT8 | DmiAspmCtrl
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
UINT8 | DmiAspmL1ExitLatency
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
UINT8 | DmiGen3RootPortPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3EndPointPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | DmiGen3EndPointHint [SA_DMI_MAX_LANE]
Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | DmiGen3RxCtlePeaking [SA_DMI_MAX_BUNDLE]
DMI Gen3 RxCTLEp per-Bundle control. More...
UINT8 | DmiGen3DsPortRxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3DsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3UsPortRxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3UsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3Ltcpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3Ltcpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3RtcoCpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3RtcoCpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | Rsvd0 [1]
Reserved bytes.
UINT8 | DmiGen4Ltcpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4Ltcpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4DsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4UsPortTxPreset [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4RtcoCpre [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen4RtcoCpo [SA_DMI_MAX_LANE]
Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiNewFom
Used for programming DMI New FOM.
UINT8 | DmiCdrRelock
Used for programming DMI CDR Relock.

Detailed Description

The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.

Revision 1:

  • Initial version. Revision 2:
  • Added Policies for Dmi Higer Speed Training. Revision 3:
  • Added DmiCdrRelock Policy.

Definition at line 76 of file CpuDmiPreMemConfig.h.

Member Data Documentation

◆ DmiGen3EqPh2Enable

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh2Enable

(Test) DMI Equalization Phase 2 Enable Control

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default)

Definition at line 92 of file CpuDmiPreMemConfig.h.

◆ DmiGen3EqPh3Method

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh3Method

(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3

Definition at line 101 of file CpuDmiPreMemConfig.h.

◆ DmiGen3ProgramStaticEq

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3ProgramStaticEq

(Test) Program DMI Gen3 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 107 of file CpuDmiPreMemConfig.h.

◆ DmiGen3RxCtlePeaking

UINT8 CPU_DMI_PREMEM_CONFIG::DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]

DMI Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 121 of file CpuDmiPreMemConfig.h.

◆ DmiMaxLinkSpeed

UINT8 CPU_DMI_PREMEM_CONFIG::DmiMaxLinkSpeed
  • Auto (0x0) : Maximum possible link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
  • Gen3 (0x3) : Limit Link to Gen3 Speed

Definition at line 85 of file CpuDmiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuDmiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_DMI_PREMEM_CONFIG Member List

This is the complete list of members for CPU_DMI_PREMEM_CONFIG, including all inherited members.

DmiAspmCtrl | CPU_DMI_PREMEM_CONFIG
DmiAspmL1ExitLatency | CPU_DMI_PREMEM_CONFIG
DmiCdrRelock | CPU_DMI_PREMEM_CONFIG
DmiDeEmphasis | CPU_DMI_PREMEM_CONFIG
DmiGen3DsPortRxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3DsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3EndPointHint | CPU_DMI_PREMEM_CONFIG
DmiGen3EndPointPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3EqPh2Enable | CPU_DMI_PREMEM_CONFIG
DmiGen3EqPh3Method | CPU_DMI_PREMEM_CONFIG
DmiGen3Ltcpo | CPU_DMI_PREMEM_CONFIG
DmiGen3Ltcpre | CPU_DMI_PREMEM_CONFIG
DmiGen3ProgramStaticEq | CPU_DMI_PREMEM_CONFIG
DmiGen3RootPortPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3RtcoCpo | CPU_DMI_PREMEM_CONFIG
DmiGen3RtcoCpre | CPU_DMI_PREMEM_CONFIG
DmiGen3RxCtlePeaking | CPU_DMI_PREMEM_CONFIG
DmiGen3UsPortRxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen3UsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen4DsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiGen4Ltcpo | CPU_DMI_PREMEM_CONFIG
DmiGen4Ltcpre | CPU_DMI_PREMEM_CONFIG
DmiGen4RtcoCpo | CPU_DMI_PREMEM_CONFIG
DmiGen4RtcoCpre | CPU_DMI_PREMEM_CONFIG
DmiGen4UsPortTxPreset | CPU_DMI_PREMEM_CONFIG
DmiMaxLinkSpeed | CPU_DMI_PREMEM_CONFIG
DmiNewFom | CPU_DMI_PREMEM_CONFIG
Header | CPU_DMI_PREMEM_CONFIG
Rsvd0 | CPU_DMI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_INFO Struct Reference

Public Attributes | List of all members
CPU_INFO Struct Reference

Processor information. More...

#include <CpuInfo.h>

Collaboration diagram for CPU_INFO:
[legend]

Public Attributes

UINT32 | CpuSignature
Processor signature and version information.
UINT64 | Features
Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
CHAR8 * | BrandString
Processor Brand String.
UINT8 | NumSupportedCores
Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
UINT8 | NumSupportedThreadsPerCore
Number of Supported Threads per Core.
UINT8 | NumCores
Number of Enabled or Active Cores.
UINT8 | NumHts
Max Number of Enabled Threads per Core. This will be 1 or 2.
UINT32 | IntendedFreq
Maximum non turbo ratio or Config TDP ratio in MHz.
UINT32 | ActualFreq
Actual frequency in MHz.
UINT32 | Voltage
Current operating voltage.
CACHE_DESCRIPTOR_INFO * CacheInfo
Cache descriptor information.
UINT8 | MaxCacheSupported
Maximum cache supported.
UINT8 | SmmbaseSwSmiNumber
Software SMI Number from Smbase. @Note: This is unused.
UINT16 | NumberOfPStates
Number of P-States.
UINT16 | NumEnabledThreads
Enabled number of threads.
UINT8 | CoreVfPointCount
The number of Core VF Point.
UINT8 | CoreVfPointRatio [CPU_OC_MAX_VF_POINTS]
OC Ratio for each Core VF Point.
UINT8 | PerCoreRatioOverride
Enable or disable Per Core PState OC supported.
UINT8 | PerCoreRatio [CPU_MAX_BIG_CORES]
Array used to specific max ratio applied to each selected Core.
UINT8 | RingVfPointCount
The number of Ring VF Point.
UINT8 | RingVfPointRatio [CPU_OC_MAX_VF_POINTS]
OC Ratio for Ring VF Point.

Detailed Description

Processor information.

Definition at line 94 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_INFO Member List

This is the complete list of members for CPU_INFO, including all inherited members.

ActualFreq | CPU_INFO
BrandString | CPU_INFO
CacheInfo | CPU_INFO
CoreVfPointCount | CPU_INFO
CoreVfPointRatio | CPU_INFO
CpuSignature | CPU_INFO
Features | CPU_INFO
IntendedFreq | CPU_INFO
MaxCacheSupported | CPU_INFO
NumberOfPStates | CPU_INFO
NumCores | CPU_INFO
NumEnabledThreads | CPU_INFO
NumHts | CPU_INFO
NumSupportedCores | CPU_INFO
NumSupportedThreadsPerCore | CPU_INFO
PerCoreRatio | CPU_INFO
PerCoreRatioOverride | CPU_INFO
RingVfPointCount | CPU_INFO
RingVfPointRatio | CPU_INFO
SmmbaseSwSmiNumber | CPU_INFO
Voltage | CPU_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_CONFIG Struct Reference

The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version. More...

#include <CpuPcieConfig.h>

Collaboration diagram for CPU_PCIE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
CPU_PCIE_ROOT_PORT_CONFIG | RootPort [CPU_PCIE_MAX_ROOT_PORTS]
These members describe the configuration of each SA PCIe root port.
CPU_PCIE_EQ_LANE_PARAM | EqPh3LaneParam [SA_PEG_MAX_LANE]
Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc. More...
PCIE_EQ_PARAM | HwEqGen4CoeffList [PCIE_HWEQ_COEFFS_MAX]
List of coefficients used during equalization (applicable to both software and hardware EQ)
UINT32 | FiaProgramming: 1
< (Test) Includes policies which are common to both SA and PCH PCIe
UINT32 | PegGen3ProgramStaticEq: 1
< Skip Fia Configuration and lock if enable More...
UINT32 | PegGen4ProgramStaticEq: 1
(Test) Program PEG Gen4 EQ Phase1 Static Presets More...
UINT32 | SetSecuredRegisterLock: 1
(Test) Cpu Pcie Secure Register Lock More...
UINT32 | SlotSelection: 1
This member allows to select between the PCI Express M2 or CEMx4 slot 1: PCIe M2; 0: CEMx4 slot.
UINT32 | PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings. More...

Detailed Description

The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version.

Revision 2:

  • SlotSelection policy added Revision 3
  • Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq Revision 4:
  • Deprecating SetSecuredRegisterLock Revision 5:
  • Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
  • Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
  • Deprecate VcEnabled policy Revision 7:
  • Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection Revision 8:
  • Added Serl policy Revision 9:
  • Align revision with CPU_PCIE_CONFIG_REVISION value Revision 10:
  • Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp

Definition at line 367 of file CpuPcieConfig.h.

Member Data Documentation

◆ EqPh3LaneParam

CPU_PCIE_EQ_LANE_PARAM CPU_PCIE_CONFIG::EqPh3LaneParam[SA_PEG_MAX_LANE]

Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.

Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).

Definition at line 377 of file CpuPcieConfig.h.

◆ PcieDeviceOverrideTablePtr

UINT32 CPU_PCIE_CONFIG::PcieDeviceOverrideTablePtr

PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.

This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0. The prototype of this policy is: PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;

Definition at line 425 of file CpuPcieConfig.h.

◆ PegGen3ProgramStaticEq

UINT32 CPU_PCIE_CONFIG::PegGen3ProgramStaticEq

< Skip Fia Configuration and lock if enable

(Test) Program PEG Gen3 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 392 of file CpuPcieConfig.h.

◆ PegGen4ProgramStaticEq

UINT32 CPU_PCIE_CONFIG::PegGen4ProgramStaticEq

(Test) Program PEG Gen4 EQ Phase1 Static Presets

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 400 of file CpuPcieConfig.h.

◆ SetSecuredRegisterLock

UINT32 CPU_PCIE_CONFIG::SetSecuredRegisterLock

(Test) Cpu Pcie Secure Register Lock

  • Disabled (0x0)
  • Enabled (0x1)

Definition at line 406 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_CONFIG Member List

This is the complete list of members for CPU_PCIE_CONFIG, including all inherited members.

EqPh3LaneParam | CPU_PCIE_CONFIG
FiaProgramming | CPU_PCIE_CONFIG
Header | CPU_PCIE_CONFIG
HwEqGen4CoeffList | CPU_PCIE_CONFIG
PcieDeviceOverrideTablePtr | CPU_PCIE_CONFIG
PegGen3ProgramStaticEq | CPU_PCIE_CONFIG
PegGen4ProgramStaticEq | CPU_PCIE_CONFIG
RootPort | CPU_PCIE_CONFIG
SetSecuredRegisterLock | CPU_PCIE_CONFIG
SlotSelection | CPU_PCIE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_EQ_LANE_PARAM Struct Reference

Public Attributes | List of all members
CPU_PCIE_EQ_LANE_PARAM Struct Reference

Represent lane specific PCIe Gen3 equalization parameters. More...

#include <CpuPcieConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | PegGen3RootPortPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
UINT8 | PegGen3EndPointPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
UINT8 | PegGen3EndPointHint
(Test) Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
UINT8 | PegGen4RootPortPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
UINT8 | PegGen4EndPointPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
UINT8 | PegGen4EndPointHint
(Test) Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane

Detailed Description

Represent lane specific PCIe Gen3 equalization parameters.

Definition at line 288 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_EQ_LANE_PARAM Member List

This is the complete list of members for CPU_PCIE_EQ_LANE_PARAM, including all inherited members.

Cm | CPU_PCIE_EQ_LANE_PARAM
Cp | CPU_PCIE_EQ_LANE_PARAM
PegGen3EndPointHint | CPU_PCIE_EQ_LANE_PARAM
PegGen3EndPointPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen3RootPortPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen4EndPointHint | CPU_PCIE_EQ_LANE_PARAM
PegGen4EndPointPreset | CPU_PCIE_EQ_LANE_PARAM
PegGen4RootPortPreset | CPU_PCIE_EQ_LANE_PARAM
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_GPIO_INFO Struct Reference

Public Attributes | List of all members
CPU_PCIE_GPIO_INFO Struct Reference

CPU PCIe GPIO Data Structure. More...

#include <HybridGraphicsConfig.h>

Public Attributes

UINT8 | ExpanderNo
Offset 0 Expander No For I2C based GPIO.
BOOLEAN | Active
Offset 1 0=Active Low; 1=Active High.
UINT8 | Rsvd0 [2]
Offset 2 Reserved.
UINT32 | GpioNo
Offset 4 GPIO pad.

Detailed Description

CPU PCIe GPIO Data Structure.

Definition at line 53 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_GPIO_INFO Member List

This is the complete list of members for CPU_PCIE_GPIO_INFO, including all inherited members.

Active | CPU_PCIE_GPIO_INFO
ExpanderNo | CPU_PCIE_GPIO_INFO
GpioNo | CPU_PCIE_GPIO_INFO
Rsvd0 | CPU_PCIE_GPIO_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_HOB Struct Reference

Public Attributes | List of all members
CPU_PCIE_HOB Struct Reference

The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers. More...

#include <CpuPcieHob.h>

Collaboration diagram for CPU_PCIE_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
These members describe the configuration of each CPU PCIe root port. More...
UINT8 | L1SubStates [CPU_PCIE_MAX_ROOT_PORTS]
The L1 Substates configuration of the root port.
UINT32 | DekelFwVersionMinor
Dekel Firmware Minor Version.
UINT32 | DekelFwVersionMajor
Dekel Firmware Major Version.
BOOLEAN | InitPcieAspmAfterOprom
1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
UINT32 | RpEnabledMask
Rootport enabled mask based on DEVEN register.
UINT32 | RpEnMaskFromDevEn
Rootport enabled mask based on Device Id.
UINT8 | DisableClkReqMsg [CPU_PCIE_MAX_ROOT_PORTS]
1=ClkReqMsg disabled, 0=ClkReqMsg enabled
UINT8 | SlotSelection
1=M2 slot, 0=CEMx4 slot
BOOLEAN | ComplianceTest
Compliance Test based on policy.
UINT32 | HsPhyRecipeVersionMajor
HS-Phy Recipe Major Version.
UINT32 | HsPhyRecipeVersionMinor
HS-Phy Recipe Minor Version.
UINT32 | HsPhyFwProdMajor
HS-Phy Firmware Product Major Verison.
UINT32 | HsPhyFwProdMinor
HS-Phy Firmware Product Minor Verison.
UINT32 | HsPhyFwHotFix
HS-Phy Firmware Hot Fix Version.
UINT32 | HsPhyFwBuild
HS-Phy Firmware Build version.
UINT32 | HsPhyFwEvBitProgMajor
HS-Phy Firmware EV Bit Prog Major.
UINT32 | HsPhyFwEvBitProgMinor
HS-Phy Firmware EV Bit Prog Minor.
UINT32 | HsPhyMap
HS-Phy Mapping Based on HS-Py supported ports.

Detailed Description

The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers.

Definition at line 48 of file CpuPcieHob.h.

Member Data Documentation

◆ EfiHobGuidType

EFI_HOB_GUID_TYPE CPU_PCIE_HOB::EfiHobGuidType

These members describe the configuration of each CPU PCIe root port.

Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid

Definition at line 52 of file CpuPcieHob.h.

The documentation for this struct was generated from the following file:
  • CpuPcieHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_HOB Member List

This is the complete list of members for CPU_PCIE_HOB, including all inherited members.

ComplianceTest | CPU_PCIE_HOB
DekelFwVersionMajor | CPU_PCIE_HOB
DekelFwVersionMinor | CPU_PCIE_HOB
DisableClkReqMsg | CPU_PCIE_HOB
EfiHobGuidType | CPU_PCIE_HOB
HsPhyFwBuild | CPU_PCIE_HOB
HsPhyFwEvBitProgMajor | CPU_PCIE_HOB
HsPhyFwEvBitProgMinor | CPU_PCIE_HOB
HsPhyFwHotFix | CPU_PCIE_HOB
HsPhyFwProdMajor | CPU_PCIE_HOB
HsPhyFwProdMinor | CPU_PCIE_HOB
HsPhyMap | CPU_PCIE_HOB
HsPhyRecipeVersionMajor | CPU_PCIE_HOB
HsPhyRecipeVersionMinor | CPU_PCIE_HOB
InitPcieAspmAfterOprom | CPU_PCIE_HOB
L1SubStates | CPU_PCIE_HOB
RpEnabledMask | CPU_PCIE_HOB
RpEnMaskFromDevEn | CPU_PCIE_HOB
SlotSelection | CPU_PCIE_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_PWR_OPT Struct Reference

Public Attributes | List of all members
CPU_PCIE_PWR_OPT Struct Reference

PCIE Power Optimizer config. More...

#include <PcieDxeConfig.h>

Public Attributes

UINT16 | LtrMaxSnoopLatency
Offset 0 LTR Maximum Snoop Latency: 0x0846=70us
UINT16 | LtrMaxNoSnoopLatency
Offset 2 LTR Maximum Non-Snoop Latency: 0x0846=70us
UINT8 | ObffEnable
Offset 4 LTR enable/disable: 0=Disable, 1=Enable
UINT8 | LtrEnable
Offset 5 LTR enable/disable: 0=Disable, 1=Enable
UINT8 | Rsvd0 [2]
Offset 6 Reserved.

Detailed Description

PCIE Power Optimizer config.

Definition at line 98 of file PcieDxeConfig.h.

The documentation for this struct was generated from the following file:
  • PcieDxeConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_PWR_OPT Member List

This is the complete list of members for CPU_PCIE_PWR_OPT, including all inherited members.

LtrEnable | CPU_PCIE_PWR_OPT
LtrMaxNoSnoopLatency | CPU_PCIE_PWR_OPT
LtrMaxSnoopLatency | CPU_PCIE_PWR_OPT
ObffEnable | CPU_PCIE_PWR_OPT
Rsvd0 | CPU_PCIE_PWR_OPT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_ROOT_PORT_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_ROOT_PORT_CONFIG Struct Reference

The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port. More...

#include <CpuPcieConfig.h>

Public Attributes

UINT32 | ExtSync: 1
Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.
UINT32 | MultiVcEnabled: 1
Multiple Virtual Channel. 0: Disable; 1: Enable
UINT32 | RsvdBits0: 30
Reserved bits.
UINT8 | Gen4EqPh3Method
PCIe Gen4 Equalization Method. More...
UINT8 | FomsCp
FOM Score Board Control Policy.
UINT8 | RsvdBytes0 [2]
Reserved bytes.
UINT32 | Gen3Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen3Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen4Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen4Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is 7.
UINT32 | Gen5Uptp: 4
(Test) Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is 5.
UINT32 | Gen5Dptp: 4
(Test) Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is 7.
UINT32 | RsvdBits1: 8
Reserved Bits.
PCIE_ROOT_PORT_COMMON_CONFIG | PcieRpCommonConfig
(Test) Includes policies which are common to both SA and PCH RootPort

Detailed Description

The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.

Definition at line 302 of file CpuPcieConfig.h.

Member Data Documentation

◆ Gen4EqPh3Method

UINT8 CPU_PCIE_ROOT_PORT_CONFIG::Gen4EqPh3Method

PCIe Gen4 Equalization Method.

  • HwEq (0x1) : Hardware Equalization (Default)
  • StaticEq (0x2) : Static Equalization

Definition at line 312 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_ROOT_PORT_CONFIG Member List

This is the complete list of members for CPU_PCIE_ROOT_PORT_CONFIG, including all inherited members.

ExtSync | CPU_PCIE_ROOT_PORT_CONFIG
FomsCp | CPU_PCIE_ROOT_PORT_CONFIG
Gen3Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen3Uptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen4Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen4EqPh3Method | CPU_PCIE_ROOT_PORT_CONFIG
Gen4Uptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen5Dptp | CPU_PCIE_ROOT_PORT_CONFIG
Gen5Uptp | CPU_PCIE_ROOT_PORT_CONFIG
MultiVcEnabled | CPU_PCIE_ROOT_PORT_CONFIG
PcieRpCommonConfig | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBits0 | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBits1 | CPU_PCIE_ROOT_PORT_CONFIG
RsvdBytes0 | CPU_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_RP_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_PCIE_RP_PREMEM_CONFIG Struct Reference

CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version. More...

#include <CpuPcieConfig.h>

Collaboration diagram for CPU_PCIE_RP_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | RpEnabledMask
Root Port enabling mask. More...
UINT8 | LinkDownGpios
Assertion on Link Down GPIOs. More...
UINT8 | ClkReqMsgEnable
Enable ClockReq Messaging. More...
UINT8 | DekelSquelchWa
Dekel Recipe Workaround 2 1=Minimal, 9=Maximum,.
UINT8 | PcieSpeed [CPU_PCIE_MAX_ROOT_PORTS]
Determines each PCIE Port speed capability. More...
UINT8 | ClkReqMsgEnableRp [CPU_PCIE_MAX_ROOT_PORTS]
Enable ClockReq Messaging Policy is for all Rootports. More...
UINT8 | NewFom [CPU_PCIE_MAX_ROOT_PORTS]
To Enable/Disable New FOM 0: Disable; 1: Enable.
UINT8 | CdrRelock [CPU_PCIE_MAX_ROOT_PORTS]
To Enable/Disable CDR Relock 0: Disable; 1: Enable.

Detailed Description

CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version.

Revision 2: - Adding Dekel Suqelch Workaround Setup Variable Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable Revision 4: - Adding New FOM Setup Variable Revision 5: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.

Definition at line 156 of file CpuPcieConfig.h.

Member Data Documentation

◆ ClkReqMsgEnable

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnable

Enable ClockReq Messaging.

  • Disabled</> (0x0) : Disable ClockReq Messaging(Default)
  • Enabled (0x1) : Enable ClockReq Messaging

Definition at line 175 of file CpuPcieConfig.h.

◆ ClkReqMsgEnableRp

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS]

Enable ClockReq Messaging Policy is for all Rootports.

  • Disabled</> (0x0) : Disable ClockReq Messaging(Default)
  • Enabled (0x1) : Enable ClockReq Messaging

Definition at line 194 of file CpuPcieConfig.h.

◆ LinkDownGpios

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::LinkDownGpios

Assertion on Link Down GPIOs.

  • Disabled (0x0) : Disable assertion on Link Down GPIOs(Default)
  • Enabled (0x1) : Enable assertion on Link Down GPIOs

Definition at line 169 of file CpuPcieConfig.h.

◆ PcieSpeed

UINT8 CPU_PCIE_RP_PREMEM_CONFIG::PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS]

Determines each PCIE Port speed capability.

0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)

Definition at line 187 of file CpuPcieConfig.h.

◆ RpEnabledMask

UINT32 CPU_PCIE_RP_PREMEM_CONFIG::RpEnabledMask

Root Port enabling mask.

Bit0 presents RP1, Bit1 presents RP2, and so on. 0: Disable; 1: Enable.

Definition at line 163 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_RP_PREMEM_CONFIG Member List

This is the complete list of members for CPU_PCIE_RP_PREMEM_CONFIG, including all inherited members.

CdrRelock | CPU_PCIE_RP_PREMEM_CONFIG
ClkReqMsgEnable | CPU_PCIE_RP_PREMEM_CONFIG
ClkReqMsgEnableRp | CPU_PCIE_RP_PREMEM_CONFIG
DekelSquelchWa | CPU_PCIE_RP_PREMEM_CONFIG
Header | CPU_PCIE_RP_PREMEM_CONFIG
LinkDownGpios | CPU_PCIE_RP_PREMEM_CONFIG
NewFom | CPU_PCIE_RP_PREMEM_CONFIG
PcieSpeed | CPU_PCIE_RP_PREMEM_CONFIG
RpEnabledMask | CPU_PCIE_RP_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_PCIE_RTD3_GPIO Struct Reference

Public Attributes | List of all members
CPU_PCIE_RTD3_GPIO Struct Reference

CPU PCIE RTD3 GPIO Data Structure. More...

#include <HybridGraphicsConfig.h>

Collaboration diagram for CPU_PCIE_RTD3_GPIO:
[legend]

Public Attributes

CPU_PCIE_GPIO_INFO HoldRst
Offset 0 This field contain PCIe HLD RESET GPIO value and level information.
CPU_PCIE_GPIO_INFO PwrEnable
Offset 8 This field contain PCIe PWR Enable GPIO value and level information.
UINT32 | WakeGpioNo
Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number.
UINT8 | GpioSupport
Offset 20 Depends on board design the GPIO configuration may be different: 0=Not Supported, 1=PCH Based, 2=I2C based.
UINT8 | Rsvd0 [3]
Offset 21.

Detailed Description

CPU PCIE RTD3 GPIO Data Structure.

Definition at line 63 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_PCIE_RTD3_GPIO Member List

This is the complete list of members for CPU_PCIE_RTD3_GPIO, including all inherited members.

GpioSupport | CPU_PCIE_RTD3_GPIO
HoldRst | CPU_PCIE_RTD3_GPIO
PwrEnable | CPU_PCIE_RTD3_GPIO
Rsvd0 | CPU_PCIE_RTD3_GPIO
WakeGpioNo | CPU_PCIE_RTD3_GPIO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_POWER_MGMT_BASIC_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_BASIC_CONFIG Struct Reference

CPU Power Management Basic Configuration Structure. More...

#include <CpuPowerMgmtBasicConfig.h>

Collaboration diagram for CPU_POWER_MGMT_BASIC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | BootFrequency: 2
Sets the boot frequency starting from reset vector. More...
UINT32 | SkipSetBootPState: 1
Choose whether to skip SetBootPState function for all APs; 0: Do not skip; 1: Skip.
UINT32 | Hwp: 2
Enable or Disable Intel Speed Shift Technology. More...
UINT32 | HdcControl: 2
Hardware Duty Cycle Control configuration. More...
UINT32 | PowerLimit2: 1
Enable or Disable short duration Power Limit (PL2). 0: Disable; 1: Enable
UINT32 | TurboPowerLimitLock: 1
MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable; 1: Enable (Lock).
UINT32 | PowerLimit3DutyCycle: 8
Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0.
UINT32 | PowerLimit3Lock: 1
Package PL3 MSR 615h lock; 0: Disable; 1: Enable (Lock).
UINT32 | PowerLimit4Lock: 1
Package PL4 MSR 601h lock; 0: Disable; 1: Enable (Lock).
UINT32 | TccOffsetClamp: 1
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1. More...
UINT32 | TccOffsetLock: 1
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: Disabled; 1: Enabled (Lock).
UINT32 | TurboMode: 1
Enable or Disable Turbo Mode. Disable; 1: Enable
UINT32 | HwpInterruptControl: 1
Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enable.
UINT32 | ApplyConfigTdp: 1
Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP.
UINT32 | HwpLock: 1
HWP Lock in MISC PWR MGMT MSR 1AAh; 0: Disable; 1: Enable (Lock).
UINT32 | DualTauBoost: 1
Dual Tau Base Performance Boost support. More...
UINT32 | RsvdBits: 6
Reserved for future use.
UINT8 | OneCoreRatioLimit
1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. More...
UINT8 | TwoCoreRatioLimit
2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins. More...
UINT8 | ThreeCoreRatioLimit
3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins. More...
UINT8 | FourCoreRatioLimit
4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins. More...
UINT8 | FiveCoreRatioLimit
5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins. More...
UINT8 | SixCoreRatioLimit
6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins. More...
UINT8 | SevenCoreRatioLimit
7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins. More...
UINT8 | EightCoreRatioLimit
8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins. More...
UINT8 | TccActivationOffset
TCC Activation Offset. More...
UINT8 | EnableItbm: 1
Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores. More...
UINT8 | EnableItbmDriver: 1
UINT8 | EnablePerCorePState: 1
Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. More...
UINT8 | EnableHwpAutoPerCorePstate: 1
HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11. More...
UINT8 | EnableHwpAutoEppGrouping: 1
HwP Autonomous EPP grouping. More...
UINT8 | EnableEpbPeciOverride: 1
EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1. More...
UINT8 | EnableFastMsrHwpReq: 1
Support for Fast MSR for IA32_HWP_REQUEST. More...
UINT8 | ReservedBits1: 1
Reserved for future use.
UINT8 | MinRingRatioLimit
Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
UINT8 | MaxRingRatioLimit
Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
UINT16 | PowerLimit1
Package Long duration turbo mode power limit (PL1). More...
UINT16 | PowerLimit2Power
Package Short duration turbo mode power limit (PL2). More...
UINT16 | PowerLimit3
Package PL3 power limit. More...
UINT16 | PowerLimit4
Package PL4 power limit. More...
UINT32 | PowerLimit1Time
Package Long duration turbo mode power limit (PL1) time window in seconds. More...
UINT32 | PowerLimit3Time
Package PL3 time window. Range from 3ms to 64ms.
UINT32 | TccOffsetTimeWindowForRatl
Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL). More...
UINT8 | TurboRatioLimitRatio [TURBO_RATIO_LIMIT_ARRAY_SIZE]
Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | TurboRatioLimitNumCore [TURBO_RATIO_LIMIT_ARRAY_SIZE]
Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | AtomTurboRatioLimitRatio [TURBO_RATIO_LIMIT_ARRAY_SIZE]
ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point. More...
UINT8 | AtomTurboRatioLimitNumCore [TURBO_RATIO_LIMIT_ARRAY_SIZE]
ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point. More...

Detailed Description

CPU Power Management Basic Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Changed EnableItbm default to be disable
  • Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driver Revision 3:
  • Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or cTDP Revision 4:
  • Add Hwp Lock support Revision 5:
  • Add TurboRatioLimitRatio, TurboRatioLimitNumCore, AtomTurboRatioLimitRatio and AtomTurboRatioLimitNumCore Revision 6:
  • Add DualTauBoost Revision 7:
  • Changed EnableItbm default to be enable

Definition at line 67 of file CpuPowerMgmtBasicConfig.h.

Member Data Documentation

◆ AtomTurboRatioLimitNumCore

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::AtomTurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE]

ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x651. Note:

  • These policies are for platforms support ATOM MSR pair 0x650 and 0x651.

Definition at line 305 of file CpuPowerMgmtBasicConfig.h.

◆ AtomTurboRatioLimitRatio

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::AtomTurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE]

ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x650. Note:

  • These policies are for platforms support ATOM MSR pair 0x650 and 0x651.

Definition at line 297 of file CpuPowerMgmtBasicConfig.h.

◆ BootFrequency

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::BootFrequency

Sets the boot frequency starting from reset vector.

  • 0: Maximum battery performance.
  • 1: Maximum non-turbo performance.
  • 2: Turbo performance.
    Note
    If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.

Definition at line 76 of file CpuPowerMgmtBasicConfig.h.

◆ DualTauBoost

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::DualTauBoost

Dual Tau Base Performance Boost support.

This will improve platform performance for desktop sku. When enabled, it exposes 2 MMIO PL1 and MMIO Tau registers, and also provides the default value.

Note
: This is only applicable for Desktop 35W/65W/125W sku.
: When this is enabled, it will override the settings in policys PowerLimit1, PowerLimit1Time, PowerLimit2Power. 0: Disable; 1: Enable

Definition at line 115 of file CpuPowerMgmtBasicConfig.h.

◆ EightCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EightCoreRatioLimit

8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 180 of file CpuPowerMgmtBasicConfig.h.

◆ EnableEpbPeciOverride

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableEpbPeciOverride

EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1.

This will allow OOB EPB PECI override control. 0: Disable; 1: Enable;

Definition at line 228 of file CpuPowerMgmtBasicConfig.h.

◆ EnableFastMsrHwpReq

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableFastMsrHwpReq

Support for Fast MSR for IA32_HWP_REQUEST.

On systems with HwP enabled, if this feature is available as indicated by MSR 0x65F[0] = 1, set MSR 0x657[0] = 1. 0: Disable; 1: Enable;

Definition at line 235 of file CpuPowerMgmtBasicConfig.h.

◆ EnableHwpAutoEppGrouping

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoEppGrouping

HwP Autonomous EPP grouping.

Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not necesarrily request the same value for all cores with same EPP. Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request same values for all cores with same EPP. 0: Disable; 1: Enable;

Definition at line 221 of file CpuPowerMgmtBasicConfig.h.

◆ EnableHwpAutoPerCorePstate

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoPerCorePstate

HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11.

When set, autonomous will request the same value for all cores all the time. 0: Disable; 1: Enable;

Definition at line 213 of file CpuPowerMgmtBasicConfig.h.

◆ EnableItbm

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableItbm

Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores.

0: Disable; 1: Enable;

Definition at line 194 of file CpuPowerMgmtBasicConfig.h.

◆ EnableItbmDriver

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
Deprecated:
: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver Enabling it will load the driver upon ACPI device with HID = INT3510. 0: Disable; 1: Enable;

Definition at line 200 of file CpuPowerMgmtBasicConfig.h.

◆ EnablePerCorePState

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::EnablePerCorePState

Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1.

When set, the highest core request is used for all other core requests. 0: Disable; 1: Enable;

Definition at line 206 of file CpuPowerMgmtBasicConfig.h.

◆ FiveCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::FiveCoreRatioLimit

5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.

Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 156 of file CpuPowerMgmtBasicConfig.h.

◆ FourCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::FourCoreRatioLimit

4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 149 of file CpuPowerMgmtBasicConfig.h.

◆ HdcControl

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::HdcControl

Hardware Duty Cycle Control configuration.

0: Disabled; 1: Enabled 2-3:Reserved HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency. This allows for increased package level C6 residency.

Note
Currently this feature is recommended to be enabled only on win10

Definition at line 91 of file CpuPowerMgmtBasicConfig.h.

◆ Hwp

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::Hwp

Enable or Disable Intel Speed Shift Technology.

Enabling allows for processor control of P-state transitions. 0: Disable; 1: Enable; Bit 1 is ignored.

Note
Currently this feature is recommended to be enabled only on win10

Definition at line 84 of file CpuPowerMgmtBasicConfig.h.

◆ OneCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::OneCoreRatioLimit

1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit.

For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins. Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 125 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit1

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1

Package Long duration turbo mode power limit (PL1).

Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 243 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit1Time

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1Time

Package Long duration turbo mode power limit (PL1) time window in seconds.

Used in calculating the average power over time. Mobile: 28s Desktop: 8s Range: 0 - 128s

Definition at line 267 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit2Power

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2Power

Package Short duration turbo mode power limit (PL2).

Allows for short excursions above TDP power limit. Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 248 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit3

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3

Package PL3 power limit.

PL3 is the CPU Peak Power Occurences Limit. Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 253 of file CpuPowerMgmtBasicConfig.h.

◆ PowerLimit4

UINT16 CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4

Package PL4 power limit.

PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded. Power is premptively lowered before limit is reached. Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.

Definition at line 259 of file CpuPowerMgmtBasicConfig.h.

◆ SevenCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::SevenCoreRatioLimit

7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 172 of file CpuPowerMgmtBasicConfig.h.

◆ SixCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::SixCoreRatioLimit

6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 164 of file CpuPowerMgmtBasicConfig.h.

◆ TccActivationOffset

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TccActivationOffset

TCC Activation Offset.

Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius. For Y SKU, the recommended default for this policy is 10 For all other SKUs the recommended default are 0, causing TCC to activate at TCC Activation temperature.

Note
The policy is recommended for validation purpose only.

Definition at line 188 of file CpuPowerMgmtBasicConfig.h.

◆ TccOffsetClamp

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetClamp

Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.

For Y SKU, the recommended default for this policy is 1: Enabled, which indicates throttling below P1 is allowed. For all other SKUs the recommended default are 0: Disabled.

Definition at line 102 of file CpuPowerMgmtBasicConfig.h.

◆ TccOffsetTimeWindowForRatl

UINT32 CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetTimeWindowForRatl

Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).

For Y SKU, the recommended default for this policy is 5000: 5 seconds, For all other SKUs the recommended default are 0: Disabled

Definition at line 273 of file CpuPowerMgmtBasicConfig.h.

◆ ThreeCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::ThreeCoreRatioLimit

3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 141 of file CpuPowerMgmtBasicConfig.h.

◆ TurboRatioLimitNumCore

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE]

Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x1AE. Note:

  • These policies are for platforms support MSR pair 0x1AD and 0x1AE.

Definition at line 289 of file CpuPowerMgmtBasicConfig.h.

◆ TurboRatioLimitRatio

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE]

Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0] to determine the active core ranges for each frequency point.

Default value is from hardware register MSR 0x1AD. Note:

  • These policies are for platforms support MSR pair 0x1AD and 0x1AE.

Definition at line 281 of file CpuPowerMgmtBasicConfig.h.

◆ TwoCoreRatioLimit

UINT8 CPU_POWER_MGMT_BASIC_CONFIG::TwoCoreRatioLimit

2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.

Default value is from hardware register MSR 0x1AD. Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.

  • This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
  • This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.

Definition at line 133 of file CpuPowerMgmtBasicConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtBasicConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_POWER_MGMT_BASIC_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_BASIC_CONFIG, including all inherited members.

ApplyConfigTdp | CPU_POWER_MGMT_BASIC_CONFIG
AtomTurboRatioLimitNumCore | CPU_POWER_MGMT_BASIC_CONFIG
AtomTurboRatioLimitRatio | CPU_POWER_MGMT_BASIC_CONFIG
BootFrequency | CPU_POWER_MGMT_BASIC_CONFIG
DualTauBoost | CPU_POWER_MGMT_BASIC_CONFIG
EightCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
EnableEpbPeciOverride | CPU_POWER_MGMT_BASIC_CONFIG
EnableFastMsrHwpReq | CPU_POWER_MGMT_BASIC_CONFIG
EnableHwpAutoEppGrouping | CPU_POWER_MGMT_BASIC_CONFIG
EnableHwpAutoPerCorePstate | CPU_POWER_MGMT_BASIC_CONFIG
EnableItbm | CPU_POWER_MGMT_BASIC_CONFIG
EnableItbmDriver | CPU_POWER_MGMT_BASIC_CONFIG
EnablePerCorePState | CPU_POWER_MGMT_BASIC_CONFIG
FiveCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
FourCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
HdcControl | CPU_POWER_MGMT_BASIC_CONFIG
Header | CPU_POWER_MGMT_BASIC_CONFIG
Hwp | CPU_POWER_MGMT_BASIC_CONFIG
HwpInterruptControl | CPU_POWER_MGMT_BASIC_CONFIG
HwpLock | CPU_POWER_MGMT_BASIC_CONFIG
MaxRingRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
MinRingRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
OneCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit1 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit1Time | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit2 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit2Power | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3DutyCycle | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3Lock | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit3Time | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit4 | CPU_POWER_MGMT_BASIC_CONFIG
PowerLimit4Lock | CPU_POWER_MGMT_BASIC_CONFIG
ReservedBits1 | CPU_POWER_MGMT_BASIC_CONFIG
RsvdBits | CPU_POWER_MGMT_BASIC_CONFIG
SevenCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
SixCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
SkipSetBootPState | CPU_POWER_MGMT_BASIC_CONFIG
TccActivationOffset | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetClamp | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetLock | CPU_POWER_MGMT_BASIC_CONFIG
TccOffsetTimeWindowForRatl | CPU_POWER_MGMT_BASIC_CONFIG
ThreeCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
TurboMode | CPU_POWER_MGMT_BASIC_CONFIG
TurboPowerLimitLock | CPU_POWER_MGMT_BASIC_CONFIG
TurboRatioLimitNumCore | CPU_POWER_MGMT_BASIC_CONFIG
TurboRatioLimitRatio | CPU_POWER_MGMT_BASIC_CONFIG
TwoCoreRatioLimit | CPU_POWER_MGMT_BASIC_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_POWER_MGMT_CUSTOM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_CUSTOM_CONFIG Struct Reference

CPU Power Management Custom Configuration Structure. More...

#include <CpuPowerMgmtCustomConfig.h>

Collaboration diagram for CPU_POWER_MGMT_CUSTOM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PPM_CUSTOM_RATIO_TABLE CustomRatioTable
Custom Processor Ratio Table Instance.
PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable [MAX_CUSTOM_CTDP_ENTRIES]
Custom ConfigTdp Settings Instance.
UINT32 | ConfigTdpLock: 1
Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable.
UINT32 | ConfigTdpBios: 1
Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
UINT32 | RsvdBits: 30
Reserved for future use.

Detailed Description

CPU Power Management Custom Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 93 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_POWER_MGMT_CUSTOM_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_CUSTOM_CONFIG, including all inherited members.

ConfigTdpBios | CPU_POWER_MGMT_CUSTOM_CONFIG
ConfigTdpLock | CPU_POWER_MGMT_CUSTOM_CONFIG
CustomConfigTdpTable | CPU_POWER_MGMT_CUSTOM_CONFIG
CustomRatioTable | CPU_POWER_MGMT_CUSTOM_CONFIG
Header | CPU_POWER_MGMT_CUSTOM_CONFIG
RsvdBits | CPU_POWER_MGMT_CUSTOM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_POWER_MGMT_PSYS_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_PSYS_CONFIG Struct Reference

CPU Power Management Psys(Platform) Configuration Structure. More...

#include <CpuPowerMgmtPsysConfig.h>

Collaboration diagram for CPU_POWER_MGMT_PSYS_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PsysPowerLimit1: 1
MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power.
UINT32 | PsysPowerLimit1Time: 8
MSR 0x65C[23:17]: PL1 timewindow in seconds.
UINT32 | PsysPowerLimit2: 1
MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power.
UINT32 | RsvdBits: 22
Reserved for future use.
UINT16 | PsysPowerLimit1Power
MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | PsysPowerLimit2Power
MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
UINT16 | PsysPmax
PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
UINT8 | Rsvd [2]
Reserved for future use and config block alignment.

Detailed Description

CPU Power Management Psys(Platform) Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 50 of file CpuPowerMgmtPsysConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtPsysConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_POWER_MGMT_PSYS_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_PSYS_CONFIG, including all inherited members.

Header | CPU_POWER_MGMT_PSYS_CONFIG
PsysPmax | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1 | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1Power | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit1Time | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit2 | CPU_POWER_MGMT_PSYS_CONFIG
PsysPowerLimit2Power | CPU_POWER_MGMT_PSYS_CONFIG
Rsvd | CPU_POWER_MGMT_PSYS_CONFIG
RsvdBits | CPU_POWER_MGMT_PSYS_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_POWER_MGMT_TEST_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_TEST_CONFIG Struct Reference

CPU Power Management Test Configuration Structure. More...

#include <CpuPowerMgmtTestConfig.h>

Collaboration diagram for CPU_POWER_MGMT_TEST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | Eist: 1
Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
UINT32 | EnergyEfficientPState: 1
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable
UINT32 | EnergyEfficientTurbo: 1
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable.
UINT32 | TStates: 1
Enable or Disable T states; 0: Disable; 1: Enable.
UINT32 | BiProcHot: 1
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
UINT32 | DisableProcHotOut: 1
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
UINT32 | ProcHotResponse: 1
Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
UINT32 | DisableVrThermalAlert: 1
Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
UINT32 | EnableAllThermalFunctions: 1
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
UINT32 | ThermalMonitor: 1
Enable or Disable Thermal Monitor; 0: Disable; 1: Enable.
UINT32 | Cx: 1
Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
UINT32 | PmgCstCfgCtrlLock: 1
If enabled, sets MSR 0xE2[15]; 0: Disable; 1: Enable.
UINT32 | C1e: 1
Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
UINT32 | C1AutoDemotion: 1
Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion
UINT32 | C1UnDemotion: 1
Enable or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion
UINT32 | C3AutoDemotion: 1
UINT32 | C3UnDemotion: 1
UINT32 | PkgCStateDemotion: 1
Enable or Disable Package Cstate Demotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
UINT32 | PkgCStateUnDemotion: 1
Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
UINT32 | CStatePreWake: 1
Enable or Disable CState-Pre wake. Disable; 1: Enable
UINT32 | TimedMwait: 1
Enable or Disable TimedMwait Support. Disable; 1: Enable.
UINT32 | CstCfgCtrIoMwaitRedirection: 1
Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
UINT32 | ProcHotLock: 1
If enabled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable.
UINT32 | RaceToHalt: 1
Enable or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
UINT32 | ConfigTdpLevel: 8
UINT16 | CstateLatencyControl1Irtl
Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto.
UINT16 | CstateLatencyControl2Irtl
Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto.
UINT16 | CstateLatencyControl3Irtl
Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto.
UINT16 | CstateLatencyControl4Irtl
Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto.
UINT16 | CstateLatencyControl5Irtl
Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto.
UINT16 | CstateLatencyControl0Irtl
Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].0 is Auto.
MAX_PKG_C_STATE PkgCStateLimit
Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit
Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns. More...
C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit
Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit
Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit
Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit
Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns.
C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit
Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns.
CUSTOM_POWER_UNIT CustomPowerUnit
Offset 51 Default power unit in watts or in 125 milliwatt increments. More...
PPM_IRM_SETTING PpmIrmSetting
Offset 52 Interrupt Redirection Mode Select. More...
UINT8 | Rsvd [4]
Offset 53-56 Reserved for future use and config block alignment.

Detailed Description

CPU Power Management Test Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add CstateLatencyControl0TimeUnit for WHL only
  • Add CstateLatencyControl0Irtl for WHL only Revision 3:
  • Change C State LatencyContol to Auto as default. Revision 4:
  • Add CstateLatencyControl0TimeUnit and CstateLatencyControl0Irtl. Revision 5:
  • Change EnergyEfficientTurbo to Disable as default. Revision 6:
  • Change ProcHotResponse and ProcHotLock to Enable as default. Revision 7:
  • Deprecate ConfigTdpLevel. Move to premem.

Definition at line 117 of file CpuPowerMgmtTestConfig.h.

Member Data Documentation

◆ C3AutoDemotion

UINT32 CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
Deprecated:
no longer used

Definition at line 134 of file CpuPowerMgmtTestConfig.h.

◆ C3UnDemotion

UINT32 CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
Deprecated:
no longer used

Definition at line 135 of file CpuPowerMgmtTestConfig.h.

◆ ConfigTdpLevel

UINT32 CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
Deprecated:
Move to premem phase.

Definition at line 143 of file CpuPowerMgmtTestConfig.h.

◆ CstateLatencyControl0TimeUnit

C_STATE_TIME_UNIT CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit

Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns.

Todo:
: The following enums have to be replaced with policies.

Definition at line 154 of file CpuPowerMgmtTestConfig.h.

◆ CustomPowerUnit

CUSTOM_POWER_UNIT CPU_POWER_MGMT_TEST_CONFIG::CustomPowerUnit

Offset 51 Default power unit in watts or in 125 milliwatt increments.

  • 0: PowerUnitWatts.
  • 1: PowerUnit125MilliWatts.

Definition at line 165 of file CpuPowerMgmtTestConfig.h.

◆ PpmIrmSetting

PPM_IRM_SETTING CPU_POWER_MGMT_TEST_CONFIG::PpmIrmSetting

Offset 52 Interrupt Redirection Mode Select.

  • 0: Fixed priority. //Default under CNL.
  • 1: Round robin.
  • 2: Hash vector.
  • 4: PAIR with fixed priority. //Default under KBL, not available under CNL.
  • 5: PAIR with round robin. //Not available under CNL.
  • 6: PAIR with hash vector. //Not available under CNL.
  • 7: No change.

Definition at line 176 of file CpuPowerMgmtTestConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtTestConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_POWER_MGMT_TEST_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_TEST_CONFIG, including all inherited members.

BiProcHot | CPU_POWER_MGMT_TEST_CONFIG
C1AutoDemotion | CPU_POWER_MGMT_TEST_CONFIG
C1e | CPU_POWER_MGMT_TEST_CONFIG
C1UnDemotion | CPU_POWER_MGMT_TEST_CONFIG
C3AutoDemotion | CPU_POWER_MGMT_TEST_CONFIG
C3UnDemotion | CPU_POWER_MGMT_TEST_CONFIG
ConfigTdpLevel | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl0Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl0TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl1Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl1TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl2Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl2TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl3Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl3TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl4Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl4TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl5Irtl | CPU_POWER_MGMT_TEST_CONFIG
CstateLatencyControl5TimeUnit | CPU_POWER_MGMT_TEST_CONFIG
CStatePreWake | CPU_POWER_MGMT_TEST_CONFIG
CstCfgCtrIoMwaitRedirection | CPU_POWER_MGMT_TEST_CONFIG
CustomPowerUnit | CPU_POWER_MGMT_TEST_CONFIG
Cx | CPU_POWER_MGMT_TEST_CONFIG
DisableProcHotOut | CPU_POWER_MGMT_TEST_CONFIG
DisableVrThermalAlert | CPU_POWER_MGMT_TEST_CONFIG
Eist | CPU_POWER_MGMT_TEST_CONFIG
EnableAllThermalFunctions | CPU_POWER_MGMT_TEST_CONFIG
EnergyEfficientPState | CPU_POWER_MGMT_TEST_CONFIG
EnergyEfficientTurbo | CPU_POWER_MGMT_TEST_CONFIG
Header | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateDemotion | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateLimit | CPU_POWER_MGMT_TEST_CONFIG
PkgCStateUnDemotion | CPU_POWER_MGMT_TEST_CONFIG
PmgCstCfgCtrlLock | CPU_POWER_MGMT_TEST_CONFIG
PpmIrmSetting | CPU_POWER_MGMT_TEST_CONFIG
ProcHotLock | CPU_POWER_MGMT_TEST_CONFIG
ProcHotResponse | CPU_POWER_MGMT_TEST_CONFIG
RaceToHalt | CPU_POWER_MGMT_TEST_CONFIG
Rsvd | CPU_POWER_MGMT_TEST_CONFIG
ThermalMonitor | CPU_POWER_MGMT_TEST_CONFIG
TimedMwait | CPU_POWER_MGMT_TEST_CONFIG
TStates | CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_POWER_MGMT_VR_CONFIG Struct Reference

Public Attributes | List of all members
CPU_POWER_MGMT_VR_CONFIG Struct Reference

CPU Power Management VR Configuration Structure. More...

#include <CpuPowerMgmtVrConfig.h>

Collaboration diagram for CPU_POWER_MGMT_VR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | AcousticNoiseMitigation: 1
Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled.
UINT32 | SendVrMbxCmd: 2
Deprecated.
UINT32 | EnableMinVoltageOverride: 1
Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8. 0: Disabled 1: Enabled.
UINT32 | RfiMitigation: 1
Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
UINT32 | RsvdBits: 27
Reserved for future use.
UINT8 | PsysSlope
PCODE MMIO Mailbox: Platform Psys slope correction. 0: Auto Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
UINT8 | PsysOffset
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. Deprecated.
UINT8 | FivrSpreadSpectrum
PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range. More...
UINT16 | FivrRfiFrequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. More...
UINT16 | MinVoltageRuntime
PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range 0 to 1999mV. 0: 0mV
UINT16 | MinVoltageC8
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. 0: 0mV
UINT16 | PsysOffset1
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348.
UINT32 | TdcTimeWindow1 [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default
UINT8 | Irms [MAX_NUM_VRS]
PCODE MMIO Mailbox: Current root mean square. 0: Disable; 1: Enable.
UINT8 | FivrSpectrumEnable
Enable or Disable FIVR Spread Spectrum 0: Disable; 1: Enable.
UINT8 | DlvrSpreadSpectrumPercentage
PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7.75%.
UINT8 | DlvrRfiEnable
PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. 0: Disable. 1:Disable.
UINT8 | PreWake
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
UINT8 | RampUp
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max ramp up randomization time in micro ticks. Range is 0-255.
UINT8 | RampDown
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.Default Value = 0 micro ticks Defines the max ramp down randomization time in micro ticks. Range is 0-255.
UINT16 | VccInAuxImonIccImax
PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp increments. Range is 0-128A8.
UINT16 | VccInAuxImonSlope
PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto
INT16 | VccInAuxImonOffset
PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
UINT16 | DlvrRfiFrequency
PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
UINT8 | PS1toPS0DynamicCutoffEnable [MAX_NUM_VRS]
Enable/Disable PS1 to PS0 Dynamic Cutoff; 0: Disable; 1: Enable.
UINT8 | PS2toPS1DynamicCutoffEnable [MAX_NUM_VRS]
Enable/Disable:PS2 to PS1 Dynamic Cutoff; 0: Disable; 1: Enable.
UINT16 | PS1toPS0MCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS1 to PS0 M Coef. This number is in M*100 units. Default: 100 Range: 0-4096.
INT16 | PS1toPS0CCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS1 to PS0 C Coef. This number is in C*100 units. Default: 2000 Range: 0-4096.
UINT16 | PS2toPS1MCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS2 to PS1 M Coef. This number is in M*100 units. Default: 100 Range: 0-4096.
INT16 | PS2toPS1CCoef [MAX_NUM_VRS]
PCODE MMIO Mailbox: PS2 to PS1 C Coef. This number is in C*100 units. Default: 500 Range: 0-4096.
UINT8 | VrPowerDeliveryDesign
This field is required to be non-zero on Desktop platforms. More...
UINT8 | VccInDemotionEnable [MAX_NUM_VRS]
Enable VCC Demotion. More...
UINT8 | VccInDemotionQuiescentPowerInMw [MAX_NUM_VRS]
User configured platform quiescent threshold in milli-watt when VCC Demotion is enabled with user configured threshold. More...
UINT8 | Rsvd5 [2]
Make next field 4-byte aligned.
UINT32 | VccInDemotionCapacitanceInUf [MAX_NUM_VRS]
User configured VR's quiescent power threshold in micro-farad when VCC Demotion is enabled with user configured threshold. More...
UINT8 | EnableVsysCritical
PCODE MMIO Mailbox: Enable/Disable Vsys Critical; 0: Disable; 1: Enable.
UINT8 | VsysFullScale
Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage where minimun is 0 and maximum is 255. More...
UINT8 | VsysAssertionDeglitchMantissa
Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent. More...
UINT16 | IccLimit [MAX_NUM_VRS]
PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit. More...
VR Settings

The VR related settings are sorted in an array where each index maps to the VR domain as defined below:

  • 0 = System Agent VR
  • 1 = IA Core VR
  • 2 = Ring Vr
  • 3 = GT VR
  • 4 = FIVR VR

The VR settings for a given domain must be populated in the appropriate index.

UINT16 | TdcCurrentLimit [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. 0: 0 Amps
UINT16 | AcLoadline [MAX_NUM_VRS]
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. Intel Recommended Defaults vary by domain and SKU.
UINT16 | DcLoadline [MAX_NUM_VRS]
PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.Intel Recommended Defaults vary by domain and SKU.
UINT16 | Psi1Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
UINT16 | Psi2Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
UINT16 | Psi3Threshold [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
INT16 | ImonOffset [MAX_NUM_VRS]
PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto
UINT16 | IccMax [MAX_NUM_VRS]
PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A. Default: 0 - Auto, no override
UINT16 | VrVoltageLimit [MAX_NUM_VRS]
PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
UINT16 | ImonSlope [MAX_NUM_VRS]
PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. 0: Auto
UINT8 | Psi3Enable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable.
UINT8 | Psi4Enable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.
UINT8 | VrConfigEnable [MAX_NUM_VRS]
Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.
UINT8 | TdcEnable [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.
UINT8 | TdcTimeWindow [MAX_NUM_VRS]
UINT8 | TdcLock [MAX_NUM_VRS]
PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.
UINT8 | FastPkgCRampDisable [MAX_NUM_VRS]
Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: False; 1: True.
UINT8 | SlowSlewRate [MAX_NUM_VRS]
Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16.

Detailed Description

CPU Power Management VR Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Updated Acoustic Noise Mitigation. Revision 3:
  • Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction Revision 4:
  • Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time Added Irms support. Revision 5:
  • Add RfiMitigation. Revision 6:
  • Add Dynamic Periodicity Alteration (DPA) tuning feature Revision 7:
  • Add VccIn Aux Imon feature Revision 8:
  • Deprecate SendVrMbxCmd Revision 9:
  • Added an option to Enable/Disable FIVR Spread Spectrum Revision 10:
  • Add DlvrRfiEnable, DlvrSpreadSpectrumPercentage and DlvrRfiFrequency for RFI control. Revision 11:
  • Added an option to Enable/Disable PS1 to PS0/PS2 to PS1 dynamic cutoff Revision 12:
  • Added an option for Vr Power Delivery design Revision 13:
  • Add VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf Revision 14:
  • Add EnableVsysCritical, VsysFullScale,VsysCriticalThreshold, VsysAssertionDeglitchMantissa
  • VsysAssertionDeglitchExponent, VsysDeassertionDeglitchMantissa, VsysDeassertionDeglitchExponent Revision 15:
  • Add Voltage Regulator Fast Vmode ICC Limit Revision 16:
  • Modified IccMax range up to 512A

Definition at line 88 of file CpuPowerMgmtVrConfig.h.

Member Data Documentation

◆ FivrRfiFrequency

UINT16 CPU_POWER_MGMT_VR_CONFIG::FivrRfiFrequency

PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.

0: Auto Range varies based on XTAL clock:

  • 0-1918 (Up to 191.8HMz) for 24MHz clock.
  • 0-1535 (Up to 153.5MHz) for 19MHz clock.

Definition at line 114 of file CpuPowerMgmtVrConfig.h.

◆ FivrSpreadSpectrum

UINT8 CPU_POWER_MGMT_VR_CONFIG::FivrSpreadSpectrum

PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.

1.5% Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.

Definition at line 105 of file CpuPowerMgmtVrConfig.h.

◆ IccLimit

UINT16 CPU_POWER_MGMT_VR_CONFIG::IccLimit[MAX_NUM_VRS]

PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit.

This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled. A value of 0 corresponds to feature disabled (no reactive protection). Default: 0 - Disable, no override

Definition at line 227 of file CpuPowerMgmtVrConfig.h.

◆ TdcTimeWindow

UINT8 CPU_POWER_MGMT_VR_CONFIG::TdcTimeWindow[MAX_NUM_VRS]
Deprecated:
. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. 1ms default

Definition at line 141 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionCapacitanceInUf

UINT32 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionCapacitanceInUf[MAX_NUM_VRS]

User configured VR's quiescent power threshold in micro-farad when VCC Demotion is enabled with user configured threshold.

Range: 0-2000.

Definition at line 200 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionEnable

UINT8 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionEnable[MAX_NUM_VRS]

Enable VCC Demotion.

0: Disable; 1: Enable with default threshold; 2: Enable with user configured threshold.

Definition at line 187 of file CpuPowerMgmtVrConfig.h.

◆ VccInDemotionQuiescentPowerInMw

UINT8 CPU_POWER_MGMT_VR_CONFIG::VccInDemotionQuiescentPowerInMw[MAX_NUM_VRS]

User configured platform quiescent threshold in milli-watt when VCC Demotion is enabled with user configured threshold.

Range: 0-255.

Definition at line 193 of file CpuPowerMgmtVrConfig.h.

◆ VrPowerDeliveryDesign

UINT8 CPU_POWER_MGMT_VR_CONFIG::VrPowerDeliveryDesign

This field is required to be non-zero on Desktop platforms.

Used to communicate the power delivery design capability of the board. This value is an enum of the available power delivery segments that are defined in the Platform Design Guide. This is required due to CPU socket compatibility across different board designs. Without this field populated, the system may experience VR OCP/OVP shutdowns, hangs, thermal and performance loss. 0 - Disable

Definition at line 179 of file CpuPowerMgmtVrConfig.h.

◆ VsysAssertionDeglitchMantissa

UINT8 CPU_POWER_MGMT_VR_CONFIG::VsysAssertionDeglitchMantissa

Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent.

The format for Assertion/De-Assertion Deglitch: 0.002ms * Mantissa * 2^(Exponent).

Definition at line 216 of file CpuPowerMgmtVrConfig.h.

◆ VsysFullScale

UINT8 CPU_POWER_MGMT_VR_CONFIG::VsysFullScale

Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage where minimun is 0 and maximum is 255.

Default 0 For example: Vsys_Crit (0x4A) = (Critical Threshold/Full Scale) * 0xFF

Definition at line 209 of file CpuPowerMgmtVrConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtVrConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_POWER_MGMT_VR_CONFIG Member List

This is the complete list of members for CPU_POWER_MGMT_VR_CONFIG, including all inherited members.

AcLoadline | CPU_POWER_MGMT_VR_CONFIG
AcousticNoiseMitigation | CPU_POWER_MGMT_VR_CONFIG
DcLoadline | CPU_POWER_MGMT_VR_CONFIG
DlvrRfiEnable | CPU_POWER_MGMT_VR_CONFIG
DlvrRfiFrequency | CPU_POWER_MGMT_VR_CONFIG
DlvrSpreadSpectrumPercentage | CPU_POWER_MGMT_VR_CONFIG
EnableMinVoltageOverride | CPU_POWER_MGMT_VR_CONFIG
EnableVsysCritical | CPU_POWER_MGMT_VR_CONFIG
FastPkgCRampDisable | CPU_POWER_MGMT_VR_CONFIG
FivrRfiFrequency | CPU_POWER_MGMT_VR_CONFIG
FivrSpectrumEnable | CPU_POWER_MGMT_VR_CONFIG
FivrSpreadSpectrum | CPU_POWER_MGMT_VR_CONFIG
Header | CPU_POWER_MGMT_VR_CONFIG
IccLimit | CPU_POWER_MGMT_VR_CONFIG
IccMax | CPU_POWER_MGMT_VR_CONFIG
ImonOffset | CPU_POWER_MGMT_VR_CONFIG
ImonSlope | CPU_POWER_MGMT_VR_CONFIG
Irms | CPU_POWER_MGMT_VR_CONFIG
MinVoltageC8 | CPU_POWER_MGMT_VR_CONFIG
MinVoltageRuntime | CPU_POWER_MGMT_VR_CONFIG
PreWake | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0CCoef | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0DynamicCutoffEnable | CPU_POWER_MGMT_VR_CONFIG
PS1toPS0MCoef | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1CCoef | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1DynamicCutoffEnable | CPU_POWER_MGMT_VR_CONFIG
PS2toPS1MCoef | CPU_POWER_MGMT_VR_CONFIG
Psi1Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi2Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi3Enable | CPU_POWER_MGMT_VR_CONFIG
Psi3Threshold | CPU_POWER_MGMT_VR_CONFIG
Psi4Enable | CPU_POWER_MGMT_VR_CONFIG
PsysOffset | CPU_POWER_MGMT_VR_CONFIG
PsysOffset1 | CPU_POWER_MGMT_VR_CONFIG
PsysSlope | CPU_POWER_MGMT_VR_CONFIG
RampDown | CPU_POWER_MGMT_VR_CONFIG
RampUp | CPU_POWER_MGMT_VR_CONFIG
RfiMitigation | CPU_POWER_MGMT_VR_CONFIG
Rsvd5 | CPU_POWER_MGMT_VR_CONFIG
RsvdBits | CPU_POWER_MGMT_VR_CONFIG
SendVrMbxCmd | CPU_POWER_MGMT_VR_CONFIG
SlowSlewRate | CPU_POWER_MGMT_VR_CONFIG
TdcCurrentLimit | CPU_POWER_MGMT_VR_CONFIG
TdcEnable | CPU_POWER_MGMT_VR_CONFIG
TdcLock | CPU_POWER_MGMT_VR_CONFIG
TdcTimeWindow | CPU_POWER_MGMT_VR_CONFIG
TdcTimeWindow1 | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonIccImax | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonOffset | CPU_POWER_MGMT_VR_CONFIG
VccInAuxImonSlope | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionCapacitanceInUf | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionEnable | CPU_POWER_MGMT_VR_CONFIG
VccInDemotionQuiescentPowerInMw | CPU_POWER_MGMT_VR_CONFIG
VrConfigEnable | CPU_POWER_MGMT_VR_CONFIG
VrPowerDeliveryDesign | CPU_POWER_MGMT_VR_CONFIG
VrVoltageLimit | CPU_POWER_MGMT_VR_CONFIG
VsysAssertionDeglitchMantissa | CPU_POWER_MGMT_VR_CONFIG
VsysFullScale | CPU_POWER_MGMT_VR_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_SECURITY_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_SECURITY_PREMEM_CONFIG Struct Reference

CPU Security PreMemory Configuration Structure. More...

#include <CpuSecurityPreMemConfig.h>

Collaboration diagram for CPU_SECURITY_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PrmrrSize
PRMRR Size.Software Control: 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB: 0x10000000, 512 MB: 0x20000000.
UINT16 | BiosSize
Flash information for BIOS Guard: BIOS Size in KB.
UINT8 | Reserved [2]
Reserved for future use.
UINT32 | BiosGuard: 1
Enable or Disable BIOS Guard; 0: Disable; 1: Enable. More...
UINT32 | BiosGuardToolsInterface: 1
BIOS Guard Tools Interface; 0: Disable, 1:Enable.
UINT32 | EnableSgx: 1
Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable. More...
UINT32 | Txt: 1
Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable. More...
UINT32 | SkipStopPbet: 1
(Test) Skip Stop PBET Timer; 0: Disable; 1: Enable.
UINT32 | EnableC6Dram: 1
(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature. More...
UINT32 | ResetAux: 1
(Test) Reset Auxiliary content, 0: Disabled, 1: Enabled
UINT32 | TxtAcheckRequest: 1
(Test) AcheckRequest 0: Disabled, 1: Enabled. When Enabled, it will call Acheck regardless of crashcode value
UINT32 | RsvdBits: 24
Reserved for future use.

Detailed Description

CPU Security PreMemory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Deprecated SGx

Definition at line 52 of file CpuSecurityPreMemConfig.h.

Member Data Documentation

◆ BiosGuard

UINT32 CPU_SECURITY_PREMEM_CONFIG::BiosGuard

Enable or Disable BIOS Guard; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG will be ignored.
  • If PeiBiosGuardLibNull is used, this policy will have no effect.

Definition at line 63 of file CpuSecurityPreMemConfig.h.

◆ EnableC6Dram

UINT32 CPU_SECURITY_PREMEM_CONFIG::EnableC6Dram

(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.

  • 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.
  • 1: Allocate PRMRR memory for C6DRAM power gating feature.

Definition at line 85 of file CpuSecurityPreMemConfig.h.

◆ EnableSgx

UINT32 CPU_SECURITY_PREMEM_CONFIG::EnableSgx

Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG will be ignored.
  • If BaseSoftwareGuardLibNull is used, this policy will have no effect.
    Deprecated:
    due to Non-POR feature.

Definition at line 71 of file CpuSecurityPreMemConfig.h.

◆ Txt

UINT32 CPU_SECURITY_PREMEM_CONFIG::Txt

Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable.

  • This is an optional feature and can be opted out.
  • If this policy is set to Disabled, the policies in the CPU_TXT_PREMEM_CONFIG will be ignored.
  • If PeiTxtLibNull is used, this policy will have no effect.

Definition at line 78 of file CpuSecurityPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • CpuSecurityPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_SECURITY_PREMEM_CONFIG Member List

This is the complete list of members for CPU_SECURITY_PREMEM_CONFIG, including all inherited members.

BiosGuard | CPU_SECURITY_PREMEM_CONFIG
BiosGuardToolsInterface | CPU_SECURITY_PREMEM_CONFIG
BiosSize | CPU_SECURITY_PREMEM_CONFIG
EnableC6Dram | CPU_SECURITY_PREMEM_CONFIG
EnableSgx | CPU_SECURITY_PREMEM_CONFIG
Header | CPU_SECURITY_PREMEM_CONFIG
PrmrrSize | CPU_SECURITY_PREMEM_CONFIG
Reserved | CPU_SECURITY_PREMEM_CONFIG
ResetAux | CPU_SECURITY_PREMEM_CONFIG
RsvdBits | CPU_SECURITY_PREMEM_CONFIG
SkipStopPbet | CPU_SECURITY_PREMEM_CONFIG
Txt | CPU_SECURITY_PREMEM_CONFIG
TxtAcheckRequest | CPU_SECURITY_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_TEST_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TEST_CONFIG Struct Reference

CPU Test Configuration Structure. More...

#include <CpuTestConfig.h>

Collaboration diagram for CPU_TEST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | MlcStreamerPrefetcher: 1
Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
UINT32 | MlcSpatialPrefetcher: 1
Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable.
UINT32 | MonitorMwaitEnable: 1
Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
UINT32 | MachineCheckEnable: 1
Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
UINT32 | ProcessorTraceOutputScheme: 1
Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
UINT32 | ProcessorTraceEnable: 1
Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
UINT32 | ThreeStrikeCounterDisable: 1
Disable Three strike counter; 0: FALSE; 1: TRUE.
UINT32 | RsvdBits: 25
Reserved for future use.
UINT32 | ProcessorTraceMemSize
Memory size per thread for Processor Trace. More...

Detailed Description

CPU Test Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Removed Voltage Optimization feature. Revision 3:
  • Add PostedInterruptCapability

Definition at line 54 of file CpuTestConfig.h.

Member Data Documentation

◆ ProcessorTraceMemSize

UINT32 CPU_TEST_CONFIG::ProcessorTraceMemSize

Memory size per thread for Processor Trace.

Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.

  • 0: Disable

Definition at line 69 of file CpuTestConfig.h.

The documentation for this struct was generated from the following file:
  • CpuTestConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_TEST_CONFIG Member List

This is the complete list of members for CPU_TEST_CONFIG, including all inherited members.

Header | CPU_TEST_CONFIG
MachineCheckEnable | CPU_TEST_CONFIG
MlcSpatialPrefetcher | CPU_TEST_CONFIG
MlcStreamerPrefetcher | CPU_TEST_CONFIG
MonitorMwaitEnable | CPU_TEST_CONFIG
ProcessorTraceEnable | CPU_TEST_CONFIG
ProcessorTraceMemSize | CPU_TEST_CONFIG
ProcessorTraceOutputScheme | CPU_TEST_CONFIG
RsvdBits | CPU_TEST_CONFIG
ThreeStrikeCounterDisable | CPU_TEST_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_TRACE_HUB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TRACE_HUB_PREMEM_CONFIG Struct Reference

CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for CPU_TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.

Detailed Description

CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version.

Definition at line 112 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for CPU_TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | CPU_TRACE_HUB_PREMEM_CONFIG
TraceHub | CPU_TRACE_HUB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CPU_TXT_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
CPU_TXT_PREMEM_CONFIG Struct Reference

CPU TXT PreMemory Configuration Structure. More...

#include <CpuTxtConfig.h>

Collaboration diagram for CPU_TXT_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | SinitMemorySize
Size of SINIT module if installed in flash part. Zero otherwise.
UINT32 | TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
UINT32 | TxtDprMemorySize
Size of DPR protected memory reserved for Intel TXT component.
EFI_PHYSICAL_ADDRESS | TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
UINT64 | TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
EFI_PHYSICAL_ADDRESS | TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
EFI_PHYSICAL_ADDRESS | ApStartupBase
Base address of TXT AP Startup code.
EFI_PHYSICAL_ADDRESS | BiosAcmBase
Base address of BIOS ACM in flash part.
UINT32 | BiosAcmSize
Size of ACM Binary.
UINT32 | TgaSize
Size of Trusted Graphics Aperture if supported by chipset.

Detailed Description

CPU TXT PreMemory Configuration Structure.

Note
Optional. These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> Txt is disabled, or PeiTxtLibNull is used.

Revision 1:

  • Initial version.

Definition at line 51 of file CpuTxtConfig.h.

The documentation for this struct was generated from the following file:
  • CpuTxtConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

CPU_TXT_PREMEM_CONFIG Member List

This is the complete list of members for CPU_TXT_PREMEM_CONFIG, including all inherited members.

ApStartupBase | CPU_TXT_PREMEM_CONFIG
BiosAcmBase | CPU_TXT_PREMEM_CONFIG
BiosAcmSize | CPU_TXT_PREMEM_CONFIG
Header | CPU_TXT_PREMEM_CONFIG
SinitMemorySize | CPU_TXT_PREMEM_CONFIG
TgaSize | CPU_TXT_PREMEM_CONFIG
TxtDprMemoryBase | CPU_TXT_PREMEM_CONFIG
TxtDprMemorySize | CPU_TXT_PREMEM_CONFIG
TxtHeapMemorySize | CPU_TXT_PREMEM_CONFIG
TxtLcpPdBase | CPU_TXT_PREMEM_CONFIG
TxtLcpPdSize | CPU_TXT_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DDI_CONFIGURATION Struct Reference

Public Attributes | List of all members
DDI_CONFIGURATION Struct Reference

This structure configures the Native GPIOs for DDI port per VBT settings. More...

#include <GraphicsConfig.h>

Public Attributes

UINT8 | DdiPortBConfig
The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set DdiPortA to MIPI DSI.
UINT8 | DdiPortAHpd
The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set DdiPortB to MIPI DSI.
UINT8 | DdiPortBHpd
The HPD setting of DDI Port A, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortCHpd
The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD
UINT8 | DdiPort1Hpd
The HPD setting of DDI Port C, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort2Hpd
The HPD setting of DDI Port 1, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort3Hpd
The HPD setting of DDI Port 2, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPort4Hpd
The HPD setting of DDI Port 3, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortADdc
The HPD setting of DDI Port 4, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - Enable HPD.
UINT8 | DdiPortBDdc
The DDC setting of DDI Port A, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPortCDdc
The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC
UINT8 | DdiPort1Ddc
The DDC setting of DDI Port C, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort2Ddc
The DDC setting of DDI Port 1, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort3Ddc
The DDC setting of DDI Port 2, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.
UINT8 | DdiPort4Ddc
The DDC setting of DDI Port 3, this settings must match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enable DDC.

Detailed Description

This structure configures the Native GPIOs for DDI port per VBT settings.

Definition at line 69 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DDI_CONFIGURATION Member List

This is the complete list of members for DDI_CONFIGURATION, including all inherited members.

DdiPort1Ddc | DDI_CONFIGURATION
DdiPort1Hpd | DDI_CONFIGURATION
DdiPort2Ddc | DDI_CONFIGURATION
DdiPort2Hpd | DDI_CONFIGURATION
DdiPort3Ddc | DDI_CONFIGURATION
DdiPort3Hpd | DDI_CONFIGURATION
DdiPort4Ddc | DDI_CONFIGURATION
DdiPort4Hpd | DDI_CONFIGURATION
DdiPortADdc | DDI_CONFIGURATION
DdiPortAHpd | DDI_CONFIGURATION
DdiPortBConfig | DDI_CONFIGURATION
DdiPortBDdc | DDI_CONFIGURATION
DdiPortBHpd | DDI_CONFIGURATION
DdiPortCDdc | DDI_CONFIGURATION
DdiPortCHpd | DDI_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DIMM_INFO Struct Reference

Public Attributes | List of all members
DIMM_INFO Struct Reference

Memory SMBIOS & OC Memory Data Hob. More...

#include <MemInfoHob.h>

Public Attributes

UINT8 | Status
See MrcDimmStatus for the definition of this field.
UINT32 | DimmCapacity
DIMM size in MBytes.
UINT8 | ModulePartNum [20]
Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes.
UINT8 | RankInDimm
The number of ranks in this DIMM.
UINT8 | SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 | SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 | SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 | SpdSave [MAX_SPD_SAVE]
Save SPD Manufacturing information needed for SMBIOS structure creation.
UINT16 | Speed
The maximum capable speed of the device, in MHz.
UINT8 | MdSocket
MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.

Detailed Description

Memory SMBIOS & OC Memory Data Hob.

Definition at line 209 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DIMM_INFO Member List

This is the complete list of members for DIMM_INFO, including all inherited members.

DimmCapacity | DIMM_INFO
MdSocket | DIMM_INFO
ModulePartNum | DIMM_INFO
RankInDimm | DIMM_INFO
SpdDramDeviceType | DIMM_INFO
SpdModuleMemoryBusWidth | DIMM_INFO
SpdModuleType | DIMM_INFO
SpdSave | DIMM_INFO
Speed | DIMM_INFO
Status | DIMM_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DMI_HW_WIDTH_CONTROL Struct Reference

Public Attributes | List of all members
DMI_HW_WIDTH_CONTROL Struct Reference

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | DmiTsawEn: 1
DMI Thermal Sensor Autonomous Width Enable.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 6
Reserved bits.
UINT32 | TS0TW: 3
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
UINT32 | TS1TW: 3
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
UINT32 | TS2TW: 3
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
UINT32 | TS3TW: 3
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
UINT32 | RsvdBits1: 12
Reserved bits.

Detailed Description

This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.

When the SuggestedSetting is enabled, the customized values are ignored. Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values

Definition at line 89 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DMI_HW_WIDTH_CONTROL Member List

This is the complete list of members for DMI_HW_WIDTH_CONTROL, including all inherited members.

DmiTsawEn | DMI_HW_WIDTH_CONTROL
RsvdBits0 | DMI_HW_WIDTH_CONTROL
RsvdBits1 | DMI_HW_WIDTH_CONTROL
SuggestedSetting | DMI_HW_WIDTH_CONTROL
TS0TW | DMI_HW_WIDTH_CONTROL
TS1TW | DMI_HW_WIDTH_CONTROL
TS2TW | DMI_HW_WIDTH_CONTROL
TS3TW | DMI_HW_WIDTH_CONTROL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DNX_REQ_CLEAR Struct Reference

List of all members
DNX_REQ_CLEAR Struct Reference

DNX Request Clear. More...

#include <MkhiMsgs.h>

Collaboration diagram for DNX_REQ_CLEAR:
[legend]

Detailed Description

DNX Request Clear.

Definition at line 857 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DNX_REQ_CLEAR Member List

This is the complete list of members for DNX_REQ_CLEAR, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DNX_REQ_SET Struct Reference

List of all members
DNX_REQ_SET Struct Reference

DNX Request Set. More...

#include <MkhiMsgs.h>

Collaboration diagram for DNX_REQ_SET:
[legend]

Detailed Description

DNX Request Set.

Definition at line 840 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DNX_REQ_SET Member List

This is the complete list of members for DNX_REQ_SET, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DPIN_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
DPIN_PREMEM_CONFIG Struct Reference

This configuration block describes DPIN settings. More...

#include <DpInPreMemConfig.h>

Collaboration diagram for DPIN_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
< Header: Struct Header Offset 0-27 Config Block Header More...
UINT8 | DpInExternalEn
NumberOfDpInPort: Total number of DpIn Port present on Board.
UINT8 | NumberOfDpInPort
DpInPortConnectMap: Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port.
UINT8 | DpInPortConnectMap
Reserved bytes for future use, align to DWORD.

Detailed Description

This configuration block describes DPIN settings.

Revision 1:

  • Initial version.

Definition at line 50 of file DpInPreMemConfig.h.

Member Data Documentation

◆ Header

CONFIG_BLOCK_HEADER DPIN_PREMEM_CONFIG::Header

< Header: Struct Header Offset 0-27 Config Block Header

DpInExternalEn: 00 = Dp-In Port is Internal Only, 01 = Dp-In Port is External First.

Definition at line 52 of file DpInPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • DpInPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DPIN_PREMEM_CONFIG Member List

This is the complete list of members for DPIN_PREMEM_CONFIG, including all inherited members.

DpInExternalEn | DPIN_PREMEM_CONFIG
DpInPortConnectMap | DPIN_PREMEM_CONFIG
Header | DPIN_PREMEM_CONFIG
NumberOfDpInPort | DPIN_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DXE_CPU_POLICY_PROTOCOL Struct Reference

Public Attributes | List of all members
DXE_CPU_POLICY_PROTOCOL Struct Reference

The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor in the DXE phase. More...

#include <CpuPolicyProtocol.h>

Public Attributes

UINT32 | DgrEnable: 1
Policy to obtain DGR status from setup option. More...
UINT32 | DgrSpaEnable: 1
Policy to obtain DGR-SPA status from setup option. More...
UINT32 | DgrStateSaveProtect: 1
Policy to obtain DGR State Save support status from setup option. More...
UINT32 | DgrSkipOemExceptionHandler: 1
Policy to obtain DGR Skip OEM Exception Handler from setup option. More...
UINT32 | RsvdBit: 26
Reserved bits, align to multiple 32;.
UINT8 | Revision
Current revision of policy.
UINT8 | SmmMsrSaveStateEnable
Indidates if SMM Save State saved in MSRs. More...
UINT8 | SmmUseDelayIndication
Indidates if SMM Delay feature is supported. More...
UINT8 | SmmUseBlockIndication
Indidates if SMM Block feature is supported. More...
UINT8 | SmmUseSmmEnableIndication
Indidates if SMM Enable/Disable feature is supported. More...
UINT8 | SmmProcTraceEnable
Specifies if SMM Proccessor Trace will be Enabled. More...
UINT8 | ReservedByte [6]
Reserved bytes, align to multiple 8.

Detailed Description

The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor in the DXE phase.

This Policy Protocol needs to be initialized for CPU configuration.

Note
The Protocol has to be published before processor DXE drivers are dispatched.

This member specifies the revision of the Cpu Policy protocol. This field is used to indicate backward compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.

Revision 1:

  • Initial version Revision 2:
  • Added DgrEnable to obtain DGR status from setup option. Revision 3:
  • Add SmmMsrSaveStateEnable, SmmUseDelayIndication, SmmUseBlockIndication, SmmUseSmmEnableIndication, SmmProcTraceEnable. Revision 4:
  • Added DgrSpaEnable to obtain DGR-SPA status from setup option. Revision 5:
  • Added DgrStateSaveProtect to obtain DGR State Save status from setup option. Revision 6:

Added DgrSkipOemExceptionHandler to Obtain DGR Skip OEM Exception Handler status from setup option. Revision 7:

  • Removed EnableDts.

Definition at line 71 of file CpuPolicyProtocol.h.

Member Data Documentation

◆ DgrEnable

UINT32 DXE_CPU_POLICY_PROTOCOL::DgrEnable

Policy to obtain DGR status from setup option.

  • 0: DGR is disabled.
  • 1: DGR is enabled.

Definition at line 77 of file CpuPolicyProtocol.h.

◆ DgrSkipOemExceptionHandler

UINT32 DXE_CPU_POLICY_PROTOCOL::DgrSkipOemExceptionHandler

Policy to obtain DGR Skip OEM Exception Handler from setup option.

  • 0: OEM exception handler will execute normal way in case of resource access violation.
  • 1: OEM Exception handler will be skipped and exceution continues in case of resource access volation.

Definition at line 95 of file CpuPolicyProtocol.h.

◆ DgrSpaEnable

UINT32 DXE_CPU_POLICY_PROTOCOL::DgrSpaEnable

Policy to obtain DGR-SPA status from setup option.

  • 0: DGR-SPA is disabled.
  • 1: DGR-SPA is enabled.

Definition at line 83 of file CpuPolicyProtocol.h.

◆ DgrStateSaveProtect

UINT32 DXE_CPU_POLICY_PROTOCOL::DgrStateSaveProtect

Policy to obtain DGR State Save support status from setup option.

  • 0: SMM can have Read/Write access to SMM State Save region .
  • 1: SMM State Save region access is protected.

Definition at line 89 of file CpuPolicyProtocol.h.

◆ SmmMsrSaveStateEnable

UINT8 DXE_CPU_POLICY_PROTOCOL::SmmMsrSaveStateEnable

Indidates if SMM Save State saved in MSRs.

if enabled, SMM Save State will use the MSRs instead of the memory.

  • 0: FALSE - SMM Save State will use the memory.
  • 1: TRUE - SMM Save State will use the MSRs.

Definition at line 105 of file CpuPolicyProtocol.h.

◆ SmmProcTraceEnable

UINT8 DXE_CPU_POLICY_PROTOCOL::SmmProcTraceEnable

Specifies if SMM Proccessor Trace will be Enabled.

  • 0: FALSE - SMM Proccessor Trace will be disabled.
  • 1: TRUE - SMM Proccessor Trace will be enabled.

Definition at line 129 of file CpuPolicyProtocol.h.

◆ SmmUseBlockIndication

UINT8 DXE_CPU_POLICY_PROTOCOL::SmmUseBlockIndication

Indidates if SMM Block feature is supported.

  • 0: FALSE - SMM Block feature is not supported.
  • 1: TRUE - SMM Block feature is supported.

Definition at line 117 of file CpuPolicyProtocol.h.

◆ SmmUseDelayIndication

UINT8 DXE_CPU_POLICY_PROTOCOL::SmmUseDelayIndication

Indidates if SMM Delay feature is supported.

  • 0: FALSE - SMM Delay feature is not supported.
  • 1: TRUE - SMM Delay feature is supported.

Definition at line 111 of file CpuPolicyProtocol.h.

◆ SmmUseSmmEnableIndication

UINT8 DXE_CPU_POLICY_PROTOCOL::SmmUseSmmEnableIndication

Indidates if SMM Enable/Disable feature is supported.

  • 0: FALSE - SMM Enable/Disable feature is not supported.
  • 1: TRUE - SMM Enable/Disable feature is supported.

Definition at line 123 of file CpuPolicyProtocol.h.

The documentation for this struct was generated from the following file:
  • CpuPolicyProtocol.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DXE_CPU_POLICY_PROTOCOL Member List

This is the complete list of members for DXE_CPU_POLICY_PROTOCOL, including all inherited members.

DgrEnable | DXE_CPU_POLICY_PROTOCOL
DgrSkipOemExceptionHandler | DXE_CPU_POLICY_PROTOCOL
DgrSpaEnable | DXE_CPU_POLICY_PROTOCOL
DgrStateSaveProtect | DXE_CPU_POLICY_PROTOCOL
ReservedByte | DXE_CPU_POLICY_PROTOCOL
Revision | DXE_CPU_POLICY_PROTOCOL
RsvdBit | DXE_CPU_POLICY_PROTOCOL
SmmMsrSaveStateEnable | DXE_CPU_POLICY_PROTOCOL
SmmProcTraceEnable | DXE_CPU_POLICY_PROTOCOL
SmmUseBlockIndication | DXE_CPU_POLICY_PROTOCOL
SmmUseDelayIndication | DXE_CPU_POLICY_PROTOCOL
SmmUseSmmEnableIndication | DXE_CPU_POLICY_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DXE_SI_POLICY_PROTOCOL Struct Reference

Public Attributes | List of all members
DXE_SI_POLICY_PROTOCOL Struct Reference

The protocol allows the platform code to publish a set of configuration information that the Silicon drivers will use to configure the processor in the DXE phase. More...

#include <SiPolicyProtocol.h>

Public Attributes

UINT8 | Revision
This member specifies the revision of the Si Policy protocol. More...
UINT8 | SmbiosOemTypeFirmwareVersionInfo
SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS, values 0-0x7F will be treated as disable FVI reporting. More...
UINT8 | ReservedByte [6]
Reserved bytes, align to multiple 8.
ADAPTER_INFO_PLATFORM_SECURITY * | Hsti
This member describes a pointer to Hsti results from previous boot. More...
UINTN | HstiSize
Size of results, if setting Hsti policy to point to previous results.

Detailed Description

The protocol allows the platform code to publish a set of configuration information that the Silicon drivers will use to configure the processor in the DXE phase.

This Policy Protocol needs to be initialized for Silicon configuration.

Note
The Protocol has to be published before processor DXE drivers are dispatched.

Definition at line 55 of file SiPolicyProtocol.h.

Member Data Documentation

◆ Hsti

ADAPTER_INFO_PLATFORM_SECURITY* DXE_SI_POLICY_PROTOCOL::Hsti

This member describes a pointer to Hsti results from previous boot.

In order to mitigate the large performance cost of performing all of the platform security tests on each boot, we can save the results across boots and retrieve and point this policy to them prior to the launch of HstiSiliconDxe. Logic should be implemented to not populate this upon major platform changes (i.e changes to setup option or platform hw)to ensure that results accurately reflect the configuration of the platform. This is a pointer to Hsti results from previous boot

Definition at line 80 of file SiPolicyProtocol.h.

◆ Revision

UINT8 DXE_SI_POLICY_PROTOCOL::Revision

This member specifies the revision of the Si Policy protocol.

This field is used to indicate backward compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.

Revision 1:

  • Initial version Revision 2:
  • Added SmbiosOemTypeFirmwareVersionInfo to determines the SMBIOS OEM type

Definition at line 65 of file SiPolicyProtocol.h.

◆ SmbiosOemTypeFirmwareVersionInfo

UINT8 DXE_SI_POLICY_PROTOCOL::SmbiosOemTypeFirmwareVersionInfo

SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS, values 0-0x7F will be treated as disable FVI reporting.

FVI structure uses it as SMBIOS OEM type to provide version information.

Definition at line 71 of file SiPolicyProtocol.h.

The documentation for this struct was generated from the following file:
  • SiPolicyProtocol.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

DXE_SI_POLICY_PROTOCOL Member List

This is the complete list of members for DXE_SI_POLICY_PROTOCOL, including all inherited members.

Hsti | DXE_SI_POLICY_PROTOCOL
HstiSize | DXE_SI_POLICY_PROTOCOL
ReservedByte | DXE_SI_POLICY_PROTOCOL
Revision | DXE_SI_POLICY_PROTOCOL
SmbiosOemTypeFirmwareVersionInfo | DXE_SI_POLICY_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FIPS_VERSION Struct Reference

List of all members
FIPS_VERSION Struct Reference

Get FIPS Mode. More...

#include <MkhiMsgs.h>

Detailed Description

Get FIPS Mode.

Definition at line 1154 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FIPS_VERSION Member List

This is the complete list of members for FIPS_VERSION, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FIVR_EXT_RAIL_CONFIG Struct Reference

Public Attributes | List of all members
FIVR_EXT_RAIL_CONFIG Struct Reference

Structure for V1p05/Vnn VR rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT32 | EnabledStates: 6
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_SX_STATE The default is FivrRailDisabled.
UINT32 | Voltage: 11
VR rail voltage value that will be used in S0i2/S0i3 states. More...
UINT32 | IccMax: 8
UINT32 | RsvdBits1: 7
UINT32 Alignement.
UINT32 | CtrlRampTmr: 8
This register holds the control hold off values to be used when changing the rail control for external bypass value in us.
UINT32 | SupportedVoltageStates: 4
Mask to set the supported configuration in VR rail. More...
UINT32 | IccMaximum: 16
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .
UINT32 | RsvdBits2: 4
UINT32 Alignment.

Detailed Description

Structure for V1p05/Vnn VR rail configuration.

Definition at line 73 of file FivrConfig.h.

Member Data Documentation

◆ IccMax

UINT32 FIVR_EXT_RAIL_CONFIG::IccMax
Deprecated:
THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD VR rail Icc Max Value Granularity of this setting is 1mA and maximal possible value is 500mA The default is 0mA .

Definition at line 94 of file FivrConfig.h.

◆ SupportedVoltageStates

UINT32 FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates

Mask to set the supported configuration in VR rail.

Use values from FIVR_RAIL_SUPPORTED_VOLTAGE

Definition at line 109 of file FivrConfig.h.

◆ Voltage

UINT32 FIVR_EXT_RAIL_CONFIG::Voltage

VR rail voltage value that will be used in S0i2/S0i3 states.

This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) The default for Vnn is set to 420 - 1050 mV.

Definition at line 86 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FIVR_EXT_RAIL_CONFIG Member List

This is the complete list of members for FIVR_EXT_RAIL_CONFIG, including all inherited members.

CtrlRampTmr | FIVR_EXT_RAIL_CONFIG
EnabledStates | FIVR_EXT_RAIL_CONFIG
IccMax | FIVR_EXT_RAIL_CONFIG
IccMaximum | FIVR_EXT_RAIL_CONFIG
RsvdBits1 | FIVR_EXT_RAIL_CONFIG
RsvdBits2 | FIVR_EXT_RAIL_CONFIG
SupportedVoltageStates | FIVR_EXT_RAIL_CONFIG
Voltage | FIVR_EXT_RAIL_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FIVR_VCCIN_AUX_CONFIG Struct Reference

Public Attributes | List of all members
FIVR_VCCIN_AUX_CONFIG Struct Reference

Structure for VCCIN_AUX voltage rail configuration. More...

#include <FivrConfig.h>

Public Attributes

UINT8 | LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage. More...
UINT8 | RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage. More...
UINT32 | OffToHighCurModeVolTranTime: 11
Transition time in microseconds from Off (0V) to High Current Mode Voltage. More...

Detailed Description

Structure for VCCIN_AUX voltage rail configuration.

Definition at line 128 of file FivrConfig.h.

Member Data Documentation

◆ LowToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime

Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage. The default is 0xC .

Definition at line 137 of file FivrConfig.h.

◆ OffToHighCurModeVolTranTime

UINT32 FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime

Transition time in microseconds from Off (0V) to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from 0V to the high current mode voltage. This field has 1us resolution. 0 = Transition to 0V is disabled Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on in all S0 & Sx power states after initial start up on G3 exit The default is 0x96 .

Definition at line 169 of file FivrConfig.h.

◆ RetToHighCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x36 .

Definition at line 147 of file FivrConfig.h.

◆ RetToLowCurModeVolTranTime

UINT8 FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime

Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.

Voltage transition time required by motherboard voltage regulator when PCH changes the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage. This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX to retention voltage. The default is 0x2B .

Definition at line 157 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FIVR_VCCIN_AUX_CONFIG Member List

This is the complete list of members for FIVR_VCCIN_AUX_CONFIG, including all inherited members.

LowToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
OffToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToHighCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
RetToLowCurModeVolTranTime | FIVR_VCCIN_AUX_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FSP_ERROR_INFO_HOB Struct Reference

Public Attributes | List of all members
FSP_ERROR_INFO_HOB Struct Reference

FSP Error Information Block. More...

#include <FspErrorInfo.h>

Public Attributes

EFI_HOB_GUID_TYPE | GuidHob
GUID HOB header.
EFI_STATUS_CODE_TYPE | Type
ReportStatusCode () type identifier.
EFI_STATUS_CODE_VALUE | Value
ReportStatusCode () value.
UINT32 | Instance
ReportStatusCode () Instance number.
EFI_GUID | CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the time of the error.
EFI_GUID | ErrorType
GUID identifying the nature of the fatal error.
UINT32 | Status
EFI_STATUS code describing the error encountered.

Detailed Description

FSP Error Information Block.

Definition at line 60 of file FspErrorInfo.h.

The documentation for this struct was generated from the following file:
  • FspErrorInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FSP_ERROR_INFO_HOB Member List

This is the complete list of members for FSP_ERROR_INFO_HOB, including all inherited members.

CallerId | FSP_ERROR_INFO_HOB
ErrorType | FSP_ERROR_INFO_HOB
GuidHob | FSP_ERROR_INFO_HOB
Instance | FSP_ERROR_INFO_HOB
Status | FSP_ERROR_INFO_HOB
Type | FSP_ERROR_INFO_HOB
Value | FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FSPM_ARCH_CONFIG_PPI Struct Reference

List of all members
FSPM_ARCH_CONFIG_PPI Struct Reference

This PPI provides FSP-M Arch Config PPI. More...

#include <FspmArchConfigPpi.h>

Detailed Description

This PPI provides FSP-M Arch Config PPI.

Definition at line 32 of file FspmArchConfigPpi.h.

The documentation for this struct was generated from the following file:
  • FspmArchConfigPpi.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FSPM_ARCH_CONFIG_PPI Member List

This is the complete list of members for FSPM_ARCH_CONFIG_PPI, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FUSA_CONFIG Struct Reference

Public Attributes | List of all members
FUSA_CONFIG Struct Reference

The FUSA_CONFIG block describes the expected configuration of Functional Safety. More...

#include <FusaConfig.h>

Collaboration diagram for FUSA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | DisplayFusaConfigEnable: 1
Enable/Disable Fusa feature on Display Fusa configuration on Display 0: Disable; 1: Enable. More...
UINT32 | GraphicFusaConfigEnable: 1
Enable/Disable FuSa feature on GT: 0=Disable, 1=Enable.
UINT32 | OpioFusaConfigEnable: 1
Enable/Disable FuSa feature on OPIO: 0=Disable, 1=Enable.
UINT32 | PsfFusaConfigEnable: 1
Enable/Disable FuSa feature on PSF: 0=Disable, 1=Enable.
UINT32 | IopFusaConfigEnable: 1
Enable/Disable FuSa feature on IOP: 0=Disable, 1=Enable.
UINT32 | IopFusaMcaCheckEnable: 1
Enable/Disable FuSa feature on IOP MCA Check Enable: 0=Disable, 1=Enable.
UINT32 | FusaConfigEnable: 1
Enable/Disable FuSa feature: 0=Disable, 1=Enable.
UINT32 | FusaRunStartupArrayBist: 1
Enabling this will execute startup array test during boot.
UINT32 | FusaRunStartupScanBist: 1
Enabling this will execute startup scan test during boot.
UINT32 | FusaRunPeriodicScanBist: 1
Enabling this will execute periodic scan test during boot.
UINT32 | Module0Lockstep: 2
Enable/Disable Lockstep for Atom module 1, which has 4 cores; 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3; 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3.
UINT32 | Module1Lockstep: 2
Enable/Disable Lockstep for Atom module 1, which has 4 cores; 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3; 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3.
UINT32 | RsvdBits0: 18
Reserved bits.

Detailed Description

The FUSA_CONFIG block describes the expected configuration of Functional Safety.

Definition at line 56 of file FusaConfig.h.

Member Data Documentation

◆ DisplayFusaConfigEnable

UINT32 FUSA_CONFIG::DisplayFusaConfigEnable

Enable/Disable Fusa feature on Display Fusa configuration on Display 0: Disable; 1: Enable.

Enable/Disable Fusa feature on IOP MCA Check Fusa configuration on IOP MCA Check 0: Disable; 1: Enable. Enable/Disable FuSa feature on DE: 0=Disable, 1=Enable

Definition at line 64 of file FusaConfig.h.

The documentation for this struct was generated from the following file:
  • FusaConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FUSA_CONFIG Member List

This is the complete list of members for FUSA_CONFIG, including all inherited members.

DisplayFusaConfigEnable | FUSA_CONFIG
FusaConfigEnable | FUSA_CONFIG
FusaRunPeriodicScanBist | FUSA_CONFIG
FusaRunStartupArrayBist | FUSA_CONFIG
FusaRunStartupScanBist | FUSA_CONFIG
GraphicFusaConfigEnable | FUSA_CONFIG
Header | FUSA_CONFIG
IopFusaConfigEnable | FUSA_CONFIG
IopFusaMcaCheckEnable | FUSA_CONFIG
Module0Lockstep | FUSA_CONFIG
Module1Lockstep | FUSA_CONFIG
OpioFusaConfigEnable | FUSA_CONFIG
PsfFusaConfigEnable | FUSA_CONFIG
RsvdBits0 | FUSA_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FVI_DATA Struct Reference

List of all members
FVI_DATA Struct Reference

The string number for ComponentName and VersionString is always calculated dynamically. More...

#include <SiFviLib.h>

Collaboration diagram for FVI_DATA:
[legend]

Detailed Description

The string number for ComponentName and VersionString is always calculated dynamically.

The initial value is ignored and should always be TO_BE_FILLED.

Definition at line 86 of file SiFviLib.h.

The documentation for this struct was generated from the following file:
  • SiFviLib.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FVI_DATA Member List

This is the complete list of members for FVI_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA Struct Reference

List of all members
FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA Struct Reference

FW Feature Shipment Time State Override. More...

#include <MkhiMsgs.h>

Detailed Description

FW Feature Shipment Time State Override.

Definition at line 1062 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA Member List

This is the complete list of members for FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FWSTS_SET_RECORD Struct Reference

Public Attributes | List of all members
FWSTS_SET_RECORD Struct Reference

FWSTS element structure. More...

#include <FwStsSmbiosTable.h>

Public Attributes

UINT8 | ComponentName
Number of Null terminated string. More...
UINT32 | Reg [MAX_FWSTS_REG]
The value of 0:22:x PCI offset 0x40 The value of 0:22:X PCI offset 0x48 The value of 0:22:X PCI offset 0x60 The value of 0:22:X PCI offset 0x64 The value of 0:22:X PCI offset 0x68 The value of 0:22:X PCI offset 0x6C.

Detailed Description

FWSTS element structure.

Definition at line 149 of file FwStsSmbiosTable.h.

Member Data Documentation

◆ ComponentName

UINT8 FWSTS_SET_RECORD::ComponentName

Number of Null terminated string.

N = 1 - One set of FWSTS registers exposed (L"MEI1" for 0:22:0, L"MEI2" for 0:22:1, L"MEI3" for 0:22:4)

Definition at line 155 of file FwStsSmbiosTable.h.

The documentation for this struct was generated from the following file:
  • FwStsSmbiosTable.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FWSTS_SET_RECORD Member List

This is the complete list of members for FWSTS_SET_RECORD, including all inherited members.

ComponentName | FWSTS_SET_RECORD
Reg | FWSTS_SET_RECORD
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FWSTS_SMBIOS_RECORD Struct Reference

Public Attributes | List of all members
FWSTS_SMBIOS_RECORD Struct Reference

FWSTS SMBIOS Record Structure. More...

#include <FwStsSmbiosTable.h>

Collaboration diagram for FWSTS_SMBIOS_RECORD:
[legend]

Public Attributes

UINT8 | Version
Version of implemented structure, current version is 1.
UINT8 | Count
Number of MEI device groups included.

Detailed Description

FWSTS SMBIOS Record Structure.

Definition at line 170 of file FwStsSmbiosTable.h.

The documentation for this struct was generated from the following file:
  • FwStsSmbiosTable.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

FWSTS_SMBIOS_RECORD Member List

This is the complete list of members for FWSTS_SMBIOS_RECORD, including all inherited members.

Count | FWSTS_SMBIOS_RECORD
Version | FWSTS_SMBIOS_RECORD
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GBE_CONFIG Struct Reference

Public Attributes | List of all members
GBE_CONFIG Struct Reference

PCH intergrated GBE controller configuration settings. More...

#include <GbeConfig.h>

Collaboration diagram for GBE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Determines if enable PCH internal GBE, 0: Disable; 1: Enable. More...
UINT32 | LtrEnable: 1
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
UINT32 | RsvdBits0: 30
Reserved bits.

Detailed Description

PCH intergrated GBE controller configuration settings.

Definition at line 46 of file GbeConfig.h.

Member Data Documentation

◆ Enable

UINT32 GBE_CONFIG::Enable

Determines if enable PCH internal GBE, 0: Disable; 1: Enable.

When Enable is changed (from disabled to enabled or from enabled to disabled), it needs to set LAN Disable regsiter, which might be locked by FDSWL register. So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.

Definition at line 54 of file GbeConfig.h.

The documentation for this struct was generated from the following file:
  • GbeConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GBE_CONFIG Member List

This is the complete list of members for GBE_CONFIG, including all inherited members.

Enable | GBE_CONFIG
Header | GBE_CONFIG
LtrEnable | GBE_CONFIG
RsvdBits0 | GBE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GEN_SEND_CPU_BRAND Struct Reference

List of all members
GEN_SEND_CPU_BRAND Struct Reference

Send CPU brand class fuse. More...

#include <MkhiMsgs.h>

Collaboration diagram for GEN_SEND_CPU_BRAND:
[legend]

Detailed Description

Send CPU brand class fuse.

Definition at line 934 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GEN_SEND_CPU_BRAND Member List

This is the complete list of members for GEN_SEND_CPU_BRAND, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_BOOT_OPTIONS Struct Reference

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GET_BOOT_OPTIONS Struct Reference

Get Boot Options Request Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_BOOT_OPTIONS:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Get Boot Options Request Structure.

Definition at line 183 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_BOOT_OPTIONS Member List

This is the complete list of members for GET_BOOT_OPTIONS, including all inherited members.

AsfHeader GET_BOOT_OPTIONS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_BOOT_OPTIONS_BUFFER Union Reference

List of all members
GET_BOOT_OPTIONS_BUFFER Union Reference

Get Boot Options Union Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_BOOT_OPTIONS_BUFFER:
[legend]

Detailed Description

Get Boot Options Union Buffer.

Definition at line 190 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_BOOT_OPTIONS_BUFFER Member List

This is the complete list of members for GET_BOOT_OPTIONS_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_BOOT_OPTIONS_RESPONSE Struct Reference

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GET_BOOT_OPTIONS_RESPONSE Struct Reference

Get Boot Options Response Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_BOOT_OPTIONS_RESPONSE:
[legend]

Public Attributes

UINT8 | Command
ASF Message Command.
UINT8 | ByteCount
ASF Message Bytes Count Beyond This Byte.
ASF_BOOT_OPTIONS AsfBootOptions
ASF Return Boot Options.

Detailed Description

Get Boot Options Response Structure.

Definition at line 174 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_BOOT_OPTIONS_RESPONSE Member List

This is the complete list of members for GET_BOOT_OPTIONS_RESPONSE, including all inherited members.

AsfBootOptions | GET_BOOT_OPTIONS_RESPONSE
ByteCount | GET_BOOT_OPTIONS_RESPONSE
Command | GET_BOOT_OPTIONS_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_FEATURE_STATE_REQUEST Struct Reference

List of all members
GET_FEATURE_STATE_REQUEST Struct Reference

Get/Set Feature State. More...

#include <UpidMsgs.h>

Collaboration diagram for GET_FEATURE_STATE_REQUEST:
[legend]

Detailed Description

Get/Set Feature State.

Definition at line 118 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_FEATURE_STATE_REQUEST Member List

This is the complete list of members for GET_FEATURE_STATE_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_FEATURE_SUPPORT_REQUEST Struct Reference

List of all members
GET_FEATURE_SUPPORT_REQUEST Struct Reference

Common Features Definitions. More...

#include <UpidMsgs.h>

Collaboration diagram for GET_FEATURE_SUPPORT_REQUEST:
[legend]

Detailed Description

Common Features Definitions.

Get Feature Support

Definition at line 100 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_FEATURE_SUPPORT_REQUEST Member List

This is the complete list of members for GET_FEATURE_SUPPORT_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_FW_VER Struct Reference

List of all members
GET_FW_VER Struct Reference

Get FW Version. More...

#include <MkhiMsgs.h>

Collaboration diagram for GET_FW_VER:
[legend]

Detailed Description

Get FW Version.

Definition at line 906 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_FW_VER Member List

This is the complete list of members for GET_FW_VER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_IMR_CMD_REQ_DATA Struct Reference

List of all members
GET_IMR_CMD_REQ_DATA Struct Reference

Get IMR size message. More...

#include <BupMsgs.h>

Detailed Description

Get IMR size message.

Definition at line 191 of file BupMsgs.h.

The documentation for this struct was generated from the following file:
  • BupMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_IMR_CMD_REQ_DATA Member List

This is the complete list of members for GET_IMR_CMD_REQ_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_MEASURED_BOOT Struct Reference

List of all members
GET_MEASURED_BOOT Struct Reference

Get CSME Measured Boot. More...

#include <MkhiMsgs.h>

Collaboration diagram for GET_MEASURED_BOOT:
[legend]

Detailed Description

Get CSME Measured Boot.

Definition at line 1201 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_MEASURED_BOOT Member List

This is the complete list of members for GET_MEASURED_BOOT, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_OS_CONTROL_FEATURE_STATE_REQUEST Struct Reference

List of all members
GET_OS_CONTROL_FEATURE_STATE_REQUEST Struct Reference

Get/Set Os Control Feature State. More...

#include <UpidMsgs.h>

Collaboration diagram for GET_OS_CONTROL_FEATURE_STATE_REQUEST:
[legend]

Detailed Description

Get/Set Os Control Feature State.

Definition at line 151 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_OS_CONTROL_FEATURE_STATE_REQUEST Member List

This is the complete list of members for GET_OS_CONTROL_FEATURE_STATE_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_PLATFORM_ID_REQUEST Struct Reference

List of all members
GET_PLATFORM_ID_REQUEST Struct Reference

Platform Id Feature Defintions. More...

#include <UpidMsgs.h>

Collaboration diagram for GET_PLATFORM_ID_REQUEST:
[legend]

Detailed Description

Platform Id Feature Defintions.

Get Platform Id

Definition at line 188 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_PLATFORM_ID_REQUEST Member List

This is the complete list of members for GET_PLATFORM_ID_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_REFURBISH_COUNTER_REQUEST Struct Reference

List of all members
GET_REFURBISH_COUNTER_REQUEST Struct Reference

Get Refurbish Counter. More...

#include <UpidMsgs.h>

Collaboration diagram for GET_REFURBISH_COUNTER_REQUEST:
[legend]

Detailed Description

Get Refurbish Counter.

Definition at line 216 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_REFURBISH_COUNTER_REQUEST Member List

This is the complete list of members for GET_REFURBISH_COUNTER_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_RPMC_STATUS Struct Reference

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GET_RPMC_STATUS Struct Reference

Get RPMC Status. More...

#include <MkhiMsgs.h>

Collaboration diagram for GET_RPMC_STATUS:
[legend]

Detailed Description

Get RPMC Status.

Definition at line 692 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_RPMC_STATUS Member List

This is the complete list of members for GET_RPMC_STATUS, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_RSE_PASSWORD Struct Reference

Public Attributes | List of all members
GET_RSE_PASSWORD Struct Reference

Get RSE Password Request Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_RSE_PASSWORD:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.

Detailed Description

Get RSE Password Request Structure.

Definition at line 213 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_RSE_PASSWORD Member List

This is the complete list of members for GET_RSE_PASSWORD, including all inherited members.

AsfHeader GET_RSE_PASSWORD
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_RSE_PASSWORD_BUFFER Union Reference

List of all members
GET_RSE_PASSWORD_BUFFER Union Reference

Get RSE Password Union Buffer. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_RSE_PASSWORD_BUFFER:
[legend]

Detailed Description

Get RSE Password Union Buffer.

Definition at line 220 of file AsfMsgs.h.

The documentation for this union was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_RSE_PASSWORD_BUFFER Member List

This is the complete list of members for GET_RSE_PASSWORD_BUFFER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_RSE_PASSWORD_RESPONSE Struct Reference

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GET_RSE_PASSWORD_RESPONSE Struct Reference

Get RSE Password Response Structure. More...

#include <AsfMsgs.h>

Collaboration diagram for GET_RSE_PASSWORD_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT16 | PasswordLength
Password length in bytes.
CHAR8 | Password [RSE_PASSWORD_MAX_LENGTH]
RSE Password.

Detailed Description

Get RSE Password Response Structure.

Definition at line 204 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_RSE_PASSWORD_RESPONSE Member List

This is the complete list of members for GET_RSE_PASSWORD_RESPONSE, including all inherited members.

AsfHeader | GET_RSE_PASSWORD_RESPONSE
Password | GET_RSE_PASSWORD_RESPONSE
PasswordLength | GET_RSE_PASSWORD_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_WIFI_CLIENT_CERT_BUFFER Union Reference

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GET_WIFI_CLIENT_CERT_BUFFER Union Reference

ASF buffer for Wifi profile client certificate. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for GET_WIFI_CLIENT_CERT_BUFFER:
[legend]

Public Attributes

ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
GET_WIFI_CLIENT_CERT_RESPONSE Response
ASF Resposne.

Detailed Description

ASF buffer for Wifi profile client certificate.

Definition at line 143 of file WifiProfileSyncAsfMsgs.h.

The documentation for this union was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_WIFI_CLIENT_CERT_BUFFER Member List

This is the complete list of members for GET_WIFI_CLIENT_CERT_BUFFER, including all inherited members.

Request | GET_WIFI_CLIENT_CERT_BUFFER
Response | GET_WIFI_CLIENT_CERT_BUFFER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_WIFI_CLIENT_KEY_BUFFER Union Reference

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GET_WIFI_CLIENT_KEY_BUFFER Union Reference

ASF buffer for Wifi profile client key. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for GET_WIFI_CLIENT_KEY_BUFFER:
[legend]

Public Attributes

ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
GET_WIFI_CLIENT_KEY_RESPONSE Response
ASF Response.

Detailed Description

ASF buffer for Wifi profile client key.

Definition at line 165 of file WifiProfileSyncAsfMsgs.h.

The documentation for this union was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_WIFI_CLIENT_KEY_BUFFER Member List

This is the complete list of members for GET_WIFI_CLIENT_KEY_BUFFER, including all inherited members.

Request | GET_WIFI_CLIENT_KEY_BUFFER
Response | GET_WIFI_CLIENT_KEY_BUFFER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_WIFI_PROFILE_DATA_BUFFER Union Reference

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GET_WIFI_PROFILE_DATA_BUFFER Union Reference

ASF buffer for Wifi profile data. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for GET_WIFI_PROFILE_DATA_BUFFER:
[legend]

Public Attributes

ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
GET_WIFI_PROFILE_DATA_RESPONSE Response
ASF Response.

Detailed Description

ASF buffer for Wifi profile data.

Definition at line 121 of file WifiProfileSyncAsfMsgs.h.

The documentation for this union was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_WIFI_PROFILE_DATA_BUFFER Member List

This is the complete list of members for GET_WIFI_PROFILE_DATA_BUFFER, including all inherited members.

Request | GET_WIFI_PROFILE_DATA_BUFFER
Response | GET_WIFI_PROFILE_DATA_BUFFER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_WIFI_PROFILE_NAME_BUFFER Union Reference

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GET_WIFI_PROFILE_NAME_BUFFER Union Reference

ASF buffer for Wifi profile name. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for GET_WIFI_PROFILE_NAME_BUFFER:
[legend]

Public Attributes

ASF_MESSAGE_HEADER Request
ASF Request.
GET_WIFI_PROFILE_NAME_RESPONSE Response
ASF Response.

Detailed Description

ASF buffer for Wifi profile name.

Definition at line 78 of file WifiProfileSyncAsfMsgs.h.

The documentation for this union was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_WIFI_PROFILE_NAME_BUFFER Member List

This is the complete list of members for GET_WIFI_PROFILE_NAME_BUFFER, including all inherited members.

Request | GET_WIFI_PROFILE_NAME_BUFFER
Response | GET_WIFI_PROFILE_NAME_BUFFER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GET_WIFI_PROFILE_NAME_RESPONSE Struct Reference

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GET_WIFI_PROFILE_NAME_RESPONSE Struct Reference

Get Wifi profile name response from ASF. More...

#include <WifiProfileSyncAsfMsgs.h>

Collaboration diagram for GET_WIFI_PROFILE_NAME_RESPONSE:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT32 | Status
ASF Response Message Status.
CHAR8 | ProfileName [PROFILE_NAME_SIZE]
ASF Return WiFi Profile Name.

Detailed Description

Get Wifi profile name response from ASF.

Definition at line 69 of file WifiProfileSyncAsfMsgs.h.

The documentation for this struct was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GET_WIFI_PROFILE_NAME_RESPONSE Member List

This is the complete list of members for GET_WIFI_PROFILE_NAME_RESPONSE, including all inherited members.

AsfHeader | GET_WIFI_PROFILE_NAME_RESPONSE
ProfileName | GET_WIFI_PROFILE_NAME_RESPONSE
Status | GET_WIFI_PROFILE_NAME_RESPONSE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GNA_CONFIG Struct Reference

Public Attributes | List of all members
GNA_CONFIG Struct Reference

GNA config block for configuring GNA. More...

#include <GnaConfig.h>

Collaboration diagram for GNA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | GnaEnable: 1
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported. More...
UINT32 | RsvdBits0: 31
Offset 28:1 :Reserved for future use.

Detailed Description

GNA config block for configuring GNA.

Revision 1:

  • Initial version.

Definition at line 45 of file GnaConfig.h.

Member Data Documentation

◆ GnaEnable

UINT32 GNA_CONFIG::GnaEnable

Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.

If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 54 of file GnaConfig.h.

The documentation for this struct was generated from the following file:
  • GnaConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GNA_CONFIG Member List

This is the complete list of members for GNA_CONFIG, including all inherited members.

GnaEnable | GNA_CONFIG
Header | GNA_CONFIG
RsvdBits0 | GNA_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GOP_POLICY_PROTOCOL Struct Reference

Public Attributes | List of all members
GOP_POLICY_PROTOCOL Struct Reference

System Agent Graphics Output Protocol (GOP) - Policy Protocol
Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot
When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization
All functions in this protocol should be initialized by platform code basing on platform implementation
. More...

#include <GopPolicy.h>

Public Attributes

UINT32 | Revision
Protocol revision.
GET_PLATFORM_LID_STATUS GetPlatformLidStatus
Protocol function to get Lid Status. Platform code should provide this function basing on design.
GET_VBT_DATA GetVbtData
Protocol function to get Vbt Data address and size. Platform code should provide this function basing on design.
GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus
Function pointer for get platform dock status.
EFI_GUID | GopOverrideGuid
A GUID provided by BIOS in case GOP is to be overridden.

Detailed Description

System Agent Graphics Output Protocol (GOP) - Policy Protocol
Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot
When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization
All functions in this protocol should be initialized by platform code basing on platform implementation
.

Definition at line 88 of file GopPolicy.h.

The documentation for this struct was generated from the following file:
  • GopPolicy.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GOP_POLICY_PROTOCOL Member List

This is the complete list of members for GOP_POLICY_PROTOCOL, including all inherited members.

GetPlatformDockStatus | GOP_POLICY_PROTOCOL
GetPlatformLidStatus | GOP_POLICY_PROTOCOL
GetVbtData | GOP_POLICY_PROTOCOL
GopOverrideGuid | GOP_POLICY_PROTOCOL
Revision | GOP_POLICY_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GPIO_CONFIG Struct Reference

Public Attributes | List of all members
GPIO_CONFIG Struct Reference

GPIO configuration structure used for pin programming. More...

#include <GpioConfig.h>

Public Attributes

UINT32 | PadMode: 5
Pad Mode Pad can be set as GPIO or one of its native functions. More...
UINT32 | HostSoftPadOwn: 2
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode. More...
UINT32 | Direction: 6
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both. More...
UINT32 | OutputState: 2
Output State Set Pad output value. More...
UINT32 | InterruptConfig: 9
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). More...
UINT32 | PowerConfig: 8
GPIO Power Configuration. More...
UINT32 | ElectricalConfig: 9
GPIO Electrical Configuration This setting controls pads termination. More...
UINT32 | LockConfig: 4
GPIO Lock Configuration This setting controls pads lock. More...
UINT32 | OtherSettings: 9
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
UINT32 | VgpioCs: 2
Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1. More...
UINT32 | RsvdBits: 8
Reserved bits for future extension.

Detailed Description

GPIO configuration structure used for pin programming.

Structure contains fields that can be used to configure pad.

Definition at line 67 of file GpioConfig.h.

Member Data Documentation

◆ Direction

UINT32 GPIO_CONFIG::Direction

GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.

Refer to definition of GPIO_DIRECTION for supported settings.

Definition at line 88 of file GpioConfig.h.

◆ ElectricalConfig

UINT32 GPIO_CONFIG::ElectricalConfig

GPIO Electrical Configuration This setting controls pads termination.

Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.

Definition at line 114 of file GpioConfig.h.

◆ HostSoftPadOwn

UINT32 GPIO_CONFIG::HostSoftPadOwn

Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.

Refer to definition of GPIO_HOSTSW_OWN.

Definition at line 82 of file GpioConfig.h.

◆ InterruptConfig

UINT32 GPIO_CONFIG::InterruptConfig

GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).

This setting is applicable only if GPIO is in GpioMode with input enabled. Refer to definition of GPIO_INT_CONFIG for supported settings.

Definition at line 102 of file GpioConfig.h.

◆ LockConfig

UINT32 GPIO_CONFIG::LockConfig

GPIO Lock Configuration This setting controls pads lock.

Refer to definition of GPIO_LOCK_CONFIG for supported settings.

Definition at line 120 of file GpioConfig.h.

◆ OutputState

UINT32 GPIO_CONFIG::OutputState

Output State Set Pad output value.

Refer to definition of GPIO_OUTPUT_STATE for supported settings. This setting takes place when output is enabled.

Definition at line 95 of file GpioConfig.h.

◆ PadMode

UINT32 GPIO_CONFIG::PadMode

Pad Mode Pad can be set as GPIO or one of its native functions.

When in native mode setting Direction (except Inversion), OutputState, InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary. Refer to definition of GPIO_PAD_MODE. Refer to EDS for each native mode according to the pad.

Definition at line 76 of file GpioConfig.h.

◆ PowerConfig

UINT32 GPIO_CONFIG::PowerConfig

GPIO Power Configuration.

This setting controls Pad Reset Configuration. Refer to definition of GPIO_RESET_CONFIG for supported settings.

Definition at line 108 of file GpioConfig.h.

◆ VgpioCs

UINT32 GPIO_CONFIG::VgpioCs

Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1.

Refer to definition of VGPIO_CS_CONFIG for supported settings.

Definition at line 132 of file GpioConfig.h.

The documentation for this struct was generated from the following file:
  • GpioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GPIO_CONFIG Member List

This is the complete list of members for GPIO_CONFIG, including all inherited members.

Direction | GPIO_CONFIG
ElectricalConfig | GPIO_CONFIG
HostSoftPadOwn | GPIO_CONFIG
InterruptConfig | GPIO_CONFIG
LockConfig | GPIO_CONFIG
OtherSettings | GPIO_CONFIG
OutputState | GPIO_CONFIG
PadMode | GPIO_CONFIG
PowerConfig | GPIO_CONFIG
RsvdBits | GPIO_CONFIG
VgpioCs | GPIO_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GPIO_DXE_CONFIG Struct Reference

Public Attributes | List of all members
GPIO_DXE_CONFIG Struct Reference

This structure contains the DXE policies which are related to GPIO device. More...

#include <GpioDevConfig.h>

Collaboration diagram for GPIO_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HideGpioAcpiDevice: 1
If GPIO ACPI device is not used by OS it can be hidden. More...
UINT32 | RsvdBits: 31
Reserved bits.

Detailed Description

This structure contains the DXE policies which are related to GPIO device.

Revision 1:

  • Inital version.

Definition at line 50 of file GpioDevConfig.h.

Member Data Documentation

◆ HideGpioAcpiDevice

UINT32 GPIO_DXE_CONFIG::HideGpioAcpiDevice

If GPIO ACPI device is not used by OS it can be hidden.

In such case no other device exposed to the system can reference GPIO device in one of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors. 0: Disable; 1: Enable

Definition at line 58 of file GpioDevConfig.h.

The documentation for this struct was generated from the following file:
  • GpioDevConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GPIO_DXE_CONFIG Member List

This is the complete list of members for GPIO_DXE_CONFIG, including all inherited members.

Header | GPIO_DXE_CONFIG
HideGpioAcpiDevice | GPIO_DXE_CONFIG
RsvdBits | GPIO_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GRAPHICS_DXE_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_DXE_CONFIG Struct Reference

This configuration block is to configure IGD related variables used in DXE. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
UINT32 | Size
Offset 28 - 31: This field gives the size of the GOP VBT Data buffer.
EFI_PHYSICAL_ADDRESS | VbtAddress
Offset 32 - 39: This field points to the GOP VBT data buffer.
UINT8 | PlatformConfig
Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, 1=Platform is not S0ix Capable, 2=Force Platform is S0ix Capable for All SKUs)
UINT8 | AlsEnable
Offset 41: Ambient Light Sensor Enable: 0=Disable, 2=Enable.
UINT8 | BacklightControlSupport
Offset 42: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
UINT8 | IgdBootType
Offset 43: IGD Boot Type CMOS option: 0=Default, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2.
UINT32 | IuerStatusVal
Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
CHAR16 | GopVersion [0x10]
Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code.
UINT8 | IgdPanelType
Offset 80: IGD Panel Type CMOS option
0=Default, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1
6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS
14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS.
UINT8 | IgdPanelScaling
Offset 81: IGD Panel Scaling: 0=AUTO, 1=OFF, 6=Force scaling.
UINT8 | IgdBlcConfig
Offset 82: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
UINT8 | IgdDvmtMemSize
Offset 83: More...
UINT8 | GfxTurboIMON
Offset 84: IMON Current Value: 14=Minimal, 31=Maximum
UINT8 | Reserved [3]
Offset 85: Reserved for DWORD alignment.
UINT16 | BCLM [MAX_BCLM_ENTRIES]
Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.

Detailed Description

This configuration block is to configure IGD related variables used in DXE.

If Intel Gfx Device is not supported or disabled, all policies will be ignored. The data elements should be initialized by a Platform Module.
Revision 1:

  • Initial version. Revision 2:
  • Removed IgdDvmtMemSize.

Definition at line 229 of file GraphicsConfig.h.

Member Data Documentation

◆ IgdDvmtMemSize

UINT8 GRAPHICS_DXE_CONFIG::IgdDvmtMemSize

Offset 83:

Deprecated:
IGD DVMT Memory Size: 1=128MB, 2=256MB, 3=MAX

Definition at line 248 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GRAPHICS_DXE_CONFIG Member List

This is the complete list of members for GRAPHICS_DXE_CONFIG, including all inherited members.

AlsEnable | GRAPHICS_DXE_CONFIG
BacklightControlSupport | GRAPHICS_DXE_CONFIG
BCLM | GRAPHICS_DXE_CONFIG
GfxTurboIMON | GRAPHICS_DXE_CONFIG
GopVersion | GRAPHICS_DXE_CONFIG
Header | GRAPHICS_DXE_CONFIG
IgdBlcConfig | GRAPHICS_DXE_CONFIG
IgdBootType | GRAPHICS_DXE_CONFIG
IgdDvmtMemSize | GRAPHICS_DXE_CONFIG
IgdPanelScaling | GRAPHICS_DXE_CONFIG
IgdPanelType | GRAPHICS_DXE_CONFIG
IuerStatusVal | GRAPHICS_DXE_CONFIG
PlatformConfig | GRAPHICS_DXE_CONFIG
Reserved | GRAPHICS_DXE_CONFIG
Size | GRAPHICS_DXE_CONFIG
VbtAddress | GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GRAPHICS_PEI_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_PEI_CONFIG Struct Reference

This configuration block is to configure IGD related variables used in PostMem PEI. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | RenderStandby
Offset 28 :(Test) This field is used to enable or disable RC6 (Render Standby): 0=FALSE, 1=TRUE
UINT8 | PmSupport
Offset 29 :(Test) Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, 1=TRUE
UINT16 | CdClock
Offset 30 CdClock Frequency select
0xFF = Auto. More...
UINT8 | PeiGraphicsPeimInit
Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable.
UINT8 | CdynmaxClampEnable
Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable, 0- Disable.
UINT16 | GtFreqMax
Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is 0xFF
UINT8 | DisableTurboGt
Offset 36 : This policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enable.
UINT8 | SkipCdClockInit
Offset 37 : SKip full CD clock initialization. 0- Disable, 1- Enable.
UINT8 | RC1pFreqEnable
Offset 38 : This policy is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable.
UINT8 | PavpEnable
Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, 1=TRUE
VOID * | LogoPtr
Offset 40 Address of Intel Gfx PEIM Logo to be displayed.
UINT32 | LogoSize
Offset 44 Intel Gfx PEIM Logo Size.
VOID * | GraphicsConfigPtr
Offset 48 Address of the Graphics Configuration Table.
VOID * | BltBufferAddress
Offset 52 Address of Blt buffer for PEIM Logo use.
UINT32 | BltBufferSize
Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
UINT8 | ProgramGtChickenBits
Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
UINT8 | SkipFspGop
Offset 61 This policy is used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Skip FSP provided GOP driver.
UINT8 | Rsvd1 [2]
Offset 62 Reserved for 4 bytes alignment.
UINT32 | LogoPixelHeight
Offset 64 Address of LogoPixelHeight for PEIM Logo use.
UINT32 | LogoPixelWidth
Offset 68 Address of LogoPixelWidth for PEIM Logo use.
UINT32 | VerticalResolution
Offset 72 Address of VerticalResolution for PEIM Logo use.
UINT32 | HorizontalResolution
Offset 76 Address of HorizontalResolution for PEIM Logo use.

Detailed Description

This configuration block is to configure IGD related variables used in PostMem PEI.

If Intel Gfx Device is not supported, all policies can be ignored. Revision 1:

  • Initial version. Revision 2:
  • Removed DfdRestoreEnable. Revision 3:
  • Removed DdiConfiguration. Revision 4:
  • Added new CdClock frequency Revision 5:
  • Added GT Chicket bits Revision 6:
  • Added LogoPixelHeight and LogoPixelWidth Revision 7:
  • Added SkipFspGop Revision 8:
  • Added VerticalResolution and HorizontalResolution

Definition at line 187 of file GraphicsConfig.h.

Member Data Documentation

◆ CdClock

UINT16 GRAPHICS_PEI_CONFIG::CdClock

Offset 30 CdClock Frequency select
0xFF = Auto.

Max CdClock freq based on Reference Clk
0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz

Definition at line 198 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GRAPHICS_PEI_CONFIG Member List

This is the complete list of members for GRAPHICS_PEI_CONFIG, including all inherited members.

BltBufferAddress | GRAPHICS_PEI_CONFIG
BltBufferSize | GRAPHICS_PEI_CONFIG
CdClock | GRAPHICS_PEI_CONFIG
CdynmaxClampEnable | GRAPHICS_PEI_CONFIG
DisableTurboGt | GRAPHICS_PEI_CONFIG
GraphicsConfigPtr | GRAPHICS_PEI_CONFIG
GtFreqMax | GRAPHICS_PEI_CONFIG
Header | GRAPHICS_PEI_CONFIG
HorizontalResolution | GRAPHICS_PEI_CONFIG
LogoPixelHeight | GRAPHICS_PEI_CONFIG
LogoPixelWidth | GRAPHICS_PEI_CONFIG
LogoPtr | GRAPHICS_PEI_CONFIG
LogoSize | GRAPHICS_PEI_CONFIG
PavpEnable | GRAPHICS_PEI_CONFIG
PeiGraphicsPeimInit | GRAPHICS_PEI_CONFIG
PmSupport | GRAPHICS_PEI_CONFIG
ProgramGtChickenBits | GRAPHICS_PEI_CONFIG
RC1pFreqEnable | GRAPHICS_PEI_CONFIG
RenderStandby | GRAPHICS_PEI_CONFIG
Rsvd1 | GRAPHICS_PEI_CONFIG
SkipCdClockInit | GRAPHICS_PEI_CONFIG
SkipFspGop | GRAPHICS_PEI_CONFIG
VerticalResolution | GRAPHICS_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GRAPHICS_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
GRAPHICS_PEI_PREMEM_CONFIG Struct Reference

This Configuration block is to configure GT related PreMem data/variables. More...

#include <GraphicsConfig.h>

Collaboration diagram for GRAPHICS_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | PrimaryDisplay
Offset 28 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3=AUTO, 4=Switchable Graphics
When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX.
UINT8 | InternalGraphics
Offset 29 Intel Gfx Support. More...
UINT16 | IgdDvmt50PreAlloc
Offset 30 Pre-allocated memory for iGFX
0 = 0MB,1 or 247 = 32MB,
2 = 64MB,
240 = 4MB, 241 = 8MB,
242 = 12MB, 243 = 16MB,
244 = 20MB, 245 = 24MB,
246 = 28MB, 248 = 36MB,
249 = 40MB, 250 = 44MB,
251 = 48MB, 252 = 52MB,
253 = 56MB, 254 = 60MB,
Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation
UINT8 | PanelPowerEnable
Offset 32 :(Test) Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, 1=TRUE
UINT8 | ApertureSize
Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, 1=256MB, 3=512MB, 7=1024MB, 15=2048MB.
UINT8 | GtPsmiSupport
Offset 34 :PSMI support On/Off: 0=FALSE, 1=TRUE.
UINT8 | PsmiRegionSize
Offset 35 :Psmi region size: 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1056MB.
UINT8 | DismSize
Offset 36 :DiSM Size for 2LM Sku: 0=0GB, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB.
UINT8 | DfdRestoreEnable
Offset 37 :(Deprecated) Display memory map programming for DFD Restore 0- Disable, 1- Enable.
UINT16 | GttSize
Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, 3=8MB
UINT32 | GttMmAdr
Offset 40 Temp Address of System Agent GTTMMADR: Default is 0xAF000000
UINT32 | GmAdr
Offset 44 Obsolete not to be used, use GmAdr64.
DDI_CONFIGURATION DdiConfiguration
Offset 48 DDI configuration, need to match with VBT settings.
UINT8 | GtClosEnable
Offset 50 Gt ClOS.
UINT8 | Rsvd0 [7]
Offset 51 Reserved for 4 bytes of alignment.
UINT64 | GmAdr64
Offset 58 Temp Address of System Agent GMADR: Default is 0xB0000000
UINT16 | DeltaT12PowerCycleDelay
Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, 0xFFFF - Auto calculate to max 500 ms< >
UINT8 | DisplayAudioLink
Offset 68 Enable/Disable Display Audio Links in Pre-OS.0- Disable, 1- Enable.
UINT8 | OemT12DelayOverride
Offset 69 :Oem T12 Delay Override Disable< >,Enable-Enable T12 Time.
UINT8 | Rsvd2 [4]
Offset 70 Reserved for 4 bytes of alignment.

Detailed Description

This Configuration block is to configure GT related PreMem data/variables.

Revision 1:

  • Initial version. Revision 2:
  • Added DfdRestoreEnable. Revision 3:
  • Added DdiConfiguration. Revision 4:
  • Added GmAdr64 and made GmAdr obselete Revision 5:
  • Added DeltaT12PowerCycleDelay Revision 6:
  • Added DisplayAudioLink Revision 7:
  • Added OemT12DelayOverride

Definition at line 105 of file GraphicsConfig.h.

Member Data Documentation

◆ InternalGraphics

UINT8 GRAPHICS_PEI_PREMEM_CONFIG::InternalGraphics

Offset 29 Intel Gfx Support.

It controls enabling/disabling iGfx device. When AUTO mode selected, iGFX will be turned off when external graphics detected. If FALSE, all other polices can be ignored. 2 = AUTO; 0 = FALSE; 1 = TRUE.

Definition at line 122 of file GraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • GraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

GRAPHICS_PEI_PREMEM_CONFIG Member List

This is the complete list of members for GRAPHICS_PEI_PREMEM_CONFIG, including all inherited members.

ApertureSize | GRAPHICS_PEI_PREMEM_CONFIG
DdiConfiguration | GRAPHICS_PEI_PREMEM_CONFIG
DeltaT12PowerCycleDelay | GRAPHICS_PEI_PREMEM_CONFIG
DfdRestoreEnable | GRAPHICS_PEI_PREMEM_CONFIG
DismSize | GRAPHICS_PEI_PREMEM_CONFIG
DisplayAudioLink | GRAPHICS_PEI_PREMEM_CONFIG
GmAdr | GRAPHICS_PEI_PREMEM_CONFIG
GmAdr64 | GRAPHICS_PEI_PREMEM_CONFIG
GtClosEnable | GRAPHICS_PEI_PREMEM_CONFIG
GtPsmiSupport | GRAPHICS_PEI_PREMEM_CONFIG
GttMmAdr | GRAPHICS_PEI_PREMEM_CONFIG
GttSize | GRAPHICS_PEI_PREMEM_CONFIG
Header | GRAPHICS_PEI_PREMEM_CONFIG
IgdDvmt50PreAlloc | GRAPHICS_PEI_PREMEM_CONFIG
InternalGraphics | GRAPHICS_PEI_PREMEM_CONFIG
OemT12DelayOverride | GRAPHICS_PEI_PREMEM_CONFIG
PanelPowerEnable | GRAPHICS_PEI_PREMEM_CONFIG
PrimaryDisplay | GRAPHICS_PEI_PREMEM_CONFIG
PsmiRegionSize | GRAPHICS_PEI_PREMEM_CONFIG
Rsvd0 | GRAPHICS_PEI_PREMEM_CONFIG
Rsvd2 | GRAPHICS_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDA_LINK_DMIC Struct Reference

Public Attributes | List of all members
HDA_LINK_DMIC Struct Reference

HD Audio DMIC Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT32 | DmicClockSelect: 2
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
HDA_DMIC_PIN_MUX | PinMux
Pin mux configuration.

Detailed Description

HD Audio DMIC Interface Policies.

Definition at line 115 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDA_LINK_DMIC Member List

This is the complete list of members for HDA_LINK_DMIC, including all inherited members.

DmicClockSelect | HDA_LINK_DMIC
Enable | HDA_LINK_DMIC
PinMux | HDA_LINK_DMIC
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDA_LINK_HDA Struct Reference

Public Attributes | List of all members
HDA_LINK_HDA Struct Reference

HD Audio Link Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 | Enable: 1
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.
UINT8 | SdiEnable [PCH_MAX_HDA_SDI]
HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: 0: Disable; 1: Enable.
UINT8 | Reserved [(4 -(PCH_MAX_HDA_SDI % 4)) % 4]
Padding for SDI enable table.

Detailed Description

HD Audio Link Policies.

Definition at line 105 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDA_LINK_HDA Member List

This is the complete list of members for HDA_LINK_HDA, including all inherited members.

Enable | HDA_LINK_HDA
Reserved | HDA_LINK_HDA
SdiEnable | HDA_LINK_HDA
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDA_LINK_SNDW Struct Reference

Public Attributes | List of all members
HDA_LINK_SNDW Struct Reference

HD Audio SNDW Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SNDW Interface Policies.

Definition at line 133 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDA_LINK_SNDW Member List

This is the complete list of members for HDA_LINK_SNDW, including all inherited members.

Enable HDA_LINK_SNDW
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDA_LINK_SSP Struct Reference

Public Attributes | List of all members
HDA_LINK_SSP Struct Reference

HD Audio SSP Interface Policies. More...

#include <HdAudioConfig.h>

Public Attributes

UINT32 Enable: 1
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enable.

Detailed Description

HD Audio SSP Interface Policies.

Definition at line 125 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDA_LINK_SSP Member List

This is the complete list of members for HDA_LINK_SSP, including all inherited members.

Enable HDA_LINK_SSP
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDA_VERB_TABLE_HEADER Struct Reference

Public Attributes | List of all members
HDA_VERB_TABLE_HEADER Struct Reference

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...

#include <HdAudioConfig.h>

Public Attributes

UINT16 | VendorId
Codec Vendor ID.
UINT16 | DeviceId
Codec Device ID.
UINT8 | RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 | SdiNum
SDI number, 0xFF matches any SDI.
UINT16 | DataDwords
Number of data DWORDs following the header.

Detailed Description

Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands.

Definition at line 72 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDA_VERB_TABLE_HEADER Member List

This is the complete list of members for HDA_VERB_TABLE_HEADER, including all inherited members.

DataDwords | HDA_VERB_TABLE_HEADER
DeviceId | HDA_VERB_TABLE_HEADER
RevisionId | HDA_VERB_TABLE_HEADER
SdiNum | HDA_VERB_TABLE_HEADER
VendorId | HDA_VERB_TABLE_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDAUDIO_CONFIG Struct Reference

Public Attributes | List of all members
HDAUDIO_CONFIG Struct Reference

This structure contains the policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Pme: 1
Azalia wake-on-ring, 0: Disable; 1: Enable.
UINT32 | CodecSxWakeCapability: 1
Capability to detect wake initiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable.
UINT32 | HdAudioLinkFrequency: 4
HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz.
UINT32 | RsvdBits0: 26
Reserved bits 0.
UINT8 | VerbTableEntryNum
Number of the verb table entry defined in VerbTablePtr. More...
UINT8 | Rsvd0 [3]
Reserved bytes, align to multiple 4.
UINT32 | VerbTablePtr
Pointer to a verb table array. More...

Detailed Description

This structure contains the policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version.

Definition at line 146 of file HdAudioConfig.h.

Member Data Documentation

◆ VerbTableEntryNum

UINT8 HDAUDIO_CONFIG::VerbTableEntryNum

Number of the verb table entry defined in VerbTablePtr.

Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.

Definition at line 156 of file HdAudioConfig.h.

◆ VerbTablePtr

UINT32 HDAUDIO_CONFIG::VerbTablePtr

Pointer to a verb table array.

This pointer points to 32bits address, and is only eligible and consumed in post mem phase. Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks. The prototype of this is: HDAUDIO_VERB_TABLE **VerbTablePtr;

Definition at line 165 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDAUDIO_CONFIG Member List

This is the complete list of members for HDAUDIO_CONFIG, including all inherited members.

CodecSxWakeCapability | HDAUDIO_CONFIG
HdAudioLinkFrequency | HDAUDIO_CONFIG
Header | HDAUDIO_CONFIG
Pme | HDAUDIO_CONFIG
Rsvd0 | HDAUDIO_CONFIG
RsvdBits0 | HDAUDIO_CONFIG
VerbTableEntryNum | HDAUDIO_CONFIG
VerbTablePtr | HDAUDIO_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDAUDIO_DXE_CONFIG Struct Reference

Public Attributes | List of all members
HDAUDIO_DXE_CONFIG Struct Reference

This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
HDAUDIO_SNDW_CONFIG | SndwConfig [PCH_MAX_HDA_SNDW_LINK_NUM]
SNDW configuration for exposed via SNDW ACPI tables:
UINT32 | DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation Default is zero.

Detailed Description

This structure contains the DXE policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add IoControlEnabled Revision 3:
  • Remove IoControlEnabled

Definition at line 244 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDAUDIO_DXE_CONFIG Member List

This is the complete list of members for HDAUDIO_DXE_CONFIG, including all inherited members.

DspFeatureMask | HDAUDIO_DXE_CONFIG
Header | HDAUDIO_DXE_CONFIG
SndwConfig | HDAUDIO_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HDAUDIO_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
HDAUDIO_PREMEM_CONFIG Struct Reference

This structure contains the premem policies which are related to HD Audio device (cAVS). More...

#include <HdAudioConfig.h>

Collaboration diagram for HDAUDIO_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
UINT32 | DspEnable: 1
DSP enablement: 0: Disable; 1: Enable
UINT32 | VcType: 1
Virtual Channel Type Select: 0: VC0, 1: VC1.
UINT32 | DspUaaCompliance: 1
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported)
UINT32 | IDispLinkFrequency: 4
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
UINT32 | IDispLinkTmode: 3
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
UINT32 | IDispCodecDisconnect: 1
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not enumerable
UINT32 | PowerGatingSupported: 1
Power Gating supported: 0: Not supported, 1: Supported.
UINT32 | RsvdBits: 19
Reserved bits 0.
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask. More...
HDA_LINK_DMIC | AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM]
DMIC link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SSP | AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM]
I2S/SSP link enablement: 0: Disable; 1: Enable. More...
HDA_LINK_SNDW | AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM]
SoundWire link enablement: 0: Disable; 1: Enable. More...
UINT16 | ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
UINT8 | Rsvd0 [2]
Reserved bytes, align to multiple 4.
UINT32 | SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.

Detailed Description

This structure contains the premem policies which are related to HD Audio device (cAVS).

Revision 1:

  • Inital version. Revision 2:
  • Add DmicClockSelect Revision 3:
  • Add AudioFpgaSocVer Revision 4:
  • Remove AudioFpgaSocVer

Definition at line 180 of file HdAudioConfig.h.

Member Data Documentation

◆ AudioLinkDmic

HDA_LINK_DMIC HDAUDIO_PREMEM_CONFIG::AudioLinkDmic[PCH_MAX_HDA_DMIC_LINK_NUM]

DMIC link enablement: 0: Disable; 1: Enable.

DMIC0 LKF: Muxed with SNDW2/SNDW4.

Definition at line 207 of file HdAudioConfig.h.

◆ AudioLinkHda

HDA_LINK_HDA HDAUDIO_PREMEM_CONFIG::AudioLinkHda

Audio Link Mode configuration bitmask.

Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire. HDA-Link enablement: 0: Disable; 1: Enable.

Definition at line 202 of file HdAudioConfig.h.

◆ AudioLinkSndw

HDA_LINK_SNDW HDAUDIO_PREMEM_CONFIG::AudioLinkSndw[PCH_MAX_HDA_SNDW_LINK_NUM]

SoundWire link enablement: 0: Disable; 1: Enable.

SNDW2 LKF: Muxed with DMIC0/DMIC1. SNDW3 LKF: Muxed with DMIC1. SNDW4 LKF: Muxed with DMIC0.

Definition at line 221 of file HdAudioConfig.h.

◆ AudioLinkSsp

HDA_LINK_SSP HDAUDIO_PREMEM_CONFIG::AudioLinkSsp[PCH_MAX_HDA_SSP_LINK_NUM]

I2S/SSP link enablement: 0: Disable; 1: Enable.

SSP0/1 LKF: Muxed with HDA.

Note
Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2 is exclusive with CNVi is present.

Definition at line 214 of file HdAudioConfig.h.

The documentation for this struct was generated from the following file:
  • HdAudioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HDAUDIO_PREMEM_CONFIG Member List

This is the complete list of members for HDAUDIO_PREMEM_CONFIG, including all inherited members.

AudioLinkDmic | HDAUDIO_PREMEM_CONFIG
AudioLinkHda | HDAUDIO_PREMEM_CONFIG
AudioLinkSndw | HDAUDIO_PREMEM_CONFIG
AudioLinkSsp | HDAUDIO_PREMEM_CONFIG
DspEnable | HDAUDIO_PREMEM_CONFIG
DspUaaCompliance | HDAUDIO_PREMEM_CONFIG
Enable | HDAUDIO_PREMEM_CONFIG
Header | HDAUDIO_PREMEM_CONFIG
IDispCodecDisconnect | HDAUDIO_PREMEM_CONFIG
IDispLinkFrequency | HDAUDIO_PREMEM_CONFIG
IDispLinkTmode | HDAUDIO_PREMEM_CONFIG
PowerGatingSupported | HDAUDIO_PREMEM_CONFIG
ResetWaitTimer | HDAUDIO_PREMEM_CONFIG
Rsvd0 | HDAUDIO_PREMEM_CONFIG
RsvdBits | HDAUDIO_PREMEM_CONFIG
SubSystemIds | HDAUDIO_PREMEM_CONFIG
VcType | HDAUDIO_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_ASF_PUSH_PROGRESS_CODE Struct Reference

Public Attributes | List of all members
HECI_ASF_PUSH_PROGRESS_CODE Struct Reference

ASF Push Progress Code. More...

#include <AsfMsgs.h>

Collaboration diagram for HECI_ASF_PUSH_PROGRESS_CODE:
[legend]

Public Attributes

UINT8 | Command
ASF Message Command.
UINT8 | ByteCount
ASF Message Bytes Count Beyond This Byte.
ASF_MESSAGE AsfMessage
ASF Message Instance.
UINT8 | EventData [3]
Additional parametric data.

Detailed Description

ASF Push Progress Code.

Definition at line 485 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_ASF_PUSH_PROGRESS_CODE Member List

This is the complete list of members for HECI_ASF_PUSH_PROGRESS_CODE, including all inherited members.

AsfMessage | HECI_ASF_PUSH_PROGRESS_CODE
ByteCount | HECI_ASF_PUSH_PROGRESS_CODE
Command | HECI_ASF_PUSH_PROGRESS_CODE
EventData | HECI_ASF_PUSH_PROGRESS_CODE
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_CONTROL_STATUS_REGISTER Union Reference

List of all members
HECI_CONTROL_STATUS_REGISTER Union Reference

Register definitions. More...

#include <HeciRegs.h>

Detailed Description

Register definitions.

H_CSR - Host Control Status Register, offset 04h ME_CSR_HA - ME Control Status Register (Host Access), offset 0Ch

Definition at line 66 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_CONTROL_STATUS_REGISTER Member List

This is the complete list of members for HECI_CONTROL_STATUS_REGISTER, including all inherited members.

CBDepth | HECI_CONTROL_STATUS_REGISTER
CBReadPointer | HECI_CONTROL_STATUS_REGISTER
CBWritePointer | HECI_CONTROL_STATUS_REGISTER
IntEnable | HECI_CONTROL_STATUS_REGISTER
IntGenerate | HECI_CONTROL_STATUS_REGISTER
IntStatus | HECI_CONTROL_STATUS_REGISTER
Ready | HECI_CONTROL_STATUS_REGISTER
Reserved | HECI_CONTROL_STATUS_REGISTER
Reset | HECI_CONTROL_STATUS_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_FW_STS3_REGISTER Union Reference

List of all members
HECI_FW_STS3_REGISTER Union Reference

HFSTS3, offset 60h. More...

#include <HeciRegs.h>

Detailed Description

HFSTS3, offset 60h.

Definition at line 137 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_FW_STS3_REGISTER Member List

This is the complete list of members for HECI_FW_STS3_REGISTER, including all inherited members.

FwSku | HECI_FW_STS3_REGISTER
Reserved | HECI_FW_STS3_REGISTER
Reserved2 | HECI_FW_STS3_REGISTER
Reserved3 | HECI_FW_STS3_REGISTER
RpmcStatus | HECI_FW_STS3_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_FW_STS4_REGISTER Union Reference

List of all members
HECI_FW_STS4_REGISTER Union Reference

HFSTS4, offset 64h. More...

#include <HeciRegs.h>

Detailed Description

HFSTS4, offset 64h.

Definition at line 151 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_FW_STS4_REGISTER Member List

This is the complete list of members for HECI_FW_STS4_REGISTER, including all inherited members.

AllTpmDisconnected | HECI_FW_STS4_REGISTER
BootGuardFwStsValid | HECI_FW_STS4_REGISTER
BootGuardSelfTest | HECI_FW_STS4_REGISTER
dTpm12Deactivated | HECI_FW_STS4_REGISTER
FwInEnfFlow | HECI_FW_STS4_REGISTER
Reserved | HECI_FW_STS4_REGISTER
Reserved2 | HECI_FW_STS4_REGISTER
Reserved3 | HECI_FW_STS4_REGISTER
Reserved4 | HECI_FW_STS4_REGISTER
SxResumeType | HECI_FW_STS4_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_FW_STS5_REGISTER Union Reference

List of all members
HECI_FW_STS5_REGISTER Union Reference

HFSTS5, offset 68h. More...

#include <HeciRegs.h>

Detailed Description

HFSTS5, offset 68h.

Definition at line 170 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_FW_STS5_REGISTER Member List

This is the complete list of members for HECI_FW_STS5_REGISTER, including all inherited members.

AcmActived | HECI_FW_STS5_REGISTER
AcmDone | HECI_FW_STS5_REGISTER
ESC | HECI_FW_STS5_REGISTER
RCS | HECI_FW_STS5_REGISTER
Reserved | HECI_FW_STS5_REGISTER
ScrtmIndicator | HECI_FW_STS5_REGISTER
Smtc | HECI_FW_STS5_REGISTER
StartEnforcement | HECI_FW_STS5_REGISTER
VLD | HECI_FW_STS5_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_FW_STS6_REGISTER Union Reference

List of all members
HECI_FW_STS6_REGISTER Union Reference

HFSTS6, offset 6Ch. More...

#include <HeciRegs.h>

Detailed Description

HFSTS6, offset 6Ch.

Definition at line 188 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_FW_STS6_REGISTER Member List

This is the complete list of members for HECI_FW_STS6_REGISTER, including all inherited members.

BootGuardDisable | HECI_FW_STS6_REGISTER
BspInitDisabled | HECI_FW_STS6_REGISTER
CpuDebugDisabled | HECI_FW_STS6_REGISTER
ENF | HECI_FW_STS6_REGISTER
Error | HECI_FW_STS6_REGISTER
ExeStatus | HECI_FW_STS6_REGISTER
ForceBootPolicy | HECI_FW_STS6_REGISTER
FpfDisable | HECI_FW_STS6_REGISTER
FpfSocConfigLock | HECI_FW_STS6_REGISTER
KmId | HECI_FW_STS6_REGISTER
ManufacturingLock | HECI_FW_STS6_REGISTER
MeasuredBootPolicy | HECI_FW_STS6_REGISTER
PBE | HECI_FW_STS6_REGISTER
Reserved | HECI_FW_STS6_REGISTER
Reserved2 | HECI_FW_STS6_REGISTER
TxtSupport | HECI_FW_STS6_REGISTER
VerifiedBootPolicy | HECI_FW_STS6_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_FWS_REGISTER Union Reference

List of all members
HECI_FWS_REGISTER Union Reference

HFSTS1, offset 40h. More...

#include <HeciRegs.h>

Detailed Description

HFSTS1, offset 40h.

Definition at line 84 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_FWS_REGISTER Member List

This is the complete list of members for HECI_FWS_REGISTER, including all inherited members.

BistResetRequest | HECI_FWS_REGISTER
BistTestState | HECI_FWS_REGISTER
CurrentPowerSource | HECI_FWS_REGISTER
CurrentState | HECI_FWS_REGISTER
D0i3SupportValid | HECI_FWS_REGISTER
D3SupportValid | HECI_FWS_REGISTER
ErrorCode | HECI_FWS_REGISTER
FptBad | HECI_FWS_REGISTER
FtBupLdFlr | HECI_FWS_REGISTER
FwInitComplete | HECI_FWS_REGISTER
FwUpdateInprogress | HECI_FWS_REGISTER
InvokeEDebugMode | HECI_FWS_REGISTER
MeBootOptionsPresent | HECI_FWS_REGISTER
MeOperationMode | HECI_FWS_REGISTER
MeOperationState | HECI_FWS_REGISTER
MeRstCnt | HECI_FWS_REGISTER
SpiProtectionMode | HECI_FWS_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HECI_GS_SHDW_REGISTER Union Reference

List of all members
HECI_GS_SHDW_REGISTER Union Reference

HFSTS2, offset 48h. More...

#include <HeciRegs.h>

Detailed Description

HFSTS2, offset 48h.

Definition at line 110 of file HeciRegs.h.

The documentation for this union was generated from the following file:
  • HeciRegs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HECI_GS_SHDW_REGISTER Member List

This is the complete list of members for HECI_GS_SHDW_REGISTER, including all inherited members.

CpuReplacedSts | HECI_GS_SHDW_REGISTER
CpuReplacedValid | HECI_GS_SHDW_REGISTER
CseToDisabled | HECI_GS_SHDW_REGISTER
ExtStatCode1 | HECI_GS_SHDW_REGISTER
ExtStatCode2 | HECI_GS_SHDW_REGISTER
FwUpdForcedSB | HECI_GS_SHDW_REGISTER
FwUpdIpu | HECI_GS_SHDW_REGISTER
HeciListCh | HECI_GS_SHDW_REGISTER
IccProgSts | HECI_GS_SHDW_REGISTER
InfPhaseCode | HECI_GS_SHDW_REGISTER
InvokeMEBx | HECI_GS_SHDW_REGISTER
LowPowerState | HECI_GS_SHDW_REGISTER
MePowerGating | HECI_GS_SHDW_REGISTER
MfsFailure | HECI_GS_SHDW_REGISTER
NftpLoadFailure | HECI_GS_SHDW_REGISTER
Reserved | HECI_GS_SHDW_REGISTER
Reserved2 | HECI_GS_SHDW_REGISTER
WarmRstReqForDF | HECI_GS_SHDW_REGISTER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HG_INFO Struct Reference

List of all members
HG_INFO Struct Reference

HG Info HOB. More...

#include <HgInfoHob.h>

Collaboration diagram for HG_INFO:
[legend]

Detailed Description

HG Info HOB.

Definition at line 66 of file HgInfoHob.h.

The documentation for this struct was generated from the following file:
  • HgInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HG_INFO Member List

This is the complete list of members for HG_INFO, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HMRFPO_ENABLE Struct Reference

List of all members
HMRFPO_ENABLE Struct Reference

HMRFPO ENABLE. More...

#include <MkhiMsgs.h>

Collaboration diagram for HMRFPO_ENABLE:
[legend]

Detailed Description

HMRFPO ENABLE.

Definition at line 538 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HMRFPO_ENABLE Member List

This is the complete list of members for HMRFPO_ENABLE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HMRFPO_GET_STATUS Struct Reference

List of all members
HMRFPO_GET_STATUS Struct Reference

HMRFPO GET STATUS. More...

#include <MkhiMsgs.h>

Collaboration diagram for HMRFPO_GET_STATUS:
[legend]

Detailed Description

HMRFPO GET STATUS.

Definition at line 591 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HMRFPO_GET_STATUS Member List

This is the complete list of members for HMRFPO_GET_STATUS, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HMRFPO_LOCK Struct Reference

List of all members
HMRFPO_LOCK Struct Reference

HMRFPO LOCK. More...

#include <MkhiMsgs.h>

Collaboration diagram for HMRFPO_LOCK:
[legend]

Detailed Description

HMRFPO LOCK.

Definition at line 566 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HMRFPO_LOCK Member List

This is the complete list of members for HMRFPO_LOCK, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HOB_SAGV_INFO Struct Reference

Public Attributes | List of all members
HOB_SAGV_INFO Struct Reference

This data structure contains SAGV config values that are considered output by the MRC. More...

#include <MemInfoHob.h>

Collaboration diagram for HOB_SAGV_INFO:
[legend]

Public Attributes

UINT32 | NumSaGvPointsEnabled
Count of the total number of SAGV Points enabled.
UINT32 | SaGvPointMask
Bit mask where each bit indicates an enabled SAGV point.

Detailed Description

This data structure contains SAGV config values that are considered output by the MRC.

Definition at line 256 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HOB_SAGV_INFO Member List

This is the complete list of members for HOB_SAGV_INFO, including all inherited members.

NumSaGvPointsEnabled | HOB_SAGV_INFO
SaGvPointMask | HOB_SAGV_INFO
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HOB_SAGV_TIMING_OUT Struct Reference

Public Attributes | List of all members
HOB_SAGV_TIMING_OUT Struct Reference

This data structure contains per-SaGv timing values that are considered output by the MRC. More...

#include <MemInfoHob.h>

Public Attributes

UINT32 | DataRate
The memory rate for the current SaGv Point in units of MT/s.
MRC_CH_TIMING | JedecTiming
Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec.
MRC_IP_TIMING | IpTiming
Timings used for this entry's corresponding SaGv Point - IP specific.

Detailed Description

This data structure contains per-SaGv timing values that are considered output by the MRC.

Definition at line 249 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HOB_SAGV_TIMING_OUT Member List

This is the complete list of members for HOB_SAGV_TIMING_OUT, including all inherited members.

DataRate | HOB_SAGV_TIMING_OUT
IpTiming | HOB_SAGV_TIMING_OUT
JedecTiming | HOB_SAGV_TIMING_OUT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HOB_USAGE_DATA_HOB Struct Reference

List of all members
HOB_USAGE_DATA_HOB Struct Reference

Hob Usage Data Hob. More...

#include <HobUsageDataHob.h>

Detailed Description

Hob Usage Data Hob.

Revision 1:

  • Initial version.

Definition at line 49 of file HobUsageDataHob.h.

The documentation for this struct was generated from the following file:
  • HobUsageDataHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HOB_USAGE_DATA_HOB Member List

This is the complete list of members for HOB_USAGE_DATA_HOB, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HOST_BRIDGE_PEI_CONFIG Struct Reference

Public Attributes | List of all members
HOST_BRIDGE_PEI_CONFIG Struct Reference

This configuration block describes HostBridge settings in Post-Mem. More...

#include <HostBridgeConfig.h>

Collaboration diagram for HOST_BRIDGE_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | Device4Enable
Offser 28 :This policy is used to control enable or disable System Agent Thermal device (0,4,0). 0=FALSE, 1=TRUE.
UINT8 | ChapDeviceEnable
Offset 29 :(Test)This policy is used to control enable or disable System Agent Chap device (0,7,0). 0=FALSE, 1=TRUE.
UINT8 | SkipPamLock
Offset 30 :To skip PAM register locking. More...
UINT8 | EdramTestMode
Offset 28 :EDRAM Test Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- EDRAM HW Mode

Detailed Description

This configuration block describes HostBridge settings in Post-Mem.

Revision 1:

  • Initial version.

Definition at line 80 of file HostBridgeConfig.h.

Member Data Documentation

◆ SkipPamLock

UINT8 HOST_BRIDGE_PEI_CONFIG::SkipPamLock

Offset 30 :To skip PAM register locking.

Note
It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.
0=All PAM registers will be locked in Silicon code, 1=Skip lock PAM registers in Silicon code.

Definition at line 84 of file HostBridgeConfig.h.

The documentation for this struct was generated from the following file:
  • HostBridgeConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HOST_BRIDGE_PEI_CONFIG Member List

This is the complete list of members for HOST_BRIDGE_PEI_CONFIG, including all inherited members.

ChapDeviceEnable | HOST_BRIDGE_PEI_CONFIG
Device4Enable | HOST_BRIDGE_PEI_CONFIG
EdramTestMode | HOST_BRIDGE_PEI_CONFIG
Header | HOST_BRIDGE_PEI_CONFIG
SkipPamLock | HOST_BRIDGE_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HOST_BRIDGE_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
HOST_BRIDGE_PREMEM_CONFIG Struct Reference

This configuration block describes HostBridge settings in PreMem. More...

#include <HostBridgeConfig.h>

Collaboration diagram for HOST_BRIDGE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | MchBar
Offset 28 Address of System Agent MCHBAR: 0xFEDC0000(TGL)/0xFEA80000(JSL)
UINT32 | DmiBar
Offset 32 Address of System Agent DMIBAR: 0xFEDA0000
UINT32 | EpBar
Offset 36 Address of System Agent EPBAR: 0xFEDA1000
UINT32 | GdxcBar
Offset 40 Address of System Agent GDXCBAR: 0xFED84000
UINT32 | RegBar
Offset 44 Address of System Agent REGBAR: 0xFB000000
UINT32 | EdramBar
Offset 48 Address of System Agent EDRAMBAR: 0xFED80000
UINT32 | MmioSize
Offset 52 : Size of reserved MMIO space for PCI devices
0=AUTO, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB, 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB
When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
UINT32 | MmioSizeAdjustment
Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): 0=no adjustment
UINT8 | EnableAbove4GBMmio
Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, 1=Enable
UINT8 | Reserved [3]
Offset 61 Reserved for future use.

Detailed Description

This configuration block describes HostBridge settings in PreMem.

Revision 1:

  • Initial version.

Definition at line 53 of file HostBridgeConfig.h.

The documentation for this struct was generated from the following file:
  • HostBridgeConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HOST_BRIDGE_PREMEM_CONFIG Member List

This is the complete list of members for HOST_BRIDGE_PREMEM_CONFIG, including all inherited members.

DmiBar | HOST_BRIDGE_PREMEM_CONFIG
EdramBar | HOST_BRIDGE_PREMEM_CONFIG
EnableAbove4GBMmio | HOST_BRIDGE_PREMEM_CONFIG
EpBar | HOST_BRIDGE_PREMEM_CONFIG
GdxcBar | HOST_BRIDGE_PREMEM_CONFIG
Header | HOST_BRIDGE_PREMEM_CONFIG
MchBar | HOST_BRIDGE_PREMEM_CONFIG
MmioSize | HOST_BRIDGE_PREMEM_CONFIG
MmioSizeAdjustment | HOST_BRIDGE_PREMEM_CONFIG
RegBar | HOST_BRIDGE_PREMEM_CONFIG
Reserved | HOST_BRIDGE_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HR_NOTIFICATION_CMD Struct Reference

List of all members
HR_NOTIFICATION_CMD Struct Reference

PM group defines. More...

#include <BupMsgs.h>

Collaboration diagram for HR_NOTIFICATION_CMD:
[legend]

Detailed Description

PM group defines.

Definition at line 484 of file BupMsgs.h.

The documentation for this struct was generated from the following file:
  • BupMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HR_NOTIFICATION_CMD Member List

This is the complete list of members for HR_NOTIFICATION_CMD, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HSIO_PARAMETERS Struct Reference

Public Attributes | List of all members
HSIO_PARAMETERS Struct Reference

This structure describes USB3 Port N configuration parameters. More...

#include <Usb3HsioConfig.h>

Public Attributes

UINT8 | HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
UINT8 | HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] Default = 29h (approximately -3.5dB De-Emphasis)
UINT8 | HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code. More...
UINT8 | HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2.4ns 2h:3.2ns 3h:4.0ns 4h:4.8ns 5h:5.6ns 6h:6.4ns Default = 0h
UINT8 | HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001 45K 010 Prohibited 011 31K 100 36K 101 36K 110 36K 111 36K Default = 3h
UINT8 | HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
UINT8 | HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
UINT8 | HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
UINT8 | HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
UINT8 | HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] Default = 4Ch
UINT8 | HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] Default = 4Ch
UINT8 | HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16] Default = 4Ch
UINT8 | HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24] Default = 4Ch
UINT8 | HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
UINT8 | HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
UINT8 | HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
UINT8 | HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.

Detailed Description

This structure describes USB3 Port N configuration parameters.

Definition at line 49 of file Usb3HsioConfig.h.

Member Data Documentation

◆ HsioCtrlAdaptOffsetCfg

UINT8 HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg

Signed Magnatude number added to the CTLE code.

(ctle_adapt_offset_cfg_4_0) HSIO_RX_DWORD25 [20:16] Ex: -1 – 1_0001. +1: 0_0001 Default = 0h

Definition at line 68 of file Usb3HsioConfig.h.

The documentation for this struct was generated from the following file:
  • Usb3HsioConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HSIO_PARAMETERS Member List

This is the complete list of members for HSIO_PARAMETERS, including all inherited members.

HsioCtrlAdaptOffsetCfg | HSIO_PARAMETERS
HsioCtrlAdaptOffsetCfgEnable | HSIO_PARAMETERS
HsioFilterSelN | HSIO_PARAMETERS
HsioFilterSelNEnable | HSIO_PARAMETERS
HsioFilterSelP | HSIO_PARAMETERS
HsioFilterSelPEnable | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnRes | HSIO_PARAMETERS
HsioOlfpsCfgPullUpDwnResEnable | HSIO_PARAMETERS
HsioTxDeEmph | HSIO_PARAMETERS
HsioTxDeEmphEnable | HSIO_PARAMETERS
HsioTxDownscaleAmp | HSIO_PARAMETERS
HsioTxDownscaleAmpEnable | HSIO_PARAMETERS
HsioTxRate0UniqTran | HSIO_PARAMETERS
HsioTxRate0UniqTranEnable | HSIO_PARAMETERS
HsioTxRate1UniqTran | HSIO_PARAMETERS
HsioTxRate1UniqTranEnable | HSIO_PARAMETERS
HsioTxRate2UniqTran | HSIO_PARAMETERS
HsioTxRate2UniqTranEnable | HSIO_PARAMETERS
HsioTxRate3UniqTran | HSIO_PARAMETERS
HsioTxRate3UniqTranEnable | HSIO_PARAMETERS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HWA_DATA Union Reference

List of all members
HWA_DATA Union Reference

HWA AppId. More...

#include <MeBiosPayloadData.h>

Detailed Description

HWA AppId.

Definition at line 246 of file MeBiosPayloadData.h.

The documentation for this union was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HWA_DATA Member List

This is the complete list of members for HWA_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HWA_MESSAGE_HEADER Union Reference

List of all members
HWA_MESSAGE_HEADER Union Reference

Definitions for Hardware Asset Header. More...

#include <DxeMeLib.h>

Detailed Description

Definitions for Hardware Asset Header.

Definition at line 58 of file DxeMeLib.h.

The documentation for this union was generated from the following file:
  • DxeMeLib.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HWA_MESSAGE_HEADER Member List

This is the complete list of members for HWA_MESSAGE_HEADER, including all inherited members.

Command HWA_MESSAGE_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HWA_PUSH_TABLES_MSG Struct Reference

List of all members
HWA_PUSH_TABLES_MSG Struct Reference

Asset Update Table Message. More...

#include <DxeMeLib.h>

Collaboration diagram for HWA_PUSH_TABLES_MSG:
[legend]

Detailed Description

Asset Update Table Message.

Definition at line 95 of file DxeMeLib.h.

The documentation for this struct was generated from the following file:
  • DxeMeLib.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HWA_PUSH_TABLES_MSG Member List

This is the complete list of members for HWA_PUSH_TABLES_MSG, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HYBRID_GRAPHICS_CONFIG Struct Reference

Public Attributes | List of all members
HYBRID_GRAPHICS_CONFIG Struct Reference

This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port. More...

#include <HybridGraphicsConfig.h>

Collaboration diagram for HYBRID_GRAPHICS_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio
Offset 28 RTD3 GPIOs used for PCIe.
UINT8 | RootPortIndex
Offset 52 Root Port Index number used for HG.
UINT8 | HgMode
Offset 53 HgMode: 0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=PEG.
UINT16 | HgSubSystemId
Offset 54 Hybrid Graphics Subsystem ID: 2212
UINT16 | HgDelayAfterPwrEn
Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, 300=300 microseconds
UINT16 | HgDelayAfterHoldReset
Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, 100=100 microseconds
CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio
Offset 60 RTD3 GPIOs used for PCIe.
CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio
Offset 84 RTD3 GPIOs used for PCIe.
CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio
Offset 108 RTD3 GPIOs used for PCIe.
UINT8 | HgSupport
Offset 132 HgSupport on specific port.
UINT8 | Rsvd0 [3]
Offset 133 Reserved bytes for future use.

Detailed Description

This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.

Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3. Revision 1:

  • Initial version. Revision 2:
  • Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics Revision 3:
  • Removed HgSlot Policy: As there is no selection between PEG or PCH Slot for Hybrid Graphics Revision 4:
  • Added HgSupport Policy: To support HG support on other PEG ports

Definition at line 83 of file HybridGraphicsConfig.h.

The documentation for this struct was generated from the following file:
  • HybridGraphicsConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HYBRID_GRAPHICS_CONFIG Member List

This is the complete list of members for HYBRID_GRAPHICS_CONFIG, including all inherited members.

CpuPcie0Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie1Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie2Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
CpuPcie3Rtd3Gpio | HYBRID_GRAPHICS_CONFIG
Header | HYBRID_GRAPHICS_CONFIG
HgDelayAfterHoldReset | HYBRID_GRAPHICS_CONFIG
HgDelayAfterPwrEn | HYBRID_GRAPHICS_CONFIG
HgMode | HYBRID_GRAPHICS_CONFIG
HgSubSystemId | HYBRID_GRAPHICS_CONFIG
HgSupport | HYBRID_GRAPHICS_CONFIG
RootPortIndex | HYBRID_GRAPHICS_CONFIG
Rsvd0 | HYBRID_GRAPHICS_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HYBRID_STORAGE_CONFIG Struct Reference

Public Attributes | List of all members
HYBRID_STORAGE_CONFIG Struct Reference

The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device. More...

#include <HybridStorageConfig.h>

Collaboration diagram for HYBRID_STORAGE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 HybridStorageMode
Hybrid Storage Mode 0: Disable, 1: Enable Dynamic Configuration.

Detailed Description

The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device.

Revision 1:

  • Init version Revision 2:
  • Added support for cpu attached hybrid storage

Definition at line 54 of file HybridStorageConfig.h.

The documentation for this struct was generated from the following file:
  • HybridStorageConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

HYBRID_STORAGE_CONFIG Member List

This is the complete list of members for HYBRID_STORAGE_CONFIG, including all inherited members.

Header | HYBRID_STORAGE_CONFIG
HybridStorageMode | HYBRID_STORAGE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): I2C_PIN_MUX Struct Reference

Public Attributes | List of all members
I2C_PIN_MUX Struct Reference

I2C signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
UINT32 | Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.

Detailed Description

I2C signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h for supported settings on a given platform

Definition at line 228 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

I2C_PIN_MUX Member List

This is the complete list of members for I2C_PIN_MUX, including all inherited members.

Scl | I2C_PIN_MUX
Sda | I2C_PIN_MUX
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_CLOCK_MODE Union Reference

List of all members
ICC_CLOCK_MODE Union Reference

Used for the Clock Mode parameter of Get/Set Clock Settings. More...

#include <IccMsgs.h>

Detailed Description

Used for the Clock Mode parameter of Get/Set Clock Settings.

Definition at line 339 of file IccMsgs.h.

The documentation for this union was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_CLOCK_MODE Member List

This is the complete list of members for ICC_CLOCK_MODE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_CLOCK_SETTINGS Struct Reference

List of all members
ICC_CLOCK_SETTINGS Struct Reference

Structure for Clock Settings. More...

#include <IccMsgs.h>

Collaboration diagram for ICC_CLOCK_SETTINGS:
[legend]

Detailed Description

Structure for Clock Settings.

Definition at line 354 of file IccMsgs.h.

The documentation for this struct was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_CLOCK_SETTINGS Member List

This is the complete list of members for ICC_CLOCK_SETTINGS, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_CLOCK_SETTINGS_CURRENT_FLAGS Union Reference

List of all members
ICC_CLOCK_SETTINGS_CURRENT_FLAGS Union Reference

Used for the CURRENT FLAGS parameter of Get/Set Clock Settings. More...

#include <IccMsgs.h>

Detailed Description

Used for the CURRENT FLAGS parameter of Get/Set Clock Settings.

Definition at line 283 of file IccMsgs.h.

Member Data Documentation

◆ PwrCyclePending

UINT16 ICC_CLOCK_SETTINGS_CURRENT_FLAGS::PwrCyclePending

New Boot settings applied and power cycle reset pending.

Flag cleared once boot settings are consumed. Reserved in Set Clock Settings.

Definition at line 303 of file IccMsgs.h.

◆ Type

UINT16 ICC_CLOCK_SETTINGS_CURRENT_FLAGS::Type

Specifies how the settings with associated clock were applied.

0 - Persistent 1 - Dynamic , indicating a run time ad-hoc change (ramp) 2 - Reserved 3 - Reserved

Definition at line 295 of file IccMsgs.h.

The documentation for this union was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_CLOCK_SETTINGS_CURRENT_FLAGS Member List

This is the complete list of members for ICC_CLOCK_SETTINGS_CURRENT_FLAGS, including all inherited members.

ForcePowerFlow | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
PwrCyclePending | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Reserved | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Reserved1 | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
SetToDefault | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Type | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_CLOCK_SETTINGS_FLAGS Union Reference

List of all members
ICC_CLOCK_SETTINGS_FLAGS Union Reference

Get/Set Clock Settings. More...

#include <IccMsgs.h>

Detailed Description

Get/Set Clock Settings.

Used for the FLAGS parameter of Get/Set Clock Settings

Definition at line 272 of file IccMsgs.h.

The documentation for this union was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_CLOCK_SETTINGS_FLAGS Member List

This is the complete list of members for ICC_CLOCK_SETTINGS_FLAGS, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS Union Reference

List of all members
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS Union Reference

Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings. More...

#include <IccMsgs.h>

Detailed Description

Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings.

Definition at line 321 of file IccMsgs.h.

The documentation for this union was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS Member List

This is the complete list of members for ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS, including all inherited members.

Bclk | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
CenterSpread | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
ChangeAllowed | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
DownSpread | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
HaltAllowed | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
PCIe | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
Reserved | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
Reserved1 | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
UpSpread | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_GET_CLK_CAPABILITIES_MESSAGE Struct Reference

List of all members
ICC_GET_CLK_CAPABILITIES_MESSAGE Struct Reference

Get/Set ICC Clock Capabilities. More...

#include <IccMsgs.h>

Detailed Description

Get/Set ICC Clock Capabilities.

Definition at line 238 of file IccMsgs.h.

The documentation for this struct was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_GET_CLK_CAPABILITIES_MESSAGE Member List

This is the complete list of members for ICC_GET_CLK_CAPABILITIES_MESSAGE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ Struct Reference

List of all members
ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ Struct Reference

Get Soft Strap Config. More...

#include <IccMsgs.h>

Detailed Description

Get Soft Strap Config.

Definition at line 495 of file IccMsgs.h.

The documentation for this struct was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ Member List

This is the complete list of members for ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_GETSET_CLOCK_SETTINGS_REQRSP Struct Reference

List of all members
ICC_GETSET_CLOCK_SETTINGS_REQRSP Struct Reference

Combined Request and Response structure for Get/Set Clock Settings. More...

#include <IccMsgs.h>

Collaboration diagram for ICC_GETSET_CLOCK_SETTINGS_REQRSP:
[legend]

Detailed Description

Combined Request and Response structure for Get/Set Clock Settings.

Definition at line 394 of file IccMsgs.h.

The documentation for this struct was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_GETSET_CLOCK_SETTINGS_REQRSP Member List

This is the complete list of members for ICC_GETSET_CLOCK_SETTINGS_REQRSP, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_MESSAGE_RESP_DATA Struct Reference

Public Attributes | List of all members
ICC_MESSAGE_RESP_DATA Struct Reference

ICC group defines. More...

#include <BupMsgs.h>

Public Attributes

UINT32 | FwNeedsWarmResetFlag:1
BIT0.
UINT32 | Reserved:31
BIT1-31.

Detailed Description

ICC group defines.

Definition at line 436 of file BupMsgs.h.

The documentation for this struct was generated from the following file:
  • BupMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_MESSAGE_RESP_DATA Member List

This is the complete list of members for ICC_MESSAGE_RESP_DATA, including all inherited members.

FwNeedsWarmResetFlag | ICC_MESSAGE_RESP_DATA
Reserved | ICC_MESSAGE_RESP_DATA
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ICC_OVERRIDE_SOFT_STRAP_CMD_REQ Struct Reference

Public Attributes | List of all members
ICC_OVERRIDE_SOFT_STRAP_CMD_REQ Struct Reference

This is only a template. More...

#include <IccMsgs.h>

Public Attributes

UINT16 | NumOfControllers
Number of PCI-E ports to be configured.
UINT8 | ControllerConfig [0]
Please refer to ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE.

Detailed Description

This is only a template.

Data should be filled in runtime

Definition at line 468 of file IccMsgs.h.

The documentation for this struct was generated from the following file:
  • IccMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ICC_OVERRIDE_SOFT_STRAP_CMD_REQ Member List

This is the complete list of members for ICC_OVERRIDE_SOFT_STRAP_CMD_REQ, including all inherited members.

ControllerConfig | ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
NumOfControllers | ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IEH_CONFIG Struct Reference

Public Attributes | List of all members
IEH_CONFIG Struct Reference

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

#include <IehConfig.h>

Collaboration diagram for IEH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Mode: 1
IEH mode 0: Bypass Mode; 1: Enable.
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.

Definition at line 53 of file IehConfig.h.

The documentation for this struct was generated from the following file:
  • IehConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IEH_CONFIG Member List

This is the complete list of members for IEH_CONFIG, including all inherited members.

Header | IEH_CONFIG
Mode | IEH_CONFIG
RsvdBits0 | IEH_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IGD_OPREGION_PROTOCOL Struct Reference

Public Attributes | List of all members
IGD_OPREGION_PROTOCOL Struct Reference

IGD OpRegion Protocol. More...

#include <IgdOpRegion.h>

Public Attributes

IGD_OPREGION_STRUCTURE * OpRegion
IGD Operation Region Structure.

Detailed Description

IGD OpRegion Protocol.

Definition at line 47 of file IgdOpRegion.h.

The documentation for this struct was generated from the following file:
  • IgdOpRegion.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IGD_OPREGION_PROTOCOL Member List

This is the complete list of members for IGD_OPREGION_PROTOCOL, including all inherited members.

OpRegion IGD_OPREGION_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): INVOCATION_CODE_BITS Union Reference

List of all members
INVOCATION_CODE_BITS Union Reference

MKHI_CBM_GROUP Definitions. More...

#include <MkhiMsgs.h>

Detailed Description

MKHI_CBM_GROUP Definitions.

Definition at line 160 of file MkhiMsgs.h.

The documentation for this union was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

INVOCATION_CODE_BITS Member List

This is the complete list of members for INVOCATION_CODE_BITS, including all inherited members.

ClsUserInfo | INVOCATION_CODE_BITS
CpuReplacement | INVOCATION_CODE_BITS
DataSyncConfirmation | INVOCATION_CODE_BITS
FirstMebxBoot | INVOCATION_CODE_BITS
FwUnconfiguration | INVOCATION_CODE_BITS
FwUpdate | INVOCATION_CODE_BITS
IderStateChange | INVOCATION_CODE_BITS
KvmStateChange | INVOCATION_CODE_BITS
Reserved2 | INVOCATION_CODE_BITS
SolStateChange | INVOCATION_CODE_BITS
SyncMngState | INVOCATION_CODE_BITS
SyncRaAvailability | INVOCATION_CODE_BITS
TableSyncError | INVOCATION_CODE_BITS
UserConsentFlow | INVOCATION_CODE_BITS
WlanPowerConfigChange | INVOCATION_CODE_BITS
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IO_TRAP_EX_REGISTER_CONTEXT Struct Reference

Public Attributes | List of all members
IO_TRAP_EX_REGISTER_CONTEXT Struct Reference

IO Trap Ex context structure containing information about the IO trap Ex event that should invoke the handler. More...

#include <IoTrapExDispatch.h>

Public Attributes

UINT16 | Address
The Address must be dword alignment.
UINT8 | ByteEnable
Bitmap to enable trap for each byte of every dword alignment address. More...
UINT8 | ByteEnableMask
ByteEnableMask bitwise to ignore the ByteEnable setting. More...

Detailed Description

IO Trap Ex context structure containing information about the IO trap Ex event that should invoke the handler.

ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for any byte access.

Here are some examples for the usage.

  1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with BYTE/WORD/DWORD read/write access: Address = 0x2000 Length = 0x100 Type = IoTrapExTypeReadWrite ByteEnable = 0x00 (BE is not matter) ByteEnableMask = 0x0F (BEM 0xF for any BYTE/WORD/DWORD access)
  2. To trigger the TRAP for port 0x61 with BYTE read access: Address = 0x60 Length = 4 Type = IoTrapExTypeRead ByteEnable = 0x02 (BE is 0010b to trap only second byte of every DWORD) ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)
  3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access: Address = 0x60 Length = 8 Type = IoTrapExTypeWrite ByteEnable = 0x01 (BE is 0001b to trap only first byte of every DWORD) ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)

Definition at line 80 of file IoTrapExDispatch.h.

Member Data Documentation

◆ ByteEnable

UINT8 IO_TRAP_EX_REGISTER_CONTEXT::ByteEnable

Bitmap to enable trap for each byte of every dword alignment address.

The Io Trap Address must be dword alignment for ByteEnable. E.g. 0001b for first byte, 0010b for second byte, 1100b for third and fourth byte.

Definition at line 92 of file IoTrapExDispatch.h.

◆ ByteEnableMask

UINT8 IO_TRAP_EX_REGISTER_CONTEXT::ByteEnableMask

ByteEnableMask bitwise to ignore the ByteEnable setting.

E.g. 1111b for any byte access. The Io Trap Address must be dword alignment for ByteEnableMask.

Definition at line 97 of file IoTrapExDispatch.h.

The documentation for this struct was generated from the following file:
  • IoTrapExDispatch.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IO_TRAP_EX_REGISTER_CONTEXT Member List

This is the complete list of members for IO_TRAP_EX_REGISTER_CONTEXT, including all inherited members.

Address | IO_TRAP_EX_REGISTER_CONTEXT
ByteEnable | IO_TRAP_EX_REGISTER_CONTEXT
ByteEnableMask | IO_TRAP_EX_REGISTER_CONTEXT
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IOM_AUX_ORI_PAD_CONFIG Struct Reference

Public Attributes | List of all members
IOM_AUX_ORI_PAD_CONFIG Struct Reference

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | GpioPullN
GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
UINT32 | GpioPullP
GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.

Detailed Description

The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.

Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer. IOM needs know Pull-Up and Pull-Down pin for Bias control

Definition at line 55 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IOM_AUX_ORI_PAD_CONFIG Member List

This is the complete list of members for IOM_AUX_ORI_PAD_CONFIG, including all inherited members.

GpioPullN | IOM_AUX_ORI_PAD_CONFIG
GpioPullP | IOM_AUX_ORI_PAD_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IOM_INTERFACE_CONFIG Struct Reference

Public Attributes | List of all members
IOM_INTERFACE_CONFIG Struct Reference

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT32 | VccSt
IOM VCCST request. (Not equal to actual VCCST value)
UINT32 | UsbOverride
IOM to override USB connection.
UINT32 | D3ColdEnable
Enable/disable D3 Cold support in TCSS.
UINT32 | D3HotEnable
Enable/disable D3 Hot support in TCSS.

Detailed Description

The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.

Definition at line 64 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IOM_INTERFACE_CONFIG Member List

This is the complete list of members for IOM_INTERFACE_CONFIG, including all inherited members.

D3ColdEnable | IOM_INTERFACE_CONFIG
D3HotEnable | IOM_INTERFACE_CONFIG
UsbOverride | IOM_INTERFACE_CONFIG
VccSt | IOM_INTERFACE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IPU_DATA_HOB Struct Reference

Public Attributes | List of all members
IPU_DATA_HOB Struct Reference

This HOB is used to pass IPU related information to DXE phase. More...

#include <IpuDataHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
GUID Hob type structure for gIpuDataHobGuid.
BOOLEAN | IpuSupport
IpuSupport - Indicates IPU support status 1 - IPU is supported by Silicon and is opted-in to BIOS 0 - IPU is either not supported by Silicon or opted out of BIOS or both.

Detailed Description

This HOB is used to pass IPU related information to DXE phase.

Definition at line 45 of file IpuDataHob.h.

The documentation for this struct was generated from the following file:
  • IpuDataHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IPU_DATA_HOB Member List

This is the complete list of members for IPU_DATA_HOB, including all inherited members.

EfiHobGuidType | IPU_DATA_HOB
IpuSupport | IPU_DATA_HOB
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IPU_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
IPU_PREMEM_CONFIG Struct Reference

IPU PreMem configuration
Revision 1: More...

#include <IpuPreMemConfig.h>

Collaboration diagram for IPU_PREMEM_CONFIG:
[legend]

Public Attributes

UINT8 | IpuEnable
Config Block Header. More...
UINT8 | IpuImrConfiguration
Deprecate.
UINT8 | ImguClkOutEn [GPIO_IMGUCLK_NUMBER_OF_PINS]
It enable the IMGU CLKOUT. More...
UINT8 | LaneUsed [MAX_CSI_PORT]
Indicate laneUsed of each CSI port 0: Not configured; 1: x1; 2:x2; 3:x3; 4:x4.
UINT8 | CsiSpeed [MAX_CSI_PORT]
Indicate speed of each CSI port 0: Sensor default; 1: <416Mbps; 2:<1.5Gbps; 3:<2Gbps; 4:<2.5Gbps; 5:<4Gbps; 6>4Gbps.

Detailed Description

IPU PreMem configuration
Revision 1:

  • Initial version. Revision 2:
  • Change Bit-wise to Byte-wise. Revision 3:
  • Add LaneUsed and Speed of each Port configuration for Mcd10 support. Revision 4:
  • Change GPIO_IMGUCLK_NUMBER_OF_PINS to 6 Revision 5:
  • Deprecate IpuImrConfiguration.

Definition at line 70 of file IpuPreMemConfig.h.

Member Data Documentation

◆ ImguClkOutEn

UINT8 IPU_PREMEM_CONFIG::ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS]

It enable the IMGU CLKOUT.

TRUE FALSE

Definition at line 88 of file IpuPreMemConfig.h.

◆ IpuEnable

UINT8 IPU_PREMEM_CONFIG::IpuEnable

Config Block Header.

(Test) It enables the SA IPU Device if supported and not fused off. If FALSE, all other policies in this config block will be ignored. 1=TRUE; 0=FALSE.

Definition at line 78 of file IpuPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • IpuPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

IPU_PREMEM_CONFIG Member List

This is the complete list of members for IPU_PREMEM_CONFIG, including all inherited members.

CsiSpeed | IPU_PREMEM_CONFIG
ImguClkOutEn | IPU_PREMEM_CONFIG
IpuEnable | IPU_PREMEM_CONFIG
IpuImrConfiguration | IPU_PREMEM_CONFIG
LaneUsed | IPU_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_CONFIG Struct Reference

Public Attributes | List of all members
ISH_CONFIG Struct Reference

The ISH_CONFIG block describes Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PdtUnlock: 1
ISH PDT Unlock Msg: 0: False 1: True.
UINT32 | MsiInterrupt: 1
ISH MSI Interrupts: 0: False 1: True.
UINT32 | RsvdBits0: 30
Reserved Bits.

Detailed Description

The ISH_CONFIG block describes Integrated Sensor Hub device.

Definition at line 137 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_CONFIG Member List

This is the complete list of members for ISH_CONFIG, including all inherited members.

Header | ISH_CONFIG
MsiInterrupt | ISH_CONFIG
PdtUnlock | ISH_CONFIG
RsvdBits0 | ISH_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_GP Struct Reference

Public Attributes | List of all members
ISH_GP Struct Reference

Struct contains GPIO pins assigned and signal settings of GP. More...

#include <IshConfig.h>

Collaboration diagram for ISH_GP:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH GP GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of GP.

Definition at line 128 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_GP Member List

This is the complete list of members for ISH_GP, including all inherited members.

Enable | ISH_GP
RsvdBits0 | ISH_GP
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_GPIO_CONFIG Struct Reference

Public Attributes | List of all members
ISH_GPIO_CONFIG Struct Reference

ISH GPIO settings. More...

#include <IshConfig.h>

Public Attributes

UINT32 | PinMux
GPIO signals pin muxing settings. More...
UINT32 | PadTermination
GPIO Pads Internal Termination. More...

Detailed Description

ISH GPIO settings.

Definition at line 50 of file IshConfig.h.

Member Data Documentation

◆ PadTermination

UINT32 ISH_GPIO_CONFIG::PadTermination

GPIO Pads Internal Termination.

For more information please see Platform Design Guide. Check GPIO_ELECTRICAL_CONFIG for reference

Definition at line 62 of file IshConfig.h.

◆ PinMux

UINT32 ISH_GPIO_CONFIG::PinMux

GPIO signals pin muxing settings.

If signal can be enable only on a single pin then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h for supported settings on a given platform GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*

Definition at line 56 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_GPIO_CONFIG Member List

This is the complete list of members for ISH_GPIO_CONFIG, including all inherited members.

PadTermination | ISH_GPIO_CONFIG
PinMux | ISH_GPIO_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_I2C Struct Reference

Public Attributes | List of all members
ISH_I2C Struct Reference

Struct contains GPIO pins assigned and signal settings of I2C. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH I2C GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of I2C.

Definition at line 119 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_I2C Member List

This is the complete list of members for ISH_I2C, including all inherited members.

Enable | ISH_I2C
RsvdBits0 | ISH_I2C
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_I2C_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_I2C_PIN_CONFIG Struct Reference

I2C signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I2C_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Sda
SDA Pin configuration.
ISH_GPIO_CONFIG Scl
SCL Pin configuration.

Detailed Description

I2C signals settings.

Definition at line 90 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_I2C_PIN_CONFIG Member List

This is the complete list of members for ISH_I2C_PIN_CONFIG, including all inherited members.

Scl | ISH_I2C_PIN_CONFIG
Sda | ISH_I2C_PIN_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_I3C_CONFIG Struct Reference

Public Attributes | List of all members
ISH_I3C_CONFIG Struct Reference

The ISH_I3C_CONFIG block describes I3C in ISH device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_I3C_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
ISH_I3C Controller
ISH I3C Controller.

Detailed Description

The ISH_I3C_CONFIG block describes I3C in ISH device.

Definition at line 154 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_I3C_CONFIG Member List

This is the complete list of members for ISH_I3C_CONFIG, including all inherited members.

Controller | ISH_I3C_CONFIG
Header | ISH_I3C_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
ISH_PREMEM_CONFIG Struct Reference

Premem Policy for Integrated Sensor Hub device. More...

#include <IshConfig.h>

Collaboration diagram for ISH_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Enable: 1
ISH Controler 0: Disable; 1: Enable. More...
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Premem Policy for Integrated Sensor Hub device.

Definition at line 163 of file IshConfig.h.

Member Data Documentation

◆ Enable

UINT32 ISH_PREMEM_CONFIG::Enable

ISH Controler 0: Disable; 1: Enable.

For Desktop sku, the ISH POR should be disabled. 0:Disable .

Definition at line 169 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_PREMEM_CONFIG Member List

This is the complete list of members for ISH_PREMEM_CONFIG, including all inherited members.

Enable | ISH_PREMEM_CONFIG
Header | ISH_PREMEM_CONFIG
RsvdBits0 | ISH_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_SPI Struct Reference

Public Attributes | List of all members
ISH_SPI Struct Reference

Struct contains GPIO pins assigned and signal settings of SPI. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI:
[legend]

Public Attributes

UINT8 | Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
UINT8 | CsEnable [PCH_MAX_ISH_SPI_CS_PINS]
ISH SPI CS pins assigned: 0: False 1: True.
UINT16 | RsvdField0
Reserved field.

Detailed Description

Struct contains GPIO pins assigned and signal settings of SPI.

Definition at line 99 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_SPI Member List

This is the complete list of members for ISH_SPI, including all inherited members.

CsEnable | ISH_SPI
Enable | ISH_SPI
RsvdField0 | ISH_SPI
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_SPI_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_SPI_PIN_CONFIG Struct Reference

SPI signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_SPI_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
ISH_GPIO_CONFIG Cs [PCH_MAX_ISH_SPI_CS_PINS]
CS Pin configuration.

Detailed Description

SPI signals settings.

Definition at line 68 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_SPI_PIN_CONFIG Member List

This is the complete list of members for ISH_SPI_PIN_CONFIG, including all inherited members.

Clk | ISH_SPI_PIN_CONFIG
Cs | ISH_SPI_PIN_CONFIG
Miso | ISH_SPI_PIN_CONFIG
Mosi | ISH_SPI_PIN_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_UART Struct Reference

Public Attributes | List of all members
ISH_UART Struct Reference

Struct contains GPIO pins assigned and signal settings of UART. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART:
[legend]

Public Attributes

UINT32 | Enable: 1
ISH UART GPIO pins assigned: 0: False 1: True.
UINT32 | RsvdBits0: 31
Reserved Bits.

Detailed Description

Struct contains GPIO pins assigned and signal settings of UART.

Definition at line 110 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_UART Member List

This is the complete list of members for ISH_UART, including all inherited members.

Enable | ISH_UART
RsvdBits0 | ISH_UART
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ISH_UART_PIN_CONFIG Struct Reference

Public Attributes | List of all members
ISH_UART_PIN_CONFIG Struct Reference

UART signals settings. More...

#include <IshConfig.h>

Collaboration diagram for ISH_UART_PIN_CONFIG:
[legend]

Public Attributes

ISH_GPIO_CONFIG Rx
RXD Pin configuration.
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
ISH_GPIO_CONFIG Cts
CTS Pin configuration.

Detailed Description

UART signals settings.

Definition at line 79 of file IshConfig.h.

The documentation for this struct was generated from the following file:
  • IshConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ISH_UART_PIN_CONFIG Member List

This is the complete list of members for ISH_UART_PIN_CONFIG, including all inherited members.

Cts | ISH_UART_PIN_CONFIG
Rts | ISH_UART_PIN_CONFIG
Rx | ISH_UART_PIN_CONFIG
Tx | ISH_UART_PIN_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ITBT_POLICY_PROTOCOL Struct Reference

Public Attributes | List of all members
ITBT_POLICY_PROTOCOL Struct Reference

ITBT DXE Policy. More...

#include <ITbtPolicy.h>

Collaboration diagram for ITBT_POLICY_PROTOCOL:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Offset 0-31.

Detailed Description

ITBT DXE Policy.

The ITBT_POLICY_PROTOCOL producer drvier is recommended to set all the ITBT_POLICY_PROTOCOL size buffer zero before init any member parameter, this clear step can make sure no random value for those unknow new version parameters.

Make sure to update the Revision if any change to the protocol, including the existing internal structure definations.
Note: Here revision will be bumped up when adding/removing any config block under this structure.
Revision 1:

  • Initial version.

Definition at line 69 of file ITbtPolicy.h.

The documentation for this struct was generated from the following file:
  • ITbtPolicy.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ITBT_POLICY_PROTOCOL Member List

This is the complete list of members for ITBT_POLICY_PROTOCOL, including all inherited members.

TableHeader ITBT_POLICY_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_FW_VERSION_NAME Struct Reference

List of all members
MBP_FW_VERSION_NAME Struct Reference

MBP items. More...

#include <MeBiosPayloadData.h>

Detailed Description

MBP items.

Kernel AppId

Definition at line 148 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_FW_VERSION_NAME Member List

This is the complete list of members for MBP_FW_VERSION_NAME, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_HEADER Struct Reference

Public Attributes | List of all members
MBP_HEADER Struct Reference

Common MBP types. More...

#include <MeBiosPayloadData.h>

Public Attributes

UINT8 | MbpSize
Byte 0 - MBP Size in DW including Header.
UINT8 | NumEntries
Byte 1 - Number of Entries (Data Items) in MBP.
UINT16 | Reserved
Byte [3:2] - Reserved.

Detailed Description

Common MBP types.

Definition at line 55 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_HEADER Member List

This is the complete list of members for MBP_HEADER, including all inherited members.

MbpSize | MBP_HEADER
NumEntries | MBP_HEADER
Reserved | MBP_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_IFWI_DNX_REQUEST Struct Reference

List of all members
MBP_IFWI_DNX_REQUEST Struct Reference

MBP IFWI DNX request structure containing IFWI Dnx request data. More...

#include <MeBiosPayloadData.h>

Detailed Description

MBP IFWI DNX request structure containing IFWI Dnx request data.

Definition at line 210 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_IFWI_DNX_REQUEST Member List

This is the complete list of members for MBP_IFWI_DNX_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_ITEM_HEADER Union Reference

List of all members
MBP_ITEM_HEADER Union Reference

MBP items header. More...

#include <MeBiosPayloadData.h>

Detailed Description

MBP items header.

Definition at line 64 of file MeBiosPayloadData.h.

The documentation for this union was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_ITEM_HEADER Member List

This is the complete list of members for MBP_ITEM_HEADER, including all inherited members.

AppId | MBP_ITEM_HEADER
Flags | MBP_ITEM_HEADER
ItemId | MBP_ITEM_HEADER
Length | MBP_ITEM_HEADER
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_MPHY_DATA Struct Reference

List of all members
MBP_MPHY_DATA Struct Reference

ICC AppId. More...

#include <MeBiosPayloadData.h>

Detailed Description

ICC AppId.

Definition at line 263 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_MPHY_DATA Member List

This is the complete list of members for MBP_MPHY_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MBP_SENSITIVE_PPI Struct Reference

Public Attributes | List of all members
MBP_SENSITIVE_PPI Struct Reference

MBP SENSITIVE PPI Contains MBP sensitive data which should not be passed on to DXE as an HOB. More...

#include <MbpSensitivePpi.h>

Collaboration diagram for MBP_SENSITIVE_PPI:
[legend]

Public Attributes

UINT8 Revision
Policy structure revision number.

Detailed Description

MBP SENSITIVE PPI Contains MBP sensitive data which should not be passed on to DXE as an HOB.

Definition at line 55 of file MbpSensitivePpi.h.

The documentation for this struct was generated from the following file:
  • MbpSensitivePpi.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MBP_SENSITIVE_PPI Member List

This is the complete list of members for MBP_SENSITIVE_PPI, including all inherited members.

Revision MBP_SENSITIVE_PPI
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_BIOS_PAYLOAD Struct Reference

List of all members
ME_BIOS_PAYLOAD Struct Reference

ME BIOS Payload structure containing insensitive data only. More...

#include <MeBiosPayloadData.h>

Collaboration diagram for ME_BIOS_PAYLOAD:
[legend]

Detailed Description

ME BIOS Payload structure containing insensitive data only.

Definition at line 289 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_BIOS_PAYLOAD Member List

This is the complete list of members for ME_BIOS_PAYLOAD, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_BIOS_PAYLOAD_SENSITIVE Struct Reference

List of all members
ME_BIOS_PAYLOAD_SENSITIVE Struct Reference

All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below structure only. More...

#include <MeBiosPayloadData.h>

Detailed Description

All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below structure only.

Definition at line 310 of file MeBiosPayloadData.h.

The documentation for this struct was generated from the following file:
  • MeBiosPayloadData.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_BIOS_PAYLOAD_SENSITIVE Member List

This is the complete list of members for ME_BIOS_PAYLOAD_SENSITIVE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_CAP Struct Reference

Public Attributes | List of all members
ME_CAP Struct Reference

ME Platform Capabilities. More...

#include <MeSmbios.h>

Public Attributes

UINT32 | MeEnabled: 1
[0] ME enabled/Disabled
UINT32 | Reserved: 2
[2:1] Reserved, must set to 0
UINT32 | IntelAmtFw: 1
[3] Intel AMT FW support
UINT32 | IntelAmtFwStandard: 1
[4] Intel AMT Standard FW support
UINT32 | IntelAmtEnabled: 1
[5] Intel AMT Enabled
UINT32 | Reserved1: 7
[12:6] Reserved
UINT32 | IntelKVMEnabled: 1
[13] Intel KVM enabled
UINT32 | IntelKVM: 1
[14] Intel KVM supported
UINT32 | LocalWakeupTimer: 1
[15] Local Wakeup Timer support
UINT32 | Reserved2: 16
[31:16] Reserved, must set to 0
UINT32 | MeMinorVer: 16
[47:32] ME FW Minor Version.
UINT32 | MeMajorVer: 16
[63:48] ME FW Major Version.
UINT32 | MeBuildNo: 16
[79:64] ME FW Build Number.
UINT32 | MeHotFixNo: 16
[95:80] ME FW Hotfix Number

Detailed Description

ME Platform Capabilities.

Definition at line 125 of file MeSmbios.h.

The documentation for this struct was generated from the following file:
  • MeSmbios.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_CAP Member List

This is the complete list of members for ME_CAP, including all inherited members.

IntelAmtEnabled | ME_CAP
IntelAmtFw | ME_CAP
IntelAmtFwStandard | ME_CAP
IntelKVM | ME_CAP
IntelKVMEnabled | ME_CAP
LocalWakeupTimer | ME_CAP
MeBuildNo | ME_CAP
MeEnabled | ME_CAP
MeHotFixNo | ME_CAP
MeMajorVer | ME_CAP
MeMinorVer | ME_CAP
Reserved | ME_CAP
Reserved1 | ME_CAP
Reserved2 | ME_CAP
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_DXE_CONFIG Struct Reference

Public Attributes | List of all members
ME_DXE_CONFIG Struct Reference

ME Dxe Configuration Structure. More...

#include <MeDxeConfig.h>

Collaboration diagram for ME_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | MeFwDownGrade: 1
0: Disabled; 1: Enabled - Enable/Disable ME FW downgrade
UINT32 | MeJhiSupport: 1
0: Disabled; 1: Enabled - Enable/Disable Intel DAL Host Interface Service.
UINT32 | CoreBiosDoneEnabled: 1
0: Disabled; 1: Enabled - Enable/Disable Sending notification that BIOS is starting to run 3rd party code
UINT32 | ExtendMeMeasuredBoot: 1
0: Disabled; 1: Enabled - Enable/Disable ME/CSME Extended Measurement to TPM-PCR
UINT32 | RsvdBits: 28
Reserved for future use & Config block alignment.
ME_REPORT_ERROR MeReportError
Function pointer for displaying error message on screen.

Detailed Description

ME Dxe Configuration Structure.

Revision 1:

  • Initial version.

Definition at line 95 of file MeDxeConfig.h.

The documentation for this struct was generated from the following file:
  • MeDxeConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_DXE_CONFIG Member List

This is the complete list of members for ME_DXE_CONFIG, including all inherited members.

CoreBiosDoneEnabled | ME_DXE_CONFIG
ExtendMeMeasuredBoot | ME_DXE_CONFIG
Header | ME_DXE_CONFIG
MeFwDownGrade | ME_DXE_CONFIG
MeJhiSupport | ME_DXE_CONFIG
MeReportError | ME_DXE_CONFIG
RsvdBits | ME_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_PEI_CONFIG Struct Reference

Public Attributes | List of all members
ME_PEI_CONFIG Struct Reference

ME Pei Post-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | EndOfPostMessage: 2
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
UINT32 | Heci3Enabled: 1
UINT32 | DisableD0I3SettingForHeci: 1
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
UINT32 | MeUnconfigOnRtcClear: 2
Enable/Disable Me Unconfig On Rtc Clear. More...
UINT32 | MctpBroadcastCycle: 1
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
UINT32 | EnforceEDebugMode: 1
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
UINT32 | CseDataResilience: 1
0: Disable; 1: Enable - CSE data resilience support
UINT32 | RsvdBits: 23
Reserved for future use & Config block alignment.

Detailed Description

ME Pei Post-Memory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Deprecated Heci3Enabled. Revision 3
  • Added EnforceEDebugMode. Revision 4
  • Added CseDataResilience.

Definition at line 128 of file MePeiConfig.h.

Member Data Documentation

◆ Heci3Enabled

UINT32 ME_PEI_CONFIG::Heci3Enabled
Deprecated:

Definition at line 132 of file MePeiConfig.h.

◆ MeUnconfigOnRtcClear

UINT32 ME_PEI_CONFIG::MeUnconfigOnRtcClear

Enable/Disable Me Unconfig On Rtc Clear.

If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0. It will cause ME to unconfig if RTC is cleared.

  • 0: Disable
  • 1: Enable
  • 2: Cmos is clear, status unkonwn
  • 3: Reserved

Definition at line 142 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_PEI_CONFIG Member List

This is the complete list of members for ME_PEI_CONFIG, including all inherited members.

CseDataResilience | ME_PEI_CONFIG
DisableD0I3SettingForHeci | ME_PEI_CONFIG
EndOfPostMessage | ME_PEI_CONFIG
EnforceEDebugMode | ME_PEI_CONFIG
Header | ME_PEI_CONFIG
Heci3Enabled | ME_PEI_CONFIG
MctpBroadcastCycle | ME_PEI_CONFIG
MeUnconfigOnRtcClear | ME_PEI_CONFIG
RsvdBits | ME_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
ME_PEI_PREMEM_CONFIG Struct Reference

ME Pei Pre-Memory Configuration Structure. More...

#include <MePeiConfig.h>

Collaboration diagram for ME_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | HeciTimeouts: 1
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
UINT32 | DidInitStat: 2
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: ME DID init stat 2 - Memory Init Error
UINT32 | DisableCpuReplacedPolling: 1
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU replacement
UINT32 | SendDidMsg: 1
(Deprecated) 0: Disable; 1: Enable - Enable/Disable to send DID message.
UINT32 | DisableMessageCheck: 1
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without checking
UINT32 | SkipMbpHob: 1
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in a MBP message. More...
UINT32 | HeciCommunication2: 1
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
UINT32 | KtDeviceEnable: 1
(Test) 0: Disable; 1: Enable - Enable/Disable Kt Device.
UINT32 | SkipCpuReplacementCheck: 1
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
UINT32 | HeciFullTrace: 1
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
UINT32 | RsvdBits: 21
Reserved for future use & Config block alignment.
UINT32 | Heci1BarAddress
HECI1 BAR address.
UINT32 | Heci2BarAddress
HECI2 BAR address.
UINT32 | Heci3BarAddress
HECI3 BAR address.

Detailed Description

ME Pei Pre-Memory Configuration Structure.

Revision 1:

  • Initial version. Revision 2:
  • Add SkipCpuReplacementCheck Option. Revision 3:
  • Deprecate SendDidMsg. Revision 4:
  • Add HeciFullTrace Option.

Definition at line 65 of file MePeiConfig.h.

Member Data Documentation

◆ SkipMbpHob

UINT32 ME_PEI_PREMEM_CONFIG::SkipMbpHob

(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in a MBP message.

If set to 1, BIOS will send the MBP message with SkipMbp flag set causing CSME to respond with MKHI header only and no MBP data 0: ME BIOS will keep MBP and create HOB for MBP data 1: ME BIOS will skip MBP data

Definition at line 97 of file MePeiConfig.h.

The documentation for this struct was generated from the following file:
  • MePeiConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_PEI_PREMEM_CONFIG Member List

This is the complete list of members for ME_PEI_PREMEM_CONFIG, including all inherited members.

DidInitStat | ME_PEI_PREMEM_CONFIG
DisableCpuReplacedPolling | ME_PEI_PREMEM_CONFIG
DisableMessageCheck | ME_PEI_PREMEM_CONFIG
Header | ME_PEI_PREMEM_CONFIG
Heci1BarAddress | ME_PEI_PREMEM_CONFIG
Heci2BarAddress | ME_PEI_PREMEM_CONFIG
Heci3BarAddress | ME_PEI_PREMEM_CONFIG
HeciCommunication2 | ME_PEI_PREMEM_CONFIG
HeciFullTrace | ME_PEI_PREMEM_CONFIG
HeciTimeouts | ME_PEI_PREMEM_CONFIG
KtDeviceEnable | ME_PEI_PREMEM_CONFIG
RsvdBits | ME_PEI_PREMEM_CONFIG
SendDidMsg | ME_PEI_PREMEM_CONFIG
SkipCpuReplacementCheck | ME_PEI_PREMEM_CONFIG
SkipMbpHob | ME_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ME_SMBIOS_TABLES_UPDATE_PROTOCOL Struct Reference

List of all members
ME_SMBIOS_TABLES_UPDATE_PROTOCOL Struct Reference

ME SMBIOS Tables update protocol The interface functions are to update SMBIOS type 130 (in case of AMT) and 131. More...

#include <MeSmbiosUpdateProtocol.h>

Detailed Description

ME SMBIOS Tables update protocol The interface functions are to update SMBIOS type 130 (in case of AMT) and 131.

It is platform vendor's responsibility to implement the function instance.

Definition at line 58 of file MeSmbiosUpdateProtocol.h.

The documentation for this struct was generated from the following file:
  • MeSmbiosUpdateProtocol.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

ME_SMBIOS_TABLES_UPDATE_PROTOCOL Member List

This is the complete list of members for ME_SMBIOS_TABLES_UPDATE_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEBX_PROTOCOL Struct Reference

List of all members
MEBX_PROTOCOL Struct Reference

MEBX protocol The interface for invoking MEBX binary. More...

#include <MebxProtocol.h>

Detailed Description

MEBX protocol The interface for invoking MEBX binary.

Definition at line 109 of file MebxProtocol.h.

The documentation for this struct was generated from the following file:
  • MebxProtocol.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEBX_PROTOCOL Member List

This is the complete list of members for MEBX_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEFWCAPS_SKU Union Reference

List of all members
MEFWCAPS_SKU Union Reference

Get Firmware Capability. More...

#include <MkhiMsgs.h>

Detailed Description

Get Firmware Capability.

Definition at line 404 of file MkhiMsgs.h.

The documentation for this union was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEFWCAPS_SKU Member List

This is the complete list of members for MEFWCAPS_SKU, including all inherited members.

Amt | MEFWCAPS_SKU
DAL | MEFWCAPS_SKU
FullMng | MEFWCAPS_SKU
IntegratedTouch | MEFWCAPS_SKU
IntelCLS | MEFWCAPS_SKU
IPV6 | MEFWCAPS_SKU
ISH | MEFWCAPS_SKU
KVM | MEFWCAPS_SKU
PAVP | MEFWCAPS_SKU
PTT | MEFWCAPS_SKU
Reserved | MEFWCAPS_SKU
Reserved1 | MEFWCAPS_SKU
Reserved2 | MEFWCAPS_SKU
Reserved3 | MEFWCAPS_SKU
Reserved4 | MEFWCAPS_SKU
Reserved5 | MEFWCAPS_SKU
Reserved6 | MEFWCAPS_SKU
Reserved7 | MEFWCAPS_SKU
Reserved8 | MEFWCAPS_SKU
Reserved9 | MEFWCAPS_SKU
StdMng | MEFWCAPS_SKU
TLS | MEFWCAPS_SKU
TrustedDevice | MEFWCAPS_SKU
WLAN | MEFWCAPS_SKU
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEI_DEV_STRING Struct Reference

List of all members
MEI_DEV_STRING Struct Reference

MEI Device Structure. More...

#include <FwStsSmbiosTable.h>

Detailed Description

MEI Device Structure.

Definition at line 141 of file FwStsSmbiosTable.h.

The documentation for this struct was generated from the following file:
  • FwStsSmbiosTable.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEI_DEV_STRING Member List

This is the complete list of members for MEI_DEV_STRING, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEM_INFO_PROTOCOL Struct Reference

Public Attributes | List of all members
MEM_INFO_PROTOCOL Struct Reference

Memory information Protocol definition. More...

#include <MemInfo.h>

Collaboration diagram for MEM_INFO_PROTOCOL:
[legend]

Public Attributes

MEMORY_INFO_DATA MemInfoData
Memory Information Data Structure.

Detailed Description

Memory information Protocol definition.

Definition at line 167 of file MemInfo.h.

The documentation for this struct was generated from the following file:
  • MemInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEM_INFO_PROTOCOL Member List

This is the complete list of members for MEM_INFO_PROTOCOL, including all inherited members.

MemInfoData MEM_INFO_PROTOCOL
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEMORY_CONFIG_NO_CRC Struct Reference

Public Attributes | List of all members
MEMORY_CONFIG_NO_CRC Struct Reference

Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection. More...

#include <MemoryConfig.h>

Collaboration diagram for MEMORY_CONFIG_NO_CRC:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
SA_FUNCTION_CALLS SaCall
Offset 28 Function calls into the SA.
SA_MEMORY_FUNCTIONS MrcCall
Offset 212 Function calls into the MRC.
SPD_DATA_BUFFER * SpdData
Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
SA_MEMORY_DQDQS_MAPPING * DqDqsMap
Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
SA_MEMORY_RCOMP * RcompData
Offset 244 DDR RCOMP resistors and target values.
UINT64 | PlatformMemorySize
Offset 248 The minimum platform memory size required to pass control into DXE.
UINT32 | CleanMemory:1
Offset 256 Ask MRC to clear memory content: FALSE=Do not Clear Memory; TRUE=Clear Memory.
UINT8 | SerialDebugLevel
Sets the serial debug message level
0x00 = Disabled
0x01 = Errors only
0x02 = Errors and Warnings
0x03 = Errors, Warnings, and Info
0x04 = Errors, Warnings, Info, and Events
0x05 = Displays Memory Init Execution Time Summary only
. More...
UINT8 | MemTestOnWarmBoot
Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, 1=Enabled
UINT8 | Reserved11 [2]
Offset 262 - 263 Reserved.

Detailed Description

Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection.

Revision 1: - Initial version. Revision 2: - Added MemTestOnWarmBoot

Definition at line 558 of file MemoryConfig.h.

Member Data Documentation

◆ SerialDebugLevel

UINT8 MEMORY_CONFIG_NO_CRC::SerialDebugLevel

Sets the serial debug message level
0x00 = Disabled
0x01 = Errors only
0x02 = Errors and Warnings
0x03 = Errors, Warnings, and Info
0x04 = Errors, Warnings, Info, and Events
0x05 = Displays Memory Init Execution Time Summary only
.

Offset 260

Definition at line 577 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEMORY_CONFIG_NO_CRC Member List

This is the complete list of members for MEMORY_CONFIG_NO_CRC, including all inherited members.

CleanMemory | MEMORY_CONFIG_NO_CRC
DqDqsMap | MEMORY_CONFIG_NO_CRC
Header | MEMORY_CONFIG_NO_CRC
MemTestOnWarmBoot | MEMORY_CONFIG_NO_CRC
MrcCall | MEMORY_CONFIG_NO_CRC
PlatformMemorySize | MEMORY_CONFIG_NO_CRC
RcompData | MEMORY_CONFIG_NO_CRC
Reserved11 | MEMORY_CONFIG_NO_CRC
SaCall | MEMORY_CONFIG_NO_CRC
SerialDebugLevel | MEMORY_CONFIG_NO_CRC
SpdData | MEMORY_CONFIG_NO_CRC
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEMORY_CONFIGURATION Struct Reference

Public Attributes | List of all members
MEMORY_CONFIGURATION Struct Reference

Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection. More...

#include <MemoryConfig.h>

Collaboration diagram for MEMORY_CONFIGURATION:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT16 | Size
Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
UINT8 | HobBufferSize
Offset 30 Size of HOB buffer for MRC.
UINT8 | SpdProfileSelected
Offset 31 SPD XMP profile selection - for XMP supported DIMM: 0=Default DIMM profile, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5.
UINT16 | tCL
Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 31=Maximum.
UINT16 | tRCDtRP
Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 63=Maximum.
UINT16 | tRAS
Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 64=Maximum.
UINT16 | tWR
Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
UINT16 | tRFC
Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 1023=Maximum.
UINT16 | tRRD
Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 15=Maximum.
UINT16 | tWTR
Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRTP
Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12.
UINT16 | tFAW
Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 63=Maximum.
UINT16 | tCWL
Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 20=Maximum.
UINT16 | tREFI
Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 65535=Maximum.
UINT16 | PciIndex
Offset 54 Pci index register address: 0xCF8=Default
UINT16 | PciData
Offset 56 Pci data register address: 0xCFC=Default
UINT16 | VddVoltage
Offset 58 DRAM voltage (Vdd) in millivolts: 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
UINT16 | Idd3n
Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
UINT16 | Idd3p
Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
UINT32 | EccSupport:1
Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, 1=Enable
UINT32 | MrcSafeConfig:1
Bit 1 - MRC Safe Mode: 0=Disable, 1=Enable.
UINT32 | RemapEnable:1
Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, 1=Enable.
UINT32 | ScramblerSupport:1
Bit 3 - Memory scrambler support: 0=Disable, 1=Enable
UINT32 | Vc1ReadMeter:1
Bit 4 - VC1 Read Metering Enable: 0=Disable, 1=Enable
UINT32 | ForceSingleSubchannel:1
Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): 0=Disable, 1=Enable.
UINT32 | SimicsFlag:1
Bit 6 - Option to Enable SIMICS: 0=Disable, 1=Enable
UINT32 | Ddr4DdpSharedClock:1
Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=Not shared, 1=Shared.
UINT32 | SharedZqPin:1
Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=Not Shared, 1=Shared.
UINT32 | LpDqsOscEn:1
Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, 1=Enable
UINT32 | RmtPerTask:1
Bit 10 - Rank Margin Tool Per Task. 0 = Disabled, 1 = Enabled.
UINT32 | TrainTrace:1
Bit 11 - Trained state tracing debug. 0 = Disabled, 1 = Enabled.
UINT32 | SafeMode:1
Bit 12 - Define if safe mode is enabled for MC/IO.
UINT32 | MsHashEnable:1
Bit 13 - Controller Hash Enable: 0=Disable, 1=Enable
UINT32 | DisPgCloseIdleTimeout:1
Bit 14 - Disable Page Close Idle Timeout: 0=Enable, 1=Disable
UINT32 | Ibecc:1
Bit 15 - In-band ECC: 0=Disable, 1=Enable.
UINT32 | IbeccOperationMode:2
Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, 2=Makes all requests protected and ignore range checks
UINT32 | ChHashOverride:1
Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
UINT32 | EccDftEn:1
Bit 19 - ECC DFT support option.
UINT32 | Write0:1
Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, 1=Enable
UINT32 | ReuseAdlSDdr5Board:1
Bit 21 - Indicate whether adl ddr5 board is reused.
UINT32 | PeriodicDcc:1
Bit 22 - Periodic DCC: 0=Disable, 1=Enable.
UINT32 | LpMode:2
Bit 23:24 - LPMode: 0=Auto, 1=Enabled, 2=Disabled, 3=Reserved.
UINT32 | RsvdO64B25to31:7
Bits 25:31 reserved.
UINT8 | DisableChannel [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]
Offset 68-75.
UINT8 | Ratio
Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. 0 = Auto
UINT8 | ProbelessTrace
Offset 77 Probeless Trace: 0=Disabled, 1=Enabled
UINT8 | ChHashInterleaveBit
Channel Hash Enable. More...
UINT8 | SmramMask
Offset 79 Reserved memory ranges for SMRAM.
UINT32 | BClkFrequency
Offset 80 Base reference clock value, in Hertz: 100000000 = 100Hz, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz.
UINT32 | ECT:1
Training Algorithms 1 Offset 84. More...
UINT32 | SOT:1
Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | ERDMPRTC2D:1
Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDMPRT:1
Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RCVET:1
Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | JWRL:1
Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | EWRTC2D:1
Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | ERDTC2D:1
Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRTC1D:1
Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRVC1D:1
Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDTC1D:1
Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMODTT:1
Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMRONT:1
Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRDSEQT:1
Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRSRT:1
Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDODTT:1
Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDEQT:1
Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDAPT:1
Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRTC2D:1
Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDTC2D:1
Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRVC2D:1
Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RDVC2D:1
Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | CMDVC:1
Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, 1=Enable.
UINT32 | LCT:1
Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RTL:1
Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | TAT:1
Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RMT:1
Bit 26 - Enable/Disable Rank Margin Tool function: 0=Disable, 1=Enable.
UINT32 | MEMTST:1
Bit 27 - Enable/Disable Memory Test function: 0=Disable, 1=Enable.
UINT32 | ALIASCHK:1
Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, 1=Enable
UINT32 | RCVENC1D:1
Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | RMC:1
Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | WRDSUDT:1
Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. More...
UINT32 | DCC: 1
Training Algorithms 2 Offset 88. More...
UINT32 | RDVC1D: 1
Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
UINT32 | TXTCO: 1
Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
UINT32 | CLKTCO: 1
Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
UINT32 | CMDSR: 1
Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
UINT32 | CMDDSEQ: 1
Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
UINT32 | DIMMODTCA: 1
Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
UINT32 | TXTCODQS: 1
Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
UINT32 | CMDDRUD: 1
Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
UINT32 | VCCDLLBP: 1
Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
UINT32 | PVTTDNLP: 1
Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
UINT32 | RDVREFDC: 1
Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
UINT32 | VDDQT: 1
Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
UINT32 | RMTBIT: 1
Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
UINT32 | PDA: 1
BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.
UINT32 | DIMMDFE: 1
BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, 1=Enable.
UINT32 | TXDQSDCC: 1
BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, 1=Enable.
UINT32 | DRAMDCA: 1
BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, 1=Enable.
UINT32 | WRDS: 1
BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, 1=Enable.
UINT32 | ReservedBits2:13
Bits 19:31 - Reserved.
UINT32 | MrcTimeMeasure:1
Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: 0=Disable, 1=Enable.
UINT32 | MrcFastBoot:1
Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, 1=Enable
UINT32 | DqPinsInterleaved:1
Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: 0=Disable, 1=Enable.
UINT32 | RankInterleave:1
Bit 3 - Rank Interleave Mode: 0=Disable, 1=Enable
UINT32 | EnhancedInterleave:1
Bit 4 - Enhanced Interleave Mode: 0=Disable, 1=Enable
UINT32 | WeaklockEn:1
Bit 5 - Weak Lock Enable: 0=Disable, 1=Enable
UINT32 | ChHashEnable:1
Bit 6 - Channel Hash Enable: 0=Disable, 1=Enable
UINT32 | EnablePwrDn:1
Bit 7 - Enable Power Down control for DDR: 0=PCODE control, 1=BIOS control
UINT32 | EnablePwrDnLpddr:1
Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, 1=BIOS control
UINT32 | SrefCfgEna:1
Bit 9 - Enable Self Refresh: 0=Disable, 1=Enable
UINT32 | ThrtCkeMinDefeatLpddr:1
Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, 1=Enable
UINT32 | ThrtCkeMinDefeat:1
Bit 11 - Throttler CKE min defeature: 0=Disable, 1=Enable.
UINT32 | AutoSelfRefreshSupport:1
Bit 12 - FALSE = No auto self refresh support, TRUE = auto self refresh support
UINT32 | ExtTemperatureSupport:1
Bit 13 - FALSE = No extended temperature support, TRUE = extended temperature support
UINT32 | MobilePlatform:1
Bit 14 - Memory controller device id indicates: TRUE if mobile, FALSE if not. Note: This will be auto-detected and updated.
UINT32 | Force1Dpc:1
Bit 15 - TRUE means force one DIMM per channel, FALSE means no limit
UINT32 | ForceSingleRank:1
Bit 16 - TRUE means use Rank0 only (in each DIMM): 0=Disable, 1=Enable.
UINT32 | VttTermination:1
Bit 17 - Vtt Termination for Data ODT: 0=Disable, 1=Enable.
UINT32 | VttCompForVsshi:1
Bit 18 - Enable/Disable Vtt Comparator For Vsshi: 0=Disable, 1=Enable.
UINT32 | ExitOnFailure:1
Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, 1=Enable
UINT32 | NewFeatureEnable1:1
Bit 20 - Generic enable knob for new feature set 1 0: Disable ; 1: Enable.
UINT32 | NewFeatureEnable2:1
Bit 21 - Generic enable knob for new feature set 2 0: Disable ; 1: Enable.
UINT32 | RhSelect:2
Bit 22-23 - RH Select: 0=Disable, 1=RFM, 2=pTRR.
UINT32 | RefreshPanicWm:4
Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
UINT32 | RefreshHpWm:4
Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
UINT32 | VddSettleWaitTime
Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: Default=0
UINT16 | SrefCfgIdleTmr
Offset 100 Self Refresh idle timer: 512=Minimal, 65535=Maximum.
UINT16 | ChHashMask
Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), 0x30CE= BIT[19:18, 13:12 ,9:7] set
UINT16 | DdrFreqLimit
Offset 104 Memory Frequency limit: 0 = Auto, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h.
UINT8 | MaxRttWr
Offset 106 Maximum DIMM RTT_WR to use in power training: 0=ODT Off, 1 = 120 ohms.
UINT8 | ThrtCkeMinTmr
Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, 0x00=Default
UINT8 | ThrtCkeMinTmrLpddr
Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default
BOOLEAN | PerBankRefresh
Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, TRUE=Enabled
UINT8 | SaGv
Offset 110 SA GV: 0=Disabled, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled.
UINT8 | NModeSupport
Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: 0=AUTO, 1=1N, 2=2N.
UINT8 | RefClk
Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, 0x00 = 133MHz
UINT8 | EnCmdRate
Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, 7=3 CMDs, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs.
UINT8 | Refresh2X
Offset 114 Refresh 2x: 0=Disable, 1=Enable for WARM or HOT, 2=Enable for HOT only.
UINT8 | EpgEnable
Offset 115 Enable Energy Performance Gain.
UINT8 | UserThresholdEnable
Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, 0=Default
UINT8 | UserBudgetEnable
Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, 0=Default
UINT8 | RetrainOnFastFail
Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, 1 = Enabled
UINT8 | PowerDownMode
Offset 119 CKE Power Down Mode: 0xFF=AUTO, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode.
UINT8 | PwdwnIdleCounter
Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, 0x80=0x80 DCLK
UINT8 | CmdRanksTerminated
Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating
UINT16 | MsHashMask
Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), 0x30CE= BIT[19:18, 13:12 ,9:7] set
UINT32 | Lp5CccConfig
Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
UINT8 | RMTLoopCount
Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, 0=Default
UINT8 | MsHashInterleaveBit
Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9.
UINT8 | GearRatio
Offset 130 Gear mode when SAGV is disabled: 0=Auto, 1 - Gear1, 2 - Gear2, 4 - Gear4.
UINT8 | Ddr4OneDpc
Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
UINT32 | BclkRfiFreq [MEM_MAX_SAGV_POINTS]
Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz 0 - No RFI Tuning. Range is 98Mhz-100Mhz.
UINT16 | SaGvFreq [MEM_MAX_SAGV_POINTS]
Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: 0=Default, 1067, 1333, 1600, 1800, 1867, etc.
UINT8 | SaGvGear [MEM_MAX_SAGV_POINTS]
Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: 0=Auto, 1, 2, 4.
UINT8 | IbeccProtectedRangeEnable [MEM_MAX_IBECC_REGIONS]
Offset 160 Enable use of address range for ECC Protection: 0=Disabled, 1=Enabled.
UINT32 | IbeccProtectedRangeBase [MEM_MAX_IBECC_REGIONS]
Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF].
UINT32 | IbeccProtectedRangeMask [MEM_MAX_IBECC_REGIONS]
Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF].
UINT8 | McRefresh2X
Offset 232 Deprecated from revision 19, use McRefreshRate instead.
UINT8 | Lfsr0Mask
Offset 233 RH pTRR LFSR0 Mask.
UINT8 | Lfsr1Mask
Offset 234 RH pTRR LFSR1 Mask.
UINT8 | CmdMirror
Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
UINT8 | AllowOppRefBelowWriteThrehold
Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
UINT8 | WriteThreshold
Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
UINT8 | PprEnable
Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR.
UINT8 | MarginLimitCheck
Offset 239 Margin limit check enable: 0=Disable, 1=L1 only, 2=L2 only, 3=Both L1 and L2.
UINT16 | MarginLimitL2
Offset 240 Margin limit check L2 threshold: 100=Default
UINT8 | LpddrRttWr
Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto.
UINT8 | LpddrRttCa
Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto.
UINT16 | VddqVoltage
Offset 244 DRAM voltage (Vddq) in millivolts: 0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
UINT16 | VppVoltage
Offset 246 DRAM voltage (Vpp) in millivolts: 0=Platform Default (no override), 1800=1.8V, 2050=2.05V etc.
UINT8 | ExtendedBankHashing
Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; 1 = Enabled
UINT8 | DynamicMemoryBoost
Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled.
UINT8 | IbeccErrInjControl
Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter.
UINT8 | RealtimeMemoryFrequency
Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. 0=Disabled, 1=Enabled.
UINT32 | IbeccErrInjCount
Offset 252 Number of transactions between ECC error injection.
UINT64 | IbeccErrInjAddress
Offset 256 Address to match against for ECC error injection.
UINT64 | IbeccErrInjMask
Offset 264 Mask to match against for ECC error injection.
UINT8 | RefreshWm
Offset 272 Refresh Watermarks, 0 = Low, 1 = High
UINT8 | McRefreshRate
Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x.
UINT8 | Reserved274 [2]
Offset 274-275 Reserved for natural alignment.
UINT32 | DebugValue
Offset 276 Debug Value for general use.
UINT16 | tRFCpb
Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRFC2
Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRFC4
Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRRD_L
Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tRRD_S
Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tWTR_L
Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tCCD_L
Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT16 | tWTR_S
Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AUTO, 28=Maximum.
UINT64 | EccErrInjAddress
Offset 296 Address to match against for ECC error injection.
UINT64 | EccErrInjMask
Offset 304 Mask to match against for ECC error injection.
UINT32 | EccErrInjCount
Offset 312 Number of transactions between ECC error injection.
UINT16 | FreqLimitMixedConfig
Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. 0=Auto, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h.
UINT8 | FirstDimmBitMask
Offset 318 Defines which DIMM should be populated first on a 2DPC board. More...
UINT8 | UserBd
Offset 319 MrcBoardType 1 - Desktop 1DPC 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order 5 - ULT Mobile.
UINT8 | SagvSwitchFactorIA
Offset 320 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorGT
Offset 321 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorIO
Offset 322 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvSwitchFactorStall
Offset 323 Sagv Switch Factor: 1 , 50=Maximum, default 30.
UINT8 | SagvHeuristicsUpControl
Offset 324 Sagv duration in ms before heuristics up: 1 , 50=Maximum, default 1ms.
UINT8 | SagvHeuristicsDownControl
Offset 325 Sagv duration in ms before heuristics down: 1 , 50=Maximum, default 1ms.
UINT16 | FreqLimitMixedConfig_1R1R_8GB
Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel). More...
UINT16 | FreqLimitMixedConfig_1R1R_16GB
Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel). More...
UINT16 | FreqLimitMixedConfig_1R1R_8GB_16GB
Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel). More...
UINT16 | FreqLimitMixedConfig_2R2R
Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel). More...
UINT16 | LctCmdEyeWidth
Offset 334 LCT Command eyewidth.
UINT8 | FirstDimmBitMaskEcc
Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board. More...
UINT8 | Lp5BankMode
Offset 337 LP5 Bank Mode.
UINT8 | Reserved336 [6]
Offset 338-343 Reserved for natural alignment.

Detailed Description

Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection.

This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure. Revision history is at the top of this file

Definition at line 307 of file MemoryConfig.h.

Member Data Documentation

◆ ChHashInterleaveBit

UINT8 MEMORY_CONFIGURATION::ChHashInterleaveBit

Channel Hash Enable.

NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8
0=BIT6, 1=BIT7, 2=BIT8, 3=BIT9 Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)

Definition at line 364 of file MemoryConfig.h.

◆ DCC

UINT32 MEMORY_CONFIGURATION::DCC

Training Algorithms 2 Offset 88.

Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.

Definition at line 402 of file MemoryConfig.h.

◆ ECT

UINT32 MEMORY_CONFIGURATION::ECT

Training Algorithms 1 Offset 84.

Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable.

Definition at line 369 of file MemoryConfig.h.

◆ FirstDimmBitMask

UINT8 MEMORY_CONFIGURATION::FirstDimmBitMask

Offset 318 Defines which DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. Note: this mask is only for non-ECC DIMM.

Definition at line 519 of file MemoryConfig.h.

◆ FirstDimmBitMaskEcc

UINT8 MEMORY_CONFIGURATION::FirstDimmBitMaskEcc

Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be be populated firstly. Note: this mask is only for ECC DIMM, not for non-ECC DIMM.

Definition at line 544 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_16GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_16GB

Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 537 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_8GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB

Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 535 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_1R1R_8GB_16GB

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB_16GB

Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 539 of file MemoryConfig.h.

◆ FreqLimitMixedConfig_2R2R

UINT16 MEMORY_CONFIGURATION::FreqLimitMixedConfig_2R2R

Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).

It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.

Definition at line 541 of file MemoryConfig.h.

◆ WRDSUDT

UINT32 MEMORY_CONFIGURATION::WRDSUDT

Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently.

Note it is not recommended to change this setting from the default value: 0=Disable, 1=Enable

Definition at line 400 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEMORY_CONFIGURATION Member List

This is the complete list of members for MEMORY_CONFIGURATION, including all inherited members.

ALIASCHK | MEMORY_CONFIGURATION
AllowOppRefBelowWriteThrehold | MEMORY_CONFIGURATION
AutoSelfRefreshSupport | MEMORY_CONFIGURATION
BClkFrequency | MEMORY_CONFIGURATION
BclkRfiFreq | MEMORY_CONFIGURATION
ChHashEnable | MEMORY_CONFIGURATION
ChHashInterleaveBit | MEMORY_CONFIGURATION
ChHashMask | MEMORY_CONFIGURATION
ChHashOverride | MEMORY_CONFIGURATION
CLKTCO | MEMORY_CONFIGURATION
CMDDRUD | MEMORY_CONFIGURATION
CMDDSEQ | MEMORY_CONFIGURATION
CmdMirror | MEMORY_CONFIGURATION
CmdRanksTerminated | MEMORY_CONFIGURATION
CMDSR | MEMORY_CONFIGURATION
CMDVC | MEMORY_CONFIGURATION
DCC | MEMORY_CONFIGURATION
Ddr4DdpSharedClock | MEMORY_CONFIGURATION
Ddr4OneDpc | MEMORY_CONFIGURATION
DdrFreqLimit | MEMORY_CONFIGURATION
DebugValue | MEMORY_CONFIGURATION
DIMMDFE | MEMORY_CONFIGURATION
DIMMODTCA | MEMORY_CONFIGURATION
DIMMODTT | MEMORY_CONFIGURATION
DIMMRONT | MEMORY_CONFIGURATION
DisableChannel | MEMORY_CONFIGURATION
DisPgCloseIdleTimeout | MEMORY_CONFIGURATION
DqPinsInterleaved | MEMORY_CONFIGURATION
DRAMDCA | MEMORY_CONFIGURATION
DynamicMemoryBoost | MEMORY_CONFIGURATION
EccDftEn | MEMORY_CONFIGURATION
EccErrInjAddress | MEMORY_CONFIGURATION
EccErrInjCount | MEMORY_CONFIGURATION
EccErrInjMask | MEMORY_CONFIGURATION
EccSupport | MEMORY_CONFIGURATION
ECT | MEMORY_CONFIGURATION
EnablePwrDn | MEMORY_CONFIGURATION
EnablePwrDnLpddr | MEMORY_CONFIGURATION
EnCmdRate | MEMORY_CONFIGURATION
EnhancedInterleave | MEMORY_CONFIGURATION
EpgEnable | MEMORY_CONFIGURATION
ERDMPRTC2D | MEMORY_CONFIGURATION
ERDTC2D | MEMORY_CONFIGURATION
EWRTC2D | MEMORY_CONFIGURATION
ExitOnFailure | MEMORY_CONFIGURATION
ExtendedBankHashing | MEMORY_CONFIGURATION
ExtTemperatureSupport | MEMORY_CONFIGURATION
FirstDimmBitMask | MEMORY_CONFIGURATION
FirstDimmBitMaskEcc | MEMORY_CONFIGURATION
Force1Dpc | MEMORY_CONFIGURATION
ForceSingleRank | MEMORY_CONFIGURATION
ForceSingleSubchannel | MEMORY_CONFIGURATION
FreqLimitMixedConfig | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_16GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_8GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_1R1R_8GB_16GB | MEMORY_CONFIGURATION
FreqLimitMixedConfig_2R2R | MEMORY_CONFIGURATION
GearRatio | MEMORY_CONFIGURATION
Header | MEMORY_CONFIGURATION
HobBufferSize | MEMORY_CONFIGURATION
Ibecc | MEMORY_CONFIGURATION
IbeccErrInjAddress | MEMORY_CONFIGURATION
IbeccErrInjControl | MEMORY_CONFIGURATION
IbeccErrInjCount | MEMORY_CONFIGURATION
IbeccErrInjMask | MEMORY_CONFIGURATION
IbeccOperationMode | MEMORY_CONFIGURATION
IbeccProtectedRangeBase | MEMORY_CONFIGURATION
IbeccProtectedRangeEnable | MEMORY_CONFIGURATION
IbeccProtectedRangeMask | MEMORY_CONFIGURATION
Idd3n | MEMORY_CONFIGURATION
Idd3p | MEMORY_CONFIGURATION
JWRL | MEMORY_CONFIGURATION
LCT | MEMORY_CONFIGURATION
LctCmdEyeWidth | MEMORY_CONFIGURATION
Lfsr0Mask | MEMORY_CONFIGURATION
Lfsr1Mask | MEMORY_CONFIGURATION
Lp5BankMode | MEMORY_CONFIGURATION
Lp5CccConfig | MEMORY_CONFIGURATION
LpddrRttCa | MEMORY_CONFIGURATION
LpddrRttWr | MEMORY_CONFIGURATION
LpDqsOscEn | MEMORY_CONFIGURATION
LpMode | MEMORY_CONFIGURATION
MarginLimitCheck | MEMORY_CONFIGURATION
MarginLimitL2 | MEMORY_CONFIGURATION
MaxRttWr | MEMORY_CONFIGURATION
McRefresh2X | MEMORY_CONFIGURATION
McRefreshRate | MEMORY_CONFIGURATION
MEMTST | MEMORY_CONFIGURATION
MobilePlatform | MEMORY_CONFIGURATION
MrcFastBoot | MEMORY_CONFIGURATION
MrcSafeConfig | MEMORY_CONFIGURATION
MrcTimeMeasure | MEMORY_CONFIGURATION
MsHashEnable | MEMORY_CONFIGURATION
MsHashInterleaveBit | MEMORY_CONFIGURATION
MsHashMask | MEMORY_CONFIGURATION
NewFeatureEnable1 | MEMORY_CONFIGURATION
NewFeatureEnable2 | MEMORY_CONFIGURATION
NModeSupport | MEMORY_CONFIGURATION
PciData | MEMORY_CONFIGURATION
PciIndex | MEMORY_CONFIGURATION
PDA | MEMORY_CONFIGURATION
PerBankRefresh | MEMORY_CONFIGURATION
PeriodicDcc | MEMORY_CONFIGURATION
PowerDownMode | MEMORY_CONFIGURATION
PprEnable | MEMORY_CONFIGURATION
ProbelessTrace | MEMORY_CONFIGURATION
PVTTDNLP | MEMORY_CONFIGURATION
PwdwnIdleCounter | MEMORY_CONFIGURATION
RankInterleave | MEMORY_CONFIGURATION
Ratio | MEMORY_CONFIGURATION
RCVENC1D | MEMORY_CONFIGURATION
RCVET | MEMORY_CONFIGURATION
RDAPT | MEMORY_CONFIGURATION
RDEQT | MEMORY_CONFIGURATION
RDMPRT | MEMORY_CONFIGURATION
RDODTT | MEMORY_CONFIGURATION
RDTC1D | MEMORY_CONFIGURATION
RDTC2D | MEMORY_CONFIGURATION
RDVC1D | MEMORY_CONFIGURATION
RDVC2D | MEMORY_CONFIGURATION
RDVREFDC | MEMORY_CONFIGURATION
RealtimeMemoryFrequency | MEMORY_CONFIGURATION
RefClk | MEMORY_CONFIGURATION
Refresh2X | MEMORY_CONFIGURATION
RefreshHpWm | MEMORY_CONFIGURATION
RefreshPanicWm | MEMORY_CONFIGURATION
RefreshWm | MEMORY_CONFIGURATION
RemapEnable | MEMORY_CONFIGURATION
Reserved274 | MEMORY_CONFIGURATION
Reserved336 | MEMORY_CONFIGURATION
ReservedBits2 | MEMORY_CONFIGURATION
RetrainOnFastFail | MEMORY_CONFIGURATION
ReuseAdlSDdr5Board | MEMORY_CONFIGURATION
RhSelect | MEMORY_CONFIGURATION
RMC | MEMORY_CONFIGURATION
RMT | MEMORY_CONFIGURATION
RMTBIT | MEMORY_CONFIGURATION
RMTLoopCount | MEMORY_CONFIGURATION
RmtPerTask | MEMORY_CONFIGURATION
RsvdO64B25to31 | MEMORY_CONFIGURATION
RTL | MEMORY_CONFIGURATION
SafeMode | MEMORY_CONFIGURATION
SaGv | MEMORY_CONFIGURATION
SaGvFreq | MEMORY_CONFIGURATION
SaGvGear | MEMORY_CONFIGURATION
SagvHeuristicsDownControl | MEMORY_CONFIGURATION
SagvHeuristicsUpControl | MEMORY_CONFIGURATION
SagvSwitchFactorGT | MEMORY_CONFIGURATION
SagvSwitchFactorIA | MEMORY_CONFIGURATION
SagvSwitchFactorIO | MEMORY_CONFIGURATION
SagvSwitchFactorStall | MEMORY_CONFIGURATION
ScramblerSupport | MEMORY_CONFIGURATION
SharedZqPin | MEMORY_CONFIGURATION
SimicsFlag | MEMORY_CONFIGURATION
Size | MEMORY_CONFIGURATION
SmramMask | MEMORY_CONFIGURATION
SOT | MEMORY_CONFIGURATION
SpdProfileSelected | MEMORY_CONFIGURATION
SrefCfgEna | MEMORY_CONFIGURATION
SrefCfgIdleTmr | MEMORY_CONFIGURATION
TAT | MEMORY_CONFIGURATION
tCCD_L | MEMORY_CONFIGURATION
tCL | MEMORY_CONFIGURATION
tCWL | MEMORY_CONFIGURATION
tFAW | MEMORY_CONFIGURATION
ThrtCkeMinDefeat | MEMORY_CONFIGURATION
ThrtCkeMinDefeatLpddr | MEMORY_CONFIGURATION
ThrtCkeMinTmr | MEMORY_CONFIGURATION
ThrtCkeMinTmrLpddr | MEMORY_CONFIGURATION
TrainTrace | MEMORY_CONFIGURATION
tRAS | MEMORY_CONFIGURATION
tRCDtRP | MEMORY_CONFIGURATION
tREFI | MEMORY_CONFIGURATION
tRFC | MEMORY_CONFIGURATION
tRFC2 | MEMORY_CONFIGURATION
tRFC4 | MEMORY_CONFIGURATION
tRFCpb | MEMORY_CONFIGURATION
tRRD | MEMORY_CONFIGURATION
tRRD_L | MEMORY_CONFIGURATION
tRRD_S | MEMORY_CONFIGURATION
tRTP | MEMORY_CONFIGURATION
tWR | MEMORY_CONFIGURATION
tWTR | MEMORY_CONFIGURATION
tWTR_L | MEMORY_CONFIGURATION
tWTR_S | MEMORY_CONFIGURATION
TXDQSDCC | MEMORY_CONFIGURATION
TXTCO | MEMORY_CONFIGURATION
TXTCODQS | MEMORY_CONFIGURATION
UserBd | MEMORY_CONFIGURATION
UserBudgetEnable | MEMORY_CONFIGURATION
UserThresholdEnable | MEMORY_CONFIGURATION
Vc1ReadMeter | MEMORY_CONFIGURATION
VCCDLLBP | MEMORY_CONFIGURATION
VDDQT | MEMORY_CONFIGURATION
VddqVoltage | MEMORY_CONFIGURATION
VddSettleWaitTime | MEMORY_CONFIGURATION
VddVoltage | MEMORY_CONFIGURATION
VppVoltage | MEMORY_CONFIGURATION
VttCompForVsshi | MEMORY_CONFIGURATION
VttTermination | MEMORY_CONFIGURATION
WeaklockEn | MEMORY_CONFIGURATION
WRDS | MEMORY_CONFIGURATION
WRDSEQT | MEMORY_CONFIGURATION
WRDSUDT | MEMORY_CONFIGURATION
Write0 | MEMORY_CONFIGURATION
WriteThreshold | MEMORY_CONFIGURATION
WRSRT | MEMORY_CONFIGURATION
WRTC1D | MEMORY_CONFIGURATION
WRTC2D | MEMORY_CONFIGURATION
WRVC1D | MEMORY_CONFIGURATION
WRVC2D | MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEMORY_INFO_DATA Struct Reference

Public Attributes | List of all members
MEMORY_INFO_DATA Struct Reference

Memory information Data Structure. More...

#include <MemInfo.h>

Collaboration diagram for MEMORY_INFO_DATA:
[legend]

Public Attributes

MEMORY_TIMING | Timing [PROFILE_NUM]
Offset 0 Timming information for the DIMM.
UINT32 | memSize
Offset 128 Total physical memory size.
UINT16 | ddrFreq
Offset 132 DDR Current Frequency.
UINT16 | ddrFreqMax
Offset 134 DDR Maximum Frequency.
UINT16 | dimmSize [NODE_NUM *CH_NUM *DIMM_NUM]
Offset 136 Size of each DIMM.
UINT16 | VddVoltage [PROFILE_NUM]
Offset 144(ICL)/168(TGL) The voltage setting for the DIMM.
UINT8 | DimmStatus [NODE_NUM *CH_NUM *DIMM_NUM]
Offset 152(ICL)/176(TGL) The enumeration value from MrcDimmSts.
UINT8 | RankInDimm [NODE_NUM *CH_NUM *DIMM_NUM]
Offset 156(ICL)/192(TGL) No. of ranks in a dimm.
UINT8 * | DimmsSpdData [NODE_NUM *CH_NUM *DIMM_NUM]
Offset 160(ICL)/208(TGL) SPD data of each DIMM.
UINT8 | RefClk
Offset 192(ICL)/336(TGL) Reference Clock.
UINT8 | Ratio
Offset 193(ICL)/337(TGL) Clock Multiplier.
BOOLEAN | EccSupport
Offset 194(ICL)/338(TGL) ECC supported or not.
UINT8 | Profile
Offset 195(ICL)/339(TGL) Currently running memory profile.
UINT8 | XmpProfileEnable
Offset 196(ICL)/340(TGL): Capability status. 0 is none supported. Bit 0: XMP 1, Bit 1: XMP 2, Bit 2: XMP 3, Bit 3: User 4, Bit 4: User 5.
UINT8 | DdrType
Offset 197(ICL)/341(TGL): Current DDR type, see DDR_TYPE_xxx defines above.
UINT16 | Ratio_UINT16
Offset 198(ICL)/342(TGL) Clock Multiplier UINT16.
UINT16 | VddqVoltage [PROFILE_NUM]
Offset 200(ICL)/344(TGL) The voltage setting for the DIMM.
UINT16 | VppVoltage [PROFILE_NUM]
Offset 208(ICL)/352(TGL) The voltage setting for the DIMM.
BOOLEAN | XmpConfigWarning
Offset 216(ICL)/360(TGL) XMP Dimm Config Warning - 1DPC capable but 2DPC is installed.
UINT8 | IsDMBRunning
Offset 217(ICL)/361(TGL) Deprecated.
BOOLEAN | MemorySpeedReducedWrongDimmSlot
Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population.
BOOLEAN | DynamicMemoryBoostTrainingFailed
TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.

Detailed Description

Memory information Data Structure.

Definition at line 138 of file MemInfo.h.

The documentation for this struct was generated from the following file:
  • MemInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEMORY_INFO_DATA Member List

This is the complete list of members for MEMORY_INFO_DATA, including all inherited members.

ddrFreq | MEMORY_INFO_DATA
ddrFreqMax | MEMORY_INFO_DATA
DdrType | MEMORY_INFO_DATA
dimmSize | MEMORY_INFO_DATA
DimmsSpdData | MEMORY_INFO_DATA
DimmStatus | MEMORY_INFO_DATA
DynamicMemoryBoostTrainingFailed | MEMORY_INFO_DATA
EccSupport | MEMORY_INFO_DATA
IsDMBRunning | MEMORY_INFO_DATA
MemorySpeedReducedWrongDimmSlot | MEMORY_INFO_DATA
memSize | MEMORY_INFO_DATA
Profile | MEMORY_INFO_DATA
RankInDimm | MEMORY_INFO_DATA
Ratio | MEMORY_INFO_DATA
Ratio_UINT16 | MEMORY_INFO_DATA
RefClk | MEMORY_INFO_DATA
Timing | MEMORY_INFO_DATA
VddqVoltage | MEMORY_INFO_DATA
VddVoltage | MEMORY_INFO_DATA
VppVoltage | MEMORY_INFO_DATA
XmpConfigWarning | MEMORY_INFO_DATA
XmpProfileEnable | MEMORY_INFO_DATA
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEMORY_PLATFORM_DATA Struct Reference

List of all members
MEMORY_PLATFORM_DATA Struct Reference

Memory Platform Data Hob. More...

#include <MemInfoHob.h>

Detailed Description

Memory Platform Data Hob.

Revision 1:

  • Initial version. Revision 2:
  • Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields

Definition at line 315 of file MemInfoHob.h.

The documentation for this struct was generated from the following file:
  • MemInfoHob.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEMORY_PLATFORM_DATA Member List

This is the complete list of members for MEMORY_PLATFORM_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MEMORY_TIMING Struct Reference

Public Attributes | List of all members
MEMORY_TIMING Struct Reference

Memory timing Structure. More...

#include <MemInfo.h>

Public Attributes

UINT32 | tCK
Offset 0 Memory cycle time, in femtoseconds.
UINT16 | NMode
Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
UINT16 | tCL
Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
UINT16 | tCWL
Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
UINT16 | tFAW
Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
UINT16 | tRAS
Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
UINT16 | tRCDtRP
Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
UINT16 | tREFI
Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
UINT16 | tRFC
Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 | tRFCpb
Offset 20 Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
UINT16 | tRFC2
Offset 22 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 | tRFC4
Offset 24 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
UINT16 | tRPab
Offset 26 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
UINT16 | tRRD
Offset 28 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
UINT16 | tRRD_L
Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
UINT16 | tRRD_S
Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
UINT16 | tRTP
Offset 34 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
UINT16 | tWR
Offset 36 Number of tCK cycles for the channel DIMM's minimum write recovery time.
UINT16 | tWTR
Offset 38 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
UINT16 | tWTR_L
Offset 40 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
UINT16 | tWTR_S
Offset 42 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
UINT16 | tCCD_L
Offset 44 Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
UINT8 | Rsvd [2]
Offset 46.

Detailed Description

Memory timing Structure.

Definition at line 108 of file MemInfo.h.

The documentation for this struct was generated from the following file:
  • MemInfo.h
Generated on Wed Jan 5 2022 01:24:04 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MEMORY_TIMING Member List

This is the complete list of members for MEMORY_TIMING, including all inherited members.

NMode | MEMORY_TIMING
Rsvd | MEMORY_TIMING
tCCD_L | MEMORY_TIMING
tCK | MEMORY_TIMING
tCL | MEMORY_TIMING
tCWL | MEMORY_TIMING
tFAW | MEMORY_TIMING
tRAS | MEMORY_TIMING
tRCDtRP | MEMORY_TIMING
tREFI | MEMORY_TIMING
tRFC | MEMORY_TIMING
tRFC2 | MEMORY_TIMING
tRFC4 | MEMORY_TIMING
tRFCpb | MEMORY_TIMING
tRPab | MEMORY_TIMING
tRRD | MEMORY_TIMING
tRRD_L | MEMORY_TIMING
tRRD_S | MEMORY_TIMING
tRTP | MEMORY_TIMING
tWR | MEMORY_TIMING
tWTR | MEMORY_TIMING
tWTR_L | MEMORY_TIMING
tWTR_S | MEMORY_TIMING
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MG_IMR_STATUS Union Reference

List of all members
MG_IMR_STATUS Union Reference

Structure for MG image status from IMR. More...

#include <TcssDataHob.h>

Detailed Description

Structure for MG image status from IMR.

Definition at line 84 of file TcssDataHob.h.

The documentation for this union was generated from the following file:
  • TcssDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MG_IMR_STATUS Member List

This is the complete list of members for MG_IMR_STATUS, including all inherited members.

Done | MG_IMR_STATUS
ErrorCode | MG_IMR_STATUS
MgFwVersion | MG_IMR_STATUS
Reserved | MG_IMR_STATUS
Valid | MG_IMR_STATUS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MKHI_MESSAGE_HEADER Union Reference

List of all members
MKHI_MESSAGE_HEADER Union Reference

MKHI host message header. More...

#include <MkhiMsgs.h>

Detailed Description

MKHI host message header.

This header is part of HECI message sent from MEBx via Host Configuration Interface (HCI). ME Configuration Manager or Power Configuration Manager also include this header with appropriate fields set as part of the response message to the HCI.

Definition at line 46 of file MkhiMsgs.h.

The documentation for this union was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MKHI_MESSAGE_HEADER Member List

This is the complete list of members for MKHI_MESSAGE_HEADER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MSR_TURBO_RATIO_LIMIT_REGISTER Union Reference

Public Attributes | List of all members
MSR_TURBO_RATIO_LIMIT_REGISTER Union Reference

MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT. More...

#include <CpuRegs.h>

Public Attributes

struct {
UINT32 MaxTurbo1Core:8
[Bits 7:0] Package. More...
UINT32 MaxTurbo2Core:8
[Bits 15:8] Package. More...
UINT32 MaxTurbo3Core:8
[Bits 23:16] Package. More...
UINT32 MaxTurbo4Core:8
[Bits 31:24] Package. More...
UINT32 MaxTurbo5Core:8
[Bits 39:32] Package. More...
UINT32 MaxTurbo6Core:8
[Bits 47:40] Package. More...
UINT32 MaxTurbo7Core:8
[Bits 55:48] Package. More...
UINT32 MaxTurbo8Core:8
[Bits 63:56] Package. More...
} Bits
Individual bit fields.
UINT64 Uint64
All bit fields as a 64-bit value.

Detailed Description

MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT.

Definition at line 74 of file CpuRegs.h.

Member Data Documentation

◆ MaxTurbo1Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo1Core

[Bits 7:0] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 1Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 1Core threshold.

Definition at line 84 of file CpuRegs.h.

◆ MaxTurbo2Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo2Core

[Bits 15:8] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 2Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 2Core threshold and greater than MaxTurbo 1Core threshold.

Definition at line 90 of file CpuRegs.h.

◆ MaxTurbo3Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo3Core

[Bits 23:16] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 3Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 3Core threshold and greater than MaxTurbo 2Core threshold.

Definition at line 96 of file CpuRegs.h.

◆ MaxTurbo4Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo4Core

[Bits 31:24] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 4Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 4Core threshold and greater than MaxTurbo 3Core threshold.

Definition at line 102 of file CpuRegs.h.

◆ MaxTurbo5Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo5Core

[Bits 39:32] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 5Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 5Core and greater than MaxTurbo 4Core threshold.

Definition at line 108 of file CpuRegs.h.

◆ MaxTurbo6Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo6Core

[Bits 47:40] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 6Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 6Core threshold and greater than MaxTurbo 5Core threshold.

Definition at line 114 of file CpuRegs.h.

◆ MaxTurbo7Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo7Core

[Bits 55:48] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 7Core Maximum turbo ratio limit when number of active cores is less or equal to Group 7 threshold and greater than MaxTurbo 6Core threshold.

Definition at line 120 of file CpuRegs.h.

◆ MaxTurbo8Core

UINT32 MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo8Core

[Bits 63:56] Package.

Maximum Ratio Limit for Active cores in MaxTurbo 8Core Maximum turbo ratio limit when number of active cores is less or equal to MaxTurbo 8Core threshold and greater than MaxTurbo 7Core threshold.

Definition at line 126 of file CpuRegs.h.

The documentation for this union was generated from the following file:
  • CpuRegs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MSR_TURBO_RATIO_LIMIT_REGISTER Member List

This is the complete list of members for MSR_TURBO_RATIO_LIMIT_REGISTER, including all inherited members.

Bits | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo1Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo2Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo3Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo4Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo5Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo6Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo7Core | MSR_TURBO_RATIO_LIMIT_REGISTER
MaxTurbo8Core | MSR_TURBO_RATIO_LIMIT_REGISTER
Uint64 | MSR_TURBO_RATIO_LIMIT_REGISTER
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MUX_GPIO_PARAM Struct Reference

Public Attributes | List of all members
MUX_GPIO_PARAM Struct Reference

SD GPIO settings. More...

#include <ScsConfig.h>

Public Attributes

UINT32 | PinMux
GPIO signals pin muxing settings. More...
UINT32 | PadTermination
GPIO Pads Internal Termination. More...

Detailed Description

SD GPIO settings.

Definition at line 78 of file ScsConfig.h.

Member Data Documentation

◆ PadTermination

UINT32 MUX_GPIO_PARAM::PadTermination

GPIO Pads Internal Termination.

For more information please see Platform Design Guide. Check GPIO_ELECTRICAL_CONFIG for reference

Definition at line 90 of file ScsConfig.h.

◆ PinMux

UINT32 MUX_GPIO_PARAM::PinMux

GPIO signals pin muxing settings.

If signal can be enable only on a single pin then this parameter should be set to 0. Refer to GPIO_*_MUXING_SDCARD_*x_* in GpioPins*.h for supported settings on a given platform

Definition at line 84 of file ScsConfig.h.

The documentation for this struct was generated from the following file:
  • ScsConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

MUX_GPIO_PARAM Member List

This is the complete list of members for MUX_GPIO_PARAM, including all inherited members.

PadTermination | MUX_GPIO_PARAM
PinMux | MUX_GPIO_PARAM
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OVERCLOCKING_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
OVERCLOCKING_PREMEM_CONFIG Struct Reference

Overclocking Configuration Structure. More...

#include <OverclockingConfig.h>

Collaboration diagram for OVERCLOCKING_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | OcSupport: 1
Overclocking support. More...
UINT32 | OcLock: 1
If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; 0: Disable; 1: Enable (Lock).
UINT32 | CoreVoltageMode: 1
Core voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | CorePllVoltageOffset: 6
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | Avx2RatioOffset: 5
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
UINT32 | Avx3RatioOffset: 5
deprecated from version 28
UINT32 | BclkAdaptiveVoltage: 1
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
UINT32 | RingDownBin: 1
Ring Downbin enable/disable. More...
UINT32 | RingVoltageMode: 1
Ring voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | GtVoltageMode: 1
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive, 1=Override.
UINT32 | RealtimeMemoryTiming: 1
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. 0=Disable, 1=Enable.
UINT32 | FivrEfficiency: 1
Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, 1: Enabled.
UINT32 | CoreVfPointOffsetMode: 1
Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled. More...
UINT32 | CoreVfConfigScope: 1
Core VF Configuration Scope. More...
UINT32 | PerCoreRatioOverride: 1
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. 0: Disable, 1: enable.
UINT32 | UnlimitedIccMax: 1
deprecated from version 32
UINT32 | SaVoltageMode: 1
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating. More...
UINT32 | CoreRatioExtensionMode: 1
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. 0: Disable, 1: enable.
UINT8 | CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0). More...
UINT8 | GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
UINT8 | RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit. More...
UINT8 | AtomL2MaxOcRatio
Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0). More...
UINT16 | CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies. More...
UINT16 | CoreVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range. More...
INT16 | CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes. More...
UINT16 | RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies. More...
UINT16 | RingVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range. More...
INT16 | RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes. More...
INT16 | GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal, 1000=Maximum.
UINT16 | GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
UINT16 | GtExtraTurboVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal, 2000=Maximum.
INT16 | SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
UINT32 | GtPllVoltageOffset: 6
GT PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | RingPllVoltageOffset: 6
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | SaPllVoltageOffset: 6
System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | McPllVoltageOffset: 6
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | IaCepEnable: 1
Enable IA Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | GtCepEnable: 1
Enable GT Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | SaCepEnable: 1
Enable SA Current Excursion Protection. 1: Enable. 0: Disable.
UINT32 | IaSirpEnable: 1
Enable IA SoC Iccmax Reactive Protector. 1: Enable. 0: Disable.
UINT32 | ItdThrottleEnable: 1
Enable Inverse Temperature Dependency Throttle Support. 1: Enable. 0: Disable.
UINT32 | DlvrBypassModeEnable: 1
Enable CPU DLVR bypass mode support, 0: Disable. 0: Enable.
UINT32 | SaPllFreqOverride: 1
Sa PLL Frequecy Override. 0: 3200MHz. 1: 1600MHz.
UINT32 | TscDisableHwFixup: 1
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
UINT8 | TjMaxOffset
TjMax Offset. More...
UINT8 | RsvdByte2 [3]
Reserved for dword alignment.
UINT32 | TvbRatioClipping: 1
This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | TvbVoltageOptimization: 1
This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature. More...
UINT32 | IaIccUnlimitedMode: 1
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | GtIccUnlimitedMode: 1
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
UINT32 | FllOcModeEn: 1
Enable FLL Mode override with the value in FllOcMode. 0: Disable. 1: Enable.
UINT32 | Etvb: 1
Enhanced Thermal Turbo Mode (eTVB). 0:eTVB is disabled on supporting products 1:eTVB is enabled on supporting products.
UINT16 | PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored. More...
UINT8 | Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. More...
UINT8 | Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. More...
INT16 | CoreVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Core Voltage Offset applied to the each selected VF Point. More...
UINT8 | RsvdByte3 [2]
Reserved for dword alignment.
UINT8 | CoreVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Core Ration.
UINT8 | CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
INT16 | PerCoreVoltageOffset [CPU_MAX_BIG_CORES]
Array used to specifies the selected Core Offset Voltage. More...
UINT8 | AtomClusterRatio [CPU_MAX_ATOM_CLUSTERS]
The Atom cluster max ratio overrides. More...
UINT8 | AtomL2VoltageMode
Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating. More...
UINT8 | RsvdByte4
Reserved for dword alignment.
UINT16 | AtomL2VoltageOverride
The atom L2 voltage override which is applied to the entire range of atom core frequencies. More...
UINT16 | AtomL2VoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range. More...
INT16 | AtomL2VoltageOffset
The atom L2 voltage offset applied on top of all other voltage modes. More...
UINT16 | SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies. More...
UINT16 | SaExtraTurboVoltage
Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range. More...
UINT8 | RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes. More...
UINT8 | RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
UINT8 | RsvdByte5 [2]
Reserved for dword alignment.
INT16 | RingVfPointOffset [CPU_OC_MAX_VF_POINTS]
Array used to specifies the Ring Voltage Offset applied to the each selected VF Point. More...
UINT8 | RsvdByte6 [2]
Reserved for dword alignment.
UINT8 | RingVfPointRatio [CPU_OC_MAX_VF_POINTS]
Array for the each selected VF Point to display the Ring Ration.
UINT8 | AtomPllVoltageOffset
Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
UINT32 | CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 8000-50000 (10KHz)
UINT32 | DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled. More...
UINT32 | DisablePerAtomMask
Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms. More...
UINT8 | PvdRatioThreshold
The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range. More...
UINT8 | PvdMode
PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0). More...
UINT8 | FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency, 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency, 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
UINT8 | PllMaxBandingRatio
The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains. More...
INT16 | PerAtomClusterVoltageOffset [CPU_MAX_ATOM_CLUSTERS]
Deprecated from revision 34.
UINT32 | SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto. Range is 4000-100000 (10KHz)
UINT16 | IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA and GT. More...
UINT8 | TvbDownBinsTempThreshold0
Down Bins (delta) for Temperature Threshold 0. More...
UINT8 | TvbTempThreshold0
TVB Temp (degrees C) - Temperature Threshold 0. More...
UINT8 | TvbTempThreshold1
TVB Temp (degrees C) - Temperature Threshold 1. More...
UINT8 | TvbDownBinsTempThreshold1
Down Bins (delta) for Temperature Threshold 1. More...

Detailed Description

Overclocking Configuration Structure.

Revision 1:

  • Initial version. Revision 2
  • Add PerCoreHtDisable Revision 3
  • Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor Revision 4
  • Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & CoreVfPointCount Revision 5
  • Change OcLock default to 'Enabled' Revision 6
  • Add CoreVfScope & PerCoreVoltageOffset Revision 7
  • Add AtomMaxOcRatio Revision 8
  • Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overclocking. Revision 9 Add UnlimitedIccMax Revision 10 Add Atom Voltage configurations Revision 11 Add SA Voltage adaptive and override configurations Revision 12 Add RingVfPointOffsetMode & RingVfPointOffset & RingVfPointRatio & RingVfPointCount Revision 13 Add CpuBclkOcFrequency Revision 14:
  • Add DisablePerCoreMask & DisablePerAtomMask. Revision 15 Add CoreRatioExtensionMode Revision 16 Add PvdRatioThreshold Revision 17 Add IaCepEnable & GtCepEnable & SaCepEnable & IaSirpEnable Revision 18 Add Per Atom Cluster VF support Corrected the policy name of AtomMaxOcRatio to be AtomL2MaxOcRatio Revision 19 Modify PllVoltageOffset of each Domain Range in 0 - 15 instead of 0 - 63 Revision 20 Add ItdThrottleEnable Revision 21 Add AtomClusterRatio & Correct max big core number to be 8 Revision 22 Add SocBclkOcFrequency Revision 23 Add AtomPllVoltageOffset Revision 24 Deprecated FivrFaults, FivrEfficiency. Revision 25 Add DlvrBypassModeEnable. Revision 26 Add PvdMode and FllOverclockMode Revision 27 Deprecated AtomL2MaxOcRatio Revision 28 Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset Revision 29 Add SaPllFreqOverride Revision 30 Add PllMaxBandingRatio Revision 31 Add TscDisableHwFixup Revision 32 Add IaIccUnlimitedMode & IaIccMax & GtIccUnlimitedMode & GtIccMax and deprecated UnlimitedIccMax Revision 33 Add TvbDownBinsTempThreshold0, TvbDownBinsTempThreshold1, TvbTempThreshold0, TvbTempThreshold1 Revision 34 Deprecated PllMaxBandingRatio Revision 35 Add FllOcModeEn Revision 36 Deprecated DisablePerAtomMask (DisablePerCoreMask is used for both the cores) Revision 37 Add Etvb

Definition at line 132 of file OverclockingConfig.h.

Member Data Documentation

◆ AtomClusterRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS]

The Atom cluster max ratio overrides.

Default: 0 Range: 0 to 120.

Definition at line 342 of file OverclockingConfig.h.

◆ AtomL2MaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomL2MaxOcRatio

Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).

0. no override/HW defaults.. non-turbo max - 120. deprecated from version 27

Definition at line 210 of file OverclockingConfig.h.

◆ AtomL2VoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range.

Used when AtomL2VoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 361 of file OverclockingConfig.h.

◆ AtomL2VoltageMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageMode

Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.

0: Adaptive Mode allows the atom processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 348 of file OverclockingConfig.h.

◆ AtomL2VoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOffset

The atom L2 voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 366 of file OverclockingConfig.h.

◆ AtomL2VoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOverride

The atom L2 voltage override which is applied to the entire range of atom core frequencies.

Used when AtomL2VoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 355 of file OverclockingConfig.h.

◆ Avx2VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor

Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX2 workloads. A value < 100 will decrease the voltage guardband on AVX2 workloads.

0. No scale factor applied

Definition at line 304 of file OverclockingConfig.h.

◆ Avx512VoltageScaleFactor

UINT8 OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor

Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.

Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor. A value of 0 means no scale factor applied (no change to voltage on AVX commands) A value of 100 applies the default voltage guardband values (1.0 factor). A value > 100 will increase the voltage guardband on AVX512 workloads. A value < 100 will decrease the voltage guardband on AVX512 workloads.

0. No scale factor applied deprecated from version 28

Definition at line 316 of file OverclockingConfig.h.

◆ CoreMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio

Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).

0. no override/HW defaults.. Range non-turbo max - 120 (Previously max turbo is 83).

Definition at line 199 of file OverclockingConfig.h.

◆ CoreVfConfigScope

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope

Core VF Configuration Scope.

Alows both all-core VF curve or per-core VF curve configuration. 0: All-core Scope, setting the VF curve for all cores. 1: Per-core Scope, setting the VF curve per-core.

Definition at line 184 of file OverclockingConfig.h.

◆ CoreVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Core Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts.

Definition at line 321 of file OverclockingConfig.h.

◆ CoreVfPointOffsetMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode

Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled.

Selects Core Voltage & Frequency Offset between Legacy and Selection modes. Need Reset System after enabling OverClocking Feature to Initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection Mode, setting a selected VF point.

Definition at line 177 of file OverclockingConfig.h.

◆ CoreVoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.

Used when CoreVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 222 of file OverclockingConfig.h.

◆ CoreVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode

Core voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 148 of file OverclockingConfig.h.

◆ CoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset

The core voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 227 of file OverclockingConfig.h.

◆ CoreVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride

The core voltage override which is applied to the entire range of cpu core frequencies.

Used when CoreVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 216 of file OverclockingConfig.h.

◆ DisablePerAtomMask

UINT32 OVERCLOCKING_PREMEM_CONFIG::DisablePerAtomMask

Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms.

Each bit represents logical core id: 1 - Disable 0 - Ignored Defalut is 0, means no Small Core disable mask setting.

Definition at line 418 of file OverclockingConfig.h.

◆ DisablePerCoreMask

UINT32 OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask

Core disable mask is a bitwise indication of which core should be disabled.

Each bit represents physical core id for both P-core and E-core: 1 - Disable 0 - Ignored Default is 0, means no Core disable mask setting.

Definition at line 410 of file OverclockingConfig.h.

◆ IaIccMax

UINT16 OVERCLOCKING_PREMEM_CONFIG::IaIccMax

Voltage Regulator Current Limit (Icc Max) for IA and GT.

This value represents the Maximum instantaneous current allowed at any given time. The value is represented in 1/4 A increments. A value of 400 = 100A. 4. Range is 4-2047.

Definition at line 450 of file OverclockingConfig.h.

◆ OcSupport

UINT32 OVERCLOCKING_PREMEM_CONFIG::OcSupport

Overclocking support.

This controls whether OC mailbox transactions are sent. If disabled, all policies in this config block besides OcSupport and OcLock will be ignored. 0: Disable; 1: Enable.

Note
If PcdOverclockEnable is disabled, this should also be disabled.

Definition at line 141 of file OverclockingConfig.h.

◆ PerCoreHtDisable

UINT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable

Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.

Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.

Definition at line 292 of file OverclockingConfig.h.

◆ PerCoreVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::PerCoreVoltageOffset[CPU_MAX_BIG_CORES]

Array used to specifies the selected Core Offset Voltage.

This voltage is specified in millivolts.

Definition at line 335 of file OverclockingConfig.h.

◆ PllMaxBandingRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::PllMaxBandingRatio

The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.

0. Hardware Default/No Override. Minimum must be greater than P0 and maximum is 120.

Definition at line 443 of file OverclockingConfig.h.

◆ PvdMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdMode

PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).

0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock) 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)

Definition at line 431 of file OverclockingConfig.h.

◆ PvdRatioThreshold

UINT8 OVERCLOCKING_PREMEM_CONFIG::PvdRatioThreshold

The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so that the output is within the DCO frequency range.

This threshold is applied to all the domains (Cores, Ring, SA, Memory and GT). 0. Default/No Override. Range 1-63.

Definition at line 425 of file OverclockingConfig.h.

◆ RingDownBin

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingDownBin

Ring Downbin enable/disable.

When enabled, the CPU will force the ring ratio to be lower than the core ratio. Disabling will allow the ring and core ratios to run at the same frequency. Uses OC Mailbox command 0x19. 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature.

Definition at line 160 of file OverclockingConfig.h.

◆ RingMaxOcRatio

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio

Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.

0. no override/HW defaults.. Range non-turbo max - 85.

Definition at line 205 of file OverclockingConfig.h.

◆ RingVfPointOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffset[CPU_OC_MAX_VF_POINTS]

Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.

This voltage is specified in millivolts.

Definition at line 395 of file OverclockingConfig.h.

◆ RingVfPointOffsetMode

UINT8 OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode

Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.

Need Reset System after enabling OverClocking Feature to Initialize the default value. 0: In Legacy Mode, setting a global offset for the entire VF curve. 1: In Selection modes, setting a selected VF point.

Definition at line 385 of file OverclockingConfig.h.

◆ RingVoltageAdaptive

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageAdaptive

Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.

Used when RingVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 239 of file OverclockingConfig.h.

◆ RingVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode

Ring voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 166 of file OverclockingConfig.h.

◆ RingVoltageOffset

INT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset

The ring voltage offset applied on top of all other voltage modes.

This offset is applied over the entire frequency range. This is a 2's complement number in mV units. Default: 0 Range: -1000 to 1000.

Definition at line 244 of file OverclockingConfig.h.

◆ RingVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride

The ring voltage override which is applied to the entire range of cpu ring frequencies.

Used when RingVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 233 of file OverclockingConfig.h.

◆ SaExtraTurboVoltage

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaExtraTurboVoltage

Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range.

Used when SaVoltageMode = Adaptive. 0. no override. Range 0-2000mV.

Definition at line 378 of file OverclockingConfig.h.

◆ SaVoltageMode

UINT32 OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode

SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.

0: Adaptive Mode allows the processor to interpolate a voltage curve when beyond fused P0 range; 1: Override, sets one voltage for for the entire frequency range, Pn-P0.

Definition at line 192 of file OverclockingConfig.h.

◆ SaVoltageOverride

UINT16 OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride

The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.

Used when SaVoltageMode = Override. 0. no override. Range 0-2000 mV.

Definition at line 372 of file OverclockingConfig.h.

◆ TjMaxOffset

UINT8 OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset

TjMax Offset.

Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius. Default: 0 Hardware Defaults Range 10 to 63. 0 = No offset / Keep HW default.

Definition at line 267 of file OverclockingConfig.h.

◆ TvbDownBinsTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold0

Down Bins (delta) for Temperature Threshold 0.

When running above Temperature Threshold 0, the ratio will be clipped by MAX_RATIO[n]-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 1 . Range 0-10.

Definition at line 457 of file OverclockingConfig.h.

◆ TvbDownBinsTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold1

Down Bins (delta) for Temperature Threshold 1.

When running above Temperature Threshold 1, the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 0-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 2 . Range 0-10.

Definition at line 475 of file OverclockingConfig.h.

◆ TvbRatioClipping

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping

This service controls Core frequency reduction caused by high package temperatures for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

It is required to be disabled for supporting overclocking at frequencies higher than the default max turbo frequency. 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping.

Definition at line 275 of file OverclockingConfig.h.

◆ TvbTempThreshold0

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold0

TVB Temp (degrees C) - Temperature Threshold 0.

Running ABOVE this temperature will clip delta Down Bins for Threshold 0 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 70 . Range 0-100.

Definition at line 463 of file OverclockingConfig.h.

◆ TvbTempThreshold1

UINT8 OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold1

TVB Temp (degrees C) - Temperature Threshold 1.

Running ABOVE this temperature, clip delta Down Bins for Threshold 1 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled). 100 . Range 0-100.

Definition at line 469 of file OverclockingConfig.h.

◆ TvbVoltageOptimization

UINT32 OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization

This service controls thermal based voltage optimizations for processors that implement the Intel Thermal Velocity Boost (TVB) feature.

0: Disables TVB voltage optimization. 1: Enables TVB voltage optimization.

Definition at line 281 of file OverclockingConfig.h.

The documentation for this struct was generated from the following file:
  • OverclockingConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

OVERCLOCKING_PREMEM_CONFIG Member List

This is the complete list of members for OVERCLOCKING_PREMEM_CONFIG, including all inherited members.

AtomClusterRatio | OVERCLOCKING_PREMEM_CONFIG
AtomL2MaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageMode | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageOffset | OVERCLOCKING_PREMEM_CONFIG
AtomL2VoltageOverride | OVERCLOCKING_PREMEM_CONFIG
AtomPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
Avx2RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx2VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
Avx3RatioOffset | OVERCLOCKING_PREMEM_CONFIG
Avx512VoltageScaleFactor | OVERCLOCKING_PREMEM_CONFIG
BclkAdaptiveVoltage | OVERCLOCKING_PREMEM_CONFIG
CoreMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
CorePllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreRatioExtensionMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfConfigScope | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointCount | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
CoreVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageMode | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
CoreVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
CpuBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
DisablePerAtomMask | OVERCLOCKING_PREMEM_CONFIG
DisablePerCoreMask | OVERCLOCKING_PREMEM_CONFIG
DlvrBypassModeEnable | OVERCLOCKING_PREMEM_CONFIG
Etvb | OVERCLOCKING_PREMEM_CONFIG
FivrEfficiency | OVERCLOCKING_PREMEM_CONFIG
FllOcModeEn | OVERCLOCKING_PREMEM_CONFIG
FllOverclockMode | OVERCLOCKING_PREMEM_CONFIG
GtCepEnable | OVERCLOCKING_PREMEM_CONFIG
GtExtraTurboVoltage | OVERCLOCKING_PREMEM_CONFIG
GtIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
GtMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
GtPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
GtVoltageMode | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
GtVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
Header | OVERCLOCKING_PREMEM_CONFIG
IaCepEnable | OVERCLOCKING_PREMEM_CONFIG
IaIccMax | OVERCLOCKING_PREMEM_CONFIG
IaIccUnlimitedMode | OVERCLOCKING_PREMEM_CONFIG
IaSirpEnable | OVERCLOCKING_PREMEM_CONFIG
ItdThrottleEnable | OVERCLOCKING_PREMEM_CONFIG
McPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
OcLock | OVERCLOCKING_PREMEM_CONFIG
OcSupport | OVERCLOCKING_PREMEM_CONFIG
PerAtomClusterVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
PerCoreHtDisable | OVERCLOCKING_PREMEM_CONFIG
PerCoreRatioOverride | OVERCLOCKING_PREMEM_CONFIG
PerCoreVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
PllMaxBandingRatio | OVERCLOCKING_PREMEM_CONFIG
PvdMode | OVERCLOCKING_PREMEM_CONFIG
PvdRatioThreshold | OVERCLOCKING_PREMEM_CONFIG
RealtimeMemoryTiming | OVERCLOCKING_PREMEM_CONFIG
RingDownBin | OVERCLOCKING_PREMEM_CONFIG
RingMaxOcRatio | OVERCLOCKING_PREMEM_CONFIG
RingPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingVfPointCount | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffset | OVERCLOCKING_PREMEM_CONFIG
RingVfPointOffsetMode | OVERCLOCKING_PREMEM_CONFIG
RingVfPointRatio | OVERCLOCKING_PREMEM_CONFIG
RingVoltageAdaptive | OVERCLOCKING_PREMEM_CONFIG
RingVoltageMode | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
RingVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
RsvdByte2 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte3 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte4 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte5 | OVERCLOCKING_PREMEM_CONFIG
RsvdByte6 | OVERCLOCKING_PREMEM_CONFIG
SaCepEnable | OVERCLOCKING_PREMEM_CONFIG
SaExtraTurboVoltage | OVERCLOCKING_PREMEM_CONFIG
SaPllFreqOverride | OVERCLOCKING_PREMEM_CONFIG
SaPllVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageMode | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOffset | OVERCLOCKING_PREMEM_CONFIG
SaVoltageOverride | OVERCLOCKING_PREMEM_CONFIG
SocBclkOcFrequency | OVERCLOCKING_PREMEM_CONFIG
TjMaxOffset | OVERCLOCKING_PREMEM_CONFIG
TscDisableHwFixup | OVERCLOCKING_PREMEM_CONFIG
TvbDownBinsTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
TvbDownBinsTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
TvbRatioClipping | OVERCLOCKING_PREMEM_CONFIG
TvbTempThreshold0 | OVERCLOCKING_PREMEM_CONFIG
TvbTempThreshold1 | OVERCLOCKING_PREMEM_CONFIG
TvbVoltageOptimization | OVERCLOCKING_PREMEM_CONFIG
UnlimitedIccMax | OVERCLOCKING_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_DCI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DCI_PREMEM_CONFIG Struct Reference

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

#include <DciConfig.h>

Collaboration diagram for PCH_DCI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | DciEn
DCI enable. More...
UINT8 | DciDbcMode
USB DbC enable mode. More...
UINT8 | DciModphyPg
Deprecated.
UINT8 | DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support. More...
UINT8 | DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state. More...
UINT8 | KeepEarlyTrace
Early trace is activated by default. More...

Detailed Description

The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)

Revision 1:

  • Initial version. Revision 2:
  • Added DciModphyPg
  • change to use data in byte unit rather than bit-field Revision 3:
  • Deprecated DciModphyPg
  • Added DciClkEnable, KeepEarlyTrace

Definition at line 71 of file DciConfig.h.

Member Data Documentation

◆ DciClkEnable

UINT8 PCH_DCI_PREMEM_CONFIG::DciClkEnable

Determine if to enable or disable DCI clock request in lowest power state.

0:Disabled; 1:Enabled

Definition at line 99 of file DciConfig.h.

◆ DciDbcMode

UINT8 PCH_DCI_PREMEM_CONFIG::DciDbcMode

USB DbC enable mode.

Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value Refer to definition of DCI_USB_DBC_MODE for supported settings. 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change

Definition at line 85 of file DciConfig.h.

◆ DciEn

UINT8 PCH_DCI_PREMEM_CONFIG::DciEn

DCI enable.

Determine if to enable DCI debug from host. 0:Disabled; 1:Enabled

Definition at line 78 of file DciConfig.h.

◆ DciUsb3TypecUfpDbg

UINT8 PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg

USB3 Type-C UFP2DFP kenel / platform debug support.

No change will do nothing to UFP2DFP configuration. When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection. It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle. Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings. 0:Disabled; 1:Enabled; 2:No Change

Definition at line 94 of file DciConfig.h.

◆ KeepEarlyTrace

UINT8 PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace

Early trace is activated by default.

Enable to keep early trace data and keep tracing; disable to stop tracing; When debug probe is connected and granted, force to no change, let host tool to set it. 0: Disable; 1: Enable early trace; 2:No Change;

Definition at line 106 of file DciConfig.h.

The documentation for this struct was generated from the following file:
  • DciConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_DCI_PREMEM_CONFIG Member List

This is the complete list of members for PCH_DCI_PREMEM_CONFIG, including all inherited members.

DciClkEnable | PCH_DCI_PREMEM_CONFIG
DciDbcMode | PCH_DCI_PREMEM_CONFIG
DciEn | PCH_DCI_PREMEM_CONFIG
DciModphyPg | PCH_DCI_PREMEM_CONFIG
DciUsb3TypecUfpDbg | PCH_DCI_PREMEM_CONFIG
Header | PCH_DCI_PREMEM_CONFIG
KeepEarlyTrace | PCH_DCI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DEVICE_INTERRUPT_CONFIG Struct Reference

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...

#include <InterruptConfig.h>

Public Attributes

UINT8 | Device
Device number.
UINT8 | Function
Device function.
UINT8 | IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
UINT8 | Irq
IRQ to be set for device.

Detailed Description

The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.

Definition at line 57 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_DEVICE_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_DEVICE_INTERRUPT_CONFIG, including all inherited members.

Device | PCH_DEVICE_INTERRUPT_CONFIG
Function | PCH_DEVICE_INTERRUPT_CONFIG
IntX | PCH_DEVICE_INTERRUPT_CONFIG
Irq | PCH_DEVICE_INTERRUPT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_DMI_CONFIG Struct Reference

Public Attributes | List of all members
PCH_DMI_CONFIG Struct Reference

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

#include <PchDmiConfig.h>

Collaboration diagram for PCH_DMI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PwrOptEnable: 1
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
UINT32 | DmiAspmCtrl: 8
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
UINT32 | CwbEnable: 1
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
UINT32 | L1RpCtl: 1
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
UINT32 | DmiPowerReduction: 1
When set to TRUE turns on: More...
UINT32 | ClockGating: 1
0: Disable; 1: Enable clock gating.
UINT32 | Rsvdbits: 19
Reserved bits.

Detailed Description

The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.

Revision 1:

  • Initial version.

Definition at line 73 of file PchDmiConfig.h.

Member Data Documentation

◆ DmiPowerReduction

UINT32 PCH_DMI_CONFIG::DmiPowerReduction

When set to TRUE turns on:

  • L1 State Controller Power Gating
  • L1 State PHY Data Lane Power Gating
  • PHY Common Lane Power Gating
  • Hardware Autonomous Enable
  • PMC Request Enable and Sleep Enable

Definition at line 88 of file PchDmiConfig.h.

The documentation for this struct was generated from the following file:
  • PchDmiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_DMI_CONFIG Member List

This is the complete list of members for PCH_DMI_CONFIG, including all inherited members.

ClockGating | PCH_DMI_CONFIG
CwbEnable | PCH_DMI_CONFIG
DmiAspmCtrl | PCH_DMI_CONFIG
DmiPowerReduction | PCH_DMI_CONFIG
Header | PCH_DMI_CONFIG
L1RpCtl | PCH_DMI_CONFIG
PwrOptEnable | PCH_DMI_CONFIG
Rsvdbits | PCH_DMI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_DMI_EQ_PARAM Struct Reference

Public Attributes | List of all members
PCH_DMI_EQ_PARAM Struct Reference

Lane specific Dmi Gen3, Gen4 equalization parameters. More...

#include <PchDmiConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Lane specific Dmi Gen3, Gen4 equalization parameters.

Definition at line 54 of file PchDmiConfig.h.

The documentation for this struct was generated from the following file:
  • PchDmiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_DMI_EQ_PARAM Member List

This is the complete list of members for PCH_DMI_EQ_PARAM, including all inherited members.

Cm | PCH_DMI_EQ_PARAM
Cp | PCH_DMI_EQ_PARAM
Rsvd0 | PCH_DMI_EQ_PARAM
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_DMI_HOB Struct Reference

Public Attributes | List of all members
PCH_DMI_HOB Struct Reference

The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization. More...

#include <PchDmiHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gPchPcieHobGuid.
UINT8 | CmGen3 [PCH_DMI_HWEQ_COEFFS_MAX]
These members describe the configuration of each PCH Dmi root port. More...
UINT8 | CpGen3 [PCH_DMI_HWEQ_COEFFS_MAX]
Coefficient C+1 for Gen3.
UINT8 | CmGen4 [PCH_DMI_HWEQ_COEFFS_MAX]
Coefficient C-1 for Gen4.
UINT8 | CpGen4 [PCH_DMI_HWEQ_COEFFS_MAX]
Coefficient C+1 for Gen4.

Detailed Description

The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization.

Definition at line 48 of file PchDmiHob.h.

Member Data Documentation

◆ CmGen3

UINT8 PCH_DMI_HOB::CmGen3[PCH_DMI_HWEQ_COEFFS_MAX]

These members describe the configuration of each PCH Dmi root port.

Coefficient C-1 for Gen3

Definition at line 53 of file PchDmiHob.h.

The documentation for this struct was generated from the following file:
  • PchDmiHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_DMI_HOB Member List

This is the complete list of members for PCH_DMI_HOB, including all inherited members.

CmGen3 | PCH_DMI_HOB
CmGen4 | PCH_DMI_HOB
CpGen3 | PCH_DMI_HOB
CpGen4 | PCH_DMI_HOB
EfiHobGuidType | PCH_DMI_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_ESPI_CONFIG Struct Reference

Public Attributes | List of all members
PCH_ESPI_CONFIG Struct Reference

This structure contains the policies which are related to ESPI. More...

#include <EspiConfig.h>

Collaboration diagram for PCH_ESPI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | LgmrEnable: 1
LPC (eSPI) Memory Range Decode Enable. More...
UINT32 | BmeMasterSlaveEnabled: 1
eSPI host and device BME settings. More...
UINT32 | HostC10ReportEnable: 1
Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE) 0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored) 1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
UINT32 | LockLinkConfiguration: 1
eSPI Link Configuration Lock (SBLCL) If set to TRUE then communication through SET_CONFIG/GET_CONFIG to eSPI device addresses from range 0x0 - 0x7FF 1: TRUE, 0: FALSE
UINT32 | EspiPmHAE: 1
Hardware Autonomous Enable (HAE) If set to TRUE, then the IP may request a PG whenever it is idle.
UINT32 | RsvdBits: 27
Reserved bits.

Detailed Description

This structure contains the policies which are related to ESPI.

Revision 1:

  • Initial revision Revision 2:
  • Added LockLinkConfiguration field to config block

Definition at line 51 of file EspiConfig.h.

Member Data Documentation

◆ BmeMasterSlaveEnabled

UINT32 PCH_ESPI_CONFIG::BmeMasterSlaveEnabled

eSPI host and device BME settings.

When TRUE, then the BME bit enabled in eSPI host and device. 0: FALSE, 1: TRUE

Definition at line 64 of file EspiConfig.h.

◆ LgmrEnable

UINT32 PCH_ESPI_CONFIG::LgmrEnable

LPC (eSPI) Memory Range Decode Enable.

When TRUE, then the range specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI). 0: FALSE, 1: TRUE

Definition at line 58 of file EspiConfig.h.

The documentation for this struct was generated from the following file:
  • EspiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_ESPI_CONFIG Member List

This is the complete list of members for PCH_ESPI_CONFIG, including all inherited members.

BmeMasterSlaveEnabled | PCH_ESPI_CONFIG
EspiPmHAE | PCH_ESPI_CONFIG
Header | PCH_ESPI_CONFIG
HostC10ReportEnable | PCH_ESPI_CONFIG
LgmrEnable | PCH_ESPI_CONFIG
LockLinkConfiguration | PCH_ESPI_CONFIG
RsvdBits | PCH_ESPI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_FIVR_CONFIG Struct Reference

Public Attributes | List of all members
PCH_FIVR_CONFIG Struct Reference

The PCH_FIVR_CONFIG block describes FIVR settings. More...

#include <FivrConfig.h>

Collaboration diagram for PCH_FIVR_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback. More...
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
UINT32 | FivrDynPm: 1
Enable/Disable FIVR Dynamic Power Management Default is 1 .
UINT32 | BypassFivrConfig: 1
Enable/Disable Bypass of FIVR configuration Default is 0 .

Detailed Description

The PCH_FIVR_CONFIG block describes FIVR settings.

Definition at line 176 of file FivrConfig.h.

Member Data Documentation

◆ ExtVnnRailSx

FIVR_EXT_RAIL_CONFIG PCH_FIVR_CONFIG::ExtVnnRailSx

Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.

Required only if External Vnn VR needs different settings for Sx than those specified in ExtVnnRail.

Definition at line 191 of file FivrConfig.h.

The documentation for this struct was generated from the following file:
  • FivrConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_FIVR_CONFIG Member List

This is the complete list of members for PCH_FIVR_CONFIG, including all inherited members.

BypassFivrConfig | PCH_FIVR_CONFIG
ExtV1p05Rail | PCH_FIVR_CONFIG
ExtVnnRail | PCH_FIVR_CONFIG
ExtVnnRailSx | PCH_FIVR_CONFIG
FivrDynPm | PCH_FIVR_CONFIG
Header | PCH_FIVR_CONFIG
VccinAux | PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_FLASH_PROTECTION_CONFIG Struct Reference

Public Attributes | List of all members
PCH_FLASH_PROTECTION_CONFIG Struct Reference

The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled. More...

#include <FlashProtectionConfig.h>

Collaboration diagram for PCH_FLASH_PROTECTION_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PROTECTED_RANGE ProtectRange [PCH_FLASH_PROTECTED_RANGES]
Protected Flash Ranges.

Detailed Description

The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled.

PROTECTED_RANGE is used to specify if flash protection are enabled, the write protection enable bit and the read protection enable bit, and to specify the upper limit and lower base for each register Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine, and set the limit and base accordingly.

Definition at line 76 of file FlashProtectionConfig.h.

The documentation for this struct was generated from the following file:
  • FlashProtectionConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_FLASH_PROTECTION_CONFIG Member List

This is the complete list of members for PCH_FLASH_PROTECTION_CONFIG, including all inherited members.

Header | PCH_FLASH_PROTECTION_CONFIG
ProtectRange | PCH_FLASH_PROTECTION_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_GENERAL_CONFIG Struct Reference

Public Attributes | List of all members
PCH_GENERAL_CONFIG Struct Reference

PCH General Configuration Revision 1: - Initial version. More...

#include <PchGeneralConfig.h>

Collaboration diagram for PCH_GENERAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Crid: 1
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled. More...
UINT32 | LegacyIoLowLatency: 1
Set to enable low latency of legacy IO. More...
UINT32 | AcpiL6dPmeHandling: 1
Enables _L6D ACPI handler. More...
UINT32 | RsvdBits0: 29
Reserved bits.

Detailed Description

PCH General Configuration Revision 1: - Initial version.

Revision 2: - Added AcpiL6dPmeHandling

Definition at line 56 of file PchGeneralConfig.h.

Member Data Documentation

◆ AcpiL6dPmeHandling

UINT32 PCH_GENERAL_CONFIG::AcpiL6dPmeHandling

Enables _L6D ACPI handler.

PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit 0: Disable, 1: Enable

Definition at line 77 of file PchGeneralConfig.h.

◆ Crid

UINT32 PCH_GENERAL_CONFIG::Crid

This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be enabled.

0: Disable; 1: Enable

Definition at line 62 of file PchGeneralConfig.h.

◆ LegacyIoLowLatency

UINT32 PCH_GENERAL_CONFIG::LegacyIoLowLatency

Set to enable low latency of legacy IO.

Some systems require lower IO latency irrespective of power. This is a tradeoff between power and IO latency.

Note
: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent and ITSS Clock Gating are forced to disabled. 0: Disable, 1: Enable

Definition at line 71 of file PchGeneralConfig.h.

The documentation for this struct was generated from the following file:
  • PchGeneralConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_GENERAL_CONFIG Member List

This is the complete list of members for PCH_GENERAL_CONFIG, including all inherited members.

AcpiL6dPmeHandling | PCH_GENERAL_CONFIG
Crid | PCH_GENERAL_CONFIG
Header | PCH_GENERAL_CONFIG
LegacyIoLowLatency | PCH_GENERAL_CONFIG
RsvdBits0 | PCH_GENERAL_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_GENERAL_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_GENERAL_PREMEM_CONFIG Struct Reference

PCH General Pre-Memory Configuration Revision 1: - Initial version. More...

#include <PchGeneralConfig.h>

Collaboration diagram for PCH_GENERAL_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Port80Route: 1
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
UINT32 | IotgPllSscEn: 1
Need to disable CPU Side SSC for A0 PO.
UINT32 | GpioOverride: 3
Gpio override Level – 0: Disable;. More...
UINT32 | IoeDebugEn: 1
Enable/Disable IOE Debug. More...
UINT32 | PmodeClkEn: 1
Enable/Disable PMODE clock. More...
UINT32 | RsvdBits0: 25
Reserved bits.

Detailed Description

PCH General Pre-Memory Configuration Revision 1: - Initial version.

Revision 2: - Added GpioOverride. Revision 3: - Added IoeDebugEn, PmodeClkEn

Definition at line 87 of file PchGeneralConfig.h.

Member Data Documentation

◆ GpioOverride

UINT32 PCH_GENERAL_PREMEM_CONFIG::GpioOverride

Gpio override Level – 0: Disable;.

  • 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
  • 2: Override Level 2 - Reserved for future use

Definition at line 100 of file PchGeneralConfig.h.

◆ IoeDebugEn

UINT32 PCH_GENERAL_PREMEM_CONFIG::IoeDebugEn

Enable/Disable IOE Debug.

When enabled, IOE D2D Dfx link and clock will keep up for debug 0: Disable; 1: Enable

Definition at line 105 of file PchGeneralConfig.h.

◆ PmodeClkEn

UINT32 PCH_GENERAL_PREMEM_CONFIG::PmodeClkEn

Enable/Disable PMODE clock.

When enabled, Pmode clock will toggle for XDP use 0: Disable; 1: Enable

Definition at line 110 of file PchGeneralConfig.h.

The documentation for this struct was generated from the following file:
  • PchGeneralConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_GENERAL_PREMEM_CONFIG Member List

This is the complete list of members for PCH_GENERAL_PREMEM_CONFIG, including all inherited members.

GpioOverride | PCH_GENERAL_PREMEM_CONFIG
Header | PCH_GENERAL_PREMEM_CONFIG
IoeDebugEn | PCH_GENERAL_PREMEM_CONFIG
IotgPllSscEn | PCH_GENERAL_PREMEM_CONFIG
PmodeClkEn | PCH_GENERAL_PREMEM_CONFIG
Port80Route | PCH_GENERAL_PREMEM_CONFIG
RsvdBits0 | PCH_GENERAL_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_CONFIG Struct Reference

Public Attributes | List of all members
PCH_HSIO_CONFIG Struct Reference

The PCH_HSIO_CONFIG block provides HSIO message related settings. More...

#include <HsioConfig.h>

Collaboration diagram for PCH_HSIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | ChipsetInitBinPtr
Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
UINT32 | ChipsetInitBinLen
Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
UINT32 | SynpsPhyBinPtr
Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME.
UINT32 | SynpsPhyBinLen
Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME.

Detailed Description

The PCH_HSIO_CONFIG block provides HSIO message related settings.

Definition at line 71 of file HsioConfig.h.

The documentation for this struct was generated from the following file:
  • HsioConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_CONFIG Member List

This is the complete list of members for PCH_HSIO_CONFIG, including all inherited members.

ChipsetInitBinLen | PCH_HSIO_CONFIG
ChipsetInitBinPtr | PCH_HSIO_CONFIG
Header | PCH_HSIO_CONFIG
SynpsPhyBinLen | PCH_HSIO_CONFIG
SynpsPhyBinPtr | PCH_HSIO_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_PCIE_LANE_CONFIG Struct Reference

Public Attributes | List of all members
PCH_HSIO_PCIE_LANE_CONFIG Struct Reference

The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane. More...

#include <HsioPcieConfig.h>

Public Attributes

UINT32 | HsioRxSetCtleEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value
UINT32 | HsioRxSetCtle: 6
PCH PCIe Gen 3 Set CTLE Value.
UINT32 | HsioTxGen1DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen1DownscaleAmp: 6
PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value.
UINT32 | HsioTxGen2DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen2DownscaleAmp: 6
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
UINT32 | HsioTxGen3DownscaleAmpEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen3DownscaleAmp: 6
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
UINT32 | RsvdBits0: 4
Reserved Bits.
UINT32 | HsioTxGen1DeEmphEnable: 1
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen1DeEmph: 6
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmph3p5Enable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph3p5: 6
PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmph6p0Enable: 1
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph6p0: 6
PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting.
UINT32 | RsvdBits1: 11
Reserved Bits.

Detailed Description

The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane.

Definition at line 48 of file HsioPcieConfig.h.

The documentation for this struct was generated from the following file:
  • HsioPcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_PCIE_LANE_CONFIG Member List

This is the complete list of members for PCH_HSIO_PCIE_LANE_CONFIG, including all inherited members.

HsioRxSetCtle | PCH_HSIO_PCIE_LANE_CONFIG
HsioRxSetCtleEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DeEmph | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DeEmphEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen1DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph3p5 | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph3p5Enable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph6p0 | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DeEmph6p0Enable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen2DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen3DownscaleAmp | PCH_HSIO_PCIE_LANE_CONFIG
HsioTxGen3DownscaleAmpEnable | PCH_HSIO_PCIE_LANE_CONFIG
RsvdBits0 | PCH_HSIO_PCIE_LANE_CONFIG
RsvdBits1 | PCH_HSIO_PCIE_LANE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_PCIE_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_HSIO_PCIE_PREMEM_CONFIG Struct Reference

The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes. More...

#include <HsioPcieConfig.h>

Collaboration diagram for PCH_HSIO_PCIE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_HSIO_PCIE_LANE_CONFIG Lane [PCH_MAX_PCIE_ROOT_PORTS]
These members describe the configuration of HSIO for PCIe lanes.

Detailed Description

The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes.

Definition at line 76 of file HsioPcieConfig.h.

The documentation for this struct was generated from the following file:
  • HsioPcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_PCIE_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_PCIE_PREMEM_CONFIG, including all inherited members.

Header | PCH_HSIO_PCIE_PREMEM_CONFIG
Lane | PCH_HSIO_PCIE_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_HSIO_PREMEM_CONFIG Struct Reference

The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings. More...

#include <HsioConfig.h>

Collaboration diagram for PCH_HSIO_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | ChipsetInitMessage
(Test) 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent 1- Enable ChipsetInit HECI message
UINT8 | BypassPhySyncReset
(Test) 0- Disable 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI message.

Detailed Description

The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.

Definition at line 48 of file HsioConfig.h.

The documentation for this struct was generated from the following file:
  • HsioConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_PREMEM_CONFIG, including all inherited members.

BypassPhySyncReset | PCH_HSIO_PREMEM_CONFIG
ChipsetInitMessage | PCH_HSIO_PREMEM_CONFIG
Header | PCH_HSIO_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_SATA_PORT_LANE Struct Reference

Public Attributes | List of all members
PCH_HSIO_SATA_PORT_LANE Struct Reference

The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane. More...

#include <HsioSataConfig.h>

Public Attributes

UINT32 | HsioRxGen1EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen1EqBoostMag: 6
SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioRxGen2EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen2EqBoostMag: 6
SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioRxGen3EqBoostMagEnable: 1
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
UINT32 | HsioRxGen3EqBoostMag: 6
SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
UINT32 | HsioTxGen1DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen1DownscaleAmp: 6
SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
UINT32 | RsvdBits0: 4
Reserved bits.
UINT32 | HsioTxGen2DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen2DownscaleAmp: 6
SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment.
UINT32 | HsioTxGen3DownscaleAmpEnable: 1
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
UINT32 | HsioTxGen3DownscaleAmp: 6
SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment.
UINT32 | HsioTxGen1DeEmphEnable: 1
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen1DeEmph: 6
SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT32 | HsioTxGen2DeEmphEnable: 1
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen2DeEmph: 6
SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
UINT32 | RsvdBits1: 4
Reserved bits.
UINT32 | HsioTxGen3DeEmphEnable: 1
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
UINT32 | HsioTxGen3DeEmph: 6
SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override.
UINT32 | RsvdBits2: 25
Reserved bits.

Detailed Description

The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane.

Definition at line 46 of file HsioSataConfig.h.

The documentation for this struct was generated from the following file:
  • HsioSataConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_SATA_PORT_LANE Member List

This is the complete list of members for PCH_HSIO_SATA_PORT_LANE, including all inherited members.

HsioRxGen1EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen1EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioRxGen2EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen2EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioRxGen3EqBoostMag | PCH_HSIO_SATA_PORT_LANE
HsioRxGen3EqBoostMagEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen1DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen2DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DeEmph | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DeEmphEnable | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DownscaleAmp | PCH_HSIO_SATA_PORT_LANE
HsioTxGen3DownscaleAmpEnable | PCH_HSIO_SATA_PORT_LANE
RsvdBits0 | PCH_HSIO_SATA_PORT_LANE
RsvdBits1 | PCH_HSIO_SATA_PORT_LANE
RsvdBits2 | PCH_HSIO_SATA_PORT_LANE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_HSIO_SATA_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_HSIO_SATA_PREMEM_CONFIG Struct Reference

The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. More...

#include <HsioSataConfig.h>

Collaboration diagram for PCH_HSIO_SATA_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_HSIO_SATA_PORT_LANE PortLane [PCH_MAX_SATA_PORTS]
These members describe the configuration of HSIO for SATA lanes.

Detailed Description

The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.

Definition at line 82 of file HsioSataConfig.h.

The documentation for this struct was generated from the following file:
  • HsioSataConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_HSIO_SATA_PREMEM_CONFIG Member List

This is the complete list of members for PCH_HSIO_SATA_PREMEM_CONFIG, including all inherited members.

Header | PCH_HSIO_SATA_PREMEM_CONFIG
PortLane | PCH_HSIO_SATA_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_INFO_HOB Struct Reference

Public Attributes | List of all members
PCH_INFO_HOB Struct Reference

This structure is used to provide the information of PCH controller. More...

#include <PchInfoHob.h>

Public Attributes

UINT8 | Revision
This member specifies the revision of the PCH Info HOB. More...
UINT8 | Thc0Strap
THC strap disable/enable status.
UINT32 | PciePortLaneEnabled
Bit map for PCIe Root Port Lane setting. More...
UINT32 | HpetBusNum: 8
Publish Hpet BDF and IoApic BDF information for VTD.
UINT32 | CridOrgRid: 8
Publish the CRID information.
UINT32 | AudioDspFusedOut: 1
Publish the HDA information.

Detailed Description

This structure is used to provide the information of PCH controller.

Revision 1:

  • Initial version. Revision 2:
  • Add CridSupport, CridOrgRid, and CridNewRid. Revision 3:
  • Add Thc0Strap. Revision 4
  • Removed GbePciePortNumber Revision 5
  • Add AudioDspFusedOut

Definition at line 59 of file PchInfoHob.h.

Member Data Documentation

◆ PciePortLaneEnabled

UINT32 PCH_INFO_HOB::PciePortLaneEnabled

Bit map for PCIe Root Port Lane setting.

If bit is set it means that corresponding Root Port has its lane enabled. BIT0 - RP0, BIT1 - RP1, ... This information needs to be passed through HOB as FIA registers are not accessible with POSTBOOT_SAI

Definition at line 80 of file PchInfoHob.h.

◆ Revision

UINT8 PCH_INFO_HOB::Revision

This member specifies the revision of the PCH Info HOB.

This field is used to indicate backwards compatible changes to the protocol. Platform code that consumes this protocol must read the correct revision value to correctly interpret the content of the protocol fields.

Definition at line 66 of file PchInfoHob.h.

The documentation for this struct was generated from the following file:
  • PchInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_INFO_HOB Member List

This is the complete list of members for PCH_INFO_HOB, including all inherited members.

AudioDspFusedOut | PCH_INFO_HOB
CridOrgRid | PCH_INFO_HOB
HpetBusNum | PCH_INFO_HOB
PciePortLaneEnabled | PCH_INFO_HOB
Revision | PCH_INFO_HOB
Thc0Strap | PCH_INFO_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_INTERRUPT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_INTERRUPT_CONFIG Struct Reference

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

#include <InterruptConfig.h>

Collaboration diagram for PCH_INTERRUPT_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | NumOfDevIntConfig
Number of entries in DevIntConfig table.
UINT8 | Rsvd0 [3]
Reserved bytes, align to multiple 4.
PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig [PCH_MAX_DEVICE_INTERRUPT_CONFIG]
Array which stores PCH devices interrupts settings.
UINT8 | GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
UINT8 | SciIrqSelect
Interrupt select for SCI. Default is 9.
UINT8 | TcoIrqSelect
Interrupt select for TCO. Default is 9.
UINT8 | TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.

Detailed Description

The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.

Definition at line 73 of file InterruptConfig.h.

The documentation for this struct was generated from the following file:
  • InterruptConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_INTERRUPT_CONFIG Member List

This is the complete list of members for PCH_INTERRUPT_CONFIG, including all inherited members.

DevIntConfig | PCH_INTERRUPT_CONFIG
GpioIrqRoute | PCH_INTERRUPT_CONFIG
Header | PCH_INTERRUPT_CONFIG
NumOfDevIntConfig | PCH_INTERRUPT_CONFIG
Rsvd0 | PCH_INTERRUPT_CONFIG
SciIrqSelect | PCH_INTERRUPT_CONFIG
TcoIrqEnable | PCH_INTERRUPT_CONFIG
TcoIrqSelect | PCH_INTERRUPT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_IOAPIC_CONFIG Struct Reference

Public Attributes | List of all members
PCH_IOAPIC_CONFIG Struct Reference

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

#include <IoApicConfig.h>

Collaboration diagram for PCH_IOAPIC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | IoApicEntry24_119: 1
0: Disable; 1: Enable IOAPIC Entry 24-119
UINT32 | Enable8254ClockGating: 1
Enable 8254 Static Clock Gating during early POST time. More...
UINT32 | Enable8254ClockGatingOnS3: 1
Enable 8254 Static Clock Gating on S3 resume path. More...
UINT32 | RsvdBits1: 29
Reserved bits.
UINT8 | IoApicId
This member determines IOAPIC ID. Default is 0x02.
UINT8 | Rsvd0 [3]
Reserved bytes.

Detailed Description

The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE.

Bus:device:function fields will be programmed to the register P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose: As the Requester ID when initiating Interrupt Messages to the processor. As the Completer ID when responding to the reads targeting the IOxAPI's Memory-Mapped I/O registers. This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can program this field to provide a unique Bus:Device:Function number for the internal IOxAPIC. The address resource range of IOAPIC must be reserved in E820 and ACPI as system resource.

Definition at line 57 of file IoApicConfig.h.

Member Data Documentation

◆ Enable8254ClockGating

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGating

Enable 8254 Static Clock Gating during early POST time.

0: Disable, 1: Enable Setting 8254CGE is required to support SLP_S0. Enable this if 8254 timer is not used. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer.

Note
: For some OS environment that it needs to set 8254CGE in late state it should set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later. This is also required during S3 resume. To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.

Definition at line 73 of file IoApicConfig.h.

◆ Enable8254ClockGatingOnS3

UINT32 PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3

Enable 8254 Static Clock Gating on S3 resume path.

0: Disable, 1: Enable This is only applicable when Enable8254ClockGating is disabled. If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on S3 resume path as well.

Definition at line 80 of file IoApicConfig.h.

The documentation for this struct was generated from the following file:
  • IoApicConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_IOAPIC_CONFIG Member List

This is the complete list of members for PCH_IOAPIC_CONFIG, including all inherited members.

Enable8254ClockGating | PCH_IOAPIC_CONFIG
Enable8254ClockGatingOnS3 | PCH_IOAPIC_CONFIG
Header | PCH_IOAPIC_CONFIG
IoApicEntry24_119 | PCH_IOAPIC_CONFIG
IoApicId | PCH_IOAPIC_CONFIG
Rsvd0 | PCH_IOAPIC_CONFIG
RsvdBits1 | PCH_IOAPIC_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_LOCK_DOWN_CONFIG Struct Reference

Public Attributes | List of all members
PCH_LOCK_DOWN_CONFIG Struct Reference

The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement. More...

#include <LockDownConfig.h>

Collaboration diagram for PCH_LOCK_DOWN_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | GlobalSmi: 1
(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. More...
UINT32 | BiosInterface: 1
(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap bit and the General Control and Status Registers Boot BIOS Straps. More...
UINT32 | BiosLock: 1
Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
UINT32 | SpiEiss: 1
Separate EISS policy to be handled separately from BiosLock.
UINT32 | UnlockGpioPads: 1
(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to POSTBOOT_SAI. More...
UINT32 | RsvdBits0: 27
Reserved bits.

Detailed Description

The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement.

Definition at line 47 of file LockDownConfig.h.

Member Data Documentation

◆ BiosInterface

UINT32 PCH_LOCK_DOWN_CONFIG::BiosInterface

(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap bit and the General Control and Status Registers Boot BIOS Straps.

Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit will mitigate malicious software attempts to replace the system BIOS with its own code. 0: Disable; 1: Enable.

Definition at line 60 of file LockDownConfig.h.

◆ BiosLock

UINT32 PCH_LOCK_DOWN_CONFIG::BiosLock

Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection.

When it is enabled, the BIOS Region can only be modified from SMM. If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also in order to write to BIOS regions of SPI Flash. If this EISS bit is clear, then the InSMM.STS is a don't care. The BIOS must set the EISS bit while BIOS Guard support is enabled. In recovery path, platform can temporary disable EISS for SPI programming in PEI phase or early DXE phase. When PcdSmmVariableEnable is FALSE, to support BIOS regions update outside of SMM, the BiosLock must be set to Disabled by platform. 0: Disable; 1: Enable.

Definition at line 75 of file LockDownConfig.h.

◆ GlobalSmi

UINT32 PCH_LOCK_DOWN_CONFIG::GlobalSmi

(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.

0: Disable; 1: Enable.

Definition at line 52 of file LockDownConfig.h.

◆ UnlockGpioPads

UINT32 PCH_LOCK_DOWN_CONFIG::UnlockGpioPads

(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to POSTBOOT_SAI.

This option should not be enabled in production configuration and used only for debug purpose when free runtime reconfiguration of GPIO pads is needed. 0: Disable; 1: Enable.

Definition at line 84 of file LockDownConfig.h.

The documentation for this struct was generated from the following file:
  • LockDownConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_LOCK_DOWN_CONFIG Member List

This is the complete list of members for PCH_LOCK_DOWN_CONFIG, including all inherited members.

BiosInterface | PCH_LOCK_DOWN_CONFIG
BiosLock | PCH_LOCK_DOWN_CONFIG
GlobalSmi | PCH_LOCK_DOWN_CONFIG
Header | PCH_LOCK_DOWN_CONFIG
RsvdBits0 | PCH_LOCK_DOWN_CONFIG
SpiEiss | PCH_LOCK_DOWN_CONFIG
UnlockGpioPads | PCH_LOCK_DOWN_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_LPC_GEN_IO_RANGE Struct Reference

List of all members
PCH_LPC_GEN_IO_RANGE Struct Reference

structure of LPC general IO range register It contains base address, address mask, and enable status. More...

#include <PchCycleDecodingLib.h>

Detailed Description

structure of LPC general IO range register It contains base address, address mask, and enable status.

Definition at line 74 of file PchCycleDecodingLib.h.

The documentation for this struct was generated from the following file:
  • PchCycleDecodingLib.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_LPC_GEN_IO_RANGE Member List

This is the complete list of members for PCH_LPC_GEN_IO_RANGE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_LPC_GEN_IO_RANGE_LIST Struct Reference

List of all members
PCH_LPC_GEN_IO_RANGE_LIST Struct Reference

structure of LPC general IO range register list It lists all LPC general IO ran registers supported by PCH. More...

#include <PchCycleDecodingLib.h>

Collaboration diagram for PCH_LPC_GEN_IO_RANGE_LIST:
[legend]

Detailed Description

structure of LPC general IO range register list It lists all LPC general IO ran registers supported by PCH.

Definition at line 87 of file PchCycleDecodingLib.h.

The documentation for this struct was generated from the following file:
  • PchCycleDecodingLib.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_LPC_GEN_IO_RANGE_LIST Member List

This is the complete list of members for PCH_LPC_GEN_IO_RANGE_LIST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_LPC_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_LPC_PREMEM_CONFIG Struct Reference

This structure contains the policies which are related to LPC. More...

#include <LpcConfig.h>

Collaboration diagram for PCH_LPC_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | EnhancePort8xhDecoding: 1
Enhance the port 8xh decoding. More...
UINT32 | LpcPmHAE: 1
Hardware Autonomous Enable. More...
UINT32 | RsvdBits: 30
Reserved bits.

Detailed Description

This structure contains the policies which are related to LPC.

Definition at line 46 of file LpcConfig.h.

Member Data Documentation

◆ EnhancePort8xhDecoding

UINT32 PCH_LPC_PREMEM_CONFIG::EnhancePort8xhDecoding

Enhance the port 8xh decoding.

Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.

Note
: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00. 0: Disable, 1: Enable

Definition at line 54 of file LpcConfig.h.

◆ LpcPmHAE

UINT32 PCH_LPC_PREMEM_CONFIG::LpcPmHAE

Hardware Autonomous Enable.

When enabled, LPC will automatically engage power gating when it has reached its idle condition. 0: Disable, 1: Enable

Definition at line 60 of file LpcConfig.h.

The documentation for this struct was generated from the following file:
  • LpcConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_LPC_PREMEM_CONFIG Member List

This is the complete list of members for PCH_LPC_PREMEM_CONFIG, including all inherited members.

EnhancePort8xhDecoding | PCH_LPC_PREMEM_CONFIG
Header | PCH_LPC_PREMEM_CONFIG
LpcPmHAE | PCH_LPC_PREMEM_CONFIG
RsvdBits | PCH_LPC_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_MEMORY_THROTTLING Struct Reference

Public Attributes | List of all members
PCH_MEMORY_THROTTLING Struct Reference

This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). More...

#include <ThermalConfig.h>

Collaboration diagram for PCH_MEMORY_THROTTLING:
[legend]

Public Attributes

UINT32 | Enable: 1
This will enable PCH memory throttling. More...
TS_GPIO_PIN_SETTING | TsGpioPinSetting [2]
GPIO_C and GPIO_D selection for memory throttling. More...

Detailed Description

This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).

Definition at line 126 of file ThermalConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_MEMORY_THROTTLING::Enable

This will enable PCH memory throttling.

While this policy is enabled, must also enable EnableExtts in SA policy. 0: Disable; 1: Enable

Definition at line 132 of file ThermalConfig.h.

◆ TsGpioPinSetting

TS_GPIO_PIN_SETTING PCH_MEMORY_THROTTLING::TsGpioPinSetting[2]

GPIO_C and GPIO_D selection for memory throttling.

It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature, and route EXTTS# accordingly.

Definition at line 139 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_MEMORY_THROTTLING Member List

This is the complete list of members for PCH_MEMORY_THROTTLING, including all inherited members.

Enable | PCH_MEMORY_THROTTLING
TsGpioPinSetting | PCH_MEMORY_THROTTLING
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_P2SB_CONFIG Struct Reference

Public Attributes | List of all members
PCH_P2SB_CONFIG Struct Reference

This structure contains the policies which are related to P2SB device. More...

#include <P2sbConfig.h>

Collaboration diagram for PCH_P2SB_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | SbAccessUnlock: 1
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution. More...
UINT32 | Rsvdbits: 31
Reserved bits.

Detailed Description

This structure contains the policies which are related to P2SB device.

Definition at line 46 of file P2sbConfig.h.

Member Data Documentation

◆ SbAccessUnlock

UINT32 PCH_P2SB_CONFIG::SbAccessUnlock

(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execution.

Currently it disables PSFx access. This policy unlocks the sideband MMIO space for those IPs. 0: Lock sideband access ; 1: Unlock sideband access. NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.

Definition at line 56 of file P2sbConfig.h.

The documentation for this struct was generated from the following file:
  • P2sbConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_P2SB_CONFIG Member List

This is the complete list of members for PCH_P2SB_CONFIG, including all inherited members.

Header | PCH_P2SB_CONFIG
Rsvdbits | PCH_P2SB_CONFIG
SbAccessUnlock | PCH_P2SB_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_PCIE_CLOCK Struct Reference

Public Attributes | List of all members
PCH_PCIE_CLOCK Struct Reference

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
UINT8 | ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
UINT8 | RsvdBytes [2]
Reserved byte.

Detailed Description

PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.

Definition at line 177 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_PCIE_CLOCK Member List

This is the complete list of members for PCH_PCIE_CLOCK, including all inherited members.

ClkReq | PCH_PCIE_CLOCK
RsvdBytes | PCH_PCIE_CLOCK
Usage | PCH_PCIE_CLOCK
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_PCIE_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_CONFIG Struct Reference

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)

Detailed Description

The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1:

  • Initial version. Revision 2:
  • Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG

Definition at line 221 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_PCIE_CONFIG Member List

This is the complete list of members for PCH_PCIE_CONFIG, including all inherited members.

Header | PCH_PCIE_CONFIG
PchPciePort8xhDecodePortIndex | PCH_PCIE_CONFIG
PcieCommonConfig | PCH_PCIE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_ROOT_PORT_CONFIG Struct Reference

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...

#include <PchPcieRpConfig.h>

Public Attributes

UINT8 | ExtSync
an instance of Pcie Common Config More...
UINT8 | SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
UINT8 | MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC. More...
UINT8 | VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed. More...
UINT8 | VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
UINT8 | RsvdBytes0 [3]
Reserved bytes.

Detailed Description

The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.

Definition at line 188 of file PchPcieRpConfig.h.

Member Data Documentation

◆ ExtSync

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::ExtSync

an instance of Pcie Common Config

Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.

Definition at line 190 of file PchPcieRpConfig.h.

◆ MvcEnabled

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled

The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.

Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0, RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be disabled. 0: Disable; 1: Enable

Definition at line 203 of file PchPcieRpConfig.h.

◆ VppPort

UINT8 PCH_PCIE_ROOT_PORT_CONFIG::VppPort

Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins expansion is needed.

It is server specific feature. 0x00: Default; 0xFF: Disabled

Definition at line 209 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_PCIE_ROOT_PORT_CONFIG Member List

This is the complete list of members for PCH_PCIE_ROOT_PORT_CONFIG, including all inherited members.

ExtSync | PCH_PCIE_ROOT_PORT_CONFIG
MvcEnabled | PCH_PCIE_ROOT_PORT_CONFIG
RsvdBytes0 | PCH_PCIE_ROOT_PORT_CONFIG
SystemErrorEnable | PCH_PCIE_ROOT_PORT_CONFIG
VppAddress | PCH_PCIE_ROOT_PORT_CONFIG
VppPort | PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PCIE_RP_PREMEM_CONFIG Struct Reference

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCH_PCIE_RP_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | RpEnabledMask
Root Port enabling mask. More...
PCH_PCIE_CLOCK | PcieClock [PCH_MAX_PCIE_CLOCKS]
Configuration of PCIe source clocks.
UINT8 | Bifurcation [PCH_MAX_PCIE_CONTROLLERS]
Per Controller Bifurcation Configuration 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)

Detailed Description

The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1:

  • Initial version.

Definition at line 243 of file PchPcieRpConfig.h.

Member Data Documentation

◆ RpEnabledMask

UINT32 PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask

Root Port enabling mask.

Bit0 presents RP1, Bit1 presents RP2, and so on. 0: Disable; 1: Enable.

Definition at line 250 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_PCIE_RP_PREMEM_CONFIG Member List

This is the complete list of members for PCH_PCIE_RP_PREMEM_CONFIG, including all inherited members.

Bifurcation | PCH_PCIE_RP_PREMEM_CONFIG
Header | PCH_PCIE_RP_PREMEM_CONFIG
PcieClock | PCH_PCIE_RP_PREMEM_CONFIG
RpEnabledMask | PCH_PCIE_RP_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_PM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_PM_CONFIG Struct Reference

The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...

#include <PmConfig.h>

Collaboration diagram for PCH_PM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
UINT32 | PchDeepSxPol: 4
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
UINT32 | PchSlpS3MinAssert: 4
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is PchSlpS350ms.
UINT32 | PchSlpS4MinAssert: 4
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is PchSlpS44s.
UINT32 | PchSlpSusMinAssert: 4
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is PchSlpSus4s.
UINT32 | PchSlpAMinAssert: 4
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is PchSlpA2s.
UINT32 | SlpStrchSusUp: 1
This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
UINT32 | SlpLanLowDc: 1
Enable/Disable SLP_LAN# Low on DC Power. More...
UINT32 | PwrBtnOverridePeriod: 3
PCH power button override period. More...
UINT32 | DisableEnergyReport: 1
(Test) Disable/Enable PCH to CPU enery report feature. More...
UINT32 | DisableDsxAcPresentPulldown: 1
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
UINT32 | DisableNativePowerButton: 1
Power button native mode disable. More...
UINT32 | MeWakeSts: 1
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | WolOvrWkSts: 1
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
UINT32 | PsOnEnable: 1
Decide if PS_ON is to be enabled. More...
UINT32 | CpuC10GatePinEnable: 1
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. More...
UINT32 | PmcDbgMsgEn: 1
Control whether to enable PMC debug messages to Trace Hub. More...
UINT32 | ModPhySusPgEnable: 1
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. More...
UINT32 | Usb2PhySusPgEnable: 1
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality. More...
UINT32 | OsIdleEnable: 1
Enable Os Idle Mode. More...
UINT32 | V1p05PhyExtFetControlEn: 1
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
UINT32 | V1p05IsExtFetControlEn: 1
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: Enable.
UINT32 | S0ixAutoDemotion: 1
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature. More...
UINT32 | LatchEventsC10Exit: 1
Enable/Disable Latch Events C10 Exit. More...
UINT8 | PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second. More...
UINT8 | PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units. More...
UINT8 | C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode. More...
UINT8 | Rsvd0 [1]
Reserved bytes.
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config. More...
UINT8 | GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks. More...
UINT8 | Rsvd1 [3]
Reserved bytes.
UINT32 | ThermTimerDelay: 10
PMC Therm Timer Delay Register (THERM_TIMER_DELAY). More...

Detailed Description

The PCH_PM_CONFIG block describes expected miscellaneous power management settings.

The PowerResetStatusClear field would clear the Power/Reset status bits, please set the bits if you want PCH Init driver to clear it, if you want to check the status later then clear the bits.

Revision 1:

  • Initial version. Revision 2
  • Added C10DynamicThresholdAdjustment Revision 3:
  • Added SkipVccInConfig

Definition at line 229 of file PmConfig.h.

Member Data Documentation

◆ C10DynamicThresholdAdjustment

UINT8 PCH_PM_CONFIG::C10DynamicThresholdAdjustment

Tells BIOS to enable C10 dynamic threshold adjustment mode.

BIOS will only attemt to enable it on PCH SKUs which support it.

Definition at line 411 of file PmConfig.h.

◆ CpuC10GatePinEnable

UINT32 PCH_PM_CONFIG::CpuC10GatePinEnable

Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin.

This policy needs to be set if board design includes support for CPU_C10_GATE# pin. 0: Disable; 1: Enable

Definition at line 315 of file PmConfig.h.

◆ DisableDsxAcPresentPulldown

UINT32 PCH_PM_CONFIG::DisableDsxAcPresentPulldown

When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.

When set to Enable, PCH will not pull down AC_PRESENT. This setting is ignored when DeepSx is not supported. Default is 0:Disable

Definition at line 276 of file PmConfig.h.

◆ DisableEnergyReport

UINT32 PCH_PM_CONFIG::DisableEnergyReport

(Test) Disable/Enable PCH to CPU enery report feature.

0: Disable; 1: Enable. Enery Report is must have feature. Wihtout Energy Report, the performance report by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted in power/performance management algorithm. If for some reason PCH energy report is too high, which forces CPU to try to reduce its power by throttling, then it could try to disable Energy Report to do first debug. This might be due to energy scaling factors are not correct or the LPM settings are not kicking in.

Definition at line 269 of file PmConfig.h.

◆ DisableNativePowerButton

UINT32 PCH_PM_CONFIG::DisableNativePowerButton

Power button native mode disable.

While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal. While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted. Default is FALSE.

Definition at line 283 of file PmConfig.h.

◆ GlobalResetMasksOverride

UINT8 PCH_PM_CONFIG::GlobalResetMasksOverride

Set true to enable override of Global Reset Event/Trigger masks.

Values from GlobalResetTriggerMask and GlobalResetEventMask will be used as override value. 0: Disable, 1: Enable

Definition at line 445 of file PmConfig.h.

◆ LatchEventsC10Exit

UINT32 PCH_PM_CONFIG::LatchEventsC10Exit

Enable/Disable Latch Events C10 Exit.

When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured on C10 exit (instead of C10 entry which is default) 0: Disable; 1: Enable.

Definition at line 371 of file PmConfig.h.

◆ LpmS0ixSubStateEnable

PMC_LPM_S0IX_SUB_STATE_EN PCH_PM_CONFIG::LpmS0ixSubStateEnable

(Test) Low Power Mode Enable/Disable config.

Configure if respective S0i2/3 sub-states are to be supported by the platform. By default all sub-states are enabled but for test purpose respective states can be disabled. Default is 0xFF

Definition at line 421 of file PmConfig.h.

◆ ModPhySusPgEnable

UINT32 PCH_PM_CONFIG::ModPhySusPgEnable

Enable/Disable ModPHY SUS Power Domain Dynamic Gating.

EXT_PWR_GATE# signal (if supported on platform) can be used to control external FET for power gating ModPHY

Note
: This setting is not supported and ignored on PCH-H 0: Disable; 1: Enable.

Definition at line 331 of file PmConfig.h.

◆ OsIdleEnable

UINT32 PCH_PM_CONFIG::OsIdleEnable

Enable Os Idle Mode.

0: Disable; 1: Enable.

Definition at line 344 of file PmConfig.h.

◆ PchPwrCycDur

UINT8 PCH_PM_CONFIG::PchPwrCycDur

Reset Power Cycle Duration could be customized in the unit of second.

Please refer to EDS for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. And make sure the setting correct, which never less than the following register.

  • GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
  • GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
  • PWRM_CFG.SLP_A_MIN_ASST_WDTH
  • PWRM_CFG.SLP_LAN_MIN_ASST_WDTH

Definition at line 398 of file PmConfig.h.

◆ PciePllSsc

UINT8 PCH_PM_CONFIG::PciePllSsc

Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units.

Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% The default is 0xFF: AUTO - No BIOS override.

Definition at line 406 of file PmConfig.h.

◆ PmcDbgMsgEn

UINT32 PCH_PM_CONFIG::PmcDbgMsgEn

Control whether to enable PMC debug messages to Trace Hub.

When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub.

Note
: When enabled, system may not enter S0ix 0: Disable; 1: Enable.

Definition at line 323 of file PmConfig.h.

◆ PsOnEnable

UINT32 PCH_PM_CONFIG::PsOnEnable

Decide if PS_ON is to be enabled.

This is available on desktop only. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled.} 0: Disable; 1: Enable.

Definition at line 308 of file PmConfig.h.

◆ PwrBtnOverridePeriod

UINT32 PCH_PM_CONFIG::PwrBtnOverridePeriod

PCH power button override period.

000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s Default is 0: 4s

Definition at line 257 of file PmConfig.h.

◆ S0ixAutoDemotion

UINT32 PCH_PM_CONFIG::S0ixAutoDemotion

Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.

This feature enables the PMC to autonomously manage the deepest allowed S0ix substate to combat thrashing between power management states. 0: Disable; 1: Enable.

Definition at line 364 of file PmConfig.h.

◆ SlpLanLowDc

UINT32 PCH_PM_CONFIG::SlpLanLowDc

Enable/Disable SLP_LAN# Low on DC Power.

0: Disable; 1: Enable. Configure On DC PHY Power Diable according to policy SlpLanLowDc. When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low. This indicates that LAN PHY should be powered off on battery mode. This will override the DC_PP_DIS setting by WolEnableOverride.

Definition at line 251 of file PmConfig.h.

◆ SlpStrchSusUp

UINT32 PCH_PM_CONFIG::SlpStrchSusUp

This member describes whether or not the LPC ClockRun feature of PCH should be enabled.

0: Disable; 1: Enable 0: Disable; 1: Enable SLP_X Stretching After SUS Well Power Up

Definition at line 243 of file PmConfig.h.

◆ ThermTimerDelay

UINT32 PCH_PM_CONFIG::ThermTimerDelay

PMC Therm Timer Delay Register (THERM_TIMER_DELAY).

Unit in us(microseconds). Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset Default is 500

Definition at line 460 of file PmConfig.h.

◆ Usb2PhySusPgEnable

UINT32 PCH_PM_CONFIG::Usb2PhySusPgEnable

(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.

Note
: This setting is not supported and ignored on PCH-H 0: disable USB2 PHY SUS Well Power Gating 1: enable USB2 PHY SUS Well Power Gating

Definition at line 339 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_PM_CONFIG Member List

This is the complete list of members for PCH_PM_CONFIG, including all inherited members.

C10DynamicThresholdAdjustment | PCH_PM_CONFIG
CpuC10GatePinEnable | PCH_PM_CONFIG
DisableDsxAcPresentPulldown | PCH_PM_CONFIG
DisableEnergyReport | PCH_PM_CONFIG
DisableNativePowerButton | PCH_PM_CONFIG
GlobalResetMasksOverride | PCH_PM_CONFIG
Header | PCH_PM_CONFIG
LatchEventsC10Exit | PCH_PM_CONFIG
LpmS0ixSubStateEnable | PCH_PM_CONFIG
MeWakeSts | PCH_PM_CONFIG
ModPhySusPgEnable | PCH_PM_CONFIG
OsIdleEnable | PCH_PM_CONFIG
PchDeepSxPol | PCH_PM_CONFIG
PchPwrCycDur | PCH_PM_CONFIG
PchSlpAMinAssert | PCH_PM_CONFIG
PchSlpS3MinAssert | PCH_PM_CONFIG
PchSlpS4MinAssert | PCH_PM_CONFIG
PchSlpSusMinAssert | PCH_PM_CONFIG
PciePllSsc | PCH_PM_CONFIG
PmcDbgMsgEn | PCH_PM_CONFIG
PsOnEnable | PCH_PM_CONFIG
PwrBtnOverridePeriod | PCH_PM_CONFIG
Rsvd0 | PCH_PM_CONFIG
Rsvd1 | PCH_PM_CONFIG
S0ixAutoDemotion | PCH_PM_CONFIG
SlpLanLowDc | PCH_PM_CONFIG
SlpStrchSusUp | PCH_PM_CONFIG
ThermTimerDelay | PCH_PM_CONFIG
Usb2PhySusPgEnable | PCH_PM_CONFIG
V1p05IsExtFetControlEn | PCH_PM_CONFIG
V1p05PhyExtFetControlEn | PCH_PM_CONFIG
WakeConfig | PCH_PM_CONFIG
WolOvrWkSts | PCH_PM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_POLICY_PROTOCOL Struct Reference

List of all members
PCH_POLICY_PROTOCOL Struct Reference

PCH DXE Policy. More...

#include <PchPolicy.h>

Collaboration diagram for PCH_POLICY_PROTOCOL:
[legend]

Detailed Description

PCH DXE Policy.

The PCH_POLICY_PROTOCOL producer drvier is recommended to set all the PCH_POLICY_PROTOCOL size buffer zero before init any member parameter, this clear step can make sure no random value for those unknown new version parameters.

Make sure to update the Revision if any change to the protocol, including the existing internal structure definations.
Note: Here revision will be bumped up when adding/removing any config block under this structure.
Revision 1:

  • Initial version.

Definition at line 62 of file PchPolicy.h.

The documentation for this struct was generated from the following file:
  • PchPolicy.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_POLICY_PROTOCOL Member List

This is the complete list of members for PCH_POLICY_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_SATA_PORT_CONFIG Struct Reference

Public Attributes | List of all members
PCH_SATA_PORT_CONFIG Struct Reference

This structure configures the features, property, and capability for each SATA port. More...

#include <SataConfig.h>

Public Attributes

UINT32 | Enable: 1
Enable SATA port. More...
UINT32 | HotPlug: 1
0: Disable; 1: Enable
UINT32 | InterlockSw: 1
0: Disable; 1: Enable
UINT32 | External: 1
0: Disable; 1: Enable
UINT32 | SpinUp: 1
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
UINT32 | SolidStateDrive: 1
0: HDD; 1: SSD
UINT32 | DevSlp: 1
0: Disable; 1: Enable DEVSLP on the port
UINT32 | EnableDitoConfig: 1
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
UINT32 | DmVal: 4
DITO multiplier. Default is 15.
UINT32 | DitoVal: 10
DEVSLP Idle Timeout (DITO), Default is 625.
UINT32 | ZpOdd: 1
Support zero power ODD 0: Disable, 1: Enable. More...
UINT32 | DevSlpResetConfig: 4
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
UINT32 | SataPmPtm: 1
Deprecated.
UINT32 | RxPolarity: 1
0: Disable; 1: Enable; Rx Polarity
UINT32 | RsvdBits0: 3
Reserved fields for future expansion w/o protocol change.

Detailed Description

This structure configures the features, property, and capability for each SATA port.

Definition at line 75 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SATA_PORT_CONFIG::Enable

Enable SATA port.

It is highly recommended to disable unused ports for power savings 0: Disable; 1: Enable

Definition at line 80 of file SataConfig.h.

◆ ZpOdd

UINT32 PCH_SATA_PORT_CONFIG::ZpOdd

Support zero power ODD 0: Disable, 1: Enable.

This is also used to disable ModPHY dynamic power gate.

Definition at line 94 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_SATA_PORT_CONFIG Member List

This is the complete list of members for PCH_SATA_PORT_CONFIG, including all inherited members.

DevSlp | PCH_SATA_PORT_CONFIG
DevSlpResetConfig | PCH_SATA_PORT_CONFIG
DitoVal | PCH_SATA_PORT_CONFIG
DmVal | PCH_SATA_PORT_CONFIG
Enable | PCH_SATA_PORT_CONFIG
EnableDitoConfig | PCH_SATA_PORT_CONFIG
External | PCH_SATA_PORT_CONFIG
HotPlug | PCH_SATA_PORT_CONFIG
InterlockSw | PCH_SATA_PORT_CONFIG
RsvdBits0 | PCH_SATA_PORT_CONFIG
RxPolarity | PCH_SATA_PORT_CONFIG
SataPmPtm | PCH_SATA_PORT_CONFIG
SolidStateDrive | PCH_SATA_PORT_CONFIG
SpinUp | PCH_SATA_PORT_CONFIG
ZpOdd | PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_SMBUS_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_SMBUS_PREMEM_CONFIG Struct Reference

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

#include <SmbusConfig.h>

Collaboration diagram for PCH_SMBUS_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Revision 1: Init version. More...
UINT32 | Enable: 1
This member describes whether or not the SMBus controller of PCH should be enabled. More...
UINT32 | ArpEnable: 1
Enable SMBus ARP support, 0: Disable; 1: Enable.
UINT32 | DynamicPowerGating: 1
(Test) Disable or Enable Smbus dynamic power gating.
UINT32 | SpdWriteDisable: 1
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. More...
UINT32 | SmbAlertEnable: 1
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
UINT32 | RsvdBits0: 27
Reserved bits.
UINT16 | SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
UINT8 | Rsvd0
Reserved bytes.
UINT8 | NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
UINT8 | RsvdSmbusAddressTable [PCH_MAX_SMBUS_RESERVED_ADDRESS]
Array of addresses reserved for non-ARP-capable SMBus devices.

Detailed Description

The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.

Definition at line 48 of file SmbusConfig.h.

Member Data Documentation

◆ Enable

UINT32 PCH_SMBUS_PREMEM_CONFIG::Enable

This member describes whether or not the SMBus controller of PCH should be enabled.

0: Disable; 1: Enable.

Definition at line 57 of file SmbusConfig.h.

◆ Header

CONFIG_BLOCK_HEADER PCH_SMBUS_PREMEM_CONFIG::Header

Revision 1: Init version.

Config Block Header

Definition at line 52 of file SmbusConfig.h.

◆ SpdWriteDisable

UINT32 PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable

(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.

For security recommendations, SPD write disable bit must be set.

Definition at line 64 of file SmbusConfig.h.

The documentation for this struct was generated from the following file:
  • SmbusConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_SMBUS_PREMEM_CONFIG Member List

This is the complete list of members for PCH_SMBUS_PREMEM_CONFIG, including all inherited members.

ArpEnable | PCH_SMBUS_PREMEM_CONFIG
DynamicPowerGating | PCH_SMBUS_PREMEM_CONFIG
Enable | PCH_SMBUS_PREMEM_CONFIG
Header | PCH_SMBUS_PREMEM_CONFIG
NumRsvdSmbusAddresses | PCH_SMBUS_PREMEM_CONFIG
Rsvd0 | PCH_SMBUS_PREMEM_CONFIG
RsvdBits0 | PCH_SMBUS_PREMEM_CONFIG
RsvdSmbusAddressTable | PCH_SMBUS_PREMEM_CONFIG
SmbAlertEnable | PCH_SMBUS_PREMEM_CONFIG
SmbusIoBase | PCH_SMBUS_PREMEM_CONFIG
SpdWriteDisable | PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_TRACE_HUB_PREMEM_CONFIG Struct Reference

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...

#include <TraceHubConfig.h>

Collaboration diagram for PCH_TRACE_HUB_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.

Detailed Description

PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version.

Definition at line 122 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_TRACE_HUB_PREMEM_CONFIG Member List

This is the complete list of members for PCH_TRACE_HUB_PREMEM_CONFIG, including all inherited members.

Header | PCH_TRACE_HUB_PREMEM_CONFIG
TraceHub | PCH_TRACE_HUB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_WAKE_CONFIG Struct Reference

Public Attributes | List of all members
PCH_WAKE_CONFIG Struct Reference

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...

#include <PmConfig.h>

Public Attributes

UINT32 | PmeB0S5Dis: 1
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. More...
UINT32 | WolEnableOverride: 1
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; 1: Enable.
UINT32 | PcieWakeFromDeepSx: 1
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
UINT32 | WoWlanEnable: 1
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | WoWlanDeepSxEnable: 1
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0: Disable; 1: Enable.
UINT32 | LanWakeFromDeepSx: 1
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.

Detailed Description

This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.

Definition at line 51 of file PmConfig.h.

Member Data Documentation

◆ PmeB0S5Dis

UINT32 PCH_WAKE_CONFIG::PmeB0S5Dis

Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.

When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN. When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. 0: Disable; 1: Enable.

Definition at line 57 of file PmConfig.h.

The documentation for this struct was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_WAKE_CONFIG Member List

This is the complete list of members for PCH_WAKE_CONFIG, including all inherited members.

LanWakeFromDeepSx | PCH_WAKE_CONFIG
PcieWakeFromDeepSx | PCH_WAKE_CONFIG
PmeB0S5Dis | PCH_WAKE_CONFIG
WolEnableOverride | PCH_WAKE_CONFIG
WoWlanDeepSxEnable | PCH_WAKE_CONFIG
WoWlanEnable | PCH_WAKE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCH_WDT_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCH_WDT_PREMEM_CONFIG Struct Reference

This policy clears status bits and disable watchdog, then lock the WDT registers. More...

#include <WatchDogConfig.h>

Collaboration diagram for PCH_WDT_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 DisableAndLock: 1
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.

Detailed Description

This policy clears status bits and disable watchdog, then lock the WDT registers.

while WDT is designed to be disabled and locked by Policy, bios should not enable WDT by WDT PPI. In such case, bios shows the warning message but not disable and lock WDT register to make sure WDT event trigger correctly.

Definition at line 51 of file WatchDogConfig.h.

The documentation for this struct was generated from the following file:
  • WatchDogConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCH_WDT_PREMEM_CONFIG Member List

This is the complete list of members for PCH_WDT_PREMEM_CONFIG, including all inherited members.

DisableAndLock | PCH_WDT_PREMEM_CONFIG
Header | PCH_WDT_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_COMMON_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_COMMON_CONFIG Struct Reference

PCIe Common Config. More...

#include <PcieConfig.h>

Collaboration diagram for PCIE_COMMON_CONFIG:
[legend]

Public Attributes

UINT32 | RpFunctionSwap: 1
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
UINT32 | ComplianceTestMode: 1
Compliance Test Mode shall be enabled when using Compliance Load Board. More...
UINT32 | RsvdBits0: 30
Reserved bits.
UINT8 | EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled. More...
PCIE_EQ_PARAM | HwEqGen3CoeffList [PCIE_HWEQ_COEFFS_MAX]
List of coefficients used during equalization (applicable to both software and hardware EQ) Deprecated Policy.

Detailed Description

PCIe Common Config.

Note
This structure will be expanded to hold all common PCIe policies between SA and PCH

Definition at line 287 of file PcieConfig.h.

Member Data Documentation

◆ ComplianceTestMode

UINT32 PCIE_COMMON_CONFIG::ComplianceTestMode

Compliance Test Mode shall be enabled when using Compliance Load Board.

0: Disable, 1: Enable

Definition at line 308 of file PcieConfig.h.

◆ EnablePort8xhDecode

UINT8 PCIE_COMMON_CONFIG::EnablePort8xhDecode

(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.

0: Disable; 1: Enable.

Definition at line 313 of file PcieConfig.h.

◆ RpFunctionSwap

UINT32 PCIE_COMMON_CONFIG::RpFunctionSwap

RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.

A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement, BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.

  • Enabled: One of enabled root ports get assigned to Function0. This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
  • Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used. That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17. NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy In other words, it only affects ports that would become hidden because they have no device connected. NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY be used when each one of root ports 1, 9, 17:
    • is configured as PCIe and has correctly configured ClkReq signal, or
    • does not own any mPhy lanes (they are configured as SATA or USB)

Definition at line 303 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_COMMON_CONFIG Member List

This is the complete list of members for PCIE_COMMON_CONFIG, including all inherited members.

ComplianceTestMode | PCIE_COMMON_CONFIG
EnablePort8xhDecode | PCIE_COMMON_CONFIG
HwEqGen3CoeffList | PCIE_COMMON_CONFIG
RpFunctionSwap | PCIE_COMMON_CONFIG
RsvdBits0 | PCIE_COMMON_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_DEVICE_OVERRIDE Struct Reference

Public Attributes | List of all members
PCIE_DEVICE_OVERRIDE Struct Reference

PCIe device table entry entry. More...

#include <PcieConfig.h>

Public Attributes

UINT16 | VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
UINT16 | DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
UINT8 | RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
UINT8 | BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
UINT8 | SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
UINT8 | EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field to take effect.
UINT16 | OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
UINT16 | L1SubstatesCapOffset
The L1Substates Capability Offset Override. More...
UINT8 | L1SubstatesCapMask
L1 Substate Capability Mask. More...
UINT8 | L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override. More...
UINT8 | L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override. More...
UINT8 | L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override. More...
UINT16 | SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT16 | NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0. More...
UINT8 | ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism. More...

Detailed Description

PCIe device table entry entry.

The PCIe device table is being used to override PCIe device ASPM settings. To take effect table consisting of such entries must be instelled as PPI on gPchPcieDeviceTablePpiGuid. Last entry VendorId must be 0.

Definition at line 337 of file PcieConfig.h.

Member Data Documentation

◆ ForceLtrOverride

UINT8 PCIE_DEVICE_OVERRIDE::ForceLtrOverride

Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message This settings allows force override of LTR mechanism.

If it's enabled, then: rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored

Definition at line 431 of file PcieConfig.h.

◆ L1sCommonModeRestoreTime

UINT8 PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime

L1 Substate Port Common Mode Restore Time Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 363 of file PcieConfig.h.

◆ L1sTpowerOnScale

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale

L1 Substate Port Tpower_on Scale Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 370 of file PcieConfig.h.

◆ L1sTpowerOnValue

UINT8 PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue

L1 Substate Port Tpower_on Value Override.

(applicable if bit 2 is set in OverrideConfig) L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue. If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored, and only L1SubstatesCapOffset is override.

Definition at line 377 of file PcieConfig.h.

◆ L1SubstatesCapMask

UINT8 PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask

L1 Substate Capability Mask.

(applicable if bit 2 is set in OverrideConfig) Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override. Only bit [3:0] are applicable. Other bits are ignored.

Definition at line 356 of file PcieConfig.h.

◆ L1SubstatesCapOffset

UINT16 PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset

The L1Substates Capability Offset Override.

(applicable if bit 2 is set in OverrideConfig) This field can be zero if only the L1 Substate value is going to be override.

Definition at line 350 of file PcieConfig.h.

◆ NonSnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::NonSnoopLatency

NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 422 of file PcieConfig.h.

◆ SnoopLatency

UINT16 PCIE_DEVICE_OVERRIDE::SnoopLatency

SnoopLatency bit definition Note: All Reserved bits must be set to 0.

BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid When clear values in bits 9:0 will be ignored BITS[14:13] - Reserved BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits 000b - 1 ns 001b - 32 ns 010b - 1024 ns 011b - 32,768 ns 100b - 1,048,576 ns 101b - 33,554,432 ns 110b - Reserved 111b - Reserved BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with the scale in bits 12:10

This field takes effect only if bit 3 is set in OverrideConfig.

Definition at line 400 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_DEVICE_OVERRIDE Member List

This is the complete list of members for PCIE_DEVICE_OVERRIDE, including all inherited members.

BaseClassCode | PCIE_DEVICE_OVERRIDE
DeviceId | PCIE_DEVICE_OVERRIDE
EndPointAspm | PCIE_DEVICE_OVERRIDE
ForceLtrOverride | PCIE_DEVICE_OVERRIDE
L1sCommonModeRestoreTime | PCIE_DEVICE_OVERRIDE
L1sTpowerOnScale | PCIE_DEVICE_OVERRIDE
L1sTpowerOnValue | PCIE_DEVICE_OVERRIDE
L1SubstatesCapMask | PCIE_DEVICE_OVERRIDE
L1SubstatesCapOffset | PCIE_DEVICE_OVERRIDE
NonSnoopLatency | PCIE_DEVICE_OVERRIDE
OverrideConfig | PCIE_DEVICE_OVERRIDE
RevId | PCIE_DEVICE_OVERRIDE
SnoopLatency | PCIE_DEVICE_OVERRIDE
SubClassCode | PCIE_DEVICE_OVERRIDE
VendorId | PCIE_DEVICE_OVERRIDE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_DXE_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_DXE_CONFIG Struct Reference

The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control for PEG ASPM. More...

#include <PcieDxeConfig.h>

Collaboration diagram for PCIE_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | PegAspm [SA_PEG_MAX_FUN]
Offset 28: This field is used to describe the ASPM control for PEG Ports
0=ASPM Disabled, 1=ASPM L0s Enabled, 2=ASPM L1 Enabled, 3=ASPM L0sL1 Enabled, 4=ASPM AUTO
UINT8 | PegRootPortHPE [SA_PEG_MAX_FUN]
Offset 32: PCIe Hot Plug Enable/Disable. More...
CPU_PCIE_PWR_OPT | PegPwrOpt [SA_PEG_MAX_FUN]
Offset 36: This field is used to describe the PCIe LTR/OBFF relevant settings.
UINT8 | CpuPcieRtd3
Deprecated Policy. More...

Detailed Description

The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control for PEG ASPM.

The data elements should be initialized by a Platform Module.

Note
Optional. These policies will be ignored if there is no PEG port present on board. Revision 1:
  • Initial version. Revision 2:
  • Adding PEG RTD3 Support Setup Variable Revision 3:
  • Adding CPU PCIE RTD3 Support Setup Variable
  • Deprecating PEG RTD3 Support Setup Variable Revision 4:
  • Deprecating CPU PCIE RTD3 Support Setup Variable

Definition at line 122 of file PcieDxeConfig.h.

Member Data Documentation

◆ CpuPcieRtd3

UINT8 PCIE_DXE_CONFIG::CpuPcieRtd3

Deprecated Policy.

Enable/Disable RTD3 Support for CPU PCIE. 0=Disable and 1=Enable (default) // Deprecated Policy

Definition at line 137 of file PcieDxeConfig.h.

◆ PegRootPortHPE

UINT8 PCIE_DXE_CONFIG::PegRootPortHPE[SA_PEG_MAX_FUN]

Offset 32: PCIe Hot Plug Enable/Disable.

It has 2 policies.

  • Disabled (0x0) : No hotplug.
  • Enabled (0x1) : Bios assist hotplug.

Definition at line 134 of file PcieDxeConfig.h.

The documentation for this struct was generated from the following file:
  • PcieDxeConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_DXE_CONFIG Member List

This is the complete list of members for PCIE_DXE_CONFIG, including all inherited members.

CpuPcieRtd3 | PCIE_DXE_CONFIG
Header | PCIE_DXE_CONFIG
PegAspm | PCIE_DXE_CONFIG
PegPwrOpt | PCIE_DXE_CONFIG
PegRootPortHPE | PCIE_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_EQ_PARAM Struct Reference

Public Attributes | List of all members
PCIE_EQ_PARAM Struct Reference

Represent lane specific PCIe Gen3 equalization parameters. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | Cm
Coefficient C-1.
UINT8 | Cp
Coefficient C+1.
UINT8 | Rsvd0 [2]
Reserved bytes.

Detailed Description

Represent lane specific PCIe Gen3 equalization parameters.

Definition at line 76 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_EQ_PARAM Member List

This is the complete list of members for PCIE_EQ_PARAM, including all inherited members.

Cm | PCIE_EQ_PARAM
Cp | PCIE_EQ_PARAM
Rsvd0 | PCIE_EQ_PARAM
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_GPIO Struct Reference

Public Attributes | List of all members
PCIE_GPIO Struct Reference

SA GPIO Data Structure. More...

#include <HgInfoHob.h>

Public Attributes

UINT8 | ExpanderNo
=Expander No For I2C based GPIO
UINT32 | GpioNo
GPIO pad.
BOOLEAN | Active
0=Active Low; 1=Active High

Detailed Description

SA GPIO Data Structure.

Definition at line 47 of file HgInfoHob.h.

The documentation for this struct was generated from the following file:
  • HgInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_GPIO Member List

This is the complete list of members for PCIE_GPIO, including all inherited members.

Active | PCIE_GPIO
ExpanderNo | PCIE_GPIO
GpioNo | PCIE_GPIO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_IMR_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_IMR_CONFIG Struct Reference

PCIe IMR Config. More...

#include <PciePreMemConfig.h>

Public Attributes

UINT8 | ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
UINT8 | ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
UINT16 | ImrSize
PCIe IMR size in megabytes.
UINT8 | ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)

Detailed Description

PCIe IMR Config.

Definition at line 53 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_IMR_CONFIG Member List

This is the complete list of members for PCIE_IMR_CONFIG, including all inherited members.

ImrEnabled | PCIE_IMR_CONFIG
ImrRpLocation | PCIE_IMR_CONFIG
ImrRpSelection | PCIE_IMR_CONFIG
ImrSize | PCIE_IMR_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

Public Attributes | List of all members
PCIE_LINK_EQ_PLATFORM_SETTINGS Struct Reference

PCIe Link EQ Platform Settings. More...

#include <PcieConfig.h>

Public Attributes

UINT8 | PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq.
UINT8 | PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC.
UINT8 | LocalTransmitterOverrideEnable
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process. More...
UINT8 | Ph3NumberOfPresetsOrCoefficients
Tells BIOS how many presets/coefficients should be used during link EQ. More...
PCIE_LINK_EQ_COEFFICIENTS | Ph3CoefficientsList [PCIE_LINK_EQ_COEFFICIENTS_MAX]
List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode.
UINT32 | Ph3PresetList [PCIE_LINK_EQ_PRESETS_MAX]
List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode.
UINT32 | Ph1DownstreamPortTransmitterPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.
UINT32 | Ph1UpstreamPortTransmitterPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes.
UINT32 | Ph2LocalTransmitterOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ process. More...
UINT32 | PCETTimer
PCET Timer value for single PCIe speed.
UINT8 | RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
UINT8 | EqPh3Bypass
PCIe Equalization Phase 3 Enable Control. More...
UINT8 | EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control. More...
UINT8 | TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer

Detailed Description

PCIe Link EQ Platform Settings.

Definition at line 132 of file PcieConfig.h.

Member Data Documentation

◆ EqPh23Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass

PCIe Equalization Phase 2-3 Enable Control.

  • Disabled (0x0) : Disable Phase 2 - Phase 3 (Default)
  • Enabled (0x1) : Enable Phase 2 - Phase 3

Definition at line 170 of file PcieConfig.h.

◆ EqPh3Bypass

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass

PCIe Equalization Phase 3 Enable Control.

  • Disabled (0x0) : Disable phase 3 (Default)
    • Enabled (0x1) : Enable phase 3

Definition at line 164 of file PcieConfig.h.

◆ LocalTransmitterOverrideEnable

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTransmitterOverrideEnable

Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.

If enabled value in Ph2LocalTransmitterOverridePreset must be valid. 0: Disabled; 1: Enabled

Definition at line 140 of file PcieConfig.h.

◆ Ph2LocalTransmitterOverridePreset

UINT32 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTransmitterOverridePreset

Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.

Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port. Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0< >

Definition at line 156 of file PcieConfig.h.

◆ Ph3NumberOfPresetsOrCoefficients

UINT8 PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NumberOfPresetsOrCoefficients

Tells BIOS how many presets/coefficients should be used during link EQ.

Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.

Definition at line 145 of file PcieConfig.h.

The documentation for this struct was generated from the following file:
  • PcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_LINK_EQ_PLATFORM_SETTINGS Member List

This is the complete list of members for PCIE_LINK_EQ_PLATFORM_SETTINGS, including all inherited members.

EqPh23Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
EqPh3Bypass | PCIE_LINK_EQ_PLATFORM_SETTINGS
LocalTransmitterOverrideEnable | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCETTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMethod | PCIE_LINK_EQ_PLATFORM_SETTINGS
PcieLinkEqMode | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1DownstreamPortTransmitterPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph1UpstreamPortTransmitterPreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph2LocalTransmitterOverridePreset | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3CoefficientsList | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3NumberOfPresetsOrCoefficients | PCIE_LINK_EQ_PLATFORM_SETTINGS
Ph3PresetList | PCIE_LINK_EQ_PLATFORM_SETTINGS
RemotePresetCoeffoverride | PCIE_LINK_EQ_PLATFORM_SETTINGS
TsLockTimer | PCIE_LINK_EQ_PLATFORM_SETTINGS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_PEI_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_PEI_CONFIG Struct Reference

PCI Express and DMI controller configuration - PostMem
. More...

#include <PciePeiConfig.h>

Collaboration diagram for PCIE_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | DmiExtSync: 1
Offset 28:0 (Test)DMI Extended Sync Control. More...
UINT32 | DmiIot: 1
Offset 28:1 (Test)DMI IOT Control. More...
UINT32 | RsvdBits1: 30
Offset 28:2-31 :Reserved for future use.
UINT8 | DmiAspm
Offset 32 This field is used to describe the ASPM control for DMI: 3=PcieAspmL0sL1, 2=PcieAspmL1, 1=PcieAspmL0s, 0=PcieAspmDisabled.
UINT8 | Rsvd1 [1]
Offset 33 to 35.
UINT8 | PegDeEmphasis [SA_PEG_MAX_FUN_GEN3]
Offset 36 This field is used to describe the DeEmphasis control for PEG (-6 dB and -3.5 dB are the options)SA_PEG_MAX_FUN = 3 for CFL and SA_PEG_MAX_FUN = 4 for CNL, offsets are adjusted accordingly.
UINT8 | PegMaxPayload [SA_PEG_MAX_FUN_GEN3]
(Test) Offset 39/40 This field is used to describe the PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
UINT8 | PegSlotPowerLimitValue [SA_PEG_MAX_FUN_GEN3]
PCIe Slot Power Capabilities. More...
UINT8 | PegSlotPowerLimitScale [SA_PEG_MAX_FUN_GEN3]
Offset 45/48 2 bit value: 00 = 1.0x, 01 = 0.1x, 10 = 0.01x and 11 = 0.001x.
UINT16 | PegPhysicalSlotNumber [SA_PEG_MAX_FUN_GEN3]
Offset 48/52 PCIe Physical Slot Number (13 bit value). More...

Detailed Description

PCI Express and DMI controller configuration - PostMem
.

Note
Optional. These policies will be ignored if there is no PEG port present on board. Revision 1:
  • Initial version.

Definition at line 51 of file PciePeiConfig.h.

Member Data Documentation

◆ DmiExtSync

UINT32 PCIE_PEI_CONFIG::DmiExtSync

Offset 28:0 (Test)DMI Extended Sync Control.

  • Disabled (0x0) : Disable DMI Extended Sync (Default)
  • Enabled (0x1) : Enable DMI Extended Sync

Definition at line 59 of file PciePeiConfig.h.

◆ DmiIot

UINT32 PCIE_PEI_CONFIG::DmiIot

Offset 28:1 (Test)DMI IOT Control.

  • Disabled (0x0) : Disable DMI IOT (Default)
  • Enabled (0x1) : Enable DMI IOT

Definition at line 66 of file PciePeiConfig.h.

◆ PegPhysicalSlotNumber

UINT16 PCIE_PEI_CONFIG::PegPhysicalSlotNumber[SA_PEG_MAX_FUN_GEN3]

Offset 48/52 PCIe Physical Slot Number (13 bit value).

Indicates the physical slot number attached to the port.

Definition at line 81 of file PciePeiConfig.h.

◆ PegSlotPowerLimitValue

UINT8 PCIE_PEI_CONFIG::PegSlotPowerLimitValue[SA_PEG_MAX_FUN_GEN3]

PCIe Slot Power Capabilities.

SlotPowerLimitValue in combination with SlotPowerLimitScale specifies the upper limit on power supplied by slot. Offset 42/44 8 bit value

Definition at line 75 of file PciePeiConfig.h.

The documentation for this struct was generated from the following file:
  • PciePeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_PEI_CONFIG Member List

This is the complete list of members for PCIE_PEI_CONFIG, including all inherited members.

DmiAspm | PCIE_PEI_CONFIG
DmiExtSync | PCIE_PEI_CONFIG
DmiIot | PCIE_PEI_CONFIG
Header | PCIE_PEI_CONFIG
PegDeEmphasis | PCIE_PEI_CONFIG
PegMaxPayload | PCIE_PEI_CONFIG
PegPhysicalSlotNumber | PCIE_PEI_CONFIG
PegSlotPowerLimitScale | PCIE_PEI_CONFIG
PegSlotPowerLimitValue | PCIE_PEI_CONFIG
Rsvd1 | PCIE_PEI_CONFIG
RsvdBits1 | PCIE_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_PEI_PREMEM_CONFIG Struct Reference

PCI Express and DMI controller configuration
. More...

#include <CpuPcieConfig.h>

Collaboration diagram for PCIE_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT32 | DmiMaxLinkSpeed: 2
Offset 28:0 : (Test) DMI Link Speed Control. More...
UINT32 | DmiGen3EqPh2Enable: 2
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control. More...
UINT32 | DmiGen3EqPh3Method: 3
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI. More...
UINT32 | DmiGen3ProgramStaticEq: 1
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets. More...
UINT32 | RsvdBits0: 24
Offset 28:8 :Reserved for future use.
UINT32 | InitPcieAspmAfterOprom: 1
Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom. More...
UINT32 | RsvdBits1: 31
Offset 32:1 :Reserved for future use.
UINT8 | DmiGen3RootPortPreset [SA_DMI_MAX_LANE]
Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3EndPointPreset [SA_DMI_MAX_LANE]
Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | DmiGen3EndPointHint [SA_DMI_MAX_LANE]
Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | DmiGen3RxCtlePeaking [SA_DMI_MAX_BUNDLE]
Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control. More...
UINT8 | DmiDeEmphasis
Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
UINT8 | Rsvd0 [3]
Offset 65.

Detailed Description

PCI Express and DMI controller configuration
.

Note
Optional. These policies will be ignored if there is no PEG port present on board. Revision 1:
  • Initial version.

Definition at line 84 of file CpuPcieConfig.h.

Member Data Documentation

◆ DmiGen3EqPh2Enable

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh2Enable

Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default)

Definition at line 102 of file CpuPcieConfig.h.

◆ DmiGen3EqPh3Method

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh3Method

Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3

Definition at line 112 of file CpuPcieConfig.h.

◆ DmiGen3ProgramStaticEq

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiGen3ProgramStaticEq

Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 119 of file CpuPcieConfig.h.

◆ DmiGen3RxCtlePeaking

UINT8 PCIE_PEI_PREMEM_CONFIG::DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]

Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 140 of file CpuPcieConfig.h.

◆ DmiMaxLinkSpeed

UINT32 PCIE_PEI_PREMEM_CONFIG::DmiMaxLinkSpeed

Offset 28:0 : (Test) DMI Link Speed Control.

  • Auto (0x0) : Maximum possible link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed
  • Gen3 (0x3) : Limit Link to Gen3 Speed

Definition at line 94 of file CpuPcieConfig.h.

◆ InitPcieAspmAfterOprom

UINT32 PCIE_PEI_PREMEM_CONFIG::InitPcieAspmAfterOprom

Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom.

  • Before (0x0) : Do PCIe ASPM programming before Oprom. (Default)
  • After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.

Definition at line 128 of file CpuPcieConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_PEI_PREMEM_CONFIG Member List

This is the complete list of members for PCIE_PEI_PREMEM_CONFIG, including all inherited members.

DmiDeEmphasis | PCIE_PEI_PREMEM_CONFIG
DmiGen3EndPointHint | PCIE_PEI_PREMEM_CONFIG
DmiGen3EndPointPreset | PCIE_PEI_PREMEM_CONFIG
DmiGen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG
DmiGen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG
DmiGen3ProgramStaticEq | PCIE_PEI_PREMEM_CONFIG
DmiGen3RootPortPreset | PCIE_PEI_PREMEM_CONFIG
DmiGen3RxCtlePeaking | PCIE_PEI_PREMEM_CONFIG
DmiMaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG
Header | PCIE_PEI_PREMEM_CONFIG
InitPcieAspmAfterOprom | PCIE_PEI_PREMEM_CONFIG
Rsvd0 | PCIE_PEI_PREMEM_CONFIG
RsvdBits0 | PCIE_PEI_PREMEM_CONFIG
RsvdBits1 | PCIE_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_PEI_PREMEM_CONFIG_GEN3 Struct Reference

Public Attributes | List of all members
PCIE_PEI_PREMEM_CONFIG_GEN3 Struct Reference

PCI Express and DMI controller configuration
. More...

#include <CpuPcieConfigGen3.h>

Collaboration diagram for PCIE_PEI_PREMEM_CONFIG_GEN3:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | DmiMaxLinkSpeed
Offset 28:0 : (Test) DMI Link Speed Control. More...
UINT8 | DmiGen3EqPh2Enable
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control. More...
UINT8 | DmiGen3EqPh3Method
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI. More...
UINT8 | DmiGen3ProgramStaticEq
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets. More...
UINT8 | Peg0Enable
Offset 28:8 to 28:15 : (Test) PEG Enable Control. More...
UINT8 | Peg1Enable
(Test) Enable/Disable PEG 0:1:1 Root Port
UINT8 | Peg2Enable
(Test) Enable/Disable PEG 0:1:2 Root Port
UINT8 | Peg3Enable
(Test) Enable/Disable PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | Peg0MaxLinkSpeed
Offset 28:16 : (Test) PCIe Link Speed Control. More...
UINT8 | Peg1MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:1:1 Root Port.
UINT8 | Peg2MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:1:2 Root Port.
UINT8 | Peg3MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | Peg0MaxLinkWidth
Offset 32:0 : (Test) PCIe Link Width Control. More...
UINT8 | Peg1MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:1:1 Root Port.
UINT8 | Peg2MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:1:2 Root Port.
UINT8 | Peg3MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | Peg0PowerDownUnusedLanes
Offset 32:12 to 32:15 : Power down unused lanes on the PEG Root Port. More...
UINT8 | Peg1PowerDownUnusedLanes
Power down unused lanes on the PEG 0:1:1 Root Port.
UINT8 | Peg2PowerDownUnusedLanes
Power down unused lanes on the PEG 0:1:2 Root Port.
UINT8 | Peg3PowerDownUnusedLanes
Power down unused lanes on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | Peg0Gen3EqPh2Enable
Offset 32:16 to 32:23 : (Test) PCIe Equalization Phase 2 Enable Control. More...
UINT8 | Peg1Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:1:1 Root Port.
UINT8 | Peg2Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:1:2 Root Port.
UINT8 | Peg3Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | Peg0Gen3EqPh3Method
Offset 36:0 to 36:11 : (Test) Select the method for performing Phase3 of Gen3 Equalization. More...
UINT8 | Peg1Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:1:1 Root Port.
UINT8 | Peg2Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:1:2 Root Port.
UINT8 | Peg3Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
UINT8 | PegGen3ProgramStaticEq
Offset 36:12 : (Test) Program PEG Gen3 EQ Phase1 Static Presets. More...
UINT8 | Gen3SwEqAlwaysAttempt
Offset 36:13 : (Test) Always Attempt Gen3 Software Equalization. More...
UINT8 | Gen3SwEqNumberOfPresets
Offset 36:14 to 36:16 : (Test) Select number of TxEq presets to test in the PCIe/DMI Software Equalization Algorithm. More...
UINT8 | Gen3SwEqEnableVocTest
Offset 36:17 to 36:18: (Test) Offset 36 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. More...
UINT8 | InitPcieAspmAfterOprom
Offset 36:19 : Select when PCIe ASPM programming will happen in relation to the Oprom. More...
UINT8 | PegRxCemTestingMode
Offset 36:20 : (Test) PCIe Rx Compliance Testing Mode. More...
UINT8 | PegRxCemLoopbackLane
Offset 36:21 to 36:24 : (Test) PCIe Rx Compliance Loopback Lane. More...
UINT8 | PegGenerateBdatMarginTable
Offset 36:25 to 36:28 : (Test) Generate PCIe BDAT Margin Table. More...
UINT8 | PegRxCemNonProtocolAwareness
Offset 36:29 : (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing. More...
UINT8 | PegDisableSpreadSpectrumClocking
Offset 36:30 : (Test) PCIe Disable Spread Spectrum Clocking. More...
UINT8 | DmiGen3RootPortPreset [SA_DMI_MAX_LANE_VER1]
Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | DmiGen3EndPointPreset [SA_DMI_MAX_LANE_VER1]
Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | DmiGen3EndPointHint [SA_DMI_MAX_LANE_VER1]
Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | DmiGen3RxCtlePeaking [SA_DMI_MAX_BUNDLE_VER1]
Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control. More...
UINT8 | PegGen3RootPortPreset [SA_PEG_MAX_LANE_GEN3]
Offset 54 (Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane.
UINT8 | PegGen3EndPointPreset [SA_PEG_MAX_LANE_GEN3]
Offset 70 (Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane.
UINT8 | PegGen3EndPointHint [SA_PEG_MAX_LANE_GEN3]
Offset 86 (Test) Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane.
UINT8 | PegGen3RxCtlePeaking [SA_PEG_MAX_BUNDLE_GEN3]
Offset 102: PCIe Gen3 RxCTLEp per-Bundle control. More...
UINT16 | Gen3SwEqJitterDwellTime
Offset 110: (Test)Used for PCIe Gen3 Software Equalization. More...
UINT8 | Rsvd0 [2]
Offset 112: This is a memory data pointer for saved preset search results. More...
UINT16 | Gen3SwEqJitterErrorTarget
Offset 116: (Test)Used for PCIe Gen3 Software Equalization. More...
UINT16 | Gen3SwEqVocDwellTime
Offset 118: (Test)Used for PCIe Gen3 Software Equalization. More...
UINT16 | Gen3SwEqVocErrorTarget
Offset 120: (Test)Used for PCIe Gen3 Software Equalization. More...
UINT8 | PegRootPortHPE [SA_PEG_MAX_FUN_GEN3]
Offset 122: PCIe Hot Plug Enable/Disable. More...
UINT8 | DmiDeEmphasis
Offset 125 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
PEG_GPIO_DATA PegGpioData
Offset 128: This contains the PCIe PERST# GPIO information. More...
UINT8 | PegGen3RxCtleOverride
Offset 156 (Test) PCIe Override RxCTLE. More...

Detailed Description

PCI Express and DMI controller configuration
.

Note
Optional. These policies will be ignored if there is no PEG port present on board. Revision 1:
  • Initial version.

Definition at line 80 of file CpuPcieConfigGen3.h.

Member Data Documentation

◆ DmiGen3EqPh2Enable

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3EqPh2Enable

Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default)

Definition at line 98 of file CpuPcieConfigGen3.h.

◆ DmiGen3EqPh3Method

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3EqPh3Method

Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3

Definition at line 108 of file CpuPcieConfigGen3.h.

◆ DmiGen3ProgramStaticEq

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3ProgramStaticEq

Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 115 of file CpuPcieConfigGen3.h.

◆ DmiGen3RxCtlePeaking

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE_VER1]

Offset 48/60 : DMI Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 287 of file CpuPcieConfigGen3.h.

◆ DmiMaxLinkSpeed

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::DmiMaxLinkSpeed

Offset 28:0 : (Test) DMI Link Speed Control.

  • Auto (0x0) : Maximum possible link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed
  • Gen3 (0x3) : Limit Link to Gen3 Speed

Definition at line 90 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqAlwaysAttempt

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqAlwaysAttempt

Offset 36:13 : (Test) Always Attempt Gen3 Software Equalization.

When enabled, Gen3 Software Equalization will be executed every boot. When disabled, it will be only executed if the CPU or EP is changed, otherwise it is skipped and the previous EQ value will be re-used.

This setting will only have an effect if Software Equalization is enabled and OEM Platform Code implements save/restore of the PegDataPtr data (see below). If PegDataPtr is not saved/restored RC forces this to be enabled.

  • Disabled (0x0) : Reuse EQ settings saved/restored from NVRAM whenever possible (Default)
  • Enabled (0x1) : Re-test and generate new EQ values every boot, not recommended

Definition at line 211 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqEnableVocTest

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqEnableVocTest

Offset 36:17 to 36:18: (Test) Offset 36 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm.

  • Disabled (0x0) : Disable VOC Test
  • Enabled (0x1) : Enable VOC Test
  • Auto (0x2) : Use the current default (Default)

Definition at line 230 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqJitterDwellTime

UINT16 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqJitterDwellTime

Offset 110: (Test)Used for PCIe Gen3 Software Equalization.

Range: 0-65535, default is 1000.

Warning
Do not change from the default. Hard to detect issues are likely.
Note
An attack on this policy could result in an apparent hang, but the system will eventually boot. This variable should be protected.

Definition at line 305 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqJitterErrorTarget

UINT16 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqJitterErrorTarget

Offset 116: (Test)Used for PCIe Gen3 Software Equalization.

Range: 0-65535, default is 1.

Warning
Do not change from the default. Hard to detect issues are likely.

Definition at line 327 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqNumberOfPresets

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqNumberOfPresets

Offset 36:14 to 36:16 : (Test) Select number of TxEq presets to test in the PCIe/DMI Software Equalization Algorithm.

  • P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8
  • P0-P9 (0x1) : Test Presets 0-9
  • Auto (0x2) : Use the current default method (Default) Auto will test Presets 7, 3, 5, and 8. It is possible for this default to change over time; using "Auto" will ensure Reference Code always uses the latest default settings.
    Warning
    Do not change from the default. Hard to detect issues are likely.

Definition at line 222 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqVocDwellTime

UINT16 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqVocDwellTime

Offset 118: (Test)Used for PCIe Gen3 Software Equalization.

Range: 0-65535, default is 10000.

Warning
Do not change from the default. Hard to detect issues are likely.
Note
An attack on this policy could result in an apparent hang, but the system will eventually boot. This variable should be protected.

Definition at line 336 of file CpuPcieConfigGen3.h.

◆ Gen3SwEqVocErrorTarget

UINT16 PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqVocErrorTarget

Offset 120: (Test)Used for PCIe Gen3 Software Equalization.

Range: 0-65535, default is 2.

Warning
Do not change from the default. Hard to detect issues are likely.

Definition at line 343 of file CpuPcieConfigGen3.h.

◆ InitPcieAspmAfterOprom

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::InitPcieAspmAfterOprom

Offset 36:19 : Select when PCIe ASPM programming will happen in relation to the Oprom.

  • Before (0x0) : Do PCIe ASPM programming before Oprom. (Default)
  • After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.

Definition at line 237 of file CpuPcieConfigGen3.h.

◆ Peg0Enable

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Enable

Offset 28:8 to 28:15 : (Test) PEG Enable Control.

  • Disabled (0x0) : Disable PEG Port
  • Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it)
  • Auto (0x2) : If an endpoint is present, enable the PEG Port, Disable otherwise (Default) Enable/Disable PEG 0:1:0 Root Port

Definition at line 124 of file CpuPcieConfigGen3.h.

◆ Peg0Gen3EqPh2Enable

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Gen3EqPh2Enable

Offset 32:16 to 32:23 : (Test) PCIe Equalization Phase 2 Enable Control.

  • Disabled (0x0) : Disable phase 2
  • Enabled (0x1) : Enable phase 2
  • Auto (0x2) : Use the current default method (Default) Phase2 EQ enable on the PEG 0:1:0 Root Port.

Definition at line 173 of file CpuPcieConfigGen3.h.

◆ Peg0Gen3EqPh3Method

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Gen3EqPh3Method

Offset 36:0 to 36:11 : (Test) Select the method for performing Phase3 of Gen3 Equalization.

  • Auto (0x0) : Use the current default method (Default)
  • HwEq (0x1) : Use Adaptive Hardware Equalization
  • SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
  • Static (0x3) : Use the Static EQs provided in PegGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
  • Disabled (0x4) : Bypass Equalization Phase 3 Phase3 EQ method on the PEG 0:1:0 Root Port.

Definition at line 187 of file CpuPcieConfigGen3.h.

◆ Peg0MaxLinkSpeed

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0MaxLinkSpeed

Offset 28:16 : (Test) PCIe Link Speed Control.

  • Auto (0x0) : Maximum possible Link speed (Default)
  • Gen1 (0x1) : Limit Link to Gen1 Speed
  • Gen2 (0x2) : Limit Link to Gen2 Speed
  • Gen3 (0x3) : Limit Link to Gen3 Speed PCIe Link Speed Control for PEG 0:1:0 Root Port.

Definition at line 137 of file CpuPcieConfigGen3.h.

◆ Peg0MaxLinkWidth

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0MaxLinkWidth

Offset 32:0 : (Test) PCIe Link Width Control.

  • Auto (0x0) : Maximum possible Link width (Default)
  • X1 (0x1) : Limit Link to X1 Width
  • X2 (0x2) : Limit Link to X2 Width
  • X4 (0x3) : Limit Link to X4 Width
  • X8 (0x4) : Limit Link to X8 Width PCIe Link Width Control for PEG 0:1:0 Root Port.

Definition at line 151 of file CpuPcieConfigGen3.h.

◆ Peg0PowerDownUnusedLanes

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0PowerDownUnusedLanes

Offset 32:12 to 32:15 : Power down unused lanes on the PEG Root Port.

  • Disabled (0x0) : No power saving.
  • Auto (0x1) : Bios will power down unused lanes based on the max possible link width Power down unused lanes on the PEG 0:1:0 Root Port.

Definition at line 161 of file CpuPcieConfigGen3.h.

◆ PegDisableSpreadSpectrumClocking

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegDisableSpreadSpectrumClocking

Offset 36:30 : (Test) PCIe Disable Spread Spectrum Clocking.

This feature should be TRUE only for compliance testing

  • False (0x0) : Normal Operation - SSC enabled (Default)
  • True (0x1) : Disable SSC - Disable SSC for compliance testing

Definition at line 276 of file CpuPcieConfigGen3.h.

◆ PegGen3ProgramStaticEq

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegGen3ProgramStaticEq

Offset 36:12 : (Test) Program PEG Gen3 EQ Phase1 Static Presets.

  • Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
  • Enabled (0x1) : Enable EQ Phase1 Static Presets Programming (Default)

Definition at line 197 of file CpuPcieConfigGen3.h.

◆ PegGen3RxCtleOverride

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegGen3RxCtleOverride

Offset 156 (Test) PCIe Override RxCTLE.

This feature should only be true to disable RxCTLE adaptive behavior for compliance testing

  • False (0x0) : Normal Operation - RxCTLE adaptive behavior enabled (Default)
  • True (0x1) : Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified From CFL onwards, modularity is introduced to this setup option so that the RxCTLE adaptive behavior could be controlled at the controller level. Making this variable a UINT8 to accomodate the values of all controllers as bit definition

Definition at line 370 of file CpuPcieConfigGen3.h.

◆ PegGen3RxCtlePeaking

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE_GEN3]

Offset 102: PCIe Gen3 RxCTLEp per-Bundle control.

The range of the setting is (0-15). This setting has to be specified based upon platform design and must follow the guideline. Default is 12.

Definition at line 297 of file CpuPcieConfigGen3.h.

◆ PegGenerateBdatMarginTable

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegGenerateBdatMarginTable

Offset 36:25 to 36:28 : (Test) Generate PCIe BDAT Margin Table.

Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.

  • Disabled (0x0) : Normal Operation - Disable PCIe BDAT margin data generation (Default)
  • PortData (0x1) : Port Data - Generate PCIe BDAT margin data

Definition at line 262 of file CpuPcieConfigGen3.h.

◆ PegGpioData

PEG_GPIO_DATA PCIE_PEI_PREMEM_CONFIG_GEN3::PegGpioData

Offset 128: This contains the PCIe PERST# GPIO information.

This structure is required for PCIe Gen3 operation. The reference code will use the information in this structure in order to reset PCIe Gen3 devices during equalization, if necessary. Refer to the Platform Developer's Guide (PDG) for additional details.

Definition at line 360 of file CpuPcieConfigGen3.h.

◆ PegRootPortHPE

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegRootPortHPE[SA_PEG_MAX_FUN_GEN3]

Offset 122: PCIe Hot Plug Enable/Disable.

It has 2 policies.

  • Disabled (0x0) : No hotplug.
  • Enabled (0x1) : Bios assist hotplug.

Definition at line 350 of file CpuPcieConfigGen3.h.

◆ PegRxCemLoopbackLane

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemLoopbackLane

Offset 36:21 to 36:24 : (Test) PCIe Rx Compliance Loopback Lane.

When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) will be used for RxCEMLoopback.

Default is Lane 0.

Definition at line 255 of file CpuPcieConfigGen3.h.

◆ PegRxCemNonProtocolAwareness

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemNonProtocolAwareness

Offset 36:29 : (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing.

  • Disabled (0x0) : Normal Operation - Disable non-protocol awareness (Default)
  • Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing

Definition at line 269 of file CpuPcieConfigGen3.h.

◆ PegRxCemTestingMode

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemTestingMode

Offset 36:20 : (Test) PCIe Rx Compliance Testing Mode.

  • Disabled (0x0) : Normal Operation - Disable PCIe Rx Compliance testing (Default)
  • Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing

Definition at line 244 of file CpuPcieConfigGen3.h.

◆ Rsvd0

UINT8 PCIE_PEI_PREMEM_CONFIG_GEN3::Rsvd0[2]

Offset 112: This is a memory data pointer for saved preset search results.

The reference code will store the Gen3 Preset Search results in the SaPegHob. In order to skip the Gen3 preset search on boots where the PEG card configuration has not changed since the previous boot, platform code can save the contents of the SaPegHob in DXE (When it present and for size reported by Header.HobLength) and provide a pointer to a restored copy of that data. Default value is NULL, which results in a full preset search every boot.

Note
An attack on this policy could prevent the PCIe display from working until a boot when PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable used to save the preset search results should be protected in a way that it can only be modified by the platform manufacturer.

Definition at line 320 of file CpuPcieConfigGen3.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfigGen3.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_PEI_PREMEM_CONFIG_GEN3 Member List

This is the complete list of members for PCIE_PEI_PREMEM_CONFIG_GEN3, including all inherited members.

DmiDeEmphasis | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3EndPointHint | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3EndPointPreset | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3ProgramStaticEq | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3RootPortPreset | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiGen3RxCtlePeaking | PCIE_PEI_PREMEM_CONFIG_GEN3
DmiMaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqAlwaysAttempt | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqEnableVocTest | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqJitterDwellTime | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqJitterErrorTarget | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqNumberOfPresets | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqVocDwellTime | PCIE_PEI_PREMEM_CONFIG_GEN3
Gen3SwEqVocErrorTarget | PCIE_PEI_PREMEM_CONFIG_GEN3
Header | PCIE_PEI_PREMEM_CONFIG_GEN3
InitPcieAspmAfterOprom | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0Gen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0Gen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0MaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0MaxLinkWidth | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg0PowerDownUnusedLanes | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1Gen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1Gen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1MaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1MaxLinkWidth | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg1PowerDownUnusedLanes | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2Gen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2Gen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2MaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2MaxLinkWidth | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg2PowerDownUnusedLanes | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3Gen3EqPh2Enable | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3Gen3EqPh3Method | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3MaxLinkSpeed | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3MaxLinkWidth | PCIE_PEI_PREMEM_CONFIG_GEN3
Peg3PowerDownUnusedLanes | PCIE_PEI_PREMEM_CONFIG_GEN3
PegDisableSpreadSpectrumClocking | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3EndPointHint | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3EndPointPreset | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3ProgramStaticEq | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3RootPortPreset | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3RxCtleOverride | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGen3RxCtlePeaking | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGenerateBdatMarginTable | PCIE_PEI_PREMEM_CONFIG_GEN3
PegGpioData | PCIE_PEI_PREMEM_CONFIG_GEN3
PegRootPortHPE | PCIE_PEI_PREMEM_CONFIG_GEN3
PegRxCemLoopbackLane | PCIE_PEI_PREMEM_CONFIG_GEN3
PegRxCemNonProtocolAwareness | PCIE_PEI_PREMEM_CONFIG_GEN3
PegRxCemTestingMode | PCIE_PEI_PREMEM_CONFIG_GEN3
Rsvd0 | PCIE_PEI_PREMEM_CONFIG_GEN3
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_PREMEM_CONFIG Struct Reference

PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

#include <PciePreMemConfig.h>

Collaboration diagram for PCIE_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
PCIE_IMR_CONFIG PcieImr
IMR Configuration.

Detailed Description

PCIe Pre-Memory Configuration Revision 1: - Initial version.

Definition at line 65 of file PciePreMemConfig.h.

The documentation for this struct was generated from the following file:
  • PciePreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_PREMEM_CONFIG Member List

This is the complete list of members for PCIE_PREMEM_CONFIG, including all inherited members.

Header | PCIE_PREMEM_CONFIG
PcieImr | PCIE_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_RP_DXE_CONFIG Struct Reference

Public Attributes | List of all members
PCIE_RP_DXE_CONFIG Struct Reference

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

#include <PchPcieRpConfig.h>

Collaboration diagram for PCIE_RP_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings. More...

Detailed Description

The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase.

Revision 1:

  • Init version

Definition at line 269 of file PchPcieRpConfig.h.

Member Data Documentation

◆ PcieDeviceOverrideTablePtr

PCIE_DEVICE_OVERRIDE* PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr

PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.

And it's only used in DXE phase. Please refer to PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId must be 0.

Definition at line 279 of file PchPcieRpConfig.h.

The documentation for this struct was generated from the following file:
  • PchPcieRpConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_RP_DXE_CONFIG Member List

This is the complete list of members for PCIE_RP_DXE_CONFIG, including all inherited members.

Header | PCIE_RP_DXE_CONFIG
PcieDeviceOverrideTablePtr | PCIE_RP_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PCIE_RTD3_GPIO Struct Reference

Public Attributes | List of all members
PCIE_RTD3_GPIO Struct Reference

SA PCIE RTD3 GPIO Data Structure. More...

#include <HgInfoHob.h>

Collaboration diagram for PCIE_RTD3_GPIO:
[legend]

Public Attributes

UINT8 | GpioSupport
0=Not Supported; 1=PCH based; 2=I2C Based
PCIE_GPIO HoldRst
Offset 8 This field contain PCIe HLD RESET GPIO value and level information.
PCIE_GPIO PwrEnable
This field contain PCIe PWR Enable GPIO value and level information.
UINT32 | WakeGpioNo
This field contain PCIe RTD3 Device Wake GPIO number.

Detailed Description

SA PCIE RTD3 GPIO Data Structure.

Definition at line 56 of file HgInfoHob.h.

The documentation for this struct was generated from the following file:
  • HgInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PCIE_RTD3_GPIO Member List

This is the complete list of members for PCIE_RTD3_GPIO, including all inherited members.

GpioSupport | PCIE_RTD3_GPIO
HoldRst | PCIE_RTD3_GPIO
PwrEnable | PCIE_RTD3_GPIO
WakeGpioNo | PCIE_RTD3_GPIO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PEG_GPIO_DATA Struct Reference

Public Attributes | List of all members
PEG_GPIO_DATA Struct Reference

SA Board PEG GPIO Info. More...

#include <CpuPcieConfigGen3.h>

Collaboration diagram for PEG_GPIO_DATA:
[legend]

Public Attributes

SA_GPIO_INFO_PCIE SaPeg0ResetGpio
Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin.
SA_GPIO_INFO_PCIE SaPeg3ResetGpio
Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin.
BOOLEAN | GpioSupport
Offset 24: 1=Supported; 0=Not Supported.
UINT8 | Rsvd0 [3]
Offset 25: Reserved for 4 bytes alignment.

Detailed Description

SA Board PEG GPIO Info.

Definition at line 67 of file CpuPcieConfigGen3.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfigGen3.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PEG_GPIO_DATA Member List

This is the complete list of members for PEG_GPIO_DATA, including all inherited members.

GpioSupport | PEG_GPIO_DATA
Rsvd0 | PEG_GPIO_DATA
SaPeg0ResetGpio | PEG_GPIO_DATA
SaPeg3ResetGpio | PEG_GPIO_DATA
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PET_ALERT Struct Reference

Public Attributes | List of all members
PET_ALERT Struct Reference

Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert. More...

#include <AsfMsgs.h>

Collaboration diagram for PET_ALERT:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT8 | EventSensorType
Default value is 0x0F to indicate it is Firmware progress/error type.
UINT8 | EventType
Default value is 0x6F to indicate it is Sensor specific.
UINT8 | EventOffset
Indicates which particular event occurred for a given Event Type. More...
UINT8 | EventSourceType
Default value is 0x68 to indicate it is ASF 1.0.
UINT8 | EventSeverity
Severity of the event. More...
UINT8 | SensorDevice
Default value is 0xFF to indicate it is Unspecified.
UINT8 | Sensornumber
Default value is 0xFF to indicate it is Unspecified.
UINT8 | Entity
Indicates the platform device or subsystem associated with the event. More...
UINT8 | EntityInstance
Identifies which unique device is associated with the event when a system includes multiple device instances. More...
UINT8 | EventData1
The Event Type determines the Event Data. More...
UINT8 | EventData2
Additional Event Data 2. More...
UINT8 | EventData3
Additional Event Data 3. More...
UINT8 | EventData4
Additional Event Data 4. More...
UINT8 | EventData5
Additional Event Data 5. More...

Detailed Description

Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert.

This structure is used for sending Remote Secure Erase / Boot Audit Entry PET Message. Elements' description is based on Remote Secure Erase / Boot Audit Entry.

Definition at line 513 of file AsfMsgs.h.

Member Data Documentation

◆ Entity

UINT8 PET_ALERT::Entity

Indicates the platform device or subsystem associated with the event.

0x00: Unspecified 0x01: Other 0x02: Unknown 0x03: Processor 0x04: Disk 0x05: Peripheral 0x07: System Board 0x0A: Power Supply 0x0B: Add-in Card 0x20: Memory 0x22: BIOS 0x23: OS

Definition at line 556 of file AsfMsgs.h.

◆ EntityInstance

UINT8 PET_ALERT::EntityInstance

Identifies which unique device is associated with the event when a system includes multiple device instances.

For Remote Secure Erase: 0xFF: Unspecified For Boot Audit Entry: 0x00: Unspecified

Definition at line 564 of file AsfMsgs.h.

◆ EventData1

UINT8 PET_ALERT::EventData1

The Event Type determines the Event Data.

For Remote Secure Erase: 0xAA: Indicate EventData 2-5 set by OEM specification. For Boot Audit Entry: 0x40: EventData 2 conforms ASF spec. 0xAA: Indicate EventData 2-5 set by OEM specification.

Definition at line 573 of file AsfMsgs.h.

◆ EventData2

UINT8 PET_ALERT::EventData2

Additional Event Data 2.

For Remote Secure Erase: 0x20: Indicate it is for Remote Secure Erase. For Boot Audit Entry: 0x13: Performing system boot.

Definition at line 581 of file AsfMsgs.h.

◆ EventData3

UINT8 PET_ALERT::EventData3

Additional Event Data 3.

For Remote Secure Erase: Success Case: 0x00 - Secure erase success Failure Case: 0x01 - General failure 0x02 - Drive authentication failure 0x03 - Feature is not supported 0x04 - 0XFF - Reserved For Boot Audit Entry (Boot Device Not Changed): 00: Not used. For Boot Audit Entry (Boot Device Changed): N/A: Most recent BAE queue entry.

Definition at line 595 of file AsfMsgs.h.

◆ EventData4

UINT8 PET_ALERT::EventData4

Additional Event Data 4.

For Remote Secure Erase: N/A: Not used. For Boot Audit Entry (Boot Device Not Changed): N/A: Not used. For Boot Audit Entry (Boot Device Changed): N/A: Next most recent BAE queue entry.

Definition at line 605 of file AsfMsgs.h.

◆ EventData5

UINT8 PET_ALERT::EventData5

Additional Event Data 5.

For Remote Secure Erase: N/A: Not used. For Boot Audit Entry (Boot Device Not Changed): N/A: Not used. For Boot Audit Entry (Boot Device Changed): N/A: Oldest BAE queue entry.

Definition at line 615 of file AsfMsgs.h.

◆ EventOffset

UINT8 PET_ALERT::EventOffset

Indicates which particular event occurred for a given Event Type.

For Remote Secure Erase: 0x03: OEM specific firmware error 0x05: OEM specific firmware progress For Boot Audit Entry: 0x00: System Firmware Error 0x01: System Firmware Hang 0x02: System Firmware In Progress

Definition at line 527 of file AsfMsgs.h.

◆ EventSeverity

UINT8 PET_ALERT::EventSeverity

Severity of the event.

0x01: Monitor 0x02: Information 0x04: Ok 0x08: Non-critical 0x10: Critical 0x20: Non-Recoverable

Definition at line 538 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PET_ALERT Member List

This is the complete list of members for PET_ALERT, including all inherited members.

AsfHeader | PET_ALERT
Entity | PET_ALERT
EntityInstance | PET_ALERT
EventData1 | PET_ALERT
EventData2 | PET_ALERT
EventData3 | PET_ALERT
EventData4 | PET_ALERT
EventData5 | PET_ALERT
EventOffset | PET_ALERT
EventSensorType | PET_ALERT
EventSeverity | PET_ALERT
EventSourceType | PET_ALERT
EventType | PET_ALERT
SensorDevice | PET_ALERT
Sensornumber | PET_ALERT
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PMC_GLOBAL_RESET_MASK Union Reference

List of all members
PMC_GLOBAL_RESET_MASK Union Reference

Description of Global Reset Trigger/Event Mask register. More...

#include <PmConfig.h>

Detailed Description

Description of Global Reset Trigger/Event Mask register.

Definition at line 152 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PMC_GLOBAL_RESET_MASK Member List

This is the complete list of members for PMC_GLOBAL_RESET_MASK, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PMC_INTERFACE_CONFIG Struct Reference

Public Attributes | List of all members
PMC_INTERFACE_CONFIG Struct Reference

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 PmcPdEnable
PMC PD Solution Enable.

Detailed Description

The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.

Definition at line 74 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PMC_INTERFACE_CONFIG Member List

This is the complete list of members for PMC_INTERFACE_CONFIG, including all inherited members.

PmcPdEnable PMC_INTERFACE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PMC_LPM_S0IX_SUB_STATE_EN Union Reference

List of all members
PMC_LPM_S0IX_SUB_STATE_EN Union Reference

Low Power Mode Enable config. More...

#include <PmConfig.h>

Detailed Description

Low Power Mode Enable config.

Used to configure if respective S0i2/3 sub-states are to be supported by the platform. Each bit corresponds to one LPM state - LPMx->BITx. Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins to gate v1p05-PHY or v1p05-IS supplies

Definition at line 119 of file PmConfig.h.

Member Data Documentation

◆ S0i2p2En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En

LPM2 - S0i2.2 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 128 of file PmConfig.h.

◆ S0i3p3En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En

LPM5 - S0i3.3 Enable.

Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. Refer to V1p05PhyExtFetControlEn.

Definition at line 137 of file PmConfig.h.

◆ S0i3p4En

UINT32 PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En

LPM7 - S0i3.4 Enable.

Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK. Refer to V1p05IsExtFetControlEn.

Definition at line 143 of file PmConfig.h.

The documentation for this union was generated from the following file:
  • PmConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PMC_LPM_S0IX_SUB_STATE_EN Member List

This is the complete list of members for PMC_LPM_S0IX_SUB_STATE_EN, including all inherited members.

Reserved | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i2p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p0En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p1En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p2En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p3En | PMC_LPM_S0IX_SUB_STATE_EN
S0i3p4En | PMC_LPM_S0IX_SUB_STATE_EN
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PORT_INFO Struct Reference

List of all members
PORT_INFO Struct Reference

PCIe device detection information. More...

#include <VmdInfoHob.h>

Detailed Description

PCIe device detection information.

This information will be used to display BIOS setup option to users.

Definition at line 49 of file VmdInfoHob.h.

The documentation for this struct was generated from the following file:
  • VmdInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PORT_INFO Member List

This is the complete list of members for PORT_INFO, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PPM_CUSTOM_RATIO_TABLE Struct Reference

Public Attributes | List of all members
PPM_CUSTOM_RATIO_TABLE Struct Reference

This structure is used to describe the custom processor ratio table desired by the platform. More...

#include <CpuPowerMgmtCustomConfig.h>

Public Attributes

UINT8 | MaxRatio
The maximum ratio of the custom ratio table.
UINT8 | NumberOfEntries
The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
UINT8 | Rsvd0 [2]
Reserved for DWORD alignment.
UINT32 | Cpuid
The CPU ID for which this custom ratio table applies.
UINT8 | StateRatio [MAX_CUSTOM_RATIO_TABLE_ENTRIES]
The processor ratios in the custom ratio table.
UINT8 | StateRatioMax16 [MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]
If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table. More...

Detailed Description

This structure is used to describe the custom processor ratio table desired by the platform.

Definition at line 59 of file CpuPowerMgmtCustomConfig.h.

Member Data Documentation

◆ StateRatioMax16

UINT8 PPM_CUSTOM_RATIO_TABLE::StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]

If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table.

Note
If NumberOfEntries is 16 or less, or the first entry of this table is 0, then this table is ignored, and up to the top 16 values from the StateRatio table is used instead.

Definition at line 70 of file CpuPowerMgmtCustomConfig.h.

The documentation for this struct was generated from the following file:
  • CpuPowerMgmtCustomConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PPM_CUSTOM_RATIO_TABLE Member List

This is the complete list of members for PPM_CUSTOM_RATIO_TABLE, including all inherited members.

Cpuid | PPM_CUSTOM_RATIO_TABLE
MaxRatio | PPM_CUSTOM_RATIO_TABLE
NumberOfEntries | PPM_CUSTOM_RATIO_TABLE
Rsvd0 | PPM_CUSTOM_RATIO_TABLE
StateRatio | PPM_CUSTOM_RATIO_TABLE
StateRatioMax16 | PPM_CUSTOM_RATIO_TABLE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PROTECTED_RANGE Struct Reference

Public Attributes | List of all members
PROTECTED_RANGE Struct Reference

Protected Flash Range. More...

#include <FlashProtectionConfig.h>

Public Attributes

UINT32 | WriteProtectionEnable: 1
Write or erase is blocked by hardware. 0: Disable; 1: Enable.
UINT32 | ReadProtectionEnable: 1
Read is blocked by hardware. 0: Disable; 1: Enable.
UINT32 | RsvdBits: 30
Reserved.
UINT16 | ProtectedRangeLimit
The address of the upper limit of protection This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
UINT16 | ProtectedRangeBase
The address of the upper limit of protection This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0.

Detailed Description

Protected Flash Range.

Definition at line 51 of file FlashProtectionConfig.h.

The documentation for this struct was generated from the following file:
  • FlashProtectionConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PROTECTED_RANGE Member List

This is the complete list of members for PROTECTED_RANGE, including all inherited members.

ProtectedRangeBase | PROTECTED_RANGE
ProtectedRangeLimit | PROTECTED_RANGE
ReadProtectionEnable | PROTECTED_RANGE
RsvdBits | PROTECTED_RANGE
WriteProtectionEnable | PROTECTED_RANGE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PSF_CONFIG Struct Reference

Public Attributes | List of all members
PSF_CONFIG Struct Reference

The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric. More...

#include <PsfConfig.h>

Collaboration diagram for PSF_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | TccEnable: 1
Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf power management features. More...
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric.

Definition at line 49 of file PsfConfig.h.

Member Data Documentation

◆ TccEnable

UINT32 PSF_CONFIG::TccEnable

Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf power management features.

0: Disable; 1: Enable.

Definition at line 55 of file PsfConfig.h.

The documentation for this struct was generated from the following file:
  • PsfConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

PSF_CONFIG Member List

This is the complete list of members for PSF_CONFIG, including all inherited members.

Header | PSF_CONFIG
RsvdBits0 | PSF_CONFIG
TccEnable | PSF_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RC_VERSION Struct Reference

List of all members
RC_VERSION Struct Reference

This structure contains the RC version details for FVI SMBIOS records. More...

#include <SiFviLib.h>

Detailed Description

This structure contains the RC version details for FVI SMBIOS records.

Definition at line 70 of file SiFviLib.h.

The documentation for this struct was generated from the following file:
  • SiFviLib.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

RC_VERSION Member List

This is the complete list of members for RC_VERSION, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): READ_FILE Struct Reference

List of all members
READ_FILE Struct Reference

Read File, Ver3 API only. More...

#include <MkhiMsgs.h>

Collaboration diagram for READ_FILE:
[legend]

Detailed Description

Read File, Ver3 API only.

Definition at line 631 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

READ_FILE Member List

This is the complete list of members for READ_FILE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): READ_FILE_EX Struct Reference

List of all members
READ_FILE_EX Struct Reference

Read File Ex. More...

#include <MkhiMsgs.h>

Collaboration diagram for READ_FILE_EX:
[legend]

Detailed Description

Read File Ex.

Definition at line 722 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

READ_FILE_EX Member List

This is the complete list of members for READ_FILE_EX, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): REPORT_BIOS_STATUS Struct Reference

Public Attributes | List of all members
REPORT_BIOS_STATUS Struct Reference

Report BIOS Status. More...

#include <AsfMsgs.h>

Collaboration diagram for REPORT_BIOS_STATUS:
[legend]

Public Attributes

ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
UINT16 | BiosStatus
Current BIOS Status. More...
UINT16 | StatusCause
The Reason Causes Current BIOS Status. More...

Detailed Description

Report BIOS Status.

Definition at line 228 of file AsfMsgs.h.

Member Data Documentation

◆ BiosStatus

UINT16 REPORT_BIOS_STATUS::BiosStatus

Current BIOS Status.

0: Success 1: In Progress 2: Not reported 0xFFFF: Failed

Definition at line 239 of file AsfMsgs.h.

◆ StatusCause

UINT16 REPORT_BIOS_STATUS::StatusCause

The Reason Causes Current BIOS Status.

0: BiosStatus is Success/InProgress 1: General Drive Failure 2: Drive Password/Authentication Failure 3: Feature is not supported

Definition at line 247 of file AsfMsgs.h.

The documentation for this struct was generated from the following file:
  • AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

REPORT_BIOS_STATUS Member List

This is the complete list of members for REPORT_BIOS_STATUS, including all inherited members.

AsfHeader | REPORT_BIOS_STATUS
BiosStatus | REPORT_BIOS_STATUS
StatusCause | REPORT_BIOS_STATUS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): REQUEST_OWNERSHIP Struct Reference

List of all members
REQUEST_OWNERSHIP Struct Reference

Request Device Ownership. More...

#include <MkhiMsgs.h>

Collaboration diagram for REQUEST_OWNERSHIP:
[legend]

Detailed Description

Request Device Ownership.

Definition at line 765 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

REQUEST_OWNERSHIP Member List

This is the complete list of members for REQUEST_OWNERSHIP, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RST_CONFIG Struct Reference

Public Attributes | List of all members
RST_CONFIG Struct Reference

Rapid Storage Technology settings. More...

#include <RstConfig.h>

Collaboration diagram for RST_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | Raid0: 1
0 : Disable; 1 : Enable RAID0
UINT32 | Raid1: 1
0 : Disable; 1 : Enable RAID1
UINT32 | Raid10: 1
0 : Disable; 1 : Enable RAID10
UINT32 | Raid5: 1
0 : Disable; 1 : Enable RAID5
UINT32 | Irrt: 1
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
UINT32 | OromUiBanner: 1
0 : Disable; 1 : Enable OROM UI and BANNER
UINT32 | OromUiDelay: 2
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
UINT32 | HddUnlock: 1
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
UINT32 | LedLocate: 1
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
UINT32 | IrrtOnly: 1
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
UINT32 | SmartStorage: 1
0 : Disable; 1 : Enable RST Smart Storage caching Bit
UINT32 | LegacyOrom: 1
0 : Disable; 1 : Enable RST Legacy OROM
UINT32 | OptaneMemory: 1
0: Disable; 1: Enable RST Optane(TM) Memory
UINT32 | CpuAttachedStorage: 1
0: Disable; 1: Enable CPU Attached Storage
UINT32 | RsvdBits0: 17
Reserved Bits.
RST_HARDWARE_REMAPPED_STORAGE_CONFIG | HardwareRemappedStorageConfig [PCH_MAX_RST_PCIE_STORAGE_CR]
This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required) Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available.

Detailed Description

Rapid Storage Technology settings.

Revision 1:

  • Initial version.

Definition at line 84 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

RST_CONFIG Member List

This is the complete list of members for RST_CONFIG, including all inherited members.

CpuAttachedStorage | RST_CONFIG
HardwareRemappedStorageConfig | RST_CONFIG
HddUnlock | RST_CONFIG
Header | RST_CONFIG
Irrt | RST_CONFIG
IrrtOnly | RST_CONFIG
LedLocate | RST_CONFIG
LegacyOrom | RST_CONFIG
OptaneMemory | RST_CONFIG
OromUiBanner | RST_CONFIG
OromUiDelay | RST_CONFIG
Raid0 | RST_CONFIG
Raid1 | RST_CONFIG
Raid10 | RST_CONFIG
Raid5 | RST_CONFIG
RsvdBits0 | RST_CONFIG
SmartStorage | RST_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

Public Attributes | List of all members
RST_HARDWARE_REMAPPED_STORAGE_CONFIG Struct Reference

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...

#include <RstConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. More...
UINT32 | RstPcieStoragePort: 5
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported ports for PCIe Storage remapping is different depend on the platform and cycle router.
UINT32 | DeviceResetDelay: 8
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step. More...
UINT32 | RsvdBits0: 18
Reserved bits.

Detailed Description

This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required.

Definition at line 56 of file RstConfig.h.

Member Data Documentation

◆ DeviceResetDelay

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay

PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.

Default value is 100ms.

Definition at line 73 of file RstConfig.h.

◆ Enable

UINT32 RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable

This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.

0: Disable; 1: Enable. Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID

Definition at line 62 of file RstConfig.h.

The documentation for this struct was generated from the following file:
  • RstConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

RST_HARDWARE_REMAPPED_STORAGE_CONFIG Member List

This is the complete list of members for RST_HARDWARE_REMAPPED_STORAGE_CONFIG, including all inherited members.

DeviceResetDelay | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
Enable | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RstPcieStoragePort | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
RsvdBits0 | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RTC_CONFIG Struct Reference

Public Attributes | List of all members
RTC_CONFIG Struct Reference

The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

#include <RtcConfig.h>

Collaboration diagram for RTC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | BiosInterfaceLock: 1
When set, prevents RTC TS (BUC.TS) from being changed. More...
UINT32 | MemoryLock: 1
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed. More...

Detailed Description

The RTC_CONFIG block describes the expected configuration of RTC configuration.

Definition at line 46 of file RtcConfig.h.

Member Data Documentation

◆ BiosInterfaceLock

UINT32 RTC_CONFIG::BiosInterfaceLock

When set, prevents RTC TS (BUC.TS) from being changed.

This BILD bit has different function compared to LPC/eSPI, SPI. 0: Disabled; 1: Enabled

Definition at line 53 of file RtcConfig.h.

◆ MemoryLock

UINT32 RTC_CONFIG::MemoryLock

When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.

Writes will be droipped and reads will not return any guaranteed data. 0: Disabled; 1: Enabled

Definition at line 60 of file RtcConfig.h.

The documentation for this struct was generated from the following file:
  • RtcConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

RTC_CONFIG Member List

This is the complete list of members for RTC_CONFIG, including all inherited members.

BiosInterfaceLock | RTC_CONFIG
Header | RTC_CONFIG
MemoryLock | RTC_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_ADDRESS_DECODE Struct Reference

Public Attributes | List of all members
SA_ADDRESS_DECODE Struct Reference

SA memory address decode. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 | Controller
Offset 0 Zero based Controller number.
UINT8 | Channel
Offset 1 Zero based Channel number.
UINT8 | Dimm
Offset 2 Zero based DIMM number.
UINT8 | Rank
Offset 3 Zero based Rank number.
UINT8 | BankGroup
Offset 4 Zero based Bank Group number.
UINT8 | Bank
Offset 5 Zero based Bank number.
UINT16 | Cas
Offset 6 Zero based CAS number.
UINT32 | Ras
Offset 8 Zero based RAS number.

Detailed Description

SA memory address decode.

Definition at line 168 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_ADDRESS_DECODE Member List

This is the complete list of members for SA_ADDRESS_DECODE, including all inherited members.

Bank | SA_ADDRESS_DECODE
BankGroup | SA_ADDRESS_DECODE
Cas | SA_ADDRESS_DECODE
Channel | SA_ADDRESS_DECODE
Controller | SA_ADDRESS_DECODE
Dimm | SA_ADDRESS_DECODE
Rank | SA_ADDRESS_DECODE
Ras | SA_ADDRESS_DECODE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_DATA_HOB Struct Reference

Public Attributes | List of all members
SA_DATA_HOB Struct Reference

System Agent Data Hob. More...

#include <SaDataHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
GUID Hob type structure for gSaDataHobGuid.
BOOLEAN | ResizableBarSupport
Resizable BAR Support.
UINT8 | Rsvd1 [2]
Reserved for future use.

Detailed Description

System Agent Data Hob.

Definition at line 48 of file SaDataHob.h.

The documentation for this struct was generated from the following file:
  • SaDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_DATA_HOB Member List

This is the complete list of members for SA_DATA_HOB, including all inherited members.

EfiHobGuidType | SA_DATA_HOB
ResizableBarSupport | SA_DATA_HOB
Rsvd1 | SA_DATA_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_FUNCTION_CALLS Struct Reference

Public Attributes | List of all members
SA_FUNCTION_CALLS Struct Reference

Function calls into the SA. More...

#include <MemoryConfig.h>

Public Attributes

SA_IO_READ_8 IoRead8
Offset 0: - CPU I/O port 8-bit read.
SA_IO_READ_16 IoRead16
Offset 4: - CPU I/O port 16-bit read.
SA_IO_READ_32 IoRead32
Offset 8: - CPU I/O port 32-bit read.
SA_IO_WRITE_8 IoWrite8
Offset 12: - CPU I/O port 8-bit write.
SA_IO_WRITE_16 IoWrite16
Offset 16: - CPU I/O port 16-bit write.
SA_IO_WRITE_32 IoWrite32
Offset 20: - CPU I/O port 32-bit write.
SA_MMIO_READ_8 MmioRead8
Offset 24: - Memory Mapped I/O port 8-bit read.
SA_MMIO_READ_16 MmioRead16
Offset 28: - Memory Mapped I/O port 16-bit read.
SA_MMIO_READ_32 MmioRead32
Offset 32: - Memory Mapped I/O port 32-bit read.
SA_MMIO_READ_64 MmioRead64
Offset 36: - Memory Mapped I/O port 64-bit read.
SA_MMIO_WRITE_8 MmioWrite8
Offset 40: - Memory Mapped I/O port 8-bit write.
SA_MMIO_WRITE_16 MmioWrite16
Offset 44: - Memory Mapped I/O port 16-bit write.
SA_MMIO_WRITE_32 MmioWrite32
Offset 48: - Memory Mapped I/O port 32-bit write.
SA_MMIO_WRITE_64 MmioWrite64
Offset 52: - Memory Mapped I/O port 64-bit write.
SA_SMBUS_READ_8 SmbusRead8
Offset 56: - Smbus 8-bit read.
SA_SMBUS_READ_16 SmbusRead16
Offset 60: - Smbus 16-bit read.
SA_SMBUS_WRITE_8 SmbusWrite8
Offset 64: - Smbus 8-bit write.
SA_SMBUS_WRITE_16 SmbusWrite16
Offset 68: - Smbus 16-bit write.
SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress
Offset 72: - Get PCI device address.
SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress
Offset 76: - Get PCI express device address.
SA_GET_RTC_TIME GetRtcTime
Offset 80: - Get the current time value.
SA_GET_CPU_TIME GetCpuTime
Offset 84: - The current CPU time in milliseconds.
SA_MEMORY_COPY CopyMem
Offset 88: - Perform byte copy operation.
SA_MEMORY_SET_BYTE SetMem
Offset 92: - Perform byte initialization operation.
SA_MEMORY_SET_WORD SetMemWord
Offset 96: - Perform word initialization operation.
SA_MEMORY_SET_DWORD SetMemDword
Offset 100: - Perform dword initialization operation.
SA_LEFT_SHIFT_64 LeftShift64
Offset 104: - Left shift the 64-bit data value by specified number of bits.
SA_RIGHT_SHIFT_64 RightShift64
Offset 108: - Right shift the 64-bit data value by specified number of bits.
SA_MULT_U64_U32 MultU64x32
Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
SA_DIV_U64_U64 DivU64x64
Offset 116: - Divide a 64-bit data value by a 64-bit data value.
SA_GET_SPD_DATA GetSpdData
Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
SA_GET_RANDOM_NUMBER GetRandomNumber
Offset 124: - Get the next random 32-bit number.
SA_CPU_MAILBOX_READ CpuMailboxRead
Offset 128: - Perform a CPU mailbox read.
SA_CPU_MAILBOX_WRITE CpuMailboxWrite
Offset 132: - Perform a CPU mailbox write.
SA_GET_MEMORY_VDD GetMemoryVdd
Offset 136: - Get the current memory voltage (VDD).
SA_SET_MEMORY_VDD SetMemoryVdd
Offset 140: - Set the memory voltage (VDD) to the given value.
SA_CHECKPOINT CheckPoint
Offset 144: - Check point that is called at various points in the MRC.
SA_DEBUG_HOOK DebugHook
Offset 148: - Typically used to display to the I/O port 80h.
SA_DEBUG_PRINT DebugPrint
Offset 152: - Output a string to the debug stream/device.
SA_GET_RTC_CMOS GetRtcCmos
Offset 156: - Get the current value of the specified RTC CMOS location.
SA_MSR_READ_64 ReadMsr64
Offset 160: - Get the current value of the specified MSR location.
SA_MSR_WRITE_64 WriteMsr64
Offset 164 - Set the current value of the specified MSR location.
SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc
Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
SA_MRC_DRAM_RESET MrcDramReset
Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
SA_DELAY_NS MrcDelayNs
Offset 176 - Delay (stall) for the given amount of nanoseconds.
SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage
Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.

Detailed Description

Function calls into the SA.

Definition at line 240 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_FUNCTION_CALLS Member List

This is the complete list of members for SA_FUNCTION_CALLS, including all inherited members.

CheckPoint | SA_FUNCTION_CALLS
CopyMem | SA_FUNCTION_CALLS
CpuMailboxRead | SA_FUNCTION_CALLS
CpuMailboxWrite | SA_FUNCTION_CALLS
DebugHook | SA_FUNCTION_CALLS
DebugPrint | SA_FUNCTION_CALLS
DivU64x64 | SA_FUNCTION_CALLS
GetCpuTime | SA_FUNCTION_CALLS
GetMemoryVdd | SA_FUNCTION_CALLS
GetPciDeviceAddress | SA_FUNCTION_CALLS
GetPcieDeviceAddress | SA_FUNCTION_CALLS
GetRandomNumber | SA_FUNCTION_CALLS
GetRtcCmos | SA_FUNCTION_CALLS
GetRtcTime | SA_FUNCTION_CALLS
GetSpdData | SA_FUNCTION_CALLS
IoRead16 | SA_FUNCTION_CALLS
IoRead32 | SA_FUNCTION_CALLS
IoRead8 | SA_FUNCTION_CALLS
IoWrite16 | SA_FUNCTION_CALLS
IoWrite32 | SA_FUNCTION_CALLS
IoWrite8 | SA_FUNCTION_CALLS
LeftShift64 | SA_FUNCTION_CALLS
MmioRead16 | SA_FUNCTION_CALLS
MmioRead32 | SA_FUNCTION_CALLS
MmioRead64 | SA_FUNCTION_CALLS
MmioRead8 | SA_FUNCTION_CALLS
MmioWrite16 | SA_FUNCTION_CALLS
MmioWrite32 | SA_FUNCTION_CALLS
MmioWrite64 | SA_FUNCTION_CALLS
MmioWrite8 | SA_FUNCTION_CALLS
MrcDelayNs | SA_FUNCTION_CALLS
MrcDramReset | SA_FUNCTION_CALLS
MrcReturnFromSmc | SA_FUNCTION_CALLS
MultU64x32 | SA_FUNCTION_CALLS
ReadMsr64 | SA_FUNCTION_CALLS
RightShift64 | SA_FUNCTION_CALLS
SetMem | SA_FUNCTION_CALLS
SetMemDword | SA_FUNCTION_CALLS
SetMemoryPmicVoltage | SA_FUNCTION_CALLS
SetMemoryVdd | SA_FUNCTION_CALLS
SetMemWord | SA_FUNCTION_CALLS
SmbusRead16 | SA_FUNCTION_CALLS
SmbusRead8 | SA_FUNCTION_CALLS
SmbusWrite16 | SA_FUNCTION_CALLS
SmbusWrite8 | SA_FUNCTION_CALLS
WriteMsr64 | SA_FUNCTION_CALLS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_GPIO_INFO_PCIE Struct Reference

Public Attributes | List of all members
SA_GPIO_INFO_PCIE Struct Reference

SA GPIO Data Structure. More...

#include <CpuPcieConfigGen3.h>

Public Attributes

GPIO_PAD GpioPad
Offset 0: GPIO Pad.
UINT8 | Value
Offset 4: GPIO Value.
UINT8 | Rsvd0 [3]
Offset 5: Reserved for 4 bytes alignment.
UINT32 | Active: 1
Offset 8: 0=Active Low; 1=Active High.

Detailed Description

SA GPIO Data Structure.

Definition at line 56 of file CpuPcieConfigGen3.h.

The documentation for this struct was generated from the following file:
  • CpuPcieConfigGen3.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_GPIO_INFO_PCIE Member List

This is the complete list of members for SA_GPIO_INFO_PCIE, including all inherited members.

Active | SA_GPIO_INFO_PCIE
GpioPad | SA_GPIO_INFO_PCIE
Rsvd0 | SA_GPIO_INFO_PCIE
Value | SA_GPIO_INFO_PCIE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_MEMORY_DQDQS_MAPPING Struct Reference

Public Attributes | List of all members
SA_MEMORY_DQDQS_MAPPING Struct Reference

DqDqs Mapping. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 | DqsMapCpu2Dram [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]
DqsMapCpu2Dram.
UINT8 | DqMapCpu2Dram [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]
DqMapCpu2Dram.

Detailed Description

DqDqs Mapping.

Definition at line 140 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_MEMORY_DQDQS_MAPPING Member List

This is the complete list of members for SA_MEMORY_DQDQS_MAPPING, including all inherited members.

DqMapCpu2Dram | SA_MEMORY_DQDQS_MAPPING
DqsMapCpu2Dram | SA_MEMORY_DQDQS_MAPPING
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_MEMORY_FUNCTIONS Struct Reference

Public Attributes | List of all members
SA_MEMORY_FUNCTIONS Struct Reference

Function calls into the MRC. More...

#include <MemoryConfig.h>

Public Attributes

SA_CHANNEL_EXIST MrcChannelExist
Offset 0: - Returns whether Channel is or is not present.
SA_PRINTF MrcPrintf
Offset 4: - Print to output stream/device.
SA_CHANGE_MARGIN MrcChangeMargin
Offset 8: - Change the margin.
SA_SIGN_EXTEND MrcSignExtend
Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain
Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
SA_UPDATE_VREF MrcUpdateVref
Offset 20: - Update the Vref value and wait until it is stable.

Detailed Description

Function calls into the MRC.

Definition at line 292 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_MEMORY_FUNCTIONS Member List

This is the complete list of members for SA_MEMORY_FUNCTIONS, including all inherited members.

MrcChangeMargin | SA_MEMORY_FUNCTIONS
MrcChannelExist | SA_MEMORY_FUNCTIONS
MrcPrintf | SA_MEMORY_FUNCTIONS
MrcSignExtend | SA_MEMORY_FUNCTIONS
MrcUpdateVref | SA_MEMORY_FUNCTIONS
ShiftPiCommandTrain | SA_MEMORY_FUNCTIONS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_MEMORY_RCOMP Struct Reference

Public Attributes | List of all members
SA_MEMORY_RCOMP Struct Reference

Rcomp Policies. More...

#include <MemoryConfig.h>

Public Attributes

UINT16 | RcompResistor
Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms.
UINT16 | RcompTarget [MRC_MAX_RCOMP_TARGETS]
Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv.

Detailed Description

Rcomp Policies.

Definition at line 149 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_MEMORY_RCOMP Member List

This is the complete list of members for SA_MEMORY_RCOMP, including all inherited members.

RcompResistor | SA_MEMORY_RCOMP
RcompTarget | SA_MEMORY_RCOMP
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_MISC_PEI_CONFIG Struct Reference

Public Attributes | List of all members
SA_MISC_PEI_CONFIG Struct Reference

This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem. More...

#include <SaMiscPeiConfig.h>

Collaboration diagram for SA_MISC_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.

Detailed Description

This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.

Revision 1:

  • Initial version.

Definition at line 47 of file SaMiscPeiConfig.h.

The documentation for this struct was generated from the following file:
  • SaMiscPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_MISC_PEI_CONFIG Member List

This is the complete list of members for SA_MISC_PEI_CONFIG, including all inherited members.

Header SA_MISC_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_MISC_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
SA_MISC_PEI_PREMEM_CONFIG Struct Reference

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

#include <SaMiscPeiPreMemConfig.h>

Collaboration diagram for SA_MISC_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | SpdAddressTable [MEM_CFG_MAX_SOCKETS]
Offset 28 Memory DIMMs' SPD address for reading SPD data. More...
VOID * | S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path.
UINT32 | SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
UINT32 | TsegSize
Offset 52 Size of TSEG in bytes. More...
UINT32 | IedSize
Offset 56 (Test) Size of IED region in bytes. More...
UINT32 | SkipExtGfxScan:1
(Test) OFfset 60:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
UINT32 | BdatEnable:1
Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE, 1=TRUE.
UINT32 | TxtImplemented:1
OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: 0=Run without waiting for TXT, 1=Run after TXT initialization by callback.
UINT32 | ScanExtGfxForLegacyOpRom:1
Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs. More...
UINT32 | RsvdBits0:28
Offset 60:4 :Reserved for future use.
UINT8 | UserBd
Offset 64 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server.
UINT8 | LockPTMregs
(Test) Offset 65 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
UINT8 | BdatTestType
Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: 0=RMT, 1=RMT Per Bit, 2=Margin 2D.
UINT8 | CridEnable
Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature: 0=FALSE, 1=TRUE.
UINT32 | AcpiReservedMemorySize
Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT32 | OpRomScanTempMmioBar
(Test) Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
UINT32 | OpRomScanTempMmioLimit
(Test) Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
UINT64 | AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT64 | SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
UINT8 | WrcFeatureEnable
Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.
UINT8 | FirstDimmBitMask
Offset 97: Defines which DIMM should be populated first on a 2DPC board. More...
UINT8 | FirstDimmBitMaskEcc
Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board. More...
UINT8 | Reserved1 [1]
Reserved for config block alignment.
UINT8 | Rsvd [4]
Reserved for config block alignment.

Detailed Description

This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc.

Revision 1:

  • Initial version. Revision 2:
  • Deprecate IedSize. Revision 3:
  • Adding ResizableBarSupport.

Definition at line 56 of file SaMiscPeiPreMemConfig.h.

Member Data Documentation

◆ FirstDimmBitMask

UINT8 SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMask

Offset 97: Defines which DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. Note: this mask is only for non-ECC DIMM.

Definition at line 124 of file SaMiscPeiPreMemConfig.h.

◆ FirstDimmBitMaskEcc

UINT8 SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMaskEcc

Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.

4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1. For each MC, the first DIMM to be populated should be set to '1'. For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be be populated firstly. Note: this mask is only for ECC DIMM, not for non-ECC DIMM.

Definition at line 128 of file SaMiscPeiPreMemConfig.h.

◆ IedSize

UINT32 SA_MISC_PEI_PREMEM_CONFIG::IedSize

Offset 56 (Test) Size of IED region in bytes.

0 : IED Disabled (no memory occupied) 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) Note: Enabling IED may also enlarge TsegSize together.

Deprecated:

Definition at line 91 of file SaMiscPeiPreMemConfig.h.

◆ ScanExtGfxForLegacyOpRom

UINT32 SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom

Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.

When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the graphics device for legacy only VGA OpROMs.

This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed. This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.

This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.

  • Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
  • Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM

Definition at line 111 of file SaMiscPeiPreMemConfig.h.

◆ SpdAddressTable

UINT8 SA_MISC_PEI_PREMEM_CONFIG::SpdAddressTable[MEM_CFG_MAX_SOCKETS]

Offset 28 Memory DIMMs' SPD address for reading SPD data.

TGL Mapping 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 1 - Controller 0 Channel 0 Dimm 1 - DDR4 2 - Controller 0 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 3 - Controller 0 Channel 1 Dimm 1 -----— DDR5 2DPC 4 - Controller 0 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 6 - Controller 0 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 9 - Controller 1 Channel 0 Dimm 1 - DDR4 10 - Controller 1 Channel 1 Dimm 0 -----— DDR5 - LPDDR4 - LPDDR5 11 - Controller 1 Channel 1 Dimm 1 -----— DDR5 2DPC 12 - Controller 1 Channel 2 Dimm 0 ------------— LPDDR4 - LPDDR5 14 - Controller 1 Channel 3 Dimm 0 ------------— LPDDR4 - LPDDR5

Definition at line 74 of file SaMiscPeiPreMemConfig.h.

◆ TsegSize

UINT32 SA_MISC_PEI_PREMEM_CONFIG::TsegSize

Offset 52 Size of TSEG in bytes.

(Must be power of 2) 0x400000: 4MB for Release build (When IED enabled, it will be 8MB) 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled)

Definition at line 82 of file SaMiscPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SaMiscPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_MISC_PEI_PREMEM_CONFIG Member List

This is the complete list of members for SA_MISC_PEI_PREMEM_CONFIG, including all inherited members.

AcpiReservedMemoryBase | SA_MISC_PEI_PREMEM_CONFIG
AcpiReservedMemorySize | SA_MISC_PEI_PREMEM_CONFIG
BdatEnable | SA_MISC_PEI_PREMEM_CONFIG
BdatTestType | SA_MISC_PEI_PREMEM_CONFIG
CridEnable | SA_MISC_PEI_PREMEM_CONFIG
FirstDimmBitMask | SA_MISC_PEI_PREMEM_CONFIG
FirstDimmBitMaskEcc | SA_MISC_PEI_PREMEM_CONFIG
Header | SA_MISC_PEI_PREMEM_CONFIG
IedSize | SA_MISC_PEI_PREMEM_CONFIG
LockPTMregs | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioBar | SA_MISC_PEI_PREMEM_CONFIG
OpRomScanTempMmioLimit | SA_MISC_PEI_PREMEM_CONFIG
Reserved1 | SA_MISC_PEI_PREMEM_CONFIG
Rsvd | SA_MISC_PEI_PREMEM_CONFIG
RsvdBits0 | SA_MISC_PEI_PREMEM_CONFIG
S3DataPtr | SA_MISC_PEI_PREMEM_CONFIG
ScanExtGfxForLegacyOpRom | SA_MISC_PEI_PREMEM_CONFIG
SkipExtGfxScan | SA_MISC_PEI_PREMEM_CONFIG
SmbusBar | SA_MISC_PEI_PREMEM_CONFIG
SpdAddressTable | SA_MISC_PEI_PREMEM_CONFIG
SystemMemoryLength | SA_MISC_PEI_PREMEM_CONFIG
TsegSize | SA_MISC_PEI_PREMEM_CONFIG
TxtImplemented | SA_MISC_PEI_PREMEM_CONFIG
UserBd | SA_MISC_PEI_PREMEM_CONFIG
WrcFeatureEnable | SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_PEG_DATA Struct Reference

Public Attributes | List of all members
SA_PEG_DATA Struct Reference

PEG data definition This structure can be saved in non-volatile memory to be re-used in the following boot. More...

#include <CpuPcieHobGen3.h>

Public Attributes

UINT32 | EndPointVendorIdDeviceId [SA_PEG_MAX_FUN_GEN3]
Offset 0 - 11: VID/DID for each PEG controller.
UINT8 | BestPreset [SA_PEG_MAX_LANE_GEN3]
Offset 12 - 27: Best preset value for each lane.
UINT8 | PegGen3PresetSearch
Offset 28: Preset search value.
UINT8 | PegLinkFailMask
Offset 29: Mask of PEG controllers to ignore.
UINT8 | Rsvd0 [2]
Offset 30: Reserved for future use.

Detailed Description

PEG data definition This structure can be saved in non-volatile memory to be re-used in the following boot.

By this way reference code will not re-do PCIe Preset Search and save POST time SI_POLICY_PPI can be used to pass the pointer of pre-saved SA_PEG_DATA by platform code

Definition at line 50 of file CpuPcieHobGen3.h.

The documentation for this struct was generated from the following file:
  • CpuPcieHobGen3.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_PEG_DATA Member List

This is the complete list of members for SA_PEG_DATA, including all inherited members.

BestPreset | SA_PEG_DATA
EndPointVendorIdDeviceId | SA_PEG_DATA
PegGen3PresetSearch | SA_PEG_DATA
PegLinkFailMask | SA_PEG_DATA
Rsvd0 | SA_PEG_DATA
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_PEG_HOB Struct Reference

Public Attributes | List of all members
SA_PEG_HOB Struct Reference

System Agent PEG NVS Hob. More...

#include <CpuPcieHobGen3.h>

Collaboration diagram for SA_PEG_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gSaPegHobGuid.
BOOLEAN | InitPcieAspmAfterOprom
1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
SA_PEG_DATA PegData
Offset 24 (Move to FSP NVS Hob) PEG data definition.
UINT8 | PowerDownUnusedBundles [SA_PEG_MAX_FUN_GEN3]
PCIe power down unused bundles support.
BOOLEAN | PegPlatformResetRequired
1=platform code should generate a cold/power cycle reset after saving PEG config data into NVRAM

Detailed Description

System Agent PEG NVS Hob.

Definition at line 61 of file CpuPcieHobGen3.h.

The documentation for this struct was generated from the following file:
  • CpuPcieHobGen3.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_PEG_HOB Member List

This is the complete list of members for SA_PEG_HOB, including all inherited members.

EfiHobGuidType | SA_PEG_HOB
InitPcieAspmAfterOprom | SA_PEG_HOB
PegData | SA_PEG_HOB
PegPlatformResetRequired | SA_PEG_HOB
PowerDownUnusedBundles | SA_PEG_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_POLICY_PROTOCOL Struct Reference

Public Attributes | List of all members
SA_POLICY_PROTOCOL Struct Reference

SA DXE Policy. More...

#include <SaPolicy.h>

Collaboration diagram for SA_POLICY_PROTOCOL:
[legend]

Public Attributes

CONFIG_BLOCK_TABLE_HEADER TableHeader
Offset 0-31.

Detailed Description

SA DXE Policy.

The SA_POLICY_PROTOCOL producer drvier is recommended to set all the SA_POLICY_PROTOCOL size buffer zero before init any member parameter, this clear step can make sure no random value for those unknow new version parameters.

Make sure to update the Revision if any change to the protocol, including the existing internal structure definations.
Note: Here revision will be bumped up when adding/removing any config block under this structure.
Revision 1:

  • Initial version.

Definition at line 82 of file SaPolicy.h.

The documentation for this struct was generated from the following file:
  • SaPolicy.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_POLICY_PROTOCOL Member List

This is the complete list of members for SA_POLICY_PROTOCOL, including all inherited members.

TableHeader SA_POLICY_PROTOCOL
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SA_XDCI_IRQ_INT_CONFIG Struct Reference

Public Attributes | List of all members
SA_XDCI_IRQ_INT_CONFIG Struct Reference

The SA XDCI INT Pin and IRQ number. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | IntPing
Int Pin Number.
UINT8 | Irq
Irq Number.

Detailed Description

The SA XDCI INT Pin and IRQ number.

Definition at line 82 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SA_XDCI_IRQ_INT_CONFIG Member List

This is the complete list of members for SA_XDCI_IRQ_INT_CONFIG, including all inherited members.

IntPing | SA_XDCI_IRQ_INT_CONFIG
Irq | SA_XDCI_IRQ_INT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SATA_CONFIG Struct Reference

Public Attributes | List of all members
SATA_CONFIG Struct Reference

The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

#include <SataConfig.h>

Collaboration diagram for SATA_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | Enable
This member describes whether or not the SATA controllers should be enabled. More...
UINT8 | TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
UINT8 | SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
UINT8 | PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
UINT8 | EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
UINT8 | LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
UINT8 | RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode. More...
UINT8 | SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect only if SATA controller is in RAID mode Default: PchSataMsix
UINT8 | SataMode
Determines the system will be configured to which SATA mode. More...
UINT8 | SpeedLimit
Indicates the maximum speed the SATA controller can support. More...
UINT8 | EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
UINT8 | SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
PCH_SATA_PORT_CONFIG | PortSettings [PCH_MAX_SATA_PORTS]
This member configures the features, property, and capability for each SATA port.
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling. More...

Detailed Description

The SATA_CONFIG block describes the expected configuration of the SATA controllers.

Revision 1:

  • Initial version. Revision 2:
  • Added DevSlpGpioPinMux.

Definition at line 134 of file SataConfig.h.

Member Data Documentation

◆ Enable

UINT8 SATA_CONFIG::Enable

This member describes whether or not the SATA controllers should be enabled.

0: Disable; 1: Enable.

Definition at line 139 of file SataConfig.h.

◆ EsataSpeedLimit

UINT8 SATA_CONFIG::EsataSpeedLimit

EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.

Please be noted, this setting could be cleared by HBA reset, which might be issued by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST. To support the Speed Limitation when POST, the EFI AHCI driver should preserve the setting before and after initialization. For support it after POST, it's dependent on driver's behavior. 0: Disable; 1: Enable

Definition at line 153 of file SataConfig.h.

◆ RaidDeviceId

UINT8 SATA_CONFIG::RaidDeviceId

This option allows to configure SATA controller device ID while in RAID mode.

Refer to SATA_RAID_DEV_ID enumeration for supported options. Choosing Client will allow RST driver loading, RSTe driver will not be able to load Choosing Alternate will not allow RST inbox driver loading in Windows Choosing Server will allow RSTe driver loading, RST driver will not load 0: Client; 1: Alternate; 2: Server

Definition at line 163 of file SataConfig.h.

◆ SataMode

UINT8 SATA_CONFIG::SataMode

Determines the system will be configured to which SATA mode.

Refer to SATA_MODE enumeration for supported options. Default is SataModeAhci.

Definition at line 175 of file SataConfig.h.

◆ SpeedLimit

UINT8 SATA_CONFIG::SpeedLimit

Indicates the maximum speed the SATA controller can support.

Refer to SATA_SPEED enumeration for supported options. 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)

Definition at line 181 of file SataConfig.h.

◆ ThermalThrottling

SATA_THERMAL_THROTTLING SATA_CONFIG::ThermalThrottling

This field decides the settings of Sata thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 196 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SATA_CONFIG Member List

This is the complete list of members for SATA_CONFIG, including all inherited members.

Enable | SATA_CONFIG
EnclosureSupport | SATA_CONFIG
EsataSpeedLimit | SATA_CONFIG
Header | SATA_CONFIG
LedEnable | SATA_CONFIG
PortSettings | SATA_CONFIG
PwrOptEnable | SATA_CONFIG
RaidDeviceId | SATA_CONFIG
SalpSupport | SATA_CONFIG
SataMode | SATA_CONFIG
SataRstInterrupt | SATA_CONFIG
SgpioSupport | SATA_CONFIG
SpeedLimit | SATA_CONFIG
TestMode | SATA_CONFIG
ThermalThrottling | SATA_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SATA_THERMAL_THROTTLING Struct Reference

Public Attributes | List of all members
SATA_THERMAL_THROTTLING Struct Reference

This structure lists PCH supported SATA thermal throttling register setting for customization. More...

#include <SataConfig.h>

Public Attributes

UINT32 | P0T1M: 2
Port 0 T1 Multipler.
UINT32 | P0T2M: 2
Port 0 T2 Multipler.
UINT32 | P0T3M: 2
Port 0 T3 Multipler.
UINT32 | P0TDisp: 2
Port 0 Tdispatch.
UINT32 | P1T1M: 2
Port 1 T1 Multipler.
UINT32 | P1T2M: 2
Port 1 T2 Multipler.
UINT32 | P1T3M: 2
Port 1 T3 Multipler.
UINT32 | P1TDisp: 2
Port 1 Tdispatch.
UINT32 | P0Tinact: 2
Port 0 Tinactive.
UINT32 | P0TDispFinit: 1
Port 0 Alternate Fast Init Tdispatch.
UINT32 | P1Tinact: 2
Port 1 Tinactive.
UINT32 | P1TDispFinit: 1
Port 1 Alternate Fast Init Tdispatch.
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values
UINT32 | RsvdBits0: 9
Reserved bits.

Detailed Description

This structure lists PCH supported SATA thermal throttling register setting for customization.

The settings is programmed through SATA Index/Data registers. When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 107 of file SataConfig.h.

The documentation for this struct was generated from the following file:
  • SataConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SATA_THERMAL_THROTTLING Member List

This is the complete list of members for SATA_THERMAL_THROTTLING, including all inherited members.

P0T1M | SATA_THERMAL_THROTTLING
P0T2M | SATA_THERMAL_THROTTLING
P0T3M | SATA_THERMAL_THROTTLING
P0TDisp | SATA_THERMAL_THROTTLING
P0TDispFinit | SATA_THERMAL_THROTTLING
P0Tinact | SATA_THERMAL_THROTTLING
P1T1M | SATA_THERMAL_THROTTLING
P1T2M | SATA_THERMAL_THROTTLING
P1T3M | SATA_THERMAL_THROTTLING
P1TDisp | SATA_THERMAL_THROTTLING
P1TDispFinit | SATA_THERMAL_THROTTLING
P1Tinact | SATA_THERMAL_THROTTLING
RsvdBits0 | SATA_THERMAL_THROTTLING
SuggestedSetting | SATA_THERMAL_THROTTLING
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SCS_SD_DLL Struct Reference

List of all members
SCS_SD_DLL Struct Reference

This structre holds the DLL configuration register values that will be programmed by RC if EnableCustomDlls field is set to TRUE. More...

#include <ScsConfig.h>

Detailed Description

This structre holds the DLL configuration register values that will be programmed by RC if EnableCustomDlls field is set to TRUE.

Those policies should be used by platform if default values provided by RC are not sufficient to provide stable operation at all supported spped modes. RC will blindly set the DLL values as provided in this structre.

For help with obtaining valid DLL values for your platform please contact enabling support.

Definition at line 66 of file ScsConfig.h.

The documentation for this struct was generated from the following file:
  • ScsConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SCS_SD_DLL Member List

This is the complete list of members for SCS_SD_DLL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SERIAL_IO_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_CONFIG Struct Reference

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

#include <SerialIoConfig.h>

Collaboration diagram for SERIAL_IO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
SERIAL_IO_SPI_CONFIG | SpiDeviceConfig [PCH_MAX_SERIALIO_SPI_CONTROLLERS]
SPI Configuration.
SERIAL_IO_I2C_CONFIG | I2cDeviceConfig [PCH_MAX_SERIALIO_I2C_CONTROLLERS]
I2C Configuration.
SERIAL_IO_UART_CONFIG | UartDeviceConfig [PCH_MAX_SERIALIO_UART_CONTROLLERS]
UART Configuration.

Detailed Description

The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.

Revision 1:

  • Inital version. Revision 2:
  • Modified SPI Config to support pinmux functionality.

Definition at line 53 of file SerialIoConfig.h.

The documentation for this struct was generated from the following file:
  • SerialIoConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SERIAL_IO_CONFIG Member List

This is the complete list of members for SERIAL_IO_CONFIG, including all inherited members.

Header | SERIAL_IO_CONFIG
I2cDeviceConfig | SERIAL_IO_CONFIG
SpiDeviceConfig | SERIAL_IO_CONFIG
UartDeviceConfig | SERIAL_IO_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SERIAL_IO_I2C_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_I2C_CONFIG Struct Reference

Serial IO I2C Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_I2C_CONFIG:
[legend]

Public Attributes

UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE More...
I2C_PIN_MUX PinMux
I2C pin mux configuration.

Detailed Description

Serial IO I2C Controller Configuration.

Definition at line 236 of file SerialIoDevices.h.

Member Data Documentation

◆ PadTermination

UINT8 SERIAL_IO_I2C_CONFIG::PadTermination

SerialIoI2cPci see SERIAL_IO_I2C_MODE

I2C Pads Internal Termination. For more information please see Platform Design Guide. Supported values (check GPIO_ELECTRICAL_CONFIG for reference): GpioTermNone: No termination, GpioTermWpu1K: 1kOhm weak pull-up, GpioTermWpu5K: 5kOhm weak pull-up, GpioTermWpu20K: 20kOhm weak pull-up

Definition at line 247 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SERIAL_IO_I2C_CONFIG Member List

This is the complete list of members for SERIAL_IO_I2C_CONFIG, including all inherited members.

PadTermination | SERIAL_IO_I2C_CONFIG
PinMux | SERIAL_IO_I2C_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SERIAL_IO_SPI_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_SPI_CONFIG Struct Reference

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_SPI_CONFIG:
[legend]

Public Attributes

UINT8 | Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
UINT8 | DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
UINT8 | CsPolarity [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
Selects SPI ChipSelect signal polarity, 0 = low 1 = High
UINT8 | CsEnable [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
0 = Enable 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
UINT8 | CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
UINT8 | CsState
0 = CS is set to low 1 = CS is set to high
SPI_PIN_MUX PinMux
SPI Pinmux configuration.

Detailed Description

The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.

Definition at line 94 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SERIAL_IO_SPI_CONFIG Member List

This is the complete list of members for SERIAL_IO_SPI_CONFIG, including all inherited members.

CsEnable | SERIAL_IO_SPI_CONFIG
CsMode | SERIAL_IO_SPI_CONFIG
CsPolarity | SERIAL_IO_SPI_CONFIG
CsState | SERIAL_IO_SPI_CONFIG
DefaultCsOutput | SERIAL_IO_SPI_CONFIG
Mode | SERIAL_IO_SPI_CONFIG
PinMux | SERIAL_IO_SPI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SERIAL_IO_UART_ATTRIBUTES Struct Reference

Public Attributes | List of all members
SERIAL_IO_UART_ATTRIBUTES Struct Reference

UART Settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
UINT8 | Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
UINT8 | DataBits
8 MdePkg.dec PcdUartDefaultDataBits
UINT8 | StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
UINT8 | AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake

Detailed Description

UART Settings.

Definition at line 151 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SERIAL_IO_UART_ATTRIBUTES Member List

This is the complete list of members for SERIAL_IO_UART_ATTRIBUTES, including all inherited members.

AutoFlow | SERIAL_IO_UART_ATTRIBUTES
BaudRate | SERIAL_IO_UART_ATTRIBUTES
DataBits | SERIAL_IO_UART_ATTRIBUTES
Parity | SERIAL_IO_UART_ATTRIBUTES
StopBits | SERIAL_IO_UART_ATTRIBUTES
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SERIAL_IO_UART_CONFIG Struct Reference

Public Attributes | List of all members
SERIAL_IO_UART_CONFIG Struct Reference

Serial IO UART Controller Configuration. More...

#include <SerialIoDevices.h>

Collaboration diagram for SERIAL_IO_UART_CONFIG:
[legend]

Public Attributes

SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
UART_PIN_MUX PinMux
UART pin mux configuration.
UINT8 | Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
UINT8 | DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
UINT8 | PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
UINT8 | DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode

Detailed Description

Serial IO UART Controller Configuration.

Definition at line 174 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SERIAL_IO_UART_CONFIG Member List

This is the complete list of members for SERIAL_IO_UART_CONFIG, including all inherited members.

Attributes | SERIAL_IO_UART_CONFIG
DBG2 | SERIAL_IO_UART_CONFIG
DmaEnable | SERIAL_IO_UART_CONFIG
Mode | SERIAL_IO_UART_CONFIG
PinMux | SERIAL_IO_UART_CONFIG
PowerGating | SERIAL_IO_UART_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SET_FILE Struct Reference

Public Attributes | List of all members
SET_FILE Struct Reference

Set File, Ver3 API only. More...

#include <MkhiMsgs.h>

Collaboration diagram for SET_FILE:
[legend]

Public Attributes

UINT8 Data []
Data Buffer.

Detailed Description

Set File, Ver3 API only.

Definition at line 653 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SET_FILE Member List

This is the complete list of members for SET_FILE, including all inherited members.

Data SET_FILE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SET_FILE_EX Struct Reference

Public Attributes | List of all members
SET_FILE_EX Struct Reference

Set File Ex. More...

#include <MkhiMsgs.h>

Collaboration diagram for SET_FILE_EX:
[legend]

Public Attributes

UINT8 Data []
Data Buffer.

Detailed Description

Set File Ex.

Definition at line 744 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SET_FILE_EX Member List

This is the complete list of members for SET_FILE_EX, including all inherited members.

Data SET_FILE_EX
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SET_ME_RESET_HALT Struct Reference

List of all members
SET_ME_RESET_HALT Struct Reference

Set Manufacturing ME Reset and Halt messages. More...

#include <MkhiMsgs.h>

Collaboration diagram for SET_ME_RESET_HALT:
[legend]

Detailed Description

Set Manufacturing ME Reset and Halt messages.

Definition at line 1051 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SET_ME_RESET_HALT Member List

This is the complete list of members for SET_ME_RESET_HALT, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SET_MEASURED_BOOT Struct Reference

List of all members
SET_MEASURED_BOOT Struct Reference

Set CSME Measured Boot. More...

#include <MkhiMsgs.h>

Collaboration diagram for SET_MEASURED_BOOT:
[legend]

Detailed Description

Set CSME Measured Boot.

Definition at line 1184 of file MkhiMsgs.h.

The documentation for this struct was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SET_MEASURED_BOOT Member List

This is the complete list of members for SET_MEASURED_BOOT, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SFAM_DATA Struct Reference

Public Attributes | List of all members
SFAM_DATA Struct Reference

Signed Flash map descriptor definition. More...

#include <BiosGuard.h>

Public Attributes

UINT32 | FirstByte
Linear flash address of the first byte of the signed range, must be aligned to be first byte in the block. Ordering is little-endian.
UINT32 | LastByte
Linear flash address of the last byte of the signed range, must be aligned to be last byte in the block. Ordering is little-endian.

Detailed Description

Signed Flash map descriptor definition.

Definition at line 150 of file BiosGuard.h.

The documentation for this struct was generated from the following file:
  • BiosGuard.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SFAM_DATA Member List

This is the complete list of members for SFAM_DATA, including all inherited members.

FirstByte | SFAM_DATA
LastByte | SFAM_DATA
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SGX_INFO Struct Reference

Public Attributes | List of all members
SGX_INFO Struct Reference

#include <CpuInfo.h>

Public Attributes

UINT64 SgxSinitNvsData
Sinit SE SVN Version saved and passed back in next boot.

Detailed Description

Deprecated:
due to Non-POR feature SGX Information

Definition at line 131 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SGX_INFO Member List

This is the complete list of members for SGX_INFO, including all inherited members.

SgxSinitNvsData SGX_INFO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SI_CONFIG Struct Reference

Public Attributes | List of all members
SI_CONFIG Struct Reference

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiConfig.h>

Collaboration diagram for SI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT8 | CsmFlag
offset 28 CSM status flag. More...
UINT8 | SkipSsidProgramming
This is used to skip the SSID programming in silicon code. More...
UINT8 | RsvdBytes0 [2]
offset 30 - 31
UINT16 | CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices. More...
UINT16 | CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices. More...
UINT32 * | SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table. More...
UINT16 | NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr. More...
UINT8 | RsvdBytes1 [2]
offset 42 - 43
UINT8 | SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode. More...
UINT8 | RsvdBytes2 [3]
Offset 45 - 47.

Detailed Description

The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1: - Initial version. Revision 2: - Deprecate CsmFlag

Definition at line 52 of file SiConfig.h.

Member Data Documentation

◆ CsmFlag

UINT8 SI_CONFIG::CsmFlag

offset 28 CSM status flag.

Deprecated:

Definition at line 57 of file SiConfig.h.

◆ CustomizedSsid

UINT16 SI_CONFIG::CustomizedSsid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for all internal devices.

0: use silicon default SSID 0x7270 , Non-zero: use customized SSID. offset 34 - 35

Definition at line 77 of file SiConfig.h.

◆ CustomizedSvid

UINT16 SI_CONFIG::CustomizedSvid

When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID for all internal devices.

0: use silicon default SVID 0x8086 , Non-zero: use customized SVID. offset 32 - 33

Definition at line 71 of file SiConfig.h.

◆ NumberOfSsidTableEntry

UINT16 SI_CONFIG::NumberOfSsidTableEntry

Number of valid enties in SsidTablePtr.

This is valid when SkipSsidProgramming is FALSE; Default is 0. offset 40 - 41

Definition at line 116 of file SiConfig.h.

◆ SkipBiosDoneWhenFwUpdate

UINT8 SI_CONFIG::SkipBiosDoneWhenFwUpdate

This is used to skip setting BIOS_DONE MSR during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting BIOS_DONE MSR at EndofPei. 0: FALSE, 1: TRUE Offset 44

Definition at line 124 of file SiConfig.h.

◆ SkipSsidProgramming

UINT8 SI_CONFIG::SkipSsidProgramming

This is used to skip the SSID programming in silicon code.

When set to TRUE, silicon code will not do any SSID programming and platform code needs to handle that by itself properly. 0: FALSE, 1: TRUE offset 29

Definition at line 64 of file SiConfig.h.

◆ SsidTablePtr

UINT32* SI_CONFIG::SsidTablePtr

SsidTablePtr contains the SVID_SID_INIT_ENTRY table.

This is valid when SkipSsidProgramming is FALSE; It doesn't need to contain entries for all Intel internal devices. It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs to be overridden. In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required. Default is NULL.

E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD, it can be done in platform like this: STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};

VOID SiPolicyUpdate () { UINT32 EntryCount = 0; SiPolicy->SkipSsidProgramming = FALSE; SiPolicy->SsidTablePtr = mSsidTablePtr;

mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB; EntryCount ++; mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber (); mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber (); mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC; mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD; EntryCount ++; ASSERT (EntryCount < SI_MAX_DEVICE_COUNT); SiPolicy->NumberOfSsidTableEntry = EntryCount; } offset 36 - 39

Definition at line 110 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SI_CONFIG Member List

This is the complete list of members for SI_CONFIG, including all inherited members.

CsmFlag | SI_CONFIG
CustomizedSsid | SI_CONFIG
CustomizedSvid | SI_CONFIG
Header | SI_CONFIG
NumberOfSsidTableEntry | SI_CONFIG
RsvdBytes0 | SI_CONFIG
RsvdBytes1 | SI_CONFIG
RsvdBytes2 | SI_CONFIG
SkipBiosDoneWhenFwUpdate | SI_CONFIG
SkipSsidProgramming | SI_CONFIG
SsidTablePtr | SI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
SI_PREMEM_CONFIG Struct Reference

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

#include <SiPreMemConfig.h>

Collaboration diagram for SI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
UINT32 | PlatformDebugConsent: 4
Platform Debug Consent As a main switch to enable platform debug capability and relevant settings with specified probe type. More...
UINT32 | RsvdBits: 28
offset 28 - 31
UINT8 | SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode. More...
UINT8 | RsvdBytes [3]
offset 32

Detailed Description

The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware.

Revision 1:

  • Initial version.

Definition at line 58 of file SiPreMemConfig.h.

Member Data Documentation

◆ PlatformDebugConsent

UINT32 SI_PREMEM_CONFIG::PlatformDebugConsent

Platform Debug Consent As a main switch to enable platform debug capability and relevant settings with specified probe type.

Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.

PDC-dependent policies are listed: DciPreMemConfig->DciEn CpuTraceHubConfig->EnableMode CpuTraceHubConfig->CpuTraceHubMemReg0Size CpuTraceHubConfig->CpuTraceHubMemReg1Size PchTraceHubPreMemConfig->EnableMode PchTraceHubPreMemConfig->MemReg0Size PchTraceHubPreMemConfig->MemReg1Size

Note: DCI OOB (aka BSSB) uses CCA probe. Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE 0:Disabled; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual

Definition at line 78 of file SiPreMemConfig.h.

◆ SkipOverrideBootModeWhenFwUpdate

UINT8 SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate

This is used to skip override boot mode during firmware update boot mode.

When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init. 0: FALSE, 1: TRUE

Definition at line 86 of file SiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • SiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SI_PREMEM_CONFIG Member List

This is the complete list of members for SI_PREMEM_CONFIG, including all inherited members.

Header | SI_PREMEM_CONFIG
PlatformDebugConsent | SI_PREMEM_CONFIG
RsvdBits | SI_PREMEM_CONFIG
RsvdBytes | SI_PREMEM_CONFIG
SkipOverrideBootModeWhenFwUpdate | SI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMBIOS_CACHE_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_CACHE_INFO Struct Reference

SMBIOS Cache Info HOB Structure. More...

#include <SmbiosCacheInfoHob.h>

Public Attributes

UINT16 | NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
UINT8 | SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
UINT16 | CacheConfiguration
Format defined in SMBIOS Spec v3.1 Section7.8 Table36.
UINT16 | MaxCacheSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT16 | InstalledSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT16 | SupportedSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
UINT16 | CurrentSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
UINT8 | CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 | ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3.
UINT8 | SystemCacheType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4.
UINT8 | Associativity
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5.
UINT32 | MaximumCacheSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
UINT32 | InstalledSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.

Detailed Description

SMBIOS Cache Info HOB Structure.

Definition at line 31 of file SmbiosCacheInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosCacheInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMBIOS_CACHE_INFO Member List

This is the complete list of members for SMBIOS_CACHE_INFO, including all inherited members.

Associativity | SMBIOS_CACHE_INFO
CacheConfiguration | SMBIOS_CACHE_INFO
CacheSpeed | SMBIOS_CACHE_INFO
CurrentSramType | SMBIOS_CACHE_INFO
ErrorCorrectionType | SMBIOS_CACHE_INFO
InstalledSize | SMBIOS_CACHE_INFO
InstalledSize2 | SMBIOS_CACHE_INFO
MaxCacheSize | SMBIOS_CACHE_INFO
MaximumCacheSize2 | SMBIOS_CACHE_INFO
NumberOfCacheLevels | SMBIOS_CACHE_INFO
SocketDesignationStrIndex | SMBIOS_CACHE_INFO
SupportedSramType | SMBIOS_CACHE_INFO
SystemCacheType | SMBIOS_CACHE_INFO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMBIOS_PROCESSOR_INFO Struct Reference

Public Attributes | List of all members
SMBIOS_PROCESSOR_INFO Struct Reference

SMBIOS Processor Info HOB Structure. More...

#include <SmbiosProcessorInfoHob.h>

Public Attributes

UINT8 | ProcessorType
ENUM defined in SMBIOS Spec v3.1 Section 7.5.1.
UINT16 | ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2.
UINT8 | ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
UINT64 | ProcessorId
ENUM defined in SMBIOS Spec v3.1 Section 7.5.3.
UINT8 | ProcessorVersionStrIndex
Index of the String in the String Buffer.
UINT8 | Voltage
Format defined in SMBIOS Spec v3.1 Section 7.5.4.
UINT16 | ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
UINT16 | MaxSpeedInMHz
Snapshot of Max processor speed during boot.
UINT16 | CurrentSpeedInMHz
Snapshot of current processor speed during boot.
UINT8 | Status
Format defined in the SMBIOS Spec v3.1 Table 21.
UINT8 | ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.1 Section 7.5.5.
UINT16 | CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.6.
UINT16 | EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.7.
UINT16 | ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec v3.1 Section 7.5.8.
UINT16 | ProcessorCharacteristics
Format defined in SMBIOS Spec v3.1 Section 7.5.9.

Detailed Description

SMBIOS Processor Info HOB Structure.

Definition at line 30 of file SmbiosProcessorInfoHob.h.

The documentation for this struct was generated from the following file:
  • SmbiosProcessorInfoHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMBIOS_PROCESSOR_INFO Member List

This is the complete list of members for SMBIOS_PROCESSOR_INFO, including all inherited members.

CoreCount | SMBIOS_PROCESSOR_INFO
CurrentSpeedInMHz | SMBIOS_PROCESSOR_INFO
EnabledCoreCount | SMBIOS_PROCESSOR_INFO
ExternalClockInMHz | SMBIOS_PROCESSOR_INFO
MaxSpeedInMHz | SMBIOS_PROCESSOR_INFO
ProcessorCharacteristics | SMBIOS_PROCESSOR_INFO
ProcessorFamily | SMBIOS_PROCESSOR_INFO
ProcessorId | SMBIOS_PROCESSOR_INFO
ProcessorManufacturerStrIndex | SMBIOS_PROCESSOR_INFO
ProcessorType | SMBIOS_PROCESSOR_INFO
ProcessorUpgrade | SMBIOS_PROCESSOR_INFO
ProcessorVersionStrIndex | SMBIOS_PROCESSOR_INFO
Status | SMBIOS_PROCESSOR_INFO
ThreadCount | SMBIOS_PROCESSOR_INFO
Voltage | SMBIOS_PROCESSOR_INFO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMBIOS_TABLE_TYPE130 Struct Reference

Public Attributes | List of all members
SMBIOS_TABLE_TYPE130 Struct Reference

This is definition for SMBIOS Oem data type 130. More...

#include <MeSmbios.h>

Public Attributes

UINT8 | AmtSignature [4]
Table signature.
UINT8 | AmtSupported
Any manageability supported, includes full or standard manageability.
UINT8 | AmtEnabled
Any manageability enabled, includes full or standard manageability.
UINT8 | SrouEnabled
Storage Redirection Over USB-R feature enablement.
UINT8 | SolEnabled
Serial Over Lan feature enablement.
UINT8 | NetworkEnabled
Network interface enablement.
UINT8 | ExtendedData
Kept for backward compatibility.
UINT8 | OemCapabilities1
1st Byte of OEM Capabilities
UINT8 | OemCapabilities2
2nd Byte of OEM Capabilities
UINT8 | OemCapabilities3
3rd Byte of OEM Capabilities
UINT8 | OemCapabilities4
4th Byte of OEM Capabilities
UINT8 | KvmEnabled
Kvm redirection enablement.
UINT8 | Reserved
Reserved.
UINT32 | RpeCapabilities
Remote Platform Erase Capbilities, keeps it at the end and 4 byte alignment.

Detailed Description

This is definition for SMBIOS Oem data type 130.

Definition at line 86 of file MeSmbios.h.

The documentation for this struct was generated from the following file:
  • MeSmbios.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMBIOS_TABLE_TYPE130 Member List

This is the complete list of members for SMBIOS_TABLE_TYPE130, including all inherited members.

AmtEnabled | SMBIOS_TABLE_TYPE130
AmtSignature | SMBIOS_TABLE_TYPE130
AmtSupported | SMBIOS_TABLE_TYPE130
ExtendedData | SMBIOS_TABLE_TYPE130
KvmEnabled | SMBIOS_TABLE_TYPE130
NetworkEnabled | SMBIOS_TABLE_TYPE130
OemCapabilities1 | SMBIOS_TABLE_TYPE130
OemCapabilities2 | SMBIOS_TABLE_TYPE130
OemCapabilities3 | SMBIOS_TABLE_TYPE130
OemCapabilities4 | SMBIOS_TABLE_TYPE130
Reserved | SMBIOS_TABLE_TYPE130
RpeCapabilities | SMBIOS_TABLE_TYPE130
SolEnabled | SMBIOS_TABLE_TYPE130
SrouEnabled | SMBIOS_TABLE_TYPE130
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMBIOS_TABLE_TYPE131 Struct Reference

Public Attributes | List of all members
SMBIOS_TABLE_TYPE131 Struct Reference

This is definition for SMBIOS Oem data type 131. More...

#include <MeSmbios.h>

Collaboration diagram for SMBIOS_TABLE_TYPE131:
[legend]

Public Attributes

MEBX_VER MebxVersion

Detailed Description

This is definition for SMBIOS Oem data type 131.

Definition at line 168 of file MeSmbios.h.

Member Data Documentation

◆ MebxVersion

MEBX_VER SMBIOS_TABLE_TYPE131::MebxVersion
Deprecated:

Definition at line 171 of file MeSmbios.h.

The documentation for this struct was generated from the following file:
  • MeSmbios.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMBIOS_TABLE_TYPE131 Member List

This is the complete list of members for SMBIOS_TABLE_TYPE131, including all inherited members.

MebxVersion SMBIOS_TABLE_TYPE131
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMM_RESOURCE_CONFIG_PROTOCOL Struct Reference

List of all members
SMM_RESOURCE_CONFIG_PROTOCOL Struct Reference

The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure IO ports & MSR registers access with in SMM. More...

#include <SmmResourceConfigProtocol.h>

Detailed Description

The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure IO ports & MSR registers access with in SMM.

Definition at line 146 of file SmmResourceConfigProtocol.h.

The documentation for this struct was generated from the following file:
  • SmmResourceConfigProtocol.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMM_RESOURCE_CONFIG_PROTOCOL Member List

This is the complete list of members for SMM_RESOURCE_CONFIG_PROTOCOL, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SMRAM_CPU_INFO Struct Reference

Public Attributes | List of all members
SMRAM_CPU_INFO Struct Reference

This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA. More...

#include <CpuInfo.h>

Public Attributes

EFI_PHYSICAL_ADDRESS | LockBoxData
First location (address) of SMRAM CPU DATA.
EFI_PHYSICAL_ADDRESS | SmramCpuData
Second location (Address) of SMRAM CPU DATA.
UINT64 | LockBoxSize
Size of SMRAM CPU DATA.

Detailed Description

This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA.

Definition at line 121 of file CpuInfo.h.

The documentation for this struct was generated from the following file:
  • CpuInfo.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SMRAM_CPU_INFO Member List

This is the complete list of members for SMRAM_CPU_INFO, including all inherited members.

LockBoxData | SMRAM_CPU_INFO
LockBoxSize | SMRAM_CPU_INFO
SmramCpuData | SMRAM_CPU_INFO
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPD_DATA_BUFFER Struct Reference

Public Attributes | List of all members
SPD_DATA_BUFFER Struct Reference

SPD Data Buffer. More...

#include <MemoryConfig.h>

Public Attributes

UINT8 SpdData [MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]
SpdData.

Detailed Description

SPD Data Buffer.

Definition at line 132 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPD_DATA_BUFFER Member List

This is the complete list of members for SPD_DATA_BUFFER, including all inherited members.

SpdData SPD_DATA_BUFFER
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPD_OFFSET_TABLE Struct Reference

Public Attributes | List of all members
SPD_OFFSET_TABLE Struct Reference

SPD Offset Table. More...

#include <MemoryConfig.h>

Public Attributes

UINT16 | Start
Offset 0.
UINT16 | End
Offset 2.
UINT8 | BootMode
Offset 4.
UINT8 | Reserved3 [3]
Offset 5 Reserved for future use.

Detailed Description

SPD Offset Table.

Definition at line 158 of file MemoryConfig.h.

The documentation for this struct was generated from the following file:
  • MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPD_OFFSET_TABLE Member List

This is the complete list of members for SPD_OFFSET_TABLE, including all inherited members.

BootMode | SPD_OFFSET_TABLE
End | SPD_OFFSET_TABLE
Reserved3 | SPD_OFFSET_TABLE
Start | SPD_OFFSET_TABLE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPECIAL_COMMAND_CAPS_STRUC Struct Reference

List of all members
SPECIAL_COMMAND_CAPS_STRUC Struct Reference

Special Commands Bit Mask. More...

#include <IndustryStandardAsf.h>

Detailed Description

Special Commands Bit Mask.

Byte1: 7:0: Reserved to identify support for ASF-RMCP Special Commands defined by a future version of this specification Byte2: 7:5: Reserved to identify support for ASF-RMCP Special Commands defined by a future version of this specification 4: Supports Force CD/DVD Boot command 3: Supports Force Diagnostic Boot command 2: Supports Force Hard-drive Safe-mode Boot command 1: Supports Force Hard-drive Boot command 0: Supports Force PXE Boot command

Definition at line 418 of file IndustryStandardAsf.h.

The documentation for this struct was generated from the following file:
  • IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPECIAL_COMMAND_CAPS_STRUC Member List

This is the complete list of members for SPECIAL_COMMAND_CAPS_STRUC, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPI_CONFIG Struct Reference

Public Attributes | List of all members
SPI_CONFIG Struct Reference

Basic configuration for option features of PCH SPI Flash controller. More...

#include <SpiConfig.h>

Collaboration diagram for SPI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | ExtendedBiosDecodeRangeEnable: 1
Enable extended BIOS Direct Read Region feature Enabling this will make all memory accesses in a decode range to be translated to BIOS region reads from SPI flash 0: Disabled, 1: Enabled.
UINT32 | RsvdBits0: 31
Reserved bits.
UINT32 | ExtendedBiosDecodeRangeBase
Base address that will be used for Extended Decode Range. More...
UINT32 | ExtendedBiosDecodeRangeLimit
Limit address that will be used for Extended Decode Range. More...

Detailed Description

Basic configuration for option features of PCH SPI Flash controller.

Definition at line 47 of file SpiConfig.h.

Member Data Documentation

◆ ExtendedBiosDecodeRangeBase

UINT32 SPI_CONFIG::ExtendedBiosDecodeRangeBase

Base address that will be used for Extended Decode Range.

This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.

Definition at line 61 of file SpiConfig.h.

◆ ExtendedBiosDecodeRangeLimit

UINT32 SPI_CONFIG::ExtendedBiosDecodeRangeLimit

Limit address that will be used for Extended Decode Range.

This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.

Definition at line 66 of file SpiConfig.h.

The documentation for this struct was generated from the following file:
  • SpiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPI_CONFIG Member List

This is the complete list of members for SPI_CONFIG, including all inherited members.

ExtendedBiosDecodeRangeBase | SPI_CONFIG
ExtendedBiosDecodeRangeEnable | SPI_CONFIG
ExtendedBiosDecodeRangeLimit | SPI_CONFIG
Header | SPI_CONFIG
RsvdBits0 | SPI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPI_PIN_MUX Struct Reference

Public Attributes | List of all members
SPI_PIN_MUX Struct Reference

SPI signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Cs [PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]
CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*.
UINT32 | Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
UINT32 | Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
UINT32 | Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.

Detailed Description

SPI signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h for supported settings on a given platform

Definition at line 84 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPI_PIN_MUX Member List

This is the complete list of members for SPI_PIN_MUX, including all inherited members.

Clk | SPI_PIN_MUX
Cs | SPI_PIN_MUX
Miso | SPI_PIN_MUX
Mosi | SPI_PIN_MUX
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SPS_RING3_EXCEPTION_HANDLER Struct Reference

List of all members
SPS_RING3_EXCEPTION_HANDLER Struct Reference

The protocol allows to handle OEM Ring-3 Exceptions. More...

#include <SmmResourceConfigProtocol.h>

Detailed Description

The protocol allows to handle OEM Ring-3 Exceptions.

Definition at line 172 of file SmmResourceConfigProtocol.h.

The documentation for this struct was generated from the following file:
  • SmmResourceConfigProtocol.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SPS_RING3_EXCEPTION_HANDLER Member List

This is the complete list of members for SPS_RING3_EXCEPTION_HANDLER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SVID_SID_VALUE Struct Reference

List of all members
SVID_SID_VALUE Struct Reference

Subsystem Vendor ID / Subsystem ID. More...

#include <SiConfig.h>

Detailed Description

Subsystem Vendor ID / Subsystem ID.

Definition at line 137 of file SiConfig.h.

The documentation for this struct was generated from the following file:
  • SiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SVID_SID_VALUE Member List

This is the complete list of members for SVID_SID_VALUE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SYSTEM_CAPS_STRUC Struct Reference

List of all members
SYSTEM_CAPS_STRUC Struct Reference

System Capabilities Bit Mask. More...

#include <IndustryStandardAsf.h>

Detailed Description

System Capabilities Bit Mask.

Byte1: 7: Supports Reset on either the compatibility or secure port 6: Supports Power-Up on either the compatibility or secure port 5: Supports Power-Down on either the compatibility or secure port 4: Supports Power Cycle Reset on either the compatibility or secure port 3: Supports Reset only on the secure port 2: Supports Power-Up only on the secure port 1: Supports Power-Down only on the secure port 0: Supports Power Cycle Reset only on the secure port

Definition at line 447 of file IndustryStandardAsf.h.

The documentation for this struct was generated from the following file:
  • IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

SYSTEM_CAPS_STRUC Member List

This is the complete list of members for SYSTEM_CAPS_STRUC, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TBT_IMR_STATUS Union Reference

List of all members
TBT_IMR_STATUS Union Reference

Structure for Tbt firmware status from IMR. More...

#include <TcssDataHob.h>

Detailed Description

Structure for Tbt firmware status from IMR.

Definition at line 70 of file TcssDataHob.h.

The documentation for this union was generated from the following file:
  • TcssDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TBT_IMR_STATUS Member List

This is the complete list of members for TBT_IMR_STATUS, including all inherited members.

Done | TBT_IMR_STATUS
ErrorCode | TBT_IMR_STATUS
Reserved | TBT_IMR_STATUS
TbtFwVersion | TBT_IMR_STATUS
Valid | TBT_IMR_STATUS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_DATA Struct Reference

Public Attributes | List of all members
TCSS_DATA Struct Reference

TCSS data definition. More...

#include <TcssDataHob.h>

Collaboration diagram for TCSS_DATA:
[legend]

Public Attributes

UINT32 | IOMReady:1
Indicate the IOM ready.
UINT32 | Rsvd:30
Deprecate < Indicate the extra segment of iTBT PCIe is enabled or not. More...
UINT32 | IomFwVersion
IOM FW version.
UINT32 | IomFwEngrVersion
IOM FW Engineer version. Non-zero value used to identify engineering versions / hotfixes. Shall be zero for official releases.
TBT_IMR_STATUS TbtImrStatus
Tbt FW IMR Status.
UINT32 | ItbtPcieSegMap
iTBT PCIE RP 0-3 Segment Map
UINT32 | ItbtPcieFuncMap
iTBT PCIE RP 0-3 Function Map
UINT8 | ItbtPcieRpEn [MAX_ITBT_PCIE_PORT]
ItbtPcieRpEn PCIE RP Device Enable.
UINT8 | ItbtXhciEn
ItbtPcieRpEn XHCI Device Enable.
UINT8 | ItbtXdciEn
ItbtPcieRpEn XDCI Device Enable.
UINT8 | ItbtDmaEn [MAX_HOST_ITBT_DMA_NUMBER]
ItbtPcieRpEn DMA Device Enable.
UINT8 | TcssxDCIInt
iTBT xDCI Int Pin number
UINT8 | TcssxDCIIrq
iTBT xDCI APIC IRQ number
UINT8 | TcssRtd3
TCSS RTD3.
UINT8 | ItbtForcePower
iTBT Force Power status
MG_IMR_STATUS MgImrStatus
MG IMR Status.
UINT8 | TcssIomVccSt
IOM VCCST request.
UINT8 | DeepstTcState
Maximum TC C State limit.

Detailed Description

TCSS data definition.

Definition at line 98 of file TcssDataHob.h.

Member Data Documentation

◆ Rsvd

UINT32 TCSS_DATA::Rsvd

Deprecate < Indicate the extra segment of iTBT PCIe is enabled or not.

Reserved for future use.

Definition at line 101 of file TcssDataHob.h.

The documentation for this struct was generated from the following file:
  • TcssDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_DATA Member List

This is the complete list of members for TCSS_DATA, including all inherited members.

DeepstTcState | TCSS_DATA
IomFwEngrVersion | TCSS_DATA
IomFwVersion | TCSS_DATA
IOMReady | TCSS_DATA
ItbtDmaEn | TCSS_DATA
ItbtForcePower | TCSS_DATA
ItbtPcieFuncMap | TCSS_DATA
ItbtPcieRpEn | TCSS_DATA
ItbtPcieSegMap | TCSS_DATA
ItbtXdciEn | TCSS_DATA
ItbtXhciEn | TCSS_DATA
MgImrStatus | TCSS_DATA
Rsvd | TCSS_DATA
TbtImrStatus | TCSS_DATA
TcssIomVccSt | TCSS_DATA
TcssRtd3 | TCSS_DATA
TcssxDCIInt | TCSS_DATA
TcssxDCIIrq | TCSS_DATA
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_DATA_HOB Struct Reference

Public Attributes | List of all members
TCSS_DATA_HOB Struct Reference

TCSS Data Hob. More...

#include <TcssDataHob.h>

Collaboration diagram for TCSS_DATA_HOB:
[legend]

Public Attributes

EFI_HOB_GUID_TYPE EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gTcssHobGuid.
TCSS_DATA TcssData
Offset 24 TCSS data definition.

Detailed Description

TCSS Data Hob.

Definition at line 137 of file TcssDataHob.h.

The documentation for this struct was generated from the following file:
  • TcssDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_DATA_HOB Member List

This is the complete list of members for TCSS_DATA_HOB, including all inherited members.

EfiHobGuidType | TCSS_DATA_HOB
TcssData | TCSS_DATA_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_DATA_SSID_HOB Struct Reference

Public Attributes | List of all members
TCSS_DATA_SSID_HOB Struct Reference

TCSS SSID Data Hob. More...

#include <TcssDataHob.h>

Public Attributes

EFI_HOB_GUID_TYPE | EfiHobGuidType
GUID.
SVID_SID_SKIP_TABLE * | TcssSsidTable
TCSS SSID table.
UINT16 | NumberOfTcssSsidTable
number of TCSS SSID table
UINT8 | Reserved [2]
Reserved for Hob size allignment.

Detailed Description

TCSS SSID Data Hob.

Definition at line 146 of file TcssDataHob.h.

The documentation for this struct was generated from the following file:
  • TcssDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_DATA_SSID_HOB Member List

This is the complete list of members for TCSS_DATA_SSID_HOB, including all inherited members.

EfiHobGuidType | TCSS_DATA_SSID_HOB
NumberOfTcssSsidTable | TCSS_DATA_SSID_HOB
Reserved | TCSS_DATA_SSID_HOB
TcssSsidTable | TCSS_DATA_SSID_HOB
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

Public Attributes | List of all members
TCSS_DEVEN_PEI_PREMEM_CONFIG Union Reference

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.

Detailed Description

The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.

Definition at line 48 of file TcssPeiPreMemConfig.h.

The documentation for this union was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_DEVEN_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_DEVEN_PEI_PREMEM_CONFIG, including all inherited members.

TcssDevEn TCSS_DEVEN_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_IOM_ORI_OVERRIDE Struct Reference

Public Attributes | List of all members
TCSS_IOM_ORI_OVERRIDE Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT16 | AuxOri
Bits defining value for IOM Aux Orientation Register.
UINT16 | HslOri
Bits defining value for IOM HSL Orientation Register.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.

Definition at line 134 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_IOM_ORI_OVERRIDE Member List

This is the complete list of members for TCSS_IOM_ORI_OVERRIDE, including all inherited members.

AuxOri | TCSS_IOM_ORI_OVERRIDE
HslOri | TCSS_IOM_ORI_OVERRIDE
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_IOM_PEI_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_IOM_PEI_CONFIG Struct Reference

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_IOM_PEI_CONFIG:
[legend]

Public Attributes

IOM_AUX_ORI_PAD_CONFIG | IomAuxPortPad [MAX_IOM_AUX_BIAS_COUNT]
The IOM_AUX_ORI_BIAS_CTRL port config setting.
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
UINT8 | TcStateLimit
Tcss C-State deep stage.
UINT8 | Reserved [3]
Reserved bytes for future use.

Detailed Description

The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.

Definition at line 142 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_IOM_PEI_CONFIG Member List

This is the complete list of members for TCSS_IOM_PEI_CONFIG, including all inherited members.

IomAuxPortPad | TCSS_IOM_PEI_CONFIG
IomInterface | TCSS_IOM_PEI_CONFIG
PmcInterface | TCSS_IOM_PEI_CONFIG
Reserved | TCSS_IOM_PEI_CONFIG
TcStateLimit | TCSS_IOM_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_MISC_PEI_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_MISC_PEI_CONFIG Struct Reference

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_MISC_PEI_CONFIG:
[legend]

Public Attributes

SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
UINT8 | EnableTcssCovTypeA [MAX_TCSS_USB3_PORTS]
Enable / Disable Type C Port X Convert to TypeA.
UINT8 | MappingPchXhciUsbA [MAX_TCSS_USB3_PORTS]
PCH xhci port number for Type C Port x mapping.
UINT8 | IomStayInTCColdSeconds
Set IOM stay in TC cold seconds.
UINT8 | IomBeforeEnteringTCColdSeconds
Set IOM before entering TC cold seconds.
UINT8 | Rsvd [2]
Reserved bytes for future use.

Detailed Description

The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.

Definition at line 154 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_MISC_PEI_CONFIG Member List

This is the complete list of members for TCSS_MISC_PEI_CONFIG, including all inherited members.

EnableTcssCovTypeA | TCSS_MISC_PEI_CONFIG
IomBeforeEnteringTCColdSeconds | TCSS_MISC_PEI_CONFIG
IomStayInTCColdSeconds | TCSS_MISC_PEI_CONFIG
MappingPchXhciUsbA | TCSS_MISC_PEI_CONFIG
Rsvd | TCSS_MISC_PEI_CONFIG
SaXdci | TCSS_MISC_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_MISC_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_MISC_PEI_PREMEM_CONFIG Struct Reference

The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT8 | PcieMultipleSegmentEnabled
This is policy to control Multiple Segment setting. More...
UINT8 | Rsvd [3]
Deprecate. More...

Detailed Description

The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.

Revision 1: - Initial version.

Definition at line 76 of file TcssPeiPreMemConfig.h.

Member Data Documentation

◆ PcieMultipleSegmentEnabled

UINT8 TCSS_MISC_PEI_PREMEM_CONFIG::PcieMultipleSegmentEnabled

This is policy to control Multiple Segment setting.

When Disabled all the iTBT PCIe RP are located at Segment0 When Enabled all the iTBT PCIe RP are located at Segment1, FSP Wrapper need to update PCIEXBAR and PcdPciExpressRegionLength to 512MB prior to FspmWrapperPeim. 0: Disable, 1: Enable

Definition at line 85 of file TcssPeiPreMemConfig.h.

◆ Rsvd

UINT8 TCSS_MISC_PEI_PREMEM_CONFIG::Rsvd[3]

Deprecate.

Reserved bytes for future use, align to multiple 4

Definition at line 86 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_MISC_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_MISC_PEI_PREMEM_CONFIG, including all inherited members.

PcieMultipleSegmentEnabled | TCSS_MISC_PEI_PREMEM_CONFIG
Rsvd | TCSS_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_PCIE_PEI_POLICY Struct Reference

List of all members
TCSS_PCIE_PEI_POLICY Struct Reference

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PCIE_PEI_POLICY:
[legend]

Detailed Description

TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.

Definition at line 127 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_PCIE_PEI_POLICY Member List

This is the complete list of members for TCSS_PCIE_PEI_POLICY, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_PCIE_PORT_POLICY Struct Reference

Public Attributes | List of all members
TCSS_PCIE_PORT_POLICY Struct Reference

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...

#include <TcssPeiConfig.h>

Public Attributes

UINT8 | AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
UINT8 | DpcEnabled
Downstream Port Containment. 0: Disable; 1: Enable
UINT8 | RpDpcExtensionsEnabled
RP Extensions for Downstream Port Containment. 0: Disable; 1: Enable
UINT8 | LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
UINT8 | PtmEnabled
Enables PTM capability.
UINT8 | Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
UINT8 | SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
UINT8 | SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is zero.
UINT16 | SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is zero.
UINT8 | AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
UINT8 | UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
UINT8 | FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
UINT8 | SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
UINT16 | LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
UINT16 | LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
UINT8 | SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
UINT8 | SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
UINT16 | SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
UINT8 | NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
UINT8 | NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
UINT16 | NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
UINT8 | ForceLtrOverride
0: Disable; 1: Enable.
UINT8 | LtrConfigLock
0: Disable; 1: Enable.

Detailed Description

The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.

Definition at line 91 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_PCIE_PORT_POLICY Member List

This is the complete list of members for TCSS_PCIE_PORT_POLICY, including all inherited members.

AcsEnabled | TCSS_PCIE_PORT_POLICY
AdvancedErrorReporting | TCSS_PCIE_PORT_POLICY
Aspm | TCSS_PCIE_PORT_POLICY
CorrectableErrorReport | TCSS_PCIE_PORT_POLICY
DpcEnabled | TCSS_PCIE_PORT_POLICY
FatalErrorReport | TCSS_PCIE_PORT_POLICY
ForceLtrOverride | TCSS_PCIE_PORT_POLICY
LtrConfigLock | TCSS_PCIE_PORT_POLICY
LtrEnable | TCSS_PCIE_PORT_POLICY
LtrMaxNoSnoopLatency | TCSS_PCIE_PORT_POLICY
LtrMaxSnoopLatency | TCSS_PCIE_PORT_POLICY
NoFatalErrorReport | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
NonSnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
PtmEnabled | TCSS_PCIE_PORT_POLICY
RpDpcExtensionsEnabled | TCSS_PCIE_PORT_POLICY
SlotNumber | TCSS_PCIE_PORT_POLICY
SlotPowerLimitScale | TCSS_PCIE_PORT_POLICY
SlotPowerLimitValue | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMode | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideMultiplier | TCSS_PCIE_PORT_POLICY
SnoopLatencyOverrideValue | TCSS_PCIE_PORT_POLICY
SystemErrorOnCorrectableError | TCSS_PCIE_PORT_POLICY
SystemErrorOnFatalError | TCSS_PCIE_PORT_POLICY
SystemErrorOnNonFatalError | TCSS_PCIE_PORT_POLICY
UnsupportedRequestReport | TCSS_PCIE_PORT_POLICY
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_PEI_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_PEI_CONFIG Struct Reference

The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

#include <TcssPeiConfig.h>

Collaboration diagram for TCSS_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.

Detailed Description

The TCSS_PEI_CONFIG block describes TCSS settings for SA.

Definition at line 166 of file TcssPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_PEI_CONFIG Member List

This is the complete list of members for TCSS_PEI_CONFIG, including all inherited members.

Header | TCSS_PEI_CONFIG
IomConfig | TCSS_PEI_CONFIG
MiscConfig | TCSS_PEI_CONFIG
PciePolicy | TCSS_PEI_CONFIG
UsbConfig | TCSS_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_PEI_PREMEM_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes TCSS settings. More...

#include <TcssPeiPreMemConfig.h>

Collaboration diagram for TCSS_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.
TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig
The MISC PreMem Config.

Detailed Description

This configuration block describes TCSS settings.

Revision 1:

  • Initial version. Revision 2:
  • Deprecate PcieMultipleSegmentEnabled

Definition at line 96 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TCSS_PEI_PREMEM_CONFIG, including all inherited members.

DevEnConfig | TCSS_PEI_PREMEM_CONFIG
Header | TCSS_PEI_PREMEM_CONFIG
MiscConfig | TCSS_PEI_PREMEM_CONFIG
UsbTcConfig | TCSS_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

Public Attributes | List of all members
TCSS_USBTC_PEI_PERMEM_CONFIG Struct Reference

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...

#include <TcssPeiPreMemConfig.h>

Public Attributes

UINT32 | UsbTcPortEn: 4
bitmap for USB Type C enabled ports
UINT32 | Rsvd: 28
Reserved bytes for future use.

Detailed Description

The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.

Definition at line 67 of file TcssPeiPreMemConfig.h.

The documentation for this struct was generated from the following file:
  • TcssPeiPreMemConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TCSS_USBTC_PEI_PERMEM_CONFIG Member List

This is the complete list of members for TCSS_USBTC_PEI_PERMEM_CONFIG, including all inherited members.

Rsvd | TCSS_USBTC_PEI_PERMEM_CONFIG
UsbTcPortEn | TCSS_USBTC_PEI_PERMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TELEMETRY_PEI_CONFIG Struct Reference

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TELEMETRY_PEI_CONFIG Struct Reference

This configuration block describes Telemetry settings in PostMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogEnable
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PostMem.

Revision 1:

  • Initial version.

Definition at line 63 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TELEMETRY_PEI_CONFIG Member List

This is the complete list of members for TELEMETRY_PEI_CONFIG, including all inherited members.

CpuCrashLogEnable TELEMETRY_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

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TELEMETRY_PEI_PREMEM_CONFIG Struct Reference

This configuration block describes Telemetry settings in PreMem. More...

#include <TelemetryPeiConfig.h>

Collaboration diagram for TELEMETRY_PEI_PREMEM_CONFIG:
[legend]

Public Attributes

UINT32 CpuCrashLogDevice
Config Block Header.

Detailed Description

This configuration block describes Telemetry settings in PreMem.

Revision 1:

  • Initial version.

Definition at line 53 of file TelemetryPeiConfig.h.

The documentation for this struct was generated from the following file:
  • TelemetryPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TELEMETRY_PEI_PREMEM_CONFIG Member List

This is the complete list of members for TELEMETRY_PEI_PREMEM_CONFIG, including all inherited members.

CpuCrashLogDevice TELEMETRY_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): THC_CONFIG Struct Reference

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THC_CONFIG Struct Reference

THC_CONFIG block provides the configurations forTouch Host Controllers. More...

#include <ThcConfig.h>

Collaboration diagram for THC_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
THC_PORT ThcPort [2]
Port Configuration.

Detailed Description

THC_CONFIG block provides the configurations forTouch Host Controllers.

Assignment field in each THC port controlls the THC behavior.

Available scenarios: 1: Single Port 0 used by THC0

  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 unassigned
  • THC1 will be automatically Disabled. 2: Both ports used by THC0
  • THC0 Enabled
  • Port0 assigned to THC0
  • Port1 assigned to THC0
  • THC1 will be automatically Disabled. 3: Port 0 used by THC0 and Port 1 used by THC1
  • THC0 Enabled
  • Port0 assigned to THC0
  • THC1 Enabled
  • Port1 assigned to THC1. 4: Both Ports unassigned. Both THC Controllers will be disabled in that case.
Note
Invalid scenario that will cause ASSERT.
  1. Same port Number assigned to THC0 or THC1.
  2. Two Ports assigned to THC1.

Definition at line 125 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

THC_CONFIG Member List

This is the complete list of members for THC_CONFIG, including all inherited members.

Header | THC_CONFIG
ThcPort | THC_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): THC_HID_OVER_SPI Struct Reference

Public Attributes | List of all members
THC_HID_OVER_SPI Struct Reference

THC Hid Over SPI mode related settings. More...

#include <ThcConfig.h>

Public Attributes

UINT32 | ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function or by the BIOS Quick SPI driver.
UINT32 | ResetPadTrigger
Reset Pad Trigger.
UINT32 | Frequency
Connection Speed - SPI Frequency in Hz.
UINT32 | InputReportHeaderAddress
Input Report Header Address.
UINT32 | InputReportBodyAddress
Input Report Body Address.
UINT32 | OutputReportAddress
Output Report Address.
UINT32 | ReadOpcode
Read Opcode.
UINT32 | WriteOpcode
Write Opcode.
UINT32 | Flags
Flags.

Detailed Description

THC Hid Over SPI mode related settings.

Only applicable when HidOverSpi is enbled.

Definition at line 66 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

THC_HID_OVER_SPI Member List

This is the complete list of members for THC_HID_OVER_SPI, including all inherited members.

Flags | THC_HID_OVER_SPI
Frequency | THC_HID_OVER_SPI
InputReportBodyAddress | THC_HID_OVER_SPI
InputReportHeaderAddress | THC_HID_OVER_SPI
OutputReportAddress | THC_HID_OVER_SPI
ReadOpcode | THC_HID_OVER_SPI
ResetPad | THC_HID_OVER_SPI
ResetPadTrigger | THC_HID_OVER_SPI
WriteOpcode | THC_HID_OVER_SPI
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): THC_PORT Struct Reference

Public Attributes | List of all members
THC_PORT Struct Reference

Port Configuration structure required for each Port that THC might use. More...

#include <ThcConfig.h>

Collaboration diagram for THC_PORT:
[legend]

Public Attributes

UINT32 | Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
UINT32 | InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
UINT8 | WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
UINT8 | Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
UINT8 | Reserved [2]
Reserved.
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
UINT32 | ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
UINT32 | IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
UINT32 | LimitPacketSize
Limit Packet Size.
UINT32 | PerformanceLimitation
Performance Limitation.

Detailed Description

Port Configuration structure required for each Port that THC might use.

Definition at line 82 of file ThcConfig.h.

The documentation for this struct was generated from the following file:
  • ThcConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

THC_PORT Member List

This is the complete list of members for THC_PORT, including all inherited members.

ActiveLtr | THC_PORT
Assignment | THC_PORT
HidOverSpi | THC_PORT
IdleLtr | THC_PORT
InterruptPinMuxing | THC_PORT
LimitPacketSize | THC_PORT
Mode | THC_PORT
PerformanceLimitation | THC_PORT
Reserved | THC_PORT
WakeOnTouch | THC_PORT
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): THERMAL_CONFIG Struct Reference

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THERMAL_CONFIG Struct Reference

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

#include <ThermalConfig.h>

Collaboration diagram for THERMAL_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PchHotEnable: 1
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled.
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling. More...
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling. More...
PCH_MEMORY_THROTTLING MemoryThrottling
Memory Thermal Management settings.
UINT16 | PchHotLevel
The recommendation is the same as Cat Trip point. More...

Detailed Description

The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.

Definition at line 145 of file ThermalConfig.h.

Member Data Documentation

◆ DmiHaAWC

DMI_HW_WIDTH_CONTROL THERMAL_CONFIG::DmiHaAWC

This field decides the settings of DMI throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 158 of file ThermalConfig.h.

◆ PchHotLevel

UINT16 THERMAL_CONFIG::PchHotLevel

The recommendation is the same as Cat Trip point.

This field decides the temperature, default is 120. Temperature value used for PCHHOT# pin assertion based on 2s complement format

  • 0x001 positive 1'C
  • 0x000 0'C
  • 0x1FF negative 1'C
  • 0x1D8 negative 40'C
  • and so on

Definition at line 173 of file ThermalConfig.h.

◆ TTLevels

THERMAL_THROTTLE_LEVELS THERMAL_CONFIG::TTLevels

This field decides the settings of Thermal throttling.

When the Suggested Setting is enabled, PCH RC will use the suggested representative values.

Definition at line 153 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

THERMAL_CONFIG Member List

This is the complete list of members for THERMAL_CONFIG, including all inherited members.

DmiHaAWC | THERMAL_CONFIG
Header | THERMAL_CONFIG
MemoryThrottling | THERMAL_CONFIG
PchHotEnable | THERMAL_CONFIG
PchHotLevel | THERMAL_CONFIG
TTLevels | THERMAL_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): THERMAL_THROTTLE_LEVELS Struct Reference

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THERMAL_THROTTLE_LEVELS Struct Reference

This structure lists PCH supported throttling register setting for custimization. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | T0Level: 9
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T1Level: 9
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | T2Level: 9
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
UINT32 | TTEnable: 1
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
UINT32 | TTState13Enable: 1
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
UINT32 | TTLock: 1
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset. More...
UINT32 | SuggestedSetting: 1
0: Disable; 1: Enable suggested representative values.
UINT32 | PchCrossThrottling: 1
ULT processors support thermal management and cross thermal throttling between the processor package and LP PCH. More...
UINT32 | Rsvd0
Reserved bytes.

Detailed Description

This structure lists PCH supported throttling register setting for custimization.

When the SuggestedSetting is enabled, the customized values are ignored.

Definition at line 47 of file ThermalConfig.h.

Member Data Documentation

◆ PchCrossThrottling

UINT32 THERMAL_THROTTLE_LEVELS::PchCrossThrottling

ULT processors support thermal management and cross thermal throttling between the processor package and LP PCH.

The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH thermal status to the processor which is factored into the processor throttling. Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled.

Definition at line 69 of file ThermalConfig.h.

◆ TTLock

UINT32 THERMAL_THROTTLE_LEVELS::TTLock

When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.

If SuggestedSetting is used, this setting is ignored.

Definition at line 61 of file ThermalConfig.h.

◆ TTState13Enable

UINT32 THERMAL_THROTTLE_LEVELS::TTState13Enable

When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.

If SuggestedSetting is used, this setting is ignored.

Definition at line 56 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

THERMAL_THROTTLE_LEVELS Member List

This is the complete list of members for THERMAL_THROTTLE_LEVELS, including all inherited members.

PchCrossThrottling | THERMAL_THROTTLE_LEVELS
Rsvd0 | THERMAL_THROTTLE_LEVELS
SuggestedSetting | THERMAL_THROTTLE_LEVELS
T0Level | THERMAL_THROTTLE_LEVELS
T1Level | THERMAL_THROTTLE_LEVELS
T2Level | THERMAL_THROTTLE_LEVELS
TTEnable | THERMAL_THROTTLE_LEVELS
TTLock | THERMAL_THROTTLE_LEVELS
TTState13Enable | THERMAL_THROTTLE_LEVELS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TPM_STATE Union Reference

List of all members
TPM_STATE Union Reference

Set ACM TPM. More...

#include <MkhiMsgs.h>

Detailed Description

Set ACM TPM.

Definition at line 500 of file MkhiMsgs.h.

The documentation for this union was generated from the following file:
  • MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TPM_STATE Member List

This is the complete list of members for TPM_STATE, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TRACE_HUB_CONFIG Struct Reference

Public Attributes | List of all members
TRACE_HUB_CONFIG Struct Reference

TRACE_HUB_CONFIG block describes TraceHub settings. More...

#include <TraceHubConfig.h>

Public Attributes

UINT8 | EnableMode
Trace hub mode. More...
UINT8 | MemReg0Size
Trace hub memory buffer region size policy. More...
UINT8 | AetEnabled
AET Trace. More...

Detailed Description

TRACE_HUB_CONFIG block describes TraceHub settings.

Definition at line 78 of file TraceHubConfig.h.

Member Data Documentation

◆ AetEnabled

UINT8 TRACE_HUB_CONFIG::AetEnabled

AET Trace.

AET base address can be set to FW Base either from CPU trace hub or PCH one. AetEnabled must be exclusive, if AetEnabled = 1 for CPU trace hub, must AetEnabled = 0 for PCH one. The default is set to PCH. CPU Trace Hub 0 = Disabled; 1 = Enabled PCH Trace Hub 0 = Disabled; 1 = Enabled

Definition at line 104 of file TraceHubConfig.h.

◆ EnableMode

UINT8 TRACE_HUB_CONFIG::EnableMode

Trace hub mode.

Default is disabled. Target Debugger mode refers to debug tool running on target device itself and it works as a conventional PCI device; Host Debugger mode refers to SUT debugged via probe on host, configured as ACPI device with PCI configuration sapce hidden. 0 = Disable; 1 = Target Debugger mode; 2 = Host Debugger mode Refer to TRACE_HUB_ENABLE_MODE

Definition at line 86 of file TraceHubConfig.h.

◆ MemReg0Size

UINT8 TRACE_HUB_CONFIG::MemReg0Size

Trace hub memory buffer region size policy.

The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB. Refer to TRACE_BUFFER_SIZE

Definition at line 93 of file TraceHubConfig.h.

The documentation for this struct was generated from the following file:
  • TraceHubConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TRACE_HUB_CONFIG Member List

This is the complete list of members for TRACE_HUB_CONFIG, including all inherited members.

AetEnabled | TRACE_HUB_CONFIG
EnableMode | TRACE_HUB_CONFIG
MemReg0Size | TRACE_HUB_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TRACEHUB_DATA_HOB Struct Reference

List of all members
TRACEHUB_DATA_HOB Struct Reference

Trace Hub Data Hob. More...

#include <TraceHubDataHob.h>

Detailed Description

Trace Hub Data Hob.

Definition at line 47 of file TraceHubDataHob.h.

The documentation for this struct was generated from the following file:
  • TraceHubDataHob.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TRACEHUB_DATA_HOB Member List

This is the complete list of members for TRACEHUB_DATA_HOB, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TS_GPIO_PIN_SETTING Struct Reference

Public Attributes | List of all members
TS_GPIO_PIN_SETTING Struct Reference

This structure configures PCH memory throttling thermal sensor GPIO PIN settings. More...

#include <ThermalConfig.h>

Public Attributes

UINT32 | PmsyncEnable: 1
GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mode. More...
UINT32 | C0TransmitEnable: 1
GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled
UINT32 | PinSelection: 1
GPIO Pin assignment selection, 0: default, 1: secondary.

Detailed Description

This structure configures PCH memory throttling thermal sensor GPIO PIN settings.

Definition at line 103 of file ThermalConfig.h.

Member Data Documentation

◆ PmsyncEnable

UINT32 TS_GPIO_PIN_SETTING::PmsyncEnable

GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mode.

For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.

Definition at line 111 of file ThermalConfig.h.

The documentation for this struct was generated from the following file:
  • ThermalConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TS_GPIO_PIN_SETTING Member List

This is the complete list of members for TS_GPIO_PIN_SETTING, including all inherited members.

C0TransmitEnable | TS_GPIO_PIN_SETTING
PinSelection | TS_GPIO_PIN_SETTING
PmsyncEnable | TS_GPIO_PIN_SETTING
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TSN_CONFIG Struct Reference

Public Attributes | List of all members
TSN_CONFIG Struct Reference

The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN) More...

#include <TsnConfig.h>

Collaboration diagram for TSN_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT8 | Enable
Determines if enable PCH internal TSN, 0: Disable; 1: Enable.
UINT8 | TsnLinkSpeed
Refer to "TSN_LINK_SPEED_OPTIONS". Default is TSN_LINK_SPEED_2_5G_34MHZ
UINT8 | MultiVcEnable
Enable Multi-Vc via Tc to DMA mapping. Deafult is 0:disable
UINT8 | Rsvd0
Reserved bytes, align to multiple 4.
UINT32 | TsnMacAddressHigh
MAC Address High bits. Only two lower bytes are used.
UINT32 | TsnMacAddressLow
MAC Address Low bits.

Detailed Description

The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)

Revision 1:

  • Initial version. Revision 2:
  • Added MultiVcEnable

Definition at line 51 of file TsnConfig.h.

The documentation for this struct was generated from the following file:
  • TsnConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

TSN_CONFIG Member List

This is the complete list of members for TSN_CONFIG, including all inherited members.

Enable | TSN_CONFIG
Header | TSN_CONFIG
MultiVcEnable | TSN_CONFIG
Rsvd0 | TSN_CONFIG
TsnLinkSpeed | TSN_CONFIG
TsnMacAddressHigh | TSN_CONFIG
TsnMacAddressLow | TSN_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UART_PIN_MUX Struct Reference

Public Attributes | List of all members
UART_PIN_MUX Struct Reference

UART signals pin muxing settings. More...

#include <SerialIoDevices.h>

Public Attributes

UINT32 | Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
UINT32 | Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
UINT32 | Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
UINT32 | Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.

Detailed Description

UART signals pin muxing settings.

If signal can be enable only on a single pin then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h for supported settings on a given platform

Definition at line 164 of file SerialIoDevices.h.

The documentation for this struct was generated from the following file:
  • SerialIoDevices.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

UART_PIN_MUX Member List

This is the complete list of members for UART_PIN_MUX, including all inherited members.

Cts | UART_PIN_MUX
Rts | UART_PIN_MUX
Rx | UART_PIN_MUX
Tx | UART_PIN_MUX
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UPDATE_OEM_PLATFORM_ID_REQUEST Struct Reference

List of all members
UPDATE_OEM_PLATFORM_ID_REQUEST Struct Reference

Update OEM Platform Id. More...

#include <UpidMsgs.h>

Collaboration diagram for UPDATE_OEM_PLATFORM_ID_REQUEST:
[legend]

Detailed Description

Update OEM Platform Id.

Definition at line 234 of file UpidMsgs.h.

The documentation for this struct was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

UPDATE_OEM_PLATFORM_ID_REQUEST Member List

This is the complete list of members for UPDATE_OEM_PLATFORM_ID_REQUEST, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UPID_MESSAGE_HEADER Union Reference

List of all members
UPID_MESSAGE_HEADER Union Reference

UPID (Unique Platform Id) Message Header. More...

#include <UpidMsgs.h>

Detailed Description

UPID (Unique Platform Id) Message Header.

Definition at line 43 of file UpidMsgs.h.

The documentation for this union was generated from the following file:
  • UpidMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

UPID_MESSAGE_HEADER Member List

This is the complete list of members for UPID_MESSAGE_HEADER, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB2_PHY_CONFIG Struct Reference

Public Attributes | List of all members
USB2_PHY_CONFIG Struct Reference

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

#include <Usb2PhyConfig.h>

Collaboration diagram for USB2_PHY_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
USB2_PHY_PARAMETERS Port [MAX_USB2_PORTS]
This structure configures per USB2 port physical settings. More...

Detailed Description

This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.

Revision 1:

  • Initial version.

Definition at line 95 of file Usb2PhyConfig.h.

Member Data Documentation

◆ Port

USB2_PHY_PARAMETERS USB2_PHY_CONFIG::Port[MAX_USB2_PORTS]

This structure configures per USB2 port physical settings.

It allows to setup the port location and port length, and configures the port strength accordingly. Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating through Usb2PhySusPgEnable on PCH-LP

Definition at line 103 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB2_PHY_CONFIG Member List

This is the complete list of members for USB2_PHY_CONFIG, including all inherited members.

Header | USB2_PHY_CONFIG
Port | USB2_PHY_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB2_PHY_PARAMETERS Struct Reference

Public Attributes | List of all members
USB2_PHY_PARAMETERS Struct Reference

This structure configures per USB2 AFE settings. More...

#include <Usb2PhyConfig.h>

Public Attributes

UINT8 | Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28.15mV 100b - 28.15mV 101b - 39.35mV 110b - 45mV 111b - 56.3mV.
UINT8 | Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre-emphasis ON 11b - Pre-emphasis & De-emphasis ON.
UINT8 | Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasis.

Detailed Description

This structure configures per USB2 AFE settings.

It allows to setup the port electrical parameters.

Definition at line 49 of file Usb2PhyConfig.h.

The documentation for this struct was generated from the following file:
  • Usb2PhyConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB2_PHY_PARAMETERS Member List

This is the complete list of members for USB2_PHY_PARAMETERS, including all inherited members.

Pehalfbit | USB2_PHY_PARAMETERS
Petxiset | USB2_PHY_PARAMETERS
Predeemp | USB2_PHY_PARAMETERS
Txiset | USB2_PHY_PARAMETERS
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB2_PORT_CONFIG Struct Reference

Public Attributes | List of all members
USB2_PORT_CONFIG Struct Reference

This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 2.0 Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | PortResetMessageEnable: 1
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
UINT32 | RsvdBits0: 22
Reserved bits.

Detailed Description

This structure configures per USB2.0 port settings like enabling and overcurrent protection.

Definition at line 54 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB2_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 2.0 Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 60 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB2_PORT_CONFIG Member List

This is the complete list of members for USB2_PORT_CONFIG, including all inherited members.

Enable | USB2_PORT_CONFIG
OverCurrentPin | USB2_PORT_CONFIG
PortResetMessageEnable | USB2_PORT_CONFIG
RsvdBits0 | USB2_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB3_HSIO_CONFIG Struct Reference

Public Attributes | List of all members
USB3_HSIO_CONFIG Struct Reference

Structure for holding USB3 tuning parameters. More...

#include <Usb3HsioConfig.h>

Collaboration diagram for USB3_HSIO_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
HSIO_PARAMETERS Port [MAX_USB3_PORTS]
These members describe whether the USB3 Port N of PCH is enabled by platform modules.

Detailed Description

Structure for holding USB3 tuning parameters.

Revision 1:

  • Initial version. Revision 2:
  • USB 3.0 TX Output Unique Transition Bit Scale policies added

Definition at line 155 of file Usb3HsioConfig.h.

The documentation for this struct was generated from the following file:
  • Usb3HsioConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB3_HSIO_CONFIG Member List

This is the complete list of members for USB3_HSIO_CONFIG, including all inherited members.

Header | USB3_HSIO_CONFIG
Port | USB3_HSIO_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB3_PORT_CONFIG Struct Reference

Public Attributes | List of all members
USB3_PORT_CONFIG Struct Reference

This structure configures per USB3.x port settings like enabling and overcurrent protection. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | OverCurrentPin: 8
These members describe the specific over current pin number of USB 3.x Port N. More...
UINT32 | Enable: 1
0: Disable; 1: Enable.
UINT32 | RsvdBits0: 23
Reserved bits.

Detailed Description

This structure configures per USB3.x port settings like enabling and overcurrent protection.

Definition at line 69 of file UsbConfig.h.

Member Data Documentation

◆ OverCurrentPin

UINT32 USB3_PORT_CONFIG::OverCurrentPin

These members describe the specific over current pin number of USB 3.x Port N.

It is SW's responsibility to ensure that a given port's bit map is set only for one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.

Definition at line 75 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB3_PORT_CONFIG Member List

This is the complete list of members for USB3_PORT_CONFIG, including all inherited members.

Enable | USB3_PORT_CONFIG
OverCurrentPin | USB3_PORT_CONFIG
RsvdBits0 | USB3_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): USB_CONFIG Struct Reference

Public Attributes | List of all members
USB_CONFIG Struct Reference

This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field. More...

#include <UsbConfig.h>

Collaboration diagram for USB_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Config Block Header.
UINT32 | PdoProgramming: 1
This policy option when set will make BIOS program Port Disable Override register during PEI phase. More...
UINT32 | OverCurrentEnable: 1
This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI. More...
UINT32 | XhciOcLock: 1
(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. More...
UINT32 | LtrOverrideEnable: 1
Enabling this feature will allow for overriding LTR values for xHCI controller. More...
UINT32 | UaolEnable: 1
Enable/disable option for USB Audio Offload feture. More...
UINT32 | HsiiEnable: 1
Enable HS Interrupt IN Alarm 0: disable - Disable HSII 1: enable - Enable HSII
UINT32 | RsvdBits0: 26
Reserved bits.
UINT32 | LtrHighIdleTimeOverride
High Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
UINT32 | LtrMediumIdleTimeOverride
Medium Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
UINT32 | LtrLowIdleTimeOverride
Low Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
USB2_PORT_CONFIG | PortUsb20 [MAX_USB2_PORTS]
These members describe whether the USB2 Port N of PCH is enabled by platform modules.
USB3_PORT_CONFIG | PortUsb30 [MAX_USB3_PORTS]
These members describe whether the USB3 Port N of PCH is enabled by platform modules.
XDCI_CONFIG XdciConfig
This member describes whether or not the xDCI controller should be enabled.

Detailed Description

This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.

The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.

Revision 1:

  • Initial version. Revision 2:
  • Added UaolEnable to control USB Audio Offload Capability. Revision 3:
  • Add HsiiEnable enable option to control HSII feature

Definition at line 106 of file UsbConfig.h.

Member Data Documentation

◆ LtrOverrideEnable

UINT32 USB_CONFIG::LtrOverrideEnable

Enabling this feature will allow for overriding LTR values for xHCI controller.

Values used for programming will be taken from this config block and BIOS will disregard recommended ones. 0: disable - do not override recommended LTR values 1: enable - override recommended LTR values

Definition at line 141 of file UsbConfig.h.

◆ OverCurrentEnable

UINT32 USB_CONFIG::OverCurrentEnable

This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.

Disabling this feature will disable overcurrent detection functionality. Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field. By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage. 1: Will program USB OC pin mapping in respective xHCI controller registers 0: Will clear OC pin mapping allow for OBS usage of OC pins

Definition at line 124 of file UsbConfig.h.

◆ PdoProgramming

UINT32 USB_CONFIG::PdoProgramming

This policy option when set will make BIOS program Port Disable Override register during PEI phase.

When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming. If this is disabled, platform code MUST set it before booting into OS. 1: Enable 0: Disable

Definition at line 115 of file UsbConfig.h.

◆ UaolEnable

UINT32 USB_CONFIG::UaolEnable

Enable/disable option for USB Audio Offload feture.

Disabling this will disable UAOL capability in xHCI and UAOL ACPI definitions will be hidden. 0: disable UAOL 1: enable UAOL

Definition at line 148 of file UsbConfig.h.

◆ XhciOcLock

UINT32 USB_CONFIG::XhciOcLock

(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.

OverCurrent mapping data is taken from respective port data structure from OverCurrentPin field. If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data. 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data 0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.

Definition at line 134 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

USB_CONFIG Member List

This is the complete list of members for USB_CONFIG, including all inherited members.

Header | USB_CONFIG
HsiiEnable | USB_CONFIG
LtrHighIdleTimeOverride | USB_CONFIG
LtrLowIdleTimeOverride | USB_CONFIG
LtrMediumIdleTimeOverride | USB_CONFIG
LtrOverrideEnable | USB_CONFIG
OverCurrentEnable | USB_CONFIG
PdoProgramming | USB_CONFIG
PortUsb20 | USB_CONFIG
PortUsb30 | USB_CONFIG
RsvdBits0 | USB_CONFIG
UaolEnable | USB_CONFIG
XdciConfig | USB_CONFIG
XhciOcLock | USB_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VMD_PEI_CONFIG Struct Reference

Public Attributes | List of all members
VMD_PEI_CONFIG Struct Reference

This configuration block is to configure VMD related variables used in PostMem PEI. More...

#include <VmdPeiConfig.h>

Collaboration diagram for VMD_PEI_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable 0=Disable(default)
UINT8 | VmdPortBEnable
Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
UINT8 | VmdPortCEnable
Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
UINT8 | VmdPortDEnable
Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
UINT8 | VmdCfgBarSize
Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default) More...
UINT8 | VmdCfgBarAttr
Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, 2: VMD_64BIT_NONPREFETCH(Default)
UINT8 | VmdMemBarSize1
Offset 35 This is used to set the VMD Mem Bar1 size. 25 (32MB).
UINT8 | VmdMemBar1Attr
Offset 36 This is used to set VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default) 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH.
UINT8 | VmdMemBarSize2
Offset 37 This is used to set the VMD Mem Bar2 size. 20(1MB).
UINT8 | VmdMemBar2Attr
Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH.
UINT8 | VmdGlobalMapping
Offset 39 This field used to enable Global Mapping 1=Enable 0=Disable(default)
RP_BDF_DATA | VmdPortEnable [VMD_MAX_DEVICES]
Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable 0=Disable (default)
UINT32 | VmdCfgBarBase
This config block will be updated as per the EFI variable.
UINT32 | VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA0000000
UINT32 | VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA2000000

Detailed Description

This configuration block is to configure VMD related variables used in PostMem PEI.

If VMD Device is not supported, all policies can be ignored. Revision 1:

  • Initial version. Revision 2:
  • Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
  • Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details. (Added B/D/F fields along with Port Enable for up to max 31 devices). Revision 3: Added policy to get the Bar values from platform PCD. Revision 4: Added VmdGlobalMapping to map all the storage devices under VMD

Definition at line 67 of file VmdPeiConfig.h.

Member Data Documentation

◆ VmdCfgBarSize

UINT8 VMD_PEI_CONFIG::VmdCfgBarSize

Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)

Offset 33 This is used to set the VMD Config Bar Size. 25(32MB)

Definition at line 74 of file VmdPeiConfig.h.

The documentation for this struct was generated from the following file:
  • VmdPeiConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

VMD_PEI_CONFIG Member List

This is the complete list of members for VMD_PEI_CONFIG, including all inherited members.

Header | VMD_PEI_CONFIG
VmdCfgBarAttr | VMD_PEI_CONFIG
VmdCfgBarBase | VMD_PEI_CONFIG
VmdCfgBarSize | VMD_PEI_CONFIG
VmdEnable | VMD_PEI_CONFIG
VmdGlobalMapping | VMD_PEI_CONFIG
VmdMemBar1Attr | VMD_PEI_CONFIG
VmdMemBar1Base | VMD_PEI_CONFIG
VmdMemBar2Attr | VMD_PEI_CONFIG
VmdMemBar2Base | VMD_PEI_CONFIG
VmdMemBarSize1 | VMD_PEI_CONFIG
VmdMemBarSize2 | VMD_PEI_CONFIG
VmdPortBEnable | VMD_PEI_CONFIG
VmdPortCEnable | VMD_PEI_CONFIG
VmdPortDEnable | VMD_PEI_CONFIG
VmdPortEnable | VMD_PEI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VTD_CONFIG Struct Reference

Public Attributes | List of all members
VTD_CONFIG Struct Reference

The data elements should be initialized by a Platform Module. More...

#include <VtdConfig.h>

Collaboration diagram for VTD_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
UINT8 | VtdDisable
Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec. More...
UINT8 | X2ApicOptOut
Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and 0=Disable/Clear
UINT8 | DmaControlGuarantee
Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIgdEnable
Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIpuEnable
Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | VtdIopEnable
Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and 0=Disable/Clear
UINT8 | PreBootDmaMask
Deprecate. More...
UINT32 | BaseAddress [VTD_ENGINE_NUMBER]
Offset 36: This field is used to describe the base addresses for VT-d function.
UINT32 | DmaBufferSize
Offset 48: Protect Memory Region (PMR) DMA buffer size.
UINT32 | Reserved
Offset 52: Reserved.
EFI_PHYSICAL_ADDRESS | EnableDmaBuffer
Offset 56: Pointer to EnableDmaBuffer function. More...

Detailed Description

The data elements should be initialized by a Platform Module.

The data structure is for VT-d driver initialization
Revision 1:

  • Initial version. Revision 2:
  • Added field EnableDmaBuffer.

Definition at line 72 of file VtdConfig.h.

Member Data Documentation

◆ EnableDmaBuffer

EFI_PHYSICAL_ADDRESS VTD_CONFIG::EnableDmaBuffer

Offset 56: Pointer to EnableDmaBuffer function.

Platform code provides an interface to enable DMA buffer. VTD_ENABLE_DMA_BUFFER is a prototype for that interface.

Definition at line 93 of file VtdConfig.h.

◆ PreBootDmaMask

UINT8 VTD_CONFIG::PreBootDmaMask

Deprecate.

Offset 35: Convey PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg

Definition at line 89 of file VtdConfig.h.

◆ VtdDisable

UINT8 VTD_CONFIG::VtdDisable

Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.

This policy is for debug purpose only. If VT-D is not supported, all other policies in this config block will be ignored. 0 = To use Vt-d; 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.

Definition at line 82 of file VtdConfig.h.

The documentation for this struct was generated from the following file:
  • VtdConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

VTD_CONFIG Member List

This is the complete list of members for VTD_CONFIG, including all inherited members.

BaseAddress | VTD_CONFIG
DmaBufferSize | VTD_CONFIG
DmaControlGuarantee | VTD_CONFIG
EnableDmaBuffer | VTD_CONFIG
Header | VTD_CONFIG
PreBootDmaMask | VTD_CONFIG
Reserved | VTD_CONFIG
VtdDisable | VTD_CONFIG
VtdIgdEnable | VTD_CONFIG
VtdIopEnable | VTD_CONFIG
VtdIpuEnable | VTD_CONFIG
X2ApicOptOut | VTD_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VTD_DXE_CONFIG Struct Reference

Public Attributes | List of all members
VTD_DXE_CONFIG Struct Reference

The data structure is for VT-d driver initialization in DXE
Revision 1: More...

#include <VtdConfig.h>

Collaboration diagram for VTD_DXE_CONFIG:
[legend]

Public Attributes

CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.

Detailed Description

The data structure is for VT-d driver initialization in DXE
Revision 1:

  • Initial version. Revision 2:
  • Added TE Disable for Igd. Revision 3:
  • Removed TE Disable for Igd.

Definition at line 106 of file VtdConfig.h.

The documentation for this struct was generated from the following file:
  • VtdConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

VTD_DXE_CONFIG Member List

This is the complete list of members for VTD_DXE_CONFIG, including all inherited members.

Header VTD_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WIFI_8021X_CLIENT_CERT Struct Reference

List of all members
WIFI_8021X_CLIENT_CERT Struct Reference

Get Wifi profile specific 8021X client certificate from ASF. More...

#include <WifiProfileSyncAsfMsgs.h>

Detailed Description

Get Wifi profile specific 8021X client certificate from ASF.

Definition at line 129 of file WifiProfileSyncAsfMsgs.h.

The documentation for this struct was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

WIFI_8021X_CLIENT_CERT Member List

This is the complete list of members for WIFI_8021X_CLIENT_CERT, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WIFI_8021X_CLIENT_KEY Struct Reference

List of all members
WIFI_8021X_CLIENT_KEY Struct Reference

Get Wifi profile specific 8021X client key from ASF. More...

#include <WifiProfileSyncAsfMsgs.h>

Detailed Description

Get Wifi profile specific 8021X client key from ASF.

Definition at line 151 of file WifiProfileSyncAsfMsgs.h.

The documentation for this struct was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

WIFI_8021X_CLIENT_KEY Member List

This is the complete list of members for WIFI_8021X_CLIENT_KEY, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WIFI_PROFILE_DATA Struct Reference

List of all members
WIFI_PROFILE_DATA Struct Reference

Get Wifi profile data response from ASF. More...

#include <WifiProfileSyncAsfMsgs.h>

Detailed Description

Get Wifi profile data response from ASF.

Definition at line 86 of file WifiProfileSyncAsfMsgs.h.

The documentation for this struct was generated from the following file:
  • WifiProfileSyncAsfMsgs.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

WIFI_PROFILE_DATA Member List

This is the complete list of members for WIFI_PROFILE_DATA, including all inherited members.

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): XDCI_CONFIG Struct Reference

Public Attributes | List of all members
XDCI_CONFIG Struct Reference

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...

#include <UsbConfig.h>

Public Attributes

UINT32 | Enable: 1
This member describes whether or not the xDCI controller should be enabled. More...
UINT32 | RsvdBits0: 31
Reserved bits.

Detailed Description

The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.

Definition at line 84 of file UsbConfig.h.

Member Data Documentation

◆ Enable

UINT32 XDCI_CONFIG::Enable

This member describes whether or not the xDCI controller should be enabled.

0: Disable; 1: Enable.

Definition at line 89 of file UsbConfig.h.

The documentation for this struct was generated from the following file:
  • UsbConfig.h
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Member List

XDCI_CONFIG Member List

This is the complete list of members for XDCI_CONFIG, including all inherited members.

Enable | XDCI_CONFIG
RsvdBits0 | XDCI_CONFIG
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Index

Class Index
_ | a | b | c | d | f | g | h | i | m | o | p | r | s | t | u | v | w | x
_
BGUP_HEADER GET_REFURBISH_COUNTER_REQUEST ME_CAP SA_DATA_HOB
BIOS_GUARD_CONFIG GET_RPMC_STATUS ME_DXE_CONFIG SA_FUNCTION_CALLS
_AMT_POLICY_PROTOCOL BIOSGUARD_HOB GET_RSE_PASSWORD ME_PEI_CONFIG SA_GPIO_INFO_PCIE
_AMT_READY_TO_BOOT_PROTOCOL BIOSGUARD_LOG GET_RSE_PASSWORD_BUFFER ME_PEI_PREMEM_CONFIG SA_MEMORY_DQDQS_MAPPING
_AMT_SAVE_MEBX_PROTOCOL BIST_HOB_DATA GET_RSE_PASSWORD_RESPONSE ME_SMBIOS_TABLES_UPDATE_PROTOCOL SA_MEMORY_FUNCTIONS
_BIOS_OS_DATA_REGION BOOT_GUARD_INFO GET_WIFI_CLIENT_CERT_BUFFER MEBX_PROTOCOL SA_MEMORY_RCOMP
_BIOSGUARD_PROTOCOL BOOT_OPTION_CAPS_STRUC GET_WIFI_CLIENT_KEY_BUFFER MEFWCAPS_SKU SA_MISC_PEI_CONFIG
_CONFIG_BLOCK BUP_MPHY_READ_FROM_MPHY GET_WIFI_PROFILE_DATA_BUFFER MEI_DEV_STRING SA_MISC_PEI_PREMEM_CONFIG
_CONFIG_BLOCK_HEADER
c
GET_WIFI_PROFILE_NAME_BUFFER MEM_INFO_PROTOCOL SA_PEG_DATA
_CONFIG_BLOCK_TABLE_STRUCT GET_WIFI_PROFILE_NAME_RESPONSE MEMORY_CONFIG_NO_CRC SA_PEG_HOB
_CPU_INFO_PROTOCOL CACHE_DESCRIPTOR_INFO GNA_CONFIG MEMORY_CONFIGURATION SA_POLICY_PROTOCOL
_DXE_ITBT_CONFIG CBM_RESET_ACK GOP_POLICY_PROTOCOL MEMORY_INFO_DATA SA_XDCI_IRQ_INT_CONFIG
_DXE_ITBT_GENERIC_CONFIG CBM_RESET_REQ GPIO_CONFIG MEMORY_PLATFORM_DATA SATA_CONFIG
_EFI_SMM_VARIABLE_PROTOCOL CBM_RESET_REQ_DATA GPIO_DXE_CONFIG MEMORY_TIMING SATA_THERMAL_THROTTLING
_FSP_TEMP_RAM_EXIT_PPI CFG_COMPLETE_CONFIGURATION_REQUEST GRAPHICS_DXE_CONFIG MG_IMR_STATUS SCS_SD_DLL
_GOP_COMPONENT_NAME2_PROTOCOL CFG_GET_FQDN_REQUEST GRAPHICS_PEI_CONFIG MKHI_MESSAGE_HEADER SERIAL_IO_CONFIG
_HEAP_BIOS_SPEC_VER_ELEMENT CFG_GET_IDLE_TIMEOUT_REQUEST GRAPHICS_PEI_PREMEM_CONFIG MSR_TURBO_RATIO_LIMIT_REGISTER SERIAL_IO_I2C_CONFIG
_HEAP_BIOSACM_ELEMENT CFG_GET_INTERFACE_VERSION_RESPONSE
h
MUX_GPIO_PARAM SERIAL_IO_SPI_CONFIG
_HEAP_EXT_DATA_ELEMENT CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE
o
SERIAL_IO_UART_ATTRIBUTES
_HECI_ACCESS_ CFG_GET_PRIVACY_LEVEL_REQUEST HDA_LINK_DMIC SERIAL_IO_UART_CONFIG
_HECI_CONTROL_ CFG_GET_REDIRECTION_STATE_REQUEST HDA_LINK_HDA OVERCLOCKING_PREMEM_CONFIG SET_FILE
_HECI_PPI CFG_GET_ZTC_ENABLED_STATUS_REQUEST HDA_LINK_SNDW
p
SET_FILE_EX
_HECI_PROTOCOL CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST HDA_LINK_SSP SET_ME_RESET_HALT
_IO_TRAP_EX_DISPATCH_PROTOCOL CFG_SET_KVM_ENABLED_REQUEST HDA_VERB_TABLE_HEADER PCH_DCI_PREMEM_CONFIG SET_MEASURED_BOOT
_ITBT_GENERIC_CONFIG CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST HDAUDIO_CONFIG PCH_DEVICE_INTERRUPT_CONFIG SFAM_DATA
_ITBT_ROOTPORT_CONFIG CFG_STOP_CONFIGURATION_REQUEST HDAUDIO_DXE_CONFIG PCH_DMI_CONFIG SGX_INFO
_ME_JHI_PROTOCOL CFG_UNPROVISION_REQUEST HDAUDIO_PREMEM_CONFIG PCH_DMI_EQ_PARAM SI_CONFIG
_ME_PLATFORM_GET_RESET_TYPE_PROTOCOL CHIPSET_INIT_INFO HECI_ASF_PUSH_PROGRESS_CODE PCH_DMI_HOB SI_PREMEM_CONFIG
_ME_POLICY_PROTOCOL CLEAR_BOOT_OPTIONS HECI_CONTROL_STATUS_REGISTER PCH_ESPI_CONFIG SMBIOS_CACHE_INFO
_MEBX_CONFIG_PROTOCOL CNVI_CONFIG HECI_FW_STS3_REGISTER PCH_FIVR_CONFIG SMBIOS_PROCESSOR_INFO
_MEBX_DISPLAY_PROTOCOL CNVI_PIN_MUX HECI_FW_STS4_REGISTER PCH_FLASH_PROTECTION_CONFIG SMBIOS_TABLE_TYPE130
_MEMORY_DXE_CONFIG CNVI_PREMEM_CONFIG HECI_FW_STS5_REGISTER PCH_GENERAL_CONFIG SMBIOS_TABLE_TYPE131
_OC_MAILBOX_FULL COMMIT_FILES HECI_FW_STS6_REGISTER PCH_GENERAL_PREMEM_CONFIG SMM_RESOURCE_CONFIG_PROTOCOL
_OC_MAILBOX_INTERFACE CORE_BIOS_DONE HECI_FWS_REGISTER PCH_HSIO_CONFIG SMRAM_CPU_INFO
_PCH_ACPI_SMI_DISPATCH_PROTOCOL CPU_CONFIG HECI_GS_SHDW_REGISTER PCH_HSIO_PCIE_LANE_CONFIG SPD_DATA_BUFFER
_PCH_ESPI_SMI_DISPATCH_PROTOCOL CPU_CONFIG_LIB_PREMEM_CONFIG HG_INFO PCH_HSIO_PCIE_PREMEM_CONFIG SPD_OFFSET_TABLE
_PCH_PCIE_SMI_DISPATCH_PROTOCOL CPU_DATA_HOB HMRFPO_ENABLE PCH_HSIO_PREMEM_CONFIG SPECIAL_COMMAND_CAPS_STRUC
_PCH_PREMEM_POLICY CPU_DMI_EQ_PARAM HMRFPO_GET_STATUS PCH_HSIO_SATA_PORT_LANE SPI_CONFIG
_PCH_SMI_DISPATCH_PROTOCOL CPU_DMI_HOB HMRFPO_LOCK PCH_HSIO_SATA_PREMEM_CONFIG SPI_PIN_MUX
_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL CPU_DMI_PREMEM_CONFIG HOB_SAGV_INFO PCH_INFO_HOB SPS_RING3_EXCEPTION_HANDLER
_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL CPU_INFO HOB_SAGV_TIMING_OUT PCH_INTERRUPT_CONFIG SVID_SID_VALUE
_PCH_SPI_PROTOCOL CPU_PCIE_CONFIG HOB_USAGE_DATA_HOB PCH_IOAPIC_CONFIG SYSTEM_CAPS_STRUC
_PCH_TCO_SMI_DISPATCH_PROTOCOL CPU_PCIE_EQ_LANE_PARAM HOST_BRIDGE_PEI_CONFIG PCH_LOCK_DOWN_CONFIG
t
_PCODE_MAILBOX_FULL CPU_PCIE_GPIO_INFO HOST_BRIDGE_PREMEM_CONFIG PCH_LPC_GEN_IO_RANGE
_PCODE_MAILBOX_INTERFACE CPU_PCIE_HOB HR_NOTIFICATION_CMD PCH_LPC_GEN_IO_RANGE_LIST TBT_IMR_STATUS
_PEI_ITBT_CONFIG CPU_PCIE_PWR_OPT HSIO_PARAMETERS PCH_LPC_PREMEM_CONFIG TCSS_DATA
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI CPU_PCIE_ROOT_PORT_CONFIG HWA_DATA PCH_MEMORY_THROTTLING TCSS_DATA_HOB
_PEI_SI_DEFAULT_POLICY_INIT_PPI CPU_PCIE_RP_PREMEM_CONFIG HWA_MESSAGE_HEADER PCH_P2SB_CONFIG TCSS_DATA_SSID_HOB
_PEI_SMM_CONTROL_PPI CPU_PCIE_RTD3_GPIO HWA_PUSH_TABLES_MSG PCH_PCIE_CLOCK TCSS_DEVEN_PEI_PREMEM_CONFIG
_PLATFORM_ME_HOOK_PROTOCOL CPU_POWER_MGMT_BASIC_CONFIG HYBRID_GRAPHICS_CONFIG PCH_PCIE_CONFIG TCSS_IOM_ORI_OVERRIDE
_PPM_CUSTOM_CTDP_TABLE CPU_POWER_MGMT_CUSTOM_CONFIG HYBRID_STORAGE_CONFIG PCH_PCIE_ROOT_PORT_CONFIG TCSS_IOM_PEI_CONFIG
_SI_POLICY_STRUCT CPU_POWER_MGMT_PSYS_CONFIG
i
PCH_PCIE_RP_PREMEM_CONFIG TCSS_MISC_PEI_CONFIG
_SI_PREMEM_POLICY_STRUCT CPU_POWER_MGMT_TEST_CONFIG PCH_PM_CONFIG TCSS_MISC_PEI_PREMEM_CONFIG
_THC_PROTOCOL CPU_POWER_MGMT_VR_CONFIG I2C_PIN_MUX PCH_POLICY_PROTOCOL TCSS_PCIE_PEI_POLICY
_TXT_INFO_DATA CPU_SECURITY_PREMEM_CONFIG ICC_CLOCK_MODE PCH_SATA_PORT_CONFIG TCSS_PCIE_PORT_POLICY
_TXT_INFO_HOB CPU_TEST_CONFIG ICC_CLOCK_SETTINGS PCH_SMBUS_PREMEM_CONFIG TCSS_PEI_CONFIG
_WDT_PROTOCOL CPU_TRACE_HUB_PREMEM_CONFIG ICC_CLOCK_SETTINGS_CURRENT_FLAGS PCH_TRACE_HUB_PREMEM_CONFIG TCSS_PEI_PREMEM_CONFIG
a
CPU_TXT_PREMEM_CONFIG ICC_CLOCK_SETTINGS_FLAGS PCH_WAKE_CONFIG TCSS_USBTC_PEI_PERMEM_CONFIG
d
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS PCH_WDT_PREMEM_CONFIG TELEMETRY_PEI_CONFIG
ADR_CONFIG ICC_GET_CLK_CAPABILITIES_MESSAGE PCIE_COMMON_CONFIG TELEMETRY_PEI_PREMEM_CONFIG
ADR_SOURCE_ENABLE DDI_CONFIGURATION ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ PCIE_DEVICE_OVERRIDE THC_CONFIG
ALERT_STANDARD_FORMAT_PROTOCOL DIMM_INFO ICC_GETSET_CLOCK_SETTINGS_REQRSP PCIE_DXE_CONFIG THC_HID_OVER_SPI
AMT_DXE_CONFIG DMI_HW_WIDTH_CONTROL ICC_MESSAGE_RESP_DATA PCIE_EQ_PARAM THC_PORT
AMT_GET_ACTIVE_LAN_INTERFACE DNX_REQ_CLEAR ICC_OVERRIDE_SOFT_STRAP_CMD_REQ PCIE_GPIO THERMAL_CONFIG
AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER DNX_REQ_SET IEH_CONFIG PCIE_IMR_CONFIG THERMAL_THROTTLE_LEVELS
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE DPIN_PREMEM_CONFIG IGD_OPREGION_PROTOCOL PCIE_LINK_EQ_PLATFORM_SETTINGS TPM_STATE
AMT_PEI_CONFIG DXE_CPU_POLICY_PROTOCOL INVOCATION_CODE_BITS PCIE_PEI_CONFIG TRACE_HUB_CONFIG
AMT_PET_QUEUE_HOB DXE_SI_POLICY_PROTOCOL IO_TRAP_EX_REGISTER_CONTEXT PCIE_PEI_PREMEM_CONFIG TRACEHUB_DATA_HOB
AMT_QUERY_KVM
f
IOM_AUX_ORI_PAD_CONFIG PCIE_PEI_PREMEM_CONFIG_GEN3 TS_GPIO_PIN_SETTING
AMT_QUERY_KVM_BUFFER IOM_INTERFACE_CONFIG PCIE_PREMEM_CONFIG TSN_CONFIG
AMT_QUERY_KVM_RESPONSE FIPS_VERSION IPU_DATA_HOB PCIE_RP_DXE_CONFIG
u
AMT_SCREEN_RESOLUTION FIVR_EXT_RAIL_CONFIG IPU_PREMEM_CONFIG PCIE_RTD3_GPIO
AMT_SET_ACTIVE_LAN_INTERFACE FIVR_VCCIN_AUX_CONFIG ISH_CONFIG PEG_GPIO_DATA UART_PIN_MUX
AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER FSP_ERROR_INFO_HOB ISH_GP PET_ALERT UPDATE_OEM_PLATFORM_ID_REQUEST
AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE FSPM_ARCH_CONFIG_PPI ISH_GPIO_CONFIG PMC_GLOBAL_RESET_MASK UPID_MESSAGE_HEADER
AMT_SET_MAC_PASSTHROUGH_BUFFER FUSA_CONFIG ISH_I2C PMC_INTERFACE_CONFIG USB2_PHY_CONFIG
AMT_SET_MAC_PASSTHROUGH_RESPONSE FVI_DATA ISH_I2C_PIN_CONFIG PMC_LPM_S0IX_SUB_STATE_EN USB2_PHY_PARAMETERS
ARB_SVN_COMMIT FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA ISH_I3C_CONFIG PORT_INFO USB2_PORT_CONFIG
ARB_SVN_GET_INFO FWSTS_SET_RECORD ISH_PREMEM_CONFIG PPM_CUSTOM_RATIO_TABLE USB3_HSIO_CONFIG
ASF_BOOT_OPTIONS FWSTS_SMBIOS_RECORD ISH_SPI PROTECTED_RANGE USB3_PORT_CONFIG
ASF_DATA_HUB_MAP
g
ISH_SPI_PIN_CONFIG PSF_CONFIG USB_CONFIG
ASF_FRAMEWORK_MESSAGE ISH_UART
r
v
ASF_MESSAGE GBE_CONFIG ISH_UART_PIN_CONFIG
ASF_MESSAGE_HEADER GEN_SEND_CPU_BRAND ITBT_POLICY_PROTOCOL RC_VERSION VMD_PEI_CONFIG
ASF_PROFILE_MESSAGE_HEADER GET_BOOT_OPTIONS
m
READ_FILE VTD_CONFIG
ASF_START_WDT GET_BOOT_OPTIONS_BUFFER READ_FILE_EX VTD_DXE_CONFIG
ASF_STOP_WDT GET_BOOT_OPTIONS_RESPONSE MBP_FW_VERSION_NAME REPORT_BIOS_STATUS
w
b
GET_FEATURE_STATE_REQUEST MBP_HEADER REQUEST_OWNERSHIP
GET_FEATURE_SUPPORT_REQUEST MBP_IFWI_DNX_REQUEST RST_CONFIG WIFI_8021X_CLIENT_CERT
BCLK_CONFIG GET_FW_VER MBP_ITEM_HEADER RST_HARDWARE_REMAPPED_STORAGE_CONFIG WIFI_8021X_CLIENT_KEY
BDAT_ACCESS_PROTOCOL GET_IMR_CMD_REQ_DATA MBP_MPHY_DATA RTC_CONFIG WIFI_PROFILE_DATA
BDAT_SCHEMA_LIST_HOB GET_MEASURED_BOOT MBP_SENSITIVE_PPI
s
x
BGPDT GET_OS_CONTROL_FEATURE_STATE_REQUEST ME_BIOS_PAYLOAD
BGUP GET_PLATFORM_ID_REQUEST ME_BIOS_PAYLOAD_SENSITIVE SA_ADDRESS_DECODE XDCI_CONFIG
_ | a | b | c | d | f | g | h | i | m | o | p | r | s | t | u | v | w | x
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- a -

  • AcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • AcmActived : HECI_FW_STS5_REGISTER
  • AcmDone : HECI_FW_STS5_REGISTER
  • AcmMajorVersion : _TXT_INFO_DATA
  • AcmMinorVersion : _TXT_INFO_DATA
  • AcmRevision : _TXT_INFO_DATA
  • AcousticNoiseMitigation : CPU_POWER_MGMT_VR_CONFIG
  • AcpiBase : _TXT_INFO_DATA
  • AcpiL6dPmeHandling : PCH_GENERAL_CONFIG
  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • AcSplitLock : CPU_CONFIG
  • Active : CPU_PCIE_GPIO_INFO , PCIE_GPIO , SA_GPIO_INFO_PCIE
  • ActiveCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveCoreCount1 : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveInterface : AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE
  • ActiveLtr : THC_PORT
  • ActiveSmallCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveSocNorthAtomCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActualFreq : CPU_INFO
  • Address : IO_TRAP_EX_REGISTER_CONTEXT
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOverride : ADR_CONFIG
  • AdrSrcSel : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AesEnable : CPU_CONFIG
  • AetEnabled : TRACE_HUB_CONFIG
  • ALIASCHK : MEMORY_CONFIGURATION
  • AllowKnownReset : _WDT_PROTOCOL
  • AllowOppRefBelowWriteThrehold : MEMORY_CONFIGURATION
  • AllTpmDisconnected : HECI_FW_STS4_REGISTER
  • AlsEnable : GRAPHICS_DXE_CONFIG
  • Amt : MEFWCAPS_SKU
  • AmtbxHotkeyPressed : AMT_DXE_CONFIG
  • AmtbxSelectionScreen : AMT_DXE_CONFIG
  • AmtEnabled : AMT_PEI_CONFIG , SMBIOS_TABLE_TYPE130
  • AmtKvmEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSignature : SMBIOS_TABLE_TYPE130
  • AmtSolEnabled : AMT_PEI_CONFIG
  • AmtSupported : SMBIOS_TABLE_TYPE130
  • ApertureSize : GRAPHICS_PEI_PREMEM_CONFIG
  • ApicId : BIST_HOB_DATA
  • AppId : MBP_ITEM_HEADER
  • ApplyConfigTdp : CPU_POWER_MGMT_BASIC_CONFIG
  • ApStartupBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • AsfBootOptions : GET_BOOT_OPTIONS_RESPONSE
  • AsfHeader : AMT_GET_ACTIVE_LAN_INTERFACE , AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_QUERY_KVM , AMT_QUERY_KVM_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE , AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_MAC_PASSTHROUGH_RESPONSE , ASF_PROFILE_MESSAGE_HEADER , ASF_START_WDT , ASF_STOP_WDT , CLEAR_BOOT_OPTIONS , GET_BOOT_OPTIONS , GET_RSE_PASSWORD , GET_RSE_PASSWORD_RESPONSE , GET_WIFI_PROFILE_NAME_RESPONSE , PET_ALERT , REPORT_BIOS_STATUS
  • AsfMessage : HECI_ASF_PUSH_PROGRESS_CODE
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • Associativity : CACHE_DESCRIPTOR_INFO , SMBIOS_CACHE_INFO
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2MaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • AtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomTurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • AtomTurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioDspFusedOut : PCH_INFO_HOB
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AutoSelfRefreshSupport : MEMORY_CONFIGURATION
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3Disable : CPU_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • AvxDisable : CPU_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- b -

  • BacklightControlSupport : GRAPHICS_DXE_CONFIG
  • Bank : SA_ADDRESS_DECODE
  • BankGroup : SA_ADDRESS_DECODE
  • BaseAddress : VTD_CONFIG
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • Bclk : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BClkFrequency : MEMORY_CONFIGURATION
  • BclkRfiFreq : MEMORY_CONFIGURATION
  • BclkSource : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BCLM : GRAPHICS_DXE_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • BestPreset : SA_PEG_DATA
  • BgModSvn : BGPDT , BIOSGUARD_LOG
  • Bgpdt : BIOSGUARD_HOB
  • BgpdtHash : BIOS_GUARD_CONFIG
  • BgpdtMajVer : BGPDT
  • BgpdtMinVer : BGPDT
  • BgpdtSize : BGPDT
  • BgupBuffer : BGUP
  • BgupHeader : BGUP , BIOSGUARD_HOB
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosAcmBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • BiosAcmSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • BiosGuard : CPU_SECURITY_PREMEM_CONFIG
  • BiosGuardAttr : BGPDT , BIOS_GUARD_CONFIG
  • BiosGuardIoTrapAddress : BIOSGUARD_HOB
  • BiosGuardIoTrapLength : BIOSGUARD_HOB
  • BiosGuardLog : BIOSGUARD_HOB
  • BiosGuardMemAddress : BIOSGUARD_HOB
  • BiosGuardMemSize : BIOSGUARD_HOB
  • BiosGuardModulePtr : BIOS_GUARD_CONFIG , BIOSGUARD_HOB
  • BiosGuardModuleSize : BIOSGUARD_HOB
  • BiosGuardToolsInterface : CPU_SECURITY_PREMEM_CONFIG
  • BiosInterface : PCH_LOCK_DOWN_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosLock : PCH_LOCK_DOWN_CONFIG
  • BiosSinitSize : _BIOS_OS_DATA_REGION
  • BiosSize : CPU_SECURITY_PREMEM_CONFIG
  • BiosStatus : REPORT_BIOS_STATUS
  • BiosSvn : BGPDT , BGUP_HEADER
  • BiosWrProtectRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • BiosWrReportRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • BiProcHot : CPU_POWER_MGMT_TEST_CONFIG
  • BistOnReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BistResetRequest : HECI_FWS_REGISTER
  • BistTestState : HECI_FWS_REGISTER
  • Bits : MSR_TURBO_RATIO_LIMIT_REGISTER
  • BltBufferAddress : GRAPHICS_PEI_CONFIG
  • BltBufferSize : GRAPHICS_PEI_CONFIG
  • BmeMasterSlaveEnabled : PCH_ESPI_CONFIG
  • BootFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG
  • BootGuardCapability : BOOT_GUARD_INFO
  • BootGuardDisable : HECI_FW_STS6_REGISTER
  • BootGuardFwStsValid : HECI_FW_STS4_REGISTER
  • BootGuardSelfTest : HECI_FW_STS4_REGISTER
  • BootMode : SPD_OFFSET_TABLE
  • BootOptionsMaskByte1 : ASF_BOOT_OPTIONS
  • BootOptionsMaskByte2 : ASF_BOOT_OPTIONS
  • BrandString : CPU_INFO
  • BspInitDisabled : HECI_FW_STS6_REGISTER
  • BtAudioOffload : CNVI_CONFIG
  • BtCore : CNVI_CONFIG
  • BypassFivrConfig : PCH_FIVR_CONFIG
  • BypassPhySyncReset : PCH_HSIO_PREMEM_CONFIG
  • ByPassTpmEventLog : BOOT_GUARD_INFO
  • BypassTpmInit : BOOT_GUARD_INFO
  • ByteCount : ASF_MESSAGE_HEADER , GET_BOOT_OPTIONS_RESPONSE , HECI_ASF_PUSH_PROGRESS_CODE
  • ByteEnable : IO_TRAP_EX_REGISTER_CONTEXT
  • ByteEnableMask : IO_TRAP_EX_REGISTER_CONTEXT
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- c -

  • C0TransmitEnable : TS_GPIO_PIN_SETTING
  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • C1AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C1e : CPU_POWER_MGMT_TEST_CONFIG
  • C1UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheInfo : CPU_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CallerId : FSP_ERROR_INFO_HOB
  • Cas : SA_ADDRESS_DECODE
  • CBDepth : HECI_CONTROL_STATUS_REGISTER
  • CBReadPointer : HECI_CONTROL_STATUS_REGISTER
  • CBWritePointer : HECI_CONTROL_STATUS_REGISTER
  • CdClock : GRAPHICS_PEI_CONFIG
  • CdrRelock : CPU_PCIE_RP_PREMEM_CONFIG
  • CdynmaxClampEnable : GRAPHICS_PEI_CONFIG
  • CenterSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • ChangeAllowed : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • Channel : SA_ADDRESS_DECODE
  • ChannelASlotMap : _MEMORY_DXE_CONFIG
  • ChapDeviceEnable : HOST_BRIDGE_PEI_CONFIG
  • CheckPoint : SA_FUNCTION_CALLS
  • CheckStatus : _WDT_PROTOCOL
  • ChHashEnable : MEMORY_CONFIGURATION
  • ChHashInterleaveBit : MEMORY_CONFIGURATION
  • ChHashMask : MEMORY_CONFIGURATION
  • ChHashOverride : MEMORY_CONFIGURATION
  • ChipsetInitBinLen : PCH_HSIO_CONFIG
  • ChipsetInitBinPtr : PCH_HSIO_CONFIG
  • ChipsetInitMessage : PCH_HSIO_PREMEM_CONFIG
  • ChipsetIsTxtCapable : _TXT_INFO_DATA
  • CiraRequest : AMT_DXE_CONFIG
  • CiraTimeout : AMT_DXE_CONFIG
  • CleanMemory : MEMORY_CONFIG_NO_CRC
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClkReqMsgEnable : CPU_PCIE_RP_PREMEM_CONFIG
  • ClkReqMsgEnableRp : CPU_PCIE_RP_PREMEM_CONFIG
  • CLKTCO : MEMORY_CONFIGURATION
  • ClockGating : PCH_DMI_CONFIG
  • CloseSession : _ME_JHI_PROTOCOL
  • ClsUserInfo : INVOCATION_CODE_BITS
  • Cm : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CMDDRUD : MEMORY_CONFIGURATION
  • CMDDSEQ : MEMORY_CONFIGURATION
  • CmdMirror : MEMORY_CONFIGURATION
  • CmdRanksTerminated : MEMORY_CONFIGURATION
  • CMDSR : MEMORY_CONFIGURATION
  • CMDVC : MEMORY_CONFIGURATION
  • CmGen3 : CPU_DMI_HOB , PCH_DMI_HOB
  • CmGen4 : CPU_DMI_HOB , PCH_DMI_HOB
  • CodecSxWakeCapability : HDAUDIO_CONFIG
  • Command : _PCODE_MAILBOX_INTERFACE , ASF_MESSAGE_HEADER , GET_BOOT_OPTIONS_RESPONSE , HECI_ASF_PUSH_PROGRESS_CODE , HWA_MESSAGE_HEADER
  • CommandCompletion : _OC_MAILBOX_INTERFACE
  • ComplianceTest : CPU_PCIE_HOB
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComponentName : FWSTS_SET_RECORD
  • ComputeDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ComputeDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ConfigTdpBios : CPU_POWER_MGMT_CUSTOM_CONFIG
  • ConfigTdpLevel : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_TEST_CONFIG
  • ConfigTdpLock : CPU_POWER_MGMT_CUSTOM_CONFIG
  • Controller : ISH_I3C_CONFIG , SA_ADDRESS_DECODE
  • ControllerConfig : ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
  • CopyMem : SA_FUNCTION_CALLS
  • CoreBiosDoneEnabled : ME_DXE_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Count : FWSTS_SMBIOS_RECORD
  • Cp : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CpGen3 : CPU_DMI_HOB , PCH_DMI_HOB
  • CpGen4 : CPU_DMI_HOB , PCH_DMI_HOB
  • CpuAttachedStorage : RST_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCommonFeatures : _CPU_INFO_PROTOCOL
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • CpuDebugDisabled : HECI_FW_STS6_REGISTER
  • Cpuid : PPM_CUSTOM_RATIO_TABLE
  • CpuInfo : _CPU_INFO_PROTOCOL
  • CpuMailboxRead : SA_FUNCTION_CALLS
  • CpuMailboxWrite : SA_FUNCTION_CALLS
  • CpuPcie0Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie1Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie2Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie3Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcieRtd3 : PCIE_DXE_CONFIG
  • CpuRatio : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CpuReplacedSts : HECI_GS_SHDW_REGISTER
  • CpuReplacedValid : HECI_GS_SHDW_REGISTER
  • CpuReplacement : INVOCATION_CODE_BITS
  • CpuReplacementTimeout : AMT_DXE_CONFIG
  • CpuSignature : CPU_INFO
  • CrashLogEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CrashLogGprs : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CreateSession : _ME_JHI_PROTOCOL
  • Crid : PCH_GENERAL_CONFIG
  • CridEnable : SA_MISC_PEI_PREMEM_CONFIG
  • CridOrgRid : PCH_INFO_HOB
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CseToDisabled : HECI_GS_SHDW_REGISTER
  • CsiSpeed : IPU_PREMEM_CONFIG
  • CsmFlag : SI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CstateLatencyControl0Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CStatePreWake : CPU_POWER_MGMT_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : CPU_POWER_MGMT_TEST_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CurrentPowerSource : HECI_FWS_REGISTER
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • CurrentState : HECI_FWS_REGISTER
  • CustomConfigTdpTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CustomRatioTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • CwbEnable : PCH_DMI_CONFIG
  • Cx : CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- d -

  • D0i3SupportValid : HECI_FWS_REGISTER
  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • D3SupportValid : HECI_FWS_REGISTER
  • DAL : MEFWCAPS_SKU
  • Data : _OC_MAILBOX_FULL , _PCODE_MAILBOX_FULL , _TXT_INFO_HOB , ASF_PROFILE_MESSAGE_HEADER , SET_FILE , SET_FILE_EX
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DataRate : HOB_SAGV_TIMING_OUT
  • DataSectionSize : BGUP_HEADER
  • DataSyncConfirmation : INVOCATION_CODE_BITS
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DCC : MEMORY_CONFIGURATION
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciModphyPg : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • DdiConfiguration : GRAPHICS_PEI_PREMEM_CONFIG
  • DdiPort1Ddc : DDI_CONFIGURATION
  • DdiPort1Hpd : DDI_CONFIGURATION
  • DdiPort2Ddc : DDI_CONFIGURATION
  • DdiPort2Hpd : DDI_CONFIGURATION
  • DdiPort3Ddc : DDI_CONFIGURATION
  • DdiPort3Hpd : DDI_CONFIGURATION
  • DdiPort4Ddc : DDI_CONFIGURATION
  • DdiPort4Hpd : DDI_CONFIGURATION
  • DdiPortADdc : DDI_CONFIGURATION
  • DdiPortAHpd : DDI_CONFIGURATION
  • DdiPortBConfig : DDI_CONFIGURATION
  • DdiPortBDdc : DDI_CONFIGURATION
  • DdiPortBHpd : DDI_CONFIGURATION
  • DdiPortCDdc : DDI_CONFIGURATION
  • DdiPortCHpd : DDI_CONFIGURATION
  • Ddr4DdpSharedClock : MEMORY_CONFIGURATION
  • Ddr4OneDpc : MEMORY_CONFIGURATION
  • ddrFreq : MEMORY_INFO_DATA
  • DdrFreqLimit : MEMORY_CONFIGURATION
  • ddrFreqMax : MEMORY_INFO_DATA
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DdrType : MEMORY_INFO_DATA
  • DebugHook : SA_FUNCTION_CALLS
  • DebugInterfaceEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugPrint : SA_FUNCTION_CALLS
  • DebugValue : MEMORY_CONFIGURATION
  • DeepstTcState : TCSS_DATA
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DekelFwVersionMajor : CPU_PCIE_HOB
  • DekelFwVersionMinor : CPU_PCIE_HOB
  • DekelSquelchWa : CPU_PCIE_RP_PREMEM_CONFIG
  • DeltaT12PowerCycleDelay : GRAPHICS_PEI_PREMEM_CONFIG
  • Desc : CACHE_DESCRIPTOR_INFO
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : HOST_BRIDGE_PEI_CONFIG
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DeviceStatus : _THC_PROTOCOL
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DfdRestoreEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • DgrEnable : DXE_CPU_POLICY_PROTOCOL
  • DgrSkipOemExceptionHandler : DXE_CPU_POLICY_PROTOCOL
  • DgrSpaEnable : DXE_CPU_POLICY_PROTOCOL
  • DgrStateSaveProtect : DXE_CPU_POLICY_PROTOCOL
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Dimm : SA_ADDRESS_DECODE
  • DimmCapacity : DIMM_INFO
  • DIMMDFE : MEMORY_CONFIGURATION
  • DIMMODTCA : MEMORY_CONFIGURATION
  • DIMMODTT : MEMORY_CONFIGURATION
  • DIMMRONT : MEMORY_CONFIGURATION
  • dimmSize : MEMORY_INFO_DATA
  • DimmsSpdData : MEMORY_INFO_DATA
  • DimmStatus : MEMORY_INFO_DATA
  • Direction : GPIO_CONFIG
  • Disable : _WDT_PROTOCOL
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableChannel : MEMORY_CONFIGURATION
  • DisableClkReqMsg : CPU_PCIE_HOB
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerAtomMask : OVERCLOCKING_PREMEM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisableProcHotOut : CPU_POWER_MGMT_TEST_CONFIG
  • DisableTurboGt : GRAPHICS_PEI_CONFIG
  • DisableVrThermalAlert : CPU_POWER_MGMT_TEST_CONFIG
  • DisconnectAllTpms : BOOT_GUARD_INFO
  • DismSize : GRAPHICS_PEI_PREMEM_CONFIG
  • DisPgCloseIdleTimeout : MEMORY_CONFIGURATION
  • DisplayAudioLink : GRAPHICS_PEI_PREMEM_CONFIG
  • DisplayFusaConfigEnable : FUSA_CONFIG
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DivU64x64 : SA_FUNCTION_CALLS
  • DlvrBypassModeEnable : OVERCLOCKING_PREMEM_CONFIG
  • DlvrRfiEnable : CPU_POWER_MGMT_VR_CONFIG
  • DlvrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • DlvrSpreadSpectrumPercentage : CPU_POWER_MGMT_VR_CONFIG
  • DmaBufferSize : VTD_CONFIG
  • DmaControlGuarantee : VTD_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspm : PCIE_PEI_CONFIG
  • DmiAspmCtrl : CPU_DMI_PREMEM_CONFIG , PCH_DMI_CONFIG
  • DmiAspmL1ExitLatency : CPU_DMI_PREMEM_CONFIG
  • DmiBar : HOST_BRIDGE_PREMEM_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiCdrRelock : CPU_DMI_PREMEM_CONFIG
  • DmiDeEmphasis : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiExtSync : PCIE_PEI_CONFIG
  • DmiGen3DsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3EndPointHint : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EndPointPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EqPh2Enable : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EqPh3Method : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3ProgramStaticEq : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3RootPortPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RxCtlePeaking : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3UsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiHaAWC : THERMAL_CONFIG
  • DmiIot : PCIE_PEI_CONFIG
  • DmiMaxLinkSpeed : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiNewFom : CPU_DMI_PREMEM_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmVal : PCH_SATA_PORT_CONFIG
  • Done : MG_IMR_STATUS , TBT_IMR_STATUS
  • DownSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • DpcEnabled : TCSS_PCIE_PORT_POLICY
  • DpInExternalEn : DPIN_PREMEM_CONFIG
  • DpInPortConnectMap : DPIN_PREMEM_CONFIG
  • DqDqsMap : MEMORY_CONFIG_NO_CRC
  • DqMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DqPinsInterleaved : MEMORY_CONFIGURATION
  • DqsMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DRAMDCA : MEMORY_CONFIGURATION
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • dTpm12Deactivated : HECI_FW_STS4_REGISTER
  • DualTauBoost : CPU_POWER_MGMT_BASIC_CONFIG
  • DynamicMemoryBoost : MEMORY_CONFIGURATION
  • DynamicMemoryBoostTrainingFailed : MEMORY_INFO_DATA
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- e -

  • EccDftEn : MEMORY_CONFIGURATION
  • EccErrInjAddress : MEMORY_CONFIGURATION
  • EccErrInjCount : MEMORY_CONFIGURATION
  • EccErrInjMask : MEMORY_CONFIGURATION
  • EcCmd : BGPDT
  • EcCmdClose : BGPDT
  • EcCmdGetSvn : BGPDT
  • EcCmdLock : BIOS_GUARD_CONFIG
  • EcCmdOpen : BGPDT
  • EcCmdPortTest : BGPDT
  • EcCmdProvisionEav : BIOS_GUARD_CONFIG
  • EccSupport : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • EcData : BGPDT
  • EcSvn : BGUP_HEADER
  • ECT : MEMORY_CONFIGURATION
  • EdramBar : HOST_BRIDGE_PREMEM_CONFIG
  • EdramTestMode : HOST_BRIDGE_PEI_CONFIG
  • EfiHobGuidType : _TXT_INFO_HOB , AMT_PET_QUEUE_HOB , BIOSGUARD_HOB , CPU_DMI_HOB , CPU_PCIE_HOB , IPU_DATA_HOB , PCH_DMI_HOB , SA_DATA_HOB , SA_PEG_HOB , TCSS_DATA_HOB , TCSS_DATA_SSID_HOB
  • EightCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Eist : CPU_POWER_MGMT_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_MEMORY_THROTTLING , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , TSN_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableAbove4GBMmio : HOST_BRIDGE_PREMEM_CONFIG
  • EnableAllThermalFunctions : CPU_POWER_MGMT_TEST_CONFIG
  • EnableC6Dram : CPU_SECURITY_PREMEM_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnableDmaBuffer : VTD_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableEpbPeciOverride : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableFastMsrHwpReq : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoEppGrouping : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoPerCorePstate : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbm : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbmDriver : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableMinVoltageOverride : CPU_POWER_MGMT_VR_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePerCorePState : CPU_POWER_MGMT_BASIC_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnablePwrDn : MEMORY_CONFIGURATION
  • EnablePwrDnLpddr : MEMORY_CONFIGURATION
  • EnableSgx : CPU_SECURITY_PREMEM_CONFIG
  • EnableTcssCovTypeA : TCSS_MISC_PEI_CONFIG
  • EnableVsysCritical : CPU_POWER_MGMT_VR_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EnCmdRate : MEMORY_CONFIGURATION
  • End : SPD_OFFSET_TABLE
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EndPointVendorIdDeviceId : SA_PEG_DATA
  • EnergyEfficientPState : CPU_POWER_MGMT_TEST_CONFIG
  • EnergyEfficientTurbo : CPU_POWER_MGMT_TEST_CONFIG
  • ENF : HECI_FW_STS6_REGISTER
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancedInterleave : MEMORY_CONFIGURATION
  • EnhancePort8xhDecoding : PCH_LPC_PREMEM_CONFIG
  • Entity : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EntityInstance : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EpBar : HOST_BRIDGE_PREMEM_CONFIG
  • EpgEnable : MEMORY_CONFIGURATION
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3LaneParam : CPU_PCIE_CONFIG
  • Erase : _BIOSGUARD_PROTOCOL
  • ERDMPRTC2D : MEMORY_CONFIGURATION
  • ERDTC2D : MEMORY_CONFIGURATION
  • Error : HECI_FW_STS6_REGISTER
  • ErrorCode : HECI_FWS_REGISTER , MG_IMR_STATUS , TBT_IMR_STATUS
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • ESC : HECI_FW_STS5_REGISTER
  • EspiPmHAE : PCH_ESPI_CONFIG
  • EspiSlaveSmiRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • Etvb : OVERCLOCKING_PREMEM_CONFIG
  • EventData : ASF_START_WDT , HECI_ASF_PUSH_PROGRESS_CODE
  • EventData1 : ASF_MESSAGE , PET_ALERT
  • EventData2 : ASF_MESSAGE , PET_ALERT
  • EventData3 : PET_ALERT
  • EventData4 : PET_ALERT
  • EventData5 : PET_ALERT
  • EventOffset : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSensorType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSeverity : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSourceType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EWRTC2D : MEMORY_CONFIGURATION
  • ExecLim : BGPDT
  • Execute : _BIOSGUARD_PROTOCOL
  • ExeStatus : HECI_FW_STS6_REGISTER
  • ExitOnFailure : MEMORY_CONFIGURATION
  • ExpanderNo : CPU_PCIE_GPIO_INFO , PCIE_GPIO
  • ExtData : _BIOS_OS_DATA_REGION
  • ExtendedBankHashing : MEMORY_CONFIGURATION
  • ExtendedBiosDecodeRangeBase : SPI_CONFIG
  • ExtendedBiosDecodeRangeEnable : SPI_CONFIG
  • ExtendedBiosDecodeRangeLimit : SPI_CONFIG
  • ExtendedData : SMBIOS_TABLE_TYPE130
  • ExtendMeMeasuredBoot : ME_DXE_CONFIG
  • External : PCH_SATA_PORT_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO
  • ExtStatCode1 : HECI_GS_SHDW_REGISTER
  • ExtStatCode2 : HECI_GS_SHDW_REGISTER
  • ExtSync : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG
  • ExtTemperatureSupport : MEMORY_CONFIGURATION
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- f -

  • FastPkgCRampDisable : CPU_POWER_MGMT_VR_CONFIG
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FClkFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Features : CPU_INFO
  • FiaProgramming : CPU_PCIE_CONFIG
  • Fields : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • FirstByte : SFAM_DATA
  • FirstDimmBitMask : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstDimmBitMaskEcc : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstMebxBoot : INVOCATION_CODE_BITS
  • FiveCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FivrDynPm : PCH_FIVR_CONFIG
  • FivrEfficiency : OVERCLOCKING_PREMEM_CONFIG
  • FivrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpectrumEnable : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpreadSpectrum : CPU_POWER_MGMT_VR_CONFIG
  • Flags : _BIOS_OS_DATA_REGION , _TXT_INFO_DATA , MBP_ITEM_HEADER , THC_HID_OVER_SPI
  • FlashErase : _PCH_SPI_PROTOCOL
  • FlashErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • FlashErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • FlashRead : _PCH_SPI_PROTOCOL
  • FlashReadJedecId : _PCH_SPI_PROTOCOL
  • FlashReadSfdp : _PCH_SPI_PROTOCOL
  • FlashReadStatus : _PCH_SPI_PROTOCOL
  • FlashWrite : _PCH_SPI_PROTOCOL
  • FlashWriteStatus : _PCH_SPI_PROTOCOL
  • FllOcModeEn : OVERCLOCKING_PREMEM_CONFIG
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • FomsCp : CPU_PCIE_ROOT_PORT_CONFIG
  • Force1Dpc : MEMORY_CONFIGURATION
  • ForceBootPolicy : HECI_FW_STS6_REGISTER
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForcePowerFlow : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • ForceSingleRank : MEMORY_CONFIGURATION
  • ForceSingleSubchannel : MEMORY_CONFIGURATION
  • ForcMebxSyncUp : AMT_PEI_CONFIG
  • FourCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FpfDisable : HECI_FW_STS6_REGISTER
  • FpfSocConfigLock : HECI_FW_STS6_REGISTER
  • FptBad : HECI_FWS_REGISTER
  • FreqLimitMixedConfig : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_2R2R : MEMORY_CONFIGURATION
  • Frequency : THC_HID_OVER_SPI
  • FtBupLdFlr : HECI_FWS_REGISTER
  • FullMng : MEFWCAPS_SKU
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FusaConfigEnable : FUSA_CONFIG
  • FusaRunPeriodicScanBist : FUSA_CONFIG
  • FusaRunStartupArrayBist : FUSA_CONFIG
  • FusaRunStartupScanBist : FUSA_CONFIG
  • FwInEnfFlow : HECI_FW_STS4_REGISTER
  • FwInitComplete : HECI_FWS_REGISTER
  • FwNeedsWarmResetFlag : ICC_MESSAGE_RESP_DATA
  • FwProgress : AMT_PEI_CONFIG
  • FwSku : HECI_FW_STS3_REGISTER
  • FwUnconfiguration : INVOCATION_CODE_BITS
  • FwUpdate : INVOCATION_CODE_BITS
  • FwUpdateInprogress : HECI_FWS_REGISTER
  • FwUpdForcedSB : HECI_GS_SHDW_REGISTER
  • FwUpdIpu : HECI_GS_SHDW_REGISTER
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- g -

  • GdxcBar : HOST_BRIDGE_PREMEM_CONFIG
  • GearRatio : MEMORY_CONFIGURATION
  • Gen3Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen3SwEqAlwaysAttempt : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqEnableVocTest : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqJitterDwellTime : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqJitterErrorTarget : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqNumberOfPresets : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqVocDwellTime : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqVocErrorTarget : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4EqPh3Method : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • GetAppletProperty : _ME_JHI_PROTOCOL
  • GetBankLocatorString : _MEMORY_DXE_CONFIG
  • GetControllerName : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetCpuTime : SA_FUNCTION_CALLS
  • GetDeviceLocatorString : _MEMORY_DXE_CONFIG
  • GetDriverName : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetDriverVersion : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetHeciInterruptMode : _HECI_ACCESS_
  • GetHeciPch : _HECI_ACCESS_
  • GetMeMode : _HECI_PPI , _HECI_PROTOCOL
  • GetMemoryVdd : SA_FUNCTION_CALLS
  • GetMeStatus : _HECI_PPI , _HECI_PROTOCOL
  • GetNextHeciAccess : _HECI_ACCESS_
  • GetPciDeviceAddress : SA_FUNCTION_CALLS
  • GetPcieDeviceAddress : SA_FUNCTION_CALLS
  • GetPlatformDockStatus : GOP_POLICY_PROTOCOL
  • GetPlatformLidStatus : GOP_POLICY_PROTOCOL
  • GetRandomNumber : SA_FUNCTION_CALLS
  • GetRegionAddress : _PCH_SPI_PROTOCOL
  • GetRtcCmos : SA_FUNCTION_CALLS
  • GetRtcTime : SA_FUNCTION_CALLS
  • GetSessionInfo : _ME_JHI_PROTOCOL
  • GetSessionsCount : _ME_JHI_PROTOCOL
  • GetSpdData : SA_FUNCTION_CALLS
  • GetVbtData : GOP_POLICY_PROTOCOL
  • GetVersionInfo : _ME_JHI_PROTOCOL
  • GfxTurboIMON : GRAPHICS_DXE_CONFIG
  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GlobalSmi : PCH_LOCK_DOWN_CONFIG
  • GmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GmAdr64 : GRAPHICS_PEI_PREMEM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GopOverrideGuid : GOP_POLICY_PROTOCOL
  • GopVersion : GRAPHICS_DXE_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioNo : CPU_PCIE_GPIO_INFO , PCIE_GPIO
  • GpioOverride : PCH_GENERAL_PREMEM_CONFIG
  • GpioPad : SA_GPIO_INFO_PCIE
  • GpioPullN : IOM_AUX_ORI_PAD_CONFIG
  • GpioPullP : IOM_AUX_ORI_PAD_CONFIG
  • GpioSupport : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO , PEG_GPIO_DATA
  • GraphicFusaConfigEnable : FUSA_CONFIG
  • GraphicsConfigPtr : GRAPHICS_PEI_CONFIG
  • GtCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • GtClosEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • GtExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtFreqMax : GRAPHICS_PEI_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtPsmiSupport : GRAPHICS_PEI_PREMEM_CONFIG
  • GttMmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GttSize : GRAPHICS_PEI_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- h -

  • HaltAllowed : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdAudioLinkFrequency : HDAUDIO_CONFIG
  • HdcControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , _DXE_ITBT_CONFIG , _HEAP_BIOS_SPEC_VER_ELEMENT , _HEAP_BIOSACM_ELEMENT , _MEMORY_DXE_CONFIG , _PEI_ITBT_CONFIG , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , BIOS_GUARD_CONFIG , CNVI_CONFIG , CNVI_PREMEM_CONFIG , CPU_CONFIG , CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_CONFIG , CPU_PCIE_RP_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , CPU_TRACE_HUB_PREMEM_CONFIG , CPU_TXT_PREMEM_CONFIG , DPIN_PREMEM_CONFIG , FUSA_CONFIG , GBE_CONFIG , GNA_CONFIG , GPIO_DXE_CONFIG , GRAPHICS_DXE_CONFIG , GRAPHICS_PEI_CONFIG , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , HOST_BRIDGE_PEI_CONFIG , HOST_BRIDGE_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , HYBRID_STORAGE_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_DXE_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , MEMORY_CONFIG_NO_CRC , MEMORY_CONFIGURATION , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_ESPI_CONFIG , PCH_FIVR_CONFIG , PCH_FLASH_PROTECTION_CONFIG , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_HSIO_CONFIG , PCH_HSIO_PCIE_PREMEM_CONFIG , PCH_HSIO_PREMEM_CONFIG , PCH_HSIO_SATA_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_LPC_PREMEM_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_DXE_CONFIG , PCIE_PEI_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , PSF_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , SPI_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TSN_CONFIG , USB2_PHY_CONFIG , USB3_HSIO_CONFIG , USB_CONFIG , VMD_PEI_CONFIG , VTD_CONFIG , VTD_DXE_CONFIG
  • Health : BIST_HOB_DATA
  • Heci1BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci2BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3Enabled : ME_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFirmwareStatus : _HECI_CONTROL_
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciListCh : HECI_GS_SHDW_REGISTER
  • HeciReceive : _HECI_CONTROL_
  • HeciReset : _HECI_CONTROL_
  • HeciSend : _HECI_CONTROL_
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HgDelayAfterHoldReset : HYBRID_GRAPHICS_CONFIG
  • HgDelayAfterPwrEn : HYBRID_GRAPHICS_CONFIG
  • HgMode : HYBRID_GRAPHICS_CONFIG
  • HgSubSystemId : HYBRID_GRAPHICS_CONFIG
  • HgSupport : HYBRID_GRAPHICS_CONFIG
  • HideGpioAcpiDevice : GPIO_DXE_CONFIG
  • HideUnConfigureMeConfirm : AMT_DXE_CONFIG
  • HidOverSpi : THC_PORT
  • HobBufferSize : MEMORY_CONFIGURATION
  • HoldRst : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • HorizontalResolution : GRAPHICS_PEI_CONFIG
  • HostC10ReportEnable : PCH_ESPI_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HotPlugRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • HpetBusNum : PCH_INFO_HOB
  • HsiiEnable : USB_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioRxGen1EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen1EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxSetCtle : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioRxSetCtleEnable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxGen1DeEmph : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DeEmphEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph3p5 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph3p5Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE
  • HsPhyFwBuild : CPU_PCIE_HOB
  • HsPhyFwEvBitProgMajor : CPU_PCIE_HOB
  • HsPhyFwEvBitProgMinor : CPU_PCIE_HOB
  • HsPhyFwHotFix : CPU_PCIE_HOB
  • HsPhyFwProdMajor : CPU_PCIE_HOB
  • HsPhyFwProdMinor : CPU_PCIE_HOB
  • HsPhyMap : CPU_PCIE_HOB
  • HsPhyRecipeVersionMajor : CPU_PCIE_HOB
  • HsPhyRecipeVersionMinor : CPU_PCIE_HOB
  • Hsti : DXE_SI_POLICY_PROTOCOL
  • HstiSize : DXE_SI_POLICY_PROTOCOL
  • HwEqGen3CoeffList : PCIE_COMMON_CONFIG
  • HwEqGen4CoeffList : CPU_PCIE_CONFIG
  • Hwp : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpInterruptControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpLock : CPU_POWER_MGMT_BASIC_CONFIG
  • HybridStorageMode : HYBRID_STORAGE_CONFIG
  • HyperThreading : CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • IaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IanaId : ASF_BOOT_OPTIONS
  • IaSirpEnable : OVERCLOCKING_PREMEM_CONFIG
  • Ibecc : MEMORY_CONFIGURATION
  • IbeccErrInjAddress : MEMORY_CONFIGURATION
  • IbeccErrInjControl : MEMORY_CONFIGURATION
  • IbeccErrInjCount : MEMORY_CONFIGURATION
  • IbeccErrInjMask : MEMORY_CONFIGURATION
  • IbeccOperationMode : MEMORY_CONFIGURATION
  • IbeccProtectedRangeBase : MEMORY_CONFIGURATION
  • IbeccProtectedRangeEnable : MEMORY_CONFIGURATION
  • IbeccProtectedRangeMask : MEMORY_CONFIGURATION
  • IccLimit : CPU_POWER_MGMT_VR_CONFIG
  • IccMax : CPU_POWER_MGMT_VR_CONFIG , FIVR_EXT_RAIL_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • IccProgSts : HECI_GS_SHDW_REGISTER
  • Idd3n : MEMORY_CONFIGURATION
  • Idd3p : MEMORY_CONFIGURATION
  • IderStateChange : INVOCATION_CODE_BITS
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • IedSize : SA_MISC_PEI_PREMEM_CONFIG
  • IgdBlcConfig : GRAPHICS_DXE_CONFIG
  • IgdBootType : GRAPHICS_DXE_CONFIG
  • IgdDvmt50PreAlloc : GRAPHICS_PEI_PREMEM_CONFIG
  • IgdDvmtMemSize : GRAPHICS_DXE_CONFIG
  • IgdPanelScaling : GRAPHICS_DXE_CONFIG
  • IgdPanelType : GRAPHICS_DXE_CONFIG
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • ImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InfDfxPwrEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • InfPhaseCode : HECI_GS_SHDW_REGISTER
  • InitHeci : _HECI_PROTOCOL
  • Initialize : _ME_JHI_PROTOCOL
  • InitializeHeci : _HECI_PPI
  • InitPcieAspmAfterOprom : CPU_PCIE_HOB , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , SA_PEG_HOB
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • InstallContent : _ME_JHI_PROTOCOL
  • InstalledSize : SMBIOS_CACHE_INFO
  • InstalledSize2 : SMBIOS_CACHE_INFO
  • InstallFile : _ME_JHI_PROTOCOL
  • Instance : FSP_ERROR_INFO_HOB
  • IntegratedTouch : MEFWCAPS_SKU
  • IntelAmtEnabled : ME_CAP
  • IntelAmtFw : ME_CAP
  • IntelAmtFwStandard : ME_CAP
  • IntelCLS : MEFWCAPS_SKU
  • IntelKVM : ME_CAP
  • IntelKVMEnabled : ME_CAP
  • IntEnable : HECI_CONTROL_STATUS_REGISTER
  • IntendedFreq : CPU_INFO
  • Interface : _OC_MAILBOX_FULL , _PCODE_MAILBOX_FULL
  • InterfaceData : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InternalGraphics : GRAPHICS_PEI_PREMEM_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntGenerate : HECI_CONTROL_STATUS_REGISTER
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntruderDetRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • IntStatus : HECI_CONTROL_STATUS_REGISTER
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • InvokeEDebugMode : HECI_FWS_REGISTER
  • InvokeMEBx : HECI_GS_SHDW_REGISTER
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IoeDebugEn : PCH_GENERAL_PREMEM_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomBeforeEnteringTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomFwEngrVersion : TCSS_DATA
  • IomFwVersion : TCSS_DATA
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IOMReady : TCSS_DATA
  • IomStayInTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IopFusaConfigEnable : FUSA_CONFIG
  • IopFusaMcaCheckEnable : FUSA_CONFIG
  • IoRead16 : SA_FUNCTION_CALLS
  • IoRead32 : SA_FUNCTION_CALLS
  • IoRead8 : SA_FUNCTION_CALLS
  • IotgPllSscEn : PCH_GENERAL_PREMEM_CONFIG
  • IoWrite16 : SA_FUNCTION_CALLS
  • IoWrite32 : SA_FUNCTION_CALLS
  • IoWrite8 : SA_FUNCTION_CALLS
  • IpTiming : HOB_SAGV_TIMING_OUT
  • IpuEnable : IPU_PREMEM_CONFIG
  • IpuImrConfiguration : IPU_PREMEM_CONFIG
  • IpuSupport : IPU_DATA_HOB
  • IPV6 : MEFWCAPS_SKU
  • Irms : CPU_POWER_MGMT_VR_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • IsDMBRunning : MEMORY_INFO_DATA
  • ISH : MEFWCAPS_SKU
  • IsWdtEnabled : _WDT_PROTOCOL
  • IsWdtRequired : _WDT_PROTOCOL
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ItbtDmaEn : TCSS_DATA
  • ITbtDmaLtr : _PEI_ITBT_CONFIG
  • ItbtForcePower : TCSS_DATA
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtGenericConfig : _DXE_ITBT_CONFIG , _PEI_ITBT_CONFIG
  • ItbtPcieFuncMap : TCSS_DATA
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ItbtPcieRpEn : TCSS_DATA
  • ItbtPcieSegMap : TCSS_DATA
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG
  • ITbtResourceConfig : _DXE_ITBT_CONFIG
  • ITbtRootPortConfig : _PEI_ITBT_CONFIG
  • ITbtRtd3 : _DXE_ITBT_GENERIC_CONFIG
  • ITbtRtd3ExitDelay : _DXE_ITBT_GENERIC_CONFIG
  • ITbtSecurityLevel : _ITBT_GENERIC_CONFIG
  • ITbtVproDockSupport : _DXE_ITBT_GENERIC_CONFIG
  • ItbtXdciEn : TCSS_DATA
  • ItbtXhciEn : TCSS_DATA
  • ItdThrottleEnable : OVERCLOCKING_PREMEM_CONFIG
  • ItemId : MBP_ITEM_HEADER
  • IuerStatusVal : GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- j -

  • JedecTiming : HOB_SAGV_TIMING_OUT
  • JtagC10PowerGateDisable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • JWRL : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KmId : HECI_FW_STS6_REGISTER
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG
  • KVM : MEFWCAPS_SKU
  • KvmEnabled : SMBIOS_TABLE_TYPE130
  • KvmStateChange : INVOCATION_CODE_BITS
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubStates : CPU_PCIE_HOB
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • Lane : PCH_HSIO_PCIE_PREMEM_CONFIG
  • LaneUsed : IPU_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LastByte : SFAM_DATA
  • LastPage : BIOSGUARD_LOG
  • LastSfam : BGPDT
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LcpPdBase : _BIOS_OS_DATA_REGION
  • LcpPdSize : _BIOS_OS_DATA_REGION
  • LCT : MEMORY_CONFIGURATION
  • LctCmdEyeWidth : MEMORY_CONFIGURATION
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LeftShift64 : SA_FUNCTION_CALLS
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : MBP_ITEM_HEADER
  • Level : CACHE_DESCRIPTOR_INFO
  • Lfsr0Mask : MEMORY_CONFIGURATION
  • Lfsr1Mask : MEMORY_CONFIGURATION
  • LgmrEnable : PCH_ESPI_CONFIG
  • LimitPacketSize : THC_PORT
  • LinkActiveRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • LinkDownGpios : CPU_PCIE_RP_PREMEM_CONFIG
  • LinkEqRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • LnkErrType1Register : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • LocalTransmitterOverrideEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LocalWakeupTimer : ME_CAP
  • LockBoxData : SMRAM_CPU_INFO
  • LockBoxSize : SMRAM_CPU_INFO
  • LockConfig : GPIO_CONFIG
  • LockLinkConfiguration : PCH_ESPI_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LoggingOptions : BIOSGUARD_LOG
  • LogoPixelHeight : GRAPHICS_PEI_CONFIG
  • LogoPixelWidth : GRAPHICS_PEI_CONFIG
  • LogoPtr : GRAPHICS_PEI_CONFIG
  • LogoSize : GRAPHICS_PEI_CONFIG
  • LowPowerState : HECI_GS_SHDW_REGISTER
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • Lp5BankMode : MEMORY_CONFIGURATION
  • Lp5CccConfig : MEMORY_CONFIGURATION
  • LpcBiosWpRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • LpcPmHAE : PCH_LPC_PREMEM_CONFIG
  • LpddrRttCa : MEMORY_CONFIGURATION
  • LpddrRttWr : MEMORY_CONFIGURATION
  • LpDqsOscEn : MEMORY_CONFIGURATION
  • LpMode : MEMORY_CONFIGURATION
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : CPU_PCIE_PWR_OPT , GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrHighIdleTimeOverride : USB_CONFIG
  • LtrLowIdleTimeOverride : USB_CONFIG
  • LtrMaxNoSnoopLatency : CPU_PCIE_PWR_OPT , TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : CPU_PCIE_PWR_OPT , TCSS_PCIE_PORT_POLICY
  • LtrMediumIdleTimeOverride : USB_CONFIG
  • LtrOverrideEnable : USB_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- m -

  • MachineCheckEnable : CPU_TEST_CONFIG
  • ManageabilityMode : AMT_PEI_CONFIG
  • ManufacturingLock : HECI_FW_STS6_REGISTER
  • MappingPchXhciUsbA : TCSS_MISC_PEI_CONFIG
  • MarginLimitCheck : MEMORY_CONFIGURATION
  • MarginLimitL2 : MEMORY_CONFIGURATION
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaxCacheSupported : CPU_INFO
  • MaximumCacheSize2 : SMBIOS_CACHE_INFO
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • MaxRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MaxRttWr : MEMORY_CONFIGURATION
  • MaxSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • MaxTurbo1Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo2Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo3Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo4Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo5Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo6Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo7Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo8Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MbpSize : MBP_HEADER
  • MchBar : HOST_BRIDGE_PREMEM_CONFIG
  • MchRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • McRefresh2X : MEMORY_CONFIGURATION
  • McRefreshRate : MEMORY_CONFIGURATION
  • McSmiRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MdSocket : DIMM_INFO
  • MeasuredBoot : BOOT_GUARD_INFO
  • MeasuredBootPolicy : HECI_FW_STS6_REGISTER
  • MeBootOptionsPresent : HECI_FWS_REGISTER
  • MeBuildNo : ME_CAP
  • MebxDebugMsg : AMT_DXE_CONFIG
  • MebxGraphicsMode : AMT_DXE_CONFIG
  • MebxNonUiTextMode : AMT_DXE_CONFIG
  • MebxUiTextMode : AMT_DXE_CONFIG
  • MebxVersion : SMBIOS_TABLE_TYPE131
  • MeEnabled : ME_CAP
  • MeFwDownGrade : ME_DXE_CONFIG
  • MeHotFixNo : ME_CAP
  • MeJhiSupport : ME_DXE_CONFIG
  • MeMajorVer : ME_CAP
  • MemInfoData : MEM_INFO_PROTOCOL
  • MeMinorVer : ME_CAP
  • MemoryLock : RTC_CONFIG
  • MemorySpeedReducedWrongDimmSlot : MEMORY_INFO_DATA
  • MemoryThrottling : THERMAL_CONFIG
  • MemReg0Size : TRACE_HUB_CONFIG
  • memSize : MEMORY_INFO_DATA
  • MemTestOnWarmBoot : MEMORY_CONFIG_NO_CRC
  • MEMTST : MEMORY_CONFIGURATION
  • MeOperationMode : HECI_FWS_REGISTER
  • MeOperationState : HECI_FWS_REGISTER
  • MePowerGating : HECI_GS_SHDW_REGISTER
  • MeReportError : ME_DXE_CONFIG
  • MeResetWait : _HECI_PROTOCOL
  • MeRstCnt : HECI_FWS_REGISTER
  • Message : ASF_FRAMEWORK_MESSAGE
  • MessageType : ASF_DATA_HUB_MAP , ASF_FRAMEWORK_MESSAGE
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MfsFailure : HECI_GS_SHDW_REGISTER
  • MgFwVersion : MG_IMR_STATUS
  • MgImrStatus : TCSS_DATA
  • MicrocodePatchAddress : CPU_CONFIG
  • MinRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MinVoltageC8 : CPU_POWER_MGMT_VR_CONFIG
  • MinVoltageRuntime : CPU_POWER_MGMT_VR_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MlcSpatialPrefetcher : CPU_TEST_CONFIG
  • MlcStreamerPrefetcher : CPU_TEST_CONFIG
  • MmioRead16 : SA_FUNCTION_CALLS
  • MmioRead32 : SA_FUNCTION_CALLS
  • MmioRead64 : SA_FUNCTION_CALLS
  • MmioRead8 : SA_FUNCTION_CALLS
  • MmioSize : HOST_BRIDGE_PREMEM_CONFIG
  • MmioSizeAdjustment : HOST_BRIDGE_PREMEM_CONFIG
  • MmioWrite16 : SA_FUNCTION_CALLS
  • MmioWrite32 : SA_FUNCTION_CALLS
  • MmioWrite64 : SA_FUNCTION_CALLS
  • MmioWrite8 : SA_FUNCTION_CALLS
  • MobilePlatform : MEMORY_CONFIGURATION
  • Mode : CNVI_CONFIG , IEH_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • Module0Lockstep : FUSA_CONFIG
  • Module1Lockstep : FUSA_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : CPU_TEST_CONFIG
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcCall : MEMORY_CONFIG_NO_CRC
  • MrcChangeMargin : SA_MEMORY_FUNCTIONS
  • MrcChannelExist : SA_MEMORY_FUNCTIONS
  • MrcDelayNs : SA_FUNCTION_CALLS
  • MrcDramReset : SA_FUNCTION_CALLS
  • MrcFastBoot : _MEMORY_DXE_CONFIG , MEMORY_CONFIGURATION
  • MrcPrintf : SA_MEMORY_FUNCTIONS
  • MrcReturnFromSmc : SA_FUNCTION_CALLS
  • MrcSafeConfig : MEMORY_CONFIGURATION
  • MrcSignExtend : SA_MEMORY_FUNCTIONS
  • MrcTimeMeasure : _MEMORY_DXE_CONFIG , MEMORY_CONFIGURATION
  • MrcUpdateVref : SA_MEMORY_FUNCTIONS
  • MsegBase : _TXT_INFO_DATA
  • MsegSize : _TXT_INFO_DATA
  • MsHashEnable : MEMORY_CONFIGURATION
  • MsHashInterleaveBit : MEMORY_CONFIGURATION
  • MsHashMask : MEMORY_CONFIGURATION
  • MsiInterrupt : ISH_CONFIG
  • MultiVcEnable : TSN_CONFIG
  • MultiVcEnabled : CPU_PCIE_ROOT_PORT_CONFIG
  • MultU64x32 : SA_FUNCTION_CALLS
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- n -

  • NetworkEnabled : SMBIOS_TABLE_TYPE130
  • NewCenturyRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • NewFeatureEnable1 : MEMORY_CONFIGURATION
  • NewFeatureEnable2 : MEMORY_CONFIGURATION
  • NewFom : CPU_PCIE_RP_PREMEM_CONFIG
  • NftpLoadFailure : HECI_GS_SHDW_REGISTER
  • NmiRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • NMode : MEMORY_TIMING
  • NModeSupport : MEMORY_CONFIGURATION
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NumAcms : _HEAP_BIOSACM_ELEMENT
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfDpInPort : DPIN_PREMEM_CONFIG
  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumberOfPStates : CPU_INFO
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumberOfTcssSsidTable : TCSS_DATA_SSID_HOB
  • NumCores : CPU_INFO
  • NumEnabledThreads : CPU_INFO
  • NumEntries : MBP_HEADER
  • NumHts : CPU_INFO
  • NumOfControllers : ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumOfEntriesInLog : BIOSGUARD_LOG
  • NumOfLogicalProcessors : _BIOS_OS_DATA_REGION
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG
  • NumSaGvPointsEnabled : HOB_SAGV_INFO
  • NumSupportedCores : CPU_INFO
  • NumSupportedThreadsPerCore : CPU_INFO
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- o -

  • ObffEnable : CPU_PCIE_PWR_OPT
  • OcLock : OVERCLOCKING_PREMEM_CONFIG
  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OemCapabilities1 : SMBIOS_TABLE_TYPE130
  • OemCapabilities2 : SMBIOS_TABLE_TYPE130
  • OemCapabilities3 : SMBIOS_TABLE_TYPE130
  • OemCapabilities4 : SMBIOS_TABLE_TYPE130
  • OemParameterByte1 : ASF_BOOT_OPTIONS
  • OemParameterByte2 : ASF_BOOT_OPTIONS
  • OemResolutionSettingsRsvd : AMT_DXE_CONFIG
  • OemT12DelayOverride : GRAPHICS_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OneCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • OpioFusaConfigEnable : FUSA_CONFIG
  • OpRegion : IGD_OPREGION_PROTOCOL
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OsTcoRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentEnable : USB_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , MUX_GPIO_PARAM , SERIAL_IO_I2C_CONFIG
  • PanelPowerEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • Param1 : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Param2 : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • Password : GET_RSE_PASSWORD_RESPONSE
  • PasswordLength : GET_RSE_PASSWORD_RESPONSE
  • Pause : _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL , _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
  • PAVP : MEFWCAPS_SKU
  • PavpEnable : GRAPHICS_PEI_CONFIG
  • PBE : HECI_FW_STS6_REGISTER
  • PcErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • PcErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchCrossThrottling : THERMAL_THROTTLE_LEVELS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PciData : MEMORY_CONFIGURATION
  • PCIe : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : CPU_PCIE_CONFIG , PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieMultipleSegmentEnabled : TCSS_MISC_PEI_PREMEM_CONFIG
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PciePortLaneEnabled : PCH_INFO_HOB
  • PcieRpCommonConfig : CPU_PCIE_ROOT_PORT_CONFIG
  • PcieSpeed : CPU_PCIE_RP_PREMEM_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PciIndex : MEMORY_CONFIGURATION
  • PDA : MEMORY_CONFIGURATION
  • PdoProgramming : USB_CONFIG
  • PdtUnlock : ISH_CONFIG
  • PeciC10Reset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PeciSxReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Peg0Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegAspm : PCIE_DXE_CONFIG
  • PegData : SA_PEG_HOB
  • PegDeEmphasis : PCIE_PEI_CONFIG
  • PegDisableSpreadSpectrumClocking : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3EndPointHint : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3EndPointPreset : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3PresetSearch : SA_PEG_DATA
  • PegGen3ProgramStaticEq : CPU_PCIE_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RootPortPreset : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RxCtleOverride : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RxCtlePeaking : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen4EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen4RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGenerateBdatMarginTable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGpioData : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegLinkFailMask : SA_PEG_DATA
  • PegMaxPayload : PCIE_PEI_CONFIG
  • PegPhysicalSlotNumber : PCIE_PEI_CONFIG
  • PegPlatformResetRequired : SA_PEG_HOB
  • PegPwrOpt : PCIE_DXE_CONFIG
  • PegRootPortHPE : PCIE_DXE_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemLoopbackLane : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemNonProtocolAwareness : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemTestingMode : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegSlotPowerLimitScale : PCIE_PEI_CONFIG
  • PegSlotPowerLimitValue : PCIE_PEI_CONFIG
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiGraphicsPeimInit : GRAPHICS_PEI_CONFIG
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerBankRefresh : MEMORY_CONFIGURATION
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatio : CPU_INFO
  • PerCoreRatioOverride : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PeriodicDcc : MEMORY_CONFIGURATION
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DownstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTransmitterOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NumberOfPresetsOrCoefficients : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PinMux : CNVI_CONFIG , HDA_LINK_DMIC , ISH_GPIO_CONFIG , MUX_GPIO_PARAM , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PinSelection : TS_GPIO_PIN_SETTING
  • PkeySlot0 : BGPDT
  • PkeySlot1 : BGPDT
  • PkeySlot2 : BGPDT
  • PkgAttributes : BGUP_HEADER
  • PkgCStateDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateLimit : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateUnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PlatformConfig : GRAPHICS_DXE_CONFIG
  • PlatformDebugConsent : SI_PREMEM_CONFIG
  • PlatformMemorySize : MEMORY_CONFIG_NO_CRC
  • PlatId : BGPDT , BGUP_HEADER
  • PllMaxBandingRatio : OVERCLOCKING_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • Pme : HDAUDIO_CONFIG
  • PmeB0Register : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmeRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • PmgCstCfgCtrlLock : CPU_POWER_MGMT_TEST_CONFIG
  • PmodeClkEn : PCH_GENERAL_PREMEM_CONFIG
  • PmSupport : GRAPHICS_PEI_CONFIG
  • PmsyncEnable : TS_GPIO_PIN_SETTING
  • Port : USB2_PHY_CONFIG , USB3_HSIO_CONFIG
  • Port80Route : PCH_GENERAL_PREMEM_CONFIG
  • PortLane : PCH_HSIO_SATA_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PortUsb20 : USB_CONFIG
  • PortUsb30 : USB_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerDownMode : MEMORY_CONFIGURATION
  • PowerDownUnusedBundles : SA_PEG_HOB
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • PowerLimit1 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit1Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2Power : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3DutyCycle : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PpinSupport : CPU_CONFIG
  • PpmIrmSetting : CPU_POWER_MGMT_TEST_CONFIG
  • PprEnable : MEMORY_CONFIGURATION
  • PreBootDmaMask : VTD_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PreGlobalReset : _PLATFORM_ME_HOOK_PROTOCOL
  • PreWake : CPU_POWER_MGMT_VR_CONFIG
  • PrimaryDisplay : GRAPHICS_PEI_PREMEM_CONFIG
  • PrmrrSize : CPU_SECURITY_PREMEM_CONFIG
  • ProbelessTrace : MEMORY_CONFIGURATION
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorIsTxtCapable : _TXT_INFO_DATA
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorTraceEnable : CPU_TEST_CONFIG
  • ProcessorTraceMemSize : CPU_TEST_CONFIG
  • ProcessorTraceOutputScheme : CPU_TEST_CONFIG
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : CPU_POWER_MGMT_TEST_CONFIG
  • ProcHotResponse : CPU_POWER_MGMT_TEST_CONFIG
  • Profile : MEMORY_INFO_DATA
  • ProfileName : GET_WIFI_PROFILE_NAME_RESPONSE
  • ProgramGtChickenBits : GRAPHICS_PEI_CONFIG
  • ProtectedRangeBase : PROTECTED_RANGE
  • ProtectedRangeLimit : PROTECTED_RANGE
  • ProtectRange : PCH_FLASH_PROTECTION_CONFIG
  • PS1toPS0CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PsfFusaConfigEnable : FUSA_CONFIG
  • Psi1Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi2Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Enable : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi4Enable : CPU_POWER_MGMT_VR_CONFIG
  • PslMajorVer : BGUP_HEADER
  • PslMinorVer : BGUP_HEADER
  • PsmiRegionSize : GRAPHICS_PEI_PREMEM_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PsysOffset : CPU_POWER_MGMT_VR_CONFIG
  • PsysOffset1 : CPU_POWER_MGMT_VR_CONFIG
  • PsysPmax : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Time : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysSlope : CPU_POWER_MGMT_VR_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PTT : MEFWCAPS_SKU
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PVTTDNLP : MEMORY_CONFIGURATION
  • PwdwnIdleCounter : MEMORY_CONFIGURATION
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrCyclePending : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • PwrEnable : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- q -

  • QueryType : AMT_QUERY_KVM
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- r -

  • RaceToHalt : CPU_POWER_MGMT_TEST_CONFIG
  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • RampDown : CPU_POWER_MGMT_VR_CONFIG
  • RampUp : CPU_POWER_MGMT_VR_CONFIG
  • Rank : SA_ADDRESS_DECODE
  • RankInDimm : DIMM_INFO , MEMORY_INFO_DATA
  • RankInterleave : MEMORY_CONFIGURATION
  • Ras : SA_ADDRESS_DECODE
  • Ratio : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • Ratio_UINT16 : MEMORY_INFO_DATA
  • RC1pFreqEnable : GRAPHICS_PEI_CONFIG
  • RcompData : MEMORY_CONFIG_NO_CRC
  • RcompResistor : SA_MEMORY_RCOMP
  • RcompTarget : SA_MEMORY_RCOMP
  • RCS : HECI_FW_STS5_REGISTER
  • RCVENC1D : MEMORY_CONFIGURATION
  • RCVET : MEMORY_CONFIGURATION
  • RDAPT : MEMORY_CONFIGURATION
  • RDEQT : MEMORY_CONFIGURATION
  • RDMPRT : MEMORY_CONFIGURATION
  • RDODTT : MEMORY_CONFIGURATION
  • RDTC1D : MEMORY_CONFIGURATION
  • RDTC2D : MEMORY_CONFIGURATION
  • RDVC1D : MEMORY_CONFIGURATION
  • RDVC2D : MEMORY_CONFIGURATION
  • RDVREFDC : MEMORY_CONFIGURATION
  • ReadCpuSoftStrap : _PCH_SPI_PROTOCOL
  • ReadMsg : _HECI_PPI , _HECI_PROTOCOL
  • ReadMsr64 : SA_FUNCTION_CALLS
  • ReadOpcode : THC_HID_OVER_SPI
  • ReadPchSoftStrap : _PCH_SPI_PROTOCOL
  • ReadProtectionEnable : PROTECTED_RANGE
  • Ready : HECI_CONTROL_STATUS_REGISTER
  • RealtimeMemoryFrequency : MEMORY_CONFIGURATION
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RefClk : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • Refresh2X : MEMORY_CONFIGURATION
  • RefreshHpWm : MEMORY_CONFIGURATION
  • RefreshPanicWm : MEMORY_CONFIGURATION
  • RefreshWm : MEMORY_CONFIGURATION
  • Reg : FWSTS_SET_RECORD
  • RegBar : HOST_BRIDGE_PREMEM_CONFIG
  • Register : _IO_TRAP_EX_DISPATCH_PROTOCOL
  • ReInitHeci : _HECI_PROTOCOL
  • ReloadAndStart : _WDT_PROTOCOL
  • RemapEnable : MEMORY_CONFIGURATION
  • RemoteAssistance : AMT_PEI_CONFIG
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • RenderStandby : GRAPHICS_PEI_CONFIG
  • Request : GET_WIFI_CLIENT_CERT_BUFFER , GET_WIFI_CLIENT_KEY_BUFFER , GET_WIFI_PROFILE_DATA_BUFFER , GET_WIFI_PROFILE_NAME_BUFFER
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE , _TXT_INFO_DATA , AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , ARB_SVN_COMMIT , BIOS_GUARD_CONFIG , BIOSGUARD_HOB , CPU_SECURITY_PREMEM_CONFIG , GRAPHICS_DXE_CONFIG , HDA_LINK_HDA , HECI_CONTROL_STATUS_REGISTER , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , HECI_FW_STS5_REGISTER , HECI_FW_STS6_REGISTER , HECI_GS_SHDW_REGISTER , HOST_BRIDGE_PREMEM_CONFIG , ICC_CLOCK_SETTINGS_CURRENT_FLAGS , ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS , ICC_MESSAGE_RESP_DATA , MBP_HEADER , ME_CAP , MEFWCAPS_SKU , MG_IMR_STATUS , PMC_LPM_S0IX_SUB_STATE_EN , SMBIOS_TABLE_TYPE130 , TBT_IMR_STATUS , TCSS_DATA_SSID_HOB , TCSS_IOM_PEI_CONFIG , THC_PORT , VTD_CONFIG
  • Reserved0 : CPU_CONFIG
  • Reserved1 : BGPDT , CPU_DATA_HOB , ICC_CLOCK_SETTINGS_CURRENT_FLAGS , ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS , ME_CAP , MEFWCAPS_SKU , SA_MISC_PEI_PREMEM_CONFIG
  • Reserved11 : MEMORY_CONFIG_NO_CRC
  • Reserved2 : BGPDT , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , HECI_FW_STS6_REGISTER , HECI_GS_SHDW_REGISTER , INVOCATION_CODE_BITS , ME_CAP , MEFWCAPS_SKU
  • Reserved274 : MEMORY_CONFIGURATION
  • Reserved3 : BGUP_HEADER , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , MEFWCAPS_SKU , SPD_OFFSET_TABLE
  • Reserved336 : MEMORY_CONFIGURATION
  • Reserved4 : BGUP_HEADER , HECI_FW_STS4_REGISTER , MEFWCAPS_SKU
  • Reserved5 : BIOSGUARD_LOG , MEFWCAPS_SKU
  • Reserved6 : MEFWCAPS_SKU
  • Reserved7 : MEFWCAPS_SKU
  • Reserved8 : MEFWCAPS_SKU
  • Reserved9 : MEFWCAPS_SKU
  • ReservedBits1 : CPU_POWER_MGMT_BASIC_CONFIG
  • ReservedBits2 : MEMORY_CONFIGURATION
  • ReservedByte : DXE_CPU_POLICY_PROTOCOL , DXE_SI_POLICY_PROTOCOL
  • Reset : HECI_CONTROL_STATUS_REGISTER
  • ResetAux : _TXT_INFO_DATA , CPU_SECURITY_PREMEM_CONFIG
  • ResetHeci : _HECI_PROTOCOL
  • ResetPad : THC_HID_OVER_SPI
  • ResetPadTrigger : THC_HID_OVER_SPI
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResizableBarSupport : SA_DATA_HOB
  • Response : GET_WIFI_CLIENT_CERT_BUFFER , GET_WIFI_CLIENT_KEY_BUFFER , GET_WIFI_PROFILE_DATA_BUFFER , GET_WIFI_PROFILE_NAME_BUFFER
  • ResponseCode : AMT_QUERY_KVM_RESPONSE
  • Resume : _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL , _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
  • RetrainOnFastFail : MEMORY_CONFIGURATION
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • ReuseAdlSDdr5Board : MEMORY_CONFIGURATION
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _AMT_READY_TO_BOOT_PROTOCOL , _CONFIG_BLOCK_HEADER , _CPU_INFO_PROTOCOL , _ME_JHI_PROTOCOL , _PCH_ACPI_SMI_DISPATCH_PROTOCOL , _PCH_ESPI_SMI_DISPATCH_PROTOCOL , _PCH_PCIE_SMI_DISPATCH_PROTOCOL , _PCH_SMI_DISPATCH_PROTOCOL , _PCH_SPI_PROTOCOL , _PCH_TCO_SMI_DISPATCH_PROTOCOL , DXE_CPU_POLICY_PROTOCOL , DXE_SI_POLICY_PROTOCOL , GOP_POLICY_PROTOCOL , MBP_SENSITIVE_PPI , PCH_INFO_HOB
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfiMitigation : CPU_POWER_MGMT_VR_CONFIG
  • RfReset : CNVI_PIN_MUX
  • RhSelect : MEMORY_CONFIGURATION
  • RightShift64 : SA_FUNCTION_CALLS
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RMC : MEMORY_CONFIGURATION
  • RMT : MEMORY_CONFIGURATION
  • RMTBIT : MEMORY_CONFIGURATION
  • RMTLoopCount : MEMORY_CONFIGURATION
  • RmtPerTask : MEMORY_CONFIGURATION
  • RootPort : CPU_PCIE_CONFIG
  • RootPortIndex : HYBRID_GRAPHICS_CONFIG
  • RpDpcExtensionsEnabled : TCSS_PCIE_PORT_POLICY
  • RpeCapabilities : SMBIOS_TABLE_TYPE130
  • RpEnabledMask : CPU_PCIE_HOB , CPU_PCIE_RP_PREMEM_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG
  • RpEnMaskFromDevEn : CPU_PCIE_HOB
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RpmcStatus : HECI_FW_STS3_REGISTER
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : _TXT_INFO_DATA , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , MEMORY_TIMING , SA_MISC_PEI_PREMEM_CONFIG , TCSS_DATA , TCSS_MISC_PEI_CONFIG , TCSS_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , CPU_DMI_EQ_PARAM , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_GPIO_INFO , CPU_PCIE_PWR_OPT , CPU_PCIE_RTD3_GPIO , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , PCH_DMI_EQ_PARAM , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , PEG_GPIO_DATA , PPM_CUSTOM_RATIO_TABLE , SA_GPIO_INFO_PCIE , SA_PEG_DATA , THERMAL_THROTTLE_LEVELS , TSN_CONFIG
  • Rsvd1 : GRAPHICS_PEI_CONFIG , PCH_PM_CONFIG , PCIE_PEI_CONFIG , SA_DATA_HOB
  • Rsvd2 : GRAPHICS_PEI_PREMEM_CONFIG
  • Rsvd5 : CPU_POWER_MGMT_VR_CONFIG
  • RsvdBit : DXE_CPU_POLICY_PROTOCOL
  • RsvdBits : _PPM_CUSTOM_CTDP_TABLE , AMT_DXE_CONFIG , AMT_PEI_CONFIG , CPU_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , GPIO_CONFIG , GPIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_DXE_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_ESPI_CONFIG , PCH_LPC_PREMEM_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : PROTECTED_RANGE , SI_PREMEM_CONFIG
  • RsvdBits0 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FUSA_CONFIG , GBE_CONFIG , GNA_CONFIG , HDAUDIO_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_LOCK_DOWN_CONFIG , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , PCIE_PEI_PREMEM_CONFIG , PSF_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , SPI_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , USB_CONFIG , XDCI_CONFIG
  • RsvdBits1 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_IOAPIC_CONFIG , PCIE_PEI_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • RsvdByte2 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte3 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte4 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte5 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte6 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdO64B25to31 : MEMORY_CONFIGURATION
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • RtcAlarmRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • RTL : MEMORY_CONFIGURATION
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RunBusy : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaCall : MEMORY_CONFIG_NO_CRC
  • SaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • SaExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SafeMode : MEMORY_CONFIGURATION
  • SaGv : MEMORY_CONFIGURATION
  • SaGvFreq : MEMORY_CONFIGURATION
  • SaGvGear : MEMORY_CONFIGURATION
  • SagvHeuristicsDownControl : MEMORY_CONFIGURATION
  • SagvHeuristicsUpControl : MEMORY_CONFIGURATION
  • SaGvPointMask : HOB_SAGV_INFO
  • SagvSwitchFactorGT : MEMORY_CONFIGURATION
  • SagvSwitchFactorIA : MEMORY_CONFIGURATION
  • SagvSwitchFactorIO : MEMORY_CONFIGURATION
  • SagvSwitchFactorStall : MEMORY_CONFIGURATION
  • SalpSupport : SATA_CONFIG
  • SaPeg0ResetGpio : PEG_GPIO_DATA
  • SaPeg3ResetGpio : PEG_GPIO_DATA
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataPmPtm : PCH_SATA_PORT_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SchemaHobCount : BDAT_SCHEMA_LIST_HOB
  • SchemaHobGuids : BDAT_SCHEMA_LIST_HOB
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • ScramblerSupport : MEMORY_CONFIGURATION
  • ScriptSectionSize : BGUP_HEADER
  • ScrtmIndicator : HECI_FW_STS5_REGISTER
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SendAndReceive : _ME_JHI_PROTOCOL
  • SendDidMsg : ME_PEI_PREMEM_CONFIG
  • SendEcCmd : BIOS_GUARD_CONFIG
  • SendMsg : _HECI_PPI , _HECI_PROTOCOL
  • SendVrMbxCmd : CPU_POWER_MGMT_VR_CONFIG
  • SendwAck : _HECI_PPI , _HECI_PROTOCOL
  • SensorDevice : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • SensorNumber : ASF_MESSAGE , ASF_START_WDT
  • Sensornumber : PET_ALERT
  • SerialDebugLevel : MEMORY_CONFIG_NO_CRC
  • SerialIrqRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SetMem : SA_FUNCTION_CALLS
  • SetMemDword : SA_FUNCTION_CALLS
  • SetMemoryPmicVoltage : SA_FUNCTION_CALLS
  • SetMemoryVdd : SA_FUNCTION_CALLS
  • SetMemWord : SA_FUNCTION_CALLS
  • SetSecuredRegisterLock : CPU_PCIE_CONFIG
  • SetToDefault : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • SevenCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • SfamData : BGPDT
  • SgpioSupport : SATA_CONFIG
  • SgxInfo : _CPU_INFO_PROTOCOL
  • SgxSinitNvsData : SGX_INFO
  • SharedZqPin : MEMORY_CONFIGURATION
  • ShiftPiCommandTrain : SA_MEMORY_FUNCTIONS
  • Signal : _AMT_READY_TO_BOOT_PROTOCOL
  • SimicsFlag : MEMORY_CONFIGURATION
  • SinitAcmBase : _TXT_INFO_DATA
  • SinitAcmSize : _TXT_INFO_DATA
  • SinitMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • SixCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Size : _HEAP_EXT_DATA_ELEMENT , CACHE_DESCRIPTOR_INFO , GRAPHICS_DXE_CONFIG , MEMORY_CONFIGURATION
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCdClockInit : GRAPHICS_PEI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipFspGop : GRAPHICS_PEI_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipMpInit : CPU_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipPamLock : HOST_BRIDGE_PEI_CONFIG
  • SkipSetBootPState : CPU_POWER_MGMT_BASIC_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SkipStopPbet : CPU_SECURITY_PREMEM_CONFIG
  • SlotMap : _MEMORY_DXE_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlotSelection : CPU_PCIE_CONFIG , CPU_PCIE_HOB
  • SlowSlewRate : CPU_POWER_MGMT_VR_CONFIG
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbiosOemTypeFirmwareVersionInfo : DXE_SI_POLICY_PROTOCOL
  • SmbiosType4MaxSpeedOverride : CPU_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SmbusRead16 : SA_FUNCTION_CALLS
  • SmbusRead8 : SA_FUNCTION_CALLS
  • SmbusRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SmbusWrite16 : SA_FUNCTION_CALLS
  • SmbusWrite8 : SA_FUNCTION_CALLS
  • SmmbaseSwSmiNumber : CPU_INFO
  • SmmMsrSaveStateEnable : DXE_CPU_POLICY_PROTOCOL
  • SmmProcTraceEnable : DXE_CPU_POLICY_PROTOCOL
  • SmmUseBlockIndication : DXE_CPU_POLICY_PROTOCOL
  • SmmUseDelayIndication : DXE_CPU_POLICY_PROTOCOL
  • SmmUseSmmEnableIndication : DXE_CPU_POLICY_PROTOCOL
  • SmramCpuData : SMRAM_CPU_INFO
  • SmramCpuInfo : _CPU_INFO_PROTOCOL
  • SmramMask : MEMORY_CONFIGURATION
  • Smtc : HECI_FW_STS5_REGISTER
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SolEnabled : SMBIOS_TABLE_TYPE130
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SolStateChange : INVOCATION_CODE_BITS
  • SOT : MEMORY_CONFIGURATION
  • SpdAddressTable : _MEMORY_DXE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • SpdData : MEMORY_CONFIG_NO_CRC , SPD_DATA_BUFFER
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : MEMORY_CONFIGURATION
  • SpdSave : DIMM_INFO
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpecialCommand : ASF_BOOT_OPTIONS
  • SpecialCommandParamHighByte : ASF_BOOT_OPTIONS
  • SpecialCommandParamLowByte : ASF_BOOT_OPTIONS
  • SpecVerMajor : _HEAP_BIOS_SPEC_VER_ELEMENT
  • SpecVerMinor : _HEAP_BIOS_SPEC_VER_ELEMENT
  • SpecVerRevision : _HEAP_BIOS_SPEC_VER_ELEMENT
  • Speed : DIMM_INFO
  • SpeedLimit : SATA_CONFIG
  • SpiAsyncRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SpiBiosWpRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpiEiss : PCH_LOCK_DOWN_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SpiProtectionMode : HECI_FWS_REGISTER
  • SrefCfgEna : MEMORY_CONFIGURATION
  • SrefCfgIdleTmr : MEMORY_CONFIGURATION
  • SrouEnabled : SMBIOS_TABLE_TYPE130
  • SsidTablePtr : SI_CONFIG
  • Start : SPD_OFFSET_TABLE
  • StartEnforcement : HECI_FW_STS5_REGISTER
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StateRatioMax16 : PPM_CUSTOM_RATIO_TABLE
  • Status : AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE , DIMM_INFO , FSP_ERROR_INFO_HOB , GET_WIFI_PROFILE_NAME_RESPONSE , SMBIOS_PROCESSOR_INFO
  • StatusCause : REPORT_BIOS_STATUS
  • StatusCodeValue : ASF_DATA_HUB_MAP
  • StdMng : MEFWCAPS_SKU
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubCommand : ASF_BOOT_OPTIONS , ASF_MESSAGE , ASF_MESSAGE_HEADER
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedLanguages : _GOP_COMPONENT_NAME2_PROTOCOL
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SvidEnabled : CPU_DATA_HOB
  • SxResumeType : HECI_FW_STS4_REGISTER
  • SyncMngState : INVOCATION_CODE_BITS
  • SyncRaAvailability : INVOCATION_CODE_BITS
  • SynpsPhyBinLen : PCH_HSIO_CONFIG
  • SynpsPhyBinPtr : PCH_HSIO_CONFIG
  • SystemCacheType : SMBIOS_CACHE_INFO
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT , ITBT_POLICY_PROTOCOL , SA_POLICY_PROTOCOL
  • TableSyncError : INVOCATION_CODE_BITS
  • TAT : MEMORY_CONFIGURATION
  • TbtCommonConfig : _DXE_ITBT_CONFIG
  • TbtFwVersion : TBT_IMR_STATUS
  • TbtImrStatus : TCSS_DATA
  • TccActivationOffset : CPU_POWER_MGMT_BASIC_CONFIG
  • tCCD_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TccEnable : PSF_CONFIG
  • TccOffsetClamp : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetTimeWindowForRatl : CPU_POWER_MGMT_BASIC_CONFIG
  • tCK : MEMORY_TIMING
  • tCL : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcoTimeoutRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • TcssData : TCSS_DATA_HOB
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcssIomVccSt : TCSS_DATA
  • TcssRtd3 : TCSS_DATA
  • TcssSsidTable : TCSS_DATA_SSID_HOB
  • TcssxDCIInt : TCSS_DATA
  • TcssxDCIIrq : TCSS_DATA
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • tCWL : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TdcCurrentLimit : CPU_POWER_MGMT_VR_CONFIG
  • TdcEnable : CPU_POWER_MGMT_VR_CONFIG
  • TdcLock : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow1 : CPU_POWER_MGMT_VR_CONFIG
  • TestMode : SATA_CONFIG
  • tFAW : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TgaSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • Thc0Strap : PCH_INFO_HOB
  • ThcPort : THC_CONFIG
  • ThermalMonitor : CPU_POWER_MGMT_TEST_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • ThreeStrikeCounterDisable : CPU_TEST_CONFIG
  • ThrtCkeMinDefeat : MEMORY_CONFIGURATION
  • ThrtCkeMinDefeatLpddr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmrLpddr : MEMORY_CONFIGURATION
  • TimedMwait : CPU_POWER_MGMT_TEST_CONFIG
  • TimeoutHigh : ASF_START_WDT
  • TimeoutLow : ASF_START_WDT
  • Timing : MEMORY_INFO_DATA
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TLS : MEFWCAPS_SKU
  • TmeEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • TmrOverflowRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • TpmStartupFailureOnS3 : BOOT_GUARD_INFO
  • TpmType : BOOT_GUARD_INFO
  • TraceHub : CPU_TRACE_HUB_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG
  • TrainTrace : MEMORY_CONFIGURATION
  • tRAS : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRCDtRP : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tREFI : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC2 : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC4 : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFCpb : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRPab : MEMORY_TIMING
  • tRRD : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRRD_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRRD_S : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRTP : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TrustedDevice : MEFWCAPS_SKU
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegBase : _TXT_INFO_DATA
  • TsegSize : _TXT_INFO_DATA , SA_MISC_PEI_PREMEM_CONFIG
  • TsGpioPinSetting : PCH_MEMORY_THROTTLING
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TsnLinkSpeed : TSN_CONFIG
  • TsnMacAddressHigh : TSN_CONFIG
  • TsnMacAddressLow : TSN_CONFIG
  • TStates : CPU_POWER_MGMT_TEST_CONFIG
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboMode : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboPowerLimitLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • TvbDownBinsTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbDownBinsTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • TwoCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • tWR : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR_S : MEMORY_CONFIGURATION , MEMORY_TIMING
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • TXDQSDCC : MEMORY_CONFIGURATION
  • Txiset : USB2_PHY_PARAMETERS
  • Txt : CPU_SECURITY_PREMEM_CONFIG
  • TxtAcheckRequest : _TXT_INFO_DATA , CPU_SECURITY_PREMEM_CONFIG
  • TXTCO : MEMORY_CONFIGURATION
  • TXTCODQS : MEMORY_CONFIGURATION
  • TxtDprMemoryBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtDprMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtEnable : CPU_CONFIG
  • TxtHeapMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • TxtLcpPdBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtLcpPdSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtMode : _TXT_INFO_DATA
  • TxtSupport : HECI_FW_STS6_REGISTER
  • Type : _HEAP_EXT_DATA_ELEMENT , AMT_PET_QUEUE_HOB , CACHE_DESCRIPTOR_INFO , FSP_ERROR_INFO_HOB , ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- u -

  • UaolEnable : USB_CONFIG
  • UartDeviceConfig : SERIAL_IO_CONFIG
  • Uint64 : MSR_TURBO_RATIO_LIMIT_REGISTER
  • UnConfigureMe : AMT_DXE_CONFIG
  • Uninit : _ME_JHI_PROTOCOL
  • Uninstall : _ME_JHI_PROTOCOL
  • UnlimitedIccMax : OVERCLOCKING_PREMEM_CONFIG
  • UnlockGpioPads : PCH_LOCK_DOWN_CONFIG
  • UnRegister : _IO_TRAP_EX_DISPATCH_PROTOCOL , _PCH_ACPI_SMI_DISPATCH_PROTOCOL , _PCH_ESPI_SMI_DISPATCH_PROTOCOL , _PCH_PCIE_SMI_DISPATCH_PROTOCOL , _PCH_SMI_DISPATCH_PROTOCOL , _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • UpSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • UserBudgetEnable : MEMORY_CONFIGURATION
  • UserConsentFlow : INVOCATION_CODE_BITS
  • UserThresholdEnable : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Valid : MG_IMR_STATUS , TBT_IMR_STATUS
  • Value : AMT_PET_QUEUE_HOB , FSP_ERROR_INFO_HOB , SA_GPIO_INFO_PCIE
  • VbtAddress : GRAPHICS_DXE_CONFIG
  • Vc1ReadMeter : MEMORY_CONFIGURATION
  • VCCDLLBP : MEMORY_CONFIGURATION
  • VccinAux : PCH_FIVR_CONFIG
  • VccInAuxImonIccImax : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionCapacitanceInUf : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionEnable : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionQuiescentPowerInMw : CPU_POWER_MGMT_VR_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VDDQT : MEMORY_CONFIGURATION
  • VddqVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VddSettleWaitTime : MEMORY_CONFIGURATION
  • VddVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • VendorSpecific : BGUP_HEADER
  • VerbTableEntryNum : HDAUDIO_CONFIG
  • VerbTablePtr : HDAUDIO_CONFIG
  • VerifiedBootPolicy : HECI_FW_STS6_REGISTER
  • Version : _BIOS_OS_DATA_REGION , ASF_BOOT_OPTIONS , ASF_MESSAGE , BGUP_HEADER , BIOSGUARD_LOG , FWSTS_SMBIOS_RECORD
  • VersionNumber : ASF_MESSAGE_HEADER
  • VerticalResolution : GRAPHICS_PEI_CONFIG
  • VgpioCs : GPIO_CONFIG
  • VLD : HECI_FW_STS5_REGISTER
  • VmdCfgBarAttr : VMD_PEI_CONFIG
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdCfgBarSize : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Attr : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Attr : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdMemBarSize1 : VMD_PEI_CONFIG
  • VmdMemBarSize2 : VMD_PEI_CONFIG
  • VmdPortBEnable : VMD_PEI_CONFIG
  • VmdPortCEnable : VMD_PEI_CONFIG
  • VmdPortDEnable : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmxEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Voltage : CPU_INFO , FIVR_EXT_RAIL_CONFIG , SMBIOS_PROCESSOR_INFO
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VppVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VrAddress : CPU_DATA_HOB
  • VrConfigEnable : CPU_POWER_MGMT_VR_CONFIG
  • VrPowerDeliveryDesign : CPU_POWER_MGMT_VR_CONFIG
  • VrVoltageLimit : CPU_POWER_MGMT_VR_CONFIG
  • VsysAssertionDeglitchMantissa : CPU_POWER_MGMT_VR_CONFIG
  • VsysFullScale : CPU_POWER_MGMT_VR_CONFIG
  • VtdDisable : VTD_CONFIG
  • VtdIgdEnable : VTD_CONFIG
  • VtdIopEnable : VTD_CONFIG
  • VtdIpuEnable : VTD_CONFIG
  • VttCompForVsshi : MEMORY_CONFIGURATION
  • VttTermination : MEMORY_CONFIGURATION
  • VwErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • VwErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeGpioNo : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • WakeOnTouch : THC_PORT
  • WarmRstReqForDF : HECI_GS_SHDW_REGISTER
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WeaklockEn : MEMORY_CONFIGURATION
  • WifiCore : CNVI_CONFIG
  • WLAN : MEFWCAPS_SKU
  • WlanPowerConfigChange : INVOCATION_CODE_BITS
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WrcFeatureEnable : SA_MISC_PEI_PREMEM_CONFIG
  • WRDS : MEMORY_CONFIGURATION
  • WRDSEQT : MEMORY_CONFIGURATION
  • WRDSUDT : MEMORY_CONFIGURATION
  • Write : _BIOSGUARD_PROTOCOL
  • Write0 : MEMORY_CONFIGURATION
  • WriteMsr64 : SA_FUNCTION_CALLS
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteProtectionEnable : PROTECTED_RANGE
  • WriteThreshold : MEMORY_CONFIGURATION
  • WRSRT : MEMORY_CONFIGURATION
  • WRTC1D : MEMORY_CONFIGURATION
  • WRTC2D : MEMORY_CONFIGURATION
  • WRVC1D : MEMORY_CONFIGURATION
  • WRVC2D : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- x -

  • X2ApicOptOut : VTD_CONFIG
  • X2ApicSupport : CPU_CONFIG
  • XdciConfig : USB_CONFIG
  • XhciOcLock : USB_CONFIG
  • XmpConfigWarning : MEMORY_INFO_DATA
  • XmpProfileEnable : MEMORY_INFO_DATA
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members

Here is a list of all documented class members with links to the class documentation for each member:

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- a -

  • AcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • AcmActived : HECI_FW_STS5_REGISTER
  • AcmDone : HECI_FW_STS5_REGISTER
  • AcmMajorVersion : _TXT_INFO_DATA
  • AcmMinorVersion : _TXT_INFO_DATA
  • AcmRevision : _TXT_INFO_DATA
  • AcousticNoiseMitigation : CPU_POWER_MGMT_VR_CONFIG
  • AcpiBase : _TXT_INFO_DATA
  • AcpiL6dPmeHandling : PCH_GENERAL_CONFIG
  • AcpiReservedMemoryBase : SA_MISC_PEI_PREMEM_CONFIG
  • AcpiReservedMemorySize : SA_MISC_PEI_PREMEM_CONFIG
  • AcsEnabled : TCSS_PCIE_PORT_POLICY
  • AcSplitLock : CPU_CONFIG
  • Active : CPU_PCIE_GPIO_INFO , PCIE_GPIO , SA_GPIO_INFO_PCIE
  • ActiveCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveCoreCount1 : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveInterface : AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE
  • ActiveLtr : THC_PORT
  • ActiveSmallCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActiveSocNorthAtomCoreCount : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ActualFreq : CPU_INFO
  • Address : IO_TRAP_EX_REGISTER_CONTEXT
  • AdrEn : ADR_CONFIG
  • AdrHostPartitionReset : ADR_CONFIG
  • AdrMultiplier1Val : ADR_CONFIG
  • AdrMultiplier2Val : ADR_CONFIG
  • AdrPlatAckEn : ADR_CONFIG
  • AdrSrcOverride : ADR_CONFIG
  • AdrSrcSel : ADR_CONFIG
  • AdrTimer1Val : ADR_CONFIG
  • AdrTimer2Val : ADR_CONFIG
  • AdrTimerEn : ADR_CONFIG
  • AdvancedErrorReporting : TCSS_PCIE_PORT_POLICY
  • AesEnable : CPU_CONFIG
  • AetEnabled : TRACE_HUB_CONFIG
  • ALIASCHK : MEMORY_CONFIGURATION
  • AllowKnownReset : _WDT_PROTOCOL
  • AllowOppRefBelowWriteThrehold : MEMORY_CONFIGURATION
  • AllTpmDisconnected : HECI_FW_STS4_REGISTER
  • AlsEnable : GRAPHICS_DXE_CONFIG
  • Amt : MEFWCAPS_SKU
  • AmtbxHotkeyPressed : AMT_DXE_CONFIG
  • AmtbxSelectionScreen : AMT_DXE_CONFIG
  • AmtEnabled : AMT_PEI_CONFIG , SMBIOS_TABLE_TYPE130
  • AmtKvmEnabled : AMT_PEI_CONFIG
  • AmtReportError : AMT_DXE_CONFIG
  • AmtSignature : SMBIOS_TABLE_TYPE130
  • AmtSolEnabled : AMT_PEI_CONFIG
  • AmtSupported : SMBIOS_TABLE_TYPE130
  • ApertureSize : GRAPHICS_PEI_PREMEM_CONFIG
  • ApicId : BIST_HOB_DATA
  • AppId : MBP_ITEM_HEADER
  • ApplyConfigTdp : CPU_POWER_MGMT_BASIC_CONFIG
  • ApStartupBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • ArpEnable : PCH_SMBUS_PREMEM_CONFIG
  • AsfBootOptions : GET_BOOT_OPTIONS_RESPONSE
  • AsfHeader : AMT_GET_ACTIVE_LAN_INTERFACE , AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_QUERY_KVM , AMT_QUERY_KVM_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE , AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_MAC_PASSTHROUGH_RESPONSE , ASF_PROFILE_MESSAGE_HEADER , ASF_START_WDT , ASF_STOP_WDT , CLEAR_BOOT_OPTIONS , GET_BOOT_OPTIONS , GET_RSE_PASSWORD , GET_RSE_PASSWORD_RESPONSE , GET_WIFI_PROFILE_NAME_RESPONSE , PET_ALERT , REPORT_BIOS_STATUS
  • AsfMessage : HECI_ASF_PUSH_PROGRESS_CODE
  • Aspm : TCSS_PCIE_PORT_POLICY
  • Assignment : THC_PORT
  • Associativity : CACHE_DESCRIPTOR_INFO , SMBIOS_CACHE_INFO
  • AtomClusterRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2MaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomL2VoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • AtomPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • AtomTurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • AtomTurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • Attributes : _CONFIG_BLOCK_HEADER , SERIAL_IO_UART_CONFIG
  • AudioDspFusedOut : PCH_INFO_HOB
  • AudioLinkDmic : HDAUDIO_PREMEM_CONFIG
  • AudioLinkHda : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSndw : HDAUDIO_PREMEM_CONFIG
  • AudioLinkSsp : HDAUDIO_PREMEM_CONFIG
  • AutoFlow : SERIAL_IO_UART_ATTRIBUTES
  • AutoSelfRefreshSupport : MEMORY_CONFIGURATION
  • AuxOri : TCSS_IOM_ORI_OVERRIDE
  • AvailableSize : _CONFIG_BLOCK_TABLE_STRUCT
  • Avx2RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx2VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • Avx3Disable : CPU_CONFIG
  • Avx3RatioOffset : OVERCLOCKING_PREMEM_CONFIG
  • Avx512VoltageScaleFactor : OVERCLOCKING_PREMEM_CONFIG
  • AvxDisable : CPU_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- b -

  • BacklightControlSupport : GRAPHICS_DXE_CONFIG
  • Bank : SA_ADDRESS_DECODE
  • BankGroup : SA_ADDRESS_DECODE
  • BaseAddress : VTD_CONFIG
  • BaseClassCode : PCIE_DEVICE_OVERRIDE
  • BaudRate : SERIAL_IO_UART_ATTRIBUTES
  • Bclk : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • BclkAdaptiveVoltage : OVERCLOCKING_PREMEM_CONFIG
  • BClkFrequency : MEMORY_CONFIGURATION
  • BclkRfiFreq : MEMORY_CONFIGURATION
  • BclkSource : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BCLM : GRAPHICS_DXE_CONFIG
  • BdatEnable : SA_MISC_PEI_PREMEM_CONFIG
  • BdatTestType : SA_MISC_PEI_PREMEM_CONFIG
  • BestPreset : SA_PEG_DATA
  • BgModSvn : BGPDT , BIOSGUARD_LOG
  • Bgpdt : BIOSGUARD_HOB
  • BgpdtHash : BIOS_GUARD_CONFIG
  • BgpdtMajVer : BGPDT
  • BgpdtMinVer : BGPDT
  • BgpdtSize : BGPDT
  • BgupBuffer : BGUP
  • BgupHeader : BGUP , BIOSGUARD_HOB
  • Bifurcation : PCH_PCIE_RP_PREMEM_CONFIG
  • BiosAcmBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • BiosAcmSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • BiosGuard : CPU_SECURITY_PREMEM_CONFIG
  • BiosGuardAttr : BGPDT , BIOS_GUARD_CONFIG
  • BiosGuardIoTrapAddress : BIOSGUARD_HOB
  • BiosGuardIoTrapLength : BIOSGUARD_HOB
  • BiosGuardLog : BIOSGUARD_HOB
  • BiosGuardMemAddress : BIOSGUARD_HOB
  • BiosGuardMemSize : BIOSGUARD_HOB
  • BiosGuardModulePtr : BIOS_GUARD_CONFIG , BIOSGUARD_HOB
  • BiosGuardModuleSize : BIOSGUARD_HOB
  • BiosGuardToolsInterface : CPU_SECURITY_PREMEM_CONFIG
  • BiosInterface : PCH_LOCK_DOWN_CONFIG
  • BiosInterfaceLock : RTC_CONFIG
  • BiosLock : PCH_LOCK_DOWN_CONFIG
  • BiosSinitSize : _BIOS_OS_DATA_REGION
  • BiosSize : CPU_SECURITY_PREMEM_CONFIG
  • BiosStatus : REPORT_BIOS_STATUS
  • BiosSvn : BGPDT , BGUP_HEADER
  • BiosWrProtectRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • BiosWrReportRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • BiProcHot : CPU_POWER_MGMT_TEST_CONFIG
  • BistOnReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • BistResetRequest : HECI_FWS_REGISTER
  • BistTestState : HECI_FWS_REGISTER
  • Bits : MSR_TURBO_RATIO_LIMIT_REGISTER
  • BltBufferAddress : GRAPHICS_PEI_CONFIG
  • BltBufferSize : GRAPHICS_PEI_CONFIG
  • BmeMasterSlaveEnabled : PCH_ESPI_CONFIG
  • BootFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG
  • BootGuardCapability : BOOT_GUARD_INFO
  • BootGuardDisable : HECI_FW_STS6_REGISTER
  • BootGuardFwStsValid : HECI_FW_STS4_REGISTER
  • BootGuardSelfTest : HECI_FW_STS4_REGISTER
  • BootMode : SPD_OFFSET_TABLE
  • BootOptionsMaskByte1 : ASF_BOOT_OPTIONS
  • BootOptionsMaskByte2 : ASF_BOOT_OPTIONS
  • BrandString : CPU_INFO
  • BspInitDisabled : HECI_FW_STS6_REGISTER
  • BtAudioOffload : CNVI_CONFIG
  • BtCore : CNVI_CONFIG
  • BypassFivrConfig : PCH_FIVR_CONFIG
  • BypassPhySyncReset : PCH_HSIO_PREMEM_CONFIG
  • ByPassTpmEventLog : BOOT_GUARD_INFO
  • BypassTpmInit : BOOT_GUARD_INFO
  • ByteCount : ASF_MESSAGE_HEADER , GET_BOOT_OPTIONS_RESPONSE , HECI_ASF_PUSH_PROGRESS_CODE
  • ByteEnable : IO_TRAP_EX_REGISTER_CONTEXT
  • ByteEnableMask : IO_TRAP_EX_REGISTER_CONTEXT
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- c -

  • C0TransmitEnable : TS_GPIO_PIN_SETTING
  • C10DynamicThresholdAdjustment : PCH_PM_CONFIG
  • C1AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C1e : CPU_POWER_MGMT_TEST_CONFIG
  • C1UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3AutoDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • C3UnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • CacheConfiguration : SMBIOS_CACHE_INFO
  • CacheInfo : CPU_INFO
  • CacheSpeed : SMBIOS_CACHE_INFO
  • CallerId : FSP_ERROR_INFO_HOB
  • Cas : SA_ADDRESS_DECODE
  • CBDepth : HECI_CONTROL_STATUS_REGISTER
  • CBReadPointer : HECI_CONTROL_STATUS_REGISTER
  • CBWritePointer : HECI_CONTROL_STATUS_REGISTER
  • CdClock : GRAPHICS_PEI_CONFIG
  • CdrRelock : CPU_PCIE_RP_PREMEM_CONFIG
  • CdynmaxClampEnable : GRAPHICS_PEI_CONFIG
  • CenterSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • ChangeAllowed : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • Channel : SA_ADDRESS_DECODE
  • ChannelASlotMap : _MEMORY_DXE_CONFIG
  • ChapDeviceEnable : HOST_BRIDGE_PEI_CONFIG
  • CheckPoint : SA_FUNCTION_CALLS
  • CheckStatus : _WDT_PROTOCOL
  • ChHashEnable : MEMORY_CONFIGURATION
  • ChHashInterleaveBit : MEMORY_CONFIGURATION
  • ChHashMask : MEMORY_CONFIGURATION
  • ChHashOverride : MEMORY_CONFIGURATION
  • ChipsetInitBinLen : PCH_HSIO_CONFIG
  • ChipsetInitBinPtr : PCH_HSIO_CONFIG
  • ChipsetInitMessage : PCH_HSIO_PREMEM_CONFIG
  • ChipsetIsTxtCapable : _TXT_INFO_DATA
  • CiraRequest : AMT_DXE_CONFIG
  • CiraTimeout : AMT_DXE_CONFIG
  • CleanMemory : MEMORY_CONFIG_NO_CRC
  • Clk : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • Clkreq : CNVI_PIN_MUX
  • ClkReq : PCH_PCIE_CLOCK
  • ClkReqMsgEnable : CPU_PCIE_RP_PREMEM_CONFIG
  • ClkReqMsgEnableRp : CPU_PCIE_RP_PREMEM_CONFIG
  • CLKTCO : MEMORY_CONFIGURATION
  • ClockGating : PCH_DMI_CONFIG
  • CloseSession : _ME_JHI_PROTOCOL
  • ClsUserInfo : INVOCATION_CODE_BITS
  • Cm : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CMDDRUD : MEMORY_CONFIGURATION
  • CMDDSEQ : MEMORY_CONFIGURATION
  • CmdMirror : MEMORY_CONFIGURATION
  • CmdRanksTerminated : MEMORY_CONFIGURATION
  • CMDSR : MEMORY_CONFIGURATION
  • CMDVC : MEMORY_CONFIGURATION
  • CmGen3 : CPU_DMI_HOB , PCH_DMI_HOB
  • CmGen4 : CPU_DMI_HOB , PCH_DMI_HOB
  • CodecSxWakeCapability : HDAUDIO_CONFIG
  • Command : _PCODE_MAILBOX_INTERFACE , ASF_MESSAGE_HEADER , GET_BOOT_OPTIONS_RESPONSE , HECI_ASF_PUSH_PROGRESS_CODE , HWA_MESSAGE_HEADER
  • CommandCompletion : _OC_MAILBOX_INTERFACE
  • ComplianceTest : CPU_PCIE_HOB
  • ComplianceTestMode : PCIE_COMMON_CONFIG
  • ComponentName : FWSTS_SET_RECORD
  • ComputeDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ComputeDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • ConfigTdpBios : CPU_POWER_MGMT_CUSTOM_CONFIG
  • ConfigTdpLevel : CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_POWER_MGMT_TEST_CONFIG
  • ConfigTdpLock : CPU_POWER_MGMT_CUSTOM_CONFIG
  • Controller : ISH_I3C_CONFIG , SA_ADDRESS_DECODE
  • ControllerConfig : ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
  • CopyMem : SA_FUNCTION_CALLS
  • CoreBiosDoneEnabled : ME_DXE_CONFIG
  • CoreCount : SMBIOS_PROCESSOR_INFO
  • CoreMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • CorePllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreRatioExtensionMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfConfigScope : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointCount : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVfPointRatio : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • CoreVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • CorrectableErrorReport : TCSS_PCIE_PORT_POLICY
  • Count : FWSTS_SMBIOS_RECORD
  • Cp : CPU_DMI_EQ_PARAM , CPU_PCIE_EQ_LANE_PARAM , PCH_DMI_EQ_PARAM , PCIE_EQ_PARAM
  • CpGen3 : CPU_DMI_HOB , PCH_DMI_HOB
  • CpGen4 : CPU_DMI_HOB , PCH_DMI_HOB
  • CpuAttachedStorage : RST_CONFIG
  • CpuBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • CpuBclkPllOn : BCLK_CONFIG
  • CpuC10GatePinEnable : PCH_PM_CONFIG
  • CpuCommonFeatures : _CPU_INFO_PROTOCOL
  • CpuCrashLogDevice : TELEMETRY_PEI_PREMEM_CONFIG
  • CpuCrashLogEnable : TELEMETRY_PEI_CONFIG
  • CpuDebugDisabled : HECI_FW_STS6_REGISTER
  • Cpuid : PPM_CUSTOM_RATIO_TABLE
  • CpuInfo : _CPU_INFO_PROTOCOL
  • CpuMailboxRead : SA_FUNCTION_CALLS
  • CpuMailboxWrite : SA_FUNCTION_CALLS
  • CpuPcie0Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie1Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie2Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcie3Rtd3Gpio : HYBRID_GRAPHICS_CONFIG
  • CpuPcieRtd3 : PCIE_DXE_CONFIG
  • CpuRatio : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CpuReplacedSts : HECI_GS_SHDW_REGISTER
  • CpuReplacedValid : HECI_GS_SHDW_REGISTER
  • CpuReplacement : INVOCATION_CODE_BITS
  • CpuReplacementTimeout : AMT_DXE_CONFIG
  • CpuSignature : CPU_INFO
  • CrashLogEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CrashLogGprs : CPU_CONFIG_LIB_PREMEM_CONFIG
  • CreateSession : _ME_JHI_PROTOCOL
  • Crid : PCH_GENERAL_CONFIG
  • CridEnable : SA_MISC_PEI_PREMEM_CONFIG
  • CridOrgRid : PCH_INFO_HOB
  • Cs : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • CseDataResilience : ME_PEI_CONFIG
  • CsEnable : ISH_SPI , SERIAL_IO_SPI_CONFIG
  • CseToDisabled : HECI_GS_SHDW_REGISTER
  • CsiSpeed : IPU_PREMEM_CONFIG
  • CsmFlag : SI_CONFIG
  • CsMode : SERIAL_IO_SPI_CONFIG
  • CsPolarity : SERIAL_IO_SPI_CONFIG
  • CsState : SERIAL_IO_SPI_CONFIG
  • CstateLatencyControl0Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl0TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl1TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl2TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl3TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl4TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5Irtl : CPU_POWER_MGMT_TEST_CONFIG
  • CstateLatencyControl5TimeUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CStatePreWake : CPU_POWER_MGMT_TEST_CONFIG
  • CstCfgCtrIoMwaitRedirection : CPU_POWER_MGMT_TEST_CONFIG
  • CtrlRampTmr : FIVR_EXT_RAIL_CONFIG
  • Cts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • CurrentPowerSource : HECI_FWS_REGISTER
  • CurrentSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • CurrentSramType : SMBIOS_CACHE_INFO
  • CurrentState : HECI_FWS_REGISTER
  • CustomConfigTdpTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomizedSsid : SI_CONFIG
  • CustomizedSvid : SI_CONFIG
  • CustomPowerLimit1 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit1Time : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerLimit2 : _PPM_CUSTOM_CTDP_TABLE
  • CustomPowerUnit : CPU_POWER_MGMT_TEST_CONFIG
  • CustomRatioTable : CPU_POWER_MGMT_CUSTOM_CONFIG
  • CustomTurboActivationRatio : _PPM_CUSTOM_CTDP_TABLE
  • CwbEnable : PCH_DMI_CONFIG
  • Cx : CPU_POWER_MGMT_TEST_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- d -

  • D0i3SupportValid : HECI_FWS_REGISTER
  • D3ColdEnable : IOM_INTERFACE_CONFIG
  • D3HotEnable : IOM_INTERFACE_CONFIG
  • D3SupportValid : HECI_FWS_REGISTER
  • DAL : MEFWCAPS_SKU
  • Data : _OC_MAILBOX_FULL , _PCODE_MAILBOX_FULL , _TXT_INFO_HOB , ASF_PROFILE_MESSAGE_HEADER , SET_FILE , SET_FILE_EX
  • DataBits : SERIAL_IO_UART_ATTRIBUTES
  • DataDwords : HDA_VERB_TABLE_HEADER
  • DataRate : HOB_SAGV_TIMING_OUT
  • DataSectionSize : BGUP_HEADER
  • DataSyncConfirmation : INVOCATION_CODE_BITS
  • DBG2 : SERIAL_IO_UART_CONFIG
  • DCC : MEMORY_CONFIGURATION
  • DciClkEnable : PCH_DCI_PREMEM_CONFIG
  • DciDbcMode : PCH_DCI_PREMEM_CONFIG
  • DciEn : PCH_DCI_PREMEM_CONFIG
  • DciModphyPg : PCH_DCI_PREMEM_CONFIG
  • DciUsb3TypecUfpDbg : PCH_DCI_PREMEM_CONFIG
  • DcLoadline : CPU_POWER_MGMT_VR_CONFIG
  • DdiConfiguration : GRAPHICS_PEI_PREMEM_CONFIG
  • DdiPort1Ddc : DDI_CONFIGURATION
  • DdiPort1Hpd : DDI_CONFIGURATION
  • DdiPort2Ddc : DDI_CONFIGURATION
  • DdiPort2Hpd : DDI_CONFIGURATION
  • DdiPort3Ddc : DDI_CONFIGURATION
  • DdiPort3Hpd : DDI_CONFIGURATION
  • DdiPort4Ddc : DDI_CONFIGURATION
  • DdiPort4Hpd : DDI_CONFIGURATION
  • DdiPortADdc : DDI_CONFIGURATION
  • DdiPortAHpd : DDI_CONFIGURATION
  • DdiPortBConfig : DDI_CONFIGURATION
  • DdiPortBDdc : DDI_CONFIGURATION
  • DdiPortBHpd : DDI_CONFIGURATION
  • DdiPortCDdc : DDI_CONFIGURATION
  • DdiPortCHpd : DDI_CONFIGURATION
  • Ddr4DdpSharedClock : MEMORY_CONFIGURATION
  • Ddr4OneDpc : MEMORY_CONFIGURATION
  • ddrFreq : MEMORY_INFO_DATA
  • DdrFreqLimit : MEMORY_CONFIGURATION
  • ddrFreqMax : MEMORY_INFO_DATA
  • DdrRfim : CNVI_PREMEM_CONFIG
  • DdrType : MEMORY_INFO_DATA
  • DebugHook : SA_FUNCTION_CALLS
  • DebugInterfaceEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugInterfaceLockEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • DebugPrint : SA_FUNCTION_CALLS
  • DebugValue : MEMORY_CONFIGURATION
  • DeepstTcState : TCSS_DATA
  • DefaultCsOutput : SERIAL_IO_SPI_CONFIG
  • DekelFwVersionMajor : CPU_PCIE_HOB
  • DekelFwVersionMinor : CPU_PCIE_HOB
  • DekelSquelchWa : CPU_PCIE_RP_PREMEM_CONFIG
  • DeltaT12PowerCycleDelay : GRAPHICS_PEI_PREMEM_CONFIG
  • Desc : CACHE_DESCRIPTOR_INFO
  • DevEnConfig : TCSS_PEI_PREMEM_CONFIG
  • Device : PCH_DEVICE_INTERRUPT_CONFIG
  • Device4Enable : HOST_BRIDGE_PEI_CONFIG
  • DeviceId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • DeviceResetDelay : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • DeviceStatus : _THC_PROTOCOL
  • DevIntConfig : PCH_INTERRUPT_CONFIG
  • DevSlp : PCH_SATA_PORT_CONFIG
  • DevSlpResetConfig : PCH_SATA_PORT_CONFIG
  • DfdRestoreEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • DgrEnable : DXE_CPU_POLICY_PROTOCOL
  • DgrSkipOemExceptionHandler : DXE_CPU_POLICY_PROTOCOL
  • DgrSpaEnable : DXE_CPU_POLICY_PROTOCOL
  • DgrStateSaveProtect : DXE_CPU_POLICY_PROTOCOL
  • DidInitStat : ME_PEI_PREMEM_CONFIG
  • Dimm : SA_ADDRESS_DECODE
  • DimmCapacity : DIMM_INFO
  • DIMMDFE : MEMORY_CONFIGURATION
  • DIMMODTCA : MEMORY_CONFIGURATION
  • DIMMODTT : MEMORY_CONFIGURATION
  • DIMMRONT : MEMORY_CONFIGURATION
  • dimmSize : MEMORY_INFO_DATA
  • DimmsSpdData : MEMORY_INFO_DATA
  • DimmStatus : MEMORY_INFO_DATA
  • Direction : GPIO_CONFIG
  • Disable : _WDT_PROTOCOL
  • DisableAndLock : PCH_WDT_PREMEM_CONFIG
  • DisableChannel : MEMORY_CONFIGURATION
  • DisableClkReqMsg : CPU_PCIE_HOB
  • DisableCpuReplacedPolling : ME_PEI_PREMEM_CONFIG
  • DisableD0I3SettingForHeci : ME_PEI_CONFIG
  • DisableDsxAcPresentPulldown : PCH_PM_CONFIG
  • DisableEnergyReport : PCH_PM_CONFIG
  • DisableMessageCheck : ME_PEI_PREMEM_CONFIG
  • DisableNativePowerButton : PCH_PM_CONFIG
  • DisablePerAtomMask : OVERCLOCKING_PREMEM_CONFIG
  • DisablePerCoreMask : OVERCLOCKING_PREMEM_CONFIG
  • DisableProcHotOut : CPU_POWER_MGMT_TEST_CONFIG
  • DisableTurboGt : GRAPHICS_PEI_CONFIG
  • DisableVrThermalAlert : CPU_POWER_MGMT_TEST_CONFIG
  • DisconnectAllTpms : BOOT_GUARD_INFO
  • DismSize : GRAPHICS_PEI_PREMEM_CONFIG
  • DisPgCloseIdleTimeout : MEMORY_CONFIGURATION
  • DisplayAudioLink : GRAPHICS_PEI_PREMEM_CONFIG
  • DisplayFusaConfigEnable : FUSA_CONFIG
  • DitoVal : PCH_SATA_PORT_CONFIG
  • DivU64x64 : SA_FUNCTION_CALLS
  • DlvrBypassModeEnable : OVERCLOCKING_PREMEM_CONFIG
  • DlvrRfiEnable : CPU_POWER_MGMT_VR_CONFIG
  • DlvrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • DlvrSpreadSpectrumPercentage : CPU_POWER_MGMT_VR_CONFIG
  • DmaBufferSize : VTD_CONFIG
  • DmaControlGuarantee : VTD_CONFIG
  • DmaEnable : SERIAL_IO_UART_CONFIG
  • DmiAspm : PCIE_PEI_CONFIG
  • DmiAspmCtrl : CPU_DMI_PREMEM_CONFIG , PCH_DMI_CONFIG
  • DmiAspmL1ExitLatency : CPU_DMI_PREMEM_CONFIG
  • DmiBar : HOST_BRIDGE_PREMEM_CONFIG
  • DmicClockSelect : HDA_LINK_DMIC
  • DmiCdrRelock : CPU_DMI_PREMEM_CONFIG
  • DmiDeEmphasis : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiExtSync : PCIE_PEI_CONFIG
  • DmiGen3DsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3EndPointHint : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EndPointPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EqPh2Enable : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3EqPh3Method : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3ProgramStaticEq : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3RootPortPreset : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen3RxCtlePeaking : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiGen3UsPortRxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen3UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4DsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4Ltcpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpo : CPU_DMI_PREMEM_CONFIG
  • DmiGen4RtcoCpre : CPU_DMI_PREMEM_CONFIG
  • DmiGen4UsPortTxPreset : CPU_DMI_PREMEM_CONFIG
  • DmiHaAWC : THERMAL_CONFIG
  • DmiIot : PCIE_PEI_CONFIG
  • DmiMaxLinkSpeed : CPU_DMI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • DmiNewFom : CPU_DMI_PREMEM_CONFIG
  • DmiPowerReduction : PCH_DMI_CONFIG
  • DmiTsawEn : DMI_HW_WIDTH_CONTROL
  • DmVal : PCH_SATA_PORT_CONFIG
  • Done : MG_IMR_STATUS , TBT_IMR_STATUS
  • DownSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • DpcEnabled : TCSS_PCIE_PORT_POLICY
  • DpInExternalEn : DPIN_PREMEM_CONFIG
  • DpInPortConnectMap : DPIN_PREMEM_CONFIG
  • DqDqsMap : MEMORY_CONFIG_NO_CRC
  • DqMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DqPinsInterleaved : MEMORY_CONFIGURATION
  • DqsMapCpu2Dram : SA_MEMORY_DQDQS_MAPPING
  • DRAMDCA : MEMORY_CONFIGURATION
  • DspEnable : HDAUDIO_PREMEM_CONFIG
  • DspFeatureMask : HDAUDIO_DXE_CONFIG
  • DspUaaCompliance : HDAUDIO_PREMEM_CONFIG
  • dTpm12Deactivated : HECI_FW_STS4_REGISTER
  • DualTauBoost : CPU_POWER_MGMT_BASIC_CONFIG
  • DynamicMemoryBoost : MEMORY_CONFIGURATION
  • DynamicMemoryBoostTrainingFailed : MEMORY_INFO_DATA
  • DynamicPowerGating : PCH_SMBUS_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- e -

  • EccDftEn : MEMORY_CONFIGURATION
  • EccErrInjAddress : MEMORY_CONFIGURATION
  • EccErrInjCount : MEMORY_CONFIGURATION
  • EccErrInjMask : MEMORY_CONFIGURATION
  • EcCmd : BGPDT
  • EcCmdClose : BGPDT
  • EcCmdGetSvn : BGPDT
  • EcCmdLock : BIOS_GUARD_CONFIG
  • EcCmdOpen : BGPDT
  • EcCmdPortTest : BGPDT
  • EcCmdProvisionEav : BIOS_GUARD_CONFIG
  • EccSupport : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • EcData : BGPDT
  • EcSvn : BGUP_HEADER
  • ECT : MEMORY_CONFIGURATION
  • EdramBar : HOST_BRIDGE_PREMEM_CONFIG
  • EdramTestMode : HOST_BRIDGE_PEI_CONFIG
  • EfiHobGuidType : _TXT_INFO_HOB , AMT_PET_QUEUE_HOB , BIOSGUARD_HOB , CPU_DMI_HOB , CPU_PCIE_HOB , IPU_DATA_HOB , PCH_DMI_HOB , SA_DATA_HOB , SA_PEG_HOB , TCSS_DATA_HOB , TCSS_DATA_SSID_HOB
  • EightCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Eist : CPU_POWER_MGMT_TEST_CONFIG
  • ElectricalConfig : GPIO_CONFIG
  • Enable : GBE_CONFIG , HDA_LINK_DMIC , HDA_LINK_HDA , HDA_LINK_SNDW , HDA_LINK_SSP , HDAUDIO_PREMEM_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_SPI , ISH_UART , PCH_MEMORY_THROTTLING , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SATA_CONFIG , TSN_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , XDCI_CONFIG
  • Enable8254ClockGating : PCH_IOAPIC_CONFIG
  • Enable8254ClockGatingOnS3 : PCH_IOAPIC_CONFIG
  • EnableAbove4GBMmio : HOST_BRIDGE_PREMEM_CONFIG
  • EnableAllThermalFunctions : CPU_POWER_MGMT_TEST_CONFIG
  • EnableC6Dram : CPU_SECURITY_PREMEM_CONFIG
  • EnabledCoreCount : SMBIOS_PROCESSOR_INFO
  • EnableDitoConfig : PCH_SATA_PORT_CONFIG
  • EnableDmaBuffer : VTD_CONFIG
  • EnabledStates : FIVR_EXT_RAIL_CONFIG
  • EnableEpbPeciOverride : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableFastMsrHwpReq : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoEppGrouping : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableHwpAutoPerCorePstate : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbm : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableItbmDriver : CPU_POWER_MGMT_BASIC_CONFIG
  • EnableMinVoltageOverride : CPU_POWER_MGMT_VR_CONFIG
  • EnableMode : TRACE_HUB_CONFIG
  • EnablePerCorePState : CPU_POWER_MGMT_BASIC_CONFIG
  • EnablePort8xhDecode : PCIE_COMMON_CONFIG
  • EnablePwrDn : MEMORY_CONFIGURATION
  • EnablePwrDnLpddr : MEMORY_CONFIGURATION
  • EnableSgx : CPU_SECURITY_PREMEM_CONFIG
  • EnableTcssCovTypeA : TCSS_MISC_PEI_CONFIG
  • EnableVsysCritical : CPU_POWER_MGMT_VR_CONFIG
  • EnclosureSupport : SATA_CONFIG
  • EnCmdRate : MEMORY_CONFIGURATION
  • End : SPD_OFFSET_TABLE
  • EndOfPostMessage : ME_PEI_CONFIG
  • EndPointAspm : PCIE_DEVICE_OVERRIDE
  • EndPointVendorIdDeviceId : SA_PEG_DATA
  • EnergyEfficientPState : CPU_POWER_MGMT_TEST_CONFIG
  • EnergyEfficientTurbo : CPU_POWER_MGMT_TEST_CONFIG
  • ENF : HECI_FW_STS6_REGISTER
  • EnforceEDebugMode : ME_PEI_CONFIG
  • EnhancedInterleave : MEMORY_CONFIGURATION
  • EnhancePort8xhDecoding : PCH_LPC_PREMEM_CONFIG
  • Entity : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EntityInstance : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EpBar : HOST_BRIDGE_PREMEM_CONFIG
  • EpgEnable : MEMORY_CONFIGURATION
  • EqPh23Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3Bypass : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • EqPh3LaneParam : CPU_PCIE_CONFIG
  • Erase : _BIOSGUARD_PROTOCOL
  • ERDMPRTC2D : MEMORY_CONFIGURATION
  • ERDTC2D : MEMORY_CONFIGURATION
  • Error : HECI_FW_STS6_REGISTER
  • ErrorCode : HECI_FWS_REGISTER , MG_IMR_STATUS , TBT_IMR_STATUS
  • ErrorCorrectionType : SMBIOS_CACHE_INFO
  • ErrorType : FSP_ERROR_INFO_HOB
  • EsataSpeedLimit : SATA_CONFIG
  • ESC : HECI_FW_STS5_REGISTER
  • EspiPmHAE : PCH_ESPI_CONFIG
  • EspiSlaveSmiRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • Etvb : OVERCLOCKING_PREMEM_CONFIG
  • EventData : ASF_START_WDT , HECI_ASF_PUSH_PROGRESS_CODE
  • EventData1 : ASF_MESSAGE , PET_ALERT
  • EventData2 : ASF_MESSAGE , PET_ALERT
  • EventData3 : PET_ALERT
  • EventData4 : PET_ALERT
  • EventData5 : PET_ALERT
  • EventOffset : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSensorType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSeverity : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventSourceType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EventType : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • EWRTC2D : MEMORY_CONFIGURATION
  • ExecLim : BGPDT
  • Execute : _BIOSGUARD_PROTOCOL
  • ExeStatus : HECI_FW_STS6_REGISTER
  • ExitOnFailure : MEMORY_CONFIGURATION
  • ExpanderNo : CPU_PCIE_GPIO_INFO , PCIE_GPIO
  • ExtData : _BIOS_OS_DATA_REGION
  • ExtendedBankHashing : MEMORY_CONFIGURATION
  • ExtendedBiosDecodeRangeBase : SPI_CONFIG
  • ExtendedBiosDecodeRangeEnable : SPI_CONFIG
  • ExtendedBiosDecodeRangeLimit : SPI_CONFIG
  • ExtendedData : SMBIOS_TABLE_TYPE130
  • ExtendMeMeasuredBoot : ME_DXE_CONFIG
  • External : PCH_SATA_PORT_CONFIG
  • ExternalClockInMHz : SMBIOS_PROCESSOR_INFO
  • ExtStatCode1 : HECI_GS_SHDW_REGISTER
  • ExtStatCode2 : HECI_GS_SHDW_REGISTER
  • ExtSync : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG
  • ExtTemperatureSupport : MEMORY_CONFIGURATION
  • ExtV1p05Rail : PCH_FIVR_CONFIG
  • ExtVnnRail : PCH_FIVR_CONFIG
  • ExtVnnRailSx : PCH_FIVR_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- f -

  • FastPkgCRampDisable : CPU_POWER_MGMT_VR_CONFIG
  • FatalErrorReport : TCSS_PCIE_PORT_POLICY
  • FClkFrequency : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Features : CPU_INFO
  • FiaProgramming : CPU_PCIE_CONFIG
  • Fields : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • FirstByte : SFAM_DATA
  • FirstDimmBitMask : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstDimmBitMaskEcc : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • FirstMebxBoot : INVOCATION_CODE_BITS
  • FiveCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FivrDynPm : PCH_FIVR_CONFIG
  • FivrEfficiency : OVERCLOCKING_PREMEM_CONFIG
  • FivrRfiFrequency : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpectrumEnable : CPU_POWER_MGMT_VR_CONFIG
  • FivrSpreadSpectrum : CPU_POWER_MGMT_VR_CONFIG
  • Flags : _BIOS_OS_DATA_REGION , _TXT_INFO_DATA , MBP_ITEM_HEADER , THC_HID_OVER_SPI
  • FlashErase : _PCH_SPI_PROTOCOL
  • FlashErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • FlashErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • FlashRead : _PCH_SPI_PROTOCOL
  • FlashReadJedecId : _PCH_SPI_PROTOCOL
  • FlashReadSfdp : _PCH_SPI_PROTOCOL
  • FlashReadStatus : _PCH_SPI_PROTOCOL
  • FlashWrite : _PCH_SPI_PROTOCOL
  • FlashWriteStatus : _PCH_SPI_PROTOCOL
  • FllOcModeEn : OVERCLOCKING_PREMEM_CONFIG
  • FllOverclockMode : OVERCLOCKING_PREMEM_CONFIG
  • FomsCp : CPU_PCIE_ROOT_PORT_CONFIG
  • Force1Dpc : MEMORY_CONFIGURATION
  • ForceBootPolicy : HECI_FW_STS6_REGISTER
  • ForceLtrOverride : PCIE_DEVICE_OVERRIDE , TCSS_PCIE_PORT_POLICY
  • ForcePowerFlow : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • ForceSingleRank : MEMORY_CONFIGURATION
  • ForceSingleSubchannel : MEMORY_CONFIGURATION
  • ForcMebxSyncUp : AMT_PEI_CONFIG
  • FourCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • FpfDisable : HECI_FW_STS6_REGISTER
  • FpfSocConfigLock : HECI_FW_STS6_REGISTER
  • FptBad : HECI_FWS_REGISTER
  • FreqLimitMixedConfig : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_1R1R_8GB_16GB : MEMORY_CONFIGURATION
  • FreqLimitMixedConfig_2R2R : MEMORY_CONFIGURATION
  • Frequency : THC_HID_OVER_SPI
  • FtBupLdFlr : HECI_FWS_REGISTER
  • FullMng : MEFWCAPS_SKU
  • Function : PCH_DEVICE_INTERRUPT_CONFIG
  • FusaConfigEnable : FUSA_CONFIG
  • FusaRunPeriodicScanBist : FUSA_CONFIG
  • FusaRunStartupArrayBist : FUSA_CONFIG
  • FusaRunStartupScanBist : FUSA_CONFIG
  • FwInEnfFlow : HECI_FW_STS4_REGISTER
  • FwInitComplete : HECI_FWS_REGISTER
  • FwNeedsWarmResetFlag : ICC_MESSAGE_RESP_DATA
  • FwProgress : AMT_PEI_CONFIG
  • FwSku : HECI_FW_STS3_REGISTER
  • FwUnconfiguration : INVOCATION_CODE_BITS
  • FwUpdate : INVOCATION_CODE_BITS
  • FwUpdateInprogress : HECI_FWS_REGISTER
  • FwUpdForcedSB : HECI_GS_SHDW_REGISTER
  • FwUpdIpu : HECI_GS_SHDW_REGISTER
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- g -

  • GdxcBar : HOST_BRIDGE_PREMEM_CONFIG
  • GearRatio : MEMORY_CONFIGURATION
  • Gen3Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen3SwEqAlwaysAttempt : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqEnableVocTest : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqJitterDwellTime : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqJitterErrorTarget : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqNumberOfPresets : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqVocDwellTime : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3SwEqVocErrorTarget : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Gen3Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4EqPh3Method : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen4Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Dptp : CPU_PCIE_ROOT_PORT_CONFIG
  • Gen5Uptp : CPU_PCIE_ROOT_PORT_CONFIG
  • GetAppletProperty : _ME_JHI_PROTOCOL
  • GetBankLocatorString : _MEMORY_DXE_CONFIG
  • GetControllerName : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetCpuTime : SA_FUNCTION_CALLS
  • GetDeviceLocatorString : _MEMORY_DXE_CONFIG
  • GetDriverName : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetDriverVersion : _GOP_COMPONENT_NAME2_PROTOCOL
  • GetHeciInterruptMode : _HECI_ACCESS_
  • GetHeciPch : _HECI_ACCESS_
  • GetMeMode : _HECI_PPI , _HECI_PROTOCOL
  • GetMemoryVdd : SA_FUNCTION_CALLS
  • GetMeStatus : _HECI_PPI , _HECI_PROTOCOL
  • GetNextHeciAccess : _HECI_ACCESS_
  • GetPciDeviceAddress : SA_FUNCTION_CALLS
  • GetPcieDeviceAddress : SA_FUNCTION_CALLS
  • GetPlatformDockStatus : GOP_POLICY_PROTOCOL
  • GetPlatformLidStatus : GOP_POLICY_PROTOCOL
  • GetRandomNumber : SA_FUNCTION_CALLS
  • GetRegionAddress : _PCH_SPI_PROTOCOL
  • GetRtcCmos : SA_FUNCTION_CALLS
  • GetRtcTime : SA_FUNCTION_CALLS
  • GetSessionInfo : _ME_JHI_PROTOCOL
  • GetSessionsCount : _ME_JHI_PROTOCOL
  • GetSpdData : SA_FUNCTION_CALLS
  • GetVbtData : GOP_POLICY_PROTOCOL
  • GetVersionInfo : _ME_JHI_PROTOCOL
  • GfxTurboIMON : GRAPHICS_DXE_CONFIG
  • GlobalResetMasksOverride : PCH_PM_CONFIG
  • GlobalSmi : PCH_LOCK_DOWN_CONFIG
  • GmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GmAdr64 : GRAPHICS_PEI_PREMEM_CONFIG
  • GnaEnable : GNA_CONFIG
  • GopOverrideGuid : GOP_POLICY_PROTOCOL
  • GopVersion : GRAPHICS_DXE_CONFIG
  • GpioIrqRoute : PCH_INTERRUPT_CONFIG
  • GpioNo : CPU_PCIE_GPIO_INFO , PCIE_GPIO
  • GpioOverride : PCH_GENERAL_PREMEM_CONFIG
  • GpioPad : SA_GPIO_INFO_PCIE
  • GpioPullN : IOM_AUX_ORI_PAD_CONFIG
  • GpioPullP : IOM_AUX_ORI_PAD_CONFIG
  • GpioSupport : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO , PEG_GPIO_DATA
  • GraphicFusaConfigEnable : FUSA_CONFIG
  • GraphicsConfigPtr : GRAPHICS_PEI_CONFIG
  • GtCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • GtClosEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • GtExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • GtFreqMax : GRAPHICS_PEI_CONFIG
  • GtIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • GtMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • GtPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtPsmiSupport : GRAPHICS_PEI_PREMEM_CONFIG
  • GttMmAdr : GRAPHICS_PEI_PREMEM_CONFIG
  • GttSize : GRAPHICS_PEI_PREMEM_CONFIG
  • GtVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • GtVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • GuidHob : _CONFIG_BLOCK_HEADER , FSP_ERROR_INFO_HOB
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- h -

  • HaltAllowed : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • HardwareRemappedStorageConfig : RST_CONFIG
  • HdAudioLinkFrequency : HDAUDIO_CONFIG
  • HdcControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HddUnlock : RST_CONFIG
  • Header : _CONFIG_BLOCK , _CONFIG_BLOCK_TABLE_STRUCT , _DXE_ITBT_CONFIG , _HEAP_BIOS_SPEC_VER_ELEMENT , _HEAP_BIOSACM_ELEMENT , _MEMORY_DXE_CONFIG , _PEI_ITBT_CONFIG , ADR_CONFIG , AMT_DXE_CONFIG , AMT_PEI_CONFIG , BCLK_CONFIG , BIOS_GUARD_CONFIG , CNVI_CONFIG , CNVI_PREMEM_CONFIG , CPU_CONFIG , CPU_CONFIG_LIB_PREMEM_CONFIG , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_CONFIG , CPU_PCIE_RP_PREMEM_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , CPU_TRACE_HUB_PREMEM_CONFIG , CPU_TXT_PREMEM_CONFIG , DPIN_PREMEM_CONFIG , FUSA_CONFIG , GBE_CONFIG , GNA_CONFIG , GPIO_DXE_CONFIG , GRAPHICS_DXE_CONFIG , GRAPHICS_PEI_CONFIG , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , HOST_BRIDGE_PEI_CONFIG , HOST_BRIDGE_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , HYBRID_STORAGE_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_I3C_CONFIG , ISH_PREMEM_CONFIG , ME_DXE_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG , MEMORY_CONFIG_NO_CRC , MEMORY_CONFIGURATION , OVERCLOCKING_PREMEM_CONFIG , PCH_DCI_PREMEM_CONFIG , PCH_DMI_CONFIG , PCH_ESPI_CONFIG , PCH_FIVR_CONFIG , PCH_FLASH_PROTECTION_CONFIG , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_HSIO_CONFIG , PCH_HSIO_PCIE_PREMEM_CONFIG , PCH_HSIO_PREMEM_CONFIG , PCH_HSIO_SATA_PREMEM_CONFIG , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_LOCK_DOWN_CONFIG , PCH_LPC_PREMEM_CONFIG , PCH_P2SB_CONFIG , PCH_PCIE_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG , PCH_WDT_PREMEM_CONFIG , PCIE_DXE_CONFIG , PCIE_PEI_CONFIG , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , PCIE_PREMEM_CONFIG , PCIE_RP_DXE_CONFIG , PSF_CONFIG , RST_CONFIG , RTC_CONFIG , SA_MISC_PEI_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_CONFIG , SERIAL_IO_CONFIG , SI_CONFIG , SI_PREMEM_CONFIG , SPI_CONFIG , TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG , THC_CONFIG , THERMAL_CONFIG , TSN_CONFIG , USB2_PHY_CONFIG , USB3_HSIO_CONFIG , USB_CONFIG , VMD_PEI_CONFIG , VTD_CONFIG , VTD_DXE_CONFIG
  • Health : BIST_HOB_DATA
  • Heci1BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci2BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3BarAddress : ME_PEI_PREMEM_CONFIG
  • Heci3Enabled : ME_PEI_CONFIG
  • HeciCommunication2 : ME_PEI_PREMEM_CONFIG
  • HeciFirmwareStatus : _HECI_CONTROL_
  • HeciFullTrace : ME_PEI_PREMEM_CONFIG
  • HeciListCh : HECI_GS_SHDW_REGISTER
  • HeciReceive : _HECI_CONTROL_
  • HeciReset : _HECI_CONTROL_
  • HeciSend : _HECI_CONTROL_
  • HeciTimeouts : ME_PEI_PREMEM_CONFIG
  • HgDelayAfterHoldReset : HYBRID_GRAPHICS_CONFIG
  • HgDelayAfterPwrEn : HYBRID_GRAPHICS_CONFIG
  • HgMode : HYBRID_GRAPHICS_CONFIG
  • HgSubSystemId : HYBRID_GRAPHICS_CONFIG
  • HgSupport : HYBRID_GRAPHICS_CONFIG
  • HideGpioAcpiDevice : GPIO_DXE_CONFIG
  • HideUnConfigureMeConfirm : AMT_DXE_CONFIG
  • HidOverSpi : THC_PORT
  • HobBufferSize : MEMORY_CONFIGURATION
  • HoldRst : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • HorizontalResolution : GRAPHICS_PEI_CONFIG
  • HostC10ReportEnable : PCH_ESPI_CONFIG
  • HostSoftPadOwn : GPIO_CONFIG
  • HotPlug : PCH_SATA_PORT_CONFIG
  • HotPlugRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • HpetBusNum : PCH_INFO_HOB
  • HsiiEnable : USB_CONFIG
  • HsioCtrlAdaptOffsetCfg : HSIO_PARAMETERS
  • HsioCtrlAdaptOffsetCfgEnable : HSIO_PARAMETERS
  • HsioFilterSelN : HSIO_PARAMETERS
  • HsioFilterSelNEnable : HSIO_PARAMETERS
  • HsioFilterSelP : HSIO_PARAMETERS
  • HsioFilterSelPEnable : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnRes : HSIO_PARAMETERS
  • HsioOlfpsCfgPullUpDwnResEnable : HSIO_PARAMETERS
  • HsioRxGen1EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen1EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen2EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMag : PCH_HSIO_SATA_PORT_LANE
  • HsioRxGen3EqBoostMagEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioRxSetCtle : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioRxSetCtleEnable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxDeEmph : HSIO_PARAMETERS
  • HsioTxDeEmphEnable : HSIO_PARAMETERS
  • HsioTxDownscaleAmp : HSIO_PARAMETERS
  • HsioTxDownscaleAmpEnable : HSIO_PARAMETERS
  • HsioTxGen1DeEmph : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DeEmphEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen1DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DeEmph3p5 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph3p5Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0 : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmph6p0Enable : PCH_HSIO_PCIE_LANE_CONFIG
  • HsioTxGen2DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen2DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmph : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DeEmphEnable : PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmp : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxGen3DownscaleAmpEnable : PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • HsioTxRate0UniqTran : HSIO_PARAMETERS
  • HsioTxRate0UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate1UniqTran : HSIO_PARAMETERS
  • HsioTxRate1UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate2UniqTran : HSIO_PARAMETERS
  • HsioTxRate2UniqTranEnable : HSIO_PARAMETERS
  • HsioTxRate3UniqTran : HSIO_PARAMETERS
  • HsioTxRate3UniqTranEnable : HSIO_PARAMETERS
  • HslOri : TCSS_IOM_ORI_OVERRIDE
  • HsPhyFwBuild : CPU_PCIE_HOB
  • HsPhyFwEvBitProgMajor : CPU_PCIE_HOB
  • HsPhyFwEvBitProgMinor : CPU_PCIE_HOB
  • HsPhyFwHotFix : CPU_PCIE_HOB
  • HsPhyFwProdMajor : CPU_PCIE_HOB
  • HsPhyFwProdMinor : CPU_PCIE_HOB
  • HsPhyMap : CPU_PCIE_HOB
  • HsPhyRecipeVersionMajor : CPU_PCIE_HOB
  • HsPhyRecipeVersionMinor : CPU_PCIE_HOB
  • Hsti : DXE_SI_POLICY_PROTOCOL
  • HstiSize : DXE_SI_POLICY_PROTOCOL
  • HwEqGen3CoeffList : PCIE_COMMON_CONFIG
  • HwEqGen4CoeffList : CPU_PCIE_CONFIG
  • Hwp : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpInterruptControl : CPU_POWER_MGMT_BASIC_CONFIG
  • HwpLock : CPU_POWER_MGMT_BASIC_CONFIG
  • HybridStorageMode : HYBRID_STORAGE_CONFIG
  • HyperThreading : CPU_CONFIG_LIB_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- i -

  • I2cDeviceConfig : SERIAL_IO_CONFIG
  • IaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • IaIccMax : OVERCLOCKING_PREMEM_CONFIG
  • IaIccUnlimitedMode : OVERCLOCKING_PREMEM_CONFIG
  • IanaId : ASF_BOOT_OPTIONS
  • IaSirpEnable : OVERCLOCKING_PREMEM_CONFIG
  • Ibecc : MEMORY_CONFIGURATION
  • IbeccErrInjAddress : MEMORY_CONFIGURATION
  • IbeccErrInjControl : MEMORY_CONFIGURATION
  • IbeccErrInjCount : MEMORY_CONFIGURATION
  • IbeccErrInjMask : MEMORY_CONFIGURATION
  • IbeccOperationMode : MEMORY_CONFIGURATION
  • IbeccProtectedRangeBase : MEMORY_CONFIGURATION
  • IbeccProtectedRangeEnable : MEMORY_CONFIGURATION
  • IbeccProtectedRangeMask : MEMORY_CONFIGURATION
  • IccLimit : CPU_POWER_MGMT_VR_CONFIG
  • IccMax : CPU_POWER_MGMT_VR_CONFIG , FIVR_EXT_RAIL_CONFIG
  • IccMaximum : FIVR_EXT_RAIL_CONFIG
  • IccProgSts : HECI_GS_SHDW_REGISTER
  • Idd3n : MEMORY_CONFIGURATION
  • Idd3p : MEMORY_CONFIGURATION
  • IderStateChange : INVOCATION_CODE_BITS
  • IDispCodecDisconnect : HDAUDIO_PREMEM_CONFIG
  • IDispLinkFrequency : HDAUDIO_PREMEM_CONFIG
  • IDispLinkTmode : HDAUDIO_PREMEM_CONFIG
  • IdleLtr : THC_PORT
  • IedSize : SA_MISC_PEI_PREMEM_CONFIG
  • IgdBlcConfig : GRAPHICS_DXE_CONFIG
  • IgdBootType : GRAPHICS_DXE_CONFIG
  • IgdDvmt50PreAlloc : GRAPHICS_PEI_PREMEM_CONFIG
  • IgdDvmtMemSize : GRAPHICS_DXE_CONFIG
  • IgdPanelScaling : GRAPHICS_DXE_CONFIG
  • IgdPanelType : GRAPHICS_DXE_CONFIG
  • ImguClkOutEn : IPU_PREMEM_CONFIG
  • ImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • ImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • ImrEnabled : PCIE_IMR_CONFIG
  • ImrRpLocation : PCIE_IMR_CONFIG
  • ImrRpSelection : PCIE_IMR_CONFIG
  • ImrSize : PCIE_IMR_CONFIG
  • InfDfxPwrEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • InfPhaseCode : HECI_GS_SHDW_REGISTER
  • InitHeci : _HECI_PROTOCOL
  • Initialize : _ME_JHI_PROTOCOL
  • InitializeHeci : _HECI_PPI
  • InitPcieAspmAfterOprom : CPU_PCIE_HOB , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , SA_PEG_HOB
  • InputReportBodyAddress : THC_HID_OVER_SPI
  • InputReportHeaderAddress : THC_HID_OVER_SPI
  • InstallContent : _ME_JHI_PROTOCOL
  • InstalledSize : SMBIOS_CACHE_INFO
  • InstalledSize2 : SMBIOS_CACHE_INFO
  • InstallFile : _ME_JHI_PROTOCOL
  • Instance : FSP_ERROR_INFO_HOB
  • IntegratedTouch : MEFWCAPS_SKU
  • IntelAmtEnabled : ME_CAP
  • IntelAmtFw : ME_CAP
  • IntelAmtFwStandard : ME_CAP
  • IntelCLS : MEFWCAPS_SKU
  • IntelKVM : ME_CAP
  • IntelKVMEnabled : ME_CAP
  • IntEnable : HECI_CONTROL_STATUS_REGISTER
  • IntendedFreq : CPU_INFO
  • Interface : _OC_MAILBOX_FULL , _PCODE_MAILBOX_FULL
  • InterfaceData : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • InterlockSw : PCH_SATA_PORT_CONFIG
  • InternalGraphics : GRAPHICS_PEI_PREMEM_CONFIG
  • InterruptConfig : GPIO_CONFIG
  • InterruptPinMuxing : THC_PORT
  • IntGenerate : HECI_CONTROL_STATUS_REGISTER
  • IntPing : SA_XDCI_IRQ_INT_CONFIG
  • IntruderDetRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • IntStatus : HECI_CONTROL_STATUS_REGISTER
  • IntX : PCH_DEVICE_INTERRUPT_CONFIG
  • InvokeEDebugMode : HECI_FWS_REGISTER
  • InvokeMEBx : HECI_GS_SHDW_REGISTER
  • IoApicEntry24_119 : PCH_IOAPIC_CONFIG
  • IoApicId : PCH_IOAPIC_CONFIG
  • IoeDebugEn : PCH_GENERAL_PREMEM_CONFIG
  • IomAuxPortPad : TCSS_IOM_PEI_CONFIG
  • IomBeforeEnteringTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IomConfig : TCSS_PEI_CONFIG
  • IomFwEngrVersion : TCSS_DATA
  • IomFwVersion : TCSS_DATA
  • IomInterface : TCSS_IOM_PEI_CONFIG
  • IOMReady : TCSS_DATA
  • IomStayInTCColdSeconds : TCSS_MISC_PEI_CONFIG
  • IopFusaConfigEnable : FUSA_CONFIG
  • IopFusaMcaCheckEnable : FUSA_CONFIG
  • IoRead16 : SA_FUNCTION_CALLS
  • IoRead32 : SA_FUNCTION_CALLS
  • IoRead8 : SA_FUNCTION_CALLS
  • IotgPllSscEn : PCH_GENERAL_PREMEM_CONFIG
  • IoWrite16 : SA_FUNCTION_CALLS
  • IoWrite32 : SA_FUNCTION_CALLS
  • IoWrite8 : SA_FUNCTION_CALLS
  • IpTiming : HOB_SAGV_TIMING_OUT
  • IpuEnable : IPU_PREMEM_CONFIG
  • IpuImrConfiguration : IPU_PREMEM_CONFIG
  • IpuSupport : IPU_DATA_HOB
  • IPV6 : MEFWCAPS_SKU
  • Irms : CPU_POWER_MGMT_VR_CONFIG
  • Irq : PCH_DEVICE_INTERRUPT_CONFIG , SA_XDCI_IRQ_INT_CONFIG
  • Irrt : RST_CONFIG
  • IrrtOnly : RST_CONFIG
  • IsDMBRunning : MEMORY_INFO_DATA
  • ISH : MEFWCAPS_SKU
  • IsWdtEnabled : _WDT_PROTOCOL
  • IsWdtRequired : _WDT_PROTOCOL
  • ITbtConnectTopologyTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ItbtDmaEn : TCSS_DATA
  • ITbtDmaLtr : _PEI_ITBT_CONFIG
  • ItbtForcePower : TCSS_DATA
  • ITbtForcePowerOnTimeoutInMs : _ITBT_GENERIC_CONFIG
  • ITbtGenericConfig : _DXE_ITBT_CONFIG , _PEI_ITBT_CONFIG
  • ItbtPcieFuncMap : TCSS_DATA
  • ITbtPcieRootPortEn : _ITBT_ROOTPORT_CONFIG
  • ItbtPcieRpEn : TCSS_DATA
  • ItbtPcieSegMap : TCSS_DATA
  • ITbtPcieTunnelingForUsb4 : _ITBT_GENERIC_CONFIG
  • ITbtResourceConfig : _DXE_ITBT_CONFIG
  • ITbtRootPortConfig : _PEI_ITBT_CONFIG
  • ITbtRtd3 : _DXE_ITBT_GENERIC_CONFIG
  • ITbtRtd3ExitDelay : _DXE_ITBT_GENERIC_CONFIG
  • ITbtSecurityLevel : _ITBT_GENERIC_CONFIG
  • ITbtVproDockSupport : _DXE_ITBT_GENERIC_CONFIG
  • ItbtXdciEn : TCSS_DATA
  • ItbtXhciEn : TCSS_DATA
  • ItdThrottleEnable : OVERCLOCKING_PREMEM_CONFIG
  • ItemId : MBP_ITEM_HEADER
  • IuerStatusVal : GRAPHICS_DXE_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- j -

  • JedecTiming : HOB_SAGV_TIMING_OUT
  • JtagC10PowerGateDisable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • JWRL : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- k -

  • KeepEarlyTrace : PCH_DCI_PREMEM_CONFIG
  • KmId : HECI_FW_STS6_REGISTER
  • KtDeviceEnable : ME_PEI_PREMEM_CONFIG
  • KVM : MEFWCAPS_SKU
  • KvmEnabled : SMBIOS_TABLE_TYPE130
  • KvmStateChange : INVOCATION_CODE_BITS
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- l -

  • L1RpCtl : PCH_DMI_CONFIG
  • L1sCommonModeRestoreTime : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnScale : PCIE_DEVICE_OVERRIDE
  • L1sTpowerOnValue : PCIE_DEVICE_OVERRIDE
  • L1SubStates : CPU_PCIE_HOB
  • L1SubstatesCapMask : PCIE_DEVICE_OVERRIDE
  • L1SubstatesCapOffset : PCIE_DEVICE_OVERRIDE
  • Lane : PCH_HSIO_PCIE_PREMEM_CONFIG
  • LaneUsed : IPU_PREMEM_CONFIG
  • LanWakeFromDeepSx : PCH_WAKE_CONFIG
  • LastByte : SFAM_DATA
  • LastPage : BIOSGUARD_LOG
  • LastSfam : BGPDT
  • LatchEventsC10Exit : PCH_PM_CONFIG
  • LcpPdBase : _BIOS_OS_DATA_REGION
  • LcpPdSize : _BIOS_OS_DATA_REGION
  • LCT : MEMORY_CONFIGURATION
  • LctCmdEyeWidth : MEMORY_CONFIGURATION
  • LedEnable : SATA_CONFIG
  • LedLocate : RST_CONFIG
  • LeftShift64 : SA_FUNCTION_CALLS
  • LegacyIoLowLatency : PCH_GENERAL_CONFIG
  • LegacyOrom : RST_CONFIG
  • Length : MBP_ITEM_HEADER
  • Level : CACHE_DESCRIPTOR_INFO
  • Lfsr0Mask : MEMORY_CONFIGURATION
  • Lfsr1Mask : MEMORY_CONFIGURATION
  • LgmrEnable : PCH_ESPI_CONFIG
  • LimitPacketSize : THC_PORT
  • LinkActiveRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • LinkDownGpios : CPU_PCIE_RP_PREMEM_CONFIG
  • LinkEqRegister : _PCH_PCIE_SMI_DISPATCH_PROTOCOL
  • LnkErrType1Register : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • LocalTransmitterOverrideEnable : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • LocalWakeupTimer : ME_CAP
  • LockBoxData : SMRAM_CPU_INFO
  • LockBoxSize : SMRAM_CPU_INFO
  • LockConfig : GPIO_CONFIG
  • LockLinkConfiguration : PCH_ESPI_CONFIG
  • LockPTMregs : SA_MISC_PEI_PREMEM_CONFIG
  • LoggingOptions : BIOSGUARD_LOG
  • LogoPixelHeight : GRAPHICS_PEI_CONFIG
  • LogoPixelWidth : GRAPHICS_PEI_CONFIG
  • LogoPtr : GRAPHICS_PEI_CONFIG
  • LogoSize : GRAPHICS_PEI_CONFIG
  • LowPowerState : HECI_GS_SHDW_REGISTER
  • LowToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • Lp5BankMode : MEMORY_CONFIGURATION
  • Lp5CccConfig : MEMORY_CONFIGURATION
  • LpcBiosWpRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • LpcPmHAE : PCH_LPC_PREMEM_CONFIG
  • LpddrRttCa : MEMORY_CONFIGURATION
  • LpddrRttWr : MEMORY_CONFIGURATION
  • LpDqsOscEn : MEMORY_CONFIGURATION
  • LpMode : MEMORY_CONFIGURATION
  • LpmS0ixSubStateEnable : PCH_PM_CONFIG
  • LtrConfigLock : TCSS_PCIE_PORT_POLICY
  • LtrEnable : CPU_PCIE_PWR_OPT , GBE_CONFIG , TCSS_PCIE_PORT_POLICY
  • LtrHighIdleTimeOverride : USB_CONFIG
  • LtrLowIdleTimeOverride : USB_CONFIG
  • LtrMaxNoSnoopLatency : CPU_PCIE_PWR_OPT , TCSS_PCIE_PORT_POLICY
  • LtrMaxSnoopLatency : CPU_PCIE_PWR_OPT , TCSS_PCIE_PORT_POLICY
  • LtrMediumIdleTimeOverride : USB_CONFIG
  • LtrOverrideEnable : USB_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- m -

  • MachineCheckEnable : CPU_TEST_CONFIG
  • ManageabilityMode : AMT_PEI_CONFIG
  • ManufacturingLock : HECI_FW_STS6_REGISTER
  • MappingPchXhciUsbA : TCSS_MISC_PEI_CONFIG
  • MarginLimitCheck : MEMORY_CONFIGURATION
  • MarginLimitL2 : MEMORY_CONFIGURATION
  • MaxCacheSize : SMBIOS_CACHE_INFO
  • MaxCacheSupported : CPU_INFO
  • MaximumCacheSize2 : SMBIOS_CACHE_INFO
  • MaxRatio : PPM_CUSTOM_RATIO_TABLE
  • MaxRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MaxRttWr : MEMORY_CONFIGURATION
  • MaxSpeedInMHz : SMBIOS_PROCESSOR_INFO
  • MaxTurbo1Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo2Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo3Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo4Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo5Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo6Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo7Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurbo8Core : MSR_TURBO_RATIO_LIMIT_REGISTER
  • MbpSize : MBP_HEADER
  • MchBar : HOST_BRIDGE_PREMEM_CONFIG
  • MchRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • McPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • McRefresh2X : MEMORY_CONFIGURATION
  • McRefreshRate : MEMORY_CONFIGURATION
  • McSmiRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • MctpBroadcastCycle : ME_PEI_CONFIG
  • MdSocket : DIMM_INFO
  • MeasuredBoot : BOOT_GUARD_INFO
  • MeasuredBootPolicy : HECI_FW_STS6_REGISTER
  • MeBootOptionsPresent : HECI_FWS_REGISTER
  • MeBuildNo : ME_CAP
  • MebxDebugMsg : AMT_DXE_CONFIG
  • MebxGraphicsMode : AMT_DXE_CONFIG
  • MebxNonUiTextMode : AMT_DXE_CONFIG
  • MebxUiTextMode : AMT_DXE_CONFIG
  • MebxVersion : SMBIOS_TABLE_TYPE131
  • MeEnabled : ME_CAP
  • MeFwDownGrade : ME_DXE_CONFIG
  • MeHotFixNo : ME_CAP
  • MeJhiSupport : ME_DXE_CONFIG
  • MeMajorVer : ME_CAP
  • MemInfoData : MEM_INFO_PROTOCOL
  • MeMinorVer : ME_CAP
  • MemoryLock : RTC_CONFIG
  • MemorySpeedReducedWrongDimmSlot : MEMORY_INFO_DATA
  • MemoryThrottling : THERMAL_CONFIG
  • MemReg0Size : TRACE_HUB_CONFIG
  • memSize : MEMORY_INFO_DATA
  • MemTestOnWarmBoot : MEMORY_CONFIG_NO_CRC
  • MEMTST : MEMORY_CONFIGURATION
  • MeOperationMode : HECI_FWS_REGISTER
  • MeOperationState : HECI_FWS_REGISTER
  • MePowerGating : HECI_GS_SHDW_REGISTER
  • MeReportError : ME_DXE_CONFIG
  • MeResetWait : _HECI_PROTOCOL
  • MeRstCnt : HECI_FWS_REGISTER
  • Message : ASF_FRAMEWORK_MESSAGE
  • MessageType : ASF_DATA_HUB_MAP , ASF_FRAMEWORK_MESSAGE
  • MeUnconfigOnRtcClear : ME_PEI_CONFIG
  • MeWakeSts : PCH_PM_CONFIG
  • MfsFailure : HECI_GS_SHDW_REGISTER
  • MgFwVersion : MG_IMR_STATUS
  • MgImrStatus : TCSS_DATA
  • MicrocodePatchAddress : CPU_CONFIG
  • MinRingRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • MinVoltageC8 : CPU_POWER_MGMT_VR_CONFIG
  • MinVoltageRuntime : CPU_POWER_MGMT_VR_CONFIG
  • MiscConfig : TCSS_PEI_CONFIG , TCSS_PEI_PREMEM_CONFIG
  • Miso : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MlcSpatialPrefetcher : CPU_TEST_CONFIG
  • MlcStreamerPrefetcher : CPU_TEST_CONFIG
  • MmioRead16 : SA_FUNCTION_CALLS
  • MmioRead32 : SA_FUNCTION_CALLS
  • MmioRead64 : SA_FUNCTION_CALLS
  • MmioRead8 : SA_FUNCTION_CALLS
  • MmioSize : HOST_BRIDGE_PREMEM_CONFIG
  • MmioSizeAdjustment : HOST_BRIDGE_PREMEM_CONFIG
  • MmioWrite16 : SA_FUNCTION_CALLS
  • MmioWrite32 : SA_FUNCTION_CALLS
  • MmioWrite64 : SA_FUNCTION_CALLS
  • MmioWrite8 : SA_FUNCTION_CALLS
  • MobilePlatform : MEMORY_CONFIGURATION
  • Mode : CNVI_CONFIG , IEH_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG , THC_PORT
  • ModPhySusPgEnable : PCH_PM_CONFIG
  • Module0Lockstep : FUSA_CONFIG
  • Module1Lockstep : FUSA_CONFIG
  • ModulePartNum : DIMM_INFO
  • MonitorMwaitEnable : CPU_TEST_CONFIG
  • Mosi : ISH_SPI_PIN_CONFIG , SPI_PIN_MUX
  • MrcCall : MEMORY_CONFIG_NO_CRC
  • MrcChangeMargin : SA_MEMORY_FUNCTIONS
  • MrcChannelExist : SA_MEMORY_FUNCTIONS
  • MrcDelayNs : SA_FUNCTION_CALLS
  • MrcDramReset : SA_FUNCTION_CALLS
  • MrcFastBoot : _MEMORY_DXE_CONFIG , MEMORY_CONFIGURATION
  • MrcPrintf : SA_MEMORY_FUNCTIONS
  • MrcReturnFromSmc : SA_FUNCTION_CALLS
  • MrcSafeConfig : MEMORY_CONFIGURATION
  • MrcSignExtend : SA_MEMORY_FUNCTIONS
  • MrcTimeMeasure : _MEMORY_DXE_CONFIG , MEMORY_CONFIGURATION
  • MrcUpdateVref : SA_MEMORY_FUNCTIONS
  • MsegBase : _TXT_INFO_DATA
  • MsegSize : _TXT_INFO_DATA
  • MsHashEnable : MEMORY_CONFIGURATION
  • MsHashInterleaveBit : MEMORY_CONFIGURATION
  • MsHashMask : MEMORY_CONFIGURATION
  • MsiInterrupt : ISH_CONFIG
  • MultiVcEnable : TSN_CONFIG
  • MultiVcEnabled : CPU_PCIE_ROOT_PORT_CONFIG
  • MultU64x32 : SA_FUNCTION_CALLS
  • MvcEnabled : PCH_PCIE_ROOT_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- n -

  • NetworkEnabled : SMBIOS_TABLE_TYPE130
  • NewCenturyRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • NewFeatureEnable1 : MEMORY_CONFIGURATION
  • NewFeatureEnable2 : MEMORY_CONFIGURATION
  • NewFom : CPU_PCIE_RP_PREMEM_CONFIG
  • NftpLoadFailure : HECI_GS_SHDW_REGISTER
  • NmiRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • NMode : MEMORY_TIMING
  • NModeSupport : MEMORY_CONFIGURATION
  • NoFatalErrorReport : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatency : PCIE_DEVICE_OVERRIDE
  • NonSnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • NonSnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • NumAcms : _HEAP_BIOSACM_ELEMENT
  • NumberOfBlocks : _CONFIG_BLOCK_TABLE_STRUCT
  • NumberOfCacheLevels : SMBIOS_CACHE_INFO
  • NumberOfDpInPort : DPIN_PREMEM_CONFIG
  • NumberOfEntries : PPM_CUSTOM_RATIO_TABLE
  • NumberOfPStates : CPU_INFO
  • NumberOfSsidTableEntry : SI_CONFIG
  • NumberOfTcssSsidTable : TCSS_DATA_SSID_HOB
  • NumCores : CPU_INFO
  • NumEnabledThreads : CPU_INFO
  • NumEntries : MBP_HEADER
  • NumHts : CPU_INFO
  • NumOfControllers : ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
  • NumOfDevIntConfig : PCH_INTERRUPT_CONFIG
  • NumOfEntriesInLog : BIOSGUARD_LOG
  • NumOfLogicalProcessors : _BIOS_OS_DATA_REGION
  • NumRsvdSmbusAddresses : PCH_SMBUS_PREMEM_CONFIG
  • NumSaGvPointsEnabled : HOB_SAGV_INFO
  • NumSupportedCores : CPU_INFO
  • NumSupportedThreadsPerCore : CPU_INFO
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- o -

  • ObffEnable : CPU_PCIE_PWR_OPT
  • OcLock : OVERCLOCKING_PREMEM_CONFIG
  • OcSupport : OVERCLOCKING_PREMEM_CONFIG
  • OemCapabilities1 : SMBIOS_TABLE_TYPE130
  • OemCapabilities2 : SMBIOS_TABLE_TYPE130
  • OemCapabilities3 : SMBIOS_TABLE_TYPE130
  • OemCapabilities4 : SMBIOS_TABLE_TYPE130
  • OemParameterByte1 : ASF_BOOT_OPTIONS
  • OemParameterByte2 : ASF_BOOT_OPTIONS
  • OemResolutionSettingsRsvd : AMT_DXE_CONFIG
  • OemT12DelayOverride : GRAPHICS_PEI_PREMEM_CONFIG
  • OffToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • OneCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • OpioFusaConfigEnable : FUSA_CONFIG
  • OpRegion : IGD_OPREGION_PROTOCOL
  • OpRomScanTempMmioBar : SA_MISC_PEI_PREMEM_CONFIG
  • OpRomScanTempMmioLimit : SA_MISC_PEI_PREMEM_CONFIG
  • OptaneMemory : RST_CONFIG
  • OromUiBanner : RST_CONFIG
  • OromUiDelay : RST_CONFIG
  • OsIdleEnable : PCH_PM_CONFIG
  • OsTcoRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • OtherSettings : GPIO_CONFIG
  • OutputReportAddress : THC_HID_OVER_SPI
  • OutputState : GPIO_CONFIG
  • OverCurrentEnable : USB_CONFIG
  • OverCurrentPin : USB2_PORT_CONFIG , USB3_PORT_CONFIG
  • OverrideConfig : PCIE_DEVICE_OVERRIDE
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- p -

  • P0T1M : SATA_THERMAL_THROTTLING
  • P0T2M : SATA_THERMAL_THROTTLING
  • P0T3M : SATA_THERMAL_THROTTLING
  • P0TDisp : SATA_THERMAL_THROTTLING
  • P0TDispFinit : SATA_THERMAL_THROTTLING
  • P0Tinact : SATA_THERMAL_THROTTLING
  • P1T1M : SATA_THERMAL_THROTTLING
  • P1T2M : SATA_THERMAL_THROTTLING
  • P1T3M : SATA_THERMAL_THROTTLING
  • P1TDisp : SATA_THERMAL_THROTTLING
  • P1TDispFinit : SATA_THERMAL_THROTTLING
  • P1Tinact : SATA_THERMAL_THROTTLING
  • PadMode : GPIO_CONFIG
  • PadTermination : ISH_GPIO_CONFIG , MUX_GPIO_PARAM , SERIAL_IO_I2C_CONFIG
  • PanelPowerEnable : GRAPHICS_PEI_PREMEM_CONFIG
  • Param1 : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Param2 : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Parity : SERIAL_IO_UART_ATTRIBUTES
  • Password : GET_RSE_PASSWORD_RESPONSE
  • PasswordLength : GET_RSE_PASSWORD_RESPONSE
  • Pause : _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL , _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
  • PAVP : MEFWCAPS_SKU
  • PavpEnable : GRAPHICS_PEI_CONFIG
  • PBE : HECI_FW_STS6_REGISTER
  • PcErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • PcErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • PCETTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PchCrossThrottling : THERMAL_THROTTLE_LEVELS
  • PchDeepSxPol : PCH_PM_CONFIG
  • PchHotEnable : THERMAL_CONFIG
  • PchHotLevel : THERMAL_CONFIG
  • PchPciePort8xhDecodePortIndex : PCH_PCIE_CONFIG
  • PchPwrCycDur : PCH_PM_CONFIG
  • PchSlpAMinAssert : PCH_PM_CONFIG
  • PchSlpS3MinAssert : PCH_PM_CONFIG
  • PchSlpS4MinAssert : PCH_PM_CONFIG
  • PchSlpSusMinAssert : PCH_PM_CONFIG
  • PciData : MEMORY_CONFIGURATION
  • PCIe : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • PcieClock : PCH_PCIE_RP_PREMEM_CONFIG
  • PcieCommonConfig : PCH_PCIE_CONFIG
  • PcieDeviceOverrideTablePtr : CPU_PCIE_CONFIG , PCIE_RP_DXE_CONFIG
  • PcieImr : PCIE_PREMEM_CONFIG
  • PcieLinkEqMethod : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieLinkEqMode : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PcieMultipleSegmentEnabled : TCSS_MISC_PEI_PREMEM_CONFIG
  • PciePllSsc : PCH_PM_CONFIG
  • PciePolicy : TCSS_PEI_CONFIG
  • PciePortLaneEnabled : PCH_INFO_HOB
  • PcieRpCommonConfig : CPU_PCIE_ROOT_PORT_CONFIG
  • PcieSpeed : CPU_PCIE_RP_PREMEM_CONFIG
  • PcieWakeFromDeepSx : PCH_WAKE_CONFIG
  • PciIndex : MEMORY_CONFIGURATION
  • PDA : MEMORY_CONFIGURATION
  • PdoProgramming : USB_CONFIG
  • PdtUnlock : ISH_CONFIG
  • PeciC10Reset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • PeciSxReset : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Peg0Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg0PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg1PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg2PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Gen3EqPh2Enable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3Gen3EqPh3Method : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3MaxLinkSpeed : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3MaxLinkWidth : PCIE_PEI_PREMEM_CONFIG_GEN3
  • Peg3PowerDownUnusedLanes : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegAspm : PCIE_DXE_CONFIG
  • PegData : SA_PEG_HOB
  • PegDeEmphasis : PCIE_PEI_CONFIG
  • PegDisableSpreadSpectrumClocking : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3EndPointHint : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3EndPointPreset : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3PresetSearch : SA_PEG_DATA
  • PegGen3ProgramStaticEq : CPU_PCIE_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RootPortPreset : CPU_PCIE_EQ_LANE_PARAM , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RxCtleOverride : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen3RxCtlePeaking : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGen4EndPointHint : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4EndPointPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGen4ProgramStaticEq : CPU_PCIE_CONFIG
  • PegGen4RootPortPreset : CPU_PCIE_EQ_LANE_PARAM
  • PegGenerateBdatMarginTable : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegGpioData : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegLinkFailMask : SA_PEG_DATA
  • PegMaxPayload : PCIE_PEI_CONFIG
  • PegPhysicalSlotNumber : PCIE_PEI_CONFIG
  • PegPlatformResetRequired : SA_PEG_HOB
  • PegPwrOpt : PCIE_DXE_CONFIG
  • PegRootPortHPE : PCIE_DXE_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemLoopbackLane : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemNonProtocolAwareness : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegRxCemTestingMode : PCIE_PEI_PREMEM_CONFIG_GEN3
  • PegSlotPowerLimitScale : PCIE_PEI_CONFIG
  • PegSlotPowerLimitValue : PCIE_PEI_CONFIG
  • Pehalfbit : USB2_PHY_PARAMETERS
  • PeiGraphicsPeimInit : GRAPHICS_PEI_CONFIG
  • PeiPolicyInit : _PEI_SI_DEFAULT_POLICY_INIT_PPI
  • PeiPreMemPolicyInit : _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
  • PerAtomClusterVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerBankRefresh : MEMORY_CONFIGURATION
  • PerCoreHtDisable : OVERCLOCKING_PREMEM_CONFIG
  • PerCoreRatio : CPU_INFO
  • PerCoreRatioOverride : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • PerCoreVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • PerformanceLimitation : THC_PORT
  • PeriodicDcc : MEMORY_CONFIGURATION
  • Petxiset : USB2_PHY_PARAMETERS
  • Ph1DownstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph1UpstreamPortTransmitterPreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph2LocalTransmitterOverridePreset : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3CoefficientsList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3NumberOfPresetsOrCoefficients : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • Ph3PresetList : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • PinMux : CNVI_CONFIG , HDA_LINK_DMIC , ISH_GPIO_CONFIG , MUX_GPIO_PARAM , SERIAL_IO_I2C_CONFIG , SERIAL_IO_SPI_CONFIG , SERIAL_IO_UART_CONFIG
  • PinSelection : TS_GPIO_PIN_SETTING
  • PkeySlot0 : BGPDT
  • PkeySlot1 : BGPDT
  • PkeySlot2 : BGPDT
  • PkgAttributes : BGUP_HEADER
  • PkgCStateDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateLimit : CPU_POWER_MGMT_TEST_CONFIG
  • PkgCStateUnDemotion : CPU_POWER_MGMT_TEST_CONFIG
  • PlatformConfig : GRAPHICS_DXE_CONFIG
  • PlatformDebugConsent : SI_PREMEM_CONFIG
  • PlatformMemorySize : MEMORY_CONFIG_NO_CRC
  • PlatId : BGPDT , BGUP_HEADER
  • PllMaxBandingRatio : OVERCLOCKING_PREMEM_CONFIG
  • PmcDbgMsgEn : PCH_PM_CONFIG
  • PmcInterface : TCSS_IOM_PEI_CONFIG
  • PmcPdEnable : PMC_INTERFACE_CONFIG
  • Pme : HDAUDIO_CONFIG
  • PmeB0Register : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • PmeB0S5Dis : PCH_WAKE_CONFIG
  • PmeRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • PmgCstCfgCtrlLock : CPU_POWER_MGMT_TEST_CONFIG
  • PmodeClkEn : PCH_GENERAL_PREMEM_CONFIG
  • PmSupport : GRAPHICS_PEI_CONFIG
  • PmsyncEnable : TS_GPIO_PIN_SETTING
  • Port : USB2_PHY_CONFIG , USB3_HSIO_CONFIG
  • Port80Route : PCH_GENERAL_PREMEM_CONFIG
  • PortLane : PCH_HSIO_SATA_PREMEM_CONFIG
  • PortResetMessageEnable : USB2_PORT_CONFIG
  • PortSettings : SATA_CONFIG
  • PortUsb20 : USB_CONFIG
  • PortUsb30 : USB_CONFIG
  • PowerConfig : GPIO_CONFIG
  • PowerDownMode : MEMORY_CONFIGURATION
  • PowerDownUnusedBundles : SA_PEG_HOB
  • PowerGating : SERIAL_IO_UART_CONFIG
  • PowerGatingSupported : HDAUDIO_PREMEM_CONFIG
  • PowerLimit1 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit1Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit2Power : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3DutyCycle : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit3Time : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4 : CPU_POWER_MGMT_BASIC_CONFIG
  • PowerLimit4Lock : CPU_POWER_MGMT_BASIC_CONFIG
  • PpinSupport : CPU_CONFIG
  • PpmIrmSetting : CPU_POWER_MGMT_TEST_CONFIG
  • PprEnable : MEMORY_CONFIGURATION
  • PreBootDmaMask : VTD_CONFIG
  • Predeemp : USB2_PHY_PARAMETERS
  • PreGlobalReset : _PLATFORM_ME_HOOK_PROTOCOL
  • PreWake : CPU_POWER_MGMT_VR_CONFIG
  • PrimaryDisplay : GRAPHICS_PEI_PREMEM_CONFIG
  • PrmrrSize : CPU_SECURITY_PREMEM_CONFIG
  • ProbelessTrace : MEMORY_CONFIGURATION
  • ProcessorCharacteristics : SMBIOS_PROCESSOR_INFO
  • ProcessorFamily : SMBIOS_PROCESSOR_INFO
  • ProcessorId : SMBIOS_PROCESSOR_INFO
  • ProcessorIsTxtCapable : _TXT_INFO_DATA
  • ProcessorManufacturerStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcessorTraceEnable : CPU_TEST_CONFIG
  • ProcessorTraceMemSize : CPU_TEST_CONFIG
  • ProcessorTraceOutputScheme : CPU_TEST_CONFIG
  • ProcessorType : SMBIOS_PROCESSOR_INFO
  • ProcessorUpgrade : SMBIOS_PROCESSOR_INFO
  • ProcessorVersionStrIndex : SMBIOS_PROCESSOR_INFO
  • ProcHotLock : CPU_POWER_MGMT_TEST_CONFIG
  • ProcHotResponse : CPU_POWER_MGMT_TEST_CONFIG
  • Profile : MEMORY_INFO_DATA
  • ProfileName : GET_WIFI_PROFILE_NAME_RESPONSE
  • ProgramGtChickenBits : GRAPHICS_PEI_CONFIG
  • ProtectedRangeBase : PROTECTED_RANGE
  • ProtectedRangeLimit : PROTECTED_RANGE
  • ProtectRange : PCH_FLASH_PROTECTION_CONFIG
  • PS1toPS0CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS1toPS0MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1CCoef : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1DynamicCutoffEnable : CPU_POWER_MGMT_VR_CONFIG
  • PS2toPS1MCoef : CPU_POWER_MGMT_VR_CONFIG
  • PsfFusaConfigEnable : FUSA_CONFIG
  • Psi1Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi2Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Enable : CPU_POWER_MGMT_VR_CONFIG
  • Psi3Threshold : CPU_POWER_MGMT_VR_CONFIG
  • Psi4Enable : CPU_POWER_MGMT_VR_CONFIG
  • PslMajorVer : BGUP_HEADER
  • PslMinorVer : BGUP_HEADER
  • PsmiRegionSize : GRAPHICS_PEI_PREMEM_CONFIG
  • PsOnEnable : PCH_PM_CONFIG
  • PsysOffset : CPU_POWER_MGMT_VR_CONFIG
  • PsysOffset1 : CPU_POWER_MGMT_VR_CONFIG
  • PsysPmax : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit1Time : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2 : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysPowerLimit2Power : CPU_POWER_MGMT_PSYS_CONFIG
  • PsysSlope : CPU_POWER_MGMT_VR_CONFIG
  • PtmEnabled : TCSS_PCIE_PORT_POLICY
  • PTT : MEFWCAPS_SKU
  • PvdMode : OVERCLOCKING_PREMEM_CONFIG
  • PvdRatioThreshold : OVERCLOCKING_PREMEM_CONFIG
  • PVTTDNLP : MEMORY_CONFIGURATION
  • PwdwnIdleCounter : MEMORY_CONFIGURATION
  • PwrBtnOverridePeriod : PCH_PM_CONFIG
  • PwrCyclePending : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • PwrEnable : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • PwrOptEnable : PCH_DMI_CONFIG , SATA_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- q -

  • QueryType : AMT_QUERY_KVM
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- r -

  • RaceToHalt : CPU_POWER_MGMT_TEST_CONFIG
  • Raid0 : RST_CONFIG
  • Raid1 : RST_CONFIG
  • Raid10 : RST_CONFIG
  • Raid5 : RST_CONFIG
  • RaidDeviceId : SATA_CONFIG
  • RampDown : CPU_POWER_MGMT_VR_CONFIG
  • RampUp : CPU_POWER_MGMT_VR_CONFIG
  • Rank : SA_ADDRESS_DECODE
  • RankInDimm : DIMM_INFO , MEMORY_INFO_DATA
  • RankInterleave : MEMORY_CONFIGURATION
  • Ras : SA_ADDRESS_DECODE
  • Ratio : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • Ratio_UINT16 : MEMORY_INFO_DATA
  • RC1pFreqEnable : GRAPHICS_PEI_CONFIG
  • RcompData : MEMORY_CONFIG_NO_CRC
  • RcompResistor : SA_MEMORY_RCOMP
  • RcompTarget : SA_MEMORY_RCOMP
  • RCS : HECI_FW_STS5_REGISTER
  • RCVENC1D : MEMORY_CONFIGURATION
  • RCVET : MEMORY_CONFIGURATION
  • RDAPT : MEMORY_CONFIGURATION
  • RDEQT : MEMORY_CONFIGURATION
  • RDMPRT : MEMORY_CONFIGURATION
  • RDODTT : MEMORY_CONFIGURATION
  • RDTC1D : MEMORY_CONFIGURATION
  • RDTC2D : MEMORY_CONFIGURATION
  • RDVC1D : MEMORY_CONFIGURATION
  • RDVC2D : MEMORY_CONFIGURATION
  • RDVREFDC : MEMORY_CONFIGURATION
  • ReadCpuSoftStrap : _PCH_SPI_PROTOCOL
  • ReadMsg : _HECI_PPI , _HECI_PROTOCOL
  • ReadMsr64 : SA_FUNCTION_CALLS
  • ReadOpcode : THC_HID_OVER_SPI
  • ReadPchSoftStrap : _PCH_SPI_PROTOCOL
  • ReadProtectionEnable : PROTECTED_RANGE
  • Ready : HECI_CONTROL_STATUS_REGISTER
  • RealtimeMemoryFrequency : MEMORY_CONFIGURATION
  • RealtimeMemoryTiming : OVERCLOCKING_PREMEM_CONFIG
  • RefClk : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • Refresh2X : MEMORY_CONFIGURATION
  • RefreshHpWm : MEMORY_CONFIGURATION
  • RefreshPanicWm : MEMORY_CONFIGURATION
  • RefreshWm : MEMORY_CONFIGURATION
  • Reg : FWSTS_SET_RECORD
  • RegBar : HOST_BRIDGE_PREMEM_CONFIG
  • Register : _IO_TRAP_EX_DISPATCH_PROTOCOL
  • ReInitHeci : _HECI_PROTOCOL
  • ReloadAndStart : _WDT_PROTOCOL
  • RemapEnable : MEMORY_CONFIGURATION
  • RemoteAssistance : AMT_PEI_CONFIG
  • RemotePresetCoeffoverride : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • RenderStandby : GRAPHICS_PEI_CONFIG
  • Request : GET_WIFI_CLIENT_CERT_BUFFER , GET_WIFI_CLIENT_KEY_BUFFER , GET_WIFI_PROFILE_DATA_BUFFER , GET_WIFI_PROFILE_NAME_BUFFER
  • Reserved : _CONFIG_BLOCK_HEADER , _ITBT_GENERIC_CONFIG , _ITBT_ROOTPORT_CONFIG , _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE , _TXT_INFO_DATA , AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , ARB_SVN_COMMIT , BIOS_GUARD_CONFIG , BIOSGUARD_HOB , CPU_SECURITY_PREMEM_CONFIG , GRAPHICS_DXE_CONFIG , HDA_LINK_HDA , HECI_CONTROL_STATUS_REGISTER , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , HECI_FW_STS5_REGISTER , HECI_FW_STS6_REGISTER , HECI_GS_SHDW_REGISTER , HOST_BRIDGE_PREMEM_CONFIG , ICC_CLOCK_SETTINGS_CURRENT_FLAGS , ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS , ICC_MESSAGE_RESP_DATA , MBP_HEADER , ME_CAP , MEFWCAPS_SKU , MG_IMR_STATUS , PMC_LPM_S0IX_SUB_STATE_EN , SMBIOS_TABLE_TYPE130 , TBT_IMR_STATUS , TCSS_DATA_SSID_HOB , TCSS_IOM_PEI_CONFIG , THC_PORT , VTD_CONFIG
  • Reserved0 : CPU_CONFIG
  • Reserved1 : BGPDT , CPU_DATA_HOB , ICC_CLOCK_SETTINGS_CURRENT_FLAGS , ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS , ME_CAP , MEFWCAPS_SKU , SA_MISC_PEI_PREMEM_CONFIG
  • Reserved11 : MEMORY_CONFIG_NO_CRC
  • Reserved2 : BGPDT , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , HECI_FW_STS6_REGISTER , HECI_GS_SHDW_REGISTER , INVOCATION_CODE_BITS , ME_CAP , MEFWCAPS_SKU
  • Reserved274 : MEMORY_CONFIGURATION
  • Reserved3 : BGUP_HEADER , HECI_FW_STS3_REGISTER , HECI_FW_STS4_REGISTER , MEFWCAPS_SKU , SPD_OFFSET_TABLE
  • Reserved336 : MEMORY_CONFIGURATION
  • Reserved4 : BGUP_HEADER , HECI_FW_STS4_REGISTER , MEFWCAPS_SKU
  • Reserved5 : BIOSGUARD_LOG , MEFWCAPS_SKU
  • Reserved6 : MEFWCAPS_SKU
  • Reserved7 : MEFWCAPS_SKU
  • Reserved8 : MEFWCAPS_SKU
  • Reserved9 : MEFWCAPS_SKU
  • ReservedBits1 : CPU_POWER_MGMT_BASIC_CONFIG
  • ReservedBits2 : MEMORY_CONFIGURATION
  • ReservedByte : DXE_CPU_POLICY_PROTOCOL , DXE_SI_POLICY_PROTOCOL
  • Reset : HECI_CONTROL_STATUS_REGISTER
  • ResetAux : _TXT_INFO_DATA , CPU_SECURITY_PREMEM_CONFIG
  • ResetHeci : _HECI_PROTOCOL
  • ResetPad : THC_HID_OVER_SPI
  • ResetPadTrigger : THC_HID_OVER_SPI
  • ResetWaitTimer : HDAUDIO_PREMEM_CONFIG
  • ResizableBarSupport : SA_DATA_HOB
  • Response : GET_WIFI_CLIENT_CERT_BUFFER , GET_WIFI_CLIENT_KEY_BUFFER , GET_WIFI_PROFILE_DATA_BUFFER , GET_WIFI_PROFILE_NAME_BUFFER
  • ResponseCode : AMT_QUERY_KVM_RESPONSE
  • Resume : _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL , _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
  • RetrainOnFastFail : MEMORY_CONFIGURATION
  • RetToHighCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • RetToLowCurModeVolTranTime : FIVR_VCCIN_AUX_CONFIG
  • ReuseAdlSDdr5Board : MEMORY_CONFIGURATION
  • RevId : PCIE_DEVICE_OVERRIDE
  • Revision : _AMT_READY_TO_BOOT_PROTOCOL , _CONFIG_BLOCK_HEADER , _CPU_INFO_PROTOCOL , _ME_JHI_PROTOCOL , _PCH_ACPI_SMI_DISPATCH_PROTOCOL , _PCH_ESPI_SMI_DISPATCH_PROTOCOL , _PCH_PCIE_SMI_DISPATCH_PROTOCOL , _PCH_SMI_DISPATCH_PROTOCOL , _PCH_SPI_PROTOCOL , _PCH_TCO_SMI_DISPATCH_PROTOCOL , DXE_CPU_POLICY_PROTOCOL , DXE_SI_POLICY_PROTOCOL , GOP_POLICY_PROTOCOL , MBP_SENSITIVE_PPI , PCH_INFO_HOB
  • RevisionId : HDA_VERB_TABLE_HEADER
  • RfiMitigation : CPU_POWER_MGMT_VR_CONFIG
  • RfReset : CNVI_PIN_MUX
  • RhSelect : MEMORY_CONFIGURATION
  • RightShift64 : SA_FUNCTION_CALLS
  • RingDownBin : OVERCLOCKING_PREMEM_CONFIG
  • RingMaxOcRatio : OVERCLOCKING_PREMEM_CONFIG
  • RingPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointCount : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointOffsetMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVfPointRatio : CPU_INFO , OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageAdaptive : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • RingVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • RMC : MEMORY_CONFIGURATION
  • RMT : MEMORY_CONFIGURATION
  • RMTBIT : MEMORY_CONFIGURATION
  • RMTLoopCount : MEMORY_CONFIGURATION
  • RmtPerTask : MEMORY_CONFIGURATION
  • RootPort : CPU_PCIE_CONFIG
  • RootPortIndex : HYBRID_GRAPHICS_CONFIG
  • RpDpcExtensionsEnabled : TCSS_PCIE_PORT_POLICY
  • RpeCapabilities : SMBIOS_TABLE_TYPE130
  • RpEnabledMask : CPU_PCIE_HOB , CPU_PCIE_RP_PREMEM_CONFIG , PCH_PCIE_RP_PREMEM_CONFIG
  • RpEnMaskFromDevEn : CPU_PCIE_HOB
  • RpFunctionSwap : PCIE_COMMON_CONFIG
  • RpmcStatus : HECI_FW_STS3_REGISTER
  • RstPcieStoragePort : RST_HARDWARE_REMAPPED_STORAGE_CONFIG
  • Rsvd : _TXT_INFO_DATA , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_TEST_CONFIG , MEMORY_TIMING , SA_MISC_PEI_PREMEM_CONFIG , TCSS_DATA , TCSS_MISC_PEI_CONFIG , TCSS_MISC_PEI_PREMEM_CONFIG , TCSS_USBTC_PEI_PERMEM_CONFIG
  • Rsvd0 : _CONFIG_BLOCK_TABLE_STRUCT , CPU_DMI_EQ_PARAM , CPU_DMI_PREMEM_CONFIG , CPU_PCIE_GPIO_INFO , CPU_PCIE_PWR_OPT , CPU_PCIE_RTD3_GPIO , GRAPHICS_PEI_PREMEM_CONFIG , HDAUDIO_CONFIG , HDAUDIO_PREMEM_CONFIG , HYBRID_GRAPHICS_CONFIG , PCH_DMI_EQ_PARAM , PCH_INTERRUPT_CONFIG , PCH_IOAPIC_CONFIG , PCH_PM_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_EQ_PARAM , PCIE_PEI_PREMEM_CONFIG , PCIE_PEI_PREMEM_CONFIG_GEN3 , PEG_GPIO_DATA , PPM_CUSTOM_RATIO_TABLE , SA_GPIO_INFO_PCIE , SA_PEG_DATA , THERMAL_THROTTLE_LEVELS , TSN_CONFIG
  • Rsvd1 : GRAPHICS_PEI_CONFIG , PCH_PM_CONFIG , PCIE_PEI_CONFIG , SA_DATA_HOB
  • Rsvd2 : GRAPHICS_PEI_PREMEM_CONFIG
  • Rsvd5 : CPU_POWER_MGMT_VR_CONFIG
  • RsvdBit : DXE_CPU_POLICY_PROTOCOL
  • RsvdBits : _PPM_CUSTOM_CTDP_TABLE , AMT_DXE_CONFIG , AMT_PEI_CONFIG , CPU_CONFIG , CPU_POWER_MGMT_BASIC_CONFIG , CPU_POWER_MGMT_CUSTOM_CONFIG , CPU_POWER_MGMT_PSYS_CONFIG , CPU_POWER_MGMT_VR_CONFIG , CPU_SECURITY_PREMEM_CONFIG , CPU_TEST_CONFIG , GPIO_CONFIG , GPIO_DXE_CONFIG , HDAUDIO_PREMEM_CONFIG , ME_DXE_CONFIG , ME_PEI_CONFIG , ME_PEI_PREMEM_CONFIG
  • Rsvdbits : PCH_DMI_CONFIG
  • RsvdBits : PCH_ESPI_CONFIG , PCH_LPC_PREMEM_CONFIG
  • Rsvdbits : PCH_P2SB_CONFIG
  • RsvdBits : PROTECTED_RANGE , SI_PREMEM_CONFIG
  • RsvdBits0 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FUSA_CONFIG , GBE_CONFIG , GNA_CONFIG , HDAUDIO_CONFIG , IEH_CONFIG , ISH_CONFIG , ISH_GP , ISH_I2C , ISH_PREMEM_CONFIG , ISH_UART , PCH_GENERAL_CONFIG , PCH_GENERAL_PREMEM_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_LOCK_DOWN_CONFIG , PCH_SATA_PORT_CONFIG , PCH_SMBUS_PREMEM_CONFIG , PCIE_COMMON_CONFIG , PCIE_PEI_PREMEM_CONFIG , PSF_CONFIG , RST_CONFIG , RST_HARDWARE_REMAPPED_STORAGE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG , SATA_THERMAL_THROTTLING , SPI_CONFIG , USB2_PORT_CONFIG , USB3_PORT_CONFIG , USB_CONFIG , XDCI_CONFIG
  • RsvdBits1 : CPU_PCIE_ROOT_PORT_CONFIG , DMI_HW_WIDTH_CONTROL , FIVR_EXT_RAIL_CONFIG , PCH_HSIO_PCIE_LANE_CONFIG , PCH_HSIO_SATA_PORT_LANE , PCH_IOAPIC_CONFIG , PCIE_PEI_CONFIG , PCIE_PEI_PREMEM_CONFIG
  • RsvdBits2 : FIVR_EXT_RAIL_CONFIG , PCH_HSIO_SATA_PORT_LANE
  • RsvdByte2 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte3 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte4 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte5 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdByte6 : OVERCLOCKING_PREMEM_CONFIG
  • RsvdBytes : PCH_PCIE_CLOCK , SI_PREMEM_CONFIG
  • RsvdBytes0 : CPU_PCIE_ROOT_PORT_CONFIG , PCH_PCIE_ROOT_PORT_CONFIG , SI_CONFIG
  • RsvdBytes1 : SI_CONFIG
  • RsvdBytes2 : SI_CONFIG
  • RsvdField0 : ISH_SPI
  • RsvdO64B25to31 : MEMORY_CONFIGURATION
  • RsvdSmbusAddressTable : PCH_SMBUS_PREMEM_CONFIG
  • RtcAlarmRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • RTL : MEMORY_CONFIGURATION
  • Rts : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RunBusy : _OC_MAILBOX_INTERFACE , _PCODE_MAILBOX_INTERFACE
  • Rx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • RxPolarity : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- s -

  • S0i2p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i2p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p0En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p1En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p2En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p3En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0i3p4En : PMC_LPM_S0IX_SUB_STATE_EN
  • S0ixAutoDemotion : PCH_PM_CONFIG
  • S3DataPtr : SA_MISC_PEI_PREMEM_CONFIG
  • SaCall : MEMORY_CONFIG_NO_CRC
  • SaCepEnable : OVERCLOCKING_PREMEM_CONFIG
  • SaExtraTurboVoltage : OVERCLOCKING_PREMEM_CONFIG
  • SafeMode : MEMORY_CONFIGURATION
  • SaGv : MEMORY_CONFIGURATION
  • SaGvFreq : MEMORY_CONFIGURATION
  • SaGvGear : MEMORY_CONFIGURATION
  • SagvHeuristicsDownControl : MEMORY_CONFIGURATION
  • SagvHeuristicsUpControl : MEMORY_CONFIGURATION
  • SaGvPointMask : HOB_SAGV_INFO
  • SagvSwitchFactorGT : MEMORY_CONFIGURATION
  • SagvSwitchFactorIA : MEMORY_CONFIGURATION
  • SagvSwitchFactorIO : MEMORY_CONFIGURATION
  • SagvSwitchFactorStall : MEMORY_CONFIGURATION
  • SalpSupport : SATA_CONFIG
  • SaPeg0ResetGpio : PEG_GPIO_DATA
  • SaPeg3ResetGpio : PEG_GPIO_DATA
  • SaPllFreqOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaPllVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SataMode : SATA_CONFIG
  • SataPmPtm : PCH_SATA_PORT_CONFIG
  • SataRstInterrupt : SATA_CONFIG
  • SaVoltageMode : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOffset : OVERCLOCKING_PREMEM_CONFIG
  • SaVoltageOverride : OVERCLOCKING_PREMEM_CONFIG
  • SaXdci : TCSS_MISC_PEI_CONFIG
  • SbAccessUnlock : PCH_P2SB_CONFIG
  • ScanExtGfxForLegacyOpRom : SA_MISC_PEI_PREMEM_CONFIG
  • SchemaHobCount : BDAT_SCHEMA_LIST_HOB
  • SchemaHobGuids : BDAT_SCHEMA_LIST_HOB
  • SciIrqSelect : PCH_INTERRUPT_CONFIG
  • Scl : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • ScramblerSupport : MEMORY_CONFIGURATION
  • ScriptSectionSize : BGUP_HEADER
  • ScrtmIndicator : HECI_FW_STS5_REGISTER
  • Sda : I2C_PIN_MUX , ISH_I2C_PIN_CONFIG
  • SdiEnable : HDA_LINK_HDA
  • SdiNum : HDA_VERB_TABLE_HEADER
  • SendAndReceive : _ME_JHI_PROTOCOL
  • SendDidMsg : ME_PEI_PREMEM_CONFIG
  • SendEcCmd : BIOS_GUARD_CONFIG
  • SendMsg : _HECI_PPI , _HECI_PROTOCOL
  • SendVrMbxCmd : CPU_POWER_MGMT_VR_CONFIG
  • SendwAck : _HECI_PPI , _HECI_PROTOCOL
  • SensorDevice : ASF_MESSAGE , ASF_START_WDT , PET_ALERT
  • SensorNumber : ASF_MESSAGE , ASF_START_WDT
  • Sensornumber : PET_ALERT
  • SerialDebugLevel : MEMORY_CONFIG_NO_CRC
  • SerialIrqRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SetMem : SA_FUNCTION_CALLS
  • SetMemDword : SA_FUNCTION_CALLS
  • SetMemoryPmicVoltage : SA_FUNCTION_CALLS
  • SetMemoryVdd : SA_FUNCTION_CALLS
  • SetMemWord : SA_FUNCTION_CALLS
  • SetSecuredRegisterLock : CPU_PCIE_CONFIG
  • SetToDefault : ICC_CLOCK_SETTINGS_CURRENT_FLAGS
  • SevenCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • SfamData : BGPDT
  • SgpioSupport : SATA_CONFIG
  • SgxInfo : _CPU_INFO_PROTOCOL
  • SgxSinitNvsData : SGX_INFO
  • SharedZqPin : MEMORY_CONFIGURATION
  • ShiftPiCommandTrain : SA_MEMORY_FUNCTIONS
  • Signal : _AMT_READY_TO_BOOT_PROTOCOL
  • SimicsFlag : MEMORY_CONFIGURATION
  • SinitAcmBase : _TXT_INFO_DATA
  • SinitAcmSize : _TXT_INFO_DATA
  • SinitMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • SixCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • Size : _HEAP_EXT_DATA_ELEMENT , CACHE_DESCRIPTOR_INFO , GRAPHICS_DXE_CONFIG , MEMORY_CONFIGURATION
  • SkipBiosDoneWhenFwUpdate : SI_CONFIG
  • SkipCdClockInit : GRAPHICS_PEI_CONFIG
  • SkipCpuReplacementCheck : ME_PEI_PREMEM_CONFIG
  • SkipExtGfxScan : SA_MISC_PEI_PREMEM_CONFIG
  • SkipFspGop : GRAPHICS_PEI_CONFIG
  • SkipMbpHob : ME_PEI_PREMEM_CONFIG
  • SkipMpInit : CPU_CONFIG
  • SkipOverrideBootModeWhenFwUpdate : SI_PREMEM_CONFIG
  • SkipPamLock : HOST_BRIDGE_PEI_CONFIG
  • SkipSetBootPState : CPU_POWER_MGMT_BASIC_CONFIG
  • SkipSsidProgramming : SI_CONFIG
  • SkipStopPbet : CPU_SECURITY_PREMEM_CONFIG
  • SlotMap : _MEMORY_DXE_CONFIG
  • SlotNumber : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitScale : TCSS_PCIE_PORT_POLICY
  • SlotPowerLimitValue : TCSS_PCIE_PORT_POLICY
  • SlotSelection : CPU_PCIE_CONFIG , CPU_PCIE_HOB
  • SlowSlewRate : CPU_POWER_MGMT_VR_CONFIG
  • SlpLanLowDc : PCH_PM_CONFIG
  • SlpStrchSusUp : PCH_PM_CONFIG
  • SmartStorage : RST_CONFIG
  • SmbAlertEnable : PCH_SMBUS_PREMEM_CONFIG
  • SmbiosOemTypeFirmwareVersionInfo : DXE_SI_POLICY_PROTOCOL
  • SmbiosType4MaxSpeedOverride : CPU_CONFIG
  • SmbusBar : SA_MISC_PEI_PREMEM_CONFIG
  • SmbusIoBase : PCH_SMBUS_PREMEM_CONFIG
  • SmbusRead16 : SA_FUNCTION_CALLS
  • SmbusRead8 : SA_FUNCTION_CALLS
  • SmbusRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SmbusWrite16 : SA_FUNCTION_CALLS
  • SmbusWrite8 : SA_FUNCTION_CALLS
  • SmmbaseSwSmiNumber : CPU_INFO
  • SmmMsrSaveStateEnable : DXE_CPU_POLICY_PROTOCOL
  • SmmProcTraceEnable : DXE_CPU_POLICY_PROTOCOL
  • SmmUseBlockIndication : DXE_CPU_POLICY_PROTOCOL
  • SmmUseDelayIndication : DXE_CPU_POLICY_PROTOCOL
  • SmmUseSmmEnableIndication : DXE_CPU_POLICY_PROTOCOL
  • SmramCpuData : SMRAM_CPU_INFO
  • SmramCpuInfo : _CPU_INFO_PROTOCOL
  • SmramMask : MEMORY_CONFIGURATION
  • Smtc : HECI_FW_STS5_REGISTER
  • SndwConfig : HDAUDIO_DXE_CONFIG
  • SnoopLatency : PCIE_DEVICE_OVERRIDE
  • SnoopLatencyOverrideMode : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideMultiplier : TCSS_PCIE_PORT_POLICY
  • SnoopLatencyOverrideValue : TCSS_PCIE_PORT_POLICY
  • SocBclkOcFrequency : OVERCLOCKING_PREMEM_CONFIG
  • SocBclkPllOn : BCLK_CONFIG
  • SocDieSscEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocDieSscValue : CPU_CONFIG_LIB_PREMEM_CONFIG
  • SocketDesignationStrIndex : SMBIOS_CACHE_INFO
  • SolEnabled : SMBIOS_TABLE_TYPE130
  • SolidStateDrive : PCH_SATA_PORT_CONFIG
  • SolStateChange : INVOCATION_CODE_BITS
  • SOT : MEMORY_CONFIGURATION
  • SpdAddressTable : _MEMORY_DXE_CONFIG , SA_MISC_PEI_PREMEM_CONFIG
  • SpdData : MEMORY_CONFIG_NO_CRC , SPD_DATA_BUFFER
  • SpdDramDeviceType : DIMM_INFO
  • SpdModuleMemoryBusWidth : DIMM_INFO
  • SpdModuleType : DIMM_INFO
  • SpdProfileSelected : MEMORY_CONFIGURATION
  • SpdSave : DIMM_INFO
  • SpdWriteDisable : PCH_SMBUS_PREMEM_CONFIG
  • SpecialCommand : ASF_BOOT_OPTIONS
  • SpecialCommandParamHighByte : ASF_BOOT_OPTIONS
  • SpecialCommandParamLowByte : ASF_BOOT_OPTIONS
  • SpecVerMajor : _HEAP_BIOS_SPEC_VER_ELEMENT
  • SpecVerMinor : _HEAP_BIOS_SPEC_VER_ELEMENT
  • SpecVerRevision : _HEAP_BIOS_SPEC_VER_ELEMENT
  • Speed : DIMM_INFO
  • SpeedLimit : SATA_CONFIG
  • SpiAsyncRegister : _PCH_SMI_DISPATCH_PROTOCOL
  • SpiBiosWpRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • SpiDeviceConfig : SERIAL_IO_CONFIG
  • SpiEiss : PCH_LOCK_DOWN_CONFIG
  • SpinUp : PCH_SATA_PORT_CONFIG
  • SpiProtectionMode : HECI_FWS_REGISTER
  • SrefCfgEna : MEMORY_CONFIGURATION
  • SrefCfgIdleTmr : MEMORY_CONFIGURATION
  • SrouEnabled : SMBIOS_TABLE_TYPE130
  • SsidTablePtr : SI_CONFIG
  • Start : SPD_OFFSET_TABLE
  • StartEnforcement : HECI_FW_STS5_REGISTER
  • StateRatio : PPM_CUSTOM_RATIO_TABLE
  • StateRatioMax16 : PPM_CUSTOM_RATIO_TABLE
  • Status : AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE , AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE , DIMM_INFO , FSP_ERROR_INFO_HOB , GET_WIFI_PROFILE_NAME_RESPONSE , SMBIOS_PROCESSOR_INFO
  • StatusCause : REPORT_BIOS_STATUS
  • StatusCodeValue : ASF_DATA_HUB_MAP
  • StdMng : MEFWCAPS_SKU
  • StopBits : SERIAL_IO_UART_ATTRIBUTES
  • SubClassCode : PCIE_DEVICE_OVERRIDE
  • SubCommand : ASF_BOOT_OPTIONS , ASF_MESSAGE , ASF_MESSAGE_HEADER
  • SubSystemIds : HDAUDIO_PREMEM_CONFIG
  • SuggestedSetting : DMI_HW_WIDTH_CONTROL , SATA_THERMAL_THROTTLING , THERMAL_THROTTLE_LEVELS
  • SupportedLanguages : _GOP_COMPONENT_NAME2_PROTOCOL
  • SupportedSramType : SMBIOS_CACHE_INFO
  • SupportedVoltageStates : FIVR_EXT_RAIL_CONFIG
  • SvidEnabled : CPU_DATA_HOB
  • SxResumeType : HECI_FW_STS4_REGISTER
  • SyncMngState : INVOCATION_CODE_BITS
  • SyncRaAvailability : INVOCATION_CODE_BITS
  • SynpsPhyBinLen : PCH_HSIO_CONFIG
  • SynpsPhyBinPtr : PCH_HSIO_CONFIG
  • SystemCacheType : SMBIOS_CACHE_INFO
  • SystemErrorEnable : PCH_PCIE_ROOT_PORT_CONFIG
  • SystemErrorOnCorrectableError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnFatalError : TCSS_PCIE_PORT_POLICY
  • SystemErrorOnNonFatalError : TCSS_PCIE_PORT_POLICY
  • SystemMemoryLength : SA_MISC_PEI_PREMEM_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- t -

  • T0Level : THERMAL_THROTTLE_LEVELS
  • T1Level : THERMAL_THROTTLE_LEVELS
  • T2Level : THERMAL_THROTTLE_LEVELS
  • TableHeader : _SI_POLICY_STRUCT , _SI_PREMEM_POLICY_STRUCT , ITBT_POLICY_PROTOCOL , SA_POLICY_PROTOCOL
  • TableSyncError : INVOCATION_CODE_BITS
  • TAT : MEMORY_CONFIGURATION
  • TbtCommonConfig : _DXE_ITBT_CONFIG
  • TbtFwVersion : TBT_IMR_STATUS
  • TbtImrStatus : TCSS_DATA
  • TccActivationOffset : CPU_POWER_MGMT_BASIC_CONFIG
  • tCCD_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TccEnable : PSF_CONFIG
  • TccOffsetClamp : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TccOffsetTimeWindowForRatl : CPU_POWER_MGMT_BASIC_CONFIG
  • tCK : MEMORY_TIMING
  • tCL : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TcoIrqEnable : PCH_INTERRUPT_CONFIG
  • TcoIrqSelect : PCH_INTERRUPT_CONFIG
  • TcoTimeoutRegister : _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • TcssData : TCSS_DATA_HOB
  • TcssDevEn : TCSS_DEVEN_PEI_PREMEM_CONFIG
  • TcssIomVccSt : TCSS_DATA
  • TcssRtd3 : TCSS_DATA
  • TcssSsidTable : TCSS_DATA_SSID_HOB
  • TcssxDCIInt : TCSS_DATA
  • TcssxDCIIrq : TCSS_DATA
  • TcStateLimit : TCSS_IOM_PEI_CONFIG
  • tCWL : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TdcCurrentLimit : CPU_POWER_MGMT_VR_CONFIG
  • TdcEnable : CPU_POWER_MGMT_VR_CONFIG
  • TdcLock : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow : CPU_POWER_MGMT_VR_CONFIG
  • TdcTimeWindow1 : CPU_POWER_MGMT_VR_CONFIG
  • TestMode : SATA_CONFIG
  • tFAW : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TgaSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • Thc0Strap : PCH_INFO_HOB
  • ThcPort : THC_CONFIG
  • ThermalMonitor : CPU_POWER_MGMT_TEST_CONFIG
  • ThermalThrottling : SATA_CONFIG
  • ThermTimerDelay : PCH_PM_CONFIG
  • ThreadCount : SMBIOS_PROCESSOR_INFO
  • ThreeCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • ThreeStrikeCounterDisable : CPU_TEST_CONFIG
  • ThrtCkeMinDefeat : MEMORY_CONFIGURATION
  • ThrtCkeMinDefeatLpddr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmr : MEMORY_CONFIGURATION
  • ThrtCkeMinTmrLpddr : MEMORY_CONFIGURATION
  • TimedMwait : CPU_POWER_MGMT_TEST_CONFIG
  • TimeoutHigh : ASF_START_WDT
  • TimeoutLow : ASF_START_WDT
  • Timing : MEMORY_INFO_DATA
  • TjMaxOffset : OVERCLOCKING_PREMEM_CONFIG
  • TLS : MEFWCAPS_SKU
  • TmeEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • TmrOverflowRegister : _PCH_ACPI_SMI_DISPATCH_PROTOCOL
  • TpmStartupFailureOnS3 : BOOT_GUARD_INFO
  • TpmType : BOOT_GUARD_INFO
  • TraceHub : CPU_TRACE_HUB_PREMEM_CONFIG , PCH_TRACE_HUB_PREMEM_CONFIG
  • TrainTrace : MEMORY_CONFIGURATION
  • tRAS : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRCDtRP : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tREFI : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC2 : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFC4 : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRFCpb : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRPab : MEMORY_TIMING
  • tRRD : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRRD_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRRD_S : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tRTP : MEMORY_CONFIGURATION , MEMORY_TIMING
  • TrustedDevice : MEFWCAPS_SKU
  • TS0TW : DMI_HW_WIDTH_CONTROL
  • TS1TW : DMI_HW_WIDTH_CONTROL
  • TS2TW : DMI_HW_WIDTH_CONTROL
  • TS3TW : DMI_HW_WIDTH_CONTROL
  • TscDisableHwFixup : OVERCLOCKING_PREMEM_CONFIG
  • TsegBase : _TXT_INFO_DATA
  • TsegSize : _TXT_INFO_DATA , SA_MISC_PEI_PREMEM_CONFIG
  • TsGpioPinSetting : PCH_MEMORY_THROTTLING
  • TsLockTimer : PCIE_LINK_EQ_PLATFORM_SETTINGS
  • TsnLinkSpeed : TSN_CONFIG
  • TsnMacAddressHigh : TSN_CONFIG
  • TsnMacAddressLow : TSN_CONFIG
  • TStates : CPU_POWER_MGMT_TEST_CONFIG
  • TTEnable : THERMAL_THROTTLE_LEVELS
  • TTLevels : THERMAL_CONFIG
  • TTLock : THERMAL_THROTTLE_LEVELS
  • TTState13Enable : THERMAL_THROTTLE_LEVELS
  • TurboMode : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboPowerLimitLock : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitNumCore : CPU_POWER_MGMT_BASIC_CONFIG
  • TurboRatioLimitRatio : CPU_POWER_MGMT_BASIC_CONFIG
  • TvbDownBinsTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbDownBinsTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbRatioClipping : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold0 : OVERCLOCKING_PREMEM_CONFIG
  • TvbTempThreshold1 : OVERCLOCKING_PREMEM_CONFIG
  • TvbVoltageOptimization : OVERCLOCKING_PREMEM_CONFIG
  • TwoCoreRatioLimit : CPU_POWER_MGMT_BASIC_CONFIG
  • tWR : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR_L : MEMORY_CONFIGURATION , MEMORY_TIMING
  • tWTR_S : MEMORY_CONFIGURATION , MEMORY_TIMING
  • Tx : ISH_UART_PIN_CONFIG , UART_PIN_MUX
  • TXDQSDCC : MEMORY_CONFIGURATION
  • Txiset : USB2_PHY_PARAMETERS
  • Txt : CPU_SECURITY_PREMEM_CONFIG
  • TxtAcheckRequest : _TXT_INFO_DATA , CPU_SECURITY_PREMEM_CONFIG
  • TXTCO : MEMORY_CONFIGURATION
  • TXTCODQS : MEMORY_CONFIGURATION
  • TxtDprMemoryBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtDprMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtEnable : CPU_CONFIG
  • TxtHeapMemorySize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtImplemented : SA_MISC_PEI_PREMEM_CONFIG
  • TxtLcpPdBase : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtLcpPdSize : _TXT_INFO_DATA , CPU_TXT_PREMEM_CONFIG
  • TxtMode : _TXT_INFO_DATA
  • TxtSupport : HECI_FW_STS6_REGISTER
  • Type : _HEAP_EXT_DATA_ELEMENT , AMT_PET_QUEUE_HOB , CACHE_DESCRIPTOR_INFO , FSP_ERROR_INFO_HOB , ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- u -

  • UaolEnable : USB_CONFIG
  • UartDeviceConfig : SERIAL_IO_CONFIG
  • Uint64 : MSR_TURBO_RATIO_LIMIT_REGISTER
  • UnConfigureMe : AMT_DXE_CONFIG
  • Uninit : _ME_JHI_PROTOCOL
  • Uninstall : _ME_JHI_PROTOCOL
  • UnlimitedIccMax : OVERCLOCKING_PREMEM_CONFIG
  • UnlockGpioPads : PCH_LOCK_DOWN_CONFIG
  • UnRegister : _IO_TRAP_EX_DISPATCH_PROTOCOL , _PCH_ACPI_SMI_DISPATCH_PROTOCOL , _PCH_ESPI_SMI_DISPATCH_PROTOCOL , _PCH_PCIE_SMI_DISPATCH_PROTOCOL , _PCH_SMI_DISPATCH_PROTOCOL , _PCH_TCO_SMI_DISPATCH_PROTOCOL
  • UnsupportedRequestReport : TCSS_PCIE_PORT_POLICY
  • UpSpread : ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
  • Usage : PCH_PCIE_CLOCK
  • Usb2PhySusPgEnable : PCH_PM_CONFIG
  • Usb4CmMode : _ITBT_GENERIC_CONFIG
  • UsbConfig : TCSS_PEI_CONFIG
  • UsbOverride : IOM_INTERFACE_CONFIG
  • UsbProvision : AMT_DXE_CONFIG
  • UsbTcConfig : TCSS_PEI_PREMEM_CONFIG
  • UsbTcPortEn : TCSS_USBTC_PEI_PERMEM_CONFIG
  • UserBd : MEMORY_CONFIGURATION , SA_MISC_PEI_PREMEM_CONFIG
  • UserBudgetEnable : MEMORY_CONFIGURATION
  • UserConsentFlow : INVOCATION_CODE_BITS
  • UserThresholdEnable : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- v -

  • V1p05IsExtFetControlEn : PCH_PM_CONFIG
  • V1p05PhyExtFetControlEn : PCH_PM_CONFIG
  • Valid : MG_IMR_STATUS , TBT_IMR_STATUS
  • Value : AMT_PET_QUEUE_HOB , FSP_ERROR_INFO_HOB , SA_GPIO_INFO_PCIE
  • VbtAddress : GRAPHICS_DXE_CONFIG
  • Vc1ReadMeter : MEMORY_CONFIGURATION
  • VCCDLLBP : MEMORY_CONFIGURATION
  • VccinAux : PCH_FIVR_CONFIG
  • VccInAuxImonIccImax : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonOffset : CPU_POWER_MGMT_VR_CONFIG
  • VccInAuxImonSlope : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionCapacitanceInUf : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionEnable : CPU_POWER_MGMT_VR_CONFIG
  • VccInDemotionQuiescentPowerInMw : CPU_POWER_MGMT_VR_CONFIG
  • VccSt : IOM_INTERFACE_CONFIG
  • VcType : HDAUDIO_PREMEM_CONFIG
  • VDDQT : MEMORY_CONFIGURATION
  • VddqVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VddSettleWaitTime : MEMORY_CONFIGURATION
  • VddVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VendorId : HDA_VERB_TABLE_HEADER , PCIE_DEVICE_OVERRIDE
  • VendorSpecific : BGUP_HEADER
  • VerbTableEntryNum : HDAUDIO_CONFIG
  • VerbTablePtr : HDAUDIO_CONFIG
  • VerifiedBootPolicy : HECI_FW_STS6_REGISTER
  • Version : _BIOS_OS_DATA_REGION , ASF_BOOT_OPTIONS , ASF_MESSAGE , BGUP_HEADER , BIOSGUARD_LOG , FWSTS_SMBIOS_RECORD
  • VersionNumber : ASF_MESSAGE_HEADER
  • VerticalResolution : GRAPHICS_PEI_CONFIG
  • VgpioCs : GPIO_CONFIG
  • VLD : HECI_FW_STS5_REGISTER
  • VmdCfgBarAttr : VMD_PEI_CONFIG
  • VmdCfgBarBase : VMD_PEI_CONFIG
  • VmdCfgBarSize : VMD_PEI_CONFIG
  • VmdEnable : VMD_PEI_CONFIG
  • VmdGlobalMapping : VMD_PEI_CONFIG
  • VmdMemBar1Attr : VMD_PEI_CONFIG
  • VmdMemBar1Base : VMD_PEI_CONFIG
  • VmdMemBar2Attr : VMD_PEI_CONFIG
  • VmdMemBar2Base : VMD_PEI_CONFIG
  • VmdMemBarSize1 : VMD_PEI_CONFIG
  • VmdMemBarSize2 : VMD_PEI_CONFIG
  • VmdPortBEnable : VMD_PEI_CONFIG
  • VmdPortCEnable : VMD_PEI_CONFIG
  • VmdPortDEnable : VMD_PEI_CONFIG
  • VmdPortEnable : VMD_PEI_CONFIG
  • VmxEnable : CPU_CONFIG_LIB_PREMEM_CONFIG
  • Voltage : CPU_INFO , FIVR_EXT_RAIL_CONFIG , SMBIOS_PROCESSOR_INFO
  • VppAddress : PCH_PCIE_ROOT_PORT_CONFIG
  • VppPort : PCH_PCIE_ROOT_PORT_CONFIG
  • VppVoltage : MEMORY_CONFIGURATION , MEMORY_INFO_DATA
  • VrAddress : CPU_DATA_HOB
  • VrConfigEnable : CPU_POWER_MGMT_VR_CONFIG
  • VrPowerDeliveryDesign : CPU_POWER_MGMT_VR_CONFIG
  • VrVoltageLimit : CPU_POWER_MGMT_VR_CONFIG
  • VsysAssertionDeglitchMantissa : CPU_POWER_MGMT_VR_CONFIG
  • VsysFullScale : CPU_POWER_MGMT_VR_CONFIG
  • VtdDisable : VTD_CONFIG
  • VtdIgdEnable : VTD_CONFIG
  • VtdIopEnable : VTD_CONFIG
  • VtdIpuEnable : VTD_CONFIG
  • VttCompForVsshi : MEMORY_CONFIGURATION
  • VttTermination : MEMORY_CONFIGURATION
  • VwErrFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
  • VwErrNonFatalRegister : _PCH_ESPI_SMI_DISPATCH_PROTOCOL
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- w -

  • WakeConfig : PCH_PM_CONFIG
  • WakeGpioNo : CPU_PCIE_RTD3_GPIO , PCIE_RTD3_GPIO
  • WakeOnTouch : THC_PORT
  • WarmRstReqForDF : HECI_GS_SHDW_REGISTER
  • WatchDogEnabled : AMT_PEI_CONFIG
  • WatchDogTimerBios : AMT_PEI_CONFIG
  • WatchDogTimerOs : AMT_PEI_CONFIG
  • WeaklockEn : MEMORY_CONFIGURATION
  • WifiCore : CNVI_CONFIG
  • WLAN : MEFWCAPS_SKU
  • WlanPowerConfigChange : INVOCATION_CODE_BITS
  • WolEnableOverride : PCH_WAKE_CONFIG
  • WolOvrWkSts : PCH_PM_CONFIG
  • WoWlanDeepSxEnable : PCH_WAKE_CONFIG
  • WoWlanEnable : PCH_WAKE_CONFIG
  • WrcFeatureEnable : SA_MISC_PEI_PREMEM_CONFIG
  • WRDS : MEMORY_CONFIGURATION
  • WRDSEQT : MEMORY_CONFIGURATION
  • WRDSUDT : MEMORY_CONFIGURATION
  • Write : _BIOSGUARD_PROTOCOL
  • Write0 : MEMORY_CONFIGURATION
  • WriteMsr64 : SA_FUNCTION_CALLS
  • WriteOpcode : THC_HID_OVER_SPI
  • WriteProtectionEnable : PROTECTED_RANGE
  • WriteThreshold : MEMORY_CONFIGURATION
  • WRSRT : MEMORY_CONFIGURATION
  • WRTC1D : MEMORY_CONFIGURATION
  • WRTC2D : MEMORY_CONFIGURATION
  • WRVC1D : MEMORY_CONFIGURATION
  • WRVC2D : MEMORY_CONFIGURATION
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- x -

  • X2ApicOptOut : VTD_CONFIG
  • X2ApicSupport : CPU_CONFIG
  • XdciConfig : USB_CONFIG
  • XhciOcLock : USB_CONFIG
  • XmpConfigWarning : MEMORY_INFO_DATA
  • XmpProfileEnable : MEMORY_INFO_DATA
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Class Members - Variables

- z -

  • ZpOdd : PCH_SATA_PORT_CONFIG
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File List

File List
Here is a list of all documented files with brief descriptions:
AcpiDebug.h | Header file for ACPI ADBG enable/disable
AcpiS3Context.h | Definitions for data structures used in S3 resume
AdrConfig.h | ADR policy
AmtConfig.h | AMT Config Block for PEI/DXE phase
AmthiMsgs.h | AMTHI Messages
AmtPetQueueHob.h | Definition of AmtPetQueueHob data structures
AmtPolicy.h | Interface definition details between AMT and platform drivers during DXE phase
AmtReadyToBoot.h | AmtReadyToBoot Protocol definitions
AmtSaveMebxProtocol.h | AmtSaveMebxProtocol definitions - deprecated protocol
ArchMsr.h | ArchMsr.h
AsfMsgs.h | AMT/ASF Messages
AsfProtocol.h | Definition of Alert Standard Format (ASF) 2.0
Bdat4.h | Definition of BDAT data structures that are applicible for all schemas
BdatAccess.h | This file abstracts Bdat Access Handler Protocol
BiosGuard.h | Describes the functions visible to the rest of the BIOS Guard
Protocol/BiosGuard.h | This file defines the BIOS Guard Protocol which implements the Intel(R) BIOS Guard Host Controller Compatibility Interface
BiosGuardConfig.h | CPU BIOS Guard Config Block
BootGuardLibVer1.h | Header file for Boot Guard Lib implementation
BootMediaLib.h | Header file for the Boot Media Library
BupMsgs.h | BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW
CacheAsRamLib.h |
ChipsetInfoHob.h | This file contains definitions of Chipset Info HOB
CnviConfig.h | CNVi policy
CnviLib.h | Header file for CnviLib
CnviRegs.h | Register names for CNVi
CommonMsr.h | CommonMsr.h
ConfigBlock.h | Header file for Config Block Lib implementation
ConfigBlockLib.h | Header file for Config Block Lib implementation
ConsoleOutDevice.h | This GUID can be installed to the device handle to specify that the device is the console-out device
CoreBiosMsg.h | Core BIOS Messages
CpuConfig.h | CPU Config Block
CpuConfigLibPreMemConfig.h | CPU Security PreMemory Config Block
CpuDataHob.h | The GUID definition for CpuDataHob
CpuDataStruct.h | This file declares various data structures used in CPU reference code
CpuDmiHob.h | The GUID definition for CpuDmiHob
CpuDmiInfoLib.h | Header file for CpuDmiInfoLib
CpuDmiPreMemConfig.h | DMI policy
CpuInfo.h | Protocol used to report CPU information
CpuLimits.h | This file declares CPU limitated definition
CpuMailboxLib.h | Header file for Cpu Mailbox Lib
CpuPcieConfig.h | Pcie root port policy
CpuPcieConfigGen3.h | Pcie root port policy
CpuPcieHob.h | The GUID definition for CpuPcieHob
CpuPcieHobGen3.h | The GUID definition for CpuPcieHob
CpuPlatformLib.h | Header file for CpuPlatform Lib
CpuPolicyLib.h | Prototype of the CpuPolicy library
CpuPolicyProtocol.h | Protocol used for specifying platform related CPU information and policy setting
CpuPowerMgmt.h | This file contains define definitions specific to processor
CpuPowerMgmtBasicConfig.h | CPU Power Management Basic Config Block
CpuPowerMgmtCustomConfig.h | CPU Power Managment Custom Config Block
CpuPowerMgmtPsysConfig.h | CPU Power Management Psys(Platform) Config Block
CpuPowerMgmtTestConfig.h | CPU Power Management Test Config Block
CpuPowerMgmtVrConfig.h | CPU Power Management VR Config Block
CpuRegbarAccessLib.h | Header file for CPU REGBAR ACCESS library
CpuRegs.h | Register names for CPU registers
CpuSecurityPreMemConfig.h | CPU Security PreMemory Config Block
CpuTestConfig.h | CPU Test Config Block
CpuTxtConfig.h | CPU TXT PreMemory Config Block
DciConfig.h | Dci policy
DebugTokenDataHob.h | The HOB definition for DebugTokenDataHob
DpInPreMemConfig.h | DPIN PreMem policy
DxeAmtHeciLib.h | Header file for AMT functionality
DxeAmtPolicyLib.h | Prototype of the DxeAmtPolicyLib library
DxeAsfHeciLib.h | Header file for ASF functionality
DxeAsfLib.h | Header file for ASF functionality
DxeITbtConfig.h | Headr file for iTBT DXE Policy
DxeITbtPolicyLib.h | Prototype of the DxeITbtPolicyLib library
DxeJhiSupportLib.h | Header file for JHI helper functionality
DxeMebxDisplayWrapperLib.h | Wrapper functions for MEBx display protocol functions
DxeMebxWrapperLib.h | Header file for MEBx Wrapper Library
DxeMeLib.h | Header file for functions to get Intel ME information
DxeMePolicyLib.h | Prototype of the DxeMePolicyLib library
DxePchPolicyLib.h | Prototype of the DxePchPolicyLib library
DxeSaPolicyLib.h | Prototype of the DxeSaPolicyLib library
DxeTbtCommonDefinition.h | TBT DXE Common Definition
DxeTbtDisBmeLib.h | Disable BME on TBT Hierarchy Lib
EspiConfig.h | Espi policy
EspiLib.h | Header file for PchEspiLib
FiaAccessLib.h | Header file for FiaAccessLib
FivrConfig.h | PCH FIVR policy
FlashProtectionConfig.h | FlashProtection policy
FlashRegs.h | Register names for Flash registers
FlashRegsVer2.h | Register names for Flash registers
FspErrorInfo.h | FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios
FspErrorInfoLib.h | Library to provide service for sending FSP error information to bootloader
FspmArchConfigPpi.h | Header file for FSP-M Arch Config PPI
FusaConfig.h | Functional Safety policy
FwStsSmbiosTable.h | Header file for Firmware Status Smbios Table Interface implementation
GbeConfig.h | Gigabit Ethernet policy
GbeLib.h | Header file for GbeLib
GetFsptApiParameter.h | Library to get FSP-T API parameter
GnaConfig.h | Policy definition for GNA Config Block
GnaInfoLib.h | This file provides GNA Public Library
GopComponentName2.h | Protocol to retrieve the GOP driver version
GopPolicy.h | Interface definition for GopPolicy Protocol
GpioConfig.h | Header file for GpioConfig structure used by GPIO library
GpioDevConfig.h | GPIO device policy
GpioLib.h | Header file for GpioLib
GpioNativeLib.h | Header file for GpioLib for native and Si specific usage
GpioPinsVer2H.h | GPIO pins for TGL-PCH-H,
GpioPinsVer2Lp.h | GPIO pins for TGL-PCH-LP,
GpioPinsVer4S.h | GPIO pins for ADL-PCH-S,
GpioRegs.h | Register names for PCH GPIO
GpioRegsVer2.h | Register names for VER2 GPIO
GpioRegsVer4.h | Register names for VER4 GPIO
GraphicsConfig.h | Policy definition for Internal Graphics Config Block
GraphicsInfoFruLib.h | Header file for Graphics Info Fru Lib implementation
GraphicsInfoLib.h | Header file for Graphics Private Info Lib implementation
Hda.h | Header file for HD Audio configuration
HdAudioConfig.h | HDAUDIO policy
HeciAccessPpi.h | ME HECI Access PPI - ME-BIOS communication over HECI in PEI
HeciAccessProtocol.h | ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM
HeciControlPpi.h | PEI Heci Control PPI - ME-BIOS communication over HECI in PEI
HeciControlProtocol.h | ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM
HeciFlowProtocol.h | HECI Flow Protocol
HeciPpi.h | PEI Heci PPI
HeciProtocol.h | HECI Protocol
HeciRegs.h | Register Definitions for HECI
HgInfoHob.h | This file contains information about Hybrid Graphics
HobUsageDataHob.h | Definitions for Hob Usage data HOB
HostBridgeConfig.h | Configurations for HostBridge
HostBridgeInfoLib.h | Header file for Host Bridge Info Lib implementation
HsioConfig.h | HSIO policy
HsioPcieConfig.h | HSIO pcie policy
HsioSataConfig.h | Hsio Sata policy
HybridGraphicsConfig.h | Hybrid Graphics policy definitions
HybridGraphicsInfoFruLib.h | Header file for Hybrid Graphics Info Fru Lib implementation
HybridStorageConfig.h | Hybrid Storage policy
IccMsgs.h | ICC Messages
IehConfig.h | Integrated Error Handler policy
IgdOpRegion.h | This file is part of the IGD OpRegion Implementation
IndustryStandardAsf.h | Include file for Industry Standard ASF definition
IntelAsfExtensions.h | Include file for Intel Extended ASF definition
InterruptConfig.h | Interrupt policy
IoApicConfig.h | IoApic policy
IoTrapExDispatch.h | PCH IO TrapEx Dispatch Protocol
IpuDataHob.h | This file defines the IPU DATA HOB
IpuLib.h | This file provides IPU Public Library
IpuPreMemConfig.h | IPU policy definitions
IshConfig.h | ISH policy
IshInfoLib.h | Ish Info Library header file
IshMsgs.h | ISH Messages
ITbtInfoHob.h | HOB definition to be used by iTBT during pre-boot enviornment
ITbtPolicy.h | Interface definition details between TBT and platform drivers during DXE phase
ItssLib.h | Header file for ItssLib
JhiProtocol.h | Header file for JHI (Intel DAL Host Interface Service) Protocol
LockDownConfig.h | Lock down policy
LpcConfig.h | Lpc policy
MbpSensitivePpi.h | MBP Sensitive PPI
MeBiosPayloadData.h | Interface definition details for MBP
MeBiosPayloadHob.h | This file contains definitions of ME BIOS Payload HOB
MebxConfigProtocol.h | MebxConfigProtocol definitions
MebxData.h | MEBx setup data definitions
MebxDisplayProtocol.h | MEBx Display Protocol definitions
MebxProtocol.h | EFI MEBx Protocol
MeChipsetLib.h | Header file for Me Chipset Lib
MeDataHob.h | The GUID definition for MeDataHob
MeDisabledEventHob.h | This file contains definition of ME Disabled Event HOB
MeDxeConfig.h | ME config block for DXE phase
MeEwlLib.h | Header file for ME Error Warning Log Lib
MeFirmwareVersionInfoHobGuid.h | ME Version Info HUB definition
MeFwHob.h | The GUID definition for MeFwHob
MeFwStsLib.h | Definition for Me FWSTS Lib
MeiBusMsg.h | Definitions for MEI Bus message support
MemInfo.h | This protocol provides the memory information data, such as total physical memory size, memory frequency, memory size of each dimm and rank
MemInfoHob.h | This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs
MemoryConfig.h | Policy definition of Memory Config Block
MemoryDxeConfig.h | Memory DXE Policy definitions
MemoryTypeInformation.h | This file defines: Memory Type Information GUID for HOB and Variable
MePeiConfig.h | ME config block for PEI phase
MePlatformGetResetType.h | Interface definition Me Platform Get Reset Type
MePolicy.h | Interface definition details between ME and platform drivers during DXE phase
MePolicyCommon.h | Definition for ME common policy
MePolicyHob.h | This file contains definitions of ME Policy HOB
MeRegs.h | Register definition for ME Devices
MeShowBufferLib.h | Definition for Me Debug Lib
MeSmbios.h | Header file for the MeSmbios Driver
MeSmbiosUpdateProtocol.h | MeSmbiosTablesUpdateProtocol definitions
MeState.h | Register Definitions for Me States
MeTypeDefs.h |
MeTypeLib.h | Header for ME type library
MeUefiFwHealthStatusLib.h | Definitions for Me Uefi Health Status Library
MeUtilsLib.h | HECI utilities for use in PEI, DXE, and SMM
MkhiMsgs.h | MKHI Messages
MmPciLib.h | Get Pci Express address library implementation
OcWdtLib.h | Header file for OC WDT Library
OneClickRecoveryProtocol.h | APIs for Intel One Click Recovery Main Protocol
OverclockingConfig.h | Overclocking Config Block
P2sbConfig.h | P2sb policy
P2sbLib.h | This file provides P2SB public library
PchAcpiSmiDispatch.h | APIs of PCH ACPI SMI Dispatch Protocol
PchCycleDecodingLib.h | Header file for PchCycleDecodingLib
PchDmi14Regs.h | Register names for PCH DMI SIP14
PchDmi15Regs.h | Register names for PCH DMI and OP-DMI
PchDmi17Regs.h | Register names for PCH DMI starting from SIP 17
PchDmiAccessLib.h | DMI library header for abstraction of DMI PCR registers access
PchDmiConfig.h | DMI policy
PchDmiHob.h | The GUID definition for CpuDmiHob
PchDmiRegs.h | Register names for PCH DMI and OP-DMI
PchEspiSmiDispatch.h | SmmEspiDispatch Protocol
PchGeneralConfig.h | PCH General policy
PchHybridStorageHob.h | Definitions required to create HybridStorageHob
PchInfoDefs.h | Header file for PchInfoDefs
PchInfoHob.h | This file contains definitions of PCH Info HOB
PchInfoLib.h | Header file for PchInfoLib
PchPciBdfLib.h | Header file for PchPciBdfLib
PchPcieRpConfig.h | PCH Pcie root port policy
PchPcieRpLib.h | Header file for PchPcieRpLib
PchPcieRpRegs.h | Register names for PCH PCI-E root port devices
PchPcieSmiDispatch.h | APIs of PCH PCIE SMI Dispatch Protocol
PchPcieStorageDetectHob.h | Definitions required to create PcieStorageInfoHob
PchPcrLib.h | Header file for PchPcrLib
PchPolicy.h | Interface definition details between Pch and platform drivers during DXE phase
PchPolicyCommon.h | PCH configuration based on PCH policy
PchPolicyLib.h | Prototype of the PeiPchPolicy library
PchPreMemPolicyCommon.h | PCH configuration based on PCH policy
PchRegs.h | Generic register definitions for PCH
PchRegsClk.h | Register names for iCLK device
PchRegsLpc.h | Register names for PCH LPC/eSPI device
PchRegsSmbus.h | Register names for PCH Smbus Device
PchResetPlatformSpecific.h | PCH Reset Platform Specific definitions
PchSmiDispatch.h | APIs of PCH SMI Dispatch Protocol
PchSmmControlLib.h | Header file for SMM Control PEI Library
PchSmmIoTrapControl.h | PCH SMM IO Trap Control Protocol
PchSmmPeriodicTimerControl.h | PCH SMM Periodic Timer Control Protocol
PchTcoSmiDispatch.h | APIs of PCH TCO SMI Dispatch Protocol
PcieConfig.h | PCIe Config Block
PcieDxeConfig.h | PCIE DXE policy definitions
PcieHelperLib.h | Header file for PCI Express helpers base library
PciePeiConfig.h | Policy definition for PCIe Config Block
PciePreMemConfig.h | PCIe Config Block PreMem
PcieRegs.h | Register names for PCIE standard register
PcieRpMacroDefinition.h | This file contains definitions of PCIE RP MACRO
PeiAmtPolicyLib.h | Prototype of the AmtPolicyLibPei library
PeiDxeSmmReserveMmio64SizeLib.h | PEI/DXE/SMM library for reserved 64-bit MMIO space
PeiITbtConfig.h | Header file for TBT PEI Policy
PeiITbtGenericStructure.h | ITBT Policy definition to be referred in both PEI and DXE phase
PeiITbtPolicyLib.h | Prototype of the PeiITbtPolicyLib library
PeiMeLib.h | Header file for PEI Me functionality
PeiMemPolicyLib.h | Header file for the PeiMemPolicyLib library
PeiMePolicyLib.h | Prototype of the MePolicyLibPei library
PeiMeServerPreMemPolicyLib.h | Prototype of the MeServerPolicyLibPei library
PeiPcieRpLib.h | Header file for PEI PCIe functionality
PeiPreMemSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PeiPreMemSiPolicyPrint.h | This file defines the PPI to print PEI Silicon PreMem Policy settings
PeiSaPolicyLib.h | Prototype of the PeiSaPolicy library
PeiSiDefaultPolicy.h | This file defines the function to initialize default silicon policy PPI
PeiSiPolicyPrint.h | This file defines the PPI to print PEI Silicon Policy settings
PeiSiPolicyUpdateLib.h | Header file for PEI SiPolicyUpdate Library
PeiTbtTaskDispatchLib.h | PEI TBT Task Dispatch library Header file
PeiVrDomainLib.h | Define Maximum Number of Voltage Regulator Domains
PlatformMeHook.h | Interface definition details for platform hook support to ME module during DXE phase
PlatformSpecificResetFilter.h | This Protocol provides services to register a platform specific reset filter for ResetSystem()
Ppi/PlatformSpecificResetHandler.h | This PPI provides services to register a platform specific handler for ResetSystem()
Protocol/PlatformSpecificResetHandler.h | This protocol provides services to register a platform specific handler for ResetSystem()
PlatformSpecificResetNotification.h | This PPI provides services to register a platform specific notification callback for ResetSystem()
PmcLib.h | Header file for PmcLib
PmConfig.h | Power Management policy
PmcRegs.h | Register names for PCH PMC device
PostCodeToScratchPadLib.h | Header file for writing the postcode value into scratchpad register
PreSiliconEnvDetectLib.h | Prototype of the PreSiliconEnvDetectLib library
PsfConfig.h | Primary Sideband Fabric policy
PsrMsgs.h | Definitions for querying PSR message
PsthLib.h | This file provides PSTH public library
PttHeciLib.h | Platform Trust Technology (PTT) HECI SkuMgr Library
PttPtpRegs.h | Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface)
ResetSystemLib.h | System reset Library Services
RstConfig.h | Rst policy
RstCrLib.h | Header file for RstCrLib
RtcAccessLib.h | RTC library header for abstraction of RTC PCR registers access
RtcConfig.h | RTC policy
RtcRegs.h | Register names for RTC device
SaDataHob.h | The GUID definition for SaDataHob
SaMiscPeiConfig.h | Policy details for miscellaneous configuration in System Agent
SaMiscPeiPreMemConfig.h | Policy details for miscellaneous configuration in System Agent
SaPcieDmiRegs.h | Register names for SA DMI and PEG
SaPlatformLib.h | Header file for SaPlatformLib
SaPolicy.h | Interface definition details between System Agent and platform drivers during DXE phase
SataConfig.h | Sata policy
SataLib.h | Header file for SataLib
SataRegs.h | Register names for SATA controllers
SataSocLib.h | Header file for SATA SoC library
ScsConfig.h | Scs policy
ScsInfoHob.h | The GUID definition for HOBs for SCS
SecPlatformLib.h | Prototype of SEC Platform hook library
SerialIoAccessLib.h | Header file for Serial Io Common Lib
SerialIoConfig.h | Serial IO policy
SerialIoDevices.h | Serial IO policy
SerialIoI2cLib.h | Basic I2C Librarary that allows I2C communication throguh Read/Write and Command Block operations
SerialIoI2cMasterLib.h | PEI I2C Initiator module
SerialIoI2cRegs.h | Register names for Serial IO I2C Controllers
SerialIoRegs.h | Register names for Serial IO Controllers
SerialIoSpiLib.h | Basic SPI Library that allows SPI communication through Read/Write/WriteRead operations
SerialIoSpiRegs.h | Register names for Serial IO SPI Controllers
SerialIoUartDebugPropertyPcdLib.h | SerialIo Uart Debug Property Pcd Library
SerialIoUartLib.h | Header file for Serial IO UART Lib implementation
SerialIoUartRegs.h | Register names for Serial IO UART Controllers
SiConfig.h | Si Config Block
SiConfigBlockLib.h | Prototype of the SiConfigBlockLib library
SiConfigHob.h | Silicon Config HOB is used for gathering platform related Intel silicon information and config setting
SiFvi.h | Header file for Reference code Firmware Version Info Init Lib implementation
SiFviLib.h | Header file for Reference code Firmware Version Info Interface Lib implementation
SiMtrrLib.h | Header file for Silicon code Mtrr Lib implementation
SiPolicyLib.h | Prototype of the SiPolicyLib library
SiPolicyProtocol.h | Protocol used for specifying platform related Silicon information and policy setting
SiPolicyStruct.h | Intel reference code configuration policies
SiPreMemConfig.h | Si Config Block PreMem
SmbiosCacheInfoHob.h | Header file for SMBIOS Cache Info HOB
SmbiosProcessorInfoHob.h | Header file for SMBIOS Processor Info HOB
SmbiosProcessorLib.h | Header file for SmbiosProcessorLib implementation
SmbusConfig.h | Smbus policy
SmbusInfoLib.h | This file provides Smbus public library
SmmControl.h | EFI SMM Control PPI definition
SmmResourceConfigProtocol.h | Protocol used for Configuring SMM Resources (IO / MSR)
SmmSmbus.h | SmmSmbus Protocol
SmmSpaLogOutputProtocol.h | This header file contains SPA log Output Protocol Interface
SmmVariable.h | EFI SMM Variable Protocol is related to EDK II-specific implementation of variables and intended for use as a means to store data in the EFI SMM environment
Ppi/Spi.h | This file defines the PCH SPI PPI which implements the Intel(R) PCH SPI Host Controller Compatibility Interface
Protocol/Spi.h | This file defines the PCH SPI Protocol which implements the Intel(R) PCH SPI Host Controller Compatibility Interface
SpiAccessLib.h | SPI library header for abstraction of SPI HW registers accesses
SpiConfig.h | PCH SPI Flash Controller config block
SpiLib.h | Header file for Spi Library
SsaPeiInit.h | Interface definition between MRC and SsaInit modules
StallPpiLib.h | Header file for a library to install StallPpi
SystemTimeLib.h | Header file for SystemTimeLib
TbtCommonLib.h | Header file of TBT common library
TbtDisBmeProtocol.h | Definitions for DisableBmeProtocol
TbtMailBoxCmdDefinition.h | Header file of TBT MailBox Command Definition shared by C and ASL code
TccLib.h | Header file for TCC Lib
TcoLib.h | Header file for TcoLib
TcoRegs.h | Register names for PCH TCO device
TcssDataHob.h | This file contains definitions of TCSS Data
TcssInfoLib.h | Header file for SmmTcss Private Info Lib implementation
TcssPeiConfig.h | TCSS PEI policy
TcssPeiPreMemConfig.h | TCSS PEI PreMem policy
TelemetryLib.h | Header file for TelemetryLib
TelemetryPeiConfig.h | Configurations for Telemetry
TelemetryRegs.h | Register names for Telemetry Conventions:
TempRamExitPpi.h | This file defines the Silicon Temp Ram Exit PPI which implements the MTRR values initialization
Thc.h | Touch Host Controller Protocol for Thc feature
ThcConfig.h | Touch Host Controller policy
ThcLib.h | Touch Host Controller Library
ThermalAccessLib.h | Thermal library header for abstraction of thermal registers access
ThermalConfig.h | Thermal policy
TmeInfoLib.h | Header file to get TME information
TopSwapLib.h | Header file for TopSwapLib
Tpm2CommandLib.h | This library is used by other modules to send TPM2 command
TpmInitialized.h | Tag GUID that must be installed by the TPM PEIM after the TPM hardware is initialized
TraceHubConfig.h | Configurations for TraceHub
TraceHubDataHob.h | The GUID definition for TraceHub Data Hob
TraceHubDebugLib.h | Definitions for the TraceHub Debug Lib
TraceHubHookLib.h | Definitions for the TraceHubHook Lib
TsnConfig.h | TSN Config policy
TsnLib.h | This file provides Tsn public library
Txt.h | This file contains definitions required to use the TXT BIOS Authenticated Code Module Library
TxtInfoHob.h | This file contains definitions required for creation of TXT Info HOB
TxtLib.h | Header file for TXT Lib implementation
UpidMsgs.h | Definitions for Unique Platform ID messages support
Usb2PhyConfig.h | USB2 PHY configuration policy
Usb3HsioConfig.h | USB3 Mod PHY configuration policy
UsbConfig.h | Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI
UsbLib.h | Header file of available functions in general USB Library
UsbRegs.h | Register names for USB Host and device controller
VmdInfoHob.h | This file contains information about VMD assigned devices
VmdPeiConfig.h | VMD PEI policy
VoltageRegulatorCommands.h | Header file containing Voltage Regulator initialization common definitions
VtdConfig.h | VT-d policy definitions
VtdInfoLib.h | Header file for VtdInfoLib
WatchDogConfig.h | WatchDog policy
Ppi/Wdt.h | Watchdog Timer PPI
Protocol/Wdt.h | Watchdog Timer protocol
WifiProfileSyncAsfMsgs.h | Supporting functions for profile sync driver ASF communication
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AcpiDebug.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
AcpiDebug.h File Reference

Header file for ACPI ADBG enable/disable. More...

Go to the source code of this file.

Detailed Description

Header file for ACPI ADBG enable/disable.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AcpiDebug.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AcpiDebug.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
AcpiDebug.h
Go to the documentation of this file.
1 /** @file
2 Header file for ACPI ADBG enable/disable.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ACPI_DEBUG_H_
36 #define _ACPI_DEBUG_H_
37
38 #if FixedPcdGetBool(PcdAcpiDebugEnableFlag) == 1 //PcdAcpiDebugEnableFlag can be updated in BoardPkgPcdInit.dsc
39 #define ADBG(x) ADBG(x) //leave it as it is
40 #define ASRT(x, y) ASRT(x, y)
41 #define ACPI_DEBUG_EXTERNAL_REFERENCE External(\ADBG, MethodObj) //additional define statement to cover ADBG external references
42 #define ACPI_ASSERT_EXTERNAL_REFERENCE External(\_SB.ASRT, MethodObj)
43 #else
44 #define ADBG(x) //remove all ADBG and ASRT references
45 #define ASRT(x, y)
46 #define ACPI_DEBUG_EXTERNAL_REFERENCE //remove all external references for ADBG and ASRT
47 #define ACPI_ASSERT_EXTERNAL_REFERENCE
48 #endif
49 #endif
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AcpiS3Context.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
AcpiS3Context.h File Reference

Definitions for data structures used in S3 resume. More...

#include <Library/BaseLib.h>
Include dependency graph for AcpiS3Context.h:

Go to the source code of this file.

Detailed Description

Definitions for data structures used in S3 resume.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file AcpiS3Context.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AcpiS3Context.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
AcpiS3Context.h
Go to the documentation of this file.
1 /** @file
2 Definitions for data structures used in S3 resume.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>
7
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions
10 of the BSD License which accompanies this distribution. The
11 full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #ifndef _ACPI_S3_DATA_H_
20 #define _ACPI_S3_DATA_H_
21
22 #include <Library/BaseLib.h>
23
24 #define SMM_S3_RESUME_SMM_32 SIGNATURE_64 ('S','M','M','S','3','_','3','2')
25 #define SMM_S3_RESUME_SMM_64 SIGNATURE_64 ('S','M','M','S','3','_','6','4')
26
27 #pragma pack(1)
28
29 typedef struct {
30 UINT64 Signature;
31 EFI_PHYSICAL_ADDRESS SmmS3ResumeEntryPoint;
32 EFI_PHYSICAL_ADDRESS SmmS3StackBase;
33 UINT64 SmmS3StackSize;
34 UINT64 SmmS3Cr0;
35 UINT64 SmmS3Cr3;
36 UINT64 SmmS3Cr4;
37 UINT16 ReturnCs;
38 EFI_PHYSICAL_ADDRESS ReturnEntryPoint;
39 EFI_PHYSICAL_ADDRESS ReturnContext1;
40 EFI_PHYSICAL_ADDRESS ReturnContext2;
41 EFI_PHYSICAL_ADDRESS ReturnStackPointer;
42 EFI_PHYSICAL_ADDRESS Smst;
43 } SMM_S3_RESUME_STATE;
44
45
46 typedef struct {
47 EFI_PHYSICAL_ADDRESS AcpiFacsTable;
48 EFI_PHYSICAL_ADDRESS IdtrProfile;
49 EFI_PHYSICAL_ADDRESS S3NvsPageTableAddress;
50 EFI_PHYSICAL_ADDRESS BootScriptStackBase;
51 UINT64 BootScriptStackSize;
52 EFI_PHYSICAL_ADDRESS S3DebugBufferAddress;
53 } ACPI_S3_CONTEXT;
54
55 typedef struct {
56 UINT16 ReturnCs;
57 UINT64 ReturnStatus;
58 EFI_PHYSICAL_ADDRESS ReturnEntryPoint;
59 EFI_PHYSICAL_ADDRESS ReturnStackPointer;
60 EFI_PHYSICAL_ADDRESS AsmTransferControl;
61 IA32_DESCRIPTOR Idtr;
62 } PEI_S3_RESUME_STATE;
63
64 #pragma pack()
65
66 #define EFI_ACPI_S3_CONTEXT_GUID \
67 { \
68 0xef98d3a, 0x3e33, 0x497a, {0xa4, 0x1, 0x77, 0xbe, 0x3e, 0xb7, 0x4f, 0x38} \
69 }
70
71 extern EFI_GUID gEfiAcpiS3ContextGuid;
72
73 extern EFI_GUID gEfiAcpiVariableGuid;
74
75 #endif
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AdrConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes
AdrConfig.h File Reference

ADR policy. More...

#include <ConfigBlock.h>
Include dependency graph for AdrConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | ADR_SOURCE_ENABLE
ADR Source Enable. More...
struct | ADR_CONFIG
ADR Configuration Revision 1: - Initial version. More...

Detailed Description

ADR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file AdrConfig.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AdrConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
AdrConfig.h
Go to the documentation of this file.
1 /** @file
2 ADR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ADR_CONFIG_H_
36 #define _ADR_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define ADR_CONFIG_REVISION 1
41 extern EFI_GUID gAdrConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 AdrScale1us,
47 AdrScale10us,
48 AdrScale100us,
49 AdrScale1ms,
50 AdrScale10ms,
51 AdrScale100ms,
52 AdrScale1s,
53 AdrScale10s
54 } ADR_TIMER_SCALE;
55
56 /**
57 ADR Source Enable
58 **/
59 typedef union {
60 struct {
61 UINT32 Reserved1 : 1;
62 UINT32 AdrSrcPbo : 1;
63 UINT32 AdrSrcPmcUncErr : 1;
64 UINT32 AdrSrcPchThrm : 1;
65 UINT32 AdrSrcMePbo : 1;
66 UINT32 AdrSrcCpuThrm : 1;
67 UINT32 AdrSrcMegbl : 1;
68 UINT32 AdrSrcLtReset : 1;
69 UINT32 AdrSrcPmcWdt : 1;
70 UINT32 AdrSrcMeWdt : 1;
71 UINT32 AdrSrcPmcFw : 1;
72 UINT32 AdrSrcPchpwrFlr : 1;
73 UINT32 AdrSrcSyspwrFlr : 1;
74 UINT32 Reserved2 : 1;
75 UINT32 AdrSrcMiaUxsErr : 1;
76 UINT32 AdrSrcMiaUxErr : 1;
77 UINT32 AdrSrcCpuThrmWdt : 1;
78 UINT32 AdrSrcMeUncErr : 1;
79 UINT32 AdrSrcAdrGpio : 1;
80 UINT32 AdrSrcOcwdtNoicc : 1;
81 UINT32 AdrSrcOcwdtIcc : 1;
82 UINT32 AdrSrcCseHecUncErr : 1;
83 UINT32 AdrSrcPmcSramUncErr : 1;
84 UINT32 AdrSrcPmcIromParity : 1;
85 UINT32 AdrSrcPmcRfFusaErr : 1;
86 UINT32 Reserved3 : 4;
87 UINT32 AdrSrcPpbrParityErr : 1;
88 UINT32 Reserved4 : 2;
89 } Field;
90 UINT32 Value;
91 } ADR_SOURCE_ENABLE;
92
93 /**
94 ADR Configuration
95 <b>Revision 1</b>: - Initial version.
96 **/
97 typedef struct {
98 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
99 UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
100 UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
101 UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
102 UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
103 UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
104 UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
105 UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
106 UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
107 UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
108 UINT32 ReservedBits : 1;
109 ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
110 } ADR_CONFIG;
111
112 #pragma pack (pop)
113
114 #endif // _ADR_CONFIG_H_
ADR_CONFIG::AdrSrcSel
ADR_SOURCE_ENABLE AdrSrcSel
Determine which ADR sources are enabled - 0: Enabled, 1: Disabled.
Definition: AdrConfig.h:109
ADR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AdrConfig.h:98
ConfigBlock.h
Header file for Config Block Lib implementation.
ADR_CONFIG::AdrSrcOverride
UINT32 AdrSrcOverride
Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten.
Definition: AdrConfig.h:106
ADR_CONFIG::AdrHostPartitionReset
UINT32 AdrHostPartitionReset
Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:105
ADR_CONFIG::AdrTimerEn
UINT32 AdrTimerEn
Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:100
ADR_CONFIG::AdrTimer1Val
UINT32 AdrTimer1Val
Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer.
Definition: AdrConfig.h:101
ADR_CONFIG::AdrMultiplier2Val
UINT32 AdrMultiplier2Val
Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:104
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ADR_CONFIG::AdrPlatAckEn
UINT32 AdrPlatAckEn
Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:107
ADR_CONFIG
ADR Configuration Revision 1: - Initial version.
Definition: AdrConfig.h:97
ADR_CONFIG::AdrMultiplier1Val
UINT32 AdrMultiplier1Val
Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to...
Definition: AdrConfig.h:102
ADR_CONFIG::AdrTimer2Val
UINT32 AdrTimer2Val
Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer.
Definition: AdrConfig.h:103
ADR_CONFIG::AdrEn
UINT32 AdrEn
Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE.
Definition: AdrConfig.h:99
ADR_SOURCE_ENABLE
ADR Source Enable.
Definition: AdrConfig.h:59
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Classes | Typedefs | Enumerations
AmtConfig.h File Reference

AMT Config Block for PEI/DXE phase. More...

#include <Library/ConfigBlockLib.h>
#include <ConfigBlock.h>
Include dependency graph for AmtConfig.h:

Go to the source code of this file.

Classes

struct | AMT_PEI_CONFIG
AMT Pei Configuration Structure. More...
struct | AMT_DXE_CONFIG
AMT Dxe Configuration Structure. More...

Typedefs

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message. More...

Enumerations

enum AMT_ERROR_MSG_ID
AMT Error Message ID.

Detailed Description

AMT Config Block for PEI/DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtConfig.h.

Typedef Documentation

◆ AMT_REPORT_ERROR

typedef VOID(* AMT_REPORT_ERROR) (IN AMT_ERROR_MSG_ID MsgId)

Show AMT Error message.

This is to display localized message in the console. This is used to display message strings in local language. To display the message, the routine will check the message ID and ConOut the message strings. For example, the End of Post error displayed in English will be: gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of Post message to ME\n"); It is recommended to clear the screen before displaying the error message and keep the message on the screen for several seconds. A sample is provided, see ShowAmtReportError () to retrieve details.

Parameters
[in] MsgId AMT error message ID for displaying on screen message

Definition at line 75 of file AmtConfig.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
AmtConfig.h
Go to the documentation of this file.
1 /** @file
2 AMT Config Block for PEI/DXE phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_CONFIG_H_
36 #define _AMT_CONFIG_H_
37
38 #include <Library/ConfigBlockLib.h>
39 #include <ConfigBlock.h>
40
41 #define AMT_PEI_CONFIG_REVISION 1
42 extern EFI_GUID gAmtPeiConfigGuid;
43
44 #define AMT_DXE_CONFIG_REVISION 1
45 extern EFI_GUID gAmtDxeConfigGuid;
46
47 ///
48 /// AMT Error Message ID
49 ///
50 typedef enum {
51 MSG_ASF_BOOT_DISK_MISSING,
52 MSG_KVM_TIMES_UP,
53 MSG_KVM_REJECTED,
54 MSG_KVM_WAIT,
55 MAX_AMT_ERROR_ENUM
56 } AMT_ERROR_MSG_ID;
57
58 /**
59 Show AMT Error message. This is to display localized message in
60 the console. This is used to display message strings in local
61 language. To display the message, the routine will check the
62 message ID and ConOut the message strings. For example, the
63 End of Post error displayed in English will be:
64 gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of
65 Post message to ME\n"); It is recommended to clear the screen
66 before displaying the error message and keep the message on
67 the screen for several seconds.
68 A sample is provided, see ShowAmtReportError () to retrieve
69 details.
70
71 @param[in] MsgId AMT error message ID for displaying on screen message
72
73 **/
74 typedef
75 VOID
76 (*AMT_REPORT_ERROR) (
77 IN AMT_ERROR_MSG_ID MsgId
78 );
79
80
81 #pragma pack (1)
82
83 /**
84 AMT Pei Configuration Structure.
85
86 <b>Revision 1</b>:
87 - Initial version.
88 **/
89 typedef struct {
90 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
91 /**
92 Enable or Disable Intel Active Management Technology feature.
93 If disabled, all Intel AMT features, including Alert Standard Format features, will not be supported.
94 0: Disable
95 <b>1: Enable.</b>
96 **/
97 UINT32 AmtEnabled : 1;
98 /**
99 ME WatchDog timer feature. If disabled, below WatchDogTimerOs/WatchDogTimerBios will be irrelevant.
100 See WatchDogTimerOs and WatchDogTimerBios description.
101 <b>0: Disable</b>
102 1: Enable ME WDT if corresponding timer value is not zero.
103 **/
104 UINT32 WatchDogEnabled : 1;
105 UINT32 FwProgress : 1; ///< PET Events Progress to receive PET Events. 0: Disable; <b>1: Enable</b>
106 UINT32 ManageabilityMode : 1; ///< @deprecated: Manageability Mode sync with Mebx, 0: Disabled; <b>1: AMT</b>
107 UINT32 AmtSolEnabled : 1; ///< Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, <b>1: Enable</b>
108 UINT32 RemoteAssistance : 1; ///< @deprecated: Remote Assistance is enabled if platform is provisioned. <b>0: Disable</b>, 1: Enable
109 UINT32 AmtKvmEnabled : 1; ///< @deprecated: KVM retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable, <b>1: Enable</b>
110 UINT32 ForcMebxSyncUp : 1; ///< <b>0: No</b>; 1: Force MEBX execution
111 UINT32 RsvdBits : 24; ///< Reserved for future use & Config block alignment
112 /**
113 OS WatchDog Timer
114 <b>0: Disable</b> OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled is 1.
115 Non zero value - OS WDT will be started after stopping BIOS WDT if WatchDogEnabled is 1. The timer is set
116 according to the value.
117 **/
118 UINT16 WatchDogTimerOs;
119 /**
120 BIOS WatchDog Timer
121 <b>0: Disable</b> BIOS WDT won't be started even if WatchDogEnabled is 1.
122 Non zero value - The BIOS WDT is set according to the value and started if WatchDogEnabled is 1.
123 **/
124 UINT16 WatchDogTimerBios;
125 } AMT_PEI_CONFIG;
126
127
128 /**
129 AMT Dxe Configuration Structure.
130
131 <b>Revision 1</b>:
132 - Initial version.
133 **/
134 typedef struct {
135 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
136 UINT32 CiraRequest : 1; ///< Trigger CIRA boot. <b>0: No CIRA request</b>; 1: Trigger CIRA request
137 UINT32 UnConfigureMe : 1; ///< OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. <b>0: No</b>; 1: Un-configure ME without password
138 UINT32 MebxDebugMsg : 1; ///< @deprecated: OEMFlag Bit 14: Enable OEM debug menu in MEBx. <b>0: Disable</b>; 1: Enable
139 UINT32 HideUnConfigureMeConfirm : 1; ///< @deprecated: OEMFlag Bit 6: Hide Unconfigure ME confirmation prompt when attempting ME unconfiguration. <b>0: Don't hide</b>; 1: Hide
140 UINT32 UsbProvision : 1; ///< Enable/Disable of AMT USB Provisioning. <b>0: Disable</b>; 1: Enable
141 UINT32 AmtbxHotkeyPressed : 1; ///< @deprecated: OEMFlag Bit 1: Enable automatic MEBx hotkey press. <b>0: Disable</b>; 1: Enable
142 /**
143 OEMFlag Bit 2: Enable MEBx selection screen with 2 options:
144 Press 1 to enter ME Configuration Screens
145 Press 2 to initiate a remote connection
146 - <b>0: Disabled</b>
147 - 1: Enabled
148 **/
149 UINT32 AmtbxSelectionScreen : 1; ///< @deprecated
150 UINT32 RsvdBits : 25; ///< Reserved for future use & Config block alignment
151 UINT32 CiraTimeout : 8; ///< @deprecated
152 /**
153 CPU Replacement Timeout
154 <b>0: 10 seconds</b>
155 1: 30 seconds
156 2~5: Reserved
157 6: No delay
158 7: Unlimited delay
159 **/
160 UINT32 CpuReplacementTimeout : 8; ///< @deprecated
161 UINT32 MebxNonUiTextMode : 4; ///< @deprecated: Resolution for non-UI text mode. <b>0: Auto</b>; 1: 80x25; 2: 100x31
162 UINT32 MebxUiTextMode : 4; ///< @deprecated: Resolution for UI text mode. <b>0: Auto</b>; 1: 80x25; 2: 100x31
163 UINT32 MebxGraphicsMode : 4; ///< @deprecated: Resolution for graphics mode. <b>0: Auto</b>; 1: 640x480; 2: 800x600; 3: 1024x768
164 UINT32 OemResolutionSettingsRsvd : 4; ///< @deprecated: Reserved for future use & Config block alignment
165 /**
166 Function pointer for displaying error message on screen
167 **/
168 AMT_REPORT_ERROR AmtReportError;
169 } AMT_DXE_CONFIG;
170
171 #pragma pack ()
172
173 #endif // _AMT_CONFIG_H_
AMT_PEI_CONFIG::FwProgress
UINT32 FwProgress
PET Events Progress to receive PET Events. 0: Disable; 1: Enable
Definition: AmtConfig.h:105
AMT_DXE_CONFIG::AmtbxHotkeyPressed
UINT32 AmtbxHotkeyPressed
Definition: AmtConfig.h:141
ConfigBlock.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::AmtbxSelectionScreen
UINT32 AmtbxSelectionScreen
OEMFlag Bit 2: Enable MEBx selection screen with 2 options: Press 1 to enter ME Configuration Screens...
Definition: AmtConfig.h:149
AMT_DXE_CONFIG::CiraRequest
UINT32 CiraRequest
Trigger CIRA boot. 0: No CIRA request; 1: Trigger CIRA request.
Definition: AmtConfig.h:136
AMT_PEI_CONFIG
AMT Pei Configuration Structure.
Definition: AmtConfig.h:89
AMT_PEI_CONFIG::AmtSolEnabled
UINT32 AmtSolEnabled
Serial Over Lan retrieved from Mebx. The default value depends on CSME/AMT. 0: Disable,...
Definition: AmtConfig.h:107
AMT_DXE_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:150
AMT_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:90
AMT_PEI_CONFIG::AmtEnabled
UINT32 AmtEnabled
Enable or Disable Intel Active Management Technology feature.
Definition: AmtConfig.h:97
AMT_DXE_CONFIG::OemResolutionSettingsRsvd
UINT32 OemResolutionSettingsRsvd
Definition: AmtConfig.h:164
AMT_ERROR_MSG_ID
AMT_ERROR_MSG_ID
AMT Error Message ID.
Definition: AmtConfig.h:50
AMT_PEI_CONFIG::WatchDogTimerOs
UINT16 WatchDogTimerOs
OS WatchDog Timer 0: Disable OS WDT won't be started after stopping BIOS WDT even if WatchDogEnabled ...
Definition: AmtConfig.h:118
AMT_DXE_CONFIG::HideUnConfigureMeConfirm
UINT32 HideUnConfigureMeConfirm
Definition: AmtConfig.h:139
AMT_DXE_CONFIG::CpuReplacementTimeout
UINT32 CpuReplacementTimeout
CPU Replacement Timeout 0: 10 seconds 1: 30 seconds 2~5: Reserved 6: No delay 7: Unlimited delay.
Definition: AmtConfig.h:160
AMT_REPORT_ERROR
VOID(* AMT_REPORT_ERROR)(IN AMT_ERROR_MSG_ID MsgId)
Show AMT Error message.
Definition: AmtConfig.h:76
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
AMT_PEI_CONFIG::AmtKvmEnabled
UINT32 AmtKvmEnabled
Definition: AmtConfig.h:109
AMT_DXE_CONFIG::MebxGraphicsMode
UINT32 MebxGraphicsMode
Definition: AmtConfig.h:163
AMT_DXE_CONFIG::MebxUiTextMode
UINT32 MebxUiTextMode
Definition: AmtConfig.h:162
AMT_DXE_CONFIG::CiraTimeout
UINT32 CiraTimeout
Definition: AmtConfig.h:151
AMT_PEI_CONFIG::RemoteAssistance
UINT32 RemoteAssistance
Definition: AmtConfig.h:108
AMT_DXE_CONFIG::UsbProvision
UINT32 UsbProvision
Enable/Disable of AMT USB Provisioning. 0: Disable; 1: Enable.
Definition: AmtConfig.h:140
ConfigBlockLib.h
Header file for Config Block Lib implementation.
AMT_DXE_CONFIG::MebxNonUiTextMode
UINT32 MebxNonUiTextMode
Definition: AmtConfig.h:161
AMT_DXE_CONFIG::AmtReportError
AMT_REPORT_ERROR AmtReportError
Function pointer for displaying error message on screen.
Definition: AmtConfig.h:168
AMT_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: AmtConfig.h:111
AMT_DXE_CONFIG::MebxDebugMsg
UINT32 MebxDebugMsg
Definition: AmtConfig.h:138
AMT_DXE_CONFIG::UnConfigureMe
UINT32 UnConfigureMe
OEMFlag Bit 15: Unconfigure ME with resetting MEBx password to default. 0: No; 1: Un-configure ME wit...
Definition: AmtConfig.h:137
AMT_PEI_CONFIG::WatchDogEnabled
UINT32 WatchDogEnabled
ME WatchDog timer feature.
Definition: AmtConfig.h:104
AMT_PEI_CONFIG::ForcMebxSyncUp
UINT32 ForcMebxSyncUp
0: No; 1: Force MEBX execution
Definition: AmtConfig.h:110
AMT_PEI_CONFIG::WatchDogTimerBios
UINT16 WatchDogTimerBios
BIOS WatchDog Timer 0: Disable BIOS WDT won't be started even if WatchDogEnabled is 1.
Definition: AmtConfig.h:124
AMT_DXE_CONFIG
AMT Dxe Configuration Structure.
Definition: AmtConfig.h:134
AMT_PEI_CONFIG::ManageabilityMode
UINT32 ManageabilityMode
Definition: AmtConfig.h:106
AMT_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: AmtConfig.h:135
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmthiMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
AmthiMsgs.h File Reference

AMTHI Messages. More...

#include <Uefi/UefiBaseType.h>
Include dependency graph for AmthiMsgs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | CFG_GET_INTERFACE_VERSION_RESPONSE
Get Interface Version. More...
struct | CFG_UNPROVISION_REQUEST
Unprovision. More...
struct | CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST
Set Sol/Storage Redirection. More...
struct | CFG_GET_ZTC_ENABLED_STATUS_REQUEST
Get/Set ZTC Enabled Status. More...
struct | CFG_GET_IDLE_TIMEOUT_REQUEST
Get/Set Idle Timeout Request. More...
struct | CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST
Open/Close/Query User Initiatied Connection for CIRA. More...
struct | CFG_GET_FQDN_REQUEST
Get/Set Fqdn. More...
struct | CFG_GET_REDIRECTION_STATE_REQUEST
Get Redirection Features State. More...
struct | CFG_COMPLETE_CONFIGURATION_REQUEST
Complete Configuration. More...
struct | CFG_STOP_CONFIGURATION_REQUEST
Stop/Start Configuration. More...
struct | CFG_SET_KVM_ENABLED_REQUEST
Get/Set KVM State. More...
struct | CFG_GET_PRIVACY_LEVEL_REQUEST
Get AMT Privacy Level. More...
struct | CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE
Get OptIn Change Availability. More...
struct | AMT_SCREEN_RESOLUTION
Get GFX UI Info/Fragment. More...

Macros

#define | MAXSEG 4
Get / Set IPV4 Settings.
#define | MAX_HASH_ENTRIES 33
Certificate Hash Operations: Enumerate Hash Entries/Get Cert Hash Entry/Set Cert Hash State/ Add Customized Cert Hash/Delete Customized Cert Hash.
#define | CERT_NAME_MAX_ASCII_STRING 32 + 1
Certificate name + null termination.
#define | MAX_ADDRESS_LENGTH 256
Get/Set PKI FQDN Suffix.
#define | CFG_IPV6_ADDR_LEN_MAX 46
Get/Set Config Server Data.
#define | MAX_INTERFACE_ID 17
Get/Set IPV6 LAN Interface Settings.
#define | MAX_PWR_PKG_COUNT 3
Enumerate Power Packages Get/Set Active Power Package.

Enumerations

enum | AMT_STATUS
AMT Status Enum.
enum | AMTHI_COMMAND
AMTHI Commands Enum.
enum | PT_PROVISIONING_STATE
Get Provision Status.
enum | CFG_EOP_STATE
Get Eop State.
enum | AMTHI_PROVISION_MODE
Partial Unprovision.
enum | LAN_INTERFACE
Get LAN Interface Settings.
enum | CFG_MEBX_PWD_CHANGE_POLICY
Get/Set MEBx Password Change Policy.
enum | PROVISIONING_TLS_MODE
Get Me Setup Audit Record.
enum | CFG_UNPROVISIONING_STATE
Get Unprovisioning State.
enum | AMT_MEBX_STATE
Set MEBx state.
enum | AMT_CONTROL_MODE
Get Control Mode.
enum | OPTIN_POLICY_BITMAP
Get/Set OptIn State.
enum | AMT_MEBX_USER_INPUT
Get UI Action.

Detailed Description

AMTHI Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmthiMsgs.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmthiMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
AmthiMsgs.h
Go to the documentation of this file.
1 /** @file
2 AMTHI Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _AMTHI_MSGS_H_
37 #define _AMTHI_MSGS_H_
38
39 #include <Uefi/UefiBaseType.h>
40
41 #pragma pack(1)
42
43 ///
44 /// AMT Status Enum
45 ///
46 typedef enum {
47 AmtStatusSuccess = 0,
48 AmtStatusInternalError = 1,
49 AmtStatusNotReady = 2,
50 AmtStatusInvalidPtMode = 3,
51 AmtStatusInvalidMessageLength = 4,
52 AmtStatusTableFingerprintNotAvailable = 5,
53 AmtStatusIntegrityCheckFailed = 6,
54 AmtStatusUnsupportedIsvsVersion = 7,
55 AmtStatusApplicationNotRegistered = 8,
56 AmtStatusInvalidRegistrationData = 9,
57 AmtStatusApplicationDoesNotExist = 10,
58 AmtStatusNotEnoughStorage = 11,
59 AmtStatusInvalidName = 12,
60 AmtStatusBlockDoesNotExist = 13,
61 AmtStatusInvalidByteOffset = 14,
62 AmtStatusInvalidByteCount = 15,
63 AmtStatusNotPermitted = 16,
64 AmtStatusNotOwner = 17,
65 AmtStatusBlockLockedByOther = 18,
66 AmtStatusBlockNotLocked = 19,
67 AmtStatusInvalidGroupPermissions = 20,
68 AmtStatusGroupDoesNotExist = 21,
69 AmtStatusInvalidMemberCount = 22,
70 AmtStatusMaxLimitReached = 23,
71 AmtStatusInvalidAuthType = 24,
72 AmtStatusAuthenticationFailed = 25,
73 AmtStatusInvalidDhcpMode = 26,
74 AmtStatusInvalidIpAddress = 27,
75 AmtStatusInvalidDomainName = 28,
76 AmtStatusUnsupportedVersion = 29,
77 AmtStatusRequestUnexpected = 30,
78 AmtStatusInvalidTableType = 31,
79 AmtStatusInvalidProvisioningMode = 32,
80 AmtStatusUnsupportedObject = 33,
81 AmtStatusInvalidTime = 34,
82 AmtStatusInvalidIndex = 35,
83 AmtStatusInvalidParameter = 36,
84 AmtStatusInvalidNetmask = 37,
85 AmtStatusFlashWriteLimitExceeded = 38,
86 AmtStatusInvalidImageLength = 39,
87 AmtStatusInvalidImageSignature = 40,
88 AmtStatusProposeAnotherVersion = 41,
89 AmtStatusInvalidPidFormat = 42,
90 AmtStatusInvalidPpsFormat = 43,
91 AmtStatusBistCommandBlocked = 44,
92 AmtStatusConnectionFailed = 45,
93 AmtStatusConnectionTooMany = 46,
94 AmtStatusRngGenerationInProgress = 47,
95 AmtStatusRngNotReady = 48,
96 AmtStatusCertificateNotReady = 49,
97 AmtStatusAuditRecordNotPrersent = 50,
98 AmtStatusRedirectionInProgress = 51,
99 AmtStatusIpSyncEnabled = 52,
100 AmtStatusRemoteAccessNotGranted = 512,
101 AmtStatusRemoteAccessHostVpnIsDisabled = 513,
102 AmtStatusSuccessWithoutDdns = 514,
103 AmtStatusSuccessWithDdns = 515,
104 AmtStatusDisabledByPolicy = 1024,
105 AmtStatusNetworkIfErrorBase = 2048,
106 AmtStatusInvalidHandle = 2053,
107 AmtStatusInvalidPassword = 2054,
108 AmtStatusDataMissing = 2057,
109 AmtStatusUnsupported = 2066,
110 AmtStatusNotFound = 2068,
111 AmtStatusNoAssociation = 2072,
112 AmtStatusAuditFail = 2075,
113 AmtStatusBlockingComponent = 2076,
114 AmtStatusDestinationUnreachable = 2077,
115 AmtStatusUpdateInProgress = 2078,
116 AmtStatusInvalidId = 2079,
117 AmtStatusDeleted = 2080,
118 AmtStatusNoData = 2081,
119 AmtStatusIpv6InterfaceDisabled = 2500,
120 AmtStatusInterfaceDoesNotExist = 2501,
121 AmtStatusIpv6IllegalInterfaceId = 2502,
122 AmtStatusIpv6IllegalStaticAddress = 2503,
123 AmtStatusIpv6IllegalRouterAddress = 2504,
124 AmtStatusIpv6IllegalDnsAddress = 2505,
125 AmtStatusSdkDefinedErrorBase = 4096
126 } AMT_STATUS;
127
128 ///
129 /// AMTHI Commands Enum
130 ///
131 typedef enum {
132 AmthiCfgGetInterfaceVersion = 0x04000000,
133 AmthiCfgGetTcpipParameters = 0x04000006,
134 AmthiCfgSetTcpipParameters = 0x04000007,
135
136 AmthiCfgUnprovision = 0x04000010,
137 AmthiCfgGetProvisioningState = 0x04000011,
138 AmthiCfgSetSolStorageRedirStatus = 0x04000014,
139
140 AmthiCfgGetEndOfPostState = 0x04000020,
141 AmthiCfgPartialUnprovision = 0x04000024,
142 AmthiCfgGetProvisioningTlsMode = 0x0400002B,
143 AmthiCfgEnumerateHashHandles = 0x0400002C,
144 AmthiCfgGetCertificateHashEntry = 0x0400002D,
145 AmthiCfgSetPkiFqdnSuffix = 0x0400002F,
146
147 AmthiCfgGetZtcEnabledStatus = 0x04000030,
148 AmthiCfgGetIdleTimeout = 0x04000031,
149 AmthiCfgSetIdleTimeout = 0x04000032,
150 AmthiCfgGetPkiFqdnSuffix = 0x04000036,
151 AmthiCfgSetCertificateHashState = 0x04000037,
152 AmthiCfgAddCustomizedCertificateHashEntry = 0x04000038,
153 AmthiCfgDeleteCustomizedCertificateHashEntry = 0x04000039,
154 AmthiCfgSetZeroTouchEnabled = 0x0400003A,
155
156 AmthiCfgOpenUserInitiatedConnection = 0x04000044,
157 AmthiCfgCloseUserInitiatedConnection = 0x04000045,
158 AmthiCfgGetRemoteAccessConnectionStatus = 0x04000046,
159 AmthiCfgGetLanInterfaceSettings = 0x04000048,
160 AmthiCfgSetMebxPwdChangePolicy = 0x0400004B,
161 AmthiCfgGetMebxPwdChangePolicy = 0x0400004C,
162 AmthiCfgGetConfigServerData = 0x0400004E,
163 AmthiCfgSetConfigServerData = 0x0400004F,
164
165 AmthiCfgGetMeSetupAuditRecord = 0x04000050,
166 AmthiCfgGetIpv6LanInterfaceStatus = 0x04000052,
167 AmthiCfgSetIpv6LanInterfaceSettings = 0x04000054,
168 AmthiCfgGetFqdn = 0x04000056,
169 AmthiCfgSetFqdn = 0x04000057,
170 AmthiCfgGetRedirectionState = 0x04000058,
171 AmthiCfgCompleteConfiguration = 0x0400005A,
172 AmthiCfgStopConfiguration = 0x0400005E,
173
174 AmthiCfgStartConfigurationEx = 0x04000062,
175 AmthiCfgGetUnprovisioningState = 0x04000068,
176 AmthiCfgSetMebxState = 0x0400006A,
177 AmthiCfgGetControlMode = 0x0400006B,
178 AmthiCfgSetOptInState = 0x0400006C,
179 AmthiCfgGetOptInState = 0x0400006D,
180 AmthiCfgSetKvmEnabled = 0x0400006E,
181 AmthiCfgGetKvmEnabled = 0x0400006F,
182
183 AmthiCfgGetPrivacyLevel = 0x04000075,
184 AmthiCfgGetOptInChangeAvailable = 0x04000076,
185 AmthiCfgUiAction = 0x04000077,
186 AmthiCfgGetGfxUiInfo = 0x04000078,
187 AmthiCfgGetGfxFragment = 0x04000079,
188 AmthiCfgEnumeratePowerPackages = 0x04000080,
189 AmthiCfgGetCurrentPowerPackage = 0x04000081,
190 AmthiCfgGetPowerPackageInfo = 0x04000082,
191 AmthiCfgSetPowerPackage = 0x04000083
192 } AMTHI_COMMAND;
193
194 #define AMTHI_VERSION_MINOR 0x01
195 #define AMTHI_VERSION_MAJOR 0x01
196
197 typedef struct {
198 UINT8 MajorVersion;
199 UINT8 MinorVersion;
200 } AMTHI_VERSION;
201
202 #define AMTHI_MESSAGE_BYTE_COUNT_MAP(a) (a-sizeof(AMTHI_HEADER))
203
204 typedef struct {
205 AMTHI_VERSION Version;
206 UINT16 Reserved;
207 UINT32 Command;
208 UINT32 Length;
209 } AMTHI_HEADER;
210
211 #define AMTHI_COMMAND_IS_RESPONSE BIT23
212
213 typedef struct {
214 AMTHI_VERSION Version;
215 UINT16 Reserved;
216 UINT32 Command;
217 UINT32 Length;
218 UINT32 Status;
219 } AMTHI_RESP_HEADER;
220
221 ///
222 /// Get Interface Version
223 ///
224 typedef struct {
225 AMTHI_HEADER Header;
226 UINT32 Status;
227 } CFG_GET_INTERFACE_VERSION_RESPONSE;
228
229 ///
230 /// Get / Set IPV4 Settings
231 ///
232 #define MAXSEG 4
233
234 typedef enum {
235 DhcpModeNone = 0,
236 DhcpModeDisabled,
237 DhcpModeEnabled
238 } DHCP_MODE;
239
240 typedef union {
241 UINT32 Address;
242 UINT8 SegAddr[MAXSEG];
243 } IP_ADDR;
244
245 #define MAX_ASCII_STRING 192
246 typedef struct {
247 UINT16 Length;
248 UINT8 Buffer[MAX_ASCII_STRING];
249 } IMB_ANSI_STRING;
250
251 #define MAX_STRING_LENGTH_FQDN 256
252 typedef struct {
253 UINT16 Length;
254 UINT8 Buffer[MAX_STRING_LENGTH_FQDN];
255 } FQDN_ANSI_STRING;
256
257 #define MAX_STRING_LENGTH_FQDN_SUFFIX 224
258 typedef struct {
259 UINT16 Length;
260 UINT8 Buffer[MAX_STRING_LENGTH_FQDN_SUFFIX];
261 } FQDN_SUFFIX_ANSI_STRING;
262
263 typedef struct {
264 UINT32 DhcpMode;
265 UINT32 LocalAddr;
266 UINT32 SubnetMask;
267 UINT32 GatewayAddr;
268 UINT32 PriDnsAddr;
269 UINT32 SecDnsAddr;
270 IMB_ANSI_STRING DomainName;
271 } IMB_TCPIP_PARAMS;
272
273 typedef struct {
274 AMTHI_HEADER Header;
275 } CFG_GET_TCPIP_PARAMETERS_REQUEST;
276
277 typedef struct {
278 AMTHI_HEADER Header;
279 UINT32 Status;
280 IMB_TCPIP_PARAMS TcpipParams;
281 } CFG_GET_TCPIP_PARAMETERS_RESPONSE;
282
283 typedef union {
284 CFG_GET_TCPIP_PARAMETERS_REQUEST Request;
285 CFG_GET_TCPIP_PARAMETERS_RESPONSE Response;
286 } CFG_GET_TCPIP_PARAMETERS_BUFFER;
287
288 typedef struct {
289 AMTHI_HEADER Header;
290 IMB_TCPIP_PARAMS TcpipParams;
291 } CFG_SET_TCPIP_PARAMETERS;
292
293 typedef struct {
294 AMTHI_HEADER Header;
295 UINT32 Status;
296 } CFG_SET_TCPIP_PARAMETERS_RESPONSE;
297
298 ///
299 /// Unprovision
300 ///
301 typedef struct {
302 AMTHI_HEADER Header;
303 UINT32 Mode;
304 } CFG_UNPROVISION_REQUEST;
305
306 typedef struct {
307 AMTHI_HEADER Header;
308 UINT32 Status;
309 } CFG_UNPROVISION_RESPONSE;
310
311 ///
312 /// Get Provision Status
313 ///
314 typedef enum {
315 ProvisioningStatePre = 0,
316 ProvisioningStateIn = 1,
317 ProvisioningStatePost = 2
318 } PT_PROVISIONING_STATE;
319
320 typedef struct {
321 AMTHI_HEADER Header;
322 UINT32 Status;
323 UINT32 ProvisioningState;
324 } CFG_GET_PROVISIONING_STATE_RESPONSE;
325
326 ///
327 /// Set Sol/Storage Redirection
328 ///
329 typedef struct {
330 AMTHI_HEADER Header;
331 UINT32 SolEnable;
332 UINT32 StorageRedirEnable;
333 } CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST;
334
335 typedef struct {
336 AMTHI_HEADER Header;
337 UINT32 Status;
338 } CFG_SET_SOL_STORAGE_REDIR_STATE_RESPONSE;
339
340 ///
341 /// Get Eop State
342 ///
343 typedef enum {
344 EopStatusBoot = 0,
345 EopStatusMebx = 1,
346 EopStatusPost = 2
347 } CFG_EOP_STATE;
348
349 typedef struct {
350 AMTHI_HEADER Header;
351 } CFG_GET_EOP_STATE_REQUEST;
352
353 typedef struct {
354 AMTHI_HEADER Header;
355 UINT32 Status;
356 UINT8 EopState;
357 } CFG_GET_EOP_STATE_RESPONSE;
358
359 typedef union {
360 CFG_GET_EOP_STATE_REQUEST Request;
361 CFG_GET_EOP_STATE_RESPONSE Response;
362 } CFG_GET_EOP_STATE_BUFFER;
363
364 ///
365 /// Partial Unprovision
366 ///
367 typedef enum {
368 ProvisioningModeNone = 0,
369 ProvisioningModeEnterprise,
370 ProvisioningModeReserved,
371 ProvisioningModeRemoteConnectivityService
372 } AMTHI_PROVISION_MODE;
373
374 typedef struct {
375 AMTHI_HEADER Header;
376 } CFG_PARTIAL_UNPROVISION_REQUEST;
377
378 typedef struct {
379 AMTHI_HEADER Header;
380 UINT32 Status;
381 } CFG_PARTIAL_UNPROVISION_RESPONSE;
382
383 ///
384 /// Certificate Hash Operations:
385 /// Enumerate Hash Entries/Get Cert Hash Entry/Set Cert Hash State/
386 /// Add Customized Cert Hash/Delete Customized Cert Hash
387 ///
388 #define MAX_HASH_ENTRIES 33
389
390 #define CERT_NAME_MAX_ASCII_STRING 32 + 1 ///< Certificate name + null termination
391
392 typedef struct {
393 UINT16 Length;
394 UINT8 Buffer[CERT_NAME_MAX_ASCII_STRING];
395 } CERT_NAME;
396
397 typedef struct {
398 UINT32 CertDefault;
399 UINT32 CertActive;
400 UINT8 CertHash[64];
401 UINT8 HashAlgorithm;
402 CERT_NAME CertName;
403 } CERT_HASH_ENTRY;
404
405 typedef struct {
406 AMTHI_HEADER Header;
407 } CFG_ENUMERATE_HASH_HANDLES_REQUEST;
408
409 typedef struct {
410 AMTHI_HEADER Header;
411 UINT32 Status;
412 UINT32 EntriesCount;
413 UINT32 Handles[MAX_HASH_ENTRIES];
414 } CFG_ENUMERATE_HASH_HANDLES_RESPONSE;
415
416 typedef struct {
417 AMTHI_HEADER Header;
418 UINT32 Handle;
419 } CFG_GET_CERTHASH_ENTRY_REQUEST;
420
421 typedef struct {
422 AMTHI_HEADER Header;
423 UINT32 Status;
424 CERT_HASH_ENTRY CertHashEntry;
425 } CFG_GET_CERTHASH_ENTRY_RESPONSE;
426
427 typedef union {
428 CFG_GET_CERTHASH_ENTRY_REQUEST Request;
429 CFG_GET_CERTHASH_ENTRY_RESPONSE Response;
430 } CFG_GET_CERTHASH_ENTRY_BUFFER;
431
432 typedef struct {
433 AMTHI_HEADER Header;
434 UINT32 Handle;
435 UINT32 IsActive;
436 } CFG_SET_CERTHASH_STATE_REQUEST;
437
438 typedef struct {
439 AMTHI_HEADER Header;
440 UINT32 Status;
441 } CFG_SET_CERTHASH_STATE_RESPONSE;
442
443 typedef enum {
444 CertHashAlgorithmMd5 = 0,
445 CertHashAlgorithmSha1 = 1,
446 CertHashAlgorithmSha256 = 2,
447 CertHashAlgorithmSha384 = 3,
448 CertHashAlgorithmSha224 = 4,
449 CertHashAlgorithmSha512 = 5,
450 } CERT_HASH_ALGORITHM;
451
452 #define MAX_CUSTOMIZED_HASHES 3
453 typedef struct {
454 AMTHI_HEADER Header;
455 UINT32 IsActive;
456 UINT8 CertificateHash[64];
457 UINT8 HashAlgorithm;
458 IMB_ANSI_STRING Name;
459 } CFG_ADD_CERTHASH_ENTRY_REQUEST;
460
461 typedef struct {
462 AMTHI_HEADER Header;
463 UINT32 Status;
464 UINT32 Handle;
465 } CFG_ADD_CERTHASH_ENTRY_RESPONSE;
466
467 typedef union {
468 CFG_ADD_CERTHASH_ENTRY_REQUEST Request;
469 CFG_ADD_CERTHASH_ENTRY_RESPONSE Response;
470 } CFG_ADD_CERTHASH_ENTRY_BUFFER;
471
472 typedef struct {
473 AMTHI_HEADER Header;
474 UINT32 Handle;
475 } CFG_DELETE_CERTHASH_ENTRY_REQUEST;
476
477 typedef struct {
478 AMTHI_HEADER Header;
479 UINT32 Status;
480 } CFG_DELETE_CERTHASH_ENTRY_RESPONSE;
481
482 ///
483 /// Get/Set PKI FQDN Suffix
484 ///
485 #define MAX_ADDRESS_LENGTH 256
486
487 typedef struct {
488 AMTHI_HEADER Header;
489 FQDN_SUFFIX_ANSI_STRING Suffix;
490 } CFG_SET_PKI_FQDN_SUFFIX_REQUEST;
491
492 typedef struct {
493 AMTHI_HEADER Header;
494 UINT32 Status;
495 } CFG_SET_PKI_FQDN_SUFFIX_RESPONSE;
496
497 typedef struct {
498 AMTHI_HEADER Header;
499 UINT32 Status;
500 FQDN_SUFFIX_ANSI_STRING Suffix;
501 } CFG_GET_PKI_FQDN_SUFFIX_RESPONSE;
502
503 typedef struct {
504 AMTHI_HEADER Header;
505 } CFG_GET_PKI_FQDN_SUFFIX_REQUEST;
506
507 ///
508 /// Get/Set ZTC Enabled Status
509 ///
510 typedef struct {
511 AMTHI_HEADER Header;
512 } CFG_GET_ZTC_ENABLED_STATUS_REQUEST;
513
514 typedef struct {
515 AMTHI_HEADER Header;
516 UINT32 Status;
517 UINT32 Enable;
518 } CFG_GET_ZTC_ENABLED_STATUS_RESPONSE;
519
520 typedef union {
521 CFG_GET_ZTC_ENABLED_STATUS_REQUEST Request;
522 CFG_GET_ZTC_ENABLED_STATUS_RESPONSE Response;
523 } CFG_GET_ZTC_ENABLED_STATUS_BUFFER;
524
525 typedef struct {
526 AMTHI_HEADER Header;
527 UINT32 Mode;
528 } CFG_SET_ZTC_MODE_REQUEST;
529
530 typedef struct {
531 AMTHI_HEADER Header;
532 UINT32 Status;
533 } CFG_SET_ZTC_MODE_RESPONSE;
534
535 ///
536 /// Get/Set Idle Timeout Request
537 ///
538 typedef struct {
539 AMTHI_HEADER Header;
540 } CFG_GET_IDLE_TIMEOUT_REQUEST;
541
542 typedef struct {
543 AMTHI_HEADER Header;
544 UINT32 Status;
545 UINT32 IdleTimeout;
546 } CFG_GET_IDLE_TIMEOUT_RESPONSE;
547
548 typedef struct {
549 AMTHI_HEADER Header;
550 UINT32 IdleTimeout;
551 } CFG_SET_IDLE_TIMEOUT_REQUEST;
552
553 typedef struct {
554 AMTHI_HEADER Header;
555 UINT32 Status;
556 } CFG_SET_IDLE_TIMEOUT_RESPONSE;
557
558 ///
559 /// Open/Close/Query User Initiatied Connection for CIRA
560 ///
561 typedef struct {
562 AMTHI_HEADER Header;
563 } CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST;
564
565 typedef struct {
566 AMTHI_HEADER Header;
567 UINT32 Status;
568 } CFG_OPEN_USER_INITIATED_CONNECTION_RESPONSE;
569
570 typedef struct {
571 AMTHI_HEADER Header;
572 } CFG_CLOSE_USER_INITIATED_CONNECTION_REQUEST;
573
574 typedef struct {
575 AMTHI_HEADER Header;
576 UINT32 Status;
577 } CFG_CLOSE_USER_INITIATED_CONNECTION_RESPONSE;
578
579 typedef enum {
580 AmtNetworkConnectionDirect = 0,
581 AmtNetworkConnectionVpn,
582 AmtNetworkConnectionOutsideEnterprise,
583 AmtNetworkConnectionOutsideUnknown
584 } AMT_NETWORK_CONNECTION_STATUS;
585
586 typedef enum {
587 RemoteAccessConnectionStatusNotConnected = 0,
588 RemoteAccessConnectionStatusConnecting,
589 RemoteAccessConnectionStatusConnected
590 } REMOTE_ACCESS_CONNECTION_STATUS;
591
592 typedef struct {
593 UINT32 AmtNetworkConnectionStatus;
594 UINT32 RemoteAccessConnectionStatus;
595 UINT32 RemoteAccessConnectionTrigger;
596 FQDN_ANSI_STRING MpsHostname;
597 } REMOTE_ACCESS_CONNECTION_STRUCT;
598
599 typedef struct {
600 AMTHI_HEADER Header;
601 } CFG_GET_REMOTE_ACCESS_CONNECTION_STATUS_REQUEST;
602
603 typedef struct {
604 AMTHI_HEADER Header;
605 UINT32 Status;
606 UINT32 AmtNetworkConnectionStatus;
607 UINT32 RemoteAccessConnectionStatus;
608 UINT32 RemoteAccessConnectionTrigger;
609 FQDN_ANSI_STRING MpsHostname;
610 } CFG_GET_REMOTE_ACCESS_CONNECTION_STATUS_RESPONSE;
611
612 ///
613 /// Get LAN Interface Settings
614 ///
615 typedef enum {
616 LanInterfaceWired = 0,
617 LanInterfaceWireless = 1
618 } LAN_INTERFACE;
619
620 typedef struct {
621 AMTHI_HEADER Header;
622 UINT32 InterfaceIndex;
623 } CFG_GET_LAN_INTERFACE_SETTINGS_REQUEST;
624
625 typedef struct {
626 UINT32 Enabled;
627 UINT32 Ipv4Address;
628 UINT32 DhcpEnabled;
629 UINT8 DhcpIpMode;
630 UINT8 LinkStatus;
631 UINT8 MacAddress[6];
632 } LAN_INTERFACE_SETTINGS;
633
634 typedef struct {
635 AMTHI_HEADER Header;
636 UINT32 Status;
637 LAN_INTERFACE_SETTINGS InterfaceSettings;
638 } CFG_GET_LAN_INTERFACE_SETTINGS_RESPONSE;
639
640 typedef union {
641 CFG_GET_LAN_INTERFACE_SETTINGS_REQUEST Request;
642 CFG_GET_LAN_INTERFACE_SETTINGS_RESPONSE Response;
643 } CFG_GET_LAN_INTERFACE_SETTINGS_BUFFER;
644
645 ///
646 /// Get/Set MEBx Password Change Policy
647 ///
648 typedef enum {
649 PwdChangePolicyOnlyDefault = 0,
650 PwdChangePolicyBlockInPost = 1,
651 PwdChangePolicyAlwaysAllowed = 2
652 } CFG_MEBX_PWD_CHANGE_POLICY;
653
654 typedef struct {
655 AMTHI_HEADER Header;
656 } CFG_GET_MEBX_PWD_CHANGE_POLICY_REQUEST;
657
658 typedef struct {
659 AMTHI_HEADER Header;
660 UINT32 Status;
661 UINT32 Policy;
662 } CFG_GET_MEBX_PWD_CHANGE_POLICY_RESPONSE;
663
664 typedef struct {
665 AMTHI_HEADER Header;
666 UINT32 Policy;
667 } CFG_SET_MEBX_PWD_CHANGE_POLICY_REQUEST;
668
669 typedef struct {
670 AMTHI_HEADER Header;
671 UINT32 Status;
672 } CFG_SET_MEBX_PWD_CHANGE_POLICY_RESPONSE;
673
674 ///
675 /// Get/Set Config Server Data
676 ///
677 #define CFG_IPV6_ADDR_LEN_MAX 46
678
679 typedef struct {
680 UINT8 Address[CFG_IPV6_ADDR_LEN_MAX];
681 } CFG_IP_ADDR;
682
683 typedef struct {
684 UINT16 ServerPort;
685 CFG_IP_ADDR ServerAddr;
686 FQDN_ANSI_STRING Fqdn;
687 } CONFIG_SERVER_DATA;
688
689 typedef struct {
690 AMTHI_HEADER Header;
691 UINT32 Status;
692 CONFIG_SERVER_DATA ConfigServerData;
693 } CFG_GET_CONFIG_SERVER_DATA_RESPONSE;
694
695 typedef struct {
696 AMTHI_HEADER Header;
697 CONFIG_SERVER_DATA ConfigServerData;
698 } CFG_SET_CONFIG_SERVER_DATA_REQUEST;
699
700 typedef struct {
701 AMTHI_HEADER Header;
702 UINT32 Status;
703 } CFG_SET_CONFIG_SERVER_DATA_RESPONSE;
704
705 typedef union {
706 CFG_SET_CONFIG_SERVER_DATA_REQUEST Request;
707 CFG_SET_CONFIG_SERVER_DATA_RESPONSE Response;
708 } CFG_SET_CONFIG_SERVER_DATA_BUFFER;
709
710 ///
711 /// Get Me Setup Audit Record
712 ///
713 typedef enum {
714 ProvisioningTlsModePki = 0
715 } PROVISIONING_TLS_MODE;
716
717 typedef struct {
718 UINT16 Year;
719 UINT16 Month;
720 UINT16 DayOfWeek;
721 UINT16 Day;
722 UINT16 Hour;
723 UINT16 Minute;
724 UINT16 Second;
725 } TIME_DATE;
726
727 typedef struct {
728 UINT8 ProvisioningTlsMode;
729 UINT32 SecureDns;
730 UINT32 HostInitiated;
731 UINT32 SelectedHashType;
732 UINT8 SelectedHashData[64];
733 UINT8 CaCertificateSerials[48];
734 UINT32 AdditionalCaSerialNums;
735 UINT32 IsOemDefault;
736 UINT32 IsTimeValid;
737 CFG_IP_ADDR ProvServerIp;
738 TIME_DATE TlsStartTime;
739 IMB_ANSI_STRING ProvServerFqdn;
740 } ME_ADMIN_AUDIT_RECORD;
741
742 typedef struct {
743 AMTHI_HEADER Header;
744 UINT32 Status;
745 ME_ADMIN_AUDIT_RECORD AuditRecord;
746 } CFG_GET_AUDIT_RECORD_RESPONSE;
747
748 typedef struct {
749 AMTHI_HEADER Header;
750 } CFG_GET_AUDIT_RECORD_REQUEST;
751
752 ///
753 /// Get/Set IPV6 LAN Interface Settings
754 ///
755 #define MAX_INTERFACE_ID 17
756
757 typedef struct {
758 CHAR8 InterfaceId[MAX_INTERFACE_ID];
759 } CFG_IPV6_INTERFACE_ID;
760
761 typedef enum {
762 Ipv6AddrTypeLinkLocal = 0,
763 Ipv6AddrTypeRouterConf = 1,
764 Ipv6AddrTypeDhcp = 2,
765 Ipv6AddrTypeManual = 3,
766 Ipv6AddrTypeUnknown = 4
767 } CFG_IPV6_ADDR_TYPE;
768
769 typedef enum {
770 Ipv6AddrStateTentative = 0,
771 Ipv6AddrStatePreferred = 1,
772 Ipv6AddrStateDeprecated = 2,
773 Ipv6AddrStateValid = 3,
774 Ipv6AddrStateInvalid = 4,
775 Ipv6AddrStateCollision = 5,
776 Ipv6AddrStateUnknown = 6
777 } CFG_IPV6_ADDR_STATE;
778
779 typedef struct {
780 CFG_IP_ADDR Address;
781 CFG_IPV6_ADDR_TYPE Type;
782 CFG_IPV6_ADDR_STATE State;
783 } CFG_IPV6_ADDR_INFO;
784
785 typedef struct {
786 UINT32 Ipv6Enabled;
787 UINT32 InterfaceIdType;
788 CFG_IPV6_INTERFACE_ID InterfaceId;
789 CFG_IP_ADDR Ipv6Address;
790 CFG_IP_ADDR Ipv6DefaultRouter;
791 CFG_IP_ADDR DnsPrimaryIpv6Address;
792 CFG_IP_ADDR DnsSecondaryIpv6Address;
793 } CFG_IPV6_LAN_INTERFACE_SETTINGS;
794
795 #define MAX_IPV6_ADDRESS_NUM 10
796
797 typedef struct {
798 CFG_IP_ADDR Ipv6DefaultRouter;
799 CFG_IP_ADDR PrimaryDns;
800 CFG_IP_ADDR SecondaryDns;
801 UINT32 NumOfAddr;
802 CFG_IPV6_ADDR_INFO Ipv6Addresses[MAX_IPV6_ADDRESS_NUM];
803 } IPV6_LAN_INTERACE_STRUC;
804
805 typedef struct {
806 AMTHI_HEADER Header;
807 UINT32 InterfaceIndex;
808 } CFG_GET_IPV6_LAN_INTERFACE_STATUS_REQUEST;
809
810 typedef struct {
811 AMTHI_HEADER Header;
812 UINT32 Status;
813 IPV6_LAN_INTERACE_STRUC Ipv6LanIntfStrc;
814 } CFG_GET_IPV6_LAN_INTERFACE_STATUS_RESPONSE;
815
816 typedef union {
817 CFG_GET_IPV6_LAN_INTERFACE_STATUS_REQUEST Request;
818 CFG_GET_IPV6_LAN_INTERFACE_STATUS_RESPONSE Response;
819 } CFG_GET_IPV6_LAN_INTERFACE_STATUS_BUFFER;
820
821 typedef struct {
822 AMTHI_HEADER Header;
823 UINT32 InterfaceIndex;
824 CFG_IPV6_LAN_INTERFACE_SETTINGS Ipv6Settings;
825 } CFG_SET_IPV6_LAN_INTERFACE_SETTINGS_REQUEST;
826
827 typedef struct {
828 AMTHI_HEADER Header;
829 UINT32 Status;
830 } CFG_SET_IPV6_LAN_INTERFACE_SETTINGS_RESPONSE;
831
832 typedef union {
833 CFG_SET_IPV6_LAN_INTERFACE_SETTINGS_REQUEST Request;
834 CFG_SET_IPV6_LAN_INTERFACE_SETTINGS_RESPONSE Response;
835 } CFG_SET_IPV6_LAN_INTERFACE_SETTINGS_BUFFER;
836
837 ///
838 /// Get/Set Fqdn
839 ///
840 typedef struct {
841 AMTHI_HEADER Header;
842 } CFG_GET_FQDN_REQUEST;
843
844 typedef struct {
845 UINT32 SharedFqdn;
846 UINT32 DdnsUpdateEnabled; ///< Deprecated starting with ME 17.X
847 UINT32 DdnsPeriodicUpdateInterval; ///< Deprecated starting with ME 17.X
848 UINT32 DdnsTtl; ///< Deprecated starting with ME 17.X
849 UINT32 HostNameLength;
850 FQDN_ANSI_STRING Fqdn;
851 } FQDN_DATA;
852
853 typedef struct {
854 AMTHI_HEADER Header;
855 UINT32 Status;
856 FQDN_DATA FqdnData;
857 } CFG_GET_FQDN_RESPONSE;
858
859 typedef union {
860 CFG_GET_FQDN_REQUEST Request;
861 CFG_GET_FQDN_RESPONSE Response;
862 } CFG_GET_FQDN_BUFFER;
863
864 typedef struct {
865 AMTHI_HEADER Header;
866 FQDN_DATA FqdnData;
867 } CFG_SET_FQDN_REQUEST;
868
869 typedef struct {
870 AMTHI_HEADER Header;
871 UINT32 Status;
872 } CFG_SET_FQDN_RESPONSE;
873
874 ///
875 /// Get Redirection Features State
876 ///
877 typedef struct {
878 AMTHI_HEADER Header;
879 } CFG_GET_REDIRECTION_STATE_REQUEST;
880
881 typedef struct {
882 UINT32 SolState : 1;
883 UINT32 StorageRedirState : 1;
884 UINT32 KvmState : 1;
885 UINT32 Reserved0 : 29;
886 } REDIRECTION_FEATURES_STATE;
887
888 typedef struct {
889 AMTHI_HEADER Header;
890 UINT32 Status;
891 REDIRECTION_FEATURES_STATE RedirectionFeatureStates;
892 } CFG_GET_REDIRECTION_STATE_RESPONSE;
893
894 ///
895 /// Complete Configuration
896 ///
897 typedef struct {
898 AMTHI_HEADER Header;
899 } CFG_COMPLETE_CONFIGURATION_REQUEST;
900
901 typedef struct {
902 AMTHI_HEADER Header;
903 UINT32 Status;
904 } CFG_COMPLETE_CONFIGURATION_RESPONSE;
905
906 ///
907 /// Stop/Start Configuration
908 ///
909 typedef struct {
910 AMTHI_HEADER Header;
911 } CFG_STOP_CONFIGURATION_REQUEST;
912
913 typedef struct {
914 AMTHI_HEADER Header;
915 UINT32 Status;
916 } CFG_STOP_CONFIGURATION_RESPONSE;
917
918 typedef struct {
919 AMTHI_HEADER Header;
920 UINT32 IPv6Enable;
921 } CFG_START_CONFIGURATION_EX_REQUEST;
922
923 typedef struct {
924 AMTHI_HEADER Header;
925 UINT32 Status;
926 } CFG_START_CONFIGURATION_EX_RESPONSE;
927
928 typedef union {
929 CFG_START_CONFIGURATION_EX_REQUEST Request;
930 CFG_START_CONFIGURATION_EX_RESPONSE Response;
931 } CFG_START_CONFIGURATION_EX_BUFFER;
932
933 ///
934 /// Get Unprovisioning State
935 ///
936 typedef enum {
937 UnprovisioningStateNone = 0,
938 UnprovisioningStateIn = 1
939 } CFG_UNPROVISIONING_STATE;
940
941 typedef struct {
942 AMTHI_HEADER Header;
943 UINT32 Status;
944 CFG_UNPROVISIONING_STATE UnprovisioningState;
945 } CFG_GET_UNPROVISIONING_STATE_RESPONSE;
946
947 ///
948 /// Set MEBx state
949 ///
950 typedef enum {
951 AmtMebxStateEnter = 0,
952 AmtMebxStateExit = 1
953 } AMT_MEBX_STATE;
954
955 typedef struct {
956 AMTHI_HEADER Header;
957 AMT_MEBX_STATE MebxState;
958 } CFG_SET_MEBX_STATE_REQUEST;
959
960 typedef struct {
961 AMTHI_HEADER Header;
962 UINT32 Status;
963 } CFG_SET_MEBX_STATE_RESPONSE;
964
965 typedef union {
966 CFG_SET_MEBX_STATE_REQUEST Request;
967 CFG_SET_MEBX_STATE_RESPONSE Response;
968 } CFG_SET_MEBX_STATE_BUFFER;
969
970 ///
971 /// Get Control Mode
972 ///
973 typedef enum {
974 AmtControlModeNone = 0,
975 AmtControlModeUser,
976 AmtControlModeAdmin
977 } AMT_CONTROL_MODE;
978
979 typedef struct {
980 AMTHI_HEADER Header;
981 UINT32 Status;
982 UINT32 ControlMode; // returned upon success only
983 } CFG_GET_CONTROL_MODE_RESPONSE;
984
985 ///
986 /// Get/Set OptIn State
987 ///
988
989 // optin policy bitmap
990 typedef enum {
991 OptinPolicyBitmapNone = 0x1,
992 OptinPolicyBitmapKvmOnly = 0x2,
993 OptinPolicyBitmapAll = 0x4
994 } OPTIN_POLICY_BITMAP;
995
996 typedef struct {
997 AMTHI_HEADER Header;
998 UINT32 OptInState;
999 UINT32 RemoteOptInState;
1000 } CFG_SET_OPTIN_STATE_REQUEST;
1001
1002 typedef struct {
1003 AMTHI_HEADER Header;
1004 UINT32 Status;
1005 } CFG_SET_OPTIN_STATE_RESPONSE;
1006
1007 typedef struct {
1008 AMTHI_HEADER Header;
1009 } CFG_GET_OPTIN_STATE_REQUEST;
1010
1011 typedef struct {
1012 AMTHI_HEADER Header;
1013 UINT32 Status;
1014 UINT32 OptInState;
1015 UINT32 RemoteOptInState;
1016 } CFG_GET_OPTIN_STATE_RESPONSE;
1017
1018 ///
1019 /// Get/Set KVM State
1020 ///
1021 typedef struct {
1022 AMTHI_HEADER Header;
1023 UINT32 Enabled;
1024 } CFG_SET_KVM_ENABLED_REQUEST;
1025
1026 typedef struct {
1027 AMTHI_HEADER Header;
1028 UINT32 Status;
1029 } CFG_SET_KVM_ENABLED_RESPONSE;
1030
1031 typedef struct {
1032 AMTHI_HEADER Header;
1033 } CFG_GET_KVM_ENABLED_REQUEST;
1034
1035 typedef struct {
1036 AMTHI_HEADER Header;
1037 UINT32 Status;
1038 UINT32 Enabled;
1039 } CFG_GET_KVM_ENABLED_RESPONSE;
1040
1041 ///
1042 /// Get AMT Privacy Level
1043 ///
1044 typedef struct {
1045 AMTHI_HEADER Header;
1046 } CFG_GET_PRIVACY_LEVEL_REQUEST;
1047
1048 typedef enum {
1049 PrivacyLevelDefault = 1,
1050 PrivacyLevelEnhanced,
1051 PrivacyLevelExtreme
1052 } AMT_PRIVACY_LEVEL;
1053
1054 typedef struct {
1055 AMTHI_HEADER Header;
1056 UINT32 Status;
1057 UINT32 PrivacyLevel;
1058 } CFG_GET_PRIVACY_LEVEL_RESPONSE;
1059
1060 ///
1061 /// Get OptIn Change Availability
1062 ///
1063 typedef struct {
1064 AMTHI_HEADER Header;
1065 UINT32 Status;
1066 UINT32 OptInPolicy;
1067 UINT32 OptInRemoteEnabled;
1068 } CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE;
1069
1070 typedef enum {
1071 NullImageId = 0,
1072 ImageIdExitUi = 1,
1073 ImageIdUserConsentCodeDialog = 256,
1074 ImageIdUserConsentGrantedDialog = 257
1075 } AMT_IMAGE_ID;
1076
1077 ///
1078 /// Get UI Action
1079 ///
1080 typedef enum {
1081 UserInputNoInput,
1082 UserInputEsc,
1083 UserInputEnter,
1084 UserInputOtherKey
1085 } AMT_MEBX_USER_INPUT;
1086
1087 typedef struct {
1088 AMTHI_HEADER Header;
1089 AMT_IMAGE_ID CurrentImageId;
1090 AMT_MEBX_USER_INPUT UserInput;
1091 } CFG_UI_ACTION_REQUEST;
1092
1093 typedef struct {
1094 AMTHI_HEADER Header;
1095 UINT32 Status;
1096 UINT32 NextScreen;
1097 } CFG_UI_ACTION_RESPONSE;
1098
1099 typedef union {
1100 CFG_UI_ACTION_REQUEST Request;
1101 CFG_UI_ACTION_RESPONSE Response;
1102 } CFG_UI_ACTION_BUFFER;
1103
1104 ///
1105 /// Get GFX UI Info/Fragment
1106 ///
1107 typedef struct {
1108 UINT16 Width;
1109 UINT16 Height;
1110 } AMT_SCREEN_RESOLUTION;
1111
1112 typedef struct {
1113 AMTHI_HEADER Header;
1114 AMT_SCREEN_RESOLUTION ScreenResolution;
1115 AMT_IMAGE_ID ImageId;
1116 } CFG_GET_GFX_UI_INFO_REQUEST;
1117
1118 typedef struct {
1119 AMTHI_HEADER Header;
1120 UINT32 Status;
1121 UINT32 ImageDataLength;
1122 UINT16 UpperLeftXPos;
1123 UINT16 UpperLeftYPos;
1124 } CFG_GET_GFX_UI_INFO_RESPONSE;
1125
1126 typedef union {
1127 CFG_GET_GFX_UI_INFO_REQUEST Request;
1128 CFG_GET_GFX_UI_INFO_RESPONSE Response;
1129 } CFG_GET_GFX_UI_INFO_BUFFER;
1130
1131 typedef struct {
1132 AMTHI_HEADER Header;
1133 AMT_IMAGE_ID ImageId;
1134 UINT32 ByteOffset;
1135 UINT32 ByteSize;
1136 } CFG_GET_GFX_FRAGMENT_REQUEST;
1137
1138 #define AMT_UI_MAX_DATA_SIZE 0x400
1139
1140 typedef struct {
1141 AMTHI_HEADER Header;
1142 UINT32 Status;
1143 UINT32 ByteSize; ///<Returned upon success only
1144 UINT8 Data[AMT_UI_MAX_DATA_SIZE]; ///<Returned upon success only
1145 } CFG_GET_GFX_FRAGMENT_RESPONSE;
1146
1147 typedef union {
1148 CFG_GET_GFX_FRAGMENT_REQUEST Request;
1149 CFG_GET_GFX_FRAGMENT_RESPONSE Response;
1150 } CFG_GET_GFX_FRAGMENT_BUFFER;
1151
1152 ///
1153 /// Enumerate Power Packages
1154 /// Get/Set Active Power Package
1155 // Get Power Package Info
1156 ///
1157 #define MAX_PWR_PKG_COUNT 3
1158 #define MAX_PWR_PKG_DESC_SIZE 64
1159
1160 typedef struct {
1161 AMTHI_HEADER Header;
1162 } CFG_ENUMERATE_POWER_PACKAGES_REQUEST;
1163
1164 typedef struct {
1165 AMTHI_HEADER Header;
1166 UINT32 Status;
1167 UINT32 NumOfGuids; ///< Returned upon success only
1168 EFI_GUID Guids[MAX_PWR_PKG_COUNT]; ///< Returned upon success only
1169 } CFG_ENUMERATE_POWER_PACKAGES_RESPONSE;
1170
1171 typedef struct {
1172 AMTHI_HEADER Header;
1173 } CFG_GET_CURRENT_POWER_PACKAGE_REQUEST;
1174
1175 typedef struct {
1176 AMTHI_HEADER Header;
1177 UINT32 Status;
1178 EFI_GUID Guid; ///< Returned upon success only
1179 } CFG_GET_CURRENT_POWER_PACKAGE_RESPONSE;
1180
1181 typedef struct {
1182 AMTHI_HEADER Header;
1183 EFI_GUID Guid;
1184 } CFG_GET_POWER_PACKAGE_INFO_REQUEST;
1185
1186 typedef struct {
1187 AMTHI_HEADER Header;
1188 UINT32 Status;
1189 UINT16 Length;
1190 CHAR8 Description[MAX_PWR_PKG_DESC_SIZE];
1191 } CFG_GET_POWER_PACKAGE_INFO_RESPONSE;
1192
1193 typedef union {
1194 CFG_GET_POWER_PACKAGE_INFO_REQUEST Request;
1195 CFG_GET_POWER_PACKAGE_INFO_RESPONSE Response;
1196 } CFG_GET_POWER_PACKAGE_INFO_BUFFER;
1197
1198 typedef struct {
1199 AMTHI_HEADER Header;
1200 EFI_GUID Guid;
1201 } CFG_SET_POWER_PACKAGE_REQUEST;
1202
1203 typedef struct {
1204 AMTHI_HEADER Header;
1205 UINT32 Status;
1206 } CFG_SET_POWER_PACKAGE_RESPONSE;
1207
1208 #pragma pack()
1209
1210 #endif // _AMTHI_MSGS_H
CFG_GET_IDLE_TIMEOUT_REQUEST
Get/Set Idle Timeout Request.
Definition: AmthiMsgs.h:538
AMT_SCREEN_RESOLUTION
Get GFX UI Info/Fragment.
Definition: AmthiMsgs.h:1107
CFG_UNPROVISION_REQUEST
Unprovision.
Definition: AmthiMsgs.h:301
CFG_GET_REDIRECTION_STATE_REQUEST
Get Redirection Features State.
Definition: AmthiMsgs.h:877
AMT_MEBX_STATE
AMT_MEBX_STATE
Set MEBx state.
Definition: AmthiMsgs.h:950
AMT_STATUS
AMT_STATUS
AMT Status Enum.
Definition: AmthiMsgs.h:46
AMTHI_COMMAND
AMTHI_COMMAND
AMTHI Commands Enum.
Definition: AmthiMsgs.h:131
CFG_GET_ZTC_ENABLED_STATUS_REQUEST
Get/Set ZTC Enabled Status.
Definition: AmthiMsgs.h:510
CFG_GET_PRIVACY_LEVEL_REQUEST
Get AMT Privacy Level.
Definition: AmthiMsgs.h:1044
OPTIN_POLICY_BITMAP
OPTIN_POLICY_BITMAP
Get/Set OptIn State.
Definition: AmthiMsgs.h:990
CFG_SET_SOL_STORAGE_REDIR_STATE_REQUEST
Set Sol/Storage Redirection.
Definition: AmthiMsgs.h:329
AMT_MEBX_USER_INPUT
AMT_MEBX_USER_INPUT
Get UI Action.
Definition: AmthiMsgs.h:1080
MAXSEG
#define MAXSEG
Get / Set IPV4 Settings.
Definition: AmthiMsgs.h:232
MAX_PWR_PKG_COUNT
#define MAX_PWR_PKG_COUNT
Enumerate Power Packages Get/Set Active Power Package.
Definition: AmthiMsgs.h:1157
AMT_CONTROL_MODE
AMT_CONTROL_MODE
Get Control Mode.
Definition: AmthiMsgs.h:973
CFG_STOP_CONFIGURATION_REQUEST
Stop/Start Configuration.
Definition: AmthiMsgs.h:909
CFG_GET_INTERFACE_VERSION_RESPONSE
Get Interface Version.
Definition: AmthiMsgs.h:224
CFG_GET_FQDN_REQUEST
Get/Set Fqdn.
Definition: AmthiMsgs.h:840
AMTHI_PROVISION_MODE
AMTHI_PROVISION_MODE
Partial Unprovision.
Definition: AmthiMsgs.h:367
PT_PROVISIONING_STATE
PT_PROVISIONING_STATE
Get Provision Status.
Definition: AmthiMsgs.h:314
CFG_GET_OPTIN_CHANGE_AVAILABLE_RESPONSE
Get OptIn Change Availability.
Definition: AmthiMsgs.h:1063
LAN_INTERFACE
LAN_INTERFACE
Get LAN Interface Settings.
Definition: AmthiMsgs.h:615
CFG_MEBX_PWD_CHANGE_POLICY
CFG_MEBX_PWD_CHANGE_POLICY
Get/Set MEBx Password Change Policy.
Definition: AmthiMsgs.h:648
CFG_UNPROVISIONING_STATE
CFG_UNPROVISIONING_STATE
Get Unprovisioning State.
Definition: AmthiMsgs.h:936
CFG_OPEN_USER_INITIATED_CONNECTION_REQUEST
Open/Close/Query User Initiatied Connection for CIRA.
Definition: AmthiMsgs.h:561
MAX_HASH_ENTRIES
#define MAX_HASH_ENTRIES
Certificate Hash Operations: Enumerate Hash Entries/Get Cert Hash Entry/Set Cert Hash State/ Add Cust...
Definition: AmthiMsgs.h:388
CFG_EOP_STATE
CFG_EOP_STATE
Get Eop State.
Definition: AmthiMsgs.h:343
CFG_IPV6_ADDR_LEN_MAX
#define CFG_IPV6_ADDR_LEN_MAX
Get/Set Config Server Data.
Definition: AmthiMsgs.h:677
CFG_SET_KVM_ENABLED_REQUEST
Get/Set KVM State.
Definition: AmthiMsgs.h:1021
CFG_COMPLETE_CONFIGURATION_REQUEST
Complete Configuration.
Definition: AmthiMsgs.h:897
CERT_NAME_MAX_ASCII_STRING
#define CERT_NAME_MAX_ASCII_STRING
Certificate name + null termination.
Definition: AmthiMsgs.h:390
PROVISIONING_TLS_MODE
PROVISIONING_TLS_MODE
Get Me Setup Audit Record.
Definition: AmthiMsgs.h:713
MAX_INTERFACE_ID
#define MAX_INTERFACE_ID
Get/Set IPV6 LAN Interface Settings.
Definition: AmthiMsgs.h:755
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtPetQueueHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
AmtPetQueueHob.h File Reference

Definition of AmtPetQueueHob data structures. More...

Go to the source code of this file.

Classes

struct AMT_PET_QUEUE_HOB
Queue Hob. More...

Detailed Description

Definition of AmtPetQueueHob data structures.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtPetQueueHob.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtPetQueueHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
AmtPetQueueHob.h
Go to the documentation of this file.
1 /** @file
2 Definition of AmtPetQueueHob data structures
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_PET_QUEUE_HOB_H_
36 #define _AMT_PET_QUEUE_HOB_H_
37
38
39 ///
40 /// Queue Hob.
41 /// This hob is used by PEI Status Code generic driver before Intel AMT PEI status code driver
42 /// starts.
43 /// 1) If AMT driver is not ready yet, StatusCode driver can save information
44 /// to QueueHob.
45 /// 2) If after AMT driver start, but ME is not ready, the AMT
46 /// driver can also save information to QueueHob.
47 /// Later, when ME is ready, AMT driver will send all the
48 /// message in the QueueHob.
49 ///
50 typedef struct {
51 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< The GUID type hob header
52 EFI_STATUS_CODE_VALUE Value; ///< Status code value
53 EFI_STATUS_CODE_TYPE Type; ///< Status code type
54 } AMT_PET_QUEUE_HOB;
55
56 extern EFI_GUID gAmtPetQueueHobGuid;
57
58 #endif
AMT_PET_QUEUE_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
The GUID type hob header.
Definition: AmtPetQueueHob.h:51
AMT_PET_QUEUE_HOB
Queue Hob.
Definition: AmtPetQueueHob.h:50
AMT_PET_QUEUE_HOB::Value
EFI_STATUS_CODE_VALUE Value
Status code value.
Definition: AmtPetQueueHob.h:52
AMT_PET_QUEUE_HOB::Type
EFI_STATUS_CODE_TYPE Type
Status code type.
Definition: AmtPetQueueHob.h:53
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
AmtPolicy.h File Reference

Interface definition details between AMT and platform drivers during DXE phase. More...

#include <ConfigBlock.h>
Include dependency graph for AmtPolicy.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _AMT_POLICY_PROTOCOL
AMT DXE Policy This protocol is initialized by Policy driver. More...

Macros

#define AMT_POLICY_PROTOCOL_REVISION 1
AMT policy provided by platform for DXE phase This protocol provides the information about Intel AMT platform configuration settings. More...

Typedefs

typedef struct _AMT_POLICY_PROTOCOL AMT_POLICY_PROTOCOL
AMT DXE Policy This protocol is initialized by Policy driver. More...

Detailed Description

Interface definition details between AMT and platform drivers during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtPolicy.h.

Macro Definition Documentation

◆ AMT_POLICY_PROTOCOL_REVISION

#define AMT_POLICY_PROTOCOL_REVISION 1

AMT policy provided by platform for DXE phase This protocol provides the information about Intel AMT platform configuration settings.

Protocol revision number Any backwards compatible changes to this protocol will result in an update in the revision number Major changes will require publication of a new protocol Initial Revision

Definition at line 50 of file AmtPolicy.h.

Typedef Documentation

◆ AMT_POLICY_PROTOCOL

typedef struct _AMT_POLICY_PROTOCOL AMT_POLICY_PROTOCOL

AMT DXE Policy This protocol is initialized by Policy driver.

Other modules can locate this protocol to retrieve Intel AMT related setup options setting

Revision 1:

  • Initial version.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
AmtPolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details between AMT and platform drivers during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_POLICY_H_
36 #define _AMT_POLICY_H_
37
38 #include <ConfigBlock.h>
39
40 ///
41 /// AMT policy provided by platform for DXE phase
42 /// This protocol provides the information about Intel AMT platform configuration settings.
43 ///
44
45 ///
46 /// Protocol revision number
47 /// Any backwards compatible changes to this protocol will result in an update in the revision number
48 /// Major changes will require publication of a new protocol
49 ///
50 #define AMT_POLICY_PROTOCOL_REVISION 1 ///< Initial Revision
51
52 extern EFI_GUID gDxeAmtPolicyGuid;
53
54 #pragma pack (push,1)
55
56 /**
57 AMT DXE Policy
58 This protocol is initialized by Policy driver. Other modules can locate this protocol
59 to retrieve Intel AMT related setup options setting
60
61 <b>Revision 1</b>:
62 - Initial version.
63 **/
64 typedef struct _AMT_POLICY_PROTOCOL {
65 CONFIG_BLOCK_TABLE_HEADER TableHeader;
66 /*
67 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
68 */
69 } AMT_POLICY_PROTOCOL;
70
71 #pragma pack (pop)
72
73 #endif // _AMT_POLICY_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
_AMT_POLICY_PROTOCOL
AMT DXE Policy This protocol is initialized by Policy driver.
Definition: AmtPolicy.h:64
AMT_POLICY_PROTOCOL
struct _AMT_POLICY_PROTOCOL AMT_POLICY_PROTOCOL
AMT DXE Policy This protocol is initialized by Policy driver.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtReadyToBoot.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
AmtReadyToBoot.h File Reference

AmtReadyToBoot Protocol definitions. More...

Go to the source code of this file.

Classes

struct _AMT_READY_TO_BOOT_PROTOCOL
AMT Ready to Boot Protocol The interface functions are for Performing all Management Engine task. More...

Macros

#define AMT_READY_TO_BOOT_PROTOCOL_REVISION 1
AMT Ready to Boot Protocol This protocol performs all Management Engine task.

Typedefs

typedef VOID(* AMT_READY_TO_BOOT_PROTOCOL_SIGNAL) (VOID)
Signal an event for Amt ready to boot. More...

Detailed Description

AmtReadyToBoot Protocol definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtReadyToBoot.h.

Typedef Documentation

◆ AMT_READY_TO_BOOT_PROTOCOL_SIGNAL

typedef VOID( * AMT_READY_TO_BOOT_PROTOCOL_SIGNAL) (VOID)

Signal an event for Amt ready to boot.

Any function registers to this protocol will be executed in ME ready to boot callback function.

Definition at line 53 of file AmtReadyToBoot.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtReadyToBoot.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
AmtReadyToBoot.h
Go to the documentation of this file.
1 /** @file
2 AmtReadyToBoot Protocol definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_READY_TO_BOOT_PROTOCOL_H_
36 #define _AMT_READY_TO_BOOT_PROTOCOL_H_
37
38 ///
39 /// AMT Ready to Boot Protocol
40 /// This protocol performs all Management Engine task
41 ///
42
43 #define AMT_READY_TO_BOOT_PROTOCOL_REVISION 1
44
45 typedef struct _AMT_READY_TO_BOOT_PROTOCOL AMT_READY_TO_BOOT_PROTOCOL;
46
47 /**
48 Signal an event for Amt ready to boot.
49
50 Any function registers to this protocol will be executed in ME ready to boot callback function.
51 **/
52 typedef
53 VOID
54 (EFIAPI *AMT_READY_TO_BOOT_PROTOCOL_SIGNAL) (
55 VOID
56 );
57
58 /**
59 AMT Ready to Boot Protocol
60 The interface functions are for Performing all Management Engine task
61 **/
62 struct _AMT_READY_TO_BOOT_PROTOCOL {
63 UINT8 Revision; ///< Revision for the protocol structure
64 AMT_READY_TO_BOOT_PROTOCOL_SIGNAL Signal; ///< Performs all Management Engine task
65 };
66
67 extern EFI_GUID gAmtReadyToBootProtocolGuid;
68
69 #endif
_AMT_READY_TO_BOOT_PROTOCOL::Revision
UINT8 Revision
Revision for the protocol structure.
Definition: AmtReadyToBoot.h:63
AMT_READY_TO_BOOT_PROTOCOL_SIGNAL
VOID(* AMT_READY_TO_BOOT_PROTOCOL_SIGNAL)(VOID)
Signal an event for Amt ready to boot.
Definition: AmtReadyToBoot.h:54
_AMT_READY_TO_BOOT_PROTOCOL::Signal
AMT_READY_TO_BOOT_PROTOCOL_SIGNAL Signal
Performs all Management Engine task.
Definition: AmtReadyToBoot.h:64
_AMT_READY_TO_BOOT_PROTOCOL
AMT Ready to Boot Protocol The interface functions are for Performing all Management Engine task.
Definition: AmtReadyToBoot.h:62
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtSaveMebxProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs | Variables
AmtSaveMebxProtocol.h File Reference

AmtSaveMebxProtocol definitions - deprecated protocol. More...

Go to the source code of this file.

Classes

struct _AMT_SAVE_MEBX_PROTOCOL
AMT Save Mebx Protocol The interface function is to save MEBX setting. More...

Macros

#define AMT_SAVE_MEBX_PROTOCOL_REVISION 1
AMT Save Mebx Data Protocol The interface function is to save MEBX setting.

Typedefs

typedef EFI_STATUS(* AMT_SAVE_MEBX_DATA) (IN UINTN DataSize, IN VOID *Data)
This function is used to save MEBX setting to NVRAM. More...

Variables

EFI_GUID gAmtSaveMebxProtocolGuid

Detailed Description

AmtSaveMebxProtocol definitions - deprecated protocol.

Do not use.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AmtSaveMebxProtocol.h.

Typedef Documentation

◆ AMT_SAVE_MEBX_DATA

typedef EFI_STATUS( * AMT_SAVE_MEBX_DATA) (IN UINTN DataSize, IN VOID *Data)

This function is used to save MEBX setting to NVRAM.

Parameters
[in] | DataSize | The size in bytes of the Mebx Data buffer.
[in] | Data | The contents for the Mebx Data.
Return values
EFI_SUCCESS | Mebx config saved.
EFI_OUT_OF_RESOURCES | Not enough storage is available to hold the variable and its data.
EFI_DEVICE_ERROR | The variable could not be retrieved due to a hardware error.

Definition at line 57 of file AmtSaveMebxProtocol.h.

Variable Documentation

◆ gAmtSaveMebxProtocolGuid

EFI_GUID gAmtSaveMebxProtocolGuid
extern
Deprecated:
: please use gMebxConfigProtocolGuid instead
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AmtSaveMebxProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
AmtSaveMebxProtocol.h
Go to the documentation of this file.
1 /** @file
2 AmtSaveMebxProtocol definitions - deprecated protocol. Do not use.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _AMT_SAVE_MEBX_PROTOCOL_H_
36 #define _AMT_SAVE_MEBX_PROTOCOL_H_
37
38 ///
39 /// AMT Save Mebx Data Protocol
40 /// The interface function is to save MEBX setting.
41 ///
42
43 #define AMT_SAVE_MEBX_PROTOCOL_REVISION 1
44 typedef struct _AMT_SAVE_MEBX_PROTOCOL AMT_SAVE_MEBX_PROTOCOL;
45
46 /**
47 This function is used to save MEBX setting to NVRAM.
48
49 @param[in] DataSize The size in bytes of the Mebx Data buffer.
50 @param[in] Data The contents for the Mebx Data.
51
52 @retval EFI_SUCCESS Mebx config saved.
53 @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold the variable and its data.
54 @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
55 **/
56 typedef
57 EFI_STATUS
58 (EFIAPI *AMT_SAVE_MEBX_DATA) (
59 IN UINTN DataSize,
60 IN VOID *Data
61 );
62
63 /**
64 AMT Save Mebx Protocol
65 The interface function is to save MEBX setting.
66 It is platform vendor's responsibility to implement the function instance.
67 **/
68 struct _AMT_SAVE_MEBX_PROTOCOL {
69 AMT_SAVE_MEBX_DATA SaveMebx;
70 };
71
72 extern EFI_GUID gAmtSaveMebxProtocolGuid; ///<@deprecated: please use gMebxConfigProtocolGuid instead
73
74 #endif
_AMT_SAVE_MEBX_PROTOCOL
AMT Save Mebx Protocol The interface function is to save MEBX setting.
Definition: AmtSaveMebxProtocol.h:68
AMT_SAVE_MEBX_DATA
EFI_STATUS(* AMT_SAVE_MEBX_DATA)(IN UINTN DataSize, IN VOID *Data)
This function is used to save MEBX setting to NVRAM.
Definition: AmtSaveMebxProtocol.h:58
gAmtSaveMebxProtocolGuid
EFI_GUID gAmtSaveMebxProtocolGuid
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ArchMsr.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Register
Macros
ArchMsr.h File Reference

ArchMsr.h. More...

#include <Base.h>
Include dependency graph for ArchMsr.h:

Go to the source code of this file.

Macros

#define | MSR_P5_MC_ADDR 0x00000001
Machine Check Status Register.
#define | MSR_MONITOR_FILTER_SIZE 0x00000006
Used by the OS or BIOS to program to the maximum MONITOR line size in the system. More...
#define | MSR_TIME_STAMP_COUNTER 0x00000010
The time-stamp counter is a 64-bit counter that is set to 0 following a RESET of the processor. More...
#define | MSR_PLATFORM_ID 0x00000017
Indicates the platform that the processor is intended for.
#define | MSR_APIC_BASE 0x0000001B
This register holds the APIC base address, permitting the relocation of the APIC memory map.
#define | MSR_OPTIN_FEATURE_CONTROL 0x0000003A
Control Features in Intel 64 Processor. More...
#define | MSR_TSC_THREAD_OFFSET 0x0000003B
Thread specific offset used in RDTSC computation.
#define | MSR_SPEC_CTRL 0x00000048
Virtual MSR to set/clear IBRS commands.
#define | MSR_PREDICT_CMD 0x00000049
Write-only virtual MSR to activate BPU flush command.
#define | MSR_BIOS_DYNAMIC_UPDATE_PTR 0x00000078
This is a read only BIOS MSR to return the dynamic update(aka push patch) pointer stored in the PCH.
#define | MSR_BIOS_UPDT_TRIG 0x00000079
Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the processor. More...
#define | MSR_BIOS_UPGD_TRIG 0x0000007A
Implements Feature Activation command. More...
#define | MSR_FZM_RANGE_INDEX 0x00000082
FZM Range Index register to R/W Domain|Index.
#define | MSR_FZM_DOMAIN_CONFIG 0x00000083
FZM Domain ConfigValue Read Only.
#define | MSR_FZM_RANGE_STARTADDR 0x00000084
FZM Domain Start Address - Ready Only.
#define | MSR_FZM_RANGE_ENDADDR 0x00000085
FZM Domain End Address - Ready Only.
#define | MSR_FZM_RANGE_WRITESTATUS 0x00000086
FZM Domain Write Status - Ready Only.
#define | MSR_BIOS_SIGN_ID 0x0000008B
Returns the microcode update signature following the execution of CPUID.01H.
#define | MSR_BIOS_DEBUG 0x000000A7
Returns indication per thread whether PPPE load was successful or not (partial success)
#define | MSR_EMON_GEN_CTR0 0x000000C1
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR1 0x000000C2
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR2 0x000000C3
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR3 0x000000C4
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR4 0x000000C5
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR5 0x000000C6
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR6 0x000000C7
GENERAL PERFORMANCE COUNTER.
#define | MSR_EMON_GEN_CTR7 0x000000C8
GENERAL PERFORMANCE COUNTER.
#define | MSR_CORE_CAPABILITIES 0x000000CF
architectural MSR to enumerate model-specific features
#define | MSR_MLC_MCNT_COUNTER 0x000000E7
Maximum Qualified Performance Clock Counter.
#define | MSR_MLC_ACNT_COUNTER 0x000000E8
Actual Performance Clock Counter.
#define | MSR_MTRRCAP 0x000000FE
MTRR Capabilities MSR.
#define | MSR_DCU_FLUSH_CMD 0x0000010B
Write-only virtual MSR to activate DCU flush command.
#define | MSR_SYSENTER_CS 0x00000174
SYSENTER_CS_MSR.
#define | MSR_SYSENTER_ESP 0x00000175
SYSENTER ESP Linear Address.
#define | MSR_SYSENTER_EIP 0x00000176
SYSENTER ESI Linear Address.
#define | MSR_MCG_CAP 0x00000179
Machine Check Capabilities register.
#define | MSR_MCG_STATUS 0x0000017A
Global Machine Check Status.
#define | MSR_PERMON_EVNTSEL_CNTR0 0x00000186
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR1 0x00000187
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR2 0x00000188
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR3 0x00000189
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR4 0x0000018A
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR5 0x0000018B
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR6 0x0000018C
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERMON_EVNTSEL_CNTR7 0x0000018D
This is a PerfMon register that is used to control the behavior of an associated performance counter and to selecting events for that counter.
#define | MSR_PERF_STATUS 0x00000198
Current performance status.
#define | MSR_PERF_CTL 0x00000199
Legacy Performance Control MSR. More...
#define | MSR_CLOCK_MODULATION 0x0000019A
This register is used to read and write the duty cycle bits, and to enable the on-demand clock modulation feature of the Intel Thermal Monitor.
#define | MSR_THERM_INTERRUPT 0x0000019B
Enables and disables the generation of an interrupt on temperature transitions detected with the processor's thermal sensors and thermal monitor.
#define | MSR_THERM_STATUS 0x0000019C
Contains status information about the processor's thermal sensor and automatic thermal monitoring facilities.
#define | MSR_MISC_ENABLES 0x000001A0
Allows a variety of processor functions to be enabled and disabled.
#define | MSR_ENERGY_PERFORMANCE_BIAS 0x000001B0
Performance Energy Bias Hint MSR. More...
#define | MSR_PACKAGE_THERM_STATUS 0x000001B1
Contains status information about the package's thermal sensor.
#define | MSR_PACKAGE_THERM_INTERRUPT 0x000001B2
Thermal Limitation Interrupt Control.
#define | MSR_DEBUGCTLMSR 0x000001D9
Debug MSR for model specific debug features.
#define | MSR_CPU_DCA_CAP 0x000001F9
DCA CPU capability register.
#define | MSR_MTRRVARBASE0 0x00000200
Variable MTRR Entry 0 PhysBase register.
#define | MSR_MTRRVARMASK0 0x00000201
Variable MTRR Entry 0 PhysMask register.
#define | MSR_MTRRVARBASE1 0x00000202
Variable MTRR Entry 1 PhysBase register.
#define | MSR_MTRRVARMASK1 0x00000203
Variable MTRR Entry 1 PhysMask register.
#define | MSR_MTRRVARBASE2 0x00000204
Variable MTRR Entry 2 PhysBase register.
#define | MSR_MTRRVARMASK2 0x00000205
Variable MTRR Entry 2 PhysMask register.
#define | MSR_MTRRVARBASE3 0x00000206
Variable MTRR Entry 3 PhysBase register.
#define | MSR_MTRRVARMASK3 0x00000207
Variable MTRR Entry 3 PhysMask register.
#define | MSR_MTRRVARBASE4 0x00000208
Variable MTRR Entry 4 PhysBase register.
#define | MSR_MTRRVARMASK4 0x00000209
Variable MTRR Entry 4 PhysMask register.
#define | MSR_MTRRVARBASE5 0x0000020A
Variable MTRR Entry 5 PhysBase register.
#define | MSR_MTRRVARMASK5 0x0000020B
Variable MTRR Entry 5 PhysMask register.
#define | MSR_MTRRVARBASE6 0x0000020C
Variable MTRR Entry 6 PhysBase register.
#define | MSR_MTRRVARMASK6 0x0000020D
Variable MTRR Entry 6 PhysMask register.
#define | MSR_MTRRVARBASE7 0x0000020E
Variable MTRR Entry 7 PhysBase register.
#define | MSR_MTRRVARMASK7 0x0000020F
Variable MTRR Entry 7 PhysMask register.
#define | MSR_MTRRVARBASE8 0x00000210
Variable MTRR Entry 8 PhysBase register.
#define | MSR_MTRRVARMASK8 0x00000211
Variable MTRR Entry 8 PhysMask register.
#define | MSR_MTRRVARBASE9 0x00000212
Variable MTRR Entry 9 PhysBase register.
#define | MSR_MTRRVARMASK9 0x00000213
Variable MTRR Entry 9 PhysMask register.
#define | MSR_MTRRFIX64K 0x00000250
Maps 512K address range from 0H-7FFFFH.
#define | MSR_MTRRFIX16K8 0x00000258
Maps 128K address range from 80000H-9FFFFH.
#define | MSR_MTRRFIX16KA 0x00000259
Maps 128K address range from A0000H-BFFFFH.
#define | MSR_MTRRFIX4KC0 0x00000268
Maps 32K address range from C0000H-C7FFFH.
#define | MSR_MTRRFIX4KC8 0x00000269
Maps 32K address range from C8000H-CFFFFH.
#define | MSR_MTRRFIX4KD0 0x0000026A
Maps 32K address range from D0000H-D7FFFH.
#define | MSR_MTRRFIX4KD8 0x0000026B
Maps 32K address range from D8000H-DFFFFH.
#define | MSR_MTRRFIX4KE0 0x0000026C
Maps 32K address range from E0000H-E7FFFH.
#define | MSR_MTRRFIX4KE8 0x0000026D
Maps 32K address range from E8000H-EFFFFH.
#define | MSR_MTRRFIX4KF0 0x0000026E
Maps 32K address range from F0000H-F7FFFH.
#define | MSR_MTRRFIX4KF8 0x0000026F
Maps 32K address range from F8000H-FFFFFH.
#define | MSR_PAT 0x00000277
PAT memtypes register. More...
#define | MSR_MC0_MISC2 0x00000280
Machine Check CTL2 Register.
#define | MSR_MC1_MISC2 0x00000281
Machine Check CTL2 Register.
#define | MSR_MC2_MISC2 0x00000282
Machine Check CTL2 Register.
#define | MSR_MC3_MISC2 0x00000283
Machine Check CTL2 Register.
#define | MSR_MC4_CTL2 0x00000284
IA32_MEE_MC_CTL2 MC MSR aliased to IA32_PCU5_MC_CTL2.
#define | MSR_MC5_CTL2 0x00000285
Machine check CTL2 MSR.
#define | MSR_MC6_CTL2 0x00000286
Machine Check CTL2 Register.
#define | MSR_MC7_CTL2 0x00000287
LLC MCA bank: Control 2 register.
#define | MSR_MC8_CTL2 0x00000288
LLC MCA bank: Control 2 register.
#define | MSR_MC9_CTL2 0x00000289
LLC MCA bank: Control 2 register.
#define | MSR_MC10_CTL2 0x0000028A
LLC MCA bank: Control 2 register.
#define | MSR_MC11_CTL2 0x0000028B
LLC MCA bank: Control 2 register.
#define | MSR_MC12_CTL2 0x0000028C
LLC MCA bank: Control 2 register.
#define | MSR_MC13_CTL2 0x0000028D
LLC MCA bank: Control 2 register.
#define | MSR_MC14_CTL2 0x0000028E
LLC MCA bank: Control 2 register.
#define | MSR_MC15_CTL2 0x0000028F
LLC MCA bank: Control 2 register.
#define | MSR_MC16_CTL2 0x00000290
LLC MCA bank: Control 2 register.
#define | MSR_MC17_CTL2 0x00000291
LLC MCA bank: Control 2 register.
#define | MSR_MC18_CTL2 0x00000292
LLC MCA bank: Control 2 register.
#define | MSR_MC19_CTL2 0x00000293
EDRAM 0 Machine Check Architecture Control 2 MSR.
#define | MSR_MC20_CTL2 0x00000294
EDRAM 1 Machine Check Architecture Control 2 MSR.
#define | MSR_MC21_CTL2 0x00000295
2LM MCA bank: Control 2 register
#define | MSR_MC22_CTL2 0x00000296
2LM MCA bank: Control 2 register
#define | MSR_MC23_CTL2 0x00000297
2LM MCA bank: Control 2 register
#define | MSR_MC24_CTL2 0x00000298
2LM MCA bank: Control 2 register
#define | MSR_MTRRDEFAULT 0x000002FF
Default MTRR related Memory Type and Enables, Details Vol. More...
#define | MSR_PERF_OCCUPANCY_CTRS 0x00000305
PERFCNTD OCCUPANCY COUNTER.
#define | MSR_EMON_FIXED_CTR0 0x00000309
FIXED PERFORMANCE COUNTER.
#define | MSR_EMON_FIXED_CTR1 0x0000030A
FIXED PERFORMANCE COUNTER.
#define | MSR_EMON_FIXED_CTR2 0x0000030B
FIXED PERFORMANCE COUNTER.
#define | MSR_EMON_FIXED_CTR3 0x0000030C
FIXED PERFORMANCE COUNTER.
#define | MSR_PERF_METRICS 0x00000329
Perfmon msr for exposure metrics on several emons.
#define | MSR_EMON_PERF_CAPABILITIES 0x00000345
This register is a Read Only MSR that enumerates the existence of certain debug features in PerfMon.
#define | MSR_EMON_FIXED_CTR_CTRL 0x0000038D
This register provides enabling for the fixed performance counters and enabling for PMI and also provides a the MYTHREADS/ALLTHREADS for each counter as well.
#define | MSR_EMON_PERF_GLOBAL_STATUS 0x0000038E
Global Performance Counter Status A write of '1' to any of the bits in this register causes the corresponding bit in the IA32_CR_PERF_GLOBAL_STATUS register to set to '1'. More...
#define | MSR_EMON_PERF_GLOBAL_CTRL 0x0000038F
The IA32_CR_PERF_GLOBAL_CTRL MSR is used to globally control all the PERFMON counters for a given thread at once. More...
#define | MSR_EMON_PERF_GLOBAL_RESET 0x00000390
Global Performance Counter Reset Control.
#define | MSR_EMON_PERF_GLOBAL_SET 0x00000391
The Core PerfMon global overflow set MSR is writable only command register. More...
#define | MSR_PEBS_ENABLE 0x000003F1
Precise Event Based Sampling controlling register.
#define | MSR_PEBS_DATA_CFG 0x000003F2
PEBS DATA CFG.
#define | MSR_MC0_CTL 0x00000400
Machine Check Control Register.
#define | MSR_MC0_STATUS 0x00000401
Machine Check Status Register.
#define | MSR_MC0_ADDR 0x00000402
Machine Check Address Register.
#define | MSR_MC0_MISC 0x00000403
Machine Check Misc Register.
#define | MSR_MC1_CTL 0x00000404
Machine Check Control Register.
#define | MSR_MC1_STATUS 0x00000405
Machine Check Status Register.
#define | MSR_MC1_ADDR 0x00000406
Machine Check Address Register.
#define | MSR_MC1_MISC 0x00000407
Machine Check Status Register.
#define | MSR_MC2_CTL 0x00000408
Machine Check Control Register.
#define | MSR_MC2_STATUS 0x00000409
DTLB Machine Check Status register.
#define | MSR_MC2_ADDR 0x0000040A
Machine Check Address Register.
#define | MSR_MC2_MISC 0x0000040B
Machine Check Misc Register.
#define | MSR_MC3_CTL 0x0000040C
Machine Check Control Register.
#define | MSR_MC3_STATUS 0x0000040D
Machine Check Status Register.
#define | MSR_MC3_ADDR 0x0000040E
Machine Check Address Register.
#define | MSR_MC3_MISC 0x0000040F
Machine Check Misc Register.
#define | MSR_MC4_CTL 0x00000410
MEE and Ucode/Xucode bank: Control register.
#define | MSR_MC4_STATUS 0x00000411
MEE and Ucode/Xucode MCA bank: Status register.
#define | MSR_MC4_ADDR 0x00000412
MEE and Ucode/Xucode bank: Address register.
#define | MSR_MC4_MISC 0x00000413
MMEE and Ucode/Xucode bank: Misc register.
#define | MSR_MC5_CTL 0x00000414
MEE1 bank: Control register.
#define | MSR_MC5_STATUS 0x00000415
MEE1 bank: Status register.
#define | MSR_MC5_ADDR 0x00000416
MEE1 bank: Address register.
#define | MSR_MC5_MISC 0x00000417
MMEE1 bank: Misc register.
#define | MSR_MC6_CTL 0x00000418
Machine Check Architecture Control MSR.
#define | MSR_MC6_STATUS 0x00000419
Machine Check Architecture Status MSR.
#define | MSR_MC6_ADDR 0x0000041A
PCU Machine Check Architecture Address MSR.
#define | MSR_MC6_MISC 0x0000041B
PCU Machine Check Architecture Misc MSR.
#define | MSR_MC7_CTL 0x0000041C
CBO and LLC MCA bank: Control register.
#define | MSR_MC7_STATUS 0x0000041D
LLC MCA bank: Status register.
#define | MSR_MC7_ADDR 0x0000041E
LLC MCA bank: Address register.
#define | MSR_MC7_MISC 0x0000041F
LLC MCA bank: Misc register.
#define | MSR_MC8_CTL 0x00000420
CBO and LLC MCA bank: Control register.
#define | MSR_MC8_STATUS 0x00000421
LLC MCA bank: Status register.
#define | MSR_MC8_ADDR 0x00000422
LLC MCA bank: Address register.
#define | MSR_MC8_MISC 0x00000423
LLC MCA bank: Misc register.
#define | MSR_MC9_CTL 0x00000424
CBO and LLC MCA bank: Control register.
#define | MSR_MC9_STATUS 0x00000425
LLC MCA bank: Status register.
#define | MSR_MC9_ADDR 0x00000426
LLC MCA bank: Address register.
#define | MSR_MC9_MISC 0x00000427
LLC MCA bank: Misc register.
#define | MSR_MC10_CTL 0x00000428
CBO and LLC MCA bank: Control register.
#define | MSR_MC10_STATUS 0x00000429
LLC MCA bank: Status register.
#define | MSR_MC10_ADDR 0x0000042A
LLC MCA bank: Address register.
#define | MSR_MC10_MISC 0x0000042B
LLC MCA bank: Misc register.
#define | MSR_MC11_CTL 0x0000042C
CBO and LLC MCA bank: Control register.
#define | MSR_MC11_STATUS 0x0000042D
LLC MCA bank: Status register.
#define | MSR_MC11_ADDR 0x0000042E
LLC MCA bank: Address register.
#define | MSR_MC11_MISC 0x0000042F
LLC MCA bank: Misc register.
#define | MSR_MC12_CTL 0x00000430
CBO and LLC MCA bank: Control register.
#define | MSR_MC12_STATUS 0x00000431
LLC MCA bank: Status register.
#define | MSR_MC12_ADDR 0x00000432
LLC MCA bank: Address register.
#define | MSR_MC12_MISC 0x00000433
LLC MCA bank: Misc register.
#define | MSR_MC13_CTL 0x00000434
CBO and LLC MCA bank: Control register.
#define | MSR_MC13_STATUS 0x00000435
LLC MCA bank: Status register.
#define | MSR_MC13_ADDR 0x00000436
LLC MCA bank: Address register.
#define | MSR_MC13_MISC 0x00000437
LLC MCA bank: Misc register.
#define | MSR_MC14_CTL 0x00000438
CBO and LLC MCA bank: Control register.
#define | MSR_MC14_STATUS 0x00000439
LLC MCA bank: Status register.
#define | MSR_MC14_ADDR 0x0000043A
LLC MCA bank: Address register.
#define | MSR_MC14_MISC 0x0000043B
LLC MCA bank: Misc register.
#define | MSR_MC15_CTL 0x0000043C
CBO and LLC MCA bank: Control register.
#define | MSR_MC15_STATUS 0x0000043D
LLC MCA bank: Status register.
#define | MSR_MC15_ADDR 0x0000043E
LLC MCA bank: Address register.
#define | MSR_MC15_MISC 0x0000043F
LLC MCA bank: Misc register.
#define | MSR_MC16_CTL 0x00000440
CBO and LLC MCA bank: Control register.
#define | MSR_MC16_STATUS 0x00000441
LLC MCA bank: Status register.
#define | MSR_MC16_ADDR 0x00000442
LLC MCA bank: Address register.
#define | MSR_MC16_MISC 0x00000443
LLC MCA bank: Misc register.
#define | MSR_MC17_CTL 0x00000444
CBO and LLC MCA bank: Control register.
#define | MSR_MC17_STATUS 0x00000445
LLC MCA bank: Status register.
#define | MSR_MC17_ADDR 0x00000446
LLC MCA bank: Address register.
#define | MSR_MC17_MISC 0x00000447
LLC MCA bank: Misc register.
#define | MSR_MC18_CTL 0x00000448
CBO and LLC MCA bank: Control register.
#define | MSR_MC18_STATUS 0x00000449
LLC MCA bank: Status register.
#define | MSR_MC18_ADDR 0x0000044A
LLC MCA bank: Address register.
#define | MSR_MC18_MISC 0x0000044B
LLC MCA bank: Misc register.
#define | MSR_MC19_CTL 0x0000044C
EDRAM 0 Machine Check Architecture Control MSR.
#define | MSR_MC19_STATUS 0x0000044D
EDRAM 0 MCA bank: Status Register.
#define | MSR_MC19_ADDR 0x0000044E
EDRAM 0 MCA bank: Address register.
#define | MSR_MC20_CTL 0x00000450
EDRAM 1 Machine Check Architecture Control MSR.
#define | MSR_MC20_STATUS 0x00000451
EDRAM 1 MCA bank: Status Register.
#define | MSR_MC20_ADDR 0x00000452
EDRAM 1 MCA bank: Address register.
#define | MSR_MC21_CTL 0x00000454
2LM MCA bank: Control register
#define | MSR_MC21_STATUS 0x00000455
2LM MCA bank: Status register
#define | MSR_MC21_ADDR 0x00000456
2LM MCA bank: Address register
#define | MSR_MC21_MISC 0x00000457
2LM MCA bank: Miscellaneous register
#define | MSR_MC22_CTL 0x00000458
2LM MCA bank: Control register
#define | MSR_MC22_STATUS 0x00000459
2LM MCA bank: Status register
#define | MSR_MC22_ADDR 0x0000045A
2LM MCA bank: Address register
#define | MSR_MC22_MISC 0x0000045B
2LM MCA bank: Miscellaneous register
#define | MSR_MC23_CTL 0x0000045C
2LM MCA bank: Control register
#define | MSR_MC23_STATUS 0x0000045D
2LM MCA bank: Status register
#define | MSR_MC23_ADDR 0x0000045E
2LM MCA bank: Address register
#define | MSR_MC23_MISC 0x0000045F
2LM MCA bank: Miscellaneous register
#define | MSR_MC24_CTL 0x00000460
2LM MCA bank: Control register
#define | MSR_MC24_STATUS 0x00000461
2LM MCA bank: Status register
#define | MSR_MC24_ADDR 0x00000462
2LM MCA bank: Address register
#define | MSR_MC24_MISC 0x00000463
2LM MCA bank: Miscellaneous register
#define | MSR_VMX_MSR_0 0x00000480
VMX Capability MSR. More...
#define | MSR_VMX_MSR_1 0x00000481
VMX Capability MSR. More...
#define | MSR_VMX_MSR_2 0x00000482
VMX Capability MSR.allowed setting for Processor-based VM-execution controls.
#define | MSR_VMX_MSR_3 0x00000483
VMX Capability MSR.allowed setting for VMEXIT controls.
#define | MSR_VMX_MSR_4 0x00000484
VMX Capability MSR.allowed setting for VMENTRY controls.
#define | MSR_VMX_MSR_5 0x00000485
VMX Capability MSR.info on preemption timer, STM and more.
#define | MSR_VMX_MSR_6 0x00000486
VMX Capability MSR.Allowed 0-settings for CR0 in VMX mode.
#define | MSR_VMX_MSR_7 0x00000487
VMX Capability MSR.Allowed 1-settings for CR0 in VMX mode.
#define | MSR_VMX_MSR_8 0x00000488
VMX Capability MSR.Allowed 0-settings for CR4 in VMX mode.
#define | MSR_VMX_MSR_9 0x00000489
VMX Capability MSR.Allowed 1-settings for CR4 in VMX mode.
#define | MSR_VMX_MSR_10 0x0000048A
VMX Capability MSR.VMCS encoding info.
#define | MSR_VMX_MSR_11 0x0000048B
VMX Capability MSR.allowed setting for SECONDARY PROCESSOR-BASED CTLS.
#define | MSR_VMX_MSR_12 0x0000048C
VMX Capability MSR.EPT CAPABILITIES.
#define | MSR_VMX_TRUE_PINBASED_CTLS 0x0000048D
VMX Capability MSR. More...
#define | MSR_VMX_TRUE_PROCBASED_CTLS 0x0000048E
Capability Reporting Register of Primary Processor-based VM-execution Flex Controls.
#define | MSR_VMX_TRUE_EXIT_CTLS 0x0000048F
Capability Reporting Register of VM-exit Flex Controls.
#define | MSR_VMX_TRUE_ENTRY_CTLS 0x00000490
Capability Reporting Register of VM-entry Flex Controls.
#define | MSR_VMX_VMFUNC_CTLS 0x00000491
VMX Capability MSR.
#define | MSR_VMX_PROCBASED_CTLS3 0x00000492
Allowed 1-settings of tertiary processor-based VM-execution controls.
#define | MSR_EMON_FULL_CTR0 0x000004C1
Full Width Writable IA32_PMC0 Alias.
#define | MSR_EMON_FULL_CTR1 0x000004C2
Full Width Writable IA32_PMC1 Alias.
#define | MSR_EMON_FULL_CTR2 0x000004C3
Full Width Writable IA32_PMC2 Alias.
#define | MSR_EMON_FULL_CTR3 0x000004C4
Full Width Writable IA32_PMC3 Alias.
#define | MSR_EMON_FULL_CTR4 0x000004C5
Full Width Writable IA32_PMC4 Alias.
#define | MSR_EMON_FULL_CTR5 0x000004C6
Full Width Writable IA32_PMC5 Alias.
#define | MSR_EMON_FULL_CTR6 0x000004C7
Full Width Writable IA32_PMC6 Alias.
#define | MSR_EMON_FULL_CTR7 0x000004C8
Full Width Writable IA32_PMC7 Alias.
#define | MSR_RTIT_OUTPUT_BASE 0x00000560
Pointer to current RTIT Table of Physical Addresses (ToPA)
#define | MSR_RTIT_OUTPUT_MASK_PTRS 0x00000561
Holds pointers to the current output region (page) in the current ToPA.
#define | MSR_RTIT_CTL 0x00000570
RTIT Control MSR.
#define | MSR_RTIT_STATUS 0x00000571
RTIT status MSR.
#define | MSR_RTIT_CR3_MATCH 0x00000572
CR3 value used for RTIT filtering.
#define | MSR_RTIT_ADDR0_A 0x00000580
MSR used to support EIP filtering.
#define | MSR_RTIT_ADDR0_B 0x00000581
MSR used to support EIP filtering.
#define | MSR_RTIT_ADDR1_A 0x00000582
MSR used to support EIP filtering.
#define | MSR_RTIT_ADDR1_B 0x00000583
MSR used to support EIP filtering.
#define | MSR_DS_AREA 0x00000600
Points to the linear address of the first byte of the DS buffer management area, which is used to manage the BTS and PEBS buffers.
#define | MSR_MLC_PCNT_COUNTER 0x0000064E
productivity cycles counter (HWP)
#define | MSR_FAST_UNCORE_MSRS_CTL 0x00000657
Fast wrmsr/rdmsr control MSR. More...
#define | MSR_U_CET 0x000006A0
CET user configuration MSR.
#define | MSR_S_CET 0x000006A2
CET supervisor configuration MSR.
#define | MSR_PL0_SSP 0x000006A4
CET register to hold CPL0s shadow stack pointer on transition to CPL3.
#define | MSR_PL1_SSP 0x000006A5
CET register to hold CPL1s shadow stack pointer on transition to CPL3.
#define | MSR_PL2_SSP 0x000006A6
CET register to hold CPL2s shadow stack pointer on transition to CPL3.
#define | MSR_PL3_SSP 0x000006A7
CET register to hold CPL3s shadow stack pointer on transition to CPL < 3.
#define | MSR_INTERRUPT_SSP_TABLE 0x000006A8
linear address of the table of pointers to shadow stacks to be switched to when initiating a stack switch in 64 bit mode through IST mechanism. More...
#define | MSR_GT_PERF_LIMIT_REASONS 0x000006B0
Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency. More...
#define | MSR_CLR_PERF_LIMIT_REASONS 0x000006B1
Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency. More...
#define | MSR_TSC_DEADLINE 0x000006E0
TSC Target of Local APIC's TSC Deadline Mode.
#define | MSR_HWP_REQUEST_PKG 0x00000772
Used to convey the OSs performance request {Min, Max. More...
#define | MSR_PERMON_EVNTSEL_AUX 0x00000966
This is a new PerfMon register is used for future user-invisible controls to be shadowed in all PerfMon units.
#define | MSR_TME_CAPABILITY 0x00000981
Read only register for encryption policies supported by TME.
#define | MSR_TME_ACTIVATE 0x00000982
Rd/Wr register to generate or restore Keys for TME.
#define | MSR_TME_EXCLUDE_MASK 0x00000983
Register for debug purposes to exclude a memory range from encryption by TME.
#define | MSR_TME_EXCLUDE_BASE 0x00000984
Register for debug purposes to exclude a memory range from encryption by TME.
#define | MSR_COPY_STATUS 0x00000990
FSCP To hold keylocker information.
#define | MSR_IWKEYBACKUP_STATUS 0x00000991
Status of IWKey Backup in PCH.
#define | MSR_PRIVACY_CONTROL 0x00000C80
This register implements Debug Interface (Privacy) MSR.
#define | MSR_L2_QOS_CFG 0x00000C82
MLC Class Of Service Configuration Register.
#define | MSR_CLOS_CONFIG 0x00000C8F
Class Of Service Configuration Register.
#define | MSR_COS_WAYS_0 0x00000C90
available ways vectors for class of service of IA core
#define | MSR_COS_WAYS_1 0x00000C91
available ways vectors for class of service of IA core
#define | MSR_COS_WAYS_2 0x00000C92
available ways vectors for class of service of IA core
#define | MSR_COS_WAYS_3 0x00000C93
available ways vectors for class of service of IA core
#define | MSR_L2_QOS_MASK_0_0 0x00000D10
Spare for WLC.
#define | MSR_L2_QOS_MASK_1_1 0x00000D11
Spare for WLC.
#define | MSR_L2_QOS_MASK_2_2 0x00000D12
Spare for WLC.
#define | MSR_L2_QOS_MASK_3_3 0x00000D13
Spare for WLC.
#define | MSR_L2_QOS_MASK_4_4 0x00000D14
Spare for WLC.
#define | MSR_L2_QOS_MASK_5_5 0x00000D15
Spare for WLC.
#define | MSR_L2_QOS_MASK_6_6 0x00000D16
Spare for WLC.
#define | MSR_L2_QOS_MASK_7_7 0x00000D17
Spare for WLC.
#define | MSR_BNDCFGS 0x00000D90
BNDCFGS MSR.
#define | MSR_COPY_LOCAL_TO_PLATFORM 0x00000D91
Initiatate copy of IWKEY from Core to PCH for Keylocker.
#define | MSR_COPY_PLATFORM_TO_LOCAL 0x00000D92
Initiatate copy of IWKEY from PCH to Core for Keylocker.
#define | MSR_PASID 0x00000D93
PASID MSR programmed by OS for ENQ* instruction (AiA)
#define | MSR_PKG_SDC_CTL 0x00000DB0
Enables options to control the SDC operation.
#define | MSR_PM_CTL1 0x00000DB1
This is a read/write MSR.
#define | MSR_MPX_LAX 0x00001000
MPX extension for determine MAWAU.
#define | MSR_HW_FB_PTR 0x000017D0
The physical address of the Hardware Scheduler Information table.
#define | MSR_HW_FB_CONFIG 0x000017D1
The operating system enables the hardware guided scheduler interface using new package scoped MSR.
#define | MSR_SF_QOS_MASK_0_0 0x00001890
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_1_1 0x00001891
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_2_2 0x00001892
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_3_3 0x00001893
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_4_4 0x00001894
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_5_5 0x00001895
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_6_6 0x00001896
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_7_7 0x00001897
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_8_8 0x00001898
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_9_9 0x00001899
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_10_10 0x0000189A
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_11_11 0x0000189B
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_12_12 0x0000189C
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_13_13 0x0000189D
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_14_14 0x0000189E
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_SF_QOS_MASK_15_15 0x0000189F
available ways vectors for class of service of LLC snoop filter " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"
#define | MSR_IA32_CR_EFER 0xC0000080
Global register for x86 EFER.
#define | MSR_STAR 0xC0000081
SYSCALL/SYSRET selectors and legacy SYSCALL target EIP.
#define | MSR_LSTAR 0xC0000082
64-bit-mode SYSCALL target RIP
#define | MSR_CSTAR 0xC0000083
MSR for compatibility-mode SYSCALL target RIP.
#define | MSR_SFMASK 0xC0000084
SYSCALL flag mask.
#define | MSR_FS_BASE 0xC0000100
FS base MSR.
#define | MSR_GS_BASE 0xC0000101
GS base MSR.
#define | MSR_KERNEL_GSBASE 0xC0000102
Swap Target of BASE Address of GS.
#define | MSR_TSC_AUX 0xC0000103
Time-stamp counter auxilliary field.

Detailed Description

ArchMsr.h.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ArchMsr.h.

Macro Definition Documentation

◆ MSR_BIOS_UPDT_TRIG

#define MSR_BIOS_UPDT_TRIG 0x00000079

Executing a WRMSR instruction to this MSR causes a microcode update to be loaded into the processor.

A processor may prevent writing to this MSR when loading guest states on VM entries or saving guest states on VM exits.

Definition at line 492 of file ArchMsr.h.

◆ MSR_BIOS_UPGD_TRIG

#define MSR_BIOS_UPGD_TRIG 0x0000007A

Implements Feature Activation command.

WRMSR to this address activates all 'activatible' features on this thread. EDX:EAX = 0x1 (SE only at this point)

Definition at line 499 of file ArchMsr.h.

◆ MSR_CLR_PERF_LIMIT_REASONS

#define MSR_CLR_PERF_LIMIT_REASONS 0x000006B1

Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency.

Status bits are updated by pcode through the io interface IO_CLR_PERF_LIMIT, log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

Definition at line 16799 of file ArchMsr.h.

◆ MSR_EMON_PERF_GLOBAL_CTRL

#define MSR_EMON_PERF_GLOBAL_CTRL 0x0000038F

The IA32_CR_PERF_GLOBAL_CTRL MSR is used to globally control all the PERFMON counters for a given thread at once.

This allows instant on/off of all PERFMON counters.

Definition at line 8220 of file ArchMsr.h.

◆ MSR_EMON_PERF_GLOBAL_SET

#define MSR_EMON_PERF_GLOBAL_SET 0x00000391

The Core PerfMon global overflow set MSR is writable only command register.

A read from this register will always return zeroes. A write of '1' to any of the bits in this register causes the corresponding bit in the IA32_CR_PERF_GLOBAL_STATUS register to set to '1'.

Definition at line 8422 of file ArchMsr.h.

◆ MSR_EMON_PERF_GLOBAL_STATUS

#define MSR_EMON_PERF_GLOBAL_STATUS 0x0000038E

Global Performance Counter Status A write of '1' to any of the bits in this register causes the corresponding bit in the IA32_CR_PERF_GLOBAL_STATUS register to set to '1'.

Write to '0 ignored.

Definition at line 8065 of file ArchMsr.h.

◆ MSR_ENERGY_PERFORMANCE_BIAS

#define MSR_ENERGY_PERFORMANCE_BIAS 0x000001B0

Performance Energy Bias Hint MSR.

This register allows software to control the Energy efficiency Policy in the CPU.

Definition at line 3385 of file ArchMsr.h.

◆ MSR_FAST_UNCORE_MSRS_CTL

#define MSR_FAST_UNCORE_MSRS_CTL 0x00000657

Fast wrmsr/rdmsr control MSR.

Each bit refers to one MSR and indicate if this MSR is set to use the FAST_UNCORE_MSRS mode. Currently , bit 0 refers to IA32_HWP_REQUEST , while bit 1 refers to THREAD_INFO MSR

Definition at line 16312 of file ArchMsr.h.

◆ MSR_GT_PERF_LIMIT_REASONS

#define MSR_GT_PERF_LIMIT_REASONS 0x000006B0

Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency.

Status bits are updated by pcode through the io interface IO_GT_PERF_LIMIT, log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

Definition at line 16534 of file ArchMsr.h.

◆ MSR_HWP_REQUEST_PKG

#define MSR_HWP_REQUEST_PKG 0x00000772

Used to convey the OSs performance request {Min, Max.

Desired, tc} to apply across threads if requested.

Definition at line 17058 of file ArchMsr.h.

◆ MSR_INTERRUPT_SSP_TABLE

#define MSR_INTERRUPT_SSP_TABLE 0x000006A8

linear address of the table of pointers to shadow stacks to be switched to when initiating a stack switch in 64 bit mode through IST mechanism.

Must be machine canonical when written in 64 bit mode. On parts that do not support 64 bit mode, this MSR is not present.

Definition at line 16527 of file ArchMsr.h.

◆ MSR_MONITOR_FILTER_SIZE

#define MSR_MONITOR_FILTER_SIZE 0x00000006

Used by the OS or BIOS to program to the maximum MONITOR line size in the system.

CPUID will return the maximum line size of the processor and the system for the purposes of Monitor and MWait. Software can use this information to pad data appropriately to avoid cross-cluster hot-spots.

Definition at line 150 of file ArchMsr.h.

◆ MSR_MTRRDEFAULT

#define MSR_MTRRDEFAULT 0x000002FF

Default MTRR related Memory Type and Enables, Details Vol.

3A 11.11.2.3

Definition at line 7500 of file ArchMsr.h.

◆ MSR_OPTIN_FEATURE_CONTROL

#define MSR_OPTIN_FEATURE_CONTROL 0x0000003A

Control Features in Intel 64 Processor.

see Appendix G.3.1

Definition at line 304 of file ArchMsr.h.

◆ MSR_PAT

#define MSR_PAT 0x00000277

PAT memtypes register.

8 seperate entries

Definition at line 5919 of file ArchMsr.h.

◆ MSR_PERF_CTL

#define MSR_PERF_CTL 0x00000199

Legacy Performance Control MSR.

SW requests a new Performance state (P-State) by writing to this MSR. [IntelRsvd]ARCH MSR in core - P-state control register reflected into P-STATE_REQ[/IntelRsvd]

Definition at line 2771 of file ArchMsr.h.

◆ MSR_TIME_STAMP_COUNTER

#define MSR_TIME_STAMP_COUNTER 0x00000010

The time-stamp counter is a 64-bit counter that is set to 0 following a RESET of the processor.

Following a RESET, the counter increments even when the processor is halted by the HLT instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop.

Definition at line 183 of file ArchMsr.h.

◆ MSR_VMX_MSR_0

#define MSR_VMX_MSR_0 0x00000480

VMX Capability MSR.

IA32_VMX_BASIC info.

Definition at line 15340 of file ArchMsr.h.

◆ MSR_VMX_MSR_1

#define MSR_VMX_MSR_1 0x00000481

VMX Capability MSR.

allowed setting for PIN BASED VMCS execution control

Definition at line 15344 of file ArchMsr.h.

◆ MSR_VMX_TRUE_PINBASED_CTLS

#define MSR_VMX_TRUE_PINBASED_CTLS 0x0000048D

VMX Capability MSR.

allowed setting for PIN BASED VMCS execution control

Definition at line 15392 of file ArchMsr.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ArchMsr.h Source File

Intel

ClientOneSiliconPkg

Cpu

Include

Register

ArchMsr.h

Go to the documentation of this file.

1

2 /** @file

3 ArchMsr.h

4

5 @copyright

6 INTEL CONFIDENTIAL

7 Copyright 2019 - 2020 Intel Corporation.

8

9 The source code contained or described herein and all documents related to the

10 source code ("Material") are owned by Intel Corporation or its suppliers or

11 licensors. Title to the Material remains with Intel Corporation or its suppliers

12 and licensors. The Material may contain trade secrets and proprietary and

13 confidential information of Intel Corporation and its suppliers and licensors,

14 and is protected by worldwide copyright and trade secret laws and treaty

15 provisions. No part of the Material may be used, copied, reproduced, modified,

16 published, uploaded, posted, transmitted, distributed, or disclosed in any way

17 without Intel's prior express written permission.

18

19 No license under any patent, copyright, trade secret or other intellectual

20 property right is granted to or conferred upon you by disclosure or delivery

21 of the Materials, either expressly, by implication, inducement, estoppel or

22 otherwise. Any license under such intellectual property rights must be

23 express and approved by Intel in writing.

24

25 Unless otherwise agreed by Intel in writing, you may not remove or alter

26 this notice or any other notice embedded in Materials by Intel or

27 Intel's suppliers or licensors in any way.

28

29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as

30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under

31 the terms of your license agreement with Intel or your vendor. This file may

32 be modified by the user, subject to additional terms of the license agreement.

33

34 @par Specification Reference:

35 **/

36

37 #ifndef _ARCHMSR_h

38 #define _ARCHMSR_h

39 #include <Base.h>

40

41 /**

42 Machine Check Status Register

43 **/

44 #define MSR_P5_MC_ADDR 0x00000001

45

46 typedef union {

47 ///

48 /// Individual bit fields

49 ///

50 struct {

51 UINT32 Mcacod : 9;

52

53 /* Bits[8:0], Access Type=RW_V, default=None*/

54

55 /* Machine Check Architecture Error Code */

56 UINT32 EnhMcaAvail0 : 7;

57

58 /* Bits[15:9], Access Type=RW_V, default=None*/

59

60 /* Reserved bits */

61 UINT32 Mscod : 4;

62

63 /* Bits[19:16], Access Type=RW_V, default=None*/

64

65 /* Machine Specific Architecture Error Code */

66 UINT32 EnhMcaAvail10 : 12;

67

68 /* Bits[31:20], Access Type=RW_V, default=None*/

69

70 /* Reserved bits */

71 UINT32 EnhMcaAvail11 : 6;

72

73 /* Bits[37:32], Access Type=RW_V, default=None*/

74

75 /* Reserved bits */

76 UINT32 CorrectedErrCnt : 14;

77

78 /* Bits[51:38], Access Type=RW_V, default=None*/

79

80 /*

81 Corrected error count since last clear of mc

82 regs

83 */

84 UINT32 Sticky : 1;

85

86 /* Bits[52:52], Access Type=RW_V, default=None*/

87

88 /* Sticky bit set when error count overflows */

89 UINT32 EnhMcaAvail2 : 2;

90

91 /* Bits[54:53], Access Type=RW_V, default=None*/

92

93 /* Reserved bits */

94 UINT32 Ar : 1;

95

96 /* Bits[55:55], Access Type=RW_V, default=None*/

97

98 /* Action required */

99 UINT32 S : 1;

100

101 /* Bits[56:56], Access Type=RW_V, default=None*/

102

103 /* Signaling */

104 UINT32 Pcc : 1;

105

106 /* Bits[57:57], Access Type=RW_V, default=None*/

107

108 /* Processor Context Corrupt */

109 UINT32 Addrv : 1;

110

111 /* Bits[58:58], Access Type=RW_V, default=None*/

112

113 /* MC0_ADDR register valid */

114 UINT32 Miscv : 1;

115

116 /* Bits[59:59], Access Type=RW_V, default=None*/

117

118 /* MC0_MISC register valid */

119 UINT32 En : 1;

120

121 /* Bits[60:60], Access Type=RW_V, default=None*/

122

123 /* Error Enabled */

124 UINT32 Uc : 1;

125

126 /* Bits[61:61], Access Type=RW_V, default=None*/

127

128 /* Uncorrectable Error */

129 UINT32 Over : 1;

130

131 /* Bits[62:62], Access Type=RW_V, default=None*/

132

133 /* Machine Check Overflow */

134 UINT32 Val : 1;

135

136 /* Bits[63:63], Access Type=RW_V, default=None*/

137

138 /* Status register Valid */

139

140 } Bits;

141

142 UINT32 Uint32;

143 UINT64 Uint64;

144

145 } MSR_P5_MC_ADDR_REGISTER;

146

147 /**

148 Used by the OS or BIOS to program to the maximum MONITOR line size in the system. CPUID will return the maximum line size of the processor and the system for the purposes of Monitor and MWait. Software can use this information to pad data appropriately to avoid cross-cluster hot-spots.

149 **/

150 #define MSR_MONITOR_FILTER_SIZE 0x00000006

151

152 typedef union {

153 ///

154 /// Individual bit fields

155 ///

156 struct {

157 UINT32 LineSize : 16;

158

159 /* Bits[15:0], Access Type=RW, default=None*/

160

161 /*

162 Specifies the number of bytes in a cache line or

163 chipset line buffer. BIOS reads this field and

164 the chipset line buffer register. BIOS then

165 programs this register field with the larger of

166 the two values.

167 */

168 UINT32 Rsvd16 : 16;

169

170 /* Bits[31:16], Access Type=RW, default=None*/

171

172 /* Reserved */

173

174 } Bits;

175

176 UINT32 Uint32;

177 UINT64 Uint64;

178

179 } MSR_MONITOR_FILTER_SIZE_REGISTER;

180 /**

181 The time-stamp counter is a 64-bit counter that is set to 0 following a RESET of the processor. Following a RESET, the counter increments even when the processor is halted by the HLT instruction or the external STPCLK# pin. Note that the assertion of the external DPSLP# pin may cause the time-stamp counter to stop.

182 **/

183 #define MSR_TIME_STAMP_COUNTER 0x00000010

184

185 /**

186 Indicates the platform that the processor is intended for.

187 **/

188 #define MSR_PLATFORM_ID 0x00000017

189

190 typedef union {

191 ///

192 /// Individual bit fields

193 ///

194 struct {

195 UINT32 Rsvd0 : 32;

196

197 /* Bits[31:0], Access Type=RO, default=None*/

198

199 /* Reserved */

200 UINT32 Rsvd32 : 18;

201

202 /* Bits[49:32], Access Type=RO, default=None*/

203

204 /* Reserved */

205 UINT32 Platformid : 3;

206

207 /* Bits[52:50], Access Type=RWS, default=0x00000000*/

208

209 /*

210 The field gives information concerning the

211 intended platform for the processor.

212 */

213 UINT32 Rsvd53 : 11;

214

215 /* Bits[63:53], Access Type=RO, default=None*/

216

217 /* Reserved */

218

219 } Bits;

220

221 UINT32 Uint32;

222 UINT64 Uint64;

223

224 } MSR_PLATFORM_ID_REGISTER;

225

226 /**

227 This register holds the APIC base address, permitting the relocation of the APIC memory map

228 **/

229 #define MSR_APIC_BASE 0x0000001B

230

231 typedef union {

232 ///

233 /// Individual bit fields

234 ///

235 struct {

236 UINT32 Rsvd0 : 8;

237

238 /* Bits[7:0], Access Type=RO, default=None*/

239

240 /* Reserved */

241 UINT32 Bsp : 1;

242

243 /* Bits[8:8], Access Type=RW, default=0x00000000*/

244

245 /*

246 Set if the processor is the Boot Strap

247 Processor.

248 */

249 UINT32 Rsvd9 : 1;

250

251 /* Bits[9:9], Access Type=RO, default=None*/

252

253 /* Reserved */

254 UINT32 ExtendedModeEnable : 1;

255

256 /* Bits[10:10], Access Type=RW, default=0x00000000*/

257

258 /*

259 Enables or Disables APIC extensions. Enable = 1,

260 Disable = 0

261 */

262 UINT32 Enable : 1;

263

264 /* Bits[11:11], Access Type=RW, default=0x00000001*/

265

266 /*

267 Enables or Disables the APIC. Enable = 1,

268 Disable = 0

269 */

270 UINT32 BaseAddress0 : 20;

271

272 /* Bits[31:12], Access Type=RW, default=0x000FEE00*/

273

274 /*

275 The base address of the xAPIC memory map. Note:

276 bits above the supported physical address size

277 reported by CPUID are reserved.

278 */

279 UINT32 BaseAddress1 : 20;

280

281 /* Bits[51:32], Access Type=RW, default=0x00000000*/

282

283 /*

284 The base address of the xAPIC memory map. Note:

285 bits above the supported physical address size

286 reported by CPUID are reserved.

287 */

288 UINT32 Rsvd52 : 12;

289

290 /* Bits[63:52], Access Type=RO, default=None*/

291

292 /* Reserved */

293

294 } Bits;

295

296 UINT32 Uint32;

297 UINT64 Uint64;

298

299 } MSR_APIC_BASE_REGISTER;

300

301 /**

302 Control Features in Intel 64 Processor. see Appendix G.3.1

303 **/

304 #define MSR_OPTIN_FEATURE_CONTROL 0x0000003A

305

306 typedef union {

307 ///

308 /// Individual bit fields

309 ///

310 struct {

311 UINT32 Lock : 1;

312

313 /* Bits[0:0], Access Type=RW, default=None*/

314

315 /*

316 When set, locks this MSR from being written,

317 writes to this bit will result in GP(0) until an

318 S5 reset occurs. BIOS must ensure this lock bit

319 is set before boot to OS. Lock bit for

320 protecting subsequent writes to this MSR. Once

321 set, any subsequent WRMSR attempt will #GP.

322 */

323 UINT32 VmxEnableSmx : 1;

324

325 /* Bits[1:1], Access Type=RW, default=None*/

326

327 /*

328 Enables VMXON when the secure environment is

329 active.

330 */

331 UINT32 VmxEnableNosmx : 1;

332

333 /* Bits[2:2], Access Type=RW, default=None*/

334

335 /*

336 Enables VMXON when no secure environment is

337 active.

338 */

339 UINT32 Reserved3 : 5;

340

341 /* Bits[7:3], Access Type=RW, default=None*/

342

343 /* reserved */

344 UINT32 SenterParameterControl : 7;

345

346 /* Bits[14:8], Access Type=RW, default=None*/

347

348 /*

349 Controls which corresponding parameter bits in

350 EDX[6:0] can be set with execution of SENTER.

351 The corresponding EDX bits are the opposite

352 polarity (disables) of the enables bits for this

353 field.

354 */

355 UINT32 SenterEnable : 1;

356

357 /* Bits[15:15], Access Type=RW, default=None*/

358

359 /* Enables SENTER when set to 1. */

360 UINT32 Reserved16 : 1;

361

362 /* Bits[16:16], Access Type=RW, default=None*/

363

364 /* reserved */

365 UINT32 LeWr : 1;

366

367 /* Bits[17:17], Access Type=RW, default=None*/

368

369 /* reserved */

370 UINT32 SeEnable : 1;

371

372 /* Bits[18:18], Access Type=RW, default=None*/

373

374 /* new SKL bit issue 1349784 - SE */

375 UINT32 PcommitEnable : 1;

376

377 /* Bits[19:19], Access Type=RW, default=None*/

378

379 /* new CNL bit 2LM - PCOMMIT */

380 UINT32 Lmce : 1;

381

382 /* Bits[20:20], Access Type=RW, default=None*/

383

384 /* Local MCE */

385 UINT32 FzmEnable : 1;

386

387 /* Bits[21:21], Access Type=RW, default=None*/

388

389 /* new CNL bit 2LM - FZM */

390 UINT32 Reserved22 : 10;

391

392 /* Bits[31:22], Access Type=RW, default=None*/

393

394 /* reserved */

395

396 } Bits;

397

398 UINT32 Uint32;

399 UINT64 Uint64;

400

401 } MSR_OPTIN_FEATURE_CONTROL_REGISTER;

402 /**

403 Thread specific offset used in RDTSC computation

404 **/

405 #define MSR_TSC_THREAD_OFFSET 0x0000003B

406

407 /**

408 Virtual MSR to set/clear IBRS commands

409 **/

410 #define MSR_SPEC_CTRL 0x00000048

411

412 typedef union {

413 ///

414 /// Individual bit fields

415 ///

416 struct {

417 UINT32 Ibrs : 1;

418

419 /* Bits[0:0], Access Type=RW, default=None*/

420

421 /* IBRS mode active */

422 UINT32 Stibp : 1;

423

424 /* Bits[1:1], Access Type=RW, default=None*/

425

426 /* STIBP mode active */

427 UINT32 Ssbd : 1;

428

429 /* Bits[2:2], Access Type=RW, default=None*/

430

431 /* Memory Disambiguation Disable */

432 UINT32 Rsvd3 : 29;

433

434 /* Bits[31:3], Access Type=RW, default=None*/

435

436 /* reserved */

437 UINT32 Rsvd32 : 32;

438

439 /* Bits[63:32], Access Type=RW, default=None*/

440

441 /* reserved */

442

443 } Bits;

444

445 UINT32 Uint32;

446 UINT64 Uint64;

447

448 } MSR_SPEC_CTRL_REGISTER;

449

450 /**

451 Write-only virtual MSR to activate BPU flush command

452 **/

453 #define MSR_PREDICT_CMD 0x00000049

454

455 typedef union {

456 ///

457 /// Individual bit fields

458 ///

459 struct {

460 UINT32 Ibpb : 1;

461

462 /* Bits[0:0], Access Type=RW, default=None*/

463

464 /* reserved */

465 UINT32 Rsvd1 : 31;

466

467 /* Bits[31:1], Access Type=RW, default=None*/

468

469 /* reserved */

470 UINT32 Rsvd32 : 32;

471

472 /* Bits[63:32], Access Type=RW, default=None*/

473

474 /* reserved */

475

476 } Bits;

477

478 UINT32 Uint32;

479 UINT64 Uint64;

480

481 } MSR_PREDICT_CMD_REGISTER;

482 /**

483 This is a read only BIOS MSR to return the dynamic update(aka push patch) pointer stored in the PCH.

484 **/

485 #define MSR_BIOS_DYNAMIC_UPDATE_PTR 0x00000078

486 /**

487 Executing a WRMSR instruction to this MSR causes a

488 microcode update to be loaded into the processor. A processor may

489 prevent writing to this MSR when loading guest states on VM entries

490 or saving guest states on VM exits.

491 **/

492 #define MSR_BIOS_UPDT_TRIG 0x00000079

493

494 /**

495 Implements Feature Activation command. WRMSR to this address

496 activates all 'activatible' features on this thread.

497 EDX:EAX = 0x1 (SE only at this point)

498 **/

499 #define MSR_BIOS_UPGD_TRIG 0x0000007A

500

501 typedef union {

502 ///

503 /// Individual bit fields

504 ///

505 struct {

506 UINT32 Se : 1;

507

508 /* Bits[0:0], Access Type=RO_V, default=None*/

509

510 /* SE feature */

511 UINT32 Rsvd1 : 31;

512

513 /* Bits[31:1], Access Type=RO_V, default=None*/

514

515 /* Reserved */

516 UINT32 Rsvd32 : 32;

517

518 /* Bits[63:32], Access Type=RO_V, default=None*/

519

520 /* Reserved */

521

522 } Bits;

523

524 UINT32 Uint32;

525 UINT64 Uint64;

526

527 } MSR_BIOS_UPGD_TRIG_REGISTER;

528

529 /**

530 FZM Range Index register to R/W Domain|Index

531 **/

532 #define MSR_FZM_RANGE_INDEX 0x00000082

533

534 typedef union {

535 ///

536 /// Individual bit fields

537 ///

538 struct {

539 UINT32 DomainIndex : 8;

540

541 /* Bits[7:0], Access Type=RW, default=0x00000000*/

542

543 /*

544 Holds the Index of domain or special encoding

545 CONFIG = 64

546 */

547 UINT32 DomainHandle0 : 24;

548

549 /* Bits[31:8], Access Type=RW, default=0x00000000*/

550

551 /* Holds the Domain Handle */

552 UINT32 DomainHandle1 : 32;

553

554 /* Bits[63:32], Access Type=RW, default=0x00000000*/

555

556 /* Holds the Domain Handle */

557

558 } Bits;

559

560 UINT32 Uint32;

561 UINT64 Uint64;

562

563 } MSR_FZM_RANGE_INDEX_REGISTER;

564 /**

565 FZM Domain ConfigValue Read Only

566 **/

567 #define MSR_FZM_DOMAIN_CONFIG 0x00000083

568 /**

569 FZM Domain Start Address - Ready Only

570 **/

571 #define MSR_FZM_RANGE_STARTADDR 0x00000084

572 /**

573 FZM Domain End Address - Ready Only

574 **/

575 #define MSR_FZM_RANGE_ENDADDR 0x00000085

576

577 /**

578 FZM Domain Write Status - Ready Only

579 **/

580 #define MSR_FZM_RANGE_WRITESTATUS 0x00000086

581

582 typedef union {

583 ///

584 /// Individual bit fields

585 ///

586 struct {

587 UINT32 WriteStatus : 1;

588

589 /* Bits[0:0], Access Type=RO, default=None*/

590

591 /*

592 Read the write status of the specified domain in

593 Index MSR

594 */

595 UINT32 ReadStatus : 1;

596

597 /* Bits[1:1], Access Type=RO, default=None*/

598

599 /*

600 Read the read status of the specified domain in

601 Index MSR

602 */

603 UINT32 Rsvd2 : 30;

604

605 /* Bits[31:2], Access Type=RO, default=None*/

606

607 /* Reserved */

608 UINT32 Rsvd32 : 32;

609

610 /* Bits[63:32], Access Type=RO, default=None*/

611

612 /* Reserved */

613

614 } Bits;

615

616 UINT32 Uint32;

617 UINT64 Uint64;

618

619 } MSR_FZM_RANGE_WRITESTATUS_REGISTER;

620

621 /**

622 Returns the microcode update signature following the execution of CPUID.01H.

623 **/

624 #define MSR_BIOS_SIGN_ID 0x0000008B

625

626 typedef union {

627 ///

628 /// Individual bit fields

629 ///

630 struct {

631 UINT32 Rsvd0 : 32;

632

633 /* Bits[31:0], Access Type=RW, default=0x00000000*/

634

635 /* RESERVED */

636 UINT32 PatchId : 32;

637

638 /* Bits[63:32], Access Type=RW, default=0x00000000*/

639

640 /*

641 It is recommended that this field be pre-loaded

642 with 0 prior to executing CPUID. If the field

643 remains 0 following the execution of CPUID; this

644 indicates that no microcode update is loaded.

645 Any non-zero value is the microcode update

646 signature.

647 */

648

649 } Bits;

650

651 UINT32 Uint32;

652 UINT64 Uint64;

653

654 } MSR_BIOS_SIGN_ID_REGISTER;

655

656 /**

657 Returns indication per thread whether PPPE load was successful or not (partial success)

658 **/

659 #define MSR_BIOS_DEBUG 0x000000A7

660

661 typedef union {

662 ///

663 /// Individual bit fields

664 ///

665 struct {

666 UINT32 Rsvd0 : 31;

667

668 /* Bits[30:0], Access Type=RW, default=0x00000000*/

669

670 /* RESERVED */

671 UINT32 PatchRevIdStatusPppeLoadFail : 1;

672

673 /* Bits[31:31], Access Type=RW, default=0x00000000*/

674

675 /*

676 indication whether PPPE load was successful or

677 not (partial success)

678 */

679 UINT32 Rsvd32 : 32;

680

681 /* Bits[63:32], Access Type=RW, default=0x00000000*/

682

683 /* Reserved */

684

685 } Bits;

686

687 UINT32 Uint32;

688 UINT64 Uint64;

689

690 } MSR_BIOS_DEBUG_REGISTER;

691

692 /**

693 GENERAL PERFORMANCE COUNTER

694 **/

695 #define MSR_EMON_GEN_CTR0 0x000000C1

696

697 typedef union {

698 ///

699 /// Individual bit fields

700 ///

701 struct {

702 UINT32 Lower : 32;

703

704 /* Bits[31:0], Access Type=RW, default=0x00000000*/

705

706 /* Lower Half of GENERAL PERFMON CNTR */

707 UINT32 Upper : 16;

708

709 /* Bits[47:32], Access Type=RW, default=0x00000000*/

710

711 /* Upper Half of GENERAL PERFMON CNTR */

712 UINT32 Rsvd48 : 16;

713

714 /* Bits[63:48], Access Type=RO, default=None*/

715

716 /* Reserved */

717

718 } Bits;

719

720 UINT32 Uint32;

721 UINT64 Uint64;

722

723 } MSR_EMON_GEN_CTR0_REGISTER;

724

725 /**

726 GENERAL PERFORMANCE COUNTER

727 **/

728 #define MSR_EMON_GEN_CTR1 0x000000C2

729

730 typedef union {

731 ///

732 /// Individual bit fields

733 ///

734 struct {

735 UINT32 Lower : 32;

736

737 /* Bits[31:0], Access Type=RW, default=0x00000000*/

738

739 /* Lower Half of GENERAL PERFMON CNTR */

740 UINT32 Upper : 16;

741

742 /* Bits[47:32], Access Type=RW, default=0x00000000*/

743

744 /* Upper Half of GENERAL PERFMON CNTR */

745 UINT32 Rsvd48 : 16;

746

747 /* Bits[63:48], Access Type=RO, default=None*/

748

749 /* Reserved */

750

751 } Bits;

752

753 UINT32 Uint32;

754 UINT64 Uint64;

755

756 } MSR_EMON_GEN_CTR1_REGISTER;

757

758 /**

759 GENERAL PERFORMANCE COUNTER

760 **/

761 #define MSR_EMON_GEN_CTR2 0x000000C3

762

763 typedef union {

764 ///

765 /// Individual bit fields

766 ///

767 struct {

768 UINT32 Lower : 32;

769

770 /* Bits[31:0], Access Type=RW, default=0x00000000*/

771

772 /* Lower Half of GENERAL PERFMON CNTR */

773 UINT32 Upper : 16;

774

775 /* Bits[47:32], Access Type=RW, default=0x00000000*/

776

777 /* Upper Half of GENERAL PERFMON CNTR */

778 UINT32 Rsvd48 : 16;

779

780 /* Bits[63:48], Access Type=RO, default=None*/

781

782 /* Reserved */

783

784 } Bits;

785

786 UINT32 Uint32;

787 UINT64 Uint64;

788

789 } MSR_EMON_GEN_CTR2_REGISTER;

790

791 /**

792 GENERAL PERFORMANCE COUNTER

793 **/

794 #define MSR_EMON_GEN_CTR3 0x000000C4

795

796 typedef union {

797 ///

798 /// Individual bit fields

799 ///

800 struct {

801 UINT32 Lower : 32;

802

803 /* Bits[31:0], Access Type=RW, default=0x00000000*/

804

805 /* Lower Half of GENERAL PERFMON CNTR */

806 UINT32 Upper : 16;

807

808 /* Bits[47:32], Access Type=RW, default=0x00000000*/

809

810 /* Upper Half of GENERAL PERFMON CNTR */

811 UINT32 Rsvd48 : 16;

812

813 /* Bits[63:48], Access Type=RO, default=None*/

814

815 /* Reserved */

816

817 } Bits;

818

819 UINT32 Uint32;

820 UINT64 Uint64;

821

822 } MSR_EMON_GEN_CTR3_REGISTER;

823

824 /**

825 GENERAL PERFORMANCE COUNTER

826 **/

827 #define MSR_EMON_GEN_CTR4 0x000000C5

828

829 typedef union {

830 ///

831 /// Individual bit fields

832 ///

833 struct {

834 UINT32 Lower : 32;

835

836 /* Bits[31:0], Access Type=RW, default=0x00000000*/

837

838 /* Lower Half of GENERAL PERFMON CNTR */

839 UINT32 Upper : 16;

840

841 /* Bits[47:32], Access Type=RW, default=0x00000000*/

842

843 /* Upper Half of GENERAL PERFMON CNTR */

844 UINT32 Rsvd48 : 16;

845

846 /* Bits[63:48], Access Type=RO, default=None*/

847

848 /* Reserved */

849

850 } Bits;

851

852 UINT32 Uint32;

853 UINT64 Uint64;

854

855 } MSR_EMON_GEN_CTR4_REGISTER;

856

857 /**

858 GENERAL PERFORMANCE COUNTER

859 **/

860 #define MSR_EMON_GEN_CTR5 0x000000C6

861

862 typedef union {

863 ///

864 /// Individual bit fields

865 ///

866 struct {

867 UINT32 Lower : 32;

868

869 /* Bits[31:0], Access Type=RW, default=0x00000000*/

870

871 /* Lower Half of GENERAL PERFMON CNTR */

872 UINT32 Upper : 16;

873

874 /* Bits[47:32], Access Type=RW, default=0x00000000*/

875

876 /* Upper Half of GENERAL PERFMON CNTR */

877 UINT32 Rsvd48 : 16;

878

879 /* Bits[63:48], Access Type=RO, default=None*/

880

881 /* Reserved */

882

883 } Bits;

884

885 UINT32 Uint32;

886 UINT64 Uint64;

887

888 } MSR_EMON_GEN_CTR5_REGISTER;

889

890 /**

891 GENERAL PERFORMANCE COUNTER

892 **/

893 #define MSR_EMON_GEN_CTR6 0x000000C7

894

895 typedef union {

896 ///

897 /// Individual bit fields

898 ///

899 struct {

900 UINT32 Lower : 32;

901

902 /* Bits[31:0], Access Type=RW, default=0x00000000*/

903

904 /* Lower Half of GENERAL PERFMON CNTR */

905 UINT32 Upper : 16;

906

907 /* Bits[47:32], Access Type=RW, default=0x00000000*/

908

909 /* Upper Half of GENERAL PERFMON CNTR */

910 UINT32 Rsvd48 : 16;

911

912 /* Bits[63:48], Access Type=RO, default=None*/

913

914 /* Reserved */

915

916 } Bits;

917

918 UINT32 Uint32;

919 UINT64 Uint64;

920

921 } MSR_EMON_GEN_CTR6_REGISTER;

922

923 /**

924 GENERAL PERFORMANCE COUNTER

925 **/

926 #define MSR_EMON_GEN_CTR7 0x000000C8

927

928 typedef union {

929 ///

930 /// Individual bit fields

931 ///

932 struct {

933 UINT32 Lower : 32;

934

935 /* Bits[31:0], Access Type=RW, default=0x00000000*/

936

937 /* Lower Half of GENERAL PERFMON CNTR */

938 UINT32 Upper : 16;

939

940 /* Bits[47:32], Access Type=RW, default=0x00000000*/

941

942 /* Upper Half of GENERAL PERFMON CNTR */

943 UINT32 Rsvd48 : 16;

944

945 /* Bits[63:48], Access Type=RO, default=None*/

946

947 /* Reserved */

948

949 } Bits;

950

951 UINT32 Uint32;

952 UINT64 Uint64;

953

954 } MSR_EMON_GEN_CTR7_REGISTER;

955

956 /**

957 architectural MSR to enumerate model-specific features

958 **/

959 #define MSR_CORE_CAPABILITIES 0x000000CF

960

961 typedef union {

962 ///

963 /// Individual bit fields

964 ///

965 struct {

966 UINT32 StlbQosSupported : 1;

967

968 /* Bits[0:0], Access Type=RO_V, default=0x00000000*/

969

970 /*

971 Indicates that processor supports STLB QoS

972 functionality

973 */

974 UINT32 RarSupported : 1;

975

976 /* Bits[1:1], Access Type=RW, default=0x00000000*/

977

978 /*

979 Indicates that processor supports Remote Action

980 Request functionality

981 */

982 UINT32 FusaSupported : 1;

983

984 /* Bits[2:2], Access Type=RW, default=0x00000000*/

985

986 /*

987 Indicates that processor supports Functional

988 Safety

989 */

990 UINT32 RsmInCpl0Only : 1;

991

992 /* Bits[3:3], Access Type=RW, default=0x00000000*/

993

994 /*

995 Indicates that RSM will only be allowed in CPL0

996 and #GP for all non-CPL0 privelege levels

997 */

998 UINT32 VmdosSupported : 1;

999

1000 /* Bits[4:4], Access Type=RW, default=0x00000000*/

1001

1002 /* Indicates that VM-DOS feature is supported */

1003 UINT32 SplitLockDisableSupported : 1;

1004

1005 /* Bits[5:5], Access Type=RW, default=0x00000001*/

1006

1007 /*

1008 Indicates that there is core support for #AC on

1009 split lock detection feature

1010 */

1011 UINT32 SnoopFilterQosSupported : 1;

1012

1013 /* Bits[6:6], Access Type=RW, default=0x00000000*/

1014

1015 /*

1016 Indicates that snoop filter quality of service

1017 MSRs are supported on this core. This is based

1018 upon the existence of a non-inclusive cache and

1019 the L2 / MLC QoS feature supported

1020 */

1021 UINT32 Rsvd7 : 25;

1022

1023 /* Bits[31:7], Access Type=RO, default=None*/

1024

1025 /* Reserved */

1026 UINT32 Rsvd32 : 32;

1027

1028 /* Bits[63:32], Access Type=RO, default=None*/

1029

1030 /* Reserved */

1031

1032 } Bits;

1033

1034 UINT32 Uint32;

1035 UINT64 Uint64;

1036

1037 } MSR_CORE_CAPABILITIES_REGISTER;

1038 /**

1039 Maximum Qualified Performance Clock Counter

1040 **/

1041 #define MSR_MLC_MCNT_COUNTER 0x000000E7

1042 /**

1043 Actual Performance Clock Counter

1044 **/

1045 #define MSR_MLC_ACNT_COUNTER 0x000000E8

1046

1047 /**

1048 MTRR Capabilities MSR

1049 **/

1050 #define MSR_MTRRCAP 0x000000FE

1051

1052 typedef union {

1053 ///

1054 /// Individual bit fields

1055 ///

1056 struct {

1057 UINT32 Vcnt : 8;

1058

1059 /* Bits[7:0], Access Type=RW, default=0x00000000*/

1060

1061 /* Number of variable range registers */

1062 UINT32 Fix : 1;

1063

1064 /* Bits[8:8], Access Type=RW, default=0x00000000*/

1065

1066 /* Fixed range registers supported if set */

1067 UINT32 Rsvd9 : 1;

1068

1069 /* Bits[9:9], Access Type=RW, default=0x00000000*/

1070

1071 /* Reserved */

1072 UINT32 Wc : 1;

1073

1074 /* Bits[10:10], Access Type=RW, default=0x00000000*/

1075

1076 /* Write-Combining memory type supported if set. */

1077 UINT32 Smrr : 1;

1078

1079 /* Bits[11:11], Access Type=RW, default=0x00000000*/

1080

1081 /* SMRRs are supported if set. */

1082 UINT32 Prmrr : 1;

1083

1084 /* Bits[12:12], Access Type=RW, default=0x00000000*/

1085

1086 /* PRMRR MSRs are supported. */

1087 UINT32 Smrr2 : 1;

1088

1089 /* Bits[13:13], Access Type=RW, default=0x00000000*/

1090

1091 /* SMRR2 is supported if set. */

1092 UINT32 SmrrLock : 1;

1093

1094 /* Bits[14:14], Access Type=RW, default=0x00000000*/

1095

1096 /* SMRRs can be locked if set. */

1097 UINT32 Rsvd15 : 17;

1098

1099 /* Bits[31:15], Access Type=RW, default=0x00000000*/

1100

1101 /* Reserved */

1102

1103 } Bits;

1104

1105 UINT32 Uint32;

1106 UINT64 Uint64;

1107

1108 } MSR_MTRRCAP_REGISTER;

1109

1110 /**

1111 Write-only virtual MSR to activate DCU flush command

1112 **/

1113 #define MSR_DCU_FLUSH_CMD 0x0000010B

1114

1115 typedef union {

1116 ///

1117 /// Individual bit fields

1118 ///

1119 struct {

1120 UINT32 DcuFlush : 1;

1121

1122 /* Bits[0:0], Access Type=RW, default=None*/

1123

1124 /* reserved */

1125 UINT32 Rsvd1 : 31;

1126

1127 /* Bits[31:1], Access Type=RW, default=None*/

1128

1129 /* reserved */

1130 UINT32 Rsvd32 : 32;

1131

1132 /* Bits[63:32], Access Type=RW, default=None*/

1133

1134 /* reserved */

1135

1136 } Bits;

1137

1138 UINT32 Uint32;

1139 UINT64 Uint64;

1140

1141 } MSR_DCU_FLUSH_CMD_REGISTER;

1142 /**

1143 SYSENTER_CS_MSR

1144 **/

1145 #define MSR_SYSENTER_CS 0x00000174

1146 /**

1147 SYSENTER ESP Linear Address

1148 **/

1149 #define MSR_SYSENTER_ESP 0x00000175

1150 /**

1151 SYSENTER ESI Linear Address

1152 **/

1153 #define MSR_SYSENTER_EIP 0x00000176

1154

1155 /**

1156 Machine Check Capabilities register

1157 **/

1158 #define MSR_MCG_CAP 0x00000179

1159

1160 typedef union {

1161 ///

1162 /// Individual bit fields

1163 ///

1164 struct {

1165 UINT32 Count : 8;

1166

1167 /* Bits[7:0], Access Type=RO_V, default=None*/

1168

1169 /*

1170 Indicates the number of hardware unit error-

1171 reporting banks available in a particular

1172 processor implementation.

1173 */

1174 UINT32 McgCtlP : 1;

1175

1176 /* Bits[8:8], Access Type=RO_V, default=None*/

1177

1178 /*

1179 Indicates that the processor implements the

1180 IA32_MCG_CTL MSR when set.

1181 */

1182 UINT32 McgExtP : 1;

1183

1184 /* Bits[9:9], Access Type=RO_V, default=None*/

1185

1186 /*

1187 Indicates that the processor implements the

1188 extended machine-check state registers found

1189 starting at MSR address 180H; these registers

1190 are absent when clear.

1191 */

1192 UINT32 McgExtErrorCntSig : 1;

1193

1194 /* Bits[10:10], Access Type=RO_V, default=None*/

1195

1196 /* Support for corrected MC error event is present. */

1197 UINT32 OvercapacitySig : 1;

1198

1199 /* Bits[11:11], Access Type=RO_V, default=None*/

1200

1201 /*

1202 Threshold-based error status register are

1203 present if this bit is set.

1204 */

1205 UINT32 Rsvd12 : 4;

1206

1207 /* Bits[15:12], Access Type=RO_V, default=None*/

1208

1209 /* Reserved */

1210 UINT32 McgExtCnt : 8;

1211

1212 /* Bits[23:16], Access Type=RO_V, default=None*/

1213

1214 /*

1215 Indicates the number of extended machinecheck

1216 state registers present. This field is

1217 meaningful only when the MCG_EXT_P flag is set.

1218 */

1219 UINT32 Gcm : 1;

1220

1221 /* Bits[24:24], Access Type=RO_V, default=None*/

1222

1223 /*

1224 The processor supports software error recovery

1225 if this bit is set.

1226 */

1227 UINT32 EnhancedMca : 1;

1228

1229 /* Bits[25:25], Access Type=RO_V, default=None*/

1230

1231 /* Set if Enhanced MCA is enabled */

1232 UINT32 ErrLog : 1;

1233

1234 /* Bits[26:26], Access Type=RO_V, default=None*/

1235

1236 /*

1237 When set, EXTENDED_MCG_PTR MSR (0x793) is

1238 available

1239 */

1240 UINT32 Lmce : 1;

1241

1242 /* Bits[27:27], Access Type=RO_V, default=None*/

1243

1244 /* Set if Local Machine Check is Enabled */

1245 UINT32 Rsvd28 : 4;

1246

1247 /* Bits[31:28], Access Type=RO_V, default=None*/

1248

1249 /* Reserved */

1250 UINT32 Rsvd32 : 32;

1251

1252 /* Bits[63:32], Access Type=RO, default=None*/

1253

1254 /* Reserved */

1255

1256 } Bits;

1257

1258 UINT32 Uint32;

1259 UINT64 Uint64;

1260

1261 } MSR_MCG_CAP_REGISTER;

1262

1263 /**

1264 Global Machine Check Status

1265 **/

1266 #define MSR_MCG_STATUS 0x0000017A

1267

1268 typedef union {

1269 ///

1270 /// Individual bit fields

1271 ///

1272 struct {

1273 UINT32 Ripv : 1;

1274

1275 /* Bits[0:0], Access Type=RW, default=None*/

1276

1277 /* Restart IP valid */

1278 UINT32 Eipv : 1;

1279

1280 /* Bits[1:1], Access Type=RW, default=None*/

1281

1282 /* Error IP valid */

1283 UINT32 Mcip : 1;

1284

1285 /* Bits[2:2], Access Type=RW, default=None*/

1286

1287 /* Machine Check In Progress. */

1288 UINT32 Lmce : 1;

1289

1290 /* Bits[3:3], Access Type=RW, default=None*/

1291

1292 /*

1293 When this bit is set, it indicates to the OS

1294 that the error logged was NOT broadcast

1295 (localized). When this bit is clear, it

1296 indicates to the OS that the error was broadcast

1297 to all threads.

1298 */

1299 UINT32 Rsvd4 : 28;

1300

1301 /* Bits[31:4], Access Type=RW, default=None*/

1302

1303 /* Reserved */

1304

1305 } Bits;

1306

1307 UINT32 Uint32;

1308 UINT64 Uint64;

1309

1310 } MSR_MCG_STATUS_REGISTER;

1311

1312 /**

1313 This is a PerfMon register that is used to control the behavior

1314 of an associated performance counter and to selecting events for that counter.

1315 **/

1316 #define MSR_PERMON_EVNTSEL_CNTR0 0x00000186

1317

1318 typedef union {

1319 ///

1320 /// Individual bit fields

1321 ///

1322 struct {

1323 UINT32 EventSelect : 8;

1324

1325 /* Bits[7:0], Access Type=RW, default=None*/

1326

1327 /*

1328 Selects the event logic unit to detect certain

1329 microarchitectural conditions

1330 */

1331 UINT32 UnitMask : 8;

1332

1333 /* Bits[15:8], Access Type=RW, default=None*/

1334

1335 /*

1336 Further qualifies the event logic unit selected

1337 in the event select field to detect a specific

1338 microarchitectural condition.

1339 */

1340 UINT32 Usr : 1;

1341

1342 /* Bits[16:16], Access Type=RW, default=None*/

1343

1344 /*

1345 This bit specifies that events are counted only

1346 when the processor is operating at current

1347 privilege levels 1, 2 or 3 (CPL != 0). This flag

1348 can be used in conjunction with the OS flag.

1349 */

1350 UINT32 Os : 1;

1351

1352 /* Bits[17:17], Access Type=RW, default=None*/

1353

1354 /*

1355 Specifies that events are counted only when the

1356 processor is operating at current privilege

1357 level 0 (CPL=0). This flag can be used in

1358 conjunction with the USR flag.

1359 */

1360 UINT32 EdgeDetect : 1;

1361

1362 /* Bits[18:18], Access Type=RW, default=0x00000000*/

1363

1364 /*

1365 Enables (when set) edge detection of events. The

1366 processor counts the number of deasserted to

1367 asserted transitions of any condition that can

1368 be expressed by the other fields. The mechanism

1369 is limited in that it does not permit back-to-

1370 back assertions to be distinguished.

1371 */

1372 UINT32 Rsvd19 : 1;

1373

1374 /* Bits[19:19], Access Type=RO, default=None*/

1375

1376 /* Reserved */

1377 UINT32 Pmi : 1;

1378

1379 /* Bits[20:20], Access Type=RW, default=0x00000000*/

1380

1381 /*

1382 APIC interrupt enable. When set, the processor

1383 generates an exception through its local APIC on

1384 counter overflow for this counter's thread.

1385 */

1386 UINT32 MythrAllthr : 1;

1387

1388 /* Bits[21:21], Access Type=RW, default=None*/

1389

1390 /*

1391 When set to 1, it enables counting the

1392 associated event conditions occurring across all

1393 logical processors sharing a processor core.

1394 When set to 0, the counter only increments the

1395 associated event conditions occurring in the

1396 logical processor which programmed the MSR.

1397 */

1398 UINT32 EnableBit : 1;

1399

1400 /* Bits[22:22], Access Type=RW, default=0x00000000*/

1401

1402 /*

1403 Enables the corresponding performance counter to

1404 commence counting when this bit is set

1405 */

1406 UINT32 Invert : 1;

1407

1408 /* Bits[23:23], Access Type=RW, default=0x00000000*/

1409

1410 /*

1411 This bit indicates how the CMASK/Threshold field

1412 will be compared to the incoming event. When

1413 '0', the comparison that will be done is:

1414 threshold >= event. When set to '1', the

1415 comparison that will be done is inverted from

1416 the case where this bit is set to '0': threshold

1417 less than event.

1418 */

1419 UINT32 Threshold : 8;

1420

1421 /* Bits[31:24], Access Type=RW, default=0x00000000*/

1422

1423 /*

1424 When CMASK is not zero, the corresponding

1425 performance counter increments each cycle if the

1426 event count is greater than or equal to the

1427 CMASK.

1428 */

1429 UINT32 HleOnly : 1;

1430

1431 /* Bits[32:32], Access Type=RW, default=0x00000000*/

1432

1433 /*

1434 Setting this bit to '1 restricts the counter to

1435 only incrementing for the programmed event

1436 during speculative and non-speculative HLE mode.

1437 This bit will treated as reserved bit if HLE is

1438 fuse disabled.

1439 */

1440 UINT32 HleCheckpointEn : 1;

1441

1442 /* Bits[33:33], Access Type=RW, default=0x00000000*/

1443

1444 /*

1445 Setting this bit to '1 enables the event

1446 programmed into the counter to only non-aborted

1447 HLE execution i.e. the event count will exclude

1448 or not count events that occurred on an aborted

1449 HLE path. Only counter 2 supports this

1450 capability. This bit will treated as reserved

1451 bit if HLE is fuse disabled.

1452 */

1453 UINT32 AdaptiveRecord : 1;

1454

1455 /* Bits[34:34], Access Type=RW, default=0x00000000*/

1456

1457 /*

1458 for Adaptive pebs feature in SNC if

1459 ADAPTIVE_RECORD bit is set, Ucode will consider

1460 MSR_PEBS_DATA_CFG and emit the requested fields

1461 */

1462 UINT32 Rsvd35 : 27;

1463

1464 /* Bits[61:35], Access Type=RO, default=None*/

1465

1466 /* Reserved */

1467 UINT32 Forceubrkpt : 1;

1468

1469 /* Bits[62:62], Access Type=RW, default=None*/

1470

1471 /*

1472 When set a MicroBreakPoint occurs each time a

1473 none zero Event enters the counter.

1474 */

1475 UINT32 Rsvd63 : 1;

1476

1477 /* Bits[63:63], Access Type=RO, default=None*/

1478

1479 /* Reserved */

1480

1481 } Bits;

1482

1483 UINT32 Uint32;

1484 UINT64 Uint64;

1485

1486 } MSR_PERMON_EVNTSEL_CNTR0_REGISTER;

1487

1488 /**

1489 This is a PerfMon register that is used to control the behavior

1490 of an associated performance counter and to selecting events for that counter.

1491 **/

1492 #define MSR_PERMON_EVNTSEL_CNTR1 0x00000187

1493

1494 typedef union {

1495 ///

1496 /// Individual bit fields

1497 ///

1498 struct {

1499 UINT32 EventSelect : 8;

1500

1501 /* Bits[7:0], Access Type=RW, default=None*/

1502

1503 /*

1504 Selects the event logic unit to detect certain

1505 microarchitectural conditions

1506 */

1507 UINT32 UnitMask : 8;

1508

1509 /* Bits[15:8], Access Type=RW, default=None*/

1510

1511 /*

1512 Further qualifies the event logic unit selected

1513 in the event select field to detect a specific

1514 microarchitectural condition.

1515 */

1516 UINT32 Usr : 1;

1517

1518 /* Bits[16:16], Access Type=RW, default=None*/

1519

1520 /*

1521 This bit specifies that events are counted only

1522 when the processor is operating at current

1523 privilege levels 1, 2 or 3 (CPL != 0). This flag

1524 can be used in conjunction with the OS flag.

1525 */

1526 UINT32 Os : 1;

1527

1528 /* Bits[17:17], Access Type=RW, default=None*/

1529

1530 /*

1531 Specifies that events are counted only when the

1532 processor is operating at current privilege

1533 level 0 (CPL=0). This flag can be used in

1534 conjunction with the USR flag.

1535 */

1536 UINT32 EdgeDetect : 1;

1537

1538 /* Bits[18:18], Access Type=RW, default=0x00000000*/

1539

1540 /*

1541 Enables (when set) edge detection of events. The

1542 processor counts the number of deasserted to

1543 asserted transitions of any condition that can

1544 be expressed by the other fields. The mechanism

1545 is limited in that it does not permit back-to-

1546 back assertions to be distinguished.

1547 */

1548 UINT32 Rsvd19 : 1;

1549

1550 /* Bits[19:19], Access Type=RO, default=None*/

1551

1552 /* Reserved */

1553 UINT32 Pmi : 1;

1554

1555 /* Bits[20:20], Access Type=RW, default=0x00000000*/

1556

1557 /*

1558 APIC interrupt enable. When set, the processor

1559 generates an exception through its local APIC on

1560 counter overflow for this counter's thread.

1561 */

1562 UINT32 MythrAllthr : 1;

1563

1564 /* Bits[21:21], Access Type=RW, default=None*/

1565

1566 /*

1567 When set to 1, it enables counting the

1568 associated event conditions occurring across all

1569 logical processors sharing a processor core.

1570 When set to 0, the counter only increments the

1571 associated event conditions occurring in the

1572 logical processor which programmed the MSR.

1573 */

1574 UINT32 EnableBit : 1;

1575

1576 /* Bits[22:22], Access Type=RW, default=0x00000000*/

1577

1578 /*

1579 Enables the corresponding performance counter to

1580 commence counting when this bit is set

1581 */

1582 UINT32 Invert : 1;

1583

1584 /* Bits[23:23], Access Type=RW, default=0x00000000*/

1585

1586 /*

1587 This bit indicates how the CMASK/Threshold field

1588 will be compared to the incoming event. When

1589 '0', the comparison that will be done is:

1590 threshold >= event. When set to '1', the

1591 comparison that will be done is inverted from

1592 the case where this bit is set to '0': threshold

1593 less than event.

1594 */

1595 UINT32 Threshold : 8;

1596

1597 /* Bits[31:24], Access Type=RW, default=0x00000000*/

1598

1599 /*

1600 When CMASK is not zero, the corresponding

1601 performance counter increments each cycle if the

1602 event count is greater than or equal to the

1603 CMASK.

1604 */

1605 UINT32 HleOnly : 1;

1606

1607 /* Bits[32:32], Access Type=RW, default=0x00000000*/

1608

1609 /*

1610 Setting this bit to '1 restricts the counter to

1611 only incrementing for the programmed event

1612 during speculative and non-speculative HLE mode.

1613 This bit will treated as reserved bit if HLE is

1614 fuse disabled.

1615 */

1616 UINT32 HleCheckpointEn : 1;

1617

1618 /* Bits[33:33], Access Type=RW, default=0x00000000*/

1619

1620 /*

1621 Setting this bit to '1 enables the event

1622 programmed into the counter to only non-aborted

1623 HLE execution i.e. the event count will exclude

1624 or not count events that occurred on an aborted

1625 HLE path. Only counter 2 supports this

1626 capability. This bit will treated as reserved

1627 bit if HLE is fuse disabled.

1628 */

1629 UINT32 AdaptiveRecord : 1;

1630

1631 /* Bits[34:34], Access Type=RW, default=0x00000000*/

1632

1633 /*

1634 for Adaptive pebs feature in SNC if

1635 ADAPTIVE_RECORD bit is set, Ucode will consider

1636 MSR_PEBS_DATA_CFG and emit the requested fields

1637 */

1638 UINT32 Rsvd35 : 27;

1639

1640 /* Bits[61:35], Access Type=RO, default=None*/

1641

1642 /* Reserved */

1643 UINT32 Forceubrkpt : 1;

1644

1645 /* Bits[62:62], Access Type=RW, default=None*/

1646

1647 /*

1648 When set a MicroBreakPoint occurs each time a

1649 none zero Event enters the counter.

1650 */

1651 UINT32 Rsvd63 : 1;

1652

1653 /* Bits[63:63], Access Type=RO, default=None*/

1654

1655 /* Reserved */

1656

1657 } Bits;

1658

1659 UINT32 Uint32;

1660 UINT64 Uint64;

1661

1662 } MSR_PERMON_EVNTSEL_CNTR1_REGISTER;

1663

1664 /**

1665 This is a PerfMon register that is used to control the behavior

1666 of an associated performance counter and to selecting events for that counter.

1667 **/

1668 #define MSR_PERMON_EVNTSEL_CNTR2 0x00000188

1669

1670 typedef union {

1671 ///

1672 /// Individual bit fields

1673 ///

1674 struct {

1675 UINT32 EventSelect : 8;

1676

1677 /* Bits[7:0], Access Type=RW, default=None*/

1678

1679 /*

1680 Selects the event logic unit to detect certain

1681 microarchitectural conditions

1682 */

1683 UINT32 UnitMask : 8;

1684

1685 /* Bits[15:8], Access Type=RW, default=None*/

1686

1687 /*

1688 Further qualifies the event logic unit selected

1689 in the event select field to detect a specific

1690 microarchitectural condition.

1691 */

1692 UINT32 Usr : 1;

1693

1694 /* Bits[16:16], Access Type=RW, default=None*/

1695

1696 /*

1697 This bit specifies that events are counted only

1698 when the processor is operating at current

1699 privilege levels 1, 2 or 3 (CPL != 0). This flag

1700 can be used in conjunction with the OS flag.

1701 */

1702 UINT32 Os : 1;

1703

1704 /* Bits[17:17], Access Type=RW, default=None*/

1705

1706 /*

1707 Specifies that events are counted only when the

1708 processor is operating at current privilege

1709 level 0 (CPL=0). This flag can be used in

1710 conjunction with the USR flag.

1711 */

1712 UINT32 EdgeDetect : 1;

1713

1714 /* Bits[18:18], Access Type=RW, default=0x00000000*/

1715

1716 /*

1717 Enables (when set) edge detection of events. The

1718 processor counts the number of deasserted to

1719 asserted transitions of any condition that can

1720 be expressed by the other fields. The mechanism

1721 is limited in that it does not permit back-to-

1722 back assertions to be distinguished.

1723 */

1724 UINT32 Rsvd19 : 1;

1725

1726 /* Bits[19:19], Access Type=RO, default=None*/

1727

1728 /* Reserved */

1729 UINT32 Pmi : 1;

1730

1731 /* Bits[20:20], Access Type=RW, default=0x00000000*/

1732

1733 /*

1734 APIC interrupt enable. When set, the processor

1735 generates an exception through its local APIC on

1736 counter overflow for this counter's thread.

1737 */

1738 UINT32 MythrAllthr : 1;

1739

1740 /* Bits[21:21], Access Type=RW, default=None*/

1741

1742 /*

1743 When set to 1, it enables counting the

1744 associated event conditions occurring across all

1745 logical processors sharing a processor core.

1746 When set to 0, the counter only increments the

1747 associated event conditions occurring in the

1748 logical processor which programmed the MSR.

1749 */

1750 UINT32 EnableBit : 1;

1751

1752 /* Bits[22:22], Access Type=RW, default=0x00000000*/

1753

1754 /*

1755 Enables the corresponding performance counter to

1756 commence counting when this bit is set

1757 */

1758 UINT32 Invert : 1;

1759

1760 /* Bits[23:23], Access Type=RW, default=0x00000000*/

1761

1762 /*

1763 This bit indicates how the CMASK/Threshold field

1764 will be compared to the incoming event. When

1765 '0', the comparison that will be done is:

1766 threshold >= event. When set to '1', the

1767 comparison that will be done is inverted from

1768 the case where this bit is set to '0': threshold

1769 less than event.

1770 */

1771 UINT32 Threshold : 8;

1772

1773 /* Bits[31:24], Access Type=RW, default=0x00000000*/

1774

1775 /*

1776 When CMASK is not zero, the corresponding

1777 performance counter increments each cycle if the

1778 event count is greater than or equal to the

1779 CMASK.

1780 */

1781 UINT32 HleOnly : 1;

1782

1783 /* Bits[32:32], Access Type=RW, default=0x00000000*/

1784

1785 /*

1786 Setting this bit to '1 restricts the counter to

1787 only incrementing for the programmed event

1788 during speculative and non-speculative HLE mode.

1789 This bit will treated as reserved bit if HLE is

1790 fuse disabled.

1791 */

1792 UINT32 HleCheckpointEn : 1;

1793

1794 /* Bits[33:33], Access Type=RW, default=0x00000000*/

1795

1796 /*

1797 Setting this bit to '1 enables the event

1798 programmed into the counter to only non-aborted

1799 HLE execution i.e. the event count will exclude

1800 or not count events that occurred on an aborted

1801 HLE path. Only counter 2 supports this

1802 capability. This bit will treated as reserved

1803 bit if HLE is fuse disabled.

1804 */

1805 UINT32 AdaptiveRecord : 1;

1806

1807 /* Bits[34:34], Access Type=RW, default=0x00000000*/

1808

1809 /*

1810 for Adaptive pebs feature in SNC if

1811 ADAPTIVE_RECORD bit is set, Ucode will consider

1812 MSR_PEBS_DATA_CFG and emit the requested fields

1813 */

1814 UINT32 Rsvd35 : 27;

1815

1816 /* Bits[61:35], Access Type=RO, default=None*/

1817

1818 /* Reserved */

1819 UINT32 Forceubrkpt : 1;

1820

1821 /* Bits[62:62], Access Type=RW, default=None*/

1822

1823 /*

1824 When set a MicroBreakPoint occurs each time a

1825 none zero Event enters the counter.

1826 */

1827 UINT32 Rsvd63 : 1;

1828

1829 /* Bits[63:63], Access Type=RO, default=None*/

1830

1831 /* Reserved */

1832

1833 } Bits;

1834

1835 UINT32 Uint32;

1836 UINT64 Uint64;

1837

1838 } MSR_PERMON_EVNTSEL_CNTR2_REGISTER;

1839

1840 /**

1841 This is a PerfMon register that is used to control the behavior

1842 of an associated performance counter and to selecting events for that counter.

1843 **/

1844 #define MSR_PERMON_EVNTSEL_CNTR3 0x00000189

1845

1846 typedef union {

1847 ///

1848 /// Individual bit fields

1849 ///

1850 struct {

1851 UINT32 EventSelect : 8;

1852

1853 /* Bits[7:0], Access Type=RW, default=None*/

1854

1855 /*

1856 Selects the event logic unit to detect certain

1857 microarchitectural conditions

1858 */

1859 UINT32 UnitMask : 8;

1860

1861 /* Bits[15:8], Access Type=RW, default=None*/

1862

1863 /*

1864 Further qualifies the event logic unit selected

1865 in the event select field to detect a specific

1866 microarchitectural condition.

1867 */

1868 UINT32 Usr : 1;

1869

1870 /* Bits[16:16], Access Type=RW, default=None*/

1871

1872 /*

1873 This bit specifies that events are counted only

1874 when the processor is operating at current

1875 privilege levels 1, 2 or 3 (CPL != 0). This flag

1876 can be used in conjunction with the OS flag.

1877 */

1878 UINT32 Os : 1;

1879

1880 /* Bits[17:17], Access Type=RW, default=None*/

1881

1882 /*

1883 Specifies that events are counted only when the

1884 processor is operating at current privilege

1885 level 0 (CPL=0). This flag can be used in

1886 conjunction with the USR flag.

1887 */

1888 UINT32 EdgeDetect : 1;

1889

1890 /* Bits[18:18], Access Type=RW, default=0x00000000*/

1891

1892 /*

1893 Enables (when set) edge detection of events. The

1894 processor counts the number of deasserted to

1895 asserted transitions of any condition that can

1896 be expressed by the other fields. The mechanism

1897 is limited in that it does not permit back-to-

1898 back assertions to be distinguished.

1899 */

1900 UINT32 Rsvd19 : 1;

1901

1902 /* Bits[19:19], Access Type=RO, default=None*/

1903

1904 /* Reserved */

1905 UINT32 Pmi : 1;

1906

1907 /* Bits[20:20], Access Type=RW, default=0x00000000*/

1908

1909 /*

1910 APIC interrupt enable. When set, the processor

1911 generates an exception through its local APIC on

1912 counter overflow for this counter's thread.

1913 */

1914 UINT32 MythrAllthr : 1;

1915

1916 /* Bits[21:21], Access Type=RW, default=None*/

1917

1918 /*

1919 When set to 1, it enables counting the

1920 associated event conditions occurring across all

1921 logical processors sharing a processor core.

1922 When set to 0, the counter only increments the

1923 associated event conditions occurring in the

1924 logical processor which programmed the MSR.

1925 */

1926 UINT32 EnableBit : 1;

1927

1928 /* Bits[22:22], Access Type=RW, default=0x00000000*/

1929

1930 /*

1931 Enables the corresponding performance counter to

1932 commence counting when this bit is set

1933 */

1934 UINT32 Invert : 1;

1935

1936 /* Bits[23:23], Access Type=RW, default=0x00000000*/

1937

1938 /*

1939 This bit indicates how the CMASK/Threshold field

1940 will be compared to the incoming event. When

1941 '0', the comparison that will be done is:

1942 threshold >= event. When set to '1', the

1943 comparison that will be done is inverted from

1944 the case where this bit is set to '0': threshold

1945 less than event.

1946 */

1947 UINT32 Threshold : 8;

1948

1949 /* Bits[31:24], Access Type=RW, default=0x00000000*/

1950

1951 /*

1952 When CMASK is not zero, the corresponding

1953 performance counter increments each cycle if the

1954 event count is greater than or equal to the

1955 CMASK.

1956 */

1957 UINT32 HleOnly : 1;

1958

1959 /* Bits[32:32], Access Type=RW, default=0x00000000*/

1960

1961 /*

1962 Setting this bit to '1 restricts the counter to

1963 only incrementing for the programmed event

1964 during speculative and non-speculative HLE mode.

1965 This bit will treated as reserved bit if HLE is

1966 fuse disabled.

1967 */

1968 UINT32 HleCheckpointEn : 1;

1969

1970 /* Bits[33:33], Access Type=RW, default=0x00000000*/

1971

1972 /*

1973 Setting this bit to '1 enables the event

1974 programmed into the counter to only non-aborted

1975 HLE execution i.e. the event count will exclude

1976 or not count events that occurred on an aborted

1977 HLE path. Only counter 2 supports this

1978 capability. This bit will treated as reserved

1979 bit if HLE is fuse disabled.

1980 */

1981 UINT32 AdaptiveRecord : 1;

1982

1983 /* Bits[34:34], Access Type=RW, default=0x00000000*/

1984

1985 /*

1986 for Adaptive pebs feature in SNC if

1987 ADAPTIVE_RECORD bit is set, Ucode will consider

1988 MSR_PEBS_DATA_CFG and emit the requested fields

1989 */

1990 UINT32 Rsvd35 : 27;

1991

1992 /* Bits[61:35], Access Type=RO, default=None*/

1993

1994 /* Reserved */

1995 UINT32 Forceubrkpt : 1;

1996

1997 /* Bits[62:62], Access Type=RW, default=None*/

1998

1999 /*

2000 When set a MicroBreakPoint occurs each time a

2001 none zero Event enters the counter.

2002 */

2003 UINT32 Rsvd63 : 1;

2004

2005 /* Bits[63:63], Access Type=RO, default=None*/

2006

2007 /* Reserved */

2008

2009 } Bits;

2010

2011 UINT32 Uint32;

2012 UINT64 Uint64;

2013

2014 } MSR_PERMON_EVNTSEL_CNTR3_REGISTER;

2015

2016 /**

2017 This is a PerfMon register that is used to control the behavior

2018 of an associated performance counter and to selecting events for that counter.

2019 **/

2020 #define MSR_PERMON_EVNTSEL_CNTR4 0x0000018A

2021

2022 typedef union {

2023 ///

2024 /// Individual bit fields

2025 ///

2026 struct {

2027 UINT32 EventSelect : 8;

2028

2029 /* Bits[7:0], Access Type=RW, default=None*/

2030

2031 /*

2032 Selects the event logic unit to detect certain

2033 microarchitectural conditions

2034 */

2035 UINT32 UnitMask : 8;

2036

2037 /* Bits[15:8], Access Type=RW, default=None*/

2038

2039 /*

2040 Further qualifies the event logic unit selected

2041 in the event select field to detect a specific

2042 microarchitectural condition.

2043 */

2044 UINT32 Usr : 1;

2045

2046 /* Bits[16:16], Access Type=RW, default=None*/

2047

2048 /*

2049 This bit specifies that events are counted only

2050 when the processor is operating at current

2051 privilege levels 1, 2 or 3 (CPL != 0). This flag

2052 can be used in conjunction with the OS flag.

2053 */

2054 UINT32 Os : 1;

2055

2056 /* Bits[17:17], Access Type=RW, default=None*/

2057

2058 /*

2059 Specifies that events are counted only when the

2060 processor is operating at current privilege

2061 level 0 (CPL=0). This flag can be used in

2062 conjunction with the USR flag.

2063 */

2064 UINT32 EdgeDetect : 1;

2065

2066 /* Bits[18:18], Access Type=RW, default=0x00000000*/

2067

2068 /*

2069 Enables (when set) edge detection of events. The

2070 processor counts the number of deasserted to

2071 asserted transitions of any condition that can

2072 be expressed by the other fields. The mechanism

2073 is limited in that it does not permit back-to-

2074 back assertions to be distinguished.

2075 */

2076 UINT32 Rsvd19 : 1;

2077

2078 /* Bits[19:19], Access Type=RO, default=None*/

2079

2080 /* Reserved */

2081 UINT32 Pmi : 1;

2082

2083 /* Bits[20:20], Access Type=RW, default=0x00000000*/

2084

2085 /*

2086 APIC interrupt enable. When set, the processor

2087 generates an exception through its local APIC on

2088 counter overflow for this counter's thread.

2089 */

2090 UINT32 MythrAllthr : 1;

2091

2092 /* Bits[21:21], Access Type=RW, default=None*/

2093

2094 /*

2095 When set to 1, it enables counting the

2096 associated event conditions occurring across all

2097 logical processors sharing a processor core.

2098 When set to 0, the counter only increments the

2099 associated event conditions occurring in the

2100 logical processor which programmed the MSR.

2101 */

2102 UINT32 EnableBit : 1;

2103

2104 /* Bits[22:22], Access Type=RW, default=0x00000000*/

2105

2106 /*

2107 Enables the corresponding performance counter to

2108 commence counting when this bit is set

2109 */

2110 UINT32 Invert : 1;

2111

2112 /* Bits[23:23], Access Type=RW, default=0x00000000*/

2113

2114 /*

2115 This bit indicates how the CMASK/Threshold field

2116 will be compared to the incoming event. When

2117 '0', the comparison that will be done is:

2118 threshold >= event. When set to '1', the

2119 comparison that will be done is inverted from

2120 the case where this bit is set to '0': threshold

2121 less than event.

2122 */

2123 UINT32 Threshold : 8;

2124

2125 /* Bits[31:24], Access Type=RW, default=0x00000000*/

2126

2127 /*

2128 When CMASK is not zero, the corresponding

2129 performance counter increments each cycle if the

2130 event count is greater than or equal to the

2131 CMASK.

2132 */

2133 UINT32 HleOnly : 1;

2134

2135 /* Bits[32:32], Access Type=RW, default=0x00000000*/

2136

2137 /*

2138 Setting this bit to '1 restricts the counter to

2139 only incrementing for the programmed event

2140 during speculative and non-speculative HLE mode.

2141 This bit will treated as reserved bit if HLE is

2142 fuse disabled.

2143 */

2144 UINT32 HleCheckpointEn : 1;

2145

2146 /* Bits[33:33], Access Type=RW, default=0x00000000*/

2147

2148 /*

2149 Setting this bit to '1 enables the event

2150 programmed into the counter to only non-aborted

2151 HLE execution i.e. the event count will exclude

2152 or not count events that occurred on an aborted

2153 HLE path. Only counter 2 supports this

2154 capability. This bit will treated as reserved

2155 bit if HLE is fuse disabled.

2156 */

2157 UINT32 AdaptiveRecord : 1;

2158

2159 /* Bits[34:34], Access Type=RW, default=0x00000000*/

2160

2161 /*

2162 for Adaptive pebs feature in SNC if

2163 ADAPTIVE_RECORD bit is set, Ucode will consider

2164 MSR_PEBS_DATA_CFG and emit the requested fields

2165 */

2166 UINT32 Rsvd35 : 27;

2167

2168 /* Bits[61:35], Access Type=RO, default=None*/

2169

2170 /* Reserved */

2171 UINT32 Forceubrkpt : 1;

2172

2173 /* Bits[62:62], Access Type=RW, default=None*/

2174

2175 /*

2176 When set a MicroBreakPoint occurs each time a

2177 none zero Event enters the counter.

2178 */

2179 UINT32 Rsvd63 : 1;

2180

2181 /* Bits[63:63], Access Type=RO, default=None*/

2182

2183 /* Reserved */

2184

2185 } Bits;

2186

2187 UINT32 Uint32;

2188 UINT64 Uint64;

2189

2190 } MSR_PERMON_EVNTSEL_CNTR4_REGISTER;

2191

2192 /**

2193 This is a PerfMon register that is used to control the behavior

2194 of an associated performance counter and to selecting events for that counter.

2195 **/

2196 #define MSR_PERMON_EVNTSEL_CNTR5 0x0000018B

2197

2198 typedef union {

2199 ///

2200 /// Individual bit fields

2201 ///

2202 struct {

2203 UINT32 EventSelect : 8;

2204

2205 /* Bits[7:0], Access Type=RW, default=None*/

2206

2207 /*

2208 Selects the event logic unit to detect certain

2209 microarchitectural conditions

2210 */

2211 UINT32 UnitMask : 8;

2212

2213 /* Bits[15:8], Access Type=RW, default=None*/

2214

2215 /*

2216 Further qualifies the event logic unit selected

2217 in the event select field to detect a specific

2218 microarchitectural condition.

2219 */

2220 UINT32 Usr : 1;

2221

2222 /* Bits[16:16], Access Type=RW, default=None*/

2223

2224 /*

2225 This bit specifies that events are counted only

2226 when the processor is operating at current

2227 privilege levels 1, 2 or 3 (CPL != 0). This flag

2228 can be used in conjunction with the OS flag.

2229 */

2230 UINT32 Os : 1;

2231

2232 /* Bits[17:17], Access Type=RW, default=None*/

2233

2234 /*

2235 Specifies that events are counted only when the

2236 processor is operating at current privilege

2237 level 0 (CPL=0). This flag can be used in

2238 conjunction with the USR flag.

2239 */

2240 UINT32 EdgeDetect : 1;

2241

2242 /* Bits[18:18], Access Type=RW, default=0x00000000*/

2243

2244 /*

2245 Enables (when set) edge detection of events. The

2246 processor counts the number of deasserted to

2247 asserted transitions of any condition that can

2248 be expressed by the other fields. The mechanism

2249 is limited in that it does not permit back-to-

2250 back assertions to be distinguished.

2251 */

2252 UINT32 Rsvd19 : 1;

2253

2254 /* Bits[19:19], Access Type=RO, default=None*/

2255

2256 /* Reserved */

2257 UINT32 Pmi : 1;

2258

2259 /* Bits[20:20], Access Type=RW, default=0x00000000*/

2260

2261 /*

2262 APIC interrupt enable. When set, the processor

2263 generates an exception through its local APIC on

2264 counter overflow for this counter's thread.

2265 */

2266 UINT32 MythrAllthr : 1;

2267

2268 /* Bits[21:21], Access Type=RW, default=None*/

2269

2270 /*

2271 When set to 1, it enables counting the

2272 associated event conditions occurring across all

2273 logical processors sharing a processor core.

2274 When set to 0, the counter only increments the

2275 associated event conditions occurring in the

2276 logical processor which programmed the MSR.

2277 */

2278 UINT32 EnableBit : 1;

2279

2280 /* Bits[22:22], Access Type=RW, default=0x00000000*/

2281

2282 /*

2283 Enables the corresponding performance counter to

2284 commence counting when this bit is set

2285 */

2286 UINT32 Invert : 1;

2287

2288 /* Bits[23:23], Access Type=RW, default=0x00000000*/

2289

2290 /*

2291 This bit indicates how the CMASK/Threshold field

2292 will be compared to the incoming event. When

2293 '0', the comparison that will be done is:

2294 threshold >= event. When set to '1', the

2295 comparison that will be done is inverted from

2296 the case where this bit is set to '0': threshold

2297 less than event.

2298 */

2299 UINT32 Threshold : 8;

2300

2301 /* Bits[31:24], Access Type=RW, default=0x00000000*/

2302

2303 /*

2304 When CMASK is not zero, the corresponding

2305 performance counter increments each cycle if the

2306 event count is greater than or equal to the

2307 CMASK.

2308 */

2309 UINT32 HleOnly : 1;

2310

2311 /* Bits[32:32], Access Type=RW, default=0x00000000*/

2312

2313 /*

2314 Setting this bit to '1 restricts the counter to

2315 only incrementing for the programmed event

2316 during speculative and non-speculative HLE mode.

2317 This bit will treated as reserved bit if HLE is

2318 fuse disabled.

2319 */

2320 UINT32 HleCheckpointEn : 1;

2321

2322 /* Bits[33:33], Access Type=RW, default=0x00000000*/

2323

2324 /*

2325 Setting this bit to '1 enables the event

2326 programmed into the counter to only non-aborted

2327 HLE execution i.e. the event count will exclude

2328 or not count events that occurred on an aborted

2329 HLE path. Only counter 2 supports this

2330 capability. This bit will treated as reserved

2331 bit if HLE is fuse disabled.

2332 */

2333 UINT32 AdaptiveRecord : 1;

2334

2335 /* Bits[34:34], Access Type=RW, default=0x00000000*/

2336

2337 /*

2338 for Adaptive pebs feature in SNC if

2339 ADAPTIVE_RECORD bit is set, Ucode will consider

2340 MSR_PEBS_DATA_CFG and emit the requested fields

2341 */

2342 UINT32 Rsvd35 : 27;

2343

2344 /* Bits[61:35], Access Type=RO, default=None*/

2345

2346 /* Reserved */

2347 UINT32 Forceubrkpt : 1;

2348

2349 /* Bits[62:62], Access Type=RW, default=None*/

2350

2351 /*

2352 When set a MicroBreakPoint occurs each time a

2353 none zero Event enters the counter.

2354 */

2355 UINT32 Rsvd63 : 1;

2356

2357 /* Bits[63:63], Access Type=RO, default=None*/

2358

2359 /* Reserved */

2360

2361 } Bits;

2362

2363 UINT32 Uint32;

2364 UINT64 Uint64;

2365

2366 } MSR_PERMON_EVNTSEL_CNTR5_REGISTER;

2367

2368 /**

2369 This is a PerfMon register that is used to control the behavior

2370 of an associated performance counter and to selecting events for that counter.

2371 **/

2372 #define MSR_PERMON_EVNTSEL_CNTR6 0x0000018C

2373

2374 typedef union {

2375 ///

2376 /// Individual bit fields

2377 ///

2378 struct {

2379 UINT32 EventSelect : 8;

2380

2381 /* Bits[7:0], Access Type=RW, default=None*/

2382

2383 /*

2384 Selects the event logic unit to detect certain

2385 microarchitectural conditions

2386 */

2387 UINT32 UnitMask : 8;

2388

2389 /* Bits[15:8], Access Type=RW, default=None*/

2390

2391 /*

2392 Further qualifies the event logic unit selected

2393 in the event select field to detect a specific

2394 microarchitectural condition.

2395 */

2396 UINT32 Usr : 1;

2397

2398 /* Bits[16:16], Access Type=RW, default=None*/

2399

2400 /*

2401 This bit specifies that events are counted only

2402 when the processor is operating at current

2403 privilege levels 1, 2 or 3 (CPL != 0). This flag

2404 can be used in conjunction with the OS flag.

2405 */

2406 UINT32 Os : 1;

2407

2408 /* Bits[17:17], Access Type=RW, default=None*/

2409

2410 /*

2411 Specifies that events are counted only when the

2412 processor is operating at current privilege

2413 level 0 (CPL=0). This flag can be used in

2414 conjunction with the USR flag.

2415 */

2416 UINT32 EdgeDetect : 1;

2417

2418 /* Bits[18:18], Access Type=RW, default=0x00000000*/

2419

2420 /*

2421 Enables (when set) edge detection of events. The

2422 processor counts the number of deasserted to

2423 asserted transitions of any condition that can

2424 be expressed by the other fields. The mechanism

2425 is limited in that it does not permit back-to-

2426 back assertions to be distinguished.

2427 */

2428 UINT32 Rsvd19 : 1;

2429

2430 /* Bits[19:19], Access Type=RO, default=None*/

2431

2432 /* Reserved */

2433 UINT32 Pmi : 1;

2434

2435 /* Bits[20:20], Access Type=RW, default=0x00000000*/

2436

2437 /*

2438 APIC interrupt enable. When set, the processor

2439 generates an exception through its local APIC on

2440 counter overflow for this counter's thread.

2441 */

2442 UINT32 MythrAllthr : 1;

2443

2444 /* Bits[21:21], Access Type=RW, default=None*/

2445

2446 /*

2447 When set to 1, it enables counting the

2448 associated event conditions occurring across all

2449 logical processors sharing a processor core.

2450 When set to 0, the counter only increments the

2451 associated event conditions occurring in the

2452 logical processor which programmed the MSR.

2453 */

2454 UINT32 EnableBit : 1;

2455

2456 /* Bits[22:22], Access Type=RW, default=0x00000000*/

2457

2458 /*

2459 Enables the corresponding performance counter to

2460 commence counting when this bit is set

2461 */

2462 UINT32 Invert : 1;

2463

2464 /* Bits[23:23], Access Type=RW, default=0x00000000*/

2465

2466 /*

2467 This bit indicates how the CMASK/Threshold field

2468 will be compared to the incoming event. When

2469 '0', the comparison that will be done is:

2470 threshold >= event. When set to '1', the

2471 comparison that will be done is inverted from

2472 the case where this bit is set to '0': threshold

2473 less than event.

2474 */

2475 UINT32 Threshold : 8;

2476

2477 /* Bits[31:24], Access Type=RW, default=0x00000000*/

2478

2479 /*

2480 When CMASK is not zero, the corresponding

2481 performance counter increments each cycle if the

2482 event count is greater than or equal to the

2483 CMASK.

2484 */

2485 UINT32 HleOnly : 1;

2486

2487 /* Bits[32:32], Access Type=RW, default=0x00000000*/

2488

2489 /*

2490 Setting this bit to '1 restricts the counter to

2491 only incrementing for the programmed event

2492 during speculative and non-speculative HLE mode.

2493 This bit will treated as reserved bit if HLE is

2494 fuse disabled.

2495 */

2496 UINT32 HleCheckpointEn : 1;

2497

2498 /* Bits[33:33], Access Type=RW, default=0x00000000*/

2499

2500 /*

2501 Setting this bit to '1 enables the event

2502 programmed into the counter to only non-aborted

2503 HLE execution i.e. the event count will exclude

2504 or not count events that occurred on an aborted

2505 HLE path. Only counter 2 supports this

2506 capability. This bit will treated as reserved

2507 bit if HLE is fuse disabled.

2508 */

2509 UINT32 AdaptiveRecord : 1;

2510

2511 /* Bits[34:34], Access Type=RW, default=0x00000000*/

2512

2513 /*

2514 for Adaptive pebs feature in SNC if

2515 ADAPTIVE_RECORD bit is set, Ucode will consider

2516 MSR_PEBS_DATA_CFG and emit the requested fields

2517 */

2518 UINT32 Rsvd35 : 27;

2519

2520 /* Bits[61:35], Access Type=RO, default=None*/

2521

2522 /* Reserved */

2523 UINT32 Forceubrkpt : 1;

2524

2525 /* Bits[62:62], Access Type=RW, default=None*/

2526

2527 /*

2528 When set a MicroBreakPoint occurs each time a

2529 none zero Event enters the counter.

2530 */

2531 UINT32 Rsvd63 : 1;

2532

2533 /* Bits[63:63], Access Type=RO, default=None*/

2534

2535 /* Reserved */

2536

2537 } Bits;

2538

2539 UINT32 Uint32;

2540 UINT64 Uint64;

2541

2542 } MSR_PERMON_EVNTSEL_CNTR6_REGISTER;

2543

2544 /**

2545 This is a PerfMon register that is used to control the behavior

2546 of an associated performance counter and to selecting events for that counter.

2547 **/

2548 #define MSR_PERMON_EVNTSEL_CNTR7 0x0000018D

2549

2550 typedef union {

2551 ///

2552 /// Individual bit fields

2553 ///

2554 struct {

2555 UINT32 EventSelect : 8;

2556

2557 /* Bits[7:0], Access Type=RW, default=None*/

2558

2559 /*

2560 Selects the event logic unit to detect certain

2561 microarchitectural conditions

2562 */

2563 UINT32 UnitMask : 8;

2564

2565 /* Bits[15:8], Access Type=RW, default=None*/

2566

2567 /*

2568 Further qualifies the event logic unit selected

2569 in the event select field to detect a specific

2570 microarchitectural condition.

2571 */

2572 UINT32 Usr : 1;

2573

2574 /* Bits[16:16], Access Type=RW, default=None*/

2575

2576 /*

2577 This bit specifies that events are counted only

2578 when the processor is operating at current

2579 privilege levels 1, 2 or 3 (CPL != 0). This flag

2580 can be used in conjunction with the OS flag.

2581 */

2582 UINT32 Os : 1;

2583

2584 /* Bits[17:17], Access Type=RW, default=None*/

2585

2586 /*

2587 Specifies that events are counted only when the

2588 processor is operating at current privilege

2589 level 0 (CPL=0). This flag can be used in

2590 conjunction with the USR flag.

2591 */

2592 UINT32 EdgeDetect : 1;

2593

2594 /* Bits[18:18], Access Type=RW, default=0x00000000*/

2595

2596 /*

2597 Enables (when set) edge detection of events. The

2598 processor counts the number of deasserted to

2599 asserted transitions of any condition that can

2600 be expressed by the other fields. The mechanism

2601 is limited in that it does not permit back-to-

2602 back assertions to be distinguished.

2603 */

2604 UINT32 Rsvd19 : 1;

2605

2606 /* Bits[19:19], Access Type=RO, default=None*/

2607

2608 /* Reserved */

2609 UINT32 Pmi : 1;

2610

2611 /* Bits[20:20], Access Type=RW, default=0x00000000*/

2612

2613 /*

2614 APIC interrupt enable. When set, the processor

2615 generates an exception through its local APIC on

2616 counter overflow for this counter's thread.

2617 */

2618 UINT32 MythrAllthr : 1;

2619

2620 /* Bits[21:21], Access Type=RW, default=None*/

2621

2622 /*

2623 When set to 1, it enables counting the

2624 associated event conditions occurring across all

2625 logical processors sharing a processor core.

2626 When set to 0, the counter only increments the

2627 associated event conditions occurring in the

2628 logical processor which programmed the MSR.

2629 */

2630 UINT32 EnableBit : 1;

2631

2632 /* Bits[22:22], Access Type=RW, default=0x00000000*/

2633

2634 /*

2635 Enables the corresponding performance counter to

2636 commence counting when this bit is set

2637 */

2638 UINT32 Invert : 1;

2639

2640 /* Bits[23:23], Access Type=RW, default=0x00000000*/

2641

2642 /*

2643 This bit indicates how the CMASK/Threshold field

2644 will be compared to the incoming event. When

2645 '0', the comparison that will be done is:

2646 threshold >= event. When set to '1', the

2647 comparison that will be done is inverted from

2648 the case where this bit is set to '0': threshold

2649 less than event.

2650 */

2651 UINT32 Threshold : 8;

2652

2653 /* Bits[31:24], Access Type=RW, default=0x00000000*/

2654

2655 /*

2656 When CMASK is not zero, the corresponding

2657 performance counter increments each cycle if the

2658 event count is greater than or equal to the

2659 CMASK.

2660 */

2661 UINT32 HleOnly : 1;

2662

2663 /* Bits[32:32], Access Type=RW, default=0x00000000*/

2664

2665 /*

2666 Setting this bit to '1 restricts the counter to

2667 only incrementing for the programmed event

2668 during speculative and non-speculative HLE mode.

2669 This bit will treated as reserved bit if HLE is

2670 fuse disabled.

2671 */

2672 UINT32 HleCheckpointEn : 1;

2673

2674 /* Bits[33:33], Access Type=RW, default=0x00000000*/

2675

2676 /*

2677 Setting this bit to '1 enables the event

2678 programmed into the counter to only non-aborted

2679 HLE execution i.e. the event count will exclude

2680 or not count events that occurred on an aborted

2681 HLE path. Only counter 2 supports this

2682 capability. This bit will treated as reserved

2683 bit if HLE is fuse disabled.

2684 */

2685 UINT32 AdaptiveRecord : 1;

2686

2687 /* Bits[34:34], Access Type=RW, default=0x00000000*/

2688

2689 /*

2690 for Adaptive pebs feature in SNC if

2691 ADAPTIVE_RECORD bit is set, Ucode will consider

2692 MSR_PEBS_DATA_CFG and emit the requested fields

2693 */

2694 UINT32 Rsvd35 : 27;

2695

2696 /* Bits[61:35], Access Type=RO, default=None*/

2697

2698 /* Reserved */

2699 UINT32 Forceubrkpt : 1;

2700

2701 /* Bits[62:62], Access Type=RW, default=None*/

2702

2703 /*

2704 When set a MicroBreakPoint occurs each time a

2705 none zero Event enters the counter.

2706 */

2707 UINT32 Rsvd63 : 1;

2708

2709 /* Bits[63:63], Access Type=RO, default=None*/

2710

2711 /* Reserved */

2712

2713 } Bits;

2714

2715 UINT32 Uint32;

2716 UINT64 Uint64;

2717

2718 } MSR_PERMON_EVNTSEL_CNTR7_REGISTER;

2719

2720 /**

2721 Current performance status

2722 **/

2723 #define MSR_PERF_STATUS 0x00000198

2724

2725 typedef union {

2726 ///

2727 /// Individual bit fields

2728 ///

2729 struct {

2730 UINT32 Rsvd0 : 8;

2731

2732 /* Bits[7:0], Access Type=RO, default=None*/

2733

2734 /* Reserved */

2735 UINT32 Ratio : 7;

2736

2737 /* Bits[14:8], Access Type=RO_V, default=0x00000000*/

2738

2739 /* Current core P-state ratio value 14:8 */

2740 UINT32 Rsvd15 : 17;

2741

2742 /* Bits[31:15], Access Type=RO, default=None*/

2743

2744 /* Reserved */

2745 UINT32 Voltage : 16;

2746

2747 /* Bits[47:32], Access Type=RO_V, default=0x00000000*/

2748

2749 /*

2750 Indicates the current operating voltage in 3.13

2751 format i.e. current voltage = float([47:32] /

2752 (2^13)).

2753 */

2754 UINT32 Rsvd48 : 16;

2755

2756 /* Bits[63:48], Access Type=RO, default=None*/

2757

2758 /* Reserved */

2759

2760 } Bits;

2761

2762 UINT32 Uint32;

2763 UINT64 Uint64;

2764

2765 } MSR_PERF_STATUS_REGISTER;

2766

2767 /**

2768 Legacy Performance Control MSR. SW requests a new Performance state (P-State) by writing to this MSR.

2769 [IntelRsvd]ARCH MSR in core - P-state control register reflected into P-STATE_REQ[/IntelRsvd]

2770 **/

2771 #define MSR_PERF_CTL 0x00000199

2772

2773 typedef union {

2774 ///

2775 /// Individual bit fields

2776 ///

2777 struct {

2778 UINT32 VReq : 8;

2779

2780 /* Bits[7:0], Access Type=RW, default=0x00000000*/

2781

2782 /* Voltage request - Not used = legacy */

2783 UINT32 PReq : 7;

2784

2785 /* Bits[14:8], Access Type=RW, default=0x00000000*/

2786

2787 /*

2788 Requested P-state ratio value for this logical

2789 processor.

2790 */

2791 UINT32 Rsvd15 : 1;

2792

2793 /* Bits[15:15], Access Type=RW, default=0x00000000*/

2794

2795 /* Reserved */

2796 UINT32 Pqosofst : 6;

2797

2798 /* Bits[21:16], Access Type=RW, default=0x00000000*/

2799

2800 /* P/H P-State QoS offset */

2801 UINT32 Rsvd22 : 10;

2802

2803 /* Bits[31:22], Access Type=RO, default=None*/

2804

2805 /* Reserved */

2806 UINT32 TurboDis : 1;

2807

2808 /* Bits[32:32], Access Type=RW, default=0x00000000*/

2809

2810 /*

2811 1 = Turbo Mode disabled, 0=Turbo Mode enabled.

2812 Note: This Turbo Mode Disable exists on each

2813 logical processor; however, setting the Turbo

2814 Mode Disable on any logical processor forces

2815 Turbo Mode to be disabled for all logical

2816 processors in the entire processor package. BIOS

2817 should not use this Turbo Mode Disable since it

2818 does not change the Turbo Mode feature flag.

2819 This Turbo Mode Disable is intended for OS use

2820 only.

2821 */

2822 UINT32 Rsvd33 : 31;

2823

2824 /* Bits[63:33], Access Type=RO, default=None*/

2825

2826 /* Reserved */

2827

2828 } Bits;

2829

2830 UINT32 Uint32;

2831 UINT64 Uint64;

2832

2833 } MSR_PERF_CTL_REGISTER;

2834

2835 /**

2836 This register is used to read and write the duty cycle bits, and to enable the on-demand

2837 clock modulation feature of the Intel Thermal Monitor.

2838 **/

2839 #define MSR_CLOCK_MODULATION 0x0000019A

2840

2841 typedef union {

2842 ///

2843 /// Individual bit fields

2844 ///

2845 struct {

2846 UINT32 TStateReq : 4;

2847

2848 /* Bits[3:0], Access Type=RW, default=0x00000000*/

2849

2850 /*

2851 Selects the on-demand clock modulation duty

2852 cycle. This field is only active when the on-

2853 demand clock modulation enable flag is set.

2854 */

2855 UINT32 ThrottleActive : 1;

2856

2857 /* Bits[4:4], Access Type=RW, default=0x00000000*/

2858

2859 /*

2860 Enables on-demand software controlled clock

2861 modulation when set; disables software-

2862 controlled clock modulation when clear

2863 */

2864 UINT32 Rsvd5 : 27;

2865

2866 /* Bits[31:5], Access Type=RO, default=None*/

2867

2868 /* Reserved */

2869

2870 } Bits;

2871

2872 UINT32 Uint32;

2873 UINT64 Uint64;

2874

2875 } MSR_CLOCK_MODULATION_REGISTER;

2876

2877 /**

2878 Enables and disables the generation of an interrupt on temperature transitions detected with the processor's thermal sensors and thermal monitor.

2879 **/

2880 #define MSR_THERM_INTERRUPT 0x0000019B

2881

2882 typedef union {

2883 ///

2884 /// Individual bit fields

2885 ///

2886 struct {

2887 UINT32 HighTempIntEnable : 1;

2888

2889 /* Bits[0:0], Access Type=RW, default=0x00000000*/

2890

2891 /*

2892 Enables a thermal interrupt to be generated on

2893 the transition from a low-temperature to a high-

2894 temperature when set, where 'high temperature'

2895 is dictated by the thermal monitor trip

2896 temperature.

2897 */

2898 UINT32 LowTempIntEnable : 1;

2899

2900 /* Bits[1:1], Access Type=RW, default=0x00000000*/

2901

2902 /*

2903 Enables a thermal interrupt to be generated on

2904 the transition from a high-temperature to a low-

2905 temperature when set, where 'high temperature'

2906 is dictated by the thermal monitor trip

2907 temperature.

2908 */

2909 UINT32 ProchotIntEnable : 1;

2910

2911 /* Bits[2:2], Access Type=RW, default=0x00000000*/

2912

2913 /*

2914 Bidirectional PROCHOT# assertion interrupt

2915 enable. If set, a thermal interrupt is delivered

2916 on the rising edge of xxPROCHOT#.

2917 */

2918 UINT32 Rsvd3 : 1;

2919

2920 /* Bits[3:3], Access Type=RO, default=None*/

2921

2922 /* Reserved */

2923 UINT32 OutOfSpecIntEnable : 1;

2924

2925 /* Bits[4:4], Access Type=RW, default=0x00000000*/

2926

2927 /*

2928 Thermal interrupt enable for the critical

2929 temperature condition which is stored in the

2930 Critical Temperature Status bit in

2931 IA32_THERM_STATUS.

2932 */

2933 UINT32 Rsvd5 : 3;

2934

2935 /* Bits[7:5], Access Type=RO, default=None*/

2936

2937 /* Reserved */

2938 UINT32 Threshold1RelTemp : 7;

2939

2940 /* Bits[14:8], Access Type=RW, default=0x00000000*/

2941

2942 /*

2943 This value indicates the offset in degrees below

2944 TJ Max Temperature that should trigger a Thermal

2945 Threshold 1 trip.

2946 */

2947 UINT32 Threshold1IntEnable : 1;

2948

2949 /* Bits[15:15], Access Type=RW, default=0x00000000*/

2950

2951 /*

2952 Controls the generation of a thermal interrupt

2953 whenever the Thermal Threshold 1 Temperature is

2954 crossed.

2955 */

2956 UINT32 Threshold2RelTemp : 7;

2957

2958 /* Bits[22:16], Access Type=RW, default=0x00000000*/

2959

2960 /*

2961 This value indicates the offset in degrees below

2962 TJ Max Temperature that should trigger a Thermal

2963 Threshold 2 trip.

2964 */

2965 UINT32 Threshold2IntEnable : 1;

2966

2967 /* Bits[23:23], Access Type=RW, default=0x00000000*/

2968

2969 /*

2970 Controls the generation of a thermal interrupt

2971 whenever the Thermal Threshold 2 Temperature is

2972 crossed.

2973 */

2974 UINT32 PowerIntEnable : 1;

2975

2976 /* Bits[24:24], Access Type=RW, default=0x00000000*/

2977

2978 /*

2979 When this bit is set, a thermal interrupt will

2980 be sent upon throttling due to power

2981 limitations.

2982 */

2983 UINT32 Rsvd25 : 7;

2984

2985 /* Bits[31:25], Access Type=RO, default=None*/

2986

2987 /* Reserved */

2988

2989 } Bits;

2990

2991 UINT32 Uint32;

2992 UINT64 Uint64;

2993

2994 } MSR_THERM_INTERRUPT_REGISTER;

2995

2996 /**

2997 Contains status information about the processor's thermal sensor and automatic thermal monitoring facilities.

2998 **/

2999 #define MSR_THERM_STATUS 0x0000019C

3000

3001 typedef union {

3002 ///

3003 /// Individual bit fields

3004 ///

3005 struct {

3006 UINT32 ThermalMonitorStatus : 1;

3007

3008 /* Bits[0:0], Access Type=RO, default=0x00000000*/

3009

3010 /*

3011 Status bit indicating that the Thermal Monitor

3012 has tripped and is currently thermally

3013 throttling.

3014 */

3015 UINT32 ThermalMonitorLog : 1;

3016

3017 /* Bits[1:1], Access Type=RW0C_FW, default=0x00000000*/

3018

3019 /*

3020 Sticky log bit indicating that the core has seen

3021 a thermal monitor event since the last time SW

3022 cleared this bit. This bit is set by HW on a 0

3023 to 1 transition of THERMAL_MONITOR_STATUS.

3024 */

3025 UINT32 ProchotStatus : 1;

3026

3027 /* Bits[2:2], Access Type=RO, default=0x00000000*/

3028

3029 /*

3030 Status bit indicating that xxPROCHOT# is

3031 currently being asserted.

3032 */

3033 UINT32 ProchotLog : 1;

3034

3035 /* Bits[3:3], Access Type=RW0C_FW, default=0x00000000*/

3036

3037 /*

3038 Sticky log bit indicating that xxPROCHOT# has

3039 been asserted since the last time this bit was

3040 cleared by SW. This bit is set by HW on a 0 to 1

3041 transition of PROCHOT_STATUS.

3042 */

3043 UINT32 OutOfSpecStatus : 1;

3044

3045 /* Bits[4:4], Access Type=RO, default=0x00000000*/

3046

3047 /*

3048 Status bit indicating that the processor is

3049 operating out of its thermal specification. Once

3050 set, this bit should only clear on a reset.

3051 */

3052 UINT32 OutOfSpecLog : 1;

3053

3054 /* Bits[5:5], Access Type=RW0C_FW, default=0x00000000*/

3055

3056 /*

3057 Sticky log bit indicating that the processor

3058 operating out of its thermal specification since

3059 the last time this bit was cleared. This bit is

3060 set by HW on a 0 to 1 transition of

3061 OUT_OF_SPEC_STATUS.

3062 */

3063 UINT32 Threshold1Status : 1;

3064

3065 /* Bits[6:6], Access Type=RO, default=0x00000000*/

3066

3067 /*

3068 Indicates that the current temperature is higher

3069 than or equal to Threshold 1 temperature.

3070 */

3071 UINT32 Threshold1Log : 1;

3072

3073 /* Bits[7:7], Access Type=RW0C_FW, default=0x00000000*/

3074

3075 /*

3076 Sticky log bit that asserts on a 0 to 1 or a 1

3077 to 0 transition of the THRESHOLD1_STATUS bit.

3078 This bit is set by HW and cleared by SW.

3079 */

3080 UINT32 Threshold2Status : 1;

3081

3082 /* Bits[8:8], Access Type=RO, default=0x00000000*/

3083

3084 /*

3085 Indicates that the current temperature is higher

3086 than or equal to Threshold 2 temperature.

3087 */

3088 UINT32 Threshold2Log : 1;

3089

3090 /* Bits[9:9], Access Type=RW0C_FW, default=0x00000000*/

3091

3092 /*

3093 Sticky log bit that asserts on a 0 to 1 or a 1

3094 to 0 transition of the THRESHOLD2_STATUS bit.

3095 This bit is set by HW and cleared by SW.

3096 */

3097 UINT32 PowerLimitationStatus : 1;

3098

3099 /* Bits[10:10], Access Type=RO, default=0x00000000*/

3100

3101 /*

3102 RO - Indicates whether the current P-state is

3103 limited by power limitation. For legacy P state

3104 method, this bit will be set only if the P-state

3105 is limit below the guaranty level

3106 */

3107 UINT32 PowerLimitationLog : 1;

3108

3109 /* Bits[11:11], Access Type=RW0C_FW, default=0x00000000*/

3110

3111 /*

3112 R/WC0 - Sticky bit which indicates whether the

3113 current P-state is limited by power limitation

3114 since the last clearing of this bit or a reset.

3115 SW may clear this bit by writing a zero (0). For

3116 legacy P state method, this bit will be set only

3117 if the P-state is limit below the guaranty level

3118 */

3119 UINT32 CurrentLimitStatus : 1;

3120

3121 /* Bits[12:12], Access Type=RO, default=0x00000000*/

3122

3123 /*

3124 RO - If set (1), indicates an electrical current

3125 limit (e.g. Electrical Design Point/IccMax) is

3126 being exceeded and is adversely impacting energy

3127 efficiency optimizations

3128 */

3129 UINT32 CurrentLimitLog : 1;

3130

3131 /* Bits[13:13], Access Type=RW0C_FW, default=0x00000000*/

3132

3133 /*

3134 R/WC0 - If set (1), an electrical current limit

3135 has been exceeded that has adversely impacted

3136 energy efficiency optimizations since the last

3137 clearing of this bit or a reset. This bit is

3138 sticky, software may clear this bit by writing a

3139 zero (0).

3140 */

3141 UINT32 CrossDomainLimitStatus : 1;

3142

3143 /* Bits[14:14], Access Type=RO, default=0x00000000*/

3144

3145 /*

3146 RO - If set (1), indicates another hardware

3147 domain (e.g. processor graphics) is currently

3148 limiting energy efficiency optimizations in the

3149 processor core domain.

3150 */

3151 UINT32 CrossDomainLimitLog : 1;

3152

3153 /* Bits[15:15], Access Type=RW0C_FW, default=0x00000000*/

3154

3155 /*

3156 R/WC0 - If set (1), indicates another hardware

3157 domain (e.g. processor graphics) has limited

3158 energy efficiency optimizations in the processor

3159 core domain since the last clearing of this bit

3160 or a reset. This bit is sticky, software may

3161 clear this bit by writing a zero (0).

3162 */

3163 UINT32 Temperature : 7;

3164

3165 /* Bits[22:16], Access Type=RO, default=0x00000000*/

3166

3167 /*

3168 This is a temperature offset in degrees C below

3169 theTJ Max temperature. This number is meaningful

3170 only if VALID bit in this register is set.

3171 */

3172 UINT32 Rsvd23 : 4;

3173

3174 /* Bits[26:23], Access Type=RO, default=None*/

3175

3176 /* Reserved */

3177 UINT32 Resolution : 4;

3178

3179 /* Bits[30:27], Access Type=RO, default=0x00000001*/

3180

3181 /* Supported resolution in degrees C. */

3182 UINT32 Valid : 1;

3183

3184 /* Bits[31:31], Access Type=RO, default=0x00000000*/

3185

3186 /*

3187 This bit indicates that the TEMPERATURE field is

3188 valid. It is set by PCODE if the temperature is

3189 within valid thermal sensor range.

3190 */

3191

3192 } Bits;

3193

3194 UINT32 Uint32;

3195 UINT64 Uint64;

3196

3197 } MSR_THERM_STATUS_REGISTER;

3198

3199 /**

3200 Allows a variety of processor functions to be enabled and disabled.

3201 **/

3202 #define MSR_MISC_ENABLES 0x000001A0

3203

3204 typedef union {

3205 ///

3206 /// Individual bit fields

3207 ///

3208 struct {

3209 UINT32 FastStrings : 1;

3210

3211 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3212

3213 /*

3214 When 1, enables fast strings for MOVS and STOS

3215 with the threshold values defined in

3216 MOVS_THRESHOLD and STOS_THRESHOLD. when 0, uses

3217 compatible strings.

3218 */

3219 UINT32 Rsvd1 : 1;

3220

3221 /* Bits[1:1], Access Type=RW, default=None*/

3222

3223 /* Reserved */

3224 UINT32 Rsvd2 : 1;

3225

3226 /* Bits[2:2], Access Type=RO, default=None*/

3227

3228 /* Reserved */

3229 UINT32 ThermalMonitorEnable : 1;

3230

3231 /* Bits[3:3], Access Type=RW, default=None*/

3232

3233 /*

3234 Automatic Thermal Control Circuit Enable. 1 =

3235 Setting this bit enables the thermal control

3236 circuit (TCC) portion of the Intel Thermal

3237 Monitor feature. This allows the processor to

3238 automatically reduce power consumption in

3239 response to TCC activation. 0 = Disabled

3240 (default). Note: In some products clearing this

3241 bit might be ignored in critical thermal

3242 conditions, and TM1, TM2 and adaptive thermal

3243 throttling will still be activated.

3244 */

3245 UINT32 Rsvd4 : 3;

3246

3247 /* Bits[6:4], Access Type=RW, default=None*/

3248

3249 /* Reserved */

3250 UINT32 EmonAvailable : 1;

3251

3252 /* Bits[7:7], Access Type=RW, default=0x00000000*/

3253

3254 /*

3255 1 = Performance monitoring enabled 0 =

3256 Performance monitoring disabled

3257 */

3258 UINT32 Rsvd8 : 3;

3259

3260 /* Bits[10:8], Access Type=RW, default=None*/

3261

3262 /* Reserved */

3263 UINT32 BtsUnavailable : 1;

3264

3265 /* Bits[11:11], Access Type=RW, default=None*/

3266

3267 /*

3268 1 = Processor doesn't support branch trace

3269 storage (BTS) 0 = BTS is supported

3270 */

3271 UINT32 PebsUnavailable : 1;

3272

3273 /* Bits[12:12], Access Type=RW, default=None*/

3274

3275 /*

3276 1 = Processor doesn't support PEBS 0 = PEBS is

3277 supported

3278 */

3279 UINT32 Rsvd13 : 3;

3280

3281 /* Bits[15:13], Access Type=RW, default=None*/

3282

3283 /* Reserved */

3284 UINT32 EnableGv3 : 1;

3285

3286 /* Bits[16:16], Access Type=RW, default=None*/

3287

3288 /*

3289 1 = Enhanced Intel SpeedStep Technology enabled

3290 0 = Enhanced Intel SpeedStep Technology disabled

3291 */

3292 UINT32 RsvdBit17 : 1;

3293

3294 /* Bits[17:17], Access Type=RW, default=None*/

3295

3296 /* Reserved */

3297 UINT32 EnableMonitorFsm : 1;

3298

3299 /* Bits[18:18], Access Type=RW, default=None*/

3300

3301 /*

3302 Enables the Monitor/Mwait FSM. This is a thread-

3303 specific bit

3304 */

3305 UINT32 Rsvd19 : 3;

3306

3307 /* Bits[21:19], Access Type=RW, default=None*/

3308

3309 /* Reserved */

3310 UINT32 BootNt4 : 1;

3311

3312 /* Bits[22:22], Access Type=RW, default=None*/

3313

3314 /*

3315 Limit CPUID Maxval. When this bit is set to 1,

3316 CPUID.00H returns a maximum value in EAX[7:0] of

3317 3. BIOS should contain a setup question that

3318 allows users to specify when the installed OS

3319 does not support CPUID functions greater than 3.

3320 Before setting this bit, BIOS must execute the

3321 CPUID.0H and examine the maximum value returned

3322 in EAX[7:0]. If the maximum value is greater

3323 than 3, the bit is supported. Otherwise, the bit

3324 is not supported. Writing to this bit when the

3325 maximum value is greater than 3 may generate a

3326 #GP exception. Setting this bit may cause

3327 unexpected behavior in software that depends on

3328 the availability of CPUID leaves greater than 3.

3329 */

3330 UINT32 TprMessageDisable : 1;

3331

3332 /* Bits[23:23], Access Type=RW, default=0x00000000*/

3333

3334 /*

3335 When set, disables update of periodic TPR

3336 updates to the I/O apic. Default = 1 (disabled).

3337 This is a thread-specific bit

3338 */

3339 UINT32 Rsvd24 : 3;

3340

3341 /* Bits[26:24], Access Type=RW, default=None*/

3342

3343 /* Reserved */

3344 UINT32 Rsvd27 : 1;

3345

3346 /* Bits[27:27], Access Type=RO, default=None*/

3347

3348 /* Reserved */

3349 UINT32 HlepDisable : 1;

3350

3351 /* Bits[28:28], Access Type=RW, default=None*/

3352

3353 /* When set, disables HLE+. */

3354 UINT32 Rsvd29 : 3;

3355

3356 /* Bits[31:29], Access Type=RW, default=None*/

3357

3358 /* Reserved */

3359 UINT32 Rsvd32 : 6;

3360

3361 /* Bits[37:32], Access Type=RW, default=None*/

3362

3363 /* Reserved */

3364 UINT32 TurboModeDisable : 1;

3365

3366 /* Bits[38:38], Access Type=RW, default=None*/

3367

3368 /* Disables turbo mode when set to 1. */

3369 UINT32 Rsvd39 : 25;

3370

3371 /* Bits[63:39], Access Type=RW, default=None*/

3372

3373 /* Reserved */

3374

3375 } Bits;

3376

3377 UINT32 Uint32;

3378 UINT64 Uint64;

3379

3380 } MSR_MISC_ENABLES_REGISTER;

3381

3382 /**

3383 Performance Energy Bias Hint MSR. This register allows software to control the Energy efficiency Policy in the CPU.

3384 **/

3385 #define MSR_ENERGY_PERFORMANCE_BIAS 0x000001B0

3386

3387 typedef union {

3388 ///

3389 /// Individual bit fields

3390 ///

3391 struct {

3392 UINT32 EnergyPolicy : 4;

3393

3394 /* Bits[3:0], Access Type=RW, default=0x00000000*/

3395

3396 /*

3397 The energy efficiency policy chosen by Operating

3398 System software. This bit is only writable when

3399 POWER_CTL[18] == 1. 0 indicates preference to

3400 highest performance. 15 indicates preference to

3401 maximize energy saving.

3402 */

3403 UINT32 Rsvd4 : 28;

3404

3405 /* Bits[31:4], Access Type=RO, default=None*/

3406

3407 /* Reserved */

3408

3409 } Bits;

3410

3411 UINT32 Uint32;

3412 UINT64 Uint64;

3413

3414 } MSR_ENERGY_PERFORMANCE_BIAS_REGISTER;

3415

3416 /**

3417 Contains status information about the package's thermal sensor.

3418 **/

3419 #define MSR_PACKAGE_THERM_STATUS 0x000001B1

3420

3421 typedef union {

3422 ///

3423 /// Individual bit fields

3424 ///

3425 struct {

3426 UINT32 ThermalMonitorStatus : 1;

3427

3428 /* Bits[0:0], Access Type=RO, default=0x00000000*/

3429

3430 /*

3431 Status bit indicating that any of the package

3432 thermal monitor have tripped and the package is

3433 currently thermally throttling.

3434 */

3435 UINT32 ThermalMonitorLog : 1;

3436

3437 /* Bits[1:1], Access Type=RW0C_FW, default=0x00000000*/

3438

3439 /*

3440 Sticky log bit indicating that the package has

3441 seen a thermal monitor event since the last time

3442 SW cleared this bit. Set by HW on a 0 to 1

3443 transition of Thermal_Monitor_Status.

3444 */

3445 UINT32 ProchotStatus : 1;

3446

3447 /* Bits[2:2], Access Type=RO, default=0x00000000*/

3448

3449 /*

3450 Status bit indicating that xxPROCHOT# is

3451 currently being asserted.

3452 */

3453 UINT32 ProchotLog : 1;

3454

3455 /* Bits[3:3], Access Type=RW0C_FW, default=0x00000000*/

3456

3457 /*

3458 Sticky log bit indicating that xxPROCHOT# has

3459 been asserted since the last time this bit was

3460 cleared by SW. Set by HW on a 0 to 1 transition

3461 of Prochot_Status.

3462 */

3463 UINT32 OutOfSpecStatus : 1;

3464

3465 /* Bits[4:4], Access Type=RO, default=0x00000000*/

3466

3467 /*

3468 Status bit indicating that the processor is

3469 operating out of its thermal specification.

3470 */

3471 UINT32 OutOfSpecLog : 1;

3472

3473 /* Bits[5:5], Access Type=RW0C_FW, default=0x00000000*/

3474

3475 /*

3476 Sticky log bit indicating that the processor

3477 operating out of its thermal specification since

3478 the last time this bit was cleared. Set by HW on

3479 a 0 to 1 transition of Out_of_Spec_Status

3480 */

3481 UINT32 Threshold1Status : 1;

3482

3483 /* Bits[6:6], Access Type=RO, default=0x00000000*/

3484

3485 /*

3486 Indicates that the current temperature (bits

3487 22:16 in this register) is higher than or equal

3488 to the Threshold1 defined in the

3489 IA32_PACKAGE_THERM_INTERRUPT MSR. Note that

3490 because temperature and thresholds are defined

3491 as negative offsets, a higher number means a

3492 lower temperature.

3493 */

3494 UINT32 Threshold1Log : 1;

3495

3496 /* Bits[7:7], Access Type=RW0C_FW, default=0x00000000*/

3497

3498 /*

3499 Sticky log bit that asserts on a 0 to 1 or 1 to

3500 0 transition of the Threshold1_Status bit. HW

3501 controls this transition.

3502 */

3503 UINT32 Threshold2Status : 1;

3504

3505 /* Bits[8:8], Access Type=RO, default=0x00000000*/

3506

3507 /*

3508 Indicates that the current temperature (bits

3509 22:16 of this register) is higher than or equal

3510 to the Threshold2 defined in the

3511 IA32_PACKAGE_THERM_INTERRUPT MSR. Note that

3512 because temperature and thresholds are defined

3513 as negative offsets, a higher number means a

3514 lower temperature.

3515 */

3516 UINT32 Threshold2Log : 1;

3517

3518 /* Bits[9:9], Access Type=RW0C_FW, default=0x00000000*/

3519

3520 /*

3521 Sticky log bit that asserts on a 0 to 1 or 1 to

3522 0 transition of the Threshold2_Status bit. HW

3523 controls this transition.

3524 */

3525 UINT32 PowerLimitationStatus : 1;

3526

3527 /* Bits[10:10], Access Type=RO, default=0x00000000*/

3528

3529 /*

3530 Status log bit that notifies that either IA is

3531 running at P-state below the (max P-state -

3532 offset) or that GT is running at P-state below

3533 its P1 frequency.

3534 */

3535 UINT32 PowerLimitationLog : 1;

3536

3537 /* Bits[11:11], Access Type=RW0C_FW, default=0x00000000*/

3538

3539 /*

3540 Sticky log bit that asserts when either IA is

3541 running at P-state below the (max P-state -

3542 offset) or that Graphics is running at P-state

3543 below its P1 frequency. Set by HW on a 0 to 1

3544 transition of Power Limitation Status. Cleared

3545 by SW.

3546 */

3547 UINT32 PmaxStatus : 1;

3548

3549 /* Bits[12:12], Access Type=RO, default=0x00000000*/

3550

3551 /*

3552 Status bit for the PMAX detector. An assertion

3553 means the PMAX detector circuit has asserted (up

3554 to a 1ms delay). The status bit is deasserted

3555 when the core throttle is released to indicate

3556 the PMAX condition has been dealt with

3557 */

3558 UINT32 PmaxLog : 1;

3559

3560 /* Bits[13:13], Access Type=RW0C_FW, default=0x00000000*/

3561

3562 /*

3563 Sticky log bit indicating the PMAX detector has

3564 been asserted since the last time this bit was

3565 cleared by SW. Set by HW on a 0 to 1 transition

3566 of PMAX_STATUS

3567 */

3568 UINT32 Rsvd14 : 2;

3569

3570 /* Bits[15:14], Access Type=RO, default=None*/

3571

3572 /* Reserved */

3573 UINT32 Temperature : 7;

3574

3575 /* Bits[22:16], Access Type=RO, default=0x00000000*/

3576

3577 /*

3578 Temperature in degrees C, relative to the

3579 thermal monitor trip temperature.

3580 */

3581 UINT32 Rsvd23 : 3;

3582

3583 /* Bits[25:23], Access Type=RO, default=None*/

3584

3585 /* Reserved */

3586 UINT32 HwFeedbackNotificationLog : 1;

3587

3588 /* Bits[26:26], Access Type=RW0C_FW, default=0x00000000*/

3589

3590 /*

3591 Sticky log bit that indicates whether a HW

3592 FEEDBACK Change has occurred (e.g. due to

3593 power/thermal limits) since the last clearing of

3594 this bit or reset. SW may clear this bit by

3595 writing a zero (0).

3596 */

3597 UINT32 Resolution : 4;

3598

3599 /* Bits[30:27], Access Type=RO, default=0x00000000*/

3600

3601 /* Supported resolution in degrees C. */

3602 UINT32 Valid : 1;

3603

3604 /* Bits[31:31], Access Type=RO, default=0x00000000*/

3605

3606 /*

3607 Set if temperature is within the valid thermal

3608 sensor range.

3609 */

3610

3611 } Bits;

3612

3613 UINT32 Uint32;

3614 UINT64 Uint64;

3615

3616 } MSR_PACKAGE_THERM_STATUS_REGISTER;

3617

3618 /**

3619 Thermal Limitation Interrupt Control.

3620 **/

3621 #define MSR_PACKAGE_THERM_INTERRUPT 0x000001B2

3622

3623 typedef union {

3624 ///

3625 /// Individual bit fields

3626 ///

3627 struct {

3628 UINT32 HighTempIntEnable : 1;

3629

3630 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3631

3632 /*

3633 Enables a thermal interrupt to be generated on

3634 the transition from a low-temperature to a high-

3635 temperature when set, where 'high temperature'

3636 is dicated by the thermal monitor trip

3637 temperature minus offset as defined in

3638 IA32_TEMPERATURE_TARGET.

3639 */

3640 UINT32 LowTempIntEnable : 1;

3641

3642 /* Bits[1:1], Access Type=RW, default=0x00000000*/

3643

3644 /*

3645 Enables a thermal interrupt to be generated on

3646 the transition from a high-temperature to a low-

3647 temperature when set, where 'high temperature'

3648 is dicated by the thermal monitor trip

3649 temperature minus offset as defined in

3650 IA32_TEMPERATURE_TARGET.

3651 */

3652 UINT32 ProchotIntEnable : 1;

3653

3654 /* Bits[2:2], Access Type=RW, default=0x00000000*/

3655

3656 /*

3657 Bidirectional PROCHOT# assertion interrupt

3658 enable. If set, a thermal interrupt is delivered

3659 on the rising edge of xxPROCHOT#.

3660 */

3661 UINT32 PmaxIntEnable : 1;

3662

3663 /* Bits[3:3], Access Type=RW, default=0x00000000*/

3664

3665 /*

3666 PMAX detector interrupt enable. If set, a PMAX

3667 interrupt is processed on a 0 to 1 transition.

3668 */

3669 UINT32 OutOfSpecIntEnable : 1;

3670

3671 /* Bits[4:4], Access Type=RW, default=0x00000000*/

3672

3673 /*

3674 Thermal interrupt enable for the Out Of Spec

3675 condition which is stored in the Out Of

3676 Spec/Critical Temperature status bit in

3677 PACKAGE_THERM_STATUS.

3678 */

3679 UINT32 Rsvd5 : 3;

3680

3681 /* Bits[7:5], Access Type=RO, default=None*/

3682

3683 /* Reserved */

3684 UINT32 Threshold1RelTemp : 7;

3685

3686 /* Bits[14:8], Access Type=RW, default=0x00000000*/

3687

3688 /*

3689 This value indicates the offset in degrees below

3690 TJ Max Temperature that should trigger a Thermal

3691 Threshold 1 trip.

3692 */

3693 UINT32 Threshold1IntEnable : 1;

3694

3695 /* Bits[15:15], Access Type=RW, default=0x00000000*/

3696

3697 /*

3698 Controls the generation of a thermal interrupt

3699 whenever the Thermal Threshold 1 Temperature is

3700 crossed.

3701 */

3702 UINT32 Threshold2RelTemp : 7;

3703

3704 /* Bits[22:16], Access Type=RW, default=0x00000000*/

3705

3706 /*

3707 This value indicates the offset in degrees below

3708 TJ Max Temperature that should trigger a Thermal

3709 Threshold 2 trip.

3710 */

3711 UINT32 Threshold2IntEnable : 1;

3712

3713 /* Bits[23:23], Access Type=RW, default=0x00000000*/

3714

3715 /*

3716 Controls the generation of a thermal interrupt

3717 whenever the Thermal Threshold 2 Temperature is

3718 crossed.

3719 */

3720 UINT32 PowerIntEnable : 1;

3721

3722 /* Bits[24:24], Access Type=RW, default=0x00000000*/

3723

3724 /*

3725 When this bit is set, a thermal interrupt will

3726 be sent upon throttling due to power

3727 limitations.

3728 */

3729 UINT32 HwFeedbackNotificationEnable : 1;

3730

3731 /* Bits[25:25], Access Type=RW, default=0x00000000*/

3732

3733 /*

3734 Enables generation of an interrupt for HW

3735 FEEDBACK change occurs (eg. due to thermal/power

3736 limits)

3737 */

3738 UINT32 Rsvd26 : 6;

3739

3740 /* Bits[31:26], Access Type=RO, default=None*/

3741

3742 /* Reserved */

3743

3744 } Bits;

3745

3746 UINT32 Uint32;

3747 UINT64 Uint64;

3748

3749 } MSR_PACKAGE_THERM_INTERRUPT_REGISTER;

3750

3751 /**

3752 Debug MSR for model specific debug features.

3753 **/

3754 #define MSR_DEBUGCTLMSR 0x000001D9

3755

3756 typedef union {

3757 ///

3758 /// Individual bit fields

3759 ///

3760 struct {

3761 UINT32 Lbr : 1;

3762

3763 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3764

3765 /* LBR Enable/Disable Last Branch Records. */

3766 UINT32 Btf : 1;

3767

3768 /* Bits[1:1], Access Type=RW, default=0x00000000*/

3769

3770 /* BTF Branch Trap Flag. */

3771 UINT32 Reserved2 : 4;

3772

3773 /* Bits[5:2], Access Type=RW, default=0x00000000*/

3774

3775 /* These bits are reserved for future use. */

3776 UINT32 Tr : 1;

3777

3778 /* Bits[6:6], Access Type=RW, default=0x00000000*/

3779

3780 /* TR Enable/Disable Execution Trace Messages. */

3781 UINT32 Bts : 1;

3782

3783 /* Bits[7:7], Access Type=RW, default=0x00000000*/

3784

3785 /* Branch trace store */

3786 UINT32 Btint : 1;

3787

3788 /* Bits[8:8], Access Type=RW, default=0x00000000*/

3789

3790 /* Branch trace interrupt */

3791 UINT32 BtsOffOs : 1;

3792

3793 /* Bits[9:9], Access Type=RW, default=0x00000000*/

3794

3795 /* BTS_OFF_OS */

3796 UINT32 BtsOffUsr : 1;

3797

3798 /* Bits[10:10], Access Type=RW, default=0x00000000*/

3799

3800 /* BTS_OFF_USR */

3801 UINT32 FreezeLbrsOnPmi : 1;

3802

3803 /* Bits[11:11], Access Type=RW, default=0x00000000*/

3804

3805 /* FREEZE_LBRS_ON_PMI */

3806 UINT32 FreezePerfmonCtrsOnPmi : 1;

3807

3808 /* Bits[12:12], Access Type=RW, default=0x00000000*/

3809

3810 /* FREEZE_PERFMON_CTRS_ON_PMI */

3811 UINT32 EnablePmiFromUncore : 1;

3812

3813 /* Bits[13:13], Access Type=RW, default=0x00000000*/

3814

3815 /*

3816 Setting this bit enables a PMI for this thread

3817 when the Uncore signals a PMI. For PERFMON

3818 */

3819 UINT32 MachineMonitoringOffInSmm : 1;

3820

3821 /* Bits[14:14], Access Type=RW, default=0x00000000*/

3822

3823 /*

3824 Setting this bit disables Machine Monitoring in

3825 SMM

3826 */

3827 UINT32 HlepDebug : 1;

3828

3829 /* Bits[15:15], Access Type=RW, default=0x00000000*/

3830

3831 /* Enables DR7 debug bit on XBEGIN */

3832 UINT32 Rsvd16 : 16;

3833

3834 /* Bits[31:16], Access Type=RO, default=None*/

3835

3836 /* Reserved */

3837

3838 } Bits;

3839

3840 UINT32 Uint32;

3841 UINT64 Uint64;

3842

3843 } MSR_DEBUGCTLMSR_REGISTER;

3844

3845 /**

3846 DCA CPU capability register

3847 **/

3848 #define MSR_CPU_DCA_CAP 0x000001F9

3849

3850 typedef union {

3851 ///

3852 /// Individual bit fields

3853 ///

3854 struct {

3855 UINT32 Type0 : 1;

3856

3857 /* Bits[0:0], Access Type=RO_V, default=None*/

3858

3859 /* If set, CPU supports Prefetch-Hint type. */

3860 UINT32 Rsvd1 : 31;

3861

3862 /* Bits[31:1], Access Type=RO, default=None*/

3863

3864 /* Reserved */

3865 UINT32 Rsvd32 : 32;

3866

3867 /* Bits[63:32], Access Type=RO, default=None*/

3868

3869 /* Reserved */

3870

3871 } Bits;

3872

3873 UINT32 Uint32;

3874 UINT64 Uint64;

3875

3876 } MSR_CPU_DCA_CAP_REGISTER;

3877

3878 /**

3879 Variable MTRR Entry 0 PhysBase register

3880 **/

3881 #define MSR_MTRRVARBASE0 0x00000200

3882

3883 typedef union {

3884 ///

3885 /// Individual bit fields

3886 ///

3887 struct {

3888 UINT32 Memtype : 3;

3889

3890 /* Bits[2:0], Access Type=RW, default=0x00000000*/

3891

3892 /* Variable MTRR MemType */

3893 UINT32 Rsvd3 : 7;

3894

3895 /* Bits[9:3], Access Type=RO, default=None*/

3896

3897 /* Reserved */

3898 UINT32 Inc1g : 1;

3899

3900 /* Bits[10:10], Access Type=RW, default=0x00000000*/

3901

3902 /* Variable Base inconsistency bit for 1G pages */

3903 UINT32 Inc : 1;

3904

3905 /* Bits[11:11], Access Type=RW, default=0x00000000*/

3906

3907 /* Variable Base inconsistency bit */

3908 UINT32 Base0 : 20;

3909

3910 /* Bits[31:12], Access Type=RW, default=0x00000000*/

3911

3912 /* Variable Base Address */

3913 UINT32 Base1 : 20;

3914

3915 /* Bits[51:32], Access Type=RW, default=0x00000000*/

3916

3917 /* Variable Base Address */

3918 UINT32 Rsvd52 : 12;

3919

3920 /* Bits[63:52], Access Type=RO, default=None*/

3921

3922 /* Reserved */

3923

3924 } Bits;

3925

3926 UINT32 Uint32;

3927 UINT64 Uint64;

3928

3929 } MSR_MTRRVARBASE0_REGISTER;

3930

3931 /**

3932 Variable MTRR Entry 0 PhysMask register

3933 **/

3934 #define MSR_MTRRVARMASK0 0x00000201

3935

3936 typedef union {

3937 ///

3938 /// Individual bit fields

3939 ///

3940 struct {

3941 UINT32 Rsvd0 : 11;

3942

3943 /* Bits[10:0], Access Type=RO, default=None*/

3944

3945 /* Reserved */

3946 UINT32 Vld : 1;

3947

3948 /* Bits[11:11], Access Type=RW, default=0x00000000*/

3949

3950 /* Variable MTRR valid bit */

3951 UINT32 Mask0 : 20;

3952

3953 /* Bits[31:12], Access Type=RW, default=0x00000000*/

3954

3955 /* Variable MTRR Mask */

3956 UINT32 Mask1 : 20;

3957

3958 /* Bits[51:32], Access Type=RW, default=0x00000000*/

3959

3960 /* Variable MTRR Mask */

3961 UINT32 Rsvd52 : 12;

3962

3963 /* Bits[63:52], Access Type=RO, default=None*/

3964

3965 /* Reserved */

3966

3967 } Bits;

3968

3969 UINT32 Uint32;

3970 UINT64 Uint64;

3971

3972 } MSR_MTRRVARMASK0_REGISTER;

3973

3974 /**

3975 Variable MTRR Entry 1 PhysBase register

3976 **/

3977 #define MSR_MTRRVARBASE1 0x00000202

3978

3979 typedef union {

3980 ///

3981 /// Individual bit fields

3982 ///

3983 struct {

3984 UINT32 Memtype : 3;

3985

3986 /* Bits[2:0], Access Type=RW, default=0x00000000*/

3987

3988 /* Variable MTRR MemType */

3989 UINT32 Rsvd3 : 7;

3990

3991 /* Bits[9:3], Access Type=RO, default=None*/

3992

3993 /* Reserved */

3994 UINT32 Inc1g : 1;

3995

3996 /* Bits[10:10], Access Type=RW, default=0x00000000*/

3997

3998 /* Variable Base inconsistency bit for 1G pages */

3999 UINT32 Inc : 1;

4000

4001 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4002

4003 /* Variable Base inconsistency bit */

4004 UINT32 Base0 : 20;

4005

4006 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4007

4008 /* Variable Base Address */

4009 UINT32 Base1 : 20;

4010

4011 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4012

4013 /* Variable Base Address */

4014 UINT32 Rsvd52 : 12;

4015

4016 /* Bits[63:52], Access Type=RO, default=None*/

4017

4018 /* Reserved */

4019

4020 } Bits;

4021

4022 UINT32 Uint32;

4023 UINT64 Uint64;

4024

4025 } MSR_MTRRVARBASE1_REGISTER;

4026

4027 /**

4028 Variable MTRR Entry 1 PhysMask register

4029 **/

4030 #define MSR_MTRRVARMASK1 0x00000203

4031

4032 typedef union {

4033 ///

4034 /// Individual bit fields

4035 ///

4036 struct {

4037 UINT32 Rsvd0 : 11;

4038

4039 /* Bits[10:0], Access Type=RO, default=None*/

4040

4041 /* Reserved */

4042 UINT32 Vld : 1;

4043

4044 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4045

4046 /* Variable MTRR valid bit */

4047 UINT32 Mask0 : 20;

4048

4049 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4050

4051 /* Variable MTRR Mask */

4052 UINT32 Mask1 : 20;

4053

4054 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4055

4056 /* Variable MTRR Mask */

4057 UINT32 Rsvd52 : 12;

4058

4059 /* Bits[63:52], Access Type=RO, default=None*/

4060

4061 /* Reserved */

4062

4063 } Bits;

4064

4065 UINT32 Uint32;

4066 UINT64 Uint64;

4067

4068 } MSR_MTRRVARMASK1_REGISTER;

4069

4070 /**

4071 Variable MTRR Entry 2 PhysBase register

4072 **/

4073 #define MSR_MTRRVARBASE2 0x00000204

4074

4075 typedef union {

4076 ///

4077 /// Individual bit fields

4078 ///

4079 struct {

4080 UINT32 Memtype : 3;

4081

4082 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4083

4084 /* Variable MTRR MemType */

4085 UINT32 Rsvd3 : 7;

4086

4087 /* Bits[9:3], Access Type=RO, default=None*/

4088

4089 /* Reserved */

4090 UINT32 Inc1g : 1;

4091

4092 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4093

4094 /* Variable Base inconsistency bit for 1G pages */

4095 UINT32 Inc : 1;

4096

4097 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4098

4099 /* Variable Base inconsistency bit */

4100 UINT32 Base0 : 20;

4101

4102 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4103

4104 /* Variable Base Address */

4105 UINT32 Base1 : 20;

4106

4107 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4108

4109 /* Variable Base Address */

4110 UINT32 Rsvd52 : 12;

4111

4112 /* Bits[63:52], Access Type=RO, default=None*/

4113

4114 /* Reserved */

4115

4116 } Bits;

4117

4118 UINT32 Uint32;

4119 UINT64 Uint64;

4120

4121 } MSR_MTRRVARBASE2_REGISTER;

4122

4123 /**

4124 Variable MTRR Entry 2 PhysMask register

4125 **/

4126 #define MSR_MTRRVARMASK2 0x00000205

4127

4128 typedef union {

4129 ///

4130 /// Individual bit fields

4131 ///

4132 struct {

4133 UINT32 Rsvd0 : 11;

4134

4135 /* Bits[10:0], Access Type=RO, default=None*/

4136

4137 /* Reserved */

4138 UINT32 Vld : 1;

4139

4140 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4141

4142 /* Variable MTRR valid bit */

4143 UINT32 Mask0 : 20;

4144

4145 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4146

4147 /* Variable MTRR Mask */

4148 UINT32 Mask1 : 20;

4149

4150 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4151

4152 /* Variable MTRR Mask */

4153 UINT32 Rsvd52 : 12;

4154

4155 /* Bits[63:52], Access Type=RO, default=None*/

4156

4157 /* Reserved */

4158

4159 } Bits;

4160

4161 UINT32 Uint32;

4162 UINT64 Uint64;

4163

4164 } MSR_MTRRVARMASK2_REGISTER;

4165

4166 /**

4167 Variable MTRR Entry 3 PhysBase register

4168 **/

4169 #define MSR_MTRRVARBASE3 0x00000206

4170

4171 typedef union {

4172 ///

4173 /// Individual bit fields

4174 ///

4175 struct {

4176 UINT32 Memtype : 3;

4177

4178 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4179

4180 /* Variable MTRR MemType */

4181 UINT32 Rsvd3 : 7;

4182

4183 /* Bits[9:3], Access Type=RO, default=None*/

4184

4185 /* Reserved */

4186 UINT32 Inc1g : 1;

4187

4188 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4189

4190 /* Variable Base inconsistency bit for 1G pages */

4191 UINT32 Inc : 1;

4192

4193 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4194

4195 /* Variable Base inconsistency bit */

4196 UINT32 Base0 : 20;

4197

4198 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4199

4200 /* Variable Base Address */

4201 UINT32 Base1 : 20;

4202

4203 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4204

4205 /* Variable Base Address */

4206 UINT32 Rsvd52 : 12;

4207

4208 /* Bits[63:52], Access Type=RO, default=None*/

4209

4210 /* Reserved */

4211

4212 } Bits;

4213

4214 UINT32 Uint32;

4215 UINT64 Uint64;

4216

4217 } MSR_MTRRVARBASE3_REGISTER;

4218

4219 /**

4220 Variable MTRR Entry 3 PhysMask register

4221 **/

4222 #define MSR_MTRRVARMASK3 0x00000207

4223

4224 typedef union {

4225 ///

4226 /// Individual bit fields

4227 ///

4228 struct {

4229 UINT32 Rsvd0 : 11;

4230

4231 /* Bits[10:0], Access Type=RO, default=None*/

4232

4233 /* Reserved */

4234 UINT32 Vld : 1;

4235

4236 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4237

4238 /* Variable MTRR valid bit */

4239 UINT32 Mask0 : 20;

4240

4241 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4242

4243 /* Variable MTRR Mask */

4244 UINT32 Mask1 : 20;

4245

4246 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4247

4248 /* Variable MTRR Mask */

4249 UINT32 Rsvd52 : 12;

4250

4251 /* Bits[63:52], Access Type=RO, default=None*/

4252

4253 /* Reserved */

4254

4255 } Bits;

4256

4257 UINT32 Uint32;

4258 UINT64 Uint64;

4259

4260 } MSR_MTRRVARMASK3_REGISTER;

4261

4262 /**

4263 Variable MTRR Entry 4 PhysBase register

4264 **/

4265 #define MSR_MTRRVARBASE4 0x00000208

4266

4267 typedef union {

4268 ///

4269 /// Individual bit fields

4270 ///

4271 struct {

4272 UINT32 Memtype : 3;

4273

4274 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4275

4276 /* Variable MTRR MemType */

4277 UINT32 Rsvd3 : 7;

4278

4279 /* Bits[9:3], Access Type=RO, default=None*/

4280

4281 /* Reserved */

4282 UINT32 Inc1g : 1;

4283

4284 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4285

4286 /* Variable Base inconsistency bit for 1G pages */

4287 UINT32 Inc : 1;

4288

4289 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4290

4291 /* Variable Base inconsistency bit */

4292 UINT32 Base0 : 20;

4293

4294 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4295

4296 /* Variable Base Address */

4297 UINT32 Base1 : 20;

4298

4299 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4300

4301 /* Variable Base Address */

4302 UINT32 Rsvd52 : 12;

4303

4304 /* Bits[63:52], Access Type=RO, default=None*/

4305

4306 /* Reserved */

4307

4308 } Bits;

4309

4310 UINT32 Uint32;

4311 UINT64 Uint64;

4312

4313 } MSR_MTRRVARBASE4_REGISTER;

4314

4315 /**

4316 Variable MTRR Entry 4 PhysMask register

4317 **/

4318 #define MSR_MTRRVARMASK4 0x00000209

4319

4320 typedef union {

4321 ///

4322 /// Individual bit fields

4323 ///

4324 struct {

4325 UINT32 Rsvd0 : 11;

4326

4327 /* Bits[10:0], Access Type=RO, default=None*/

4328

4329 /* Reserved */

4330 UINT32 Vld : 1;

4331

4332 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4333

4334 /* Variable MTRR valid bit */

4335 UINT32 Mask0 : 20;

4336

4337 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4338

4339 /* Variable MTRR Mask */

4340 UINT32 Mask1 : 20;

4341

4342 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4343

4344 /* Variable MTRR Mask */

4345 UINT32 Rsvd52 : 12;

4346

4347 /* Bits[63:52], Access Type=RO, default=None*/

4348

4349 /* Reserved */

4350

4351 } Bits;

4352

4353 UINT32 Uint32;

4354 UINT64 Uint64;

4355

4356 } MSR_MTRRVARMASK4_REGISTER;

4357

4358 /**

4359 Variable MTRR Entry 5 PhysBase register

4360 **/

4361 #define MSR_MTRRVARBASE5 0x0000020A

4362

4363 typedef union {

4364 ///

4365 /// Individual bit fields

4366 ///

4367 struct {

4368 UINT32 Memtype : 3;

4369

4370 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4371

4372 /* Variable MTRR MemType */

4373 UINT32 Rsvd3 : 7;

4374

4375 /* Bits[9:3], Access Type=RO, default=None*/

4376

4377 /* Reserved */

4378 UINT32 Inc1g : 1;

4379

4380 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4381

4382 /* Variable Base inconsistency bit for 1G pages */

4383 UINT32 Inc : 1;

4384

4385 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4386

4387 /* Variable Base inconsistency bit */

4388 UINT32 Base0 : 20;

4389

4390 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4391

4392 /* Variable Base Address */

4393 UINT32 Base1 : 20;

4394

4395 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4396

4397 /* Variable Base Address */

4398 UINT32 Rsvd52 : 12;

4399

4400 /* Bits[63:52], Access Type=RO, default=None*/

4401

4402 /* Reserved */

4403

4404 } Bits;

4405

4406 UINT32 Uint32;

4407 UINT64 Uint64;

4408

4409 } MSR_MTRRVARBASE5_REGISTER;

4410

4411 /**

4412 Variable MTRR Entry 5 PhysMask register

4413 **/

4414 #define MSR_MTRRVARMASK5 0x0000020B

4415

4416 typedef union {

4417 ///

4418 /// Individual bit fields

4419 ///

4420 struct {

4421 UINT32 Rsvd0 : 11;

4422

4423 /* Bits[10:0], Access Type=RO, default=None*/

4424

4425 /* Reserved */

4426 UINT32 Vld : 1;

4427

4428 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4429

4430 /* Variable MTRR valid bit */

4431 UINT32 Mask0 : 20;

4432

4433 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4434

4435 /* Variable MTRR Mask */

4436 UINT32 Mask1 : 20;

4437

4438 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4439

4440 /* Variable MTRR Mask */

4441 UINT32 Rsvd52 : 12;

4442

4443 /* Bits[63:52], Access Type=RO, default=None*/

4444

4445 /* Reserved */

4446

4447 } Bits;

4448

4449 UINT32 Uint32;

4450 UINT64 Uint64;

4451

4452 } MSR_MTRRVARMASK5_REGISTER;

4453

4454 /**

4455 Variable MTRR Entry 6 PhysBase register

4456 **/

4457 #define MSR_MTRRVARBASE6 0x0000020C

4458

4459 typedef union {

4460 ///

4461 /// Individual bit fields

4462 ///

4463 struct {

4464 UINT32 Memtype : 3;

4465

4466 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4467

4468 /* Variable MTRR MemType */

4469 UINT32 Rsvd3 : 7;

4470

4471 /* Bits[9:3], Access Type=RO, default=None*/

4472

4473 /* Reserved */

4474 UINT32 Inc1g : 1;

4475

4476 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4477

4478 /* Variable Base inconsistency bit for 1G pages */

4479 UINT32 Inc : 1;

4480

4481 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4482

4483 /* Variable Base inconsistency bit */

4484 UINT32 Base0 : 20;

4485

4486 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4487

4488 /* Variable Base Address */

4489 UINT32 Base1 : 20;

4490

4491 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4492

4493 /* Variable Base Address */

4494 UINT32 Rsvd52 : 12;

4495

4496 /* Bits[63:52], Access Type=RO, default=None*/

4497

4498 /* Reserved */

4499

4500 } Bits;

4501

4502 UINT32 Uint32;

4503 UINT64 Uint64;

4504

4505 } MSR_MTRRVARBASE6_REGISTER;

4506

4507 /**

4508 Variable MTRR Entry 6 PhysMask register

4509 **/

4510 #define MSR_MTRRVARMASK6 0x0000020D

4511

4512 typedef union {

4513 ///

4514 /// Individual bit fields

4515 ///

4516 struct {

4517 UINT32 Rsvd0 : 11;

4518

4519 /* Bits[10:0], Access Type=RO, default=None*/

4520

4521 /* Reserved */

4522 UINT32 Vld : 1;

4523

4524 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4525

4526 /* Variable MTRR valid bit */

4527 UINT32 Mask0 : 20;

4528

4529 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4530

4531 /* Variable MTRR Mask */

4532 UINT32 Mask1 : 20;

4533

4534 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4535

4536 /* Variable MTRR Mask */

4537 UINT32 Rsvd52 : 12;

4538

4539 /* Bits[63:52], Access Type=RO, default=None*/

4540

4541 /* Reserved */

4542

4543 } Bits;

4544

4545 UINT32 Uint32;

4546 UINT64 Uint64;

4547

4548 } MSR_MTRRVARMASK6_REGISTER;

4549

4550 /**

4551 Variable MTRR Entry 7 PhysBase register

4552 **/

4553 #define MSR_MTRRVARBASE7 0x0000020E

4554

4555 typedef union {

4556 ///

4557 /// Individual bit fields

4558 ///

4559 struct {

4560 UINT32 Memtype : 3;

4561

4562 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4563

4564 /* Variable MTRR MemType */

4565 UINT32 Rsvd3 : 7;

4566

4567 /* Bits[9:3], Access Type=RO, default=None*/

4568

4569 /* Reserved */

4570 UINT32 Inc1g : 1;

4571

4572 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4573

4574 /* Variable Base inconsistency bit for 1G pages */

4575 UINT32 Inc : 1;

4576

4577 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4578

4579 /* Variable Base inconsistency bit */

4580 UINT32 Base0 : 20;

4581

4582 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4583

4584 /* Variable Base Address */

4585 UINT32 Base1 : 20;

4586

4587 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4588

4589 /* Variable Base Address */

4590 UINT32 Rsvd52 : 12;

4591

4592 /* Bits[63:52], Access Type=RO, default=None*/

4593

4594 /* Reserved */

4595

4596 } Bits;

4597

4598 UINT32 Uint32;

4599 UINT64 Uint64;

4600

4601 } MSR_MTRRVARBASE7_REGISTER;

4602

4603 /**

4604 Variable MTRR Entry 7 PhysMask register

4605 **/

4606 #define MSR_MTRRVARMASK7 0x0000020F

4607

4608 typedef union {

4609 ///

4610 /// Individual bit fields

4611 ///

4612 struct {

4613 UINT32 Rsvd0 : 11;

4614

4615 /* Bits[10:0], Access Type=RO, default=None*/

4616

4617 /* Reserved */

4618 UINT32 Vld : 1;

4619

4620 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4621

4622 /* Variable MTRR valid bit */

4623 UINT32 Mask0 : 20;

4624

4625 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4626

4627 /* Variable MTRR Mask */

4628 UINT32 Mask1 : 20;

4629

4630 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4631

4632 /* Variable MTRR Mask */

4633 UINT32 Rsvd52 : 12;

4634

4635 /* Bits[63:52], Access Type=RO, default=None*/

4636

4637 /* Reserved */

4638

4639 } Bits;

4640

4641 UINT32 Uint32;

4642 UINT64 Uint64;

4643

4644 } MSR_MTRRVARMASK7_REGISTER;

4645

4646 /**

4647 Variable MTRR Entry 8 PhysBase register

4648 **/

4649 #define MSR_MTRRVARBASE8 0x00000210

4650

4651 typedef union {

4652 ///

4653 /// Individual bit fields

4654 ///

4655 struct {

4656 UINT32 Memtype : 3;

4657

4658 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4659

4660 /* Variable MTRR MemType */

4661 UINT32 Rsvd3 : 7;

4662

4663 /* Bits[9:3], Access Type=RO, default=None*/

4664

4665 /* Reserved */

4666 UINT32 Inc1g : 1;

4667

4668 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4669

4670 /* Variable Base inconsistency bit for 1G pages */

4671 UINT32 Inc : 1;

4672

4673 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4674

4675 /* Variable Base inconsistency bit */

4676 UINT32 Base0 : 20;

4677

4678 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4679

4680 /* Variable Base Address */

4681 UINT32 Base1 : 20;

4682

4683 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4684

4685 /* Variable Base Address */

4686 UINT32 Rsvd52 : 12;

4687

4688 /* Bits[63:52], Access Type=RO, default=None*/

4689

4690 /* Reserved */

4691

4692 } Bits;

4693

4694 UINT32 Uint32;

4695 UINT64 Uint64;

4696

4697 } MSR_MTRRVARBASE8_REGISTER;

4698

4699 /**

4700 Variable MTRR Entry 8 PhysMask register

4701 **/

4702 #define MSR_MTRRVARMASK8 0x00000211

4703

4704 typedef union {

4705 ///

4706 /// Individual bit fields

4707 ///

4708 struct {

4709 UINT32 Rsvd0 : 11;

4710

4711 /* Bits[10:0], Access Type=RO, default=None*/

4712

4713 /* Reserved */

4714 UINT32 Vld : 1;

4715

4716 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4717

4718 /* Variable MTRR valid bit */

4719 UINT32 Mask0 : 20;

4720

4721 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4722

4723 /* Variable MTRR Mask */

4724 UINT32 Mask1 : 20;

4725

4726 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4727

4728 /* Variable MTRR Mask */

4729 UINT32 Rsvd52 : 12;

4730

4731 /* Bits[63:52], Access Type=RO, default=None*/

4732

4733 /* Reserved */

4734

4735 } Bits;

4736

4737 UINT32 Uint32;

4738 UINT64 Uint64;

4739

4740 } MSR_MTRRVARMASK8_REGISTER;

4741

4742 /**

4743 Variable MTRR Entry 9 PhysBase register

4744 **/

4745 #define MSR_MTRRVARBASE9 0x00000212

4746

4747 typedef union {

4748 ///

4749 /// Individual bit fields

4750 ///

4751 struct {

4752 UINT32 Memtype : 3;

4753

4754 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4755

4756 /* Variable MTRR MemType */

4757 UINT32 Rsvd3 : 7;

4758

4759 /* Bits[9:3], Access Type=RO, default=None*/

4760

4761 /* Reserved */

4762 UINT32 Inc1g : 1;

4763

4764 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4765

4766 /* Variable Base inconsistency bit for 1G pages */

4767 UINT32 Inc : 1;

4768

4769 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4770

4771 /* Variable Base inconsistency bit */

4772 UINT32 Base0 : 20;

4773

4774 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4775

4776 /* Variable Base Address */

4777 UINT32 Base1 : 20;

4778

4779 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4780

4781 /* Variable Base Address */

4782 UINT32 Rsvd52 : 12;

4783

4784 /* Bits[63:52], Access Type=RO, default=None*/

4785

4786 /* Reserved */

4787

4788 } Bits;

4789

4790 UINT32 Uint32;

4791 UINT64 Uint64;

4792

4793 } MSR_MTRRVARBASE9_REGISTER;

4794

4795 /**

4796 Variable MTRR Entry 9 PhysMask register

4797 **/

4798 #define MSR_MTRRVARMASK9 0x00000213

4799

4800 typedef union {

4801 ///

4802 /// Individual bit fields

4803 ///

4804 struct {

4805 UINT32 Rsvd0 : 11;

4806

4807 /* Bits[10:0], Access Type=RO, default=None*/

4808

4809 /* Reserved */

4810 UINT32 Vld : 1;

4811

4812 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4813

4814 /* Variable MTRR valid bit */

4815 UINT32 Mask0 : 20;

4816

4817 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4818

4819 /* Variable MTRR Mask */

4820 UINT32 Mask1 : 20;

4821

4822 /* Bits[51:32], Access Type=RW, default=0x00000000*/

4823

4824 /* Variable MTRR Mask */

4825 UINT32 Rsvd52 : 12;

4826

4827 /* Bits[63:52], Access Type=RO, default=None*/

4828

4829 /* Reserved */

4830

4831 } Bits;

4832

4833 UINT32 Uint32;

4834 UINT64 Uint64;

4835

4836 } MSR_MTRRVARMASK9_REGISTER;

4837

4838 /**

4839 Maps 512K address range from 0H-7FFFFH

4840 **/

4841 #define MSR_MTRRFIX64K 0x00000250

4842

4843 typedef union {

4844 ///

4845 /// Individual bit fields

4846 ///

4847 struct {

4848 UINT32 Range0 : 3;

4849

4850 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4851

4852 /* Maps 64K addr range from 00000-0FFFF */

4853 UINT32 Rsvd3 : 5;

4854

4855 /* Bits[7:3], Access Type=RO, default=None*/

4856

4857 /* Reserved */

4858 UINT32 Range1 : 3;

4859

4860 /* Bits[10:8], Access Type=RW, default=0x00000000*/

4861

4862 /* Maps 64K addr range from 10000-1FFFF */

4863 UINT32 Rsvd11 : 5;

4864

4865 /* Bits[15:11], Access Type=RO, default=None*/

4866

4867 /* Reserved */

4868 UINT32 Range2 : 3;

4869

4870 /* Bits[18:16], Access Type=RW, default=0x00000000*/

4871

4872 /* Maps 64K addr range from 20000-2FFFF */

4873 UINT32 Rsvd19 : 5;

4874

4875 /* Bits[23:19], Access Type=RO, default=None*/

4876

4877 /* Reserved */

4878 UINT32 Range3 : 3;

4879

4880 /* Bits[26:24], Access Type=RW, default=0x00000000*/

4881

4882 /* Maps 64K addr range from 30000-3FFFF */

4883 UINT32 Rsvd27 : 5;

4884

4885 /* Bits[31:27], Access Type=RO, default=None*/

4886

4887 /* Reserved */

4888 UINT32 Range4 : 3;

4889

4890 /* Bits[34:32], Access Type=RW, default=0x00000000*/

4891

4892 /* Maps 64K addr range from 40000-4FFFF */

4893 UINT32 Rsvd35 : 5;

4894

4895 /* Bits[39:35], Access Type=RO, default=None*/

4896

4897 /* Reserved */

4898 UINT32 Range5 : 3;

4899

4900 /* Bits[42:40], Access Type=RW, default=0x00000000*/

4901

4902 /* Maps 64K addr range from 50000-5FFFF */

4903 UINT32 Rsvd43 : 5;

4904

4905 /* Bits[47:43], Access Type=RO, default=None*/

4906

4907 /* Reserved */

4908 UINT32 Range6 : 3;

4909

4910 /* Bits[50:48], Access Type=RW, default=0x00000000*/

4911

4912 /* Maps 64K addr range from 60000-6FFFF */

4913 UINT32 Rsvd51 : 5;

4914

4915 /* Bits[55:51], Access Type=RO, default=None*/

4916

4917 /* Reserved */

4918 UINT32 Range7 : 3;

4919

4920 /* Bits[58:56], Access Type=RW, default=0x00000000*/

4921

4922 /* Maps 64K addr range from 70000-7FFFF */

4923 UINT32 Rsvd59 : 5;

4924

4925 /* Bits[63:59], Access Type=RO, default=None*/

4926

4927 /* Reserved */

4928

4929 } Bits;

4930

4931 UINT32 Uint32;

4932 UINT64 Uint64;

4933

4934 } MSR_MTRRFIX64K_REGISTER;

4935

4936 /**

4937 Maps 128K address range from 80000H-9FFFFH

4938 **/

4939 #define MSR_MTRRFIX16K8 0x00000258

4940

4941 typedef union {

4942 ///

4943 /// Individual bit fields

4944 ///

4945 struct {

4946 UINT32 Range0 : 3;

4947

4948 /* Bits[2:0], Access Type=RW, default=0x00000000*/

4949

4950 /* Maps 16K addr range from 80000-83FFF */

4951 UINT32 Rsvd3 : 5;

4952

4953 /* Bits[7:3], Access Type=RO, default=None*/

4954

4955 /* Reserved */

4956 UINT32 Range1 : 3;

4957

4958 /* Bits[10:8], Access Type=RW, default=0x00000000*/

4959

4960 /* Maps 16K addr range from 84000-87FFF */

4961 UINT32 Rsvd11 : 5;

4962

4963 /* Bits[15:11], Access Type=RO, default=None*/

4964

4965 /* Reserved */

4966 UINT32 Range2 : 3;

4967

4968 /* Bits[18:16], Access Type=RW, default=0x00000000*/

4969

4970 /* Maps 16K addr range from 88000-8BFFF */

4971 UINT32 Rsvd19 : 5;

4972

4973 /* Bits[23:19], Access Type=RO, default=None*/

4974

4975 /* Reserved */

4976 UINT32 Range3 : 3;

4977

4978 /* Bits[26:24], Access Type=RW, default=0x00000000*/

4979

4980 /* Maps 16K addr range from 8C000-8FFFF */

4981 UINT32 Rsvd27 : 5;

4982

4983 /* Bits[31:27], Access Type=RO, default=None*/

4984

4985 /* Reserved */

4986 UINT32 Range4 : 3;

4987

4988 /* Bits[34:32], Access Type=RW, default=0x00000000*/

4989

4990 /* Maps 16K addr range from 90000-93FFF */

4991 UINT32 Rsvd35 : 5;

4992

4993 /* Bits[39:35], Access Type=RO, default=None*/

4994

4995 /* Reserved */

4996 UINT32 Range5 : 3;

4997

4998 /* Bits[42:40], Access Type=RW, default=0x00000000*/

4999

5000 /* Maps 16K addr range from 94000-97FFF */

5001 UINT32 Rsvd43 : 5;

5002

5003 /* Bits[47:43], Access Type=RO, default=None*/

5004

5005 /* Reserved */

5006 UINT32 Range6 : 3;

5007

5008 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5009

5010 /* Maps 16K addr range from 98000-9BFFF */

5011 UINT32 Rsvd51 : 5;

5012

5013 /* Bits[55:51], Access Type=RO, default=None*/

5014

5015 /* Reserved */

5016 UINT32 Range7 : 3;

5017

5018 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5019

5020 /* Maps 16K addr range from 9C000-9FFFF */

5021 UINT32 Rsvd59 : 5;

5022

5023 /* Bits[63:59], Access Type=RO, default=None*/

5024

5025 /* Reserved */

5026

5027 } Bits;

5028

5029 UINT32 Uint32;

5030 UINT64 Uint64;

5031

5032 } MSR_MTRRFIX16K8_REGISTER;

5033

5034 /**

5035 Maps 128K address range from A0000H-BFFFFH

5036 **/

5037 #define MSR_MTRRFIX16KA 0x00000259

5038

5039 typedef union {

5040 ///

5041 /// Individual bit fields

5042 ///

5043 struct {

5044 UINT32 Range0 : 3;

5045

5046 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5047

5048 /* Maps 16K addr range from A0000-A3FFF */

5049 UINT32 Rsvd3 : 5;

5050

5051 /* Bits[7:3], Access Type=RO, default=None*/

5052

5053 /* Reserved */

5054 UINT32 Range1 : 3;

5055

5056 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5057

5058 /* Maps 16K addr range from A4000-A7FFF */

5059 UINT32 Rsvd11 : 5;

5060

5061 /* Bits[15:11], Access Type=RO, default=None*/

5062

5063 /* Reserved */

5064 UINT32 Range2 : 3;

5065

5066 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5067

5068 /* Maps 16K addr range from A8000-ABFFF */

5069 UINT32 Rsvd19 : 5;

5070

5071 /* Bits[23:19], Access Type=RO, default=None*/

5072

5073 /* Reserved */

5074 UINT32 Range3 : 3;

5075

5076 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5077

5078 /* Maps 16K addr range from AC000-AFFFF */

5079 UINT32 Rsvd27 : 5;

5080

5081 /* Bits[31:27], Access Type=RO, default=None*/

5082

5083 /* Reserved */

5084 UINT32 Range4 : 3;

5085

5086 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5087

5088 /* Maps 16K addr range from B0000-B3FFF */

5089 UINT32 Rsvd35 : 5;

5090

5091 /* Bits[39:35], Access Type=RO, default=None*/

5092

5093 /* Reserved */

5094 UINT32 Range5 : 3;

5095

5096 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5097

5098 /* Maps 16K addr range from B4000-B7FFF */

5099 UINT32 Rsvd43 : 5;

5100

5101 /* Bits[47:43], Access Type=RO, default=None*/

5102

5103 /* Reserved */

5104 UINT32 Range6 : 3;

5105

5106 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5107

5108 /* Maps 16K addr range from B8000-BBFFF */

5109 UINT32 Rsvd51 : 5;

5110

5111 /* Bits[55:51], Access Type=RO, default=None*/

5112

5113 /* Reserved */

5114 UINT32 Range7 : 3;

5115

5116 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5117

5118 /* Maps 16K addr range from BC000-BFFFF */

5119 UINT32 Rsvd59 : 5;

5120

5121 /* Bits[63:59], Access Type=RO, default=None*/

5122

5123 /* Reserved */

5124

5125 } Bits;

5126

5127 UINT32 Uint32;

5128 UINT64 Uint64;

5129

5130 } MSR_MTRRFIX16KA_REGISTER;

5131

5132 /**

5133 Maps 32K address range from C0000H-C7FFFH

5134 **/

5135 #define MSR_MTRRFIX4KC0 0x00000268

5136

5137 typedef union {

5138 ///

5139 /// Individual bit fields

5140 ///

5141 struct {

5142 UINT32 Range0 : 3;

5143

5144 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5145

5146 /* Maps 16K addr range from C0000-C0FFF */

5147 UINT32 Rsvd3 : 5;

5148

5149 /* Bits[7:3], Access Type=RO, default=None*/

5150

5151 /* Reserved */

5152 UINT32 Range1 : 3;

5153

5154 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5155

5156 /* Maps 16K addr range from C1000-C1FFF */

5157 UINT32 Rsvd11 : 5;

5158

5159 /* Bits[15:11], Access Type=RO, default=None*/

5160

5161 /* Reserved */

5162 UINT32 Range2 : 3;

5163

5164 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5165

5166 /* Maps 16K addr range from C2000-C2FFF */

5167 UINT32 Rsvd19 : 5;

5168

5169 /* Bits[23:19], Access Type=RO, default=None*/

5170

5171 /* Reserved */

5172 UINT32 Range3 : 3;

5173

5174 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5175

5176 /* Maps 16K addr range from C3000-C3FFF */

5177 UINT32 Rsvd27 : 5;

5178

5179 /* Bits[31:27], Access Type=RO, default=None*/

5180

5181 /* Reserved */

5182 UINT32 Range4 : 3;

5183

5184 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5185

5186 /* Maps 16K addr range from C4000-C4FFF */

5187 UINT32 Rsvd35 : 5;

5188

5189 /* Bits[39:35], Access Type=RO, default=None*/

5190

5191 /* Reserved */

5192 UINT32 Range5 : 3;

5193

5194 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5195

5196 /* Maps 16K addr range from C5000-C5FFF */

5197 UINT32 Rsvd43 : 5;

5198

5199 /* Bits[47:43], Access Type=RO, default=None*/

5200

5201 /* Reserved */

5202 UINT32 Range6 : 3;

5203

5204 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5205

5206 /* Maps 16K addr range from C6000-C6FFF */

5207 UINT32 Rsvd51 : 5;

5208

5209 /* Bits[55:51], Access Type=RO, default=None*/

5210

5211 /* Reserved */

5212 UINT32 Range7 : 3;

5213

5214 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5215

5216 /* Maps 16K addr range from C7000-C7FFF */

5217 UINT32 Rsvd59 : 5;

5218

5219 /* Bits[63:59], Access Type=RO, default=None*/

5220

5221 /* Reserved */

5222

5223 } Bits;

5224

5225 UINT32 Uint32;

5226 UINT64 Uint64;

5227

5228 } MSR_MTRRFIX4KC0_REGISTER;

5229

5230 /**

5231 Maps 32K address range from C8000H-CFFFFH

5232 **/

5233 #define MSR_MTRRFIX4KC8 0x00000269

5234

5235 typedef union {

5236 ///

5237 /// Individual bit fields

5238 ///

5239 struct {

5240 UINT32 Range0 : 3;

5241

5242 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5243

5244 /* Maps 16K addr range from C8000-C8FFF */

5245 UINT32 Rsvd3 : 5;

5246

5247 /* Bits[7:3], Access Type=RO, default=None*/

5248

5249 /* Reserved */

5250 UINT32 Range1 : 3;

5251

5252 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5253

5254 /* Maps 16K addr range from C9000-C8FFF */

5255 UINT32 Rsvd11 : 5;

5256

5257 /* Bits[15:11], Access Type=RO, default=None*/

5258

5259 /* Reserved */

5260 UINT32 Range2 : 3;

5261

5262 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5263

5264 /* Maps 16K addr range from CA000-CAFFF */

5265 UINT32 Rsvd19 : 5;

5266

5267 /* Bits[23:19], Access Type=RO, default=None*/

5268

5269 /* Reserved */

5270 UINT32 Range3 : 3;

5271

5272 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5273

5274 /* Maps 16K addr range from CB000-CBFFF */

5275 UINT32 Rsvd27 : 5;

5276

5277 /* Bits[31:27], Access Type=RO, default=None*/

5278

5279 /* Reserved */

5280 UINT32 Range4 : 3;

5281

5282 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5283

5284 /* Maps 16K addr range from CC000-CCFFF */

5285 UINT32 Rsvd35 : 5;

5286

5287 /* Bits[39:35], Access Type=RO, default=None*/

5288

5289 /* Reserved */

5290 UINT32 Range5 : 3;

5291

5292 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5293

5294 /* Maps 16K addr range from CD000-CDFFF */

5295 UINT32 Rsvd43 : 5;

5296

5297 /* Bits[47:43], Access Type=RO, default=None*/

5298

5299 /* Reserved */

5300 UINT32 Range6 : 3;

5301

5302 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5303

5304 /* Maps 16K addr range from CE000-CEFFF */

5305 UINT32 Rsvd51 : 5;

5306

5307 /* Bits[55:51], Access Type=RO, default=None*/

5308

5309 /* Reserved */

5310 UINT32 Range7 : 3;

5311

5312 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5313

5314 /* Maps 16K addr range from CF000-CFFFF */

5315 UINT32 Rsvd59 : 5;

5316

5317 /* Bits[63:59], Access Type=RO, default=None*/

5318

5319 /* Reserved */

5320

5321 } Bits;

5322

5323 UINT32 Uint32;

5324 UINT64 Uint64;

5325

5326 } MSR_MTRRFIX4KC8_REGISTER;

5327

5328 /**

5329 Maps 32K address range from D0000H-D7FFFH

5330 **/

5331 #define MSR_MTRRFIX4KD0 0x0000026A

5332

5333 typedef union {

5334 ///

5335 /// Individual bit fields

5336 ///

5337 struct {

5338 UINT32 Range0 : 3;

5339

5340 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5341

5342 /* Maps 16K addr range from D0000-D0FFF */

5343 UINT32 Rsvd3 : 5;

5344

5345 /* Bits[7:3], Access Type=RO, default=None*/

5346

5347 /* Reserved */

5348 UINT32 Range1 : 3;

5349

5350 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5351

5352 /* Maps 16K addr range from D1000-D1FFF */

5353 UINT32 Rsvd11 : 5;

5354

5355 /* Bits[15:11], Access Type=RO, default=None*/

5356

5357 /* Reserved */

5358 UINT32 Range2 : 3;

5359

5360 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5361

5362 /* Maps 16K addr range from D2000-D2FFF */

5363 UINT32 Rsvd19 : 5;

5364

5365 /* Bits[23:19], Access Type=RO, default=None*/

5366

5367 /* Reserved */

5368 UINT32 Range3 : 3;

5369

5370 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5371

5372 /* Maps 16K addr range from D3000-D3FFF */

5373 UINT32 Rsvd27 : 5;

5374

5375 /* Bits[31:27], Access Type=RO, default=None*/

5376

5377 /* Reserved */

5378 UINT32 Range4 : 3;

5379

5380 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5381

5382 /* Maps 16K addr range from D4000-D4FFF */

5383 UINT32 Rsvd35 : 5;

5384

5385 /* Bits[39:35], Access Type=RO, default=None*/

5386

5387 /* Reserved */

5388 UINT32 Range5 : 3;

5389

5390 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5391

5392 /* Maps 16K addr range from D5000-D5FFF */

5393 UINT32 Rsvd43 : 5;

5394

5395 /* Bits[47:43], Access Type=RO, default=None*/

5396

5397 /* Reserved */

5398 UINT32 Range6 : 3;

5399

5400 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5401

5402 /* Maps 16K addr range from D6000-D6FFF */

5403 UINT32 Rsvd51 : 5;

5404

5405 /* Bits[55:51], Access Type=RO, default=None*/

5406

5407 /* Reserved */

5408 UINT32 Range7 : 3;

5409

5410 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5411

5412 /* Maps 16K addr range from D7000-D7FFF */

5413 UINT32 Rsvd59 : 5;

5414

5415 /* Bits[63:59], Access Type=RO, default=None*/

5416

5417 /* Reserved */

5418

5419 } Bits;

5420

5421 UINT32 Uint32;

5422 UINT64 Uint64;

5423

5424 } MSR_MTRRFIX4KD0_REGISTER;

5425

5426 /**

5427 Maps 32K address range from D8000H-DFFFFH

5428 **/

5429 #define MSR_MTRRFIX4KD8 0x0000026B

5430

5431 typedef union {

5432 ///

5433 /// Individual bit fields

5434 ///

5435 struct {

5436 UINT32 Range0 : 3;

5437

5438 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5439

5440 /* Maps 16K addr range from D8000-D8FFF */

5441 UINT32 Rsvd3 : 5;

5442

5443 /* Bits[7:3], Access Type=RO, default=None*/

5444

5445 /* Reserved */

5446 UINT32 Range1 : 3;

5447

5448 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5449

5450 /* Maps 16K addr range from D9000-D9FFF */

5451 UINT32 Rsvd11 : 5;

5452

5453 /* Bits[15:11], Access Type=RO, default=None*/

5454

5455 /* Reserved */

5456 UINT32 Range2 : 3;

5457

5458 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5459

5460 /* Maps 16K addr range from DA000-DAFFF */

5461 UINT32 Rsvd19 : 5;

5462

5463 /* Bits[23:19], Access Type=RO, default=None*/

5464

5465 /* Reserved */

5466 UINT32 Range3 : 3;

5467

5468 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5469

5470 /* Maps 16K addr range from DB000-DBFFF */

5471 UINT32 Rsvd27 : 5;

5472

5473 /* Bits[31:27], Access Type=RO, default=None*/

5474

5475 /* Reserved */

5476 UINT32 Range4 : 3;

5477

5478 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5479

5480 /* Maps 16K addr range from DC000-DCFFF */

5481 UINT32 Rsvd35 : 5;

5482

5483 /* Bits[39:35], Access Type=RO, default=None*/

5484

5485 /* Reserved */

5486 UINT32 Range5 : 3;

5487

5488 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5489

5490 /* Maps 16K addr range from DD000-DDFFF */

5491 UINT32 Rsvd43 : 5;

5492

5493 /* Bits[47:43], Access Type=RO, default=None*/

5494

5495 /* Reserved */

5496 UINT32 Range6 : 3;

5497

5498 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5499

5500 /* Maps 16K addr range from DE000-DEFFF */

5501 UINT32 Rsvd51 : 5;

5502

5503 /* Bits[55:51], Access Type=RO, default=None*/

5504

5505 /* Reserved */

5506 UINT32 Range7 : 3;

5507

5508 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5509

5510 /* Maps 16K addr range from DF000-DFFFF */

5511 UINT32 Rsvd59 : 5;

5512

5513 /* Bits[63:59], Access Type=RO, default=None*/

5514

5515 /* Reserved */

5516

5517 } Bits;

5518

5519 UINT32 Uint32;

5520 UINT64 Uint64;

5521

5522 } MSR_MTRRFIX4KD8_REGISTER;

5523

5524 /**

5525 Maps 32K address range from E0000H-E7FFFH

5526 **/

5527 #define MSR_MTRRFIX4KE0 0x0000026C

5528

5529 typedef union {

5530 ///

5531 /// Individual bit fields

5532 ///

5533 struct {

5534 UINT32 Range0 : 3;

5535

5536 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5537

5538 /* Maps 16K addr range from E0000-E0FFF */

5539 UINT32 Rsvd3 : 5;

5540

5541 /* Bits[7:3], Access Type=RO, default=None*/

5542

5543 /* Reserved */

5544 UINT32 Range1 : 3;

5545

5546 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5547

5548 /* Maps 16K addr range from E1000-E1FFF */

5549 UINT32 Rsvd11 : 5;

5550

5551 /* Bits[15:11], Access Type=RO, default=None*/

5552

5553 /* Reserved */

5554 UINT32 Range2 : 3;

5555

5556 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5557

5558 /* Maps 16K addr range from E2000-E2FFF */

5559 UINT32 Rsvd19 : 5;

5560

5561 /* Bits[23:19], Access Type=RO, default=None*/

5562

5563 /* Reserved */

5564 UINT32 Range3 : 3;

5565

5566 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5567

5568 /* Maps 16K addr range from E3000-E3FFF */

5569 UINT32 Rsvd27 : 5;

5570

5571 /* Bits[31:27], Access Type=RO, default=None*/

5572

5573 /* Reserved */

5574 UINT32 Range4 : 3;

5575

5576 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5577

5578 /* Maps 16K addr range from E4000-E4FFF */

5579 UINT32 Rsvd35 : 5;

5580

5581 /* Bits[39:35], Access Type=RO, default=None*/

5582

5583 /* Reserved */

5584 UINT32 Range5 : 3;

5585

5586 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5587

5588 /* Maps 16K addr range from E5000-E5FFF */

5589 UINT32 Rsvd43 : 5;

5590

5591 /* Bits[47:43], Access Type=RO, default=None*/

5592

5593 /* Reserved */

5594 UINT32 Range6 : 3;

5595

5596 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5597

5598 /* Maps 16K addr range from E6000-E6FFF */

5599 UINT32 Rsvd51 : 5;

5600

5601 /* Bits[55:51], Access Type=RO, default=None*/

5602

5603 /* Reserved */

5604 UINT32 Range7 : 3;

5605

5606 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5607

5608 /* Maps 16K addr range from E7000-E7FFF */

5609 UINT32 Rsvd59 : 5;

5610

5611 /* Bits[63:59], Access Type=RO, default=None*/

5612

5613 /* Reserved */

5614

5615 } Bits;

5616

5617 UINT32 Uint32;

5618 UINT64 Uint64;

5619

5620 } MSR_MTRRFIX4KE0_REGISTER;

5621

5622 /**

5623 Maps 32K address range from E8000H-EFFFFH

5624 **/

5625 #define MSR_MTRRFIX4KE8 0x0000026D

5626

5627 typedef union {

5628 ///

5629 /// Individual bit fields

5630 ///

5631 struct {

5632 UINT32 Range0 : 3;

5633

5634 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5635

5636 /* Maps 16K addr range from E8000-E8FFF */

5637 UINT32 Rsvd3 : 5;

5638

5639 /* Bits[7:3], Access Type=RO, default=None*/

5640

5641 /* Reserved */

5642 UINT32 Range1 : 3;

5643

5644 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5645

5646 /* Maps 16K addr range from E9000-E9FFF */

5647 UINT32 Rsvd11 : 5;

5648

5649 /* Bits[15:11], Access Type=RO, default=None*/

5650

5651 /* Reserved */

5652 UINT32 Range2 : 3;

5653

5654 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5655

5656 /* Maps 16K addr range from EA000-EAFFF */

5657 UINT32 Rsvd19 : 5;

5658

5659 /* Bits[23:19], Access Type=RO, default=None*/

5660

5661 /* Reserved */

5662 UINT32 Range3 : 3;

5663

5664 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5665

5666 /* Maps 16K addr range from EB000-EBFFF */

5667 UINT32 Rsvd27 : 5;

5668

5669 /* Bits[31:27], Access Type=RO, default=None*/

5670

5671 /* Reserved */

5672 UINT32 Range4 : 3;

5673

5674 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5675

5676 /* Maps 16K addr range from EC000-ECFFF */

5677 UINT32 Rsvd35 : 5;

5678

5679 /* Bits[39:35], Access Type=RO, default=None*/

5680

5681 /* Reserved */

5682 UINT32 Range5 : 3;

5683

5684 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5685

5686 /* Maps 16K addr range from ED000-EDFFF */

5687 UINT32 Rsvd43 : 5;

5688

5689 /* Bits[47:43], Access Type=RO, default=None*/

5690

5691 /* Reserved */

5692 UINT32 Range6 : 3;

5693

5694 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5695

5696 /* Maps 16K addr range from EE000-EEFFF */

5697 UINT32 Rsvd51 : 5;

5698

5699 /* Bits[55:51], Access Type=RO, default=None*/

5700

5701 /* Reserved */

5702 UINT32 Range7 : 3;

5703

5704 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5705

5706 /* Maps 16K addr range from EF000-EFFFF */

5707 UINT32 Rsvd59 : 5;

5708

5709 /* Bits[63:59], Access Type=RO, default=None*/

5710

5711 /* Reserved */

5712

5713 } Bits;

5714

5715 UINT32 Uint32;

5716 UINT64 Uint64;

5717

5718 } MSR_MTRRFIX4KE8_REGISTER;

5719

5720 /**

5721 Maps 32K address range from F0000H-F7FFFH

5722 **/

5723 #define MSR_MTRRFIX4KF0 0x0000026E

5724

5725 typedef union {

5726 ///

5727 /// Individual bit fields

5728 ///

5729 struct {

5730 UINT32 Range0 : 3;

5731

5732 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5733

5734 /* Maps 16K addr range from F0000-F0FFF */

5735 UINT32 Rsvd3 : 5;

5736

5737 /* Bits[7:3], Access Type=RO, default=None*/

5738

5739 /* Reserved */

5740 UINT32 Range1 : 3;

5741

5742 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5743

5744 /* Maps 16K addr range from F1000-F1FFF */

5745 UINT32 Rsvd11 : 5;

5746

5747 /* Bits[15:11], Access Type=RO, default=None*/

5748

5749 /* Reserved */

5750 UINT32 Range2 : 3;

5751

5752 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5753

5754 /* Maps 16K addr range from F2000-F2FFF */

5755 UINT32 Rsvd19 : 5;

5756

5757 /* Bits[23:19], Access Type=RO, default=None*/

5758

5759 /* Reserved */

5760 UINT32 Range3 : 3;

5761

5762 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5763

5764 /* Maps 16K addr range from F3000-F3FFF */

5765 UINT32 Rsvd27 : 5;

5766

5767 /* Bits[31:27], Access Type=RO, default=None*/

5768

5769 /* Reserved */

5770 UINT32 Range4 : 3;

5771

5772 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5773

5774 /* Maps 16K addr range from F4000-F4FFF */

5775 UINT32 Rsvd35 : 5;

5776

5777 /* Bits[39:35], Access Type=RO, default=None*/

5778

5779 /* Reserved */

5780 UINT32 Range5 : 3;

5781

5782 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5783

5784 /* Maps 16K addr range from F5000-F5FFF */

5785 UINT32 Rsvd43 : 5;

5786

5787 /* Bits[47:43], Access Type=RO, default=None*/

5788

5789 /* Reserved */

5790 UINT32 Range6 : 3;

5791

5792 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5793

5794 /* Maps 16K addr range from F6000-F6FFF */

5795 UINT32 Rsvd51 : 5;

5796

5797 /* Bits[55:51], Access Type=RO, default=None*/

5798

5799 /* Reserved */

5800 UINT32 Range7 : 3;

5801

5802 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5803

5804 /* Maps 16K addr range from F7000-F7FFF */

5805 UINT32 Rsvd59 : 5;

5806

5807 /* Bits[63:59], Access Type=RO, default=None*/

5808

5809 /* Reserved */

5810

5811 } Bits;

5812

5813 UINT32 Uint32;

5814 UINT64 Uint64;

5815

5816 } MSR_MTRRFIX4KF0_REGISTER;

5817

5818 /**

5819 Maps 32K address range from F8000H-FFFFFH

5820 **/

5821 #define MSR_MTRRFIX4KF8 0x0000026F

5822

5823 typedef union {

5824 ///

5825 /// Individual bit fields

5826 ///

5827 struct {

5828 UINT32 Range0 : 3;

5829

5830 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5831

5832 /* Maps 16K addr range from F8000-F8FFF */

5833 UINT32 Rsvd3 : 5;

5834

5835 /* Bits[7:3], Access Type=RO, default=None*/

5836

5837 /* Reserved */

5838 UINT32 Range1 : 3;

5839

5840 /* Bits[10:8], Access Type=RW, default=0x00000000*/

5841

5842 /* Maps 16K addr range from F9000-F9FFF */

5843 UINT32 Rsvd11 : 5;

5844

5845 /* Bits[15:11], Access Type=RO, default=None*/

5846

5847 /* Reserved */

5848 UINT32 Range2 : 3;

5849

5850 /* Bits[18:16], Access Type=RW, default=0x00000000*/

5851

5852 /* Maps 16K addr range from FA000-FAFFF */

5853 UINT32 Rsvd19 : 5;

5854

5855 /* Bits[23:19], Access Type=RO, default=None*/

5856

5857 /* Reserved */

5858 UINT32 Range3 : 3;

5859

5860 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5861

5862 /* Maps 16K addr range from FB000-FBFFF */

5863 UINT32 Rsvd27 : 5;

5864

5865 /* Bits[31:27], Access Type=RO, default=None*/

5866

5867 /* Reserved */

5868 UINT32 Range4 : 3;

5869

5870 /* Bits[34:32], Access Type=RW, default=0x00000000*/

5871

5872 /* Maps 16K addr range from FC000-FCFFF */

5873 UINT32 Rsvd35 : 5;

5874

5875 /* Bits[39:35], Access Type=RO, default=None*/

5876

5877 /* Reserved */

5878 UINT32 Range5 : 3;

5879

5880 /* Bits[42:40], Access Type=RW, default=0x00000000*/

5881

5882 /* Maps 16K addr range from FD000-FDFFF */

5883 UINT32 Rsvd43 : 5;

5884

5885 /* Bits[47:43], Access Type=RO, default=None*/

5886

5887 /* Reserved */

5888 UINT32 Range6 : 3;

5889

5890 /* Bits[50:48], Access Type=RW, default=0x00000000*/

5891

5892 /* Maps 16K addr range from FE000-FEFFF */

5893 UINT32 Rsvd51 : 5;

5894

5895 /* Bits[55:51], Access Type=RO, default=None*/

5896

5897 /* Reserved */

5898 UINT32 Range7 : 3;

5899

5900 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5901

5902 /* Maps 16K addr range from FF000-FFFFF */

5903 UINT32 Rsvd59 : 5;

5904

5905 /* Bits[63:59], Access Type=RO, default=None*/

5906

5907 /* Reserved */

5908

5909 } Bits;

5910

5911 UINT32 Uint32;

5912 UINT64 Uint64;

5913

5914 } MSR_MTRRFIX4KF8_REGISTER;

5915

5916 /**

5917 PAT memtypes register. 8 seperate entries

5918 **/

5919 #define MSR_PAT 0x00000277

5920

5921 typedef union {

5922 ///

5923 /// Individual bit fields

5924 ///

5925 struct {

5926 UINT32 Entry0 : 3;

5927

5928 /* Bits[2:0], Access Type=RW, default=0x00000006*/

5929

5930 /* PAT Memtype entry-0 */

5931 UINT32 Rsvd3 : 5;

5932

5933 /* Bits[7:3], Access Type=RO, default=None*/

5934

5935 /* Reserved */

5936 UINT32 Entry1 : 3;

5937

5938 /* Bits[10:8], Access Type=RW, default=0x00000004*/

5939

5940 /* PAT Memtype entry-1 */

5941 UINT32 Rsvd11 : 5;

5942

5943 /* Bits[15:11], Access Type=RO, default=None*/

5944

5945 /* Reserved */

5946 UINT32 Entry2 : 3;

5947

5948 /* Bits[18:16], Access Type=RW, default=0x00000007*/

5949

5950 /* PAT Memtype entry-2 */

5951 UINT32 Rsvd19 : 5;

5952

5953 /* Bits[23:19], Access Type=RO, default=None*/

5954

5955 /* Reserved */

5956 UINT32 Entry3 : 3;

5957

5958 /* Bits[26:24], Access Type=RW, default=0x00000000*/

5959

5960 /* PAT Memtype entry-3 */

5961 UINT32 Rsvd27 : 5;

5962

5963 /* Bits[31:27], Access Type=RO, default=None*/

5964

5965 /* Reserved */

5966 UINT32 Entry4 : 3;

5967

5968 /* Bits[34:32], Access Type=RW, default=0x00000006*/

5969

5970 /* PAT Memtype entry-4 */

5971 UINT32 Rsvd35 : 5;

5972

5973 /* Bits[39:35], Access Type=RO, default=None*/

5974

5975 /* Reserved */

5976 UINT32 Entry5 : 3;

5977

5978 /* Bits[42:40], Access Type=RW, default=0x00000004*/

5979

5980 /* PAT Memtype entry-5 */

5981 UINT32 Rsvd43 : 5;

5982

5983 /* Bits[47:43], Access Type=RO, default=None*/

5984

5985 /* Reserved */

5986 UINT32 Entry6 : 3;

5987

5988 /* Bits[50:48], Access Type=RW, default=0x00000007*/

5989

5990 /* PAT Memtype entry-6 */

5991 UINT32 Rsvd51 : 5;

5992

5993 /* Bits[55:51], Access Type=RO, default=None*/

5994

5995 /* Reserved */

5996 UINT32 Entry7 : 3;

5997

5998 /* Bits[58:56], Access Type=RW, default=0x00000000*/

5999

6000 /* PAT Memtype entry-7 */

6001 UINT32 Rsvd59 : 5;

6002

6003 /* Bits[63:59], Access Type=RO, default=None*/

6004

6005 /* Reserved */

6006

6007 } Bits;

6008

6009 UINT32 Uint32;

6010 UINT64 Uint64;

6011

6012 } MSR_PAT_REGISTER;

6013

6014 /**

6015 Machine Check CTL2 Register

6016 **/

6017 #define MSR_MC0_MISC2 0x00000280

6018

6019 typedef union {

6020 ///

6021 /// Individual bit fields

6022 ///

6023 struct {

6024 UINT32 CorrectedErrThrsh : 15;

6025

6026 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6027

6028 /* corrected error count threshold */

6029 UINT32 Rsvd15 : 15;

6030

6031 /* Bits[29:15], Access Type=RO, default=None*/

6032

6033 /* Reserved */

6034 UINT32 CorrectedErrEn : 1;

6035

6036 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6037

6038 /* Corrected error interupt enable/disable */

6039 UINT32 Rsvd31 : 1;

6040

6041 /* Bits[31:31], Access Type=RO, default=None*/

6042

6043 /* Reserved */

6044 UINT32 CmciCtl : 1;

6045

6046 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6047

6048 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6049 UINT32 Rsvd33 : 1;

6050

6051 /* Bits[33:33], Access Type=RO, default=None*/

6052

6053 /* Reserved */

6054 UINT32 MceCtl : 1;

6055

6056 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6057

6058 /* Controls MCE Remapping 0 MCE 1 MSMI */

6059 UINT32 Rsvd35 : 29;

6060

6061 /* Bits[63:35], Access Type=RO, default=None*/

6062

6063 /* Reserved */

6064

6065 } Bits;

6066

6067 UINT32 Uint32;

6068 UINT64 Uint64;

6069

6070 } MSR_MC0_MISC2_REGISTER;

6071

6072 /**

6073 Machine Check CTL2 Register

6074 **/

6075 #define MSR_MC1_MISC2 0x00000281

6076

6077 typedef union {

6078 ///

6079 /// Individual bit fields

6080 ///

6081 struct {

6082 UINT32 Cet : 15;

6083

6084 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6085

6086 /*

6087 Correctable error threshold selects the

6088 threshold at which the corrected error count

6089 logged in the status register will signal an

6090 interrupt

6091 */

6092 UINT32 Reserved15 : 15;

6093

6094 /* Bits[29:15], Access Type=WO, default=0x00000000*/

6095

6096 /*

6097 All the RESERVED bits described here are not

6098 implemented in the DCU. They can be hardwired to

6099 0s

6100 */

6101 UINT32 E : 1;

6102

6103 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6104

6105 /* The corrected error threshold enable/disable bit */

6106 UINT32 Reserved31 : 1;

6107

6108 /* Bits[31:31], Access Type=WO, default=0x00000000*/

6109

6110 /*

6111 All the RESERVED bits described here are not

6112 implemented in the DCU. They can be hardwired to

6113 0s.

6114 */

6115 UINT32 CmciCtl : 1;

6116

6117 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6118

6119 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6120 UINT32 Rsvd33 : 1;

6121

6122 /* Bits[33:33], Access Type=RO, default=None*/

6123

6124 /* Reserved */

6125 UINT32 MceCtl : 1;

6126

6127 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6128

6129 /* Controls MCE Remapping 0 MCE 1 MSMI */

6130 UINT32 Rsvd35 : 1;

6131

6132 /* Bits[35:35], Access Type=RO, default=None*/

6133

6134 /* Reserved */

6135 UINT32 Reserved36 : 28;

6136

6137 /* Bits[63:36], Access Type=WO, default=0x00000000*/

6138

6139 /*

6140 All the RESERVED bits described here are not

6141 implemented in the DCU. They can be hardwired to

6142 0s.

6143 */

6144

6145 } Bits;

6146

6147 UINT32 Uint32;

6148 UINT64 Uint64;

6149

6150 } MSR_MC1_MISC2_REGISTER;

6151

6152 /**

6153 Machine Check CTL2 Register

6154 **/

6155 #define MSR_MC2_MISC2 0x00000282

6156

6157 typedef union {

6158 ///

6159 /// Individual bit fields

6160 ///

6161 struct {

6162 UINT32 CorErrThres : 15;

6163

6164 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6165

6166 /* Correctable error count threshold */

6167 UINT32 Reserved15 : 15;

6168

6169 /* Bits[29:15], Access Type=RW, default=None*/

6170

6171 /*

6172 Unimplemented - will return all '0s when read.

6173 writes will be dropped on the floor

6174 */

6175 UINT32 CmciEn : 1;

6176

6177 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6178

6179 /* CMCI Enable */

6180 UINT32 Rsvd31 : 1;

6181

6182 /* Bits[31:31], Access Type=RO, default=None*/

6183

6184 /* Reserved */

6185 UINT32 CmciCtl : 1;

6186

6187 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6188

6189 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6190 UINT32 Rsvd33 : 1;

6191

6192 /* Bits[33:33], Access Type=RO, default=None*/

6193

6194 /* Reserved */

6195 UINT32 MceCtl : 1;

6196

6197 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6198

6199 /* Controls MCE Remapping 0 MCE 1 MSMI */

6200 UINT32 Rsvd35 : 29;

6201

6202 /* Bits[63:35], Access Type=RO, default=None*/

6203

6204 /* Reserved */

6205

6206 } Bits;

6207

6208 UINT32 Uint32;

6209 UINT64 Uint64;

6210

6211 } MSR_MC2_MISC2_REGISTER;

6212

6213 /**

6214 Machine Check CTL2 Register

6215 **/

6216 #define MSR_MC3_MISC2 0x00000283

6217

6218 typedef union {

6219 ///

6220 /// Individual bit fields

6221 ///

6222 struct {

6223 UINT32 Cet : 15;

6224

6225 /* Bits[14:0], Access Type=RW, default=None*/

6226

6227 /*

6228 The default value for the corrected error

6229 threshold bits is 0. Software can set a

6230 threshold value by writing to this field.

6231 */

6232 UINT32 ReservedBits15 : 15;

6233

6234 /* Bits[29:15], Access Type=RW, default=None*/

6235

6236 /* Reserved bits not implemented */

6237 UINT32 En : 1;

6238

6239 /* Bits[30:30], Access Type=RW, default=None*/

6240

6241 /*

6242 The EN bit is set by software to enable the

6243 generation of corrected error threshold

6244 interrupts corrected error threshold

6245 */

6246 UINT32 ReservedBit31 : 1;

6247

6248 /* Bits[31:31], Access Type=RW, default=None*/

6249

6250 /* Reserved bits not implemented */

6251 UINT32 CmciCtl : 1;

6252

6253 /* Bits[32:32], Access Type=RW, default=None*/

6254

6255 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6256 UINT32 Rsvd33 : 1;

6257

6258 /* Bits[33:33], Access Type=RO, default=None*/

6259

6260 /* Reserved */

6261 UINT32 MceCtl : 1;

6262

6263 /* Bits[34:34], Access Type=RW, default=None*/

6264

6265 /* Controls MCE Remapping 0 MCE 1 MSMI */

6266 UINT32 Rsvd35 : 29;

6267

6268 /* Bits[63:35], Access Type=RO, default=None*/

6269

6270 /* Reserved */

6271

6272 } Bits;

6273

6274 UINT32 Uint32;

6275 UINT64 Uint64;

6276

6277 } MSR_MC3_MISC2_REGISTER;

6278

6279 /**

6280 IA32_MEE_MC_CTL2 MC MSR aliased to IA32_PCU5_MC_CTL2

6281 **/

6282 #define MSR_MC4_CTL2 0x00000284

6283

6284 typedef union {

6285 ///

6286 /// Individual bit fields

6287 ///

6288 struct {

6289 UINT32 Threshold : 15;

6290

6291 /* Bits[14:0], Access Type=RO, default=0x00000000*/

6292

6293 /* */

6294 UINT32 Rsvd15 : 15;

6295

6296 /* Bits[29:15], Access Type=RO, default=None*/

6297

6298 /* Reserved */

6299 UINT32 Enable : 1;

6300

6301 /* Bits[30:30], Access Type=RO, default=0x00000000*/

6302

6303 /* */

6304 UINT32 Rsvd31 : 1;

6305

6306 /* Bits[31:31], Access Type=RO, default=None*/

6307

6308 /* Reserved */

6309 UINT32 CmciCtl : 1;

6310

6311 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6312

6313 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6314 UINT32 Rsvd33 : 1;

6315

6316 /* Bits[33:33], Access Type=RO, default=None*/

6317

6318 /* Reserved */

6319 UINT32 MceCtl : 1;

6320

6321 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6322

6323 /* Controls MCE Remapping 0 MCE 1 MSMI */

6324 UINT32 Rsvd35 : 29;

6325

6326 /* Bits[63:35], Access Type=RO, default=None*/

6327

6328 /* Reserved */

6329

6330 } Bits;

6331

6332 UINT32 Uint32;

6333 UINT64 Uint64;

6334

6335 } MSR_MC4_CTL2_REGISTER;

6336

6337 /**

6338 Machine check CTL2 MSR

6339 **/

6340 #define MSR_MC5_CTL2 0x00000285

6341

6342 typedef union {

6343 ///

6344 /// Individual bit fields

6345 ///

6346 struct {

6347 UINT32 Threshold : 15;

6348

6349 /* Bits[14:0], Access Type=RO, default=0x00000000*/

6350

6351 /* */

6352 UINT32 Rsvd15 : 15;

6353

6354 /* Bits[29:15], Access Type=RO, default=None*/

6355

6356 /* Reserved */

6357 UINT32 Enable : 1;

6358

6359 /* Bits[30:30], Access Type=RO, default=0x00000000*/

6360

6361 /* */

6362 UINT32 Rsvd31 : 1;

6363

6364 /* Bits[31:31], Access Type=RO, default=None*/

6365

6366 /* Reserved */

6367 UINT32 CmciCtl : 1;

6368

6369 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6370

6371 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6372 UINT32 Rsvd33 : 1;

6373

6374 /* Bits[33:33], Access Type=RO, default=None*/

6375

6376 /* Reserved */

6377 UINT32 MceCtl : 1;

6378

6379 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6380

6381 /* Controls MCE Remapping 0 MCE 1 MSMI */

6382 UINT32 Rsvd35 : 29;

6383

6384 /* Bits[63:35], Access Type=RO, default=None*/

6385

6386 /* Reserved */

6387

6388 } Bits;

6389

6390 UINT32 Uint32;

6391 UINT64 Uint64;

6392

6393 } MSR_MC5_CTL2_REGISTER;

6394

6395 /**

6396 Machine Check CTL2 Register

6397 **/

6398 #define MSR_MC6_CTL2 0x00000286

6399

6400 typedef union {

6401 ///

6402 /// Individual bit fields

6403 ///

6404 struct {

6405 UINT32 Threshold : 15;

6406

6407 /* Bits[14:0], Access Type=RO, default=0x00000000*/

6408

6409 /* */

6410 UINT32 Rsvd15 : 15;

6411

6412 /* Bits[29:15], Access Type=RO, default=None*/

6413

6414 /* Reserved */

6415 UINT32 Enable : 1;

6416

6417 /* Bits[30:30], Access Type=RO, default=0x00000000*/

6418

6419 /* */

6420 UINT32 Rsvd31 : 1;

6421

6422 /* Bits[31:31], Access Type=RO, default=None*/

6423

6424 /* Reserved */

6425 UINT32 CmciCtl : 1;

6426

6427 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6428

6429 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6430 UINT32 Rsvd33 : 1;

6431

6432 /* Bits[33:33], Access Type=RO, default=None*/

6433

6434 /* Reserved */

6435 UINT32 MceCtl : 1;

6436

6437 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6438

6439 /* Controls MCE Remapping 0 MCE 1 MSMI */

6440 UINT32 Rsvd35 : 29;

6441

6442 /* Bits[63:35], Access Type=RO, default=None*/

6443

6444 /* Reserved */

6445

6446 } Bits;

6447

6448 UINT32 Uint32;

6449 UINT64 Uint64;

6450

6451 } MSR_MC6_CTL2_REGISTER;

6452

6453 /**

6454 LLC MCA bank: Control 2 register

6455 **/

6456 #define MSR_MC7_CTL2 0x00000287

6457

6458 typedef union {

6459 ///

6460 /// Individual bit fields

6461 ///

6462 struct {

6463 UINT32 CorCntrThreshold : 15;

6464

6465 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6466

6467 /* Corrected Error Counter Threshold */

6468 UINT32 Rsvd15 : 15;

6469

6470 /* Bits[29:15], Access Type=RO, default=None*/

6471

6472 /* Reserved */

6473 UINT32 En : 1;

6474

6475 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6476

6477 /* EN: Enable corrected error interrupts */

6478 UINT32 Rsvd31 : 1;

6479

6480 /* Bits[31:31], Access Type=RO, default=None*/

6481

6482 /* Reserved */

6483 UINT32 CmciCtl : 1;

6484

6485 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6486

6487 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6488 UINT32 Rsvd33 : 1;

6489

6490 /* Bits[33:33], Access Type=RO, default=None*/

6491

6492 /* Reserved */

6493 UINT32 MceCtl : 1;

6494

6495 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6496

6497 /* Controls MCE Remapping 0 MCE 1 MSMI */

6498 UINT32 Rsvd35 : 29;

6499

6500 /* Bits[63:35], Access Type=RO, default=None*/

6501

6502 /* Reserved */

6503

6504 } Bits;

6505

6506 UINT32 Uint32;

6507 UINT64 Uint64;

6508

6509 } MSR_MC7_CTL2_REGISTER;

6510

6511 /**

6512 LLC MCA bank: Control 2 register

6513 **/

6514 #define MSR_MC8_CTL2 0x00000288

6515

6516 typedef union {

6517 ///

6518 /// Individual bit fields

6519 ///

6520 struct {

6521 UINT32 CorCntrThreshold : 15;

6522

6523 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6524

6525 /* Corrected Error Counter Threshold */

6526 UINT32 Rsvd15 : 15;

6527

6528 /* Bits[29:15], Access Type=RO, default=None*/

6529

6530 /* Reserved */

6531 UINT32 En : 1;

6532

6533 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6534

6535 /* EN: Enable corrected error interrupts */

6536 UINT32 Rsvd31 : 1;

6537

6538 /* Bits[31:31], Access Type=RO, default=None*/

6539

6540 /* Reserved */

6541 UINT32 CmciCtl : 1;

6542

6543 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6544

6545 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6546 UINT32 Rsvd33 : 1;

6547

6548 /* Bits[33:33], Access Type=RO, default=None*/

6549

6550 /* Reserved */

6551 UINT32 MceCtl : 1;

6552

6553 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6554

6555 /* Controls MCE Remapping 0 MCE 1 MSMI */

6556 UINT32 Rsvd35 : 29;

6557

6558 /* Bits[63:35], Access Type=RO, default=None*/

6559

6560 /* Reserved */

6561

6562 } Bits;

6563

6564 UINT32 Uint32;

6565 UINT64 Uint64;

6566

6567 } MSR_MC8_CTL2_REGISTER;

6568

6569 /**

6570 LLC MCA bank: Control 2 register

6571 **/

6572 #define MSR_MC9_CTL2 0x00000289

6573

6574 typedef union {

6575 ///

6576 /// Individual bit fields

6577 ///

6578 struct {

6579 UINT32 CorCntrThreshold : 15;

6580

6581 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6582

6583 /* Corrected Error Counter Threshold */

6584 UINT32 Rsvd15 : 15;

6585

6586 /* Bits[29:15], Access Type=RO, default=None*/

6587

6588 /* Reserved */

6589 UINT32 En : 1;

6590

6591 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6592

6593 /* EN: Enable corrected error interrupts */

6594 UINT32 Rsvd31 : 1;

6595

6596 /* Bits[31:31], Access Type=RO, default=None*/

6597

6598 /* Reserved */

6599 UINT32 CmciCtl : 1;

6600

6601 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6602

6603 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6604 UINT32 Rsvd33 : 1;

6605

6606 /* Bits[33:33], Access Type=RO, default=None*/

6607

6608 /* Reserved */

6609 UINT32 MceCtl : 1;

6610

6611 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6612

6613 /* Controls MCE Remapping 0 MCE 1 MSMI */

6614 UINT32 Rsvd35 : 29;

6615

6616 /* Bits[63:35], Access Type=RO, default=None*/

6617

6618 /* Reserved */

6619

6620 } Bits;

6621

6622 UINT32 Uint32;

6623 UINT64 Uint64;

6624

6625 } MSR_MC9_CTL2_REGISTER;

6626

6627 /**

6628 LLC MCA bank: Control 2 register

6629 **/

6630 #define MSR_MC10_CTL2 0x0000028A

6631

6632 typedef union {

6633 ///

6634 /// Individual bit fields

6635 ///

6636 struct {

6637 UINT32 CorCntrThreshold : 15;

6638

6639 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6640

6641 /* Corrected Error Counter Threshold */

6642 UINT32 Rsvd15 : 15;

6643

6644 /* Bits[29:15], Access Type=RO, default=None*/

6645

6646 /* Reserved */

6647 UINT32 En : 1;

6648

6649 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6650

6651 /* EN: Enable corrected error interrupts */

6652 UINT32 Rsvd31 : 1;

6653

6654 /* Bits[31:31], Access Type=RO, default=None*/

6655

6656 /* Reserved */

6657 UINT32 CmciCtl : 1;

6658

6659 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6660

6661 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6662 UINT32 Rsvd33 : 1;

6663

6664 /* Bits[33:33], Access Type=RO, default=None*/

6665

6666 /* Reserved */

6667 UINT32 MceCtl : 1;

6668

6669 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6670

6671 /* Controls MCE Remapping 0 MCE 1 MSMI */

6672 UINT32 Rsvd35 : 29;

6673

6674 /* Bits[63:35], Access Type=RO, default=None*/

6675

6676 /* Reserved */

6677

6678 } Bits;

6679

6680 UINT32 Uint32;

6681 UINT64 Uint64;

6682

6683 } MSR_MC10_CTL2_REGISTER;

6684

6685 /**

6686 LLC MCA bank: Control 2 register

6687 **/

6688 #define MSR_MC11_CTL2 0x0000028B

6689

6690 typedef union {

6691 ///

6692 /// Individual bit fields

6693 ///

6694 struct {

6695 UINT32 CorCntrThreshold : 15;

6696

6697 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6698

6699 /* Corrected Error Counter Threshold */

6700 UINT32 Rsvd15 : 15;

6701

6702 /* Bits[29:15], Access Type=RO, default=None*/

6703

6704 /* Reserved */

6705 UINT32 En : 1;

6706

6707 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6708

6709 /* EN: Enable corrected error interrupts */

6710 UINT32 Rsvd31 : 1;

6711

6712 /* Bits[31:31], Access Type=RO, default=None*/

6713

6714 /* Reserved */

6715 UINT32 CmciCtl : 1;

6716

6717 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6718

6719 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6720 UINT32 Rsvd33 : 1;

6721

6722 /* Bits[33:33], Access Type=RO, default=None*/

6723

6724 /* Reserved */

6725 UINT32 MceCtl : 1;

6726

6727 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6728

6729 /* Controls MCE Remapping 0 MCE 1 MSMI */

6730 UINT32 Rsvd35 : 29;

6731

6732 /* Bits[63:35], Access Type=RO, default=None*/

6733

6734 /* Reserved */

6735

6736 } Bits;

6737

6738 UINT32 Uint32;

6739 UINT64 Uint64;

6740

6741 } MSR_MC11_CTL2_REGISTER;

6742

6743 /**

6744 LLC MCA bank: Control 2 register

6745 **/

6746 #define MSR_MC12_CTL2 0x0000028C

6747

6748 typedef union {

6749 ///

6750 /// Individual bit fields

6751 ///

6752 struct {

6753 UINT32 CorCntrThreshold : 15;

6754

6755 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6756

6757 /* Corrected Error Counter Threshold */

6758 UINT32 Rsvd15 : 15;

6759

6760 /* Bits[29:15], Access Type=RO, default=None*/

6761

6762 /* Reserved */

6763 UINT32 En : 1;

6764

6765 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6766

6767 /* EN: Enable corrected error interrupts */

6768 UINT32 Rsvd31 : 1;

6769

6770 /* Bits[31:31], Access Type=RO, default=None*/

6771

6772 /* Reserved */

6773 UINT32 CmciCtl : 1;

6774

6775 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6776

6777 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6778 UINT32 Rsvd33 : 1;

6779

6780 /* Bits[33:33], Access Type=RO, default=None*/

6781

6782 /* Reserved */

6783 UINT32 MceCtl : 1;

6784

6785 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6786

6787 /* Controls MCE Remapping 0 MCE 1 MSMI */

6788 UINT32 Rsvd35 : 29;

6789

6790 /* Bits[63:35], Access Type=RO, default=None*/

6791

6792 /* Reserved */

6793

6794 } Bits;

6795

6796 UINT32 Uint32;

6797 UINT64 Uint64;

6798

6799 } MSR_MC12_CTL2_REGISTER;

6800

6801 /**

6802 LLC MCA bank: Control 2 register

6803 **/

6804 #define MSR_MC13_CTL2 0x0000028D

6805

6806 typedef union {

6807 ///

6808 /// Individual bit fields

6809 ///

6810 struct {

6811 UINT32 CorCntrThreshold : 15;

6812

6813 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6814

6815 /* Corrected Error Counter Threshold */

6816 UINT32 Rsvd15 : 15;

6817

6818 /* Bits[29:15], Access Type=RO, default=None*/

6819

6820 /* Reserved */

6821 UINT32 En : 1;

6822

6823 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6824

6825 /* EN: Enable corrected error interrupts */

6826 UINT32 Rsvd31 : 1;

6827

6828 /* Bits[31:31], Access Type=RO, default=None*/

6829

6830 /* Reserved */

6831 UINT32 CmciCtl : 1;

6832

6833 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6834

6835 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6836 UINT32 Rsvd33 : 1;

6837

6838 /* Bits[33:33], Access Type=RO, default=None*/

6839

6840 /* Reserved */

6841 UINT32 MceCtl : 1;

6842

6843 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6844

6845 /* Controls MCE Remapping 0 MCE 1 MSMI */

6846 UINT32 Rsvd35 : 29;

6847

6848 /* Bits[63:35], Access Type=RO, default=None*/

6849

6850 /* Reserved */

6851

6852 } Bits;

6853

6854 UINT32 Uint32;

6855 UINT64 Uint64;

6856

6857 } MSR_MC13_CTL2_REGISTER;

6858

6859 /**

6860 LLC MCA bank: Control 2 register

6861 **/

6862 #define MSR_MC14_CTL2 0x0000028E

6863

6864 typedef union {

6865 ///

6866 /// Individual bit fields

6867 ///

6868 struct {

6869 UINT32 CorCntrThreshold : 15;

6870

6871 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6872

6873 /* Corrected Error Counter Threshold */

6874 UINT32 Rsvd15 : 15;

6875

6876 /* Bits[29:15], Access Type=RO, default=None*/

6877

6878 /* Reserved */

6879 UINT32 En : 1;

6880

6881 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6882

6883 /* EN: Enable corrected error interrupts */

6884 UINT32 Rsvd31 : 1;

6885

6886 /* Bits[31:31], Access Type=RO, default=None*/

6887

6888 /* Reserved */

6889 UINT32 CmciCtl : 1;

6890

6891 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6892

6893 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6894 UINT32 Rsvd33 : 1;

6895

6896 /* Bits[33:33], Access Type=RO, default=None*/

6897

6898 /* Reserved */

6899 UINT32 MceCtl : 1;

6900

6901 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6902

6903 /* Controls MCE Remapping 0 MCE 1 MSMI */

6904 UINT32 Rsvd35 : 29;

6905

6906 /* Bits[63:35], Access Type=RO, default=None*/

6907

6908 /* Reserved */

6909

6910 } Bits;

6911

6912 UINT32 Uint32;

6913 UINT64 Uint64;

6914

6915 } MSR_MC14_CTL2_REGISTER;

6916

6917 /**

6918 LLC MCA bank: Control 2 register

6919 **/

6920 #define MSR_MC15_CTL2 0x0000028F

6921

6922 typedef union {

6923 ///

6924 /// Individual bit fields

6925 ///

6926 struct {

6927 UINT32 CorCntrThreshold : 15;

6928

6929 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6930

6931 /* Corrected Error Counter Threshold */

6932 UINT32 Rsvd15 : 15;

6933

6934 /* Bits[29:15], Access Type=RO, default=None*/

6935

6936 /* Reserved */

6937 UINT32 En : 1;

6938

6939 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6940

6941 /* EN: Enable corrected error interrupts */

6942 UINT32 Rsvd31 : 1;

6943

6944 /* Bits[31:31], Access Type=RO, default=None*/

6945

6946 /* Reserved */

6947 UINT32 CmciCtl : 1;

6948

6949 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6950

6951 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

6952 UINT32 Rsvd33 : 1;

6953

6954 /* Bits[33:33], Access Type=RO, default=None*/

6955

6956 /* Reserved */

6957 UINT32 MceCtl : 1;

6958

6959 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6960

6961 /* Controls MCE Remapping 0 MCE 1 MSMI */

6962 UINT32 Rsvd35 : 29;

6963

6964 /* Bits[63:35], Access Type=RO, default=None*/

6965

6966 /* Reserved */

6967

6968 } Bits;

6969

6970 UINT32 Uint32;

6971 UINT64 Uint64;

6972

6973 } MSR_MC15_CTL2_REGISTER;

6974

6975 /**

6976 LLC MCA bank: Control 2 register

6977 **/

6978 #define MSR_MC16_CTL2 0x00000290

6979

6980 typedef union {

6981 ///

6982 /// Individual bit fields

6983 ///

6984 struct {

6985 UINT32 CorCntrThreshold : 15;

6986

6987 /* Bits[14:0], Access Type=RW, default=0x00000000*/

6988

6989 /* Corrected Error Counter Threshold */

6990 UINT32 Rsvd15 : 15;

6991

6992 /* Bits[29:15], Access Type=RO, default=None*/

6993

6994 /* Reserved */

6995 UINT32 En : 1;

6996

6997 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6998

6999 /* EN: Enable corrected error interrupts */

7000 UINT32 Rsvd31 : 1;

7001

7002 /* Bits[31:31], Access Type=RO, default=None*/

7003

7004 /* Reserved */

7005 UINT32 CmciCtl : 1;

7006

7007 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7008

7009 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7010 UINT32 Rsvd33 : 1;

7011

7012 /* Bits[33:33], Access Type=RO, default=None*/

7013

7014 /* Reserved */

7015 UINT32 MceCtl : 1;

7016

7017 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7018

7019 /* Controls MCE Remapping 0 MCE 1 MSMI */

7020 UINT32 Rsvd35 : 29;

7021

7022 /* Bits[63:35], Access Type=RO, default=None*/

7023

7024 /* Reserved */

7025

7026 } Bits;

7027

7028 UINT32 Uint32;

7029 UINT64 Uint64;

7030

7031 } MSR_MC16_CTL2_REGISTER;

7032

7033 /**

7034 LLC MCA bank: Control 2 register

7035 **/

7036 #define MSR_MC17_CTL2 0x00000291

7037

7038 typedef union {

7039 ///

7040 /// Individual bit fields

7041 ///

7042 struct {

7043 UINT32 CorCntrThreshold : 15;

7044

7045 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7046

7047 /* Corrected Error Counter Threshold */

7048 UINT32 Rsvd15 : 15;

7049

7050 /* Bits[29:15], Access Type=RO, default=None*/

7051

7052 /* Reserved */

7053 UINT32 En : 1;

7054

7055 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7056

7057 /* EN: Enable corrected error interrupts */

7058 UINT32 Rsvd31 : 1;

7059

7060 /* Bits[31:31], Access Type=RO, default=None*/

7061

7062 /* Reserved */

7063 UINT32 CmciCtl : 1;

7064

7065 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7066

7067 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7068 UINT32 Rsvd33 : 1;

7069

7070 /* Bits[33:33], Access Type=RO, default=None*/

7071

7072 /* Reserved */

7073 UINT32 MceCtl : 1;

7074

7075 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7076

7077 /* Controls MCE Remapping 0 MCE 1 MSMI */

7078 UINT32 Rsvd35 : 29;

7079

7080 /* Bits[63:35], Access Type=RO, default=None*/

7081

7082 /* Reserved */

7083

7084 } Bits;

7085

7086 UINT32 Uint32;

7087 UINT64 Uint64;

7088

7089 } MSR_MC17_CTL2_REGISTER;

7090

7091 /**

7092 LLC MCA bank: Control 2 register

7093 **/

7094 #define MSR_MC18_CTL2 0x00000292

7095

7096 typedef union {

7097 ///

7098 /// Individual bit fields

7099 ///

7100 struct {

7101 UINT32 CorCntrThreshold : 15;

7102

7103 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7104

7105 /* Corrected Error Counter Threshold */

7106 UINT32 Rsvd15 : 15;

7107

7108 /* Bits[29:15], Access Type=RO, default=None*/

7109

7110 /* Reserved */

7111 UINT32 En : 1;

7112

7113 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7114

7115 /* EN: Enable corrected error interrupts */

7116 UINT32 Rsvd31 : 1;

7117

7118 /* Bits[31:31], Access Type=RO, default=None*/

7119

7120 /* Reserved */

7121 UINT32 CmciCtl : 1;

7122

7123 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7124

7125 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7126 UINT32 Rsvd33 : 1;

7127

7128 /* Bits[33:33], Access Type=RO, default=None*/

7129

7130 /* Reserved */

7131 UINT32 MceCtl : 1;

7132

7133 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7134

7135 /* Controls MCE Remapping 0 MCE 1 MSMI */

7136 UINT32 Rsvd35 : 29;

7137

7138 /* Bits[63:35], Access Type=RO, default=None*/

7139

7140 /* Reserved */

7141

7142 } Bits;

7143

7144 UINT32 Uint32;

7145 UINT64 Uint64;

7146

7147 } MSR_MC18_CTL2_REGISTER;

7148

7149 /**

7150 EDRAM 0 Machine Check Architecture Control 2 MSR

7151 **/

7152 #define MSR_MC19_CTL2 0x00000293

7153

7154 typedef union {

7155 ///

7156 /// Individual bit fields

7157 ///

7158 struct {

7159 UINT32 Threshold : 15;

7160

7161 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7162

7163 /* Corrected Error Counter Threshold */

7164 UINT32 Rsvd15 : 15;

7165

7166 /* Bits[29:15], Access Type=RO, default=None*/

7167

7168 /* Reserved */

7169 UINT32 En : 1;

7170

7171 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7172

7173 /* EN: Enable corrected error interrupts */

7174 UINT32 Rsvd31 : 1;

7175

7176 /* Bits[31:31], Access Type=RO, default=None*/

7177

7178 /* Reserved */

7179 UINT32 CmciCtl : 1;

7180

7181 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7182

7183 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7184 UINT32 Rsvd33 : 1;

7185

7186 /* Bits[33:33], Access Type=RO, default=None*/

7187

7188 /* Reserved */

7189 UINT32 MceCtl : 1;

7190

7191 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7192

7193 /* Controls MCE Remapping 0 MCE 1 MSMI */

7194 UINT32 Rsvd35 : 29;

7195

7196 /* Bits[63:35], Access Type=RO, default=None*/

7197

7198 /* Reserved */

7199

7200 } Bits;

7201

7202 UINT32 Uint32;

7203 UINT64 Uint64;

7204

7205 } MSR_MC19_CTL2_REGISTER;

7206

7207 /**

7208 EDRAM 1 Machine Check Architecture Control 2 MSR

7209 **/

7210 #define MSR_MC20_CTL2 0x00000294

7211

7212 typedef union {

7213 ///

7214 /// Individual bit fields

7215 ///

7216 struct {

7217 UINT32 Threshold : 15;

7218

7219 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7220

7221 /* Corrected Error Counter Threshold */

7222 UINT32 Rsvd15 : 15;

7223

7224 /* Bits[29:15], Access Type=RO, default=None*/

7225

7226 /* Reserved */

7227 UINT32 En : 1;

7228

7229 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7230

7231 /* EN: Enable corrected error interrupts */

7232 UINT32 Rsvd31 : 1;

7233

7234 /* Bits[31:31], Access Type=RO, default=None*/

7235

7236 /* Reserved */

7237 UINT32 CmciCtl : 1;

7238

7239 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7240

7241 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7242 UINT32 Rsvd33 : 1;

7243

7244 /* Bits[33:33], Access Type=RO, default=None*/

7245

7246 /* Reserved */

7247 UINT32 MceCtl : 1;

7248

7249 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7250

7251 /* Controls MCE Remapping 0 MCE 1 MSMI */

7252 UINT32 Rsvd35 : 29;

7253

7254 /* Bits[63:35], Access Type=RO, default=None*/

7255

7256 /* Reserved */

7257

7258 } Bits;

7259

7260 UINT32 Uint32;

7261 UINT64 Uint64;

7262

7263 } MSR_MC20_CTL2_REGISTER;

7264

7265 /**

7266 2LM MCA bank: Control 2 register

7267 **/

7268 #define MSR_MC21_CTL2 0x00000295

7269

7270 typedef union {

7271 ///

7272 /// Individual bit fields

7273 ///

7274 struct {

7275 UINT32 Threshold : 15;

7276

7277 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7278

7279 /* Corrected Error Counter Threshold */

7280 UINT32 Rsvd15 : 15;

7281

7282 /* Bits[29:15], Access Type=RO, default=None*/

7283

7284 /* Reserved */

7285 UINT32 En : 1;

7286

7287 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7288

7289 /* EN: Enable corrected error interrupts */

7290 UINT32 Rsvd31 : 1;

7291

7292 /* Bits[31:31], Access Type=RO, default=None*/

7293

7294 /* Reserved */

7295 UINT32 CmciCtl : 1;

7296

7297 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7298

7299 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7300 UINT32 Rsvd33 : 1;

7301

7302 /* Bits[33:33], Access Type=RO, default=None*/

7303

7304 /* Reserved */

7305 UINT32 MceCtl : 1;

7306

7307 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7308

7309 /* Controls MCE Remapping 0 MCE 1 MSMI */

7310 UINT32 Rsvd35 : 29;

7311

7312 /* Bits[63:35], Access Type=RO, default=None*/

7313

7314 /* Reserved */

7315

7316 } Bits;

7317

7318 UINT32 Uint32;

7319 UINT64 Uint64;

7320

7321 } MSR_MC21_CTL2_REGISTER;

7322

7323 /**

7324 2LM MCA bank: Control 2 register

7325 **/

7326 #define MSR_MC22_CTL2 0x00000296

7327

7328 typedef union {

7329 ///

7330 /// Individual bit fields

7331 ///

7332 struct {

7333 UINT32 Threshold : 15;

7334

7335 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7336

7337 /* Corrected Error Counter Threshold */

7338 UINT32 Rsvd15 : 15;

7339

7340 /* Bits[29:15], Access Type=RO, default=None*/

7341

7342 /* Reserved */

7343 UINT32 En : 1;

7344

7345 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7346

7347 /* EN: Enable corrected error interrupts */

7348 UINT32 Rsvd31 : 1;

7349

7350 /* Bits[31:31], Access Type=RO, default=None*/

7351

7352 /* Reserved */

7353 UINT32 CmciCtl : 1;

7354

7355 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7356

7357 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7358 UINT32 Rsvd33 : 1;

7359

7360 /* Bits[33:33], Access Type=RO, default=None*/

7361

7362 /* Reserved */

7363 UINT32 MceCtl : 1;

7364

7365 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7366

7367 /* Controls MCE Remapping 0 MCE 1 MSMI */

7368 UINT32 Rsvd35 : 29;

7369

7370 /* Bits[63:35], Access Type=RO, default=None*/

7371

7372 /* Reserved */

7373

7374 } Bits;

7375

7376 UINT32 Uint32;

7377 UINT64 Uint64;

7378

7379 } MSR_MC22_CTL2_REGISTER;

7380

7381 /**

7382 2LM MCA bank: Control 2 register

7383 **/

7384 #define MSR_MC23_CTL2 0x00000297

7385

7386 typedef union {

7387 ///

7388 /// Individual bit fields

7389 ///

7390 struct {

7391 UINT32 Threshold : 15;

7392

7393 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7394

7395 /* Corrected Error Counter Threshold */

7396 UINT32 Rsvd15 : 15;

7397

7398 /* Bits[29:15], Access Type=RO, default=None*/

7399

7400 /* Reserved */

7401 UINT32 En : 1;

7402

7403 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7404

7405 /* EN: Enable corrected error interrupts */

7406 UINT32 Rsvd31 : 1;

7407

7408 /* Bits[31:31], Access Type=RO, default=None*/

7409

7410 /* Reserved */

7411 UINT32 CmciCtl : 1;

7412

7413 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7414

7415 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7416 UINT32 Rsvd33 : 1;

7417

7418 /* Bits[33:33], Access Type=RO, default=None*/

7419

7420 /* Reserved */

7421 UINT32 MceCtl : 1;

7422

7423 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7424

7425 /* Controls MCE Remapping 0 MCE 1 MSMI */

7426 UINT32 Rsvd35 : 29;

7427

7428 /* Bits[63:35], Access Type=RO, default=None*/

7429

7430 /* Reserved */

7431

7432 } Bits;

7433

7434 UINT32 Uint32;

7435 UINT64 Uint64;

7436

7437 } MSR_MC23_CTL2_REGISTER;

7438

7439 /**

7440 2LM MCA bank: Control 2 register

7441 **/

7442 #define MSR_MC24_CTL2 0x00000298

7443

7444 typedef union {

7445 ///

7446 /// Individual bit fields

7447 ///

7448 struct {

7449 UINT32 Threshold : 15;

7450

7451 /* Bits[14:0], Access Type=RW, default=0x00000000*/

7452

7453 /* Corrected Error Counter Threshold */

7454 UINT32 Rsvd15 : 15;

7455

7456 /* Bits[29:15], Access Type=RO, default=None*/

7457

7458 /* Reserved */

7459 UINT32 En : 1;

7460

7461 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7462

7463 /* EN: Enable corrected error interrupts */

7464 UINT32 Rsvd31 : 1;

7465

7466 /* Bits[31:31], Access Type=RO, default=None*/

7467

7468 /* Reserved */

7469 UINT32 CmciCtl : 1;

7470

7471 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7472

7473 /* Controls CMCI Remapping 0 CMCI 1 CSMI */

7474 UINT32 Rsvd33 : 1;

7475

7476 /* Bits[33:33], Access Type=RO, default=None*/

7477

7478 /* Reserved */

7479 UINT32 MceCtl : 1;

7480

7481 /* Bits[34:34], Access Type=RW, default=0x00000000*/

7482

7483 /* Controls MCE Remapping 0 MCE 1 MSMI */

7484 UINT32 Rsvd35 : 29;

7485

7486 /* Bits[63:35], Access Type=RO, default=None*/

7487

7488 /* Reserved */

7489

7490 } Bits;

7491

7492 UINT32 Uint32;

7493 UINT64 Uint64;

7494

7495 } MSR_MC24_CTL2_REGISTER;

7496

7497 /**

7498 Default MTRR related Memory Type and Enables, Details Vol. 3A 11.11.2.3

7499 **/

7500 #define MSR_MTRRDEFAULT 0x000002FF

7501

7502 typedef union {

7503 ///

7504 /// Individual bit fields

7505 ///

7506 struct {

7507 UINT32 Memtype : 3;

7508

7509 /* Bits[2:0], Access Type=RW, default=0x00000000*/

7510

7511 /* Default MTRR MemType */

7512 UINT32 Rsvd3 : 7;

7513

7514 /* Bits[9:3], Access Type=RO, default=None*/

7515

7516 /* Reserved */

7517 UINT32 Fe : 1;

7518

7519 /* Bits[10:10], Access Type=RW, default=0x00000000*/

7520

7521 /* Default Fix MTRR Enable */

7522 UINT32 En : 1;

7523

7524 /* Bits[11:11], Access Type=RW, default=0x00000000*/

7525

7526 /* Default MTRR Enable */

7527 UINT32 Rsvd12 : 20;

7528

7529 /* Bits[31:12], Access Type=RO, default=None*/

7530

7531 /* Reserved */

7532 UINT32 Rsvd32 : 32;

7533

7534 /* Bits[63:32], Access Type=RO, default=None*/

7535

7536 /* Reserved */

7537

7538 } Bits;

7539

7540 UINT32 Uint32;

7541 UINT64 Uint64;

7542

7543 } MSR_MTRRDEFAULT_REGISTER;

7544

7545 /**

7546 PERFCNTD OCCUPANCY COUNTER

7547 **/

7548 #define MSR_PERF_OCCUPANCY_CTRS 0x00000305

7549

7550 typedef union {

7551 ///

7552 /// Individual bit fields

7553 ///

7554 struct {

7555 UINT32 Ctr0 : 6;

7556

7557 /* Bits[5:0], Access Type=RW_V, default=0x00000000*/

7558

7559 /* OCCUPANCY CTR 0 */

7560 UINT32 Ctr1 : 6;

7561

7562 /* Bits[11:6], Access Type=RW_V, default=0x00000000*/

7563

7564 /* OCCUPANCY CTR 1 */

7565 UINT32 Ctr2 : 6;

7566

7567 /* Bits[17:12], Access Type=RW_V, default=0x00000000*/

7568

7569 /* OCCUPANCY CTR 2 */

7570 UINT32 Ctr3 : 6;

7571

7572 /* Bits[23:18], Access Type=RW_V, default=0x00000000*/

7573

7574 /* OCCUPANCY CTR 3 */

7575 UINT32 Rsvd24 : 8;

7576

7577 /* Bits[31:24], Access Type=RO, default=None*/

7578

7579 /* Reserved */

7580

7581 } Bits;

7582

7583 UINT32 Uint32;

7584 UINT64 Uint64;

7585

7586 } MSR_PERF_OCCUPANCY_CTRS_REGISTER;

7587

7588 /**

7589 FIXED PERFORMANCE COUNTER

7590 **/

7591 #define MSR_EMON_FIXED_CTR0 0x00000309

7592

7593 typedef union {

7594 ///

7595 /// Individual bit fields

7596 ///

7597 struct {

7598 UINT32 Lower : 32;

7599

7600 /* Bits[31:0], Access Type=RW, default=0x00000000*/

7601

7602 /* Lower Half of PERFMON FIXED CNTR */

7603 UINT32 Upper : 16;

7604

7605 /* Bits[47:32], Access Type=RW, default=0x00000000*/

7606

7607 /* Upper Half of PERFMON FIXED CNTR */

7608 UINT32 Rsvd48 : 16;

7609

7610 /* Bits[63:48], Access Type=RO, default=None*/

7611

7612 /* Reserved */

7613

7614 } Bits;

7615

7616 UINT32 Uint32;

7617 UINT64 Uint64;

7618

7619 } MSR_EMON_FIXED_CTR0_REGISTER;

7620

7621 /**

7622 FIXED PERFORMANCE COUNTER

7623 **/

7624 #define MSR_EMON_FIXED_CTR1 0x0000030A

7625

7626 typedef union {

7627 ///

7628 /// Individual bit fields

7629 ///

7630 struct {

7631 UINT32 Lower : 32;

7632

7633 /* Bits[31:0], Access Type=RW, default=0x00000000*/

7634

7635 /* Lower Half of PERFMON FIXED CNTR */

7636 UINT32 Upper : 16;

7637

7638 /* Bits[47:32], Access Type=RW, default=0x00000000*/

7639

7640 /* Upper Half of PERFMON FIXED CNTR */

7641 UINT32 Rsvd48 : 16;

7642

7643 /* Bits[63:48], Access Type=RO, default=None*/

7644

7645 /* Reserved */

7646

7647 } Bits;

7648

7649 UINT32 Uint32;

7650 UINT64 Uint64;

7651

7652 } MSR_EMON_FIXED_CTR1_REGISTER;

7653

7654 /**

7655 FIXED PERFORMANCE COUNTER

7656 **/

7657 #define MSR_EMON_FIXED_CTR2 0x0000030B

7658

7659 typedef union {

7660 ///

7661 /// Individual bit fields

7662 ///

7663 struct {

7664 UINT32 Lower : 32;

7665

7666 /* Bits[31:0], Access Type=RW, default=0x00000000*/

7667

7668 /* Lower Half of PERFMON FIXED CNTR */

7669 UINT32 Upper : 16;

7670

7671 /* Bits[47:32], Access Type=RW, default=0x00000000*/

7672

7673 /* Upper Half of PERFMON FIXED CNTR */

7674 UINT32 Rsvd48 : 16;

7675

7676 /* Bits[63:48], Access Type=RO, default=None*/

7677

7678 /* Reserved */

7679

7680 } Bits;

7681

7682 UINT32 Uint32;

7683 UINT64 Uint64;

7684

7685 } MSR_EMON_FIXED_CTR2_REGISTER;

7686

7687 /**

7688 FIXED PERFORMANCE COUNTER

7689 **/

7690 #define MSR_EMON_FIXED_CTR3 0x0000030C

7691

7692 typedef union {

7693 ///

7694 /// Individual bit fields

7695 ///

7696 struct {

7697 UINT32 Lower : 32;

7698

7699 /* Bits[31:0], Access Type=RW, default=0x00000000*/

7700

7701 /* Lower Half of PERFMON FIXED CNTR */

7702 UINT32 Upper : 16;

7703

7704 /* Bits[47:32], Access Type=RW, default=0x00000000*/

7705

7706 /* Upper Half of PERFMON FIXED CNTR */

7707 UINT32 Rsvd48 : 16;

7708

7709 /* Bits[63:48], Access Type=RO, default=None*/

7710

7711 /* Reserved */

7712

7713 } Bits;

7714

7715 UINT32 Uint32;

7716 UINT64 Uint64;

7717

7718 } MSR_EMON_FIXED_CTR3_REGISTER;

7719

7720 /**

7721 Perfmon msr for exposure metrics on several emons

7722 **/

7723 #define MSR_PERF_METRICS 0x00000329

7724

7725 typedef union {

7726 ///

7727 /// Individual bit fields

7728 ///

7729 struct {

7730 UINT32 Retiring : 8;

7731

7732 /* Bits[7:0], Access Type=RW, default=0x00000000*/

7733

7734 /* retired */

7735 UINT32 BadSpeculation : 8;

7736

7737 /* Bits[15:8], Access Type=RW, default=0x00000000*/

7738

7739 /* bad speculation */

7740 UINT32 FrontendBound : 8;

7741

7742 /* Bits[23:16], Access Type=RW, default=0x00000000*/

7743

7744 /* frontend bound */

7745 UINT32 BackendBound : 8;

7746

7747 /* Bits[31:24], Access Type=RW, default=0x00000000*/

7748

7749 /* backend bound */

7750 UINT32 Reserved32 : 32;

7751

7752 /* Bits[63:32], Access Type=RW, default=0x00000000*/

7753

7754 /* frontend bound */

7755

7756 } Bits;

7757

7758 UINT32 Uint32;

7759 UINT64 Uint64;

7760

7761 } MSR_PERF_METRICS_REGISTER;

7762

7763 /**

7764 This register is a Read Only MSR that enumerates the existence of certain

7765 debug features in PerfMon.

7766 **/

7767 #define MSR_EMON_PERF_CAPABILITIES 0x00000345

7768

7769 typedef union {

7770 ///

7771 /// Individual bit fields

7772 ///

7773 struct {

7774 UINT32 Lbrformat : 6;

7775

7776 /* Bits[5:0], Access Type=RO_V, default=None*/

7777

7778 /*

7779 Last Branch Record Format. 0=32-bit, 1=64-bit

7780 LIP, 2=64-bit EIP

7781 */

7782 UINT32 Pebstrap : 1;

7783

7784 /* Bits[6:6], Access Type=RO_V, default=None*/

7785

7786 /*

7787 When set, PEBS recording is trap-like. After the

7788 PEBS-enabled counter has overflowed, PEBS record

7789 is recorded for the next PEBS-able event at the

7790 completion of the sampled instruction causing

7791 the PEBS event. When clear, PEBS recording is

7792 fault-like. The PEBS record is recorded before

7793 the sampled instruction causing the PEBS event.

7794 */

7795 UINT32 Pebssavearchreg : 1;

7796

7797 /* Bits[7:7], Access Type=RO_V, default=None*/

7798

7799 /*

7800 When set, PEBS will save architectural register

7801 and state information according to the encoded

7802 value of the PEBSRecordFormat field. On

7803 processors based on Intel Core

7804 microarchitecture, this bit is always 1.

7805 */

7806 UINT32 Pebsrecordformat : 4;

7807

7808 /* Bits[11:8], Access Type=RO_V, default=None*/

7809

7810 /*

7811 Valid encodings are: 0000B: Only general-purpose

7812 registers, instruction pointer and RFLAGS

7813 registers are saved in each PEBS record.

7814 */

7815 UINT32 Disablemmduringsmm : 1;

7816

7817 /* Bits[12:12], Access Type=RO_V, default=None*/

7818

7819 /*

7820 If set this indicates the ability to disable

7821 machine monitoring in SMM.

7822 */

7823 UINT32 Perfmonfullwidthwrite : 1;

7824

7825 /* Bits[13:13], Access Type=RO_V, default=None*/

7826

7827 /* Indicates support of full-width writes. */

7828 UINT32 Pebsadaptivedata : 1;

7829

7830 /* Bits[14:14], Access Type=RO_V, default=None*/

7831

7832 /*

7833 Indicates PEBS support adaptive records (SNC and

7834 on).

7835 */

7836 UINT32 Perfmetricsavailable : 1;

7837

7838 /* Bits[15:15], Access Type=RO_V, default=None*/

7839

7840 /*

7841 Indicates PERF METRICS is supported (SNC and

7842 on).

7843 */

7844 UINT32 Rsvd16 : 16;

7845

7846 /* Bits[31:16], Access Type=RO, default=None*/

7847

7848 /* Reserved */

7849 UINT32 Rsvd32 : 32;

7850

7851 /* Bits[63:32], Access Type=RO, default=None*/

7852

7853 /* Reserved */

7854

7855 } Bits;

7856

7857 UINT32 Uint32;

7858 UINT64 Uint64;

7859

7860 } MSR_EMON_PERF_CAPABILITIES_REGISTER;

7861

7862 /**

7863 This register provides enabling for the fixed performance counters

7864 and enabling for PMI and also provides a the MYTHREADS/ALLTHREADS

7865 for each counter as well.

7866 **/

7867 #define MSR_EMON_FIXED_CTR_CTRL 0x0000038D

7868

7869 typedef union {

7870 ///

7871 /// Individual bit fields

7872 ///

7873 struct {

7874 UINT32 EnCtr0 : 2;

7875

7876 /* Bits[1:0], Access Type=RW, default=0x00000000*/

7877

7878 /*

7879 This bit is the local enable for the Fixed

7880 counter 0. Disabling these bits or the bits in

7881 ia32_cr_perf_global_ctrl[35:32] enable bit will

7882 cause the counters to halt. Counter is enabled

7883 by setting CPL Level: 00 - Disable 01 - Ring 0

7884 (OS) 10 - Ring 1,2,3 (User) 11 - All ring levels

7885 (OS or User) when CPL changes to one of the

7886 above the counter gets enabled.

7887 */

7888 UINT32 MyallthrCtr0 : 1;

7889

7890 /* Bits[2:2], Access Type=RW, default=0x00000000*/

7891

7892 /*

7893 When this bit is set fixed counter 0 will count

7894 instructions retired for both threads.

7895 */

7896 UINT32 EnPmiCtr0 : 1;

7897

7898 /* Bits[3:3], Access Type=RW, default=0x00000000*/

7899

7900 /*

7901 When set to 1 will cause a PMI when the 48 bit

7902 Fixed counter overflows.

7903 */

7904 UINT32 EnCtr1 : 2;

7905

7906 /* Bits[5:4], Access Type=RW, default=0x00000000*/

7907

7908 /*

7909 This bit is the local enable for the Fixed

7910 counter 1. Disabling these bits or the bits in

7911 ia32_cr_perf_global_ctrl[35:32] enable bit will

7912 cause the counters to halt. Counter is enabled

7913 by setting CPL Level: 00 - Disable 01 - Ring 0

7914 (OS) 10 - Ring 1,2,3 (User) 11 - All ring levels

7915 (OS or User) when CPL changes to one of the

7916 above the counter gets enabled.

7917 */

7918 UINT32 MyallthrCtr1 : 1;

7919

7920 /* Bits[6:6], Access Type=RW, default=0x00000000*/

7921

7922 /*

7923 When this bit is set fixed counter 1 will count

7924 instructions retired for both threads.

7925 */

7926 UINT32 EnPmiCtr1 : 1;

7927

7928 /* Bits[7:7], Access Type=RW, default=0x00000000*/

7929

7930 /*

7931 When set to 1 will cause a PMI when the 48 bit

7932 Fixed counter overflows.

7933 */

7934 UINT32 EnCtr2 : 2;

7935

7936 /* Bits[9:8], Access Type=RW, default=0x00000000*/

7937

7938 /*

7939 This bit is the local enable for the Fixed

7940 counter 2. Disabling these bits or the bits in

7941 ia32_cr_perf_global_ctrl[35:32] enable bit will

7942 cause the counters to halt. Counter is enabled

7943 by setting CPL Level: 00 - Disable 01 - Ring 0

7944 (OS) 10 - Ring 1,2,3 (User) 11 - All ring levels

7945 (OS or User) when CPL changes to one of the

7946 above the counter gets enabled.

7947 */

7948 UINT32 MyallthrCtr2 : 1;

7949

7950 /* Bits[10:10], Access Type=RW, default=0x00000000*/

7951

7952 /*

7953 When this bit is set fixed counter 2 will count

7954 instructions retired for both threads.

7955 */

7956 UINT32 EnPmiCtr2 : 1;

7957

7958 /* Bits[11:11], Access Type=RW, default=0x00000000*/

7959

7960 /*

7961 When set to 1 will cause a PMI when the 48 bit

7962 Fixed counter overflows.

7963 */

7964 UINT32 EnCtr3 : 2;

7965

7966 /* Bits[13:12], Access Type=RW, default=0x00000000*/

7967

7968 /*

7969 This bit is the local enable for the Fixed

7970 counter 3. Disabling these bits or the bits in

7971 ia32_cr_perf_global_ctrl[35:32] enable bit will

7972 cause the counters to halt. Counter is enabled

7973 by setting CPL Level: 00 - Disable 01 - Ring 0

7974 (OS) 10 - Ring 1,2,3 (User) 11 - All ring levels

7975 (OS or User) when CPL changes to one of the

7976 above the counter gets enabled.

7977 */

7978 UINT32 Rsvd14 : 1;

7979

7980 /* Bits[14:14], Access Type=RO, default=None*/

7981

7982 /* Reserved */

7983 UINT32 EnPmiCtr3 : 1;

7984

7985 /* Bits[15:15], Access Type=RW, default=0x00000000*/

7986

7987 /*

7988 When set to 1 will cause a PMI when the 48 bit

7989 Fixed counter overflows.

7990 */

7991 UINT32 Rsvd16 : 16;

7992

7993 /* Bits[31:16], Access Type=RO, default=None*/

7994

7995 /* Reserved */

7996 UINT32 AdaptiveRecordCtr0 : 1;

7997

7998 /* Bits[32:32], Access Type=RW, default=0x00000000*/

7999

8000 /*

8001 for adaptive pebs feature in SNC if

8002 adaptive_record bit is set, Ucode will consider

8003 MSR_PEBS_DATA_CFG and emit the requested fields

8004 */

8005 UINT32 Rsvd33 : 3;

8006

8007 /* Bits[35:33], Access Type=RO, default=None*/

8008

8009 /* Reserved */

8010 UINT32 AdaptiveRecordCtr1 : 1;

8011

8012 /* Bits[36:36], Access Type=RW, default=0x00000000*/

8013

8014 /*

8015 for adaptive pebs feature in SNC if

8016 adaptive_record bit is set, Ucode will consider

8017 MSR_PEBS_DATA_CFG and emit the requested fields

8018 */

8019 UINT32 Rsvd37 : 3;

8020

8021 /* Bits[39:37], Access Type=RO, default=None*/

8022

8023 /* Reserved */

8024 UINT32 AdaptiveRecordCtr2 : 1;

8025

8026 /* Bits[40:40], Access Type=RW, default=0x00000000*/

8027

8028 /*

8029 for adaptive pebs feature in SNC if

8030 adaptive_record bit is set, Ucode will consider

8031 MSR_PEBS_DATA_CFG and emit the requested fields

8032 */

8033 UINT32 Rsvd41 : 3;

8034

8035 /* Bits[43:41], Access Type=RO, default=None*/

8036

8037 /* Reserved */

8038 UINT32 AdaptiveRecordCtr3 : 1;

8039

8040 /* Bits[44:44], Access Type=RW, default=0x00000000*/

8041

8042 /*

8043 for adaptive pebs feature in SNC if

8044 adaptive_record bit is set, Ucode will consider

8045 MSR_PEBS_DATA_CFG and emit the requested fields

8046 */

8047 UINT32 Rsvd45 : 19;

8048

8049 /* Bits[63:45], Access Type=RO, default=None*/

8050

8051 /* Reserved */

8052

8053 } Bits;

8054

8055 UINT32 Uint32;

8056 UINT64 Uint64;

8057

8058 } MSR_EMON_FIXED_CTR_CTRL_REGISTER;

8059

8060 /**

8061 Global Performance Counter Status

8062 A write of '1' to any of the bits in this register causes the corresponding bit

8063 in the IA32_CR_PERF_GLOBAL_STATUS register to set to '1'. Write to '0 ignored.

8064 **/

8065 #define MSR_EMON_PERF_GLOBAL_STATUS 0x0000038E

8066

8067 typedef union {

8068 ///

8069 /// Individual bit fields

8070 ///

8071 struct {

8072 UINT32 OvfGenCtr : 8;

8073

8074 /* Bits[7:0], Access Type=RW1S, default=0x00000000*/

8075

8076 /*

8077 This bit range 7:0 represents the overflow of

8078 general counter 7 to 0 respecitively. These

8079 status bits normally gets set whenever general

8080 counters 7:0 overflow. Since the fixed and

8081 general counters contain only positive 48 bit

8082 count values, an overflow is the case where the

8083 counter generates a carryout.

8084 */

8085 UINT32 Rsvd8 : 24;

8086

8087 /* Bits[31:8], Access Type=RO, default=None*/

8088

8089 /* Reserved */

8090 UINT32 OvfFixedCtr : 4;

8091

8092 /* Bits[35:32], Access Type=RW1S, default=0x00000000*/

8093

8094 /*

8095 This bit range 35:32 represents the overflow of

8096 fixed counters 3-0 respecitively. This status

8097 bit normally gets set whenever the associated

8098 fixed cntr overflows. Since the fixed and

8099 general counters contain only positive 48 bit

8100 count values, an overflow is the case where the

8101 counter generates a carryout. Note, Only fixed

8102 counter 0 can cause a PEBS thus writing bit for

8103 fixed counter 0 will enable a PEBS on the next

8104 occurrence of a PEBS-able event.

8105 */

8106 UINT32 Rsvd36 : 12;

8107

8108 /* Bits[47:36], Access Type=RO, default=None*/

8109

8110 /* Reserved */

8111 UINT32 OvfPerfMetricsCtr : 1;

8112

8113 /* Bits[48:48], Access Type=RW1S, default=0x00000000*/

8114

8115 /*

8116 This bit is asserted when there is a overflow on

8117 any perf_metric counters.

8118 */

8119 UINT32 Rsvd49 : 6;

8120

8121 /* Bits[54:49], Access Type=RO, default=None*/

8122

8123 /* Reserved */

8124 UINT32 RtitTopaPmi : 1;

8125

8126 /* Bits[55:55], Access Type=RW1S, default=0x00000000*/

8127

8128 /*

8129 RTIT ToPA PMI bit is an indication that a ToPA

8130 entry tagged with INTERRUPT was filled up. RTIT

8131 continues tracing and no resource/counter will

8132 be frozen regardless of

8133 IA32_DEBUGCTL.Freeze_Perfmon_on_PMI setting.

8134 This bit remains set until cleared by a WRMSR to

8135 IA32_PERF_GLOBAL_STATUS_RESET.

8136 */

8137 UINT32 Rsvd56 : 2;

8138

8139 /* Bits[57:56], Access Type=RO, default=None*/

8140

8141 /* Reserved */

8142 UINT32 LbrsFrozen : 1;

8143

8144 /* Bits[58:58], Access Type=RW1S, default=0x00000000*/

8145

8146 /*

8147 DEBUGCTL.FREEZE_LBRS_ON_PMI is used, and there

8148 was PMI HW sets a new bit, called LBRS_FROZEN

8149 LBR effective enable become: DEBUGCTL.LBR and

8150 ~LBRS_FROZEN

8151 */

8152 UINT32 CtrsFrozen : 1;

8153

8154 /* Bits[59:59], Access Type=RW1S, default=0x00000000*/

8155

8156 /*

8157 DEBUGCTL.FREEZE_PERFMON_ON_PMI is used, and

8158 there was PMI ROB sets a new CTRS_FROZEN bit 59

8159 in PERF_GLOBAL_STATUS Counter i effective

8160 enable: PERF_GLOBAL_CTRL[i] and PerfEvntSeli.EN

8161 and ~CTRS_FROZEN

8162 */

8163 UINT32 Interference : 1;

8164

8165 /* Bits[60:60], Access Type=RW1S, default=0x00000000*/

8166

8167 /*

8168 communicate to performance monitoring software

8169 that the performance measurements by various

8170 counters may not be completely accurate due to

8171 interference from some other blinding technology

8172 (SE).

8173 */

8174 UINT32 OvfUncore : 1;

8175

8176 /* Bits[61:61], Access Type=RW1S, default=0x00000000*/

8177

8178 /*

8179 Overflow Uncore bit is an indication that there

8180 was an overflow of a counter in the UNCORE that

8181 was set to cause a PMI. This bit remains set

8182 until cleared by IA32_CR_PERF_GLOBAL_RESET. This

8183 bit is also routed to the PMI logic. See PMI

8184 section.

8185 */

8186 UINT32 OvfPebs : 1;

8187

8188 /* Bits[62:62], Access Type=RW1S, default=0x00000000*/

8189

8190 /*

8191 Overflow PEBS bit is an indication that there

8192 was an PEBS overflow of a counter that cause a

8193 PMI. This bit remains set until cleared by

8194 writing a '0.

8195 */

8196 UINT32 CondChanged : 1;

8197

8198 /* Bits[63:63], Access Type=RW1S, default=0x00000000*/

8199

8200 /*

8201 The Condition Changed bit is set in case of a

8202 change to IA32_MISC_ENABLES.PERFMON_AVAILABLE

8203 (bit 7). In SNC and on, we can't clear

8204 PERFMON_AVAILABLE, thus cond_changed will

8205 allways be 0

8206 */

8207

8208 } Bits;

8209

8210 UINT32 Uint32;

8211 UINT64 Uint64;

8212

8213 } MSR_EMON_PERF_GLOBAL_STATUS_REGISTER;

8214

8215 /**

8216 The IA32_CR_PERF_GLOBAL_CTRL MSR is used to globally

8217 control all the PERFMON counters for a given thread at once.

8218 This allows instant on/off of all PERFMON counters.

8219 **/

8220 #define MSR_EMON_PERF_GLOBAL_CTRL 0x0000038F

8221

8222 typedef union {

8223 ///

8224 /// Individual bit fields

8225 ///

8226 struct {

8227 UINT32 EnGenCtr : 8;

8228

8229 /* Bits[7:0], Access Type=RW, default=0x000000FF*/

8230

8231 /*

8232 Global Enables for PerfMon Counters 7:0

8233 respectively. When the appropriate bit gets set

8234 and the local enable of counter is enabled the

8235 PerfMon counter will be allowed to counter. If

8236 either the global or local enables are not

8237 asserted, the counters will be disabled. The

8238 global enables allow for simultaneous enabling

8239 or disabling of all or some ofthe Core PerfMon

8240 counters.

8241 */

8242 UINT32 Rsvd8 : 24;

8243

8244 /* Bits[31:8], Access Type=RO, default=None*/

8245

8246 /* Reserved */

8247 UINT32 EnFixedCtr : 4;

8248

8249 /* Bits[35:32], Access Type=RW, default=0x00000000*/

8250

8251 /*

8252 Global Enable for Fixed Counter 3, 2, 1, 0

8253 respecitvely to bit range 35:32. Both this

8254 enable and the local enable for the fixed

8255 counter needs to be asserted for the fixed

8256 counter to be counting.

8257 */

8258 UINT32 Rsvd36 : 12;

8259

8260 /* Bits[47:36], Access Type=RO, default=None*/

8261

8262 /* Reserved */

8263 UINT32 EnPerfMetricsCtr : 1;

8264

8265 /* Bits[48:48], Access Type=RW, default=0x00000000*/

8266

8267 /*

8268 This is the global enable for the 4 internal

8269 perf metric counters.

8270 */

8271 UINT32 Rsvd49 : 15;

8272

8273 /* Bits[63:49], Access Type=RO, default=None*/

8274

8275 /* Reserved */

8276

8277 } Bits;

8278

8279 UINT32 Uint32;

8280 UINT64 Uint64;

8281

8282 } MSR_EMON_PERF_GLOBAL_CTRL_REGISTER;

8283

8284 /**

8285 Global Performance Counter Reset Control

8286 **/

8287 #define MSR_EMON_PERF_GLOBAL_RESET 0x00000390

8288

8289 typedef union {

8290 ///

8291 /// Individual bit fields

8292 ///

8293 struct {

8294 UINT32 ClrOvfGenCtr : 8;

8295

8296 /* Bits[7:0], Access Type=WO, default=None*/

8297

8298 /*

8299 Range 7:0 relates to General 7:0 respecitively.

8300 Writes of '1' to any of the bits in this field

8301 causes the corresponding bits in the 'Overflow

8302 General Counter' field in the

8303 IA32_CR_PERF_GLOBAL_STATUS register to clear to

8304 '0'.

8305 */

8306 UINT32 Rsvd8 : 24;

8307

8308 /* Bits[31:8], Access Type=RO, default=None*/

8309

8310 /* Reserved */

8311 UINT32 ClrOvfFixedCtr : 4;

8312

8313 /* Bits[35:32], Access Type=WO, default=None*/

8314

8315 /*

8316 Range 35:32 relates to Fixed Cntr 3, 2 ,1, 0

8317 respecitively. Writes of '1' to any of the bits

8318 in this field causes the corresponding bits in

8319 the 'Overflow Fixed Counter' field of

8320 IA32_CR_PERF_GLOBAL_STATUS to clear to '0'.

8321 */

8322 UINT32 Rsvd36 : 12;

8323

8324 /* Bits[47:36], Access Type=RO, default=None*/

8325

8326 /* Reserved */

8327 UINT32 ClrOvfPerfMetricsCtr : 1;

8328

8329 /* Bits[48:48], Access Type=WO, default=None*/

8330

8331 /*

8332 Write 1'b1 to this bit will clear the proper

8333 ovf_perm_metrics_ctr bit in perf_global_status.

8334 */

8335 UINT32 Rsvd49 : 6;

8336

8337 /* Bits[54:49], Access Type=RO, default=None*/

8338

8339 /* Reserved */

8340 UINT32 ClrRtitTopaPmi : 1;

8341

8342 /* Bits[55:55], Access Type=WO, default=None*/

8343

8344 /*

8345 Writes of '1' to this bit causes the

8346 'rtit_topa_pmi' bit in the global status

8347 register to clear to '0'.

8348 */

8349 UINT32 Rsvd56 : 2;

8350

8351 /* Bits[57:56], Access Type=RO, default=None*/

8352

8353 /* Reserved */

8354 UINT32 ClrLbrsFrozen : 1;

8355

8356 /* Bits[58:58], Access Type=WO, default=None*/

8357

8358 /*

8359 Writes of '1' to this bit causes the

8360 'lbrs_frozen' bit in the global status register

8361 to clear to '0'.

8362 */

8363 UINT32 ClrCtrsFrozen : 1;

8364

8365 /* Bits[59:59], Access Type=WO, default=None*/

8366

8367 /*

8368 Writes of '1' to this bit causes the

8369 'ctrs_frozen' bit in the global status register

8370 to clear to '0'.

8371 */

8372 UINT32 ClrInterference : 1;

8373

8374 /* Bits[60:60], Access Type=WO, default=None*/

8375

8376 /*

8377 Writes of '1' to this bit causes the

8378 'interference' bit in the global status register

8379 to clear to '0'.

8380 */

8381 UINT32 ClrOvfUncore : 1;

8382

8383 /* Bits[61:61], Access Type=WO, default=None*/

8384

8385 /*

8386 Writes of '1' to this bit causes the 'Overflow

8387 UnCore' bit in the global status register to

8388 clear to '0'.

8389 */

8390 UINT32 ClrOvfPebs : 1;

8391

8392 /* Bits[62:62], Access Type=WO, default=None*/

8393

8394 /*

8395 Writes of '1' to this bit causes the 'Overflow

8396 pebs' bit in the global status register to clear

8397 to '0'.

8398 */

8399 UINT32 ClrCondChanged : 1;

8400

8401 /* Bits[63:63], Access Type=WO, default=None*/

8402

8403 /*

8404 Writes of '1' to this bit causes the 'Condition

8405 Change' bit (bit 63) in the

8406 IA32_CR_PERF_GLOBAL_STATUS to clear to '0'.

8407 */

8408

8409 } Bits;

8410

8411 UINT32 Uint32;

8412 UINT64 Uint64;

8413

8414 } MSR_EMON_PERF_GLOBAL_RESET_REGISTER;

8415

8416 /**

8417 The Core PerfMon global overflow set MSR is writable only command

8418 register. A read from this register will always return zeroes. A write

8419 of '1' to any of the bits in this register causes the corresponding bit

8420 in the IA32_CR_PERF_GLOBAL_STATUS register to set to '1'.

8421 **/

8422 #define MSR_EMON_PERF_GLOBAL_SET 0x00000391

8423

8424 typedef union {

8425 ///

8426 /// Individual bit fields

8427 ///

8428 struct {

8429 UINT32 SetOvfGenCtr : 8;

8430

8431 /* Bits[7:0], Access Type=WO, default=None*/

8432

8433 /*

8434 Range 7:0 relates to General 7-0 respecitively.

8435 Writes of '1' to any of the bits in this field

8436 causes the corresponding bits in the 'Overflow

8437 General Counter' field in the

8438 IA32_CR_PERF_GLOBAL_STATUS register to set to

8439 '1'.

8440 */

8441 UINT32 Rsvd8 : 24;

8442

8443 /* Bits[31:8], Access Type=RO, default=None*/

8444

8445 /* Reserved */

8446 UINT32 SetOvfFixedCtr : 4;

8447

8448 /* Bits[35:32], Access Type=WO, default=None*/

8449

8450 /*

8451 Range 35:32 relates to Fixed Cntr 3, 2 ,1, 0

8452 respecitively. Writes of '1' to any of the bits

8453 in this field causes the corresponding bits in

8454 the 'Overflow Fixed Counter' field of

8455 IA32_CR_PERF_GLOBAL_STATUS to set to '1'.

8456 */

8457 UINT32 Rsvd36 : 12;

8458

8459 /* Bits[47:36], Access Type=RO, default=None*/

8460

8461 /* Reserved */

8462 UINT32 SetOvfPerfMetricsCtr : 1;

8463

8464 /* Bits[48:48], Access Type=WO, default=None*/

8465

8466 /*

8467 Write to this bit will set the ovf_status to

8468 1'b1

8469 */

8470 UINT32 Rsvd49 : 6;

8471

8472 /* Bits[54:49], Access Type=RO, default=None*/

8473

8474 /* Reserved */

8475 UINT32 SetRtitTopaPmi : 1;

8476

8477 /* Bits[55:55], Access Type=WO, default=0x00000000*/

8478

8479 /*

8480 RTIT ToPA PMI bit is an indication that a ToPA

8481 entry tagged with INTERRUPT was filled up. RTIT

8482 continues tracing and no resource/counter will

8483 be frozen regardless of

8484 IA32_DEBUGCTL.Freeze_Perfmon_on_PMI setting.

8485 wrmsr of this bit sets the corresponding bit in

8486 IA32_PERF_GLOBAL_STATUS_RESET.

8487 */

8488 UINT32 Rsvd56 : 2;

8489

8490 /* Bits[57:56], Access Type=RO, default=None*/

8491

8492 /* Reserved */

8493 UINT32 SetLbrsFrozen : 1;

8494

8495 /* Bits[58:58], Access Type=WO, default=None*/

8496

8497 /*

8498 Writes of '1' to this bit causes the

8499 'clr_lbrs_frozen' bit in the global status

8500 register to set to '1'.

8501 */

8502 UINT32 SetCtrsFrozen : 1;

8503

8504 /* Bits[59:59], Access Type=WO, default=None*/

8505

8506 /*

8507 Writes of '1' to this bit causes the

8508 'clr_ctrs_frozen' bit in the global status

8509 register to set to '1'.

8510 */

8511 UINT32 SetInterference : 1;

8512

8513 /* Bits[60:60], Access Type=WO, default=None*/

8514

8515 /*

8516 Writes of '1' to this bit causes the

8517 'clr_interference' bit in the global status

8518 register to set to '1'.

8519 */

8520 UINT32 SetOvfUncore : 1;

8521

8522 /* Bits[61:61], Access Type=WO, default=None*/

8523

8524 /*

8525 Writes of '1' to this bit causes the 'Overflow

8526 UnCore' bit in the global status register to set

8527 to '1'.

8528 */

8529 UINT32 SetOvfPebs : 1;

8530

8531 /* Bits[62:62], Access Type=WO, default=None*/

8532

8533 /*

8534 Writes of '1' to this bit causes the 'Overflow

8535 pebs' bit in the global status register to set

8536 to '1'.

8537 */

8538 UINT32 SetCondChanged : 1;

8539

8540 /* Bits[63:63], Access Type=WO, default=None*/

8541

8542 /*

8543 Writes of '1' to this bit causes the 'Condition

8544 Change' bit (bit 63) in the

8545 IA32_CR_PERF_GLOBAL_STATUS to set to '1'.

8546 */

8547

8548 } Bits;

8549

8550 UINT32 Uint32;

8551 UINT64 Uint64;

8552

8553 } MSR_EMON_PERF_GLOBAL_SET_REGISTER;

8554

8555 /**

8556 Precise Event Based Sampling controlling register

8557 **/

8558 #define MSR_PEBS_ENABLE 0x000003F1

8559

8560 typedef union {

8561 ///

8562 /// Individual bit fields

8563 ///

8564 struct {

8565 UINT32 CntrEnable : 8;

8566

8567 /* Bits[7:0], Access Type=RW, default=0x00000000*/

8568

8569 /* Set to enable the general PEBS counters */

8570 UINT32 Rsvd8 : 24;

8571

8572 /* Bits[31:8], Access Type=RO, default=None*/

8573

8574 /* Reserved */

8575 UINT32 FixedCntrEnable : 4;

8576

8577 /* Bits[35:32], Access Type=RW, default=0x00000000*/

8578

8579 /*

8580 Set to enable the fixed counters 3:0 PEBS

8581 counters

8582 */

8583 UINT32 Rsvd36 : 28;

8584

8585 /* Bits[63:36], Access Type=RO, default=None*/

8586

8587 /* Reserved */

8588

8589 } Bits;

8590

8591 UINT32 Uint32;

8592 UINT64 Uint64;

8593

8594 } MSR_PEBS_ENABLE_REGISTER;

8595

8596 /**

8597 PEBS DATA CFG

8598 **/

8599 #define MSR_PEBS_DATA_CFG 0x000003F2

8600

8601 typedef union {

8602 ///

8603 /// Individual bit fields

8604 ///

8605 struct {

8606 UINT32 MemoryInfo : 1;

8607

8608 /* Bits[0:0], Access Type=RW, default=0x00000000*/

8609

8610 /* Memory info enable bit */

8611 UINT32 GprRegs : 1;

8612

8613 /* Bits[1:1], Access Type=RW, default=0x00000000*/

8614

8615 /* gpr regs enable bit */

8616 UINT32 XmmRegs : 1;

8617

8618 /* Bits[2:2], Access Type=RW, default=0x00000000*/

8619

8620 /* xmm regs enable bit */

8621 UINT32 Lbrs : 1;

8622

8623 /* Bits[3:3], Access Type=RW, default=0x00000000*/

8624

8625 /* lbrs enable bit */

8626 UINT32 Rsvd4 : 20;

8627

8628 /* Bits[23:4], Access Type=RW, default=0x00000000*/

8629

8630 /* reserved bits */

8631 UINT32 NumLbrs : 5;

8632

8633 /* Bits[28:24], Access Type=RW, default=0x00000000*/

8634

8635 /* Num lbrs bits */

8636 UINT32 Rsvd29 : 3;

8637

8638 /* Bits[31:29], Access Type=RW, default=0x00000000*/

8639

8640 /* reserved bits */

8641 UINT32 Rsvd32 : 32;

8642

8643 /* Bits[63:32], Access Type=RW, default=0x00000000*/

8644

8645 /* reserved bits */

8646

8647 } Bits;

8648

8649 UINT32 Uint32;

8650 UINT64 Uint64;

8651

8652 } MSR_PEBS_DATA_CFG_REGISTER;

8653

8654 /**

8655 Machine Check Control Register

8656 **/

8657 #define MSR_MC0_CTL 0x00000400

8658

8659 typedef union {

8660 ///

8661 /// Individual bit fields

8662 ///

8663 struct {

8664 UINT32 EnableRob : 1;

8665

8666 /* Bits[0:0], Access Type=RW, default=0x00000000*/

8667

8668 /* Enable ROB MCA Logging */

8669 UINT32 EnableMs : 1;

8670

8671 /* Bits[1:1], Access Type=RW, default=0x00000000*/

8672

8673 /* Enable MS MCA Logging */

8674 UINT32 EnableIq : 1;

8675

8676 /* Bits[2:2], Access Type=RW, default=0x00000000*/

8677

8678 /* Enable IQ MCA Logging */

8679 UINT32 EnableIfu : 1;

8680

8681 /* Bits[3:3], Access Type=RW, default=0x00000000*/

8682

8683 /* Enable IFU MCA Logging */

8684 UINT32 EnableDsb : 1;

8685

8686 /* Bits[4:4], Access Type=RW, default=0x00000000*/

8687

8688 /* Enable DSB MCA Logging */

8689 UINT32 EnableIdq : 1;

8690

8691 /* Bits[5:5], Access Type=RW, default=0x00000000*/

8692

8693 /* Enable IDQ MCA Logging */

8694 UINT32 EnableUrom : 1;

8695

8696 /* Bits[6:6], Access Type=RW, default=0x00000000*/

8697

8698 /* Enable UROM MCA Logging */

8699 UINT32 EnableBit : 1;

8700

8701 /* Bits[7:7], Access Type=RW, default=0x00000000*/

8702

8703 /* Enable BIT MCA Logging */

8704 UINT32 Reserved8 : 1;

8705

8706 /* Bits[8:8], Access Type=RW, default=0x00000000*/

8707

8708 /*

8709 Reserved bit previously used for SCP parity in

8710 FIT but no longer needed

8711 */

8712 UINT32 EnableSdb : 1;

8713

8714 /* Bits[9:9], Access Type=RW, default=0x00000000*/

8715

8716 /* Enable SDB MCA Logging */

8717 UINT32 EnableExe : 1;

8718

8719 /* Bits[10:10], Access Type=RW, default=0x00000000*/

8720

8721 /* Enable EXE MCA Logging */

8722 UINT32 EnableRs : 1;

8723

8724 /* Bits[11:11], Access Type=RW, default=0x00000000*/

8725

8726 /* Enable RS MCA Logging */

8727 UINT32 Rsvd12 : 20;

8728

8729 /* Bits[31:12], Access Type=RO, default=None*/

8730

8731 /* Reserved */

8732 UINT32 Rsvd32 : 32;

8733

8734 /* Bits[63:32], Access Type=RO, default=None*/

8735

8736 /* Reserved */

8737

8738 } Bits;

8739

8740 UINT32 Uint32;

8741 UINT64 Uint64;

8742

8743 } MSR_MC0_CTL_REGISTER;

8744

8745 /**

8746 Machine Check Status Register

8747 **/

8748 #define MSR_MC0_STATUS 0x00000401

8749

8750 typedef union {

8751 ///

8752 /// Individual bit fields

8753 ///

8754 struct {

8755 UINT32 Mcacod : 11;

8756

8757 /* Bits[10:0], Access Type=RW_V, default=None*/

8758

8759 /* Machine Check Architecture Error Code */

8760 UINT32 EnhMcaAvail0 : 5;

8761

8762 /* Bits[15:11], Access Type=RW_V, default=None*/

8763

8764 /* Reserved bits */

8765 UINT32 Mscod : 4;

8766

8767 /* Bits[19:16], Access Type=RW_V, default=None*/

8768

8769 /* Machine Specific Architecture Error Code */

8770 UINT32 EnhMcaAvail10 : 12;

8771

8772 /* Bits[31:20], Access Type=RW_V, default=None*/

8773

8774 /* Reserved bits */

8775 UINT32 EnhMcaAvail11 : 6;

8776

8777 /* Bits[37:32], Access Type=RW_V, default=None*/

8778

8779 /* Reserved bits */

8780 UINT32 CorrectedErrCnt : 14;

8781

8782 /* Bits[51:38], Access Type=RW_V, default=None*/

8783

8784 /*

8785 Corrected error count since last clear of mc

8786 regs

8787 */

8788 UINT32 Sticky : 1;

8789

8790 /* Bits[52:52], Access Type=RW_V, default=None*/

8791

8792 /* Sticky bit set when error count overflows */

8793 UINT32 EnhMcaAvail2 : 2;

8794

8795 /* Bits[54:53], Access Type=RW_V, default=None*/

8796

8797 /* Reserved bits */

8798 UINT32 Ar : 1;

8799

8800 /* Bits[55:55], Access Type=RW_V, default=None*/

8801

8802 /* Action required */

8803 UINT32 S : 1;

8804

8805 /* Bits[56:56], Access Type=RW_V, default=None*/

8806

8807 /* Signaling */

8808 UINT32 Pcc : 1;

8809

8810 /* Bits[57:57], Access Type=RW_V, default=None*/

8811

8812 /* Processor Context Corrupt */

8813 UINT32 Addrv : 1;

8814

8815 /* Bits[58:58], Access Type=RW_V, default=None*/

8816

8817 /* MC0_ADDR register valid */

8818 UINT32 Miscv : 1;

8819

8820 /* Bits[59:59], Access Type=RW_V, default=None*/

8821

8822 /* MC0_MISC register valid */

8823 UINT32 En : 1;

8824

8825 /* Bits[60:60], Access Type=RW_V, default=None*/

8826

8827 /* Error Enabled */

8828 UINT32 Uc : 1;

8829

8830 /* Bits[61:61], Access Type=RW_V, default=None*/

8831

8832 /* Uncorrectable Error */

8833 UINT32 Over : 1;

8834

8835 /* Bits[62:62], Access Type=RW_V, default=None*/

8836

8837 /* Machine Check Overflow */

8838 UINT32 Val : 1;

8839

8840 /* Bits[63:63], Access Type=RW_V, default=None*/

8841

8842 /* Status register Valid */

8843

8844 } Bits;

8845

8846 UINT32 Uint32;

8847 UINT64 Uint64;

8848

8849 } MSR_MC0_STATUS_REGISTER;

8850

8851 /**

8852 Machine Check Address Register

8853 **/

8854 #define MSR_MC0_ADDR 0x00000402

8855

8856 typedef union {

8857 ///

8858 /// Individual bit fields

8859 ///

8860 struct {

8861 UINT32 Addr0 : 32;

8862

8863 /* Bits[31:0], Access Type=RW_V, default=None*/

8864

8865 /* LIP of access */

8866 UINT32 Addr1 : 26;

8867

8868 /* Bits[57:32], Access Type=RW_V, default=None*/

8869

8870 /* LIP of access */

8871 UINT32 EnhMcaAvail0 : 6;

8872

8873 /* Bits[63:58], Access Type=RW_V, default=None*/

8874

8875 /* Reserved bits */

8876

8877 } Bits;

8878

8879 UINT32 Uint32;

8880 UINT64 Uint64;

8881

8882 } MSR_MC0_ADDR_REGISTER;

8883

8884 /**

8885 Machine Check Misc Register

8886 **/

8887 #define MSR_MC0_MISC 0x00000403

8888

8889 typedef union {

8890 ///

8891 /// Individual bit fields

8892 ///

8893 struct {

8894 UINT32 IfuAddrLsb : 6;

8895

8896 /* Bits[5:0], Access Type=RW, default=None*/

8897

8898 /*

8899 address mode (physical,linear,segment

8900 offset,memory,generic)

8901 */

8902 UINT32 AddressMode : 3;

8903

8904 /* Bits[8:6], Access Type=RW, default=None*/

8905

8906 /*

8907 address mode (physical,linear,segment

8908 offset,memory,generic)

8909 */

8910 UINT32 EnhMcaAvail00 : 23;

8911

8912 /* Bits[31:9], Access Type=RW, default=None*/

8913

8914 /* Reserved bits */

8915 UINT32 EnhMcaAvail01 : 32;

8916

8917 /* Bits[63:32], Access Type=RW, default=None*/

8918

8919 /* Reserved bits */

8920

8921 } Bits;

8922

8923 UINT32 Uint32;

8924 UINT64 Uint64;

8925

8926 } MSR_MC0_MISC_REGISTER;

8927

8928 /**

8929 Machine Check Control Register

8930 **/

8931 #define MSR_MC1_CTL 0x00000404

8932

8933 typedef union {

8934 ///

8935 /// Individual bit fields

8936 ///

8937 struct {

8938 UINT32 En : 1;

8939

8940 /* Bits[0:0], Access Type=RW, default=0x00000000*/

8941

8942 /*

8943 Enable or Disable all error signaling in the MC

8944 bank1

8945 */

8946 UINT32 Rsvd1 : 31;

8947

8948 /* Bits[31:1], Access Type=RO, default=None*/

8949

8950 /* Reserved */

8951 UINT32 Rsvd32 : 32;

8952

8953 /* Bits[63:32], Access Type=RO, default=None*/

8954

8955 /* Reserved */

8956

8957 } Bits;

8958

8959 UINT32 Uint32;

8960 UINT64 Uint64;

8961

8962 } MSR_MC1_CTL_REGISTER;

8963

8964 /**

8965 Machine Check Status Register

8966 **/

8967 #define MSR_MC1_STATUS 0x00000405

8968

8969 typedef union {

8970 ///

8971 /// Individual bit fields

8972 ///

8973 struct {

8974 UINT32 Mcacod : 16;

8975

8976 /* Bits[15:0], Access Type=RW_V, default=None*/

8977

8978 /*

8979 Machine Check Architecture Error Code: Ld,St,

8980 Apic, Eviction, Posion or Snoop Error

8981 */

8982 UINT32 Mscod0 : 16;

8983

8984 /* Bits[31:16], Access Type=RW_V, default=None*/

8985

8986 /* Model Specific Error Code. */

8987 UINT32 Mscod1 : 6;

8988

8989 /* Bits[37:32], Access Type=RW_V, default=None*/

8990

8991 /* Model Specific Error Code. */

8992 UINT32 Cecnt : 15;

8993

8994 /* Bits[52:38], Access Type=RW_V, default=None*/

8995

8996 /*

8997 This field increments for every correctable

8998 error detected in the DCU even if an uncorrected

8999 error is already logged. If the counter

9000 overflows the bit 52 of this register will be

9001 sticky. This bit will only cleared by software.

9002 */

9003 UINT32 EnhMcaAvail : 2;

9004

9005 /* Bits[54:53], Access Type=RW_V, default=None*/

9006

9007 /* Available when Enhnaced MCA is in use */

9008 UINT32 Ar : 1;

9009

9010 /* Bits[55:55], Access Type=RW_V, default=None*/

9011

9012 /*

9013 AR stands for Action Required. When set it means

9014 that error logged requires handling by SW before

9015 it can resume execution otherwise it will have

9016 to fail if it is not able to handle it. When

9017 clear it means that error recovery action is

9018 optional for the SW and if it can not handle it

9019 there is no need to bring down the sytem.

9020 */

9021 UINT32 S : 1;

9022

9023 /* Bits[56:56], Access Type=RW_V, default=None*/

9024

9025 /*

9026 S bit: When set it means that the error logged

9027 was signaled via MCE. Clear means that the error

9028 was signled via CMCI.

9029 */

9030 UINT32 Pcc : 1;

9031

9032 /* Bits[57:57], Access Type=RW_V, default=None*/

9033

9034 /*

9035 Processor Context Corrupt indicates if machine

9036 state damage has occurred as a result of the

9037 error.

9038 */

9039 UINT32 Addrv : 1;

9040

9041 /* Bits[58:58], Access Type=RW_V, default=None*/

9042

9043 /*

9044 Indicates if there is an address associated with

9045 the reported error.

9046 */

9047 UINT32 Miscv : 1;

9048

9049 /* Bits[59:59], Access Type=RW_V, default=None*/

9050

9051 /*

9052 Indicates if the MC1_MISC register contains

9053 valid data

9054 */

9055 UINT32 En : 1;

9056

9057 /* Bits[60:60], Access Type=RW_V, default=None*/

9058

9059 /* The enabled error bit. */

9060 UINT32 Uc : 1;

9061

9062 /* Bits[61:61], Access Type=RW_V, default=None*/

9063

9064 /*

9065 The uncorrected error bit. It indicates that the

9066 error is uncorrected when set.

9067 */

9068 UINT32 O : 1;

9069

9070 /* Bits[62:62], Access Type=RW_V, default=None*/

9071

9072 /*

9073 The overflow bit. It indicates that an error has

9074 occurred while the valid bit is set.

9075 */

9076 UINT32 V : 1;

9077

9078 /* Bits[63:63], Access Type=RW_V, default=None*/

9079

9080 /*

9081 The valid bit. It indicates if the error

9082 information in this register is Valid ('1) or

9083 Invalid ('0). This bit is set by hardware when

9084 an error (correctable or uncorrectable) is

9085 written into the register. It is cleared only by

9086 software.

9087 */

9088

9089 } Bits;

9090

9091 UINT32 Uint32;

9092 UINT64 Uint64;

9093

9094 } MSR_MC1_STATUS_REGISTER;

9095

9096 /**

9097 Machine Check Address Register

9098 **/

9099 #define MSR_MC1_ADDR 0x00000406

9100

9101 typedef union {

9102 ///

9103 /// Individual bit fields

9104 ///

9105 struct {

9106 UINT32 Low : 32;

9107

9108 /* Bits[31:0], Access Type=RW_V, default=None*/

9109

9110 /*

9111 Lower physical address of a uop which either a

9112 correctable/uncorrectable parity err

9113 */

9114 UINT32 High : 20;

9115

9116 /* Bits[51:32], Access Type=RW_V, default=None*/

9117

9118 /*

9119 Upper physical address of a uop which either a

9120 correctable/uncorrectable parity err

9121 */

9122 UINT32 EnhMcaAvail : 12;

9123

9124 /* Bits[63:52], Access Type=RW_V, default=None*/

9125

9126 /*

9127 Available to software when Enhnaced MCA is in

9128 use

9129 */

9130

9131 } Bits;

9132

9133 UINT32 Uint32;

9134 UINT64 Uint64;

9135

9136 } MSR_MC1_ADDR_REGISTER;

9137

9138 /**

9139 Machine Check Status Register

9140 **/

9141 #define MSR_MC1_MISC 0x00000407

9142

9143 typedef union {

9144 ///

9145 /// Individual bit fields

9146 ///

9147 struct {

9148 UINT32 Recaddrlsb : 6;

9149

9150 /* Bits[5:0], Access Type=RW_V, default=None*/

9151

9152 /*

9153 OS should treat Machine check address from

9154 resolution of LSB (ignore LSB-1:0 bits of given

9155 address in MC0_ADDR)

9156 */

9157 UINT32 Addrmode : 3;

9158

9159 /* Bits[8:6], Access Type=RW_V, default=None*/

9160

9161 /*

9162 OS should treat Machine check address from

9163 resolution of LSB (ignore LSB-1:0 bits of given

9164 address in MC0_ADDR)

9165 */

9166 UINT32 EnhMcaAvail0 : 23;

9167

9168 /* Bits[31:9], Access Type=RW_V, default=None*/

9169

9170 /*

9171 Available to software when Enhnaced MCA is in

9172 use.

9173 */

9174 UINT32 EnhMcaAvail1 : 32;

9175

9176 /* Bits[63:32], Access Type=RW_V, default=None*/

9177

9178 /*

9179 Available to software when Enhnaced MCA is in

9180 use.

9181 */

9182

9183 } Bits;

9184

9185 UINT32 Uint32;

9186 UINT64 Uint64;

9187

9188 } MSR_MC1_MISC_REGISTER;

9189

9190 /**

9191 Machine Check Control Register

9192 **/

9193 #define MSR_MC2_CTL 0x00000408

9194

9195 typedef union {

9196 ///

9197 /// Individual bit fields

9198 ///

9199 struct {

9200 UINT32 EnDtlb : 1;

9201

9202 /* Bits[0:0], Access Type=RW, default=0x00000000*/

9203

9204 /* Enable bit for MC signaling */

9205 UINT32 EnFscp : 1;

9206

9207 /* Bits[1:1], Access Type=RW, default=0x00000000*/

9208

9209 /* Enable bit for MC signaling */

9210 UINT32 EnSrf : 1;

9211

9212 /* Bits[2:2], Access Type=RW, default=0x00000000*/

9213

9214 /* Enable bit for MC signaling */

9215 UINT32 Rsvd3 : 29;

9216

9217 /* Bits[31:3], Access Type=RO, default=None*/

9218

9219 /* Reserved */

9220 UINT32 Rsvd32 : 32;

9221

9222 /* Bits[63:32], Access Type=RO, default=None*/

9223

9224 /* Reserved */

9225

9226 } Bits;

9227

9228 UINT32 Uint32;

9229 UINT64 Uint64;

9230

9231 } MSR_MC2_CTL_REGISTER;

9232

9233 /**

9234 DTLB Machine Check Status register

9235 **/

9236 #define MSR_MC2_STATUS 0x00000409

9237

9238 typedef union {

9239 ///

9240 /// Individual bit fields

9241 ///

9242 struct {

9243 UINT32 Mcacod : 16;

9244

9245 /* Bits[15:0], Access Type=RW_V, default=None*/

9246

9247 /* Model Specific Error Code */

9248 UINT32 Mscod : 16;

9249

9250 /* Bits[31:16], Access Type=RW_V, default=None*/

9251

9252 /*

9253 Error type - Dat-parity = 0x0001 Tag-parity =

9254 0x0000

9255 */

9256 UINT32 EnhMcaAvail0 : 6;

9257

9258 /* Bits[37:32], Access Type=RW_V, default=None*/

9259

9260 /* Available when Enhanced MCA is in use */

9261 UINT32 CorErrCnt : 15;

9262

9263 /* Bits[52:38], Access Type=RW_V, default=None*/

9264

9265 /* Correctable error counter */

9266 UINT32 EnhMcaAvail1 : 4;

9267

9268 /* Bits[56:53], Access Type=RW_V, default=None*/

9269

9270 /* Available when Enhanced MCA is in use */

9271 UINT32 Pcc : 1;

9272

9273 /* Bits[57:57], Access Type=RW_V, default=None*/

9274

9275 /*

9276 Processor Context Corrupt - State damage has

9277 occurred

9278 */

9279 UINT32 Adrv : 1;

9280

9281 /* Bits[58:58], Access Type=RW_V, default=None*/

9282

9283 /*

9284 MCi_ADDR register is valid for signalled MCA

9285 error

9286 */

9287 UINT32 Miscv : 1;

9288

9289 /* Bits[59:59], Access Type=RW_V, default=None*/

9290

9291 /*

9292 MCi_MISC register is valid for signalled MCA

9293 error

9294 */

9295 UINT32 En : 1;

9296

9297 /* Bits[60:60], Access Type=RW_V, default=None*/

9298

9299 /* Error Enabled */

9300 UINT32 Uc : 1;

9301

9302 /* Bits[61:61], Access Type=RW_V, default=None*/

9303

9304 /* Uncorrectable Error */

9305 UINT32 Over : 1;

9306

9307 /* Bits[62:62], Access Type=RW_V, default=None*/

9308

9309 /*

9310 Set if MCA error detected and valid bit already

9311 set for previous error

9312 */

9313 UINT32 Valid : 1;

9314

9315 /* Bits[63:63], Access Type=RW_V, default=None*/

9316

9317 /* Set if MCA error detected */

9318

9319 } Bits;

9320

9321 UINT32 Uint32;

9322 UINT64 Uint64;

9323

9324 } MSR_MC2_STATUS_REGISTER;

9325 /**

9326 Machine Check Address Register

9327 **/

9328 #define MSR_MC2_ADDR 0x0000040A

9329 /**

9330 Machine Check Misc Register

9331 **/

9332 #define MSR_MC2_MISC 0x0000040B

9333

9334 /**

9335 Machine Check Control Register

9336 **/

9337 #define MSR_MC3_CTL 0x0000040C

9338

9339 typedef union {

9340 ///

9341 /// Individual bit fields

9342 ///

9343 struct {

9344 UINT32 MlcTagError : 1;

9345

9346 /* Bits[0:0], Access Type=RW, default=0x00000000*/

9347

9348 /* Enable machine check signaling */

9349 UINT32 MlcSqdbIdiParError : 1;

9350

9351 /* Bits[1:1], Access Type=RW, default=0x00000000*/

9352

9353 /* Enable machine check signaling */

9354 UINT32 MlcDataError : 1;

9355

9356 /* Bits[2:2], Access Type=RW, default=0x00000000*/

9357

9358 /* Enable machine check signaling */

9359 UINT32 MlcMesiStateError : 1;

9360

9361 /* Bits[3:3], Access Type=RW, default=0x00000000*/

9362

9363 /* Enable machine check signaling */

9364 UINT32 MlcDpfPoisonError : 1;

9365

9366 /* Bits[4:4], Access Type=RW, default=0x00000000*/

9367

9368 /* Enable machine check signaling */

9369 UINT32 MlcIdiAddrParError : 1;

9370

9371 /* Bits[5:5], Access Type=RW, default=0x00000000*/

9372

9373 /* Enable machine check signaling */

9374 UINT32 Rsvd6 : 26;

9375

9376 /* Bits[31:6], Access Type=RO, default=None*/

9377

9378 /* Reserved */

9379 UINT32 Rsvd32 : 32;

9380

9381 /* Bits[63:32], Access Type=RO, default=None*/

9382

9383 /* Reserved */

9384

9385 } Bits;

9386

9387 UINT32 Uint32;

9388 UINT64 Uint64;

9389

9390 } MSR_MC3_CTL_REGISTER;

9391

9392 /**

9393 Machine Check Status Register

9394 **/

9395 #define MSR_MC3_STATUS 0x0000040D

9396

9397 typedef union {

9398 ///

9399 /// Individual bit fields

9400 ///

9401 struct {

9402 UINT32 Mcacod : 16;

9403

9404 /* Bits[15:0], Access Type=RW_V, default=None*/

9405

9406 /* Machine Check Architecture Error Code */

9407 UINT32 Mscod : 16;

9408

9409 /* Bits[31:16], Access Type=RW_V, default=None*/

9410

9411 /* Model Specific Error Code */

9412 UINT32 EnhMcaAvail0 : 6;

9413

9414 /* Bits[37:32], Access Type=RW_V, default=None*/

9415

9416 /* Available when Enhnaced MCA is in use */

9417 UINT32 Cec : 15;

9418

9419 /* Bits[52:38], Access Type=RW_V, default=None*/

9420

9421 /* Correctable Error Count */

9422 UINT32 BitfixAllocated : 1;

9423

9424 /* Bits[53:53], Access Type=RW_V, default=None*/

9425

9426 /*

9427 Status tracking is Green if this bit is set when

9428 a logged error is allocated into bitfix CAM

9429 */

9430 UINT32 BitfixOvercapacity : 1;

9431

9432 /* Bits[54:54], Access Type=RW_V, default=None*/

9433

9434 /*

9435 Status tracking is Yellow if this bit is set

9436 when a logged error overflows bitfix CAM (and

9437 bitfixing is enabled)

9438 */

9439 UINT32 EnhMcaAvail1 : 2;

9440

9441 /* Bits[56:55], Access Type=RW_V, default=None*/

9442

9443 /* Available when Enhnaced MCA is in use */

9444 UINT32 Pcc : 1;

9445

9446 /* Bits[57:57], Access Type=RW_V, default=None*/

9447

9448 /* Processor Context Corrupt */

9449 UINT32 Addrv : 1;

9450

9451 /* Bits[58:58], Access Type=RW_V, default=None*/

9452

9453 /* MC3_ADDR register valid */

9454 UINT32 Miscv : 1;

9455

9456 /* Bits[59:59], Access Type=RW_V, default=None*/

9457

9458 /* MC3_MISC register valid */

9459 UINT32 En : 1;

9460

9461 /* Bits[60:60], Access Type=RW_V, default=None*/

9462

9463 /* Error Enabled */

9464 UINT32 Uc : 1;

9465

9466 /* Bits[61:61], Access Type=RW_V, default=None*/

9467

9468 /* Uncorrectable Error */

9469 UINT32 Over : 1;

9470

9471 /* Bits[62:62], Access Type=RW_V, default=None*/

9472

9473 /* Machine Check Overflow */

9474 UINT32 Val : 1;

9475

9476 /* Bits[63:63], Access Type=RW_V, default=None*/

9477

9478 /* Status register Valid */

9479

9480 } Bits;

9481

9482 UINT32 Uint32;

9483 UINT64 Uint64;

9484

9485 } MSR_MC3_STATUS_REGISTER;

9486

9487 /**

9488 Machine Check Address Register

9489 **/

9490 #define MSR_MC3_ADDR 0x0000040E

9491

9492 typedef union {

9493 ///

9494 /// Individual bit fields

9495 ///

9496 struct {

9497 UINT32 Addr0 : 32;

9498

9499 /* Bits[31:0], Access Type=RW_V, default=None*/

9500

9501 /* Address of the request that got an error */

9502 UINT32 Addr1 : 20;

9503

9504 /* Bits[51:32], Access Type=RW_V, default=None*/

9505

9506 /* Address of the request that got an error */

9507 UINT32 EnhMcaAvail : 12;

9508

9509 /* Bits[63:52], Access Type=RW_V, default=None*/

9510

9511 /* Available when Enhnaced MCA is in use */

9512

9513 } Bits;

9514

9515 UINT32 Uint32;

9516 UINT64 Uint64;

9517

9518 } MSR_MC3_ADDR_REGISTER;

9519

9520 /**

9521 Machine Check Misc Register

9522 **/

9523 #define MSR_MC3_MISC 0x0000040F

9524

9525 typedef union {

9526 ///

9527 /// Individual bit fields

9528 ///

9529 struct {

9530 UINT32 Recaddrlsb : 6;

9531

9532 /* Bits[5:0], Access Type=RW_V, default=None*/

9533

9534 /* Const: 000101 */

9535 UINT32 Addrmode : 3;

9536

9537 /* Bits[8:6], Access Type=RW_V, default=None*/

9538

9539 /* Const: 010 */

9540 UINT32 Opcode : 7;

9541

9542 /* Bits[15:9], Access Type=RW_V, default=None*/

9543

9544 /* Opcode */

9545 UINT32 Sqid : 5;

9546

9547 /* Bits[20:16], Access Type=RW_V, default=None*/

9548

9549 /* SQID */

9550 UINT32 Way : 5;

9551

9552 /* Bits[25:21], Access Type=RW_V, default=None*/

9553

9554 /* Way */

9555 UINT32 Thread : 1;

9556

9557 /* Bits[26:26], Access Type=RW_V, default=None*/

9558

9559 /* Thread */

9560 UINT32 EnhMcaAvail0 : 5;

9561

9562 /* Bits[31:27], Access Type=RW_V, default=None*/

9563

9564 /* Available when Enhnaced MCA is in use */

9565 UINT32 EnhMcaAvail1 : 32;

9566

9567 /* Bits[63:32], Access Type=RW_V, default=None*/

9568

9569 /* Available when Enhnaced MCA is in use */

9570

9571 } Bits;

9572

9573 UINT32 Uint32;

9574 UINT64 Uint64;

9575

9576 } MSR_MC3_MISC_REGISTER;

9577

9578 /**

9579 MEE and Ucode/Xucode bank: Control register

9580 **/

9581 #define MSR_MC4_CTL 0x00000410

9582

9583 typedef union {

9584 ///

9585 /// Individual bit fields

9586 ///

9587 struct {

9588 UINT32 Ee00 : 1;

9589

9590 /* Bits[0:0], Access Type=RW, default=0x00000000*/

9591

9592 /*

9593 LLC: Uncorrectable tag error flag Enable

9594 signaling of Uncorrectable Tag error which

9595 includes : Tag/MESI/CV/GFDT

9596 */

9597 UINT32 Ee01 : 1;

9598

9599 /* Bits[1:1], Access Type=RW, default=0x00000000*/

9600

9601 /*

9602 Flag enables signaling of all errors by MCA

9603 message

9604 */

9605 UINT32 Rsvd2 : 30;

9606

9607 /* Bits[31:2], Access Type=RO, default=None*/

9608

9609 /* Reserved */

9610 UINT32 Rsvd32 : 32;

9611

9612 /* Bits[63:32], Access Type=RO, default=None*/

9613

9614 /* Reserved */

9615

9616 } Bits;

9617

9618 UINT32 Uint32;

9619 UINT64 Uint64;

9620

9621 } MSR_MC4_CTL_REGISTER;

9622

9623 /**

9624 MEE and Ucode/Xucode MCA bank: Status register

9625 **/

9626 #define MSR_MC4_STATUS 0x00000411

9627

9628 typedef union {

9629 ///

9630 /// Individual bit fields

9631 ///

9632 struct {

9633 UINT32 Mcacod : 16;

9634

9635 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

9636

9637 /* MCA error code */

9638 UINT32 Mscod : 16;

9639

9640 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

9641

9642 /* Model specific error code */

9643 UINT32 OtherInfo : 6;

9644

9645 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

9646

9647 /* Other info */

9648 UINT32 CorrectedErrorCount : 15;

9649

9650 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

9651

9652 /* Correctable error count */

9653 UINT32 ThresholdBasedErrorStatus : 2;

9654

9655 /* Bits[54:53], Access Type=RWS_V, default=0x00000000*/

9656

9657 /*

9658 These bits are used to indicate when the number

9659 of corrected errors has exceeded the safe

9660 threshold to the point where an uncorrected

9661 error has become more likely to happen.

9662 */

9663 UINT32 Ar : 1;

9664

9665 /* Bits[55:55], Access Type=RWS_V, default=0x00000000*/

9666

9667 /* Available when Enhanced MCA is in use */

9668 UINT32 S : 1;

9669

9670 /* Bits[56:56], Access Type=RWS_V, default=0x00000000*/

9671

9672 /* Available when Enhanced MCA is in use */

9673 UINT32 Pcc : 1;

9674

9675 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

9676

9677 /* PCC: Processor context corrupt */

9678 UINT32 Addrv : 1;

9679

9680 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

9681

9682 /*

9683 ADDRV: The address held in the MC4_ADDR_MSR is

9684 valid

9685 */

9686 UINT32 Miscv : 1;

9687

9688 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

9689

9690 /*

9691 MISCV: The value held in the MC4_MISC_MSR is

9692 valid

9693 */

9694 UINT32 En : 1;

9695

9696 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

9697

9698 /*

9699 EN: Error enabled flag Indicates (when set) that

9700 signaling of the machine check exception for

9701 this error was enabled by an associated flag bit

9702 of the Mci_CTL register.

9703 */

9704 UINT32 Uc : 1;

9705

9706 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

9707

9708 /*

9709 UC: Error uncorrected flag Indicates (when set)

9710 that the processor did not correct the error

9711 condition. When clear, this flag indicates that

9712 the processor was able to correct the error

9713 condition.

9714 */

9715 UINT32 Over : 1;

9716

9717 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

9718

9719 /* OVER: Machine check overflow */

9720 UINT32 Val : 1;

9721

9722 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

9723

9724 /*

9725 VAL: Valid flag Indicates (when set) that the

9726 information within the Mci_STATUS register is

9727 valid. When this flag is set, the processor

9728 follows the rules given for the OVER flag in the

9729 Mci_STATUS register when overwriting previously

9730 valid entries. The processor sets the VAL flag

9731 and software is responsible for clearing it.

9732 */

9733

9734 } Bits;

9735

9736 UINT32 Uint32;

9737 UINT64 Uint64;

9738

9739 } MSR_MC4_STATUS_REGISTER;

9740 /**

9741 MEE and Ucode/Xucode bank: Address register

9742 **/

9743 #define MSR_MC4_ADDR 0x00000412

9744

9745 /**

9746 MMEE and Ucode/Xucode bank: Misc register

9747 **/

9748 #define MSR_MC4_MISC 0x00000413

9749

9750 typedef union {

9751 ///

9752 /// Individual bit fields

9753 ///

9754 struct {

9755 UINT32 RecoverableAddressLsb : 6;

9756

9757 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

9758

9759 /* Points to where the supported LSB in MCi_Addr */

9760 UINT32 AddressMode : 3;

9761

9762 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

9763

9764 /*

9765 Address Mode = 010 since we always have only PA

9766 in the SNB LLC

9767 */

9768 UINT32 ModelSpecifcInfoEntry : 10;

9769

9770 /* Bits[18:9], Access Type=RWS_V, default=0x00000000*/

9771

9772 /*

9773 The cache/TLC entry associated with the looged

9774 error

9775 */

9776 UINT32 ModelSpecifcInfoBank : 3;

9777

9778 /* Bits[21:19], Access Type=RWS_V, default=0x00000000*/

9779

9780 /* The cache bank associated with the looged error */

9781 UINT32 ModelSpecifcInfoSource : 1;

9782

9783 /* Bits[22:22], Access Type=RWS_V, default=0x00000000*/

9784

9785 /*

9786 The ECC source of failure (Cache ECC failure =

9787 0, TLC ECC failure = 1)

9788 */

9789 UINT32 ModelSpecifcInfo0 : 9;

9790

9791 /* Bits[31:23], Access Type=RWS_V, default=0x00000000*/

9792

9793 /* Available when Enhanced MCA is in use */

9794 UINT32 ModelSpecifcInfo1 : 32;

9795

9796 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

9797

9798 /* Available when Enhanced MCA is in use */

9799

9800 } Bits;

9801

9802 UINT32 Uint32;

9803 UINT64 Uint64;

9804

9805 } MSR_MC4_MISC_REGISTER;

9806

9807 /**

9808 MEE1 bank: Control register

9809 **/

9810 #define MSR_MC5_CTL 0x00000414

9811

9812 typedef union {

9813 ///

9814 /// Individual bit fields

9815 ///

9816 struct {

9817 UINT32 Ee00 : 1;

9818

9819 /* Bits[0:0], Access Type=RW, default=0x00000000*/

9820

9821 /* MC bank enable bit */

9822 UINT32 Ee01 : 1;

9823

9824 /* Bits[1:1], Access Type=RW, default=0x00000000*/

9825

9826 /*

9827 Flag enables signaling of all errors by MCA

9828 message

9829 */

9830 UINT32 Rsvd2 : 30;

9831

9832 /* Bits[31:2], Access Type=RO, default=None*/

9833

9834 /* Reserved */

9835 UINT32 Rsvd32 : 32;

9836

9837 /* Bits[63:32], Access Type=RO, default=None*/

9838

9839 /* Reserved */

9840

9841 } Bits;

9842

9843 UINT32 Uint32;

9844 UINT64 Uint64;

9845

9846 } MSR_MC5_CTL_REGISTER;

9847

9848 /**

9849 MEE1 bank: Status register

9850 **/

9851 #define MSR_MC5_STATUS 0x00000415

9852

9853 typedef union {

9854 ///

9855 /// Individual bit fields

9856 ///

9857 struct {

9858 UINT32 Mcacod : 16;

9859

9860 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

9861

9862 /* MCA error code */

9863 UINT32 Mscod : 16;

9864

9865 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

9866

9867 /* Model specific error code */

9868 UINT32 OtherInfo : 6;

9869

9870 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

9871

9872 /* Other info */

9873 UINT32 CorrectedErrorCount : 15;

9874

9875 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

9876

9877 /* Correctable error count */

9878 UINT32 ThresholdBasedErrorStatus : 2;

9879

9880 /* Bits[54:53], Access Type=RWS_V, default=0x00000000*/

9881

9882 /*

9883 These bits are used to indicate when the number

9884 of corrected errors has exceeded the safe

9885 threshold to the point where an uncorrected

9886 error has become more likely to happen.

9887 */

9888 UINT32 Ar : 1;

9889

9890 /* Bits[55:55], Access Type=RWS_V, default=0x00000000*/

9891

9892 /* Available when Enhanced MCA is in use */

9893 UINT32 S : 1;

9894

9895 /* Bits[56:56], Access Type=RWS_V, default=0x00000000*/

9896

9897 /* Available when Enhanced MCA is in use */

9898 UINT32 Pcc : 1;

9899

9900 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

9901

9902 /* PCC: Processor context corrupt */

9903 UINT32 Addrv : 1;

9904

9905 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

9906

9907 /*

9908 ADDRV: The address held in the MC5_ADDR_MSR is

9909 valid

9910 */

9911 UINT32 Miscv : 1;

9912

9913 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

9914

9915 /*

9916 MISCV: The value held in the MC5_MISC_MSR is

9917 valid

9918 */

9919 UINT32 En : 1;

9920

9921 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

9922

9923 /*

9924 EN: Error enabled flag Indicates (when set) that

9925 signaling of the machine check exception for

9926 this error was enabled by an associated flag bit

9927 of the Mci_CTL register.

9928 */

9929 UINT32 Uc : 1;

9930

9931 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

9932

9933 /*

9934 UC: Error uncorrected flag Indicates (when set)

9935 that the processor did not correct the error

9936 condition. When clear, this flag indicates that

9937 the processor was able to correct the error

9938 condition.

9939 */

9940 UINT32 Over : 1;

9941

9942 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

9943

9944 /* OVER: Machine check overflow */

9945 UINT32 Val : 1;

9946

9947 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

9948

9949 /*

9950 VAL: Valid flag Indicates (when set) that the

9951 information within the Mci_STATUS register is

9952 valid. When this flag is set, the processor

9953 follows the rules given for the OVER flag in the

9954 Mci_STATUS register when overwriting previously

9955 valid entries. The processor sets the VAL flag

9956 and software is responsible for clearing it.

9957 */

9958

9959 } Bits;

9960

9961 UINT32 Uint32;

9962 UINT64 Uint64;

9963

9964 } MSR_MC5_STATUS_REGISTER;

9965 /**

9966 MEE1 bank: Address register

9967 **/

9968 #define MSR_MC5_ADDR 0x00000416

9969

9970 /**

9971 MMEE1 bank: Misc register

9972 **/

9973 #define MSR_MC5_MISC 0x00000417

9974

9975 typedef union {

9976 ///

9977 /// Individual bit fields

9978 ///

9979 struct {

9980 UINT32 RecoverableAddressLsb : 6;

9981

9982 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

9983

9984 /* Points to where the supported LSB in MCi_Addr */

9985 UINT32 AddressMode : 3;

9986

9987 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

9988

9989 /* Address Mode */

9990 UINT32 ModelSpecifcInfoEntry : 10;

9991

9992 /* Bits[18:9], Access Type=RWS_V, default=0x00000000*/

9993

9994 /*

9995 The cache/TLC entry associated with the looged

9996 error

9997 */

9998 UINT32 ModelSpecifcInfoBank : 3;

9999

10000 /* Bits[21:19], Access Type=RWS_V, default=0x00000000*/

10001

10002 /* The cache bank associated with the looged error */

10003 UINT32 ModelSpecifcInfoSource : 1;

10004

10005 /* Bits[22:22], Access Type=RWS_V, default=0x00000000*/

10006

10007 /*

10008 The ECC source of failure (Cache ECC failure =

10009 0, TLC ECC failure = 1)

10010 */

10011 UINT32 ModelSpecifcInfo0 : 9;

10012

10013 /* Bits[31:23], Access Type=RWS_V, default=0x00000000*/

10014

10015 /* Available when Enhanced MCA is in use */

10016 UINT32 ModelSpecifcInfo1 : 32;

10017

10018 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

10019

10020 /* Available when Enhanced MCA is in use */

10021

10022 } Bits;

10023

10024 UINT32 Uint32;

10025 UINT64 Uint64;

10026

10027 } MSR_MC5_MISC_REGISTER;

10028

10029 /**

10030 Machine Check Architecture Control MSR.

10031 **/

10032 #define MSR_MC6_CTL 0x00000418

10033

10034 typedef union {

10035 ///

10036 /// Individual bit fields

10037 ///

10038 struct {

10039 UINT32 EnPcuHwError : 1;

10040

10041 /* Bits[0:0], Access Type=RW, default=0x00000001*/

10042

10043 /* Enable bit for MC signaling */

10044 UINT32 EnPcuUcError : 1;

10045

10046 /* Bits[1:1], Access Type=RW, default=0x00000001*/

10047

10048 /* Enable bit for MC signaling */

10049 UINT32 EnPcuFwError : 1;

10050

10051 /* Bits[2:2], Access Type=RW, default=0x00000001*/

10052

10053 /* Enable bit for MC signaling */

10054 UINT32 EnVcuHwError : 1;

10055

10056 /* Bits[3:3], Access Type=RW, default=0x00000001*/

10057

10058 /* Enable bit for MC signaling */

10059 UINT32 EnVcuUcError : 1;

10060

10061 /* Bits[4:4], Access Type=RW, default=0x00000001*/

10062

10063 /* Enable bit for MC signaling */

10064 UINT32 EnVcuFwError : 1;

10065

10066 /* Bits[5:5], Access Type=RW, default=0x00000001*/

10067

10068 /* Enable bit for MC signaling */

10069 UINT32 Rsvd6 : 26;

10070

10071 /* Bits[31:6], Access Type=RO, default=None*/

10072

10073 /* Reserved */

10074 UINT32 Rsvd32 : 32;

10075

10076 /* Bits[63:32], Access Type=RO, default=None*/

10077

10078 /* Reserved */

10079

10080 } Bits;

10081

10082 UINT32 Uint32;

10083 UINT64 Uint64;

10084

10085 } MSR_MC6_CTL_REGISTER;

10086

10087 /**

10088 Machine Check Architecture Status MSR.

10089 **/

10090 #define MSR_MC6_STATUS 0x00000419

10091

10092 typedef union {

10093 ///

10094 /// Individual bit fields

10095 ///

10096 struct {

10097 UINT32 Mccod : 16;

10098

10099 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

10100

10101 /* Machine Check Error Code. */

10102 UINT32 MsecUc : 4;

10103

10104 /* Bits[19:16], Access Type=RWS_V, default=0x00000000*/

10105

10106 /* Model specific error code bits 19:16 */

10107 UINT32 MsecHw : 4;

10108

10109 /* Bits[23:20], Access Type=RWS_V, default=0x00000000*/

10110

10111 /* Model specific error code bits 23:20. */

10112 UINT32 MsecFw : 8;

10113

10114 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

10115

10116 /* Model specific error code bits 31:24. */

10117 UINT32 EnhMcaAvail0 : 6;

10118

10119 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10120

10121 /* Available when Enhanced MCA is in use */

10122 UINT32 CorrErrCount : 15;

10123

10124 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

10125

10126 /* Correctable error count. */

10127 UINT32 Correrrorstatusind : 2;

10128

10129 /* Bits[54:53], Access Type=RWS_V, default=0x00000000*/

10130

10131 /*

10132 These bits are used to indicate when the number

10133 of corrected errors has exceeded the safe

10134 threshold to the point where an uncorrected

10135 error has become more likely to happen. Table 3

10136 shows the encoding of these bits.

10137 */

10138 UINT32 EnhMcaAvail1 : 2;

10139

10140 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

10141

10142 /* Available when Enhanced MCA is in use */

10143 UINT32 Pcc : 1;

10144

10145 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

10146

10147 /* PCC: Processor context corrupt */

10148 UINT32 Addrv : 1;

10149

10150 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

10151

10152 /*

10153 ADDRV: The address held in the MC6_ADDR_MSR is

10154 valid

10155 */

10156 UINT32 Miscv : 1;

10157

10158 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

10159

10160 /*

10161 MISCV: The value held in the MC6_MISC_MSR is

10162 valid

10163 */

10164 UINT32 En : 1;

10165

10166 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

10167

10168 /*

10169 Enable bit - Whether the logged error was

10170 enabled or not.

10171 */

10172 UINT32 Uc : 1;

10173

10174 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

10175

10176 /*

10177 Indicates (when set) that the processor did not

10178 correct the error condition. 0b Correctable

10179 Error 1b Uncorrectable Error

10180 */

10181 UINT32 Ovr : 1;

10182

10183 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

10184

10185 /*

10186 Another MCA error was detected when VALID was

10187 already set to 1b. In other words, a second MCA

10188 error was detected while an earlier error was

10189 already logged.

10190 */

10191 UINT32 Valid : 1;

10192

10193 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

10194

10195 /*

10196 Indicates that this register contains a valid

10197 MCA error that was detected.

10198 */

10199

10200 } Bits;

10201

10202 UINT32 Uint32;

10203 UINT64 Uint64;

10204

10205 } MSR_MC6_STATUS_REGISTER;

10206 /**

10207 PCU Machine Check Architecture Address MSR.

10208 **/

10209 #define MSR_MC6_ADDR 0x0000041A

10210

10211 /**

10212 PCU Machine Check Architecture Misc MSR.

10213 **/

10214 #define MSR_MC6_MISC 0x0000041B

10215

10216 typedef union {

10217 ///

10218 /// Individual bit fields

10219 ///

10220 struct {

10221 UINT32 ErrorAddress : 16;

10222

10223 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

10224

10225 /*

10226 This field contains the address of uncorrected

10227 error seen in the PCU/VCU. It is updated on an

10228 uncorrectable error. To maintain e-MCA support

10229 this register must be writable.

10230 */

10231 UINT32 CorrectedErrorCount : 8;

10232

10233 /* Bits[23:16], Access Type=RWS_V, default=0x00000000*/

10234

10235 /* Corrected Error Count */

10236 UINT32 EnhMcaAvail0 : 8;

10237

10238 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

10239

10240 /* Available when enhanced MCA is in use */

10241 UINT32 EnhMcaAvail1 : 32;

10242

10243 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

10244

10245 /* Available when enhanced MCA is in use */

10246

10247 } Bits;

10248

10249 UINT32 Uint32;

10250 UINT64 Uint64;

10251

10252 } MSR_MC6_MISC_REGISTER;

10253

10254 /**

10255 CBO and LLC MCA bank: Control register

10256 **/

10257 #define MSR_MC7_CTL 0x0000041C

10258

10259 typedef union {

10260 ///

10261 /// Individual bit fields

10262 ///

10263 struct {

10264 UINT32 LlcTagError : 1;

10265

10266 /* Bits[0:0], Access Type=RW, default=0x00000000*/

10267

10268 /* Enable bit for MC signaling */

10269 UINT32 LlcDataError : 1;

10270

10271 /* Bits[1:1], Access Type=RW, default=0x00000000*/

10272

10273 /* Enable bit for MC signaling */

10274 UINT32 SadErrWbToMmio : 1;

10275

10276 /* Bits[2:2], Access Type=RW, default=0x00000000*/

10277

10278 /* Enable bit for MC signaling */

10279 UINT32 SadErrIaAccessToGsm : 1;

10280

10281 /* Bits[3:3], Access Type=RW, default=0x00000000*/

10282

10283 /* Enable bit for MC signaling */

10284 UINT32 SadCorrupingErrOther : 1;

10285

10286 /* Bits[4:4], Access Type=RW, default=0x00000000*/

10287

10288 /* Enable bit for MC signaling */

10289 UINT32 SadNonCorrupingErrOther : 1;

10290

10291 /* Bits[5:5], Access Type=RW, default=0x00000000*/

10292

10293 /* Enable bit for MC signaling */

10294 UINT32 MultipleTagMatchErr : 1;

10295

10296 /* Bits[6:6], Access Type=RW, default=0x00000000*/

10297

10298 /* Enable bit for MC signaling */

10299 UINT32 IdiJitterError : 1;

10300

10301 /* Bits[7:7], Access Type=RW, default=0x00000000*/

10302

10303 /* Enable bit for MC signaling */

10304 UINT32 Rsvd8 : 24;

10305

10306 /* Bits[31:8], Access Type=RO, default=None*/

10307

10308 /* Reserved */

10309 UINT32 Rsvd32 : 32;

10310

10311 /* Bits[63:32], Access Type=RO, default=None*/

10312

10313 /* Reserved */

10314

10315 } Bits;

10316

10317 UINT32 Uint32;

10318 UINT64 Uint64;

10319

10320 } MSR_MC7_CTL_REGISTER;

10321

10322 /**

10323 LLC MCA bank: Status register

10324 **/

10325 #define MSR_MC7_STATUS 0x0000041D

10326

10327 typedef union {

10328 ///

10329 /// Individual bit fields

10330 ///

10331 struct {

10332 UINT32 McaErrorCode : 16;

10333

10334 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

10335

10336 /* MCA error code */

10337 UINT32 ModelSpecificErrorCode : 16;

10338

10339 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

10340

10341 /* Model specific error code */

10342 UINT32 EnhMcaAvail0 : 6;

10343

10344 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10345

10346 /* Available when Enhanced MCA is in use */

10347 UINT32 CorrErrCount : 15;

10348

10349 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

10350

10351 /* Correctable error count */

10352 UINT32 Correrrorstatusind : 2;

10353

10354 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

10355

10356 /*

10357 These bits are used to indicate when the number

10358 of corrected errors has exceeded the safe

10359 threshold to the point where an uncorrected

10360 error has become more likely to happen. Table 3

10361 shows the encoding of these bits.

10362 */

10363 UINT32 EnhMcaAvail1 : 2;

10364

10365 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

10366

10367 /* Available when Enhanced MCA is in use */

10368 UINT32 Pcc : 1;

10369

10370 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

10371

10372 /* PCC: Processor context corrupt */

10373 UINT32 Addrv : 1;

10374

10375 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

10376

10377 /*

10378 ADDRV: The address held in the MC6_ADDR_MSR is

10379 valid

10380 */

10381 UINT32 Miscv : 1;

10382

10383 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

10384

10385 /*

10386 MISCV: The value held in the MC6_MISC_MSR is

10387 valid

10388 */

10389 UINT32 En : 1;

10390

10391 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

10392

10393 /*

10394 EN: Error enabled flag Indicates (when set) that

10395 signaling of the machine check exception for

10396 this error was enabled by an associated flag bit

10397 of the Mci_CTL register.

10398 */

10399 UINT32 Uc : 1;

10400

10401 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

10402

10403 /*

10404 UC: Error uncorrected flag Indicates (when set)

10405 that the processor did not correct the error

10406 condition. When clear, this flag indicates that

10407 the processor was able to correct the error

10408 condition.

10409 */

10410 UINT32 Over : 1;

10411

10412 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

10413

10414 /* OVER: Machine check overflow */

10415 UINT32 Val : 1;

10416

10417 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

10418

10419 /*

10420 VAL: Valid flag Indicates (when set) that the

10421 information within the Mci_STATUS register is

10422 valid. When this flag is set, the processor

10423 follows the rules given for the OVER flag in the

10424 Mci_STATUS register when overwriting previously

10425 valid entries. The processor sets the VAL flag

10426 and software is responsible for clearing it.

10427 */

10428

10429 } Bits;

10430

10431 UINT32 Uint32;

10432 UINT64 Uint64;

10433

10434 } MSR_MC7_STATUS_REGISTER;

10435

10436 /**

10437 LLC MCA bank: Address register

10438 **/

10439 #define MSR_MC7_ADDR 0x0000041E

10440

10441 typedef union {

10442 ///

10443 /// Individual bit fields

10444 ///

10445 struct {

10446 UINT32 AddressOffset : 6;

10447

10448 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

10449

10450 /*

10451 Bits [5:0] of the Machine Check logged address.

10452 Enchanced MCA feature made this field writable

10453 */

10454 UINT32 Address0 : 26;

10455

10456 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

10457

10458 /* address of the logged error */

10459 UINT32 Address1 : 7;

10460

10461 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

10462

10463 /* address of the logged error */

10464 UINT32 EnhMcaAvail : 25;

10465

10466 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

10467

10468 /* Available when Enhanced MCA is in use */

10469

10470 } Bits;

10471

10472 UINT32 Uint32;

10473 UINT64 Uint64;

10474

10475 } MSR_MC7_ADDR_REGISTER;

10476

10477 /**

10478 LLC MCA bank: Misc register

10479 **/

10480 #define MSR_MC7_MISC 0x0000041F

10481

10482 typedef union {

10483 ///

10484 /// Individual bit fields

10485 ///

10486 struct {

10487 UINT32 LsbAddr : 6;

10488

10489 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

10490

10491 /*

10492 Points to where the supported LSB in MCi_Addr in

10493 SNB LLC cases it's always 6 (=000110)

10494 */

10495 UINT32 Addrmode : 3;

10496

10497 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

10498

10499 /*

10500 Address Mode = 010 since we always have only PA

10501 in the SNB LLC

10502 */

10503 UINT32 EnhMcaAvail0 : 5;

10504

10505 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

10506

10507 /* Available when Enhanced MCA is in use */

10508 UINT32 Way : 4;

10509

10510 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

10511

10512 /* The way associated with the logged error */

10513 UINT32 EnhMcaAvail1 : 6;

10514

10515 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

10516

10517 /* Available when Enhanced MCA is in use */

10518 UINT32 Threadid : 1;

10519

10520 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

10521

10522 /* Thread ID associated with the logged error */

10523 UINT32 Coreid : 4;

10524

10525 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

10526

10527 /* Core ID associated with the logged error */

10528 UINT32 Opcode0 : 3;

10529

10530 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

10531

10532 /* pipe command associated with the error */

10533 UINT32 Opcode1 : 6;

10534

10535 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10536

10537 /* pipe command associated with the error */

10538 UINT32 Torid : 6;

10539

10540 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

10541

10542 /* Entry in the TOR */

10543 UINT32 EnhMcaAvail2 : 20;

10544

10545 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

10546

10547 /* Available when Enhanced MCA is in use */

10548

10549 } Bits;

10550

10551 UINT32 Uint32;

10552 UINT64 Uint64;

10553

10554 } MSR_MC7_MISC_REGISTER;

10555

10556 /**

10557 CBO and LLC MCA bank: Control register

10558 **/

10559 #define MSR_MC8_CTL 0x00000420

10560

10561 typedef union {

10562 ///

10563 /// Individual bit fields

10564 ///

10565 struct {

10566 UINT32 LlcTagError : 1;

10567

10568 /* Bits[0:0], Access Type=RW, default=0x00000000*/

10569

10570 /* Enable bit for MC signaling */

10571 UINT32 LlcDataError : 1;

10572

10573 /* Bits[1:1], Access Type=RW, default=0x00000000*/

10574

10575 /* Enable bit for MC signaling */

10576 UINT32 SadErrWbToMmio : 1;

10577

10578 /* Bits[2:2], Access Type=RW, default=0x00000000*/

10579

10580 /* Enable bit for MC signaling */

10581 UINT32 SadErrIaAccessToGsm : 1;

10582

10583 /* Bits[3:3], Access Type=RW, default=0x00000000*/

10584

10585 /* Enable bit for MC signaling */

10586 UINT32 SadCorrupingErrOther : 1;

10587

10588 /* Bits[4:4], Access Type=RW, default=0x00000000*/

10589

10590 /* Enable bit for MC signaling */

10591 UINT32 SadNonCorrupingErrOther : 1;

10592

10593 /* Bits[5:5], Access Type=RW, default=0x00000000*/

10594

10595 /* Enable bit for MC signaling */

10596 UINT32 MultipleTagMatchErr : 1;

10597

10598 /* Bits[6:6], Access Type=RW, default=0x00000000*/

10599

10600 /* Enable bit for MC signaling */

10601 UINT32 IdiJitterError : 1;

10602

10603 /* Bits[7:7], Access Type=RW, default=0x00000000*/

10604

10605 /* Enable bit for MC signaling */

10606 UINT32 Rsvd8 : 24;

10607

10608 /* Bits[31:8], Access Type=RO, default=None*/

10609

10610 /* Reserved */

10611 UINT32 Rsvd32 : 32;

10612

10613 /* Bits[63:32], Access Type=RO, default=None*/

10614

10615 /* Reserved */

10616

10617 } Bits;

10618

10619 UINT32 Uint32;

10620 UINT64 Uint64;

10621

10622 } MSR_MC8_CTL_REGISTER;

10623

10624 /**

10625 LLC MCA bank: Status register

10626 **/

10627 #define MSR_MC8_STATUS 0x00000421

10628

10629 typedef union {

10630 ///

10631 /// Individual bit fields

10632 ///

10633 struct {

10634 UINT32 McaErrorCode : 16;

10635

10636 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

10637

10638 /* MCA error code */

10639 UINT32 ModelSpecificErrorCode : 16;

10640

10641 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

10642

10643 /* Model specific error code */

10644 UINT32 EnhMcaAvail0 : 6;

10645

10646 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10647

10648 /* Available when Enhanced MCA is in use */

10649 UINT32 CorrErrCount : 15;

10650

10651 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

10652

10653 /* Correctable error count */

10654 UINT32 Correrrorstatusind : 2;

10655

10656 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

10657

10658 /*

10659 These bits are used to indicate when the number

10660 of corrected errors has exceeded the safe

10661 threshold to the point where an uncorrected

10662 error has become more likely to happen. Table 3

10663 shows the encoding of these bits.

10664 */

10665 UINT32 EnhMcaAvail1 : 2;

10666

10667 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

10668

10669 /* Available when Enhanced MCA is in use */

10670 UINT32 Pcc : 1;

10671

10672 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

10673

10674 /* PCC: Processor context corrupt */

10675 UINT32 Addrv : 1;

10676

10677 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

10678

10679 /*

10680 ADDRV: The address held in the MC6_ADDR_MSR is

10681 valid

10682 */

10683 UINT32 Miscv : 1;

10684

10685 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

10686

10687 /*

10688 MISCV: The value held in the MC6_MISC_MSR is

10689 valid

10690 */

10691 UINT32 En : 1;

10692

10693 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

10694

10695 /*

10696 EN: Error enabled flag Indicates (when set) that

10697 signaling of the machine check exception for

10698 this error was enabled by an associated flag bit

10699 of the Mci_CTL register.

10700 */

10701 UINT32 Uc : 1;

10702

10703 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

10704

10705 /*

10706 UC: Error uncorrected flag Indicates (when set)

10707 that the processor did not correct the error

10708 condition. When clear, this flag indicates that

10709 the processor was able to correct the error

10710 condition.

10711 */

10712 UINT32 Over : 1;

10713

10714 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

10715

10716 /* OVER: Machine check overflow */

10717 UINT32 Val : 1;

10718

10719 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

10720

10721 /*

10722 VAL: Valid flag Indicates (when set) that the

10723 information within the Mci_STATUS register is

10724 valid. When this flag is set, the processor

10725 follows the rules given for the OVER flag in the

10726 Mci_STATUS register when overwriting previously

10727 valid entries. The processor sets the VAL flag

10728 and software is responsible for clearing it.

10729 */

10730

10731 } Bits;

10732

10733 UINT32 Uint32;

10734 UINT64 Uint64;

10735

10736 } MSR_MC8_STATUS_REGISTER;

10737

10738 /**

10739 LLC MCA bank: Address register

10740 **/

10741 #define MSR_MC8_ADDR 0x00000422

10742

10743 typedef union {

10744 ///

10745 /// Individual bit fields

10746 ///

10747 struct {

10748 UINT32 AddressOffset : 6;

10749

10750 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

10751

10752 /*

10753 Bits [5:0] of the Machine Check logged address.

10754 Enchanced MCA feature made this field writable

10755 */

10756 UINT32 Address0 : 26;

10757

10758 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

10759

10760 /* address of the logged error */

10761 UINT32 Address1 : 7;

10762

10763 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

10764

10765 /* address of the logged error */

10766 UINT32 EnhMcaAvail : 25;

10767

10768 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

10769

10770 /* Available when Enhanced MCA is in use */

10771

10772 } Bits;

10773

10774 UINT32 Uint32;

10775 UINT64 Uint64;

10776

10777 } MSR_MC8_ADDR_REGISTER;

10778

10779 /**

10780 LLC MCA bank: Misc register

10781 **/

10782 #define MSR_MC8_MISC 0x00000423

10783

10784 typedef union {

10785 ///

10786 /// Individual bit fields

10787 ///

10788 struct {

10789 UINT32 LsbAddr : 6;

10790

10791 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

10792

10793 /*

10794 Points to where the supported LSB in MCi_Addr in

10795 SNB LLC cases it's always 6 (=000110)

10796 */

10797 UINT32 Addrmode : 3;

10798

10799 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

10800

10801 /*

10802 Address Mode = 010 since we always have only PA

10803 in the SNB LLC

10804 */

10805 UINT32 EnhMcaAvail0 : 5;

10806

10807 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

10808

10809 /* Available when Enhanced MCA is in use */

10810 UINT32 Way : 4;

10811

10812 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

10813

10814 /* The way associated with the logged error */

10815 UINT32 EnhMcaAvail1 : 6;

10816

10817 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

10818

10819 /* Available when Enhanced MCA is in use */

10820 UINT32 Threadid : 1;

10821

10822 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

10823

10824 /* Thread ID associated with the logged error */

10825 UINT32 Coreid : 4;

10826

10827 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

10828

10829 /* Core ID associated with the logged error */

10830 UINT32 Opcode0 : 3;

10831

10832 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

10833

10834 /* pipe command associated with the error */

10835 UINT32 Opcode1 : 6;

10836

10837 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10838

10839 /* pipe command associated with the error */

10840 UINT32 Torid : 6;

10841

10842 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

10843

10844 /* Entry in the TOR */

10845 UINT32 EnhMcaAvail2 : 20;

10846

10847 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

10848

10849 /* Available when Enhanced MCA is in use */

10850

10851 } Bits;

10852

10853 UINT32 Uint32;

10854 UINT64 Uint64;

10855

10856 } MSR_MC8_MISC_REGISTER;

10857

10858 /**

10859 CBO and LLC MCA bank: Control register

10860 **/

10861 #define MSR_MC9_CTL 0x00000424

10862

10863 typedef union {

10864 ///

10865 /// Individual bit fields

10866 ///

10867 struct {

10868 UINT32 LlcTagError : 1;

10869

10870 /* Bits[0:0], Access Type=RW, default=0x00000000*/

10871

10872 /* Enable bit for MC signaling */

10873 UINT32 LlcDataError : 1;

10874

10875 /* Bits[1:1], Access Type=RW, default=0x00000000*/

10876

10877 /* Enable bit for MC signaling */

10878 UINT32 SadErrWbToMmio : 1;

10879

10880 /* Bits[2:2], Access Type=RW, default=0x00000000*/

10881

10882 /* Enable bit for MC signaling */

10883 UINT32 SadErrIaAccessToGsm : 1;

10884

10885 /* Bits[3:3], Access Type=RW, default=0x00000000*/

10886

10887 /* Enable bit for MC signaling */

10888 UINT32 SadCorrupingErrOther : 1;

10889

10890 /* Bits[4:4], Access Type=RW, default=0x00000000*/

10891

10892 /* Enable bit for MC signaling */

10893 UINT32 SadNonCorrupingErrOther : 1;

10894

10895 /* Bits[5:5], Access Type=RW, default=0x00000000*/

10896

10897 /* Enable bit for MC signaling */

10898 UINT32 MultipleTagMatchErr : 1;

10899

10900 /* Bits[6:6], Access Type=RW, default=0x00000000*/

10901

10902 /* Enable bit for MC signaling */

10903 UINT32 IdiJitterError : 1;

10904

10905 /* Bits[7:7], Access Type=RW, default=0x00000000*/

10906

10907 /* Enable bit for MC signaling */

10908 UINT32 Rsvd8 : 24;

10909

10910 /* Bits[31:8], Access Type=RO, default=None*/

10911

10912 /* Reserved */

10913 UINT32 Rsvd32 : 32;

10914

10915 /* Bits[63:32], Access Type=RO, default=None*/

10916

10917 /* Reserved */

10918

10919 } Bits;

10920

10921 UINT32 Uint32;

10922 UINT64 Uint64;

10923

10924 } MSR_MC9_CTL_REGISTER;

10925

10926 /**

10927 LLC MCA bank: Status register

10928 **/

10929 #define MSR_MC9_STATUS 0x00000425

10930

10931 typedef union {

10932 ///

10933 /// Individual bit fields

10934 ///

10935 struct {

10936 UINT32 McaErrorCode : 16;

10937

10938 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

10939

10940 /* MCA error code */

10941 UINT32 ModelSpecificErrorCode : 16;

10942

10943 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

10944

10945 /* Model specific error code */

10946 UINT32 EnhMcaAvail0 : 6;

10947

10948 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

10949

10950 /* Available when Enhanced MCA is in use */

10951 UINT32 CorrErrCount : 15;

10952

10953 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

10954

10955 /* Correctable error count */

10956 UINT32 Correrrorstatusind : 2;

10957

10958 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

10959

10960 /*

10961 These bits are used to indicate when the number

10962 of corrected errors has exceeded the safe

10963 threshold to the point where an uncorrected

10964 error has become more likely to happen. Table 3

10965 shows the encoding of these bits.

10966 */

10967 UINT32 EnhMcaAvail1 : 2;

10968

10969 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

10970

10971 /* Available when Enhanced MCA is in use */

10972 UINT32 Pcc : 1;

10973

10974 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

10975

10976 /* PCC: Processor context corrupt */

10977 UINT32 Addrv : 1;

10978

10979 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

10980

10981 /*

10982 ADDRV: The address held in the MC6_ADDR_MSR is

10983 valid

10984 */

10985 UINT32 Miscv : 1;

10986

10987 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

10988

10989 /*

10990 MISCV: The value held in the MC6_MISC_MSR is

10991 valid

10992 */

10993 UINT32 En : 1;

10994

10995 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

10996

10997 /*

10998 EN: Error enabled flag Indicates (when set) that

10999 signaling of the machine check exception for

11000 this error was enabled by an associated flag bit

11001 of the Mci_CTL register.

11002 */

11003 UINT32 Uc : 1;

11004

11005 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

11006

11007 /*

11008 UC: Error uncorrected flag Indicates (when set)

11009 that the processor did not correct the error

11010 condition. When clear, this flag indicates that

11011 the processor was able to correct the error

11012 condition.

11013 */

11014 UINT32 Over : 1;

11015

11016 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

11017

11018 /* OVER: Machine check overflow */

11019 UINT32 Val : 1;

11020

11021 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

11022

11023 /*

11024 VAL: Valid flag Indicates (when set) that the

11025 information within the Mci_STATUS register is

11026 valid. When this flag is set, the processor

11027 follows the rules given for the OVER flag in the

11028 Mci_STATUS register when overwriting previously

11029 valid entries. The processor sets the VAL flag

11030 and software is responsible for clearing it.

11031 */

11032

11033 } Bits;

11034

11035 UINT32 Uint32;

11036 UINT64 Uint64;

11037

11038 } MSR_MC9_STATUS_REGISTER;

11039

11040 /**

11041 LLC MCA bank: Address register

11042 **/

11043 #define MSR_MC9_ADDR 0x00000426

11044

11045 typedef union {

11046 ///

11047 /// Individual bit fields

11048 ///

11049 struct {

11050 UINT32 AddressOffset : 6;

11051

11052 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11053

11054 /*

11055 Bits [5:0] of the Machine Check logged address.

11056 Enchanced MCA feature made this field writable

11057 */

11058 UINT32 Address0 : 26;

11059

11060 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

11061

11062 /* address of the logged error */

11063 UINT32 Address1 : 7;

11064

11065 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

11066

11067 /* address of the logged error */

11068 UINT32 EnhMcaAvail : 25;

11069

11070 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

11071

11072 /* Available when Enhanced MCA is in use */

11073

11074 } Bits;

11075

11076 UINT32 Uint32;

11077 UINT64 Uint64;

11078

11079 } MSR_MC9_ADDR_REGISTER;

11080

11081 /**

11082 LLC MCA bank: Misc register

11083 **/

11084 #define MSR_MC9_MISC 0x00000427

11085

11086 typedef union {

11087 ///

11088 /// Individual bit fields

11089 ///

11090 struct {

11091 UINT32 LsbAddr : 6;

11092

11093 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11094

11095 /*

11096 Points to where the supported LSB in MCi_Addr in

11097 SNB LLC cases it's always 6 (=000110)

11098 */

11099 UINT32 Addrmode : 3;

11100

11101 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

11102

11103 /*

11104 Address Mode = 010 since we always have only PA

11105 in the SNB LLC

11106 */

11107 UINT32 EnhMcaAvail0 : 5;

11108

11109 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

11110

11111 /* Available when Enhanced MCA is in use */

11112 UINT32 Way : 4;

11113

11114 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

11115

11116 /* The way associated with the logged error */

11117 UINT32 EnhMcaAvail1 : 6;

11118

11119 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

11120

11121 /* Available when Enhanced MCA is in use */

11122 UINT32 Threadid : 1;

11123

11124 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

11125

11126 /* Thread ID associated with the logged error */

11127 UINT32 Coreid : 4;

11128

11129 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

11130

11131 /* Core ID associated with the logged error */

11132 UINT32 Opcode0 : 3;

11133

11134 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

11135

11136 /* pipe command associated with the error */

11137 UINT32 Opcode1 : 6;

11138

11139 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11140

11141 /* pipe command associated with the error */

11142 UINT32 Torid : 6;

11143

11144 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

11145

11146 /* Entry in the TOR */

11147 UINT32 EnhMcaAvail2 : 20;

11148

11149 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

11150

11151 /* Available when Enhanced MCA is in use */

11152

11153 } Bits;

11154

11155 UINT32 Uint32;

11156 UINT64 Uint64;

11157

11158 } MSR_MC9_MISC_REGISTER;

11159

11160 /**

11161 CBO and LLC MCA bank: Control register

11162 **/

11163 #define MSR_MC10_CTL 0x00000428

11164

11165 typedef union {

11166 ///

11167 /// Individual bit fields

11168 ///

11169 struct {

11170 UINT32 LlcTagError : 1;

11171

11172 /* Bits[0:0], Access Type=RW, default=0x00000000*/

11173

11174 /* Enable bit for MC signaling */

11175 UINT32 LlcDataError : 1;

11176

11177 /* Bits[1:1], Access Type=RW, default=0x00000000*/

11178

11179 /* Enable bit for MC signaling */

11180 UINT32 SadErrWbToMmio : 1;

11181

11182 /* Bits[2:2], Access Type=RW, default=0x00000000*/

11183

11184 /* Enable bit for MC signaling */

11185 UINT32 SadErrIaAccessToGsm : 1;

11186

11187 /* Bits[3:3], Access Type=RW, default=0x00000000*/

11188

11189 /* Enable bit for MC signaling */

11190 UINT32 SadCorrupingErrOther : 1;

11191

11192 /* Bits[4:4], Access Type=RW, default=0x00000000*/

11193

11194 /* Enable bit for MC signaling */

11195 UINT32 SadNonCorrupingErrOther : 1;

11196

11197 /* Bits[5:5], Access Type=RW, default=0x00000000*/

11198

11199 /* Enable bit for MC signaling */

11200 UINT32 MultipleTagMatchErr : 1;

11201

11202 /* Bits[6:6], Access Type=RW, default=0x00000000*/

11203

11204 /* Enable bit for MC signaling */

11205 UINT32 IdiJitterError : 1;

11206

11207 /* Bits[7:7], Access Type=RW, default=0x00000000*/

11208

11209 /* Enable bit for MC signaling */

11210 UINT32 Rsvd8 : 24;

11211

11212 /* Bits[31:8], Access Type=RO, default=None*/

11213

11214 /* Reserved */

11215 UINT32 Rsvd32 : 32;

11216

11217 /* Bits[63:32], Access Type=RO, default=None*/

11218

11219 /* Reserved */

11220

11221 } Bits;

11222

11223 UINT32 Uint32;

11224 UINT64 Uint64;

11225

11226 } MSR_MC10_CTL_REGISTER;

11227

11228 /**

11229 LLC MCA bank: Status register

11230 **/

11231 #define MSR_MC10_STATUS 0x00000429

11232

11233 typedef union {

11234 ///

11235 /// Individual bit fields

11236 ///

11237 struct {

11238 UINT32 McaErrorCode : 16;

11239

11240 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

11241

11242 /* MCA error code */

11243 UINT32 ModelSpecificErrorCode : 16;

11244

11245 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

11246

11247 /* Model specific error code */

11248 UINT32 EnhMcaAvail0 : 6;

11249

11250 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11251

11252 /* Available when Enhanced MCA is in use */

11253 UINT32 CorrErrCount : 15;

11254

11255 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

11256

11257 /* Correctable error count */

11258 UINT32 Correrrorstatusind : 2;

11259

11260 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

11261

11262 /*

11263 These bits are used to indicate when the number

11264 of corrected errors has exceeded the safe

11265 threshold to the point where an uncorrected

11266 error has become more likely to happen. Table 3

11267 shows the encoding of these bits.

11268 */

11269 UINT32 EnhMcaAvail1 : 2;

11270

11271 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

11272

11273 /* Available when Enhanced MCA is in use */

11274 UINT32 Pcc : 1;

11275

11276 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

11277

11278 /* PCC: Processor context corrupt */

11279 UINT32 Addrv : 1;

11280

11281 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

11282

11283 /*

11284 ADDRV: The address held in the MC6_ADDR_MSR is

11285 valid

11286 */

11287 UINT32 Miscv : 1;

11288

11289 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

11290

11291 /*

11292 MISCV: The value held in the MC6_MISC_MSR is

11293 valid

11294 */

11295 UINT32 En : 1;

11296

11297 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

11298

11299 /*

11300 EN: Error enabled flag Indicates (when set) that

11301 signaling of the machine check exception for

11302 this error was enabled by an associated flag bit

11303 of the Mci_CTL register.

11304 */

11305 UINT32 Uc : 1;

11306

11307 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

11308

11309 /*

11310 UC: Error uncorrected flag Indicates (when set)

11311 that the processor did not correct the error

11312 condition. When clear, this flag indicates that

11313 the processor was able to correct the error

11314 condition.

11315 */

11316 UINT32 Over : 1;

11317

11318 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

11319

11320 /* OVER: Machine check overflow */

11321 UINT32 Val : 1;

11322

11323 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

11324

11325 /*

11326 VAL: Valid flag Indicates (when set) that the

11327 information within the Mci_STATUS register is

11328 valid. When this flag is set, the processor

11329 follows the rules given for the OVER flag in the

11330 Mci_STATUS register when overwriting previously

11331 valid entries. The processor sets the VAL flag

11332 and software is responsible for clearing it.

11333 */

11334

11335 } Bits;

11336

11337 UINT32 Uint32;

11338 UINT64 Uint64;

11339

11340 } MSR_MC10_STATUS_REGISTER;

11341

11342 /**

11343 LLC MCA bank: Address register

11344 **/

11345 #define MSR_MC10_ADDR 0x0000042A

11346

11347 typedef union {

11348 ///

11349 /// Individual bit fields

11350 ///

11351 struct {

11352 UINT32 AddressOffset : 6;

11353

11354 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11355

11356 /*

11357 Bits [5:0] of the Machine Check logged address.

11358 Enchanced MCA feature made this field writable

11359 */

11360 UINT32 Address0 : 26;

11361

11362 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

11363

11364 /* address of the logged error */

11365 UINT32 Address1 : 7;

11366

11367 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

11368

11369 /* address of the logged error */

11370 UINT32 EnhMcaAvail : 25;

11371

11372 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

11373

11374 /* Available when Enhanced MCA is in use */

11375

11376 } Bits;

11377

11378 UINT32 Uint32;

11379 UINT64 Uint64;

11380

11381 } MSR_MC10_ADDR_REGISTER;

11382

11383 /**

11384 LLC MCA bank: Misc register

11385 **/

11386 #define MSR_MC10_MISC 0x0000042B

11387

11388 typedef union {

11389 ///

11390 /// Individual bit fields

11391 ///

11392 struct {

11393 UINT32 LsbAddr : 6;

11394

11395 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11396

11397 /*

11398 Points to where the supported LSB in MCi_Addr in

11399 SNB LLC cases it's always 6 (=000110)

11400 */

11401 UINT32 Addrmode : 3;

11402

11403 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

11404

11405 /*

11406 Address Mode = 010 since we always have only PA

11407 in the SNB LLC

11408 */

11409 UINT32 EnhMcaAvail0 : 5;

11410

11411 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

11412

11413 /* Available when Enhanced MCA is in use */

11414 UINT32 Way : 4;

11415

11416 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

11417

11418 /* The way associated with the logged error */

11419 UINT32 EnhMcaAvail1 : 6;

11420

11421 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

11422

11423 /* Available when Enhanced MCA is in use */

11424 UINT32 Threadid : 1;

11425

11426 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

11427

11428 /* Thread ID associated with the logged error */

11429 UINT32 Coreid : 4;

11430

11431 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

11432

11433 /* Core ID associated with the logged error */

11434 UINT32 Opcode0 : 3;

11435

11436 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

11437

11438 /* pipe command associated with the error */

11439 UINT32 Opcode1 : 6;

11440

11441 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11442

11443 /* pipe command associated with the error */

11444 UINT32 Torid : 6;

11445

11446 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

11447

11448 /* Entry in the TOR */

11449 UINT32 EnhMcaAvail2 : 20;

11450

11451 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

11452

11453 /* Available when Enhanced MCA is in use */

11454

11455 } Bits;

11456

11457 UINT32 Uint32;

11458 UINT64 Uint64;

11459

11460 } MSR_MC10_MISC_REGISTER;

11461

11462 /**

11463 CBO and LLC MCA bank: Control register

11464 **/

11465 #define MSR_MC11_CTL 0x0000042C

11466

11467 typedef union {

11468 ///

11469 /// Individual bit fields

11470 ///

11471 struct {

11472 UINT32 LlcTagError : 1;

11473

11474 /* Bits[0:0], Access Type=RW, default=0x00000000*/

11475

11476 /* Enable bit for MC signaling */

11477 UINT32 LlcDataError : 1;

11478

11479 /* Bits[1:1], Access Type=RW, default=0x00000000*/

11480

11481 /* Enable bit for MC signaling */

11482 UINT32 SadErrWbToMmio : 1;

11483

11484 /* Bits[2:2], Access Type=RW, default=0x00000000*/

11485

11486 /* Enable bit for MC signaling */

11487 UINT32 SadErrIaAccessToGsm : 1;

11488

11489 /* Bits[3:3], Access Type=RW, default=0x00000000*/

11490

11491 /* Enable bit for MC signaling */

11492 UINT32 SadCorrupingErrOther : 1;

11493

11494 /* Bits[4:4], Access Type=RW, default=0x00000000*/

11495

11496 /* Enable bit for MC signaling */

11497 UINT32 SadNonCorrupingErrOther : 1;

11498

11499 /* Bits[5:5], Access Type=RW, default=0x00000000*/

11500

11501 /* Enable bit for MC signaling */

11502 UINT32 MultipleTagMatchErr : 1;

11503

11504 /* Bits[6:6], Access Type=RW, default=0x00000000*/

11505

11506 /* Enable bit for MC signaling */

11507 UINT32 IdiJitterError : 1;

11508

11509 /* Bits[7:7], Access Type=RW, default=0x00000000*/

11510

11511 /* Enable bit for MC signaling */

11512 UINT32 Rsvd8 : 24;

11513

11514 /* Bits[31:8], Access Type=RO, default=None*/

11515

11516 /* Reserved */

11517 UINT32 Rsvd32 : 32;

11518

11519 /* Bits[63:32], Access Type=RO, default=None*/

11520

11521 /* Reserved */

11522

11523 } Bits;

11524

11525 UINT32 Uint32;

11526 UINT64 Uint64;

11527

11528 } MSR_MC11_CTL_REGISTER;

11529

11530 /**

11531 LLC MCA bank: Status register

11532 **/

11533 #define MSR_MC11_STATUS 0x0000042D

11534

11535 typedef union {

11536 ///

11537 /// Individual bit fields

11538 ///

11539 struct {

11540 UINT32 McaErrorCode : 16;

11541

11542 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

11543

11544 /* MCA error code */

11545 UINT32 ModelSpecificErrorCode : 16;

11546

11547 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

11548

11549 /* Model specific error code */

11550 UINT32 EnhMcaAvail0 : 6;

11551

11552 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11553

11554 /* Available when Enhanced MCA is in use */

11555 UINT32 CorrErrCount : 15;

11556

11557 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

11558

11559 /* Correctable error count */

11560 UINT32 Correrrorstatusind : 2;

11561

11562 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

11563

11564 /*

11565 These bits are used to indicate when the number

11566 of corrected errors has exceeded the safe

11567 threshold to the point where an uncorrected

11568 error has become more likely to happen. Table 3

11569 shows the encoding of these bits.

11570 */

11571 UINT32 EnhMcaAvail1 : 2;

11572

11573 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

11574

11575 /* Available when Enhanced MCA is in use */

11576 UINT32 Pcc : 1;

11577

11578 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

11579

11580 /* PCC: Processor context corrupt */

11581 UINT32 Addrv : 1;

11582

11583 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

11584

11585 /*

11586 ADDRV: The address held in the MC6_ADDR_MSR is

11587 valid

11588 */

11589 UINT32 Miscv : 1;

11590

11591 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

11592

11593 /*

11594 MISCV: The value held in the MC6_MISC_MSR is

11595 valid

11596 */

11597 UINT32 En : 1;

11598

11599 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

11600

11601 /*

11602 EN: Error enabled flag Indicates (when set) that

11603 signaling of the machine check exception for

11604 this error was enabled by an associated flag bit

11605 of the Mci_CTL register.

11606 */

11607 UINT32 Uc : 1;

11608

11609 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

11610

11611 /*

11612 UC: Error uncorrected flag Indicates (when set)

11613 that the processor did not correct the error

11614 condition. When clear, this flag indicates that

11615 the processor was able to correct the error

11616 condition.

11617 */

11618 UINT32 Over : 1;

11619

11620 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

11621

11622 /* OVER: Machine check overflow */

11623 UINT32 Val : 1;

11624

11625 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

11626

11627 /*

11628 VAL: Valid flag Indicates (when set) that the

11629 information within the Mci_STATUS register is

11630 valid. When this flag is set, the processor

11631 follows the rules given for the OVER flag in the

11632 Mci_STATUS register when overwriting previously

11633 valid entries. The processor sets the VAL flag

11634 and software is responsible for clearing it.

11635 */

11636

11637 } Bits;

11638

11639 UINT32 Uint32;

11640 UINT64 Uint64;

11641

11642 } MSR_MC11_STATUS_REGISTER;

11643

11644 /**

11645 LLC MCA bank: Address register

11646 **/

11647 #define MSR_MC11_ADDR 0x0000042E

11648

11649 typedef union {

11650 ///

11651 /// Individual bit fields

11652 ///

11653 struct {

11654 UINT32 AddressOffset : 6;

11655

11656 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11657

11658 /*

11659 Bits [5:0] of the Machine Check logged address.

11660 Enchanced MCA feature made this field writable

11661 */

11662 UINT32 Address0 : 26;

11663

11664 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

11665

11666 /* address of the logged error */

11667 UINT32 Address1 : 7;

11668

11669 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

11670

11671 /* address of the logged error */

11672 UINT32 EnhMcaAvail : 25;

11673

11674 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

11675

11676 /* Available when Enhanced MCA is in use */

11677

11678 } Bits;

11679

11680 UINT32 Uint32;

11681 UINT64 Uint64;

11682

11683 } MSR_MC11_ADDR_REGISTER;

11684

11685 /**

11686 LLC MCA bank: Misc register

11687 **/

11688 #define MSR_MC11_MISC 0x0000042F

11689

11690 typedef union {

11691 ///

11692 /// Individual bit fields

11693 ///

11694 struct {

11695 UINT32 LsbAddr : 6;

11696

11697 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11698

11699 /*

11700 Points to where the supported LSB in MCi_Addr in

11701 SNB LLC cases it's always 6 (=000110)

11702 */

11703 UINT32 Addrmode : 3;

11704

11705 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

11706

11707 /*

11708 Address Mode = 010 since we always have only PA

11709 in the SNB LLC

11710 */

11711 UINT32 EnhMcaAvail0 : 5;

11712

11713 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

11714

11715 /* Available when Enhanced MCA is in use */

11716 UINT32 Way : 4;

11717

11718 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

11719

11720 /* The way associated with the logged error */

11721 UINT32 EnhMcaAvail1 : 6;

11722

11723 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

11724

11725 /* Available when Enhanced MCA is in use */

11726 UINT32 Threadid : 1;

11727

11728 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

11729

11730 /* Thread ID associated with the logged error */

11731 UINT32 Coreid : 4;

11732

11733 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

11734

11735 /* Core ID associated with the logged error */

11736 UINT32 Opcode0 : 3;

11737

11738 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

11739

11740 /* pipe command associated with the error */

11741 UINT32 Opcode1 : 6;

11742

11743 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11744

11745 /* pipe command associated with the error */

11746 UINT32 Torid : 6;

11747

11748 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

11749

11750 /* Entry in the TOR */

11751 UINT32 EnhMcaAvail2 : 20;

11752

11753 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

11754

11755 /* Available when Enhanced MCA is in use */

11756

11757 } Bits;

11758

11759 UINT32 Uint32;

11760 UINT64 Uint64;

11761

11762 } MSR_MC11_MISC_REGISTER;

11763

11764 /**

11765 CBO and LLC MCA bank: Control register

11766 **/

11767 #define MSR_MC12_CTL 0x00000430

11768

11769 typedef union {

11770 ///

11771 /// Individual bit fields

11772 ///

11773 struct {

11774 UINT32 LlcTagError : 1;

11775

11776 /* Bits[0:0], Access Type=RW, default=0x00000000*/

11777

11778 /* Enable bit for MC signaling */

11779 UINT32 LlcDataError : 1;

11780

11781 /* Bits[1:1], Access Type=RW, default=0x00000000*/

11782

11783 /* Enable bit for MC signaling */

11784 UINT32 SadErrWbToMmio : 1;

11785

11786 /* Bits[2:2], Access Type=RW, default=0x00000000*/

11787

11788 /* Enable bit for MC signaling */

11789 UINT32 SadErrIaAccessToGsm : 1;

11790

11791 /* Bits[3:3], Access Type=RW, default=0x00000000*/

11792

11793 /* Enable bit for MC signaling */

11794 UINT32 SadCorrupingErrOther : 1;

11795

11796 /* Bits[4:4], Access Type=RW, default=0x00000000*/

11797

11798 /* Enable bit for MC signaling */

11799 UINT32 SadNonCorrupingErrOther : 1;

11800

11801 /* Bits[5:5], Access Type=RW, default=0x00000000*/

11802

11803 /* Enable bit for MC signaling */

11804 UINT32 MultipleTagMatchErr : 1;

11805

11806 /* Bits[6:6], Access Type=RW, default=0x00000000*/

11807

11808 /* Enable bit for MC signaling */

11809 UINT32 IdiJitterError : 1;

11810

11811 /* Bits[7:7], Access Type=RW, default=0x00000000*/

11812

11813 /* Enable bit for MC signaling */

11814 UINT32 Rsvd8 : 24;

11815

11816 /* Bits[31:8], Access Type=RO, default=None*/

11817

11818 /* Reserved */

11819 UINT32 Rsvd32 : 32;

11820

11821 /* Bits[63:32], Access Type=RO, default=None*/

11822

11823 /* Reserved */

11824

11825 } Bits;

11826

11827 UINT32 Uint32;

11828 UINT64 Uint64;

11829

11830 } MSR_MC12_CTL_REGISTER;

11831

11832 /**

11833 LLC MCA bank: Status register

11834 **/

11835 #define MSR_MC12_STATUS 0x00000431

11836

11837 typedef union {

11838 ///

11839 /// Individual bit fields

11840 ///

11841 struct {

11842 UINT32 McaErrorCode : 16;

11843

11844 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

11845

11846 /* MCA error code */

11847 UINT32 ModelSpecificErrorCode : 16;

11848

11849 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

11850

11851 /* Model specific error code */

11852 UINT32 EnhMcaAvail0 : 6;

11853

11854 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

11855

11856 /* Available when Enhanced MCA is in use */

11857 UINT32 CorrErrCount : 15;

11858

11859 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

11860

11861 /* Correctable error count */

11862 UINT32 Correrrorstatusind : 2;

11863

11864 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

11865

11866 /*

11867 These bits are used to indicate when the number

11868 of corrected errors has exceeded the safe

11869 threshold to the point where an uncorrected

11870 error has become more likely to happen. Table 3

11871 shows the encoding of these bits.

11872 */

11873 UINT32 EnhMcaAvail1 : 2;

11874

11875 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

11876

11877 /* Available when Enhanced MCA is in use */

11878 UINT32 Pcc : 1;

11879

11880 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

11881

11882 /* PCC: Processor context corrupt */

11883 UINT32 Addrv : 1;

11884

11885 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

11886

11887 /*

11888 ADDRV: The address held in the MC6_ADDR_MSR is

11889 valid

11890 */

11891 UINT32 Miscv : 1;

11892

11893 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

11894

11895 /*

11896 MISCV: The value held in the MC6_MISC_MSR is

11897 valid

11898 */

11899 UINT32 En : 1;

11900

11901 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

11902

11903 /*

11904 EN: Error enabled flag Indicates (when set) that

11905 signaling of the machine check exception for

11906 this error was enabled by an associated flag bit

11907 of the Mci_CTL register.

11908 */

11909 UINT32 Uc : 1;

11910

11911 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

11912

11913 /*

11914 UC: Error uncorrected flag Indicates (when set)

11915 that the processor did not correct the error

11916 condition. When clear, this flag indicates that

11917 the processor was able to correct the error

11918 condition.

11919 */

11920 UINT32 Over : 1;

11921

11922 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

11923

11924 /* OVER: Machine check overflow */

11925 UINT32 Val : 1;

11926

11927 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

11928

11929 /*

11930 VAL: Valid flag Indicates (when set) that the

11931 information within the Mci_STATUS register is

11932 valid. When this flag is set, the processor

11933 follows the rules given for the OVER flag in the

11934 Mci_STATUS register when overwriting previously

11935 valid entries. The processor sets the VAL flag

11936 and software is responsible for clearing it.

11937 */

11938

11939 } Bits;

11940

11941 UINT32 Uint32;

11942 UINT64 Uint64;

11943

11944 } MSR_MC12_STATUS_REGISTER;

11945

11946 /**

11947 LLC MCA bank: Address register

11948 **/

11949 #define MSR_MC12_ADDR 0x00000432

11950

11951 typedef union {

11952 ///

11953 /// Individual bit fields

11954 ///

11955 struct {

11956 UINT32 AddressOffset : 6;

11957

11958 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

11959

11960 /*

11961 Bits [5:0] of the Machine Check logged address.

11962 Enchanced MCA feature made this field writable

11963 */

11964 UINT32 Address0 : 26;

11965

11966 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

11967

11968 /* address of the logged error */

11969 UINT32 Address1 : 7;

11970

11971 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

11972

11973 /* address of the logged error */

11974 UINT32 EnhMcaAvail : 25;

11975

11976 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

11977

11978 /* Available when Enhanced MCA is in use */

11979

11980 } Bits;

11981

11982 UINT32 Uint32;

11983 UINT64 Uint64;

11984

11985 } MSR_MC12_ADDR_REGISTER;

11986

11987 /**

11988 LLC MCA bank: Misc register

11989 **/

11990 #define MSR_MC12_MISC 0x00000433

11991

11992 typedef union {

11993 ///

11994 /// Individual bit fields

11995 ///

11996 struct {

11997 UINT32 LsbAddr : 6;

11998

11999 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12000

12001 /*

12002 Points to where the supported LSB in MCi_Addr in

12003 SNB LLC cases it's always 6 (=000110)

12004 */

12005 UINT32 Addrmode : 3;

12006

12007 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

12008

12009 /*

12010 Address Mode = 010 since we always have only PA

12011 in the SNB LLC

12012 */

12013 UINT32 EnhMcaAvail0 : 5;

12014

12015 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

12016

12017 /* Available when Enhanced MCA is in use */

12018 UINT32 Way : 4;

12019

12020 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

12021

12022 /* The way associated with the logged error */

12023 UINT32 EnhMcaAvail1 : 6;

12024

12025 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

12026

12027 /* Available when Enhanced MCA is in use */

12028 UINT32 Threadid : 1;

12029

12030 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

12031

12032 /* Thread ID associated with the logged error */

12033 UINT32 Coreid : 4;

12034

12035 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

12036

12037 /* Core ID associated with the logged error */

12038 UINT32 Opcode0 : 3;

12039

12040 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

12041

12042 /* pipe command associated with the error */

12043 UINT32 Opcode1 : 6;

12044

12045 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12046

12047 /* pipe command associated with the error */

12048 UINT32 Torid : 6;

12049

12050 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

12051

12052 /* Entry in the TOR */

12053 UINT32 EnhMcaAvail2 : 20;

12054

12055 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

12056

12057 /* Available when Enhanced MCA is in use */

12058

12059 } Bits;

12060

12061 UINT32 Uint32;

12062 UINT64 Uint64;

12063

12064 } MSR_MC12_MISC_REGISTER;

12065

12066 /**

12067 CBO and LLC MCA bank: Control register

12068 **/

12069 #define MSR_MC13_CTL 0x00000434

12070

12071 typedef union {

12072 ///

12073 /// Individual bit fields

12074 ///

12075 struct {

12076 UINT32 LlcTagError : 1;

12077

12078 /* Bits[0:0], Access Type=RW, default=0x00000000*/

12079

12080 /* Enable bit for MC signaling */

12081 UINT32 LlcDataError : 1;

12082

12083 /* Bits[1:1], Access Type=RW, default=0x00000000*/

12084

12085 /* Enable bit for MC signaling */

12086 UINT32 SadErrWbToMmio : 1;

12087

12088 /* Bits[2:2], Access Type=RW, default=0x00000000*/

12089

12090 /* Enable bit for MC signaling */

12091 UINT32 SadErrIaAccessToGsm : 1;

12092

12093 /* Bits[3:3], Access Type=RW, default=0x00000000*/

12094

12095 /* Enable bit for MC signaling */

12096 UINT32 SadCorrupingErrOther : 1;

12097

12098 /* Bits[4:4], Access Type=RW, default=0x00000000*/

12099

12100 /* Enable bit for MC signaling */

12101 UINT32 SadNonCorrupingErrOther : 1;

12102

12103 /* Bits[5:5], Access Type=RW, default=0x00000000*/

12104

12105 /* Enable bit for MC signaling */

12106 UINT32 MultipleTagMatchErr : 1;

12107

12108 /* Bits[6:6], Access Type=RW, default=0x00000000*/

12109

12110 /* Enable bit for MC signaling */

12111 UINT32 IdiJitterError : 1;

12112

12113 /* Bits[7:7], Access Type=RW, default=0x00000000*/

12114

12115 /* Enable bit for MC signaling */

12116 UINT32 Rsvd8 : 24;

12117

12118 /* Bits[31:8], Access Type=RO, default=None*/

12119

12120 /* Reserved */

12121 UINT32 Rsvd32 : 32;

12122

12123 /* Bits[63:32], Access Type=RO, default=None*/

12124

12125 /* Reserved */

12126

12127 } Bits;

12128

12129 UINT32 Uint32;

12130 UINT64 Uint64;

12131

12132 } MSR_MC13_CTL_REGISTER;

12133

12134 /**

12135 LLC MCA bank: Status register

12136 **/

12137 #define MSR_MC13_STATUS 0x00000435

12138

12139 typedef union {

12140 ///

12141 /// Individual bit fields

12142 ///

12143 struct {

12144 UINT32 McaErrorCode : 16;

12145

12146 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

12147

12148 /* MCA error code */

12149 UINT32 ModelSpecificErrorCode : 16;

12150

12151 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

12152

12153 /* Model specific error code */

12154 UINT32 EnhMcaAvail0 : 6;

12155

12156 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12157

12158 /* Available when Enhanced MCA is in use */

12159 UINT32 CorrErrCount : 15;

12160

12161 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

12162

12163 /* Correctable error count */

12164 UINT32 Correrrorstatusind : 2;

12165

12166 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

12167

12168 /*

12169 These bits are used to indicate when the number

12170 of corrected errors has exceeded the safe

12171 threshold to the point where an uncorrected

12172 error has become more likely to happen. Table 3

12173 shows the encoding of these bits.

12174 */

12175 UINT32 EnhMcaAvail1 : 2;

12176

12177 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

12178

12179 /* Available when Enhanced MCA is in use */

12180 UINT32 Pcc : 1;

12181

12182 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

12183

12184 /* PCC: Processor context corrupt */

12185 UINT32 Addrv : 1;

12186

12187 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

12188

12189 /*

12190 ADDRV: The address held in the MC6_ADDR_MSR is

12191 valid

12192 */

12193 UINT32 Miscv : 1;

12194

12195 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

12196

12197 /*

12198 MISCV: The value held in the MC6_MISC_MSR is

12199 valid

12200 */

12201 UINT32 En : 1;

12202

12203 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

12204

12205 /*

12206 EN: Error enabled flag Indicates (when set) that

12207 signaling of the machine check exception for

12208 this error was enabled by an associated flag bit

12209 of the Mci_CTL register.

12210 */

12211 UINT32 Uc : 1;

12212

12213 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

12214

12215 /*

12216 UC: Error uncorrected flag Indicates (when set)

12217 that the processor did not correct the error

12218 condition. When clear, this flag indicates that

12219 the processor was able to correct the error

12220 condition.

12221 */

12222 UINT32 Over : 1;

12223

12224 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

12225

12226 /* OVER: Machine check overflow */

12227 UINT32 Val : 1;

12228

12229 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

12230

12231 /*

12232 VAL: Valid flag Indicates (when set) that the

12233 information within the Mci_STATUS register is

12234 valid. When this flag is set, the processor

12235 follows the rules given for the OVER flag in the

12236 Mci_STATUS register when overwriting previously

12237 valid entries. The processor sets the VAL flag

12238 and software is responsible for clearing it.

12239 */

12240

12241 } Bits;

12242

12243 UINT32 Uint32;

12244 UINT64 Uint64;

12245

12246 } MSR_MC13_STATUS_REGISTER;

12247

12248 /**

12249 LLC MCA bank: Address register

12250 **/

12251 #define MSR_MC13_ADDR 0x00000436

12252

12253 typedef union {

12254 ///

12255 /// Individual bit fields

12256 ///

12257 struct {

12258 UINT32 AddressOffset : 6;

12259

12260 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12261

12262 /*

12263 Bits [5:0] of the Machine Check logged address.

12264 Enchanced MCA feature made this field writable

12265 */

12266 UINT32 Address0 : 26;

12267

12268 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

12269

12270 /* address of the logged error */

12271 UINT32 Address1 : 7;

12272

12273 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

12274

12275 /* address of the logged error */

12276 UINT32 EnhMcaAvail : 25;

12277

12278 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

12279

12280 /* Available when Enhanced MCA is in use */

12281

12282 } Bits;

12283

12284 UINT32 Uint32;

12285 UINT64 Uint64;

12286

12287 } MSR_MC13_ADDR_REGISTER;

12288

12289 /**

12290 LLC MCA bank: Misc register

12291 **/

12292 #define MSR_MC13_MISC 0x00000437

12293

12294 typedef union {

12295 ///

12296 /// Individual bit fields

12297 ///

12298 struct {

12299 UINT32 LsbAddr : 6;

12300

12301 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12302

12303 /*

12304 Points to where the supported LSB in MCi_Addr in

12305 SNB LLC cases it's always 6 (=000110)

12306 */

12307 UINT32 Addrmode : 3;

12308

12309 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

12310

12311 /*

12312 Address Mode = 010 since we always have only PA

12313 in the SNB LLC

12314 */

12315 UINT32 EnhMcaAvail0 : 5;

12316

12317 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

12318

12319 /* Available when Enhanced MCA is in use */

12320 UINT32 Way : 4;

12321

12322 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

12323

12324 /* The way associated with the logged error */

12325 UINT32 EnhMcaAvail1 : 6;

12326

12327 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

12328

12329 /* Available when Enhanced MCA is in use */

12330 UINT32 Threadid : 1;

12331

12332 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

12333

12334 /* Thread ID associated with the logged error */

12335 UINT32 Coreid : 4;

12336

12337 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

12338

12339 /* Core ID associated with the logged error */

12340 UINT32 Opcode0 : 3;

12341

12342 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

12343

12344 /* pipe command associated with the error */

12345 UINT32 Opcode1 : 6;

12346

12347 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12348

12349 /* pipe command associated with the error */

12350 UINT32 Torid : 6;

12351

12352 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

12353

12354 /* Entry in the TOR */

12355 UINT32 EnhMcaAvail2 : 20;

12356

12357 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

12358

12359 /* Available when Enhanced MCA is in use */

12360

12361 } Bits;

12362

12363 UINT32 Uint32;

12364 UINT64 Uint64;

12365

12366 } MSR_MC13_MISC_REGISTER;

12367

12368 /**

12369 CBO and LLC MCA bank: Control register

12370 **/

12371 #define MSR_MC14_CTL 0x00000438

12372

12373 typedef union {

12374 ///

12375 /// Individual bit fields

12376 ///

12377 struct {

12378 UINT32 LlcTagError : 1;

12379

12380 /* Bits[0:0], Access Type=RW, default=0x00000000*/

12381

12382 /* Enable bit for MC signaling */

12383 UINT32 LlcDataError : 1;

12384

12385 /* Bits[1:1], Access Type=RW, default=0x00000000*/

12386

12387 /* Enable bit for MC signaling */

12388 UINT32 SadErrWbToMmio : 1;

12389

12390 /* Bits[2:2], Access Type=RW, default=0x00000000*/

12391

12392 /* Enable bit for MC signaling */

12393 UINT32 SadErrIaAccessToGsm : 1;

12394

12395 /* Bits[3:3], Access Type=RW, default=0x00000000*/

12396

12397 /* Enable bit for MC signaling */

12398 UINT32 SadCorrupingErrOther : 1;

12399

12400 /* Bits[4:4], Access Type=RW, default=0x00000000*/

12401

12402 /* Enable bit for MC signaling */

12403 UINT32 SadNonCorrupingErrOther : 1;

12404

12405 /* Bits[5:5], Access Type=RW, default=0x00000000*/

12406

12407 /* Enable bit for MC signaling */

12408 UINT32 MultipleTagMatchErr : 1;

12409

12410 /* Bits[6:6], Access Type=RW, default=0x00000000*/

12411

12412 /* Enable bit for MC signaling */

12413 UINT32 IdiJitterError : 1;

12414

12415 /* Bits[7:7], Access Type=RW, default=0x00000000*/

12416

12417 /* Enable bit for MC signaling */

12418 UINT32 Rsvd8 : 24;

12419

12420 /* Bits[31:8], Access Type=RO, default=None*/

12421

12422 /* Reserved */

12423 UINT32 Rsvd32 : 32;

12424

12425 /* Bits[63:32], Access Type=RO, default=None*/

12426

12427 /* Reserved */

12428

12429 } Bits;

12430

12431 UINT32 Uint32;

12432 UINT64 Uint64;

12433

12434 } MSR_MC14_CTL_REGISTER;

12435

12436 /**

12437 LLC MCA bank: Status register

12438 **/

12439 #define MSR_MC14_STATUS 0x00000439

12440

12441 typedef union {

12442 ///

12443 /// Individual bit fields

12444 ///

12445 struct {

12446 UINT32 McaErrorCode : 16;

12447

12448 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

12449

12450 /* MCA error code */

12451 UINT32 ModelSpecificErrorCode : 16;

12452

12453 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

12454

12455 /* Model specific error code */

12456 UINT32 EnhMcaAvail0 : 6;

12457

12458 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12459

12460 /* Available when Enhanced MCA is in use */

12461 UINT32 CorrErrCount : 15;

12462

12463 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

12464

12465 /* Correctable error count */

12466 UINT32 Correrrorstatusind : 2;

12467

12468 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

12469

12470 /*

12471 These bits are used to indicate when the number

12472 of corrected errors has exceeded the safe

12473 threshold to the point where an uncorrected

12474 error has become more likely to happen. Table 3

12475 shows the encoding of these bits.

12476 */

12477 UINT32 EnhMcaAvail1 : 2;

12478

12479 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

12480

12481 /* Available when Enhanced MCA is in use */

12482 UINT32 Pcc : 1;

12483

12484 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

12485

12486 /* PCC: Processor context corrupt */

12487 UINT32 Addrv : 1;

12488

12489 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

12490

12491 /*

12492 ADDRV: The address held in the MC6_ADDR_MSR is

12493 valid

12494 */

12495 UINT32 Miscv : 1;

12496

12497 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

12498

12499 /*

12500 MISCV: The value held in the MC6_MISC_MSR is

12501 valid

12502 */

12503 UINT32 En : 1;

12504

12505 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

12506

12507 /*

12508 EN: Error enabled flag Indicates (when set) that

12509 signaling of the machine check exception for

12510 this error was enabled by an associated flag bit

12511 of the Mci_CTL register.

12512 */

12513 UINT32 Uc : 1;

12514

12515 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

12516

12517 /*

12518 UC: Error uncorrected flag Indicates (when set)

12519 that the processor did not correct the error

12520 condition. When clear, this flag indicates that

12521 the processor was able to correct the error

12522 condition.

12523 */

12524 UINT32 Over : 1;

12525

12526 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

12527

12528 /* OVER: Machine check overflow */

12529 UINT32 Val : 1;

12530

12531 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

12532

12533 /*

12534 VAL: Valid flag Indicates (when set) that the

12535 information within the Mci_STATUS register is

12536 valid. When this flag is set, the processor

12537 follows the rules given for the OVER flag in the

12538 Mci_STATUS register when overwriting previously

12539 valid entries. The processor sets the VAL flag

12540 and software is responsible for clearing it.

12541 */

12542

12543 } Bits;

12544

12545 UINT32 Uint32;

12546 UINT64 Uint64;

12547

12548 } MSR_MC14_STATUS_REGISTER;

12549

12550 /**

12551 LLC MCA bank: Address register

12552 **/

12553 #define MSR_MC14_ADDR 0x0000043A

12554

12555 typedef union {

12556 ///

12557 /// Individual bit fields

12558 ///

12559 struct {

12560 UINT32 AddressOffset : 6;

12561

12562 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12563

12564 /*

12565 Bits [5:0] of the Machine Check logged address.

12566 Enchanced MCA feature made this field writable

12567 */

12568 UINT32 Address0 : 26;

12569

12570 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

12571

12572 /* address of the logged error */

12573 UINT32 Address1 : 7;

12574

12575 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

12576

12577 /* address of the logged error */

12578 UINT32 EnhMcaAvail : 25;

12579

12580 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

12581

12582 /* Available when Enhanced MCA is in use */

12583

12584 } Bits;

12585

12586 UINT32 Uint32;

12587 UINT64 Uint64;

12588

12589 } MSR_MC14_ADDR_REGISTER;

12590

12591 /**

12592 LLC MCA bank: Misc register

12593 **/

12594 #define MSR_MC14_MISC 0x0000043B

12595

12596 typedef union {

12597 ///

12598 /// Individual bit fields

12599 ///

12600 struct {

12601 UINT32 LsbAddr : 6;

12602

12603 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12604

12605 /*

12606 Points to where the supported LSB in MCi_Addr in

12607 SNB LLC cases it's always 6 (=000110)

12608 */

12609 UINT32 Addrmode : 3;

12610

12611 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

12612

12613 /*

12614 Address Mode = 010 since we always have only PA

12615 in the SNB LLC

12616 */

12617 UINT32 EnhMcaAvail0 : 5;

12618

12619 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

12620

12621 /* Available when Enhanced MCA is in use */

12622 UINT32 Way : 4;

12623

12624 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

12625

12626 /* The way associated with the logged error */

12627 UINT32 EnhMcaAvail1 : 6;

12628

12629 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

12630

12631 /* Available when Enhanced MCA is in use */

12632 UINT32 Threadid : 1;

12633

12634 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

12635

12636 /* Thread ID associated with the logged error */

12637 UINT32 Coreid : 4;

12638

12639 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

12640

12641 /* Core ID associated with the logged error */

12642 UINT32 Opcode0 : 3;

12643

12644 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

12645

12646 /* pipe command associated with the error */

12647 UINT32 Opcode1 : 6;

12648

12649 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12650

12651 /* pipe command associated with the error */

12652 UINT32 Torid : 6;

12653

12654 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

12655

12656 /* Entry in the TOR */

12657 UINT32 EnhMcaAvail2 : 20;

12658

12659 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

12660

12661 /* Available when Enhanced MCA is in use */

12662

12663 } Bits;

12664

12665 UINT32 Uint32;

12666 UINT64 Uint64;

12667

12668 } MSR_MC14_MISC_REGISTER;

12669

12670 /**

12671 CBO and LLC MCA bank: Control register

12672 **/

12673 #define MSR_MC15_CTL 0x0000043C

12674

12675 typedef union {

12676 ///

12677 /// Individual bit fields

12678 ///

12679 struct {

12680 UINT32 LlcTagError : 1;

12681

12682 /* Bits[0:0], Access Type=RW, default=0x00000000*/

12683

12684 /* Enable bit for MC signaling */

12685 UINT32 LlcDataError : 1;

12686

12687 /* Bits[1:1], Access Type=RW, default=0x00000000*/

12688

12689 /* Enable bit for MC signaling */

12690 UINT32 SadErrWbToMmio : 1;

12691

12692 /* Bits[2:2], Access Type=RW, default=0x00000000*/

12693

12694 /* Enable bit for MC signaling */

12695 UINT32 SadErrIaAccessToGsm : 1;

12696

12697 /* Bits[3:3], Access Type=RW, default=0x00000000*/

12698

12699 /* Enable bit for MC signaling */

12700 UINT32 SadCorrupingErrOther : 1;

12701

12702 /* Bits[4:4], Access Type=RW, default=0x00000000*/

12703

12704 /* Enable bit for MC signaling */

12705 UINT32 SadNonCorrupingErrOther : 1;

12706

12707 /* Bits[5:5], Access Type=RW, default=0x00000000*/

12708

12709 /* Enable bit for MC signaling */

12710 UINT32 MultipleTagMatchErr : 1;

12711

12712 /* Bits[6:6], Access Type=RW, default=0x00000000*/

12713

12714 /* Enable bit for MC signaling */

12715 UINT32 IdiJitterError : 1;

12716

12717 /* Bits[7:7], Access Type=RW, default=0x00000000*/

12718

12719 /* Enable bit for MC signaling */

12720 UINT32 Rsvd8 : 24;

12721

12722 /* Bits[31:8], Access Type=RO, default=None*/

12723

12724 /* Reserved */

12725 UINT32 Rsvd32 : 32;

12726

12727 /* Bits[63:32], Access Type=RO, default=None*/

12728

12729 /* Reserved */

12730

12731 } Bits;

12732

12733 UINT32 Uint32;

12734 UINT64 Uint64;

12735

12736 } MSR_MC15_CTL_REGISTER;

12737

12738 /**

12739 LLC MCA bank: Status register

12740 **/

12741 #define MSR_MC15_STATUS 0x0000043D

12742

12743 typedef union {

12744 ///

12745 /// Individual bit fields

12746 ///

12747 struct {

12748 UINT32 McaErrorCode : 16;

12749

12750 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

12751

12752 /* MCA error code */

12753 UINT32 ModelSpecificErrorCode : 16;

12754

12755 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

12756

12757 /* Model specific error code */

12758 UINT32 EnhMcaAvail0 : 6;

12759

12760 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12761

12762 /* Available when Enhanced MCA is in use */

12763 UINT32 CorrErrCount : 15;

12764

12765 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

12766

12767 /* Correctable error count */

12768 UINT32 Correrrorstatusind : 2;

12769

12770 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

12771

12772 /*

12773 These bits are used to indicate when the number

12774 of corrected errors has exceeded the safe

12775 threshold to the point where an uncorrected

12776 error has become more likely to happen. Table 3

12777 shows the encoding of these bits.

12778 */

12779 UINT32 EnhMcaAvail1 : 2;

12780

12781 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

12782

12783 /* Available when Enhanced MCA is in use */

12784 UINT32 Pcc : 1;

12785

12786 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

12787

12788 /* PCC: Processor context corrupt */

12789 UINT32 Addrv : 1;

12790

12791 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

12792

12793 /*

12794 ADDRV: The address held in the MC6_ADDR_MSR is

12795 valid

12796 */

12797 UINT32 Miscv : 1;

12798

12799 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

12800

12801 /*

12802 MISCV: The value held in the MC6_MISC_MSR is

12803 valid

12804 */

12805 UINT32 En : 1;

12806

12807 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

12808

12809 /*

12810 EN: Error enabled flag Indicates (when set) that

12811 signaling of the machine check exception for

12812 this error was enabled by an associated flag bit

12813 of the Mci_CTL register.

12814 */

12815 UINT32 Uc : 1;

12816

12817 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

12818

12819 /*

12820 UC: Error uncorrected flag Indicates (when set)

12821 that the processor did not correct the error

12822 condition. When clear, this flag indicates that

12823 the processor was able to correct the error

12824 condition.

12825 */

12826 UINT32 Over : 1;

12827

12828 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

12829

12830 /* OVER: Machine check overflow */

12831 UINT32 Val : 1;

12832

12833 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

12834

12835 /*

12836 VAL: Valid flag Indicates (when set) that the

12837 information within the Mci_STATUS register is

12838 valid. When this flag is set, the processor

12839 follows the rules given for the OVER flag in the

12840 Mci_STATUS register when overwriting previously

12841 valid entries. The processor sets the VAL flag

12842 and software is responsible for clearing it.

12843 */

12844

12845 } Bits;

12846

12847 UINT32 Uint32;

12848 UINT64 Uint64;

12849

12850 } MSR_MC15_STATUS_REGISTER;

12851

12852 /**

12853 LLC MCA bank: Address register

12854 **/

12855 #define MSR_MC15_ADDR 0x0000043E

12856

12857 typedef union {

12858 ///

12859 /// Individual bit fields

12860 ///

12861 struct {

12862 UINT32 AddressOffset : 6;

12863

12864 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12865

12866 /*

12867 Bits [5:0] of the Machine Check logged address.

12868 Enchanced MCA feature made this field writable

12869 */

12870 UINT32 Address0 : 26;

12871

12872 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

12873

12874 /* address of the logged error */

12875 UINT32 Address1 : 7;

12876

12877 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

12878

12879 /* address of the logged error */

12880 UINT32 EnhMcaAvail : 25;

12881

12882 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

12883

12884 /* Available when Enhanced MCA is in use */

12885

12886 } Bits;

12887

12888 UINT32 Uint32;

12889 UINT64 Uint64;

12890

12891 } MSR_MC15_ADDR_REGISTER;

12892

12893 /**

12894 LLC MCA bank: Misc register

12895 **/

12896 #define MSR_MC15_MISC 0x0000043F

12897

12898 typedef union {

12899 ///

12900 /// Individual bit fields

12901 ///

12902 struct {

12903 UINT32 LsbAddr : 6;

12904

12905 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

12906

12907 /*

12908 Points to where the supported LSB in MCi_Addr in

12909 SNB LLC cases it's always 6 (=000110)

12910 */

12911 UINT32 Addrmode : 3;

12912

12913 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

12914

12915 /*

12916 Address Mode = 010 since we always have only PA

12917 in the SNB LLC

12918 */

12919 UINT32 EnhMcaAvail0 : 5;

12920

12921 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

12922

12923 /* Available when Enhanced MCA is in use */

12924 UINT32 Way : 4;

12925

12926 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

12927

12928 /* The way associated with the logged error */

12929 UINT32 EnhMcaAvail1 : 6;

12930

12931 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

12932

12933 /* Available when Enhanced MCA is in use */

12934 UINT32 Threadid : 1;

12935

12936 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

12937

12938 /* Thread ID associated with the logged error */

12939 UINT32 Coreid : 4;

12940

12941 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

12942

12943 /* Core ID associated with the logged error */

12944 UINT32 Opcode0 : 3;

12945

12946 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

12947

12948 /* pipe command associated with the error */

12949 UINT32 Opcode1 : 6;

12950

12951 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

12952

12953 /* pipe command associated with the error */

12954 UINT32 Torid : 6;

12955

12956 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

12957

12958 /* Entry in the TOR */

12959 UINT32 EnhMcaAvail2 : 20;

12960

12961 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

12962

12963 /* Available when Enhanced MCA is in use */

12964

12965 } Bits;

12966

12967 UINT32 Uint32;

12968 UINT64 Uint64;

12969

12970 } MSR_MC15_MISC_REGISTER;

12971

12972 /**

12973 CBO and LLC MCA bank: Control register

12974 **/

12975 #define MSR_MC16_CTL 0x00000440

12976

12977 typedef union {

12978 ///

12979 /// Individual bit fields

12980 ///

12981 struct {

12982 UINT32 LlcTagError : 1;

12983

12984 /* Bits[0:0], Access Type=RW, default=0x00000000*/

12985

12986 /* Enable bit for MC signaling */

12987 UINT32 LlcDataError : 1;

12988

12989 /* Bits[1:1], Access Type=RW, default=0x00000000*/

12990

12991 /* Enable bit for MC signaling */

12992 UINT32 SadErrWbToMmio : 1;

12993

12994 /* Bits[2:2], Access Type=RW, default=0x00000000*/

12995

12996 /* Enable bit for MC signaling */

12997 UINT32 SadErrIaAccessToGsm : 1;

12998

12999 /* Bits[3:3], Access Type=RW, default=0x00000000*/

13000

13001 /* Enable bit for MC signaling */

13002 UINT32 SadCorrupingErrOther : 1;

13003

13004 /* Bits[4:4], Access Type=RW, default=0x00000000*/

13005

13006 /* Enable bit for MC signaling */

13007 UINT32 SadNonCorrupingErrOther : 1;

13008

13009 /* Bits[5:5], Access Type=RW, default=0x00000000*/

13010

13011 /* Enable bit for MC signaling */

13012 UINT32 MultipleTagMatchErr : 1;

13013

13014 /* Bits[6:6], Access Type=RW, default=0x00000000*/

13015

13016 /* Enable bit for MC signaling */

13017 UINT32 IdiJitterError : 1;

13018

13019 /* Bits[7:7], Access Type=RW, default=0x00000000*/

13020

13021 /* Enable bit for MC signaling */

13022 UINT32 Rsvd8 : 24;

13023

13024 /* Bits[31:8], Access Type=RO, default=None*/

13025

13026 /* Reserved */

13027 UINT32 Rsvd32 : 32;

13028

13029 /* Bits[63:32], Access Type=RO, default=None*/

13030

13031 /* Reserved */

13032

13033 } Bits;

13034

13035 UINT32 Uint32;

13036 UINT64 Uint64;

13037

13038 } MSR_MC16_CTL_REGISTER;

13039

13040 /**

13041 LLC MCA bank: Status register

13042 **/

13043 #define MSR_MC16_STATUS 0x00000441

13044

13045 typedef union {

13046 ///

13047 /// Individual bit fields

13048 ///

13049 struct {

13050 UINT32 McaErrorCode : 16;

13051

13052 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

13053

13054 /* MCA error code */

13055 UINT32 ModelSpecificErrorCode : 16;

13056

13057 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

13058

13059 /* Model specific error code */

13060 UINT32 EnhMcaAvail0 : 6;

13061

13062 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13063

13064 /* Available when Enhanced MCA is in use */

13065 UINT32 CorrErrCount : 15;

13066

13067 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

13068

13069 /* Correctable error count */

13070 UINT32 Correrrorstatusind : 2;

13071

13072 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

13073

13074 /*

13075 These bits are used to indicate when the number

13076 of corrected errors has exceeded the safe

13077 threshold to the point where an uncorrected

13078 error has become more likely to happen. Table 3

13079 shows the encoding of these bits.

13080 */

13081 UINT32 EnhMcaAvail1 : 2;

13082

13083 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

13084

13085 /* Available when Enhanced MCA is in use */

13086 UINT32 Pcc : 1;

13087

13088 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

13089

13090 /* PCC: Processor context corrupt */

13091 UINT32 Addrv : 1;

13092

13093 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

13094

13095 /*

13096 ADDRV: The address held in the MC6_ADDR_MSR is

13097 valid

13098 */

13099 UINT32 Miscv : 1;

13100

13101 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

13102

13103 /*

13104 MISCV: The value held in the MC6_MISC_MSR is

13105 valid

13106 */

13107 UINT32 En : 1;

13108

13109 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

13110

13111 /*

13112 EN: Error enabled flag Indicates (when set) that

13113 signaling of the machine check exception for

13114 this error was enabled by an associated flag bit

13115 of the Mci_CTL register.

13116 */

13117 UINT32 Uc : 1;

13118

13119 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

13120

13121 /*

13122 UC: Error uncorrected flag Indicates (when set)

13123 that the processor did not correct the error

13124 condition. When clear, this flag indicates that

13125 the processor was able to correct the error

13126 condition.

13127 */

13128 UINT32 Over : 1;

13129

13130 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

13131

13132 /* OVER: Machine check overflow */

13133 UINT32 Val : 1;

13134

13135 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

13136

13137 /*

13138 VAL: Valid flag Indicates (when set) that the

13139 information within the Mci_STATUS register is

13140 valid. When this flag is set, the processor

13141 follows the rules given for the OVER flag in the

13142 Mci_STATUS register when overwriting previously

13143 valid entries. The processor sets the VAL flag

13144 and software is responsible for clearing it.

13145 */

13146

13147 } Bits;

13148

13149 UINT32 Uint32;

13150 UINT64 Uint64;

13151

13152 } MSR_MC16_STATUS_REGISTER;

13153

13154 /**

13155 LLC MCA bank: Address register

13156 **/

13157 #define MSR_MC16_ADDR 0x00000442

13158

13159 typedef union {

13160 ///

13161 /// Individual bit fields

13162 ///

13163 struct {

13164 UINT32 AddressOffset : 6;

13165

13166 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13167

13168 /*

13169 Bits [5:0] of the Machine Check logged address.

13170 Enchanced MCA feature made this field writable

13171 */

13172 UINT32 Address0 : 26;

13173

13174 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

13175

13176 /* address of the logged error */

13177 UINT32 Address1 : 7;

13178

13179 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

13180

13181 /* address of the logged error */

13182 UINT32 EnhMcaAvail : 25;

13183

13184 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

13185

13186 /* Available when Enhanced MCA is in use */

13187

13188 } Bits;

13189

13190 UINT32 Uint32;

13191 UINT64 Uint64;

13192

13193 } MSR_MC16_ADDR_REGISTER;

13194

13195 /**

13196 LLC MCA bank: Misc register

13197 **/

13198 #define MSR_MC16_MISC 0x00000443

13199

13200 typedef union {

13201 ///

13202 /// Individual bit fields

13203 ///

13204 struct {

13205 UINT32 LsbAddr : 6;

13206

13207 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13208

13209 /*

13210 Points to where the supported LSB in MCi_Addr in

13211 SNB LLC cases it's always 6 (=000110)

13212 */

13213 UINT32 Addrmode : 3;

13214

13215 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

13216

13217 /*

13218 Address Mode = 010 since we always have only PA

13219 in the SNB LLC

13220 */

13221 UINT32 EnhMcaAvail0 : 5;

13222

13223 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

13224

13225 /* Available when Enhanced MCA is in use */

13226 UINT32 Way : 4;

13227

13228 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

13229

13230 /* The way associated with the logged error */

13231 UINT32 EnhMcaAvail1 : 6;

13232

13233 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

13234

13235 /* Available when Enhanced MCA is in use */

13236 UINT32 Threadid : 1;

13237

13238 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

13239

13240 /* Thread ID associated with the logged error */

13241 UINT32 Coreid : 4;

13242

13243 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

13244

13245 /* Core ID associated with the logged error */

13246 UINT32 Opcode0 : 3;

13247

13248 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

13249

13250 /* pipe command associated with the error */

13251 UINT32 Opcode1 : 6;

13252

13253 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13254

13255 /* pipe command associated with the error */

13256 UINT32 Torid : 6;

13257

13258 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

13259

13260 /* Entry in the TOR */

13261 UINT32 EnhMcaAvail2 : 20;

13262

13263 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

13264

13265 /* Available when Enhanced MCA is in use */

13266

13267 } Bits;

13268

13269 UINT32 Uint32;

13270 UINT64 Uint64;

13271

13272 } MSR_MC16_MISC_REGISTER;

13273

13274 /**

13275 CBO and LLC MCA bank: Control register

13276 **/

13277 #define MSR_MC17_CTL 0x00000444

13278

13279 typedef union {

13280 ///

13281 /// Individual bit fields

13282 ///

13283 struct {

13284 UINT32 LlcTagError : 1;

13285

13286 /* Bits[0:0], Access Type=RW, default=0x00000000*/

13287

13288 /* Enable bit for MC signaling */

13289 UINT32 LlcDataError : 1;

13290

13291 /* Bits[1:1], Access Type=RW, default=0x00000000*/

13292

13293 /* Enable bit for MC signaling */

13294 UINT32 SadErrWbToMmio : 1;

13295

13296 /* Bits[2:2], Access Type=RW, default=0x00000000*/

13297

13298 /* Enable bit for MC signaling */

13299 UINT32 SadErrIaAccessToGsm : 1;

13300

13301 /* Bits[3:3], Access Type=RW, default=0x00000000*/

13302

13303 /* Enable bit for MC signaling */

13304 UINT32 SadCorrupingErrOther : 1;

13305

13306 /* Bits[4:4], Access Type=RW, default=0x00000000*/

13307

13308 /* Enable bit for MC signaling */

13309 UINT32 SadNonCorrupingErrOther : 1;

13310

13311 /* Bits[5:5], Access Type=RW, default=0x00000000*/

13312

13313 /* Enable bit for MC signaling */

13314 UINT32 MultipleTagMatchErr : 1;

13315

13316 /* Bits[6:6], Access Type=RW, default=0x00000000*/

13317

13318 /* Enable bit for MC signaling */

13319 UINT32 IdiJitterError : 1;

13320

13321 /* Bits[7:7], Access Type=RW, default=0x00000000*/

13322

13323 /* Enable bit for MC signaling */

13324 UINT32 Rsvd8 : 24;

13325

13326 /* Bits[31:8], Access Type=RO, default=None*/

13327

13328 /* Reserved */

13329 UINT32 Rsvd32 : 32;

13330

13331 /* Bits[63:32], Access Type=RO, default=None*/

13332

13333 /* Reserved */

13334

13335 } Bits;

13336

13337 UINT32 Uint32;

13338 UINT64 Uint64;

13339

13340 } MSR_MC17_CTL_REGISTER;

13341

13342 /**

13343 LLC MCA bank: Status register

13344 **/

13345 #define MSR_MC17_STATUS 0x00000445

13346

13347 typedef union {

13348 ///

13349 /// Individual bit fields

13350 ///

13351 struct {

13352 UINT32 McaErrorCode : 16;

13353

13354 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

13355

13356 /* MCA error code */

13357 UINT32 ModelSpecificErrorCode : 16;

13358

13359 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

13360

13361 /* Model specific error code */

13362 UINT32 EnhMcaAvail0 : 6;

13363

13364 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13365

13366 /* Available when Enhanced MCA is in use */

13367 UINT32 CorrErrCount : 15;

13368

13369 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

13370

13371 /* Correctable error count */

13372 UINT32 Correrrorstatusind : 2;

13373

13374 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

13375

13376 /*

13377 These bits are used to indicate when the number

13378 of corrected errors has exceeded the safe

13379 threshold to the point where an uncorrected

13380 error has become more likely to happen. Table 3

13381 shows the encoding of these bits.

13382 */

13383 UINT32 EnhMcaAvail1 : 2;

13384

13385 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

13386

13387 /* Available when Enhanced MCA is in use */

13388 UINT32 Pcc : 1;

13389

13390 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

13391

13392 /* PCC: Processor context corrupt */

13393 UINT32 Addrv : 1;

13394

13395 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

13396

13397 /*

13398 ADDRV: The address held in the MC6_ADDR_MSR is

13399 valid

13400 */

13401 UINT32 Miscv : 1;

13402

13403 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

13404

13405 /*

13406 MISCV: The value held in the MC6_MISC_MSR is

13407 valid

13408 */

13409 UINT32 En : 1;

13410

13411 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

13412

13413 /*

13414 EN: Error enabled flag Indicates (when set) that

13415 signaling of the machine check exception for

13416 this error was enabled by an associated flag bit

13417 of the Mci_CTL register.

13418 */

13419 UINT32 Uc : 1;

13420

13421 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

13422

13423 /*

13424 UC: Error uncorrected flag Indicates (when set)

13425 that the processor did not correct the error

13426 condition. When clear, this flag indicates that

13427 the processor was able to correct the error

13428 condition.

13429 */

13430 UINT32 Over : 1;

13431

13432 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

13433

13434 /* OVER: Machine check overflow */

13435 UINT32 Val : 1;

13436

13437 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

13438

13439 /*

13440 VAL: Valid flag Indicates (when set) that the

13441 information within the Mci_STATUS register is

13442 valid. When this flag is set, the processor

13443 follows the rules given for the OVER flag in the

13444 Mci_STATUS register when overwriting previously

13445 valid entries. The processor sets the VAL flag

13446 and software is responsible for clearing it.

13447 */

13448

13449 } Bits;

13450

13451 UINT32 Uint32;

13452 UINT64 Uint64;

13453

13454 } MSR_MC17_STATUS_REGISTER;

13455

13456 /**

13457 LLC MCA bank: Address register

13458 **/

13459 #define MSR_MC17_ADDR 0x00000446

13460

13461 typedef union {

13462 ///

13463 /// Individual bit fields

13464 ///

13465 struct {

13466 UINT32 AddressOffset : 6;

13467

13468 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13469

13470 /*

13471 Bits [5:0] of the Machine Check logged address.

13472 Enchanced MCA feature made this field writable

13473 */

13474 UINT32 Address0 : 26;

13475

13476 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

13477

13478 /* address of the logged error */

13479 UINT32 Address1 : 7;

13480

13481 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

13482

13483 /* address of the logged error */

13484 UINT32 EnhMcaAvail : 25;

13485

13486 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

13487

13488 /* Available when Enhanced MCA is in use */

13489

13490 } Bits;

13491

13492 UINT32 Uint32;

13493 UINT64 Uint64;

13494

13495 } MSR_MC17_ADDR_REGISTER;

13496

13497 /**

13498 LLC MCA bank: Misc register

13499 **/

13500 #define MSR_MC17_MISC 0x00000447

13501

13502 typedef union {

13503 ///

13504 /// Individual bit fields

13505 ///

13506 struct {

13507 UINT32 LsbAddr : 6;

13508

13509 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13510

13511 /*

13512 Points to where the supported LSB in MCi_Addr in

13513 SNB LLC cases it's always 6 (=000110)

13514 */

13515 UINT32 Addrmode : 3;

13516

13517 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

13518

13519 /*

13520 Address Mode = 010 since we always have only PA

13521 in the SNB LLC

13522 */

13523 UINT32 EnhMcaAvail0 : 5;

13524

13525 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

13526

13527 /* Available when Enhanced MCA is in use */

13528 UINT32 Way : 4;

13529

13530 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

13531

13532 /* The way associated with the logged error */

13533 UINT32 EnhMcaAvail1 : 6;

13534

13535 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

13536

13537 /* Available when Enhanced MCA is in use */

13538 UINT32 Threadid : 1;

13539

13540 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

13541

13542 /* Thread ID associated with the logged error */

13543 UINT32 Coreid : 4;

13544

13545 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

13546

13547 /* Core ID associated with the logged error */

13548 UINT32 Opcode0 : 3;

13549

13550 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

13551

13552 /* pipe command associated with the error */

13553 UINT32 Opcode1 : 6;

13554

13555 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13556

13557 /* pipe command associated with the error */

13558 UINT32 Torid : 6;

13559

13560 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

13561

13562 /* Entry in the TOR */

13563 UINT32 EnhMcaAvail2 : 20;

13564

13565 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

13566

13567 /* Available when Enhanced MCA is in use */

13568

13569 } Bits;

13570

13571 UINT32 Uint32;

13572 UINT64 Uint64;

13573

13574 } MSR_MC17_MISC_REGISTER;

13575

13576 /**

13577 CBO and LLC MCA bank: Control register

13578 **/

13579 #define MSR_MC18_CTL 0x00000448

13580

13581 typedef union {

13582 ///

13583 /// Individual bit fields

13584 ///

13585 struct {

13586 UINT32 LlcTagError : 1;

13587

13588 /* Bits[0:0], Access Type=RW, default=0x00000000*/

13589

13590 /* Enable bit for MC signaling */

13591 UINT32 LlcDataError : 1;

13592

13593 /* Bits[1:1], Access Type=RW, default=0x00000000*/

13594

13595 /* Enable bit for MC signaling */

13596 UINT32 SadErrWbToMmio : 1;

13597

13598 /* Bits[2:2], Access Type=RW, default=0x00000000*/

13599

13600 /* Enable bit for MC signaling */

13601 UINT32 SadErrIaAccessToGsm : 1;

13602

13603 /* Bits[3:3], Access Type=RW, default=0x00000000*/

13604

13605 /* Enable bit for MC signaling */

13606 UINT32 SadCorrupingErrOther : 1;

13607

13608 /* Bits[4:4], Access Type=RW, default=0x00000000*/

13609

13610 /* Enable bit for MC signaling */

13611 UINT32 SadNonCorrupingErrOther : 1;

13612

13613 /* Bits[5:5], Access Type=RW, default=0x00000000*/

13614

13615 /* Enable bit for MC signaling */

13616 UINT32 MultipleTagMatchErr : 1;

13617

13618 /* Bits[6:6], Access Type=RW, default=0x00000000*/

13619

13620 /* Enable bit for MC signaling */

13621 UINT32 IdiJitterError : 1;

13622

13623 /* Bits[7:7], Access Type=RW, default=0x00000000*/

13624

13625 /* Enable bit for MC signaling */

13626 UINT32 Rsvd8 : 24;

13627

13628 /* Bits[31:8], Access Type=RO, default=None*/

13629

13630 /* Reserved */

13631 UINT32 Rsvd32 : 32;

13632

13633 /* Bits[63:32], Access Type=RO, default=None*/

13634

13635 /* Reserved */

13636

13637 } Bits;

13638

13639 UINT32 Uint32;

13640 UINT64 Uint64;

13641

13642 } MSR_MC18_CTL_REGISTER;

13643

13644 /**

13645 LLC MCA bank: Status register

13646 **/

13647 #define MSR_MC18_STATUS 0x00000449

13648

13649 typedef union {

13650 ///

13651 /// Individual bit fields

13652 ///

13653 struct {

13654 UINT32 McaErrorCode : 16;

13655

13656 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

13657

13658 /* MCA error code */

13659 UINT32 ModelSpecificErrorCode : 16;

13660

13661 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

13662

13663 /* Model specific error code */

13664 UINT32 EnhMcaAvail0 : 6;

13665

13666 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13667

13668 /* Available when Enhanced MCA is in use */

13669 UINT32 CorrErrCount : 15;

13670

13671 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

13672

13673 /* Correctable error count */

13674 UINT32 Correrrorstatusind : 2;

13675

13676 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

13677

13678 /*

13679 These bits are used to indicate when the number

13680 of corrected errors has exceeded the safe

13681 threshold to the point where an uncorrected

13682 error has become more likely to happen. Table 3

13683 shows the encoding of these bits.

13684 */

13685 UINT32 EnhMcaAvail1 : 2;

13686

13687 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

13688

13689 /* Available when Enhanced MCA is in use */

13690 UINT32 Pcc : 1;

13691

13692 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

13693

13694 /* PCC: Processor context corrupt */

13695 UINT32 Addrv : 1;

13696

13697 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

13698

13699 /*

13700 ADDRV: The address held in the MC6_ADDR_MSR is

13701 valid

13702 */

13703 UINT32 Miscv : 1;

13704

13705 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

13706

13707 /*

13708 MISCV: The value held in the MC6_MISC_MSR is

13709 valid

13710 */

13711 UINT32 En : 1;

13712

13713 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

13714

13715 /*

13716 EN: Error enabled flag Indicates (when set) that

13717 signaling of the machine check exception for

13718 this error was enabled by an associated flag bit

13719 of the Mci_CTL register.

13720 */

13721 UINT32 Uc : 1;

13722

13723 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

13724

13725 /*

13726 UC: Error uncorrected flag Indicates (when set)

13727 that the processor did not correct the error

13728 condition. When clear, this flag indicates that

13729 the processor was able to correct the error

13730 condition.

13731 */

13732 UINT32 Over : 1;

13733

13734 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

13735

13736 /* OVER: Machine check overflow */

13737 UINT32 Val : 1;

13738

13739 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

13740

13741 /*

13742 VAL: Valid flag Indicates (when set) that the

13743 information within the Mci_STATUS register is

13744 valid. When this flag is set, the processor

13745 follows the rules given for the OVER flag in the

13746 Mci_STATUS register when overwriting previously

13747 valid entries. The processor sets the VAL flag

13748 and software is responsible for clearing it.

13749 */

13750

13751 } Bits;

13752

13753 UINT32 Uint32;

13754 UINT64 Uint64;

13755

13756 } MSR_MC18_STATUS_REGISTER;

13757

13758 /**

13759 LLC MCA bank: Address register

13760 **/

13761 #define MSR_MC18_ADDR 0x0000044A

13762

13763 typedef union {

13764 ///

13765 /// Individual bit fields

13766 ///

13767 struct {

13768 UINT32 AddressOffset : 6;

13769

13770 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13771

13772 /*

13773 Bits [5:0] of the Machine Check logged address.

13774 Enchanced MCA feature made this field writable

13775 */

13776 UINT32 Address0 : 26;

13777

13778 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

13779

13780 /* address of the logged error */

13781 UINT32 Address1 : 7;

13782

13783 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

13784

13785 /* address of the logged error */

13786 UINT32 EnhMcaAvail : 25;

13787

13788 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

13789

13790 /* Available when Enhanced MCA is in use */

13791

13792 } Bits;

13793

13794 UINT32 Uint32;

13795 UINT64 Uint64;

13796

13797 } MSR_MC18_ADDR_REGISTER;

13798

13799 /**

13800 LLC MCA bank: Misc register

13801 **/

13802 #define MSR_MC18_MISC 0x0000044B

13803

13804 typedef union {

13805 ///

13806 /// Individual bit fields

13807 ///

13808 struct {

13809 UINT32 LsbAddr : 6;

13810

13811 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

13812

13813 /*

13814 Points to where the supported LSB in MCi_Addr in

13815 SNB LLC cases it's always 6 (=000110)

13816 */

13817 UINT32 Addrmode : 3;

13818

13819 /* Bits[8:6], Access Type=RWS_V, default=0x00000000*/

13820

13821 /*

13822 Address Mode = 010 since we always have only PA

13823 in the SNB LLC

13824 */

13825 UINT32 EnhMcaAvail0 : 5;

13826

13827 /* Bits[13:9], Access Type=RWS_V, default=0x00000000*/

13828

13829 /* Available when Enhanced MCA is in use */

13830 UINT32 Way : 4;

13831

13832 /* Bits[17:14], Access Type=RWS_V, default=0x00000000*/

13833

13834 /* The way associated with the logged error */

13835 UINT32 EnhMcaAvail1 : 6;

13836

13837 /* Bits[23:18], Access Type=RWS_V, default=0x00000000*/

13838

13839 /* Available when Enhanced MCA is in use */

13840 UINT32 Threadid : 1;

13841

13842 /* Bits[24:24], Access Type=RWS_V, default=0x00000000*/

13843

13844 /* Thread ID associated with the logged error */

13845 UINT32 Coreid : 4;

13846

13847 /* Bits[28:25], Access Type=RWS_V, default=0x00000000*/

13848

13849 /* Core ID associated with the logged error */

13850 UINT32 Opcode0 : 3;

13851

13852 /* Bits[31:29], Access Type=RWS_V, default=0x00000000*/

13853

13854 /* pipe command associated with the error */

13855 UINT32 Opcode1 : 6;

13856

13857 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13858

13859 /* pipe command associated with the error */

13860 UINT32 Torid : 6;

13861

13862 /* Bits[43:38], Access Type=RWS_V, default=0x00000000*/

13863

13864 /* Entry in the TOR */

13865 UINT32 EnhMcaAvail2 : 20;

13866

13867 /* Bits[63:44], Access Type=RWS_V, default=0x00000000*/

13868

13869 /* Available when Enhanced MCA is in use */

13870

13871 } Bits;

13872

13873 UINT32 Uint32;

13874 UINT64 Uint64;

13875

13876 } MSR_MC18_MISC_REGISTER;

13877

13878 /**

13879 EDRAM 0 Machine Check Architecture Control MSR.

13880 **/

13881 #define MSR_MC19_CTL 0x0000044C

13882

13883 typedef union {

13884 ///

13885 /// Individual bit fields

13886 ///

13887 struct {

13888 UINT32 EdcDataUncorrError : 1;

13889

13890 /* Bits[0:0], Access Type=RW, default=0x00000000*/

13891

13892 /* Enable bit for MC signaling */

13893 UINT32 AddrCmdParity : 1;

13894

13895 /* Bits[1:1], Access Type=RW, default=0x00000000*/

13896

13897 /* Enable bit for MC signaling */

13898 UINT32 EtagUncorrError : 1;

13899

13900 /* Bits[2:2], Access Type=RW, default=0x00000000*/

13901

13902 /* Enable bit for MC signaling */

13903 UINT32 EtagMultiMatchError : 1;

13904

13905 /* Bits[3:3], Access Type=RW, default=0x00000000*/

13906

13907 /* Enable bit for MC signaling */

13908 UINT32 EtrogUnknownError : 1;

13909

13910 /* Bits[4:4], Access Type=RW, default=0x00000000*/

13911

13912 /* Enable bit for MC signaling */

13913 UINT32 SaveRestoreUncorrError : 1;

13914

13915 /* Bits[5:5], Access Type=RW, default=0x00000000*/

13916

13917 /* Enable bit for MC signaling */

13918 UINT32 Rsvd6 : 26;

13919

13920 /* Bits[31:6], Access Type=RO, default=None*/

13921

13922 /* Reserved */

13923 UINT32 Rsvd32 : 32;

13924

13925 /* Bits[63:32], Access Type=RO, default=None*/

13926

13927 /* Reserved */

13928

13929 } Bits;

13930

13931 UINT32 Uint32;

13932 UINT64 Uint64;

13933

13934 } MSR_MC19_CTL_REGISTER;

13935

13936 /**

13937 EDRAM 0 MCA bank: Status Register

13938 **/

13939 #define MSR_MC19_STATUS 0x0000044D

13940

13941 typedef union {

13942 ///

13943 /// Individual bit fields

13944 ///

13945 struct {

13946 UINT32 Mcacod : 16;

13947

13948 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

13949

13950 /* MCA error code */

13951 UINT32 Mscod : 16;

13952

13953 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

13954

13955 /* Model specific error code */

13956 UINT32 EnhMcaAvail0 : 6;

13957

13958 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

13959

13960 /*

13961 Available when Enhanced MCA is in use - unused

13962 in etrog

13963 */

13964 UINT32 CorrectedErrorCount : 15;

13965

13966 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

13967

13968 /* Correctable error count */

13969 UINT32 ThresholdBasedErrorStatus : 2;

13970

13971 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

13972

13973 /*

13974 These bits are used to indicate when the number

13975 of corrected errors has exceeded the safe

13976 threshold to the point where an uncorrected

13977 error has become more likely to happen.

13978 */

13979 UINT32 Ar : 2;

13980

13981 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

13982

13983 /*

13984 Available when Enhanced MCA is in use, unused in

13985 etrog

13986 */

13987 UINT32 Pcc : 1;

13988

13989 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

13990

13991 /* PCC: Processor context corrupt */

13992 UINT32 Addrv : 1;

13993

13994 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

13995

13996 /*

13997 ADDRV: The address held in the MCi_ADDR_MSR is

13998 valid

13999 */

14000 UINT32 Miscv : 1;

14001

14002 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

14003

14004 /*

14005 MISCV: The value held in the MCi_MISC_MSR is

14006 valid

14007 */

14008 UINT32 En : 1;

14009

14010 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

14011

14012 /*

14013 EN: Error enabled flag Indicates (when set) that

14014 signaling of the machine check exception for

14015 this error was enabled by an associated flag bit

14016 of the Mci_CTL register.

14017 */

14018 UINT32 Uc : 1;

14019

14020 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

14021

14022 /*

14023 UC: Error uncorrected flag Indicates (when set)

14024 that the processor did not correct the error

14025 condition. When clear, this flag indicates that

14026 the processor was able to correct the error

14027 condition.

14028 */

14029 UINT32 Over : 1;

14030

14031 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

14032

14033 /* OVER: Machine check overflow */

14034 UINT32 Val : 1;

14035

14036 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

14037

14038 /*

14039 VAL: Valid flag Indicates (when set) that the

14040 information within the Mci_STATUS register is

14041 valid. When this flag is set, the processor

14042 follows the rules given for the OVER flag in the

14043 Mci_STATUS register when overwriting previously

14044 valid entries. The processor sets the VAL flag

14045 and software is responsible for clearing it.

14046 */

14047

14048 } Bits;

14049

14050 UINT32 Uint32;

14051 UINT64 Uint64;

14052

14053 } MSR_MC19_STATUS_REGISTER;

14054

14055 /**

14056 EDRAM 0 MCA bank: Address register

14057 **/

14058 #define MSR_MC19_ADDR 0x0000044E

14059

14060 typedef union {

14061 ///

14062 /// Individual bit fields

14063 ///

14064 struct {

14065 UINT32 AddressOffset : 6;

14066

14067 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

14068

14069 /*

14070 Bits [5:0] of the Machine Check logged address.

14071 Enchanced MCA feature made this field writable

14072 */

14073 UINT32 Address0 : 26;

14074

14075 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

14076

14077 /* address of the logged error */

14078 UINT32 Address1 : 7;

14079

14080 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

14081

14082 /* address of the logged error */

14083 UINT32 EnhMcaAvail : 25;

14084

14085 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

14086

14087 /* Available when Enhanced MCA is in use */

14088

14089 } Bits;

14090

14091 UINT32 Uint32;

14092 UINT64 Uint64;

14093

14094 } MSR_MC19_ADDR_REGISTER;

14095

14096 /**

14097 EDRAM 1 Machine Check Architecture Control MSR.

14098 **/

14099 #define MSR_MC20_CTL 0x00000450

14100

14101 typedef union {

14102 ///

14103 /// Individual bit fields

14104 ///

14105 struct {

14106 UINT32 EdcDataUncorrError : 1;

14107

14108 /* Bits[0:0], Access Type=RW, default=0x00000000*/

14109

14110 /* Enable bit for MC signaling */

14111 UINT32 AddrCmdParity : 1;

14112

14113 /* Bits[1:1], Access Type=RW, default=0x00000000*/

14114

14115 /* Enable bit for MC signaling */

14116 UINT32 EtagUncorrError : 1;

14117

14118 /* Bits[2:2], Access Type=RW, default=0x00000000*/

14119

14120 /* Enable bit for MC signaling */

14121 UINT32 EtagMultiMatchError : 1;

14122

14123 /* Bits[3:3], Access Type=RW, default=0x00000000*/

14124

14125 /* Enable bit for MC signaling */

14126 UINT32 EtrogUnknownError : 1;

14127

14128 /* Bits[4:4], Access Type=RW, default=0x00000000*/

14129

14130 /* Enable bit for MC signaling */

14131 UINT32 SaveRestoreUncorrError : 1;

14132

14133 /* Bits[5:5], Access Type=RW, default=0x00000000*/

14134

14135 /* Enable bit for MC signaling */

14136 UINT32 Rsvd6 : 26;

14137

14138 /* Bits[31:6], Access Type=RO, default=None*/

14139

14140 /* Reserved */

14141 UINT32 Rsvd32 : 32;

14142

14143 /* Bits[63:32], Access Type=RO, default=None*/

14144

14145 /* Reserved */

14146

14147 } Bits;

14148

14149 UINT32 Uint32;

14150 UINT64 Uint64;

14151

14152 } MSR_MC20_CTL_REGISTER;

14153

14154 /**

14155 EDRAM 1 MCA bank: Status Register

14156 **/

14157 #define MSR_MC20_STATUS 0x00000451

14158

14159 typedef union {

14160 ///

14161 /// Individual bit fields

14162 ///

14163 struct {

14164 UINT32 Mcacod : 16;

14165

14166 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14167

14168 /* MCA error code */

14169 UINT32 Mscod : 16;

14170

14171 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

14172

14173 /* Model specific error code */

14174 UINT32 EnhMcaAvail0 : 6;

14175

14176 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

14177

14178 /*

14179 Available when Enhanced MCA is in use - unused

14180 in etrog

14181 */

14182 UINT32 CorrectedErrorCount : 15;

14183

14184 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

14185

14186 /* Correctable error count */

14187 UINT32 ThresholdBasedErrorStatus : 2;

14188

14189 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

14190

14191 /*

14192 These bits are used to indicate when the number

14193 of corrected errors has exceeded the safe

14194 threshold to the point where an uncorrected

14195 error has become more likely to happen.

14196 */

14197 UINT32 Ar : 2;

14198

14199 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

14200

14201 /*

14202 Available when Enhanced MCA is in use, unused in

14203 etrog

14204 */

14205 UINT32 Pcc : 1;

14206

14207 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

14208

14209 /* PCC: Processor context corrupt */

14210 UINT32 Addrv : 1;

14211

14212 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

14213

14214 /*

14215 ADDRV: The address held in the MCi_ADDR_MSR is

14216 valid

14217 */

14218 UINT32 Miscv : 1;

14219

14220 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

14221

14222 /*

14223 MISCV: The value held in the MCi_MISC_MSR is

14224 valid

14225 */

14226 UINT32 En : 1;

14227

14228 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

14229

14230 /*

14231 EN: Error enabled flag Indicates (when set) that

14232 signaling of the machine check exception for

14233 this error was enabled by an associated flag bit

14234 of the Mci_CTL register.

14235 */

14236 UINT32 Uc : 1;

14237

14238 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

14239

14240 /*

14241 UC: Error uncorrected flag Indicates (when set)

14242 that the processor did not correct the error

14243 condition. When clear, this flag indicates that

14244 the processor was able to correct the error

14245 condition.

14246 */

14247 UINT32 Over : 1;

14248

14249 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

14250

14251 /* OVER: Machine check overflow */

14252 UINT32 Val : 1;

14253

14254 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

14255

14256 /*

14257 VAL: Valid flag Indicates (when set) that the

14258 information within the Mci_STATUS register is

14259 valid. When this flag is set, the processor

14260 follows the rules given for the OVER flag in the

14261 Mci_STATUS register when overwriting previously

14262 valid entries. The processor sets the VAL flag

14263 and software is responsible for clearing it.

14264 */

14265

14266 } Bits;

14267

14268 UINT32 Uint32;

14269 UINT64 Uint64;

14270

14271 } MSR_MC20_STATUS_REGISTER;

14272

14273 /**

14274 EDRAM 1 MCA bank: Address register

14275 **/

14276 #define MSR_MC20_ADDR 0x00000452

14277

14278 typedef union {

14279 ///

14280 /// Individual bit fields

14281 ///

14282 struct {

14283 UINT32 AddressOffset : 6;

14284

14285 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

14286

14287 /*

14288 Bits [5:0] of the Machine Check logged address.

14289 Enchanced MCA feature made this field writable

14290 */

14291 UINT32 Address0 : 26;

14292

14293 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

14294

14295 /* address of the logged error */

14296 UINT32 Address1 : 7;

14297

14298 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

14299

14300 /* address of the logged error */

14301 UINT32 EnhMcaAvail : 25;

14302

14303 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

14304

14305 /* Available when Enhanced MCA is in use */

14306

14307 } Bits;

14308

14309 UINT32 Uint32;

14310 UINT64 Uint64;

14311

14312 } MSR_MC20_ADDR_REGISTER;

14313

14314 /**

14315 2LM MCA bank: Control register

14316 **/

14317 #define MSR_MC21_CTL 0x00000454

14318

14319 typedef union {

14320 ///

14321 /// Individual bit fields

14322 ///

14323 struct {

14324 UINT32 EnUncorrectableTcMultipleTagMatchError : 1;

14325

14326 /* Bits[0:0], Access Type=RW, default=0x00000000*/

14327

14328 /* Enable bit for MC signaling */

14329 UINT32 EnUncorrectableTcTagError : 1;

14330

14331 /* Bits[1:1], Access Type=RW, default=0x00000000*/

14332

14333 /* Enable bit for MC signaling */

14334 UINT32 EnUncorrectableSdtCorruptionError : 1;

14335

14336 /* Bits[2:2], Access Type=RW, default=0x00000000*/

14337

14338 /* Enable bit for MC signaling */

14339 UINT32 EnUncorrectableAddressRangeError : 1;

14340

14341 /* Bits[3:3], Access Type=RW, default=0x00000000*/

14342

14343 /* Enable bit for MC signaling */

14344 UINT32 EnCorrectableTcTagError : 1;

14345

14346 /* Bits[4:4], Access Type=RW, default=0x00000000*/

14347

14348 /* Enable bit for MC signaling */

14349 UINT32 Rsvd5 : 27;

14350

14351 /* Bits[31:5], Access Type=RO, default=None*/

14352

14353 /* Reserved */

14354 UINT32 Rsvd32 : 32;

14355

14356 /* Bits[63:32], Access Type=RO, default=None*/

14357

14358 /* Reserved */

14359

14360 } Bits;

14361

14362 UINT32 Uint32;

14363 UINT64 Uint64;

14364

14365 } MSR_MC21_CTL_REGISTER;

14366

14367 /**

14368 2LM MCA bank: Status register

14369 **/

14370 #define MSR_MC21_STATUS 0x00000455

14371

14372 typedef union {

14373 ///

14374 /// Individual bit fields

14375 ///

14376 struct {

14377 UINT32 Mcacod : 16;

14378

14379 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14380

14381 /* MCA error code */

14382 UINT32 Mscod : 16;

14383

14384 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

14385

14386 /* Model specific error code */

14387 UINT32 EnhMcaAvail0 : 6;

14388

14389 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

14390

14391 /*

14392 Available when Enhanced MCA is in use - unused

14393 in 2LMc

14394 */

14395 UINT32 CorrectedErrorCount : 15;

14396

14397 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

14398

14399 /* Correctable error count */

14400 UINT32 ThresholdBasedErrorStatus : 2;

14401

14402 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

14403

14404 /*

14405 These bits are used to indicate when the number

14406 of corrected errors has exceeded the safe

14407 threshold to the point where an uncorrected

14408 error has become more likely to happen.

14409 */

14410 UINT32 Ar : 2;

14411

14412 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

14413

14414 /*

14415 Available when Enhanced MCA is in use, unused in

14416 2LMc

14417 */

14418 UINT32 Pcc : 1;

14419

14420 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

14421

14422 /* PCC: Processor context corrupt */

14423 UINT32 Addrv : 1;

14424

14425 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

14426

14427 /*

14428 ADDRV: The address held in the MCi_ADDR_MSR is

14429 valid

14430 */

14431 UINT32 Miscv : 1;

14432

14433 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

14434

14435 /*

14436 MISCV: The value held in the MCi_MISC_MSR is

14437 valid

14438 */

14439 UINT32 En : 1;

14440

14441 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

14442

14443 /*

14444 EN: Error enabled flag Indicates (when set) that

14445 signaling of the machine check exception for

14446 this error was enabled by an associated flag bit

14447 of the Mci_CTL register.

14448 */

14449 UINT32 Uc : 1;

14450

14451 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

14452

14453 /*

14454 UC: Error uncorrected flag Indicates (when set)

14455 that the processor did not correct the error

14456 condition. When clear, this flag indicates that

14457 the processor was able to correct the error

14458 condition.

14459 */

14460 UINT32 Over : 1;

14461

14462 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

14463

14464 /* OVER: Machine check overflow */

14465 UINT32 Val : 1;

14466

14467 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

14468

14469 /*

14470 VAL: Valid flag Indicates (when set) that the

14471 information within the Mci_STATUS register is

14472 valid. When this flag is set, the processor

14473 follows the rules given for the OVER flag in the

14474 Mci_STATUS register when overwriting previously

14475 valid entries. The processor sets the VAL flag

14476 and software is responsible for clearing it.

14477 */

14478

14479 } Bits;

14480

14481 UINT32 Uint32;

14482 UINT64 Uint64;

14483

14484 } MSR_MC21_STATUS_REGISTER;

14485

14486 /**

14487 2LM MCA bank: Address register

14488 **/

14489 #define MSR_MC21_ADDR 0x00000456

14490

14491 typedef union {

14492 ///

14493 /// Individual bit fields

14494 ///

14495 struct {

14496 UINT32 AddressOffset : 6;

14497

14498 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

14499

14500 /*

14501 Bits [5:0] of the Machine Check logged address.

14502 Enchanced MCA feature made this field writable

14503 */

14504 UINT32 Address0 : 26;

14505

14506 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

14507

14508 /* address of the logged error */

14509 UINT32 Address1 : 7;

14510

14511 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

14512

14513 /* address of the logged error */

14514 UINT32 EnhMcaAvail : 25;

14515

14516 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

14517

14518 /* Available when Enhanced MCA is in use */

14519

14520 } Bits;

14521

14522 UINT32 Uint32;

14523 UINT64 Uint64;

14524

14525 } MSR_MC21_ADDR_REGISTER;

14526

14527 /**

14528 2LM MCA bank: Miscellaneous register

14529 **/

14530 #define MSR_MC21_MISC 0x00000457

14531

14532 typedef union {

14533 ///

14534 /// Individual bit fields

14535 ///

14536 struct {

14537 UINT32 ErrorAddress : 16;

14538

14539 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14540

14541 /*

14542 This field contains the address of uncorrected

14543 error seen in the 2LMC/MLMc. It is updated on an

14544 uncorrectable error. To maintain e-MCA support

14545 this register must be writable.

14546 */

14547 UINT32 CorrectedErrorCount : 8;

14548

14549 /* Bits[23:16], Access Type=RWS_V, default=0x00000000*/

14550

14551 /* Corrected Error Count */

14552 UINT32 EnhMcaAvail0 : 8;

14553

14554 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

14555

14556 /* Available when enhanced MCA is in use */

14557 UINT32 EnhMcaAvail1 : 32;

14558

14559 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

14560

14561 /* Available when enhanced MCA is in use */

14562

14563 } Bits;

14564

14565 UINT32 Uint32;

14566 UINT64 Uint64;

14567

14568 } MSR_MC21_MISC_REGISTER;

14569

14570 /**

14571 2LM MCA bank: Control register

14572 **/

14573 #define MSR_MC22_CTL 0x00000458

14574

14575 typedef union {

14576 ///

14577 /// Individual bit fields

14578 ///

14579 struct {

14580 UINT32 EnUncorrectableTcMultipleTagMatchError : 1;

14581

14582 /* Bits[0:0], Access Type=RW, default=0x00000000*/

14583

14584 /* Enable bit for MC signaling */

14585 UINT32 EnUncorrectableTcTagError : 1;

14586

14587 /* Bits[1:1], Access Type=RW, default=0x00000000*/

14588

14589 /* Enable bit for MC signaling */

14590 UINT32 EnUncorrectableSdtCorruptionError : 1;

14591

14592 /* Bits[2:2], Access Type=RW, default=0x00000000*/

14593

14594 /* Enable bit for MC signaling */

14595 UINT32 EnUncorrectableAddressRangeError : 1;

14596

14597 /* Bits[3:3], Access Type=RW, default=0x00000000*/

14598

14599 /* Enable bit for MC signaling */

14600 UINT32 EnCorrectableTcTagError : 1;

14601

14602 /* Bits[4:4], Access Type=RW, default=0x00000000*/

14603

14604 /* Enable bit for MC signaling */

14605 UINT32 Rsvd5 : 27;

14606

14607 /* Bits[31:5], Access Type=RO, default=None*/

14608

14609 /* Reserved */

14610 UINT32 Rsvd32 : 32;

14611

14612 /* Bits[63:32], Access Type=RO, default=None*/

14613

14614 /* Reserved */

14615

14616 } Bits;

14617

14618 UINT32 Uint32;

14619 UINT64 Uint64;

14620

14621 } MSR_MC22_CTL_REGISTER;

14622

14623 /**

14624 2LM MCA bank: Status register

14625 **/

14626 #define MSR_MC22_STATUS 0x00000459

14627

14628 typedef union {

14629 ///

14630 /// Individual bit fields

14631 ///

14632 struct {

14633 UINT32 Mcacod : 16;

14634

14635 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14636

14637 /* MCA error code */

14638 UINT32 Mscod : 16;

14639

14640 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

14641

14642 /* Model specific error code */

14643 UINT32 EnhMcaAvail0 : 6;

14644

14645 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

14646

14647 /*

14648 Available when Enhanced MCA is in use - unused

14649 in 2LMc

14650 */

14651 UINT32 CorrectedErrorCount : 15;

14652

14653 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

14654

14655 /* Correctable error count */

14656 UINT32 ThresholdBasedErrorStatus : 2;

14657

14658 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

14659

14660 /*

14661 These bits are used to indicate when the number

14662 of corrected errors has exceeded the safe

14663 threshold to the point where an uncorrected

14664 error has become more likely to happen.

14665 */

14666 UINT32 Ar : 2;

14667

14668 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

14669

14670 /*

14671 Available when Enhanced MCA is in use, unused in

14672 2LMc

14673 */

14674 UINT32 Pcc : 1;

14675

14676 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

14677

14678 /* PCC: Processor context corrupt */

14679 UINT32 Addrv : 1;

14680

14681 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

14682

14683 /*

14684 ADDRV: The address held in the MCi_ADDR_MSR is

14685 valid

14686 */

14687 UINT32 Miscv : 1;

14688

14689 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

14690

14691 /*

14692 MISCV: The value held in the MCi_MISC_MSR is

14693 valid

14694 */

14695 UINT32 En : 1;

14696

14697 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

14698

14699 /*

14700 EN: Error enabled flag Indicates (when set) that

14701 signaling of the machine check exception for

14702 this error was enabled by an associated flag bit

14703 of the Mci_CTL register.

14704 */

14705 UINT32 Uc : 1;

14706

14707 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

14708

14709 /*

14710 UC: Error uncorrected flag Indicates (when set)

14711 that the processor did not correct the error

14712 condition. When clear, this flag indicates that

14713 the processor was able to correct the error

14714 condition.

14715 */

14716 UINT32 Over : 1;

14717

14718 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

14719

14720 /* OVER: Machine check overflow */

14721 UINT32 Val : 1;

14722

14723 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

14724

14725 /*

14726 VAL: Valid flag Indicates (when set) that the

14727 information within the Mci_STATUS register is

14728 valid. When this flag is set, the processor

14729 follows the rules given for the OVER flag in the

14730 Mci_STATUS register when overwriting previously

14731 valid entries. The processor sets the VAL flag

14732 and software is responsible for clearing it.

14733 */

14734

14735 } Bits;

14736

14737 UINT32 Uint32;

14738 UINT64 Uint64;

14739

14740 } MSR_MC22_STATUS_REGISTER;

14741

14742 /**

14743 2LM MCA bank: Address register

14744 **/

14745 #define MSR_MC22_ADDR 0x0000045A

14746

14747 typedef union {

14748 ///

14749 /// Individual bit fields

14750 ///

14751 struct {

14752 UINT32 AddressOffset : 6;

14753

14754 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

14755

14756 /*

14757 Bits [5:0] of the Machine Check logged address.

14758 Enchanced MCA feature made this field writable

14759 */

14760 UINT32 Address0 : 26;

14761

14762 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

14763

14764 /* address of the logged error */

14765 UINT32 Address1 : 7;

14766

14767 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

14768

14769 /* address of the logged error */

14770 UINT32 EnhMcaAvail : 25;

14771

14772 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

14773

14774 /* Available when Enhanced MCA is in use */

14775

14776 } Bits;

14777

14778 UINT32 Uint32;

14779 UINT64 Uint64;

14780

14781 } MSR_MC22_ADDR_REGISTER;

14782

14783 /**

14784 2LM MCA bank: Miscellaneous register

14785 **/

14786 #define MSR_MC22_MISC 0x0000045B

14787

14788 typedef union {

14789 ///

14790 /// Individual bit fields

14791 ///

14792 struct {

14793 UINT32 ErrorAddress : 16;

14794

14795 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14796

14797 /*

14798 This field contains the address of uncorrected

14799 error seen in the 2LMC/MLMc. It is updated on an

14800 uncorrectable error. To maintain e-MCA support

14801 this register must be writable.

14802 */

14803 UINT32 CorrectedErrorCount : 8;

14804

14805 /* Bits[23:16], Access Type=RWS_V, default=0x00000000*/

14806

14807 /* Corrected Error Count */

14808 UINT32 EnhMcaAvail0 : 8;

14809

14810 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

14811

14812 /* Available when enhanced MCA is in use */

14813 UINT32 EnhMcaAvail1 : 32;

14814

14815 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

14816

14817 /* Available when enhanced MCA is in use */

14818

14819 } Bits;

14820

14821 UINT32 Uint32;

14822 UINT64 Uint64;

14823

14824 } MSR_MC22_MISC_REGISTER;

14825

14826 /**

14827 2LM MCA bank: Control register

14828 **/

14829 #define MSR_MC23_CTL 0x0000045C

14830

14831 typedef union {

14832 ///

14833 /// Individual bit fields

14834 ///

14835 struct {

14836 UINT32 EnUncorrectableTcMultipleTagMatchError : 1;

14837

14838 /* Bits[0:0], Access Type=RW, default=0x00000000*/

14839

14840 /* Enable bit for MC signaling */

14841 UINT32 EnUncorrectableTcTagError : 1;

14842

14843 /* Bits[1:1], Access Type=RW, default=0x00000000*/

14844

14845 /* Enable bit for MC signaling */

14846 UINT32 EnUncorrectableSdtCorruptionError : 1;

14847

14848 /* Bits[2:2], Access Type=RW, default=0x00000000*/

14849

14850 /* Enable bit for MC signaling */

14851 UINT32 EnUncorrectableAddressRangeError : 1;

14852

14853 /* Bits[3:3], Access Type=RW, default=0x00000000*/

14854

14855 /* Enable bit for MC signaling */

14856 UINT32 EnCorrectableTcTagError : 1;

14857

14858 /* Bits[4:4], Access Type=RW, default=0x00000000*/

14859

14860 /* Enable bit for MC signaling */

14861 UINT32 Rsvd5 : 27;

14862

14863 /* Bits[31:5], Access Type=RO, default=None*/

14864

14865 /* Reserved */

14866 UINT32 Rsvd32 : 32;

14867

14868 /* Bits[63:32], Access Type=RO, default=None*/

14869

14870 /* Reserved */

14871

14872 } Bits;

14873

14874 UINT32 Uint32;

14875 UINT64 Uint64;

14876

14877 } MSR_MC23_CTL_REGISTER;

14878

14879 /**

14880 2LM MCA bank: Status register

14881 **/

14882 #define MSR_MC23_STATUS 0x0000045D

14883

14884 typedef union {

14885 ///

14886 /// Individual bit fields

14887 ///

14888 struct {

14889 UINT32 Mcacod : 16;

14890

14891 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

14892

14893 /* MCA error code */

14894 UINT32 Mscod : 16;

14895

14896 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

14897

14898 /* Model specific error code */

14899 UINT32 EnhMcaAvail0 : 6;

14900

14901 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

14902

14903 /*

14904 Available when Enhanced MCA is in use - unused

14905 in 2LMc

14906 */

14907 UINT32 CorrectedErrorCount : 15;

14908

14909 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

14910

14911 /* Correctable error count */

14912 UINT32 ThresholdBasedErrorStatus : 2;

14913

14914 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

14915

14916 /*

14917 These bits are used to indicate when the number

14918 of corrected errors has exceeded the safe

14919 threshold to the point where an uncorrected

14920 error has become more likely to happen.

14921 */

14922 UINT32 Ar : 2;

14923

14924 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

14925

14926 /*

14927 Available when Enhanced MCA is in use, unused in

14928 2LMc

14929 */

14930 UINT32 Pcc : 1;

14931

14932 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

14933

14934 /* PCC: Processor context corrupt */

14935 UINT32 Addrv : 1;

14936

14937 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

14938

14939 /*

14940 ADDRV: The address held in the MCi_ADDR_MSR is

14941 valid

14942 */

14943 UINT32 Miscv : 1;

14944

14945 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

14946

14947 /*

14948 MISCV: The value held in the MCi_MISC_MSR is

14949 valid

14950 */

14951 UINT32 En : 1;

14952

14953 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

14954

14955 /*

14956 EN: Error enabled flag Indicates (when set) that

14957 signaling of the machine check exception for

14958 this error was enabled by an associated flag bit

14959 of the Mci_CTL register.

14960 */

14961 UINT32 Uc : 1;

14962

14963 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

14964

14965 /*

14966 UC: Error uncorrected flag Indicates (when set)

14967 that the processor did not correct the error

14968 condition. When clear, this flag indicates that

14969 the processor was able to correct the error

14970 condition.

14971 */

14972 UINT32 Over : 1;

14973

14974 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

14975

14976 /* OVER: Machine check overflow */

14977 UINT32 Val : 1;

14978

14979 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

14980

14981 /*

14982 VAL: Valid flag Indicates (when set) that the

14983 information within the Mci_STATUS register is

14984 valid. When this flag is set, the processor

14985 follows the rules given for the OVER flag in the

14986 Mci_STATUS register when overwriting previously

14987 valid entries. The processor sets the VAL flag

14988 and software is responsible for clearing it.

14989 */

14990

14991 } Bits;

14992

14993 UINT32 Uint32;

14994 UINT64 Uint64;

14995

14996 } MSR_MC23_STATUS_REGISTER;

14997

14998 /**

14999 2LM MCA bank: Address register

15000 **/

15001 #define MSR_MC23_ADDR 0x0000045E

15002

15003 typedef union {

15004 ///

15005 /// Individual bit fields

15006 ///

15007 struct {

15008 UINT32 AddressOffset : 6;

15009

15010 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

15011

15012 /*

15013 Bits [5:0] of the Machine Check logged address.

15014 Enchanced MCA feature made this field writable

15015 */

15016 UINT32 Address0 : 26;

15017

15018 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

15019

15020 /* address of the logged error */

15021 UINT32 Address1 : 7;

15022

15023 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

15024

15025 /* address of the logged error */

15026 UINT32 EnhMcaAvail : 25;

15027

15028 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

15029

15030 /* Available when Enhanced MCA is in use */

15031

15032 } Bits;

15033

15034 UINT32 Uint32;

15035 UINT64 Uint64;

15036

15037 } MSR_MC23_ADDR_REGISTER;

15038

15039 /**

15040 2LM MCA bank: Miscellaneous register

15041 **/

15042 #define MSR_MC23_MISC 0x0000045F

15043

15044 typedef union {

15045 ///

15046 /// Individual bit fields

15047 ///

15048 struct {

15049 UINT32 ErrorAddress : 16;

15050

15051 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

15052

15053 /*

15054 This field contains the address of uncorrected

15055 error seen in the 2LMC/MLMc. It is updated on an

15056 uncorrectable error. To maintain e-MCA support

15057 this register must be writable.

15058 */

15059 UINT32 CorrectedErrorCount : 8;

15060

15061 /* Bits[23:16], Access Type=RWS_V, default=0x00000000*/

15062

15063 /* Corrected Error Count */

15064 UINT32 EnhMcaAvail0 : 8;

15065

15066 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

15067

15068 /* Available when enhanced MCA is in use */

15069 UINT32 EnhMcaAvail1 : 32;

15070

15071 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

15072

15073 /* Available when enhanced MCA is in use */

15074

15075 } Bits;

15076

15077 UINT32 Uint32;

15078 UINT64 Uint64;

15079

15080 } MSR_MC23_MISC_REGISTER;

15081

15082 /**

15083 2LM MCA bank: Control register

15084 **/

15085 #define MSR_MC24_CTL 0x00000460

15086

15087 typedef union {

15088 ///

15089 /// Individual bit fields

15090 ///

15091 struct {

15092 UINT32 EnUncorrectableTcMultipleTagMatchError : 1;

15093

15094 /* Bits[0:0], Access Type=RW, default=0x00000000*/

15095

15096 /* Enable bit for MC signaling */

15097 UINT32 EnUncorrectableTcTagError : 1;

15098

15099 /* Bits[1:1], Access Type=RW, default=0x00000000*/

15100

15101 /* Enable bit for MC signaling */

15102 UINT32 EnUncorrectableSdtCorruptionError : 1;

15103

15104 /* Bits[2:2], Access Type=RW, default=0x00000000*/

15105

15106 /* Enable bit for MC signaling */

15107 UINT32 EnUncorrectableAddressRangeError : 1;

15108

15109 /* Bits[3:3], Access Type=RW, default=0x00000000*/

15110

15111 /* Enable bit for MC signaling */

15112 UINT32 EnCorrectableTcTagError : 1;

15113

15114 /* Bits[4:4], Access Type=RW, default=0x00000000*/

15115

15116 /* Enable bit for MC signaling */

15117 UINT32 Rsvd5 : 27;

15118

15119 /* Bits[31:5], Access Type=RO, default=None*/

15120

15121 /* Reserved */

15122 UINT32 Rsvd32 : 32;

15123

15124 /* Bits[63:32], Access Type=RO, default=None*/

15125

15126 /* Reserved */

15127

15128 } Bits;

15129

15130 UINT32 Uint32;

15131 UINT64 Uint64;

15132

15133 } MSR_MC24_CTL_REGISTER;

15134

15135 /**

15136 2LM MCA bank: Status register

15137 **/

15138 #define MSR_MC24_STATUS 0x00000461

15139

15140 typedef union {

15141 ///

15142 /// Individual bit fields

15143 ///

15144 struct {

15145 UINT32 Mcacod : 16;

15146

15147 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

15148

15149 /* MCA error code */

15150 UINT32 Mscod : 16;

15151

15152 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

15153

15154 /* Model specific error code */

15155 UINT32 EnhMcaAvail0 : 6;

15156

15157 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

15158

15159 /*

15160 Available when Enhanced MCA is in use - unused

15161 in 2LMc

15162 */

15163 UINT32 CorrectedErrorCount : 15;

15164

15165 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

15166

15167 /* Correctable error count */

15168 UINT32 ThresholdBasedErrorStatus : 2;

15169

15170 /* Bits[54:53], Access Type=RWS_V, default=0x00000001*/

15171

15172 /*

15173 These bits are used to indicate when the number

15174 of corrected errors has exceeded the safe

15175 threshold to the point where an uncorrected

15176 error has become more likely to happen.

15177 */

15178 UINT32 Ar : 2;

15179

15180 /* Bits[56:55], Access Type=RWS_V, default=0x00000000*/

15181

15182 /*

15183 Available when Enhanced MCA is in use, unused in

15184 2LMc

15185 */

15186 UINT32 Pcc : 1;

15187

15188 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

15189

15190 /* PCC: Processor context corrupt */

15191 UINT32 Addrv : 1;

15192

15193 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

15194

15195 /*

15196 ADDRV: The address held in the MCi_ADDR_MSR is

15197 valid

15198 */

15199 UINT32 Miscv : 1;

15200

15201 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

15202

15203 /*

15204 MISCV: The value held in the MCi_MISC_MSR is

15205 valid

15206 */

15207 UINT32 En : 1;

15208

15209 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

15210

15211 /*

15212 EN: Error enabled flag Indicates (when set) that

15213 signaling of the machine check exception for

15214 this error was enabled by an associated flag bit

15215 of the Mci_CTL register.

15216 */

15217 UINT32 Uc : 1;

15218

15219 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

15220

15221 /*

15222 UC: Error uncorrected flag Indicates (when set)

15223 that the processor did not correct the error

15224 condition. When clear, this flag indicates that

15225 the processor was able to correct the error

15226 condition.

15227 */

15228 UINT32 Over : 1;

15229

15230 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

15231

15232 /* OVER: Machine check overflow */

15233 UINT32 Val : 1;

15234

15235 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

15236

15237 /*

15238 VAL: Valid flag Indicates (when set) that the

15239 information within the Mci_STATUS register is

15240 valid. When this flag is set, the processor

15241 follows the rules given for the OVER flag in the

15242 Mci_STATUS register when overwriting previously

15243 valid entries. The processor sets the VAL flag

15244 and software is responsible for clearing it.

15245 */

15246

15247 } Bits;

15248

15249 UINT32 Uint32;

15250 UINT64 Uint64;

15251

15252 } MSR_MC24_STATUS_REGISTER;

15253

15254 /**

15255 2LM MCA bank: Address register

15256 **/

15257 #define MSR_MC24_ADDR 0x00000462

15258

15259 typedef union {

15260 ///

15261 /// Individual bit fields

15262 ///

15263 struct {

15264 UINT32 AddressOffset : 6;

15265

15266 /* Bits[5:0], Access Type=RWS_V, default=0x00000000*/

15267

15268 /*

15269 Bits [5:0] of the Machine Check logged address.

15270 Enchanced MCA feature made this field writable

15271 */

15272 UINT32 Address0 : 26;

15273

15274 /* Bits[31:6], Access Type=RWS_V, default=0x00000000*/

15275

15276 /* address of the logged error */

15277 UINT32 Address1 : 7;

15278

15279 /* Bits[38:32], Access Type=RWS_V, default=0x00000000*/

15280

15281 /* address of the logged error */

15282 UINT32 EnhMcaAvail : 25;

15283

15284 /* Bits[63:39], Access Type=RWS_V, default=0x00000000*/

15285

15286 /* Available when Enhanced MCA is in use */

15287

15288 } Bits;

15289

15290 UINT32 Uint32;

15291 UINT64 Uint64;

15292

15293 } MSR_MC24_ADDR_REGISTER;

15294

15295 /**

15296 2LM MCA bank: Miscellaneous register

15297 **/

15298 #define MSR_MC24_MISC 0x00000463

15299

15300 typedef union {

15301 ///

15302 /// Individual bit fields

15303 ///

15304 struct {

15305 UINT32 ErrorAddress : 16;

15306

15307 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

15308

15309 /*

15310 This field contains the address of uncorrected

15311 error seen in the 2LMC/MLMc. It is updated on an

15312 uncorrectable error. To maintain e-MCA support

15313 this register must be writable.

15314 */

15315 UINT32 CorrectedErrorCount : 8;

15316

15317 /* Bits[23:16], Access Type=RWS_V, default=0x00000000*/

15318

15319 /* Corrected Error Count */

15320 UINT32 EnhMcaAvail0 : 8;

15321

15322 /* Bits[31:24], Access Type=RWS_V, default=0x00000000*/

15323

15324 /* Available when enhanced MCA is in use */

15325 UINT32 EnhMcaAvail1 : 32;

15326

15327 /* Bits[63:32], Access Type=RWS_V, default=0x00000000*/

15328

15329 /* Available when enhanced MCA is in use */

15330

15331 } Bits;

15332

15333 UINT32 Uint32;

15334 UINT64 Uint64;

15335

15336 } MSR_MC24_MISC_REGISTER;

15337 /**

15338 VMX Capability MSR. IA32_VMX_BASIC info.

15339 **/

15340 #define MSR_VMX_MSR_0 0x00000480

15341 /**

15342 VMX Capability MSR. allowed setting for PIN BASED VMCS execution control

15343 **/

15344 #define MSR_VMX_MSR_1 0x00000481

15345 /**

15346 VMX Capability MSR.allowed setting for Processor-based VM-execution controls

15347 **/

15348 #define MSR_VMX_MSR_2 0x00000482

15349 /**

15350 VMX Capability MSR.allowed setting for VMEXIT controls

15351 **/

15352 #define MSR_VMX_MSR_3 0x00000483

15353 /**

15354 VMX Capability MSR.allowed setting for VMENTRY controls

15355 **/

15356 #define MSR_VMX_MSR_4 0x00000484

15357 /**

15358 VMX Capability MSR.info on preemption timer, STM and more.

15359 **/

15360 #define MSR_VMX_MSR_5 0x00000485

15361 /**

15362 VMX Capability MSR.Allowed 0-settings for CR0 in VMX mode.

15363 **/

15364 #define MSR_VMX_MSR_6 0x00000486

15365 /**

15366 VMX Capability MSR.Allowed 1-settings for CR0 in VMX mode.

15367 **/

15368 #define MSR_VMX_MSR_7 0x00000487

15369 /**

15370 VMX Capability MSR.Allowed 0-settings for CR4 in VMX mode.

15371 **/

15372 #define MSR_VMX_MSR_8 0x00000488

15373 /**

15374 VMX Capability MSR.Allowed 1-settings for CR4 in VMX mode.

15375 **/

15376 #define MSR_VMX_MSR_9 0x00000489

15377 /**

15378 VMX Capability MSR.VMCS encoding info.

15379 **/

15380 #define MSR_VMX_MSR_10 0x0000048A

15381 /**

15382 VMX Capability MSR.allowed setting for SECONDARY PROCESSOR-BASED CTLS.

15383 **/

15384 #define MSR_VMX_MSR_11 0x0000048B

15385 /**

15386 VMX Capability MSR.EPT CAPABILITIES.

15387 **/

15388 #define MSR_VMX_MSR_12 0x0000048C

15389 /**

15390 VMX Capability MSR. allowed setting for PIN BASED VMCS execution control

15391 **/

15392 #define MSR_VMX_TRUE_PINBASED_CTLS 0x0000048D

15393 /**

15394 Capability Reporting Register of Primary Processor-based VM-execution Flex Controls

15395 **/

15396 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x0000048E

15397 /**

15398 Capability Reporting Register of VM-exit Flex Controls

15399 **/

15400 #define MSR_VMX_TRUE_EXIT_CTLS 0x0000048F

15401 /**

15402 Capability Reporting Register of VM-entry Flex Controls

15403 **/

15404 #define MSR_VMX_TRUE_ENTRY_CTLS 0x00000490

15405 /**

15406 VMX Capability MSR.

15407 **/

15408 #define MSR_VMX_VMFUNC_CTLS 0x00000491

15409 /**

15410 Allowed 1-settings of tertiary processor-based VM-execution controls.

15411 **/

15412 #define MSR_VMX_PROCBASED_CTLS3 0x00000492

15413

15414 /**

15415 Full Width Writable IA32_PMC0 Alias

15416 **/

15417 #define MSR_EMON_FULL_CTR0 0x000004C1

15418

15419 typedef union {

15420 ///

15421 /// Individual bit fields

15422 ///

15423 struct {

15424 UINT32 Rsvd0 : 32;

15425

15426 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15427

15428 /* Counter */

15429 UINT32 Rsvd32 : 16;

15430

15431 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15432

15433 /* Counter */

15434 UINT32 Rsvd48 : 16;

15435

15436 /* Bits[63:48], Access Type=RO, default=None*/

15437

15438 /* Reserved */

15439

15440 } Bits;

15441

15442 UINT32 Uint32;

15443 UINT64 Uint64;

15444

15445 } MSR_EMON_FULL_CTR0_REGISTER;

15446

15447 /**

15448 Full Width Writable IA32_PMC1 Alias

15449 **/

15450 #define MSR_EMON_FULL_CTR1 0x000004C2

15451

15452 typedef union {

15453 ///

15454 /// Individual bit fields

15455 ///

15456 struct {

15457 UINT32 Rsvd0 : 32;

15458

15459 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15460

15461 /* Counter */

15462 UINT32 Rsvd32 : 16;

15463

15464 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15465

15466 /* Counter */

15467 UINT32 Rsvd48 : 16;

15468

15469 /* Bits[63:48], Access Type=RO, default=None*/

15470

15471 /* Reserved */

15472

15473 } Bits;

15474

15475 UINT32 Uint32;

15476 UINT64 Uint64;

15477

15478 } MSR_EMON_FULL_CTR1_REGISTER;

15479

15480 /**

15481 Full Width Writable IA32_PMC2 Alias

15482 **/

15483 #define MSR_EMON_FULL_CTR2 0x000004C3

15484

15485 typedef union {

15486 ///

15487 /// Individual bit fields

15488 ///

15489 struct {

15490 UINT32 Rsvd0 : 32;

15491

15492 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15493

15494 /* Counter */

15495 UINT32 Rsvd32 : 16;

15496

15497 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15498

15499 /* Counter */

15500 UINT32 Rsvd48 : 16;

15501

15502 /* Bits[63:48], Access Type=RO, default=None*/

15503

15504 /* Reserved */

15505

15506 } Bits;

15507

15508 UINT32 Uint32;

15509 UINT64 Uint64;

15510

15511 } MSR_EMON_FULL_CTR2_REGISTER;

15512

15513 /**

15514 Full Width Writable IA32_PMC3 Alias

15515 **/

15516 #define MSR_EMON_FULL_CTR3 0x000004C4

15517

15518 typedef union {

15519 ///

15520 /// Individual bit fields

15521 ///

15522 struct {

15523 UINT32 Rsvd0 : 32;

15524

15525 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15526

15527 /* Counter */

15528 UINT32 Rsvd32 : 16;

15529

15530 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15531

15532 /* Counter */

15533 UINT32 Rsvd48 : 16;

15534

15535 /* Bits[63:48], Access Type=RO, default=None*/

15536

15537 /* Reserved */

15538

15539 } Bits;

15540

15541 UINT32 Uint32;

15542 UINT64 Uint64;

15543

15544 } MSR_EMON_FULL_CTR3_REGISTER;

15545

15546 /**

15547 Full Width Writable IA32_PMC4 Alias

15548 **/

15549 #define MSR_EMON_FULL_CTR4 0x000004C5

15550

15551 typedef union {

15552 ///

15553 /// Individual bit fields

15554 ///

15555 struct {

15556 UINT32 Rsvd0 : 32;

15557

15558 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15559

15560 /* Counter */

15561 UINT32 Rsvd32 : 16;

15562

15563 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15564

15565 /* Counter */

15566 UINT32 Rsvd48 : 16;

15567

15568 /* Bits[63:48], Access Type=RO, default=None*/

15569

15570 /* Reserved */

15571

15572 } Bits;

15573

15574 UINT32 Uint32;

15575 UINT64 Uint64;

15576

15577 } MSR_EMON_FULL_CTR4_REGISTER;

15578

15579 /**

15580 Full Width Writable IA32_PMC5 Alias

15581 **/

15582 #define MSR_EMON_FULL_CTR5 0x000004C6

15583

15584 typedef union {

15585 ///

15586 /// Individual bit fields

15587 ///

15588 struct {

15589 UINT32 Rsvd0 : 32;

15590

15591 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15592

15593 /* Counter */

15594 UINT32 Rsvd32 : 16;

15595

15596 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15597

15598 /* Counter */

15599 UINT32 Rsvd48 : 16;

15600

15601 /* Bits[63:48], Access Type=RO, default=None*/

15602

15603 /* Reserved */

15604

15605 } Bits;

15606

15607 UINT32 Uint32;

15608 UINT64 Uint64;

15609

15610 } MSR_EMON_FULL_CTR5_REGISTER;

15611

15612 /**

15613 Full Width Writable IA32_PMC6 Alias

15614 **/

15615 #define MSR_EMON_FULL_CTR6 0x000004C7

15616

15617 typedef union {

15618 ///

15619 /// Individual bit fields

15620 ///

15621 struct {

15622 UINT32 Rsvd0 : 32;

15623

15624 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15625

15626 /* Counter */

15627 UINT32 Rsvd32 : 16;

15628

15629 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15630

15631 /* Counter */

15632 UINT32 Rsvd48 : 16;

15633

15634 /* Bits[63:48], Access Type=RO, default=None*/

15635

15636 /* Reserved */

15637

15638 } Bits;

15639

15640 UINT32 Uint32;

15641 UINT64 Uint64;

15642

15643 } MSR_EMON_FULL_CTR6_REGISTER;

15644

15645 /**

15646 Full Width Writable IA32_PMC7 Alias

15647 **/

15648 #define MSR_EMON_FULL_CTR7 0x000004C8

15649

15650 typedef union {

15651 ///

15652 /// Individual bit fields

15653 ///

15654 struct {

15655 UINT32 Rsvd0 : 32;

15656

15657 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15658

15659 /* Counter */

15660 UINT32 Rsvd32 : 16;

15661

15662 /* Bits[47:32], Access Type=RW, default=0x00000000*/

15663

15664 /* Counter */

15665 UINT32 Rsvd48 : 16;

15666

15667 /* Bits[63:48], Access Type=RO, default=None*/

15668

15669 /* Reserved */

15670

15671 } Bits;

15672

15673 UINT32 Uint32;

15674 UINT64 Uint64;

15675

15676 } MSR_EMON_FULL_CTR7_REGISTER;

15677

15678 /**

15679 Pointer to current RTIT Table of Physical Addresses (ToPA)

15680 **/

15681 #define MSR_RTIT_OUTPUT_BASE 0x00000560

15682

15683 typedef union {

15684 ///

15685 /// Individual bit fields

15686 ///

15687 struct {

15688 UINT32 Rsvd0 : 7;

15689

15690 /* Bits[6:0], Access Type=RO, default=None*/

15691

15692 /* Reserved */

15693 UINT32 BasePhysAddrLsb : 5;

15694

15695 /* Bits[11:7], Access Type=RW, default=None*/

15696

15697 /*

15698 RTIT output base physical address (low bits).

15699 How this address is used depends on the value of

15700 IA32_RTIT_CTL.ToPA: 0: This is the LSB of base

15701 physical address of a single, contiguous

15702 physical output region. This could be mapped to

15703 DRAM or to MMIO, depending on the value. 1: In

15704 ToPA mode this field is reserved - ERROR is not

15705 aligned to 4KB

15706 */

15707 UINT32 BasePhysAddrMsb0 : 20;

15708

15709 /* Bits[31:12], Access Type=RW, default=None*/

15710

15711 /*

15712 RTIT output base physical address (high bits).

15713 How this address is used depends on the value of

15714 IA32_RTIT_CTL.ToPA: 0: This is the MSB of base

15715 physical address of a single, contiguous

15716 physical output region. This could be mapped to

15717 DRAM or to MMIO, depending on the value. 1: This

15718 is the MSB of base physical address of the first

15719 ToPA table. In this case, the address must be 4K

15720 aligned, and thus bits 11:7 checked for ERROR

15721 */

15722 UINT32 BasePhysAddrMsb1 : 20;

15723

15724 /* Bits[51:32], Access Type=RW, default=None*/

15725

15726 /*

15727 RTIT output base physical address (high bits).

15728 How this address is used depends on the value of

15729 IA32_RTIT_CTL.ToPA: 0: This is the MSB of base

15730 physical address of a single, contiguous

15731 physical output region. This could be mapped to

15732 DRAM or to MMIO, depending on the value. 1: This

15733 is the MSB of base physical address of the first

15734 ToPA table. In this case, the address must be 4K

15735 aligned, and thus bits 11:7 checked for ERROR

15736 */

15737 UINT32 Rsvd52 : 12;

15738

15739 /* Bits[63:52], Access Type=RO, default=None*/

15740

15741 /* Reserved */

15742

15743 } Bits;

15744

15745 UINT32 Uint32;

15746 UINT64 Uint64;

15747

15748 } MSR_RTIT_OUTPUT_BASE_REGISTER;

15749

15750 /**

15751 Holds pointers to the current output region (page) in the current ToPA

15752 **/

15753 #define MSR_RTIT_OUTPUT_MASK_PTRS 0x00000561

15754

15755 typedef union {

15756 ///

15757 /// Individual bit fields

15758 ///

15759 struct {

15760 UINT32 Lower : 7;

15761

15762 /* Bits[6:0], Access Type=RW, default=None*/

15763

15764 /*

15765 Reserved - always '1 to enable using this MSR as

15766 a mask

15767 */

15768 UINT32 MaskTableOffset : 25;

15769

15770 /* Bits[31:7], Access Type=RW, default=None*/

15771

15772 /*

15773 [27:3] - Index into the current RTIT Table entry

15774 (8B granularity)

15775 */

15776 UINT32 OutputOffset : 32;

15777

15778 /* Bits[63:32], Access Type=RW, default=None*/

15779

15780 /*

15781 [31:0] - Index into the current RTIT output

15782 region (1B granularity)

15783 */

15784

15785 } Bits;

15786

15787 UINT32 Uint32;

15788 UINT64 Uint64;

15789

15790 } MSR_RTIT_OUTPUT_MASK_PTRS_REGISTER;

15791

15792 /**

15793 RTIT Control MSR

15794 **/

15795 #define MSR_RTIT_CTL 0x00000570

15796

15797 typedef union {

15798 ///

15799 /// Individual bit fields

15800 ///

15801 struct {

15802 UINT32 TraceEn : 1;

15803

15804 /* Bits[0:0], Access Type=RW, default=0x00000000*/

15805

15806 /* Enable RTIT Trace on thread */

15807 UINT32 CycEn : 1;

15808

15809 /* Bits[1:1], Access Type=RW, default=None*/

15810

15811 /* Enable Cycle Pkt */

15812 UINT32 Os : 1;

15813

15814 /* Bits[2:2], Access Type=RW, default=None*/

15815

15816 /*

15817 When set, only branches in ring 0 (OS mode) will

15818 get tracked for RTIT. When both CPL_EQ_0 and

15819 CPL_NEQ_0 bits are set, all branches will get

15820 tracked for RTIT.

15821 */

15822 UINT32 Usr : 1;

15823

15824 /* Bits[3:3], Access Type=RW, default=None*/

15825

15826 /*

15827 When set, only branches in non-ring 0 (User

15828 mode) will get tracked for RTIT. When both

15829 CPL_EQ_0 and CPL_NEQ_0 bits are set, all

15830 branches will get tracked for RTIT.

15831 */

15832 UINT32 Rsvd4 : 3;

15833

15834 /* Bits[6:4], Access Type=RO, default=None*/

15835

15836 /* Reserved */

15837 UINT32 Cr3FilterEn : 1;

15838

15839 /* Bits[7:7], Access Type=RW, default=None*/

15840

15841 /*

15842 Enable CR3 filtering, such that tracing is

15843 enabled only if CR3 matches the value in

15844 IA32_RTIT_CR3

15845 */

15846 UINT32 TopaEn : 1;

15847

15848 /* Bits[8:8], Access Type=RW, default=None*/

15849

15850 /*

15851 When set causes the RTIT output to be in memory

15852 via ToPA, else to a single address range

15853 */

15854 UINT32 MtcEn : 1;

15855

15856 /* Bits[9:9], Access Type=RW, default=None*/

15857

15858 /* Enable mini time stamp counter */

15859 UINT32 TscEn : 1;

15860

15861 /* Bits[10:10], Access Type=RW, default=None*/

15862

15863 /*

15864 Enable TSC packets, on RTIT enable as well as on

15865 bus ratio changes (with CBR). Implies that CBR

15866 is also enabled.

15867 */

15868 UINT32 DisableRetComp : 1;

15869

15870 /* Bits[11:11], Access Type=RW, default=None*/

15871

15872 /* When set, RETURN compression will be disabled */

15873 UINT32 Rsvd12 : 1;

15874

15875 /* Bits[12:12], Access Type=RO, default=None*/

15876

15877 /* Reserved */

15878 UINT32 BranchEn : 1;

15879

15880 /* Bits[13:13], Access Type=RW, default=None*/

15881

15882 /*

15883 0: Disable COFI-based packets; 1: Enable COFI-

15884 based packets (FUP, TIP, TNT, PIP, CSB);

15885 */

15886 UINT32 MtcFreq : 4;

15887

15888 /* Bits[17:14], Access Type=RW, default=None*/

15889

15890 /*

15891 Defines MTC Frequency, which is based on the HW

15892 Crystal Clock (CTC). MTC will be sent each time

15893 the selected CTC bit toggles. Encodings: 0:

15894 CTC[0] 4: CTC[4] 8: CTC[8] 12: CTC[12] 1: CTC[1]

15895 5: CTC[5] 9: CTC[9] 13: CTC[13] 2: CTC[2] 6:

15896 CTC[6] 10: CTC[10] 14: CTC[14] 3: CTC[3] 7:

15897 CTC[7] 11: CTC[11] 15: CTC[15]

15898 */

15899 UINT32 Rsvd18 : 1;

15900

15901 /* Bits[18:18], Access Type=RO, default=None*/

15902

15903 /* Reserved */

15904 UINT32 CycThresh : 4;

15905

15906 /* Bits[22:19], Access Type=RW, default=None*/

15907

15908 /*

15909 CYC packet threshold, see 4.53.4 for details.

15910 CYC packets will be sent with the first eligible

15911 packet after N cycles have passed since the last

15912 CYC packet. If CycThresh is 0 then N=0,

15913 otherwise N is defined as 2(CycThresh-1).

15914 Encodings: 0: 0 4: 8 8: 128 12: 2048 1: 1 5: 16

15915 9: 256 13: 4096 2: 2 6: 32 10: 512 14: 8192 3: 4

15916 7: 64 11: 1024 15: 16384

15917 */

15918 UINT32 Rsvd23 : 1;

15919

15920 /* Bits[23:23], Access Type=RO, default=None*/

15921

15922 /* Reserved */

15923 UINT32 PsbFreq : 4;

15924

15925 /* Bits[27:24], Access Type=RW, default=None*/

15926

15927 /*

15928 Indicates the frequency of PSB packets. PSB

15929 packet frequency is based on the number of RTIT

15930 packet bytes output, so this field allows the

15931 user to determine the increment of

15932 IA32_IA32_RTIT_STATUS. PacketByteCnt that should

15933 cause a PSB to be generated. Note that PSB

15934 insertion is not precise, but the average output

15935 bytes per PSB should approximate the SW selected

15936 period. The average PSB period, in RTIT output

15937 bytes, can be expressed as 2(PSBFreq+11).

15938 Encodings: 0: 2K 4: 32K 8: 512K 12: 8M 1: 4K 5:

15939 64K 9: 1M 13: 16M 2: 8K 6: 128K 10: 2M 14: 32M

15940 3: 16K 7: 256K 11: 4M 15: 64M

15941 */

15942 UINT32 Rsvd28 : 4;

15943

15944 /* Bits[31:28], Access Type=RO, default=None*/

15945

15946 /* Reserved */

15947 UINT32 Addr0Cfg : 4;

15948

15949 /* Bits[35:32], Access Type=RW, default=None*/

15950

15951 /*

15952 0x0 No address filtering 0x1 Enable tracing when

15953 IP in [A..B] range 0x2 Stop tracing when IP in

15954 [A..B] range 0x3..0xf Reserved

15955 */

15956 UINT32 Addr1Cfg : 4;

15957

15958 /* Bits[39:36], Access Type=RW, default=None*/

15959

15960 /*

15961 0x0 No address filtering 0x1 Enable tracing when

15962 IP in [A..B] range 0x2 Stop tracing when IP in

15963 [A..B] range 0x3..0xf Reserved

15964 */

15965 UINT32 Rsvd40 : 16;

15966

15967 /* Bits[55:40], Access Type=RO, default=None*/

15968

15969 /* Reserved */

15970 UINT32 InjectPsbPmiOnEnable : 1;

15971

15972 /* Bits[56:56], Access Type=RW, default=None*/

15973

15974 /*

15975 Enable preservation of PMI/PSB over

15976 xsaves/xrstors. Note: #GP on SNC. May be enabled

15977 by patch later. See ticket 1405267396

15978 */

15979 UINT32 Rsvd57 : 7;

15980

15981 /* Bits[63:57], Access Type=RO, default=None*/

15982

15983 /* Reserved */

15984

15985 } Bits;

15986

15987 UINT32 Uint32;

15988 UINT64 Uint64;

15989

15990 } MSR_RTIT_CTL_REGISTER;

15991

15992 /**

15993 RTIT status MSR

15994 **/

15995 #define MSR_RTIT_STATUS 0x00000571

15996

15997 typedef union {

15998 ///

15999 /// Individual bit fields

16000 ///

16001 struct {

16002 UINT32 FilterEn : 1;

16003

16004 /* Bits[0:0], Access Type=RW_V, default=None*/

16005

16006 /*

16007 Indicates that the LIP is within the filter

16008 region. In SKL it compares the current EIP to

16009 the EIP calculated when the LIP value was

16010 programmed in IA32_RTIT_LIP0/2. FILTER_EN is not

16011 writeable, but is re-evaluated by HW on TRACE

16012 enabling

16013 */

16014 UINT32 ContextEn : 1;

16015

16016 /* Bits[1:1], Access Type=RW_V, default=None*/

16017

16018 /*

16019 Indicates that the processor is within a

16020 traceable context (USR mode, OS mode, VMX mode,

16021 SMM mode, SE etc)

16022 */

16023 UINT32 TriggerEn : 1;

16024

16025 /* Bits[2:2], Access Type=RO_V, default=None*/

16026

16027 /*

16028 Indicates that RTIT Tracing is enabled

16029 (IA32_RTIT_CTL bits TRACE_EN and TRACE_ACTIVE

16030 are set)

16031 */

16032 UINT32 Rsvd3 : 1;

16033

16034 /* Bits[3:3], Access Type=RO, default=None*/

16035

16036 /* Reserved */

16037 UINT32 Error : 1;

16038

16039 /* Bits[4:4], Access Type=RW_V, default=None*/

16040

16041 /*

16042 Indicates that RTIT has hit an Error, such as

16043 ToPA accessing a protected memory range

16044 */

16045 UINT32 Stopped : 1;

16046

16047 /* Bits[5:5], Access Type=RW_V, default=None*/

16048

16049 /*

16050 Indicates that RTIT Tracing Stopped when

16051 branching into either a REGION_TRACE_STOP or a

16052 TOPA_STOP

16053 */

16054 UINT32 PendPsb : 1;

16055

16056 /* Bits[6:6], Access Type=RW_V, default=None*/

16057

16058 /*

16059 Indicates that ucode/sw has pending PSB that

16060 hasn't yet handled. Note: #GP on SNC. May be

16061 enabled by patch later. See ticket 1405267396

16062 */

16063 UINT32 PendTopaPmi : 1;

16064

16065 /* Bits[7:7], Access Type=RW_V, default=None*/

16066

16067 /*

16068 Indicates that ucode/sw has pending PMI that

16069 hasn't yet handled. Note: #GP on SNC. May be

16070 enabled by patch later. See ticket 1405267396

16071 */

16072 UINT32 Rsvd8 : 24;

16073

16074 /* Bits[31:8], Access Type=RO, default=None*/

16075

16076 /* Reserved */

16077 UINT32 PacketByteCount : 17;

16078

16079 /* Bits[48:32], Access Type=RW_V, default=None*/

16080

16081 /*

16082 Indicates how many Bytes have been traced so

16083 far. This field is not cleared on TRACE_EN:=0.

16084 Granularity of this counter in SKL is 8 Bytes.

16085 Lower 3bits can change only if written by the

16086 user as non-zeros

16087 */

16088 UINT32 Rsvd49 : 15;

16089

16090 /* Bits[63:49], Access Type=RO, default=None*/

16091

16092 /* Reserved */

16093

16094 } Bits;

16095

16096 UINT32 Uint32;

16097 UINT64 Uint64;

16098

16099 } MSR_RTIT_STATUS_REGISTER;

16100

16101 /**

16102 CR3 value used for RTIT filtering

16103 **/

16104 #define MSR_RTIT_CR3_MATCH 0x00000572

16105

16106 typedef union {

16107 ///

16108 /// Individual bit fields

16109 ///

16110 struct {

16111 UINT32 Rsvd0 : 5;

16112

16113 /* Bits[4:0], Access Type=RO, default=None*/

16114

16115 /* Reserved */

16116 UINT32 FilterValue0 : 27;

16117

16118 /* Bits[31:5], Access Type=RW, default=None*/

16119

16120 /*

16121 Bits [63:5] to be compared against next updated

16122 CR3 physical address. The unsupported MSBs, e.g.

16123 [63:46] should be programmed to '0, else there

16124 will not be a match.

16125 */

16126 UINT32 FilterValue1 : 32;

16127

16128 /* Bits[63:32], Access Type=RW, default=None*/

16129

16130 /*

16131 Bits [63:5] to be compared against next updated

16132 CR3 physical address. The unsupported MSBs, e.g.

16133 [63:46] should be programmed to '0, else there

16134 will not be a match.

16135 */

16136

16137 } Bits;

16138

16139 UINT32 Uint32;

16140 UINT64 Uint64;

16141

16142 } MSR_RTIT_CR3_MATCH_REGISTER;

16143

16144 /**

16145 MSR used to support EIP filtering

16146 **/

16147 #define MSR_RTIT_ADDR0_A 0x00000580

16148

16149 typedef union {

16150 ///

16151 /// Individual bit fields

16152 ///

16153 struct {

16154 UINT32 Addr0 : 32;

16155

16156 /* Bits[31:0], Access Type=RW, default=None*/

16157

16158 /*

16159 Low end of LIP filter ADDR0. SKL transfers the

16160 EIP to ROB

16161 */

16162 UINT32 Addr1 : 25;

16163

16164 /* Bits[56:32], Access Type=RW, default=None*/

16165

16166 /*

16167 Low end of LIP filter ADDR0. SKL transfers the

16168 EIP to ROB

16169 */

16170 UINT32 Rsvd57 : 7;

16171

16172 /* Bits[63:57], Access Type=RO, default=None*/

16173

16174 /* Reserved */

16175

16176 } Bits;

16177

16178 UINT32 Uint32;

16179 UINT64 Uint64;

16180

16181 } MSR_RTIT_ADDR0_A_REGISTER;

16182

16183 /**

16184 MSR used to support EIP filtering

16185 **/

16186 #define MSR_RTIT_ADDR0_B 0x00000581

16187

16188 typedef union {

16189 ///

16190 /// Individual bit fields

16191 ///

16192 struct {

16193 UINT32 Addr0 : 32;

16194

16195 /* Bits[31:0], Access Type=RW, default=None*/

16196

16197 /*

16198 High end of LIP filter ADDR0. SKL transfers the

16199 EIP to ROB

16200 */

16201 UINT32 Addr1 : 25;

16202

16203 /* Bits[56:32], Access Type=RW, default=None*/

16204

16205 /*

16206 High end of LIP filter ADDR0. SKL transfers the

16207 EIP to ROB

16208 */

16209 UINT32 Rsvd57 : 7;

16210

16211 /* Bits[63:57], Access Type=RO, default=None*/

16212

16213 /* Reserved */

16214

16215 } Bits;

16216

16217 UINT32 Uint32;

16218 UINT64 Uint64;

16219

16220 } MSR_RTIT_ADDR0_B_REGISTER;

16221

16222 /**

16223 MSR used to support EIP filtering

16224 **/

16225 #define MSR_RTIT_ADDR1_A 0x00000582

16226

16227 typedef union {

16228 ///

16229 /// Individual bit fields

16230 ///

16231 struct {

16232 UINT32 Addr0 : 32;

16233

16234 /* Bits[31:0], Access Type=RW, default=None*/

16235

16236 /*

16237 Low end of LIP filter ADDR1. SKL transfers the

16238 EIP to ROB

16239 */

16240 UINT32 Addr1 : 25;

16241

16242 /* Bits[56:32], Access Type=RW, default=None*/

16243

16244 /*

16245 Low end of LIP filter ADDR1. SKL transfers the

16246 EIP to ROB

16247 */

16248 UINT32 Rsvd57 : 7;

16249

16250 /* Bits[63:57], Access Type=RO, default=None*/

16251

16252 /* Reserved */

16253

16254 } Bits;

16255

16256 UINT32 Uint32;

16257 UINT64 Uint64;

16258

16259 } MSR_RTIT_ADDR1_A_REGISTER;

16260

16261 /**

16262 MSR used to support EIP filtering

16263 **/

16264 #define MSR_RTIT_ADDR1_B 0x00000583

16265

16266 typedef union {

16267 ///

16268 /// Individual bit fields

16269 ///

16270 struct {

16271 UINT32 Addr0 : 32;

16272

16273 /* Bits[31:0], Access Type=RW, default=None*/

16274

16275 /*

16276 High end of LIP filter ADDR1. SKL transfers the

16277 EIP to ROB

16278 */

16279 UINT32 Addr1 : 25;

16280

16281 /* Bits[56:32], Access Type=RW, default=None*/

16282

16283 /*

16284 High end of LIP filter ADDR1. SKL transfers the

16285 EIP to ROB

16286 */

16287 UINT32 Rsvd57 : 7;

16288

16289 /* Bits[63:57], Access Type=RO, default=None*/

16290

16291 /* Reserved */

16292

16293 } Bits;

16294

16295 UINT32 Uint32;

16296 UINT64 Uint64;

16297

16298 } MSR_RTIT_ADDR1_B_REGISTER;

16299 /**

16300 Points to the linear address of the first byte of the DS buffer management area, which is used to manage the BTS and PEBS buffers.

16301 **/

16302 #define MSR_DS_AREA 0x00000600

16303 /**

16304 productivity cycles counter (HWP)

16305 **/

16306 #define MSR_MLC_PCNT_COUNTER 0x0000064E

16307

16308 /**

16309 Fast wrmsr/rdmsr control MSR. Each bit refers to one MSR and indicate if this MSR

16310 is set to use the FAST_UNCORE_MSRS mode. Currently , bit 0 refers to IA32_HWP_REQUEST , while bit 1 refers to THREAD_INFO MSR

16311 **/

16312 #define MSR_FAST_UNCORE_MSRS_CTL 0x00000657

16313

16314 typedef union {

16315 ///

16316 /// Individual bit fields

16317 ///

16318 struct {

16319 UINT32 FastAccessEnable : 4;

16320

16321 /* Bits[3:0], Access Type=RW, default=0x00000000*/

16322

16323 /* indicates, for each msr, if we're in fast_mode */

16324 UINT32 Rsvd4 : 28;

16325

16326 /* Bits[31:4], Access Type=RW, default=0x00000000*/

16327

16328 /* Reserved */

16329

16330 } Bits;

16331

16332 UINT32 Uint32;

16333 UINT64 Uint64;

16334

16335 } MSR_FAST_UNCORE_MSRS_CTL_REGISTER;

16336

16337 /**

16338 CET user configuration MSR

16339 **/

16340 #define MSR_U_CET 0x000006A0

16341

16342 typedef union {

16343 ///

16344 /// Individual bit fields

16345 ///

16346 struct {

16347 UINT32 ShStkEn : 1;

16348

16349 /* Bits[0:0], Access Type=RW, default=0x00000000*/

16350

16351 /* Enable shadow stacks */

16352 UINT32 WrShstkEn : 1;

16353

16354 /* Bits[1:1], Access Type=RW, default=0x00000000*/

16355

16356 /* Enable WRSS instruction */

16357 UINT32 EndbrEn : 1;

16358

16359 /* Bits[2:2], Access Type=RW, default=0x00000000*/

16360

16361 /* Enable indirect call/jmp tracking */

16362 UINT32 LegiwEn : 1;

16363

16364 /* Bits[3:3], Access Type=RW, default=0x00000000*/

16365

16366 /*

16367 Enable legacy interworking for indirect

16368 calls/jumps tracking

16369 */

16370 UINT32 NoTrackEn : 1;

16371

16372 /* Bits[4:4], Access Type=RW, default=0x00000000*/

16373

16374 /*

16375 Enables use of 3E byte as "no-track" prefix for

16376 indirect calls and jumps

16377 */

16378 UINT32 SuppressDis : 1;

16379

16380 /* Bits[5:5], Access Type=RW, default=0x00000000*/

16381

16382 /*

16383 disables suppression of CET indirect branch

16384 tracking on legacy interwork (each violation

16385 requires re-check via bitmap)

16386 */

16387 UINT32 Rsvd6 : 4;

16388

16389 /* Bits[9:6], Access Type=RW, default=0x00000000*/

16390

16391 /* reserved */

16392 UINT32 Suppress : 1;

16393

16394 /* Bits[10:10], Access Type=RW_V, default=0x00000000*/

16395

16396 /* Suppresses state of ENDBRANCH tracker4 */

16397 UINT32 Tracker : 1;

16398

16399 /* Bits[11:11], Access Type=RW_V, default=0x00000000*/

16400

16401 /*

16402 State of ENDBRANCH tracker [0: idle, 1: wait for

16403 endbranch]

16404 */

16405 UINT32 EbLegBitmapBase0 : 20;

16406

16407 /* Bits[31:12], Access Type=RW, default=0x00000000*/

16408

16409 /* Linear address of bitmap of legacy code pages */

16410 UINT32 EbLegBitmapBase1 : 32;

16411

16412 /* Bits[63:32], Access Type=RW, default=0x00000000*/

16413

16414 /* Linear address of bitmap of legacy code pages */

16415

16416 } Bits;

16417

16418 UINT32 Uint32;

16419 UINT64 Uint64;

16420

16421 } MSR_U_CET_REGISTER;

16422

16423 /**

16424 CET supervisor configuration MSR

16425 **/

16426 #define MSR_S_CET 0x000006A2

16427

16428 typedef union {

16429 ///

16430 /// Individual bit fields

16431 ///

16432 struct {

16433 UINT32 ShStkEn : 1;

16434

16435 /* Bits[0:0], Access Type=RW, default=0x00000000*/

16436

16437 /* Enable shadow stacks */

16438 UINT32 WrShstkEn : 1;

16439

16440 /* Bits[1:1], Access Type=RW, default=0x00000000*/

16441

16442 /* Enable WRSS instruction */

16443 UINT32 EndbrEn : 1;

16444

16445 /* Bits[2:2], Access Type=RW, default=0x00000000*/

16446

16447 /* Enable indirect call/jmp tracking */

16448 UINT32 LegiwEn : 1;

16449

16450 /* Bits[3:3], Access Type=RW, default=0x00000000*/

16451

16452 /*

16453 Enable legacy interworking for indirect

16454 calls/jumps tracking

16455 */

16456 UINT32 NoTrackEn : 1;

16457

16458 /* Bits[4:4], Access Type=RW, default=0x00000000*/

16459

16460 /*

16461 Enables use of 3E byte as "no-track" prefix for

16462 indirect calls and jumps

16463 */

16464 UINT32 SuppressDis : 1;

16465

16466 /* Bits[5:5], Access Type=RW, default=0x00000000*/

16467

16468 /*

16469 disables suppression of CET indirect branch

16470 tracking on legacy interwork (each violation

16471 requires re-check via bitmap)

16472 */

16473 UINT32 Rsvd6 : 4;

16474

16475 /* Bits[9:6], Access Type=RW, default=0x00000000*/

16476

16477 /* reserved */

16478 UINT32 Suppress : 1;

16479

16480 /* Bits[10:10], Access Type=RW_V, default=0x00000000*/

16481

16482 /* Suppresses state of ENDBRANCH tracker4 */

16483 UINT32 Tracker : 1;

16484

16485 /* Bits[11:11], Access Type=RW_V, default=0x00000000*/

16486

16487 /*

16488 State of ENDBRANCH tracker [0: idle, 1: wait for

16489 endbranch]

16490 */

16491 UINT32 EbLegBitmapBase0 : 20;

16492

16493 /* Bits[31:12], Access Type=RW, default=0x00000000*/

16494

16495 /* Linear address of bitmap of legacy code pages */

16496 UINT32 EbLegBitmapBase1 : 32;

16497

16498 /* Bits[63:32], Access Type=RW, default=0x00000000*/

16499

16500 /* Linear address of bitmap of legacy code pages */

16501

16502 } Bits;

16503

16504 UINT32 Uint32;

16505 UINT64 Uint64;

16506

16507 } MSR_S_CET_REGISTER;

16508 /**

16509 CET register to hold CPL0s shadow stack pointer on transition to CPL3

16510 **/

16511 #define MSR_PL0_SSP 0x000006A4

16512 /**

16513 CET register to hold CPL1s shadow stack pointer on transition to CPL3

16514 **/

16515 #define MSR_PL1_SSP 0x000006A5

16516 /**

16517 CET register to hold CPL2s shadow stack pointer on transition to CPL3

16518 **/

16519 #define MSR_PL2_SSP 0x000006A6

16520 /**

16521 CET register to hold CPL3s shadow stack pointer on transition to CPL &lt; 3

16522 **/

16523 #define MSR_PL3_SSP 0x000006A7

16524 /**

16525 linear address of the table of pointers to shadow stacks to be switched to when initiating a stack switch in 64 bit mode through IST mechanism. Must be machine canonical when written in 64 bit mode. On parts that do not support 64 bit mode, this MSR is not present.

16526 **/

16527 #define MSR_INTERRUPT_SSP_TABLE 0x000006A8

16528

16529 /**

16530 Interface to allow software to determine what is causing resolved frequency to be clamped

16531 below the requested frequency. Status bits are updated by pcode through the io interface IO_GT_PERF_LIMIT,

16532 log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

16533 **/

16534 #define MSR_GT_PERF_LIMIT_REASONS 0x000006B0

16535

16536 typedef union {

16537 ///

16538 /// Individual bit fields

16539 ///

16540 struct {

16541 UINT32 Prochot : 1;

16542

16543 /* Bits[0:0], Access Type=RO, default=0x00000000*/

16544

16545 /*

16546 PROCHOT# Status, RO, When set by PCODE indicates

16547 that PROCHOT# has cause GT frequency clipping

16548 */

16549 UINT32 Thermal : 1;

16550

16551 /* Bits[1:1], Access Type=RO, default=0x00000000*/

16552

16553 /*

16554 Thermal Status, RO, When set by PCODE indicates

16555 that Thermal event has cause GT frequency

16556 clipping

16557 */

16558 UINT32 SpareGt2 : 1;

16559

16560 /* Bits[2:2], Access Type=RO, default=0x00000000*/

16561

16562 /* Reserved */

16563 UINT32 SpareGt3 : 1;

16564

16565 /* Bits[3:3], Access Type=RO, default=0x00000000*/

16566

16567 /* Reserved */

16568 UINT32 RsrLimit : 1;

16569

16570 /* Bits[4:4], Access Type=RO, default=0x00000000*/

16571

16572 /* Reserved */

16573 UINT32 Ratl : 1;

16574

16575 /* Bits[5:5], Access Type=RO, default=0x00000000*/

16576

16577 /*

16578 Running average thermal limit Status, R0, When

16579 set by PCODE indicates that Running average

16580 thermal limit has cause GT frequency clipping

16581 */

16582 UINT32 VrThermalert : 1;

16583

16584 /* Bits[6:6], Access Type=RO, default=0x00000000*/

16585

16586 /*

16587 Hot VR (any processor VR) Status, RO, When set

16588 by PCODE indicates that Hot VR (any processor

16589 VR) has cause GT frequency clipping

16590 */

16591 UINT32 VrTdc : 1;

16592

16593 /* Bits[7:7], Access Type=RO, default=0x00000000*/

16594

16595 /*

16596 VR TDC (Thermal design current) Status, RO, When

16597 set by PCODE indicates that VR TDC (Thermal

16598 design current has cause GT frequency clipping

16599 */

16600 UINT32 Other : 1;

16601

16602 /* Bits[8:8], Access Type=RO, default=0x00000000*/

16603

16604 /*

16605 Other (IccMax, PL4, etc) Status, RO, When set by

16606 PCODE indicates that other has cause reason GT

16607 frequency clipping

16608 */

16609 UINT32 SpareGt9 : 1;

16610

16611 /* Bits[9:9], Access Type=RO, default=0x00000000*/

16612

16613 /* Reserved */

16614 UINT32 PbmPl1 : 1;

16615

16616 /* Bits[10:10], Access Type=RO, default=0x00000000*/

16617

16618 /*

16619 PBM PL1 (pkg, platform), RO, When set by PCODE

16620 indicates that PBM PL1 (package or platform PL1)

16621 has cause GT frequency clipping

16622 */

16623 UINT32 PbmPl2 : 1;

16624

16625 /* Bits[11:11], Access Type=RO, default=0x00000000*/

16626

16627 /*

16628 PBM PL2, PL3 (pkg, platform) Status, RO, When

16629 set by PCODE indicates that PBM PL2 or

16630 PL3(package or platform PL2 or PL3) has cause GT

16631 frequency clipping

16632 */

16633 UINT32 InefficientOperation : 1;

16634

16635 /* Bits[12:12], Access Type=RO, default=0x00000000*/

16636

16637 /*

16638 Inefficient operation Status, RO, The current GT

16639 Frequency lower than the DCC target Frequency

16640 */

16641 UINT32 SpareGt13 : 1;

16642

16643 /* Bits[13:13], Access Type=RO, default=0x00000000*/

16644

16645 /* Reserved */

16646 UINT32 SpareGt14 : 1;

16647

16648 /* Bits[14:14], Access Type=RO, default=0x00000000*/

16649

16650 /* Reserved */

16651 UINT32 SpareGt15 : 1;

16652

16653 /* Bits[15:15], Access Type=RO, default=0x00000000*/

16654

16655 /* Reserved */

16656 UINT32 ProchotLog : 1;

16657

16658 /* Bits[16:16], Access Type=RW0C_FW, default=0x00000000*/

16659

16660 /*

16661 PROCHOT# Log, RW, When set by PCODE indicates

16662 that PROCHOT# has cause GT frequency clipping.

16663 Software should write to this bit to clear the

16664 status in this bit

16665 */

16666 UINT32 ThermalLog : 1;

16667

16668 /* Bits[17:17], Access Type=RW0C_FW, default=0x00000000*/

16669

16670 /*

16671 Thermal Log, RW, When set by PCODE indicates

16672 that Thermal event has cause GT frequency

16673 clipping. Software should write to this bit to

16674 clear the status in this bit

16675 */

16676 UINT32 SpareGtLog2 : 1;

16677

16678 /* Bits[18:18], Access Type=RW0C_FW, default=0x00000000*/

16679

16680 /* Reserved */

16681 UINT32 SpareGt3Log : 1;

16682

16683 /* Bits[19:19], Access Type=RW0C_FW, default=0x00000000*/

16684

16685 /* Reserved */

16686 UINT32 RsrLimitLog : 1;

16687

16688 /* Bits[20:20], Access Type=RW0C_FW, default=0x00000000*/

16689

16690 /* Reserved */

16691 UINT32 RatlLog : 1;

16692

16693 /* Bits[21:21], Access Type=RW0C_FW, default=0x00000000*/

16694

16695 /*

16696 Running average thermal limit Log, RW, When set

16697 by PCODE indicates that Running average thermal

16698 limit has cause GT frequency clipping. Software

16699 should write to this bit to clear the status in

16700 this bit

16701 */

16702 UINT32 VrThermalertLog : 1;

16703

16704 /* Bits[22:22], Access Type=RW0C_FW, default=0x00000000*/

16705

16706 /*

16707 Hot VR (any processor VR) Log, RW, When set by

16708 PCODE indicates that Hot VR (any processor VR)

16709 has cause GT frequency clipping. Software should

16710 write to this bit to clear the status in this

16711 bit

16712 */

16713 UINT32 VrTdcLog : 1;

16714

16715 /* Bits[23:23], Access Type=RW0C_FW, default=0x00000000*/

16716

16717 /*

16718 VR TDC (Thermal design current) Log, RW, When

16719 set by PCODE indicates that VR TDC (Thermal

16720 design current has cause GT frequency clipping.

16721 Software should write to this bit to clear the

16722 status in this bit

16723 */

16724 UINT32 OtherLog : 1;

16725

16726 /* Bits[24:24], Access Type=RW0C_FW, default=0x00000000*/

16727

16728 /*

16729 Other (IccMax, PL4, etc) Log, RW, When set by

16730 PCODE indicates that other has cause reason GT

16731 frequency clipping. Software should write to

16732 this bit to clear the status in this bit

16733 */

16734 UINT32 SpareGt9Log : 1;

16735

16736 /* Bits[25:25], Access Type=RW0C_FW, default=0x00000000*/

16737

16738 /* Reserved */

16739 UINT32 PbmPl1Log : 1;

16740

16741 /* Bits[26:26], Access Type=RW0C_FW, default=0x00000000*/

16742

16743 /*

16744 PBM PL1 (pkg, platform) Log, RW, When set by

16745 PCODE indicates that PBM PL1 (package or

16746 platform PL1) has cause GT frequency clipping.

16747 Software should write to this bit to clear the

16748 status in this bit

16749 */

16750 UINT32 PbmPl2Log : 1;

16751

16752 /* Bits[27:27], Access Type=RW0C_FW, default=0x00000000*/

16753

16754 /*

16755 PBM PL2, PL3 (pkg, platform) Log, RW, When set

16756 by PCODE indicates that PBM PL2 or PL3(package

16757 or platform PL2 or PL3) has cause GT frequency

16758 clipping. Software should write to this bit to

16759 clear the status in this bit

16760 */

16761 UINT32 InefficientOperationLog : 1;

16762

16763 /* Bits[28:28], Access Type=RW0C_FW, default=0x00000000*/

16764

16765 /*

16766 Inefficient operation Log, RW, The current GT

16767 Frequency lower than the DCC target Frequency.

16768 Software should write to this bit to clear the

16769 status in this bit

16770 */

16771 UINT32 SpareGt13Log : 1;

16772

16773 /* Bits[29:29], Access Type=RW0C_FW, default=0x00000000*/

16774

16775 /* Reserved */

16776 UINT32 SpareGt14Log : 1;

16777

16778 /* Bits[30:30], Access Type=RW0C_FW, default=0x00000000*/

16779

16780 /* Reserved */

16781 UINT32 SpareGt15Log : 1;

16782

16783 /* Bits[31:31], Access Type=RW0C_FW, default=0x00000000*/

16784

16785 /* Reserved */

16786

16787 } Bits;

16788

16789 UINT32 Uint32;

16790 UINT64 Uint64;

16791

16792 } MSR_GT_PERF_LIMIT_REASONS_REGISTER;

16793

16794 /**

16795 Interface to allow software to determine what is causing resolved frequency to be clamped

16796 below the requested frequency. Status bits are updated by pcode through the io interface IO_CLR_PERF_LIMIT,

16797 log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

16798 **/

16799 #define MSR_CLR_PERF_LIMIT_REASONS 0x000006B1

16800

16801 typedef union {

16802 ///

16803 /// Individual bit fields

16804 ///

16805 struct {

16806 UINT32 Prochot : 1;

16807

16808 /* Bits[0:0], Access Type=RO, default=0x00000000*/

16809

16810 /*

16811 PROCHOT# Status, RO, When set by PCODE indicates

16812 that PROCHOT# has cause RING frequency clipping

16813 */

16814 UINT32 Thermal : 1;

16815

16816 /* Bits[1:1], Access Type=RO, default=0x00000000*/

16817

16818 /*

16819 Thermal Status, RO, When set by PCODE indicates

16820 that Thermal event has cause RING frequency

16821 clipping

16822 */

16823 UINT32 SpareClr2 : 1;

16824

16825 /* Bits[2:2], Access Type=RO, default=0x00000000*/

16826

16827 /* Reserved */

16828 UINT32 SpareClr3 : 1;

16829

16830 /* Bits[3:3], Access Type=RO, default=0x00000000*/

16831

16832 /* Reserved */

16833 UINT32 Rsr : 1;

16834

16835 /* Bits[4:4], Access Type=RO, default=0x00000000*/

16836

16837 /* Reserved */

16838 UINT32 Ratl : 1;

16839

16840 /* Bits[5:5], Access Type=RO, default=0x00000000*/

16841

16842 /*

16843 Running average thermal limit Status, R0, When

16844 set by PCODE indicates that Running average

16845 thermal limit has cause RING frequency clipping

16846 */

16847 UINT32 VrThermalert : 1;

16848

16849 /* Bits[6:6], Access Type=RO, default=0x00000000*/

16850

16851 /*

16852 Hot VR (any processor VR) Status, RO, When set

16853 by PCODE indicates that Hot VR (any processor

16854 VR) has cause RING frequency clipping

16855 */

16856 UINT32 VrTdc : 1;

16857

16858 /* Bits[7:7], Access Type=RO, default=0x00000000*/

16859

16860 /*

16861 VR TDC (Thermal design current) Status, RO, When

16862 set by PCODE indicates that VR TDC (Thermal

16863 design current has cause RING frequency clipping

16864 */

16865 UINT32 Other : 1;

16866

16867 /* Bits[8:8], Access Type=RO, default=0x00000000*/

16868

16869 /*

16870 Other (IccMax, PL4, etc) Status, RO, When set by

16871 PCODE indicates that other has cause reason RING

16872 frequency clipping

16873 */

16874 UINT32 SpareClr9 : 1;

16875

16876 /* Bits[9:9], Access Type=RO, default=0x00000000*/

16877

16878 /* Reserved */

16879 UINT32 PbmPl1 : 1;

16880

16881 /* Bits[10:10], Access Type=RO, default=0x00000000*/

16882

16883 /*

16884 PBM PL1 (pkg, platform), RO, When set by PCODE

16885 indicates that PBM PL1 (package or platform PL1)

16886 has cause RING frequency clipping

16887 */

16888 UINT32 PbmPl2 : 1;

16889

16890 /* Bits[11:11], Access Type=RO, default=0x00000000*/

16891

16892 /*

16893 PBM PL2, PL3 (pkg, platform) Status, RO, When

16894 set by PCODE indicates that PBM PL2 or

16895 PL3(package or platform PL2 or PL3) has cause

16896 RING frequency clipping

16897 */

16898 UINT32 SpareClr12 : 1;

16899

16900 /* Bits[12:12], Access Type=RO, default=0x00000000*/

16901

16902 /* Reserved */

16903 UINT32 SpareClr13 : 1;

16904

16905 /* Bits[13:13], Access Type=RO, default=0x00000000*/

16906

16907 /* Reserved */

16908 UINT32 SpareClr14 : 1;

16909

16910 /* Bits[14:14], Access Type=RO, default=0x00000000*/

16911

16912 /* Reserved */

16913 UINT32 SpareClr15 : 1;

16914

16915 /* Bits[15:15], Access Type=RO, default=0x00000000*/

16916

16917 /* Reserved */

16918 UINT32 ProchotLog : 1;

16919

16920 /* Bits[16:16], Access Type=RW0C_FW, default=0x00000000*/

16921

16922 /*

16923 PROCHOT# Log, RW, When set by PCODE indicates

16924 that PROCHOT# has cause RING frequency clipping.

16925 Software should write to this bit to clear the

16926 status in this bit

16927 */

16928 UINT32 ThermalLog : 1;

16929

16930 /* Bits[17:17], Access Type=RW0C_FW, default=0x00000000*/

16931

16932 /*

16933 Thermal Log, RW, When set by PCODE indicates

16934 that Thermal event has cause RING frequency

16935 clipping. Software should write to this bit to

16936 clear the status in this bit

16937 */

16938 UINT32 SpareClr2Log : 1;

16939

16940 /* Bits[18:18], Access Type=RW0C_FW, default=0x00000000*/

16941

16942 /* Reserved */

16943 UINT32 SpareClr3Log : 1;

16944

16945 /* Bits[19:19], Access Type=RW0C_FW, default=0x00000000*/

16946

16947 /* Reserved */

16948 UINT32 RsrLog : 1;

16949

16950 /* Bits[20:20], Access Type=RW0C_FW, default=0x00000000*/

16951

16952 /* Reserved */

16953 UINT32 RatlLog : 1;

16954

16955 /* Bits[21:21], Access Type=RW0C_FW, default=0x00000000*/

16956

16957 /*

16958 Running average thermal limit Log, RW, When set

16959 by PCODE indicates that Running average thermal

16960 limit has cause RING frequency clipping.

16961 Software should write to this bit to clear the

16962 status in this bit

16963 */

16964 UINT32 VrThermalertLog : 1;

16965

16966 /* Bits[22:22], Access Type=RW0C_FW, default=0x00000000*/

16967

16968 /*

16969 Hot VR (any processor VR) Log, RW, When set by

16970 PCODE indicates that Hot VR (any processor VR)

16971 has cause RING frequency clipping. Software

16972 should write to this bit to clear the status in

16973 this bit

16974 */

16975 UINT32 VrTdcLog : 1;

16976

16977 /* Bits[23:23], Access Type=RW0C_FW, default=0x00000000*/

16978

16979 /*

16980 VR TDC (Thermal design current) Log, RW, When

16981 set by PCODE indicates that VR TDC (Thermal

16982 design current has cause RING frequency

16983 clipping. Software should write to this bit to

16984 clear the status in this bit

16985 */

16986 UINT32 OtherLog : 1;

16987

16988 /* Bits[24:24], Access Type=RW0C_FW, default=0x00000000*/

16989

16990 /*

16991 Other (IccMax, PL4, etc) Log, RW, When set by

16992 PCODE indicates that other has cause reason RING

16993 frequency clipping. Software should write to

16994 this bit to clear the status in this bit

16995 */

16996 UINT32 SpareClr9Log : 1;

16997

16998 /* Bits[25:25], Access Type=RW0C_FW, default=0x00000000*/

16999

17000 /* Reserved */

17001 UINT32 PbmPl1Log : 1;

17002

17003 /* Bits[26:26], Access Type=RW0C_FW, default=0x00000000*/

17004

17005 /*

17006 PBM PL1 (pkg, platform) Log, RW, When set by

17007 PCODE indicates that PBM PL1 (package or

17008 platform PL1) has cause RING frequency clipping.

17009 Software should write to this bit to clear the

17010 status in this bit

17011 */

17012 UINT32 PbmPl2Log : 1;

17013

17014 /* Bits[27:27], Access Type=RW0C_FW, default=0x00000000*/

17015

17016 /*

17017 PBM PL2, PL3 (pkg, platform) Log, RW, When set

17018 by PCODE indicates that PBM PL2 or PL3(package

17019 or platform PL2 or PL3) has cause RING frequency

17020 clipping. Software should write to this bit to

17021 clear the status in this bit

17022 */

17023 UINT32 SpareClr12Log : 1;

17024

17025 /* Bits[28:28], Access Type=RW0C_FW, default=0x00000000*/

17026

17027 /* Reserved */

17028 UINT32 SpareClr13Log : 1;

17029

17030 /* Bits[29:29], Access Type=RW0C_FW, default=0x00000000*/

17031

17032 /* Reserved */

17033 UINT32 SpareClr14Log : 1;

17034

17035 /* Bits[30:30], Access Type=RW0C_FW, default=0x00000000*/

17036

17037 /* Reserved */

17038 UINT32 SpareClr15Log : 1;

17039

17040 /* Bits[31:31], Access Type=RW0C_FW, default=0x00000000*/

17041

17042 /* Reserved */

17043

17044 } Bits;

17045

17046 UINT32 Uint32;

17047 UINT64 Uint64;

17048

17049 } MSR_CLR_PERF_LIMIT_REASONS_REGISTER;

17050 /**

17051 TSC Target of Local APIC's TSC Deadline Mode

17052 **/

17053 #define MSR_TSC_DEADLINE 0x000006E0

17054

17055 /**

17056 Used to convey the OSs performance request {Min, Max. Desired, tc} to apply across threads if requested.

17057 **/

17058 #define MSR_HWP_REQUEST_PKG 0x00000772

17059

17060 typedef union {

17061 ///

17062 /// Individual bit fields

17063 ///

17064 struct {

17065 UINT32 MinimumPerformance : 8;

17066

17067 /* Bits[7:0], Access Type=RW, default=0x00000001*/

17068

17069 /*

17070 Limits the instantaneous minimum performance

17071 while in C0. HW will observe this constraint

17072 unless and until an overriding condition occurs

17073 (e.g. thermal). Set to zero (0) if SW does not

17074 care (no limit). Default = zero (0).

17075 */

17076 UINT32 MaximumPerformance : 8;

17077

17078 /* Bits[15:8], Access Type=RW, default=0x000000FF*/

17079

17080 /*

17081 Limits the instantaneous maximum performance

17082 level while in C0. Set to all ones (1s) if SW

17083 does not care (no limit). Default = all ones

17084 (1s).

17085 */

17086 UINT32 DesiredPerformance : 8;

17087

17088 /* Bits[23:16], Access Type=RW, default=0x00000000*/

17089

17090 /*

17091 When set to zero, HW autonomous selection

17092 determines the performance target. When set to a

17093 non-zero value, in the range of Lowest

17094 Performance to Highest Performance

17095 (IA32_HWP_CAPABILITIES), conveys an explicit

17096 performance request hint to the hardware;

17097 effectively disabling HW Autonomous selection.

17098 The Desired Performance input is non-

17099 constraining in terms of Performance and Energy

17100 Efficiency optimizations, which are

17101 independently controlled.

17102 */

17103 UINT32 EnergyPerformancePreference : 8;

17104

17105 /* Bits[31:24], Access Type=RW, default=0x00000080*/

17106

17107 /* tbd */

17108 UINT32 ActivityWindow : 10;

17109

17110 /* Bits[41:32], Access Type=RW, default=0x00000000*/

17111

17112 /*

17113 Used as a hint to the H/W. The OS writes a time

17114 value (10^3-bit exp * 7-bit mantissa in 1sec

17115 units: 1us to 1270 sec) to this field to

17116 indicate a moving workload history observation

17117 window. Combined with the Energy Performance

17118 Preference input, influences the rate of

17119 performance increase / decrease. This field only

17120 has meaning when Desired Performance = 0. 41:39

17121 Exponent 38:32 Mantissa

17122 */

17123 UINT32 ReservedForEco42 : 6;

17124

17125 /* Bits[47:42], Access Type=RW, default=0x00000000*/

17126

17127 /* Reserved_for_eco */

17128 UINT32 Reserved48 : 16;

17129

17130 /* Bits[63:48], Access Type=RO, default=0x00000000*/

17131

17132 /* Reserved */

17133

17134 } Bits;

17135

17136 UINT32 Uint32;

17137 UINT64 Uint64;

17138

17139 } MSR_HWP_REQUEST_PKG_REGISTER;

17140

17141 /**

17142

17143 **/

17144 #define MSR_PECI_HWP_REQUEST_INFO 0x00000775

17145

17146 typedef union {

17147 ///

17148 /// Individual bit fields

17149 ///

17150 struct {

17151 UINT32 MinimumPerformance : 8;

17152

17153 /* Bits[7:0], Access Type=RO, default=0x00000000*/

17154

17155 /*

17156 RO (default = 0x0), Used by OS to read the

17157 latest value of PECI minimum performance input

17158 */

17159 UINT32 MaximumPerformance : 8;

17160

17161 /* Bits[15:8], Access Type=RO, default=0x00000000*/

17162

17163 /*

17164 RO (default = 0x0), Used by OS to read the

17165 latest value of PECI maximum performance input

17166 */

17167 UINT32 Rsvd16 : 8;

17168

17169 /* Bits[23:16], Access Type=RO, default=None*/

17170

17171 /* Reserved */

17172 UINT32 EnergyPerformancePreference : 8;

17173

17174 /* Bits[31:24], Access Type=RO, default=0x00000000*/

17175

17176 /*

17177 RO (default = 0x0), Used by OS to read the

17178 latest value of PECI Energy Performance

17179 Preference input

17180 */

17181 UINT32 Rsvd32 : 28;

17182

17183 /* Bits[59:32], Access Type=RO, default=None*/

17184

17185 /* Reserved */

17186 UINT32 EppPeciOverride : 1;

17187

17188 /* Bits[60:60], Access Type=RO, default=0x00000000*/

17189

17190 /*

17191 RO (default = 0x0). Indicates whether PECI if

17192 currently overriding the Energy Performance

17193 Preference input. If set(1), PECI is overriding

17194 the Energy Performance Preference input. If

17195 clear(0), OS has control over Energy Performance

17196 Preference input

17197 */

17198 UINT32 Rsvd61 : 1;

17199

17200 /* Bits[61:61], Access Type=RO, default=None*/

17201

17202 /* Reserved */

17203 UINT32 MaxPeciOverride : 1;

17204

17205 /* Bits[62:62], Access Type=RO, default=0x00000000*/

17206

17207 /*

17208 RO (default = 0x0).Indicates whether PECI is

17209 currently overriding the Maximum Performance

17210 input. If set(1), PECI is overriding the Maximum

17211 Performance input. If clear(0), OS has control

17212 over Maximum Performance input

17213 */

17214 UINT32 MinPeciOverride : 1;

17215

17216 /* Bits[63:63], Access Type=RO, default=0x00000000*/

17217

17218 /*

17219 RO (default = 0x0).Indicates whether PECI is

17220 currently overriding the Minimum Performance

17221 input. If set(1), PECI is overriding the Minimum

17222 Performance input. If clear(0), OS has control

17223 over Minimum Performance input

17224 */

17225

17226 } Bits;

17227

17228 UINT32 Uint32;

17229 UINT64 Uint64;

17230

17231 } MSR_PECI_HWP_REQUEST_INFO_REGISTER;

17232

17233 /**

17234 This is a new PerfMon register is used for future user-invisible controls to be shadowed in all PerfMon units.

17235 **/

17236 #define MSR_PERMON_EVNTSEL_AUX 0x00000966

17237

17238 typedef union {

17239 ///

17240 /// Individual bit fields

17241 ///

17242 struct {

17243 UINT32 BlkCnt : 1;

17244

17245 /* Bits[0:0], Access Type=RW, default=0x00000000*/

17246

17247 /*

17248 manageable by x/ucode. Suppress PMON/ROP

17249 counting in SE

17250 */

17251 UINT32 BlkRtitTrc : 1;

17252

17253 /* Bits[1:1], Access Type=RW, default=0x00000000*/

17254

17255 /*

17256 manageable by x/ucode. used to suppress

17257 ContextEn on opt-out enclave entries

17258 */

17259 UINT32 BlkRop : 1;

17260

17261 /* Bits[2:2], Access Type=RW, default=0x00000000*/

17262

17263 /*

17264 manageable by x/ucode. used to suppress ROP

17265 counters on opt-out enclave entries

17266 */

17267 UINT32 Rsvd3 : 29;

17268

17269 /* Bits[31:3], Access Type=RO, default=None*/

17270

17271 /* Reserved */

17272

17273 } Bits;

17274

17275 UINT32 Uint32;

17276 UINT64 Uint64;

17277

17278 } MSR_PERMON_EVNTSEL_AUX_REGISTER;

17279

17280 /**

17281 Read only register for encryption policies supported by TME

17282 **/

17283 #define MSR_TME_CAPABILITY 0x00000981

17284

17285 typedef union {

17286 ///

17287 /// Individual bit fields

17288 ///

17289 struct {

17290 UINT32 AesXts : 1;

17291

17292 /* Bits[0:0], Access Type=RO, default=0x00000001*/

17293

17294 /* Enumerate support for AES-XTS */

17295 UINT32 Rsvd1 : 31;

17296

17297 /* Bits[31:1], Access Type=RO, default=0x00000000*/

17298

17299 /* Reserved */

17300 UINT32 MkTmeMaxKeyidBits : 4;

17301

17302 /* Bits[35:32], Access Type=RO, default=0x00000000*/

17303

17304 /*

17305 Number of bits which can be allocated for usage

17306 as key identifiers for multi-key memory

17307 encryption. Zero if MK-TME is not supported

17308 */

17309 UINT32 MkTmeMaxKeys : 15;

17310

17311 /* Bits[50:36], Access Type=RO, default=0x00000000*/

17312

17313 /*

17314 Indicates the maximum number of keys which are

17315 available for usage and may be a non-power of 2.

17316 This maximum value of this field will be

17317 (2^MK_TME_MAX_KEYID_BITS)-1. Zero if MK-TME is

17318 not supported

17319 */

17320 UINT32 Rsvd51 : 13;

17321

17322 /* Bits[63:51], Access Type=RO, default=0x00000000*/

17323

17324 /* Reserved */

17325

17326 } Bits;

17327

17328 UINT32 Uint32;

17329 UINT64 Uint64;

17330

17331 } MSR_TME_CAPABILITY_REGISTER;

17332

17333 /**

17334 Rd/Wr register to generate or restore Keys for TME

17335 **/

17336 #define MSR_TME_ACTIVATE 0x00000982

17337

17338 typedef union {

17339 ///

17340 /// Individual bit fields

17341 ///

17342 struct {

17343 UINT32 Lock : 1;

17344

17345 /* Bits[0:0], Access Type=RO, default=0x00000000*/

17346

17347 /*

17348 Will be set upon successful WRMSR; written

17349 valuei gnored Lock for MSRs: IA32_TME_ACTIVATE

17350 IA32_TME_EXCLUDE_MASK IA32_TME_EXCLUDE_BASE

17351 */

17352 UINT32 TmeEnable : 1;

17353

17354 /* Bits[1:1], Access Type=RW_L, default=0x00000000*/

17355

17356 /*

17357 Set to enable TME Encryption using DRNG

17358 operation

17359 */

17360 UINT32 KeySelect : 1;

17361

17362 /* Bits[2:2], Access Type=RW_L, default=0x00000000*/

17363

17364 /*

17365 0 - Create a new ke (expected cold/warm boot) 1

17366 - Restore the key from storage (Expected when

17367 resume from standby)

17368 */

17369 UINT32 SaveKeyForStandby : 1;

17370

17371 /* Bits[3:3], Access Type=RW_L, default=0x00000000*/

17372

17373 /*

17374 Save key into storage to be used when resume

17375 from standby

17376 */

17377 UINT32 TmePolicy : 4;

17378

17379 /* Bits[7:4], Access Type=RW_L, default=0x00000000*/

17380

17381 /* 0000 = AES-XTS Other Values are reserved */

17382 UINT32 SgxTemEnable : 1;

17383

17384 /* Bits[8:8], Access Type=RO, default=0x00000000*/

17385

17386 /* Enables TME for SGX-TEM. */

17387 UINT32 Rsvd9 : 23;

17388

17389 /* Bits[31:9], Access Type=RO, default=0x00000000*/

17390

17391 /* Reserved Bits; Must be 0 */

17392 UINT32 MkTmeKeyidBits : 4;

17393

17394 /* Bits[35:32], Access Type=RW_L, default=0x00000000*/

17395

17396 /*

17397 The number of key identifier bits to allocate to

17398 MK-TME usage. Similar to enumeration, this is an

17399 encoded value. Writing a value greater than

17400 MK_TME_MAX_KEYID_BITS will result in #GP.

17401 Writing a non-zero value to this field will #GP

17402 if bit 1 (TME Enable) is not set to '1, as TME

17403 must be enabled to use MK-TME.

17404 */

17405 UINT32 Rsvd36 : 12;

17406

17407 /* Bits[47:36], Access Type=RO, default=0x00000000*/

17408

17409 /* Reserved Bits; Must be 0 */

17410 UINT32 MkTmeCryptoAlgs : 16;

17411

17412 /* Bits[63:48], Access Type=RW_L, default=0x00000000*/

17413

17414 /*

17415 Bitmask for BIOS to set which encryption

17416 algorithms are allowed for MK-TME, would be

17417 later enforced by the key loading ISA ('1 =

17418 allowed). #GP if corresponding algorithm bits

17419 are zero in TME Capability MSR

17420 */

17421

17422 } Bits;

17423

17424 UINT32 Uint32;

17425 UINT64 Uint64;

17426

17427 } MSR_TME_ACTIVATE_REGISTER;

17428

17429 /**

17430 Register for debug purposes to exclude a memory range from encryption by TME

17431 **/

17432 #define MSR_TME_EXCLUDE_MASK 0x00000983

17433

17434 typedef union {

17435 ///

17436 /// Individual bit fields

17437 ///

17438 struct {

17439 UINT32 Rsvd0 : 11;

17440

17441 /* Bits[10:0], Access Type=RO, default=0x00000000*/

17442

17443 /* Reserved */

17444 UINT32 Enable : 1;

17445

17446 /* Bits[11:11], Access Type=RW, default=0x00000000*/

17447

17448 /*

17449 When set to 1, then IA32_TME_EXCLUDE_BASE and

17450 IA32_TME_EXCLUDE_MASK are used to define an

17451 exclusion region for TME.

17452 */

17453 UINT32 Tmemask0 : 20;

17454

17455 /* Bits[31:12], Access Type=RW, default=0x00000000*/

17456

17457 /*

17458 This field indicates the bits that must match

17459 TMEEBASE in order to qualify as a TME exclusion

17460 memory range access. This cannot exceed

17461 MAX_PHYS_ADDR

17462 */

17463 UINT32 Tmemask1 : 32;

17464

17465 /* Bits[63:32], Access Type=RW, default=0x00000000*/

17466

17467 /*

17468 This field indicates the bits that must match

17469 TMEEBASE in order to qualify as a TME exclusion

17470 memory range access. This cannot exceed

17471 MAX_PHYS_ADDR

17472 */

17473

17474 } Bits;

17475

17476 UINT32 Uint32;

17477 UINT64 Uint64;

17478

17479 } MSR_TME_EXCLUDE_MASK_REGISTER;

17480

17481 /**

17482 Register for debug purposes to exclude a memory range from encryption by TME

17483 **/

17484 #define MSR_TME_EXCLUDE_BASE 0x00000984

17485

17486 typedef union {

17487 ///

17488 /// Individual bit fields

17489 ///

17490 struct {

17491 UINT32 Rsvd0 : 12;

17492

17493 /* Bits[11:0], Access Type=RO, default=0x00000000*/

17494

17495 /* Reserved */

17496 UINT32 Tmebase0 : 20;

17497

17498 /* Bits[31:12], Access Type=RW, default=0x00000000*/

17499

17500 /*

17501 Base physical address to be excluded for TME

17502 encryption. This cannot exceed MAX_PHYS_ADDR

17503 */

17504 UINT32 Tmebase1 : 32;

17505

17506 /* Bits[63:32], Access Type=RW, default=0x00000000*/

17507

17508 /*

17509 Base physical address to be excluded for TME

17510 encryption. This cannot exceed MAX_PHYS_ADDR

17511 */

17512

17513 } Bits;

17514

17515 UINT32 Uint32;

17516 UINT64 Uint64;

17517

17518 } MSR_TME_EXCLUDE_BASE_REGISTER;

17519

17520 /**

17521 FSCP To hold keylocker information

17522 **/

17523 #define MSR_COPY_STATUS 0x00000990

17524

17525 typedef union {

17526 ///

17527 /// Individual bit fields

17528 ///

17529 struct {

17530 UINT32 CopyStatus : 1;

17531

17532 /* Bits[0:0], Access Type=RW, default=None*/

17533

17534 /* Bit to hold COPY_STATUS bit for the MSR */

17535 UINT32 HandlePtr : 1;

17536

17537 /* Bits[1:1], Access Type=RW, default=None*/

17538

17539 /* Bit to hold Handle lookup */

17540 UINT32 Rsvd2 : 2;

17541

17542 /* Bits[3:2], Access Type=RO, default=None*/

17543

17544 /* Reserved */

17545 UINT32 HandleValidMask : 2;

17546

17547 /* Bits[5:4], Access Type=RW, default=None*/

17548

17549 /*

17550 Mask to indicate whether the handles are valid

17551 or not. Two bits currently for 2 handles

17552 */

17553 UINT32 Rsvd6 : 26;

17554

17555 /* Bits[31:6], Access Type=RO, default=None*/

17556

17557 /* Reserved */

17558

17559 } Bits;

17560

17561 UINT32 Uint32;

17562 UINT64 Uint64;

17563

17564 } MSR_COPY_STATUS_REGISTER;

17565

17566 /**

17567 Status of IWKey Backup in PCH

17568 **/

17569 #define MSR_IWKEYBACKUP_STATUS 0x00000991

17570

17571 typedef union {

17572 ///

17573 /// Individual bit fields

17574 ///

17575 struct {

17576 UINT32 BackupRestoreValid : 1;

17577

17578 /* Bits[0:0], Access Type=RO_V, default=0x00000000*/

17579

17580 /*

17581 Indication of a successful backup or restore of

17582 IWKEY

17583 */

17584 UINT32 BackupKeyCorrupted : 1;

17585

17586 /* Bits[1:1], Access Type=RO_V, default=0x00000000*/

17587

17588 /*

17589 Indicates if ICV/Tag Check passes or fails for

17590 IWKey

17591 */

17592 UINT32 BackupKeyStorageRwError : 1;

17593

17594 /* Bits[2:2], Access Type=RO_V, default=0x00000000*/

17595

17596 /*

17597 Indicates if there was a read/write error

17598 to/from SPI Flash

17599 */

17600 UINT32 IwkeybackupConsumed : 1;

17601

17602 /* Bits[3:3], Access Type=RO_V, default=0x00000000*/

17603

17604 /*

17605 Indicates if the CSE has consume the IWKeybackup

17606 written by Core

17607 */

17608 UINT32 Rsvd4 : 28;

17609

17610 /* Bits[31:4], Access Type=RO, default=None*/

17611

17612 /* Reserved */

17613 UINT32 Rsvd32 : 32;

17614

17615 /* Bits[63:32], Access Type=RO, default=None*/

17616

17617 /* Reserved */

17618

17619 } Bits;

17620

17621 UINT32 Uint32;

17622 UINT64 Uint64;

17623

17624 } MSR_IWKEYBACKUP_STATUS_REGISTER;

17625

17626 /**

17627 This register implements Debug Interface (Privacy) MSR

17628 **/

17629 #define MSR_PRIVACY_CONTROL 0x00000C80

17630

17631 typedef union {

17632 ///

17633 /// Individual bit fields

17634 ///

17635 struct {

17636 UINT32 Enable : 1;

17637

17638 /* Bits[0:0], Access Type=RW, default=0x00000000*/

17639

17640 /*

17641 This bit enables or disables a variety of debug

17642 features as defined in the ECO. All consumers of

17643 this bit are FW agents.

17644 */

17645 UINT32 Rsvd1 : 29;

17646

17647 /* Bits[29:1], Access Type=RO, default=None*/

17648

17649 /* Reserved */

17650 UINT32 Lock : 1;

17651

17652 /* Bits[30:30], Access Type=RW, default=0x00000000*/

17653

17654 /*

17655 This bit locks the enable bit. Once set the

17656 enable bit should not be changed. The lock is

17657 enforced in ucode.

17658 */

17659 UINT32 DebugHasOccurred : 1;

17660

17661 /* Bits[31:31], Access Type=RO_V, default=0x00000000*/

17662

17663 /*

17664 This bit reflects a sticky flop that is the OR

17665 of itself and bit 0 (enable bit) of this

17666 register. Hardware also allows a sideband write

17667 of 1 to this bit. PCODE/VCODE will assert this

17668 bit on warm reset if a sticky debug patch is

17669 detected

17670 */

17671

17672 } Bits;

17673

17674 UINT32 Uint32;

17675 UINT64 Uint64;

17676

17677 } MSR_PRIVACY_CONTROL_REGISTER;

17678

17679 /**

17680 MLC Class Of Service Configuration Register

17681 **/

17682 #define MSR_L2_QOS_CFG 0x00000C82

17683

17684 typedef union {

17685 ///

17686 /// Individual bit fields

17687 ///

17688 struct {

17689 UINT32 CdpEn : 1;

17690

17691 /* Bits[0:0], Access Type=RW, default=0x00000000*/

17692

17693 /*

17694 CDP (code data prioritization) enable control.

17695 '0 indicates no CDP, '1 indicates CDP is

17696 enabled.

17697 */

17698 UINT32 Rsvd1 : 31;

17699

17700 /* Bits[31:1], Access Type=RO, default=None*/

17701

17702 /* Reserved */

17703

17704 } Bits;

17705

17706 UINT32 Uint32;

17707 UINT64 Uint64;

17708

17709 } MSR_L2_QOS_CFG_REGISTER;

17710

17711 /**

17712 Class Of Service Configuration Register

17713 **/

17714 #define MSR_CLOS_CONFIG 0x00000C8F

17715

17716 typedef union {

17717 ///

17718 /// Individual bit fields

17719 ///

17720 struct {

17721 UINT32 ClosValue : 5;

17722

17723 /* Bits[4:0], Access Type=RW, default=0x00000000*/

17724

17725 /* The Class Of Service of the Thread */

17726 UINT32 Rsvd5 : 27;

17727

17728 /* Bits[31:5], Access Type=RO, default=None*/

17729

17730 /* Reserved */

17731

17732 } Bits;

17733

17734 UINT32 Uint32;

17735 UINT64 Uint64;

17736

17737 } MSR_CLOS_CONFIG_REGISTER;

17738

17739 /**

17740 available ways vectors for class of service of IA core

17741 **/

17742 #define MSR_COS_WAYS_0 0x00000C90

17743

17744 typedef union {

17745 ///

17746 /// Individual bit fields

17747 ///

17748 struct {

17749 UINT32 Iacosways : 24;

17750

17751 /* Bits[23:0], Access Type=RWS, default=0x00FFFFFF*/

17752

17753 /*

17754 available ways vectors for class of service of

17755 IA core

17756 */

17757 UINT32 Rsvd24 : 8;

17758

17759 /* Bits[31:24], Access Type=RO, default=None*/

17760

17761 /* Reserved */

17762

17763 } Bits;

17764

17765 UINT32 Uint32;

17766 UINT64 Uint64;

17767

17768 } MSR_COS_WAYS_0_REGISTER;

17769

17770 /**

17771 available ways vectors for class of service of IA core

17772 **/

17773 #define MSR_COS_WAYS_1 0x00000C91

17774

17775 typedef union {

17776 ///

17777 /// Individual bit fields

17778 ///

17779 struct {

17780 UINT32 Iacosways : 24;

17781

17782 /* Bits[23:0], Access Type=RWS, default=0x0000000F*/

17783

17784 /*

17785 available ways vectors for class of service of

17786 IA core

17787 */

17788 UINT32 Rsvd24 : 8;

17789

17790 /* Bits[31:24], Access Type=RO, default=None*/

17791

17792 /* Reserved */

17793

17794 } Bits;

17795

17796 UINT32 Uint32;

17797 UINT64 Uint64;

17798

17799 } MSR_COS_WAYS_1_REGISTER;

17800

17801 /**

17802 available ways vectors for class of service of IA core

17803 **/

17804 #define MSR_COS_WAYS_2 0x00000C92

17805

17806 typedef union {

17807 ///

17808 /// Individual bit fields

17809 ///

17810 struct {

17811 UINT32 Iacosways : 24;

17812

17813 /* Bits[23:0], Access Type=RWS, default=0x000003FF*/

17814

17815 /*

17816 available ways vectors for class of service of

17817 IA core

17818 */

17819 UINT32 Rsvd24 : 8;

17820

17821 /* Bits[31:24], Access Type=RO, default=None*/

17822

17823 /* Reserved */

17824

17825 } Bits;

17826

17827 UINT32 Uint32;

17828 UINT64 Uint64;

17829

17830 } MSR_COS_WAYS_2_REGISTER;

17831

17832 /**

17833 available ways vectors for class of service of IA core

17834 **/

17835 #define MSR_COS_WAYS_3 0x00000C93

17836

17837 typedef union {

17838 ///

17839 /// Individual bit fields

17840 ///

17841 struct {

17842 UINT32 Iacosways : 24;

17843

17844 /* Bits[23:0], Access Type=RWS, default=0x00000FFF*/

17845

17846 /*

17847 available ways vectors for class of service of

17848 IA core

17849 */

17850 UINT32 Rsvd24 : 8;

17851

17852 /* Bits[31:24], Access Type=RO, default=None*/

17853

17854 /* Reserved */

17855

17856 } Bits;

17857

17858 UINT32 Uint32;

17859 UINT64 Uint64;

17860

17861 } MSR_COS_WAYS_3_REGISTER;

17862

17863 /**

17864 Spare for WLC

17865 **/

17866 #define MSR_L2_QOS_MASK_0_0 0x00000D10

17867

17868 typedef union {

17869 ///

17870 /// Individual bit fields

17871 ///

17872 struct {

17873 UINT32 WayMask : 20;

17874

17875 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

17876

17877 /*

17878 Way Allocation Mask per way in MLC. '1 in bit

17879 indicates allocation to the way is allowed. '0

17880 indicates allocation to the way is not allowed.

17881 restrictions: Only contiguous 1s are allowed. We

17882 had this formula: ucode_reset:IF

17883 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

17884 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

17885 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

17886 but we are ok to have 20 bits set if fuse says

17887 512k b/c the ways don't exist anyway (no one can

17888 write)... upon first WRMSR, we?ll #GP check for

17889 bits set above # of ways based upon bug

17890 1407940993.

17891 */

17892 UINT32 Rsvd20 : 12;

17893

17894 /* Bits[31:20], Access Type=RW, default=None*/

17895

17896 /* RSVD restrictions: None */

17897

17898 } Bits;

17899

17900 UINT32 Uint32;

17901 UINT64 Uint64;

17902

17903 } MSR_L2_QOS_MASK_0_0_REGISTER;

17904

17905 /**

17906 Spare for WLC

17907 **/

17908 #define MSR_L2_QOS_MASK_1_1 0x00000D11

17909

17910 typedef union {

17911 ///

17912 /// Individual bit fields

17913 ///

17914 struct {

17915 UINT32 WayMask : 20;

17916

17917 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

17918

17919 /*

17920 Way Allocation Mask per way in MLC. '1 in bit

17921 indicates allocation to the way is allowed. '0

17922 indicates allocation to the way is not allowed.

17923 restrictions: Only contiguous 1s are allowed. We

17924 had this formula: ucode_reset:IF

17925 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

17926 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

17927 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

17928 but we are ok to have 20 bits set if fuse says

17929 512k b/c the ways don't exist anyway (no one can

17930 write)... upon first WRMSR, we?ll #GP check for

17931 bits set above # of ways based upon bug

17932 1407940993.

17933 */

17934 UINT32 Rsvd20 : 12;

17935

17936 /* Bits[31:20], Access Type=RW, default=None*/

17937

17938 /* RSVD restrictions: None */

17939

17940 } Bits;

17941

17942 UINT32 Uint32;

17943 UINT64 Uint64;

17944

17945 } MSR_L2_QOS_MASK_1_1_REGISTER;

17946

17947 /**

17948 Spare for WLC

17949 **/

17950 #define MSR_L2_QOS_MASK_2_2 0x00000D12

17951

17952 typedef union {

17953 ///

17954 /// Individual bit fields

17955 ///

17956 struct {

17957 UINT32 WayMask : 20;

17958

17959 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

17960

17961 /*

17962 Way Allocation Mask per way in MLC. '1 in bit

17963 indicates allocation to the way is allowed. '0

17964 indicates allocation to the way is not allowed.

17965 restrictions: Only contiguous 1s are allowed. We

17966 had this formula: ucode_reset:IF

17967 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

17968 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

17969 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

17970 but we are ok to have 20 bits set if fuse says

17971 512k b/c the ways don't exist anyway (no one can

17972 write)... upon first WRMSR, we?ll #GP check for

17973 bits set above # of ways based upon bug

17974 1407940993.

17975 */

17976 UINT32 Rsvd20 : 12;

17977

17978 /* Bits[31:20], Access Type=RW, default=None*/

17979

17980 /* RSVD restrictions: None */

17981

17982 } Bits;

17983

17984 UINT32 Uint32;

17985 UINT64 Uint64;

17986

17987 } MSR_L2_QOS_MASK_2_2_REGISTER;

17988

17989 /**

17990 Spare for WLC

17991 **/

17992 #define MSR_L2_QOS_MASK_3_3 0x00000D13

17993

17994 typedef union {

17995 ///

17996 /// Individual bit fields

17997 ///

17998 struct {

17999 UINT32 WayMask : 20;

18000

18001 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

18002

18003 /*

18004 Way Allocation Mask per way in MLC. '1 in bit

18005 indicates allocation to the way is allowed. '0

18006 indicates allocation to the way is not allowed.

18007 restrictions: Only contiguous 1s are allowed. We

18008 had this formula: ucode_reset:IF

18009 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

18010 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

18011 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

18012 but we are ok to have 20 bits set if fuse says

18013 512k b/c the ways don't exist anyway (no one can

18014 write)... upon first WRMSR, we?ll #GP check for

18015 bits set above # of ways based upon bug

18016 1407940993.

18017 */

18018 UINT32 Rsvd20 : 12;

18019

18020 /* Bits[31:20], Access Type=RW, default=None*/

18021

18022 /* RSVD restrictions: None */

18023

18024 } Bits;

18025

18026 UINT32 Uint32;

18027 UINT64 Uint64;

18028

18029 } MSR_L2_QOS_MASK_3_3_REGISTER;

18030

18031 /**

18032 Spare for WLC

18033 **/

18034 #define MSR_L2_QOS_MASK_4_4 0x00000D14

18035

18036 typedef union {

18037 ///

18038 /// Individual bit fields

18039 ///

18040 struct {

18041 UINT32 WayMask : 20;

18042

18043 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

18044

18045 /*

18046 Way Allocation Mask per way in MLC. '1 in bit

18047 indicates allocation to the way is allowed. '0

18048 indicates allocation to the way is not allowed.

18049 restrictions: Only contiguous 1s are allowed. We

18050 had this formula: ucode_reset:IF

18051 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

18052 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

18053 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

18054 but we are ok to have 20 bits set if fuse says

18055 512k b/c the ways don't exist anyway (no one can

18056 write)... upon first WRMSR, we?ll #GP check for

18057 bits set above # of ways based upon bug

18058 1407940993.

18059 */

18060 UINT32 Rsvd20 : 12;

18061

18062 /* Bits[31:20], Access Type=RW, default=None*/

18063

18064 /* RSVD restrictions: None */

18065

18066 } Bits;

18067

18068 UINT32 Uint32;

18069 UINT64 Uint64;

18070

18071 } MSR_L2_QOS_MASK_4_4_REGISTER;

18072

18073 /**

18074 Spare for WLC

18075 **/

18076 #define MSR_L2_QOS_MASK_5_5 0x00000D15

18077

18078 typedef union {

18079 ///

18080 /// Individual bit fields

18081 ///

18082 struct {

18083 UINT32 WayMask : 20;

18084

18085 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

18086

18087 /*

18088 Way Allocation Mask per way in MLC. '1 in bit

18089 indicates allocation to the way is allowed. '0

18090 indicates allocation to the way is not allowed.

18091 restrictions: Only contiguous 1s are allowed. We

18092 had this formula: ucode_reset:IF

18093 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

18094 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

18095 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

18096 but we are ok to have 20 bits set if fuse says

18097 512k b/c the ways don't exist anyway (no one can

18098 write)... upon first WRMSR, we?ll #GP check for

18099 bits set above # of ways based upon bug

18100 1407940993.

18101 */

18102 UINT32 Rsvd20 : 12;

18103

18104 /* Bits[31:20], Access Type=RW, default=None*/

18105

18106 /* RSVD restrictions: None */

18107

18108 } Bits;

18109

18110 UINT32 Uint32;

18111 UINT64 Uint64;

18112

18113 } MSR_L2_QOS_MASK_5_5_REGISTER;

18114

18115 /**

18116 Spare for WLC

18117 **/

18118 #define MSR_L2_QOS_MASK_6_6 0x00000D16

18119

18120 typedef union {

18121 ///

18122 /// Individual bit fields

18123 ///

18124 struct {

18125 UINT32 WayMask : 20;

18126

18127 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

18128

18129 /*

18130 Way Allocation Mask per way in MLC. '1 in bit

18131 indicates allocation to the way is allowed. '0

18132 indicates allocation to the way is not allowed.

18133 restrictions: Only contiguous 1s are allowed. We

18134 had this formula: ucode_reset:IF

18135 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

18136 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

18137 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

18138 but we are ok to have 20 bits set if fuse says

18139 512k b/c the ways don't exist anyway (no one can

18140 write)... upon first WRMSR, we?ll #GP check for

18141 bits set above # of ways based upon bug

18142 1407940993.

18143 */

18144 UINT32 Rsvd20 : 12;

18145

18146 /* Bits[31:20], Access Type=RW, default=None*/

18147

18148 /* RSVD restrictions: None */

18149

18150 } Bits;

18151

18152 UINT32 Uint32;

18153 UINT64 Uint64;

18154

18155 } MSR_L2_QOS_MASK_6_6_REGISTER;

18156

18157 /**

18158 Spare for WLC

18159 **/

18160 #define MSR_L2_QOS_MASK_7_7 0x00000D17

18161

18162 typedef union {

18163 ///

18164 /// Individual bit fields

18165 ///

18166 struct {

18167 UINT32 WayMask : 20;

18168

18169 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

18170

18171 /*

18172 Way Allocation Mask per way in MLC. '1 in bit

18173 indicates allocation to the way is allowed. '0

18174 indicates allocation to the way is not allowed.

18175 restrictions: Only contiguous 1s are allowed. We

18176 had this formula: ucode_reset:IF

18177 (FUSE_FORCE512KMLC) THEN 0x000FF ELSE (IF

18178 (FUSE_FORCE768KMLC) THEN 0x00FFF ELSE (IF

18179 (FUSE_FORCE1MBMLC) THEN 0x0FFFF ELSE 0xFFFFF)),

18180 but we are ok to have 20 bits set if fuse says

18181 512k b/c the ways don't exist anyway (no one can

18182 write)... upon first WRMSR, we?ll #GP check for

18183 bits set above # of ways based upon bug

18184 1407940993.

18185 */

18186 UINT32 Rsvd20 : 12;

18187

18188 /* Bits[31:20], Access Type=RW, default=None*/

18189

18190 /* RSVD restrictions: None */

18191

18192 } Bits;

18193

18194 UINT32 Uint32;

18195 UINT64 Uint64;

18196

18197 } MSR_L2_QOS_MASK_7_7_REGISTER;

18198 /**

18199 BNDCFGS MSR.

18200 **/

18201 #define MSR_BNDCFGS 0x00000D90

18202

18203 /**

18204 Initiatate copy of IWKEY from Core to PCH for Keylocker

18205 **/

18206 #define MSR_COPY_LOCAL_TO_PLATFORM 0x00000D91

18207

18208 typedef union {

18209 ///

18210 /// Individual bit fields

18211 ///

18212 struct {

18213 UINT32 CopyIwkeyToPltfrmPersStorage : 1;

18214

18215 /* Bits[0:0], Access Type=WO, default=0x00000000*/

18216

18217 /*

18218 Command bit to initiate copy IWKEY from Core to

18219 PCH

18220 */

18221 UINT32 Rsvd1 : 31;

18222

18223 /* Bits[31:1], Access Type=RO, default=None*/

18224

18225 /* Reserved */

18226 UINT32 Rsvd32 : 32;

18227

18228 /* Bits[63:32], Access Type=RO, default=None*/

18229

18230 /* Reserved */

18231

18232 } Bits;

18233

18234 UINT32 Uint32;

18235 UINT64 Uint64;

18236

18237 } MSR_COPY_LOCAL_TO_PLATFORM_REGISTER;

18238

18239 /**

18240 Initiatate copy of IWKEY from PCH to Core for Keylocker

18241 **/

18242 #define MSR_COPY_PLATFORM_TO_LOCAL 0x00000D92

18243

18244 typedef union {

18245 ///

18246 /// Individual bit fields

18247 ///

18248 struct {

18249 UINT32 CopyIwkeyFromPltfrmPersStorage : 1;

18250

18251 /* Bits[0:0], Access Type=WO, default=0x00000000*/

18252

18253 /*

18254 Command bit to initiate copy IWKEY from PCH to

18255 Core

18256 */

18257 UINT32 Rsvd1 : 31;

18258

18259 /* Bits[31:1], Access Type=RO, default=None*/

18260

18261 /* Reserved */

18262 UINT32 Rsvd32 : 32;

18263

18264 /* Bits[63:32], Access Type=RO, default=None*/

18265

18266 /* Reserved */

18267

18268 } Bits;

18269

18270 UINT32 Uint32;

18271 UINT64 Uint64;

18272

18273 } MSR_COPY_PLATFORM_TO_LOCAL_REGISTER;

18274

18275 /**

18276 PASID MSR programmed by OS for ENQ* instruction (AiA)

18277 **/

18278 #define MSR_PASID 0x00000D93

18279

18280 typedef union {

18281 ///

18282 /// Individual bit fields

18283 ///

18284 struct {

18285 UINT32 PasidValue : 20;

18286

18287 /* Bits[19:0], Access Type=RW, default=0x00000000*/

18288

18289 /*

18290 Specifies the Process Address Space Identifier

18291 (PASID) value for the currently running thread

18292 */

18293 UINT32 Rsvd20 : 11;

18294

18295 /* Bits[30:20], Access Type=RO, default=None*/

18296

18297 /* Reserved */

18298 UINT32 PasidValid : 1;

18299

18300 /* Bits[31:31], Access Type=RW, default=0x00000000*/

18301

18302 /*

18303 If set, bits 19:0 of this MSR contains a valid

18304 PASID Value

18305 */

18306

18307 } Bits;

18308

18309 UINT32 Uint32;

18310 UINT64 Uint64;

18311

18312 } MSR_PASID_REGISTER;

18313

18314 /**

18315 Enables options to control the SDC operation.

18316 **/

18317 #define MSR_PKG_SDC_CTL 0x00000DB0

18318

18319 typedef union {

18320 ///

18321 /// Individual bit fields

18322 ///

18323 struct {

18324 UINT32 SdcPackageEnable : 1;

18325

18326 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18327

18328 /*

18329 Set this bit to enable SDC, Clearing this bit

18330 disables SDC and wakes up cores that were force

18331 to idle by SDC. Default=0x0

18332 */

18333 UINT32 SdcWasOnceEnabled : 1;

18334

18335 /* Bits[1:1], Access Type=RW, default=0x00000000*/

18336

18337 /*

18338 uCode sets this sticky indication on the first

18339 successful RD/WRMSR to any SDC MSR

18340 */

18341 UINT32 Rsvd2 : 30;

18342

18343 /* Bits[31:2], Access Type=RO, default=None*/

18344

18345 /* Reserved */

18346 UINT32 Rsvd32 : 32;

18347

18348 /* Bits[63:32], Access Type=RO, default=None*/

18349

18350 /* Reserved */

18351

18352 } Bits;

18353

18354 UINT32 Uint32;

18355 UINT64 Uint64;

18356

18357 } MSR_PKG_SDC_CTL_REGISTER;

18358

18359 /**

18360 This is a read/write MSR

18361 **/

18362 #define MSR_PM_CTL1 0x00000DB1

18363

18364 typedef union {

18365 ///

18366 /// Individual bit fields

18367 ///

18368 struct {

18369 UINT32 SdcAllowed : 1;

18370

18371 /* Bits[0:0], Access Type=RW, default=None*/

18372

18373 /*

18374 Set this bit to enable SDC, Clearing this bit

18375 disables SDC option to forced this thread only

18376 into idle state. (default=1)

18377 */

18378 UINT32 Rsvd1 : 31;

18379

18380 /* Bits[31:1], Access Type=RO, default=None*/

18381

18382 /* Reserved */

18383 UINT32 Rsvd32 : 32;

18384

18385 /* Bits[63:32], Access Type=RO, default=None*/

18386

18387 /* Reserved */

18388

18389 } Bits;

18390

18391 UINT32 Uint32;

18392 UINT64 Uint64;

18393

18394 } MSR_PM_CTL1_REGISTER;

18395

18396 /**

18397 MPX extension for determine MAWAU

18398 **/

18399 #define MSR_MPX_LAX 0x00001000

18400

18401 typedef union {

18402 ///

18403 /// Individual bit fields

18404 ///

18405 struct {

18406 UINT32 Mawa9 : 1;

18407

18408 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18409

18410 /*

18411 When set, enables MAWA9 MPX extensions in user

18412 mode (when CR4.LA57 is set). If cleared (or

18413 CR4.LA57 is cleared), then MPX will operate on

18414 48-bit addresses

18415 */

18416 UINT32 Rsvd1 : 31;

18417

18418 /* Bits[31:1], Access Type=RO, default=None*/

18419

18420 /* Reserved */

18421

18422 } Bits;

18423

18424 UINT32 Uint32;

18425 UINT64 Uint64;

18426

18427 } MSR_MPX_LAX_REGISTER;

18428

18429 /**

18430 The physical address of the Hardware Scheduler Information table

18431 **/

18432 #define MSR_HW_FB_PTR 0x000017D0

18433

18434 typedef union {

18435 ///

18436 /// Individual bit fields

18437 ///

18438 struct {

18439 UINT32 Valid : 1;

18440

18441 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18442

18443 /*

18444 When set to 1, indicates a valid pointer is

18445 programmed into the MSR

18446 */

18447 UINT32 Rsvd1 : 11;

18448

18449 /* Bits[11:1], Access Type=RW, default=0x00000000*/

18450

18451 /* Writing non zero values causes #GP */

18452 UINT32 Addr0 : 20;

18453

18454 /* Bits[31:12], Access Type=RW, default=0x00000000*/

18455

18456 /*

18457 Physical address of the page frame of the first

18458 page of this table

18459 */

18460 UINT32 Addr1 : 32;

18461

18462 /* Bits[63:32], Access Type=RW, default=0x00000000*/

18463

18464 /*

18465 Physical address of the page frame of the first

18466 page of this table

18467 */

18468

18469 } Bits;

18470

18471 UINT32 Uint32;

18472 UINT64 Uint64;

18473

18474 } MSR_HW_FB_PTR_REGISTER;

18475

18476 /**

18477 The operating system enables the hardware guided scheduler interface using new package scoped MSR

18478 **/

18479 #define MSR_HW_FB_CONFIG 0x000017D1

18480

18481 typedef union {

18482 ///

18483 /// Individual bit fields

18484 ///

18485 struct {

18486 UINT32 Enable : 1;

18487

18488 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18489

18490 /*

18491 when set to 1 enables HE guided scheduler

18492 interface

18493 */

18494 UINT32 Rsvd1 : 31;

18495

18496 /* Bits[31:1], Access Type=RO, default=None*/

18497

18498 /* Reserved */

18499 UINT32 Rsvd32 : 32;

18500

18501 /* Bits[63:32], Access Type=RO, default=None*/

18502

18503 /* Reserved */

18504

18505 } Bits;

18506

18507 UINT32 Uint32;

18508 UINT64 Uint64;

18509

18510 } MSR_HW_FB_CONFIG_REGISTER;

18511 /**

18512 available ways vectors for class of service of LLC snoop filter

18513 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18514 **/

18515 #define MSR_SF_QOS_MASK_0_0 0x00001890

18516 /**

18517 available ways vectors for class of service of LLC snoop filter

18518 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18519 **/

18520 #define MSR_SF_QOS_MASK_1_1 0x00001891

18521 /**

18522 available ways vectors for class of service of LLC snoop filter

18523 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18524 **/

18525 #define MSR_SF_QOS_MASK_2_2 0x00001892

18526 /**

18527 available ways vectors for class of service of LLC snoop filter

18528 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18529 **/

18530 #define MSR_SF_QOS_MASK_3_3 0x00001893

18531 /**

18532 available ways vectors for class of service of LLC snoop filter

18533 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18534 **/

18535 #define MSR_SF_QOS_MASK_4_4 0x00001894

18536 /**

18537 available ways vectors for class of service of LLC snoop filter

18538 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18539 **/

18540 #define MSR_SF_QOS_MASK_5_5 0x00001895

18541 /**

18542 available ways vectors for class of service of LLC snoop filter

18543 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18544 **/

18545 #define MSR_SF_QOS_MASK_6_6 0x00001896

18546 /**

18547 available ways vectors for class of service of LLC snoop filter

18548 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18549 **/

18550 #define MSR_SF_QOS_MASK_7_7 0x00001897

18551 /**

18552 available ways vectors for class of service of LLC snoop filter

18553 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18554 **/

18555 #define MSR_SF_QOS_MASK_8_8 0x00001898

18556 /**

18557 available ways vectors for class of service of LLC snoop filter

18558 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18559 **/

18560 #define MSR_SF_QOS_MASK_9_9 0x00001899

18561 /**

18562 available ways vectors for class of service of LLC snoop filter

18563 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18564 **/

18565 #define MSR_SF_QOS_MASK_10_10 0x0000189A

18566 /**

18567 available ways vectors for class of service of LLC snoop filter

18568 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18569 **/

18570 #define MSR_SF_QOS_MASK_11_11 0x0000189B

18571 /**

18572 available ways vectors for class of service of LLC snoop filter

18573 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18574 **/

18575 #define MSR_SF_QOS_MASK_12_12 0x0000189C

18576 /**

18577 available ways vectors for class of service of LLC snoop filter

18578 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18579 **/

18580 #define MSR_SF_QOS_MASK_13_13 0x0000189D

18581 /**

18582 available ways vectors for class of service of LLC snoop filter

18583 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18584 **/

18585 #define MSR_SF_QOS_MASK_14_14 0x0000189E

18586 /**

18587 available ways vectors for class of service of LLC snoop filter

18588 " seq has 16 instances in addresses range 0x1C90 to 0x1C9F"

18589 **/

18590 #define MSR_SF_QOS_MASK_15_15 0x0000189F

18591

18592 /**

18593 Global register for x86 EFER

18594 **/

18595 #define MSR_IA32_CR_EFER 0xC0000080

18596

18597 typedef union {

18598 ///

18599 /// Individual bit fields

18600 ///

18601 struct {

18602 UINT32 Sce : 1;

18603

18604 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18605

18606 /* System Call Enable Bit */

18607 UINT32 Rsvd1 : 7;

18608

18609 /* Bits[7:1], Access Type=RO, default=None*/

18610

18611 /* Reserved */

18612 UINT32 Lme : 1;

18613

18614 /* Bits[8:8], Access Type=RW, default=0x00000000*/

18615

18616 /* Long Mode Enabled */

18617 UINT32 Rsvd9 : 1;

18618

18619 /* Bits[9:9], Access Type=RO, default=None*/

18620

18621 /* Reserved */

18622 UINT32 Lma : 1;

18623

18624 /* Bits[10:10], Access Type=RW, default=0x00000000*/

18625

18626 /* Long Mode Active */

18627 UINT32 Nxe : 1;

18628

18629 /* Bits[11:11], Access Type=RW, default=0x00000000*/

18630

18631 /* Enable No-Execute Mode */

18632 UINT32 Rsvd12 : 20;

18633

18634 /* Bits[31:12], Access Type=RO, default=None*/

18635

18636 /* Reserved */

18637

18638 } Bits;

18639

18640 UINT32 Uint32;

18641 UINT64 Uint64;

18642

18643 } MSR_IA32_CR_EFER_REGISTER;

18644

18645 /**

18646 SYSCALL/SYSRET selectors and legacy SYSCALL target EIP

18647 **/

18648 #define MSR_STAR 0xC0000081

18649

18650 typedef union {

18651 ///

18652 /// Individual bit fields

18653 ///

18654 struct {

18655 UINT32 SyscallTargetEip : 32;

18656

18657 /* Bits[31:0], Access Type=RW, default=0x00000000*/

18658

18659 /* Legacy SYSCALL target EIP */

18660 UINT32 SyscallCsSs : 16;

18661

18662 /* Bits[47:32], Access Type=RW, default=0x00000000*/

18663

18664 /* SYSCALL CS/SS Selector */

18665 UINT32 SysretCsSs : 16;

18666

18667 /* Bits[63:48], Access Type=RW, default=0x00000000*/

18668

18669 /* SYSRET CS/SS Selector */

18670

18671 } Bits;

18672

18673 UINT32 Uint32;

18674 UINT64 Uint64;

18675

18676 } MSR_STAR_REGISTER;

18677 /**

18678 64-bit-mode SYSCALL target RIP

18679 **/

18680 #define MSR_LSTAR 0xC0000082

18681 /**

18682 MSR for compatibility-mode SYSCALL target RIP

18683 **/

18684 #define MSR_CSTAR 0xC0000083

18685 /**

18686 SYSCALL flag mask

18687 **/

18688 #define MSR_SFMASK 0xC0000084

18689 /**

18690 FS base MSR

18691 **/

18692 #define MSR_FS_BASE 0xC0000100

18693 /**

18694 GS base MSR

18695 **/

18696 #define MSR_GS_BASE 0xC0000101

18697 /**

18698 Swap Target of BASE Address of GS.

18699 **/

18700 #define MSR_KERNEL_GSBASE 0xC0000102

18701 /**

18702 Time-stamp counter auxilliary field

18703 **/

18704 #define MSR_TSC_AUX 0xC0000103

18705 #endif /* _ARCHMSR_h */

Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by 1.8.20


AlderLake Firmware Support Package (FSP): AsfMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
AsfMsgs.h File Reference

AMT/ASF Messages. More...

#include <AmthiMsgs.h>
#include <Pi/PiStatusCode.h>
#include <IndustryStandardAsf.h>
#include <IntelAsfExtensions.h>
Include dependency graph for AsfMsgs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | ASF_MESSAGE_HEADER
Abstract ASF message header. More...
struct | ASF_START_WDT
Start Watchdog Timer Message Structure. More...
struct | ASF_STOP_WDT
Stop Watchdog Timer Message Structure. More...
struct | CLEAR_BOOT_OPTIONS
Clear Boot Options Message Structure. More...
struct | ASF_BOOT_OPTIONS
Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message. More...
struct | GET_BOOT_OPTIONS_RESPONSE
Get Boot Options Response Structure. More...
struct | GET_BOOT_OPTIONS
Get Boot Options Request Structure. More...
union | GET_BOOT_OPTIONS_BUFFER
Get Boot Options Union Buffer. More...
struct | GET_RSE_PASSWORD_RESPONSE
Get RSE Password Response Structure. More...
struct | GET_RSE_PASSWORD
Get RSE Password Request Structure. More...
union | GET_RSE_PASSWORD_BUFFER
Get RSE Password Union Buffer. More...
struct | REPORT_BIOS_STATUS
Report BIOS Status. More...
struct | ASF_MESSAGE
ASF Message. More...
struct | HECI_ASF_PUSH_PROGRESS_CODE
ASF Push Progress Code. More...
struct | ASF_FRAMEWORK_MESSAGE
ASF Framework Message. More...
struct | ASF_DATA_HUB_MAP
Data Hub of ASF Progress Status. More...
struct | PET_ALERT
Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert. More...
struct | AMT_SET_ACTIVE_LAN_INTERFACE
Set Active LAN Interface Request Structure. More...
struct | AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE
Set Active LAN Interface Response Structure. More...
union | AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER
Set Active LAN Interface Union Buffer. More...
struct | AMT_GET_ACTIVE_LAN_INTERFACE
Get Active LAN Interface Request Structure. More...
struct | AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
Get Active LAN Interface Response Structure. More...
union | AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER
Get Active LAN Interface Union Buffer. More...
struct | AMT_QUERY_KVM_RESPONSE
Query KVM Response Structure. More...
struct | AMT_QUERY_KVM
Query KVM Request Structure. More...
union | AMT_QUERY_KVM_BUFFER
Query KVM Union Buffer. More...
struct | AMT_SET_MAC_PASSTHROUGH_RESPONSE
Set MAC Passthrough. More...
union | AMT_SET_MAC_PASSTHROUGH_BUFFER
Set MAC Passthrough Buffer. More...

Macros

#define | ASF_START_BIOS_WDT 0
Start Watchdog Timer Type.
#define | KVM_STALL_1_SECOND 1000000
AMT Query KVM timer related definition. More...
#define | KVM_MAX_WAIT_TIME (60 * 8)
8 Mins

Enumerations

enum | RESPONSE_CODE
Query KVM Response Type.
enum | QUERY_TYPE
Query KVM Type.

Detailed Description

AMT/ASF Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AsfMsgs.h.

Macro Definition Documentation

◆ KVM_STALL_1_SECOND

#define KVM_STALL_1_SECOND 1000000

AMT Query KVM timer related definition.

Stall 1 second

Definition at line 680 of file AsfMsgs.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AsfMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
AsfMsgs.h
Go to the documentation of this file.
1 /** @file
2 AMT/ASF Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ASF_MSGS_H_
37 #define _ASF_MSGS_H_
38
39 #include <AmthiMsgs.h>
40 #include <Pi/PiStatusCode.h>
41 #include <IndustryStandardAsf.h>
42 #include <IntelAsfExtensions.h>
43
44 #pragma pack(1)
45
46
47 //
48 // Calculates Byte count of ASF MESSAGE structure
49 //
50 #define ASF_MESSAGE_BYTE_COUNT(a) (a-2)
51
52 //
53 // Always define the whole ASF message structure so you can use the macro for ByteCount calculation
54 //
55 #define ASF_MESSAGE_BYTE_COUNT_MAP(a) (ASF_MESSAGE_BYTE_COUNT(sizeof(a)))
56
57 ///
58 /// Abstract ASF message header. This header is part of HECI message sent from BIOS to AMT/ASF ME Client
59 ///
60 typedef union {
61 UINT32 Data;
62 struct {
63 UINT32 Command : 8; ///< ASF Message Command.
64 UINT32 ByteCount : 8; ///< ASF Message Bytes Count Beyond This Byte.
65 UINT32 SubCommand : 8; ///< ASF Message Sub-command.
66 UINT32 VersionNumber : 8; ///< ASF Specification Version.
67 } Fields;
68 } ASF_MESSAGE_HEADER;
69
70 //
71 // Management Control Command Definitions
72 //
73
74 ///
75 /// Start Watchdog Timer Type
76 ///
77 #define ASF_START_BIOS_WDT 0
78 #define ASF_START_OS_WDT 1
79
80 ///
81 /// Start Watchdog Timer Message Structure.
82 /// This structure is only used for Starting Watchdog Timer Message.
83 /// Elements' description is based on Start Watchdog Timer.
84 ///
85 typedef struct {
86 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
87 UINT8 TimeoutLow; ///< Low byte of watchdog timeout value in seconds.
88 UINT8 TimeoutHigh; ///< High byte of watchdog timeout value in seconds.
89 UINT8 EventSensorType; ///< Default value is 0x23 to indicate it is for Watchdog 2.
90 UINT8 EventType; ///< Default value is 0x6F to indicate it is Sensor specific.
91 UINT8 EventOffset; ///< Default value is 0x00 to indicate it is for Timer expired.
92 /**
93 Class of device or type of software that originated the event.
94 0x00: Platform firmware
95 0x48: OS vendor
96 **/
97 UINT8 EventSourceType;
98 UINT8 EventSeverity; ///< Default value is 0x10 to indicate it is Critical.
99 UINT8 SensorDevice; ///< Default value is 0xFF to indicate it is Unspecified.
100 UINT8 SensorNumber; ///< Default value is 0xFF to indicate it is Unspecified.
101 UINT8 Entity; ///< Default value is 0x00 to indicate it is Unspecified.
102 UINT8 EntityInstance; ///< Default value is 0x00 to indicate it is Unspecified.
103 /**
104 Additional parametric data byte.
105 BYTE 0: 0x40
106 BYTE 1: 0x02, BIOS POST WDT Timeout
107 0x04, OS WDT Timeout
108 BYTE 2-4: Not defined.
109 **/
110 UINT8 EventData[5];
111 } ASF_START_WDT;
112
113 ///
114 /// Stop Watchdog Timer Message Structure
115 ///
116 typedef struct {
117 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
118 } ASF_STOP_WDT;
119
120
121 //
122 // ASF Configuration Command Definitions
123 //
124
125 ///
126 /// Clear Boot Options Message Structure
127 ///
128 typedef struct {
129 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
130 } CLEAR_BOOT_OPTIONS;
131
132 ///
133 /// Return Boot Options
134 /// Elements' description is based on Get Boot Options and No Boot Options Message.
135 ///
136 typedef struct {
137 /**
138 ASF Message Sub-command.
139 0x16: Return boot option
140 0x17: No boot option
141 **/
142 UINT8 SubCommand;
143 UINT8 Version; ///< Default value is 0x10 to indicate ASF Specification Version.
144 /**
145 IANA-assigned Enterprise Number.
146 0x000011BE: IANA Enterprise Number for ASF
147 0x00000157: IANA Enterprise Number for Intel
148 **/
149 UINT32 IanaId;
150 /**
151 Defines commands to be processed by the managed client on the boot initiated by the ASF-RMCP message.
152 0x00: NOP
153 0x01: Force PXE Boot
154 0x02: Force Hard-drive Boot
155 0x03: Force Hard-drive Safe Mode Boot
156 0x04: Force Diagnostic Boot
157 0x05: Force CD/DVD Boot
158 0x06-0xBF: Reserved
159 0xC0-0xFF: OEM special commands
160 0xC1: Intel special command
161 **/
162 UINT8 SpecialCommand;
163 UINT8 SpecialCommandParamHighByte; ///< Defines a command parameter to augment the Special Command High Byte.
164 UINT8 SpecialCommandParamLowByte; ///< Defines a command parameter to augment the Special Command Low Byte.
165 UINT8 BootOptionsMaskByte1; ///< Defines a standard set of firmware operations.
166 UINT8 BootOptionsMaskByte2; ///< Defines a standard set of firmware operations.
167 UINT8 OemParameterByte1; ///< Defines parameters that further augment the Special Command definition.
168 UINT8 OemParameterByte2; ///< Defines parameters that further augment the Special Command definition.
169 } ASF_BOOT_OPTIONS;
170
171 ///
172 /// Get Boot Options Response Structure
173 ///
174 typedef struct {
175 UINT8 Command; ///< ASF Message Command.
176 UINT8 ByteCount; ///< ASF Message Bytes Count Beyond This Byte.
177 ASF_BOOT_OPTIONS AsfBootOptions; ///< ASF Return Boot Options.
178 } GET_BOOT_OPTIONS_RESPONSE;
179
180 ///
181 /// Get Boot Options Request Structure
182 ///
183 typedef struct {
184 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
185 } GET_BOOT_OPTIONS;
186
187 ///
188 /// Get Boot Options Union Buffer
189 ///
190 typedef union {
191 GET_BOOT_OPTIONS Request;
192 GET_BOOT_OPTIONS_RESPONSE Response;
193 } GET_BOOT_OPTIONS_BUFFER;
194
195 //
196 // Get Remote Secure Erase Password
197 //
198
199 #define RSE_PASSWORD_MAX_LENGTH 32
200
201 ///
202 /// Get RSE Password Response Structure
203 ///
204 typedef struct {
205 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
206 UINT16 PasswordLength; ///< Password length in bytes.
207 CHAR8 Password[RSE_PASSWORD_MAX_LENGTH]; ///< RSE Password.
208 } GET_RSE_PASSWORD_RESPONSE;
209
210 ///
211 /// Get RSE Password Request Structure
212 ///
213 typedef struct {
214 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
215 } GET_RSE_PASSWORD;
216
217 ///
218 /// Get RSE Password Union Buffer
219 ///
220 typedef union {
221 GET_RSE_PASSWORD Request;
222 GET_RSE_PASSWORD_RESPONSE Response;
223 } GET_RSE_PASSWORD_BUFFER;
224
225 ///
226 /// Report BIOS Status
227 ///
228 typedef struct {
229 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
230 union {
231 struct {
232 /**
233 Current BIOS Status.
234 0: Success
235 1: In Progress
236 2: Not reported
237 0xFFFF: Failed
238 **/
239 UINT16 BiosStatus;
240 /**
241 The Reason Causes Current BIOS Status.
242 0: BiosStatus is Success/InProgress
243 1: General Drive Failure
244 2: Drive Password/Authentication Failure
245 3: Feature is not supported
246 **/
247 UINT16 StatusCause;
248 } Field;
249 UINT32 Data;
250 } AsfBiosStatus;
251 } REPORT_BIOS_STATUS;
252
253 //
254 // AMT Boot Control Structure
255 //
256 typedef union {
257 // Individual bit fields
258 struct {
259 UINT32 Reserved : 1; ///< [0] Reserved
260 UINT32 AmtTrigBootToHttps : 1; ///< [1] AMT can trigger Https Boot
261 UINT32 AmtTrigBootToPba : 1; ///< [2] AMT can trigger PBA Boot
262 UINT32 AmtTrigBootToWinRe : 1; ///< [3] AMT can trigger WinRe Boot
263 UINT32 AmtAllowedToDisSecureBoot : 1; ///< [4] AMT is allowed to disable secure boot
264 UINT32 WifiProfileSync : 1; ///< [5] Wifi Profile Sync
265 UINT32 BiosPasswordAuthRequired : 1; ///< [6] BIOS password authorization required
266 UINT32 Reserved1 : 1; ///< [7] Reserved
267 UINT32 RemotePlatformErase : 1; ///< [8] Remote Platform Erase
268 UINT32 Reserved2 : 23; ///< [31:9] Reserved
269 } Bits;
270
271 UINT32 Uint32;
272
273 } AMT_BOOT_CONTROL;
274
275 //
276 // Set UEFI Boot Options State Message Structure
277 //
278 typedef struct {
279 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
280 AMT_BOOT_CONTROL AmtBootControl; ///< AMT Boot Control
281 } SET_UEFI_BOOT_OPTIONS_STATE;
282
283 //
284 // Set UEFI Boot Options State Response Structure
285 //
286 typedef struct {
287 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
288 AMT_STATUS Status; ///< AMT Status
289 } SET_UEFI_BOOT_OPTIONS_STATE_RESPONSE;
290
291 //
292 // Set UEFI Boot Options State Union Buffer
293 //
294 typedef union {
295 SET_UEFI_BOOT_OPTIONS_STATE Request;
296 SET_UEFI_BOOT_OPTIONS_STATE_RESPONSE Response;
297 } SET_UEFI_BOOT_OPTIONS_STATE_BUFFER;
298
299 //
300 // Get UEFI Boot Options State Structure
301 //
302 typedef struct {
303 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
304 } GET_UEFI_BOOT_OPTIONS_STATE;
305
306 //
307 // Get UEFI Boot Options State Response Structure
308 //
309 typedef struct {
310 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
311 AMT_BOOT_CONTROL AmtBootControl; ///< AMT Boot Control
312 } GET_UEFI_BOOT_OPTIONS_STATE_RESPONSE;
313
314 //
315 // Get UEFI Boot Options State Union Buffer
316 //
317 typedef union {
318 GET_UEFI_BOOT_OPTIONS_STATE Request;
319 GET_UEFI_BOOT_OPTIONS_STATE_RESPONSE Response;
320 } GET_UEFI_BOOT_OPTIONS_STATE_BUFFER;
321
322 //
323 // Boot Options Types
324 //
325 typedef enum {
326 Https,
327 Pba,
328 WinRe
329 } BOOT_OPTION_TYPE;
330
331
332 // Max Description Length of UEFI Boot Option
333 #define MAX_UEFI_BOOT_OPTION_DESC_LENGTH 100
334
335 // Max Device Path Length of UEFI Boot Option
336 #define MAX_UEFI_BOOT_OPTION_DEV_PATH_LENGTH 300
337
338 // Max Number of UEFI Boot Options
339 #define MAX_UEFI_BOOT_OPTIONS 10
340
341 //
342 // UEFI Boot Option Stucture
343 //
344 typedef struct {
345 UINT32 UefiBootOptionType; ///< Type of UEFI Boot Option
346 UINT16 DescriptionLength; ///< Length of Description
347 UINT8 Description[MAX_UEFI_BOOT_OPTION_DESC_LENGTH]; ///< Description
348 UINT16 DevicePathLength; ///< Length of Device Path
349 UINT8 EfiDevicePath[MAX_UEFI_BOOT_OPTION_DEV_PATH_LENGTH]; ///< EFi Device Path
350 } UEFI_BOOT_OPTION;
351
352 //
353 // Update UEFI Boot Options Message Structure
354 //
355 typedef struct {
356 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
357 UINT16 NumOfUefiBootOptions; ///< Number of UEFI Boot Options
358 UEFI_BOOT_OPTION UefiBootOptions[0]; ///< UEFI Boot Options
359 } UPDATE_UEFI_BOOT_OPTIONS;
360
361 //
362 // Update UEFI Boot Options Response Structure
363 //
364 typedef struct {
365 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
366 AMT_STATUS Status; ///< AMT Status
367 } UPDATE_UEFI_BOOT_OPTIONS_RESPONSE;
368
369 //
370 // Update UEFI Boot Options Union Buffer
371 //
372 typedef union {
373 UPDATE_UEFI_BOOT_OPTIONS Request;
374 UPDATE_UEFI_BOOT_OPTIONS_RESPONSE Response;
375 } UPDATE_UEFI_BOOT_OPTIONS_BUFFER;
376
377 //
378 // Get UEFI Boot Parameters Message structure
379 //
380 typedef struct {
381 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
382 UINT32 Nonce; ///< Nonce
383 } GET_UEFI_BOOT_PARAMETERS;
384
385
386 // Max Size of UEFI Boot Parameter Array
387 #define MAX_UEFI_BOOT_PARAMETERS_ARRAY_SIZE 1024
388
389 //
390 // UEFI Boot Parameter Option Strcuture
391 //
392 typedef struct {
393 UINT32 UefiBootOptionType; ///< Type of UEFI Boot Option
394 UINT16 EfiDevicePathLen; ///< Length of EFI Device Path
395 UINT8 EfiDevicePath[MAX_UEFI_BOOT_OPTION_DEV_PATH_LENGTH]; ///< EFI Device Path
396 UINT32 NumberOfParams; ///< Number of Parameters
397 UINT32 LengthOfParamsArray; ///< Length of Parameter Array
398 UINT8 ParametersArray[MAX_UEFI_BOOT_PARAMETERS_ARRAY_SIZE]; ///< Parameter Array
399 } UEFI_BOOT_OPTION_PARAMETER;
400
401 //
402 // Get UEFI Boot Parameters Response structure
403 //
404 typedef struct {
405 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
406 UINT32 Nonce; ///< Nonce
407 UEFI_BOOT_OPTION_PARAMETER UefiBootOptionWithParams; ///< Uefi Boot Option Parameters
408 } GET_UEFI_BOOT_OPTION_PARAMETERS_RESPONSE;
409
410 //
411 // Get UEFI Boot Parameters Union Buffer
412 //
413 typedef union {
414 GET_UEFI_BOOT_PARAMETERS Request;
415 GET_UEFI_BOOT_OPTION_PARAMETERS_RESPONSE Response;
416 } GET_UEFI_BOOT_OPTION_PARAMETERS_BUFFER;
417
418 //
419 // Get Root Certificate Authority(CA) Certificate Message structure
420 //
421 typedef struct {
422 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
423 UINT32 Nonce; ///< Nonce
424 UINT32 RootCACertIndex; ///< Index of Root CA Certificate
425 } GET_ROOT_CA_CERTIFICATE;
426
427 // Max Number of Root Certificate Authority(CA) Certificate
428 #define MAX_NUM_ROOT_CA_CERTIFICATE 4
429
430 // Max Size of a Root Certificate Authority(CA) Certificate
431 #define MAX_ROOT_CA_CERTIFICATE_SIZE 4100
432
433 //
434 // Root Certificate Authority(CA) Certificate Stucture
435 //
436 typedef struct {
437 UINT32 CertSize; ///< Size of Certificate
438 UINT8 Cert[MAX_ROOT_CA_CERTIFICATE_SIZE]; ///< Certificate
439 UINT32 LastCert; ///< Is this the Last Certificate
440 } ROOT_CA_CERTIFICATE;
441
442 //
443 // Get Root Certificate Authority(CA) Certificate Response structure
444 //
445 typedef struct {
446 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
447 UINT32 Nonce; ///< Nonce
448 ROOT_CA_CERTIFICATE Cert; ///< Root CA Certificate
449 } GET_ROOT_CA_CERTIFICATE_RESPONSE;
450
451 //
452 // Get Root CA Certificate Union Buffer
453 //
454 typedef union {
455 GET_ROOT_CA_CERTIFICATE Request;
456 GET_ROOT_CA_CERTIFICATE_RESPONSE Response;
457 } GET_ROOT_CA_CERTIFICATE_BUFFER;
458
459 //
460 // Messaging Command Definitions
461 //
462
463 ///
464 /// ASF Message
465 ///
466 typedef struct {
467 UINT8 SubCommand; ///< ASF Message Sub-command.
468 UINT8 Version; ///< ASF Specification Version.
469 UINT8 EventSensorType; ///< The Event Sensor Type field indicates what types of events the sensor is monitoring.
470 UINT8 EventType; ///< Code indicating what type of transition/state change triggered the trap.
471 UINT8 EventOffset; ///< Indicates which particular event occurred for a given Event Type.
472 UINT8 EventSourceType; ///< Class of device or type of software that originated the event.
473 UINT8 EventSeverity; ///< Severity of the event.
474 UINT8 SensorDevice; ///< Identifies the instance of the device that holds the sensor that generated the event.
475 UINT8 SensorNumber; ///< Identify a given instance of a sensor relative to the Sensor Device.
476 UINT8 Entity; ///< Indicates the platform entity the event is associated with.
477 UINT8 EntityInstance; ///< Indicates which instance of the Entity the event is for.
478 UINT8 EventData1; ///< Additional parametric data 1.
479 UINT8 EventData2; ///< Additional parametric data 2.
480 } ASF_MESSAGE;
481
482 ///
483 /// ASF Push Progress Code
484 ///
485 typedef struct {
486 UINT8 Command; ///< ASF Message Command.
487 UINT8 ByteCount; ///< ASF Message Bytes Count Beyond This Byte.
488 ASF_MESSAGE AsfMessage; ///< ASF Message Instance.
489 UINT8 EventData[3]; ///< Additional parametric data.
490 } HECI_ASF_PUSH_PROGRESS_CODE;
491
492 ///
493 /// ASF Framework Message
494 ///
495 typedef struct {
496 ASF_FRAMEWORK_MESSAGE_TYPE MessageType; ///< ASF Message Type.
497 ASF_MESSAGE Message; ///< ASF Message Instance.
498 } ASF_FRAMEWORK_MESSAGE;
499
500 ///
501 /// Data Hub of ASF Progress Status
502 ///
503 typedef struct {
504 ASF_FRAMEWORK_MESSAGE_TYPE MessageType; ///< ASF Message Type.
505 EFI_STATUS_CODE_VALUE StatusCodeValue; ///< Platform Progress Status Code.
506 } ASF_DATA_HUB_MAP;
507
508 ///
509 /// Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert.
510 /// This structure is used for sending Remote Secure Erase / Boot Audit Entry PET Message.
511 /// Elements' description is based on Remote Secure Erase / Boot Audit Entry.
512 ///
513 typedef struct {
514 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
515 UINT8 EventSensorType; ///< Default value is 0x0F to indicate it is Firmware progress/error type.
516 UINT8 EventType; ///< Default value is 0x6F to indicate it is Sensor specific.
517 /**
518 Indicates which particular event occurred for a given Event Type.
519 For Remote Secure Erase:
520 0x03: OEM specific firmware error
521 0x05: OEM specific firmware progress
522 For Boot Audit Entry:
523 0x00: System Firmware Error
524 0x01: System Firmware Hang
525 0x02: System Firmware In Progress
526 **/
527 UINT8 EventOffset;
528 UINT8 EventSourceType; ///< Default value is 0x68 to indicate it is ASF 1.0.
529 /**
530 Severity of the event.
531 0x01: Monitor
532 0x02: Information
533 0x04: Ok
534 0x08: Non-critical
535 0x10: Critical
536 0x20: Non-Recoverable
537 **/
538 UINT8 EventSeverity;
539 UINT8 SensorDevice; ///< Default value is 0xFF to indicate it is Unspecified.
540 UINT8 Sensornumber; ///< Default value is 0xFF to indicate it is Unspecified.
541 /**
542 Indicates the platform device or subsystem associated with the event.
543 0x00: Unspecified
544 0x01: Other
545 0x02: Unknown
546 0x03: Processor
547 0x04: Disk
548 0x05: Peripheral
549 0x07: System Board
550 0x0A: Power Supply
551 0x0B: Add-in Card
552 0x20: Memory
553 0x22: BIOS
554 0x23: OS
555 **/
556 UINT8 Entity;
557 /**
558 Identifies which unique device is associated with the event when a system includes multiple device instances.
559 For Remote Secure Erase:
560 0xFF: Unspecified
561 For Boot Audit Entry:
562 0x00: Unspecified
563 **/
564 UINT8 EntityInstance;
565 /**
566 The Event Type determines the Event Data.
567 For Remote Secure Erase:
568 0xAA: Indicate EventData 2-5 set by OEM specification.
569 For Boot Audit Entry:
570 0x40: EventData 2 conforms ASF spec.
571 0xAA: Indicate EventData 2-5 set by OEM specification.
572 **/
573 UINT8 EventData1;
574 /**
575 Additional Event Data 2.
576 For Remote Secure Erase:
577 0x20: Indicate it is for Remote Secure Erase.
578 For Boot Audit Entry:
579 0x13: Performing system boot.
580 **/
581 UINT8 EventData2;
582 /**
583 Additional Event Data 3.
584 For Remote Secure Erase:
585 Success Case: 0x00 - Secure erase success
586 Failure Case: 0x01 - General failure
587 0x02 - Drive authentication failure
588 0x03 - Feature is not supported
589 0x04 - 0XFF - Reserved
590 For Boot Audit Entry (Boot Device Not Changed):
591 00: Not used.
592 For Boot Audit Entry (Boot Device Changed):
593 N/A: Most recent BAE queue entry.
594 **/
595 UINT8 EventData3;
596 /**
597 Additional Event Data 4.
598 For Remote Secure Erase:
599 N/A: Not used.
600 For Boot Audit Entry (Boot Device Not Changed):
601 N/A: Not used.
602 For Boot Audit Entry (Boot Device Changed):
603 N/A: Next most recent BAE queue entry.
604 **/
605 UINT8 EventData4;
606 /**
607 Additional Event Data 5.
608 For Remote Secure Erase:
609 N/A: Not used.
610 For Boot Audit Entry (Boot Device Not Changed):
611 N/A: Not used.
612 For Boot Audit Entry (Boot Device Changed):
613 N/A: Oldest BAE queue entry.
614 **/
615 UINT8 EventData5;
616 } PET_ALERT;
617
618 //
619 // LAN Command Definitions
620 //
621
622 ///
623 /// Set Active LAN Interface Request Structure
624 ///
625 typedef struct {
626 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
627 UINT8 ActiveInterface; ///< 0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.
628 } AMT_SET_ACTIVE_LAN_INTERFACE;
629
630 ///
631 /// Set Active LAN Interface Response Structure
632 ///
633 typedef struct {
634 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
635 UINT32 Status; ///< Response status.
636 } AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE;
637
638 ///
639 /// Set Active LAN Interface Union Buffer
640 ///
641 typedef union {
642 AMT_SET_ACTIVE_LAN_INTERFACE Request;
643 AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE Response;
644 } AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER;
645
646
647 ///
648 /// Get Active LAN Interface Request Structure
649 ///
650 typedef struct {
651 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
652 } AMT_GET_ACTIVE_LAN_INTERFACE;
653
654 ///
655 /// Get Active LAN Interface Response Structure
656 ///
657 typedef struct {
658 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
659 UINT32 Status; ///< Response status.
660 UINT8 ActiveInterface; ///< 0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.
661 UINT32 Reserved[4]; ///< Reserved for future use.
662 } AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE;
663
664 ///
665 /// Get Active LAN Interface Union Buffer
666 ///
667 typedef union {
668 AMT_GET_ACTIVE_LAN_INTERFACE Request;
669 AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE Response;
670 } AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER;
671
672
673 //
674 // KVM Command Definitions
675 //
676
677 ///
678 /// AMT Query KVM timer related definition
679 ///
680 #define KVM_STALL_1_SECOND 1000000 ///< Stall 1 second
681 #define KVM_MAX_WAIT_TIME (60 * 8) ///< 8 Mins
682
683 ///
684 /// Query KVM Response Type
685 ///
686 typedef enum {
687 KvmSessionEstablished = 1,
688 KvmSessionCancelled
689 } RESPONSE_CODE;
690
691 ///
692 /// Query KVM Response Structure
693 ///
694 typedef struct {
695 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
696 /**
697 Response Code of KVM Session Status.
698 0x01: the KVM session established
699 0x02: the KVM session cancelled
700 **/
701 UINT32 ResponseCode;
702 } AMT_QUERY_KVM_RESPONSE;
703
704 ///
705 /// Query KVM Type
706 ///
707 typedef enum {
708 QueryRequest = 0,
709 CancelRequest
710 } QUERY_TYPE;
711
712 ///
713 /// Query KVM Request Structure
714 ///
715 typedef struct {
716 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
717 /**
718 KVM Session Query Type.
719 0x00: Query the KVM session request
720 0x01: Cancel the KVM session request
721 **/
722 UINT32 QueryType;
723 } AMT_QUERY_KVM;
724
725 ///
726 /// Query KVM Union Buffer
727 ///
728 typedef union {
729 AMT_QUERY_KVM Request;
730 AMT_QUERY_KVM_RESPONSE Response;
731 } AMT_QUERY_KVM_BUFFER;
732
733 //
734 // MAC Command Definitions
735 //
736
737 ///
738 /// Set MAC Passthrough
739 ///
740 typedef struct {
741 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
742 UINT32 Status;
743 } AMT_SET_MAC_PASSTHROUGH_RESPONSE;
744
745 #define MAC_ADDRESS_SIZE 6
746
747 typedef struct {
748 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header.
749 UINT8 Enabled;
750 UINT8 MacAddress[MAC_ADDRESS_SIZE];
751 } AMT_SET_MAC_PASSTHROUGH;
752
753 ///
754 /// Set MAC Passthrough Buffer
755 ///
756 typedef union {
757 AMT_SET_MAC_PASSTHROUGH Request;
758 AMT_SET_MAC_PASSTHROUGH_RESPONSE Response;
759 } AMT_SET_MAC_PASSTHROUGH_BUFFER;
760
761 #pragma pack()
762
763 #endif // _ASF_MSGS_H
AMT_SET_MAC_PASSTHROUGH_BUFFER
Set MAC Passthrough Buffer.
Definition: AsfMsgs.h:756
ASF_BOOT_OPTIONS::BootOptionsMaskByte2
UINT8 BootOptionsMaskByte2
Defines a standard set of firmware operations.
Definition: AsfMsgs.h:166
CLEAR_BOOT_OPTIONS::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:129
AmthiMsgs.h
AMTHI Messages.
ASF_MESSAGE_HEADER::Command
UINT32 Command
ASF Message Command.
Definition: AsfMsgs.h:63
ASF_MESSAGE::SubCommand
UINT8 SubCommand
ASF Message Sub-command.
Definition: AsfMsgs.h:467
ASF_MESSAGE_HEADER::SubCommand
UINT32 SubCommand
ASF Message Sub-command.
Definition: AsfMsgs.h:65
ASF_MESSAGE::EntityInstance
UINT8 EntityInstance
Indicates which instance of the Entity the event is for.
Definition: AsfMsgs.h:477
AMT_STATUS
AMT_STATUS
AMT Status Enum.
Definition: AmthiMsgs.h:46
ASF_MESSAGE::EventSeverity
UINT8 EventSeverity
Severity of the event.
Definition: AsfMsgs.h:473
REPORT_BIOS_STATUS::BiosStatus
UINT16 BiosStatus
Current BIOS Status.
Definition: AsfMsgs.h:239
ASF_MESSAGE_HEADER::VersionNumber
UINT32 VersionNumber
ASF Specification Version.
Definition: AsfMsgs.h:66
AMT_SET_ACTIVE_LAN_INTERFACE_BUFFER
Set Active LAN Interface Union Buffer.
Definition: AsfMsgs.h:641
ASF_START_WDT::EntityInstance
UINT8 EntityInstance
Default value is 0x00 to indicate it is Unspecified.
Definition: AsfMsgs.h:102
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE::ActiveInterface
UINT8 ActiveInterface
0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.
Definition: AsfMsgs.h:660
ASF_START_WDT::EventSensorType
UINT8 EventSensorType
Default value is 0x23 to indicate it is for Watchdog 2.
Definition: AsfMsgs.h:89
PET_ALERT::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:514
GET_RSE_PASSWORD
Get RSE Password Request Structure.
Definition: AsfMsgs.h:213
ASF_START_WDT::EventType
UINT8 EventType
Default value is 0x6F to indicate it is Sensor specific.
Definition: AsfMsgs.h:90
AMT_QUERY_KVM_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:695
ASF_DATA_HUB_MAP
Data Hub of ASF Progress Status.
Definition: AsfMsgs.h:503
AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:634
ASF_BOOT_OPTIONS::SpecialCommandParamHighByte
UINT8 SpecialCommandParamHighByte
Defines a command parameter to augment the Special Command High Byte.
Definition: AsfMsgs.h:163
AMT_QUERY_KVM_RESPONSE::ResponseCode
UINT32 ResponseCode
Response Code of KVM Session Status.
Definition: AsfMsgs.h:701
ASF_DATA_HUB_MAP::MessageType
ASF_FRAMEWORK_MESSAGE_TYPE MessageType
ASF Message Type.
Definition: AsfMsgs.h:504
GET_RSE_PASSWORD_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:205
HECI_ASF_PUSH_PROGRESS_CODE
ASF Push Progress Code.
Definition: AsfMsgs.h:485
GET_RSE_PASSWORD_BUFFER
Get RSE Password Union Buffer.
Definition: AsfMsgs.h:220
ASF_MESSAGE::Version
UINT8 Version
ASF Specification Version.
Definition: AsfMsgs.h:468
PET_ALERT::EventSourceType
UINT8 EventSourceType
Default value is 0x68 to indicate it is ASF 1.0.
Definition: AsfMsgs.h:528
ASF_MESSAGE_HEADER::ByteCount
UINT32 ByteCount
ASF Message Bytes Count Beyond This Byte.
Definition: AsfMsgs.h:64
AMT_QUERY_KVM::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:716
AMT_QUERY_KVM_BUFFER
Query KVM Union Buffer.
Definition: AsfMsgs.h:728
ASF_MESSAGE::EventData2
UINT8 EventData2
Additional parametric data 2.
Definition: AsfMsgs.h:479
GET_BOOT_OPTIONS::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:184
ASF_BOOT_OPTIONS::Version
UINT8 Version
Default value is 0x10 to indicate ASF Specification Version.
Definition: AsfMsgs.h:143
AMT_QUERY_KVM::QueryType
UINT32 QueryType
KVM Session Query Type.
Definition: AsfMsgs.h:722
PET_ALERT::Sensornumber
UINT8 Sensornumber
Default value is 0xFF to indicate it is Unspecified.
Definition: AsfMsgs.h:540
ASF_START_WDT::EventSourceType
UINT8 EventSourceType
Class of device or type of software that originated the event.
Definition: AsfMsgs.h:97
ASF_BOOT_OPTIONS::IanaId
UINT32 IanaId
IANA-assigned Enterprise Number.
Definition: AsfMsgs.h:149
ASF_FRAMEWORK_MESSAGE::MessageType
ASF_FRAMEWORK_MESSAGE_TYPE MessageType
ASF Message Type.
Definition: AsfMsgs.h:496
ASF_START_WDT::SensorDevice
UINT8 SensorDevice
Default value is 0xFF to indicate it is Unspecified.
Definition: AsfMsgs.h:99
GET_RSE_PASSWORD_RESPONSE::PasswordLength
UINT16 PasswordLength
Password length in bytes.
Definition: AsfMsgs.h:206
ASF_MESSAGE
ASF Message.
Definition: AsfMsgs.h:466
AMT_QUERY_KVM
Query KVM Request Structure.
Definition: AsfMsgs.h:715
ASF_FRAMEWORK_MESSAGE
ASF Framework Message.
Definition: AsfMsgs.h:495
ASF_BOOT_OPTIONS::SpecialCommandParamLowByte
UINT8 SpecialCommandParamLowByte
Defines a command parameter to augment the Special Command Low Byte.
Definition: AsfMsgs.h:164
RESPONSE_CODE
RESPONSE_CODE
Query KVM Response Type.
Definition: AsfMsgs.h:686
ASF_START_WDT::EventOffset
UINT8 EventOffset
Default value is 0x00 to indicate it is for Timer expired.
Definition: AsfMsgs.h:91
ASF_MESSAGE::EventOffset
UINT8 EventOffset
Indicates which particular event occurred for a given Event Type.
Definition: AsfMsgs.h:471
AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE::Status
UINT32 Status
Response status.
Definition: AsfMsgs.h:635
GET_BOOT_OPTIONS_RESPONSE::AsfBootOptions
ASF_BOOT_OPTIONS AsfBootOptions
ASF Return Boot Options.
Definition: AsfMsgs.h:177
ASF_START_WDT::SensorNumber
UINT8 SensorNumber
Default value is 0xFF to indicate it is Unspecified.
Definition: AsfMsgs.h:100
GET_RSE_PASSWORD_RESPONSE
Get RSE Password Response Structure.
Definition: AsfMsgs.h:204
HECI_ASF_PUSH_PROGRESS_CODE::ByteCount
UINT8 ByteCount
ASF Message Bytes Count Beyond This Byte.
Definition: AsfMsgs.h:487
ASF_DATA_HUB_MAP::StatusCodeValue
EFI_STATUS_CODE_VALUE StatusCodeValue
Platform Progress Status Code.
Definition: AsfMsgs.h:505
ASF_START_WDT
Start Watchdog Timer Message Structure.
Definition: AsfMsgs.h:85
PET_ALERT::SensorDevice
UINT8 SensorDevice
Default value is 0xFF to indicate it is Unspecified.
Definition: AsfMsgs.h:539
PET_ALERT::EventData2
UINT8 EventData2
Additional Event Data 2.
Definition: AsfMsgs.h:581
ASF_STOP_WDT::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:117
ASF_MESSAGE::SensorDevice
UINT8 SensorDevice
Identifies the instance of the device that holds the sensor that generated the event.
Definition: AsfMsgs.h:474
GET_BOOT_OPTIONS_RESPONSE::Command
UINT8 Command
ASF Message Command.
Definition: AsfMsgs.h:175
PET_ALERT::EntityInstance
UINT8 EntityInstance
Identifies which unique device is associated with the event when a system includes multiple device in...
Definition: AsfMsgs.h:564
AMT_GET_ACTIVE_LAN_INTERFACE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:651
REPORT_BIOS_STATUS
Report BIOS Status.
Definition: AsfMsgs.h:228
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:658
IntelAsfExtensions.h
Include file for Intel Extended ASF definition.
ASF_MESSAGE::EventData1
UINT8 EventData1
Additional parametric data 1.
Definition: AsfMsgs.h:478
ASF_BOOT_OPTIONS::SubCommand
UINT8 SubCommand
ASF Message Sub-command.
Definition: AsfMsgs.h:142
AMT_GET_ACTIVE_LAN_INTERFACE
Get Active LAN Interface Request Structure.
Definition: AsfMsgs.h:650
GET_BOOT_OPTIONS_RESPONSE::ByteCount
UINT8 ByteCount
ASF Message Bytes Count Beyond This Byte.
Definition: AsfMsgs.h:176
PET_ALERT::EventOffset
UINT8 EventOffset
Indicates which particular event occurred for a given Event Type.
Definition: AsfMsgs.h:527
ASF_BOOT_OPTIONS
Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message.
Definition: AsfMsgs.h:136
REPORT_BIOS_STATUS::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:229
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE::Status
UINT32 Status
Response status.
Definition: AsfMsgs.h:659
ASF_START_WDT::Entity
UINT8 Entity
Default value is 0x00 to indicate it is Unspecified.
Definition: AsfMsgs.h:101
ASF_START_WDT::TimeoutLow
UINT8 TimeoutLow
Low byte of watchdog timeout value in seconds.
Definition: AsfMsgs.h:87
AMT_GET_ACTIVE_LAN_INTERFACE_BUFFER
Get Active LAN Interface Union Buffer.
Definition: AsfMsgs.h:667
AMT_QUERY_KVM_RESPONSE
Query KVM Response Structure.
Definition: AsfMsgs.h:694
AMT_GET_ACTIVE_LAN_INTERFACE_RESPONSE
Get Active LAN Interface Response Structure.
Definition: AsfMsgs.h:657
ASF_MESSAGE::EventSensorType
UINT8 EventSensorType
The Event Sensor Type field indicates what types of events the sensor is monitoring.
Definition: AsfMsgs.h:469
ASF_BOOT_OPTIONS::BootOptionsMaskByte1
UINT8 BootOptionsMaskByte1
Defines a standard set of firmware operations.
Definition: AsfMsgs.h:165
PET_ALERT::EventData4
UINT8 EventData4
Additional Event Data 4.
Definition: AsfMsgs.h:605
PET_ALERT::EventType
UINT8 EventType
Default value is 0x6F to indicate it is Sensor specific.
Definition: AsfMsgs.h:516
CLEAR_BOOT_OPTIONS
Clear Boot Options Message Structure.
Definition: AsfMsgs.h:128
HECI_ASF_PUSH_PROGRESS_CODE::Command
UINT8 Command
ASF Message Command.
Definition: AsfMsgs.h:486
ASF_FRAMEWORK_MESSAGE::Message
ASF_MESSAGE Message
ASF Message Instance.
Definition: AsfMsgs.h:497
PET_ALERT::EventSensorType
UINT8 EventSensorType
Default value is 0x0F to indicate it is Firmware progress/error type.
Definition: AsfMsgs.h:515
AMT_SET_MAC_PASSTHROUGH_RESPONSE
Set MAC Passthrough.
Definition: AsfMsgs.h:740
ASF_MESSAGE::EventType
UINT8 EventType
Code indicating what type of transition/state change triggered the trap.
Definition: AsfMsgs.h:470
ASF_MESSAGE::EventSourceType
UINT8 EventSourceType
Class of device or type of software that originated the event.
Definition: AsfMsgs.h:472
IndustryStandardAsf.h
Include file for Industry Standard ASF definition.
ASF_START_WDT::EventSeverity
UINT8 EventSeverity
Default value is 0x10 to indicate it is Critical.
Definition: AsfMsgs.h:98
PET_ALERT::EventData1
UINT8 EventData1
The Event Type determines the Event Data.
Definition: AsfMsgs.h:573
ASF_BOOT_OPTIONS::SpecialCommand
UINT8 SpecialCommand
Defines commands to be processed by the managed client on the boot initiated by the ASF-RMCP message.
Definition: AsfMsgs.h:162
AMT_SET_ACTIVE_LAN_INTERFACE
Set Active LAN Interface Request Structure.
Definition: AsfMsgs.h:625
AMT_SET_MAC_PASSTHROUGH_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:741
GET_BOOT_OPTIONS_RESPONSE
Get Boot Options Response Structure.
Definition: AsfMsgs.h:174
PET_ALERT::EventSeverity
UINT8 EventSeverity
Severity of the event.
Definition: AsfMsgs.h:538
ASF_STOP_WDT
Stop Watchdog Timer Message Structure.
Definition: AsfMsgs.h:116
ASF_MESSAGE_HEADER
Abstract ASF message header.
Definition: AsfMsgs.h:60
AMT_SET_ACTIVE_LAN_INTERFACE::ActiveInterface
UINT8 ActiveInterface
0:As defined in FIT; 1:Integrated LAN; 2:Discrete LAN.
Definition: AsfMsgs.h:627
GET_BOOT_OPTIONS
Get Boot Options Request Structure.
Definition: AsfMsgs.h:183
ASF_START_WDT::TimeoutHigh
UINT8 TimeoutHigh
High byte of watchdog timeout value in seconds.
Definition: AsfMsgs.h:88
REPORT_BIOS_STATUS::StatusCause
UINT16 StatusCause
The Reason Causes Current BIOS Status.
Definition: AsfMsgs.h:247
ASF_START_WDT::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:86
GET_BOOT_OPTIONS_BUFFER
Get Boot Options Union Buffer.
Definition: AsfMsgs.h:190
QUERY_TYPE
QUERY_TYPE
Query KVM Type.
Definition: AsfMsgs.h:707
AMT_SET_ACTIVE_LAN_INTERFACE_RESPONSE
Set Active LAN Interface Response Structure.
Definition: AsfMsgs.h:633
AMT_SET_ACTIVE_LAN_INTERFACE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:626
ASF_MESSAGE::SensorNumber
UINT8 SensorNumber
Identify a given instance of a sensor relative to the Sensor Device.
Definition: AsfMsgs.h:475
PET_ALERT
Platform Event Trap (PET) Alert To Indicate Which Event Causes The Alert.
Definition: AsfMsgs.h:513
GET_RSE_PASSWORD::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: AsfMsgs.h:214
ASF_MESSAGE::Entity
UINT8 Entity
Indicates the platform entity the event is associated with.
Definition: AsfMsgs.h:476
ASF_BOOT_OPTIONS::OemParameterByte1
UINT8 OemParameterByte1
Defines parameters that further augment the Special Command definition.
Definition: AsfMsgs.h:167
ASF_BOOT_OPTIONS::OemParameterByte2
UINT8 OemParameterByte2
Defines parameters that further augment the Special Command definition.
Definition: AsfMsgs.h:168
PET_ALERT::EventData3
UINT8 EventData3
Additional Event Data 3.
Definition: AsfMsgs.h:595
PET_ALERT::EventData5
UINT8 EventData5
Additional Event Data 5.
Definition: AsfMsgs.h:615
HECI_ASF_PUSH_PROGRESS_CODE::AsfMessage
ASF_MESSAGE AsfMessage
ASF Message Instance.
Definition: AsfMsgs.h:488
PET_ALERT::Entity
UINT8 Entity
Indicates the platform device or subsystem associated with the event.
Definition: AsfMsgs.h:556
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AsfProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros
AsfProtocol.h File Reference

Definition of Alert Standard Format (ASF) 2.0. More...

#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/AlertStandardFormatTable.h>
#include <AsfMsgs.h>
Include dependency graph for AsfProtocol.h:

Go to the source code of this file.

Classes

struct ALERT_STANDARD_FORMAT_PROTOCOL
Intel specific definitions end. More...

Macros

#define | ASF_BOOT_OPTIONS_PRESENT 0x16
Sub-Command Attributes.
#define | ASF_INDUSTRY_IANA 0x000011BE
ASF Internet Assigned Numbers Authority Manufacturer ID (The firmware sends 0XBE110000 for decimal value 4542)
#define | ASF_INDUSTRY_CONVERTED_IANA INTEL_IANA_SWAP32 (ASF_INDUSTRY_IANA)
0XBE110000, received from ME FW
#define | INTEL_IANA_SWAP32(x)
Intel specific definitions start. More...
#define | ASF_INTEL_CONVERTED_IANA INTEL_IANA_SWAP32 (ASF_INTEL_IANA)
0X57010000, received from ME
#define | ASF_INTEL_OEM_CMD 0xC1
Intel OEM Special Command.
#define | USE_SOL BIT0
Intel OEM Parameters Byte1 values. More...
#define | USE_STORAGE_REDIR BIT0
Intel Special Command Parameter Low byte values. More...
#define | ENFORCE_SECURE_BOOT BIT1
0000 0010 - bit 1 Enforce secure boot over Storage Redirection
#define | REFLASH_BIOS BIT2
0000 0100 - bit 2
#define | BIOS_SETUP BIT3
0000 1000 - bit 3
#define | BIOS_PAUSE BIT4
0001 0000 - bit 4
#define | USE_KVM BIT5
0010 0000 - bit 5
#define | ENABLE_SECURE_ERASE BIT6
0100 0000 - bit 6
#define | ENABLE_REMOTE_PLATFORM_ERASE BIT7
1000 0000 - bit 7
#define | STORAGE_REDIRECTION_BOOT_DEVICE_MASK (BIT1 | BIT0)
Intel Special Command Parameter High byte values. More...

Detailed Description

Definition of Alert Standard Format (ASF) 2.0.

Copyright
INTEL CONFIDENTIAL Copyright 2005 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file AsfProtocol.h.

Macro Definition Documentation

◆ INTEL_IANA_SWAP32

#define INTEL_IANA_SWAP32 ( x )
Value:
((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | \
(((x) & 0xff0000) >> 8) | (((x) & 0xff000000) >> 24))

Intel specific definitions start.

Intel Internet Assigned Numbers Authority Manufacturer ID (The firmware sends 0x57010000 for decimal value 343)

Definition at line 69 of file AsfProtocol.h.

◆ STORAGE_REDIRECTION_BOOT_DEVICE_MASK

#define STORAGE_REDIRECTION_BOOT_DEVICE_MASK (BIT1 | BIT0)

Intel Special Command Parameter High byte values.

00: SRoU is connected to CD/DVD device 01: SRoU is connected to floppy device

Definition at line 105 of file AsfProtocol.h.

◆ USE_SOL

#define USE_SOL BIT0

Intel OEM Parameters Byte1 values.

0000 0001 - bit 0, use SOL on the next boot

Definition at line 84 of file AsfProtocol.h.

◆ USE_STORAGE_REDIR

#define USE_STORAGE_REDIR BIT0

Intel Special Command Parameter Low byte values.

0000 0001 - bit 0 High Byte will be used to indicate the channel

Definition at line 89 of file AsfProtocol.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): AsfProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
AsfProtocol.h
Go to the documentation of this file.
1 /** @file
2 Definition of Alert Standard Format (ASF) 2.0
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2005 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ASF_PROTOCOL_H_
36 #define _ASF_PROTOCOL_H_
37
38 #include <IndustryStandard/Acpi.h>
39 #include <IndustryStandard/AlertStandardFormatTable.h>
40 #include <AsfMsgs.h>
41
42 typedef enum {
43 Byte1,
44 Byte2
45 } OPTION_INDEX;
46
47
48 ///
49 /// Sub-Command Attributes
50 ///
51 #define ASF_BOOT_OPTIONS_PRESENT 0x16
52 #define ASF_BOOT_OPTIONS_NOT_PRESENT 0x17
53
54 ///
55 /// ASF Internet Assigned Numbers Authority Manufacturer ID
56 /// (The firmware sends 0XBE110000 for decimal value 4542)
57 ///
58 #define ASF_INDUSTRY_IANA 0x000011BE
59 #define ASF_INDUSTRY_CONVERTED_IANA INTEL_IANA_SWAP32 (ASF_INDUSTRY_IANA) ///< 0XBE110000, received from ME FW
60
61 ///
62 /// Intel specific definitions start
63 ///
64
65 ///
66 /// Intel Internet Assigned Numbers Authority Manufacturer ID
67 /// (The firmware sends 0x57010000 for decimal value 343)
68 ///
69 #define INTEL_IANA_SWAP32(x) ((((x) & 0xff) << 24) | (((x) & 0xff00) << 8) | \
70 (((x) & 0xff0000) >> 8) | (((x) & 0xff000000) >> 24))
71 #define ASF_INTEL_IANA 0x00000157
72 #define ASF_INTEL_CONVERTED_IANA INTEL_IANA_SWAP32 (ASF_INTEL_IANA) ///< 0X57010000, received from ME
73
74 ///
75 /// Intel OEM Special Command
76 ///
77 #define ASF_INTEL_OEM_CMD 0xC1
78 #define ASF_INTEL_OEM_FORCE_HTTPS_BOOT_CMD 0xC2
79 #define ASF_INTEL_OEM_FORCE_PBA_BOOT_CMD 0xC3
80
81 ///
82 /// Intel OEM Parameters Byte1 values
83 ///
84 #define USE_SOL BIT0 ///< 0000 0001 - bit 0, use SOL on the next boot
85
86 ///
87 /// Intel Special Command Parameter Low byte values
88 ///
89 #define USE_STORAGE_REDIR BIT0 ///< 0000 0001 - bit 0 High Byte will be used to indicate the channel
90 #define ENFORCE_SECURE_BOOT BIT1 ///< 0000 0010 - bit 1 Enforce secure boot over Storage Redirection
91 #define REFLASH_BIOS BIT2 ///< 0000 0100 - bit 2
92 #define BIOS_SETUP BIT3 ///< 0000 1000 - bit 3
93 #define BIOS_PAUSE BIT4 ///< 0001 0000 - bit 4
94 #define USE_KVM BIT5 ///< 0010 0000 - bit 5
95 #define ENABLE_SECURE_ERASE BIT6 ///< 0100 0000 - bit 6
96 #define ENABLE_REMOTE_PLATFORM_ERASE BIT7 ///< 1000 0000 - bit 7
97
98 ///
99 /// Intel Special Command Parameter High byte values
100 ///
101 /**
102 00: SRoU is connected to CD/DVD device
103 01: SRoU is connected to floppy device
104 **/
105 #define STORAGE_REDIRECTION_BOOT_DEVICE_MASK (BIT1 | BIT0)
106
107 ///
108 /// Intel specific definitions end
109 ///
110
111 ///
112 /// Alert Standard Format Protocol
113 /// This protocol provides interfaces to get ASF Boot Options
114 /// HECI protocol is consumed and used to send ASF messages and receive ASF Boot Options
115 ///
116 typedef struct {
117 ASF_BOOT_OPTIONS AsfBootOptions;
118 } ALERT_STANDARD_FORMAT_PROTOCOL;
119
120 //
121 // Extern the GUID for protocol users.
122 //
123 extern EFI_GUID gAlertStandardFormatProtocolGuid;
124
125 #endif
AsfMsgs.h
AMT/ASF Messages.
ASF_BOOT_OPTIONS
Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message.
Definition: AsfMsgs.h:136
ALERT_STANDARD_FORMAT_PROTOCOL
Intel specific definitions end.
Definition: AsfProtocol.h:116
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Bdat4.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Classes
Bdat4.h File Reference

Definition of BDAT data structures that are applicible for all schemas. More...

#include <Base.h>
Include dependency graph for Bdat4.h:

Go to the source code of this file.

Classes

struct BDAT_SCHEMA_LIST_HOB
Not strictly part of the BDAT spec. More...

Detailed Description

Definition of BDAT data structures that are applicible for all schemas.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Bdat4.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Bdat4.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Bdat4.h
Go to the documentation of this file.
1 /** @file
2 Definition of BDAT data structures that are applicible for all schemas
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef BDAT4_H_
36 #define BDAT4_H_
37
38 #include <Base.h>
39
40 #pragma pack(push, 1)
41
42 typedef struct {
43 UINT8 BiosDataSignature[8]; ///< "BDATHEAD"
44 UINT32 BiosDataStructSize; ///< sizeof BDAT_STRUCTURE
45 UINT16 Crc16; ///< 16-bit CRC of BDAT_STRUCTURE (calculated with 0 in this field)
46 UINT16 Reserved;
47 union {
48 struct {
49 UINT16 Primary;
50 UINT16 Secondary;
51 } Rev;
52 UINT32 Data32;
53 UINT16 Data16[2];
54 UINT8 Data8[4];
55 } Version; ///< Version, primary then secondary.
56 UINT32 OemOffset; ///< Optional offset to OEM-defined structure
57 UINT32 Reserved1;
58 UINT32 Reserved2;
59 } BDAT_HEADER_STRUCTURE;
60
61 typedef struct {
62 UINT16 SchemaListLength; ///< How many offsets are listed in the schema list.
63 UINT16 Reserved1;
64 struct {
65 UINT16 Year;
66 UINT8 Month;
67 UINT8 Day;
68 UINT8 Hour;
69 UINT8 Minute;
70 UINT8 Second;
71 UINT8 Reserved2;
72 } Time; ///< Schema update time.
73 } BDAT_SCHEMA_LIST_STRUCTURE;
74
75 typedef struct {
76 BDAT_HEADER_STRUCTURE Header;
77 BDAT_SCHEMA_LIST_STRUCTURE Schemas;
78 } BDAT_STRUCTURE;
79
80 //
81 //
82 #define MAX_SCHEMA_LIST_LENGTH (10)
83
84 //
85 // Every BDAT schema should begin with this structure definition
86 //
87 typedef struct {
88 EFI_GUID SchemaId; ///< The GUID uniquely identifies the format of the data contained within the structure.
89 UINT32 DataSize; ///< The total size of the memory block, including both the header as well as the schema specific data.
90 UINT16 Crc16; ///< Crc16 is computed in the same manner as the field in the BDAT_HEADER_STRUCTURE.
91 } BDAT_SCHEMA_HEADER_STRUCTURE;
92
93 #pragma pack (pop)
94
95 /**
96 Not strictly part of the BDAT spec. This HOB is used to identify which HOBs
97 contain data that should be copied into the final BDAT structure as a schema
98 **/
99 typedef struct {
100 EFI_HOB_GUID_TYPE HobGuidType;
101 /**
102 SchemaHobCount : Number of HOBs that exist which contain data that should be
103 copied to the BDAT structure.
104 **/
105 UINT16 SchemaHobCount;
106 UINT16 Reserved;
107 /**
108 SchemaHobGuids : Array of GUIDs which identify HOBs that contain data
109 that should be copied into the BDAT structure. The contents
110 of the HOB contains a schema. The GUID for the HOB is the
111 same as the SchemaId GUID.
112 **/
113 EFI_GUID SchemaHobGuids[MAX_SCHEMA_LIST_LENGTH];
114 } BDAT_SCHEMA_LIST_HOB;
115
116 #endif
BDAT_SCHEMA_LIST_HOB
Not strictly part of the BDAT spec.
Definition: Bdat4.h:99
BDAT_SCHEMA_LIST_HOB::SchemaHobCount
UINT16 SchemaHobCount
SchemaHobCount : Number of HOBs that exist which contain data that should be copied to the BDAT struc...
Definition: Bdat4.h:105
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BdatAccess.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
Classes
BdatAccess.h File Reference

This file abstracts Bdat Access Handler Protocol. More...

Go to the source code of this file.

Classes

struct BDAT_ACCESS_PROTOCOL
BDAT access protocol - For accessing some data generated by MRC or PCIe modules. More...

Detailed Description

This file abstracts Bdat Access Handler Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BdatAccess.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BdatAccess.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
BdatAccess.h
Go to the documentation of this file.
1 /** @file
2 This file abstracts Bdat Access Handler Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _BDAT_ACCESS_PROTOCOL_H_
36 #define _BDAT_ACCESS_PROTOCOL_H_
37
38 /**
39 BDAT access protocol - For accessing some data generated by MRC or PCIe modules.
40 **/
41 typedef struct {
42 UINTN bdat;
43 } BDAT_ACCESS_PROTOCOL;
44
45 extern EFI_GUID gBdatAccessGuid;
46
47 #endif
BDAT_ACCESS_PROTOCOL
BDAT access protocol - For accessing some data generated by MRC or PCIe modules.
Definition: BdatAccess.h:41
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuard.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
BiosGuard.h File Reference

Describes the functions visible to the rest of the BIOS Guard. More...

Go to the source code of this file.

Classes

struct | SFAM_DATA
Signed Flash map descriptor definition. More...
struct | BGPDT
BIOS Guard Platform Data Table (BGPDT) Provides platform specific data required by BIOS Guard Module. More...
struct | BGUP_HEADER
BIOS Guard update Package Header. More...
struct | BGUP
BIOS Guard update package definition for BIOS SMM Initiated runtime calls. More...
struct | BIOSGUARD_LOG
BIOS Guard Log The logging facility is used to communicate detailed information regarding the execution of a BIOS Guard script from the SMI handler which invoked the BIOS Guard module itself. More...
struct | BIOSGUARD_HOB
HOB used to pass data through every phase of BIOS Guard Bios. More...

Macros

#define | ALIGN_256KB 0x00040000
256KB alignment
#define | EFI_PAGE_SIZE 0x00001000
4KB page size
#define | BIOSGUARD_COMMAND_NOP 0x00
BIOS Guard Module Commands. More...
#define | BIOSGUARD_COMMAND_BEGIN 0x01
BIOS Guard Begin.
#define | BIOSGUARD_COMMAND_WRITE_INDEX 0x10
BIOS Guard Write Index.
#define | BIOSGUARD_COMMAND_WRITE_IMM 0x11
BIOS Guard Write Immediate.
#define | BIOSGUARD_COMMAND_READ_INDEX 0x12
BIOS Guard Read Index.
#define | BIOSGUARD_COMMAND_READ_IMM 0x13
BIOS Guard Read Immediate.
#define | BIOSGUARD_COMMAND_ERASE_BLK 0x14
BIOS Guard Erase Block.
#define | BIOSGUARD_COMMAND_EC_CMD_WR_INDEX 0x20
EC_CMD Write Index.
#define | BIOSGUARD_COMMAND_EC_CMD_WR_IMM 0x21
EC_CMD Write Immediate.
#define | BIOSGUARD_COMMAND_EC_STS_RD 0x22
EC_CMD Read Status.
#define | BIOSGUARD_COMMAND_EC_DATA_WR_INDEX 0x23
EC_DATA Write Index.
#define | BIOSGUARD_COMMAND_EC_DATA_WR_IMM 0x24
EC_DATA Write Immediate.
#define | BIOSGUARD_COMMAND_EC_DATA_RD 0x25
EC_DATA Read.
#define | BIOSGUARD_COMMAND_SET_BUFFER_INDEX 0x53
BIOS Guard Set Buffer Index.
#define | BIOSGUARD_COMMAND_SET_FLASH_INDEX 0x55
BIOS Guard Set Flash Index.
#define | BIOSGUARD_COMMAND_RD_STS 0xB0
BIOS Guard Read Status.
#define | BIOSGUARD_COMMAND_END 0xFF
BIOS Guard End.
#define | ERR_OK 0x0000
BIOS Guard Module Error Codes. More...
#define | ERR_UNSUPPORTED_CPU 0x0001
BIOS Guard module detected an incompatibility with the installed CPU.
#define | ERR_BAD_DIRECTORY 0x0002
BIOSGUARD_DIRECTORY check failed.
#define | ERR_BAD_BGPDT 0x0003
A pre-execution check of the BGPDT failed.
#define | ERR_BAD_BGUP 0x0004
An inconsistency was found in the update package.
#define | ERR_SCRIPT_SYNTAX 0x0005
Unknown operator or name, or invalid syntax found in script.
#define | ERR_UNDEFINED_FLASH_OBJECT 0x0006
An unimplemented flash object was referenced.
#define | ERR_INVALID_LINE 0x0007
A JMP, JE, JNE, JG, JGE, JL, or JLE operator has a target that is not within the script buffer (between BEGIN and END inclusive).
#define | ERR_BAD_BGUPC 0x0008
BGUPC inconsistency found.
#define | ERR_BAD_SVN 0x0009
BIOS Guard module SVN is lower than required by BGPDT.
#define | ERR_UNEXPECTED_OPCODE 0x000A
An EC related opcode found in a script when the BGPDT indicates there is no EC in the system.
#define | ERR_RANGE_VIOLATION 0x8001
Buffer or flash operation exceeded object bounds.
#define | ERR_SFAM_VIOLATION 0x8002
An unsigned script attempted to write or erase a bock of flash that overlaps with the SFAM.
#define | ERR_OVERFLOW 0x8003
An integer overflow occurred.
#define | ERR_EXEC_LIMIT 0x8004
Total number of script opcodes retired exceeds either platform limit, or global limit.
#define | ERR_INTERNAL_ERROR 0x8005
An internal consistency check failed within the BIOS Guard module.
#define | ERR_LAUNCH_FAIL 0xFFFF
CPU detected an error and did not execute the BIOS Guard module.
#define | BIOSGUARD_F0_INDEX 0x0
PCH flash object index.
#define | BIOSGUARD_B0_INDEX 0x0
Buffer object index.
#define | BIOSGUARD_IF_INDEX 0xF
Integer variable index.
#define | BIOSGUARD_MEMORY_PAGES 64
BIOS Guard Module needs 256KB of reserved memory (64 pages of 4KB each one).
#define | ALIGNMENT_IN_PAGES 64
BIOS Guard requires 256KB alignment (64 pages of 4KB each one).
#define | BIOSGUARD_MODULE_SIZE_IN_PAGES 16
Used to allocate 64K memory (16 pages of 4KB each) for reading BIOS Guard Module.
#define | BIOSGUARD_INTERNAL_HEADER_MODULE_ID_OFFSET 140
Offset of Module ID. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Module ID (12 Bytes).
#define | BIOSGUARD_INTERNAL_HEADER_SVN_OFFSET 144
Offset of Module SVN. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Major Revision ID (16 Bytes).
#define | BIOSGUARD_INTERNAL_HEADER_SE_SVN_OFFSET 200
Offset of Module SE SVN. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Major Revision ID (72 Bytes).
#define | BIOSGUARD_MODULE_SIZE_OFFSET 16
Offset of Size in BIOS Guard Module header.
#define | BIOSGUARD_REVISION_ID_MAJOR_OFFSET 6
Offset of Revision ID (Major).
#define | BIOSGUARD_REVISION_ID_MINOR_OFFSET 4
Offset of Revision ID (Minor).
#define | BIOSGUARD_PRODUCT_ID_OFFSET 56
Offset of Product ID.
#define | BIOSGUARD_BUILD_NUMBER_OFFSET 58
Offset of Build Number.
#define | BGPDT_MAJOR_VERSION 2
BGPDT Major Version.
#define | BGPDT_MINOR_VERSION 0
BGPDT Minor Version.
#define | BGUP_HDR_VERSION 2
BGUP Header Version.
#define | PSL_MAJOR_VERSION 2
PSL Major Version.
#define | PSL_MINOR_VERSION 0
PSL Major Version.
#define | BIOSGUARD_LOG_VERSION 1
BIOS Guard log version.
#define | BIOSGUARD_LOG_OPT_STEP_TRACE BIT0
BIOS Guard logging option - Step trace.
#define | BIOSGUARD_LOG_OPT_BRANCH_TRACE BIT1
BIOS Guard logging option - Branch trace.
#define | BIOSGUARD_LOG_OPT_FLASH_WRITE BIT2
BIOS Guard logging option - Flash write.
#define | BIOSGUARD_LOG_OPT_FLASH_ERASE BIT3
BIOS Guard logging option - Flash erase.
#define | BIOSGUARD_LOG_OPT_FLASH_ERROR BIT4
BIOS Guard logging option - Flash error.
#define | BIOSGUARD_LOG_OPT_DEBUG BIT5
BIOS Guard logging option - Debug opcode execution.
#define | MIN_SFAM_COUNT 1
Minimum SFAM Count.
#define | MAX_SFAM_COUNT 64
Maximum SFAM Count.
#define | BGUPC_MEMORY_SIZE 0x00008000
Memory location for BGUPC and BIOS Guard LOG inside BIOS Guard DPR allocated memory for Tool interface. More...
#define | BIOSGUARD_LOG_MEMORY_SIZE 0x00020000
128KB
#define | BGUPC_MEMORY_OFFSET (BGUPC_MEMORY_SIZE + BIOSGUARD_LOG_MEMORY_SIZE)
BiosGuardMemAddress + BiosGuardMemSize - BIOSGUARD_LOG_MEMORY_SIZE - 32KB.
#define | BIOSGUARD_LOG_MEMORY_OFFSET BIOSGUARD_LOG_MEMORY_SIZE
BiosGuardMemAddress + BiosGuardMemSize - 128KB.
#define | MAX_BIOSGUARD_LOG_PAGE ((BIOSGUARD_LOG_MEMORY_SIZE / EFI_PAGE_SIZE) - 2)
30 4KB Pages
#define | BGUP_TSEG_BUFFER_SIZE 0x00014000
Memory Size for BIOS Guard Update Package when in TSEG. More...

Enumerations

enum | BIOSGUARD_ATTRIBUTES
BIOS Guard attribute definition.
enum | SPI_COMPONENT_SIZE
SPI component size selection.

Detailed Description

Describes the functions visible to the rest of the BIOS Guard.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BiosGuard.h.

Macro Definition Documentation

◆ BGUP_TSEG_BUFFER_SIZE

#define BGUP_TSEG_BUFFER_SIZE 0x00014000

Memory Size for BIOS Guard Update Package when in TSEG.

16KB Script + 64KB Flash Block.

Definition at line 285 of file BiosGuard.h.

◆ BGUPC_MEMORY_SIZE

#define BGUPC_MEMORY_SIZE 0x00008000

Memory location for BGUPC and BIOS Guard LOG inside BIOS Guard DPR allocated memory for Tool interface.

32KB

Definition at line 276 of file BiosGuard.h.

◆ BIOSGUARD_COMMAND_NOP

#define BIOSGUARD_COMMAND_NOP 0x00

BIOS Guard Module Commands.

NO OP.

Definition at line 48 of file BiosGuard.h.

◆ ERR_OK

#define ERR_OK 0x0000

BIOS Guard Module Error Codes.

Operation completed without error.

Definition at line 69 of file BiosGuard.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuard.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
BiosGuard.h
Go to the documentation of this file.
1 /** @file
2 Describes the functions visible to the rest of the BIOS Guard.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _BIOSGUARD_DEFINITIONS_H_
36 #define _BIOSGUARD_DEFINITIONS_H_
37
38 #ifndef ALIGN_256KB
39 #define ALIGN_256KB 0x00040000 ///< 256KB alignment
40 #endif
41 #ifndef EFI_PAGE_SIZE
42 #define EFI_PAGE_SIZE 0x00001000 ///< 4KB page size
43 #endif
44
45 ///
46 /// BIOS Guard Module Commands
47 ///
48 #define BIOSGUARD_COMMAND_NOP 0x00 ///< NO OP.
49 #define BIOSGUARD_COMMAND_BEGIN 0x01 ///< BIOS Guard Begin.
50 #define BIOSGUARD_COMMAND_WRITE_INDEX 0x10 ///< BIOS Guard Write Index.
51 #define BIOSGUARD_COMMAND_WRITE_IMM 0x11 ///< BIOS Guard Write Immediate.
52 #define BIOSGUARD_COMMAND_READ_INDEX 0x12 ///< BIOS Guard Read Index.
53 #define BIOSGUARD_COMMAND_READ_IMM 0x13 ///< BIOS Guard Read Immediate.
54 #define BIOSGUARD_COMMAND_ERASE_BLK 0x14 ///< BIOS Guard Erase Block.
55 #define BIOSGUARD_COMMAND_EC_CMD_WR_INDEX 0x20 ///< EC_CMD Write Index.
56 #define BIOSGUARD_COMMAND_EC_CMD_WR_IMM 0x21 ///< EC_CMD Write Immediate.
57 #define BIOSGUARD_COMMAND_EC_STS_RD 0x22 ///< EC_CMD Read Status.
58 #define BIOSGUARD_COMMAND_EC_DATA_WR_INDEX 0x23 ///< EC_DATA Write Index.
59 #define BIOSGUARD_COMMAND_EC_DATA_WR_IMM 0x24 ///< EC_DATA Write Immediate.
60 #define BIOSGUARD_COMMAND_EC_DATA_RD 0x25 ///< EC_DATA Read.
61 #define BIOSGUARD_COMMAND_SET_BUFFER_INDEX 0x53 ///< BIOS Guard Set Buffer Index.
62 #define BIOSGUARD_COMMAND_SET_FLASH_INDEX 0x55 ///< BIOS Guard Set Flash Index.
63 #define BIOSGUARD_COMMAND_RD_STS 0xB0 ///< BIOS Guard Read Status.
64 #define BIOSGUARD_COMMAND_END 0xFF ///< BIOS Guard End.
65
66 ///
67 /// BIOS Guard Module Error Codes
68 ///
69 #define ERR_OK 0x0000 ///< Operation completed without error.
70 #define ERR_UNSUPPORTED_CPU 0x0001 ///< BIOS Guard module detected an incompatibility with the installed CPU.
71 #define ERR_BAD_DIRECTORY 0x0002 ///< BIOSGUARD_DIRECTORY check failed.
72 #define ERR_BAD_BGPDT 0x0003 ///< A pre-execution check of the BGPDT failed.
73 #define ERR_BAD_BGUP 0x0004 ///< An inconsistency was found in the update package.
74 #define ERR_SCRIPT_SYNTAX 0x0005 ///< Unknown operator or name, or invalid syntax found in script.
75 #define ERR_UNDEFINED_FLASH_OBJECT 0x0006 ///< An unimplemented flash object was referenced.
76 #define ERR_INVALID_LINE 0x0007 ///< A JMP, JE, JNE, JG, JGE, JL, or JLE operator has a target that is not within the script buffer (between BEGIN and END inclusive).
77 #define ERR_BAD_BGUPC 0x0008 ///< BGUPC inconsistency found.
78 #define ERR_BAD_SVN 0x0009 ///< BIOS Guard module SVN is lower than required by BGPDT.
79 #define ERR_UNEXPECTED_OPCODE 0x000A ///< An EC related opcode found in a script when the BGPDT indicates there is no EC in the system.
80 #define ERR_RANGE_VIOLATION 0x8001 ///< Buffer or flash operation exceeded object bounds.
81 #define ERR_SFAM_VIOLATION 0x8002 ///< An unsigned script attempted to write or erase a bock of flash that overlaps with the SFAM.
82 #define ERR_OVERFLOW 0x8003 ///< An integer overflow occurred.
83 #define ERR_EXEC_LIMIT 0x8004 ///< Total number of script opcodes retired exceeds either platform limit, or global limit.
84 #define ERR_INTERNAL_ERROR 0x8005 ///< An internal consistency check failed within the BIOS Guard module.
85 #define ERR_LAUNCH_FAIL 0xFFFF ///< CPU detected an error and did not execute the BIOS Guard module.
86
87 #define BIOSGUARD_F0_INDEX 0x0 ///< PCH flash object index
88 #define BIOSGUARD_B0_INDEX 0x0 ///< Buffer object index
89 #define BIOSGUARD_IF_INDEX 0xF ///< Integer variable index
90
91 #define BIOSGUARD_MEMORY_PAGES 64 ///< BIOS Guard Module needs 256KB of reserved memory (64 pages of 4KB each one).
92 #define ALIGNMENT_IN_PAGES 64 ///< BIOS Guard requires 256KB alignment (64 pages of 4KB each one).
93
94 #define BIOSGUARD_MODULE_SIZE_IN_PAGES 16 ///< Used to allocate 64K memory (16 pages of 4KB each) for reading BIOS Guard Module.
95 #define BIOSGUARD_INTERNAL_HEADER_MODULE_ID_OFFSET 140 ///< Offset of Module ID. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Module ID (12 Bytes).
96 #define BIOSGUARD_INTERNAL_HEADER_SVN_OFFSET 144 ///< Offset of Module SVN. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Major Revision ID (16 Bytes).
97 #define BIOSGUARD_INTERNAL_HEADER_SE_SVN_OFFSET 200 ///< Offset of Module SE SVN. Size of BIOS HEADER (128 Bytes) + Offset of Internal Header Major Revision ID (72 Bytes).
98 #define BIOSGUARD_MODULE_SIZE_OFFSET 16 ///< Offset of Size in BIOS Guard Module header.
99 #define BIOSGUARD_REVISION_ID_MAJOR_OFFSET 6 ///< Offset of Revision ID (Major).
100 #define BIOSGUARD_REVISION_ID_MINOR_OFFSET 4 ///< Offset of Revision ID (Minor).
101 #define BIOSGUARD_PRODUCT_ID_OFFSET 56 ///< Offset of Product ID.
102 #define BIOSGUARD_BUILD_NUMBER_OFFSET 58 ///< Offset of Build Number.
103
104 #define BGPDT_MAJOR_VERSION 2 ///< BGPDT Major Version
105 #define BGPDT_MINOR_VERSION 0 ///< BGPDT Minor Version
106 #define BGUP_HDR_VERSION 2 ///< BGUP Header Version
107 #define PSL_MAJOR_VERSION 2 ///< PSL Major Version
108 #define PSL_MINOR_VERSION 0 ///< PSL Major Version
109
110 #define BIOSGUARD_LOG_VERSION 1 ///< BIOS Guard log version
111 #define BIOSGUARD_LOG_OPT_STEP_TRACE BIT0 ///< BIOS Guard logging option - Step trace
112 #define BIOSGUARD_LOG_OPT_BRANCH_TRACE BIT1 ///< BIOS Guard logging option - Branch trace
113 #define BIOSGUARD_LOG_OPT_FLASH_WRITE BIT2 ///< BIOS Guard logging option - Flash write
114 #define BIOSGUARD_LOG_OPT_FLASH_ERASE BIT3 ///< BIOS Guard logging option - Flash erase
115 #define BIOSGUARD_LOG_OPT_FLASH_ERROR BIT4 ///< BIOS Guard logging option - Flash error
116 #define BIOSGUARD_LOG_OPT_DEBUG BIT5 ///< BIOS Guard logging option - Debug opcode execution
117
118 ///
119 /// BIOS Guard attribute definition
120 ///
121 typedef enum {
122 EnumEcPresent = BIT1,
123 EnumEcBiosGuardProtected = BIT2,
124 EnumDescriptorOverridePolicy = BIT3,
125 EnumFlashwearoutProtection = BIT4,
126 EnumFtuEnable = BIT5
127 } BIOSGUARD_ATTRIBUTES;
128
129 ///
130 /// SPI component size selection
131 ///
132 typedef enum {
133 EnumSpiCompSize512KB = 0,
134 EnumSpiCompSize1MB,
135 EnumSpiCompSize2MB,
136 EnumSpiCompSize4MB,
137 EnumSpiCompSize8MB,
138 EnumSpiCompSize16MB,
139 EnumSpiCompSize32MB,
140 EnumSpiCompSize64MB,
141 EnumSpiCompSize128MB
142 } SPI_COMPONENT_SIZE;
143
144 #define MIN_SFAM_COUNT 1 ///< Minimum SFAM Count
145 #define MAX_SFAM_COUNT 64 ///< Maximum SFAM Count
146
147 ///
148 /// Signed Flash map descriptor definition.
149 ///
150 typedef struct {
151 UINT32 FirstByte; ///< Linear flash address of the first byte of the signed range, must be aligned to be first byte in the block. Ordering is little-endian.
152 UINT32 LastByte; ///< Linear flash address of the last byte of the signed range, must be aligned to be last byte in the block. Ordering is little-endian.
153 } SFAM_DATA;
154
155 ///
156 /// BIOS Guard Platform Data Table (BGPDT)
157 /// Provides platform specific data required by BIOS Guard Module
158 ///
159 typedef struct {
160 UINT32 BgpdtSize; ///< Size in bytes of BGPDT including SFAM.
161 UINT16 BgpdtMajVer; ///< Indicates major version of BGPDT.
162 UINT16 BgpdtMinVer; ///< Indicates minor version of BGPDT.
163 UINT8 PlatId[16]; ///< PLAT_ID used to be compared against the one found in the BGUP Header to prevent cross platform flashing.
164 UINT8 PkeySlot0[32]; ///< SHA256 hash for BGUP verification key 0.
165 UINT8 PkeySlot1[32]; ///< SHA256 hash for BGUP verification key 1.
166 UINT8 PkeySlot2[32]; ///< SHA256 hash for BGUP verification key 2.
167 UINT32 BgModSvn; ///< BIOS Guard Module SVN.
168 UINT32 BiosSvn; ///< BIOS_SVN to prevent back-flashing.
169 UINT32 ExecLim; ///< Limit the number of opcodes that can be executed on any invocation of BIOS Guard.
170 /**
171 Bitmap of Policy attributes
172 - BIT[0]: Reserved. Must be 0
173 - BIT[2:1]: EC_PRESENT
174 - 00b = EC does not exist in the system.
175 - 01b = There exists an EC in the system, BIOS Guard does not extend any protection to the EC.
176 - 11b = There exist an EC in the system, BIOS Guard extends protection to the EC.
177 - 10b = Reserved. Must not be used.
178 - BIT[3]: DESCRIPTOR_OVERRIDE_POLICY
179 - 0b = Do not override BIOS Guard security policy.
180 - 1b = Override BIOS Guard security policy.
181 - BIT[4]: FLASH_WEAROUT_POLICY
182 - 0b = Legacy BIOS Guard behavior.
183 - 1b = Enable Flash Wear-Out Protection mitigation.
184 - BIT[5]: FTU_ENABLE
185 - 0b = Legacy BIOS Guard behavior.
186 - 1b = Enable fault tolerant update.
187 - BIT[23:6]: Reserved, must be 0
188 - BIT[31:24]: Reserved for platform specific definition. Must be 0 if not defined.
189 **/
190 UINT32 BiosGuardAttr;
191 /**
192 Read/Write command sent to EC
193 - BIT[9:0]: 8 bit IO port used for sending EC commands (writes), and reading EC status (reads).
194 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
195 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
196 - BIT[31:10]: Reserved. Must be 0.
197 **/
198 UINT32 EcCmd;
199 /**
200 Data read or written to EC
201 - BIT[9:0]: 8 bit IO port used for reading and writing data to the EC based on a command issued to EC_CMD.
202 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
203 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
204 - BIT[31:10]: Reserved. Must be 0
205 **/
206 UINT32 EcData;
207 /**
208 EC command indicating a read of the current EC firmware SVN.
209 - BIT[7:0]: EC command.
210 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
211 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
212 - BIT[31:8]: Reserved. Must be 0.
213 **/
214 UINT32 EcCmdGetSvn;
215 /**
216 EC command indicating begin of flash update session.
217 - BIT[7:0]: EC command.
218 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
219 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
220 - BIT[31:8]: Reserved. Must be 0.
221 **/
222 UINT32 EcCmdOpen;
223 /**
224 EC command indicating the termination of BIOS Guard protected session.
225 - BIT[7:0]: EC command indicating the termination of BIOS Guard protected session.
226 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
227 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
228 - BIT[31:8]: Reserved. Must be 0.
229 **/
230 UINT32 EcCmdClose;
231 /**
232 EC command used to verify connectivity between BIOS Guard and EC.
233 - BIT[7:0]: EC command.
234 - This field must be populated if PLAT_ATTR.EC_PRESENT != 0.
235 - This field must be zero if PLAT_ATTR.EC_PRESENT == 0.
236 - BIT[31:8]: Reserved. Must be 0.
237 **/
238 UINT32 EcCmdPortTest;
239 UINT8 Reserved1[4]; ///< Reserved bits.
240 /**
241 Defines number of elements in SFAM array
242 - BIT[5..0]: Index of the last SFAM element
243 - BIT[7..6]: Reserved for future use. Must be 0
244 **/
245 UINT8 LastSfam;
246 UINT8 Reserved2[3]; ///< Reserved 3 bits.
247 SFAM_DATA SfamData[MAX_SFAM_COUNT]; ///< Array of flash address map descriptors. sizeof (SFAM_DATA) == 8
248 } BGPDT;
249
250 ///
251 /// BIOS Guard update Package Header
252 ///
253 typedef struct {
254 UINT16 Version; ///< Version of the update package header. Must be 0x0002.
255 UINT8 Reserved3[2]; ///< Reserved bits.
256 UINT8 PlatId[16]; ///< PLAT_ID used to be compared against the one found in the BGPDT to prevent cross platform flashing.
257 /**
258 If any bit set in this field then BGUP must be signed and valid BGUPC must be provided for BGUP to be processed.
259 - BIT[0]: Indicates write/erase operations will be executed on protected flash area indicated in the BGPDT SFAM.
260 - BIT[1]: Indicates protected EC operations included.
261 **/
262 UINT16 PkgAttributes;
263 UINT8 Reserved4[2]; ///< Reserved bits.
264 UINT16 PslMajorVer; ///< Indicates the PSL major version. Must be 2.
265 UINT16 PslMinorVer; ///< Indicates the PSL minor version. Must be 0.
266 UINT32 ScriptSectionSize; ///< Size in bytes of the script.
267 UINT32 DataSectionSize; ///< Size of the data region in bytes.
268 UINT32 BiosSvn; ///< BIOS SVN.
269 UINT32 EcSvn; ///< EC SVN.
270 UINT32 VendorSpecific; ///< Vendor specific data.
271 } BGUP_HEADER;
272
273 ///
274 /// Memory location for BGUPC and BIOS Guard LOG inside BIOS Guard DPR allocated memory for Tool interface
275 ///
276 #define BGUPC_MEMORY_SIZE 0x00008000 ///< 32KB
277 #define BIOSGUARD_LOG_MEMORY_SIZE 0x00020000 ///< 128KB
278 #define BGUPC_MEMORY_OFFSET (BGUPC_MEMORY_SIZE + BIOSGUARD_LOG_MEMORY_SIZE) ///< BiosGuardMemAddress + BiosGuardMemSize - BIOSGUARD_LOG_MEMORY_SIZE - 32KB
279 #define BIOSGUARD_LOG_MEMORY_OFFSET BIOSGUARD_LOG_MEMORY_SIZE ///< BiosGuardMemAddress + BiosGuardMemSize - 128KB
280 #define MAX_BIOSGUARD_LOG_PAGE ((BIOSGUARD_LOG_MEMORY_SIZE / EFI_PAGE_SIZE) - 2) ///< 30 4KB Pages
281
282 ///
283 /// Memory Size for BIOS Guard Update Package when in TSEG
284 ///
285 #define BGUP_TSEG_BUFFER_SIZE 0x00014000 ///< 16KB Script + 64KB Flash Block.
286
287 ///
288 /// BIOS Guard update package definition for BIOS SMM Initiated runtime calls
289 ///
290 typedef struct {
291 BGUP_HEADER BgupHeader; ///< BIOS Guard update package header.
292 UINT64 BgupBuffer[BGUP_TSEG_BUFFER_SIZE / 8]; ///< BIOS Guard update buffer - Designed to contain the BIOS Guard Script followed immediately by the Update Data
293 } BGUP;
294
295 ///
296 /// BIOS Guard Log
297 /// The logging facility is used to communicate detailed information regarding the execution of a BIOS Guard script
298 /// from the SMI handler which invoked the BIOS Guard module itself.
299 ///
300 typedef struct {
301 UINT16 Version; ///< Indicates the version of the log. Must be 0x0001.
302 UINT16 LastPage; ///< Last valid page index for the log.
303 /**
304 Bitmap indicating what events to log
305 - BIT[0]: Step trace. This indicates a full execution trace. Each line is entered into the log with an EXECUTION_TRACE entry.
306 - BIT[1]: Branch trace. All taken jumps are logged with a BRANCH_TRACE entry.
307 - BIT[2]: Flash write All flash write operations are logged with a FLASH_WRITE entry.
308 - BIT[3]: Flash erase All flash erase operations are logged with a FLASH_ERASE entry.
309 - BIT[4]: Flash error. All error conditions from flash operations are logged with FLASH_ERROR entry.
310 - BIT[5]: Debug. Log Debug opcode execution.
311 - BIT[6]: BIOS Guard module debug message. Log implementation specific debug messages from debug module.
312 - BIT[31:7]: Reserved. Must be 0. If any reserved bits are set in Header.LoggingOptions, the BIOS Guard module must disable the logging feature.
313 **/
314 UINT32 LoggingOptions;
315 UINT8 Reserved5[8]; ///< Reserved bits.
316 UINT32 BgModSvn; ///< Indicates a version number of the BIOS Guard module.
317 UINT32 NumOfEntriesInLog; ///< Total number of log entries that have been written to the log.
318 } BIOSGUARD_LOG;
319
320 ///
321 /// HOB used to pass data through every phase of BIOS Guard Bios.
322 /// BIOS Guard BIOS code is executed in PEI, DXE and SMM and HOB is the only method to properly pass data between every phase.
323 ///
324 typedef struct {
325 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type header.
326 BGPDT Bgpdt; ///< BIOS Guard Platform Data Table.
327 BGUP_HEADER BgupHeader; ///< BIOS Guard update package header, this header will be appended to all flash updates along with PSL script.
328 BIOSGUARD_LOG BiosGuardLog; ///< Header for BIOS Guard Log Buffer.
329 EFI_PHYSICAL_ADDRESS BiosGuardModulePtr; ///< Pointer to the BIOS Guard Module.
330 UINT64 BiosGuardMemAddress; ///< BIOS Guard Memory Address for Tool Interface
331 UINT8 BiosGuardMemSize; ///< BIOS Guard Memory Size for Tool Interface
332 UINT8 Reserved[3]; ///< Reserved for alignment
333 UINT16 BiosGuardIoTrapAddress; ///< BIOS Guard IoTrap Address for Tool Interface
334 UINT16 BiosGuardIoTrapLength; ///< BIOS Guard IoTrap Length for Tool Interface
335 UINT32 BiosGuardModuleSize; ///< BIOS Guard Module Size.
336 } BIOSGUARD_HOB;
337
338 #endif
BIOSGUARD_HOB::BiosGuardIoTrapLength
UINT16 BiosGuardIoTrapLength
BIOS Guard IoTrap Length for Tool Interface.
Definition: BiosGuard.h:334
SFAM_DATA
Signed Flash map descriptor definition.
Definition: BiosGuard.h:150
SFAM_DATA::FirstByte
UINT32 FirstByte
Linear flash address of the first byte of the signed range, must be aligned to be first byte in the b...
Definition: BiosGuard.h:151
BGPDT::EcCmdOpen
UINT32 EcCmdOpen
EC command indicating begin of flash update session.
Definition: BiosGuard.h:222
BGUP_HEADER
BIOS Guard update Package Header.
Definition: BiosGuard.h:253
BGPDT::EcData
UINT32 EcData
Data read or written to EC.
Definition: BiosGuard.h:206
BGPDT::BgpdtMajVer
UINT16 BgpdtMajVer
Indicates major version of BGPDT.
Definition: BiosGuard.h:161
BIOSGUARD_HOB::BiosGuardMemSize
UINT8 BiosGuardMemSize
BIOS Guard Memory Size for Tool Interface.
Definition: BiosGuard.h:331
BGPDT::EcCmdClose
UINT32 EcCmdClose
EC command indicating the termination of BIOS Guard protected session.
Definition: BiosGuard.h:230
BIOSGUARD_HOB::BiosGuardModulePtr
EFI_PHYSICAL_ADDRESS BiosGuardModulePtr
Pointer to the BIOS Guard Module.
Definition: BiosGuard.h:329
BIOSGUARD_HOB::Bgpdt
BGPDT Bgpdt
BIOS Guard Platform Data Table.
Definition: BiosGuard.h:326
BGPDT
BIOS Guard Platform Data Table (BGPDT) Provides platform specific data required by BIOS Guard Module.
Definition: BiosGuard.h:159
BGPDT::EcCmdPortTest
UINT32 EcCmdPortTest
EC command used to verify connectivity between BIOS Guard and EC.
Definition: BiosGuard.h:238
BIOSGUARD_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
GUID Hob type header.
Definition: BiosGuard.h:325
BIOSGUARD_HOB::BiosGuardMemAddress
UINT64 BiosGuardMemAddress
BIOS Guard Memory Address for Tool Interface.
Definition: BiosGuard.h:330
BIOSGUARD_HOB::BgupHeader
BGUP_HEADER BgupHeader
BIOS Guard update package header, this header will be appended to all flash updates along with PSL sc...
Definition: BiosGuard.h:327
BIOSGUARD_LOG::LoggingOptions
UINT32 LoggingOptions
Bitmap indicating what events to log.
Definition: BiosGuard.h:314
MAX_SFAM_COUNT
#define MAX_SFAM_COUNT
Maximum SFAM Count.
Definition: BiosGuard.h:145
BIOSGUARD_HOB
HOB used to pass data through every phase of BIOS Guard Bios.
Definition: BiosGuard.h:324
BGUP::BgupHeader
BGUP_HEADER BgupHeader
BIOS Guard update package header.
Definition: BiosGuard.h:291
BIOSGUARD_HOB::BiosGuardLog
BIOSGUARD_LOG BiosGuardLog
Header for BIOS Guard Log Buffer.
Definition: BiosGuard.h:328
SFAM_DATA::LastByte
UINT32 LastByte
Linear flash address of the last byte of the signed range, must be aligned to be last byte in the blo...
Definition: BiosGuard.h:152
BIOSGUARD_LOG::NumOfEntriesInLog
UINT32 NumOfEntriesInLog
Total number of log entries that have been written to the log.
Definition: BiosGuard.h:317
BGUP_HEADER::Version
UINT16 Version
Version of the update package header. Must be 0x0002.
Definition: BiosGuard.h:254
BGPDT::BgpdtSize
UINT32 BgpdtSize
Size in bytes of BGPDT including SFAM.
Definition: BiosGuard.h:160
BGPDT::EcCmd
UINT32 EcCmd
Read/Write command sent to EC.
Definition: BiosGuard.h:198
BIOSGUARD_ATTRIBUTES
BIOSGUARD_ATTRIBUTES
BIOS Guard attribute definition.
Definition: BiosGuard.h:121
BGUP_TSEG_BUFFER_SIZE
#define BGUP_TSEG_BUFFER_SIZE
Memory Size for BIOS Guard Update Package when in TSEG.
Definition: BiosGuard.h:285
BGPDT::LastSfam
UINT8 LastSfam
Defines number of elements in SFAM array.
Definition: BiosGuard.h:245
BGPDT::BiosSvn
UINT32 BiosSvn
BIOS_SVN to prevent back-flashing.
Definition: BiosGuard.h:168
BGUP_HEADER::PslMinorVer
UINT16 PslMinorVer
Indicates the PSL minor version. Must be 0.
Definition: BiosGuard.h:265
BIOSGUARD_LOG::LastPage
UINT16 LastPage
Last valid page index for the log.
Definition: BiosGuard.h:302
BGPDT::BgModSvn
UINT32 BgModSvn
BIOS Guard Module SVN.
Definition: BiosGuard.h:167
BGPDT::ExecLim
UINT32 ExecLim
Limit the number of opcodes that can be executed on any invocation of BIOS Guard.
Definition: BiosGuard.h:169
BGUP_HEADER::ScriptSectionSize
UINT32 ScriptSectionSize
Size in bytes of the script.
Definition: BiosGuard.h:266
BGUP_HEADER::BiosSvn
UINT32 BiosSvn
BIOS SVN.
Definition: BiosGuard.h:268
BGUP_HEADER::PslMajorVer
UINT16 PslMajorVer
Indicates the PSL major version. Must be 2.
Definition: BiosGuard.h:264
SPI_COMPONENT_SIZE
SPI_COMPONENT_SIZE
SPI component size selection.
Definition: BiosGuard.h:132
BGUP_HEADER::VendorSpecific
UINT32 VendorSpecific
Vendor specific data.
Definition: BiosGuard.h:270
BGPDT::EcCmdGetSvn
UINT32 EcCmdGetSvn
EC command indicating a read of the current EC firmware SVN.
Definition: BiosGuard.h:214
BIOSGUARD_LOG::BgModSvn
UINT32 BgModSvn
Indicates a version number of the BIOS Guard module.
Definition: BiosGuard.h:316
BIOSGUARD_LOG::Version
UINT16 Version
Indicates the version of the log. Must be 0x0001.
Definition: BiosGuard.h:301
BGUP_HEADER::PkgAttributes
UINT16 PkgAttributes
If any bit set in this field then BGUP must be signed and valid BGUPC must be provided for BGUP to be...
Definition: BiosGuard.h:262
BGPDT::BiosGuardAttr
UINT32 BiosGuardAttr
Bitmap of Policy attributes.
Definition: BiosGuard.h:190
BGPDT::BgpdtMinVer
UINT16 BgpdtMinVer
Indicates minor version of BGPDT.
Definition: BiosGuard.h:162
BGUP_HEADER::EcSvn
UINT32 EcSvn
EC SVN.
Definition: BiosGuard.h:269
BGUP
BIOS Guard update package definition for BIOS SMM Initiated runtime calls.
Definition: BiosGuard.h:290
BGUP_HEADER::DataSectionSize
UINT32 DataSectionSize
Size of the data region in bytes.
Definition: BiosGuard.h:267
BIOSGUARD_HOB::BiosGuardIoTrapAddress
UINT16 BiosGuardIoTrapAddress
BIOS Guard IoTrap Address for Tool Interface.
Definition: BiosGuard.h:333
BIOSGUARD_LOG
BIOS Guard Log The logging facility is used to communicate detailed information regarding the executi...
Definition: BiosGuard.h:300
BIOSGUARD_HOB::BiosGuardModuleSize
UINT32 BiosGuardModuleSize
BIOS Guard Module Size.
Definition: BiosGuard.h:335
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuard.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs | Variables
Protocol/BiosGuard.h File Reference

This file defines the BIOS Guard Protocol which implements the Intel(R) BIOS Guard Host Controller Compatibility Interface. More...

Go to the source code of this file.

Classes

struct _BIOSGUARD_PROTOCOL
This protocol provides all the services required for flash writes/erases via BIOS Guard BIOS Guard Module can only be launched from SMM. More...

Typedefs

typedef struct _BIOSGUARD_PROTOCOL | BIOSGUARD_PROTOCOL
Forward reference of BIOS Guard Protocol for ANSI C compatibility.
typedef EFI_STATUS(* | BIOSGUARD_EXECUTE) (IN BIOSGUARD_PROTOCOL *This, IN BOOLEAN BiosUpdate)
This service will write BIOSGUARD_DIRECTORY MSR and invoke the BIOS Guard Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash. More...
typedef EFI_STATUS(* | BIOSGUARD_WRITE) (IN BIOSGUARD_PROTOCOL *This, IN UINTN Address, IN UINT32 DataByteCount, IN OUT UINT8 *Buffer)
This service fills BIOS Guard script buffer for flash writes. More...
typedef VOID(* | BIOSGUARD_ERASE) (IN BIOSGUARD_PROTOCOL *This, IN UINTN Address)
This service fills BIOS Guard script buffer for erasing blocks in flash. More...

Variables

EFI_GUID gSmmBiosGuardProtocolGuid
Extern the GUID for protocol users.

Detailed Description

This file defines the BIOS Guard Protocol which implements the Intel(R) BIOS Guard Host Controller Compatibility Interface.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Protocol/BiosGuard.h.

Typedef Documentation

◆ BIOSGUARD_ERASE

typedef VOID( * BIOSGUARD_ERASE) (IN BIOSGUARD_PROTOCOL *This, IN UINTN Address)

This service fills BIOS Guard script buffer for erasing blocks in flash.

BIOS should invoke this function prior to calling BIOSGUARD_PROTOCOL.Execute() with all the relevant data required for flash erase. This function will not invoke BIOS Guard module, only create script required for erasing each block in the flash.

Warning
This function would be called by runtime driver, please do not use any MMIO macro here.
Parameters
[in] | This | Pointer to the BIOSGUARD_PROTOCOL instance.
[in] | Address | This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.

Definition at line 109 of file Protocol/BiosGuard.h.

◆ BIOSGUARD_EXECUTE

typedef EFI_STATUS( * BIOSGUARD_EXECUTE) (IN BIOSGUARD_PROTOCOL *This, IN BOOLEAN BiosUpdate)

This service will write BIOSGUARD_DIRECTORY MSR and invoke the BIOS Guard Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash.

BIOS should invoke BIOSGUARD_PROTOCOL.Write() or BIOSGUARD_PROTOCOL.Erase() function prior to calling BIOSGUARD_PROTOCOL.Execute() for flash writes/erases (except for BiosUpdate). Write()/Erase() function will render BIOS Guard script during execution. Execute() function will implement the following steps:

  • 1. Update BIOS Guard directory with address of BGUP.
  • 2. All the AP's except the BSP thread are put to sleep.
  • 3. BIOS Guard module is invoked from BSP to execute desired operation.

If BiosUpdate flag is set to true, BGUP (BGUP Header + BIOS Guard Script + Update data) is part of data that is passed to SMI Handler. SMI Handler invokes BIOS Guard module to process the update. This function would be called by runtime driver, please do not use any MMIO macro here.

Parameters
[in] | This | Pointer to the BIOSGUARD_PROTOCOL instance.
[in] | BiosUpdate | Flag to indicate flash update is requested by the Tool
Return values
EFI_SUCCESS | Successfully completed flash operation.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_UNSUPPORTED | The CPU or SPI memory is not supported.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 70 of file Protocol/BiosGuard.h.

◆ BIOSGUARD_WRITE

typedef EFI_STATUS( * BIOSGUARD_WRITE) (IN BIOSGUARD_PROTOCOL *This, IN UINTN Address, IN UINT32 DataByteCount, IN OUT UINT8 *Buffer)

This service fills BIOS Guard script buffer for flash writes.

BIOS should invoke this function prior to calling BIOSGUARD_PROTOCOL.Execute() with all the relevant data required for flash write. This function will not invoke BIOS Guard Module, only create script required for writing to flash.

Warning
This function would be called by runtime driver, please do not use any MMIO macro here.
Parameters
[in] | This | Pointer to the BIOSGUARD_PROTOCOL instance.
[in] | Address | This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
[in] | DataByteCount | Number of bytes in the data portion.
[in] | Buffer | Pointer to caller-allocated buffer containing the data sent.
Return values
EFI_SUCCESS | Successfully filled the BIOS Guard script buffer.
EFI_BAD_BUFFER_SIZE | DataSectionSize in BGUP header exceeds the size of BIOS Guard script buffer

Definition at line 91 of file Protocol/BiosGuard.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuard.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol/BiosGuard.h
Go to the documentation of this file.
1 /** @file
2 This file defines the BIOS Guard Protocol which implements the
3 Intel(R) BIOS Guard Host Controller Compatibility Interface.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2011 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _BIOSGUARD_H_
37 #define _BIOSGUARD_H_
38
39 ///
40 /// Extern the GUID for protocol users.
41 ///
42 extern EFI_GUID gSmmBiosGuardProtocolGuid;
43
44 /**
45 Forward reference of BIOS Guard Protocol for ANSI C compatibility
46 **/
47 typedef struct _BIOSGUARD_PROTOCOL BIOSGUARD_PROTOCOL;
48
49 /**
50 This service will write BIOSGUARD_DIRECTORY MSR and invoke the BIOS Guard Module by writing to PLAT_FRMW_PROT_TRIGGER MSR for writing/erasing to flash.
51 BIOS should invoke BIOSGUARD_PROTOCOL.Write() or BIOSGUARD_PROTOCOL.Erase() function prior to calling BIOSGUARD_PROTOCOL.Execute() for flash writes/erases (except for BiosUpdate).
52 Write()/Erase() function will render BIOS Guard script during execution.
53 Execute() function will implement the following steps:
54 - 1. Update BIOS Guard directory with address of BGUP.
55 - 2. All the AP's except the BSP thread are put to sleep.
56 - 3. BIOS Guard module is invoked from BSP to execute desired operation.
57
58 If BiosUpdate flag is set to true, BGUP (BGUP Header + BIOS Guard Script + Update data) is part of data that is passed to SMI Handler. SMI Handler invokes BIOS Guard module to process the update.
59 This function would be called by runtime driver, please do not use any MMIO macro here.
60
61 @param[in] This Pointer to the BIOSGUARD_PROTOCOL instance.
62 @param[in] BiosUpdate Flag to indicate flash update is requested by the Tool
63
64 @retval EFI_SUCCESS Successfully completed flash operation.
65 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
66 @retval EFI_UNSUPPORTED The CPU or SPI memory is not supported.
67 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
68 **/
69 typedef
70 EFI_STATUS
71 (EFIAPI *BIOSGUARD_EXECUTE)(
72 IN BIOSGUARD_PROTOCOL *This,
73 IN BOOLEAN BiosUpdate
74 );
75
76 /**
77 This service fills BIOS Guard script buffer for flash writes.
78 BIOS should invoke this function prior to calling BIOSGUARD_PROTOCOL.Execute() with all the relevant data required for flash write.
79 This function will not invoke BIOS Guard Module, only create script required for writing to flash.
80 @warning This function would be called by runtime driver, please do not use any MMIO macro here.
81
82 @param[in] This Pointer to the BIOSGUARD_PROTOCOL instance.
83 @param[in] Address This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
84 @param[in] DataByteCount Number of bytes in the data portion.
85 @param[in] Buffer Pointer to caller-allocated buffer containing the data sent.
86
87 @retval EFI_SUCCESS Successfully filled the BIOS Guard script buffer.
88 @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the size of BIOS Guard script buffer
89 **/
90 typedef
91 EFI_STATUS
92 (EFIAPI *BIOSGUARD_WRITE)(
93 IN BIOSGUARD_PROTOCOL *This,
94 IN UINTN Address,
95 IN UINT32 DataByteCount,
96 IN OUT UINT8 *Buffer
97 );
98
99 /**
100 This service fills BIOS Guard script buffer for erasing blocks in flash.
101 BIOS should invoke this function prior to calling BIOSGUARD_PROTOCOL.Execute() with all the relevant data required for flash erase.
102 This function will not invoke BIOS Guard module, only create script required for erasing each block in the flash.
103 @warning This function would be called by runtime driver, please do not use any MMIO macro here.
104
105 @param[in] This Pointer to the BIOSGUARD_PROTOCOL instance.
106 @param[in] Address This value specifies the offset from the start of the SPI Flash component where BIOS Image is located.
107 **/
108 typedef
109 VOID
110 (EFIAPI *BIOSGUARD_ERASE)(
111 IN BIOSGUARD_PROTOCOL *This,
112 IN UINTN Address
113 );
114
115
116 /**
117 This protocol provides all the services required for flash writes/erases via BIOS Guard
118 BIOS Guard Module can only be launched from SMM
119 @warning All flash writes & erases that BIOS needs to do must flow thru SMI Handler and so dependency on SMM_BASE_PROTOCOL
120 for installing BIOS Guard Protocol. Prior to BIOS Guard SMM Protocol being installed there should be no writes/erases to flash.
121 **/
122 struct _BIOSGUARD_PROTOCOL {
123 BIOSGUARD_WRITE Write; ///< Invoked to fill up BIOS Guard script buffer for flash writes
124 BIOSGUARD_ERASE Erase; ///< Invoked to fill up BIOS Guard script buffer for flash erases
125 BIOSGUARD_EXECUTE Execute; ///< Will trigger invocation of BIOS Guard module
126 };
127
128 #endif
BIOSGUARD_EXECUTE
EFI_STATUS(* BIOSGUARD_EXECUTE)(IN BIOSGUARD_PROTOCOL *This, IN BOOLEAN BiosUpdate)
This service will write BIOSGUARD_DIRECTORY MSR and invoke the BIOS Guard Module by writing to PLAT_F...
Definition: Protocol/BiosGuard.h:71
_BIOSGUARD_PROTOCOL::Write
BIOSGUARD_WRITE Write
Invoked to fill up BIOS Guard script buffer for flash writes.
Definition: Protocol/BiosGuard.h:123
gSmmBiosGuardProtocolGuid
EFI_GUID gSmmBiosGuardProtocolGuid
Extern the GUID for protocol users.
BIOSGUARD_WRITE
EFI_STATUS(* BIOSGUARD_WRITE)(IN BIOSGUARD_PROTOCOL *This, IN UINTN Address, IN UINT32 DataByteCount, IN OUT UINT8 *Buffer)
This service fills BIOS Guard script buffer for flash writes.
Definition: Protocol/BiosGuard.h:92
BIOSGUARD_ERASE
VOID(* BIOSGUARD_ERASE)(IN BIOSGUARD_PROTOCOL *This, IN UINTN Address)
This service fills BIOS Guard script buffer for erasing blocks in flash.
Definition: Protocol/BiosGuard.h:110
_BIOSGUARD_PROTOCOL
This protocol provides all the services required for flash writes/erases via BIOS Guard BIOS Guard Mo...
Definition: Protocol/BiosGuard.h:122
_BIOSGUARD_PROTOCOL::Execute
BIOSGUARD_EXECUTE Execute
Will trigger invocation of BIOS Guard module.
Definition: Protocol/BiosGuard.h:125
_BIOSGUARD_PROTOCOL::Erase
BIOSGUARD_ERASE Erase
Invoked to fill up BIOS Guard script buffer for flash erases.
Definition: Protocol/BiosGuard.h:124
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuardConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
Classes | Macros | Typedefs | Enumerations | Variables
BiosGuardConfig.h File Reference

CPU BIOS Guard Config Block. More...

#include <BiosGuard.h>
Include dependency graph for BiosGuardConfig.h:

Go to the source code of this file.

Classes

struct BIOS_GUARD_CONFIG
BIOS Guard Configuration Structure. More...

Macros

#define BIOS_GUARD_CONFIG_REVISION 1
BIOS Guard Configuration Revision.

Typedefs

typedef EFI_STATUS(* PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)
This function is for platform code to provide EC Commands since different BIOS might have different EC. More...

Enumerations

enum EC_COMMAND_TYPE
Enums for EC Command Type.

Variables

EFI_GUID gBiosGuardConfigGuid
BIOS Guard Configuration GUID.

Detailed Description

CPU BIOS Guard Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BiosGuardConfig.h.

Typedef Documentation

◆ PLATFORM_SEND_EC_COMMAND

typedef EFI_STATUS( * PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)

This function is for platform code to provide EC Commands since different BIOS might have different EC.

Platform code need to provide a function for CPU code to call to communicate with EC.

Parameters
[in] | EcCmdType | - EC Command Type.
[in] | EcCmd | - EC Command Byte to send.
[in] | SendData | - EC Data Byte to send.
[in] | ReceiveData | - EC Data Byte received.
Return values
EFI_SUCCESS | Command Read/ Write Success.
EFI_DEVICE_ERROR | Command Read/ Write Error.
EFI_OUT_OF_RESOURCES | No enough resources (such as out of memory).

Definition at line 93 of file BiosGuardConfig.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuardConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
BiosGuardConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU BIOS Guard Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _BIOS_GUARD_CONFIG_H_
36 #define _BIOS_GUARD_CONFIG_H_
37
38 #include <BiosGuard.h>
39
40 #define BIOS_GUARD_CONFIG_REVISION 1 ///< BIOS Guard Configuration Revision
41
42 extern EFI_GUID gBiosGuardConfigGuid; ///< BIOS Guard Configuration GUID
43
44 #pragma pack (push,1)
45
46 /**
47 BIOS Guard Configuration Structure.
48 Platform policies for BIOS Guard Configuration for all processor security features configuration.
49 Platform code can pass relevant configuration data through this structure.
50 @note <b>Optional.</b> These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> BiosGuard is disabled, or PeiBiosGuardLibNull is used.
51
52 <b>Revision 1</b>:
53 - Initial version.
54 **/
55 typedef struct {
56 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
57 BIOSGUARD_ATTRIBUTES BiosGuardAttr; ///< BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy, BIT4 - Flash wearout protection, BIT5 - FTU enable
58 UINT64 BgpdtHash[4]; ///< Hash of the BGPDT that will be programmed to PLAT_FRMW_PROT_HASH_0/1/2/3 MSR.
59 EFI_PHYSICAL_ADDRESS BiosGuardModulePtr; ///< Pointer to the BIOS Guard Module.
60 EFI_PHYSICAL_ADDRESS SendEcCmd; ///< Platform code can provide interface to communicate with EC through this function.
61 UINT8 EcCmdProvisionEav; ///< EC Command Provision Eav.
62 UINT8 EcCmdLock; ///< EC Command Lock.
63
64 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
65 UINT8 Reserved[6]; ///< Reserved for future use and config block alignment.
66 } BIOS_GUARD_CONFIG;
67 #pragma pack (pop)
68
69 ///
70 /// Enums for EC Command Type
71 ///
72 typedef enum {
73 SendEcCmds = 1,
74 SendEcValue,
75 ReceiveEcValue,
76 EcCmdMax
77 } EC_COMMAND_TYPE;
78
79 /**
80 This function is for platform code to provide EC Commands since different BIOS might have different EC.
81 Platform code need to provide a function for CPU code to call to communicate with EC.
82
83 @param[in] EcCmdType - EC Command Type.
84 @param[in] EcCmd - EC Command Byte to send.
85 @param[in] SendData - EC Data Byte to send.
86 @param[in] ReceiveData - EC Data Byte received.
87
88 @retval EFI_SUCCESS Command Read/ Write Success.
89 @retval EFI_DEVICE_ERROR Command Read/ Write Error.
90 @retval EFI_OUT_OF_RESOURCES No enough resources (such as out of memory).
91 **/
92 typedef
93 EFI_STATUS
94 (EFIAPI *PLATFORM_SEND_EC_COMMAND) (
95 IN EC_COMMAND_TYPE EcCmdType,
96 IN UINT8 EcCmd,
97 IN UINT8 SendData,
98 IN OUT UINT8 *ReceiveData
99 );
100
101 #endif // _BIOS_GUARD_CONFIG_H_
BIOS_GUARD_CONFIG::BiosGuardModulePtr
EFI_PHYSICAL_ADDRESS BiosGuardModulePtr
Pointer to the BIOS Guard Module.
Definition: BiosGuardConfig.h:59
BIOS_GUARD_CONFIG::EcCmdProvisionEav
UINT8 EcCmdProvisionEav
EC Command Provision Eav.
Definition: BiosGuardConfig.h:61
EC_COMMAND_TYPE
EC_COMMAND_TYPE
Enums for EC Command Type.
Definition: BiosGuardConfig.h:72
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
BIOSGUARD_ATTRIBUTES
BIOSGUARD_ATTRIBUTES
BIOS Guard attribute definition.
Definition: BiosGuard.h:121
BIOS_GUARD_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: BiosGuardConfig.h:56
BIOS_GUARD_CONFIG::EcCmdLock
UINT8 EcCmdLock
EC Command Lock.
Definition: BiosGuardConfig.h:62
gBiosGuardConfigGuid
EFI_GUID gBiosGuardConfigGuid
BIOS Guard Configuration GUID.
BIOS_GUARD_CONFIG
BIOS Guard Configuration Structure.
Definition: BiosGuardConfig.h:55
PLATFORM_SEND_EC_COMMAND
EFI_STATUS(* PLATFORM_SEND_EC_COMMAND)(IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData)
This function is for platform code to provide EC Commands since different BIOS might have different E...
Definition: BiosGuardConfig.h:94
BIOS_GUARD_CONFIG::BiosGuardAttr
BIOSGUARD_ATTRIBUTES BiosGuardAttr
BIT1 - EC Present, BIT2 - EC BIOS Guard protection, BIT3 - Descriptor Override policy,...
Definition: BiosGuardConfig.h:57
BIOS_GUARD_CONFIG::SendEcCmd
EFI_PHYSICAL_ADDRESS SendEcCmd
Platform code can provide interface to communicate with EC through this function.
Definition: BiosGuardConfig.h:60
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BootGuardLibVer1.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Classes | Enumerations | Functions
BootGuardLibVer1.h File Reference

Header file for Boot Guard Lib implementation. More...

Go to the source code of this file.

Classes

struct BOOT_GUARD_INFO
Information related to Boot Guard Configuration. More...

Enumerations

enum TPM_TYPE
The TPM category, TPM 1.2, TPM 2.0 and PTT are defined. More...

Functions

BOOLEAN | IsBootGuardSupported (VOID)
Determine if Boot Guard is supported. More...
VOID | HandleTpmStartupFailureOnS3 (IN BOOT_GUARD_INFO *BootGuardInfo)
Handle Tpm2Startup (State) failures reported by ACM. More...
VOID | GetBootGuardInfo (OUT BOOT_GUARD_INFO *BootGuardInfo)
Report platform specific Boot Guard information. More...

Detailed Description

Header file for Boot Guard Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BootGuardLibVer1.h.

Enumeration Type Documentation

◆ TPM_TYPE

enum TPM_TYPE

The TPM category, TPM 1.2, TPM 2.0 and PTT are defined.

Enumerator
TpmNone | 0: No TPM device present on system
dTpm12 | 1: TPM 1.2 device present on system
dTpm20 | 2: TPM 2.0 device present on system
Ptt | 3: PTT present on system
TpmTypeMax | 4: Unknown device

Definition at line 42 of file BootGuardLibVer1.h.

Function Documentation

◆ GetBootGuardInfo()

VOID GetBootGuardInfo ( OUT BOOT_GUARD_INFO * BootGuardInfo )

Report platform specific Boot Guard information.

Parameters
[out] *BootGuardInfo - Pointer to BootGuardInfo.

◆ HandleTpmStartupFailureOnS3()

VOID HandleTpmStartupFailureOnS3 ( IN BOOT_GUARD_INFO * BootGuardInfo )

Handle Tpm2Startup (State) failures reported by ACM.

The function checks for the TpmStartupFailureOnS3 flag if TRUE it will request the system to perform a cold reset.

Parameters
[in] *BootGuardInfo - Pointer to BootGuardInfo.

◆ IsBootGuardSupported()

BOOLEAN IsBootGuardSupported ( VOID )

Determine if Boot Guard is supported.

Return values
TRUE | - Processor is Boot Guard capable.
FALSE | - Processor is not Boot Guard capable.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BootGuardLibVer1.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
BootGuardLibVer1.h
Go to the documentation of this file.
1 /** @file
2 Header file for Boot Guard Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _BOOT_GUARD_LIB_C1SH_
37 #define _BOOT_GUARD_LIB_C1SH_
38
39 ///
40 /// The TPM category, TPM 1.2, TPM 2.0 and PTT are defined.
41 ///
42 typedef enum {
43 TpmNone = 0, ///< 0: No TPM device present on system
44 dTpm12, ///< 1: TPM 1.2 device present on system
45 dTpm20, ///< 2: TPM 2.0 device present on system
46 Ptt, ///< 3: PTT present on system
47 TpmTypeMax ///< 4: Unknown device
48 } TPM_TYPE;
49
50 ///
51 /// Information related to Boot Guard Configuration.
52 ///
53 typedef struct {
54 BOOLEAN MeasuredBoot; ///< Report Measured Boot setting in Boot Guard profile. 0: Disable; 1: Enable.
55 /**
56 ByPassTpmInit is set to 1 if Boot Guard ACM does TPM initialization successfully.
57 - 0: No TPM initialization happen in Boot Guard ACM.
58 - 1: TPM initialization is done by Boot Guard ACM.
59 **/
60 BOOLEAN BypassTpmInit;
61 TPM_TYPE TpmType; ///< Report what TPM device is available on system.
62 BOOLEAN BootGuardCapability; ///< Value is set to 1 if chipset is Boot Guard capable.
63 /**
64 Value is set to 1 if microcode failed to load Boot Guard ACM or ENF Shutdown path is taken by ME FW.
65 - 0: BIOS TPM code continue with TPM initization based on MeasuredBoot.
66 - 1: BIOS TPM code is not to do any futher TPM initization and extends.
67 **/
68 BOOLEAN DisconnectAllTpms;
69 /**
70 It is indicated BIOS TPM code is not to create DetailPCR or AuthorityPCR event log if Sx resume type is S3,
71 Deep-S3, or iFFS Resume.
72 - 0: Create TPM event log if not Sx Resume Type.
73 - 1: Bypass TPM Event Log if Sx Resume Type is identified.
74 **/
75 BOOLEAN ByPassTpmEventLog;
76 /**
77 This field indicates that the ACM's Tpm2Startup (State) command failed during S3 resume.
78 - 0: Successful Tpm2Startup (State)
79 - 1: Failure during Tpm2Startup (State). BIOS will need to perform a cold reset to handle the error.
80 **/
81 BOOLEAN TpmStartupFailureOnS3;
82
83 } BOOT_GUARD_INFO;
84
85 /**
86 Determine if Boot Guard is supported
87
88 @retval TRUE - Processor is Boot Guard capable.
89 @retval FALSE - Processor is not Boot Guard capable.
90
91 **/
92 BOOLEAN
93 IsBootGuardSupported (
94 VOID
95 );
96
97 /**
98 Handle Tpm2Startup (State) failures reported by ACM.
99
100 The function checks for the TpmStartupFailureOnS3 flag if TRUE it will
101 request the system to perform a cold reset.
102
103 @param[in] *BootGuardInfo - Pointer to BootGuardInfo.
104 **/
105 VOID
106 HandleTpmStartupFailureOnS3(
107 IN BOOT_GUARD_INFO *BootGuardInfo
108 );
109
110 /**
111 Report platform specific Boot Guard information.
112
113 @param[out] *BootGuardInfo - Pointer to BootGuardInfo.
114 **/
115 VOID
116 GetBootGuardInfo (
117 OUT BOOT_GUARD_INFO *BootGuardInfo
118 );
119
120 #endif
dTpm20
@ dTpm20
2: TPM 2.0 device present on system
Definition: BootGuardLibVer1.h:45
BOOT_GUARD_INFO::BypassTpmInit
BOOLEAN BypassTpmInit
ByPassTpmInit is set to 1 if Boot Guard ACM does TPM initialization successfully.
Definition: BootGuardLibVer1.h:60
BOOT_GUARD_INFO::MeasuredBoot
BOOLEAN MeasuredBoot
Report Measured Boot setting in Boot Guard profile. 0: Disable; 1: Enable.
Definition: BootGuardLibVer1.h:54
TpmNone
@ TpmNone
0: No TPM device present on system
Definition: BootGuardLibVer1.h:43
BOOT_GUARD_INFO
Information related to Boot Guard Configuration.
Definition: BootGuardLibVer1.h:53
BOOT_GUARD_INFO::TpmStartupFailureOnS3
BOOLEAN TpmStartupFailureOnS3
This field indicates that the ACM's Tpm2Startup (State) command failed during S3 resume.
Definition: BootGuardLibVer1.h:81
BOOT_GUARD_INFO::ByPassTpmEventLog
BOOLEAN ByPassTpmEventLog
It is indicated BIOS TPM code is not to create DetailPCR or AuthorityPCR event log if Sx resume type ...
Definition: BootGuardLibVer1.h:75
BOOT_GUARD_INFO::TpmType
TPM_TYPE TpmType
Report what TPM device is available on system.
Definition: BootGuardLibVer1.h:61
TPM_TYPE
TPM_TYPE
The TPM category, TPM 1.2, TPM 2.0 and PTT are defined.
Definition: BootGuardLibVer1.h:42
TpmTypeMax
@ TpmTypeMax
4: Unknown device
Definition: BootGuardLibVer1.h:47
IsBootGuardSupported
BOOLEAN IsBootGuardSupported(VOID)
Determine if Boot Guard is supported.
Ptt
@ Ptt
3: PTT present on system
Definition: BootGuardLibVer1.h:46
HandleTpmStartupFailureOnS3
VOID HandleTpmStartupFailureOnS3(IN BOOT_GUARD_INFO *BootGuardInfo)
Handle Tpm2Startup (State) failures reported by ACM.
BOOT_GUARD_INFO::DisconnectAllTpms
BOOLEAN DisconnectAllTpms
Value is set to 1 if microcode failed to load Boot Guard ACM or ENF Shutdown path is taken by ME FW.
Definition: BootGuardLibVer1.h:68
GetBootGuardInfo
VOID GetBootGuardInfo(OUT BOOT_GUARD_INFO *BootGuardInfo)
Report platform specific Boot Guard information.
dTpm12
@ dTpm12
1: TPM 1.2 device present on system
Definition: BootGuardLibVer1.h:44
BOOT_GUARD_INFO::BootGuardCapability
BOOLEAN BootGuardCapability
Value is set to 1 if chipset is Boot Guard capable.
Definition: BootGuardLibVer1.h:62
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BootMediaLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
BootMediaLib.h File Reference

Header file for the Boot Media Library. More...

#include <Uefi.h>
Include dependency graph for BootMediaLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | GetBootMediaType (OUT BOOT_MEDIA_TYPE *BootMedia)
Determines the current platform boot media device. More...
BOOLEAN | BootMediaIsKnown (VOID)
Determines if the boot media is presently known. More...
BOOLEAN | BootMediaIsSpi (VOID)
Determines if the platform firmware is booting from SPI or not. More...
BOOLEAN | BootMediaIsUfs (VOID)
Determines if the platform firmware is booting from UFS or not. More...

Detailed Description

Header file for the Boot Media Library.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification

Definition in file BootMediaLib.h.

Function Documentation

◆ BootMediaIsKnown()

BOOLEAN BootMediaIsKnown ( VOID )

Determines if the boot media is presently known.

Note: Very early in boot this data may not be available.

Return values
TRUE | Boot media is known
FALSE | Boot media is not known

◆ BootMediaIsSpi()

BOOLEAN BootMediaIsSpi ( VOID )

Determines if the platform firmware is booting from SPI or not.

Return values
TRUE | Platform firmware is booting from SPI
FALSE | Platform firmware is booting from a non-SPI device (eMMC, UFS, etc.)

◆ BootMediaIsUfs()

BOOLEAN BootMediaIsUfs ( VOID )

Determines if the platform firmware is booting from UFS or not.

Return values
TRUE | Platform firmware is booting from UFS
FALSE | Platform firmware is booting from a non-UFS device (eMMC, SPI, etc.)

◆ GetBootMediaType()

EFI_STATUS GetBootMediaType ( OUT BOOT_MEDIA_TYPE * BootMedia )

Determines the current platform boot media device.

Parameters
[out] BootMedia The current platform Boot Media type.
Return values
EFI_SUCCESS | The operation completed successfully.
EFI_NOT_FOUND | The boot media type could not be found.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BootMediaLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
BootMediaLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the Boot Media Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 @par Specification
21 **/
22
23 #ifndef _BOOT_MEDIA_LIB_H_
24 #define _BOOT_MEDIA_LIB_H_
25
26 #include <Uefi.h>
27
28 typedef enum {
29 BootMediaSpi,
30 BootMediaUfs,
31 BootMediaMax
32 } BOOT_MEDIA_TYPE;
33
34 typedef struct {
35 BOOT_MEDIA_TYPE BootMedia;
36 } BOOT_MEDIA_HOB_DATA;
37
38 /**
39 Determines the current platform boot media device.
40
41 @param[out] BootMedia The current platform Boot Media type.
42
43 @retval EFI_SUCCESS The operation completed successfully.
44 @retval EFI_NOT_FOUND The boot media type could not be found.
45 **/
46 EFI_STATUS
47 EFIAPI
48 GetBootMediaType (
49 OUT BOOT_MEDIA_TYPE *BootMedia
50 );
51
52 /**
53 Determines if the boot media is presently known.
54
55 Note: Very early in boot this data may not be available.
56
57 @retval TRUE Boot media is known
58 @retval FALSE Boot media is not known
59 **/
60 BOOLEAN
61 EFIAPI
62 BootMediaIsKnown (
63 VOID
64 );
65
66 /**
67 Determines if the platform firmware is booting from SPI or not.
68
69 @retval TRUE Platform firmware is booting from SPI
70 @retval FALSE Platform firmware is booting from a non-SPI device (eMMC, UFS, etc.)
71 **/
72 BOOLEAN
73 EFIAPI
74 BootMediaIsSpi (
75 VOID
76 );
77
78 /**
79 Determines if the platform firmware is booting from UFS or not.
80
81 @retval TRUE Platform firmware is booting from UFS
82 @retval FALSE Platform firmware is booting from a non-UFS device (eMMC, SPI, etc.)
83 **/
84 BOOLEAN
85 EFIAPI
86 BootMediaIsUfs (
87 VOID
88 );
89
90 #endif
BootMediaIsSpi
BOOLEAN BootMediaIsSpi(VOID)
Determines if the platform firmware is booting from SPI or not.
GetBootMediaType
EFI_STATUS GetBootMediaType(OUT BOOT_MEDIA_TYPE *BootMedia)
Determines the current platform boot media device.
BootMediaIsUfs
BOOLEAN BootMediaIsUfs(VOID)
Determines if the platform firmware is booting from UFS or not.
BootMediaIsKnown
BOOLEAN BootMediaIsKnown(VOID)
Determines if the boot media is presently known.
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BupMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
BupMsgs.h File Reference

BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW. More...

#include <MeBiosPayloadData.h>
Include dependency graph for BupMsgs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | GET_IMR_CMD_REQ_DATA
Get IMR size message. More...
struct | ICC_MESSAGE_RESP_DATA
ICC group defines. More...
struct | BUP_MPHY_READ_FROM_MPHY
MPHY group defines. More...
struct | HR_NOTIFICATION_CMD
PM group defines. More...

Macros

#define | BUP_COMMON_GROUP_ID 0xF0
BUP group IDs.
#define | DRAM_INIT_DONE_CMD 0x01
Defines for Command. More...
#define | ICC_CMD 0x01
Defines for BUP_MPHY_GROUP_ID Command.
#define | MPHY_READ_FROM_MPHY_CMD 0x2
Defines for BUP_MPHY_GROUP_ID Command.
#define | NPCR_NOTIFICATION_CMD 0x1
Defines for BUP_PM_GROUP_ID Command.
#define | BIOS_MSG_DID_SUCCESS 0
Common group definitions. More...
#define | DID_ACK_NON_PCR 0x1
BIOS Reset Action Codes.

Enumerations

enum STREAMING_TRACE_SINK
Enable Debug Transports specifying Power Controls. More...

Detailed Description

BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file BupMsgs.h.

Macro Definition Documentation

◆ BIOS_MSG_DID_SUCCESS

#define BIOS_MSG_DID_SUCCESS 0

Common group definitions.

DRAM Init Done definitions Memory Init Status codes

Definition at line 95 of file BupMsgs.h.

◆ DRAM_INIT_DONE_CMD

#define DRAM_INIT_DONE_CMD 0x01

Defines for Command.

Defines for BUP_COMMON_GROUP_ID Command

Definition at line 56 of file BupMsgs.h.

Enumeration Type Documentation

◆ STREAMING_TRACE_SINK

enum STREAMING_TRACE_SINK

Enable Debug Transports specifying Power Controls.

0000: Use existing setup settings 0001: Enable DCI.OOB + DCI.DBC w/ power overrides. 0010: Enable DCI.OOB-2 w/o power overrides. 0011: Disable Debug. Everything else is reserved.

Definition at line 336 of file BupMsgs.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BupMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
BupMsgs.h
Go to the documentation of this file.
1 /** @file
2 BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _BUP_MSGS_H
36 #define _BUP_MSGS_H
37
38 #include <MeBiosPayloadData.h>
39
40 #pragma pack(1)
41
42 ///
43 /// BUP group IDs
44 ///
45 #define BUP_COMMON_GROUP_ID 0xF0
46 #define BUP_ICC_GROUP_ID 0xF1
47 #define BUP_MPHY_GROUP_ID 0xF2
48 #define BUP_PM_GROUP_ID 0xF3
49
50 ///
51 /// Defines for Command
52 ///
53 ///
54 /// Defines for BUP_COMMON_GROUP_ID Command
55 ///
56 #define DRAM_INIT_DONE_CMD 0x01
57 #define MBP_REQUEST_CMD 0x02
58 #define ME_ENABLE_CMD 0x03
59 #define HMRFPO_DISABLE_CMD 0x04
60 #define TERMINATE_HECI_CMD 0x05
61 #define GET_IMR_SIZE_CMD 0x0C
62 #define MANUF_RESET_AND_HALT_CMD 0x0E
63 #define BUP_GET_ME_TYPE 0x11
64 #define GET_ER_LOG_CMD 0x1B
65 #define SET_EDEBUG_STATE_CMD 0x1E
66 #define DATA_CLEAR_CMD 0x20
67 #define GET_IP_FIRMWARE_CMD 0x21
68 #define GET_DEBUG_TOKEN_DATA_CMD 0x22
69 #define GET_BIOS_SEED_CMD 0x23
70
71 ///
72 /// Defines for BUP_MPHY_GROUP_ID Command
73 ///
74 #define ICC_CMD 0x01
75 ///
76 /// Defines for BUP_MPHY_GROUP_ID Command
77 ///
78 #define MPHY_READ_FROM_MPHY_CMD 0x2
79 ///
80 /// Defines for BUP_PM_GROUP_ID Command
81 ///
82 #define NPCR_NOTIFICATION_CMD 0x1
83
84 ///
85 /// Common group definitions
86 ///
87
88 ///
89 /// DRAM Init Done definitions
90 ///
91
92 ///
93 /// Memory Init Status codes
94 ///
95 #define BIOS_MSG_DID_SUCCESS 0
96 #define BIOS_MSG_DID_NO_MEMORY 0x1
97 #define BIOS_MSG_DID_INIT_ERROR 0x2
98
99 typedef struct {
100 UINT32 BiosImrsBaLow;
101 UINT32 BiosImrsBaHigh;
102 } DRAM_INIT_DONE_IMRS_REQ_DATA;
103
104 typedef struct {
105 MKHI_MESSAGE_HEADER MkhiHeader;
106 DRAM_INIT_DONE_IMRS_REQ_DATA ImrData;
107 UINT32 Flags;
108 UINT8 Reserved1[2];
109 UINT8 MemStatus;
110 UINT8 Reserved2;
111 } DRAM_INIT_DONE_CMD_REQ;
112
113 //
114 // Response Flags Definitions
115 //
116 #define ME_OPTIMIZED_BOOT_FLAG BIT1
117
118 ///
119 /// BIOS Reset Action Codes
120 ///
121 #define DID_ACK_NON_PCR 0x1
122 #define DID_ACK_PCR 0x2
123 #define DID_ACK_GRST 0x3
124
125 typedef struct {
126 UINT32 AdrLow;
127 UINT32 AdrHigh;
128 } PCI_2_PRIV_BASE;
129
130 typedef struct {
131 MKHI_MESSAGE_HEADER MkhiHeader;
132 UINT32 Reserved1[4];
133 PCI_2_PRIV_BASE Pci2PrivBase;
134 UINT8 Flags;
135 UINT8 BiosAction;
136 UINT8 Reserved2[6];
137 } DRAM_INIT_DONE_CMD_RESP;
138
139 typedef union {
140 DRAM_INIT_DONE_CMD_REQ Request;
141 DRAM_INIT_DONE_CMD_RESP Response;
142 } DRAM_INIT_DONE_CMD_BUFFER;
143
144 #define MAX_MBP_ITEMS_SIZE 125 * sizeof (UINT32)
145
146 typedef struct {
147 MKHI_MESSAGE_HEADER MkhiHeader;
148 UINT32 SkipMbp;
149 } GET_MBP_REQ;
150
151 typedef struct {
152 MKHI_MESSAGE_HEADER MkhiHeader;
153 MBP_HEADER MbpHeader;
154 UINT32 MbpItems[MAX_MBP_ITEMS_SIZE];
155 } GET_MBP_RESP;
156
157 typedef union {
158 GET_MBP_REQ Request;
159 GET_MBP_RESP Response;
160 } GET_MBP_BUFFER;
161
162 typedef struct {
163 MKHI_MESSAGE_HEADER MkhiHeader;
164 } ME_ENABLE_CMD_REQ;
165
166 typedef struct {
167 MKHI_MESSAGE_HEADER MkhiHeader;
168 } ME_ENABLE_CMD_RESP;
169
170 typedef struct {
171 MKHI_MESSAGE_HEADER MkhiHeader;
172 } HMRFPO_DISABLE_CMD_REQ;
173
174 typedef struct {
175 MKHI_MESSAGE_HEADER MkhiHeader;
176 } HMRFPO_DISABLE_CMD_RESP;
177
178 typedef union {
179 HMRFPO_DISABLE_CMD_REQ Request;
180 HMRFPO_DISABLE_CMD_RESP Response;
181 } HMRFPO_DISABLE_CMD_BUFFER;
182
183 typedef struct {
184 MKHI_MESSAGE_HEADER MkhiHeader;
185 UINT32 Reserved;
186 } TERMINATE_HECI_CMD_REQ;
187
188 ///
189 /// Get IMR size message
190 ///
191 typedef struct {
192 UINT32 BiosImrDisableMask0;
193 UINT32 BiosImrDisableMask1;
194 UINT32 Pci2PrivSize;
195 } GET_IMR_CMD_REQ_DATA;
196
197 typedef struct {
198 MKHI_MESSAGE_HEADER MkhiHeader;
199 GET_IMR_CMD_REQ_DATA Data;
200 } GET_IMR_CMD_REQ;
201
202 typedef struct {
203 UINT32 ImrsSize;
204 UINT32 Alignment;
205 UINT32 Flags;
206 } GET_IMR_CMD_RESP_DATA;
207
208 typedef struct {
209 MKHI_MESSAGE_HEADER MkhiHeader;
210 GET_IMR_CMD_RESP_DATA Data;
211 } GET_IMR_CMD_RESP;
212
213 typedef union {
214 GET_IMR_CMD_REQ Request;
215 GET_IMR_CMD_RESP Response;
216 } GET_IMR_CMD_BUFFER;
217
218 typedef struct {
219 MKHI_MESSAGE_HEADER MkhiHeader;
220 } MANUF_RESET_AND_HALT_REQ;
221
222 typedef struct {
223 MKHI_MESSAGE_HEADER MkhiHeader;
224 } MANUF_RESET_AND_HALT_RESP;
225
226 typedef union {
227 MANUF_RESET_AND_HALT_REQ Request;
228 MANUF_RESET_AND_HALT_RESP Response;
229 } MANUF_RESET_AND_HALT_BUFFER;
230
231 typedef struct {
232 UINT32 FwType : 3;
233 UINT32 FwSubType : 8;
234 UINT32 Reserved : 21;
235 } FW_TYPE_DATA;
236
237 typedef struct {
238 MKHI_MESSAGE_HEADER MkhiHeader;
239 FW_TYPE_DATA FwTypeData;
240 } GEN_GET_FW_TYPE_ACK;
241
242 typedef struct {
243 MKHI_MESSAGE_HEADER MkhiHeader;
244 } GEN_GET_FW_TYPE;
245
246 typedef union {
247 GEN_GET_FW_TYPE Request;
248 GEN_GET_FW_TYPE_ACK Response;
249 } GEN_GET_FW_TYPE_BUFFER;
250
251 typedef struct {
252 MKHI_MESSAGE_HEADER MkhiHeader;
253 UINT8 FirstLogEntryIndex;
254 UINT16 Flags;
255 UINT8 Reserved;
256 } GET_ER_LOG_CMD_REQ;
257
258 typedef struct {
259 MKHI_MESSAGE_HEADER MkhiHeader;
260 UINT8 MeasuredBootEnabled;
261 UINT8 FirstLogEntryIndex;
262 UINT8 LastLogEntryIndex;
263 UINT8 RemainingEntries;
264 UINT16 DataLength;
265 UINT8 LogData[]; // Data buffer
266 } GET_ER_LOG_CMD_RESP;
267
268 typedef union {
269 GET_ER_LOG_CMD_REQ Request;
270 GET_ER_LOG_CMD_RESP Response;
271 } GET_ER_LOG_BUFFER;
272
273 typedef struct {
274 MKHI_MESSAGE_HEADER MkhiHeader;
275 UINT32 State;
276 } SET_EDEBUG_MODE_STATE_REQ;
277
278 typedef struct {
279 MKHI_MESSAGE_HEADER MkhiHeader;
280 } SET_EDEBUG_MODE_STATE_RESP;
281
282 typedef union {
283 SET_EDEBUG_MODE_STATE_REQ Request;
284 SET_EDEBUG_MODE_STATE_RESP Response;
285 } SET_EDEBUG_MODE_STATE_BUFFER;
286
287 typedef struct {
288 MKHI_MESSAGE_HEADER MkhiHeader;
289 UINT32 Reserved;
290 } DATA_CLEAR_REQ;
291
292 typedef struct {
293 MKHI_MESSAGE_HEADER MkhiHeader;
294 } DATA_CLEAR_RESP;
295
296 typedef union {
297 DATA_CLEAR_REQ Request;
298 DATA_CLEAR_RESP Response;
299 } DATA_CLEAR_BUFFER;
300
301 #define MAX_DIGEST_SIZE 64
302 #define IP_LOADING_CMD_VERSION 1
303
304 typedef struct {
305 MKHI_MESSAGE_HEADER MkhiHeader;
306 UINT32 Version;
307 UINT32 Operation;
308 UINT32 DramBaseLow;
309 UINT32 DramBaseHigh;
310 UINT32 MemorySize;
311 UINT32 Reserved;
312 } IP_LOADING_CMD_REQ;
313
314 typedef struct {
315 MKHI_MESSAGE_HEADER MkhiHeader;
316 UINT32 PayloadSize;
317 UINT32 Reserved[2];
318 UINT32 Status;
319 UINT8 HashType;
320 UINT8 Hash[];
321 } IP_LOADING_CMD_RESP;
322
323 typedef union {
324 IP_LOADING_CMD_REQ Request;
325 IP_LOADING_CMD_RESP Response;
326 } IP_LOADING_CMD_BUFFER;
327
328 /**
329 Enable Debug Transports specifying Power Controls.
330 0000: Use existing setup settings</b>
331 0001: Enable DCI.OOB + DCI.DBC w/ power overrides.
332 0010: Enable DCI.OOB-2 w/o power overrides.
333 0011: Disable Debug.
334 Everything else is reserved.
335 **/
336 typedef enum {
337 SetupMenuDefault = 0x0,
338 EnabledAll = 0x1,
339 EnabledLowPower = 0x2,
340 ForceDisabled = 0x3
341 } STREAMING_TRACE_SINK;
342
343 typedef union {
344 struct {
345 UINT32 ExposeDebugMenu : 1; ///< Expose Debug Menu. 0: Debug menu is hidden; 1: Expose debug menu if hidden
346 /**
347 Refer to definition of STREAMING_TRACE_SINK
348 **/
349 UINT32 StreamingTraceSink : 4;
350 /**
351 Force TraceHub "on" unconditionally.
352 0: Normal. BIOS shall enable or disable TraceHub according to the value of BIT24 in scratchpad 0 register or BIOS menu configuration
353 1: Force on. BIOS shall keep TraceHub enabled unconditionally
354 **/
355 UINT32 TraceHubForceOn : 1;
356 UINT32 TraceEnable : 1; ///< Enable BIOS traces. 0: Normal behavior; 1: Enable Trace Messaging
357 UINT32 JtagC10PgDis : 1; ///< Disable JTAG C10 power gate 0: Normal behavior (Follow BIOS menu configuration); 1: Disable JTAG C10 power gate
358 UINT32 UsbOverCurrentOvrd : 1; ///< Enable USB overcurrent override. 0: Normal behavior (Follow BIOS menu configuration); 1: Enable USB overcurrent override
359 UINT32 IntelReserved : 7; ///< Reserved for future Intel use
360 UINT32 OemReserved : 16; ///< Reserved for OEM use
361 } Fields;
362 UINT32 Data;
363 } DEBUG_TOKEN_KNOB_DATA;
364
365 #define BOOTLOADER_SEED_LEN_EX 64
366 #define BIOS_ADDITIONAL_DATA_LEN 48
367
368 typedef struct {
369 UINT32 SeedDebugProperty : 1;
370 UINT32 SeedHwFpfProperty : 1;
371 UINT32 SeedBtgProperty : 1;
372 UINT32 SeedType : 3;
373 UINT32 SeedLength : 2;
374 UINT32 Reserved : 24;
375 } SEED_PROPERTIES_BIT_MAP;
376
377 typedef struct {
378 UINT32 IsIntelUnlocked : 1;
379 UINT32 IsOemUnlocked : 1;
380 UINT32 IsDamEnabled : 1;
381 UINT32 IsHwFpfEnabled : 1;
382 UINT32 IsBtgEnabled : 1;
383 UINT32 Reserved : 27;
384 } SEED_INFO_BIT_MAP;
385
386 typedef struct {
387 UINT8 CsmeSvn;
388 UINT8 BiosSvn;
389 SEED_INFO_BIT_MAP SeedInfoBitMap;
390 } SEED_INFO;
391
392 typedef struct {
393 UINT8 CsmeSvn;
394 UINT8 BiosSvn;
395 SEED_PROPERTIES_BIT_MAP SeedPropertiesBitMap;
396 UINT8 BiosAdditionalData[BIOS_ADDITIONAL_DATA_LEN];
397 } SEED_PROPERTIES;
398
399 typedef struct {
400 MKHI_MESSAGE_HEADER MkhiHeader;
401 SEED_PROPERTIES BiosSeedProperties;
402 UINT8 LockSeedGeneration;
403 } GET_BIOS_SEED_REQ;
404
405 typedef struct {
406 MKHI_MESSAGE_HEADER MkhiHeader;
407 UINT32 EphemeralKeyCounter;
408 SEED_INFO BiosSeedInfo;
409 UINT8 BiosSeed[BOOTLOADER_SEED_LEN_EX];
410 } GET_BIOS_SEED_RESP;
411
412 typedef union {
413 GET_BIOS_SEED_REQ Request;
414 GET_BIOS_SEED_RESP Response;
415 } GET_BIOS_SEED_BUFFER;
416
417 typedef struct {
418 MKHI_MESSAGE_HEADER MkhiHeader;
419 } GET_DEBUG_TOKEN_DATA_REQ;
420
421 typedef struct {
422 MKHI_MESSAGE_HEADER MkhiHeader;
423 UINT8 TokenId; ///< 1: Intel Token. 2: OEM Token
424 UINT8 Reserved[3];
425 DEBUG_TOKEN_KNOB_DATA KnobData;
426 } GET_DEBUG_TOKEN_DATA_RESP;
427
428 typedef union {
429 GET_DEBUG_TOKEN_DATA_REQ Request;
430 GET_DEBUG_TOKEN_DATA_RESP Response;
431 } GET_DEBUG_TOKEN_DATA_BUFFER;
432
433 ///
434 /// ICC group defines
435 ///
436 typedef struct {
437 UINT32 FwNeedsWarmResetFlag:1; ///< BIT0
438 UINT32 Reserved:31; ///< BIT1-31
439 } ICC_MESSAGE_RESP_DATA;
440
441 typedef struct {
442 MKHI_MESSAGE_HEADER MkhiHeader;
443 } ICC_CMD_REQ;
444
445 typedef struct {
446 MKHI_MESSAGE_HEADER MkhiHeader;
447 ICC_MESSAGE_RESP_DATA Data;
448 } ICC_CMD_RESP;
449
450 typedef union {
451 ICC_CMD_REQ Request;
452 ICC_CMD_RESP Response;
453 } ICC_CMD_BUFFER;
454
455 ///
456 /// MPHY group defines
457 ///
458 typedef struct{
459 MKHI_MESSAGE_HEADER MkhiHeader;
460 UINT32 Reserved1;
461 UINT32 Offset;
462 UINT32 Reserved2;
463 UINT32 NumOfBytes;
464 } BUP_MPHY_READ_FROM_MPHY;
465
466 typedef struct {
467 MKHI_MESSAGE_HEADER MkhiHeader;
468 UINT32 Reserved1;
469 UINT32 FileSize;
470 UINT32 Reserved2;
471 UINT32 ReadSize;
472 UINT32 Reserved3;
473 UINT8 Data[];
474 } BUP_MPHY_READ_FROM_MPHY_ACK;
475
476 typedef union {
477 BUP_MPHY_READ_FROM_MPHY Request;
478 BUP_MPHY_READ_FROM_MPHY_ACK Response;
479 } BUP_MPHY_READ_FROM_MPHY_BUFFER;
480
481 ///
482 /// PM group defines
483 ///
484 typedef struct {
485 MKHI_MESSAGE_HEADER MkhiHeader;
486 } HR_NOTIFICATION_CMD;
487
488 typedef struct {
489 MKHI_MESSAGE_HEADER MkhiHeader;
490 UINT8 ResetRequested;
491 } HR_NOTIFICATION_CMD_RESP;
492
493 typedef union {
494 HR_NOTIFICATION_CMD Request;
495 HR_NOTIFICATION_CMD_RESP Response;
496 } HR_NOTIFICATION_BUFFER;
497
498 #pragma pack()
499
500 #endif // _BUP_MSGS_H
501
ICC_MESSAGE_RESP_DATA
ICC group defines.
Definition: BupMsgs.h:436
GET_IMR_CMD_REQ_DATA
Get IMR size message.
Definition: BupMsgs.h:191
HR_NOTIFICATION_CMD
PM group defines.
Definition: BupMsgs.h:484
MKHI_MESSAGE_HEADER
MKHI host message header.
Definition: MkhiMsgs.h:46
BUP_MPHY_READ_FROM_MPHY
MPHY group defines.
Definition: BupMsgs.h:458
STREAMING_TRACE_SINK
STREAMING_TRACE_SINK
Enable Debug Transports specifying Power Controls.
Definition: BupMsgs.h:336
ICC_MESSAGE_RESP_DATA::FwNeedsWarmResetFlag
UINT32 FwNeedsWarmResetFlag
BIT0.
Definition: BupMsgs.h:437
ICC_MESSAGE_RESP_DATA::Reserved
UINT32 Reserved
BIT1-31.
Definition: BupMsgs.h:438
MBP_HEADER
Common MBP types.
Definition: MeBiosPayloadData.h:55
MeBiosPayloadData.h
Interface definition details for MBP.
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CacheAsRamLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
CacheAsRamLib.h File Reference

Go to the source code of this file.

Functions

VOID DisableCacheAsRam (IN BOOLEAN DisableCar)
This function disable CAR. More...

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright (c) 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file CacheAsRamLib.h.

Function Documentation

◆ DisableCacheAsRam()

VOID DisableCacheAsRam ( IN BOOLEAN DisableCar )

This function disable CAR.

Parameters
[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CacheAsRamLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
CacheAsRamLib.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #ifndef _CACHE_AS_RAM_LIB_H_
17 #define _CACHE_AS_RAM_LIB_H_
18
19 /**
20 This function disable CAR.
21
22 @param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD
23
24 **/
25 VOID
26 EFIAPI
27 DisableCacheAsRam (
28 IN BOOLEAN DisableCar
29 );
30
31 #endif
32
DisableCacheAsRam
VOID DisableCacheAsRam(IN BOOLEAN DisableCar)
This function disable CAR.
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ChipsetInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Classes
ChipsetInfoHob.h File Reference

This file contains definitions of Chipset Info HOB. More...

Go to the source code of this file.

Classes

struct CHIPSET_INIT_INFO
Revision 1: - Initial version. More...

Detailed Description

This file contains definitions of Chipset Info HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ChipsetInfoHob.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ChipsetInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
ChipsetInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of Chipset Info HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CHIPSET_INFO_HOB_H_
36 #define _CHIPSET_INFO_HOB_H_
37
38 /**
39 <b>Revision 1</b>: - Initial version.
40 <b>Revision 2</b>: - Added ChipsetInit version 3.
41 The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
42 **/
43 typedef struct {
44 UINT8 Revision;
45 UINT8 BaseVersion;
46 UINT8 OemVersion;
47 UINT8 Rsvd;
48 UINT16 BaseCrc;
49 UINT16 SusCrc;
50 UINT16 OemCrc;
51 UINT16 IntelMajor; // ChipsetInit Version 3
52 UINT16 IntelMinor; // ChipsetInit Version 3
53 UINT16 IntelHotFix; // ChipsetInit Version 3
54 UINT16 IntelBuild; // ChipsetInit Version 3
55 UINT16 OemMajor; // ChipsetInit Version 3
56 UINT16 OemMinor; // ChipsetInit Version 3
57 UINT16 OemHotFix; // ChipsetInit Version 3
58 UINT16 OemBuild; // ChipsetInit Version 3
59 UINT8 Rsvd1[2];
60 } CHIPSET_INIT_INFO;
61
62 extern EFI_GUID gChipsetInitHobGuid;
63
64 #define CHIPSET_INIT_INFO_REVISION 2
65
66 #endif // _CHIPSET_INFO_HOB_H_
67
CHIPSET_INIT_INFO
Revision 1: - Initial version.
Definition: ChipsetInfoHob.h:43
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Classes | Enumerations
CnviConfig.h File Reference

CNVi policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | CNVI_PIN_MUX
CNVi signals pin muxing settings. More...
struct | CNVI_CONFIG
The CNVI_CONFIG block describes the expected configuration of the CNVi IP. More...
struct | CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP. More...

Enumerations

enum CNVI_MODE
CNVi Mode options.

Detailed Description

CNVi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CnviConfig.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
CnviConfig.h
Go to the documentation of this file.
1 /** @file
2 CNVi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CNVI_CONFIG_H_
36 #define _CNVI_CONFIG_H_
37
38 #define CNVI_CONFIG_REVISION 4
39 extern EFI_GUID gCnviConfigGuid;
40
41 #define CNVI_PREMEM_CONFIG_REVISION 1
42 extern EFI_GUID gCnviPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 CNVi Mode options
48 **/
49 typedef enum {
50 CnviModeDisabled = 0,
51 CnviModeAuto
52 } CNVI_MODE;
53
54
55 /**
56 CNVi signals pin muxing settings. If signal can be enable only on a single pin
57 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in GpioPins*.h
58 for supported settings on a given platform
59 **/
60 typedef struct {
61 UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*
62 UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*
63 } CNVI_PIN_MUX;
64
65 /**
66 The CNVI_CONFIG block describes the expected configuration of the CNVi IP.
67
68 <b>Revision 1</b>: - Initial version.
69 <b>Revision 2</b>: - Add DdrRfim.
70 <b>Revision 3</b>: - Add WifiCore.
71 <b>Revision 4</b>: - Move DdrRfim to Pre-Mem config.
72 **/
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75 /**
76 This option allows for automatic detection of Connectivity Solution.
77 Auto Detection assumes that CNVi will be enabled when available;
78 Disable allows for disabling CNVi.
79 CnviModeDisabled = Disabled,
80 <b>CnviModeAuto = Auto Detection</b>
81 **/
82 UINT32 Mode : 1;
83 UINT32 BtCore : 1; ///< The option to turn ON or OFF the BT Core. 0: Disabled, <b>1: Enabled</b>
84 /**
85 The option to enable or disable BT Audio Offload.
86 <b>0: Disabled</b>, 1: Enabled
87 @note This feature only support with Intel(R) Wireless-AX 22560
88 **/
89 UINT32 BtAudioOffload : 1;
90 UINT32 WifiCore : 1; ///< The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, <b>1: Enabled</b>
91 UINT32 RsvdBits : 28;
92 /**
93 CNVi PinMux Configuration
94 RESET#/CLKREQ to CRF, can have two alternative mappings, depending on board routing requirements.
95 **/
96 CNVI_PIN_MUX PinMux;
97 } CNVI_CONFIG;
98
99
100 /**
101 The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
102
103 <b>Revision 1</b>: - Initial version.
104 **/
105 typedef struct {
106 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
107 UINT8 DdrRfim; ///< The option to enable or disable DDR RFI Mitigation. 0: Disabled, <b>1: Enabled</b>
108 UINT8 RsvdByte[3];
109 } CNVI_PREMEM_CONFIG;
110
111 #pragma pack (pop)
112
113 #endif // _CNVI_CONFIG_H_
CNVI_CONFIG::PinMux
CNVI_PIN_MUX PinMux
CNVi PinMux Configuration RESET#/CLKREQ to CRF, can have two alternative mappings,...
Definition: CnviConfig.h:96
CNVI_CONFIG::Mode
UINT32 Mode
This option allows for automatic detection of Connectivity Solution.
Definition: CnviConfig.h:82
CNVI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CnviConfig.h:106
CNVI_CONFIG::BtCore
UINT32 BtCore
The option to turn ON or OFF the BT Core. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:83
CNVI_PIN_MUX::Clkreq
UINT32 Clkreq
CLKREQ Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_*_CLKREQ_*.
Definition: CnviConfig.h:62
CNVI_CONFIG::WifiCore
UINT32 WifiCore
The option to turn ON or OFF the Wi-Fi Core. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:90
CNVI_PREMEM_CONFIG::DdrRfim
UINT8 DdrRfim
The option to enable or disable DDR RFI Mitigation. 0: Disabled, 1: Enabled
Definition: CnviConfig.h:107
CNVI_CONFIG
The CNVI_CONFIG block describes the expected configuration of the CNVi IP.
Definition: CnviConfig.h:73
CNVI_PIN_MUX
CNVi signals pin muxing settings.
Definition: CnviConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CNVI_PIN_MUX::RfReset
UINT32 RfReset
RF_RESET# Pin mux configuration. Refer to GPIO_*_MUXING_CNVI_RF_RESET_*.
Definition: CnviConfig.h:61
CNVI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CnviConfig.h:74
CNVI_MODE
CNVI_MODE
CNVi Mode options.
Definition: CnviConfig.h:49
CNVI_CONFIG::BtAudioOffload
UINT32 BtAudioOffload
The option to enable or disable BT Audio Offload.
Definition: CnviConfig.h:89
CNVI_PREMEM_CONFIG
The CNVI_PREMEM_CONFIG block describes the expected configuration of the CNVi IP.
Definition: CnviConfig.h:105
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
CnviLib.h File Reference

Header file for CnviLib. More...

Go to the source code of this file.

Functions

BOOLEAN CnviIsPresent (VOID)
Check if CNVi is present. More...

Detailed Description

Header file for CnviLib.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CnviLib.h.

Function Documentation

◆ CnviIsPresent()

BOOLEAN CnviIsPresent ( VOID )

Check if CNVi is present.

Return values
TRUE | CNVi is enabled
FALSE | CNVi is disabled
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
CnviLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for CnviLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CNVI_LIB_H_
36 #define _CNVI_LIB_H_
37
38 /**
39 Check if CNVi is present.
40
41 @retval TRUE CNVi is enabled
42 @retval FALSE CNVi is disabled
43
44 **/
45 BOOLEAN
46 CnviIsPresent (
47 VOID
48 );
49
50 #endif // _CNVI_LIB_H_
CnviIsPresent
BOOLEAN CnviIsPresent(VOID)
Check if CNVi is present.
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
CnviRegs.h File Reference

Register names for CNVi. More...

Go to the source code of this file.

Macros

#define | R_CNVI_CFG_WIFI_GIO_DEV_CAP 0x44
Device Capabilities.
#define | R_CNVI_CFG_WIFI_GIO_DEV_CTRL 0x48
Device Control.
#define | B_CNVI_CFG_WIFI_GIO_DEV_CTRL_FLR BIT15
FLR.
#define | R_CNVI_CFG_WIFI_GIO_DEV_CAP_2 0x64
Device Capabilities 2.
#define | B_CNVI_CFG_WIFI_GIO_DEV_CAP_2_LTR_MEC_SUP BIT11
LTR Mechanism Supported.
#define | R_CNVI_CFG_WIFI_GIO_DEV_2 0x68
Device Control 2.
#define | B_CNVI_CFG_WIFI_GIO_DEV_2_LTR_MEC_EN BIT10
LTR Mechanism Enable.
#define | R_CNVI_CFG_WIFI_PMCSR 0xCC
Power Management Status and Control Register.
#define | B_CNVI_CFG_WIFI_PMCSR_PS (BIT0 | BIT1)
Power State.
#define | R_CNVI_PCR_WIFI_WIDGET_CONTROL 0x8114
Widget Control.
#define | B_CNVI_PCR_WIFI_WIDGET_CONTROL_MEM_INT 0xFF
IRQ number.

Detailed Description

Register names for CNVi.

Conventions:

  • Prefixes: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register sizes Definitions beginning with "N_" are the bit position
  • In general, PCH registers are denoted by "_PCH_" in register names
  • Registers / bits that are different between PCH generations are denoted by "_PCH_[generation_name]_" in register/bit names.
  • Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names. Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names. e.g., "_PCH_H_", "_PCH_LP_" Registers / bits names without H or LP apply for both H and LP.
  • Registers / bits that are different between SKUs are denoted by "_[SKU_name]" at the end of the register/bit names
  • Registers / bits of new devices introduced in a PCH generation will be just named as "_PCH_" without [generation_name] inserted.
Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CnviRegs.h.

Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CnviRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
CnviRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for CNVi
3
4 Conventions:
5
6 - Prefixes:
7 Definitions beginning with "R_" are registers
8 Definitions beginning with "B_" are bits within registers
9 Definitions beginning with "V_" are meaningful values within the bits
10 Definitions beginning with "S_" are register sizes
11 Definitions beginning with "N_" are the bit position
12 - In general, PCH registers are denoted by "_PCH_" in register names
13 - Registers / bits that are different between PCH generations are denoted by
14 "_PCH_[generation_name]_" in register/bit names.
15 - Registers / bits that are specific to PCH-H denoted by "_H_" in register/bit names.
16 Registers / bits that are specific to PCH-LP denoted by "_LP_" in register/bit names.
17 e.g., "_PCH_H_", "_PCH_LP_"
18 Registers / bits names without _H_ or _LP_ apply for both H and LP.
19 - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
20 at the end of the register/bit names
21 - Registers / bits of new devices introduced in a PCH generation will be just named
22 as "_PCH_" without [generation_name] inserted.
23
24 @copyright
25 INTEL CONFIDENTIAL
26 Copyright 2017 - 2021 Intel Corporation.
27
28 The source code contained or described herein and all documents related to the
29 source code ("Material") are owned by Intel Corporation or its suppliers or
30 licensors. Title to the Material remains with Intel Corporation or its suppliers
31 and licensors. The Material may contain trade secrets and proprietary and
32 confidential information of Intel Corporation and its suppliers and licensors,
33 and is protected by worldwide copyright and trade secret laws and treaty
34 provisions. No part of the Material may be used, copied, reproduced, modified,
35 published, uploaded, posted, transmitted, distributed, or disclosed in any way
36 without Intel's prior express written permission.
37
38 No license under any patent, copyright, trade secret or other intellectual
39 property right is granted to or conferred upon you by disclosure or delivery
40 of the Materials, either expressly, by implication, inducement, estoppel or
41 otherwise. Any license under such intellectual property rights must be
42 express and approved by Intel in writing.
43
44 Unless otherwise agreed by Intel in writing, you may not remove or alter
45 this notice or any other notice embedded in Materials by Intel or
46 Intel's suppliers or licensors in any way.
47
48 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
49 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
50 the terms of your license agreement with Intel or your vendor. This file may
51 be modified by the user, subject to additional terms of the license agreement.
52
53 @par Specification Reference:
54 **/
55 #ifndef _CNVI_REGS_H_
56 #define _CNVI_REGS_H_
57
58 //
59 // CNVi WiFi Registers (D20:F3)
60 //
61 #define R_CNVI_CFG_WIFI_GIO_DEV_CAP 0x44 ///< Device Capabilities
62 #define R_CNVI_CFG_WIFI_GIO_DEV_CTRL 0x48 ///< Device Control
63 #define B_CNVI_CFG_WIFI_GIO_DEV_CTRL_FLR BIT15 ///< FLR
64 #define R_CNVI_CFG_WIFI_GIO_DEV_CAP_2 0x64 ///< Device Capabilities 2
65 #define B_CNVI_CFG_WIFI_GIO_DEV_CAP_2_LTR_MEC_SUP BIT11 ///< LTR Mechanism Supported
66 #define R_CNVI_CFG_WIFI_GIO_DEV_2 0x68 ///< Device Control 2
67 #define B_CNVI_CFG_WIFI_GIO_DEV_2_LTR_MEC_EN BIT10 ///< LTR Mechanism Enable
68 #define R_CNVI_CFG_WIFI_PMCSR 0xCC ///< Power Management Status and Control Register
69 #define B_CNVI_CFG_WIFI_PMCSR_PS (BIT0 | BIT1) ///< Power State
70 //
71 // Private registers description for CNVi WiFi
72 //
73 #define R_CNVI_VER2_PCR_CNVI_PLDR_ABORT 0x80
74 #define R_CNVI_VER4_PCR_CNVI_PLDR_ABORT 0x44
75 #define B_CNVI_PCR_CNVI_PLDR_ABORT_ENABLE BIT0
76 #define B_CNVI_PCR_CNVI_PLDR_ABORT_REQUEST BIT1
77 #define B_CNVI_PCR_SCU_CNVB_CNVI_READY BIT2
78 #define R_CNVI_PCR_STAT 0x8100
79 #define R_CNVI_PCR_WIFI_WIDGET_CONTROL 0x8114 ///< Widget Control
80 #define B_CNVI_PCR_WIFI_WIDGET_CONTROL_MEM_INT 0xFF ///< IRQ number
81 #endif // _CNVI_REGS_H_
Generated on Wed Jan 5 2022 01:23:59 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CommonMsr.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Register
Macros
CommonMsr.h File Reference

CommonMsr.h. More...

#include <Base.h>
Include dependency graph for CommonMsr.h:

Go to the source code of this file.

Macros

#define | MSR_POWERON 0x0000002A
MSR read by Sandra and HotCPU test. More...
#define | MSR_THREAD_SMI_ERR_INJ_CONTROL 0x0000002B
Enhanced MCA Thread error injection control.
#define | MSR_CORE_SMI_ERR_INJ_CONTROL 0x0000002C
Enhanced MCA Core error injection control.
#define | MSR_UNCORE_SMI_ERR_INJ_CONTROL 0x0000002D
Enhanced MCA Uncore error injection control.
#define | MSR_PIC_MSG_CONTROL 0x0000002E
MSR used to control APIC TPR Update messages from the processor's Local APIC.
#define | MSR_DCU_MODE_CONTROL 0x00000031
MSR used to select the mode for the Data Cache Unit (DCU). More...
#define | MSR_MEMORY_CONTROL 0x00000033
Register to disable split locks, which are locked instructions that split a cache line.
#define | MSR_SMI_COUNT 0x00000034
Keeps a running count of SMI events.
#define | MSR_CORE_THREAD_COUNT 0x00000035
This is a Read Only MSR that is shared in the processor package and used to determine the current count of enabled Cores and Threads.
#define | MSR_SOCKET_ID 0x00000039
The SOCKET_ID MSR is used to reassign the package-specific portions of the APIC ID. More...
#define | MSR_SMM_SAVE_CONTROL 0x0000003E
Contains bits that determine what additional state SMI/RSM must save and restore FSCP Crunch - 1:32.
#define | MSR_PPIN_CTL 0x0000004E
MSR for PPIN feature.
#define | MSR_PPIN 0x0000004F
PPIN value.
#define | MSR_QUIESCE_CTL1 0x00000050
MSR that is used to initiate quiesce and unquiesce of CSI links.
#define | MSR_QUIESCE_CTL2 0x00000051
MSR that is used for PSMI handshake before initiating a RAS quiesce.
#define | MSR_CLOAKING 0x00000052
Cloaking error Virtual MSR in core Creg PLA.
#define | MSR_THD_LOGICAL_ID 0x00000053
Spare Virtual MSRs in uncore Creg PLA.
#define | MSR_SMM_CLEAR_SMI 0x00000057
This MSR clars smi.
#define | MSR_SMM_CFG_OPTIONS 0x00000058
This MSR reads/writes bit 0 in smm_cfg_options fscp.
#define | MSR_THERM_EVENT_FFM 0x0000005E
This register provides support for the Firmware-First-Mode thermal interrup feature.
#define | MSR_SUPPRESS_SHUTDOWN 0x00000060
Shutdown supression feature.
#define | MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN 0x00000061
This MSR reads/writes CBO_CR_CBO_COH_CONFIG[0]. More...
#define | MSR_ACE_SPI_COMMAND 0x00000062
command reg in ACE IP
#define | MSR_ACE_SPI_DATA 0x00000063
command reg in ACE IP
#define | MSR_ACE_SPI_STATUS 0x00000064
status reg in ACE IP
#define | MSR_ACE_SPI_CONFIG 0x00000065
config reg in ACE IP
#define | MSR_PFR_EXIT 0x00000066
Used to exit out of PFR VCM. More...
#define | MSR_PFR_VCM_PROVISION 0x00000067
MSR to provision VCM key hash to CPU.
#define | MSR_PFR_VCM_PROVISION_STATUS 0x00000068
MSR to read PFR provision status.
#define | MSR_PROBE_TO_FROM_PDR 0x00000070
Not really a register. More...
#define | MSR_PROBE_GP_REG 0x00000071
Not really a register. More...
#define | MSR_PROBE_SEG_REG_1 0x00000072
Not really a register. More...
#define | MSR_PROBE_PL_REG 0x00000073
Not really a register. More...
#define | MSR_PROBE_MMX2_REG 0x00000074
Not really a register. More...
#define | MSR_PROBE_SEG_REG_3 0x00000075
Not really a register. More...
#define | MSR_PROBE_LT_SPC_CYC 0x00000076
Not really a register. More...
#define | MSR_PROBE_CHANGE_PG 0x00000077
Not really a register. More...
#define | MSR_SE_RDINFO_CMD 0x0000007D
Allows Probe Mode ITP software to access relevant information located in the SECS and EPCM that is not accessible using EDBGRD instruction.
#define | MSR_EINIT_FAIL_CTR 0x0000007E
TBD.
#define | MSR_NPK_STH_ACPIBAR_BASE 0x00000080
This register is used by BIOS to program Trace Hub (NPK) STH base address that will be used by AET messages.
#define | MSR_FME_ACTIVATE 0x00000081
Rd/Wr register to generate or restore Far Memory Keys.
#define | MSR_SGXLEPUBKEYHASH0 0x0000008C
Launch Enclave Provider signing key hash.
#define | MSR_SGXLEPUBKEYHASH1 0x0000008D
Launch Enclave Provider signing key hash.
#define | MSR_SGXLEPUBKEYHASH2 0x0000008E
Launch Enclave Provider signing key hash.
#define | MSR_SGXLEPUBKEYHASH3 0x0000008F
Launch Enclave Provider signing key hash.
#define | MSR_TIO_DEBUG_STATUS 0x00000090
emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support and in SNC HSD 1304428988 - HCTIO/SoftCE: uArch support for TIO_DEBUG_STATUS MSRs
#define | MSR_TIO_UNWRAP 0x00000091
emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support
#define | MSR_TIO_PRM_CLEANUP 0x00000092
emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support
#define | MSR_TIO_COPY_ENCRYPT 0x00000093
emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support
#define | MSR_ENABLE_DISABLE_CACHE_QOS 0x00000095
Used to enable or disable cache QoS.
#define | MSR_TIORR_PHYSBASE 0x00000096
Address Match Range Register - Physical Mask Control Register.
#define | MSR_TIORR_PHYSMASK 0x00000097
Address Match Range Register - Physical Mask Control Register.
#define | MSR_VMX_MSEG_BASE 0x0000009B
SMM Monitor Control MSR.
#define | MSR_SMM_PROT_MODE_BASE 0x0000009D
SMM Protected Mode Base MSR.
#define | MSR_SMBASE_ADDR 0x0000009E
This is a read only of SMM Base register.
#define | MSR_PRID_0_0 0x000000A1
SGX PRID values " seq has 2 instances in addresses range 0xA1 to 0xA2".
#define | MSR_PRID_1_1 0x000000A2
SGX PRID values " seq has 2 instances in addresses range 0xA1 to 0xA2".
#define | MSR_SGX_RAS 0x000000A3
MSR to opt in to SGX and opt out of advanceed RAS features.
#define | MSR_BIOS_PKG_CONFIG 0x000000A4
SGX QoS MSR.
#define | MSR_FIT_BIOS_ERROR 0x000000A5
FIT BIOS and ACM error type and code.
#define | MSR_MPX_FUSE_OVERRIDE 0x000000A6
Override MPX Fuse.
#define | MSR_BIOS_AVX_DIS 0x000000AF
Virtual MSR to disable AVX instructions from BIOS.
#define | MSR_VMSR_U2P_0_0 0x000000B0
vMSRs for power mgmt
#define | MSR_VMSR_U2P_1_1 0x000000B1
vMSRs for power mgmt
#define | MSR_VMSR_U2P_2_2 0x000000B2
vMSRs for power mgmt
#define | MSR_VMSR_U2P_3_3 0x000000B3
vMSRs for power mgmt
#define | MSR_SSKU_DATA 0x000000D0
SoftSKU data MSR.
#define | MSR_SSKU_CMD 0x000000D1
SoftSKU cmd MSR.
#define | MSR_SSKU_SMM_ADDR 0x000000D2
SoftSKU SMM access to LB regs.
#define | MSR_SSKU_SMM_DATA 0x000000D3
SoftSKU SMM access to LB regs.
#define | MSR_SSKU_ENFORCE 0x000000D4
SoftSKU enforcement MSR.
#define | MSR_CLOCK_CST_CONFIG_CONTROL 0x000000E2
C-State Configuration register.
#define | MSR_PMG_IO_CAPTURE_BASE 0x000000E4
Power Management I/O base address for I/O trapping to C-states.
#define | MSR_PROBE_CPL 0x00000101
Not really a register. More...
#define | MSR_PAIR_WEIGHT_OVERRIDE 0x00000102
Software PAIR weight override.
#define | MSR_PAIR_PKG_THREAD_PARTICIPATION 0x00000103
Pair package level thread participation.
#define | MSR_PAIR_THREAD_PARTICIPATION 0x00000104
Register to specify a thread's inclusion or exclusion in Power Aware Interrupt Routing.
#define | MSR_PLAT_FRMW_PROT_CTRL 0x00000110
Platform Firmware Control MSR.
#define | MSR_PLAT_FRMW_PROT_HASH_0 0x00000111
Platform Firmware Hash Value 063:000.
#define | MSR_PLAT_FRMW_PROT_HASH_1 0x00000112
Platform Firmware Hash Value 127:064.
#define | MSR_PLAT_FRMW_PROT_HASH_2 0x00000113
Platform Firmware Hash Value 191:128.
#define | MSR_PLAT_FRMW_PROT_HASH_3 0x00000114
Platform Firmware Hash Value 255:192.
#define | MSR_PLAT_FRMW_PROT_TRIG_PARAM 0x00000115
This registers contains the 64-bit physical address of the start of the PFAT DIRECTORY.
#define | MSR_PLAT_FRMW_PROT_TRIGGER 0x00000116
This is a Write-Only command MSR. More...
#define | MSR_PFAT_EC_PASSWORD 0x00000117
MSR to enable PFAT support on embedded controller discrete flash.
#define | MSR_PFAT_GT_SLEEP_CMDSTS 0x00000118
send to Sleep MSR
#define | MSR_BIOS_INFO_FLAGS 0x0000011F
Read bits 23:16 of uncore SCP (storage for this 8b MSR)
#define | MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG 0x00000121
This is a read/write MSR that will control the ucode emulation of the PM_TMR. More...
#define | MSR_CPU_BUSNUMBER 0x00000128
This RO MSR will be used to read the Ubox CPUBUSNO/CPUBUSNO1/CPUBUSNO_VALID CSRs.
#define | MSR_MMCFG_RULE_CFG 0x00000129
This RO MSR will be used to read the Ubox MMCFG_RULE_CFG list.
#define | MSR_MMCFG_RULE_TARGET_LIST 0x0000012A
This RO MSR will be used to read the Ubox MMCFG_RULE_TARGET_LIST.
#define | MSR_ANC_BOOT_POLICY_0_0 0x00000130
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_1_1 0x00000131
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_2_2 0x00000132
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_3_3 0x00000133
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_4_4 0x00000134
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_5_5 0x00000135
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_6_6 0x00000136
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_BOOT_POLICY_7_7 0x00000137
Anchor Cove MSR for reading boot policy information from the PCH. More...
#define | MSR_ANC_FORCE_BOOT_POLICY_ENFORCED 0x00000138
Anchor Cove MSR to indicate that the initial boot block is complete, and to re-enable events. More...
#define | MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE 0x00000139
Anchor Cove MSR to tell PCH that the ACM has successfully launched and to stop the deadman timer countdown. More...
#define | MSR_ANC_SACM_INFO 0x0000013A
An MSR for communicating basic policy information from the Anchor Cove ACM to early BIOS. More...
#define | MSR_FEATURE_CONFIG 0x0000013C
AES Feature configuration. More...
#define | MSR_CORE_SPECIFIC_SPARE_0_0 0x0000013D
Spare core MSRs supported by the cregpla. More...
#define | MSR_CORE_SPECIFIC_SPARE_1_1 0x0000013E
Spare core MSRs supported by the cregpla. More...
#define | MSR_CORE_SPECIFIC_SPARE_2_2 0x0000013F
Spare core MSRs supported by the cregpla. More...
#define | MSR_MISC_THD_FEATURE_ENABLES 0x00000140
Miscellaneous enables for thread specific features. More...
#define | MSR_SMM_SUPOVR_STATE_LOCK 0x00000141
SMM-only MSR which allows locking of various states while in SMM mode.
#define | MSR_THREAD_SPECIFIC_SPARE_0_0 0x00000142
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_1_1 0x00000143
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_2_2 0x00000144
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_3_3 0x00000145
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_4_4 0x00000146
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_5_5 0x00000147
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_6_6 0x00000148
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_7_7 0x00000149
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_8_8 0x0000014A
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_9_9 0x0000014B
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_10_10 0x0000014C
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_11_11 0x0000014D
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_12_12 0x0000014E
Spare thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_SPARE_13_13 0x0000014F
Spare thread MSRs supported by the cregpla. More...
#define | MSR_OVERCLOCKING_MAILBOX 0x00000150
An Interface to perform various overclocking oriented commands.
#define | MSR_BIOS_DONE 0x00000151
BIOS Done register for CNL issue 1351547. More...
#define | MSR_SNC_CONFIG 0x00000152
SNC_CONFIG_BASE register decription.
#define | MSR_SNC_RANGE0_BASE 0x00000153
SNC_RANGE1_BASE register decription.
#define | MSR_SNC_RANGE1_BASE 0x00000154
SNC_RANGE2_BASE register decription.
#define | MSR_SNC_RANGE2_BASE 0x00000155
SNC_RANGE3_BASE register decription.
#define | MSR_SNC_RANGE3_BASE 0x00000156
SNC_RANGE4_BASE register decription.
#define | MSR_SNC_RANGE4_BASE 0x00000157
SNC_RANGE5_BASE register decription.
#define | MSR_THREAD_SMI_ERR_SRC 0x00000158
Core SMI Error Source.
#define | MSR_SNC_UPPER_BASE 0x00000159
SNC range upper 6 bits per range register.
#define | MSR_SPCL_UNCORE_USAGE 0x0000015B
Special uncore usage msr, work in PFAT or in SMM BIOS flash.
#define | MSR_PERMEM_CONFIG_INFO 0x0000015C
Read-only MSR that specifies the maximum number of memory controllers on the platform capable of supporting memory persistence.
#define | MSR_PERMEM_CTRLR_INDEX 0x0000015D
Index into the list of persistent memory addresses which is accessed when the PERMEM_CTRLR_ID MSR is read/written.
#define | MSR_PERMEM_CTRLR_ID 0x0000015E
Read-only MSR that specifies the maximum number of memory controllers on the platform capable of supporting memory persistence.
#define | MSR_REGISTER_0 0x00000160
Probe mode MSR, used also in cache flush and segmentation C6NoSave Candidate.
#define | MSR_REGISTER_1 0x00000161
Probe mode MSR, used also in PDM flows C6NoSave Candidate.
#define | MSR_REGISTER_2 0x00000162
Probe mode MSR, used also in PDM flows C6NoSave Candidate.
#define | MSR_REGISTER_3 0x00000163
Probe mode MSR, used also in page a/d assist and vmx flows C6NoSave Candidate: actually, we'll leave this in the C6 save loop because it's also an MSR.
#define | MSR_REGISTER_4 0x00000164
Probe mode MSR, used also in PDM and paging flows C6NoSave Candidate.
#define | MSR_REGISTER_5 0x00000165
Probe mode MSR, used also in PDM and paging flows C6NoSave Candidate.
#define | MSR_REGISTER_6 0x00000166
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_7 0x00000167
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_8 0x00000168
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_9 0x00000169
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_10 0x0000016A
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_11 0x0000016B
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_12 0x0000016C
Probe mode MSR C6NoSave Candidate.
#define | MSR_REGISTER_13 0x0000016D
Probe mode MSR C6NoSave Candidate.
#define | MSR_TASK_SWITCH_OR_SMI_RIP 0x0000016E
SCP used by Task Switch and SMI code to save RIP Probe mode MSR, used also in PDM flows.
#define | MSR_TASK_SWITCH_OR_PROBE_MODE_MISC 0x0000016F
Probe mode MSR, used also in task switch C6NoSave Candidate.
#define | MSR_P6_CR_SMREVID 0x00000170
SMM revision identifier. More...
#define | MSR_P6_CR_SMBASE 0x00000171
SMM Base register.
#define | MSR_PROBE_MODE_PPPE_REDIRECTION 0x00000172
Used to save PPPE exit reason for probe mode redirection C6NoSave Candidate.
#define | MSR_PROBE_MODE_DR 0x00000173
Probe mode data register result.
#define | MSR_MCG_CONTAIN 0x00000178
Register that contains the poison and viral bit valid / invalid state.
#define | MSR_CORE_SMI_ERR_SRC 0x0000017C
Core SMI Error Source.
#define | MSR_SMM_MCA_CAP 0x0000017D
Enhanced MCA Capabilities register.
#define | MSR_UNCORE_SMI_ERR_SRC 0x0000017E
Uncore SMI Error Source.
#define | MSR_ERROR_CONTROL 0x0000017F
[p]A non-architectural, package-scoped MSR intended for use by BIOS. More...
#define | MSR_FLEX_RATIO 0x00000194
This 'flexible boot' register is written by BIOS in order to modify the maximum non-turbo ratio on the next reset.
#define | MSR_MSR_THERM2_CTL 0x0000019D
Deprecated. More...
#define | MSR_PACKAGE_THERM_MARGIN 0x000001A1
Temperature margin in PECI temperature counts from the thermal profile specification. More...
#define | MSR_TEMPERATURE_TARGET 0x000001A2
Legacy register holding temperature related constants for Platform use.
#define | MSR_MISC_FEATURE_CONTROL 0x000001A4
Miscellaneous Feature Control Register.
#define | MSR_THREAD_SW_DEFEATURE 0x000001A8
MSR for thread specific defeature.
#define | MSR_MISC_PWR_MGMT 0x000001AA
Miscellaneous Power Management control; Various model specific features enumeration.
#define | MSR_TURBO_RATIO_LIMIT_CORES 0x000001AE
This register defines the active core ranges for each frequency point NUMCORE[0:7] must be populated in ascending order. More...
#define | MSR_HW_GET_LP_PM_META_DATA 0x000001C2
Current Logical Processor PM Meta Data and CTC data.
#define | MSR_HW_SET_LP_PM_META_DATA 0x000001C3
Deliver the LP PM Meta Data into the H/W.
#define | MSR_DEBUG_RESOURCE_STATUS 0x000001C6
This MSR return the status of debug resources (Used to be in MISC_ENABLES MSR).
#define | MSR_LBR_SELECT 0x000001C8
NHM creg to filter LBR writes.
#define | MSR_LBR_TOS 0x000001C9
LBR creg that holds the TOS value.
#define | MSR_LAST_BRANCH_INFO 0x000001DA
LAST_BRANCH LBR MSR that holds non-IP information.
#define | MSR_LAST_BRANCH_FROM_IP 0x000001DB
Top of LBR Stack.
#define | MSR_LAST_BRANCH_TO_IP 0x000001DC
Top of LBR Stack.
#define | MSR_LAST_INT_FROM_IP 0x000001DD
Last Exeception Record.
#define | MSR_LAST_INT_TO_IP 0x000001DE
Last Exeception Record.
#define | MSR_ICECTLPMR 0x000001DF
Probe mode control and status register. More...
#define | MSR_LAST_INT_INFO 0x000001E0
LER MSR that holds non-IP information.
#define | MSR_CPU_TYPE 0x000001E1
This RO MSR will be used to report the fuse_cpu_type bits from PCU Package Config CSR.
#define | MSR_CUSTOMER_SPECIFIC_FEATURE_ENABLE 0x000001E2
Register used to enable customer specific features.
#define | MSR_DEBUG_ERR_INJ_CTL 0x000001E3
This MSR holds the capability of error spoofing. More...
#define | MSR_DEBUG_ERR_INJ_CTL2 0x000001E4
This MSR will be used to trigger MCA(bit0)/CMCI(bit1)
#define | MSR_ULI_VECTOR_INFO 0x000001E5
User-level Interrupts Vector.
#define | MSR_ULI_TARGET_RIP 0x000001E7
User-level Interrupts Target RIP.
#define | MSR_VLW_CAPABILITY 0x000001F0
VLW capability MSR that reports information about the VLW messages that are supported.
#define | MSR_CRASHLOG_CONTROL 0x000001F1
Virtual MSR to will write data to an Crash Log configuration CR address is taken from CORE_CRASHLOG_CONTROL writing and reading CDDIS - CrashLog_Disable.
#define | MSR_SMRR_BASE 0x000001F2
SMM Range Register - Physical Base Control Register.
#define | MSR_SMRR_MASK 0x000001F3
SMM Range Register Base - Physical Mask Control Register.
#define | MSR_PRMRR_MASK 0x000001F5
Processor Reserved Memory Range Register - Physical Mask Control Register.
#define | MSR_SMRR2_BASE 0x000001F6
SMM Range Register #2 - Physical Base Control Register.
#define | MSR_SMRR2_MASK 0x000001F7
SMM Range Register Base #2 - Physical Mask Control Register.
#define | MSR_PRMRR_VALID_CONFIG 0x000001FB
Valid PRMRR configurations.
#define | MSR_POWER_CTL 0x000001FC
Power Control Register.
#define | MSR_SPCL_CHIPSET_USAGE 0x000001FE
Special Chipset Usage MSR.
#define | MSR_ICECTLPMR_2 0x0000025B
Scratch Pad register P6_CR_ICECTLPMR_2 Bit descriptions are derived from review of Merom ucode - May be incomplete (RajeshP)
#define | MSR_MCI_CTL2 0x00000298
This register is used for generating corrected error interrupts. More...
#define | MSR_PRMRR_BASE_0 0x000002A0
Processor Reserved Memory Range Register - Physical Base Control Register.
#define | MSR_PRMRR_BASE_1_1 0x000002A1
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_2_2 0x000002A2
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_3_3 0x000002A3
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_4_4 0x000002A4
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_5_5 0x000002A5
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_6_6 0x000002A6
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_PRMRR_BASE_7_7 0x000002A7
Processor Reserved Memory Range Register - Physical Base Control Register " seq has 7 instances in addresses range 0x2A1 to 0x2A7".
#define | MSR_NEM 0x000002E0
No-Evict Mode MSR.
#define | MSR_LT_UNLOCK_MEMORY 0x000002E6
Used by Intel TXT enabled BIOS to unlock memory after checking that the TPM is valid.
#define | MSR_EDRAM_ACM 0x000002E8
ACM Only MSR for EDRAM management.
#define | MSR_SE_EPOCH_0 0x00000300
External 128-bit entropy for SGX keys derivation.
#define | MSR_SE_EPOCH_1 0x00000301
External 128-bit entropy for SGX keys derivation.
#define | MSR_BIOS_SE_SVN 0x00000302
MSR to read and update SGX SVN by BIOS.
#define | MSR_MCHECK_BOOT_SCENARIO 0x00000304
BOOT MSR for communicating boot protocol to MCHECK uses NcuScratchpad26.
#define | MSR_COMPOUND_CTR_CTRL 0x00000306
IVB i1026245 - PerfMon Compound Counter enhancement.
#define | MSR_COMPOUND_PERF_CTR 0x00000307
IVB i1026245 - PerfMon Compound Counter enhancement.
#define | MSR_ROP_DETECT_CTRL 0x00000350
The BM_DETECT_CTRL is used to enable Branck Monitoring detection (BM), enable PMI exceptions on BM detect, set BM window size, determine counting method for BM window, and determine if trip is due to all counting conditions being met.
#define | MSR_ROP_DETECT_STATUS 0x00000351
Branch Monitoring detect status - threshold tripped, which counter tripped, and tripping count.
#define | MSR_ROP_DETECT_CAPABILITIES 0x00000352
Branch Monitoring Detect Capabilities.
#define | MSR_ROP_COUNTER_CONFIG_0 0x00000354
Counter_0: Counter enables, events selection, counter trip threshold.
#define | MSR_ROP_COUNTER_CONFIG_1 0x00000355
Counter_1: Counter enables, events selection, counter trip threshold.
#define | MSR_ROP_EVENT_FILTER0 0x00000360
Branch Monitoring event filter 0.
#define | MSR_ROP_EVENT_FILTER0_DATA 0x00000361
ROP event filter 0 Data.
#define | MSR_EMON_PERF_RES_PROGRAMMED 0x00000392
This MSR displays the programming status of all the PerfMon counters. More...
#define | MSR_PERFCTR0 0x000003B8
IDP 1 PMON Counter 1 data register The Fix counter is counting UCLK cycles. More...
#define | MSR_PERFCTR1 0x000003B9
IDP 1 PMON Counter 2 data register The Fix counter is counting UCLK cycles. More...
#define | MSR_PEBS_LD_LAT_THRESHOLD 0x000003F6
Threshold value for the load latency.
#define | MSR_PEBS_FRONTEND 0x000003F7
Precise Performance Monitoring (PPMON) Event Control. More...
#define | MSR_PC3_RCNTR 0x000003F8
Time spent in the Package C-State. More...
#define | MSR_PC6_RCNTR 0x000003F9
Time spent in the Package C-State. More...
#define | MSR_PC7_RCNTR 0x000003FA
Time spent in the Package C-State. More...
#define | MSR_CC3_RCNTR 0x000003FC
Time spent in the Core C-State. More...
#define | MSR_CORE_C6_RESIDENCY_COUNTER 0x000003FD
Time spent in the Core C-State. More...
#define | MSR_CC7_RCNTR 0x000003FE
Time spent in the Core C-State. More...
#define | MSR_IMC0_MC_CTL 0x00000464
The MCiCTL MSR controls the signalling of machine check exceptions generated by the bank.
#define | MSR_IMC0_MC_STATUS 0x00000465
The MCiSTATUS MSR contains information related to a machine check error if its VAL (valid) flag is set.
#define | MSR_IMC1_MC9_ADDR 0x0000046A
The MCiADDR MSR contains the address of the code or data memory location that produced the machine check error if the ADDRV flag in the MCiSTATUS register is set.
#define | MSR_IMC2_MCA_ADDR 0x0000046E
The MCiADDR MSR contains the address of the code or data memory location that produced the machine check error if the ADDRV flag in the MCiSTATUS register is set.
#define | MSR_MCG_EXE_CTL 0x000004D0
SW opt-in for none-broadcast behavior.
#define | MSR_SMM_FEATURE_CONTROL 0x000004E0
This CSR holds enable bits for on-chip storage of SMM and Code Access Check Violation features.
#define | MSR_SMM_ENABLE_MATCH 0x000004E8
Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's) that should be servicing a Targeted SMI. More...
#define | MSR_SMM_ENABLE_MASK 0x000004EA
Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's) that should be servicing a Targeted SMI. More...
#define | MSR_IA32_SE_SVN 0x00000500
SGX SVN Status MSR.
#define | MSR_SGX_DEBUG_MODE 0x00000503
SGX_DEBUG_MODE MSR to allow non-Intel debugger to enter debug mode equal to DEBUG_UNLOCK_MODE functionality.
#define | MSR_PROBE_MODE_VMEXIT_REDIRECTION_REASON 0x00000504
Scratch Pad register PROBE_MODE_4 C6NoSave Candidate.
#define | MSR_PROBE_MODE_VMX_REDIRECTION_INFO 0x00000505
VMX Redirection info used for Probe Mode.
#define | MSR_PROBE_TLB_FLUSH 0x00000508
Not really a register. More...
#define | MSR_PROBE_VMX_POINTER 0x00000509
Not really a register. More...
#define | MSR_TIO_PM_DEBUG_STATUS 0x0000050A
emulated by xucode --> cause pppe exit, described in SNC HSD 1304428988 - HCTIO/SoftCE: uArch support for TIO_DEBUG_STATUS MSRs
#define | MSR_AET_MISC_ENABLE 0x00000511
Programmed in Probe mode, used in PDM. More...
#define | MSR_AET_EVENT_CTRL 0x00000512
AET (PDM) Event Control Register.
#define | MSR_PROBE_MODE_PPPE_REDIRECTION_INFO 0x00000513
PPPE Redirection info used for Probe Mode.
#define | MSR_PROBE_MODE_RESERVED_1_1 0x00000514
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_2_2 0x00000515
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_3_3 0x00000516
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_4_4 0x00000517
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_5_5 0x00000518
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_6_6 0x00000519
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_7_7 0x0000051A
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_8_8 0x0000051B
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_9_9 0x0000051C
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_10_10 0x0000051D
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_11_11 0x0000051E
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_PROBE_MODE_RESERVED_12_12 0x0000051F
This define is used to reserve some MSR addresses for probe mode. More...
#define | MSR_ICECTLPMR_PRIOR_STATE 0x00000520
Scratch Pad register ICECTLPMR_PRIOR_STATE Used only by probe mode. More...
#define | MSR_AET_BASE_ADDRESS 0x00000521
AET base address. More...
#define | MSR_CORE_UARCH_CTL 0x00000541
Core UARCH_CTL msr.
#define | MSR_VR_CURRENT_CONFIG 0x00000601
PL4 limit. More...
#define | MSR_PACKAGE_POWER_SKU_UNIT 0x00000606
Defines units for calculating SKU power and timing parameters.
#define | MSR_BIOS_MAILBOX_INTERFACE 0x00000607
Control and Status register for the BIOS-to-PCODE mailbox. More...
#define | MSR_BIOS_MAILBOX_DATA 0x00000608
Data register for the BIOS-to-PCODE mailbox. More...
#define | MSR_PST_CONFIG_CONTROL 0x00000609
This MSR reads/writes THREAD_P_REQ[P_STATE_OFFSET]. More...
#define | MSR_C_STATE_LATENCY_CONTROL_0 0x0000060A
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_C_STATE_LATENCY_CONTROL_1 0x0000060B
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_C_STATE_LATENCY_CONTROL_2 0x0000060C
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_PC2_RCNTR 0x0000060D
Time spent in the Package C-State. More...
#define | MSR_PACKAGE_RAPL_LIMIT 0x00000610
This register allows platform BIOS to limit the power consumption of the processor to the specified values.
#define | MSR_PACKAGE_ENERGY_STATUS 0x00000611
Package energy consumed by the entire CPU (including IA, GT and uncore). More...
#define | MSR_PACKAGE_RAPL_PERF_STATUS 0x00000613
Package RAPL Performance Status Register. More...
#define | MSR_PACKAGE_POWER_SKU 0x00000614
Defines allowed SKU power and timing parameters. More...
#define | MSR_PL3_CONTROL 0x00000615
Read/write data from/to pcode through internal mailbox.
#define | MSR_DDR_RAPL_LIMIT 0x00000618
Allows software to set power limits for the DRAM domain and measurement attributes associated with each limit.
#define | MSR_DDR_ENERGY_STATUS 0x00000619
Accumulates the energy consumed by the DIMMs (summed across all channels).
#define | MSR_DDR_RAPL_PERF_STATUS 0x0000061B
Memory RAPL performance excursion counter. More...
#define | MSR_LLC_FLUSHED_RCNTR 0x0000061D
Time spent with LLC flushed. More...
#define | MSR_LCLK_PLL_RATIO 0x0000061E
This register provides additional support for BCLK overclocking.
#define | MSR_UNCORE_RATIO_LIMIT 0x00000620
Min/Max Ratio Limits for Uncore.
#define | MSR_UNCORE_PERF_STATUS 0x00000621
Ring and Last Level Cache Performance Status.
#define | MSR_PCH_EA_CONTROL 0x00000622
Gives SW ability to trigger a PMReq through Pcode to put the chipset and other devices off of the chipset into a low power state.
#define | MSR_PCH_EA_STATUS 0x00000623
Reflect the value of control when PCH has responded to request from PCH_EA_CONTROL.
#define | MSR_PC8_RCNTR 0x00000630
Time spent in the Package C-State. More...
#define | MSR_PC9_RCNTR 0x00000631
Time spent in the Package C-State. More...
#define | MSR_PC10_RCNTR 0x00000632
Time spent in the Package C-State. More...
#define | MSR_C_STATE_LATENCY_CONTROL_3 0x00000633
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_C_STATE_LATENCY_CONTROL_4 0x00000634
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_C_STATE_LATENCY_CONTROL_5 0x00000635
The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. More...
#define | MSR_VR_MISC_CONFIG2 0x00000636
Input voltage regulator configuration parameters.
#define | MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT 0x00000638
This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Primary Power Plane. More...
#define | MSR_PRIMARY_PLANE_ENERGY_STATUS 0x00000639
Reports total energy consumed. More...
#define | MSR_PRIMARY_PLANE_TURBO_POWER_POLICY 0x0000063A
The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes. More...
#define | MSR_PRIMARY_PLANE_OVERFLOW_STATUS 0x0000063B
Memory RAPL performance excursion counter. More...
#define | MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT 0x00000640
This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Secondary Power Plane. More...
#define | MSR_SECONDARY_PLANE_ENERGY_STATUS 0x00000641
Reports total energy consumed. More...
#define | MSR_SECONDARY_PLANE_TURBO_POWER_POLICY 0x00000642
The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes. More...
#define | MSR_CONFIG_TDP_NOMINAL 0x00000648
This register is used to indicate the Nominal Configurable TDP ratio available for this specific sku. More...
#define | MSR_CONFIG_TDP_LEVEL1 0x00000649
Level 1 configurable TDP settings.
#define | MSR_CONFIG_TDP_LEVEL2 0x0000064A
Level 2 configurable TDP settings.
#define | MSR_CONFIG_TDP_CONTROL 0x0000064B
Rd/Wr register to allow platform SW to select TDP point and set lock.
#define | MSR_TURBO_ACTIVATION_RATIO 0x0000064C
indicate the new maximum non-turbo ratio to be used by the processor. More...
#define | MSR_PLATFORM_ENERGY_STATUS 0x0000064D
Reports the actual energy used by the platform.
#define | MSR_IA_PERF_LIMIT_REASONS 0x0000064F
Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency. More...
#define | MSR_PKG_SDC_CONFIG_CONTROL 0x00000652
MSR Name: PKG_HDC_CONFIG_CONTROL, Enables tune options for the HDC operation.
#define | MSR_CORE_SDC_RESIDENCY 0x00000653
Core SDC Residency counter.
#define | MSR_THREAD_INFO 0x00000654
Contains software threads information for the current ia_thread.
#define | MSR_PKG_SDC_SHALLOW_RESIDENCY 0x00000655
MSR Name: PKG_HDC_SHALLOW_RESIDENCY, PKG shallow CX cycles Residency Counter.
#define | MSR_PKG_SDC_DEEP_RESIDENCY 0x00000656
MSR Name: PKG_HDC_DEEP_RESIDENCY PKG Deep CX duty cycles Residency Counter.
#define | MSR_PKG_IA_C0_ANY_SUM 0x00000658
Sum the cycles per number of active cores.
#define | MSR_PKG_IA_C0_ANY 0x00000659
C0.Any - Sum the cycles of any active cores.
#define | MSR_PKG_GT_C0_ANY 0x0000065A
Sum the cycles of active GT.
#define | MSR_PKG_GT_AND_IA_OVERLAP 0x0000065B
Sum the cycles of overlap time between any IA cores and GT.
#define | MSR_PLATFORM_POWER_LIMIT 0x0000065C
Platform power limit.
#define | MSR_DISTRIBUTED_STATUS 0x0000065E
FAST_UNCORE_MSRS _STATUS, Eanble coplition deliver status report.
#define | MSR_FAST_UNCORE_MSRS_CAPABILITY 0x0000065F
Fast wrmsr/rdmsr enumeration MSR. More...
#define | MSR_CORE_C1_RESIDENCY 0x00000660
Core C1 Residency counter.
#define | MSR_LBR_FROM_IP_0_0 0x00000680
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_1_1 0x00000681
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_2_2 0x00000682
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_3_3 0x00000683
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_4_4 0x00000684
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_5_5 0x00000685
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_6_6 0x00000686
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_7_7 0x00000687
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_8_8 0x00000688
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_9_9 0x00000689
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_10_10 0x0000068A
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_11_11 0x0000068B
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_18_18 0x00000692
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_19_19 0x00000693
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_20_20 0x00000694
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_21_21 0x00000695
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_22_22 0x00000696
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_23_23 0x00000697
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_24_24 0x00000698
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_25_25 0x00000699
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_26_26 0x0000069A
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_27_27 0x0000069B
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_28_28 0x0000069C
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_29_29 0x0000069D
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_30_30 0x0000069E
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_FROM_IP_31_31 0x0000069F
LBR MSR that holds the from IP, canonical check for write, see Vol 3A.
#define | MSR_LBR_TO_IP_0_0 0x000006C0
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_1_1 0x000006C1
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_2_2 0x000006C2
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_3_3 0x000006C3
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_4_4 0x000006C4
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_5_5 0x000006C5
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_6_6 0x000006C6
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_7_7 0x000006C7
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_8_8 0x000006C8
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_9_9 0x000006C9
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_10_10 0x000006CA
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_11_11 0x000006CB
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_12_12 0x000006CC
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_13_13 0x000006CD
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_14_14 0x000006CE
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_15_15 0x000006CF
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_16_16 0x000006D0
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_17_17 0x000006D1
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_18_18 0x000006D2
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_19_19 0x000006D3
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_20_20 0x000006D4
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_21_21 0x000006D5
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_22_22 0x000006D6
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_23_23 0x000006D7
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_24_24 0x000006D8
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_25_25 0x000006D9
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_26_26 0x000006DA
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_27_27 0x000006DB
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_28_28 0x000006DC
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_29_29 0x000006DD
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_30_30 0x000006DE
LBR MSR that holds the from IP.
#define | MSR_LBR_TO_IP_31_31 0x000006DF
LBR MSR that holds the from IP.
#define | MSR_NCUPMONCTRLGLCTR 0x00000707
Holds global control fields for the NCU PMON counters. More...
#define | MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL0 0x0000070B
Ubox local PMON mask for NCDEC events.
#define | MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL1 0x0000070C
Ubox local PMON mask for NCDEC events for subunit target.
#define | MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR 0x0000070D
Address offset match value for Ubox match/mask. More...
#define | MSR_NCUPMONGLSTS1 0x0000070F
PMON Global Status register. More...
#define | MSR_PCUPMONCNTRCFG_0 0x00000711
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTRCFG_1 0x00000712
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTRCFG_2 0x00000713
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTRCFG_3 0x00000714
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTR_0 0x00000717
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTR_1 0x00000718
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTR_2 0x00000719
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_PCUPMONCNTR_3 0x0000071A
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_RESIDENCY_CTR_SELECT 0x0000071B
Spare Virtual MSRs in uncore Creg PLA.
#define | MSR_RESIDENCY_CTR_CONFIG 0x0000071C
Spare Virtual MSRs in uncore Creg PLA.
#define | MSR_RESIDENCY_CTR 0x0000071D
Spare Virtual MSRs in uncore Creg PLA.
#define | MSR_ERR_INJ_LCK_UNLOCK_CTL 0x00000790
This MSR will write the ERRINJLCK bit of IIO, QPI, CBO, MC.
#define | MSR_UNCORE_SPARE_0_0 0x00000791
Spare Virtual MSRs in uncore Creg PLA " seq has 2 instances in addresses range 0x791 to 0x792".
#define | MSR_UNCORE_SPARE_1_1 0x00000792
Spare Virtual MSRs in uncore Creg PLA " seq has 2 instances in addresses range 0x791 to 0x792".
#define | MSR_EXTENDED_MCG_PTR 0x00000793
Extended MCi Status Pointer.
#define | MSR_UNCORE_SPARE_2_2 0x00000794
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_3_3 0x00000795
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_4_4 0x00000796
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_5_5 0x00000797
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_6_6 0x00000798
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_7_7 0x00000799
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_8_8 0x0000079A
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_9_9 0x0000079B
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_10_10 0x0000079C
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_11_11 0x0000079D
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_12_12 0x0000079E
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_UNCORE_SPARE_13_13 0x0000079F
Spare Virtual MSRs in uncore Creg PLA " seq has 12 instances in addresses range 0x794 to 0x79F".
#define | MSR_VIRTUAL_APIC_0_0 0x00000800
Virtual APIC MSRs that are modeled by ucode " seq has 2 instances in addresses range 0x800 to 0x801".
#define | MSR_VIRTUAL_APIC_1_1 0x00000801
Virtual APIC MSRs that are modeled by ucode " seq has 2 instances in addresses range 0x800 to 0x801".
#define | MSR_PIC_EXTENDED_LOCAL_APIC_ID 0x00000802
X2APIC Local APIC ID register.
#define | MSR_PIC_LOCAL_UNIT_VERSION 0x00000803
Local APIC Version register.
#define | MSR_VIRTUAL_APIC_2_2 0x00000804
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x804 to 0x807".
#define | MSR_VIRTUAL_APIC_3_3 0x00000805
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x804 to 0x807".
#define | MSR_VIRTUAL_APIC_4_4 0x00000806
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x804 to 0x807".
#define | MSR_VIRTUAL_APIC_5_5 0x00000807
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x804 to 0x807".
#define | MSR_PIC_TASK_PRIORITY 0x00000808
APIC Task Priority Register.
#define | MSR_VIRTUAL_APIC_6_6 0x00000809
Virtual APIC MSRs that are modeled by ucode " seq has 1 instances in addresses range 0x809 to 0x809".
#define | MSR_PIC_PROCESSOR_PRIORITY 0x0000080A
APIC Processor Priority Register.
#define | MSR_PIC_EOI 0x0000080B
APIC EOI Register.
#define | MSR_VIRTUAL_APIC_7_7 0x0000080C
Virtual APIC MSRs that are modeled by ucode " seq has 1 instances in addresses range 0x80C to 0x80C".
#define | MSR_PIC_EXTENDED_LOGICAL_DESTINATION 0x0000080D
X2APIC Logical Destination register.
#define | MSR_VIRTUAL_APIC_8_8 0x0000080E
Virtual APIC MSRs that are modeled by ucode " seq has 1 instances in addresses range 0x80E to 0x80E".
#define | MSR_PIC_SPURIOUS_INTERRUPT 0x0000080F
Spurious Interrupt Vector register.
#define | MSR_PIC_ISR_DWORD_0_0 0x00000810
APIC In-Service register bits " seq has 1 instances in addresses range 0x810 to 0x810".
#define | MSR_PIC_ISR_DWORD_1_1 0x00000811
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_2_2 0x00000812
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_3_3 0x00000813
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_4_4 0x00000814
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_5_5 0x00000815
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_6_6 0x00000816
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_ISR_DWORD_7_7 0x00000817
APIC In-Service register bits " seq has 7 instances in addresses range 0x811 to 0x817".
#define | MSR_PIC_TMR_DWORD_0_0 0x00000818
APIC Trigger Mode register bits " seq has 1 instances in addresses range 0x818 to 0x818".
#define | MSR_PIC_TMR_DWORD_1_1 0x00000819
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_2_2 0x0000081A
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_3_3 0x0000081B
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_4_4 0x0000081C
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_5_5 0x0000081D
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_6_6 0x0000081E
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_TMR_DWORD_7_7 0x0000081F
APIC Trigger Mode register bits " seq has 7 instances in addresses range 0x819 to 0x81F".
#define | MSR_PIC_IRR_DWORD_0_0 0x00000820
APIC Interrupt Request register bits " seq has 1 instances in addresses range 0x820 to 0x820".
#define | MSR_PIC_IRR_DWORD_1_1 0x00000821
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_2_2 0x00000822
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_3_3 0x00000823
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_4_4 0x00000824
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_5_5 0x00000825
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_6_6 0x00000826
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_IRR_DWORD_7_7 0x00000827
APIC Interrupt Request register bits " seq has 7 instances in addresses range 0x821 to 0x827".
#define | MSR_PIC_ERROR_STATUS 0x00000828
APIC Error Status register.
#define | MSR_VIRTUAL_APIC_9_9 0x00000829
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_VIRTUAL_APIC_10_10 0x0000082A
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_VIRTUAL_APIC_11_11 0x0000082B
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_VIRTUAL_APIC_12_12 0x0000082C
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_VIRTUAL_APIC_13_13 0x0000082D
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_VIRTUAL_APIC_14_14 0x0000082E
Virtual APIC MSRs that are modeled by ucode " seq has 6 instances in addresses range 0x829 to 0x82E".
#define | MSR_PIC_LVT_CMCI 0x0000082F
LVT Entry for Correctable MCA Interrupt.
#define | MSR_PIC_INTERRUPT_COMMAND 0x00000830
APIC Interrupt Command register.
#define | MSR_VIRTUAL_APIC_15_15 0x00000831
Virtual APIC MSRs that are modeled by ucode " seq has 1 instances in addresses range 0x831 to 0x831".
#define | MSR_PIC_LVT_TIMER 0x00000832
LVT Entry for the PIC Timer.
#define | MSR_PIC_LVT_THERM 0x00000833
LVT Entry for the Thermal Interrupt.
#define | MSR_PIC_LVT_PERF 0x00000834
LVT Entry for PerfMon Interrupt.
#define | MSR_PIC_LVT_LINT0 0x00000835
LVT Entry for Lint Pin 0 Interrupt.
#define | MSR_PIC_LVT_LINT1 0x00000836
LVT Entry for Lint Pin 1 Interrupt.
#define | MSR_PIC_LVT_ERROR 0x00000837
LVT Entry for Error Interrupt.
#define | MSR_PIC_TIMER_INITIAL_COUNT_REG 0x00000838
APIC Initial Count register.
#define | MSR_PIC_TIMER_CURRENT_COUNT_REG 0x00000839
APIC Current Count register.
#define | MSR_VIRTUAL_APIC_16_16 0x0000083A
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x83A to 0x83D".
#define | MSR_VIRTUAL_APIC_17_17 0x0000083B
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x83A to 0x83D".
#define | MSR_VIRTUAL_APIC_18_18 0x0000083C
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x83A to 0x83D".
#define | MSR_VIRTUAL_APIC_19_19 0x0000083D
Virtual APIC MSRs that are modeled by ucode " seq has 4 instances in addresses range 0x83A to 0x83D".
#define | MSR_PIC_TIMER_DIVIDE_CONFIG_REG 0x0000083E
APIC Divide Configuration register.
#define | MSR_SELF_IPI 0x0000083F
x2APIC Self IPI register
#define | MSR_VIRTUAL_APIC_20_20 0x00000840
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_21_21 0x00000841
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_22_22 0x00000842
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_23_23 0x00000843
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_24_24 0x00000844
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_25_25 0x00000845
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_26_26 0x00000846
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_27_27 0x00000847
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_28_28 0x00000848
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_29_29 0x00000849
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_30_30 0x0000084A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_31_31 0x0000084B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_32_32 0x0000084C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_33_33 0x0000084D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_34_34 0x0000084E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_35_35 0x0000084F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_36_36 0x00000850
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_37_37 0x00000851
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_38_38 0x00000852
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_39_39 0x00000853
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_40_40 0x00000854
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_41_41 0x00000855
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_42_42 0x00000856
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_43_43 0x00000857
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_44_44 0x00000858
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_45_45 0x00000859
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_46_46 0x0000085A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_47_47 0x0000085B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_48_48 0x0000085C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_49_49 0x0000085D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_50_50 0x0000085E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_51_51 0x0000085F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_52_52 0x00000860
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_53_53 0x00000861
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_54_54 0x00000862
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_55_55 0x00000863
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_56_56 0x00000864
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_57_57 0x00000865
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_58_58 0x00000866
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_59_59 0x00000867
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_60_60 0x00000868
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_61_61 0x00000869
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_62_62 0x0000086A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_63_63 0x0000086B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_64_64 0x0000086C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_65_65 0x0000086D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_66_66 0x0000086E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_67_67 0x0000086F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_68_68 0x00000870
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_69_69 0x00000871
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_70_70 0x00000872
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_71_71 0x00000873
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_72_72 0x00000874
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_73_73 0x00000875
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_74_74 0x00000876
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_75_75 0x00000877
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_76_76 0x00000878
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_77_77 0x00000879
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_78_78 0x0000087A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_79_79 0x0000087B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_80_80 0x0000087C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_81_81 0x0000087D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_82_82 0x0000087E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_83_83 0x0000087F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_84_84 0x00000880
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_85_85 0x00000881
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_86_86 0x00000882
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_87_87 0x00000883
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_88_88 0x00000884
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_89_89 0x00000885
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_90_90 0x00000886
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_91_91 0x00000887
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_92_92 0x00000888
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_93_93 0x00000889
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_94_94 0x0000088A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_95_95 0x0000088B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_96_96 0x0000088C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_97_97 0x0000088D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_98_98 0x0000088E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_99_99 0x0000088F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_100_100 0x00000890
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_101_101 0x00000891
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_102_102 0x00000892
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_103_103 0x00000893
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_104_104 0x00000894
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_105_105 0x00000895
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_106_106 0x00000896
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_107_107 0x00000897
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_108_108 0x00000898
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_109_109 0x00000899
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_110_110 0x0000089A
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_111_111 0x0000089B
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_112_112 0x0000089C
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_113_113 0x0000089D
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_114_114 0x0000089E
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_115_115 0x0000089F
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_116_116 0x000008A0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_117_117 0x000008A1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_118_118 0x000008A2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_119_119 0x000008A3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_120_120 0x000008A4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_121_121 0x000008A5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_122_122 0x000008A6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_123_123 0x000008A7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_124_124 0x000008A8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_125_125 0x000008A9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_126_126 0x000008AA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_127_127 0x000008AB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_128_128 0x000008AC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_129_129 0x000008AD
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_130_130 0x000008AE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_131_131 0x000008AF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_132_132 0x000008B0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_133_133 0x000008B1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_134_134 0x000008B2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_135_135 0x000008B3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_136_136 0x000008B4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_137_137 0x000008B5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_138_138 0x000008B6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_139_139 0x000008B7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_140_140 0x000008B8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_141_141 0x000008B9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_142_142 0x000008BA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_143_143 0x000008BB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_144_144 0x000008BC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_145_145 0x000008BD
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_146_146 0x000008BE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_147_147 0x000008BF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_148_148 0x000008C0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_149_149 0x000008C1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_150_150 0x000008C2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_151_151 0x000008C3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_152_152 0x000008C4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_153_153 0x000008C5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_154_154 0x000008C6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_155_155 0x000008C7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_156_156 0x000008C8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_157_157 0x000008C9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_158_158 0x000008CA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_159_159 0x000008CB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_160_160 0x000008CC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_161_161 0x000008CD
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_162_162 0x000008CE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_163_163 0x000008CF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_164_164 0x000008D0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_165_165 0x000008D1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_166_166 0x000008D2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_167_167 0x000008D3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_168_168 0x000008D4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_169_169 0x000008D5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_170_170 0x000008D6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_171_171 0x000008D7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_172_172 0x000008D8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_173_173 0x000008D9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_174_174 0x000008DA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_175_175 0x000008DB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_176_176 0x000008DC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_177_177 0x000008DD
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_178_178 0x000008DE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_179_179 0x000008DF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_180_180 0x000008E0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_181_181 0x000008E1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_182_182 0x000008E2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_183_183 0x000008E3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_184_184 0x000008E4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_185_185 0x000008E5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_186_186 0x000008E6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_187_187 0x000008E7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_188_188 0x000008E8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_189_189 0x000008E9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_190_190 0x000008EA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_191_191 0x000008EB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_192_192 0x000008EC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_193_193 0x000008ED
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_194_194 0x000008EE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_195_195 0x000008EF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_196_196 0x000008F0
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_197_197 0x000008F1
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_198_198 0x000008F2
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_199_199 0x000008F3
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_200_200 0x000008F4
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_201_201 0x000008F5
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_202_202 0x000008F6
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_203_203 0x000008F7
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_204_204 0x000008F8
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_205_205 0x000008F9
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_206_206 0x000008FA
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_207_207 0x000008FB
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_208_208 0x000008FC
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_209_209 0x000008FD
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_210_210 0x000008FE
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_VIRTUAL_APIC_211_211 0x000008FF
Virtual APIC MSRs that are modeled by ucode " seq has 192 instances in addresses range 0x840 to 0x8FF".
#define | MSR_XRSTOR_INFO 0x00000900
Holds XSAVE_AREA "triplet" w/ addition of XCompaction vector for the XMODIFIED optimization.
#define | MSR_VMX_IO_EXIT_QUAL 0x00000901
Contains Exit Qual used on SMI I/O exits C6NoSave Candidate.
#define | MSR_TMPDR6 0x00000902
Equivalent to architectural DR6 reg. More...
#define | MSR_XU_MACROINSTRUCTION_ALIAS 0x00000903
Millicode MSR used to read/write certain fields of the Macroalias register. More...
#define | MSR_XU_VMX_CONTROL 0x00000904
Millicode MSR used to update the POST_VMXON and CURRENT_WP_IS_SHADOW_VMCS mode-based branch bits WRMSR will ignore the undefined bits RDMSR will always return 0 in undefined bits.
#define | MSR_VMX_PLE_FIRST 0x00000905
Pause-Loop Exiting: First value.
#define | MSR_VMX_PLE_LAST 0x00000906
Pause-Loop Exiting: Last value.
#define | MSR_VMX_VMENTRY_AVRR_TBIT_MAILBOX 0x00000907
Holds address bits [11:0] of a guest load/store access that hit the AVRR range C6NoSave Candidate FSCP Crunch: 12:32 Used only 12 bits out of 32.
#define | MSR_XU_SMM_STATE 0x00000908
Millicode MSR used to control SMM states WRMSR will ignore the undefined bits (63:32, 30:1). More...
#define | MSR_IO_SMI_BACKUP_RSI 0x00000909
Saved RSI value from IO SMI, used by parallel VMExit and SMI C6NoSave Candidate.
#define | MSR_IO_SMI_BACKUP_RCX 0x0000090A
Saved RCX value from IO SMI, used by parallel VMExit and SMI C6NoSave Candidate.
#define | MSR_IO_SMI_BACKUP_RDI 0x0000090B
Saved RDI value from IO SMI, used by parallel VMExit and SMI C6NoSave Candidate.
#define | MSR_VMX_VPPR 0x0000090C
Holds VPPR bits [7:4] FSCP Crunch: 4/32 Used only 4 bits out of 32.
#define | MSR_PDM_GDXC_MSG 0x0000090D
Write only MSR for Xucode to write PDM data out to the GDXC.
#define | MSR_GT_FLUSH_RELOAD 0x0000090E
This is a Write-Only cmd MSR. More...
#define | MSR_GT_FLUSH_BCLD_ACK 0x0000090F
GT writes a '1 to this bit to acknowledge PPPE range registers are loaded into GT.
#define | MSR_XRSTOR_XCOMPACTION_VECTOR 0x00000911
Holds XSAVE_AREA XCompaction vector for the XMODIFIED optimization.
#define | MSR_XU_TIO_CF_INFO 0x00000912
Trusted IO - CAM Filter Info.
#define | MSR_XU_TIO_CF_TABLE 0x00000913
MSR used to access the CAM Filter Table.
#define | MSR_VMX_AVRR_REMAP 0x00000915
VMX AVRR Remap Addr used in RR assist.
#define | MSR_AVRR_BASE 0x00000916
APIC Virtualization Range Register - Base address of virtual APIC.
#define | MSR_XU_RESERVED_1_1 0x00000917
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_2_2 0x00000918
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_3_3 0x00000919
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_4_4 0x0000091A
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_EM_EXCEPTIONS_HANDLING_EIP 0x0000091B
PPPE Exception Handling Entrypoint.
#define | MSR_XU_RESERVED_5_5 0x0000091C
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_6_6 0x0000091D
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_7_7 0x0000091E
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_8_8 0x0000091F
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_NCUWHOAMI 0x00000920
The who-am-I register is used by uCode to set up the APIC ID. More...
#define | MSR_PDM_HEADER 0x00000922
Write only MSR for Xucode to modify the PDM header for GDXC messages.
#define | MSR_MLC_PWR_MGMT_TIMER_CTRL 0x00000923
Timer control bits for various MLC/APIC Timers.
#define | MSR_PPPE_DOORBELL_EXIT_BITMAP 0x00000924
Scratch space exposed via MSR in PPPE.
#define | MSR_XU_RESERVED_9_9 0x00000928
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_10_10 0x00000929
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_11_11 0x0000092A
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_12_12 0x0000092B
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_13_13 0x0000092C
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_14_14 0x0000092D
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_15_15 0x0000092E
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_PIC_LT_DOORBELL 0x0000092F
Register decription.
#define | MSR_XU_RESERVED_16_16 0x00000930
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_17_17 0x00000931
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_18_18 0x00000932
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_VMCS_CACHE_BASE 0x00000933
PPPE will have read/write access to the FSCP_CR_VMCS_CACHE_BASE register for implementing the VMCS cache (i387450). More...
#define | MSR_PSMI_BASE 0x00000934
Scratch Pad register BNS_CR_PSMBASE.
#define | MSR_LT_SMX_STATE 0x00000936
Holds various SMX state.
#define | MSR_MLC_VT_TIMER_COUNT 0x00000937
VMX timer current count.
#define | MSR_MLC_VT_TIMER_CONTROL 0x00000938
VMX timer control.
#define | MSR_IOMISCINFO 0x00000939
SMM IO MISC INFO Register. More...
#define | MSR_XU_RESERVED_19_19 0x0000093B
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_IO_MEM_ADDR 0x0000093E
Memory address accessed by the last IO instruction. More...
#define | MSR_XU_RESERVED_20_20 0x0000093F
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_PDPTR_0_0 0x00000940
Mode C - Protected Mode PagDir Pointers - 0 " seq has 4 instances in addresses range 0x940 to 0x943".
#define | MSR_PDPTR_1_1 0x00000941
Mode C - Protected Mode PagDir Pointers - 0 " seq has 4 instances in addresses range 0x940 to 0x943".
#define | MSR_PDPTR_2_2 0x00000942
Mode C - Protected Mode PagDir Pointers - 0 " seq has 4 instances in addresses range 0x940 to 0x943".
#define | MSR_PDPTR_3_3 0x00000943
Mode C - Protected Mode PagDir Pointers - 0 " seq has 4 instances in addresses range 0x940 to 0x943".
#define | MSR_XU_RESERVED_21_21 0x00000944
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_22_22 0x00000945
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_23_23 0x00000946
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_24_24 0x00000947
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_25_25 0x00000948
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_26_26 0x00000949
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_27_27 0x0000094A
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_28_28 0x0000094B
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_29_29 0x0000094C
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XU_RESERVED_30_30 0x0000094D
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_XUCODE_UCODE_COMMAND 0x00000950
Each bit is command from xucode for specific action. More...
#define | MSR_GLOBAL_SE_ENABLE 0x00000951
An uncore register indicating that SE is fully installed. More...
#define | MSR_ELSRR_BASE 0x00000955
Enclave Linear Space Range Register - Physical Base Control Register.
#define | MSR_ELSRR_MASK 0x00000956
Enclave Linear Space Range Register - Physical Mask Control Register.
#define | MSR_TCS_PA 0x00000958
TCS Physical Address. More...
#define | MSR_SECS_SID 0x00000959
Holds SE Active SECS.
#define | MSR_FUSE_KEY1_0 0x00000960
This is a Read-Only xucode MSR.
#define | MSR_FUSE_KEY1_1 0x00000961
This is a Read-Only xucode MSR.
#define | MSR_EMRR_BASE 0x00000962
Millicode Memory Range Register - Physical Base Control Register.
#define | MSR_EMRR_MASK 0x00000963
Millicode Memory Range Register - Physical Mask Control Register.
#define | MSR_EMXRR_BASE 0x00000964
Xucode Memory Range Register - Physical Base Control Register.
#define | MSR_EMXRR_MASK 0x00000965
Xucode Memory Range Register - Physical Mask Control Register.
#define | MSR_XU_RESERVED_31_31 0x00000967
This define is used to reserve some MSR addresses for XuCode. More...
#define | MSR_MEE_SETUP 0x0000096A
This is uncore SCP. More...
#define | MSR_EE_INIT 0x0000096C
MEE init register.
#define | MSR_XCR0 0x0000096D
Holds XCR0 and XSAVE Compaction Vector (used for XMODIFIED optimization check)
#define | MSR_SGX_RDPCHSGXID_0 0x00000970
PCHSGXID 0 exposed in PCH by CSME.
#define | MSR_SGX_RDPCHSGXID_1 0x00000971
PCHSGXID 1 exposed in PCH by CSME.
#define | MSR_MCHECK_CPU_REGISTER_ADDRESS 0x00000972
MCHECK XuCode register that holds address of uncore register to be written.
#define | MSR_MCHECK_CPU_REGISTER_DATA 0x00000973
Virtual MSR to will write data to an Uncore CR. More...
#define | MSR_BIOS_TME_KEY_0 0x00000992
MSR to read/write ubox LOW TME EPHEMERAL KEY.
#define | MSR_BIOS_TME_KEY_1 0x00000993
MSR to read/write ubox HIGH TME EPHEMERAL KEY.
#define | MSR_CORE_MKTME_ACTIVATION 0x000009FF
Virtual MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS] from SoC. More...
#define | MSR_IO_BW_P_LIMIT_OVERRIDE 0x00000A00
Various controls.
#define | MSR_ENERGY_PERF_BIAS_CONFIG 0x00000A01
This register effectively governs all major power saving engines and hueristics on the die.
#define | MSR_SW_LTR_OVRD 0x00000A02
This register is intended for OS usage. More...
#define | MSR_M2PPMONCNTRCFG_2 0x00000B18
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_M2PPMONCNTRCFG_3 0x00000B19
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IRPPMONCNTRCFG_0 0x00000B1D
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IRPPMONCNTRCFG_1 0x00000B1E
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IIOPMONCNTR_0 0x00000B21
This register is a perf counter. More...
#define | MSR_IIOPMONCNTR_1 0x00000B22
This register is a perf counter. More...
#define | MSR_IIOPMONCNTR_2 0x00000B23
This register is a perf counter. More...
#define | MSR_IIOPMONCNTR_3 0x00000B24
This register is a perf counter. More...
#define | MSR_IOPMONCNTRCFG_0 0x00000B28
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IOPMONCNTRCFG_1 0x00000B29
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IOPMONCNTRCFG_2 0x00000B2A
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IOPMONCNTRCFG_3 0x00000B2B
Holds the status information and control the operation of the the PMON Fixed Counter.
#define | MSR_IIOPMONFRCNTR_0 0x00000B50
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_1 0x00000B51
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_2 0x00000B52
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_3 0x00000B53
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_4 0x00000B54
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_5 0x00000B55
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_6 0x00000B56
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_7 0x00000B57
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_8 0x00000B58
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_9 0x00000B59
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_10 0x00000B5A
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_11 0x00000B5B
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_12 0x00000B5C
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_13 0x00000B5D
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_14 0x00000B5E
This is the foward counter. More...
#define | MSR_IIOPMONFRCNTR_15 0x00000B5F
This is the foward counter. More...
#define | MSR_SMRAM_CR0 0x00000C00
Available only in SMM. More...
#define | MSR_SMRAM_CR3 0x00000C01
Available only in SMM. More...
#define | MSR_SMRAM_EFLAGS 0x00000C02
Available only in SMM. More...
#define | MSR_SMRAM_EFER 0x00000C03
Available only in SMM. More...
#define | MSR_SMRAM_RIP 0x00000C04
Available only in SMM. More...
#define | MSR_SMRAM_DR6 0x00000C05
Available only in SMM. More...
#define | MSR_SMRAM_DR7 0x00000C06
Available only in SMM. More...
#define | MSR_SMRAM_TR_LDTR 0x00000C07
Available only in SMM. More...
#define | MSR_SMRAM_GS_FS 0x00000C08
Available only in SMM. More...
#define | MSR_SMRAM_DS_SS 0x00000C09
Available only in SMM. More...
#define | MSR_SMRAM_CS_ES 0x00000C0A
Available only in SMM. More...
#define | MSR_SMRAM_IOMISCINFO 0x00000C0B
Available only in SMM. More...
#define | MSR_SMRAM_IO_MEM_ADDR 0x00000C0C
Available only in SMM. More...
#define | MSR_SMRAM_RDI 0x00000C0D
Available only in SMM. More...
#define | MSR_SMRAM_RSI 0x00000C0E
Available only in SMM. More...
#define | MSR_SMRAM_RBP 0x00000C0F
Available only in SMM. More...
#define | MSR_SMRAM_RSP 0x00000C10
Available only in SMM. More...
#define | MSR_SMRAM_RBX 0x00000C11
Available only in SMM. More...
#define | MSR_SMRAM_RDX 0x00000C12
Available only in SMM. More...
#define | MSR_SMRAM_RCX 0x00000C13
Available only in SMM. More...
#define | MSR_SMRAM_RAX 0x00000C14
Available only in SMM. More...
#define | MSR_SMRAM_R8 0x00000C15
Available only in SMM. More...
#define | MSR_SMRAM_R9 0x00000C16
Available only in SMM. More...
#define | MSR_SMRAM_R10 0x00000C17
Available only in SMM. More...
#define | MSR_SMRAM_R11 0x00000C18
Available only in SMM. More...
#define | MSR_SMRAM_R12 0x00000C19
Available only in SMM. More...
#define | MSR_SMRAM_R13 0x00000C1A
Available only in SMM. More...
#define | MSR_SMRAM_R14 0x00000C1B
Available only in SMM. More...
#define | MSR_SMRAM_R15 0x00000C1C
Available only in SMM. More...
#define | MSR_SMRAM_EVENT_CTL_HLT_IO 0x00000C1F
Available only in SMM. More...
#define | MSR_SMRAM_SMBASE 0x00000C20
Available only in SMM. More...
#define | MSR_SMRAM_SMM_REVID 0x00000C21
Available only in SMM. More...
#define | MSR_SMRAM_IEDBASE 0x00000C22
Available only in SMM. More...
#define | MSR_SMRAM_EPTP_ENABLE 0x00000C23
Available only in SMM. More...
#define | MSR_SMRAM_EPTP 0x00000C24
Available only in SMM. More...
#define | MSR_SMRAM_BNDCFGS 0x00000C25
Available only in SMM. More...
#define | MSR_SMRAM_LDTR_BASE 0x00000C2C
Available only in SMM. More...
#define | MSR_SMRAM_IDTR_BASE 0x00000C2D
Available only in SMM. More...
#define | MSR_SMRAM_GDTR_BASE 0x00000C2E
Available only in SMM. More...
#define | MSR_SMRAM_CR4 0x00000C37
Available only in SMM. More...
#define | MSR_SMRAM_IO_RSI 0x00000C40
Available only in SMM. More...
#define | MSR_SMRAM_IO_RCX 0x00000C41
Available only in SMM. More...
#define | MSR_SMRAM_IO_RIP 0x00000C42
Available only in SMM. More...
#define | MSR_SMRAM_IO_RDI 0x00000C43
Available only in SMM. More...
#define | MSR_PQOS_CDP_ENABLE 0x00000C81
CDP enable.
#define | MSR_IO_QOS_CFG 0x00000C83
IO QOS cfg.
#define | MSR_MBA_CFG 0x00000C84
MBA (mem bandwidth alloc) cfg.
#define | MSR_L3_PROTECTED_WAYS 0x00000C85
way mask for locked LLC ways. More...
#define | MSR_MBM_CFG_3DXP 0x00000C86
model specific msr to enable maksing of events that MBM counts
#define | MSR_QLRU_CONFIG 0x00000C8C
uCR: LRU Update values for various opcodes that update the LRU bits.
#define | MSR_QOSEVTSEL 0x00000C8D
MSR that is used to receive query id from software for which data will be looked up by another MSR.
#define | MSR_QMC 0x00000C8E
MSR that is used to convey the counter value for the RMID queried by the QOSEVTSEL MSR. More...
#define | MSR_LLC_QOS_MASK_0 0x00000C90
available ways vectors for class of service of IA core
#define | MSR_LLC_QOS_MASK_1 0x00000C91
available ways vectors for class of service of IA core
#define | MSR_LLC_QOS_MASK_2 0x00000C92
available ways vectors for class of service of IA core
#define | MSR_LLC_QOS_MASK_3 0x00000C93
available ways vectors for class of service of IA core
#define | MSR_LLC_QOS_MASK_4_4 0x00000C94
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_5_5 0x00000C95
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_6_6 0x00000C96
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_7_7 0x00000C97
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_8_8 0x00000C98
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_9_9 0x00000C99
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_10_10 0x00000C9A
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_11_11 0x00000C9B
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_12_12 0x00000C9C
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_13_13 0x00000C9D
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_LLC_QOS_MASK_14_14 0x00000C9E
available ways vectors for class of service of IA core " seq has 12 instances in addresses range 0x94 to 0x9F"
#define | MSR_QOS_EXT_BW_THRTL_0_0 0x00000D50
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_1_1 0x00000D51
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_2_2 0x00000D52
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_3_3 0x00000D53
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_4_4 0x00000D54
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_5_5 0x00000D55
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_6_6 0x00000D56
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_7_7 0x00000D57
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_8_8 0x00000D58
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_9_9 0x00000D59
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_10_10 0x00000D5A
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_11_11 0x00000D5B
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_12_12 0x00000D5C
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_13_13 0x00000D5D
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_QOS_EXT_BW_THRTL_14_14 0x00000D5E
This MSR is used for Memory BW enforcement " seq has 16 instances in addresses range 0xD50 to 0xD5F".
#define | MSR_THREAD_STALL_COUNTER 0x00000DB2
Accumulates value of THREAD_TSC_SAMPLE_PRE_OPD_ENTER on every OPD_EXIT when transitioning back to C0.
#define | MSR_LBR_INFO_0_0 0x00000DC0
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_1_1 0x00000DC1
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_2_2 0x00000DC2
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_3_3 0x00000DC3
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_4_4 0x00000DC4
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_5_5 0x00000DC5
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_6_6 0x00000DC6
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_7_7 0x00000DC7
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_8_8 0x00000DC8
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_9_9 0x00000DC9
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_10_10 0x00000DCA
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_11_11 0x00000DCB
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_12_12 0x00000DCC
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_13_13 0x00000DCD
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_14_14 0x00000DCE
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_15_15 0x00000DCF
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_16_16 0x00000DD0
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_17_17 0x00000DD1
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_18_18 0x00000DD2
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_19_19 0x00000DD3
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_20_20 0x00000DD4
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_21_21 0x00000DD5
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_22_22 0x00000DD6
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_23_23 0x00000DD7
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_24_24 0x00000DD8
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_25_25 0x00000DD9
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_26_26 0x00000DDA
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_27_27 0x00000DDB
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_28_28 0x00000DDC
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_29_29 0x00000DDD
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_30_30 0x00000DDE
LBR MSR that holds non-IP information.
#define | MSR_LBR_INFO_31_31 0x00000DDF
LBR MSR that holds non-IP information.
#define | MSR_AMRR_BASE_0_0 0x00000F00
Address Match Range Register - Physical Base Control Register for Hidden Lake " seq has 1 instances in addresses range 0xF00 to 0xF00".
#define | MSR_AMRR_MASK_0_0 0x00000F01
Address Match Range Register - Physical Mask Control Register for Hidden Lake " seq has 1 instances in addresses range 0xF01 to 0xF01".
#define | MSR_AMRR_BASE_1_1 0x00000F02
Address Match Range Register - Physical Base Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF02 to 0xF04".
#define | MSR_AMRR_MASK_1_1 0x00000F03
Address Match Range Register - Physical Mask Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF03 to 0xF05".
#define | MSR_AMRR_BASE_2_2 0x00000F04
Address Match Range Register - Physical Base Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF02 to 0xF04".
#define | MSR_AMRR_MASK_2_2 0x00000F05
Address Match Range Register - Physical Mask Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF03 to 0xF05".
#define | MSR_AMRR_BASE_3_3 0x00000F06
Address Match Range Register - Physical Base Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF06 to 0xF08".
#define | MSR_AMRR_MASK_3_3 0x00000F07
Address Match Range Register - Physical Mask Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF07 to 0xF09".
#define | MSR_AMRR_BASE_4_4 0x00000F08
Address Match Range Register - Physical Base Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF06 to 0xF08".
#define | MSR_AMRR_MASK_4_4 0x00000F09
Address Match Range Register - Physical Mask Control Register for Hidden Lake " seq has 2 instances in addresses range 0xF07 to 0xF09".
#define | MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0 0x00001001
Spare core MSRs supported by the cregpla. More...
#define | MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1 0x00001002
Spare core MSRs supported by the cregpla. More...
#define | MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2 0x00001003
Spare core MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0 0x00001004
Spare Thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1 0x00001005
Spare Thread MSRs supported by the cregpla. More...
#define | MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2 0x00001006
Spare Thread MSRs supported by the cregpla. More...

Detailed Description

CommonMsr.h.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CommonMsr.h.

Macro Definition Documentation

◆ MSR_AET_BASE_ADDRESS

#define MSR_AET_BASE_ADDRESS 0x00000521

AET base address.

programmed by probe mode software. cmoshe Ucode will use it as the address where it will send all PDM messages.

Definition at line 9378 of file CommonMsr.h.

◆ MSR_AET_MISC_ENABLE

#define MSR_AET_MISC_ENABLE 0x00000511

Programmed in Probe mode, used in PDM.

Need to save in C6

Definition at line 9081 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_0_0

#define MSR_ANC_BOOT_POLICY_0_0 0x00000130

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2656 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_1_1

#define MSR_ANC_BOOT_POLICY_1_1 0x00000131

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2663 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_2_2

#define MSR_ANC_BOOT_POLICY_2_2 0x00000132

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2670 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_3_3

#define MSR_ANC_BOOT_POLICY_3_3 0x00000133

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2677 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_4_4

#define MSR_ANC_BOOT_POLICY_4_4 0x00000134

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2684 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_5_5

#define MSR_ANC_BOOT_POLICY_5_5 0x00000135

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2691 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_6_6

#define MSR_ANC_BOOT_POLICY_6_6 0x00000136

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2698 of file CommonMsr.h.

◆ MSR_ANC_BOOT_POLICY_7_7

#define MSR_ANC_BOOT_POLICY_7_7 0x00000137

Anchor Cove MSR for reading boot policy information from the PCH.

8 new RDMSR range (addr 0x130-0x137), which read 64b each. Base addr is 0xFED58000 and reads are consecutive. " seq has 8 instances in addresses range 0x130 to 0x137"

Definition at line 2705 of file CommonMsr.h.

◆ MSR_ANC_FORCE_BOOT_POLICY_ENFORCED

#define MSR_ANC_FORCE_BOOT_POLICY_ENFORCED 0x00000138

Anchor Cove MSR to indicate that the initial boot block is complete, and to re-enable events.

Write-only and accessible via the ACM.

Definition at line 2711 of file CommonMsr.h.

◆ MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE

#define MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE 0x00000139

Anchor Cove MSR to tell PCH that the ACM has successfully launched and to stop the deadman timer countdown.

Write-only and accessible via the ACM.

Definition at line 2740 of file CommonMsr.h.

◆ MSR_ANC_SACM_INFO

#define MSR_ANC_SACM_INFO 0x0000013A

An MSR for communicating basic policy information from the Anchor Cove ACM to early BIOS.

Things like executing in NEM, thread protection enabled etc., will be communicated.

Definition at line 2777 of file CommonMsr.h.

◆ MSR_BIOS_DONE

#define MSR_BIOS_DONE 0x00000151

BIOS Done register for CNL issue 1351547.

  • Bit 0 (R/W): ENABLE_IA_UNTRUSTED o Cleared only by reset (cold/warm). o A change from 0->1 will increment BIOS_DONE_COUNTER in the SoC o Writes to the bit will be ignored if the EAX[0] is 0
  • Bit 1 (R): SOC_BIOS_DONE o Returns '1 if all available threads set their ENABLE_IA_UNTRUSTED. o Writes will be silently dropped.
  • Bits 31:2: Reserved - write '1 results in #GP.

Definition at line 3113 of file CommonMsr.h.

◆ MSR_BIOS_MAILBOX_DATA

#define MSR_BIOS_MAILBOX_DATA 0x00000608

Data register for the BIOS-to-PCODE mailbox.

This mailbox is implemented as a means for accessing statistics and implementing PCODE patches. This register is used in conjunction with BIOS_MAILBOX_INTERFACE.

Definition at line 9638 of file CommonMsr.h.

◆ MSR_BIOS_MAILBOX_INTERFACE

#define MSR_BIOS_MAILBOX_INTERFACE 0x00000607

Control and Status register for the BIOS-to-PCODE mailbox.

This mailbox is implemented as a means for accessing statistics and implementing PCODE patches. This register is used in conjunction with BIOS_MAILBOX_DATA.

Definition at line 9585 of file CommonMsr.h.

◆ MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG

#define MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG 0x00000121

This is a read/write MSR that will control the ucode emulation of the PM_TMR.

BIOS will program this register.

Definition at line 2525 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_0

#define MSR_C_STATE_LATENCY_CONTROL_0 0x0000060A

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 9676 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_1

#define MSR_C_STATE_LATENCY_CONTROL_1 0x0000060B

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 9730 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_2

#define MSR_C_STATE_LATENCY_CONTROL_2 0x0000060C

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 9784 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_3

#define MSR_C_STATE_LATENCY_CONTROL_3 0x00000633

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 10721 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_4

#define MSR_C_STATE_LATENCY_CONTROL_4 0x00000634

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 10775 of file CommonMsr.h.

◆ MSR_C_STATE_LATENCY_CONTROL_5

#define MSR_C_STATE_LATENCY_CONTROL_5 0x00000635

The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control.

This setting affects the selected package state.

Definition at line 10829 of file CommonMsr.h.

◆ MSR_CC3_RCNTR

#define MSR_CC3_RCNTR 0x000003FC

Time spent in the Core C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 8303 of file CommonMsr.h.

◆ MSR_CC7_RCNTR

#define MSR_CC7_RCNTR 0x000003FE

Time spent in the Core C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 8340 of file CommonMsr.h.

◆ MSR_CONFIG_TDP_NOMINAL

#define MSR_CONFIG_TDP_NOMINAL 0x00000648

This register is used to indicate the Nominal Configurable TDP ratio available for this specific sku.

System BIOS must use this value while building the _PSS table if the feature is enabled.

Definition at line 11156 of file CommonMsr.h.

◆ MSR_CORE_C6_RESIDENCY_COUNTER

#define MSR_CORE_C6_RESIDENCY_COUNTER 0x000003FD

Time spent in the Core C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency). CNL NEW: Moved from uncore to core

Definition at line 8335 of file CommonMsr.h.

◆ MSR_CORE_MKTME_ACTIVATION

#define MSR_CORE_MKTME_ACTIVATION 0x000009FF

Virtual MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS] from SoC.

Write with EDX:EAX == 0 will translate the above value into PMH mask register.

Definition at line 20488 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0

#define MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0 0x00001001

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1001 to 0x1003"

Definition at line 28256 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1

#define MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1 0x00001002

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1001 to 0x1003"

Definition at line 28261 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2

#define MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2 0x00001003

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1001 to 0x1003"

Definition at line 28266 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_SPARE_0_0

#define MSR_CORE_SPECIFIC_SPARE_0_0 0x0000013D

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 3 instances in addresses range 0x13D to 0x13F"

Definition at line 2883 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_SPARE_1_1

#define MSR_CORE_SPECIFIC_SPARE_1_1 0x0000013E

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 3 instances in addresses range 0x13D to 0x13F"

Definition at line 2888 of file CommonMsr.h.

◆ MSR_CORE_SPECIFIC_SPARE_2_2

#define MSR_CORE_SPECIFIC_SPARE_2_2 0x0000013F

Spare core MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 3 instances in addresses range 0x13D to 0x13F"

Definition at line 2893 of file CommonMsr.h.

◆ MSR_DCU_MODE_CONTROL

#define MSR_DCU_MODE_CONTROL 0x00000031

MSR used to select the mode for the Data Cache Unit (DCU).

This MSR is only available when more than one DCU Mode is selectable and is only intended for use in early BIOS before the first transition of the CR0.CD from 1 to 0.

Definition at line 356 of file CommonMsr.h.

◆ MSR_DDR_RAPL_PERF_STATUS

#define MSR_DDR_RAPL_PERF_STATUS 0x0000061B

Memory RAPL performance excursion counter.

This register can report the performance impact of power limiting.

Definition at line 10289 of file CommonMsr.h.

◆ MSR_DEBUG_ERR_INJ_CTL

#define MSR_DEBUG_ERR_INJ_CTL 0x000001E3

This MSR holds the capability of error spoofing.

Bit 1 for unlock MCA/ CMCI generation capability (allows event injection), bit 0 to unlock writing to MC banks

Definition at line 5435 of file CommonMsr.h.

◆ MSR_EMON_PERF_RES_PROGRAMMED

#define MSR_EMON_PERF_RES_PROGRAMMED 0x00000392

This MSR displays the programming status of all the PerfMon counters.

It is a per logical processor read-only MSR used to observe the [IntelRsvd]?in-use?[/IntelRsvd] status of all the counters at once. [IntelRsvd]It is made architectural starting Skylake called IA32_PERF_GLOBAL_INUSE (MSR address 0x392)[/IntelRsvd]

Definition at line 7967 of file CommonMsr.h.

◆ MSR_ERROR_CONTROL

#define MSR_ERROR_CONTROL 0x0000017F

[p]A non-architectural, package-scoped MSR intended for use by BIOS.

ERROR_CONTROL[4] is a r/w bit that defeatures CMCI. Storage for this bit is in the UNCORE_SCP_MISC2_CREG[4]. The bit will be saved and restored in C7+ states.[/p] [p]The reset value for the bit is 0. It will not survive warm reset.[/p] [p]When MSR 0x17F bit 4 is set, two actions will happen:[/p] [list] [*]RDMSR to MCG_CAP will have bit 10 cleared to 0. [*]WRMSR to MCi_MISC2 registers will clear bits[31:0] in all modes. [/list]

Definition at line 4085 of file CommonMsr.h.

◆ MSR_FAST_UNCORE_MSRS_CAPABILITY

#define MSR_FAST_UNCORE_MSRS_CAPABILITY 0x0000065F

Fast wrmsr/rdmsr enumeration MSR.

This is read-only MSR. Each bit refers to one MSR and indicate if this MSR is enabled to be use in FAST_UNCORE_MSRS.

Definition at line 12043 of file CommonMsr.h.

◆ MSR_FEATURE_CONFIG

#define MSR_FEATURE_CONFIG 0x0000013C

AES Feature configuration.

This MSR is visible only if one of the following holds: CPUID.(EAX=01h):ECX[25]=1, which indicates the processor was manufactured with AES-NI enabled.

Definition at line 2843 of file CommonMsr.h.

◆ MSR_GLOBAL_SE_ENABLE

#define MSR_GLOBAL_SE_ENABLE 0x00000951

An uncore register indicating that SE is fully installed.

Used by CPUID and preamble need to check the option to cache it for each core

Definition at line 19894 of file CommonMsr.h.

◆ MSR_GT_FLUSH_RELOAD

#define MSR_GT_FLUSH_RELOAD 0x0000090E

This is a Write-Only cmd MSR.

A write causes GT to flush outstanding transactions and re-load it's boot context. A Rd will GP Fault. With the removal of the GT_CREG_ADDR_DIFFERENTIATOR there is no need for this to be virtual

Definition at line 18460 of file CommonMsr.h.

◆ MSR_IA_PERF_LIMIT_REASONS

#define MSR_IA_PERF_LIMIT_REASONS 0x0000064F

Interface to allow software to determine what is causing resolved frequency to be clamped below the requested frequency.

Status bits are updated by pcode through the io interface IO_IA_PERF_LIMIT, log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

Definition at line 11429 of file CommonMsr.h.

◆ MSR_ICECTLPMR

#define MSR_ICECTLPMR 0x000001DF

Probe mode control and status register.

16 bit. (Mrm roctlregc/roctlregd/icectlpmrSM306L)

Definition at line 5159 of file CommonMsr.h.

◆ MSR_ICECTLPMR_PRIOR_STATE

#define MSR_ICECTLPMR_PRIOR_STATE 0x00000520

Scratch Pad register ICECTLPMR_PRIOR_STATE Used only by probe mode.

C6NoSave candidate

Definition at line 9372 of file CommonMsr.h.

◆ MSR_IIOPMONCNTR_0

#define MSR_IIOPMONCNTR_0 0x00000B21

This register is a perf counter.

Software can read it and write it

Definition at line 21530 of file CommonMsr.h.

◆ MSR_IIOPMONCNTR_1

#define MSR_IIOPMONCNTR_1 0x00000B22

This register is a perf counter.

Software can read it and write it

Definition at line 21563 of file CommonMsr.h.

◆ MSR_IIOPMONCNTR_2

#define MSR_IIOPMONCNTR_2 0x00000B23

This register is a perf counter.

Software can read it and write it

Definition at line 21596 of file CommonMsr.h.

◆ MSR_IIOPMONCNTR_3

#define MSR_IIOPMONCNTR_3 0x00000B24

This register is a perf counter.

Software can read it and write it

Definition at line 21629 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_0

#define MSR_IIOPMONFRCNTR_0 0x00000B50

This is the foward counter.

Software can read and write into it

Definition at line 22548 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_1

#define MSR_IIOPMONFRCNTR_1 0x00000B51

This is the foward counter.

Software can read and write into it

Definition at line 22581 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_10

#define MSR_IIOPMONFRCNTR_10 0x00000B5A

This is the foward counter.

Software can read and write into it

Definition at line 22878 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_11

#define MSR_IIOPMONFRCNTR_11 0x00000B5B

This is the foward counter.

Software can read and write into it

Definition at line 22911 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_12

#define MSR_IIOPMONFRCNTR_12 0x00000B5C

This is the foward counter.

Software can read and write into it

Definition at line 22944 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_13

#define MSR_IIOPMONFRCNTR_13 0x00000B5D

This is the foward counter.

Software can read and write into it

Definition at line 22977 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_14

#define MSR_IIOPMONFRCNTR_14 0x00000B5E

This is the foward counter.

Software can read and write into it

Definition at line 23010 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_15

#define MSR_IIOPMONFRCNTR_15 0x00000B5F

This is the foward counter.

Software can read and write into it

Definition at line 23043 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_2

#define MSR_IIOPMONFRCNTR_2 0x00000B52

This is the foward counter.

Software can read and write into it

Definition at line 22614 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_3

#define MSR_IIOPMONFRCNTR_3 0x00000B53

This is the foward counter.

Software can read and write into it

Definition at line 22647 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_4

#define MSR_IIOPMONFRCNTR_4 0x00000B54

This is the foward counter.

Software can read and write into it

Definition at line 22680 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_5

#define MSR_IIOPMONFRCNTR_5 0x00000B55

This is the foward counter.

Software can read and write into it

Definition at line 22713 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_6

#define MSR_IIOPMONFRCNTR_6 0x00000B56

This is the foward counter.

Software can read and write into it

Definition at line 22746 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_7

#define MSR_IIOPMONFRCNTR_7 0x00000B57

This is the foward counter.

Software can read and write into it

Definition at line 22779 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_8

#define MSR_IIOPMONFRCNTR_8 0x00000B58

This is the foward counter.

Software can read and write into it

Definition at line 22812 of file CommonMsr.h.

◆ MSR_IIOPMONFRCNTR_9

#define MSR_IIOPMONFRCNTR_9 0x00000B59

This is the foward counter.

Software can read and write into it

Definition at line 22845 of file CommonMsr.h.

◆ MSR_IO_MEM_ADDR

#define MSR_IO_MEM_ADDR 0x0000093E

Memory address accessed by the last IO instruction.

Used to communicate between io and SMI/PPPE. C6NoSave candidate

Definition at line 19476 of file CommonMsr.h.

◆ MSR_IOMISCINFO

#define MSR_IOMISCINFO 0x00000939

SMM IO MISC INFO Register.

32 bit. (Mrm roctlregc/roapes/roiomiscinfoSM306L)

Definition at line 19427 of file CommonMsr.h.

◆ MSR_L3_PROTECTED_WAYS

#define MSR_L3_PROTECTED_WAYS 0x00000C85

way mask for locked LLC ways.

If the hit way intersects this mask, LLC to SF migration is disabled

Definition at line 24333 of file CommonMsr.h.

◆ MSR_LLC_FLUSHED_RCNTR

#define MSR_LLC_FLUSHED_RCNTR 0x0000061D

Time spent with LLC flushed.

Count at the same frequency as the TSC

Definition at line 10382 of file CommonMsr.h.

◆ MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN

#define MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN 0x00000061

This MSR reads/writes CBO_CR_CBO_COH_CONFIG[0].

SKX bug 305692

Definition at line 966 of file CommonMsr.h.

◆ MSR_MCHECK_CPU_REGISTER_DATA

#define MSR_MCHECK_CPU_REGISTER_DATA 0x00000973

Virtual MSR to will write data to an Uncore CR.

The write is invoked by MCHECK flow. CR address is taken from MSR 0x972

Definition at line 20475 of file CommonMsr.h.

◆ MSR_MCI_CTL2

#define MSR_MCI_CTL2 0x00000298

This register is used for generating corrected error interrupts.

This is a 64 bits register. Refer to the MCA HAS for details. x86_architectural: true creg_msr_symbol: MCi_CTL2 creg_msr_mask: 64'hFFFFFFFABFFF8000

Definition at line 6306 of file CommonMsr.h.

◆ MSR_MEE_SETUP

#define MSR_MEE_SETUP 0x0000096A

This is uncore SCP.

RO MSR to provide 128 bits of external entropy used for key derivation.

Definition at line 20315 of file CommonMsr.h.

◆ MSR_MISC_THD_FEATURE_ENABLES

#define MSR_MISC_THD_FEATURE_ENABLES 0x00000140

Miscellaneous enables for thread specific features.

[IntelRsvd]FSCP Crunch - 1:32 Used only 1 bit out of 32[/IntelRsvd]

Definition at line 2899 of file CommonMsr.h.

◆ MSR_MSR_THERM2_CTL

#define MSR_MSR_THERM2_CTL 0x0000019D

Deprecated.

The MSR always return zero.

Definition at line 4225 of file CommonMsr.h.

◆ MSR_NCUPMONCTRLGLCTR

#define MSR_NCUPMONCTRLGLCTR 0x00000707

Holds global control fields for the NCU PMON counters.

All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCtrClr] is set to 1b.

Definition at line 14167 of file CommonMsr.h.

◆ MSR_NCUPMONGLSTS1

#define MSR_NCUPMONGLSTS1 0x0000070F

PMON Global Status register.

All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

Definition at line 14324 of file CommonMsr.h.

◆ MSR_NCUWHOAMI

#define MSR_NCUWHOAMI 0x00000920

The who-am-I register is used by uCode to set up the APIC ID.

This register is initialized by the PCU according to the socket configuration using the NcuPcuWHOAMI register. The who-am-i register returns a thread specific identifier, however some of the fields of this registers are shared between all threads as indicated by the fields description.

Definition at line 18787 of file CommonMsr.h.

◆ MSR_P6_CR_SMREVID

#define MSR_P6_CR_SMREVID 0x00000170

SMM revision identifier.

[IntelRsvd] REVIEW: Register could be removed if RDMSR and SMM ucode use constants[/IntelRsvd]

Definition at line 3668 of file CommonMsr.h.

◆ MSR_PACKAGE_ENERGY_STATUS

#define MSR_PACKAGE_ENERGY_STATUS 0x00000611

Package energy consumed by the entire CPU (including IA, GT and uncore).

The counter will wrap around and continue counting when it reaches its limit. The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].

Definition at line 10017 of file CommonMsr.h.

◆ MSR_PACKAGE_POWER_SKU

#define MSR_PACKAGE_POWER_SKU 0x00000614

Defines allowed SKU power and timing parameters.

PCODE will update the contents of this register.

Definition at line 10027 of file CommonMsr.h.

◆ MSR_PACKAGE_RAPL_PERF_STATUS

#define MSR_PACKAGE_RAPL_PERF_STATUS 0x00000613

Package RAPL Performance Status Register.

This register provides information on the performance impact of the RAPL power limit and indicates the duration for processor went below the requested P-state due to package power constraint.

Definition at line 10021 of file CommonMsr.h.

◆ MSR_PACKAGE_THERM_MARGIN

#define MSR_PACKAGE_THERM_MARGIN 0x000001A1

Temperature margin in PECI temperature counts from the thermal profile specification.

Platform fan control SW is expected to read therm_margin value to control fan or blower speed.

Definition at line 4230 of file CommonMsr.h.

◆ MSR_PC10_RCNTR

#define MSR_PC10_RCNTR 0x00000632

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency). This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs). For C2, this value includes any forced or popup time from other states. For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

Definition at line 10688 of file CommonMsr.h.

◆ MSR_PC2_RCNTR

#define MSR_PC2_RCNTR 0x0000060D

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 9838 of file CommonMsr.h.

◆ MSR_PC3_RCNTR

#define MSR_PC3_RCNTR 0x000003F8

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 8204 of file CommonMsr.h.

◆ MSR_PC6_RCNTR

#define MSR_PC6_RCNTR 0x000003F9

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 8237 of file CommonMsr.h.

◆ MSR_PC7_RCNTR

#define MSR_PC7_RCNTR 0x000003FA

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

Definition at line 8270 of file CommonMsr.h.

◆ MSR_PC8_RCNTR

#define MSR_PC8_RCNTR 0x00000630

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency). This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs). For C2, this value includes any forced or popup time from other states. For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

Definition at line 10616 of file CommonMsr.h.

◆ MSR_PC9_RCNTR

#define MSR_PC9_RCNTR 0x00000631

Time spent in the Package C-State.

It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency). This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs). For C2, this value includes any forced or popup time from other states. For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

Definition at line 10652 of file CommonMsr.h.

◆ MSR_PEBS_FRONTEND

#define MSR_PEBS_FRONTEND 0x000003F7

Precise Performance Monitoring (PPMON) Event Control.

This register is read-write.

Definition at line 8134 of file CommonMsr.h.

◆ MSR_PERFCTR0

#define MSR_PERFCTR0 0x000003B8

IDP 1 PMON Counter 1 data register The Fix counter is counting UCLK cycles.

All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

Definition at line 8026 of file CommonMsr.h.

◆ MSR_PERFCTR1

#define MSR_PERFCTR1 0x000003B9

IDP 1 PMON Counter 2 data register The Fix counter is counting UCLK cycles.

All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

Definition at line 8067 of file CommonMsr.h.

◆ MSR_PFR_EXIT

#define MSR_PFR_EXIT 0x00000066

Used to exit out of PFR VCM.

Write only command MSR. Read will #GP

Definition at line 1195 of file CommonMsr.h.

◆ MSR_PLAT_FRMW_PROT_TRIGGER

#define MSR_PLAT_FRMW_PROT_TRIGGER 0x00000116

This is a Write-Only command MSR.

A write triggers the command. A Rd will GP Fault.

Definition at line 2442 of file CommonMsr.h.

◆ MSR_POWERON

#define MSR_POWERON 0x0000002A

MSR read by Sandra and HotCPU test.

Added to prevent these benchmarks from crashing. See NHM-B bug 2425276

Definition at line 59 of file CommonMsr.h.

◆ MSR_PRIMARY_PLANE_ENERGY_STATUS

#define MSR_PRIMARY_PLANE_ENERGY_STATUS 0x00000639

Reports total energy consumed.

The counter will wrap around and continue counting when it reaches its limit. The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT]. SW will read this value and subtract the difference from last value read. The value of this register is updated every 1mSec.

Definition at line 11001 of file CommonMsr.h.

◆ MSR_PRIMARY_PLANE_OVERFLOW_STATUS

#define MSR_PRIMARY_PLANE_OVERFLOW_STATUS 0x0000063B

Memory RAPL performance excursion counter.

This register can report the performance impact of power limiting.

Definition at line 11037 of file CommonMsr.h.

◆ MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT

#define MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT 0x00000638

This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Primary Power Plane.

The overall package turbo power limitation is controlled by PACKAGE_RAPL_LIMIT.

Definition at line 10926 of file CommonMsr.h.

◆ MSR_PRIMARY_PLANE_TURBO_POWER_POLICY

#define MSR_PRIMARY_PLANE_TURBO_POWER_POLICY 0x0000063A

The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes.

The power plane with the higher policy will get a higher priority. The default value will aim to maintain same ratio for IA and GT.

Definition at line 11007 of file CommonMsr.h.

◆ MSR_PROBE_CHANGE_PG

#define MSR_PROBE_CHANGE_PG 0x00000077

Not really a register.

Probe mode MSR used for changing CR0.PG to the value specified in bit 31 of EAX. It allows ITP to transition into and back out of Pseudo-64-bit mode (Long Mode, but with paging turned off).

Definition at line 1321 of file CommonMsr.h.

◆ MSR_PROBE_CPL

#define MSR_PROBE_CPL 0x00000101

Not really a register.

Probe mode MSR used to modify CPL.

Definition at line 2302 of file CommonMsr.h.

◆ MSR_PROBE_GP_REG

#define MSR_PROBE_GP_REG 0x00000071

Not really a register.

Probe mode MSR used for copying EDX, EAX, EFLAGS, ST0 and the SMMEM bit to/from the scratch pad

Definition at line 1293 of file CommonMsr.h.

◆ MSR_PROBE_LT_SPC_CYC

#define MSR_PROBE_LT_SPC_CYC 0x00000076

Not really a register.

Probe mode MSR Register used for issuing Special Cycles to the LT chipset.

Definition at line 1316 of file CommonMsr.h.

◆ MSR_PROBE_MMX2_REG

#define MSR_PROBE_MMX2_REG 0x00000074

Not really a register.

Probe mode MSR used for copying XMM0 and MXCSR to the scratch pad for probe mode.

Definition at line 1308 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_10_10

#define MSR_PROBE_MODE_RESERVED_10_10 0x0000051D

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9356 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_11_11

#define MSR_PROBE_MODE_RESERVED_11_11 0x0000051E

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9361 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_12_12

#define MSR_PROBE_MODE_RESERVED_12_12 0x0000051F

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9366 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_1_1

#define MSR_PROBE_MODE_RESERVED_1_1 0x00000514

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9311 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_2_2

#define MSR_PROBE_MODE_RESERVED_2_2 0x00000515

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9316 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_3_3

#define MSR_PROBE_MODE_RESERVED_3_3 0x00000516

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9321 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_4_4

#define MSR_PROBE_MODE_RESERVED_4_4 0x00000517

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9326 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_5_5

#define MSR_PROBE_MODE_RESERVED_5_5 0x00000518

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9331 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_6_6

#define MSR_PROBE_MODE_RESERVED_6_6 0x00000519

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9336 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_7_7

#define MSR_PROBE_MODE_RESERVED_7_7 0x0000051A

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9341 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_8_8

#define MSR_PROBE_MODE_RESERVED_8_8 0x0000051B

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9346 of file CommonMsr.h.

◆ MSR_PROBE_MODE_RESERVED_9_9

#define MSR_PROBE_MODE_RESERVED_9_9 0x0000051C

This define is used to reserve some MSR addresses for probe mode.

Ucode would have a dedicated handler for these MSRs " seq has 12 instances in addresses range 0x514 to 0x51F"

Definition at line 9351 of file CommonMsr.h.

◆ MSR_PROBE_PL_REG

#define MSR_PROBE_PL_REG 0x00000073

Not really a register.

Probe mode MSR added in SKL i1350201 that on RD/WRMSR does the following operations: R16/R17 to/from CTAP_CR_PROBE_MODE_DR/FSCP_CR_REGISTER_1 BND_STATUS to/from FSCP_CR_REGISTER_2 BNDCFG3_BASE_FIELD to/from FSCP_CR_REGISTER_3

Definition at line 1304 of file CommonMsr.h.

◆ MSR_PROBE_SEG_REG_1

#define MSR_PROBE_SEG_REG_1 0x00000072

Not really a register.

Probe mode MSR used for copying SS, CS, ES, LDTR, and GDTR to the scratch pad for probe mode.

Definition at line 1297 of file CommonMsr.h.

◆ MSR_PROBE_SEG_REG_3

#define MSR_PROBE_SEG_REG_3 0x00000075

Not really a register.

Probe mode MSR used for copying shadow copies of ES, DS, FS, and GS to the scratch pad for probe mode.

Definition at line 1312 of file CommonMsr.h.

◆ MSR_PROBE_TLB_FLUSH

#define MSR_PROBE_TLB_FLUSH 0x00000508

Not really a register.

Probe mode MSR used to flush all TLBs.

Definition at line 9067 of file CommonMsr.h.

◆ MSR_PROBE_TO_FROM_PDR

#define MSR_PROBE_TO_FROM_PDR 0x00000070

Not really a register.

Probe mode MSR used to move data from/to PDR

Definition at line 1289 of file CommonMsr.h.

◆ MSR_PROBE_VMX_POINTER

#define MSR_PROBE_VMX_POINTER 0x00000509

Not really a register.

Probe mode MSR used to read/write VMX pointers.

Definition at line 9071 of file CommonMsr.h.

◆ MSR_PST_CONFIG_CONTROL

#define MSR_PST_CONFIG_CONTROL 0x00000609

This MSR reads/writes THREAD_P_REQ[P_STATE_OFFSET].

HSW ECO 4400429

Definition at line 9643 of file CommonMsr.h.

◆ MSR_QMC

#define MSR_QMC 0x00000C8E

MSR that is used to convey the counter value for the RMID queried by the QOSEVTSEL MSR.

This is a Read only MSR.

Definition at line 24652 of file CommonMsr.h.

◆ MSR_SECONDARY_PLANE_ENERGY_STATUS

#define MSR_SECONDARY_PLANE_ENERGY_STATUS 0x00000641

Reports total energy consumed.

The counter will wrap around and continue counting when it reaches its limit. The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT]. SW will read this value and subtract the difference from last value read. The value of this register is updated every 1mSec.

Definition at line 11118 of file CommonMsr.h.

◆ MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT

#define MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT 0x00000640

This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Secondary Power Plane.

The overall package turbo power limitation is controlled by PACKAGE_RAPL_LIMIT.

Definition at line 11043 of file CommonMsr.h.

◆ MSR_SECONDARY_PLANE_TURBO_POWER_POLICY

#define MSR_SECONDARY_PLANE_TURBO_POWER_POLICY 0x00000642

The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes.

The power plane with the higher policy will get a higher priority. The default value will aim to maintain same ratio for IA and GT.

Definition at line 11124 of file CommonMsr.h.

◆ MSR_SMM_ENABLE_MASK

#define MSR_SMM_ENABLE_MASK 0x000004EA

Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's) that should be servicing a Targeted SMI.

BIOS programs the MASK register to indicate which bits should be masked before doing a MATCH check

Definition at line 8941 of file CommonMsr.h.

◆ MSR_SMM_ENABLE_MATCH

#define MSR_SMM_ENABLE_MATCH 0x000004E8

Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's) that should be servicing a Targeted SMI.

BIOS programs the MASK register to indicate which bits should be masked before doing a MATCH check

Definition at line 8900 of file CommonMsr.h.

◆ MSR_SMRAM_BNDCFGS

#define MSR_SMRAM_BNDCFGS 0x00000C25

Available only in SMM.

SMRAM copy of BNDCFGS saved by SMI

Definition at line 24068 of file CommonMsr.h.

◆ MSR_SMRAM_CR0

#define MSR_SMRAM_CR0 0x00000C00

Available only in SMM.

SMRAM copy of CR0 saved by SMI

Definition at line 23076 of file CommonMsr.h.

◆ MSR_SMRAM_CR3

#define MSR_SMRAM_CR3 0x00000C01

Available only in SMM.

SMRAM copy of CR3 saved by SMI

Definition at line 23180 of file CommonMsr.h.

◆ MSR_SMRAM_CR4

#define MSR_SMRAM_CR4 0x00000C37

Available only in SMM.

SMRAM copy of CR0 saved by SMI

Definition at line 24085 of file CommonMsr.h.

◆ MSR_SMRAM_CS_ES

#define MSR_SMRAM_CS_ES 0x00000C0A

Available only in SMM.

SMRAM copy of CS and ES saved by SMI

Definition at line 23771 of file CommonMsr.h.

◆ MSR_SMRAM_DR6

#define MSR_SMRAM_DR6 0x00000C05

Available only in SMM.

SMRAM copy of DR6 saved by SMI

Definition at line 23443 of file CommonMsr.h.

◆ MSR_SMRAM_DR7

#define MSR_SMRAM_DR7 0x00000C06

Available only in SMM.

SMRAM copy of DR7 saved by SMI

Definition at line 23526 of file CommonMsr.h.

◆ MSR_SMRAM_DS_SS

#define MSR_SMRAM_DS_SS 0x00000C09

Available only in SMM.

SMRAM copy of DS and SS saved by SMI

Definition at line 23733 of file CommonMsr.h.

◆ MSR_SMRAM_EFER

#define MSR_SMRAM_EFER 0x00000C03

Available only in SMM.

SMRAM copy of EFER saved by SMI

Definition at line 23381 of file CommonMsr.h.

◆ MSR_SMRAM_EFLAGS

#define MSR_SMRAM_EFLAGS 0x00000C02

Available only in SMM.

SMRAM copy of EFLAGS saved by SMI

Definition at line 23248 of file CommonMsr.h.

◆ MSR_SMRAM_EPTP

#define MSR_SMRAM_EPTP 0x00000C24

Available only in SMM.

SMRAM copy of EPTP saved by SMI

Definition at line 24064 of file CommonMsr.h.

◆ MSR_SMRAM_EPTP_ENABLE

#define MSR_SMRAM_EPTP_ENABLE 0x00000C23

Available only in SMM.

SMRAM copy of EPTP_ENABLE saved by SMI

Definition at line 24027 of file CommonMsr.h.

◆ MSR_SMRAM_EVENT_CTL_HLT_IO

#define MSR_SMRAM_EVENT_CTL_HLT_IO 0x00000C1F

Available only in SMM.

SMRAM copy of EVENT_CTL, HLT flag and IO flag saved by SMI

Definition at line 23905 of file CommonMsr.h.

◆ MSR_SMRAM_GDTR_BASE

#define MSR_SMRAM_GDTR_BASE 0x00000C2E

Available only in SMM.

SMRAM copy of IDTR_BASE saved by SMI

Definition at line 24080 of file CommonMsr.h.

◆ MSR_SMRAM_GS_FS

#define MSR_SMRAM_GS_FS 0x00000C08

Available only in SMM.

SMRAM copy of GS and FS saved by SMI

Definition at line 23695 of file CommonMsr.h.

◆ MSR_SMRAM_IDTR_BASE

#define MSR_SMRAM_IDTR_BASE 0x00000C2D

Available only in SMM.

SMRAM copy of IDTR_BASE saved by SMI

Definition at line 24076 of file CommonMsr.h.

◆ MSR_SMRAM_IEDBASE

#define MSR_SMRAM_IEDBASE 0x00000C22

Available only in SMM.

SMRAM copy of IEDBASE saved by SMI

Definition at line 23999 of file CommonMsr.h.

◆ MSR_SMRAM_IO_MEM_ADDR

#define MSR_SMRAM_IO_MEM_ADDR 0x00000C0C

Available only in SMM.

SMRAM copy of IO_MEM_ADDR saved by SMI

Definition at line 23836 of file CommonMsr.h.

◆ MSR_SMRAM_IO_RCX

#define MSR_SMRAM_IO_RCX 0x00000C41

Available only in SMM.

SMRAM copy of IO_RCX saved by SMI

Definition at line 24226 of file CommonMsr.h.

◆ MSR_SMRAM_IO_RDI

#define MSR_SMRAM_IO_RDI 0x00000C43

Available only in SMM.

SMRAM copy of IO_RDI saved by SMI

Definition at line 24234 of file CommonMsr.h.

◆ MSR_SMRAM_IO_RIP

#define MSR_SMRAM_IO_RIP 0x00000C42

Available only in SMM.

SMRAM copy of IO_RIP saved by SMI

Definition at line 24230 of file CommonMsr.h.

◆ MSR_SMRAM_IO_RSI

#define MSR_SMRAM_IO_RSI 0x00000C40

Available only in SMM.

SMRAM copy of IO_RSI saved by SMI

Definition at line 24222 of file CommonMsr.h.

◆ MSR_SMRAM_IOMISCINFO

#define MSR_SMRAM_IOMISCINFO 0x00000C0B

Available only in SMM.

SMRAM copy of IOMISCINFO saved by SMI

Definition at line 23809 of file CommonMsr.h.

◆ MSR_SMRAM_LDTR_BASE

#define MSR_SMRAM_LDTR_BASE 0x00000C2C

Available only in SMM.

SMRAM copy of LDTR_BASE saved by SMI

Definition at line 24072 of file CommonMsr.h.

◆ MSR_SMRAM_R10

#define MSR_SMRAM_R10 0x00000C17

Available only in SMM.

SMRAM copy of R10 saved by SMI

Definition at line 23880 of file CommonMsr.h.

◆ MSR_SMRAM_R11

#define MSR_SMRAM_R11 0x00000C18

Available only in SMM.

SMRAM copy of R11 saved by SMI

Definition at line 23884 of file CommonMsr.h.

◆ MSR_SMRAM_R12

#define MSR_SMRAM_R12 0x00000C19

Available only in SMM.

SMRAM copy of R12 saved by SMI

Definition at line 23888 of file CommonMsr.h.

◆ MSR_SMRAM_R13

#define MSR_SMRAM_R13 0x00000C1A

Available only in SMM.

SMRAM copy of R13 saved by SMI

Definition at line 23892 of file CommonMsr.h.

◆ MSR_SMRAM_R14

#define MSR_SMRAM_R14 0x00000C1B

Available only in SMM.

SMRAM copy of R14 saved by SMI

Definition at line 23896 of file CommonMsr.h.

◆ MSR_SMRAM_R15

#define MSR_SMRAM_R15 0x00000C1C

Available only in SMM.

SMRAM copy of RDI saved by SMI

Definition at line 23900 of file CommonMsr.h.

◆ MSR_SMRAM_R8

#define MSR_SMRAM_R8 0x00000C15

Available only in SMM.

SMRAM copy of R8 saved by SMI

Definition at line 23872 of file CommonMsr.h.

◆ MSR_SMRAM_R9

#define MSR_SMRAM_R9 0x00000C16

Available only in SMM.

SMRAM copy of R9 saved by SMI

Definition at line 23876 of file CommonMsr.h.

◆ MSR_SMRAM_RAX

#define MSR_SMRAM_RAX 0x00000C14

Available only in SMM.

SMRAM copy of RAX saved by SMI

Definition at line 23868 of file CommonMsr.h.

◆ MSR_SMRAM_RBP

#define MSR_SMRAM_RBP 0x00000C0F

Available only in SMM.

SMRAM copy of RBP saved by SMI

Definition at line 23848 of file CommonMsr.h.

◆ MSR_SMRAM_RBX

#define MSR_SMRAM_RBX 0x00000C11

Available only in SMM.

SMRAM copy of RBX saved by SMI

Definition at line 23856 of file CommonMsr.h.

◆ MSR_SMRAM_RCX

#define MSR_SMRAM_RCX 0x00000C13

Available only in SMM.

SMRAM copy of RCX saved by SMI

Definition at line 23864 of file CommonMsr.h.

◆ MSR_SMRAM_RDI

#define MSR_SMRAM_RDI 0x00000C0D

Available only in SMM.

SMRAM copy of RDI saved by SMI

Definition at line 23840 of file CommonMsr.h.

◆ MSR_SMRAM_RDX

#define MSR_SMRAM_RDX 0x00000C12

Available only in SMM.

SMRAM copy of RDX saved by SMI

Definition at line 23860 of file CommonMsr.h.

◆ MSR_SMRAM_RIP

#define MSR_SMRAM_RIP 0x00000C04

Available only in SMM.

SMRAM copy of RIP saved by SMI, introduced in HSW

Definition at line 23438 of file CommonMsr.h.

◆ MSR_SMRAM_RSI

#define MSR_SMRAM_RSI 0x00000C0E

Available only in SMM.

SMRAM copy of RSI saved by SMI

Definition at line 23844 of file CommonMsr.h.

◆ MSR_SMRAM_RSP

#define MSR_SMRAM_RSP 0x00000C10

Available only in SMM.

SMRAM copy of RSP saved by SMI

Definition at line 23852 of file CommonMsr.h.

◆ MSR_SMRAM_SMBASE

#define MSR_SMRAM_SMBASE 0x00000C20

Available only in SMM.

SMRAM copy of SMBASE saved by SMI

Definition at line 23943 of file CommonMsr.h.

◆ MSR_SMRAM_SMM_REVID

#define MSR_SMRAM_SMM_REVID 0x00000C21

Available only in SMM.

SMRAM copy of SMM_REVID saved by SMI

Definition at line 23971 of file CommonMsr.h.

◆ MSR_SMRAM_TR_LDTR

#define MSR_SMRAM_TR_LDTR 0x00000C07

Available only in SMM.

SMRAM copy of TR Sel and LDTR Sel saved by SMI

Definition at line 23657 of file CommonMsr.h.

◆ MSR_SOCKET_ID

#define MSR_SOCKET_ID 0x00000039

The SOCKET_ID MSR is used to reassign the package-specific portions of the APIC ID.

This MSR is intended only to be used on scalable DP and high-end MP platforms to resolve legacy-mode APIC ID conflicts.

Definition at line 499 of file CommonMsr.h.

◆ MSR_SW_LTR_OVRD

#define MSR_SW_LTR_OVRD 0x00000A02

This register is intended for OS usage.

It enables the OS to write an LTR value if they choose to participate in the LTR process. This register includes parameters that PCODE will use to override information received from PCI Express via LTR messages. Pcode will choose this value, or PCIE_LTR_OVRD, or actual LTR values from IIO depending on selection function in POWER_CTL uCR PCODE will sample this register at slow loop. This register needs to be exposed as MSR - details TBD

Definition at line 20621 of file CommonMsr.h.

◆ MSR_TCS_PA

#define MSR_TCS_PA 0x00000958

TCS Physical Address.

Pointer to TCS structure, to be used at ASEX

Definition at line 20042 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0

#define MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0 0x00001004

Spare Thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1004 to 0x1006"

Definition at line 28271 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1

#define MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1 0x00001005

Spare Thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1004 to 0x1006"

Definition at line 28276 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2

#define MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2 0x00001006

Spare Thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559 " seq has 3 instances in addresses range 0x1004 to 0x1006"

Definition at line 28281 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_0_0

#define MSR_THREAD_SPECIFIC_SPARE_0_0 0x00000142

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 2975 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_10_10

#define MSR_THREAD_SPECIFIC_SPARE_10_10 0x0000014C

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3025 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_11_11

#define MSR_THREAD_SPECIFIC_SPARE_11_11 0x0000014D

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3030 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_12_12

#define MSR_THREAD_SPECIFIC_SPARE_12_12 0x0000014E

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3035 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_13_13

#define MSR_THREAD_SPECIFIC_SPARE_13_13 0x0000014F

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3040 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_1_1

#define MSR_THREAD_SPECIFIC_SPARE_1_1 0x00000143

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 2980 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_2_2

#define MSR_THREAD_SPECIFIC_SPARE_2_2 0x00000144

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 2985 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_3_3

#define MSR_THREAD_SPECIFIC_SPARE_3_3 0x00000145

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 2990 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_4_4

#define MSR_THREAD_SPECIFIC_SPARE_4_4 0x00000146

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 2995 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_5_5

#define MSR_THREAD_SPECIFIC_SPARE_5_5 0x00000147

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3000 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_6_6

#define MSR_THREAD_SPECIFIC_SPARE_6_6 0x00000148

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3005 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_7_7

#define MSR_THREAD_SPECIFIC_SPARE_7_7 0x00000149

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3010 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_8_8

#define MSR_THREAD_SPECIFIC_SPARE_8_8 0x0000014A

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3015 of file CommonMsr.h.

◆ MSR_THREAD_SPECIFIC_SPARE_9_9

#define MSR_THREAD_SPECIFIC_SPARE_9_9 0x0000014B

Spare thread MSRs supported by the cregpla.

Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232 " seq has 14 instances in addresses range 0x142 to 0x14F"

Definition at line 3020 of file CommonMsr.h.

◆ MSR_TMPDR6

#define MSR_TMPDR6 0x00000902

Equivalent to architectural DR6 reg.

16 bit. (Mrm roctlregc/roctlregd/{tmpdr6lowSM306L|tmpdr6hiSM306L}) !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! !!! !!! !!! CAUTION: Adding more bits to this creg or changing the layout of this creg !!! !!! will require MSR ucode changes. Talk to MSR ucode owner (rpartha on NHM) if!!! !!! you want to make changes to this creg !!! !!! !!! !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

Definition at line 18073 of file CommonMsr.h.

◆ MSR_TURBO_ACTIVATION_RATIO

#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C

indicate the new maximum non-turbo ratio to be used by the processor.

Attempts to write to this MSR when the PLATFORM_INFO[34:33] ==0, may result in a GP fault#.

Definition at line 11379 of file CommonMsr.h.

◆ MSR_TURBO_RATIO_LIMIT_CORES

#define MSR_TURBO_RATIO_LIMIT_CORES 0x000001AE

This register defines the active core ranges for each frequency point NUMCORE[0:7] must be populated in ascending order.

NUMCORE[i+1] must be greater than NUMCORE[i] Entries with NUMCORE[i] == 0 will be ignored The last valid entry must have NUMCORE >= the number of cores in the SKU If any of the rules above are broken, we will silently reject the configuration.

Definition at line 4657 of file CommonMsr.h.

◆ MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR

#define MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR 0x0000070D

Address offset match value for Ubox match/mask.

Will compare bits that are not masked

Definition at line 14296 of file CommonMsr.h.

◆ MSR_VMCS_CACHE_BASE

#define MSR_VMCS_CACHE_BASE 0x00000933

PPPE will have read/write access to the FSCP_CR_VMCS_CACHE_BASE register for implementing the VMCS cache (i387450).

Can be cut to 32-bits if not used by PPPE

Definition at line 19180 of file CommonMsr.h.

◆ MSR_VR_CURRENT_CONFIG

#define MSR_VR_CURRENT_CONFIG 0x00000601

PL4 limit.

It is Icc limit on some power-delivery board element, mapped into W. It is proactive, instantaneous limit.

Definition at line 9452 of file CommonMsr.h.

◆ MSR_XU_MACROINSTRUCTION_ALIAS

#define MSR_XU_MACROINSTRUCTION_ALIAS 0x00000903

Millicode MSR used to read/write certain fields of the Macroalias register.

WRMSR will ignore the undefined bits (63:18, 14:13, 10, 6:2). WRMSR will not signal fault on any combination of bits, it is softwares responsiblity to make sure that values programmed this register are consistent and correct RDMSR will always return 0 in bits 63:18, 14:13, 10:9, 6:2. RDMSR will return the last value successfully updated by WRMSR

Definition at line 18156 of file CommonMsr.h.

◆ MSR_XU_RESERVED_10_10

#define MSR_XU_RESERVED_10_10 0x00000929

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19030 of file CommonMsr.h.

◆ MSR_XU_RESERVED_11_11

#define MSR_XU_RESERVED_11_11 0x0000092A

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19035 of file CommonMsr.h.

◆ MSR_XU_RESERVED_12_12

#define MSR_XU_RESERVED_12_12 0x0000092B

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19040 of file CommonMsr.h.

◆ MSR_XU_RESERVED_13_13

#define MSR_XU_RESERVED_13_13 0x0000092C

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19045 of file CommonMsr.h.

◆ MSR_XU_RESERVED_14_14

#define MSR_XU_RESERVED_14_14 0x0000092D

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19050 of file CommonMsr.h.

◆ MSR_XU_RESERVED_15_15

#define MSR_XU_RESERVED_15_15 0x0000092E

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19055 of file CommonMsr.h.

◆ MSR_XU_RESERVED_16_16

#define MSR_XU_RESERVED_16_16 0x00000930

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 3 instances in addresses range 0x930 to 0x932"

Definition at line 19164 of file CommonMsr.h.

◆ MSR_XU_RESERVED_17_17

#define MSR_XU_RESERVED_17_17 0x00000931

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 3 instances in addresses range 0x930 to 0x932"

Definition at line 19169 of file CommonMsr.h.

◆ MSR_XU_RESERVED_18_18

#define MSR_XU_RESERVED_18_18 0x00000932

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 3 instances in addresses range 0x930 to 0x932"

Definition at line 19174 of file CommonMsr.h.

◆ MSR_XU_RESERVED_19_19

#define MSR_XU_RESERVED_19_19 0x0000093B

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 1 instances in addresses range 0x93B to 0x93B"

Definition at line 19470 of file CommonMsr.h.

◆ MSR_XU_RESERVED_1_1

#define MSR_XU_RESERVED_1_1 0x00000917

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x917 to 0x91A"

Definition at line 18741 of file CommonMsr.h.

◆ MSR_XU_RESERVED_20_20

#define MSR_XU_RESERVED_20_20 0x0000093F

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 1 instances in addresses range 0x93F to 0x93F"

Definition at line 19481 of file CommonMsr.h.

◆ MSR_XU_RESERVED_21_21

#define MSR_XU_RESERVED_21_21 0x00000944

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19722 of file CommonMsr.h.

◆ MSR_XU_RESERVED_22_22

#define MSR_XU_RESERVED_22_22 0x00000945

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19727 of file CommonMsr.h.

◆ MSR_XU_RESERVED_23_23

#define MSR_XU_RESERVED_23_23 0x00000946

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19732 of file CommonMsr.h.

◆ MSR_XU_RESERVED_24_24

#define MSR_XU_RESERVED_24_24 0x00000947

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19737 of file CommonMsr.h.

◆ MSR_XU_RESERVED_25_25

#define MSR_XU_RESERVED_25_25 0x00000948

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19742 of file CommonMsr.h.

◆ MSR_XU_RESERVED_26_26

#define MSR_XU_RESERVED_26_26 0x00000949

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19747 of file CommonMsr.h.

◆ MSR_XU_RESERVED_27_27

#define MSR_XU_RESERVED_27_27 0x0000094A

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19752 of file CommonMsr.h.

◆ MSR_XU_RESERVED_28_28

#define MSR_XU_RESERVED_28_28 0x0000094B

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19757 of file CommonMsr.h.

◆ MSR_XU_RESERVED_29_29

#define MSR_XU_RESERVED_29_29 0x0000094C

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19762 of file CommonMsr.h.

◆ MSR_XU_RESERVED_2_2

#define MSR_XU_RESERVED_2_2 0x00000918

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x917 to 0x91A"

Definition at line 18746 of file CommonMsr.h.

◆ MSR_XU_RESERVED_30_30

#define MSR_XU_RESERVED_30_30 0x0000094D

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 10 instances in addresses range 0x944 to 0x94D"

Definition at line 19767 of file CommonMsr.h.

◆ MSR_XU_RESERVED_31_31

#define MSR_XU_RESERVED_31_31 0x00000967

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 1 instances in addresses range 0x967 to 0x967"

Definition at line 20311 of file CommonMsr.h.

◆ MSR_XU_RESERVED_3_3

#define MSR_XU_RESERVED_3_3 0x00000919

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x917 to 0x91A"

Definition at line 18751 of file CommonMsr.h.

◆ MSR_XU_RESERVED_4_4

#define MSR_XU_RESERVED_4_4 0x0000091A

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x917 to 0x91A"

Definition at line 18756 of file CommonMsr.h.

◆ MSR_XU_RESERVED_5_5

#define MSR_XU_RESERVED_5_5 0x0000091C

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x91C to 0x91F"

Definition at line 18765 of file CommonMsr.h.

◆ MSR_XU_RESERVED_6_6

#define MSR_XU_RESERVED_6_6 0x0000091D

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x91C to 0x91F"

Definition at line 18770 of file CommonMsr.h.

◆ MSR_XU_RESERVED_7_7

#define MSR_XU_RESERVED_7_7 0x0000091E

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x91C to 0x91F"

Definition at line 18775 of file CommonMsr.h.

◆ MSR_XU_RESERVED_8_8

#define MSR_XU_RESERVED_8_8 0x0000091F

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 4 instances in addresses range 0x91C to 0x91F"

Definition at line 18780 of file CommonMsr.h.

◆ MSR_XU_RESERVED_9_9

#define MSR_XU_RESERVED_9_9 0x00000928

This define is used to reserve some MSR addresses for XuCode.

Ucode would have a dedicated handler for these MSRs " seq has 7 instances in addresses range 0x928 to 0x92E"

Definition at line 19025 of file CommonMsr.h.

◆ MSR_XU_SMM_STATE

#define MSR_XU_SMM_STATE 0x00000908

Millicode MSR used to control SMM states WRMSR will ignore the undefined bits (63:32, 30:1).

RDMSR will always return 0 in bits 63:32, 30:1.

Definition at line 18331 of file CommonMsr.h.

◆ MSR_XUCODE_UCODE_COMMAND

#define MSR_XUCODE_UCODE_COMMAND 0x00000950

Each bit is command from xucode for specific action.

Not really a register.

Definition at line 19819 of file CommonMsr.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CommonMsr.h Source File

Intel

ClientOneSiliconPkg

Cpu

Include

Register

CommonMsr.h

Go to the documentation of this file.

1

2 /** @file

3 CommonMsr.h

4

5 @copyright

6 INTEL CONFIDENTIAL

7 Copyright 2019 - 2020 Intel Corporation.

8

9 The source code contained or described herein and all documents related to the

10 source code ("Material") are owned by Intel Corporation or its suppliers or

11 licensors. Title to the Material remains with Intel Corporation or its suppliers

12 and licensors. The Material may contain trade secrets and proprietary and

13 confidential information of Intel Corporation and its suppliers and licensors,

14 and is protected by worldwide copyright and trade secret laws and treaty

15 provisions. No part of the Material may be used, copied, reproduced, modified,

16 published, uploaded, posted, transmitted, distributed, or disclosed in any way

17 without Intel's prior express written permission.

18

19 No license under any patent, copyright, trade secret or other intellectual

20 property right is granted to or conferred upon you by disclosure or delivery

21 of the Materials, either expressly, by implication, inducement, estoppel or

22 otherwise. Any license under such intellectual property rights must be

23 express and approved by Intel in writing.

24

25 Unless otherwise agreed by Intel in writing, you may not remove or alter

26 this notice or any other notice embedded in Materials by Intel or

27 Intel's suppliers or licensors in any way.

28

29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as

30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under

31 the terms of your license agreement with Intel or your vendor. This file may

32 be modified by the user, subject to additional terms of the license agreement.

33

34 @par Specification Reference:

35 **/

36

37 #ifndef _COMMONMSR_h

38 #define _COMMONMSR_h

39 #include <Base.h>

40 /**

41

42 **/

43 #define MSR_ACM_CPU_KEY_HASH_0 0x00000020

44 /**

45

46 **/

47 #define MSR_ACM_CPU_KEY_HASH_1 0x00000021

48 /**

49

50 **/

51 #define MSR_ACM_CPU_KEY_HASH_2 0x00000022

52 /**

53

54 **/

55 #define MSR_ACM_CPU_KEY_HASH_3 0x00000023

56 /**

57 MSR read by Sandra and HotCPU test. Added to prevent these benchmarks from crashing. See NHM-B bug 2425276

58 **/

59 #define MSR_POWERON 0x0000002A

60

61 /**

62 Enhanced MCA Thread error injection control

63 **/

64 #define MSR_THREAD_SMI_ERR_INJ_CONTROL 0x0000002B

65

66 typedef union {

67 ///

68 /// Individual bit fields

69 ///

70 struct {

71 UINT32 Ifu : 1;

72

73 /* Bits[0:0], Access Type=RW, default=0x00000000*/

74

75 /* */

76 UINT32 Dcu : 1;

77

78 /* Bits[1:1], Access Type=RW, default=0x00000000*/

79

80 /* */

81 UINT32 Rsvd2 : 30;

82

83 /* Bits[31:2], Access Type=RO, default=None*/

84

85 /* Reserved */

86 UINT32 Rsvd32 : 32;

87

88 /* Bits[63:32], Access Type=RO, default=None*/

89

90 /* Reserved */

91

92 } Bits;

93

94 UINT32 Uint32;

95 UINT64 Uint64;

96

97 } MSR_THREAD_SMI_ERR_INJ_CONTROL_REGISTER;

98

99 /**

100 Enhanced MCA Core error injection control

101 **/

102 #define MSR_CORE_SMI_ERR_INJ_CONTROL 0x0000002C

103

104 typedef union {

105 ///

106 /// Individual bit fields

107 ///

108 struct {

109 UINT32 Rsvd0 : 2;

110

111 /* Bits[1:0], Access Type=RW, default=0x00000000*/

112

113 /* */

114 UINT32 Dtlb : 1;

115

116 /* Bits[2:2], Access Type=RW, default=0x00000000*/

117

118 /* */

119 UINT32 Mlc : 1;

120

121 /* Bits[3:3], Access Type=RW, default=0x00000000*/

122

123 /* */

124 UINT32 Rsvd4 : 28;

125

126 /* Bits[31:4], Access Type=RO, default=None*/

127

128 /* Reserved */

129 UINT32 Rsvd32 : 32;

130

131 /* Bits[63:32], Access Type=RO, default=None*/

132

133 /* Reserved */

134

135 } Bits;

136

137 UINT32 Uint32;

138 UINT64 Uint64;

139

140 } MSR_CORE_SMI_ERR_INJ_CONTROL_REGISTER;

141

142 /**

143 Enhanced MCA Uncore error injection control

144 **/

145 #define MSR_UNCORE_SMI_ERR_INJ_CONTROL 0x0000002D

146

147 typedef union {

148 ///

149 /// Individual bit fields

150 ///

151 struct {

152 UINT32 Rsvd0 : 4;

153

154 /* Bits[3:0], Access Type=RO, default=None*/

155

156 /* Reserved */

157 UINT32 McaBankId4 : 1;

158

159 /* Bits[4:4], Access Type=RW, default=0x00000000*/

160

161 /* */

162 UINT32 McaBankId5 : 1;

163

164 /* Bits[5:5], Access Type=RW, default=0x00000000*/

165

166 /* */

167 UINT32 McaBankId6 : 1;

168

169 /* Bits[6:6], Access Type=RW, default=0x00000000*/

170

171 /* */

172 UINT32 McaBankId7 : 1;

173

174 /* Bits[7:7], Access Type=RW, default=0x00000000*/

175

176 /* */

177 UINT32 McaBankId8 : 1;

178

179 /* Bits[8:8], Access Type=RW, default=0x00000000*/

180

181 /* */

182 UINT32 McaBankId9 : 1;

183

184 /* Bits[9:9], Access Type=RW, default=0x00000000*/

185

186 /* */

187 UINT32 McaBankId10 : 1;

188

189 /* Bits[10:10], Access Type=RW, default=0x00000000*/

190

191 /* */

192 UINT32 McaBankId11 : 1;

193

194 /* Bits[11:11], Access Type=RW, default=0x00000000*/

195

196 /* */

197 UINT32 McaBankId12 : 1;

198

199 /* Bits[12:12], Access Type=RW, default=0x00000000*/

200

201 /* */

202 UINT32 McaBankId13 : 1;

203

204 /* Bits[13:13], Access Type=RW, default=0x00000000*/

205

206 /* */

207 UINT32 McaBankId14 : 1;

208

209 /* Bits[14:14], Access Type=RW, default=0x00000000*/

210

211 /* */

212 UINT32 McaBankId15 : 1;

213

214 /* Bits[15:15], Access Type=RW, default=0x00000000*/

215

216 /* */

217 UINT32 McaBankId16 : 1;

218

219 /* Bits[16:16], Access Type=RW, default=0x00000000*/

220

221 /* */

222 UINT32 McaBankId17 : 1;

223

224 /* Bits[17:17], Access Type=RW, default=0x00000000*/

225

226 /* */

227 UINT32 McaBankId18 : 1;

228

229 /* Bits[18:18], Access Type=RW, default=0x00000000*/

230

231 /* */

232 UINT32 McaBankId19 : 1;

233

234 /* Bits[19:19], Access Type=RW, default=0x00000000*/

235

236 /* */

237 UINT32 McaBankId20 : 1;

238

239 /* Bits[20:20], Access Type=RW, default=0x00000000*/

240

241 /* */

242 UINT32 McaBankId21 : 1;

243

244 /* Bits[21:21], Access Type=RW, default=0x00000000*/

245

246 /* */

247 UINT32 McaBankId22 : 1;

248

249 /* Bits[22:22], Access Type=RW, default=0x00000000*/

250

251 /* */

252 UINT32 McaBankId23 : 1;

253

254 /* Bits[23:23], Access Type=RW, default=0x00000000*/

255

256 /* */

257 UINT32 McaBankId24 : 1;

258

259 /* Bits[24:24], Access Type=RW, default=0x00000000*/

260

261 /* */

262 UINT32 McaBankId25 : 1;

263

264 /* Bits[25:25], Access Type=RW, default=0x00000000*/

265

266 /* */

267 UINT32 McaBankId26 : 1;

268

269 /* Bits[26:26], Access Type=RW, default=0x00000000*/

270

271 /* */

272 UINT32 McaBankId27 : 1;

273

274 /* Bits[27:27], Access Type=RW, default=0x00000000*/

275

276 /* */

277 UINT32 McaBankId28 : 1;

278

279 /* Bits[28:28], Access Type=RW, default=0x00000000*/

280

281 /* */

282 UINT32 McaBankId29 : 1;

283

284 /* Bits[29:29], Access Type=RW, default=0x00000000*/

285

286 /* */

287 UINT32 McaBankId30 : 1;

288

289 /* Bits[30:30], Access Type=RW, default=0x00000000*/

290

291 /* */

292 UINT32 McaBankId31 : 1;

293

294 /* Bits[31:31], Access Type=RW, default=0x00000000*/

295

296 /* */

297 UINT32 Rsvd32 : 32;

298

299 /* Bits[63:32], Access Type=RO, default=None*/

300

301 /* Reserved */

302

303 } Bits;

304

305 UINT32 Uint32;

306 UINT64 Uint64;

307

308 } MSR_UNCORE_SMI_ERR_INJ_CONTROL_REGISTER;

309

310 /**

311 MSR used to control APIC TPR Update messages from the processor's Local APIC.

312 **/

313 #define MSR_PIC_MSG_CONTROL 0x0000002E

314

315 typedef union {

316 ///

317 /// Individual bit fields

318 ///

319 struct {

320 UINT32 Rsvd0 : 10;

321

322 /* Bits[9:0], Access Type=RO, default=None*/

323

324 /* Reserved */

325 UINT32 TprMsgOff : 1;

326

327 /* Bits[10:10], Access Type=RW, default=None*/

328

329 /*

330 When set to 1 (which is the default at reset),

331 no APIC messages (TPR updates) will be sent.

332 When set to 0, APIC messages (TPR updates) will

333 be sent. Writes from 1 to 0 are allowed, but

334 writes of 1 are ignored. BIOS must write 0 to

335 this bit for each thread in each package before

336 any Local APIC mode changes occur. Note: If BIOS

337 does not clear this bit, OS initialization of

338 interrupts will fail.

339 */

340 UINT32 Rsvd11 : 21;

341

342 /* Bits[31:11], Access Type=RO, default=None*/

343

344 /* Reserved */

345

346 } Bits;

347

348 UINT32 Uint32;

349 UINT64 Uint64;

350

351 } MSR_PIC_MSG_CONTROL_REGISTER;

352

353 /**

354 MSR used to select the mode for the Data Cache Unit (DCU). This MSR is only available when more than one DCU Mode is selectable and is only intended for use in early BIOS before the first transition of the CR0.CD from 1 to 0.

355 **/

356 #define MSR_DCU_MODE_CONTROL 0x00000031

357

358 typedef union {

359 ///

360 /// Individual bit fields

361 ///

362 struct {

363 UINT32 EnableDcu16kMode : 1;

364

365 /* Bits[0:0], Access Type=RW, default=0x00000000*/

366

367 /*

368 When read as 0 (default), the DCU Mode is 32-KB

369 8-way without ECC. When read as 1, the BIOS has

370 changed the DCU mode to 16-KB 4-way with ECC. If

371 the DCU Mode is 0 and the first transition of

372 the CR0.CD bit from 1 to 0 has not occurred by

373 either thread in this core, then a write of 1

374 selects the DCU mode as 16-KB 4-way with ECC.

375 After the first write, all further writes are

376 ignored.

377 */

378 UINT32 Rsvd1 : 31;

379

380 /* Bits[31:1], Access Type=RO, default=None*/

381

382 /* Reserved */

383 UINT32 Rsvd32 : 32;

384

385 /* Bits[63:32], Access Type=RO, default=None*/

386

387 /* Reserved */

388

389 } Bits;

390

391 UINT32 Uint32;

392 UINT64 Uint64;

393

394 } MSR_DCU_MODE_CONTROL_REGISTER;

395

396 /**

397 Register to disable split locks, which are locked instructions that split a cache line.

398 **/

399 #define MSR_MEMORY_CONTROL 0x00000033

400

401 typedef union {

402 ///

403 /// Individual bit fields

404 ///

405 struct {

406 UINT32 Rsvd0 : 29;

407

408 /* Bits[28:0], Access Type=RO, default=None*/

409

410 /* Reserved */

411 UINT32 SplitLockDisable : 1;

412

413 /* Bits[29:29], Access Type=RW, default=0x00000000*/

414

415 /*

416 If set to 1, a split lock will trigger an #AC

417 fault. If clear to 0, split locks proceed

418 normally (subjected to the SUPPRESS_SPLIT_LOCK

419 behavior. If both this bit and

420 SUPPRESS_SPLIT_LOCK are set, then only this bit

421 will be honored (has priority).

422 */

423 UINT32 Rsvd30 : 1;

424

425 /* Bits[30:30], Access Type=RO, default=None*/

426

427 /* Reserved */

428 UINT32 SuppressSplitLock : 1;

429

430 /* Bits[31:31], Access Type=RW, default=0x00000000*/

431

432 /*

433 If set to 1, disables split locks. If clear to

434 0, enables split locks. Setting this bit will

435 cause split locks to be non-atomic, despite the

436 lock attribute of the instruction.

437 */

438

439 } Bits;

440

441 UINT32 Uint32;

442 UINT64 Uint64;

443

444 } MSR_MEMORY_CONTROL_REGISTER;

445 /**

446 Keeps a running count of SMI events

447 **/

448 #define MSR_SMI_COUNT 0x00000034

449

450 /**

451 This is a Read Only MSR that is shared in the processor package and used to

452 determine the current count of enabled Cores and Threads.

453 **/

454 #define MSR_CORE_THREAD_COUNT 0x00000035

455

456 typedef union {

457 ///

458 /// Individual bit fields

459 ///

460 struct {

461 UINT32 Threadcount : 16;

462

463 /* Bits[15:0], Access Type=RO_V, default=None*/

464

465 /*

466 The Thread Count reflects the enabled threads

467 based on the factory-configured thread count and

468 the value of the RESOLVED_CORES_MASK register

469 for Server processors or the PCH Soft Reset Data

470 register for Client processors at reset time.

471 */

472 UINT32 Corecount : 16;

473

474 /* Bits[31:16], Access Type=RO_V, default=None*/

475

476 /*

477 The Core Count reflects the enabled cores based

478 on the factory-configured core count and the

479 value of the RESOLVED_CORES_MASK register for

480 Server processors or the PCH Soft Reset Data

481 register for Client processors at reset time.

482 */

483 UINT32 Rsvd32 : 32;

484

485 /* Bits[63:32], Access Type=RO, default=None*/

486

487 /* Reserved */

488

489 } Bits;

490

491 UINT32 Uint32;

492 UINT64 Uint64;

493

494 } MSR_CORE_THREAD_COUNT_REGISTER;

495

496 /**

497 The SOCKET_ID MSR is used to reassign the package-specific portions of the APIC ID. This MSR is intended only to be used on scalable DP and high-end MP platforms to resolve legacy-mode APIC ID conflicts.

498 **/

499 #define MSR_SOCKET_ID 0x00000039

500

501 typedef union {

502 ///

503 /// Individual bit fields

504 ///

505 struct {

506 UINT32 PackageId : 11;

507

508 /* Bits[10:0], Access Type=RO_V, default=None*/

509

510 /*

511 Holds package ID. This reflects the upper 8 bits

512 of the APIC ID

513 */

514 UINT32 Rsvd11 : 21;

515

516 /* Bits[31:11], Access Type=RO, default=None*/

517

518 /* Reserved */

519

520 } Bits;

521

522 UINT32 Uint32;

523 UINT64 Uint64;

524

525 } MSR_SOCKET_ID_REGISTER;

526

527 /**

528 Contains bits that determine what additional state SMI/RSM must save and restore

529 FSCP Crunch - 1:32

530 **/

531 #define MSR_SMM_SAVE_CONTROL 0x0000003E

532

533 typedef union {

534 ///

535 /// Individual bit fields

536 ///

537 struct {

538 UINT32 SaveFpState : 1;

539

540 /* Bits[0:0], Access Type=RW, default=None*/

541

542 /* If set, SMI/RSM will save/restore FP state */

543 UINT32 Reserved1 : 31;

544

545 /* Bits[31:1], Access Type=RW, default=None*/

546

547 /* Unallocated bits */

548

549 } Bits;

550

551 UINT32 Uint32;

552 UINT64 Uint64;

553

554 } MSR_SMM_SAVE_CONTROL_REGISTER;

555

556 /**

557 MSR for PPIN feature

558 **/

559 #define MSR_PPIN_CTL 0x0000004E

560

561 typedef union {

562 ///

563 /// Individual bit fields

564 ///

565 struct {

566 UINT32 Lock : 1;

567

568 /* Bits[0:0], Access Type=RW, default=0x00000000*/

569

570 /*

571 Bit indicates if PPIN_CTL is locked 0 - Not

572 locked (SW free to write to PPIN_CTL) 1 - Locked

573 (SW can no longer write to PPIN_CTL).

574 */

575 UINT32 Enable : 1;

576

577 /* Bits[1:1], Access Type=RW, default=0x00000000*/

578

579 /*

580 Indication to SW about presence of PPIN 0 - PPIN

581 not present. Read of PPIN MSR would #GP 1 - PPIN

582 present. Read of PPIN MSR by SW allowed.

583 */

584 UINT32 Rsvd2 : 30;

585

586 /* Bits[31:2], Access Type=RO, default=None*/

587

588 /* Reserved */

589 UINT32 Rsvd32 : 32;

590

591 /* Bits[63:32], Access Type=RO, default=None*/

592

593 /* Reserved */

594

595 } Bits;

596

597 UINT32 Uint32;

598 UINT64 Uint64;

599

600 } MSR_PPIN_CTL_REGISTER;

601 /**

602 PPIN value

603 **/

604 #define MSR_PPIN 0x0000004F

605

606 /**

607 MSR that is used to initiate quiesce and unquiesce of CSI links

608 **/

609 #define MSR_QUIESCE_CTL1 0x00000050

610

611 typedef union {

612 ///

613 /// Individual bit fields

614 ///

615 struct {

616 UINT32 Quiesce : 1;

617

618 /* Bits[0:0], Access Type=RW, default=0x00000000*/

619

620 /* 1 = quiesce initiated */

621 UINT32 Unquiesce : 1;

622

623 /* Bits[1:1], Access Type=RW, default=0x00000000*/

624

625 /* 1 = unquiesce initiated */

626 UINT32 CboEvictionsDrain : 1;

627

628 /* Bits[2:2], Access Type=RW, default=0x00000000*/

629

630 /*

631 This bit will be updated in RDMSR flow Value 1 =

632 Victim pending bit in uCR is set Value 0 =

633 Victim pending bit in uCR is not set

634 */

635 UINT32 Rsvd3 : 4;

636

637 /* Bits[6:3], Access Type=RO, default=None*/

638

639 /* Reserved */

640 UINT32 QuiesceCapability : 1;

641

642 /* Bits[7:7], Access Type=RW, default=0x00000000*/

643

644 /*

645 1 = quiesce feature enabled; 0 = quiesce feature

646 not enabled. This is a read only bit that is

647 updated in RDMSR flow.

648 */

649 UINT32 RsvdPsmi8 : 8;

650

651 /* Bits[15:8], Access Type=RW, default=0x00000000*/

652

653 /* Reserved for PSMI handshake */

654 UINT32 RsvdDca16 : 6;

655

656 /* Bits[21:16], Access Type=RW, default=0x00000000*/

657

658 /* Reserved for storing DCA info */

659 UINT32 DisableitlbSpecfillSave : 1;

660

661 /* Bits[22:22], Access Type=RW, default=0x00000000*/

662

663 /*

664 Used to save/restore

665 IFU_CR_DEBUG_MODE[DISABLEITLB_SPECFILL]. See HSX

666 bug 233740.

667 */

668 UINT32 Rsvd23 : 9;

669

670 /* Bits[31:23], Access Type=RO, default=None*/

671

672 /* Reserved */

673 UINT32 Rsvd32 : 32;

674

675 /* Bits[63:32], Access Type=RO, default=None*/

676

677 /* Reserved */

678

679 } Bits;

680

681 UINT32 Uint32;

682 UINT64 Uint64;

683

684 } MSR_QUIESCE_CTL1_REGISTER;

685

686 /**

687 MSR that is used for PSMI handshake before initiating a RAS quiesce

688 **/

689 #define MSR_QUIESCE_CTL2 0x00000051

690

691 typedef union {

692 ///

693 /// Individual bit fields

694 ///

695 struct {

696 UINT32 SignalHandshake : 1;

697

698 /* Bits[0:0], Access Type=RW, default=0x00000000*/

699

700 /* 1 = signal a psmi event as a handshake */

701 UINT32 Rsvd1 : 31;

702

703 /* Bits[31:1], Access Type=RO, default=None*/

704

705 /* Reserved */

706 UINT32 Rsvd32 : 32;

707

708 /* Bits[63:32], Access Type=RO, default=None*/

709

710 /* Reserved */

711

712 } Bits;

713

714 UINT32 Uint32;

715 UINT64 Uint64;

716

717 } MSR_QUIESCE_CTL2_REGISTER;

718

719 /**

720 Cloaking error Virtual MSR in core Creg PLA

721 **/

722 #define MSR_CLOAKING 0x00000052

723

724 typedef union {

725 ///

726 /// Individual bit fields

727 ///

728 struct {

729 UINT32 CerrRdStatusInSmmOnly : 1;

730

731 /* Bits[0:0], Access Type=RW, default=0x00000000*/

732

733 /*

734 When 0 (default), legacy rdmsr behavior is

735 maintained for MCi_STATUS registers. When set to

736 1, a rdmsr to any MCi_STATUS register will

737 return 0 while a corrected error is logged in

738 the register unless the processor is in SMM mode

739 */

740 UINT32 UcnaRdStatusInSmmOnly : 1;

741

742 /* Bits[1:1], Access Type=RW, default=0x00000000*/

743

744 /*

745 When 0 (default), legacy rdmsr and wrmsr

746 behavior is maintained for register. When set to

747 1, a rdmsr to any MCi_STATUS register will

748 return 0 while a UCNA error is logged in the

749 register unless the processor is in SMM mode.

750 */

751 UINT32 DualSignalSmi : 1;

752

753 /* Bits[2:2], Access Type=RW, default=0x00000000*/

754

755 /*

756 Enable SMI when MCA is set. This feature is part

757 of Enhanced MCA Gen 1 that enables the silicon

758 to issue SMI to the local cores along with

759 MCError. The silicon manages timing of SMI/MCE

760 so that the SMI handler is invoked early in

761 Int18 process.

762 */

763 UINT32 Rsvd3 : 29;

764

765 /* Bits[31:3], Access Type=RO, default=None*/

766

767 /* Reserved */

768

769 } Bits;

770

771 UINT32 Uint32;

772 UINT64 Uint64;

773

774 } MSR_CLOAKING_REGISTER;

775

776 /**

777 Spare Virtual MSRs in uncore Creg PLA

778 **/

779 #define MSR_THD_LOGICAL_ID 0x00000053

780

781 typedef union {

782 ///

783 /// Individual bit fields

784 ///

785 struct {

786 UINT32 LogicalId : 8;

787

788 /* Bits[7:0], Access Type=RW, default=0x00000000*/

789

790 /* Core and Thread ID */

791 UINT32 Rsvd8 : 24;

792

793 /* Bits[31:8], Access Type=RO, default=None*/

794

795 /* Reserved */

796

797 } Bits;

798

799 UINT32 Uint32;

800 UINT64 Uint64;

801

802 } MSR_THD_LOGICAL_ID_REGISTER;

803

804 /**

805 This MSR clars smi

806 **/

807 #define MSR_SMM_CLEAR_SMI 0x00000057

808

809 typedef union {

810 ///

811 /// Individual bit fields

812 ///

813 struct {

814 UINT32 ClearSmi : 1;

815

816 /* Bits[0:0], Access Type=RW, default=None*/

817

818 /*

819 This field when set clears the SMI bit in

820 ML3_CR_PIC_EVENT_STATUS register

821 */

822 UINT32 MsmiToMceEn : 1;

823

824 /* Bits[1:1], Access Type=RW, default=None*/

825

826 /*

827 Write of 1 will enable MSMI to MCE morphing,

828 Writes of 0 will disable MSMI to MCE morphing

829 */

830 UINT32 Rsvd2 : 30;

831

832 /* Bits[31:2], Access Type=RO, default=None*/

833

834 /* Reserved */

835

836 } Bits;

837

838 UINT32 Uint32;

839 UINT64 Uint64;

840

841 } MSR_SMM_CLEAR_SMI_REGISTER;

842

843 /**

844 This MSR reads/writes bit 0 in smm_cfg_options fscp

845 **/

846 #define MSR_SMM_CFG_OPTIONS 0x00000058

847

848 typedef union {

849 ///

850 /// Individual bit fields

851 ///

852 struct {

853 UINT32 CfgOption : 1;

854

855 /* Bits[0:0], Access Type=RW, default=None*/

856

857 /*

858 This field updates bit 0 in

859 FSCP_CR_SMM_CFG_OPTIONS_ADDR

860 */

861 UINT32 Rsvd1 : 31;

862

863 /* Bits[31:1], Access Type=RO, default=None*/

864

865 /* Reserved */

866

867 } Bits;

868

869 UINT32 Uint32;

870 UINT64 Uint64;

871

872 } MSR_SMM_CFG_OPTIONS_REGISTER;

873

874 /**

875 This register provides support for the Firmware-First-Mode thermal interrup feature.

876 **/

877 #define MSR_THERM_EVENT_FFM 0x0000005E

878

879 typedef union {

880 ///

881 /// Individual bit fields

882 ///

883 struct {

884 UINT32 EnableFfm : 1;

885

886 /* Bits[0:0], Access Type=RW, default=0x00000000*/

887

888 /*

889 Can be set by BIOS in SMM only. When set,

890 instead of delivering a thermal interrupt to

891 core PCU FW must send an SMI.

892 */

893 UINT32 FfmSmiSignaled : 1;

894

895 /* Bits[1:1], Access Type=RW0C, default=0x00000000*/

896

897 /*

898 BIOS in SMM mode is responsible for checking

899 this bit to determine if the origin of the SMI

900 is from a thermal event or not. When set, the

901 interrupt is thermal related and BIOS must read

902 the thermal status registers to determine which

903 cores to send an IPI to. PCU FW will read this

904 bit before sending a thermal related SMI. If the

905 bit is set it will not deliver another

906 interrupt. BIOS must clear this bit when it is

907 ready to receive another interrupt.

908 */

909 UINT32 Rsvd2 : 30;

910

911 /* Bits[31:2], Access Type=RO, default=None*/

912

913 /* Reserved */

914

915 } Bits;

916

917 UINT32 Uint32;

918 UINT64 Uint64;

919

920 } MSR_THERM_EVENT_FFM_REGISTER;

921

922 /**

923 Shutdown supression feature

924 **/

925 #define MSR_SUPPRESS_SHUTDOWN 0x00000060

926

927 typedef union {

928 ///

929 /// Individual bit fields

930 ///

931 struct {

932 UINT32 SuppressShutdownAndLogmcaIerr : 1;

933

934 /* Bits[0:0], Access Type=RW, default=0x00000000*/

935

936 /*

937 suppress shutdown spc cycle and send ierr with

938 logging

939 */

940 UINT32 ShutdownLogmcaIerr : 1;

941

942 /* Bits[1:1], Access Type=RW, default=0x00000000*/

943

944 /* trigger ierr and log errors for shutdown cycle */

945 UINT32 Rsvd2 : 30;

946

947 /* Bits[31:2], Access Type=RO, default=None*/

948

949 /* Reserved */

950 UINT32 Rsvd32 : 32;

951

952 /* Bits[63:32], Access Type=RO, default=None*/

953

954 /* Reserved */

955

956 } Bits;

957

958 UINT32 Uint32;

959 UINT64 Uint64;

960

961 } MSR_SUPPRESS_SHUTDOWN_REGISTER;

962

963 /**

964 This MSR reads/writes CBO_CR_CBO_COH_CONFIG[0]. SKX bug 305692

965 **/

966 #define MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN 0x00000061

967

968 typedef union {

969 ///

970 /// Individual bit fields

971 ///

972 struct {

973 UINT32 McaNonnemCacheableMmioEn : 1;

974

975 /* Bits[0:0], Access Type=RW, default=None*/

976

977 /*

978 This bit when set enables MCA on nonnem

979 cacheable MMIO

980 */

981 UINT32 Rsvd1 : 31;

982

983 /* Bits[31:1], Access Type=RO, default=None*/

984

985 /* Reserved */

986

987 } Bits;

988

989 UINT32 Uint32;

990 UINT64 Uint64;

991

992 } MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN_REGISTER;

993

994 /**

995 command reg in ACE IP

996 **/

997 #define MSR_ACE_SPI_COMMAND 0x00000062

998

999 typedef union {

1000 ///

1001 /// Individual bit fields

1002 ///

1003 struct {

1004 UINT32 Start : 1;

1005

1006 /* Bits[0:0], Access Type=RW, default=0x00000000*/

1007

1008 /* set to trigger SPI txn */

1009 UINT32 AddrSize12 : 1;

1010

1011 /* Bits[1:1], Access Type=RW, default=0x00000000*/

1012

1013 /* num of addr bytes */

1014 UINT32 AddrSize34 : 1;

1015

1016 /* Bits[2:2], Access Type=RW, default=0x00000000*/

1017

1018 /* num of addr bytes */

1019 UINT32 SoftRst : 1;

1020

1021 /* Bits[3:3], Access Type=RW, default=0x00000000*/

1022

1023 /* soft reset if *code detects a SPI hang */

1024 UINT32 AddrPhase : 1;

1025

1026 /* Bits[4:4], Access Type=RW, default=0x00000000*/

1027

1028 /* 1: addr phase present */

1029 UINT32 Abort : 1;

1030

1031 /* Bits[5:5], Access Type=RW, default=0x00000000*/

1032

1033 /* abort phase */

1034 UINT32 FreezeSpi : 1;

1035

1036 /* Bits[6:6], Access Type=RW, default=0x00000000*/

1037

1038 /* 1:frz present, 0: absent */

1039 UINT32 DummyPhase : 1;

1040

1041 /* Bits[7:7], Access Type=RW, default=0x00000000*/

1042

1043 /* 1:present, 0:absent */

1044 UINT32 DummyCycles : 4;

1045

1046 /* Bits[11:8], Access Type=RW, default=0x00000000*/

1047

1048 /* num of dummy cycles */

1049 UINT32 DataPhase : 1;

1050

1051 /* Bits[12:12], Access Type=RW, default=0x00000000*/

1052

1053 /* 1:present, 0:absent */

1054 UINT32 ReadWriteb : 1;

1055

1056 /* Bits[13:13], Access Type=RW, default=0x00000000*/

1057

1058 /* 1: read, 0:write */

1059 UINT32 Dual : 1;

1060

1061 /* Bits[14:14], Access Type=RW, default=0x00000000*/

1062

1063 /* SPI dual mode */

1064 UINT32 Quad : 1;

1065

1066 /* Bits[15:15], Access Type=RW, default=0x00000000*/

1067

1068 /* SPI quad mode */

1069 UINT32 TxnDataSize : 8;

1070

1071 /* Bits[23:16], Access Type=RW, default=0x00000000*/

1072

1073 /* txn data size */

1074 UINT32 Opcode : 8;

1075

1076 /* Bits[31:24], Access Type=RW, default=0x00000000*/

1077

1078 /* txn data size */

1079 UINT32 Address : 32;

1080

1081 /* Bits[63:32], Access Type=RW, default=0x00000000*/

1082

1083 /* address */

1084

1085 } Bits;

1086

1087 UINT32 Uint32;

1088 UINT64 Uint64;

1089

1090 } MSR_ACE_SPI_COMMAND_REGISTER;

1091 /**

1092 command reg in ACE IP

1093 **/

1094 #define MSR_ACE_SPI_DATA 0x00000063

1095

1096 /**

1097 status reg in ACE IP

1098 **/

1099 #define MSR_ACE_SPI_STATUS 0x00000064

1100

1101 typedef union {

1102 ///

1103 /// Individual bit fields

1104 ///

1105 struct {

1106 UINT32 Busy : 1;

1107

1108 /* Bits[0:0], Access Type=RO, default=0x00000000*/

1109

1110 /* 1:busy, 0:idle */

1111 UINT32 Error : 1;

1112

1113 /* Bits[1:1], Access Type=RO, default=0x00000000*/

1114

1115 /* 1:error, 0: no error */

1116 UINT32 Empty : 1;

1117

1118 /* Bits[2:2], Access Type=RW, default=0x00000000*/

1119

1120 /* indicates SPI buffer is empty */

1121 UINT32 Full : 1;

1122

1123 /* Bits[3:3], Access Type=RW, default=0x00000000*/

1124

1125 /* indicates SPI buffer is full */

1126 UINT32 Rsvd4 : 28;

1127

1128 /* Bits[31:4], Access Type=RW, default=0x00000000*/

1129

1130 /* data field */

1131 UINT32 Rsvd32 : 32;

1132

1133 /* Bits[63:32], Access Type=RW, default=0x00000000*/

1134

1135 /* data field */

1136

1137 } Bits;

1138

1139 UINT32 Uint32;

1140 UINT64 Uint64;

1141

1142 } MSR_ACE_SPI_STATUS_REGISTER;

1143

1144 /**

1145 config reg in ACE IP

1146 **/

1147 #define MSR_ACE_SPI_CONFIG 0x00000065

1148

1149 typedef union {

1150 ///

1151 /// Individual bit fields

1152 ///

1153 struct {

1154 UINT32 ClkLow : 5;

1155

1156 /* Bits[4:0], Access Type=RW, default=0x00000000*/

1157

1158 /* clk low */

1159 UINT32 ClkHigh : 5;

1160

1161 /* Bits[9:5], Access Type=RW, default=0x00000000*/

1162

1163 /* clk hi */

1164 UINT32 Drive : 5;

1165

1166 /* Bits[14:10], Access Type=RW, default=0x00000000*/

1167

1168 /* drive */

1169 UINT32 Sample : 5;

1170

1171 /* Bits[19:15], Access Type=RW, default=0x00000000*/

1172

1173 /* sample */

1174 UINT32 Rsvd20 : 12;

1175

1176 /* Bits[31:20], Access Type=RW, default=0x00000000*/

1177

1178 /* reserved */

1179 UINT32 Rsvd32 : 32;

1180

1181 /* Bits[63:32], Access Type=RW, default=0x00000000*/

1182

1183 /* reserved */

1184

1185 } Bits;

1186

1187 UINT32 Uint32;

1188 UINT64 Uint64;

1189

1190 } MSR_ACE_SPI_CONFIG_REGISTER;

1191

1192 /**

1193 Used to exit out of PFR VCM. Write only command MSR. Read will #GP

1194 **/

1195 #define MSR_PFR_EXIT 0x00000066

1196

1197 typedef union {

1198 ///

1199 /// Individual bit fields

1200 ///

1201 struct {

1202 UINT32 Rsvd0 : 1;

1203

1204 /* Bits[0:0], Access Type=RW, default=0x00000000*/

1205

1206 /* dummy */

1207 UINT32 Rsvd1 : 31;

1208

1209 /* Bits[31:1], Access Type=RO, default=None*/

1210

1211 /* Reserved */

1212 UINT32 Rsvd32 : 32;

1213

1214 /* Bits[63:32], Access Type=RO, default=None*/

1215

1216 /* Reserved */

1217

1218 } Bits;

1219

1220 UINT32 Uint32;

1221 UINT64 Uint64;

1222

1223 } MSR_PFR_EXIT_REGISTER;

1224 /**

1225 MSR to provision VCM key hash to CPU

1226 **/

1227 #define MSR_PFR_VCM_PROVISION 0x00000067

1228

1229 /**

1230 MSR to read PFR provision status

1231 **/

1232 #define MSR_PFR_VCM_PROVISION_STATUS 0x00000068

1233

1234 typedef union {

1235 ///

1236 /// Individual bit fields

1237 ///

1238 struct {

1239 UINT32 Signature : 16;

1240

1241 /* Bits[15:0], Access Type=RW, default=None*/

1242

1243 /* PFR signature in CPLD */

1244 UINT32 PfrEnabled : 1;

1245

1246 /* Bits[16:16], Access Type=RW, default=None*/

1247

1248 /* PFR enable indication */

1249 UINT32 CpuProvision : 1;

1250

1251 /* Bits[17:17], Access Type=RW, default=None*/

1252

1253 /* CPU NVRAM is provisioned */

1254 UINT32 CpuProvisionLock : 1;

1255

1256 /* Bits[18:18], Access Type=RW, default=None*/

1257

1258 /* CPU NVRAM is locked */

1259 UINT32 Rsvd19 : 11;

1260

1261 /* Bits[29:19], Access Type=RO, default=None*/

1262

1263 /* Reserved */

1264 UINT32 Error : 1;

1265

1266 /* Bits[30:30], Access Type=RW, default=None*/

1267

1268 /* Error indicatoin */

1269 UINT32 Rsvd31 : 1;

1270

1271 /* Bits[31:31], Access Type=RO, default=None*/

1272

1273 /* Reserved */

1274 UINT32 Rsvd32 : 32;

1275

1276 /* Bits[63:32], Access Type=RO, default=None*/

1277

1278 /* Reserved */

1279

1280 } Bits;

1281

1282 UINT32 Uint32;

1283 UINT64 Uint64;

1284

1285 } MSR_PFR_VCM_PROVISION_STATUS_REGISTER;

1286 /**

1287 Not really a register. Probe mode MSR used to move data from/to PDR

1288 **/

1289 #define MSR_PROBE_TO_FROM_PDR 0x00000070

1290 /**

1291 Not really a register. Probe mode MSR used for copying EDX, EAX, EFLAGS, ST0 and the SMMEM bit to/from the scratch pad

1292 **/

1293 #define MSR_PROBE_GP_REG 0x00000071

1294 /**

1295 Not really a register. Probe mode MSR used for copying SS, CS, ES, LDTR, and GDTR to the scratch pad for probe mode.

1296 **/

1297 #define MSR_PROBE_SEG_REG_1 0x00000072

1298 /**

1299 Not really a register. Probe mode MSR added in SKL i1350201 that on RD/WRMSR does the following operations:

1300 R16/R17 to/from CTAP_CR_PROBE_MODE_DR/FSCP_CR_REGISTER_1

1301 BND_STATUS to/from FSCP_CR_REGISTER_2

1302 BNDCFG3_BASE_FIELD to/from FSCP_CR_REGISTER_3

1303 **/

1304 #define MSR_PROBE_PL_REG 0x00000073

1305 /**

1306 Not really a register. Probe mode MSR used for copying XMM0 and MXCSR to the scratch pad for probe mode.

1307 **/

1308 #define MSR_PROBE_MMX2_REG 0x00000074

1309 /**

1310 Not really a register. Probe mode MSR used for copying shadow copies of ES, DS, FS, and GS to the scratch pad for probe mode.

1311 **/

1312 #define MSR_PROBE_SEG_REG_3 0x00000075

1313 /**

1314 Not really a register. Probe mode MSR Register used for issuing Special Cycles to the LT chipset.

1315 **/

1316 #define MSR_PROBE_LT_SPC_CYC 0x00000076

1317

1318 /**

1319 Not really a register. Probe mode MSR used for changing CR0.PG to the value specified in bit 31 of EAX. It allows ITP to transition into and back out of Pseudo-64-bit mode (Long Mode, but with paging turned off).

1320 **/

1321 #define MSR_PROBE_CHANGE_PG 0x00000077

1322

1323 typedef union {

1324 ///

1325 /// Individual bit fields

1326 ///

1327 struct {

1328 UINT32 Rsvd0 : 31;

1329

1330 /* Bits[30:0], Access Type=RO_V, default=None*/

1331

1332 /* Junk */

1333 UINT32 Cr0Pg : 1;

1334

1335 /* Bits[31:31], Access Type=RO_V, default=None*/

1336

1337 /* Copied to CR0.PG */

1338

1339 } Bits;

1340

1341 UINT32 Uint32;

1342 UINT64 Uint64;

1343

1344 } MSR_PROBE_CHANGE_PG_REGISTER;

1345

1346 /**

1347 Allows Probe Mode ITP software to access relevant information located in the SECS and EPCM that is not accessible using EDBGRD instruction

1348 **/

1349 #define MSR_SE_RDINFO_CMD 0x0000007D

1350

1351 typedef union {

1352 ///

1353 /// Individual bit fields

1354 ///

1355 struct {

1356 UINT32 Command : 12;

1357

1358 /* Bits[11:0], Access Type=RW, default=None*/

1359

1360 /* Command Code */

1361 UINT32 EpcPage0 : 20;

1362

1363 /* Bits[31:12], Access Type=RW, default=None*/

1364

1365 /*

1366 Bits [63:12] of the platform physical address of

1367 the EPC page.

1368 */

1369 UINT32 EpcPage1 : 32;

1370

1371 /* Bits[63:32], Access Type=RW, default=None*/

1372

1373 /*

1374 Bits [63:12] of the platform physical address of

1375 the EPC page.

1376 */

1377

1378 } Bits;

1379

1380 UINT32 Uint32;

1381 UINT64 Uint64;

1382

1383 } MSR_SE_RDINFO_CMD_REGISTER;

1384 /**

1385 TBD

1386 **/

1387 #define MSR_EINIT_FAIL_CTR 0x0000007E

1388

1389 /**

1390 This register is used by BIOS to program Trace Hub (NPK) STH base address that will be used by AET messages

1391 **/

1392 #define MSR_NPK_STH_ACPIBAR_BASE 0x00000080

1393

1394 typedef union {

1395 ///

1396 /// Individual bit fields

1397 ///

1398 struct {

1399 UINT32 Lock : 1;

1400

1401 /* Bits[0:0], Access Type=RW, default=None*/

1402

1403 /*

1404 Lock bit - if set then this MSR cannot be re-

1405 written anymore. Lock bit has to be set in order

1406 for the AET packets to be directed to NPK MMIO.

1407 */

1408 UINT32 Rsvd1 : 17;

1409

1410 /* Bits[17:1], Access Type=RW, default=None*/

1411

1412 /* Reserved */

1413 UINT32 Address0 : 14;

1414

1415 /* Bits[31:18], Access Type=RW, default=None*/

1416

1417 /*

1418 ACPIBAR_BASE_ADDRESS - AET target address in NPK

1419 MMIO space.

1420 */

1421 UINT32 Address1 : 32;

1422

1423 /* Bits[63:32], Access Type=RW, default=None*/

1424

1425 /*

1426 ACPIBAR_BASE_ADDRESS - AET target address in NPK

1427 MMIO space.

1428 */

1429

1430 } Bits;

1431

1432 UINT32 Uint32;

1433 UINT64 Uint64;

1434

1435 } MSR_NPK_STH_ACPIBAR_BASE_REGISTER;

1436

1437 /**

1438 Rd/Wr register to generate or restore Far Memory Keys

1439 **/

1440 #define MSR_FME_ACTIVATE 0x00000081

1441

1442 typedef union {

1443 ///

1444 /// Individual bit fields

1445 ///

1446 struct {

1447 UINT32 Lock : 1;

1448

1449 /* Bits[0:0], Access Type=RW, default=0x00000000*/

1450

1451 /* When set will cause #GP on write. */

1452 UINT32 FmeEnable : 1;

1453

1454 /* Bits[1:1], Access Type=RW, default=0x00000000*/

1455

1456 /* Set to enable FME Encryption */

1457 UINT32 KeySelect : 1;

1458

1459 /* Bits[2:2], Access Type=WO, default=0x00000000*/

1460

1461 /* Select key 0 = new key, 1 = standby restore */

1462 UINT32 SaveKeyForStandby : 1;

1463

1464 /* Bits[3:3], Access Type=WO, default=0x00000000*/

1465

1466 /* Set to save key for standby */

1467 UINT32 Rsvd4 : 28;

1468

1469 /* Bits[31:4], Access Type=RO, default=0x00000000*/

1470

1471 /* Reserved Bits */

1472

1473 } Bits;

1474

1475 UINT32 Uint32;

1476 UINT64 Uint64;

1477

1478 } MSR_FME_ACTIVATE_REGISTER;

1479 /**

1480 Launch Enclave Provider signing key hash

1481 **/

1482 #define MSR_SGXLEPUBKEYHASH0 0x0000008C

1483 /**

1484 Launch Enclave Provider signing key hash

1485 **/

1486 #define MSR_SGXLEPUBKEYHASH1 0x0000008D

1487 /**

1488 Launch Enclave Provider signing key hash

1489 **/

1490 #define MSR_SGXLEPUBKEYHASH2 0x0000008E

1491 /**

1492 Launch Enclave Provider signing key hash

1493 **/

1494 #define MSR_SGXLEPUBKEYHASH3 0x0000008F

1495 /**

1496 emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support

1497 and in

1498 SNC HSD 1304428988 - HCTIO/SoftCE: uArch support for TIO_DEBUG_STATUS MSRs

1499 **/

1500 #define MSR_TIO_DEBUG_STATUS 0x00000090

1501 /**

1502 emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support

1503 **/

1504 #define MSR_TIO_UNWRAP 0x00000091

1505 /**

1506 emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support

1507 **/

1508 #define MSR_TIO_PRM_CLEANUP 0x00000092

1509 /**

1510 emulated by xucode --> cause pppe exit, described in SNC HSD 1304290485 - HCTIO/SoftCE: SoftCE ISA support

1511 **/

1512 #define MSR_TIO_COPY_ENCRYPT 0x00000093

1513

1514 /**

1515 Used to enable or disable cache QoS

1516 **/

1517 #define MSR_ENABLE_DISABLE_CACHE_QOS 0x00000095

1518

1519 typedef union {

1520 ///

1521 /// Individual bit fields

1522 ///

1523 struct {

1524 UINT32 LlcQosEn : 1;

1525

1526 /* Bits[0:0], Access Type=RW, default=None*/

1527

1528 /* Used to enable or disable cache QoS */

1529 UINT32 Rsvd1 : 31;

1530

1531 /* Bits[31:1], Access Type=RO, default=None*/

1532

1533 /* Reserved */

1534

1535 } Bits;

1536

1537 UINT32 Uint32;

1538 UINT64 Uint64;

1539

1540 } MSR_ENABLE_DISABLE_CACHE_QOS_REGISTER;

1541

1542 /**

1543 Address Match Range Register - Physical Mask Control Register

1544 **/

1545 #define MSR_TIORR_PHYSBASE 0x00000096

1546

1547 typedef union {

1548 ///

1549 /// Individual bit fields

1550 ///

1551 struct {

1552 UINT32 Rsvd0 : 12;

1553

1554 /* Bits[11:0], Access Type=RO, default=None*/

1555

1556 /* Reserved */

1557 UINT32 Base0 : 20;

1558

1559 /* Bits[31:12], Access Type=RW, default=0x00000000*/

1560

1561 /*

1562 The 4K-aligned platform physical base addresses

1563 of the TIORR register for debugging. These

1564 registers are programmed like MTRRs with base

1565 and mask. Address matches of an AMRR can be

1566 programmed to cause an "assist" or "abort".

1567 Assists invoke the address match ucode handler

1568 and populate the RR_MATCH_ADDR and

1569 RR_MATCH_RESULT CREGs with useful information

1570 about the access. Aborts force the memory type

1571 to UC and redirect the access to the abort page

1572 (causing it to get garbage data from the

1573 uncore). See AMRR_MASK bits for more information

1574 on how to program. See the PRF register

1575 definition for how to resume AMRR assist

1576 matches. restrictions : Set corresponding

1577 AMRR_MASK appropriately for the address.

1578 */

1579 UINT32 Base1 : 20;

1580

1581 /* Bits[51:32], Access Type=RW, default=0x00000000*/

1582

1583 /*

1584 The 4K-aligned platform physical base addresses

1585 of the TIORR register for debugging. These

1586 registers are programmed like MTRRs with base

1587 and mask. Address matches of an AMRR can be

1588 programmed to cause an "assist" or "abort".

1589 Assists invoke the address match ucode handler

1590 and populate the RR_MATCH_ADDR and

1591 RR_MATCH_RESULT CREGs with useful information

1592 about the access. Aborts force the memory type

1593 to UC and redirect the access to the abort page

1594 (causing it to get garbage data from the

1595 uncore). See AMRR_MASK bits for more information

1596 on how to program. See the PRF register

1597 definition for how to resume AMRR assist

1598 matches. restrictions : Set corresponding

1599 AMRR_MASK appropriately for the address.

1600 */

1601 UINT32 Rsvd52 : 12;

1602

1603 /* Bits[63:52], Access Type=RO, default=None*/

1604

1605 /* Reserved */

1606

1607 } Bits;

1608

1609 UINT32 Uint32;

1610 UINT64 Uint64;

1611

1612 } MSR_TIORR_PHYSBASE_REGISTER;

1613

1614 /**

1615 Address Match Range Register - Physical Mask Control Register

1616 **/

1617 #define MSR_TIORR_PHYSMASK 0x00000097

1618

1619 typedef union {

1620 ///

1621 /// Individual bit fields

1622 ///

1623 struct {

1624 UINT32 Rsvd0 : 3;

1625

1626 /* Bits[2:0], Access Type=RO, default=None*/

1627

1628 /* Reserved */

1629 UINT32 IgnorePw : 1;

1630

1631 /* Bits[3:3], Access Type=RO_V, default=0x00000000*/

1632

1633 /*

1634 If set, hitting the AMRR on a stuffed load will

1635 be ignored and will not cause assist nor abort.

1636 Only the real PA (on redispatch) can cause an

1637 assist if matches. restrictions :

1638 */

1639 UINT32 PhysegOvrd : 1;

1640

1641 /* Bits[4:4], Access Type=RO_V, default=0x00000000*/

1642

1643 /*

1644 If set, hitting the AMRR with PhySegSupOvr is

1645 allowed, and will not cause assist or abort

1646 restrictions :

1647 */

1648 UINT32 ForceWb : 1;

1649

1650 /* Bits[5:5], Access Type=RO_V, default=0x00000000*/

1651

1652 /*

1653 If set, hitting AMRR legally (see above bit),

1654 will also force WB memtype. This is subject to

1655 memtype priorities and can be overridden due to

1656 higher priority mem types restrictions :

1657 */

1658 UINT32 Rsvd6 : 2;

1659

1660 /* Bits[7:6], Access Type=RO, default=None*/

1661

1662 /* Reserved */

1663 UINT32 Ifetch : 1;

1664

1665 /* Bits[8:8], Access Type=RO_V, default=0x00000000*/

1666

1667 /*

1668 If set, allow AMRR assist matches for both

1669 I-side and D-side, else assist match D-side

1670 only. Pagewalk accesses (stuffed loads and

1671 loadpxelocks) always count as D-side. This bit

1672 has no effect on abort matches. restrictions :

1673 Set corresponding AMRR_BASE appropriately for

1674 the address. Set VLD, ASSIST, IFETCH, and MASK.

1675 */

1676 UINT32 Assist : 1;

1677

1678 /* Bits[9:9], Access Type=RO_V, default=0x00000000*/

1679

1680 /*

1681 If set, AMRR matches to the programmed address

1682 will invoke ucode's address match handler. If

1683 clear, AMRR matches will "abort" and redirect

1684 the access to the abort page and a UC memory

1685 type. restrictions : Set corresponding AMRR_BASE

1686 appropriately for the address. Set VLD, ASSIST,

1687 IFETCH, and MASK.

1688 */

1689 UINT32 L : 1;

1690

1691 /* Bits[10:10], Access Type=RW, default=0x00000000*/

1692

1693 /* Lock bit for the AMRR */

1694 UINT32 Valid : 1;

1695

1696 /* Bits[11:11], Access Type=RO_V, default=0x00000000*/

1697

1698 /* valid bit for the AMRR */

1699 UINT32 Mask0 : 20;

1700

1701 /* Bits[31:12], Access Type=RW, default=0x00000000*/

1702

1703 /*

1704 The mask value used in MTRR-like address

1705 matching of platform. Minimum granularity for

1706 matches is 4K (aligned), but the ucode handler

1707 can use RR_MATCH_ADDR and the resume capability

1708 (see the PRF register definition) to achieve

1709 narrower checking. restrictions : Set

1710 corresponding AMRR_BASE appropriately for the

1711 address. Set VLD, ASSIST, IFETCH, and MASK.

1712 */

1713 UINT32 Mask1 : 20;

1714

1715 /* Bits[51:32], Access Type=RW, default=0x00000000*/

1716

1717 /*

1718 The mask value used in MTRR-like address

1719 matching of platform. Minimum granularity for

1720 matches is 4K (aligned), but the ucode handler

1721 can use RR_MATCH_ADDR and the resume capability

1722 (see the PRF register definition) to achieve

1723 narrower checking. restrictions : Set

1724 corresponding AMRR_BASE appropriately for the

1725 address. Set VLD, ASSIST, IFETCH, and MASK.

1726 */

1727 UINT32 Rsvd52 : 12;

1728

1729 /* Bits[63:52], Access Type=RO, default=None*/

1730

1731 /* Reserved */

1732

1733 } Bits;

1734

1735 UINT32 Uint32;

1736 UINT64 Uint64;

1737

1738 } MSR_TIORR_PHYSMASK_REGISTER;

1739

1740 /**

1741 SMM Monitor Control MSR

1742 **/

1743 #define MSR_VMX_MSEG_BASE 0x0000009B

1744

1745 typedef union {

1746 ///

1747 /// Individual bit fields

1748 ///

1749 struct {

1750 UINT32 Valid : 1;

1751

1752 /* Bits[0:0], Access Type=RW, default=None*/

1753

1754 /* MSEG MSR Valid bit */

1755 UINT32 Reserved1 : 1;

1756

1757 /* Bits[1:1], Access Type=RW, default=None*/

1758

1759 /* Reserved */

1760 UINT32 Vmxoffctrl : 1;

1761

1762 /* Bits[2:2], Access Type=RW, default=None*/

1763

1764 /* Controls SMI unmasking during VMXOFF. */

1765 UINT32 Reserved3 : 9;

1766

1767 /* Bits[11:3], Access Type=RW, default=None*/

1768

1769 /* Reserved */

1770 UINT32 MsegBase : 20;

1771

1772 /* Bits[31:12], Access Type=RW, default=None*/

1773

1774 /* Address of Page Frame of MSEG base */

1775

1776 } Bits;

1777

1778 UINT32 Uint32;

1779 UINT64 Uint64;

1780

1781 } MSR_VMX_MSEG_BASE_REGISTER;

1782

1783 /**

1784 SMM Protected Mode Base MSR

1785 **/

1786 #define MSR_SMM_PROT_MODE_BASE 0x0000009D

1787

1788 typedef union {

1789 ///

1790 /// Individual bit fields

1791 ///

1792 struct {

1793 UINT32 Enable : 1;

1794

1795 /* Bits[0:0], Access Type=RW, default=None*/

1796

1797 /* Protected Mode SMM Enable */

1798 UINT32 Rsvd1 : 11;

1799

1800 /* Bits[11:1], Access Type=RW, default=None*/

1801

1802 /* Reserved */

1803 UINT32 PhysicalAddr : 20;

1804

1805 /* Bits[31:12], Access Type=RW, default=None*/

1806

1807 /* The physical address of the SMMSEG Table */

1808

1809 } Bits;

1810

1811 UINT32 Uint32;

1812 UINT64 Uint64;

1813

1814 } MSR_SMM_PROT_MODE_BASE_REGISTER;

1815 /**

1816 This is a read only of SMM Base register

1817 **/

1818 #define MSR_SMBASE_ADDR 0x0000009E

1819 /**

1820 SGX PRID values

1821 " seq has 2 instances in addresses range 0xA1 to 0xA2"

1822 **/

1823 #define MSR_PRID_0_0 0x000000A1

1824 /**

1825 SGX PRID values

1826 " seq has 2 instances in addresses range 0xA1 to 0xA2"

1827 **/

1828 #define MSR_PRID_1_1 0x000000A2

1829

1830 /**

1831 MSR to opt in to SGX and opt out of advanceed RAS features

1832 **/

1833 #define MSR_SGX_RAS 0x000000A3

1834

1835 typedef union {

1836 ///

1837 /// Individual bit fields

1838 ///

1839 struct {

1840 UINT32 Optin : 1;

1841

1842 /* Bits[0:0], Access Type=RW, default=0x00000000*/

1843

1844 /* optin bit */

1845 UINT32 Rsvd1 : 31;

1846

1847 /* Bits[31:1], Access Type=RO, default=None*/

1848

1849 /* Reserved */

1850 UINT32 Rsvd32 : 32;

1851

1852 /* Bits[63:32], Access Type=RO, default=None*/

1853

1854 /* Reserved */

1855

1856 } Bits;

1857

1858 UINT32 Uint32;

1859 UINT64 Uint64;

1860

1861 } MSR_SGX_RAS_REGISTER;

1862

1863 /**

1864 SGX QoS MSR

1865 **/

1866 #define MSR_BIOS_PKG_CONFIG 0x000000A4

1867

1868 typedef union {

1869 ///

1870 /// Individual bit fields

1871 ///

1872 struct {

1873 UINT32 Lock : 1;

1874

1875 /* Bits[0:0], Access Type=RW, default=0x00000000*/

1876

1877 /* Lock bit */

1878 UINT32 Enable : 1;

1879

1880 /* Bits[1:1], Access Type=RW, default=0x00000000*/

1881

1882 /* Lock bit */

1883 UINT32 Rsvd2 : 30;

1884

1885 /* Bits[31:2], Access Type=RO, default=None*/

1886

1887 /* Reserved */

1888

1889 } Bits;

1890

1891 UINT32 Uint32;

1892 UINT64 Uint64;

1893

1894 } MSR_BIOS_PKG_CONFIG_REGISTER;

1895

1896 /**

1897 FIT BIOS and ACM error type and code

1898 **/

1899 #define MSR_FIT_BIOS_ERROR 0x000000A5

1900

1901 typedef union {

1902 ///

1903 /// Individual bit fields

1904 ///

1905 struct {

1906 UINT32 ErrorCode : 8;

1907

1908 /* Bits[7:0], Access Type=RW, default=None*/

1909

1910 /* error code optype */

1911 UINT32 EntryType : 8;

1912

1913 /* Bits[15:8], Access Type=RW, default=None*/

1914

1915 /* entry type optype */

1916 UINT32 FitPatchEntry : 1;

1917

1918 /* Bits[16:16], Access Type=RW, default=None*/

1919

1920 /* indication whether patch entry exists in FIT */

1921 UINT32 Rsvd17 : 15;

1922

1923 /* Bits[31:17], Access Type=RW, default=None*/

1924

1925 /* Reserved */

1926 UINT32 Rsvd32 : 31;

1927

1928 /* Bits[62:32], Access Type=RW, default=None*/

1929

1930 /* Reserved */

1931 UINT32 Lock : 1;

1932

1933 /* Bits[63:63], Access Type=RW, default=None*/

1934

1935 /* Lock bit - set when FIT error is written to FSCP */

1936

1937 } Bits;

1938

1939 UINT32 Uint32;

1940 UINT64 Uint64;

1941

1942 } MSR_FIT_BIOS_ERROR_REGISTER;

1943

1944 /**

1945 Override MPX Fuse.

1946 **/

1947 #define MSR_MPX_FUSE_OVERRIDE 0x000000A6

1948

1949 typedef union {

1950 ///

1951 /// Individual bit fields

1952 ///

1953 struct {

1954 UINT32 MpxEnabled : 1;

1955

1956 /* Bits[0:0], Access Type=RO_V, default=None*/

1957

1958 /* MPX Enable */

1959 UINT32 Rsvd1 : 31;

1960

1961 /* Bits[31:1], Access Type=RO_V, default=None*/

1962

1963 /* Reserved */

1964 UINT32 Rsvd32 : 32;

1965

1966 /* Bits[63:32], Access Type=RO_V, default=None*/

1967

1968 /* Reserved */

1969

1970 } Bits;

1971

1972 UINT32 Uint32;

1973 UINT64 Uint64;

1974

1975 } MSR_MPX_FUSE_OVERRIDE_REGISTER;

1976

1977 /**

1978 Virtual MSR to disable AVX instructions from BIOS

1979 **/

1980 #define MSR_BIOS_AVX_DIS 0x000000AF

1981

1982 typedef union {

1983 ///

1984 /// Individual bit fields

1985 ///

1986 struct {

1987 UINT32 AvxDis : 1;

1988

1989 /* Bits[0:0], Access Type=RW, default=None*/

1990

1991 /* disable AVX/2/3 instructions */

1992 UINT32 Avx3Dis : 1;

1993

1994 /* Bits[1:1], Access Type=RW, default=None*/

1995

1996 /* disable AVX3 instructions */

1997 UINT32 Reserved2 : 30;

1998

1999 /* Bits[31:2], Access Type=RW, default=None*/

2000

2001 /* Reserved */

2002

2003 } Bits;

2004

2005 UINT32 Uint32;

2006 UINT64 Uint64;

2007

2008 } MSR_BIOS_AVX_DIS_REGISTER;

2009 /**

2010 vMSRs for power mgmt

2011 **/

2012 #define MSR_VMSR_U2P_0_0 0x000000B0

2013 /**

2014 vMSRs for power mgmt

2015 **/

2016 #define MSR_VMSR_U2P_1_1 0x000000B1

2017 /**

2018 vMSRs for power mgmt

2019 **/

2020 #define MSR_VMSR_U2P_2_2 0x000000B2

2021 /**

2022 vMSRs for power mgmt

2023 **/

2024 #define MSR_VMSR_U2P_3_3 0x000000B3

2025 /**

2026 SoftSKU data MSR

2027 **/

2028 #define MSR_SSKU_DATA 0x000000D0

2029

2030 /**

2031 SoftSKU cmd MSR

2032 **/

2033 #define MSR_SSKU_CMD 0x000000D1

2034

2035 typedef union {

2036 ///

2037 /// Individual bit fields

2038 ///

2039 struct {

2040 UINT32 Cmd : 16;

2041

2042 /* Bits[15:0], Access Type=RW, default=0x00000000*/

2043

2044 /* different cmds for ssku */

2045 UINT32 Rsvd16 : 16;

2046

2047 /* Bits[31:16], Access Type=RO, default=None*/

2048

2049 /* Reserved */

2050 UINT32 Rsvd32 : 32;

2051

2052 /* Bits[63:32], Access Type=RO, default=None*/

2053

2054 /* Reserved */

2055

2056 } Bits;

2057

2058 UINT32 Uint32;

2059 UINT64 Uint64;

2060

2061 } MSR_SSKU_CMD_REGISTER;

2062

2063 /**

2064 SoftSKU SMM access to LB regs

2065 **/

2066 #define MSR_SSKU_SMM_ADDR 0x000000D2

2067

2068 typedef union {

2069 ///

2070 /// Individual bit fields

2071 ///

2072 struct {

2073 UINT32 Addr : 32;

2074

2075 /* Bits[31:0], Access Type=RW, default=0x00000000*/

2076

2077 /* different cmds for ssku */

2078 UINT32 Rsvd32 : 32;

2079

2080 /* Bits[63:32], Access Type=RO, default=None*/

2081

2082 /* Reserved */

2083

2084 } Bits;

2085

2086 UINT32 Uint32;

2087 UINT64 Uint64;

2088

2089 } MSR_SSKU_SMM_ADDR_REGISTER;

2090

2091 /**

2092 SoftSKU SMM access to LB regs

2093 **/

2094 #define MSR_SSKU_SMM_DATA 0x000000D3

2095

2096 typedef union {

2097 ///

2098 /// Individual bit fields

2099 ///

2100 struct {

2101 UINT32 Addr : 32;

2102

2103 /* Bits[31:0], Access Type=RW, default=0x00000000*/

2104

2105 /* different cmds for ssku */

2106 UINT32 Rsvd32 : 32;

2107

2108 /* Bits[63:32], Access Type=RO, default=None*/

2109

2110 /* Reserved */

2111

2112 } Bits;

2113

2114 UINT32 Uint32;

2115 UINT64 Uint64;

2116

2117 } MSR_SSKU_SMM_DATA_REGISTER;

2118 /**

2119 SoftSKU enforcement MSR

2120 **/

2121 #define MSR_SSKU_ENFORCE 0x000000D4

2122

2123 /**

2124 C-State Configuration register

2125 **/

2126 #define MSR_CLOCK_CST_CONFIG_CONTROL 0x000000E2

2127

2128 typedef union {

2129 ///

2130 /// Individual bit fields

2131 ///

2132 struct {

2133 UINT32 MaxPkgCState : 4;

2134

2135 /* Bits[3:0], Access Type=RW, default=None*/

2136

2137 /*

2138 Specifies the lowest C-state for the package.

2139 This feature does not limit the processor core

2140 into specific C-state. The default is set as the

2141 factory-configured package C-state limit. 0000b

2142 C0/C1 (No package C-state support) 0001b C2

2143 0010b C3 0011b C6 0100b C7 0101b C7s 0110b C8

2144 0111b C9 1000b C10

2145 */

2146 UINT32 Rsvd4 : 6;

2147

2148 /* Bits[9:4], Access Type=RW, default=None*/

2149

2150 /* Reserved */

2151 UINT32 IoMwaitRedirection : 1;

2152

2153 /* Bits[10:10], Access Type=RW, default=None*/

2154

2155 /*

2156 When set, will map IO_read instructions sent to

2157 IO registers PMG_IO_BASE_ADDRBASE+offset to

2158 MWAIT(offset)

2159 */

2160 UINT32 Rsvd11 : 4;

2161

2162 /* Bits[14:11], Access Type=RW, default=None*/

2163

2164 /* Reserved */

2165 UINT32 Lock : 1;

2166

2167 /* Bits[15:15], Access Type=RW, default=None*/

2168

2169 /*

2170 When set, locks bits 15-0 of this register for

2171 further writes, until the next reset occurs.

2172 */

2173 UINT32 AccEnable : 1;

2174

2175 /* Bits[16:16], Access Type=RW, default=None*/

2176

2177 /*

2178 BDX new. Autonomous C-state control enable. When

2179 set, enables conversion of HALT instructions to

2180 MWAIT(C6). MWAIT(C1) is also converted into a

2181 MWAIT(C6) when enabled. This bit can be set only

2182 when ACC is fuse enabled (SERVER_UNCORE_FUSES).

2183 This bit is implemented in the FSCP (not part of

2184 the PCU register)

2185 */

2186 UINT32 Rsvd17 : 8;

2187

2188 /* Bits[24:17], Access Type=RW, default=None*/

2189

2190 /* Reserved */

2191 UINT32 C3StateAutoDemotionEnable : 1;

2192

2193 /* Bits[25:25], Access Type=RW, default=None*/

2194

2195 /*

2196 When set, processor will conditionally demote

2197 C6/C7 requests to C3 based on uncore auto-demote

2198 information

2199 */

2200 UINT32 C1StateAutoDemotionEnable : 1;

2201

2202 /* Bits[26:26], Access Type=RW, default=None*/

2203

2204 /*

2205 When set, processor will conditionally demote

2206 C6/C7 requests to C1 based on uncore auto-demote

2207 information

2208 */

2209 UINT32 Enc3undemotion : 1;

2210

2211 /* Bits[27:27], Access Type=RW, default=None*/

2212

2213 /* Enable Un-Demotion from Demoted C3 */

2214 UINT32 Enc1undemotion : 1;

2215

2216 /* Bits[28:28], Access Type=RW, default=None*/

2217

2218 /* Enable Un-Demotion from Demoted C1 */

2219 UINT32 Enpkgcautodemotion : 1;

2220

2221 /* Bits[29:29], Access Type=RW, default=None*/

2222

2223 /*

2224 Enable Package C-State auto-demotion. It enables

2225 the use of the history of past package C-State

2226 depth and residence as a factor in determining

2227 C-Sstate depth

2228 */

2229 UINT32 Enpkgcundemotion : 1;

2230

2231 /* Bits[30:30], Access Type=RW, default=None*/

2232

2233 /*

2234 Enable Package C-State Un-Demotion. It enables

2235 considering cases where demotion was the

2236 incorrect decision in determining C-State depth

2237 */

2238 UINT32 TimedMwaitEnable : 1;

2239

2240 /* Bits[31:31], Access Type=RW, default=None*/

2241

2242 /* When set, enables Timed MWAIT feature. */

2243

2244 } Bits;

2245

2246 UINT32 Uint32;

2247 UINT64 Uint64;

2248

2249 } MSR_CLOCK_CST_CONFIG_CONTROL_REGISTER;

2250

2251 /**

2252 Power Management I/O base address for I/O trapping to C-states.

2253 **/

2254 #define MSR_PMG_IO_CAPTURE_BASE 0x000000E4

2255

2256 typedef union {

2257 ///

2258 /// Individual bit fields

2259 ///

2260 struct {

2261 UINT32 Lvl2b : 16;

2262

2263 /* Bits[15:0], Access Type=RW, default=None*/

2264

2265 /*

2266 Base address of the LVL_2 register visible to

2267 software. If IO MWAIT Redirection is enabled

2268 using IO MWAIT Redirection Enable

2269 (PMG_CST_CONFIG_CONTROL MSR bit 10), reads to

2270 this address will be consumed by the power

2271 management logic and decoded to MWAIT

2272 instructions. When IO port address redirection

2273 is enabled, this is the IO port address reported

2274 to the OS/software.

2275 */

2276 UINT32 CstRange : 3;

2277

2278 /* Bits[18:16], Access Type=RW, default=None*/

2279

2280 /*

2281 The IO-port block size in which IO-redirection

2282 will be executed (0-7). Should be programmed

2283 based on the number of LVLx registers existing

2284 in the chipset

2285 */

2286 UINT32 Rsvd19 : 13;

2287

2288 /* Bits[31:19], Access Type=RW, default=None*/

2289

2290 /* Reserved */

2291

2292 } Bits;

2293

2294 UINT32 Uint32;

2295 UINT64 Uint64;

2296

2297 } MSR_PMG_IO_CAPTURE_BASE_REGISTER;

2298

2299 /**

2300 Not really a register. Probe mode MSR used to modify CPL.

2301 **/

2302 #define MSR_PROBE_CPL 0x00000101

2303

2304 typedef union {

2305 ///

2306 /// Individual bit fields

2307 ///

2308 struct {

2309 UINT32 Cpl : 2;

2310

2311 /* Bits[1:0], Access Type=RO_V, default=None*/

2312

2313 /* CPLk */

2314 UINT32 Rsvd2 : 30;

2315

2316 /* Bits[31:2], Access Type=RO, default=None*/

2317

2318 /* Reserved */

2319

2320 } Bits;

2321

2322 UINT32 Uint32;

2323 UINT64 Uint64;

2324

2325 } MSR_PROBE_CPL_REGISTER;

2326 /**

2327 Software PAIR weight override

2328 **/

2329 #define MSR_PAIR_WEIGHT_OVERRIDE 0x00000102

2330 /**

2331 Pair package level thread participation

2332 **/

2333 #define MSR_PAIR_PKG_THREAD_PARTICIPATION 0x00000103

2334 /**

2335 Register to specify a thread's inclusion or exclusion in Power Aware Interrupt Routing

2336 **/

2337 #define MSR_PAIR_THREAD_PARTICIPATION 0x00000104

2338

2339 #if 0 // Duplicate with ArchMsr.h.

2340 /**

2341 Write-only virtual MSR to activate DCU flush command

2342 **/

2343 #define MSR_DCU_FLUSH_CMD 0x0000010B

2344

2345 typedef union {

2346 ///

2347 /// Individual bit fields

2348 ///

2349 struct {

2350 UINT32 DcuFlush : 1;

2351

2352 /* Bits[0:0], Access Type=RW, default=None*/

2353

2354 /* */

2355 UINT32 Rsvd1 : 31;

2356

2357 /* Bits[31:1], Access Type=RW, default=None*/

2358

2359 /* reserved */

2360 UINT32 Rsvd32 : 32;

2361

2362 /* Bits[63:32], Access Type=RW, default=None*/

2363

2364 /* reserved */

2365

2366 } Bits;

2367

2368 UINT32 Uint32;

2369 UINT64 Uint64;

2370

2371 } MSR_DCU_FLUSH_CMD_REGISTER;

2372 #endif

2373

2374 /**

2375 Platform Firmware Control MSR.

2376 **/

2377 #define MSR_PLAT_FRMW_PROT_CTRL 0x00000110

2378

2379 typedef union {

2380 ///

2381 /// Individual bit fields

2382 ///

2383 struct {

2384 UINT32 PfatLock : 1;

2385

2386 /* Bits[0:0], Access Type=RW, default=0x00000000*/

2387

2388 /* Locks the PFAT configuration */

2389 UINT32 PfatEnable : 1;

2390

2391 /* Bits[1:1], Access Type=RW, default=0x00000000*/

2392

2393 /* Enables PFAT */

2394 UINT32 PfatDp : 1;

2395

2396 /* Bits[2:2], Access Type=RW, default=0x00000000*/

2397

2398 /*

2399 When set this bit indicates that a second socket

2400 exists. Applicable to dual socket systems only.

2401 */

2402 UINT32 Reserved3 : 29;

2403

2404 /* Bits[31:3], Access Type=RW, default=0x00000000*/

2405

2406 /* Reserved */

2407 UINT32 Reserved32 : 32;

2408

2409 /* Bits[63:32], Access Type=RW, default=0x00000000*/

2410

2411 /* Reserved */

2412

2413 } Bits;

2414

2415 UINT32 Uint32;

2416 UINT64 Uint64;

2417

2418 } MSR_PLAT_FRMW_PROT_CTRL_REGISTER;

2419 /**

2420 Platform Firmware Hash Value 063:000.

2421 **/

2422 #define MSR_PLAT_FRMW_PROT_HASH_0 0x00000111

2423 /**

2424 Platform Firmware Hash Value 127:064.

2425 **/

2426 #define MSR_PLAT_FRMW_PROT_HASH_1 0x00000112

2427 /**

2428 Platform Firmware Hash Value 191:128.

2429 **/

2430 #define MSR_PLAT_FRMW_PROT_HASH_2 0x00000113

2431 /**

2432 Platform Firmware Hash Value 255:192.

2433 **/

2434 #define MSR_PLAT_FRMW_PROT_HASH_3 0x00000114

2435 /**

2436 This registers contains the 64-bit physical address of the start of the PFAT DIRECTORY.

2437 **/

2438 #define MSR_PLAT_FRMW_PROT_TRIG_PARAM 0x00000115

2439 /**

2440 This is a Write-Only command MSR. A write triggers the command. A Rd will GP Fault.

2441 **/

2442 #define MSR_PLAT_FRMW_PROT_TRIGGER 0x00000116

2443 /**

2444 MSR to enable PFAT support on embedded controller discrete flash.

2445 **/

2446 #define MSR_PFAT_EC_PASSWORD 0x00000117

2447

2448 /**

2449 send to Sleep MSR

2450 **/

2451 #define MSR_PFAT_GT_SLEEP_CMDSTS 0x00000118

2452

2453 typedef union {

2454 ///

2455 /// Individual bit fields

2456 ///

2457 struct {

2458 UINT32 MailboxInternalPcodeKeepGtRc6 : 1;

2459

2460 /* Bits[0:0], Access Type=RW, default=0x00000000*/

2461

2462 /*

2463 MAILBOX_INTERNAL_PCODE_KEEP_GT_RC6_DISABLE (0x0)

2464 or MAILBOX_INTERNAL_PCODE_KEEP_GT_RC6_ENABLE

2465 (0x1)

2466 */

2467 UINT32 Rsvd1 : 31;

2468

2469 /* Bits[31:1], Access Type=RW, default=0x00000000*/

2470

2471 /* Reserved Bits */

2472 UINT32 Rsvd32 : 32;

2473

2474 /* Bits[63:32], Access Type=RW, default=0x00000000*/

2475

2476 /* Reserved Bits */

2477

2478 } Bits;

2479

2480 UINT32 Uint32;

2481 UINT64 Uint64;

2482

2483 } MSR_PFAT_GT_SLEEP_CMDSTS_REGISTER;

2484

2485 /**

2486 Read bits 23:16 of uncore SCP (storage for this 8b MSR)

2487 **/

2488 #define MSR_BIOS_INFO_FLAGS 0x0000011F

2489

2490 typedef union {

2491 ///

2492 /// Individual bit fields

2493 ///

2494 struct {

2495 UINT32 BiosInfoFlagsData : 8;

2496

2497 /* Bits[7:0], Access Type=RW, default=0x00000000*/

2498

2499 /*

2500 BIOS_INFO_FLAGS_DATA only 1 defined bit so far,

2501 but want to have the flexibility to use other 7

2502 bits w/o patching

2503 */

2504 UINT32 Rsvd8 : 24;

2505

2506 /* Bits[31:8], Access Type=RW, default=0x00000000*/

2507

2508 /* Reserved Bits */

2509 UINT32 Rsvd32 : 32;

2510

2511 /* Bits[63:32], Access Type=RW, default=0x00000000*/

2512

2513 /* Reserved Bits */

2514

2515 } Bits;

2516

2517 UINT32 Uint32;

2518 UINT64 Uint64;

2519

2520 } MSR_BIOS_INFO_FLAGS_REGISTER;

2521

2522 /**

2523 This is a read/write MSR that will control the ucode emulation of the PM_TMR. BIOS will program this register.

2524 **/

2525 #define MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG 0x00000121

2526

2527 typedef union {

2528 ///

2529 /// Individual bit fields

2530 ///

2531 struct {

2532 UINT32 EmulatedIoPort : 16;

2533

2534 /* Bits[15:0], Access Type=RW, default=None*/

2535

2536 /*

2537 I/O port which ucode will intercept if the valid

2538 bit is set. This port is the PM_TMR

2539 */

2540 UINT32 Valid : 1;

2541

2542 /* Bits[16:16], Access Type=RW, default=None*/

2543

2544 /*

2545 Indication if this configuration is valid. If

2546 this isn't valid, then the port in

2547 EMULATED_IO_PORT won't be intercepted. BIOS must

2548 set this bit to enable PM_TMR emulation

2549 */

2550 UINT32 Rsvd17 : 3;

2551

2552 /* Bits[19:17], Access Type=RW, default=None*/

2553

2554 /* Reserved */

2555 UINT32 RspDelayLoopCount : 12;

2556

2557 /* Bits[31:20], Access Type=RW, default=None*/

2558

2559 /*

2560 Number of PAUSE-like delay loops that should be

2561 completed before returning the response. This

2562 will allow for better timing emulation of ACPI

2563 timer response, which was causing issues in

2564 BIOS.

2565 */

2566 UINT32 CorrectionFactor : 32;

2567

2568 /* Bits[63:32], Access Type=RW, default=None*/

2569

2570 /*

2571 Factor to use to correct calculation of PM_TMR

2572 (against TSC[CTC])

2573 */

2574

2575 } Bits;

2576

2577 UINT32 Uint32;

2578 UINT64 Uint64;

2579

2580 } MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG_REGISTER;

2581

2582 /**

2583 This RO MSR will be used to read the Ubox CPUBUSNO/CPUBUSNO1/CPUBUSNO_VALID CSRs

2584 **/

2585 #define MSR_CPU_BUSNUMBER 0x00000128

2586

2587 typedef union {

2588 ///

2589 /// Individual bit fields

2590 ///

2591 struct {

2592 UINT32 Cpubusno0 : 8;

2593

2594 /* Bits[7:0], Access Type=RW, default=0x00000000*/

2595

2596 /* Bus Number 0 */

2597 UINT32 Cpubusno1 : 8;

2598

2599 /* Bits[15:8], Access Type=RW, default=0x00000000*/

2600

2601 /* Bus Number 1 */

2602 UINT32 Cpubusno2 : 8;

2603

2604 /* Bits[23:16], Access Type=RW, default=0x00000000*/

2605

2606 /* Bus Number 2 */

2607 UINT32 Cpubusno3 : 8;

2608

2609 /* Bits[31:24], Access Type=RW, default=0x00000000*/

2610

2611 /* Bus Number 3 */

2612 UINT32 Cpubusno4 : 8;

2613

2614 /* Bits[39:32], Access Type=RW, default=0x00000000*/

2615

2616 /* Bus Number 4 */

2617 UINT32 Cpubusno5 : 8;

2618

2619 /* Bits[47:40], Access Type=RW, default=0x00000000*/

2620

2621 /* Bus Number 5 */

2622 UINT32 Rsvd48 : 15;

2623

2624 /* Bits[62:48], Access Type=RO, default=None*/

2625

2626 /* Reserved */

2627 UINT32 Valid : 1;

2628

2629 /* Bits[63:63], Access Type=RW, default=0x00000000*/

2630

2631 /*

2632 Set when the CSR is written with valid bus

2633 numbers

2634 */

2635

2636 } Bits;

2637

2638 UINT32 Uint32;

2639 UINT64 Uint64;

2640

2641 } MSR_CPU_BUSNUMBER_REGISTER;

2642 /**

2643 This RO MSR will be used to read the Ubox MMCFG_RULE_CFG list

2644 **/

2645 #define MSR_MMCFG_RULE_CFG 0x00000129

2646 /**

2647 This RO MSR will be used to read the Ubox MMCFG_RULE_TARGET_LIST

2648 **/

2649 #define MSR_MMCFG_RULE_TARGET_LIST 0x0000012A

2650 /**

2651 Anchor Cove MSR for reading boot policy information from the PCH.

2652 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2653 Base addr is 0xFED58000 and reads are consecutive.

2654 " seq has 8 instances in addresses range 0x130 to 0x137"

2655 **/

2656 #define MSR_ANC_BOOT_POLICY_0_0 0x00000130

2657 /**

2658 Anchor Cove MSR for reading boot policy information from the PCH.

2659 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2660 Base addr is 0xFED58000 and reads are consecutive.

2661 " seq has 8 instances in addresses range 0x130 to 0x137"

2662 **/

2663 #define MSR_ANC_BOOT_POLICY_1_1 0x00000131

2664 /**

2665 Anchor Cove MSR for reading boot policy information from the PCH.

2666 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2667 Base addr is 0xFED58000 and reads are consecutive.

2668 " seq has 8 instances in addresses range 0x130 to 0x137"

2669 **/

2670 #define MSR_ANC_BOOT_POLICY_2_2 0x00000132

2671 /**

2672 Anchor Cove MSR for reading boot policy information from the PCH.

2673 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2674 Base addr is 0xFED58000 and reads are consecutive.

2675 " seq has 8 instances in addresses range 0x130 to 0x137"

2676 **/

2677 #define MSR_ANC_BOOT_POLICY_3_3 0x00000133

2678 /**

2679 Anchor Cove MSR for reading boot policy information from the PCH.

2680 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2681 Base addr is 0xFED58000 and reads are consecutive.

2682 " seq has 8 instances in addresses range 0x130 to 0x137"

2683 **/

2684 #define MSR_ANC_BOOT_POLICY_4_4 0x00000134

2685 /**

2686 Anchor Cove MSR for reading boot policy information from the PCH.

2687 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2688 Base addr is 0xFED58000 and reads are consecutive.

2689 " seq has 8 instances in addresses range 0x130 to 0x137"

2690 **/

2691 #define MSR_ANC_BOOT_POLICY_5_5 0x00000135

2692 /**

2693 Anchor Cove MSR for reading boot policy information from the PCH.

2694 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2695 Base addr is 0xFED58000 and reads are consecutive.

2696 " seq has 8 instances in addresses range 0x130 to 0x137"

2697 **/

2698 #define MSR_ANC_BOOT_POLICY_6_6 0x00000136

2699 /**

2700 Anchor Cove MSR for reading boot policy information from the PCH.

2701 8 new RDMSR range (addr 0x130-0x137), which read 64b each.

2702 Base addr is 0xFED58000 and reads are consecutive.

2703 " seq has 8 instances in addresses range 0x130 to 0x137"

2704 **/

2705 #define MSR_ANC_BOOT_POLICY_7_7 0x00000137

2706

2707 /**

2708 Anchor Cove MSR to indicate that the initial boot block is complete, and to re-enable events.

2709 Write-only and accessible via the ACM.

2710 **/

2711 #define MSR_ANC_FORCE_BOOT_POLICY_ENFORCED 0x00000138

2712

2713 typedef union {

2714 ///

2715 /// Individual bit fields

2716 ///

2717 struct {

2718 UINT32 Data : 32;

2719

2720 /* Bits[31:0], Access Type=RW, default=None*/

2721

2722 /* Force Boot Policy Enforced */

2723 UINT32 Rsvd32 : 32;

2724

2725 /* Bits[63:32], Access Type=RO, default=None*/

2726

2727 /* Reserved */

2728

2729 } Bits;

2730

2731 UINT32 Uint32;

2732 UINT64 Uint64;

2733

2734 } MSR_ANC_FORCE_BOOT_POLICY_ENFORCED_REGISTER;

2735

2736 /**

2737 Anchor Cove MSR to tell PCH that the ACM has successfully launched and to stop the deadman timer countdown.

2738 Write-only and accessible via the ACM.

2739 **/

2740 #define MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE 0x00000139

2741

2742 typedef union {

2743 ///

2744 /// Individual bit fields

2745 ///

2746 struct {

2747 UINT32 Done : 1;

2748

2749 /* Bits[0:0], Access Type=RW, default=None*/

2750

2751 /*

2752 Bit indicates that ACM has successfully

2753 launched. Stop deadman timer counter

2754 */

2755 UINT32 Rsvd1 : 31;

2756

2757 /* Bits[31:1], Access Type=RO, default=None*/

2758

2759 /* Reserved */

2760 UINT32 Rsvd32 : 32;

2761

2762 /* Bits[63:32], Access Type=RO, default=None*/

2763

2764 /* Reserved */

2765

2766 } Bits;

2767

2768 UINT32 Uint32;

2769 UINT64 Uint64;

2770

2771 } MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE_REGISTER;

2772

2773 /**

2774 An MSR for communicating basic policy information from the Anchor Cove ACM to early BIOS.

2775 Things like executing in NEM, thread protection enabled etc., will be communicated.

2776 **/

2777 #define MSR_ANC_SACM_INFO 0x0000013A

2778

2779 typedef union {

2780 ///

2781 /// Individual bit fields

2782 ///

2783 struct {

2784 UINT32 SacmData : 8;

2785

2786 /* Bits[7:0], Access Type=RW, default=None*/

2787

2788 /*

2789 Anchor Cove boot policy information populated by

2790 the AnC StartupACM

2791 */

2792 UINT32 Rsvd8 : 24;

2793

2794 /* Bits[31:8], Access Type=RO, default=None*/

2795

2796 /* Reserved */

2797 UINT32 AnchorCoveEnFuse : 1;

2798

2799 /* Bits[32:32], Access Type=RW, default=None*/

2800

2801 /*

2802 Read-only bit to reflect the Anchor Cove enable

2803 fuse

2804 */

2805 UINT32 Pbe : 1;

2806

2807 /* Bits[33:33], Access Type=RW, default=None*/

2808

2809 /*

2810 Read-only bit to reflect the PCH Protect BIOS

2811 Environment bit

2812 */

2813 UINT32 LtSxEnFuse : 1;

2814

2815 /* Bits[34:34], Access Type=RW, default=None*/

2816

2817 /* Read-only bit to reflect the LT-SX enable fuse */

2818 UINT32 NoResetSecretsProt : 1;

2819

2820 /* Bits[35:35], Access Type=RW, default=None*/

2821

2822 /*

2823 Read-only bit to reflect no reset secrets

2824 protection

2825 */

2826 UINT32 Rsvd36 : 28;

2827

2828 /* Bits[63:36], Access Type=RO, default=None*/

2829

2830 /* Reserved */

2831

2832 } Bits;

2833

2834 UINT32 Uint32;

2835 UINT64 Uint64;

2836

2837 } MSR_ANC_SACM_INFO_REGISTER;

2838

2839 /**

2840 AES Feature configuration. This MSR is visible only if one of the following holds:

2841 CPUID.(EAX=01h):ECX[25]=1, which indicates the processor was manufactured with AES-NI enabled.

2842 **/

2843 #define MSR_FEATURE_CONFIG 0x0000013C

2844

2845 typedef union {

2846 ///

2847 /// Individual bit fields

2848 ///

2849 struct {

2850 UINT32 Lock : 1;

2851

2852 /* Bits[0:0], Access Type=RW, default=None*/

2853

2854 /*

2855 Once this bit is set, writes to this register

2856 will not be allowed

2857 */

2858 UINT32 AesDisable : 1;

2859

2860 /* Bits[1:1], Access Type=RW, default=None*/

2861

2862 /*

2863 This bit disables Advanced Encryption Standard

2864 feature on this processor core. To disable AES,

2865 BIOS will write '11 to this MSR on every core.

2866 */

2867 UINT32 Reserved2 : 30;

2868

2869 /* Bits[31:2], Access Type=RW, default=None*/

2870

2871 /* Reserved bits */

2872

2873 } Bits;

2874

2875 UINT32 Uint32;

2876 UINT64 Uint64;

2877

2878 } MSR_FEATURE_CONFIG_REGISTER;

2879 /**

2880 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2881 " seq has 3 instances in addresses range 0x13D to 0x13F"

2882 **/

2883 #define MSR_CORE_SPECIFIC_SPARE_0_0 0x0000013D

2884 /**

2885 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2886 " seq has 3 instances in addresses range 0x13D to 0x13F"

2887 **/

2888 #define MSR_CORE_SPECIFIC_SPARE_1_1 0x0000013E

2889 /**

2890 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2891 " seq has 3 instances in addresses range 0x13D to 0x13F"

2892 **/

2893 #define MSR_CORE_SPECIFIC_SPARE_2_2 0x0000013F

2894

2895 /**

2896 Miscellaneous enables for thread specific features.

2897 [IntelRsvd]FSCP Crunch - 1:32 Used only 1 bit out of 32[/IntelRsvd]

2898 **/

2899 #define MSR_MISC_THD_FEATURE_ENABLES 0x00000140

2900

2901 typedef union {

2902 ///

2903 /// Individual bit fields

2904 ///

2905 struct {

2906 UINT32 CpuidGpOnCplGt0 : 1;

2907

2908 /* Bits[0:0], Access Type=RW, default=None*/

2909

2910 /*

2911 Causes CPUID to #GP if CPL greater than 0 and

2912 not in SMM.

2913 */

2914 UINT32 Reserved1 : 31;

2915

2916 /* Bits[31:1], Access Type=RW, default=None*/

2917

2918 /* SCP Register Reserved Bits */

2919

2920 } Bits;

2921

2922 UINT32 Uint32;

2923 UINT64 Uint64;

2924

2925 } MSR_MISC_THD_FEATURE_ENABLES_REGISTER;

2926

2927 /**

2928 SMM-only MSR which allows locking of various states while in SMM mode

2929 **/

2930 #define MSR_SMM_SUPOVR_STATE_LOCK 0x00000141

2931

2932 typedef union {

2933 ///

2934 /// Individual bit fields

2935 ///

2936 struct {

2937 UINT32 PagingStates : 1;

2938

2939 /* Bits[0:0], Access Type=RW, default=None*/

2940

2941 /*

2942 When set, prevents changing various paging state

2943 bits (CR0,CR3,CR4,EFER), and prevents task

2944 switches

2945 */

2946 UINT32 Smbase : 1;

2947

2948 /* Bits[1:1], Access Type=RW, default=None*/

2949

2950 /* When set, prevents RSM(SMI) from updating SMBASE */

2951 UINT32 Ia32SmmMonitorCtlMsr : 1;

2952

2953 /* Bits[2:2], Access Type=RW, default=None*/

2954

2955 /*

2956 When set, prevents WRMSR to IA32_SMM_MONITOR_CTL

2957 (aka MSEG) MSR

2958 */

2959 UINT32 Reserved3 : 29;

2960

2961 /* Bits[31:3], Access Type=RW, default=None*/

2962

2963 /* Reserved for future usage */

2964

2965 } Bits;

2966

2967 UINT32 Uint32;

2968 UINT64 Uint64;

2969

2970 } MSR_SMM_SUPOVR_STATE_LOCK_REGISTER;

2971 /**

2972 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2973 " seq has 14 instances in addresses range 0x142 to 0x14F"

2974 **/

2975 #define MSR_THREAD_SPECIFIC_SPARE_0_0 0x00000142

2976 /**

2977 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2978 " seq has 14 instances in addresses range 0x142 to 0x14F"

2979 **/

2980 #define MSR_THREAD_SPECIFIC_SPARE_1_1 0x00000143

2981 /**

2982 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2983 " seq has 14 instances in addresses range 0x142 to 0x14F"

2984 **/

2985 #define MSR_THREAD_SPECIFIC_SPARE_2_2 0x00000144

2986 /**

2987 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2988 " seq has 14 instances in addresses range 0x142 to 0x14F"

2989 **/

2990 #define MSR_THREAD_SPECIFIC_SPARE_3_3 0x00000145

2991 /**

2992 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2993 " seq has 14 instances in addresses range 0x142 to 0x14F"

2994 **/

2995 #define MSR_THREAD_SPECIFIC_SPARE_4_4 0x00000146

2996 /**

2997 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

2998 " seq has 14 instances in addresses range 0x142 to 0x14F"

2999 **/

3000 #define MSR_THREAD_SPECIFIC_SPARE_5_5 0x00000147

3001 /**

3002 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3003 " seq has 14 instances in addresses range 0x142 to 0x14F"

3004 **/

3005 #define MSR_THREAD_SPECIFIC_SPARE_6_6 0x00000148

3006 /**

3007 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3008 " seq has 14 instances in addresses range 0x142 to 0x14F"

3009 **/

3010 #define MSR_THREAD_SPECIFIC_SPARE_7_7 0x00000149

3011 /**

3012 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3013 " seq has 14 instances in addresses range 0x142 to 0x14F"

3014 **/

3015 #define MSR_THREAD_SPECIFIC_SPARE_8_8 0x0000014A

3016 /**

3017 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3018 " seq has 14 instances in addresses range 0x142 to 0x14F"

3019 **/

3020 #define MSR_THREAD_SPECIFIC_SPARE_9_9 0x0000014B

3021 /**

3022 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3023 " seq has 14 instances in addresses range 0x142 to 0x14F"

3024 **/

3025 #define MSR_THREAD_SPECIFIC_SPARE_10_10 0x0000014C

3026 /**

3027 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3028 " seq has 14 instances in addresses range 0x142 to 0x14F"

3029 **/

3030 #define MSR_THREAD_SPECIFIC_SPARE_11_11 0x0000014D

3031 /**

3032 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3033 " seq has 14 instances in addresses range 0x142 to 0x14F"

3034 **/

3035 #define MSR_THREAD_SPECIFIC_SPARE_12_12 0x0000014E

3036 /**

3037 Spare thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. WSM eco 653232

3038 " seq has 14 instances in addresses range 0x142 to 0x14F"

3039 **/

3040 #define MSR_THREAD_SPECIFIC_SPARE_13_13 0x0000014F

3041

3042 /**

3043 An Interface to perform various overclocking oriented commands.

3044 **/

3045 #define MSR_OVERCLOCKING_MAILBOX 0x00000150

3046

3047 typedef union {

3048 ///

3049 /// Individual bit fields

3050 ///

3051 struct {

3052 UINT32 Data : 32;

3053

3054 /* Bits[31:0], Access Type=RW, default=None*/

3055

3056 /* Command specific data field. */

3057 UINT32 Command : 8;

3058

3059 /* Bits[39:32], Access Type=RW, default=None*/

3060

3061 /*

3062 This field holds the command ID for WRMSR

3063 operations and holds the error code on RDMSR

3064 operations. [list] [*]Commands in 0x1 to 0xf

3065 range are read-only capabilities. [*]Commands in

3066 0x10 and up are read/write. [/list]

3067 */

3068 UINT32 Param1 : 8;

3069

3070 /* Bits[47:40], Access Type=RW, default=None*/

3071

3072 /* Command specific Parameter 1 */

3073 UINT32 Param2 : 8;

3074

3075 /* Bits[55:48], Access Type=RW, default=None*/

3076

3077 /*

3078 Command specific Parameter 2 [IntelRsvd]SNC:

3079 This is now supported : b1304634937[/IntelRsvd]

3080 */

3081 UINT32 Rsvd56 : 7;

3082

3083 /* Bits[62:56], Access Type=RO, default=None*/

3084

3085 /* Reserved */

3086 UINT32 RunBusy : 1;

3087

3088 /* Bits[63:63], Access Type=RW, default=None*/

3089

3090 /*

3091 Writes without Run/Busy indicator set are

3092 dropped on the floor

3093 */

3094

3095 } Bits;

3096

3097 UINT32 Uint32;

3098 UINT64 Uint64;

3099

3100 } MSR_OVERCLOCKING_MAILBOX_REGISTER;

3101

3102 /**

3103 BIOS Done register for CNL issue 1351547

3104 - Bit 0 (R/W): ENABLE_IA_UNTRUSTED

3105 o Cleared only by reset (cold/warm).

3106 o A change from 0->1 will increment BIOS_DONE_COUNTER in the SoC

3107 o Writes to the bit will be ignored if the EAX[0] is 0

3108 - Bit 1 (R): SOC_BIOS_DONE

3109 o Returns '1 if all available threads set their ENABLE_IA_UNTRUSTED.

3110 o Writes will be silently dropped.

3111 - Bits 31:2: Reserved - write '1 results in #GP.

3112 **/

3113 #define MSR_BIOS_DONE 0x00000151

3114

3115 typedef union {

3116 ///

3117 /// Individual bit fields

3118 ///

3119 struct {

3120 UINT32 EnableIaUntrusted : 1;

3121

3122 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3123

3124 /*

3125 o Cleared only by reset (cold/warm). o A change

3126 from 0->1 will increment BIOS_DONE_COUNTER in

3127 the SoC o Writes to the bit will be ignored if

3128 the EAX[0] is 0

3129 */

3130 UINT32 SocBiosDone : 1;

3131

3132 /* Bits[1:1], Access Type=RO_V, default=0x00000000*/

3133

3134 /*

3135 o Cleared only by reset (cold/warm). o A change

3136 from 0->1 will increment BIOS_DONE_COUNTER in

3137 the SoC o Writes to the bit will be ignored if

3138 the EAX[0] is 0

3139 */

3140 UINT32 Rsvd2 : 30;

3141

3142 /* Bits[31:2], Access Type=RO, default=None*/

3143

3144 /* Reserved */

3145

3146 } Bits;

3147

3148 UINT32 Uint32;

3149 UINT64 Uint64;

3150

3151 } MSR_BIOS_DONE_REGISTER;

3152

3153 /**

3154 SNC_CONFIG_BASE register decription

3155 **/

3156 #define MSR_SNC_CONFIG 0x00000152

3157

3158 typedef union {

3159 ///

3160 /// Individual bit fields

3161 ///

3162 struct {

3163 UINT32 SncEnable : 1;

3164

3165 /* Bits[0:0], Access Type=RW_V, default=0x00000000*/

3166

3167 /* SNC Enable bit */

3168 UINT32 SncIndicationEnable : 1;

3169

3170 /* Bits[1:1], Access Type=RW_V, default=0x00000000*/

3171

3172 /* SNC Enable bit */

3173 UINT32 NumberOfClusters : 2;

3174

3175 /* Bits[3:2], Access Type=RW_V, default=0x00000000*/

3176

3177 /* Number Of Clusters */

3178 UINT32 Cluster1Base : 6;

3179

3180 /* Bits[9:4], Access Type=RW_V, default=0x00000000*/

3181

3182 /* Cluster 2 Base */

3183 UINT32 Cluster2Base : 6;

3184

3185 /* Bits[15:10], Access Type=RW_V, default=0x00000000*/

3186

3187 /* Cluster 3 Base */

3188 UINT32 Cluster3Base : 6;

3189

3190 /* Bits[21:16], Access Type=RW_V, default=0x00000000*/

3191

3192 /* Cluster 4 Base */

3193 UINT32 Rsvd22 : 6;

3194

3195 /* Bits[27:22], Access Type=RO, default=None*/

3196

3197 /* Reserved */

3198 UINT32 SncLock : 1;

3199

3200 /* Bits[28:28], Access Type=RW_V, default=0x00000000*/

3201

3202 /*

3203 Due to SKL B0 freeze this late arrving bit is

3204 implemented in

3205 FSCP_CR_MISC_FEATURE_ENABLES[SNC_LOCK]

3206 */

3207 UINT32 Rsvd29 : 3;

3208

3209 /* Bits[31:29], Access Type=RO, default=None*/

3210

3211 /* Reserved */

3212

3213 } Bits;

3214

3215 UINT32 Uint32;

3216 UINT64 Uint64;

3217

3218 } MSR_SNC_CONFIG_REGISTER;

3219

3220 /**

3221 SNC_RANGE1_BASE register decription

3222 **/

3223 #define MSR_SNC_RANGE0_BASE 0x00000153

3224

3225 typedef union {

3226 ///

3227 /// Individual bit fields

3228 ///

3229 struct {

3230 UINT32 Range : 16;

3231

3232 /* Bits[15:0], Access Type=RW_V, default=0x00000000*/

3233

3234 /* Range1 Base Addr */

3235 UINT32 Rsvd16 : 16;

3236

3237 /* Bits[31:16], Access Type=RO, default=None*/

3238

3239 /* Reserved */

3240

3241 } Bits;

3242

3243 UINT32 Uint32;

3244 UINT64 Uint64;

3245

3246 } MSR_SNC_RANGE0_BASE_REGISTER;

3247

3248 /**

3249 SNC_RANGE2_BASE register decription

3250 **/

3251 #define MSR_SNC_RANGE1_BASE 0x00000154

3252

3253 typedef union {

3254 ///

3255 /// Individual bit fields

3256 ///

3257 struct {

3258 UINT32 Range : 16;

3259

3260 /* Bits[15:0], Access Type=RW_V, default=0x00000000*/

3261

3262 /* Range2 Base Addr */

3263 UINT32 Rsvd16 : 16;

3264

3265 /* Bits[31:16], Access Type=RO, default=None*/

3266

3267 /* Reserved */

3268

3269 } Bits;

3270

3271 UINT32 Uint32;

3272 UINT64 Uint64;

3273

3274 } MSR_SNC_RANGE1_BASE_REGISTER;

3275

3276 /**

3277 SNC_RANGE3_BASE register decription

3278 **/

3279 #define MSR_SNC_RANGE2_BASE 0x00000155

3280

3281 typedef union {

3282 ///

3283 /// Individual bit fields

3284 ///

3285 struct {

3286 UINT32 Range : 16;

3287

3288 /* Bits[15:0], Access Type=RW_V, default=0x00000000*/

3289

3290 /* Range 3 Base Addr */

3291 UINT32 Rsvd16 : 16;

3292

3293 /* Bits[31:16], Access Type=RO, default=None*/

3294

3295 /* Reserved */

3296

3297 } Bits;

3298

3299 UINT32 Uint32;

3300 UINT64 Uint64;

3301

3302 } MSR_SNC_RANGE2_BASE_REGISTER;

3303

3304 /**

3305 SNC_RANGE4_BASE register decription

3306 **/

3307 #define MSR_SNC_RANGE3_BASE 0x00000156

3308

3309 typedef union {

3310 ///

3311 /// Individual bit fields

3312 ///

3313 struct {

3314 UINT32 Range : 16;

3315

3316 /* Bits[15:0], Access Type=RW_V, default=0x00000000*/

3317

3318 /* Range4 Base Addr */

3319 UINT32 Rsvd16 : 16;

3320

3321 /* Bits[31:16], Access Type=RO, default=None*/

3322

3323 /* Reserved */

3324

3325 } Bits;

3326

3327 UINT32 Uint32;

3328 UINT64 Uint64;

3329

3330 } MSR_SNC_RANGE3_BASE_REGISTER;

3331

3332 /**

3333 SNC_RANGE5_BASE register decription

3334 **/

3335 #define MSR_SNC_RANGE4_BASE 0x00000157

3336

3337 typedef union {

3338 ///

3339 /// Individual bit fields

3340 ///

3341 struct {

3342 UINT32 Range : 16;

3343

3344 /* Bits[15:0], Access Type=RW_V, default=0x00000000*/

3345

3346 /* Range 5 Base Addr */

3347 UINT32 Rsvd16 : 16;

3348

3349 /* Bits[31:16], Access Type=RO, default=None*/

3350

3351 /* Reserved */

3352

3353 } Bits;

3354

3355 UINT32 Uint32;

3356 UINT64 Uint64;

3357

3358 } MSR_SNC_RANGE4_BASE_REGISTER;

3359

3360 /**

3361 Core SMI Error Source

3362 **/

3363 #define MSR_THREAD_SMI_ERR_SRC 0x00000158

3364

3365 typedef union {

3366 ///

3367 /// Individual bit fields

3368 ///

3369 struct {

3370 UINT32 Ifu : 1;

3371

3372 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3373

3374 /* */

3375 UINT32 Dcu : 1;

3376

3377 /* Bits[1:1], Access Type=RW, default=0x00000000*/

3378

3379 /* */

3380 UINT32 Rsvd2 : 30;

3381

3382 /* Bits[31:2], Access Type=RO, default=None*/

3383

3384 /* Reserved */

3385

3386 } Bits;

3387

3388 UINT32 Uint32;

3389 UINT64 Uint64;

3390

3391 } MSR_THREAD_SMI_ERR_SRC_REGISTER;

3392

3393 /**

3394 SNC range upper 6 bits per range register

3395 **/

3396 #define MSR_SNC_UPPER_BASE 0x00000159

3397

3398 typedef union {

3399 ///

3400 /// Individual bit fields

3401 ///

3402 struct {

3403 UINT32 UpperBase0 : 6;

3404

3405 /* Bits[5:0], Access Type=RW_V, default=0x00000000*/

3406

3407 /* Base Address [51:46] for 1st cluster */

3408 UINT32 UpperBase1 : 6;

3409

3410 /* Bits[11:6], Access Type=RW_V, default=0x00000000*/

3411

3412 /* Base Address [51:46] for 2nd cluster */

3413 UINT32 UpperBase2 : 6;

3414

3415 /* Bits[17:12], Access Type=RW_V, default=0x00000000*/

3416

3417 /* Base Address [51:46] for 3rd cluster */

3418 UINT32 UpperBase3 : 6;

3419

3420 /* Bits[23:18], Access Type=RW_V, default=0x00000000*/

3421

3422 /* Base Address [51:46] for 4th cluster */

3423 UINT32 UpperBase4 : 6;

3424

3425 /* Bits[29:24], Access Type=RW_V, default=0x00000000*/

3426

3427 /* Base Address [51:46] for 5th cluster */

3428 UINT32 Rsvd30 : 2;

3429

3430 /* Bits[31:30], Access Type=RO, default=None*/

3431

3432 /* Reserved */

3433

3434 } Bits;

3435

3436 UINT32 Uint32;

3437 UINT64 Uint64;

3438

3439 } MSR_SNC_UPPER_BASE_REGISTER;

3440

3441 /**

3442 Special uncore usage msr, work in PFAT or in SMM BIOS flash

3443 **/

3444 #define MSR_SPCL_UNCORE_USAGE 0x0000015B

3445

3446 typedef union {

3447 ///

3448 /// Individual bit fields

3449 ///

3450 struct {

3451 UINT32 Data : 1;

3452

3453 /* Bits[0:0], Access Type=RW, default=0x00000000*/

3454

3455 /* */

3456 UINT32 Rsvd1 : 31;

3457

3458 /* Bits[31:1], Access Type=RW, default=0x00000000*/

3459

3460 /* Reserved Bits */

3461

3462 } Bits;

3463

3464 UINT32 Uint32;

3465 UINT64 Uint64;

3466

3467 } MSR_SPCL_UNCORE_USAGE_REGISTER;

3468

3469 /**

3470 Read-only MSR that specifies the maximum number of memory controllers on the platform capable of supporting memory persistence

3471 **/

3472 #define MSR_PERMEM_CONFIG_INFO 0x0000015C

3473

3474 typedef union {

3475 ///

3476 /// Individual bit fields

3477 ///

3478 struct {

3479 UINT32 ControllerCount : 8;

3480

3481 /* Bits[7:0], Access Type=RW, default=None*/

3482

3483 /*

3484 maximum number of memory controllers on the

3485 platform capable of supporting memory

3486 persistence

3487 */

3488 UINT32 Rsvd8 : 24;

3489

3490 /* Bits[31:8], Access Type=RW, default=None*/

3491

3492 /* Reserved */

3493 UINT32 Rsvd32 : 32;

3494

3495 /* Bits[63:32], Access Type=RW, default=None*/

3496

3497 /* Reserved */

3498

3499 } Bits;

3500

3501 UINT32 Uint32;

3502 UINT64 Uint64;

3503

3504 } MSR_PERMEM_CONFIG_INFO_REGISTER;

3505

3506 /**

3507 Index into the list of persistent memory addresses which is accessed when the PERMEM_CTRLR_ID MSR is read/written

3508 **/

3509 #define MSR_PERMEM_CTRLR_INDEX 0x0000015D

3510

3511 typedef union {

3512 ///

3513 /// Individual bit fields

3514 ///

3515 struct {

3516 UINT32 ControllerIndex : 8;

3517

3518 /* Bits[7:0], Access Type=RW, default=None*/

3519

3520 /* Index into persistent memory address list */

3521 UINT32 Rsvd8 : 24;

3522

3523 /* Bits[31:8], Access Type=RW, default=None*/

3524

3525 /* Reserved */

3526 UINT32 Rsvd32 : 31;

3527

3528 /* Bits[62:32], Access Type=RW, default=None*/

3529

3530 /* Reserved */

3531 UINT32 Lock : 1;

3532

3533 /* Bits[63:63], Access Type=RW, default=None*/

3534

3535 /* Reserved */

3536

3537 } Bits;

3538

3539 UINT32 Uint32;

3540 UINT64 Uint64;

3541

3542 } MSR_PERMEM_CTRLR_INDEX_REGISTER;

3543

3544 /**

3545 Read-only MSR that specifies the maximum number of memory controllers on the platform capable of supporting memory persistence

3546 **/

3547 #define MSR_PERMEM_CTRLR_ID 0x0000015E

3548

3549 typedef union {

3550 ///

3551 /// Individual bit fields

3552 ///

3553 struct {

3554 UINT32 Rsvd0 : 6;

3555

3556 /* Bits[5:0], Access Type=RW, default=None*/

3557

3558 /* Reserved */

3559 UINT32 ControllerIdentifier0 : 26;

3560

3561 /* Bits[31:6], Access Type=RW, default=None*/

3562

3563 /*

3564 memory address that uniquely identifies a

3565 persistent memory controller, whose index in

3566 list is specified by PERMEM_CTRLR_INDEX

3567 */

3568 UINT32 ControllerIdentifier1 : 32;

3569

3570 /* Bits[63:32], Access Type=RW, default=None*/

3571

3572 /*

3573 memory address that uniquely identifies a

3574 persistent memory controller, whose index in

3575 list is specified by PERMEM_CTRLR_INDEX

3576 */

3577

3578 } Bits;

3579

3580 UINT32 Uint32;

3581 UINT64 Uint64;

3582

3583 } MSR_PERMEM_CTRLR_ID_REGISTER;

3584 /**

3585 Probe mode MSR, used also in cache flush and segmentation

3586 C6NoSave Candidate

3587 **/

3588 #define MSR_REGISTER_0 0x00000160

3589 /**

3590 Probe mode MSR, used also in PDM flows

3591 C6NoSave Candidate

3592 **/

3593 #define MSR_REGISTER_1 0x00000161

3594 /**

3595 Probe mode MSR, used also in PDM flows

3596 C6NoSave Candidate

3597 **/

3598 #define MSR_REGISTER_2 0x00000162

3599 /**

3600 Probe mode MSR, used also in page a/d assist and vmx flows

3601 C6NoSave Candidate: actually, we'll leave this in the C6 save loop because it's also an MSR

3602 **/

3603 #define MSR_REGISTER_3 0x00000163

3604 /**

3605 Probe mode MSR, used also in PDM and paging flows

3606 C6NoSave Candidate

3607 **/

3608 #define MSR_REGISTER_4 0x00000164

3609 /**

3610 Probe mode MSR, used also in PDM and paging flows

3611 C6NoSave Candidate

3612 **/

3613 #define MSR_REGISTER_5 0x00000165

3614 /**

3615 Probe mode MSR

3616 C6NoSave Candidate

3617 **/

3618 #define MSR_REGISTER_6 0x00000166

3619 /**

3620 Probe mode MSR

3621 C6NoSave Candidate

3622 **/

3623 #define MSR_REGISTER_7 0x00000167

3624 /**

3625 Probe mode MSR

3626 C6NoSave Candidate

3627 **/

3628 #define MSR_REGISTER_8 0x00000168

3629 /**

3630 Probe mode MSR

3631 C6NoSave Candidate

3632 **/

3633 #define MSR_REGISTER_9 0x00000169

3634 /**

3635 Probe mode MSR

3636 C6NoSave Candidate

3637 **/

3638 #define MSR_REGISTER_10 0x0000016A

3639 /**

3640 Probe mode MSR

3641 C6NoSave Candidate

3642 **/

3643 #define MSR_REGISTER_11 0x0000016B

3644 /**

3645 Probe mode MSR

3646 C6NoSave Candidate

3647 **/

3648 #define MSR_REGISTER_12 0x0000016C

3649 /**

3650 Probe mode MSR

3651 C6NoSave Candidate

3652 **/

3653 #define MSR_REGISTER_13 0x0000016D

3654 /**

3655 SCP used by Task Switch and SMI code to save RIP

3656 Probe mode MSR, used also in PDM flows

3657 **/

3658 #define MSR_TASK_SWITCH_OR_SMI_RIP 0x0000016E

3659 /**

3660 Probe mode MSR, used also in task switch

3661 C6NoSave Candidate

3662 **/

3663 #define MSR_TASK_SWITCH_OR_PROBE_MODE_MISC 0x0000016F

3664

3665 /**

3666 SMM revision identifier.[IntelRsvd] REVIEW: Register could be removed if RDMSR and SMM ucode use constants[/IntelRsvd]

3667 **/

3668 #define MSR_P6_CR_SMREVID 0x00000170

3669

3670 typedef union {

3671 ///

3672 /// Individual bit fields

3673 ///

3674 struct {

3675 UINT32 Id : 16;

3676

3677 /* Bits[15:0], Access Type=RW, default=None*/

3678

3679 /* SMM Revision identifier */

3680 UINT32 IoInstrRestart : 1;

3681

3682 /* Bits[16:16], Access Type=RW, default=None*/

3683

3684 /*

3685 If set, IO instruction restart is supported.

3686 [IntelRsvd]NHM will set this bit [/IntelRsvd]

3687 */

3688 UINT32 SmbaseRelocation : 1;

3689

3690 /* Bits[17:17], Access Type=RW, default=None*/

3691

3692 /*

3693 If set, SMRAM base address relocation is

3694 supported. [IntelRsvd]NHM will set this bit

3695 [/IntelRsvd]

3696 */

3697 UINT32 Rsvd18 : 14;

3698

3699 /* Bits[31:18], Access Type=RW, default=None*/

3700

3701 /* Reserved */

3702

3703 } Bits;

3704

3705 UINT32 Uint32;

3706 UINT64 Uint64;

3707

3708 } MSR_P6_CR_SMREVID_REGISTER;

3709 /**

3710 SMM Base register

3711 **/

3712 #define MSR_P6_CR_SMBASE 0x00000171

3713 /**

3714 Used to save PPPE exit reason for probe mode redirection

3715 C6NoSave Candidate

3716 **/

3717 #define MSR_PROBE_MODE_PPPE_REDIRECTION 0x00000172

3718

3719 /**

3720 Probe mode data register result

3721 **/

3722 #define MSR_PROBE_MODE_DR 0x00000173

3723

3724 typedef union {

3725 ///

3726 /// Individual bit fields

3727 ///

3728 struct {

3729 UINT32 PrdLo : 32;

3730

3731 /* Bits[31:0], Access Type=RW, default=0x00000000*/

3732

3733 /*

3734 Probe data register result for lower 32 bits

3735 restrictions : ucode only

3736 */

3737 UINT32 PrdHi : 32;

3738

3739 /* Bits[63:32], Access Type=RW, default=0x00000000*/

3740

3741 /*

3742 Probe data register result for upper 32 bits

3743 restrictions : None

3744 */

3745

3746 } Bits;

3747

3748 UINT32 Uint32;

3749 UINT64 Uint64;

3750

3751 } MSR_PROBE_MODE_DR_REGISTER;

3752

3753 /**

3754 Register that contains the poison and viral bit valid / invalid state.

3755 **/

3756 #define MSR_MCG_CONTAIN 0x00000178

3757

3758 typedef union {

3759 ///

3760 /// Individual bit fields

3761 ///

3762 struct {

3763 UINT32 Pe : 1;

3764

3765 /* Bits[0:0], Access Type=RW_V, default=None*/

3766

3767 /*

3768 Poison Enable - when set to '1' then the

3769 Enhanced Containment Mode feature should be

3770 enabled , when '0' then the behavior should be

3771 legacy behavior.

3772 */

3773 UINT32 EnableViral : 1;

3774

3775 /* Bits[1:1], Access Type=RW_V, default=0x00000000*/

3776

3777 /*

3778 [list] [*]0: (default) legacy behavior [*]1:

3779 Enable Viral Support [/list]

3780 */

3781 UINT32 Rsvd2 : 30;

3782

3783 /* Bits[31:2], Access Type=RO, default=None*/

3784

3785 /* Reserved */

3786

3787 } Bits;

3788

3789 UINT32 Uint32;

3790 UINT64 Uint64;

3791

3792 } MSR_MCG_CONTAIN_REGISTER;

3793

3794 /**

3795 Core SMI Error Source

3796 **/

3797 #define MSR_CORE_SMI_ERR_SRC 0x0000017C

3798

3799 typedef union {

3800 ///

3801 /// Individual bit fields

3802 ///

3803 struct {

3804 UINT32 Rsvd0 : 2;

3805

3806 /* Bits[1:0], Access Type=RW, default=0x00000000*/

3807

3808 /* */

3809 UINT32 Dtlb : 1;

3810

3811 /* Bits[2:2], Access Type=RW, default=0x00000000*/

3812

3813 /* */

3814 UINT32 Mlc : 1;

3815

3816 /* Bits[3:3], Access Type=RW, default=0x00000000*/

3817

3818 /* */

3819 UINT32 Rsvd4 : 28;

3820

3821 /* Bits[31:4], Access Type=RO, default=None*/

3822

3823 /* Reserved */

3824

3825 } Bits;

3826

3827 UINT32 Uint32;

3828 UINT64 Uint64;

3829

3830 } MSR_CORE_SMI_ERR_SRC_REGISTER;

3831

3832 /**

3833 Enhanced MCA Capabilities register

3834 **/

3835 #define MSR_SMM_MCA_CAP 0x0000017D

3836

3837 typedef union {

3838 ///

3839 /// Individual bit fields

3840 ///

3841 struct {

3842 UINT32 BankSupport : 32;

3843

3844 /* Bits[31:0], Access Type=RO_V, default=None*/

3845

3846 /*

3847 One bit per bank. If bit is set, then the

3848 corresponding bank supports enhanced MCA.

3849 */

3850 UINT32 Rsvd32 : 22;

3851

3852 /* Bits[53:32], Access Type=RO_V, default=None*/

3853

3854 /* Reserved */

3855 UINT32 SmmProtMode : 1;

3856

3857 /* Bits[54:54], Access Type=RO_V, default=None*/

3858

3859 /* Set if SMM Protected Mode is supported */

3860 UINT32 ErrorSpoofing : 1;

3861

3862 /* Bits[55:55], Access Type=RO_V, default=None*/

3863

3864 /*

3865 Set if Error Spoofing and Enhanced MCA are

3866 supported

3867 */

3868 UINT32 TargetedSmi : 1;

3869

3870 /* Bits[56:56], Access Type=RO_V, default=None*/

3871

3872 /*

3873 Set to 1 if the thread supports targeted SMI and

3874 the SMM_ENABLE register (MSR 4E1h) is supported.

3875 */

3876 UINT32 SmmCpuSvrstr : 1;

3877

3878 /* Bits[57:57], Access Type=RO_V, default=None*/

3879

3880 /*

3881 Set to 1 if the SAVE/RESTORE feature is

3882 supported and the SMM_FEATURE_CONTROL register

3883 (MSR 4E0h) is supported.

3884 */

3885 UINT32 SmmCodeAccessChk : 1;

3886

3887 /* Bits[58:58], Access Type=RO_V, default=None*/

3888

3889 /*

3890 Set to 1 if the SMM code access check feature is

3891 supported and the SMM_FEATURE_CONTROL register

3892 (MSR 4E0h) is supported.

3893 */

3894 UINT32 LongFlowIndication : 1;

3895

3896 /* Bits[59:59], Access Type=RO_V, default=None*/

3897

3898 /* Set to indicate SMM long flow indicator support */

3899 UINT32 SmmRsvd : 4;

3900

3901 /* Bits[63:60], Access Type=RO_V, default=None*/

3902

3903 /* Reserved */

3904

3905 } Bits;

3906

3907 UINT32 Uint32;

3908 UINT64 Uint64;

3909

3910 } MSR_SMM_MCA_CAP_REGISTER;

3911

3912 /**

3913 Uncore SMI Error Source

3914 **/

3915 #define MSR_UNCORE_SMI_ERR_SRC 0x0000017E

3916

3917 typedef union {

3918 ///

3919 /// Individual bit fields

3920 ///

3921 struct {

3922 UINT32 Rsvd0 : 4;

3923

3924 /* Bits[3:0], Access Type=RO, default=None*/

3925

3926 /* Reserved */

3927 UINT32 McaBankId4 : 1;

3928

3929 /* Bits[4:4], Access Type=RW, default=0x00000000*/

3930

3931 /* */

3932 UINT32 McaBankId5 : 1;

3933

3934 /* Bits[5:5], Access Type=RW, default=0x00000000*/

3935

3936 /* */

3937 UINT32 McaBankId6 : 1;

3938

3939 /* Bits[6:6], Access Type=RW, default=0x00000000*/

3940

3941 /* */

3942 UINT32 McaBankId7 : 1;

3943

3944 /* Bits[7:7], Access Type=RW, default=0x00000000*/

3945

3946 /* */

3947 UINT32 McaBankId8 : 1;

3948

3949 /* Bits[8:8], Access Type=RW, default=0x00000000*/

3950

3951 /* */

3952 UINT32 McaBankId9 : 1;

3953

3954 /* Bits[9:9], Access Type=RW, default=0x00000000*/

3955

3956 /* */

3957 UINT32 McaBankId10 : 1;

3958

3959 /* Bits[10:10], Access Type=RW, default=0x00000000*/

3960

3961 /* */

3962 UINT32 McaBankId11 : 1;

3963

3964 /* Bits[11:11], Access Type=RW, default=0x00000000*/

3965

3966 /* */

3967 UINT32 McaBankId12 : 1;

3968

3969 /* Bits[12:12], Access Type=RW, default=0x00000000*/

3970

3971 /* */

3972 UINT32 McaBankId13 : 1;

3973

3974 /* Bits[13:13], Access Type=RW, default=0x00000000*/

3975

3976 /* */

3977 UINT32 McaBankId14 : 1;

3978

3979 /* Bits[14:14], Access Type=RW, default=0x00000000*/

3980

3981 /* */

3982 UINT32 McaBankId15 : 1;

3983

3984 /* Bits[15:15], Access Type=RW, default=0x00000000*/

3985

3986 /* */

3987 UINT32 McaBankId16 : 1;

3988

3989 /* Bits[16:16], Access Type=RW, default=0x00000000*/

3990

3991 /* */

3992 UINT32 McaBankId17 : 1;

3993

3994 /* Bits[17:17], Access Type=RW, default=0x00000000*/

3995

3996 /* */

3997 UINT32 McaBankId18 : 1;

3998

3999 /* Bits[18:18], Access Type=RW, default=0x00000000*/

4000

4001 /* */

4002 UINT32 McaBankId19 : 1;

4003

4004 /* Bits[19:19], Access Type=RW, default=0x00000000*/

4005

4006 /* */

4007 UINT32 McaBankId20 : 1;

4008

4009 /* Bits[20:20], Access Type=RW, default=0x00000000*/

4010

4011 /* */

4012 UINT32 McaBankId21 : 1;

4013

4014 /* Bits[21:21], Access Type=RW, default=0x00000000*/

4015

4016 /* */

4017 UINT32 McaBankId22 : 1;

4018

4019 /* Bits[22:22], Access Type=RW, default=0x00000000*/

4020

4021 /* */

4022 UINT32 McaBankId23 : 1;

4023

4024 /* Bits[23:23], Access Type=RW, default=0x00000000*/

4025

4026 /* */

4027 UINT32 McaBankId24 : 1;

4028

4029 /* Bits[24:24], Access Type=RW, default=0x00000000*/

4030

4031 /* */

4032 UINT32 McaBankId25 : 1;

4033

4034 /* Bits[25:25], Access Type=RW, default=0x00000000*/

4035

4036 /* */

4037 UINT32 McaBankId26 : 1;

4038

4039 /* Bits[26:26], Access Type=RW, default=0x00000000*/

4040

4041 /* */

4042 UINT32 McaBankId27 : 1;

4043

4044 /* Bits[27:27], Access Type=RW, default=0x00000000*/

4045

4046 /* */

4047 UINT32 McaBankId28 : 1;

4048

4049 /* Bits[28:28], Access Type=RW, default=0x00000000*/

4050

4051 /* */

4052 UINT32 McaBankId29 : 1;

4053

4054 /* Bits[29:29], Access Type=RW, default=0x00000000*/

4055

4056 /* */

4057 UINT32 McaBankId30 : 1;

4058

4059 /* Bits[30:30], Access Type=RW, default=0x00000000*/

4060

4061 /* */

4062 UINT32 McaBankId31 : 1;

4063

4064 /* Bits[31:31], Access Type=RW, default=0x00000000*/

4065

4066 /* */

4067

4068 } Bits;

4069

4070 UINT32 Uint32;

4071 UINT64 Uint64;

4072

4073 } MSR_UNCORE_SMI_ERR_SRC_REGISTER;

4074

4075 /**

4076 [p]A non-architectural, package-scoped MSR intended for use by BIOS. ERROR_CONTROL[4] is a r/w bit that defeatures CMCI.

4077 Storage for this bit is in the UNCORE_SCP_MISC2_CREG[4]. The bit will be saved and restored in C7+ states.[/p]

4078 [p]The reset value for the bit is 0. It will not survive warm reset.[/p]

4079 [p]When MSR 0x17F bit 4 is set, two actions will happen:[/p]

4080 [list]

4081 [*]RDMSR to MCG_CAP will have bit 10 cleared to 0.

4082 [*]WRMSR to MCi_MISC2 registers will clear bits[31:0] in all modes.

4083 [/list]

4084 **/

4085 #define MSR_ERROR_CONTROL 0x0000017F

4086

4087 typedef union {

4088 ///

4089 /// Individual bit fields

4090 ///

4091 struct {

4092 UINT32 Rsvd0 : 4;

4093

4094 /* Bits[3:0], Access Type=RO, default=None*/

4095

4096 /* Reserved */

4097 UINT32 CmciDisable : 1;

4098

4099 /* Bits[4:4], Access Type=RW, default=0x00000000*/

4100

4101 /* When set, will disable CMCI signaling */

4102 UINT32 Rsvd5 : 2;

4103

4104 /* Bits[6:5], Access Type=RO, default=None*/

4105

4106 /* Reserved */

4107 UINT32 LlcEwbSraoPromote : 1;

4108

4109 /* Bits[7:7], Access Type=RW, default=0x00000000*/

4110

4111 /*

4112 For LLC EWB errors, allows EWB errors to be

4113 promoted to SRAO from UCNA

4114 */

4115 UINT32 Rsvd8 : 24;

4116

4117 /* Bits[31:8], Access Type=RO, default=None*/

4118

4119 /* Reserved */

4120 UINT32 Rsvd32 : 32;

4121

4122 /* Bits[63:32], Access Type=RO, default=None*/

4123

4124 /* Reserved */

4125

4126 } Bits;

4127

4128 UINT32 Uint32;

4129 UINT64 Uint64;

4130

4131 } MSR_ERROR_CONTROL_REGISTER;

4132

4133 /**

4134 This 'flexible boot' register is written by BIOS in order to modify the maximum non-turbo ratio on the next reset.

4135 **/

4136 #define MSR_FLEX_RATIO 0x00000194

4137

4138 typedef union {

4139 ///

4140 /// Individual bit fields

4141 ///

4142 struct {

4143 UINT32 OcExtraVoltage : 8;

4144

4145 /* Bits[7:0], Access Type=RWS, default=0x00000000*/

4146

4147 /*

4148 Depracated. Extra voltage to be used for

4149 Overclocking.The voltage is defined in units of

4150 1/256 Volts.

4151 */

4152 UINT32 FlexRatio : 8;

4153

4154 /* Bits[15:8], Access Type=RWS, default=0x00000000*/

4155

4156 /*

4157 When enabled by the ENABLE bit, the value in

4158 this field sets the maximum non-turbo ratio. If

4159 this value is greater than the maximum ratio set

4160 by hardware, this field is silently ignored. The

4161 override value applies on the next reset and not

4162 immediately.

4163 */

4164 UINT32 Enable : 1;

4165

4166 /* Bits[16:16], Access Type=RWS, default=0x00000000*/

4167

4168 /*

4169 When set to 1, indicates that the value

4170 programmed in FLEX_RATIO field will be used to

4171 override the maximum non-turbo ratio on next

4172 reboot. When this bit is set to zero, all writes

4173 to FLEX_RATIO field are silently ignored.

4174 */

4175 UINT32 OcBins : 3;

4176

4177 /* Bits[19:17], Access Type=RW_L, default=0x00000000*/

4178

4179 /*

4180 [p]If overclocking is enabled, this field

4181 contains how many bins of Core ratio

4182 overclocking are supported.[/p] [p]The encoding

4183 is:[/p] [list] [*]0: No Core overclocking is

4184 supported [*]1-6: Max 1-6 bins of Core ratio

4185 overclocking is supported. [*]7: Unlimited

4186 [/list] [p]If overclocking is disabled then this

4187 field should be ignored.[/p] [p]Overclocking

4188 bins imply programming the TURBO_RATIO_LIMIT MSR

4189 above its hardware default value.[/p]

4190 Overclocking enabled/disabled can be checked in

4191 CAPID0_B_0_0_0_PCI.OC_ENABLED.

4192 */

4193 UINT32 OcLock : 1;

4194

4195 /* Bits[20:20], Access Type=RW1S, default=0x00000000*/

4196

4197 /*

4198 If set, all writes to overclocking limits are

4199 disabled. Anyway modifications to overclocking

4200 limits prior to setting this lock bit are

4201 maintained. This field may only be set by

4202 software and it is cleared by hardware only on

4203 reset.

4204 */

4205 UINT32 Rsvd21 : 11;

4206

4207 /* Bits[31:21], Access Type=RO, default=None*/

4208

4209 /* Reserved */

4210 UINT32 Rsvd32 : 32;

4211

4212 /* Bits[63:32], Access Type=RO, default=None*/

4213

4214 /* Reserved */

4215

4216 } Bits;

4217

4218 UINT32 Uint32;

4219 UINT64 Uint64;

4220

4221 } MSR_FLEX_RATIO_REGISTER;

4222 /**

4223 Deprecated. The MSR always return zero.

4224 **/

4225 #define MSR_MSR_THERM2_CTL 0x0000019D

4226

4227 /**

4228 Temperature margin in PECI temperature counts from the thermal profile specification. Platform fan control SW is expected to read therm_margin value to control fan or blower speed.

4229 **/

4230 #define MSR_PACKAGE_THERM_MARGIN 0x000001A1

4231

4232 typedef union {

4233 ///

4234 /// Individual bit fields

4235 ///

4236 struct {

4237 UINT32 ThermMargin : 16;

4238

4239 /* Bits[15:0], Access Type=RO_V, default=0x00007F00*/

4240

4241 /*

4242 Temperature margin in PECI temperature counts

4243 from the thermal profile specification.

4244 THERM_MARGIN is in 2's complement format (8.8

4245 format where MSB equals 1 Sign bit + 7 bits of

4246 integer temperature value and the LSB equals 8

4247 precison bits of temperature value). A value of

4248 zero indicates the hottest CPU die temperature

4249 is on the thermal profile line. A negative value

4250 indicates gap to the thermal profile that

4251 platform SW should increase cooling capacity. A

4252 sustained negative value should be avoided as it

4253 may impact part reliability.

4254 */

4255 UINT32 Rsvd16 : 16;

4256

4257 /* Bits[31:16], Access Type=RO, default=None*/

4258

4259 /* Reserved */

4260

4261 } Bits;

4262

4263 UINT32 Uint32;

4264 UINT64 Uint64;

4265

4266 } MSR_PACKAGE_THERM_MARGIN_REGISTER;

4267

4268 /**

4269 Legacy register holding temperature related constants for Platform use.

4270 **/

4271 #define MSR_TEMPERATURE_TARGET 0x000001A2

4272

4273 typedef union {

4274 ///

4275 /// Individual bit fields

4276 ///

4277 struct {

4278 UINT32 TccOffsetTimeWindow : 7;

4279

4280 /* Bits[6:0], Access Type=RO_V, default=0x00000000*/

4281

4282 /* Describes the RATL averaging time window */

4283 UINT32 TccOffsetClampingBit : 1;

4284

4285 /* Bits[7:7], Access Type=RO_V, default=0x00000000*/

4286

4287 /* When enabled will allow RATL throttling below P1 */

4288 UINT32 FanTempTargetOfst : 8;

4289

4290 /* Bits[15:8], Access Type=RW_L, default=0x00000000*/

4291

4292 /*

4293 Fan Temperature Target Offset (a.k.a. T-Control)

4294 indicates the relative offset from the Thermal

4295 Monitor Trip Temperature at which fans should be

4296 engaged.

4297 */

4298 UINT32 RefTemp : 8;

4299

4300 /* Bits[23:16], Access Type=RW_L, default=0x00000000*/

4301

4302 /*

4303 This field indicates the maximum junction

4304 temperature, also referred to as the Throttle

4305 Temperature, TCC Activation Temperature or

4306 Prochot Temperature. This is the temperature at

4307 which the Adaptive Thermal Monitor is activated.

4308 */

4309 UINT32 TjMaxTccOffset : 6;

4310

4311 /* Bits[29:24], Access Type=RO_V, default=0x00000000*/

4312

4313 /*

4314 Temperature offset in degrees (C) from the TJ

4315 Max. Used for throttling temperature. Will not

4316 impact temperature reading. If offset is allowed

4317 and set - the throttle will occur and reported

4318 at lower then Tj_max.

4319 */

4320 UINT32 Rsvd30 : 1;

4321

4322 /* Bits[30:30], Access Type=RO, default=None*/

4323

4324 /* Reserved */

4325 UINT32 Locked : 1;

4326

4327 /* Bits[31:31], Access Type=RW_KL, default=0x00000000*/

4328

4329 /*

4330 When set, this entire register becomes read-

4331 only.

4332 */

4333

4334 } Bits;

4335

4336 UINT32 Uint32;

4337 UINT64 Uint64;

4338

4339 } MSR_TEMPERATURE_TARGET_REGISTER;

4340

4341 /**

4342 Miscellaneous Feature Control Register

4343 **/

4344 #define MSR_MISC_FEATURE_CONTROL 0x000001A4

4345

4346 typedef union {

4347 ///

4348 /// Individual bit fields

4349 ///

4350 struct {

4351 UINT32 MlcStreamerPrefetchDisable : 1;

4352

4353 /* Bits[0:0], Access Type=RW, default=0x00000000*/

4354

4355 /* Set to disable MLC streamer prefetcher. */

4356 UINT32 MlcSpatialPrefetchDisable : 1;

4357

4358 /* Bits[1:1], Access Type=RW, default=0x00000000*/

4359

4360 /* Set to disable MLC spatial prefetcher. */

4361 UINT32 DcuStreamerPrefetchDisable : 1;

4362

4363 /* Bits[2:2], Access Type=RW, default=0x00000000*/

4364

4365 /* Set to disable DCU streamer prefetcher. */

4366 UINT32 DcuIpPrefetchDisable : 1;

4367

4368 /* Bits[3:3], Access Type=RW, default=0x00000000*/

4369

4370 /* Set to disable DCU IP prefetcher. */

4371 UINT32 Rsvd4 : 1;

4372

4373 /* Bits[4:4], Access Type=RO, default=None*/

4374

4375 /* Reserved */

4376 UINT32 Rsvd5 : 1;

4377

4378 /* Bits[5:5], Access Type=RW, default=0x00000000*/

4379

4380 /* Reserved */

4381 UINT32 Rsvd6 : 5;

4382

4383 /* Bits[10:6], Access Type=RO, default=None*/

4384

4385 /* Reserved */

4386 UINT32 DisableThreeStrikeCnt : 1;

4387

4388 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4389

4390 /*

4391 Prevent the Three Strike Counter from

4392 incrementing

4393 */

4394 UINT32 Rsvd12 : 20;

4395

4396 /* Bits[31:12], Access Type=RW, default=0x00000000*/

4397

4398 /* Reserved */

4399

4400 } Bits;

4401

4402 UINT32 Uint32;

4403 UINT64 Uint64;

4404

4405 } MSR_MISC_FEATURE_CONTROL_REGISTER;

4406

4407 /**

4408 MSR for thread specific defeature

4409 **/

4410 #define MSR_THREAD_SW_DEFEATURE 0x000001A8

4411

4412 typedef union {

4413 ///

4414 /// Individual bit fields

4415 ///

4416 struct {

4417 UINT32 XinitDisable : 1;

4418

4419 /* Bits[0:0], Access Type=RW, default=0x00000000*/

4420

4421 /* When this bit set: READ_XINIT_AS_NON_INIT */

4422 UINT32 XmodifiedDisable : 1;

4423

4424 /* Bits[1:1], Access Type=RW, default=0x00000000*/

4425

4426 /* When this bit set: READ_XMODIFIED_AS_MODIFIED */

4427 UINT32 Rsvd2 : 30;

4428

4429 /* Bits[31:2], Access Type=RO, default=None*/

4430

4431 /* Reserved */

4432

4433 } Bits;

4434

4435 UINT32 Uint32;

4436 UINT64 Uint64;

4437

4438 } MSR_THREAD_SW_DEFEATURE_REGISTER;

4439

4440 /**

4441 Miscellaneous Power Management control; Various model specific features enumeration.

4442 **/

4443 #define MSR_MISC_PWR_MGMT 0x000001AA

4444

4445 typedef union {

4446 ///

4447 /// Individual bit fields

4448 ///

4449 struct {

4450 UINT32 SinglePctlEn : 1;

4451

4452 /* Bits[0:0], Access Type=RW, default=0x00000000*/

4453

4454 /*

4455 Single_PCTL: When set (1), will cause PST

4456 commands (writes to IA32_PERF_CTL) from any

4457 cores to set the P-state target (no

4458 coordination). This mean that the last thread

4459 that writes the P-state request, is the dominant

4460 one. If not set this mean that coordination

4461 between all the thread requests will be

4462 initiated and the resolved result will dominant.

4463 Default = 0 (disabled).

4464 */

4465 UINT32 Rsvd1 : 5;

4466

4467 /* Bits[5:1], Access Type=RO, default=None*/

4468

4469 /* Reserved */

4470 UINT32 EnableHwp : 1;

4471

4472 /* Bits[6:6], Access Type=RW, default=0x00000000*/

4473

4474 /*

4475 Setting this bit (1) will cause the HWP Base

4476 feature bit to report as present (1) in CPUID;

4477 clearing this bit will cause CPUID to report the

4478 feature as non-present (0). This bit can be set

4479 only if IA32_PM_ENABLE (HWP_Enable) is clear(0).

4480 */

4481 UINT32 EnableHwpInterrupt : 1;

4482

4483 /* Bits[7:7], Access Type=RW, default=0x00000000*/

4484

4485 /*

4486 RW Setting this bit (1) will cause the HWP

4487 CPUID[6].EAX[8] Notifications feature bit to

4488 report as present (1); clearing will report as

4489 non-present (0). This bit can be set only if

4490 IA32_PM_ENABLE (HWP_Enable) is clear(0) and

4491 MISC_PWR_MGT[6] is set.

4492 */

4493 UINT32 EnableOutOfBandAutonomous : 1;

4494

4495 /* Bits[8:8], Access Type=RW, default=0x00000000*/

4496

4497 /*

4498 Setting this bit (1) will enable HWP with its

4499 default settings but without the ability for

4500 software to access HWP MSRs. This bit can be set

4501 only if Enumerate HWP bit is clear,

4502 MISC_PWR_MGT[6] (0).

4503 */

4504 UINT32 EnableSdcOob : 1;

4505

4506 /* Bits[9:9], Access Type=RW, default=0x00000000*/

4507

4508 /*

4509 RW Setting this bit (1) will enable HDC with its

4510 default settings but without the ability for

4511 software to access IA32_PKG_HDC_CTL,

4512 IA32_PM_CTL1 and IA32_THREAD_STALL_COUNTER MSR.

4513 This bit can be set only if Enumerate HDC bit is

4514 clear (0). Default = 0.

4515 */

4516 UINT32 EnableSdc : 1;

4517

4518 /* Bits[10:10], Access Type=RW, default=0x00000000*/

4519

4520 /*

4521 This bit is reflected in CPUID[6].EAX[13] to

4522 represent HDC as present as well the I

4523 IA32_PKG_HDC_CTL, IA32_PM_CTL1 and

4524 IA32_THREAD_STALL_COUNTER MSRs. (default value

4525 is according to HDC-enabled-fuse)

4526 */

4527 UINT32 SdcOobCapable : 1;

4528

4529 /* Bits[11:11], Access Type=RW, default=0x00000000*/

4530

4531 /*

4532 Read-Only bit in which RDMSR reflects the

4533 ENABLE_SDC_OOB fuse value for BIOS to know

4534 whether it can ENABLE_SDC_OOB

4535 */

4536 UINT32 EnableHwpEpp : 1;

4537

4538 /* Bits[12:12], Access Type=RW, default=0x00000000*/

4539

4540 /*

4541 Enable EPP, RW Setting this bit (1) will cause

4542 the HWP CPUID[6].EAX[10] Energy Performance

4543 Preference bit to report as present (1);

4544 clearing will report as non-present (0). This

4545 bit can be set only if IA32_PM_ENABLE

4546 (HWP_Enable) is clear(0) and MISC_PWR_MGT[6] is

4547 set.

4548 */

4549 UINT32 Lock : 1;

4550

4551 /* Bits[13:13], Access Type=RW, default=0x00000000*/

4552

4553 /*

4554 Set this bit will lock this MSR until the next

4555 reset

4556 */

4557 UINT32 Rsvd14 : 4;

4558

4559 /* Bits[17:14], Access Type=RO, default=None*/

4560

4561 /* Reserved */

4562 UINT32 PlatPStateCtrl : 1;

4563

4564 /* Bits[18:18], Access Type=RW, default=0x00000000*/

4565

4566 /*

4567 Adding for Dell request to add

4568 platform_p_stat_ctrl bit 18 to 0x1aa msr

4569 */

4570 UINT32 Rsvd19 : 3;

4571

4572 /* Bits[21:19], Access Type=RO, default=None*/

4573

4574 /* Reserved */

4575 UINT32 LockThermInt : 1;

4576

4577 /* Bits[22:22], Access Type=RW, default=0x00000000*/

4578

4579 /*

4580 Lock_Therm_Int - Ties thermal interrupts from

4581 all cores. If set, then a thermal interrupt on

4582 one core is routed to all cores. A value = 0

4583 indicates not active, and a value = 1 indicates

4584 active.

4585 */

4586 UINT32 Rsvd23 : 9;

4587

4588 /* Bits[31:23], Access Type=RO, default=None*/

4589

4590 /* Reserved */

4591 UINT32 Rsvd32 : 32;

4592

4593 /* Bits[63:32], Access Type=RO, default=None*/

4594

4595 /* Reserved */

4596

4597 } Bits;

4598

4599 UINT32 Uint32;

4600 UINT64 Uint64;

4601

4602 } MSR_MISC_PWR_MGMT_REGISTER;

4603

4604 #if 0 // This definition is out of date. Prefer to use the definition in CpuRegs.h.

4605 /**

4606 This MSR indicates the factory configured values for of 1-core, 2-core, 3-core and 4-core turbo ratio limits for all processors and also allows configuration of those values on parts with PLATFORM_INFO MSR 0CEh[28]==1.

4607 **/

4608 #define MSR_TURBO_RATIO_LIMIT 0x000001AD

4609

4610 typedef union {

4611 ///

4612 /// Individual bit fields

4613 ///

4614 struct {

4615 UINT32 MaxTurbo1Core : 8;

4616

4617 /* Bits[7:0], Access Type=RW_L, default=0x00000000*/

4618

4619 /* Maximum turbo ratio limit with 1 core active. */

4620 UINT32 MaxTurbo2Cores : 8;

4621

4622 /* Bits[15:8], Access Type=RW_L, default=0x00000000*/

4623

4624 /* Maximum turbo ratio limit with 2 cores active. */

4625 UINT32 MaxTurbo3Cores : 8;

4626

4627 /* Bits[23:16], Access Type=RW_L, default=0x00000000*/

4628

4629 /* Maximum turbo ratio limit with 3 cores active. */

4630 UINT32 MaxTurbo4Cores : 8;

4631

4632 /* Bits[31:24], Access Type=RW_L, default=0x00000000*/

4633

4634 /* Maximum turbo ratio limit with 4 cores active. */

4635 UINT32 Rsvd32 : 32;

4636

4637 /* Bits[63:32], Access Type=RO, default=None*/

4638

4639 /* Reserved */

4640

4641 } Bits;

4642

4643 UINT32 Uint32;

4644 UINT64 Uint64;

4645

4646 } MSR_TURBO_RATIO_LIMIT_REGISTER;

4647 #endif

4648

4649 /**

4650 This register defines the active core ranges for each frequency point

4651 NUMCORE[0:7] must be populated in ascending order.

4652 NUMCORE[i+1] must be greater than NUMCORE[i]

4653 Entries with NUMCORE[i] == 0 will be ignored

4654 The last valid entry must have NUMCORE >= the number of cores in the SKU

4655 If any of the rules above are broken, we will silently reject the configuration.

4656 **/

4657 #define MSR_TURBO_RATIO_LIMIT_CORES 0x000001AE

4658

4659 typedef union {

4660 ///

4661 /// Individual bit fields

4662 ///

4663 struct {

4664 UINT32 Numcore0 : 8;

4665

4666 /* Bits[7:0], Access Type=RW, default=0x00000000*/

4667

4668 /*

4669 defines the active core ranges for each

4670 frequency point.

4671 */

4672 UINT32 Numcore1 : 8;

4673

4674 /* Bits[15:8], Access Type=RW, default=0x00000000*/

4675

4676 /*

4677 defines the active core ranges for each

4678 frequency point.

4679 */

4680 UINT32 Numcore2 : 8;

4681

4682 /* Bits[23:16], Access Type=RW, default=0x00000000*/

4683

4684 /*

4685 defines the active core ranges for each

4686 frequency point.

4687 */

4688 UINT32 Numcore3 : 8;

4689

4690 /* Bits[31:24], Access Type=RW, default=0x00000000*/

4691

4692 /*

4693 defines the active core ranges for each

4694 frequency point.

4695 */

4696 UINT32 Numcore4 : 8;

4697

4698 /* Bits[39:32], Access Type=RW, default=0x00000000*/

4699

4700 /*

4701 defines the active core ranges for each

4702 frequency point.

4703 */

4704 UINT32 Numcore5 : 8;

4705

4706 /* Bits[47:40], Access Type=RW, default=0x00000000*/

4707

4708 /*

4709 defines the active core ranges for each

4710 frequency point.

4711 */

4712 UINT32 Numcore6 : 8;

4713

4714 /* Bits[55:48], Access Type=RW, default=0x00000000*/

4715

4716 /*

4717 defines the active core ranges for each

4718 frequency point.

4719 */

4720 UINT32 Numcore7 : 8;

4721

4722 /* Bits[63:56], Access Type=RW, default=0x00000000*/

4723

4724 /*

4725 defines the active core ranges for each

4726 frequency point.

4727 */

4728

4729 } Bits;

4730

4731 UINT32 Uint32;

4732 UINT64 Uint64;

4733

4734 } MSR_TURBO_RATIO_LIMIT_CORES_REGISTER;

4735

4736 /**

4737 Current Logical Processor PM Meta Data and CTC data

4738 **/

4739 #define MSR_HW_GET_LP_PM_META_DATA 0x000001C2

4740

4741 typedef union {

4742 ///

4743 /// Individual bit fields

4744 ///

4745 struct {

4746 UINT32 LpId : 10;

4747

4748 /* Bits[9:0], Access Type=RO_V, default=None*/

4749

4750 /* LP ID */

4751 UINT32 Rsvd10 : 22;

4752

4753 /* Bits[31:10], Access Type=RO_V, default=None*/

4754

4755 /* Reserved */

4756 UINT32 AbsoluteTimeUponRead : 24;

4757

4758 /* Bits[55:32], Access Type=RO_V, default=None*/

4759

4760 /* Absolute time upon read */

4761 UINT32 Rsvd56 : 8;

4762

4763 /* Bits[63:56], Access Type=RO_V, default=None*/

4764

4765 /* Reserved */

4766

4767 } Bits;

4768

4769 UINT32 Uint32;

4770 UINT64 Uint64;

4771

4772 } MSR_HW_GET_LP_PM_META_DATA_REGISTER;

4773

4774 /**

4775 Deliver the LP PM Meta Data into the H/W

4776 **/

4777 #define MSR_HW_SET_LP_PM_META_DATA 0x000001C3

4778

4779 typedef union {

4780 ///

4781 /// Individual bit fields

4782 ///

4783 struct {

4784 UINT32 SetPmMetaData0 : 32;

4785

4786 /* Bits[31:0], Access Type=RO_V, default=None*/

4787

4788 /* Set PM Meta Data */

4789 UINT32 SetPmMetaData1 : 24;

4790

4791 /* Bits[55:32], Access Type=RO_V, default=None*/

4792

4793 /* Set PM Meta Data */

4794 UINT32 OsScenario : 4;

4795

4796 /* Bits[59:56], Access Type=RO_V, default=None*/

4797

4798 /* OS Scenario */

4799 UINT32 Rsvd60 : 4;

4800

4801 /* Bits[63:60], Access Type=RO_V, default=None*/

4802

4803 /* Reserved */

4804

4805 } Bits;

4806

4807 UINT32 Uint32;

4808 UINT64 Uint64;

4809

4810 } MSR_HW_SET_LP_PM_META_DATA_REGISTER;

4811

4812 /**

4813 This MSR return the status of debug resources (Used to be in MISC_ENABLES MSR).

4814 **/

4815 #define MSR_DEBUG_RESOURCE_STATUS 0x000001C6

4816

4817 typedef union {

4818 ///

4819 /// Individual bit fields

4820 ///

4821 struct {

4822 UINT32 DebugDrxAvailable : 1;

4823

4824 /* Bits[0:0], Access Type=RO_V, default=None*/

4825

4826 /*

4827 Read-only bit. Inverted

4828 P6_CR_ICECTLPMR[PRESERVE_DEBUG_RESOURCES]

4829 */

4830 UINT32 DebugAvailable : 1;

4831

4832 /* Bits[1:1], Access Type=RO_V, default=None*/

4833

4834 /*

4835 Read-only bit. Inverted

4836 P6_CR_ICECTLPMR[PRESERVE_LBR_RESOURCES]

4837 */

4838 UINT32 Rsvd2 : 30;

4839

4840 /* Bits[31:2], Access Type=RO, default=None*/

4841

4842 /* Reserved */

4843

4844 } Bits;

4845

4846 UINT32 Uint32;

4847 UINT64 Uint64;

4848

4849 } MSR_DEBUG_RESOURCE_STATUS_REGISTER;

4850

4851 /**

4852 NHM creg to filter LBR writes

4853 **/

4854 #define MSR_LBR_SELECT 0x000001C8

4855

4856 typedef union {

4857 ///

4858 /// Individual bit fields

4859 ///

4860 struct {

4861 UINT32 CplEq0 : 1;

4862

4863 /* Bits[0:0], Access Type=RW, default=None*/

4864

4865 /* filter out ring 0 branches */

4866 UINT32 CplNeq0 : 1;

4867

4868 /* Bits[1:1], Access Type=RW, default=None*/

4869

4870 /* filter out non-ring 0 branches */

4871 UINT32 Jcc : 1;

4872

4873 /* Bits[2:2], Access Type=RW, default=None*/

4874

4875 /* filter out taken conditional branches */

4876 UINT32 NearRelCall : 1;

4877

4878 /* Bits[3:3], Access Type=RW, default=None*/

4879

4880 /* filter out near relative calls */

4881 UINT32 NearIndirectCall : 1;

4882

4883 /* Bits[4:4], Access Type=RW, default=None*/

4884

4885 /* filter out near indirect calls */

4886 UINT32 NearRet : 1;

4887

4888 /* Bits[5:5], Access Type=RW, default=None*/

4889

4890 /* filter out near returns */

4891 UINT32 NearIndirectJmp : 1;

4892

4893 /* Bits[6:6], Access Type=RW, default=None*/

4894

4895 /* filter out near unconditional indirect jumps */

4896 UINT32 NearRelJmp : 1;

4897

4898 /* Bits[7:7], Access Type=RW, default=None*/

4899

4900 /* filter out near unconditional relative branches */

4901 UINT32 FarBranch : 1;

4902

4903 /* Bits[8:8], Access Type=RW, default=None*/

4904

4905 /* filter out far branches */

4906 UINT32 CallStack : 1;

4907

4908 /* Bits[9:9], Access Type=RW, default=None*/

4909

4910 /* enable LBR to only collect calls */

4911 UINT32 Rsvd10 : 22;

4912

4913 /* Bits[31:10], Access Type=RO, default=None*/

4914

4915 /* Reserved */

4916

4917 } Bits;

4918

4919 UINT32 Uint32;

4920 UINT64 Uint64;

4921

4922 } MSR_LBR_SELECT_REGISTER;

4923

4924 /**

4925 LBR creg that holds the TOS value

4926 **/

4927 #define MSR_LBR_TOS 0x000001C9

4928

4929 typedef union {

4930 ///

4931 /// Individual bit fields

4932 ///

4933 struct {

4934 UINT32 Tos : 5;

4935

4936 /* Bits[4:0], Access Type=RW_V, default=None*/

4937

4938 /* LBR TOS */

4939 UINT32 Rsvd5 : 27;

4940

4941 /* Bits[31:5], Access Type=RO, default=None*/

4942

4943 /* Reserved */

4944

4945 } Bits;

4946

4947 UINT32 Uint32;

4948 UINT64 Uint64;

4949

4950 } MSR_LBR_TOS_REGISTER;

4951

4952 /**

4953 LAST_BRANCH LBR MSR that holds non-IP information

4954 **/

4955 #define MSR_LAST_BRANCH_INFO 0x000001DA

4956

4957 typedef union {

4958 ///

4959 /// Individual bit fields

4960 ///

4961 struct {

4962 UINT32 CycleCount : 16;

4963

4964 /* Bits[15:0], Access Type=RO_V, default=None*/

4965

4966 /* core-clocks elapsed since last LBR array update */

4967 UINT32 Rsvd16 : 16;

4968

4969 /* Bits[31:16], Access Type=RO, default=None*/

4970

4971 /* Reserved */

4972 UINT32 Rsvd32 : 29;

4973

4974 /* Bits[60:32], Access Type=RO, default=None*/

4975

4976 /* Reserved */

4977 UINT32 HleAbort : 1;

4978

4979 /* Bits[61:61], Access Type=RO_V, default=None*/

4980

4981 /* HLE/+ TX Abort occured */

4982 UINT32 InTx : 1;

4983

4984 /* Bits[62:62], Access Type=RO_V, default=None*/

4985

4986 /* Executing in HLE/+ TX */

4987 UINT32 Mispred : 1;

4988

4989 /* Bits[63:63], Access Type=RO_V, default=None*/

4990

4991 /* Misprediction bit */

4992

4993 } Bits;

4994

4995 UINT32 Uint32;

4996 UINT64 Uint64;

4997

4998 } MSR_LAST_BRANCH_INFO_REGISTER;

4999

5000 /**

5001 Top of LBR Stack

5002 **/

5003 #define MSR_LAST_BRANCH_FROM_IP 0x000001DB

5004

5005 typedef union {

5006 ///

5007 /// Individual bit fields

5008 ///

5009 struct {

5010 UINT32 Data0 : 32;

5011

5012 /* Bits[31:0], Access Type=RO_V, default=None*/

5013

5014 /* FROM LBR at Top of stack */

5015 UINT32 Data1 : 16;

5016

5017 /* Bits[47:32], Access Type=RO_V, default=None*/

5018

5019 /* FROM LBR at Top of stack */

5020 UINT32 SignExt : 16;

5021

5022 /* Bits[63:48], Access Type=RO_V, default=None*/

5023

5024 /* sign extension of bit 47 */

5025

5026 } Bits;

5027

5028 UINT32 Uint32;

5029 UINT64 Uint64;

5030

5031 } MSR_LAST_BRANCH_FROM_IP_REGISTER;

5032

5033 /**

5034 Top of LBR Stack

5035 **/

5036 #define MSR_LAST_BRANCH_TO_IP 0x000001DC

5037

5038 typedef union {

5039 ///

5040 /// Individual bit fields

5041 ///

5042 struct {

5043 UINT32 Data0 : 32;

5044

5045 /* Bits[31:0], Access Type=RO_V, default=None*/

5046

5047 /* TO LBR at top of stack */

5048 UINT32 Data1 : 16;

5049

5050 /* Bits[47:32], Access Type=RO_V, default=None*/

5051

5052 /* TO LBR at top of stack */

5053 UINT32 SignExt : 16;

5054

5055 /* Bits[63:48], Access Type=RO_V, default=None*/

5056

5057 /* sign extension of bit 47 */

5058

5059 } Bits;

5060

5061 UINT32 Uint32;

5062 UINT64 Uint64;

5063

5064 } MSR_LAST_BRANCH_TO_IP_REGISTER;

5065

5066 /**

5067 Last Exeception Record

5068 **/

5069 #define MSR_LAST_INT_FROM_IP 0x000001DD

5070

5071 typedef union {

5072 ///

5073 /// Individual bit fields

5074 ///

5075 struct {

5076 UINT32 LoData : 32;

5077

5078 /* Bits[31:0], Access Type=RW, default=None*/

5079

5080 /* low FROM addr of Last Exeception Record */

5081 UINT32 HiData : 25;

5082

5083 /* Bits[56:32], Access Type=RW, default=None*/

5084

5085 /* high FROM addr of Last Exeception Record */

5086 UINT32 CycleCount : 3;

5087

5088 /* Bits[59:57], Access Type=RO_V, default=None*/

5089

5090 /* 3 MSBs of the cycle counter */

5091 UINT32 CycCtrMode : 1;

5092

5093 /* Bits[60:60], Access Type=RO_V, default=None*/

5094

5095 /* cycle counter mode */

5096 UINT32 HleAbort : 1;

5097

5098 /* Bits[61:61], Access Type=RW, default=None*/

5099

5100 /* TX Abort occured */

5101 UINT32 InTx : 1;

5102

5103 /* Bits[62:62], Access Type=RW, default=None*/

5104

5105 /* ROB is in TX */

5106 UINT32 Mispred : 1;

5107

5108 /* Bits[63:63], Access Type=RW, default=None*/

5109

5110 /* MBr was mispredicted */

5111

5112 } Bits;

5113

5114 UINT32 Uint32;

5115 UINT64 Uint64;

5116

5117 } MSR_LAST_INT_FROM_IP_REGISTER;

5118

5119 /**

5120 Last Exeception Record

5121 **/

5122 #define MSR_LAST_INT_TO_IP 0x000001DE

5123

5124 typedef union {

5125 ///

5126 /// Individual bit fields

5127 ///

5128 struct {

5129 UINT32 LoData : 32;

5130

5131 /* Bits[31:0], Access Type=RW, default=None*/

5132

5133 /* low TO addr of Last Exeception Record */

5134 UINT32 HiData : 25;

5135

5136 /* Bits[56:32], Access Type=RW, default=None*/

5137

5138 /*

5139 high TO addr of Last Exeception Record. If VAPA

5140 is fuse-disabled, then bits [56:48] are also

5141 part of the CYCLE_COUNT

5142 */

5143 UINT32 CycleCount : 7;

5144

5145 /* Bits[63:57], Access Type=RW, default=None*/

5146

5147 /* Elapsed cycle counter from previous branch */

5148

5149 } Bits;

5150

5151 UINT32 Uint32;

5152 UINT64 Uint64;

5153

5154 } MSR_LAST_INT_TO_IP_REGISTER;

5155

5156 /**

5157 Probe mode control and status register. 16 bit. (Mrm roctlregc/roctlregd/icectlpmrSM306L)

5158 **/

5159 #define MSR_ICECTLPMR 0x000001DF

5160

5161 typedef union {

5162 ///

5163 /// Individual bit fields

5164 ///

5165 struct {

5166 UINT32 Ir : 1;

5167

5168 /* Bits[0:0], Access Type=RW, default=0x00000000*/

5169

5170 /* ICECTLIR: Interrupt Redirection */

5171 UINT32 Urdmsr : 1;

5172

5173 /* Bits[1:1], Access Type=RW, default=0x00000000*/

5174

5175 /* ICECTLURDMSR: User Mode Access to Performance */

5176 UINT32 Pmen : 1;

5177

5178 /* Bits[2:2], Access Type=RO_V, default=0x00000000*/

5179

5180 /* ICECTLPMEN: ProbeMode Enabled */

5181 UINT32 PirStt : 1;

5182

5183 /* Bits[3:3], Access Type=RO_V, default=0x00000000*/

5184

5185 /* ICECTLPIR: Submit Probe Instruction Reg status */

5186 UINT32 PmIs : 1;

5187

5188 /* Bits[4:4], Access Type=RW, default=0x00000000*/

5189

5190 /* ICECTLPM_IS: Probe Mode Instruction Status */

5191 UINT32 PmMce : 1;

5192

5193 /* Bits[5:5], Access Type=RW, default=0x00000000*/

5194

5195 /* ICECTLPM_MCE: Machine Check Enabled */

5196 UINT32 ShutdownBit : 1;

5197

5198 /* Bits[6:6], Access Type=RW, default=0x00000000*/

5199

5200 /* Reserved. Not used in PM */

5201 UINT32 HaltBit : 1;

5202

5203 /* Bits[7:7], Access Type=RW, default=0x00000000*/

5204

5205 /* Reserved. Not used in PM */

5206 UINT32 PmInitBit : 1;

5207

5208 /* Bits[8:8], Access Type=RW, default=0x00000000*/

5209

5210 /* ICECTL_PM_INIT_BIT_POS: Enter Probe Mode on INIT */

5211 UINT32 PmMcEnBit : 1;

5212

5213 /* Bits[9:9], Access Type=RW, default=0x00000000*/

5214

5215 /* ICECTL_PM_MC_EN_BIT_POS: Enter PM on enabled MC */

5216 UINT32 PmSmmEnterBit : 1;

5217

5218 /* Bits[10:10], Access Type=RW, default=0x00000000*/

5219

5220 /* ICECTL_PM_SMM_ENTER_BIT_POS */

5221 UINT32 PmSmmExitBit : 1;

5222

5223 /* Bits[11:11], Access Type=RW, default=0x00000000*/

5224

5225 /* ICECTL_PM_SMM_EXIT_BIT_POS */

5226 UINT32 Res1Low : 1;

5227

5228 /* Bits[12:12], Access Type=RW, default=0x00000000*/

5229

5230 /* ICECTLRES1_LOW: Reserved */

5231 UINT32 Res1High : 1;

5232

5233 /* Bits[13:13], Access Type=RW, default=0x00000000*/

5234

5235 /* ICECTLRES1_HIGH: Reserved */

5236 UINT32 PreserveDebugResources : 1;

5237

5238 /* Bits[14:14], Access Type=RW, default=0x00000000*/

5239

5240 /* ICECTLPMR_PRESERVE_DEBUG_RESOURCES: */

5241 UINT32 PreserveLbrResources : 1;

5242

5243 /* Bits[15:15], Access Type=RW, default=0x00000000*/

5244

5245 /*

5246 ICECTLPMR_PRESERVE_LBR_RESOURCES: PM S/W may

5247 program the LBRs to trace the DUT. Before PM

5248 exit, the PM S/W should reserve LBRs for itself

5249 by setting ICECTLPMR.Preserve_LBR_Resources.

5250 This will ensure that any other software running

5251 on the CPU cannot use the LBRs. Setting this bit

5252 will also effectively preserve RTIT resources.

5253 */

5254 UINT32 CsiOffTapDrainOn : 1;

5255

5256 /* Bits[16:16], Access Type=RW, default=0x00000000*/

5257

5258 /*

5259 Enable the tap and turn off the csi link packet:

5260 Ynh

5261 */

5262 UINT32 RemainProbemode : 1;

5263

5264 /* Bits[17:17], Access Type=RW, default=0x00000000*/

5265

5266 /* Remain in Probe mode */

5267 UINT32 PmHleBit : 1;

5268

5269 /* Bits[18:18], Access Type=RW, default=0x00000000*/

5270

5271 /*

5272 ICECTL_PM_HLE_BIT_POS: Enter Probe Mode on HLE

5273 Aborts

5274 */

5275 UINT32 PmHlepBit : 1;

5276

5277 /* Bits[19:19], Access Type=RW, default=0x00000000*/

5278

5279 /*

5280 ICECTL_PM_HLEP_BIT_POS: Enter Probe Mode on HLE+

5281 Aborts

5282 */

5283 UINT32 ClrPir : 1;

5284

5285 /* Bits[20:20], Access Type=WO, default=0x00000000*/

5286

5287 /* ICECTLPIR: Clear PIR bit state */

5288 UINT32 EnclaveInterruption : 1;

5289

5290 /* Bits[21:21], Access Type=RW, default=0x00000000*/

5291

5292 /*

5293 ICECTLPIR: ENCLAVE INTERRUPTION bit to be set in

5294 ICECTLPMR once probe mode got signaled inside

5295 enclave

5296 */

5297 UINT32 PreserveRtitResources : 1;

5298

5299 /* Bits[22:22], Access Type=RW, default=0x00000000*/

5300

5301 /*

5302 ICECTLPMR_PRESERVE_RTIT_RESOURCES: PM S/W may

5303 program RTIT to trace the DUT. Before PM exit,

5304 the PM S/W should reserve RTIT for itself by

5305 setting ICECTLPMR.Preserve_RTIT_Resources. This

5306 will ensure that any other software running on

5307 the CPU cannot use RTIT. Setting this bit will

5308 also effectively preserve LBR/DEBUG resources.

5309 */

5310 UINT32 Rsvd23 : 9;

5311

5312 /* Bits[31:23], Access Type=RO, default=None*/

5313

5314 /* Reserved */

5315

5316 } Bits;

5317

5318 UINT32 Uint32;

5319 UINT64 Uint64;

5320

5321 } MSR_ICECTLPMR_REGISTER;

5322

5323 /**

5324 LER MSR that holds non-IP information

5325 **/

5326 #define MSR_LAST_INT_INFO 0x000001E0

5327

5328 typedef union {

5329 ///

5330 /// Individual bit fields

5331 ///

5332 struct {

5333 UINT32 CycleCount : 16;

5334

5335 /* Bits[15:0], Access Type=RW_V, default=None*/

5336

5337 /* core-clocks elapsed since last LBR array update */

5338 UINT32 Rsvd16 : 16;

5339

5340 /* Bits[31:16], Access Type=RO, default=None*/

5341

5342 /* Reserved */

5343 UINT32 Rsvd32 : 29;

5344

5345 /* Bits[60:32], Access Type=RO, default=None*/

5346

5347 /* Reserved */

5348 UINT32 HleAbort : 1;

5349

5350 /* Bits[61:61], Access Type=RW_V, default=None*/

5351

5352 /* HLE/+ TX Abort occured */

5353 UINT32 InTx : 1;

5354

5355 /* Bits[62:62], Access Type=RW_V, default=None*/

5356

5357 /* Executing in HLE/+ TX */

5358 UINT32 Mispred : 1;

5359

5360 /* Bits[63:63], Access Type=RW_V, default=None*/

5361

5362 /* Misprediction bit */

5363

5364 } Bits;

5365

5366 UINT32 Uint32;

5367 UINT64 Uint64;

5368

5369 } MSR_LAST_INT_INFO_REGISTER;

5370

5371 /**

5372 This RO MSR will be used to report the fuse_cpu_type bits from PCU Package Config CSR

5373 **/

5374 #define MSR_CPU_TYPE 0x000001E1

5375

5376 typedef union {

5377 ///

5378 /// Individual bit fields

5379 ///

5380 struct {

5381 UINT32 FuseCpuType : 4;

5382

5383 /* Bits[3:0], Access Type=RW, default=0x00000000*/

5384

5385 /* CPU Type Indication */

5386 UINT32 Rsvd4 : 28;

5387

5388 /* Bits[31:4], Access Type=RO, default=None*/

5389

5390 /* Reserved */

5391

5392 } Bits;

5393

5394 UINT32 Uint32;

5395 UINT64 Uint64;

5396

5397 } MSR_CPU_TYPE_REGISTER;

5398

5399 /**

5400 Register used to enable customer specific features

5401 **/

5402 #define MSR_CUSTOMER_SPECIFIC_FEATURE_ENABLE 0x000001E2

5403

5404 typedef union {

5405 ///

5406 /// Individual bit fields

5407 ///

5408 struct {

5409 UINT32 Rsvd0 : 1;

5410

5411 /* Bits[0:0], Access Type=RW, default=None*/

5412

5413 /* RSVD */

5414 UINT32 UserLevelMwaitEnable : 1;

5415

5416 /* Bits[1:1], Access Type=RW, default=None*/

5417

5418 /* Enable bit for user-level mwait */

5419 UINT32 RsvdUpper2 : 30;

5420

5421 /* Bits[31:2], Access Type=RW, default=None*/

5422

5423 /* RSVD */

5424

5425 } Bits;

5426

5427 UINT32 Uint32;

5428 UINT64 Uint64;

5429

5430 } MSR_CUSTOMER_SPECIFIC_FEATURE_ENABLE_REGISTER;

5431

5432 /**

5433 This MSR holds the capability of error spoofing. Bit 1 for unlock MCA/ CMCI generation capability (allows event injection), bit 0 to unlock writing to MC banks

5434 **/

5435 #define MSR_DEBUG_ERR_INJ_CTL 0x000001E3

5436

5437 typedef union {

5438 ///

5439 /// Individual bit fields

5440 ///

5441 struct {

5442 UINT32 McbwE : 1;

5443

5444 /* Bits[0:0], Access Type=RW, default=0x00000000*/

5445

5446 /*

5447 Bit indicates if writing to MC banks is allowed

5448 0 - Writing to MC banks Not allowed 1 - Writing

5449 to MC banks allowed

5450 */

5451 UINT32 McaCmciSe : 1;

5452

5453 /* Bits[1:1], Access Type=RW, default=0x00000000*/

5454

5455 /*

5456 Bit indicates if error spoofing is allowed 0 -

5457 Error spoofing not allowed 1 - Error spoofing

5458 allowed(MCA/CMCI)

5459 */

5460 UINT32 Rsvd2 : 30;

5461

5462 /* Bits[31:2], Access Type=RO, default=None*/

5463

5464 /* Reserved */

5465

5466 } Bits;

5467

5468 UINT32 Uint32;

5469 UINT64 Uint64;

5470

5471 } MSR_DEBUG_ERR_INJ_CTL_REGISTER;

5472

5473 /**

5474 This MSR will be used to trigger MCA(bit0)/CMCI(bit1)

5475 **/

5476 #define MSR_DEBUG_ERR_INJ_CTL2 0x000001E4

5477

5478 typedef union {

5479 ///

5480 /// Individual bit fields

5481 ///

5482 struct {

5483 UINT32 McaG : 1;

5484

5485 /* Bits[0:0], Access Type=RW, default=0x00000000*/

5486

5487 /*

5488 Bit indicates if MC banks is triggered 0 - Not

5489 triggered 1 - Triggered

5490 */

5491 UINT32 CmciG : 1;

5492

5493 /* Bits[1:1], Access Type=RW, default=0x00000000*/

5494

5495 /*

5496 Bit indicates if CMCI is triggered 0 - Not

5497 triggered 1 - Triggered

5498 */

5499 UINT32 Rsvd2 : 30;

5500

5501 /* Bits[31:2], Access Type=RO, default=None*/

5502

5503 /* Reserved */

5504

5505 } Bits;

5506

5507 UINT32 Uint32;

5508 UINT64 Uint64;

5509

5510 } MSR_DEBUG_ERR_INJ_CTL2_REGISTER;

5511

5512 /**

5513 User-level Interrupts Vector

5514 **/

5515 #define MSR_ULI_VECTOR_INFO 0x000001E5

5516

5517 typedef union {

5518 ///

5519 /// Individual bit fields

5520 ///

5521 struct {

5522 UINT32 MatchVector : 8;

5523

5524 /* Bits[7:0], Access Type=RW, default=None*/

5525

5526 /*

5527 Interrupt vector to match on to provide ULI

5528 handling

5529 */

5530 UINT32 Enable : 1;

5531

5532 /* Bits[8:8], Access Type=RW, default=None*/

5533

5534 /* Enable bit for ULI handling */

5535 UINT32 Rsvd9 : 23;

5536

5537 /* Bits[31:9], Access Type=RW, default=None*/

5538

5539 /* Reserved */

5540

5541 } Bits;

5542

5543 UINT32 Uint32;

5544 UINT64 Uint64;

5545

5546 } MSR_ULI_VECTOR_INFO_REGISTER;

5547 /**

5548 User-level Interrupts Target RIP

5549 **/

5550 #define MSR_ULI_TARGET_RIP 0x000001E7

5551

5552 /**

5553 VLW capability MSR that reports information about the VLW messages that are supported

5554 **/

5555 #define MSR_VLW_CAPABILITY 0x000001F0

5556

5557 typedef union {

5558 ///

5559 /// Individual bit fields

5560 ///

5561 struct {

5562 UINT32 Ignne : 1;

5563

5564 /* Bits[0:0], Access Type=RO_V, default=None*/

5565

5566 /*

5567 '0 since IGNNE VLW message is not supported on

5568 NHM

5569 */

5570 UINT32 A20m : 1;

5571

5572 /* Bits[1:1], Access Type=RO_V, default=None*/

5573

5574 /* '1 means A20M message is supported */

5575 UINT32 Intr : 1;

5576

5577 /* Bits[2:2], Access Type=RO_V, default=None*/

5578

5579 /* '1 means INTR message is supported */

5580 UINT32 Rsvd3 : 1;

5581

5582 /* Bits[3:3], Access Type=RO_V, default=None*/

5583

5584 /* Reserved */

5585 UINT32 Smi : 1;

5586

5587 /* Bits[4:4], Access Type=RO_V, default=None*/

5588

5589 /* '1 means SMI message is supported */

5590 UINT32 Init : 1;

5591

5592 /* Bits[5:5], Access Type=RO_V, default=None*/

5593

5594 /* '1 means INIT message is supported */

5595 UINT32 Nmi : 1;

5596

5597 /* Bits[6:6], Access Type=RO_V, default=None*/

5598

5599 /* '1 means NMI message is supported */

5600 UINT32 Rsvd7 : 25;

5601

5602 /* Bits[31:7], Access Type=RO, default=None*/

5603

5604 /* Reserved */

5605 UINT32 Rsvd32 : 32;

5606

5607 /* Bits[63:32], Access Type=RO, default=None*/

5608

5609 /* Reserved */

5610

5611 } Bits;

5612

5613 UINT32 Uint32;

5614 UINT64 Uint64;

5615

5616 } MSR_VLW_CAPABILITY_REGISTER;

5617

5618 /**

5619 Virtual MSR to will write data to an Crash Log configuration

5620 CR address is taken from CORE_CRASHLOG_CONTROL

5621 writing and reading CDDIS - CrashLog_Disable

5622 **/

5623 #define MSR_CRASHLOG_CONTROL 0x000001F1

5624

5625 typedef union {

5626 ///

5627 /// Individual bit fields

5628 ///

5629 struct {

5630 UINT32 Cddis : 1;

5631

5632 /* Bits[0:0], Access Type=RW, default=None*/

5633

5634 /*

5635 CrashDump_Disable - If set, indicates that Crash

5636 Dump is disabled. Default value will come from

5637 the CORE_CRASHLOG_DIS fuse.

5638 */

5639 UINT32 Reserved1 : 31;

5640

5641 /* Bits[31:1], Access Type=RW, default=None*/

5642

5643 /* Reserved */

5644 UINT32 Rsvd32 : 32;

5645

5646 /* Bits[63:32], Access Type=RO, default=None*/

5647

5648 /* Reserved */

5649

5650 } Bits;

5651

5652 UINT32 Uint32;

5653 UINT64 Uint64;

5654

5655 } MSR_CRASHLOG_CONTROL_REGISTER;

5656

5657 /**

5658 SMM Range Register - Physical Base Control Register

5659 **/

5660 #define MSR_SMRR_BASE 0x000001F2

5661

5662 typedef union {

5663 ///

5664 /// Individual bit fields

5665 ///

5666 struct {

5667 UINT32 Memtype : 3;

5668

5669 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5670

5671 /* SMRR BASE MemType */

5672 UINT32 Rsvd3 : 9;

5673

5674 /* Bits[11:3], Access Type=RO, default=None*/

5675

5676 /* Reserved */

5677 UINT32 Base : 20;

5678

5679 /* Bits[31:12], Access Type=RW, default=0x00000000*/

5680

5681 /* SMRR BASE Physical Base Address */

5682 UINT32 Rsvd32 : 32;

5683

5684 /* Bits[63:32], Access Type=RO, default=None*/

5685

5686 /* Reserved */

5687

5688 } Bits;

5689

5690 UINT32 Uint32;

5691 UINT64 Uint64;

5692

5693 } MSR_SMRR_BASE_REGISTER;

5694

5695 /**

5696 SMM Range Register Base - Physical Mask Control Register

5697 **/

5698 #define MSR_SMRR_MASK 0x000001F3

5699

5700 typedef union {

5701 ///

5702 /// Individual bit fields

5703 ///

5704 struct {

5705 UINT32 Rsvd0 : 9;

5706

5707 /* Bits[8:0], Access Type=RO, default=None*/

5708

5709 /* Reserved */

5710 UINT32 Assist : 1;

5711

5712 /* Bits[9:9], Access Type=RW, default=0x00000000*/

5713

5714 /*

5715 If set, SMRR is in assist-mode - else in page

5716 abort-mode (defeature only)

5717 */

5718 UINT32 L : 1;

5719

5720 /* Bits[10:10], Access Type=RW, default=0x00000000*/

5721

5722 /* Lock bit for the SMRR */

5723 UINT32 Vld : 1;

5724

5725 /* Bits[11:11], Access Type=RW, default=0x00000000*/

5726

5727 /* SMM Mask Valid Bit */

5728 UINT32 Mask : 20;

5729

5730 /* Bits[31:12], Access Type=RW, default=0x00000000*/

5731

5732 /* SMM MASK MTRR Mask */

5733 UINT32 Rsvd32 : 32;

5734

5735 /* Bits[63:32], Access Type=RO, default=None*/

5736

5737 /* Reserved */

5738

5739 } Bits;

5740

5741 UINT32 Uint32;

5742 UINT64 Uint64;

5743

5744 } MSR_SMRR_MASK_REGISTER;

5745

5746 /**

5747 Processor Reserved Memory Range Register - Physical Mask Control Register

5748 **/

5749 #define MSR_PRMRR_MASK 0x000001F5

5750

5751 typedef union {

5752 ///

5753 /// Individual bit fields

5754 ///

5755 struct {

5756 UINT32 Rsvd0 : 9;

5757

5758 /* Bits[8:0], Access Type=RO, default=None*/

5759

5760 /* Reserved */

5761 UINT32 Assist : 1;

5762

5763 /* Bits[9:9], Access Type=RW, default=0x00000000*/

5764

5765 /*

5766 If set, PRMRR is in assist-mode - else in page

5767 abort-mode (defeature only)

5768 */

5769 UINT32 L : 1;

5770

5771 /* Bits[10:10], Access Type=RW, default=0x00000000*/

5772

5773 /* Lock bit for the PRMRR */

5774 UINT32 Vld : 1;

5775

5776 /* Bits[11:11], Access Type=RW, default=0x00000000*/

5777

5778 /* Enable bit for the PRMRR */

5779 UINT32 Mask0 : 20;

5780

5781 /* Bits[31:12], Access Type=RW, default=0x00000000*/

5782

5783 /* PRMRR MASK bits */

5784 UINT32 Mask1 : 20;

5785

5786 /* Bits[51:32], Access Type=RW, default=0x00000000*/

5787

5788 /* PRMRR MASK bits */

5789 UINT32 Rsvd52 : 12;

5790

5791 /* Bits[63:52], Access Type=RO, default=None*/

5792

5793 /* Reserved */

5794

5795 } Bits;

5796

5797 UINT32 Uint32;

5798 UINT64 Uint64;

5799

5800 } MSR_PRMRR_MASK_REGISTER;

5801

5802 /**

5803 SMM Range Register #2 - Physical Base Control Register

5804 **/

5805 #define MSR_SMRR2_BASE 0x000001F6

5806

5807 typedef union {

5808 ///

5809 /// Individual bit fields

5810 ///

5811 struct {

5812 UINT32 Memtype : 3;

5813

5814 /* Bits[2:0], Access Type=RW, default=0x00000000*/

5815

5816 /* SMRR BASE MemType */

5817 UINT32 Rsvd3 : 9;

5818

5819 /* Bits[11:3], Access Type=RO, default=None*/

5820

5821 /* Reserved */

5822 UINT32 Base : 20;

5823

5824 /* Bits[31:12], Access Type=RW, default=0x00000000*/

5825

5826 /* SMRR BASE Physical Base Address */

5827

5828 } Bits;

5829

5830 UINT32 Uint32;

5831 UINT64 Uint64;

5832

5833 } MSR_SMRR2_BASE_REGISTER;

5834

5835 /**

5836 SMM Range Register Base #2 - Physical Mask Control Register

5837 **/

5838 #define MSR_SMRR2_MASK 0x000001F7

5839

5840 typedef union {

5841 ///

5842 /// Individual bit fields

5843 ///

5844 struct {

5845 UINT32 Rsvd0 : 9;

5846

5847 /* Bits[8:0], Access Type=RO, default=None*/

5848

5849 /* Reserved */

5850 UINT32 Assist : 1;

5851

5852 /* Bits[9:9], Access Type=RW, default=0x00000000*/

5853

5854 /*

5855 If set, SMRR is in assist-mode - else in page

5856 abort-mode (defeature only)

5857 */

5858 UINT32 L : 1;

5859

5860 /* Bits[10:10], Access Type=RW, default=0x00000000*/

5861

5862 /* Lock bit for the SMRR2 */

5863 UINT32 Vld : 1;

5864

5865 /* Bits[11:11], Access Type=RW, default=0x00000000*/

5866

5867 /* SMM Mask Valid Bit */

5868 UINT32 Mask : 20;

5869

5870 /* Bits[31:12], Access Type=RW, default=0x00000000*/

5871

5872 /* SMM MASK MTRR Mask */

5873

5874 } Bits;

5875

5876 UINT32 Uint32;

5877 UINT64 Uint64;

5878

5879 } MSR_SMRR2_MASK_REGISTER;

5880

5881 /**

5882 Valid PRMRR configurations

5883 **/

5884 #define MSR_PRMRR_VALID_CONFIG 0x000001FB

5885

5886 typedef union {

5887 ///

5888 /// Individual bit fields

5889 ///

5890 struct {

5891 UINT32 Config1m : 1;

5892

5893 /* Bits[0:0], Access Type=RW, default=None*/

5894

5895 /* 1M supported MEE size */

5896 UINT32 Config2m : 1;

5897

5898 /* Bits[1:1], Access Type=RW, default=None*/

5899

5900 /* 2M supported MEE size */

5901 UINT32 Rsvd2 : 3;

5902

5903 /* Bits[4:2], Access Type=RW, default=None*/

5904

5905 /* Reserved */

5906 UINT32 Config32m : 1;

5907

5908 /* Bits[5:5], Access Type=RW, default=None*/

5909

5910 /* 32M supported MEE size */

5911 UINT32 Config64m : 1;

5912

5913 /* Bits[6:6], Access Type=RW, default=None*/

5914

5915 /* 64M supported MEE size */

5916 UINT32 Config128m : 1;

5917

5918 /* Bits[7:7], Access Type=RW, default=None*/

5919

5920 /* 128M supported MEE size */

5921 UINT32 Config256m : 1;

5922

5923 /* Bits[8:8], Access Type=RW, default=None*/

5924

5925 /* 256M supported MEE size */

5926 UINT32 Rsvd9 : 23;

5927

5928 /* Bits[31:9], Access Type=RW, default=None*/

5929

5930 /* Reserved */

5931

5932 } Bits;

5933

5934 UINT32 Uint32;

5935 UINT64 Uint64;

5936

5937 } MSR_PRMRR_VALID_CONFIG_REGISTER;

5938

5939 /**

5940 Power Control Register

5941 **/

5942 #define MSR_POWER_CTL 0x000001FC

5943

5944 typedef union {

5945 ///

5946 /// Individual bit fields

5947 ///

5948 struct {

5949 UINT32 EnableBidirProchot : 1;

5950

5951 /* Bits[0:0], Access Type=RW, default=0x00000000*/

5952

5953 /*

5954 Used to enable or disable the response to

5955 PROCHOT# input. When set/enabled, platform can

5956 force CPU to throttle to a lower power condition

5957 such as Pn/Pm by asserting prochot#. When

5958 clear/disabled (default), CPU ignores the status

5959 of the prochot input signal.

5960 */

5961 UINT32 C1eEnable : 1;

5962

5963 /* Bits[1:1], Access Type=RW, default=0x00000001*/

5964

5965 /*

5966 [p]Used to enable C1E behavior on every C1 entry

5967 (even if MWAIT C1E substate bit was not set or

5968 when using HLT).[/p] [p]When this package-

5969 visible bit is set, it will cause the CPU to

5970 switch to minimum GV point (P State) when all

5971 cores have entered C1. The frequency will switch

5972 immediately, followed by gradual voltage

5973 switching (GV3 style).[/p]

5974 */

5975 UINT32 SapmImcC2Policy : 1;

5976

5977 /* Bits[2:2], Access Type=RW, default=0x00000001*/

5978

5979 /*

5980 Enables Self Refresh entry when the CPU is in

5981 package-C2 (popup) state. Should be disabled

5982 only if platform traffic cannot withstand even

5983 the SR exit latency while in C2.

5984 */

5985 UINT32 FastBrkSnpEn : 1;

5986

5987 /* Bits[3:3], Access Type=RW, default=0x00000000*/

5988

5989 /*

5990 Controls the VID swing rate for Other_Snp_Wake

5991 events detected at the iMPH. Will override a

5992 "SLOW" sideband wake indication primarily for

5993 PCIe traffic!). '1' - Use 'fast' VID swing rate

5994 */

5995 UINT32 FastBrkIntEn : 1;

5996

5997 /* Bits[4:4], Access Type=RW, default=0x00000001*/

5998

5999 /*

6000 Controls the VID swing rate for Other_Intp_Wake

6001 events detected at the iMPH. Will override a

6002 "SLOW" sideband wake indication (for C7 or

6003 PCIe). '1' - Use 'fast' VID swing rate

6004 */

6005 UINT32 Rsrvd5 : 1;

6006

6007 /* Bits[5:5], Access Type=RW, default=0x00000000*/

6008

6009 /*

6010 Rsrvd uCode needs to copy this bit to/from

6011 POWER_CTL1_CR[5] on writes.reads

6012 */

6013 UINT32 PholdCstPreventionInit : 11;

6014

6015 /* Bits[16:6], Access Type=RW, default=0x00000001*/

6016

6017 /*

6018 Init value for the PHOLD_CST_PREVENTION_Timer.

6019 Values are between 0 and 1023 in 2^21*10nS

6020 resolution (matching 0 - ~21sec)

6021 */

6022 UINT32 PholdSrDisable : 1;

6023

6024 /* Bits[17:17], Access Type=RW, default=0x00000000*/

6025

6026 /*

6027 if set to '1', CPU will also prevent the memory

6028 from going to SR during the CST_PREVENTION

6029 timeout;

6030 */

6031 UINT32 PwrPerfPltfrmOvr : 1;

6032

6033 /* Bits[18:18], Access Type=RW, default=0x00000000*/

6034

6035 /*

6036 When set to 0 (default), will disable access to

6037 IA32_ENERGY_PERFORMANCE_BIAS MSR 1B0h (causing a

6038 GP# fault on access). CPUID.(EAX=6):ECX[3] will

6039 read 0. When set to 1 will enable access to

6040 IA32_ENERGY_PERFORMANCE_BIAS MSR 1B0h.

6041 CPUID.(EAX=6):ECX[3] will read 1

6042 */

6043 UINT32 EeTurboDisable : 1;

6044

6045 /* Bits[19:19], Access Type=RW, default=0x00000000*/

6046

6047 /*

6048 Setting this bit disables the Turbo P-States

6049 energy efficiency optimizations. In P-State

6050 legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] =

6051 0), the processor will set the P-State to P0

6052 when in the Turbo range. When HWP is enabled, if

6053 the processor is in Autonomous mode it will

6054 select the P-State based on Processor residency

6055 and with no energy efficiency considerations. If

6056 the OS selects the desired P-State, the

6057 processor will adhere to this request unless any

6058 physical constraints prevent that.

6059 */

6060 UINT32 RthDisable : 1;

6061

6062 /* Bits[20:20], Access Type=RW, default=0x00000000*/

6063

6064 /*

6065 Setting this bit disables the Race to Halt

6066 optimization and enables the processor to

6067 execute down to the HWP Lowest frequency.

6068 Default value is 0 for processors that support

6069 HWP. Default value is 1 for processors that do

6070 not support HWP.

6071 */

6072 UINT32 DisProchotOut : 1;

6073

6074 /* Bits[21:21], Access Type=RW, default=0x00000000*/

6075

6076 /* Prochot output disable */

6077 UINT32 ProchotResponse : 1;

6078

6079 /* Bits[22:22], Access Type=RW, default=0x00000000*/

6080

6081 /* Prochhot Configurable Response Enable */

6082 UINT32 ProchotLock : 1;

6083

6084 /* Bits[23:23], Access Type=RW, default=0x00000000*/

6085

6086 /*

6087 When set to 1, locks bits 0, 21, 22 and 23 of

6088 this MSR. Once set, a reset is required to clear

6089 this bit.

6090 */

6091 UINT32 VrThermAlertDisable : 1;

6092

6093 /* Bits[24:24], Access Type=RW, default=0x00000000*/

6094

6095 /*

6096 When set to 1, disables the VR_THERMAL_ALERT

6097 signaling.

6098 */

6099 UINT32 DisableRingEe : 1;

6100

6101 /* Bits[25:25], Access Type=RW, default=0x00000000*/

6102

6103 /*

6104 Setting this bit disables the H/W based Ring

6105 energy efficiency optimization. Default value is

6106 0 for processors that support Ring energy

6107 efficiency optimization. Default value is 1 for

6108 processors that do not support Ring energy

6109 efficiency optimization.

6110 */

6111 UINT32 DisableSaOptimization : 1;

6112

6113 /* Bits[26:26], Access Type=RW, default=0x00000000*/

6114

6115 /* DISABLE_SA_OPTIMIZATION */

6116 UINT32 DisableOok : 1;

6117

6118 /* Bits[27:27], Access Type=RW, default=0x00000000*/

6119

6120 /*

6121 Setting this bit disables the H/W base duty

6122 cycles heuristics for performance boost during

6123 power/thermal limitation. Default value is 0 for

6124 processors that support HDC. Default value is 1

6125 for processors that do not support HDC.

6126 */

6127 UINT32 DisableAutonomous : 1;

6128

6129 /* Bits[28:28], Access Type=RW, default=0x00000000*/

6130

6131 /*

6132 [p]When this bit is set H/W Autonomous algorithm

6133 for P-State selection is disabled. Default value

6134 is 0 for processors that support HWP. Default

6135 value is 1 for processors that do not support

6136 H/W Autonomous algorithm for P-State.[/p]

6137 [p]When P-State Legacy mode is enabled

6138 (IA32_PM_ENABLE[HWP_ENABLE] = 0), the H/W only

6139 owns selecting the P-State in the turbo range.

6140 If POWER_CTL[28] is also set to 0, the algorithm

6141 that selects the P-State in the Turbo range is

6142 H/W Autonomous. In this case, mapping of the

6143 Legacy Energy Performance Bias value to HWP EPP

6144 is done internally to feed the Autonomous

6145 algorithm. If POWER_CTL[28] is set to 1, the

6146 legacy algorithm is in effect.[/p] [p]While H/W

6147 Base P state is in use,

6148 IA32_PM_ENABLE[HWP_ENABLE] = 1 and the

6149 IA32_HWP_REQUEST[DESREID_PERF] = 0, the P-state

6150 selection will be only the highest support

6151 performance level[/p]

6152 */

6153 UINT32 Rsvd29 : 1;

6154

6155 /* Bits[29:29], Access Type=RO, default=None*/

6156

6157 /* Reserved */

6158 UINT32 CstatePrewakeDisable : 1;

6159

6160 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6161

6162 /*

6163 This bit can be used to disable core/pkg C-state

6164 Prewake timers.

6165 */

6166 UINT32 ReservedMode31 : 1;

6167

6168 /* Bits[31:31], Access Type=RW, default=0x00000000*/

6169

6170 /* Reserved */

6171 UINT32 Rsvd32 : 32;

6172

6173 /* Bits[63:32], Access Type=RO, default=None*/

6174

6175 /* Reserved */

6176

6177 } Bits;

6178

6179 UINT32 Uint32;

6180 UINT64 Uint64;

6181

6182 } MSR_POWER_CTL_REGISTER;

6183 /**

6184 Special Chipset Usage MSR

6185 **/

6186 #define MSR_SPCL_CHIPSET_USAGE 0x000001FE

6187

6188 /**

6189 Scratch Pad register P6_CR_ICECTLPMR_2

6190 Bit descriptions are derived from review of Merom ucode - May be incomplete (RajeshP)

6191 **/

6192 #define MSR_ICECTLPMR_2 0x0000025B

6193

6194 typedef union {

6195 ///

6196 /// Individual bit fields

6197 ///

6198 struct {

6199 UINT32 RsvdB0 : 8;

6200

6201 /* Bits[7:0], Access Type=RW, default=None*/

6202

6203 /* SCP Register Value */

6204 UINT32 C6Exit : 1;

6205

6206 /* Bits[8:8], Access Type=RW, default=None*/

6207

6208 /* Redirect to probe mode at the end of C6 exit */

6209 UINT32 Getsec : 1;

6210

6211 /* Bits[9:9], Access Type=RW, default=None*/

6212

6213 /* Redirect to probe mode at the start of GETSEC */

6214 UINT32 PreCram : 1;

6215

6216 /* Bits[10:10], Access Type=RW, default=None*/

6217

6218 /*

6219 Redirect to probe mode just before loading LT

6220 CRAM

6221 */

6222 UINT32 AcmodeEnter : 1;

6223

6224 /* Bits[11:11], Access Type=RW, default=None*/

6225

6226 /*

6227 Redirect to probe mode just before launching an

6228 AC-module

6229 */

6230 UINT32 AcmodeExit : 1;

6231

6232 /* Bits[12:12], Access Type=RW, default=None*/

6233

6234 /*

6235 Redirect to probe mode after exiting an AC-

6236 module (end of EXITAC)

6237 */

6238 UINT32 SexitEnd : 1;

6239

6240 /* Bits[13:13], Access Type=RW, default=None*/

6241

6242 /* Redirect to probe mode at the end of SEXIT */

6243 UINT32 Enclu : 1;

6244

6245 /* Bits[14:14], Access Type=RW, default=None*/

6246

6247 /* Redirect to probe mode in ENCLU instruction */

6248 UINT32 Rsvd15 : 7;

6249

6250 /* Bits[21:15], Access Type=RW, default=None*/

6251

6252 /* SCP Register Value */

6253 UINT32 Int1 : 1;

6254

6255 /* Bits[22:22], Access Type=RW, default=None*/

6256

6257 /* Redirect to probe mode in INT1 instruction */

6258 UINT32 StepInto : 1;

6259

6260 /* Bits[23:23], Access Type=RW, default=None*/

6261

6262 /*

6263 For SNB i366110: ITP Step Into Interrupts and

6264 Exceptions

6265 */

6266 UINT32 Shutdown : 1;

6267

6268 /* Bits[24:24], Access Type=RW, default=None*/

6269

6270 /* SCP Register Value */

6271 UINT32 Rsvd25 : 1;

6272

6273 /* Bits[25:25], Access Type=RW, default=None*/

6274

6275 /* SCP Register Value */

6276 UINT32 Vmexit : 1;

6277

6278 /* Bits[26:26], Access Type=RW, default=None*/

6279

6280 /* SCP Register Value */

6281 UINT32 Rsvd27 : 2;

6282

6283 /* Bits[28:27], Access Type=RW, default=None*/

6284

6285 /* SCP Register Value */

6286 UINT32 Vmentry : 3;

6287

6288 /* Bits[31:29], Access Type=RW, default=None*/

6289

6290 /* SCP Register Value */

6291

6292 } Bits;

6293

6294 UINT32 Uint32;

6295 UINT64 Uint64;

6296

6297 } MSR_ICECTLPMR_2_REGISTER;

6298

6299 /**

6300 This register is used for generating corrected error interrupts.

6301 This is a 64 bits register. Refer to the MCA HAS for details.

6302 x86_architectural: true

6303 creg_msr_symbol: MCi_CTL2

6304 creg_msr_mask: 64'hFFFFFFFABFFF8000

6305 **/

6306 #define MSR_MCI_CTL2 0x00000298

6307

6308 typedef union {

6309 ///

6310 /// Individual bit fields

6311 ///

6312 struct {

6313 UINT32 Correrrthrhd : 15;

6314

6315 /* Bits[14:0], Access Type=RWS, default=0x00000000*/

6316

6317 /*

6318 Correctable Error Threshold (CorrErrThrhd): When

6319 the correctable error count

6320 (MCi_STATUS.CorrCount) transitions to being

6321 equal to this threshold, a CMCI will be signaled

6322 if the CorrErrCmciEn bit is set. Typically used

6323 to indicate to OS that a certain amount of

6324 corrected errors were observed.

6325 */

6326 UINT32 Rsvd15 : 15;

6327

6328 /* Bits[29:15], Access Type=RO, default=None*/

6329

6330 /* Reserved */

6331 UINT32 Cmcien : 1;

6332

6333 /* Bits[30:30], Access Type=RW, default=0x00000000*/

6334

6335 /*

6336 Corrected Error Interrupt Enable (CmciEn):

6337 Enable CMCI signaling (when 1). Usage model is

6338 to generate a CMCI interrupt for OS on corrected

6339 or recoverable error. When the corrected error

6340 threshold (CorrErrThrhd) is reached a CMCI will

6341 be signaled.

6342 */

6343 UINT32 Rsvd31 : 1;

6344

6345 /* Bits[31:31], Access Type=RO, default=None*/

6346

6347 /* Reserved */

6348 UINT32 Mapcmcitocsmi : 1;

6349

6350 /* Bits[32:32], Access Type=RW, default=0x00000000*/

6351

6352 /*

6353 Map Correctable Machine Check Interrupt to

6354 Correctable SM Interrupt (MapCmciToCsmi): If set

6355 then any correctable machine check interrupt

6356 will be transformed into a correctable SM

6357 interrupt so BIOS can intercept it.

6358 */

6359 UINT32 Rsvd33 : 1;

6360

6361 /* Bits[33:33], Access Type=RO, default=None*/

6362

6363 /* Reserved */

6364 UINT32 Mapmcetomsmi : 1;

6365

6366 /* Bits[34:34], Access Type=RW, default=0x00000000*/

6367

6368 /*

6369 Map Machine Check Errors to Machine Check SM

6370 Interrupt (MapCmciToCsmi): If set then any

6371 machine check error (i.e. a fatal condition

6372 signalled to OS) will be transformed into a

6373 machine check SM interrupt so BIOS can intercept

6374 it.

6375 */

6376 UINT32 Rsvd35 : 29;

6377

6378 /* Bits[63:35], Access Type=RO, default=None*/

6379

6380 /* Reserved */

6381

6382 } Bits;

6383

6384 UINT32 Uint32;

6385 UINT64 Uint64;

6386

6387 } MSR_MCI_CTL2_REGISTER;

6388

6389 /**

6390 Processor Reserved Memory Range Register - Physical Base Control Register

6391 **/

6392 #define MSR_PRMRR_BASE_0 0x000002A0

6393

6394 typedef union {

6395 ///

6396 /// Individual bit fields

6397 ///

6398 struct {

6399 UINT32 Memtype : 3;

6400

6401 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6402

6403 /* PRMRR BASE MemType */

6404 UINT32 Configured : 1;

6405

6406 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6407

6408 /* PRMRR BASE Configured */

6409 UINT32 Rsvd4 : 8;

6410

6411 /* Bits[11:4], Access Type=RO, default=None*/

6412

6413 /* Reserved */

6414 UINT32 Base0 : 20;

6415

6416 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6417

6418 /* PRMRR Base Address */

6419 UINT32 Base1 : 20;

6420

6421 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6422

6423 /* PRMRR Base Address */

6424 UINT32 Rsvd52 : 12;

6425

6426 /* Bits[63:52], Access Type=RO, default=None*/

6427

6428 /* Reserved */

6429

6430 } Bits;

6431

6432 UINT32 Uint32;

6433 UINT64 Uint64;

6434

6435 } MSR_PRMRR_BASE_0_REGISTER;

6436

6437 /**

6438 Processor Reserved Memory Range Register - Physical Base Control Register

6439 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6440 **/

6441 #define MSR_PRMRR_BASE_1_1 0x000002A1

6442

6443 typedef union {

6444 ///

6445 /// Individual bit fields

6446 ///

6447 struct {

6448 UINT32 Memtype : 3;

6449

6450 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6451

6452 /* PRMRR BASE MemType */

6453 UINT32 Configured : 1;

6454

6455 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6456

6457 /* PRMRR BASE Configured */

6458 UINT32 Rsvd4 : 8;

6459

6460 /* Bits[11:4], Access Type=RO, default=None*/

6461

6462 /* Reserved */

6463 UINT32 Base0 : 20;

6464

6465 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6466

6467 /* PRMRR Base Address */

6468 UINT32 Base1 : 20;

6469

6470 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6471

6472 /* PRMRR Base Address */

6473 UINT32 Rsvd52 : 12;

6474

6475 /* Bits[63:52], Access Type=RO, default=None*/

6476

6477 /* Reserved */

6478

6479 } Bits;

6480

6481 UINT32 Uint32;

6482 UINT64 Uint64;

6483

6484 } MSR_PRMRR_BASE_1_1_REGISTER;

6485

6486 /**

6487 Processor Reserved Memory Range Register - Physical Base Control Register

6488 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6489 **/

6490 #define MSR_PRMRR_BASE_2_2 0x000002A2

6491

6492 typedef union {

6493 ///

6494 /// Individual bit fields

6495 ///

6496 struct {

6497 UINT32 Memtype : 3;

6498

6499 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6500

6501 /* PRMRR BASE MemType */

6502 UINT32 Configured : 1;

6503

6504 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6505

6506 /* PRMRR BASE Configured */

6507 UINT32 Rsvd4 : 8;

6508

6509 /* Bits[11:4], Access Type=RO, default=None*/

6510

6511 /* Reserved */

6512 UINT32 Base0 : 20;

6513

6514 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6515

6516 /* PRMRR Base Address */

6517 UINT32 Base1 : 20;

6518

6519 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6520

6521 /* PRMRR Base Address */

6522 UINT32 Rsvd52 : 12;

6523

6524 /* Bits[63:52], Access Type=RO, default=None*/

6525

6526 /* Reserved */

6527

6528 } Bits;

6529

6530 UINT32 Uint32;

6531 UINT64 Uint64;

6532

6533 } MSR_PRMRR_BASE_2_2_REGISTER;

6534

6535 /**

6536 Processor Reserved Memory Range Register - Physical Base Control Register

6537 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6538 **/

6539 #define MSR_PRMRR_BASE_3_3 0x000002A3

6540

6541 typedef union {

6542 ///

6543 /// Individual bit fields

6544 ///

6545 struct {

6546 UINT32 Memtype : 3;

6547

6548 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6549

6550 /* PRMRR BASE MemType */

6551 UINT32 Configured : 1;

6552

6553 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6554

6555 /* PRMRR BASE Configured */

6556 UINT32 Rsvd4 : 8;

6557

6558 /* Bits[11:4], Access Type=RO, default=None*/

6559

6560 /* Reserved */

6561 UINT32 Base0 : 20;

6562

6563 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6564

6565 /* PRMRR Base Address */

6566 UINT32 Base1 : 20;

6567

6568 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6569

6570 /* PRMRR Base Address */

6571 UINT32 Rsvd52 : 12;

6572

6573 /* Bits[63:52], Access Type=RO, default=None*/

6574

6575 /* Reserved */

6576

6577 } Bits;

6578

6579 UINT32 Uint32;

6580 UINT64 Uint64;

6581

6582 } MSR_PRMRR_BASE_3_3_REGISTER;

6583

6584 /**

6585 Processor Reserved Memory Range Register - Physical Base Control Register

6586 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6587 **/

6588 #define MSR_PRMRR_BASE_4_4 0x000002A4

6589

6590 typedef union {

6591 ///

6592 /// Individual bit fields

6593 ///

6594 struct {

6595 UINT32 Memtype : 3;

6596

6597 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6598

6599 /* PRMRR BASE MemType */

6600 UINT32 Configured : 1;

6601

6602 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6603

6604 /* PRMRR BASE Configured */

6605 UINT32 Rsvd4 : 8;

6606

6607 /* Bits[11:4], Access Type=RO, default=None*/

6608

6609 /* Reserved */

6610 UINT32 Base0 : 20;

6611

6612 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6613

6614 /* PRMRR Base Address */

6615 UINT32 Base1 : 20;

6616

6617 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6618

6619 /* PRMRR Base Address */

6620 UINT32 Rsvd52 : 12;

6621

6622 /* Bits[63:52], Access Type=RO, default=None*/

6623

6624 /* Reserved */

6625

6626 } Bits;

6627

6628 UINT32 Uint32;

6629 UINT64 Uint64;

6630

6631 } MSR_PRMRR_BASE_4_4_REGISTER;

6632

6633 /**

6634 Processor Reserved Memory Range Register - Physical Base Control Register

6635 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6636 **/

6637 #define MSR_PRMRR_BASE_5_5 0x000002A5

6638

6639 typedef union {

6640 ///

6641 /// Individual bit fields

6642 ///

6643 struct {

6644 UINT32 Memtype : 3;

6645

6646 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6647

6648 /* PRMRR BASE MemType */

6649 UINT32 Configured : 1;

6650

6651 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6652

6653 /* PRMRR BASE Configured */

6654 UINT32 Rsvd4 : 8;

6655

6656 /* Bits[11:4], Access Type=RO, default=None*/

6657

6658 /* Reserved */

6659 UINT32 Base0 : 20;

6660

6661 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6662

6663 /* PRMRR Base Address */

6664 UINT32 Base1 : 20;

6665

6666 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6667

6668 /* PRMRR Base Address */

6669 UINT32 Rsvd52 : 12;

6670

6671 /* Bits[63:52], Access Type=RO, default=None*/

6672

6673 /* Reserved */

6674

6675 } Bits;

6676

6677 UINT32 Uint32;

6678 UINT64 Uint64;

6679

6680 } MSR_PRMRR_BASE_5_5_REGISTER;

6681

6682 /**

6683 Processor Reserved Memory Range Register - Physical Base Control Register

6684 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6685 **/

6686 #define MSR_PRMRR_BASE_6_6 0x000002A6

6687

6688 typedef union {

6689 ///

6690 /// Individual bit fields

6691 ///

6692 struct {

6693 UINT32 Memtype : 3;

6694

6695 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6696

6697 /* PRMRR BASE MemType */

6698 UINT32 Configured : 1;

6699

6700 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6701

6702 /* PRMRR BASE Configured */

6703 UINT32 Rsvd4 : 8;

6704

6705 /* Bits[11:4], Access Type=RO, default=None*/

6706

6707 /* Reserved */

6708 UINT32 Base0 : 20;

6709

6710 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6711

6712 /* PRMRR Base Address */

6713 UINT32 Base1 : 20;

6714

6715 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6716

6717 /* PRMRR Base Address */

6718 UINT32 Rsvd52 : 12;

6719

6720 /* Bits[63:52], Access Type=RO, default=None*/

6721

6722 /* Reserved */

6723

6724 } Bits;

6725

6726 UINT32 Uint32;

6727 UINT64 Uint64;

6728

6729 } MSR_PRMRR_BASE_6_6_REGISTER;

6730

6731 /**

6732 Processor Reserved Memory Range Register - Physical Base Control Register

6733 " seq has 7 instances in addresses range 0x2A1 to 0x2A7"

6734 **/

6735 #define MSR_PRMRR_BASE_7_7 0x000002A7

6736

6737 typedef union {

6738 ///

6739 /// Individual bit fields

6740 ///

6741 struct {

6742 UINT32 Memtype : 3;

6743

6744 /* Bits[2:0], Access Type=RW, default=0x00000000*/

6745

6746 /* PRMRR BASE MemType */

6747 UINT32 Configured : 1;

6748

6749 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6750

6751 /* PRMRR BASE Configured */

6752 UINT32 Rsvd4 : 8;

6753

6754 /* Bits[11:4], Access Type=RO, default=None*/

6755

6756 /* Reserved */

6757 UINT32 Base0 : 20;

6758

6759 /* Bits[31:12], Access Type=RW, default=0x00000000*/

6760

6761 /* PRMRR Base Address */

6762 UINT32 Base1 : 20;

6763

6764 /* Bits[51:32], Access Type=RW, default=0x00000000*/

6765

6766 /* PRMRR Base Address */

6767 UINT32 Rsvd52 : 12;

6768

6769 /* Bits[63:52], Access Type=RO, default=None*/

6770

6771 /* Reserved */

6772

6773 } Bits;

6774

6775 UINT32 Uint32;

6776 UINT64 Uint64;

6777

6778 } MSR_PRMRR_BASE_7_7_REGISTER;

6779

6780 /**

6781 No-Evict Mode MSR.

6782 **/

6783 #define MSR_NEM 0x000002E0

6784

6785 typedef union {

6786 ///

6787 /// Individual bit fields

6788 ///

6789 struct {

6790 UINT32 Setup : 1;

6791

6792 /* Bits[0:0], Access Type=RW, default=None*/

6793

6794 /*

6795 BIOS sets this when it is ready to fill the NEM

6796 region, and then executes the requests to fill

6797 the NEM

6798 */

6799 UINT32 Run : 1;

6800

6801 /* Bits[1:1], Access Type=RW, default=None*/

6802

6803 /*

6804 BIOS sets this bit when it's done filling the

6805 NEM region. At this point, the cache is locked.

6806 */

6807 UINT32 Rsvd2 : 30;

6808

6809 /* Bits[31:2], Access Type=RW, default=None*/

6810

6811 /* Reserved */

6812

6813 } Bits;

6814

6815 UINT32 Uint32;

6816 UINT64 Uint64;

6817

6818 } MSR_NEM_REGISTER;

6819 /**

6820 Used by Intel TXT enabled BIOS to unlock memory after checking that the TPM is valid.

6821 **/

6822 #define MSR_LT_UNLOCK_MEMORY 0x000002E6

6823

6824 /**

6825

6826 **/

6827 #define MSR_LTCTRLSTS 0x000002E7

6828

6829 typedef union {

6830 ///

6831 /// Individual bit fields

6832 ///

6833 struct {

6834 UINT32 Configlock : 1;

6835

6836 /* Bits[0:0], Access Type=RW, default=0x00000000*/

6837

6838 /*

6839 This bit has been depracated [IntelRsvd]This bit

6840 is used for indicating 'LT Config Lock'. This

6841 bit is no loger supported from CNL [/IntelRsvd]

6842 */

6843 UINT32 Memlockcpu : 1;

6844

6845 /* Bits[1:1], Access Type=RW, default=0x00000001*/

6846

6847 /*

6848 This bit is implemented in the IMPH version of

6849 the register only (as RO-VFW), the NCU holds a

6850 shadow of the bit. This bit is used for

6851 indicating 'LT Lock of CPU access to Memory'' to

6852 read operations. The bit is cleared by a write

6853 of 1 to the MemLockCPUClr bit. 0 - Memory access

6854 is enabled 1 - Memory is Locked

6855 */

6856 UINT32 Memlockdev : 1;

6857

6858 /* Bits[2:2], Access Type=RW, default=0x00000001*/

6859

6860 /*

6861 This bit is implemented in the IMPH version of

6862 the register only (as RO-VFW), the NCU holds a

6863 shadow of the bit. This bit is used for

6864 indicating 'LT Lock of Device access to Memory''

6865 to read operations. The bit is cleared by a

6866 write of 1 to the MemLockDevClr bit. 0 - Memory

6867 access is enabled 1 - Memory is Locked

6868 */

6869 UINT32 SmmlockRsvd : 1;

6870

6871 /* Bits[3:3], Access Type=RW, default=0x00000000*/

6872

6873 /* Reserved for implemention in JKT */

6874 UINT32 ScheckPass : 1;

6875

6876 /* Bits[4:4], Access Type=RW, default=0x00000000*/

6877

6878 /*

6879 This bit is set once by SCHECK once it passes.

6880 it is cleared by the SCHECK_PASS_clr bit.

6881 */

6882 UINT32 Poison : 1;

6883

6884 /* Bits[5:5], Access Type=RW, default=0x00000000*/

6885

6886 /*

6887 ucode will set this bit whenever it sends out a

6888 poison cycle. cleared by PoisonClr bit.

6889 */

6890 UINT32 Private : 1;

6891

6892 /* Bits[6:6], Access Type=RW, default=0x00000000*/

6893

6894 /*

6895 This bit is copied in the NCU and Cbo. This bit

6896 is cleared by the PrivateClr bit. Read : 0 -

6897 Private flag is cleared 1 - Private flag is set

6898 Write : 0 - ignored 1 -Set the Private flag

6899 */

6900 UINT32 Inacm : 1;

6901

6902 /* Bits[7:7], Access Type=RW, default=0x00000000*/

6903

6904 /*

6905 This bit is copied in the NCU IMPH and Cbo. This

6906 bit is cleared by the respective bit in

6907 NcuLTCtrClr register. Read : 0 - In ACM flag is

6908 cleared 1 - In ACM flag is set Write : 0 -

6909 ignored 1 -Set the InACM flag

6910 */

6911 UINT32 Loc3guarddis : 1;

6912

6913 /* Bits[8:8], Access Type=RW, default=0x00000000*/

6914

6915 /*

6916 This bit is implemented in the Cbo and has a

6917 shadow in NCU. This bit is cleared by writint a

6918 1 to the respective bit in NcuLTCtrClr register.

6919 Read : 0 - Locality 3 Guard is Enabled 1 -

6920 Locality 3 Guard is Disable Write : 0 - ignored

6921 1 -Set the Loc3Guard

6922 */

6923 UINT32 Hskinprog : 1;

6924

6925 /* Bits[9:9], Access Type=RW, default=0x00000000*/

6926

6927 /*

6928 Indicates that the core is in the process of

6929 SENTER or SEXIT handshake. This is a sticky bit

6930 used by uCode as part of LT flow. No HW action

6931 in NCU. This bit is cleared by writint a 1 to

6932 the respective bit in NcuLTCtrClr register. Read

6933 : 0 - Hand Shake not in progress 1 - Hand Shake

6934 in progress Write : 0 - ignored 1 -Set the

6935 HskInProg

6936 */

6937 UINT32 Faterrdursacm : 1;

6938

6939 /* Bits[10:10], Access Type=RW, default=0x00000000*/

6940

6941 /*

6942 FATAL_ERROR_DURING_SACM Indicates that an error

6943 occurred during Startup ACM processing that

6944 caused an LT-shutdown. This register is

6945 preserved across warm reset, so reset uCode can

6946 check this bit and skip Startup ACM processing

6947 if it is set to prevent an infinite loop of

6948 resets This is a sticky bit used by uCode as

6949 part of LT flow. No HW action in NCU. This bit

6950 is cleared by writint a 1 to the respective bit

6951 in NcuLTCtrClr register. Read : 0 - No Error 1 -

6952 Fatal Error During SACM Write : 0 - ignored 1

6953 -Set the FatErrDurSACM

6954 */

6955 UINT32 IlpMsegValid : 1;

6956

6957 /* Bits[11:11], Access Type=RW, default=0x00000000*/

6958

6959 /*

6960 This is a sticky bit used by uCode as part of LT

6961 flow. It is used to stash the ILP's copy of

6962 FSCP_CR_VMX_MSEG_BASE[VALID]. It is used by

6963 UCODE for consistency check to verify that all

6964 threads select the same type of SMM handling. No

6965 HW action in NCU. This bit is cleared by writing

6966 a 1 to the respective bit in NcuLTCtrClr

6967 register. Read : 0 - Bit is at cleared state 1 -

6968 Bit is set state Write : 0 - ignored 1 -Set the

6969 ILP_MSEG_VALID

6970 */

6971 UINT32 PostSenter : 1;

6972

6973 /* Bits[12:12], Access Type=RW, default=0x00000000*/

6974

6975 /*

6976 This is a sticky bit used by uCode as part of LT

6977 flow. The POST_SENTER bit will be set between

6978 SENTER and SEXIT. It is used to detect

6979 spontaneous reset during secure mode. The

6980 POST_SENTER bit must survive warm reset. It will

6981 be checked along with the existing AC-mode check

6982 in reset UCODE. No HW action in NCU. This bit is

6983 cleared by writing a 1 to the respective bit in

6984 NcuLTCtrClr register. Read : 0 - Bit is at

6985 cleared state 1 - Bit is set state Write : 0 -

6986 ignored 1 -Set the POST_SENTER bit

6987 */

6988 UINT32 LtScp3Rsrv : 1;

6989

6990 /* Bits[13:13], Access Type=RW, default=0x00000000*/

6991

6992 /*

6993 This is a sticky bit used by uCode as part of LT

6994 flow - currently as spare bit. No HW action in

6995 NCU. This bit is cleared by writint a 1 to the

6996 respective bit in NcuLTCtrClr register. Read : 0

6997 - Bit is at cleared state 1 - Bit is set state

6998 Write : 0 - ignored 1 -Set the LT_scp3_rsrv

6999 */

7000 UINT32 Rsvd14 : 2;

7001

7002 /* Bits[15:14], Access Type=RO, default=None*/

7003

7004 /* Reserved */

7005 UINT32 Configunloc : 1;

7006

7007 /* Bits[16:16], Access Type=RW, default=0x00000000*/

7008

7009 /*

7010 Writing a value of 0 to this bit has no effect.

7011 Writing a value of 1 to this bit will clear the

7012 ConfigLock flag. NOTE: The HW can assume that

7013 only SW in ACM mode will write to this bit a

7014 value of 1.

7015 */

7016 UINT32 Memlockcpuclr : 1;

7017

7018 /* Bits[17:17], Access Type=RW, default=0x00000000*/

7019

7020 /*

7021 Writing 1 to this bit clears MemLockCPU bit in

7022 this register. Writing 0 to this bit has no

7023 effect.

7024 */

7025 UINT32 Memlockdevclr : 1;

7026

7027 /* Bits[18:18], Access Type=RW, default=0x00000000*/

7028

7029 /*

7030 Writing 1 to this bit clears MemLockDev bit in

7031 this register. Writing 0 to this bit has no

7032 effect.

7033 */

7034 UINT32 SmmlockclrReserved : 1;

7035

7036 /* Bits[19:19], Access Type=RW, default=0x00000000*/

7037

7038 /* Reserved for use by JKT with SMMLock bit. */

7039 UINT32 ScheckPassClr : 1;

7040

7041 /* Bits[20:20], Access Type=RW, default=0x00000000*/

7042

7043 /*

7044 0 : Ignored 1 : Clear the SCHECK_PASS bit in

7045 this register.

7046 */

7047 UINT32 Poisonclr : 1;

7048

7049 /* Bits[21:21], Access Type=RW, default=0x00000000*/

7050

7051 /*

7052 0 : Ignored 1 : Clear the Poison bit in this

7053 register.

7054 */

7055 UINT32 Privateclr : 1;

7056

7057 /* Bits[22:22], Access Type=RW, default=0x00000000*/

7058

7059 /*

7060 0 : Ignored 1 : Clear the Private bit in this

7061 register.

7062 */

7063 UINT32 Inacmclr : 1;

7064

7065 /* Bits[23:23], Access Type=RW, default=0x00000000*/

7066

7067 /* 0 : ignored 1 : Clears the InACM flag */

7068 UINT32 Loc3guarddisclear : 1;

7069

7070 /* Bits[24:24], Access Type=RW, default=0x00000000*/

7071

7072 /*

7073 Write : If Loc3GuardDis=0 (including the result

7074 of this write) - Ignored. else 0 - ignored 1 -

7075 Clear the Loc3GuardDis flag

7076 */

7077 UINT32 Hskinprogclr : 1;

7078

7079 /* Bits[25:25], Access Type=RW, default=0x00000000*/

7080

7081 /*

7082 Write : If HskInProgs=0 (including the result of

7083 this write) - Ignored. else 0 - ignored 1 -

7084 Clear the HskInProg flag

7085 */

7086 UINT32 Faterrdursacmclr : 1;

7087

7088 /* Bits[26:26], Access Type=RW, default=0x00000000*/

7089

7090 /*

7091 Write : If FatErrDurSACM=0 (including the result

7092 of this write) - Ignored. else 0 - ignored 1 -

7093 Clear the FatErrDurSACM flag

7094 */

7095 UINT32 IlpMsegValidClr : 1;

7096

7097 /* Bits[27:27], Access Type=RW, default=0x00000000*/

7098

7099 /*

7100 Write : If ILP_MSEG_VALID=0 (including the

7101 result of this write) - Ignored. else 0 -

7102 ignored 1 - Clear the ILP_MSEG_VALID flag

7103 */

7104 UINT32 PostSenterClr : 1;

7105

7106 /* Bits[28:28], Access Type=RW, default=0x00000000*/

7107

7108 /*

7109 Write : If POST_SENTER=0 (including the result

7110 of this write) - Ignored. else 0 - ignored 1 -

7111 Clear the POST_SENTER flag

7112 */

7113 UINT32 LtScp3RsrvClr : 1;

7114

7115 /* Bits[29:29], Access Type=RW, default=0x00000000*/

7116

7117 /*

7118 Write : If LT_scp3_rsrv=0 (including the result

7119 of this write) - Ignored. else 0 - ignored 1 -

7120 Clear the LT_scp3_rsrv flag

7121 */

7122 UINT32 Ltpmonctrclr : 1;

7123

7124 /* Bits[30:30], Access Type=RW, default=0x00000000*/

7125

7126 /*

7127 This bit is copied in the NCU and Cbo. This bit

7128 is used for LT uCode control over the PMON

7129 counters. The NCU copy of the register must be

7130 cleared last to prevent race conditions with

7131 clear operations of other module's counters. 0b

7132 No action 1b Clear all PMON control registers

7133 (including Fixed counter control)

7134 */

7135 UINT32 Ltpmoncntclr : 1;

7136

7137 /* Bits[31:31], Access Type=RW, default=0x00000000*/

7138

7139 /*

7140 This bit is copied in the NCU and Cbo. This bit

7141 is used for LT uCode control over the PMON

7142 counters. 0b No Action 1b Clear all PMON Counter

7143 registers and Unit overflow status registers

7144 (including Fixed Counter and Global Overflow

7145 Status).

7146 */

7147

7148 } Bits;

7149

7150 UINT32 Uint32;

7151 UINT64 Uint64;

7152

7153 } MSR_LTCTRLSTS_REGISTER;

7154

7155 /**

7156 ACM Only MSR for EDRAM management

7157 **/

7158 #define MSR_EDRAM_ACM 0x000002E8

7159

7160 typedef union {

7161 ///

7162 /// Individual bit fields

7163 ///

7164 struct {

7165 UINT32 ForceEdramDisabled : 1;

7166

7167 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7168

7169 /* */

7170 UINT32 EdramIsDisabled : 1;

7171

7172 /* Bits[1:1], Access Type=RW, default=0x00000000*/

7173

7174 /* eDRAM is disabled as a result of force disable */

7175 UINT32 EdramExists : 1;

7176

7177 /* Bits[2:2], Access Type=RW, default=0x00000000*/

7178

7179 /* */

7180 UINT32 Rsvd3 : 29;

7181

7182 /* Bits[31:3], Access Type=RO, default=None*/

7183

7184 /* Reserved */

7185 UINT32 Rsvd32 : 32;

7186

7187 /* Bits[63:32], Access Type=RO, default=None*/

7188

7189 /* Reserved */

7190

7191 } Bits;

7192

7193 UINT32 Uint32;

7194 UINT64 Uint64;

7195

7196 } MSR_EDRAM_ACM_REGISTER;

7197 /**

7198 External 128-bit entropy for SGX keys derivation

7199 **/

7200 #define MSR_SE_EPOCH_0 0x00000300

7201 /**

7202 External 128-bit entropy for SGX keys derivation

7203 **/

7204 #define MSR_SE_EPOCH_1 0x00000301

7205

7206 /**

7207 MSR to read and update SGX SVN by BIOS

7208 **/

7209 #define MSR_BIOS_SE_SVN 0x00000302

7210

7211 typedef union {

7212 ///

7213 /// Individual bit fields

7214 ///

7215 struct {

7216 UINT32 Reserved0 : 16;

7217

7218 /* Bits[15:0], Access Type=RO_V, default=None*/

7219

7220 /* */

7221 UINT32 SinitSeSvn : 8;

7222

7223 /* Bits[23:16], Access Type=RO_V, default=None*/

7224

7225 /* Security Version Number for the SINIT ACM */

7226 UINT32 ScleanSeSvn : 8;

7227

7228 /* Bits[31:24], Access Type=RO_V, default=None*/

7229

7230 /* Security Version Number for the SCLEAN ACM */

7231 UINT32 AncSeSvn : 8;

7232

7233 /* Bits[39:32], Access Type=RO_V, default=None*/

7234

7235 /* Security Version Number for SGX HW */

7236 UINT32 PfatSeSvn : 8;

7237

7238 /* Bits[47:40], Access Type=RO_V, default=None*/

7239

7240 /* Security Version Number for the PFAT ACM */

7241 UINT32 Reserved48 : 16;

7242

7243 /* Bits[63:48], Access Type=RO_V, default=None*/

7244

7245 /* */

7246

7247 } Bits;

7248

7249 UINT32 Uint32;

7250 UINT64 Uint64;

7251

7252 } MSR_BIOS_SE_SVN_REGISTER;

7253 /**

7254 BOOT MSR for communicating boot protocol to MCHECK uses NcuScratchpad26

7255 **/

7256 #define MSR_MCHECK_BOOT_SCENARIO 0x00000304

7257

7258 /**

7259 IVB i1026245 - PerfMon Compound Counter enhancement

7260 **/

7261 #define MSR_COMPOUND_CTR_CTRL 0x00000306

7262

7263 typedef union {

7264 ///

7265 /// Individual bit fields

7266 ///

7267 struct {

7268 UINT32 FlopCtr0Inc : 3;

7269

7270 /* Bits[2:0], Access Type=RW, default=0x00000000*/

7271

7272 /* Flopped counter 0 inc */

7273 UINT32 FlopCtr1Inc : 3;

7274

7275 /* Bits[5:3], Access Type=RW, default=0x00000000*/

7276

7277 /* Flopped counter 1 inc */

7278 UINT32 FlopCtr2Inc : 3;

7279

7280 /* Bits[8:6], Access Type=RW, default=0x00000000*/

7281

7282 /* Flopped counter 2 inc */

7283 UINT32 FlopCtr3Inc : 3;

7284

7285 /* Bits[11:9], Access Type=RW, default=0x00000000*/

7286

7287 /* Flopped counter 3 inc */

7288 UINT32 Flop0 : 1;

7289

7290 /* Bits[12:12], Access Type=RW, default=0x00000000*/

7291

7292 /* Flopped signal 0 */

7293 UINT32 Flop1 : 1;

7294

7295 /* Bits[13:13], Access Type=RW, default=0x00000000*/

7296

7297 /* Flopped signal 1 */

7298 UINT32 Flop2 : 1;

7299

7300 /* Bits[14:14], Access Type=RW, default=0x00000000*/

7301

7302 /* Flopped signal 2 */

7303 UINT32 Flop3 : 1;

7304

7305 /* Bits[15:15], Access Type=RW, default=0x00000000*/

7306

7307 /* Flopped signal 3 */

7308 UINT32 OrFlop0123 : 1;

7309

7310 /* Bits[16:16], Access Type=RW, default=0x00000000*/

7311

7312 /* OR of Flopped signals 0,1,2,3 */

7313 UINT32 OrFlop012 : 1;

7314

7315 /* Bits[17:17], Access Type=RW, default=0x00000000*/

7316

7317 /* OR of Flopped signals 0,1,2 */

7318 UINT32 OrFlop01 : 1;

7319

7320 /* Bits[18:18], Access Type=RW, default=0x00000000*/

7321

7322 /* OR of Flopped signals 0,1 */

7323 UINT32 OrFlop23 : 1;

7324

7325 /* Bits[19:19], Access Type=RW, default=0x00000000*/

7326

7327 /* OR of Flopped signals 2,3 */

7328 UINT32 Pmi : 1;

7329

7330 /* Bits[20:20], Access Type=RW, default=0x00000000*/

7331

7332 /*

7333 APIC interrupt enable. When set, the processor

7334 generates an exception through its local APIC on

7335 counter overflow for this counter's thread. This

7336 bit gets AND-ed with the overflow of the counter

7337 and Not the GlobalStatus overflow of the

7338 counter. This means that the GlobalStatus

7339 Overflow flag cannot cause a PMI.

7340 */

7341 UINT32 MythrAllthr : 1;

7342

7343 /* Bits[21:21], Access Type=RW, default=0x00000000*/

7344

7345 /*

7346 The 8 general counters have been divided into

7347 two banks T0 and T1 for each thread. When this

7348 bit is set to zero the counters in each bank

7349 counts its own predominant thread type. If set

7350 to 1 the counters counts events for both

7351 threads. Note, a counter can never be programmed

7352 to only count the none predominant thread.

7353 */

7354 UINT32 Enable : 1;

7355

7356 /* Bits[22:22], Access Type=RW, default=0x00000000*/

7357

7358 /*

7359 This field is the local enable for PerfMon

7360 Counter. This bit must be asserted in order for

7361 the PerfMon counter to begin counting the events

7362 selected by the 'event select', 'unit mask'.

7363 This bit gets AND-ed with the respective global

7364 enable bit in register IA32_CR_PERF_GLOBAL_CTRL

7365 to enable the counter to count.

7366 */

7367 UINT32 Invert : 1;

7368

7369 /* Bits[23:23], Access Type=RW, default=0x00000000*/

7370

7371 /*

7372 This field controls the counting behavior of the

7373 compound counter. When set to '1' the compound

7374 counter will count cycles that the compound

7375 event did not occur, When set to '0' the

7376 compound counter will count cycles that the

7377 compound event did occur.

7378 */

7379 UINT32 EdgeDetect : 1;

7380

7381 /* Bits[24:24], Access Type=RW, default=0x00000000*/

7382

7383 /*

7384 When this bit is set to 0 no edge detection is

7385 performed. We set to 1 edge detection is enabled

7386 and detects when an event has crossed the

7387 threshold value. For example if the threshold is

7388 set to 2 and the current count is 0 and then on

7389 the next cycle the current count is 2 or greater

7390 an edge detection will ocurr which signals the

7391 incrementer to increment by one. The if on the

7392 next cycle The count coming is 2 or greater edge

7393 detection will not fire. Now lets say five cycle

7394 later the value drops to below two and then a

7395 cycle later rises to two or greater an edge

7396 detect will fire. Edge detection only signals

7397 the counter to increment by 1. Note -> If edge

7398 detection is set to 1 and the threshold is set

7399 to zero edge detection is meaningless and

7400 becomes disabled. This is because you can never

7401 dip below a value of 0.

7402 */

7403 UINT32 Rsvd25 : 7;

7404

7405 /* Bits[31:25], Access Type=RO, default=None*/

7406

7407 /* Reserved */

7408 UINT32 Rsvd32 : 29;

7409

7410 /* Bits[60:32], Access Type=RO, default=None*/

7411

7412 /* Reserved */

7413 UINT32 UbrkptCtr0 : 1;

7414

7415 /* Bits[61:61], Access Type=RW, default=0x00000000*/

7416

7417 /* Override counter 0 MicroBreakPoint */

7418 UINT32 Forceubrkpt : 1;

7419

7420 /* Bits[62:62], Access Type=RW, default=0x00000000*/

7421

7422 /*

7423 When set a MicroBreakPoint occurs each time a

7424 none zero Event enters the counter.

7425 */

7426 UINT32 Rsvd63 : 1;

7427

7428 /* Bits[63:63], Access Type=RO, default=None*/

7429

7430 /* Reserved */

7431

7432 } Bits;

7433

7434 UINT32 Uint32;

7435 UINT64 Uint64;

7436

7437 } MSR_COMPOUND_CTR_CTRL_REGISTER;

7438

7439 /**

7440 IVB i1026245 - PerfMon Compound Counter enhancement

7441 **/

7442 #define MSR_COMPOUND_PERF_CTR 0x00000307

7443

7444 typedef union {

7445 ///

7446 /// Individual bit fields

7447 ///

7448 struct {

7449 UINT32 Lower : 32;

7450

7451 /* Bits[31:0], Access Type=RW, default=0x00000000*/

7452

7453 /* Lower Half of COMPOUND PERF CTR */

7454 UINT32 Upper : 16;

7455

7456 /* Bits[47:32], Access Type=RW, default=0x00000000*/

7457

7458 /* Upper Half of COMPOUND PERF CTR */

7459 UINT32 Rsvd48 : 16;

7460

7461 /* Bits[63:48], Access Type=RO, default=None*/

7462

7463 /* Reserved */

7464

7465 } Bits;

7466

7467 UINT32 Uint32;

7468 UINT64 Uint64;

7469

7470 } MSR_COMPOUND_PERF_CTR_REGISTER;

7471

7472 /**

7473 The BM_DETECT_CTRL is used to enable Branck Monitoring detection (BM), enable PMI exceptions

7474 on BM detect, set BM window size, determine counting method for BM window, and

7475 determine if trip is due to all counting conditions being met.

7476 **/

7477 #define MSR_ROP_DETECT_CTRL 0x00000350

7478

7479 typedef union {

7480 ///

7481 /// Individual bit fields

7482 ///

7483 struct {

7484 UINT32 EnRopDetect : 1;

7485

7486 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7487

7488 /* Global enable for Branch Monitoring counting. */

7489 UINT32 EnRopExcept : 1;

7490

7491 /* Bits[1:1], Access Type=RW, default=0x00000000*/

7492

7493 /*

7494 Enable Branch Monitoring event signaling on

7495 thresholds trip. Event will be signaled via PMI

7496 signaling mechanism.

7497 */

7498 UINT32 EnRopLbrFrz : 1;

7499

7500 /* Bits[2:2], Access Type=RW, default=0x00000000*/

7501

7502 /*

7503 Enable LBR freeze on Branch Monitoring threshold

7504 trip.

7505 */

7506 UINT32 RopGuestDisable : 1;

7507

7508 /* Bits[3:3], Access Type=RW, default=0x00000000*/

7509

7510 /*

7511 When set to 1, Branch Montoring event triggering

7512 and LBR freeze actions are disabled when

7513 operating at VMX non-root operation.

7514 */

7515 UINT32 Rsvd4 : 4;

7516

7517 /* Bits[7:4], Access Type=RW, default=0x00000000*/

7518

7519 /* Reserved bits. */

7520 UINT32 RopWindowSize : 10;

7521

7522 /* Bits[17:8], Access Type=RW, default=0x00000000*/

7523

7524 /*

7525 Branch Monitoring window size. Default is 1023.

7526 Legal range is 8 - 1023.

7527 */

7528 UINT32 Rsvd18 : 6;

7529

7530 /* Bits[23:18], Access Type=RO, default=None*/

7531

7532 /* Reserved */

7533 UINT32 WindowCntSel : 2;

7534

7535 /* Bits[25:24], Access Type=RW, default=0x00000000*/

7536

7537 /*

7538 Window count Options: 00 - Instructions retired.

7539 01 - Branches retired. 10 - Return instructions

7540 retired. 11 - Indirect branches retired.

7541 */

7542 UINT32 CntAndMode : 1;

7543

7544 /* Bits[26:26], Access Type=RW, default=0x00000000*/

7545

7546 /*

7547 When set to 1, then threshold trip occurs only

7548 if threshold conditions are true for all enabled

7549 event counters. When set to 0, then threshold

7550 trip occurs if either counter's onditions are

7551 true. If a counter is not enabled then it does

7552 not factor into the AND logic.

7553 */

7554 UINT32 EnRopEventFilter : 1;

7555

7556 /* Bits[27:27], Access Type=RW, default=0x00000000*/

7557

7558 /*

7559 Global enable for Branch Monitoring Event

7560 filtering.

7561 */

7562 UINT32 Rsvd28 : 4;

7563

7564 /* Bits[31:28], Access Type=RO, default=None*/

7565

7566 /* Reserved */

7567

7568 } Bits;

7569

7570 UINT32 Uint32;

7571 UINT64 Uint64;

7572

7573 } MSR_ROP_DETECT_CTRL_REGISTER;

7574

7575 /**

7576 Branch Monitoring detect status - threshold tripped, which counter tripped, and tripping count.

7577 **/

7578 #define MSR_ROP_DETECT_STATUS 0x00000351

7579

7580 typedef union {

7581 ///

7582 /// Individual bit fields

7583 ///

7584 struct {

7585 UINT32 Ropevent : 1;

7586

7587 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7588

7589 /*

7590 A Branch Monitoring event was detected. When

7591 this event status bit is set to 1, no further

7592 logging is performed until this status bit is

7593 cleared by software.

7594 */

7595 UINT32 Roplbrsvalid : 1;

7596

7597 /* Bits[1:1], Access Type=RO_V, default=0x00000000*/

7598

7599 /*

7600 Set to 1 if the LBR state is considered valid

7601 for sampling.

7602 */

7603 UINT32 Rsvd2 : 6;

7604

7605 /* Bits[7:2], Access Type=RO, default=None*/

7606

7607 /* Reserved */

7608 UINT32 Ropcntrhit0 : 1;

7609

7610 /* Bits[8:8], Access Type=RO_V, default=0x00000000*/

7611

7612 /*

7613 Set to 1 when Branch Monitoring counter 0 caused

7614 threshold trip.

7615 */

7616 UINT32 Ropcntrhit1 : 1;

7617

7618 /* Bits[9:9], Access Type=RO_V, default=0x00000000*/

7619

7620 /*

7621 Set to 1 when Branch Monitoring counter 1 caused

7622 threshold trip.

7623 */

7624 UINT32 Rsvd10 : 6;

7625

7626 /* Bits[15:10], Access Type=RO, default=None*/

7627

7628 /* Reserved */

7629 UINT32 Ropwindowcount : 10;

7630

7631 /* Bits[25:16], Access Type=RW_V, default=0x00000000*/

7632

7633 /*

7634 Current value of window counter. The count value

7635 is frozen on a valid event triggering condition.

7636 A 10-bit unsigned value.

7637 */

7638 UINT32 Rsvd26 : 6;

7639

7640 /* Bits[31:26], Access Type=RO, default=None*/

7641

7642 /* Reserved */

7643 UINT32 Ropcount0 : 8;

7644

7645 /* Bits[39:32], Access Type=RW_V, default=0x00000000*/

7646

7647 /*

7648 Measured count over the last window period for

7649 Counter 0.

7650 */

7651 UINT32 Ropcount1 : 8;

7652

7653 /* Bits[47:40], Access Type=RW_V, default=0x00000000*/

7654

7655 /*

7656 Measured count over the last window period for

7657 Counter 1.

7658 */

7659 UINT32 Rsvd48 : 16;

7660

7661 /* Bits[63:48], Access Type=RO, default=None*/

7662

7663 /* Reserved */

7664

7665 } Bits;

7666

7667 UINT32 Uint32;

7668 UINT64 Uint64;

7669

7670 } MSR_ROP_DETECT_STATUS_REGISTER;

7671

7672 /**

7673 Branch Monitoring Detect Capabilities

7674 **/

7675 #define MSR_ROP_DETECT_CAPABILITIES 0x00000352

7676

7677 typedef union {

7678 ///

7679 /// Individual bit fields

7680 ///

7681 struct {

7682 UINT32 RopDetect : 1;

7683

7684 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7685

7686 /*

7687 1 - Branch Monitoring Detection is supported 0 -

7688 Branch Monitoring Detection is not supported

7689 */

7690 UINT32 RopEventFiltering : 1;

7691

7692 /* Bits[1:1], Access Type=RW, default=0x00000001*/

7693

7694 /*

7695 1 - Branch Monitoring Event Filtering is

7696 supported 0 - ROP Event Filtering is not

7697 supported

7698 */

7699 UINT32 Rsvd2 : 6;

7700

7701 /* Bits[7:2], Access Type=RO, default=None*/

7702

7703 /* Reserved */

7704 UINT32 RopCounterNumber : 4;

7705

7706 /* Bits[11:8], Access Type=RW, default=0x00000002*/

7707

7708 /*

7709 Number of supported counters (Number of

7710 BM_COUNTER_CONFIG_i MSRs)

7711 */

7712 UINT32 RopFiltersNumber : 4;

7713

7714 /* Bits[15:12], Access Type=RW, default=0x00000001*/

7715

7716 /*

7717 Number of supportedevent filters

7718 (BM_EVENT_FILTERx MSRs)

7719 */

7720 UINT32 Rsvd16 : 8;

7721

7722 /* Bits[23:16], Access Type=RO, default=None*/

7723

7724 /* Reserved */

7725 UINT32 RopFilterSupported : 8;

7726

7727 /* Bits[31:24], Access Type=RW, default=0x00000001*/

7728

7729 /*

7730 Bitmask of supported event filers. Each bit of

7731 FilterTypesSupported filed corresponds to a

7732 specific event filter: Bit 16: Stack Pivoting

7733 Detection Bits 17-23 reserved

7734 */

7735 UINT32 Rsvd32 : 32;

7736

7737 /* Bits[63:32], Access Type=RO, default=None*/

7738

7739 /* Reserved */

7740

7741 } Bits;

7742

7743 UINT32 Uint32;

7744 UINT64 Uint64;

7745

7746 } MSR_ROP_DETECT_CAPABILITIES_REGISTER;

7747

7748 /**

7749 Counter_0: Counter enables, events selection, counter trip threshold.

7750 **/

7751 #define MSR_ROP_COUNTER_CONFIG_0 0x00000354

7752

7753 typedef union {

7754 ///

7755 /// Individual bit fields

7756 ///

7757 struct {

7758 UINT32 RopCntrEn : 1;

7759

7760 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7761

7762 /* Enable Branch Monitoring Counter 0. */

7763 UINT32 RopCntrEvSel : 7;

7764

7765 /* Bits[7:1], Access Type=RW, default=0x00000000*/

7766

7767 /*

7768 Counter_0 event select: 0 - RET 1 - RET - Call

7769 bias 2 - RET mispredicts (at retirement) 3 -

7770 Branch mispredicts (at retirement) 4 - Indirect

7771 branch mispredicts (at front-end) 5 - Far branch

7772 instructions (at retirement) 6 - 127 - reserved.

7773 */

7774 UINT32 RopCntrThreshold : 7;

7775

7776 /* Bits[14:8], Access Type=RW, default=0x00000000*/

7777

7778 /*

7779 Counter_0 Threshold trip count. Legal values are

7780 0 - 127.

7781 */

7782 UINT32 MispredEventCnt : 1;

7783

7784 /* Bits[15:15], Access Type=RW, default=0x00000000*/

7785

7786 /*

7787 Mispredict counting behavior: 0 - all

7788 mispredicts are counted in a window. 1 - Only

7789 consecutive mispredicts are counted in a window.

7790 (i.e. correctly predicted event clears the

7791 count.)

7792 */

7793 UINT32 Rsvd16 : 8;

7794

7795 /* Bits[23:16], Access Type=RO, default=None*/

7796

7797 /* Reserved */

7798 UINT32 RopFilterEnable : 1;

7799

7800 /* Bits[24:24], Access Type=RW, default=0x00000000*/

7801

7802 /*

7803 Branch Monitoring filter enable for counter_0: 0

7804 - No additional event filter is enabled for this

7805 counter 1 - Filter 0 is enabled for this counter

7806 (defined by BM_EVENT_FILTER0)

7807 */

7808 UINT32 Rsvd25 : 7;

7809

7810 /* Bits[31:25], Access Type=RO, default=None*/

7811

7812 /* Reserved */

7813

7814 } Bits;

7815

7816 UINT32 Uint32;

7817 UINT64 Uint64;

7818

7819 } MSR_ROP_COUNTER_CONFIG_0_REGISTER;

7820

7821 /**

7822 Counter_1: Counter enables, events selection, counter trip threshold.

7823 **/

7824 #define MSR_ROP_COUNTER_CONFIG_1 0x00000355

7825

7826 typedef union {

7827 ///

7828 /// Individual bit fields

7829 ///

7830 struct {

7831 UINT32 RopCntrEn : 1;

7832

7833 /* Bits[0:0], Access Type=RW, default=0x00000000*/

7834

7835 /* Enable Counter_1. */

7836 UINT32 RopCntrEvSel : 7;

7837

7838 /* Bits[7:1], Access Type=RW, default=0x00000000*/

7839

7840 /*

7841 Counter_1 event select. Legal combinations are:

7842 0 - RET 1 - RET - Call bias 2 - RET mispredicts

7843 (at retirement) 3 - Branch mispredicts (at

7844 retirement) 4 - Indirect branch mispredicts (at

7845 front-end) 5 - Far branch instructions (at

7846 retirement) 6 - 127 - reserved

7847 */

7848 UINT32 RopCntrThreshold : 7;

7849

7850 /* Bits[14:8], Access Type=RW, default=0x00000000*/

7851

7852 /*

7853 Counter_1 Threshold trip count. Legal values are

7854 0 - 127.

7855 */

7856 UINT32 MispredEventCnt : 1;

7857

7858 /* Bits[15:15], Access Type=RW, default=0x00000000*/

7859

7860 /*

7861 Mispredict counting behavior: 0 - all

7862 mispredicts are counted in a window. 1 -

7863 consecutive mispredicts are counted in a window.

7864 (i.e. correctly predicted event clears the

7865 count.)

7866 */

7867 UINT32 Rsvd16 : 8;

7868

7869 /* Bits[23:16], Access Type=RO, default=None*/

7870

7871 /* Reserved */

7872 UINT32 RopFilterEnable : 1;

7873

7874 /* Bits[24:24], Access Type=RW, default=0x00000000*/

7875

7876 /*

7877 Branch Monitoring filter enable for counte_1: 0

7878 - No additional event filter is enabled for this

7879 counter 1 - Filter 0 is enabled for this counter

7880 (defined by BM_EVENT_FILTER0)

7881 */

7882 UINT32 Rsvd25 : 7;

7883

7884 /* Bits[31:25], Access Type=RO, default=None*/

7885

7886 /* Reserved */

7887

7888 } Bits;

7889

7890 UINT32 Uint32;

7891 UINT64 Uint64;

7892

7893 } MSR_ROP_COUNTER_CONFIG_1_REGISTER;

7894

7895 /**

7896 Branch Monitoring event filter 0

7897 **/

7898 #define MSR_ROP_EVENT_FILTER0 0x00000360

7899

7900 typedef union {

7901 ///

7902 /// Individual bit fields

7903 ///

7904 struct {

7905 UINT32 RopFilterType : 4;

7906

7907 /* Bits[3:0], Access Type=RW, default=0x00000000*/

7908

7909 /*

7910 Type of additional Branch Monitoring event

7911 filtering configured 0000 - No event filter is

7912 configured 0001 - "Stack Pivoting Detection"

7913 Heuristic 1111 - 0010 = Reserved

7914 */

7915 UINT32 RopFilterHit : 1;

7916

7917 /* Bits[4:4], Access Type=RW, default=0x00000000*/

7918

7919 /*

7920 0 - Filter didn't detect ROP condition 1 -

7921 Filter detected ROP condition

7922 */

7923 UINT32 Rsvd5 : 3;

7924

7925 /* Bits[7:5], Access Type=RO, default=None*/

7926

7927 /* Reserved */

7928 UINT32 RopStackBase0 : 24;

7929

7930 /* Bits[31:8], Access Type=RW, default=0x00000000*/

7931

7932 /*

7933 Event Filter Specific Configuration. Contents of

7934 this field depend on the type of filtering used

7935 defined by FilterType field. For Stack Pivoting

7936 Filter this can be set as 256 byte aligned

7937 linear address of the base of the stack range.

7938 */

7939 UINT32 RopStackBase1 : 32;

7940

7941 /* Bits[63:32], Access Type=RW, default=0x00000000*/

7942

7943 /*

7944 Event Filter Specific Configuration. Contents of

7945 this field depend on the type of filtering used

7946 defined by FilterType field. For Stack Pivoting

7947 Filter this can be set as 256 byte aligned

7948 linear address of the base of the stack range.

7949 */

7950

7951 } Bits;

7952

7953 UINT32 Uint32;

7954 UINT64 Uint64;

7955

7956 } MSR_ROP_EVENT_FILTER0_REGISTER;

7957 /**

7958 ROP event filter 0 Data

7959 **/

7960 #define MSR_ROP_EVENT_FILTER0_DATA 0x00000361

7961

7962 /**

7963 This MSR displays the programming status of all the PerfMon counters.

7964 It is a per logical processor read-only MSR used to observe the [IntelRsvd]?in-use?[/IntelRsvd] status of all the counters at once.

7965 [IntelRsvd]It is made architectural starting Skylake called IA32_PERF_GLOBAL_INUSE (MSR address 0x392)[/IntelRsvd]

7966 **/

7967 #define MSR_EMON_PERF_RES_PROGRAMMED 0x00000392

7968

7969 typedef union {

7970 ///

7971 /// Individual bit fields

7972 ///

7973 struct {

7974 UINT32 EnabledGenCntr : 8;

7975

7976 /* Bits[7:0], Access Type=RO_V, default=0x00000000*/

7977

7978 /*

7979 Counter is in-use for General Counters 7, 6, 5,

7980 4, 3, 2 ,1, 0 respectively. A '1 indicates the

7981 counter is in-use, that is the corresponding

7982 CORE_CR_PERMON_EVNTSEL_CNTrX.EVENT_SELECT[7:0]

7983 is non zero

7984 */

7985 UINT32 Rsvd8 : 24;

7986

7987 /* Bits[31:8], Access Type=RO, default=None*/

7988

7989 /* Reserved */

7990 UINT32 EnabledFixedCntr : 4;

7991

7992 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

7993

7994 /*

7995 Counter is in-use for Fixed Counters 3, 2 ,1, 0

7996 respectively. A '1 indicates the counter is in-

7997 use, that is its corresponding

7998 ROB1_CR_EMON_FIXED_CTR_CTRL.en_ctrX[1:0] is non

7999 zero

8000 CORE_CR_PERMON_EVNTSEL_CNTR.EVENT_SELECT[7:0] is

8001 non zero

8002 */

8003 UINT32 Rsvd36 : 27;

8004

8005 /* Bits[62:36], Access Type=RO, default=None*/

8006

8007 /* Reserved */

8008 UINT32 Pmi : 1;

8009

8010 /* Bits[63:63], Access Type=RO_V, default=0x00000000*/

8011

8012 /* PMI */

8013

8014 } Bits;

8015

8016 UINT32 Uint32;

8017 UINT64 Uint64;

8018

8019 } MSR_EMON_PERF_RES_PROGRAMMED_REGISTER;

8020

8021 /**

8022 IDP 1 PMON Counter 1 data register

8023 The Fix counter is counting UCLK cycles.

8024 All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

8025 **/

8026 #define MSR_PERFCTR0 0x000003B8

8027

8028 typedef union {

8029 ///

8030 /// Individual bit fields

8031 ///

8032 struct {

8033 UINT32 Pmonctrdata0 : 32;

8034

8035 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

8036

8037 /*

8038 Pmon Counter data. The register may be read and

8039 written when the counter is stopped.

8040 */

8041 UINT32 Pmonctrdata1 : 12;

8042

8043 /* Bits[43:32], Access Type=RW_V, default=0x00000000*/

8044

8045 /*

8046 Pmon Counter data. The register may be read and

8047 written when the counter is stopped.

8048 */

8049 UINT32 Rsvd44 : 20;

8050

8051 /* Bits[63:44], Access Type=RO, default=None*/

8052

8053 /* Reserved */

8054

8055 } Bits;

8056

8057 UINT32 Uint32;

8058 UINT64 Uint64;

8059

8060 } MSR_PERFCTR0_REGISTER;

8061

8062 /**

8063 IDP 1 PMON Counter 2 data register

8064 The Fix counter is counting UCLK cycles.

8065 All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

8066 **/

8067 #define MSR_PERFCTR1 0x000003B9

8068

8069 typedef union {

8070 ///

8071 /// Individual bit fields

8072 ///

8073 struct {

8074 UINT32 Pmonctrdata0 : 32;

8075

8076 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

8077

8078 /*

8079 Pmon Counter data. The register may be read and

8080 written when the counter is stopped.

8081 */

8082 UINT32 Pmonctrdata1 : 12;

8083

8084 /* Bits[43:32], Access Type=RW_V, default=0x00000000*/

8085

8086 /*

8087 Pmon Counter data. The register may be read and

8088 written when the counter is stopped.

8089 */

8090 UINT32 Rsvd44 : 20;

8091

8092 /* Bits[63:44], Access Type=RO, default=None*/

8093

8094 /* Reserved */

8095

8096 } Bits;

8097

8098 UINT32 Uint32;

8099 UINT64 Uint64;

8100

8101 } MSR_PERFCTR1_REGISTER;

8102

8103 /**

8104 Threshold value for the load latency

8105 **/

8106 #define MSR_PEBS_LD_LAT_THRESHOLD 0x000003F6

8107

8108 typedef union {

8109 ///

8110 /// Individual bit fields

8111 ///

8112 struct {

8113 UINT32 Thrshold : 16;

8114

8115 /* Bits[15:0], Access Type=RW, default=0x0000FFFF*/

8116

8117 /* Threshold for the Latency value */

8118 UINT32 Rsvd16 : 16;

8119

8120 /* Bits[31:16], Access Type=RO, default=None*/

8121

8122 /* Reserved */

8123

8124 } Bits;

8125

8126 UINT32 Uint32;

8127 UINT64 Uint64;

8128

8129 } MSR_PEBS_LD_LAT_THRESHOLD_REGISTER;

8130

8131 /**

8132 Precise Performance Monitoring (PPMON) Event Control. This register is read-write.

8133 **/

8134 #define MSR_PEBS_FRONTEND 0x000003F7

8135

8136 typedef union {

8137 ///

8138 /// Individual bit fields

8139 ///

8140 struct {

8141 UINT32 EventId : 3;

8142

8143 /* Bits[2:0], Access Type=RW, default=0x00000000*/

8144

8145 /*

8146 Choose which event to monitor (ie. 1: L1_IMISS,

8147 2: MLC_MISS, 3: ITLB_MISS, 4: STLB_MISS, 5:

8148 DSB_MISS, 6: IDQ_READ_BUBBLES)

8149 */

8150 UINT32 Rsvd3 : 1;

8151

8152 /* Bits[3:3], Access Type=RW, default=0x00000000*/

8153

8154 /* Reserved */

8155 UINT32 CriticalFilter : 1;

8156

8157 /* Bits[4:4], Access Type=RW, default=0x00000000*/

8158

8159 /*

8160 When asserted, cycles occurring while IDQ is

8161 empty are filtered, otherwise they are

8162 monitored.

8163 */

8164 UINT32 Rsvd5 : 3;

8165

8166 /* Bits[7:5], Access Type=RW, default=0x00000000*/

8167

8168 /* Reserved */

8169 UINT32 FeLatency : 12;

8170

8171 /* Bits[19:8], Access Type=RW, default=0x00000008*/

8172

8173 /*

8174 Number of consecutive cycles not having less

8175 than FE_THRESHOLD bubbles which must occur

8176 before logging the event.

8177 */

8178 UINT32 FeThreshold : 3;

8179

8180 /* Bits[22:20], Access Type=RW, default=0x00000000*/

8181

8182 /*

8183 Number of delivery bubbles (or more) of cycles

8184 to count. If number of delivery bubbles is

8185 greater than or equal to this field, then count

8186 it.

8187 */

8188 UINT32 Rsvd23 : 9;

8189

8190 /* Bits[31:23], Access Type=RW, default=0x00000000*/

8191

8192 /* Reserved */

8193

8194 } Bits;

8195

8196 UINT32 Uint32;

8197 UINT64 Uint64;

8198

8199 } MSR_PEBS_FRONTEND_REGISTER;

8200

8201 /**

8202 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

8203 **/

8204 #define MSR_PC3_RCNTR 0x000003F8

8205

8206 typedef union {

8207 ///

8208 /// Individual bit fields

8209 ///

8210 struct {

8211 UINT32 Data0 : 32;

8212

8213 /* Bits[31:0], Access Type=RW, default=0x00000000*/

8214

8215 /* Counter Value */

8216 UINT32 Data1 : 28;

8217

8218 /* Bits[59:32], Access Type=RW, default=0x00000000*/

8219

8220 /* Counter Value */

8221 UINT32 Rsvd60 : 4;

8222

8223 /* Bits[63:60], Access Type=RO, default=None*/

8224

8225 /* Reserved */

8226

8227 } Bits;

8228

8229 UINT32 Uint32;

8230 UINT64 Uint64;

8231

8232 } MSR_PC3_RCNTR_REGISTER;

8233

8234 /**

8235 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

8236 **/

8237 #define MSR_PC6_RCNTR 0x000003F9

8238

8239 typedef union {

8240 ///

8241 /// Individual bit fields

8242 ///

8243 struct {

8244 UINT32 Data0 : 32;

8245

8246 /* Bits[31:0], Access Type=RW, default=0x00000000*/

8247

8248 /* Counter Value */

8249 UINT32 Data1 : 28;

8250

8251 /* Bits[59:32], Access Type=RW, default=0x00000000*/

8252

8253 /* Counter Value */

8254 UINT32 Rsvd60 : 4;

8255

8256 /* Bits[63:60], Access Type=RO, default=None*/

8257

8258 /* Reserved */

8259

8260 } Bits;

8261

8262 UINT32 Uint32;

8263 UINT64 Uint64;

8264

8265 } MSR_PC6_RCNTR_REGISTER;

8266

8267 /**

8268 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

8269 **/

8270 #define MSR_PC7_RCNTR 0x000003FA

8271

8272 typedef union {

8273 ///

8274 /// Individual bit fields

8275 ///

8276 struct {

8277 UINT32 Data0 : 32;

8278

8279 /* Bits[31:0], Access Type=RW, default=0x00000000*/

8280

8281 /* Counter Value */

8282 UINT32 Data1 : 28;

8283

8284 /* Bits[59:32], Access Type=RW, default=0x00000000*/

8285

8286 /* Counter Value */

8287 UINT32 Rsvd60 : 4;

8288

8289 /* Bits[63:60], Access Type=RO, default=None*/

8290

8291 /* Reserved */

8292

8293 } Bits;

8294

8295 UINT32 Uint32;

8296 UINT64 Uint64;

8297

8298 } MSR_PC7_RCNTR_REGISTER;

8299

8300 /**

8301 Time spent in the Core C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

8302 **/

8303 #define MSR_CC3_RCNTR 0x000003FC

8304

8305 typedef union {

8306 ///

8307 /// Individual bit fields

8308 ///

8309 struct {

8310 UINT32 Data0 : 32;

8311

8312 /* Bits[31:0], Access Type=RW, default=None*/

8313

8314 /* Data */

8315 UINT32 Data1 : 28;

8316

8317 /* Bits[59:32], Access Type=RW, default=None*/

8318

8319 /* Data */

8320 UINT32 Rsvd60 : 4;

8321

8322 /* Bits[63:60], Access Type=RO, default=None*/

8323

8324 /* Reserved */

8325

8326 } Bits;

8327

8328 UINT32 Uint32;

8329 UINT64 Uint64;

8330

8331 } MSR_CC3_RCNTR_REGISTER;

8332 /**

8333 Time spent in the Core C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency). CNL NEW: Moved from uncore to core

8334 **/

8335 #define MSR_CORE_C6_RESIDENCY_COUNTER 0x000003FD

8336

8337 /**

8338 Time spent in the Core C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

8339 **/

8340 #define MSR_CC7_RCNTR 0x000003FE

8341

8342 typedef union {

8343 ///

8344 /// Individual bit fields

8345 ///

8346 struct {

8347 UINT32 Data0 : 32;

8348

8349 /* Bits[31:0], Access Type=RW, default=0x00000000*/

8350

8351 /* Counter Value */

8352 UINT32 Data1 : 28;

8353

8354 /* Bits[59:32], Access Type=RW, default=0x00000000*/

8355

8356 /* Counter Value */

8357 UINT32 Rsvd60 : 4;

8358

8359 /* Bits[63:60], Access Type=RO, default=None*/

8360

8361 /* Reserved */

8362

8363 } Bits;

8364

8365 UINT32 Uint32;

8366 UINT64 Uint64;

8367

8368 } MSR_CC7_RCNTR_REGISTER;

8369

8370 /**

8371 The MCiCTL MSR controls the signalling of machine check exceptions generated by the bank.

8372 **/

8373 #define MSR_IMC0_MC_CTL 0x00000464

8374

8375 typedef union {

8376 ///

8377 /// Individual bit fields

8378 ///

8379 struct {

8380 UINT32 DataSpareErr : 1;

8381

8382 /* Bits[0:0], Access Type=RW, default=0x00000000*/

8383

8384 /*

8385 enable exception signaling for data sparing

8386 errors.

8387 */

8388 UINT32 DataScrubErr : 1;

8389

8390 /* Bits[1:1], Access Type=RW, default=0x00000000*/

8391

8392 /*

8393 enable exception signaling for data scrubbing

8394 errors.

8395 */

8396 UINT32 DataWrtErr : 1;

8397

8398 /* Bits[2:2], Access Type=RW, default=0x00000000*/

8399

8400 /* enable exception signaling for data write errors */

8401 UINT32 DataByteEnableErr : 1;

8402

8403 /* Bits[3:3], Access Type=RW, default=0x00000000*/

8404

8405 /*

8406 enable exception signaling for data byte enable

8407 errors

8408 */

8409 UINT32 AddrErr : 1;

8410

8411 /* Bits[4:4], Access Type=RW, default=0x00000000*/

8412

8413 /* enable exception signaling for address errors */

8414 UINT32 CorrRdErr : 1;

8415

8416 /* Bits[5:5], Access Type=RW, default=0x00000000*/

8417

8418 /*

8419 Enables exception signalling for normal read

8420 errors.

8421 */

8422 UINT32 WdbParErr : 1;

8423

8424 /* Bits[6:6], Access Type=RW, default=0x00000000*/

8425

8426 /* enable exception signaling for WDB parity err */

8427 UINT32 ApppParErr : 1;

8428

8429 /* Bits[7:7], Access Type=RW, default=0x00000000*/

8430

8431 /*

8432 enable exception signaling for address path

8433 parity protection err

8434 */

8435 UINT32 Mc2lmInvalReqErr : 1;

8436

8437 /* Bits[8:8], Access Type=RW, default=0x00000000*/

8438

8439 /*

8440 enable exception signaling for unrecognized

8441 request to 2LM controller

8442 */

8443 UINT32 Mc2lmDatToInvalEntErr : 1;

8444

8445 /* Bits[9:9], Access Type=RW, default=0x00000000*/

8446

8447 /*

8448 enable exception signaling for read response to

8449 an invalid 2LM scoreboard entry

8450 */

8451 UINT32 Mc2lmUnexpectedReadrspErr : 1;

8452

8453 /* Bits[10:10], Access Type=RW, default=0x00000000*/

8454

8455 /*

8456 enable exception signaling for unexpected 2LM

8457 read response

8458 */

8459 UINT32 Mc2lmDdr4CmpErr : 1;

8460

8461 /* Bits[11:11], Access Type=RW, default=0x00000000*/

8462

8463 /*

8464 enable exception signaling for DDR4 completion

8465 to an invalid 2LM scoreboard entry

8466 */

8467 UINT32 Mc2lmDdrtCmpErr : 1;

8468

8469 /* Bits[12:12], Access Type=RW, default=0x00000000*/

8470

8471 /*

8472 enable exception signaling for DDRt completion

8473 to an invalid 2LM scoreboard entry

8474 */

8475 UINT32 Mc2lmFifoOvflwErr : 1;

8476

8477 /* Bits[13:13], Access Type=RW, default=0x00000000*/

8478

8479 /*

8480 enable exception signaling for 2LM data or

8481 completion FIFO overflow

8482 */

8483 UINT32 VdbParErr : 1;

8484

8485 /* Bits[14:14], Access Type=RW, default=0x00000000*/

8486

8487 /*

8488 enable exception signaling for DDRT WDB parity

8489 err

8490 */

8491 UINT32 RpaParErr : 1;

8492

8493 /* Bits[15:15], Access Type=RW, default=0x00000000*/

8494

8495 /* enable exception signaling for RPA parity err */

8496 UINT32 WpaParErr : 1;

8497

8498 /* Bits[16:16], Access Type=RW, default=0x00000000*/

8499

8500 /* enable exception signaling for WPA parity err */

8501 UINT32 DdrtEridUc : 1;

8502

8503 /* Bits[17:17], Access Type=RW, default=0x00000000*/

8504

8505 /* Enable exception signalling for ERID UC Error */

8506 UINT32 DdrtIntrOverflow : 1;

8507

8508 /* Bits[18:18], Access Type=RW, default=0x00000000*/

8509

8510 /*

8511 Enable exception signalling for interrupt seen

8512 from FNV

8513 */

8514 UINT32 DdrtEridFifoOverflow : 1;

8515

8516 /* Bits[19:19], Access Type=RW, default=0x00000000*/

8517

8518 /*

8519 Enable exception signalling for for ERID FIFO

8520 overflow error

8521 */

8522 UINT32 DdrtFnvWrCreditError : 1;

8523

8524 /* Bits[20:20], Access Type=RW, default=0x00000000*/

8525

8526 /*

8527 Enable exception signalling for FNV Write credit

8528 error

8529 */

8530 UINT32 DdrtFnvRdCreditError : 1;

8531

8532 /* Bits[21:21], Access Type=RW, default=0x00000000*/

8533

8534 /*

8535 Enable exception signalling for FNV Read credi

8536 error

8537 */

8538 UINT32 DdrtSchedError : 1;

8539

8540 /* Bits[22:22], Access Type=RW, default=0x00000000*/

8541

8542 /*

8543 Enable exception signalling for DDRT scheduler

8544 error

8545 */

8546 UINT32 DdrtEridPar : 1;

8547

8548 /* Bits[23:23], Access Type=RW, default=0x00000000*/

8549

8550 /*

8551 Enable exception signalling for DDRT scheduler

8552 error

8553 */

8554 UINT32 LinkFail : 1;

8555

8556 /* Bits[24:24], Access Type=RW, default=0x00000000*/

8557

8558 /*

8559 Enable exception signalling for DDRT scheduler

8560 error

8561 */

8562 UINT32 DdrtFnvThermal : 1;

8563

8564 /* Bits[25:25], Access Type=RW, default=0x00000000*/

8565

8566 /*

8567 Enable exception signalling for FNV Thermal

8568 event error

8569 */

8570 UINT32 Rsvd26 : 6;

8571

8572 /* Bits[31:26], Access Type=RO, default=None*/

8573

8574 /* Reserved */

8575 UINT32 Rsvd32 : 32;

8576

8577 /* Bits[63:32], Access Type=RO, default=None*/

8578

8579 /* Reserved */

8580

8581 } Bits;

8582

8583 UINT32 Uint32;

8584 UINT64 Uint64;

8585

8586 } MSR_IMC0_MC_CTL_REGISTER;

8587

8588 /**

8589 The MCiSTATUS MSR contains information related to a machine check error if its VAL (valid) flag is set.

8590 **/

8591 #define MSR_IMC0_MC_STATUS 0x00000465

8592

8593 typedef union {

8594 ///

8595 /// Individual bit fields

8596 ///

8597 struct {

8598 UINT32 Mcacod : 16;

8599

8600 /* Bits[15:0], Access Type=RWS_V, default=0x00000000*/

8601

8602 /*

8603 Specifies the machine check architecture defined

8604 error code for the machine check error condition

8605 detected

8606 */

8607 UINT32 Mscod : 16;

8608

8609 /* Bits[31:16], Access Type=RWS_V, default=0x00000000*/

8610

8611 /*

8612 Specifies a model specific error code that

8613 uniquely identifies the machine check error

8614 condition that has been detected

8615 */

8616 UINT32 OtherInfo : 6;

8617

8618 /* Bits[37:32], Access Type=RWS_V, default=0x00000000*/

8619

8620 /*

8621 The functions of the bits in this field are

8622 implementation specific and are not part of the

8623 machine check architecture.

8624 */

8625 UINT32 CorErrCnt : 15;

8626

8627 /* Bits[52:38], Access Type=RWS_V, default=0x00000000*/

8628

8629 /*

8630 A 15 bit counter that is incremented each time a

8631 corrected (or uncorrected but ignorable) error

8632 is observed by the MCA recording bank

8633 */

8634 UINT32 CorErrStat : 2;

8635

8636 /* Bits[54:53], Access Type=RWS, default=0x00000000*/

8637

8638 /*

8639 These bits are used to indicate when the number

8640 of corrected errors has exceeded the safe

8641 threshold to the point where an uncorrected

8642 error has become more likely to happen

8643 CORR_ERR_STAT does not apply to IMC and is

8644 marked as reserved attribute

8645 */

8646 UINT32 Ar : 1;

8647

8648 /* Bits[55:55], Access Type=RWS_V, default=0x00000000*/

8649

8650 /*

8651 AR - Action REquired. When set it indicates that

8652 SW needs to take immediate recovery action for

8653 the error. When clear, SW does not need to take

8654 immediate action. Similar to the S bit, the AR

8655 bit has meaning only when an error is logged

8656 with UC=1 and PCC=0.

8657 */

8658 UINT32 S : 1;

8659

8660 /* Bits[56:56], Access Type=RWS_V, default=0x00000000*/

8661

8662 /*

8663 S - Signaling. When set it indicates that the

8664 error was signaled with an MCERR. When clear it

8665 indicates that the error was signaled via a

8666 CMCI. The S bit has meaning only when an error

8667 is logged with UC=1 and PCC=0.

8668 */

8669 UINT32 Pcc : 1;

8670

8671 /* Bits[57:57], Access Type=RWS_V, default=0x00000000*/

8672

8673 /*

8674 Indicates (when set) that the state of the

8675 processor might have been corrupted by the error

8676 condition detected and that reliable restarting

8677 of the processor may not be possible

8678 */

8679 UINT32 Addrv : 1;

8680

8681 /* Bits[58:58], Access Type=RWS_V, default=0x00000000*/

8682

8683 /*

8684 indicates (when set) that the MCiADDR register

8685 contains the address where the error occurred

8686 */

8687 UINT32 Miscv : 1;

8688

8689 /* Bits[59:59], Access Type=RWS_V, default=0x00000000*/

8690

8691 /*

8692 Indicates (when set) that the MCiMISC register

8693 contains additional information regarding the

8694 error.

8695 */

8696 UINT32 En : 1;

8697

8698 /* Bits[60:60], Access Type=RWS_V, default=0x00000000*/

8699

8700 /*

8701 Indicates (when set) that signaling of the

8702 machine check exception for this error was

8703 enabled by an associated flag bit of the MCiCTL

8704 register

8705 */

8706 UINT32 Uc : 1;

8707

8708 /* Bits[61:61], Access Type=RWS_V, default=0x00000000*/

8709

8710 /*

8711 Error logged in this banks is an uncorrected

8712 error.

8713 */

8714 UINT32 Over : 1;

8715

8716 /* Bits[62:62], Access Type=RWS_V, default=0x00000000*/

8717

8718 /*

8719 (Overflow) Indicates (when set) that a machine

8720 check error occurred while the results of a

8721 previous error were still in the register bank

8722 */

8723 UINT32 Valid : 1;

8724

8725 /* Bits[63:63], Access Type=RWS_V, default=0x00000000*/

8726

8727 /* Error logged in this bank is valid */

8728

8729 } Bits;

8730

8731 UINT32 Uint32;

8732 UINT64 Uint64;

8733

8734 } MSR_IMC0_MC_STATUS_REGISTER;

8735

8736 /**

8737 The MCiADDR MSR contains the address of the code or data memory location that produced the machine check error if the ADDRV flag in the MCiSTATUS register is set.

8738 **/

8739 #define MSR_IMC1_MC9_ADDR 0x0000046A

8740

8741 typedef union {

8742 ///

8743 /// Individual bit fields

8744 ///

8745 struct {

8746 UINT32 Address0 : 32;

8747

8748 /* Bits[31:0], Access Type=RWS_V, default=0x00000000*/

8749

8750 /* Address associated with the error. */

8751 UINT32 Address1 : 14;

8752

8753 /* Bits[45:32], Access Type=RWS_V, default=0x00000000*/

8754

8755 /* Address associated with the error. */

8756 UINT32 UnimplementedUpperAddress : 18;

8757

8758 /* Bits[63:46], Access Type=RWS, default=0x00000000*/

8759

8760 /*

8761 These bits are not implemented in that they will

8762 never by set to one due to a detected error.

8763 They can be written and read for software

8764 testing.

8765 */

8766

8767 } Bits;

8768

8769 UINT32 Uint32;

8770 UINT64 Uint64;

8771

8772 } MSR_IMC1_MC9_ADDR_REGISTER;

8773

8774 /**

8775 The MCiADDR MSR contains the address of the code or data memory location that produced the machine check error if the ADDRV flag in the MCiSTATUS register is set.

8776 **/

8777 #define MSR_IMC2_MCA_ADDR 0x0000046E

8778

8779 typedef union {

8780 ///

8781 /// Individual bit fields

8782 ///

8783 struct {

8784 UINT32 Address0 : 32;

8785

8786 /* Bits[31:0], Access Type=RWS_V, default=0x00000000*/

8787

8788 /* Address associated with the error. */

8789 UINT32 Address1 : 14;

8790

8791 /* Bits[45:32], Access Type=RWS_V, default=0x00000000*/

8792

8793 /* Address associated with the error. */

8794 UINT32 UnimplementedUpperAddress : 18;

8795

8796 /* Bits[63:46], Access Type=RWS, default=0x00000000*/

8797

8798 /*

8799 These bits are not implemented in that they will

8800 never by set to one due to a detected error.

8801 They can be written and read for software

8802 testing.

8803 */

8804

8805 } Bits;

8806

8807 UINT32 Uint32;

8808 UINT64 Uint64;

8809

8810 } MSR_IMC2_MCA_ADDR_REGISTER;

8811

8812 /**

8813 SW opt-in for none-broadcast behavior

8814 **/

8815 #define MSR_MCG_EXE_CTL 0x000004D0

8816

8817 typedef union {

8818 ///

8819 /// Individual bit fields

8820 ///

8821 struct {

8822 UINT32 Lmce : 1;

8823

8824 /* Bits[0:0], Access Type=RW, default=None*/

8825

8826 /* Local MCE SW opt-in */

8827 UINT32 Lmsmi : 1;

8828

8829 /* Bits[1:1], Access Type=RW, default=None*/

8830

8831 /* Local MSMI SW opt-in */

8832 UINT32 Rsvd2 : 30;

8833

8834 /* Bits[31:2], Access Type=RW, default=None*/

8835

8836 /* */

8837

8838 } Bits;

8839

8840 UINT32 Uint32;

8841 UINT64 Uint64;

8842

8843 } MSR_MCG_EXE_CTL_REGISTER;

8844

8845 /**

8846 This CSR holds enable bits for on-chip storage of SMM and

8847 Code Access Check Violation features.

8848 **/

8849 #define MSR_SMM_FEATURE_CONTROL 0x000004E0

8850

8851 typedef union {

8852 ///

8853 /// Individual bit fields

8854 ///

8855 struct {

8856 UINT32 Lock : 1;

8857

8858 /* Bits[0:0], Access Type=RW, default=0x00000000*/

8859

8860 /*

8861 If Lock = 1, CPU will drop writes to the

8862 register If Lock = 0, CPU will allow update to

8863 b[2:0]

8864 */

8865 UINT32 SmmCpuSaveEn : 1;

8866

8867 /* Bits[1:1], Access Type=RW, default=0x00000000*/

8868

8869 /*

8870 If 0, SMI/RSM will save/restore state in SMRAM

8871 If 1, SMI/RSM will save/restore state from SRAM

8872 */

8873 UINT32 SmmCodeChkEn : 1;

8874

8875 /* Bits[2:2], Access Type=RW, default=0x00000000*/

8876

8877 /*

8878 If 1, generate unrecoverable MCHK on code fetch

8879 outside SMRRs If 0, do not report any errors for

8880 code fetch outside SMRRs

8881 */

8882 UINT32 Rsvd3 : 29;

8883

8884 /* Bits[31:3], Access Type=RO, default=None*/

8885

8886 /* Reserved */

8887

8888 } Bits;

8889

8890 UINT32 Uint32;

8891 UINT64 Uint64;

8892

8893 } MSR_SMM_FEATURE_CONTROL_REGISTER;

8894

8895 /**

8896 Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's)

8897 that should be servicing a Targeted SMI. BIOS programs the MASK register to indicate which bits should

8898 be masked before doing a MATCH check

8899 **/

8900 #define MSR_SMM_ENABLE_MATCH 0x000004E8

8901

8902 typedef union {

8903 ///

8904 /// Individual bit fields

8905 ///

8906 struct {

8907 UINT32 ThreadIdMatch : 12;

8908

8909 /* Bits[11:0], Access Type=RW, default=0x00000000*/

8910

8911 /*

8912 Each bit in this field corresponds to a logical

8913 thread-id bit. When set, ucode masks the

8914 corresponding thread-id bit before checking for

8915 a match against the MATCH register during

8916 targeted SMIs

8917 */

8918 UINT32 Reserved12 : 20;

8919

8920 /* Bits[31:12], Access Type=RO, default=0x00000000*/

8921

8922 /* Reserved for future */

8923 UINT32 Rsvd32 : 32;

8924

8925 /* Bits[63:32], Access Type=RO, default=None*/

8926

8927 /* Reserved */

8928

8929 } Bits;

8930

8931 UINT32 Uint32;

8932 UINT64 Uint64;

8933

8934 } MSR_SMM_ENABLE_MATCH_REGISTER;

8935

8936 /**

8937 Description: This SMM_ENABLE_MASK and MATCH registers are used to select threads (Logical thread Id's)

8938 that should be servicing a Targeted SMI. BIOS programs the MASK register to indicate which bits should

8939 be masked before doing a MATCH check

8940 **/

8941 #define MSR_SMM_ENABLE_MASK 0x000004EA

8942

8943 typedef union {

8944 ///

8945 /// Individual bit fields

8946 ///

8947 struct {

8948 UINT32 ThreadIdMask : 12;

8949

8950 /* Bits[11:0], Access Type=RW, default=0x00000FFF*/

8951

8952 /*

8953 Each bit in this field corresponds to a logical

8954 thread-id bit. When set, ucode masks the

8955 corresponding thread-id bit before checking for

8956 a match against the MATCH register during

8957 targeted SMIs

8958 */

8959 UINT32 Reserved12 : 20;

8960

8961 /* Bits[31:12], Access Type=RO, default=0x00000000*/

8962

8963 /* Reserved for future */

8964 UINT32 Rsvd32 : 32;

8965

8966 /* Bits[63:32], Access Type=RO, default=None*/

8967

8968 /* Reserved */

8969

8970 } Bits;

8971

8972 UINT32 Uint32;

8973 UINT64 Uint64;

8974

8975 } MSR_SMM_ENABLE_MASK_REGISTER;

8976

8977 /**

8978 SGX SVN Status MSR

8979 **/

8980 #define MSR_IA32_SE_SVN 0x00000500

8981

8982 typedef union {

8983 ///

8984 /// Individual bit fields

8985 ///

8986 struct {

8987 UINT32 Lock : 1;

8988

8989 /* Bits[0:0], Access Type=RO_V, default=None*/

8990

8991 /* */

8992 UINT32 Reserved1 : 15;

8993

8994 /* Bits[15:1], Access Type=RO_V, default=None*/

8995

8996 /* */

8997 UINT32 SinitSeSvn : 8;

8998

8999 /* Bits[23:16], Access Type=RO_V, default=None*/

9000

9001 /* */

9002 UINT32 Reserved24 : 8;

9003

9004 /* Bits[31:24], Access Type=RO_V, default=None*/

9005

9006 /* */

9007 UINT32 Reserved32 : 32;

9008

9009 /* Bits[63:32], Access Type=RO_V, default=None*/

9010

9011 /* */

9012

9013 } Bits;

9014

9015 UINT32 Uint32;

9016 UINT64 Uint64;

9017

9018 } MSR_IA32_SE_SVN_REGISTER;

9019

9020 /**

9021 SGX_DEBUG_MODE MSR to allow non-Intel debugger to enter debug mode equal to DEBUG_UNLOCK_MODE functionality

9022 **/

9023 #define MSR_SGX_DEBUG_MODE 0x00000503

9024

9025 typedef union {

9026 ///

9027 /// Individual bit fields

9028 ///

9029 struct {

9030 UINT32 NpkRequest : 1;

9031

9032 /* Bits[0:0], Access Type=RW, default=None*/

9033

9034 /* Trace Hub request */

9035 UINT32 DebugUnlockMode : 1;

9036

9037 /* Bits[1:1], Access Type=RW, default=None*/

9038

9039 /*

9040 Indication whether the system is under debug via

9041 Intel Trace Hub

9042 */

9043 UINT32 Rsvd2 : 30;

9044

9045 /* Bits[31:2], Access Type=RO, default=None*/

9046

9047 /* Reserved */

9048

9049 } Bits;

9050

9051 UINT32 Uint32;

9052 UINT64 Uint64;

9053

9054 } MSR_SGX_DEBUG_MODE_REGISTER;

9055 /**

9056 Scratch Pad register PROBE_MODE_4

9057 C6NoSave Candidate

9058 **/

9059 #define MSR_PROBE_MODE_VMEXIT_REDIRECTION_REASON 0x00000504

9060 /**

9061 VMX Redirection info used for Probe Mode

9062 **/

9063 #define MSR_PROBE_MODE_VMX_REDIRECTION_INFO 0x00000505

9064 /**

9065 Not really a register. Probe mode MSR used to flush all TLBs.

9066 **/

9067 #define MSR_PROBE_TLB_FLUSH 0x00000508

9068 /**

9069 Not really a register. Probe mode MSR used to read/write VMX pointers.

9070 **/

9071 #define MSR_PROBE_VMX_POINTER 0x00000509

9072 /**

9073 emulated by xucode --> cause pppe exit, described in SNC HSD 1304428988 - HCTIO/SoftCE: uArch support for TIO_DEBUG_STATUS MSRs

9074 **/

9075 #define MSR_TIO_PM_DEBUG_STATUS 0x0000050A

9076

9077 /**

9078 Programmed in Probe mode, used in PDM.

9079 Need to save in C6

9080 **/

9081 #define MSR_AET_MISC_ENABLE 0x00000511

9082

9083 typedef union {

9084 ///

9085 /// Individual bit fields

9086 ///

9087 struct {

9088 UINT32 HwInt : 1;

9089

9090 /* Bits[0:0], Access Type=RW, default=None*/

9091

9092 /* HW Interrupt trace enable */

9093 UINT32 Iret : 1;

9094

9095 /* Bits[1:1], Access Type=RW, default=None*/

9096

9097 /* IRET trace enable */

9098 UINT32 Exception : 1;

9099

9100 /* Bits[2:2], Access Type=RW, default=None*/

9101

9102 /* Exception trace enable */

9103 UINT32 Msr : 1;

9104

9105 /* Bits[3:3], Access Type=RW, default=None*/

9106

9107 /* MSR trace enable */

9108 UINT32 PowerEvent : 1;

9109

9110 /* Bits[4:4], Access Type=RW, default=None*/

9111

9112 /* Reserved */

9113 UINT32 Io : 1;

9114

9115 /* Bits[5:5], Access Type=RW, default=None*/

9116

9117 /* IO trace enable */

9118 UINT32 Se : 1;

9119

9120 /* Bits[6:6], Access Type=RW, default=None*/

9121

9122 /* Secure Enclaves entry and exit trace enable */

9123 UINT32 Wbinvd : 1;

9124

9125 /* Bits[7:7], Access Type=RW, default=None*/

9126

9127 /* WBINVD trace enable */

9128 UINT32 Rsvd8 : 1;

9129

9130 /* Bits[8:8], Access Type=RW, default=None*/

9131

9132 /* Reserved */

9133 UINT32 CodeBreakpoint : 1;

9134

9135 /* Bits[9:9], Access Type=RW, default=None*/

9136

9137 /* Code breakpoint trace enable */

9138 UINT32 DataBreakpoint : 1;

9139

9140 /* Bits[10:10], Access Type=RW, default=None*/

9141

9142 /* Data breakpoint trace enable */

9143 UINT32 Rsvd11 : 1;

9144

9145 /* Bits[11:11], Access Type=RW, default=None*/

9146

9147 /* Reserved */

9148 UINT32 Btm : 1;

9149

9150 /* Bits[12:12], Access Type=RW, default=None*/

9151

9152 /* BTM trace enable */

9153 UINT32 Smi : 1;

9154

9155 /* Bits[13:13], Access Type=RW, default=None*/

9156

9157 /* SMI trace enable */

9158 UINT32 Mwait : 1;

9159

9160 /* Bits[14:14], Access Type=RW, default=None*/

9161

9162 /* Monitor/Mwait trace enable */

9163 UINT32 Rsvd15 : 13;

9164

9165 /* Bits[27:15], Access Type=RW, default=None*/

9166

9167 /* Reserved */

9168 UINT32 LipDisable : 1;

9169

9170 /* Bits[28:28], Access Type=RW, default=None*/

9171

9172 /* disable LIP for the pdm packet. */

9173 UINT32 RicDisable : 1;

9174

9175 /* Bits[29:29], Access Type=RW, default=None*/

9176

9177 /* disnable RIC for the pdm packet. */

9178 UINT32 Rsvd30 : 1;

9179

9180 /* Bits[30:30], Access Type=RW, default=None*/

9181

9182 /* Reserved */

9183 UINT32 Rsvd31 : 1;

9184

9185 /* Bits[31:31], Access Type=RW, default=None*/

9186

9187 /* Reserved */

9188

9189 } Bits;

9190

9191 UINT32 Uint32;

9192 UINT64 Uint64;

9193

9194 } MSR_AET_MISC_ENABLE_REGISTER;

9195

9196 /**

9197 AET (PDM) Event Control Register

9198 **/

9199 #define MSR_AET_EVENT_CTRL 0x00000512

9200

9201 typedef union {

9202 ///

9203 /// Individual bit fields

9204 ///

9205 struct {

9206 UINT32 HwInt : 1;

9207

9208 /* Bits[0:0], Access Type=RW, default=None*/

9209

9210 /* HW Interrupt trace enable */

9211 UINT32 Iret : 1;

9212

9213 /* Bits[1:1], Access Type=RW, default=None*/

9214

9215 /* IRET trace enable */

9216 UINT32 Exception : 1;

9217

9218 /* Bits[2:2], Access Type=RW, default=None*/

9219

9220 /* Exception trace enable */

9221 UINT32 Msr : 1;

9222

9223 /* Bits[3:3], Access Type=RW, default=None*/

9224

9225 /* MSR trace enable */

9226 UINT32 PowerEvent : 1;

9227

9228 /* Bits[4:4], Access Type=RW, default=None*/

9229

9230 /* Reserved */

9231 UINT32 Io : 1;

9232

9233 /* Bits[5:5], Access Type=RW, default=None*/

9234

9235 /* IO trace enable */

9236 UINT32 Se : 1;

9237

9238 /* Bits[6:6], Access Type=RW, default=None*/

9239

9240 /* Secure Enclaves entry and exit trace enable */

9241 UINT32 Wbinvd : 1;

9242

9243 /* Bits[7:7], Access Type=RW, default=None*/

9244

9245 /* WBINVD trace enable */

9246 UINT32 Rsvd8 : 1;

9247

9248 /* Bits[8:8], Access Type=RW, default=None*/

9249

9250 /* Reserved */

9251 UINT32 CodeBreakpoint : 1;

9252

9253 /* Bits[9:9], Access Type=RW, default=None*/

9254

9255 /* Code breakpoint trace enable */

9256 UINT32 DataBreakpoint : 1;

9257

9258 /* Bits[10:10], Access Type=RW, default=None*/

9259

9260 /* Data breakpoint trace enable */

9261 UINT32 Rsvd11 : 1;

9262

9263 /* Bits[11:11], Access Type=RW, default=None*/

9264

9265 /* Reserved */

9266 UINT32 Btm : 1;

9267

9268 /* Bits[12:12], Access Type=RW, default=None*/

9269

9270 /* BTM trace enable */

9271 UINT32 Smi : 1;

9272

9273 /* Bits[13:13], Access Type=RW, default=None*/

9274

9275 /* SMI trace enable */

9276 UINT32 Mwait : 1;

9277

9278 /* Bits[14:14], Access Type=RW, default=None*/

9279

9280 /* Monitor/Mwait trace enable */

9281 UINT32 Rsvd15 : 15;

9282

9283 /* Bits[29:15], Access Type=RW, default=None*/

9284

9285 /* Reserved */

9286 UINT32 Npk : 1;

9287

9288 /* Bits[30:30], Access Type=RW, default=None*/

9289

9290 /* NPK output enable */

9291 UINT32 PdmMasterEnable : 1;

9292

9293 /* Bits[31:31], Access Type=RW, default=None*/

9294

9295 /* Mater enable for PDM. */

9296

9297 } Bits;

9298

9299 UINT32 Uint32;

9300 UINT64 Uint64;

9301

9302 } MSR_AET_EVENT_CTRL_REGISTER;

9303 /**

9304 PPPE Redirection info used for Probe Mode

9305 **/

9306 #define MSR_PROBE_MODE_PPPE_REDIRECTION_INFO 0x00000513

9307 /**

9308 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9309 " seq has 12 instances in addresses range 0x514 to 0x51F"

9310 **/

9311 #define MSR_PROBE_MODE_RESERVED_1_1 0x00000514

9312 /**

9313 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9314 " seq has 12 instances in addresses range 0x514 to 0x51F"

9315 **/

9316 #define MSR_PROBE_MODE_RESERVED_2_2 0x00000515

9317 /**

9318 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9319 " seq has 12 instances in addresses range 0x514 to 0x51F"

9320 **/

9321 #define MSR_PROBE_MODE_RESERVED_3_3 0x00000516

9322 /**

9323 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9324 " seq has 12 instances in addresses range 0x514 to 0x51F"

9325 **/

9326 #define MSR_PROBE_MODE_RESERVED_4_4 0x00000517

9327 /**

9328 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9329 " seq has 12 instances in addresses range 0x514 to 0x51F"

9330 **/

9331 #define MSR_PROBE_MODE_RESERVED_5_5 0x00000518

9332 /**

9333 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9334 " seq has 12 instances in addresses range 0x514 to 0x51F"

9335 **/

9336 #define MSR_PROBE_MODE_RESERVED_6_6 0x00000519

9337 /**

9338 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9339 " seq has 12 instances in addresses range 0x514 to 0x51F"

9340 **/

9341 #define MSR_PROBE_MODE_RESERVED_7_7 0x0000051A

9342 /**

9343 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9344 " seq has 12 instances in addresses range 0x514 to 0x51F"

9345 **/

9346 #define MSR_PROBE_MODE_RESERVED_8_8 0x0000051B

9347 /**

9348 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9349 " seq has 12 instances in addresses range 0x514 to 0x51F"

9350 **/

9351 #define MSR_PROBE_MODE_RESERVED_9_9 0x0000051C

9352 /**

9353 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9354 " seq has 12 instances in addresses range 0x514 to 0x51F"

9355 **/

9356 #define MSR_PROBE_MODE_RESERVED_10_10 0x0000051D

9357 /**

9358 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9359 " seq has 12 instances in addresses range 0x514 to 0x51F"

9360 **/

9361 #define MSR_PROBE_MODE_RESERVED_11_11 0x0000051E

9362 /**

9363 This define is used to reserve some MSR addresses for probe mode. Ucode would have a dedicated handler for these MSRs

9364 " seq has 12 instances in addresses range 0x514 to 0x51F"

9365 **/

9366 #define MSR_PROBE_MODE_RESERVED_12_12 0x0000051F

9367 /**

9368 Scratch Pad register ICECTLPMR_PRIOR_STATE

9369 Used only by probe mode.

9370 C6NoSave candidate

9371 **/

9372 #define MSR_ICECTLPMR_PRIOR_STATE 0x00000520

9373

9374 /**

9375 AET base address. programmed by probe mode software. cmoshe

9376 Ucode will use it as the address where it will send all PDM messages.

9377 **/

9378 #define MSR_AET_BASE_ADDRESS 0x00000521

9379

9380 typedef union {

9381 ///

9382 /// Individual bit fields

9383 ///

9384 struct {

9385 UINT32 Valid : 1;

9386

9387 /* Bits[0:0], Access Type=RW, default=None*/

9388

9389 /*

9390 Valid. Ucode will write PDMs only if valid is

9391 set

9392 */

9393 UINT32 Rsvd1 : 5;

9394

9395 /* Bits[5:1], Access Type=RW, default=None*/

9396

9397 /* Reserved */

9398 UINT32 Address0 : 26;

9399

9400 /* Bits[31:6], Access Type=RW, default=None*/

9401

9402 /* Base address for AET */

9403 UINT32 Address1 : 32;

9404

9405 /* Bits[63:32], Access Type=RW, default=None*/

9406

9407 /* Base address for AET */

9408

9409 } Bits;

9410

9411 UINT32 Uint32;

9412 UINT64 Uint64;

9413

9414 } MSR_AET_BASE_ADDRESS_REGISTER;

9415

9416 /**

9417 Core UARCH_CTL msr

9418 **/

9419 #define MSR_CORE_UARCH_CTL 0x00000541

9420

9421 typedef union {

9422 ///

9423 /// Individual bit fields

9424 ///

9425 struct {

9426 UINT32 DcuScrubEn : 1;

9427

9428 /* Bits[0:0], Access Type=RW, default=None*/

9429

9430 /* L1 scrubbing enable */

9431 UINT32 Rsvd1 : 31;

9432

9433 /* Bits[31:1], Access Type=RO, default=None*/

9434

9435 /* Reserved */

9436 UINT32 Rsvd32 : 32;

9437

9438 /* Bits[63:32], Access Type=RO, default=None*/

9439

9440 /* Reserved */

9441

9442 } Bits;

9443

9444 UINT32 Uint32;

9445 UINT64 Uint64;

9446

9447 } MSR_CORE_UARCH_CTL_REGISTER;

9448

9449 /**

9450 PL4 limit. It is Icc limit on some power-delivery board element, mapped into W. It is proactive, instantaneous limit.

9451 **/

9452 #define MSR_VR_CURRENT_CONFIG 0x00000601

9453

9454 typedef union {

9455 ///

9456 /// Individual bit fields

9457 ///

9458 struct {

9459 UINT32 CurrentLimit : 13;

9460

9461 /* Bits[12:0], Access Type=RO_V, default=0x00000000*/

9462

9463 /*

9464 Current limitation in 0.125 A increments. This

9465 field is locked by VR_CURRENT_CONFIG[LOCK]. When

9466 the LOCK bit is set to 1b, this field becomes

9467 Read Only.

9468 */

9469 UINT32 Rsvd13 : 18;

9470

9471 /* Bits[30:13], Access Type=RO, default=None*/

9472

9473 /* Reserved */

9474 UINT32 Lock : 1;

9475

9476 /* Bits[31:31], Access Type=ROS_V, default=0x00000000*/

9477

9478 /*

9479 This bit will lock the CURRENT_LIMIT settings in

9480 this register and will also lock this setting.

9481 This means that once set to 1b, the

9482 CURRENT_LIMIT setting and this bit become Read

9483 Only until the next Warm Reset.

9484 */

9485 UINT32 Psi1Threshold : 10;

9486

9487 /* Bits[41:32], Access Type=RO_V, default=0x00000000*/

9488

9489 /* Not in use */

9490 UINT32 Psi2Threshold : 10;

9491

9492 /* Bits[51:42], Access Type=RO_V, default=0x00000000*/

9493

9494 /* Not in use */

9495 UINT32 Psi3Threshold : 10;

9496

9497 /* Bits[61:52], Access Type=RO_V, default=0x00000000*/

9498

9499 /* Not in use */

9500 UINT32 Ps4Enable : 1;

9501

9502 /* Bits[62:62], Access Type=RO_V, default=0x00000000*/

9503

9504 /* Not in use */

9505 UINT32 Reserved63 : 1;

9506

9507 /* Bits[63:63], Access Type=RO_V, default=0x00000000*/

9508

9509 /* Reserved */

9510

9511 } Bits;

9512

9513 UINT32 Uint32;

9514 UINT64 Uint64;

9515

9516 } MSR_VR_CURRENT_CONFIG_REGISTER;

9517

9518 /**

9519 Defines units for calculating SKU power and timing parameters.

9520 **/

9521 #define MSR_PACKAGE_POWER_SKU_UNIT 0x00000606

9522

9523 typedef union {

9524 ///

9525 /// Individual bit fields

9526 ///

9527 struct {

9528 UINT32 PwrUnit : 4;

9529

9530 /* Bits[3:0], Access Type=RO_V, default=0x00000003*/

9531

9532 /*

9533 Power Units used for power control registers.

9534 The actual unit value is calculated by 1 W /

9535 Power(2,PWR_UNIT). The default value of 0011b

9536 corresponds to 1/8 W.

9537 */

9538 UINT32 Rsvd4 : 4;

9539

9540 /* Bits[7:4], Access Type=RO, default=None*/

9541

9542 /* Reserved */

9543 UINT32 EnergyUnit : 5;

9544

9545 /* Bits[12:8], Access Type=RO_V, default=0x0000000E*/

9546

9547 /*

9548 Energy Units used for power control registers.

9549 The actual unit value is calculated by 1 J /

9550 Power(2,ENERGY_UNIT). The default value of 14

9551 corresponds to Ux.14 number.

9552 */

9553 UINT32 Rsvd13 : 3;

9554

9555 /* Bits[15:13], Access Type=RO, default=None*/

9556

9557 /* Reserved */

9558 UINT32 TimeUnit : 4;

9559

9560 /* Bits[19:16], Access Type=RO_V, default=0x0000000A*/

9561

9562 /*

9563 Time Units used for power control registers. The

9564 actual unit value is calculated by 1 s /

9565 Power(2,TIME_UNIT). The default value of Ah

9566 corresponds to 976 usec.

9567 */

9568 UINT32 Rsvd20 : 12;

9569

9570 /* Bits[31:20], Access Type=RO, default=None*/

9571

9572 /* Reserved */

9573

9574 } Bits;

9575

9576 UINT32 Uint32;

9577 UINT64 Uint64;

9578

9579 } MSR_PACKAGE_POWER_SKU_UNIT_REGISTER;

9580

9581 /**

9582 Control and Status register for the BIOS-to-PCODE mailbox. This mailbox is implemented as a means for accessing statistics and implementing PCODE patches.

9583 This register is used in conjunction with BIOS_MAILBOX_DATA.

9584 **/

9585 #define MSR_BIOS_MAILBOX_INTERFACE 0x00000607

9586

9587 typedef union {

9588 ///

9589 /// Individual bit fields

9590 ///

9591 struct {

9592 UINT32 Command : 8;

9593

9594 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

9595

9596 /*

9597 This field contains the SW request command or

9598 the PCODE response code, depending on the

9599 setting of RUN_BUSY.

9600 */

9601 UINT32 Addr : 21;

9602

9603 /* Bits[28:8], Access Type=RW_V, default=0x00000000*/

9604

9605 /*

9606 This field contains the address associated with

9607 specific commands.

9608 */

9609 UINT32 Rsvd29 : 2;

9610

9611 /* Bits[30:29], Access Type=RO, default=None*/

9612

9613 /* Reserved */

9614 UINT32 RunBusy : 1;

9615

9616 /* Bits[31:31], Access Type=RW1S, default=0x00000000*/

9617

9618 /*

9619 SW may write to the two mailbox registers only

9620 when RUN_BUSY is cleared (0b). Setting RUN_BUSY

9621 to 1b will create a Fast Path event. After

9622 setting this bit, SW will poll this bit until it

9623 is cleared. PCODE will clear RUN_BUSY after

9624 updating the mailbox registers with the result

9625 and error code.

9626 */

9627

9628 } Bits;

9629

9630 UINT32 Uint32;

9631 UINT64 Uint64;

9632

9633 } MSR_BIOS_MAILBOX_INTERFACE_REGISTER;

9634 /**

9635 Data register for the BIOS-to-PCODE mailbox. This mailbox is implemented as a means for accessing statistics and implementing PCODE patches.

9636 This register is used in conjunction with BIOS_MAILBOX_INTERFACE.

9637 **/

9638 #define MSR_BIOS_MAILBOX_DATA 0x00000608

9639

9640 /**

9641 This MSR reads/writes THREAD_P_REQ[P_STATE_OFFSET]. HSW ECO 4400429

9642 **/

9643 #define MSR_PST_CONFIG_CONTROL 0x00000609

9644

9645 typedef union {

9646 ///

9647 /// Individual bit fields

9648 ///

9649 struct {

9650 UINT32 PStateOffset : 8;

9651

9652 /* Bits[7:0], Access Type=RW, default=None*/

9653

9654 /* P-state offset of Thread-P-Req */

9655 UINT32 Rsvd8 : 24;

9656

9657 /* Bits[31:8], Access Type=RO, default=None*/

9658

9659 /* Reserved */

9660 UINT32 Rsvd32 : 32;

9661

9662 /* Bits[63:32], Access Type=RO, default=None*/

9663

9664 /* Reserved */

9665

9666 } Bits;

9667

9668 UINT32 Uint32;

9669 UINT64 Uint64;

9670

9671 } MSR_PST_CONFIG_CONTROL_REGISTER;

9672

9673 /**

9674 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

9675 **/

9676 #define MSR_C_STATE_LATENCY_CONTROL_0 0x0000060A

9677

9678 typedef union {

9679 ///

9680 /// Individual bit fields

9681 ///

9682 struct {

9683 UINT32 Value : 10;

9684

9685 /* Bits[9:0], Access Type=RW, default=0x00000000*/

9686

9687 /*

9688 The Interrupt Response Time Limit is given in

9689 units defined in the Multipler field of this

9690 register.

9691 */

9692 UINT32 Multiplier : 3;

9693

9694 /* Bits[12:10], Access Type=RW, default=0x00000000*/

9695

9696 /*

9697 This field indicates the unit of measurement

9698 that is defined for the Value field in this

9699 register.

9700 */

9701 UINT32 Rsvd13 : 2;

9702

9703 /* Bits[14:13], Access Type=RO, default=None*/

9704

9705 /* Reserved */

9706 UINT32 Valid : 1;

9707

9708 /* Bits[15:15], Access Type=RW, default=0x00000000*/

9709

9710 /*

9711 This field qualifies the validity of the Value

9712 field in this register.

9713 */

9714 UINT32 Rsvd16 : 16;

9715

9716 /* Bits[31:16], Access Type=RO, default=None*/

9717

9718 /* Reserved */

9719

9720 } Bits;

9721

9722 UINT32 Uint32;

9723 UINT64 Uint64;

9724

9725 } MSR_C_STATE_LATENCY_CONTROL_0_REGISTER;

9726

9727 /**

9728 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

9729 **/

9730 #define MSR_C_STATE_LATENCY_CONTROL_1 0x0000060B

9731

9732 typedef union {

9733 ///

9734 /// Individual bit fields

9735 ///

9736 struct {

9737 UINT32 Value : 10;

9738

9739 /* Bits[9:0], Access Type=RW, default=0x00000000*/

9740

9741 /*

9742 The Interrupt Response Time Limit is given in

9743 units defined in the Multipler field of this

9744 register.

9745 */

9746 UINT32 Multiplier : 3;

9747

9748 /* Bits[12:10], Access Type=RW, default=0x00000000*/

9749

9750 /*

9751 This field indicates the unit of measurement

9752 that is defined for the Value field in this

9753 register.

9754 */

9755 UINT32 Rsvd13 : 2;

9756

9757 /* Bits[14:13], Access Type=RO, default=None*/

9758

9759 /* Reserved */

9760 UINT32 Valid : 1;

9761

9762 /* Bits[15:15], Access Type=RW, default=0x00000000*/

9763

9764 /*

9765 This field qualifies the validity of the Value

9766 field in this register.

9767 */

9768 UINT32 Rsvd16 : 16;

9769

9770 /* Bits[31:16], Access Type=RO, default=None*/

9771

9772 /* Reserved */

9773

9774 } Bits;

9775

9776 UINT32 Uint32;

9777 UINT64 Uint64;

9778

9779 } MSR_C_STATE_LATENCY_CONTROL_1_REGISTER;

9780

9781 /**

9782 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

9783 **/

9784 #define MSR_C_STATE_LATENCY_CONTROL_2 0x0000060C

9785

9786 typedef union {

9787 ///

9788 /// Individual bit fields

9789 ///

9790 struct {

9791 UINT32 Value : 10;

9792

9793 /* Bits[9:0], Access Type=RW, default=0x00000000*/

9794

9795 /*

9796 The Interrupt Response Time Limit is given in

9797 units defined in the Multipler field of this

9798 register.

9799 */

9800 UINT32 Multiplier : 3;

9801

9802 /* Bits[12:10], Access Type=RW, default=0x00000000*/

9803

9804 /*

9805 This field indicates the unit of measurement

9806 that is defined for the Value field in this

9807 register.

9808 */

9809 UINT32 Rsvd13 : 2;

9810

9811 /* Bits[14:13], Access Type=RO, default=None*/

9812

9813 /* Reserved */

9814 UINT32 Valid : 1;

9815

9816 /* Bits[15:15], Access Type=RW, default=0x00000000*/

9817

9818 /*

9819 This field qualifies the validity of the Value

9820 field in this register.

9821 */

9822 UINT32 Rsvd16 : 16;

9823

9824 /* Bits[31:16], Access Type=RO, default=None*/

9825

9826 /* Reserved */

9827

9828 } Bits;

9829

9830 UINT32 Uint32;

9831 UINT64 Uint64;

9832

9833 } MSR_C_STATE_LATENCY_CONTROL_2_REGISTER;

9834

9835 /**

9836 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

9837 **/

9838 #define MSR_PC2_RCNTR 0x0000060D

9839

9840 typedef union {

9841 ///

9842 /// Individual bit fields

9843 ///

9844 struct {

9845 UINT32 Data0 : 32;

9846

9847 /* Bits[31:0], Access Type=RW, default=0x00000000*/

9848

9849 /* Counter Value */

9850 UINT32 Data1 : 28;

9851

9852 /* Bits[59:32], Access Type=RW, default=0x00000000*/

9853

9854 /* Counter Value */

9855 UINT32 Rsvd60 : 4;

9856

9857 /* Bits[63:60], Access Type=RO, default=None*/

9858

9859 /* Reserved */

9860

9861 } Bits;

9862

9863 UINT32 Uint32;

9864 UINT64 Uint64;

9865

9866 } MSR_PC2_RCNTR_REGISTER;

9867

9868 /**

9869 This register allows platform BIOS to limit the power consumption of the processor to the specified values.

9870 **/

9871 #define MSR_PACKAGE_RAPL_LIMIT 0x00000610

9872

9873 typedef union {

9874 ///

9875 /// Individual bit fields

9876 ///

9877 struct {

9878 UINT32 PkgPwrLim1 : 15;

9879

9880 /* Bits[14:0], Access Type=RW_L, default=0x00000118*/

9881

9882 /*

9883 Average Power limit value which the package must

9884 not exceed over a time window as specified by

9885 Power_Limit_1_TIME field above. The processor

9886 power consumption will be controlled to the

9887 Power_Limit_1 value over an exponential weighted

9888 moving average of the time window. This field is

9889 specified in the units as identified by the

9890 PACKAGE_POWER_SKU_UNIT (MSR 606h). Initial value

9891 varies based on the SKU.

9892 */

9893 UINT32 PkgPwrLim1En : 1;

9894

9895 /* Bits[15:15], Access Type=RO, default=0x00000001*/

9896

9897 /*

9898 When set, enables processor to apply control

9899 policies such that the package average power

9900 does not exceed Power_Limit_1 value over an

9901 exponential weighted moving average of the time

9902 window. This bit is always enabled indicating

9903 Power_Limit_1 is always active. Because the

9904 processor must maintain the power consumption to

9905 the TDP value, Power_Limit_1 is always enabled.

9906 */

9907 UINT32 PkgClmpLim1 : 1;

9908

9909 /* Bits[16:16], Access Type=RW_L, default=0x00000000*/

9910

9911 /*

9912 When set, allows processor to go below the OS

9913 requested P States in order to maintain the

9914 power below Power_Limit_1 value specified below.

9915 This bit is writable only when

9916 CPUID.(EAX=06h):EAX[4] is set.

9917 */

9918 UINT32 PkgPwrLim1Time : 7;

9919

9920 /* Bits[23:17], Access Type=RW_L, default=0x0000000A*/

9921

9922 /*

9923 This indicates the time window over which

9924 Power_Limit_1 value should be maintained. This

9925 field is made up of two numbers from the

9926 following equation. The processor power

9927 consumption will be controlled to the

9928 Power_Limit_1 value over an exponential weighted

9929 moving average of the time window. Time Window =

9930 (float) ((1+(X/4)) * (2 ^ Y)) Where: X =

9931 POWER_LIMIT_1_TIME[23:22] Y =

9932 POWER_LIMIT_1_TIME[21:17] The unit of

9933 measurement for this field is available from

9934 PACKAGE_POWER_SKU_UNIT (MSR 606h). The maximum

9935 allowed value in this field is defined in

9936 PACKAGE_POWER_SKU (MSR 614h) PACKAGE_MAX_TIME

9937 field.

9938 */

9939 UINT32 Rsvd24 : 8;

9940

9941 /* Bits[31:24], Access Type=RO, default=None*/

9942

9943 /* Reserved */

9944 UINT32 PkgPwrLim2 : 15;

9945

9946 /* Bits[46:32], Access Type=RW_L, default=0x00000000*/

9947

9948 /*

9949 This field indicates the power limitation #2.

9950 The unit of measurement is defined in

9951 PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].

9952 */

9953 UINT32 PkgPwrLim2En : 1;

9954

9955 /* Bits[47:47], Access Type=RW_L, default=0x00000000*/

9956

9957 /*

9958 This bit enables/disables PKG_PWR_LIM_2. 0b

9959 Package Power Limit 2 is Disabled 1b Package

9960 Power Limit 2 is Enabled

9961 */

9962 UINT32 PkgClmpLim2 : 1;

9963

9964 /* Bits[48:48], Access Type=RW_L, default=0x00000000*/

9965

9966 /*

9967 When set, allows processor to go below the OS

9968 requested P States in order to maintain the

9969 power below Power_Limit_2 value specified below.

9970 This bit is writable only when

9971 CPUID.(EAX=6):EAX[4] is set.

9972 */

9973 UINT32 PkgPwrLim2Time : 7;

9974

9975 /* Bits[55:49], Access Type=RW_L, default=0x00000000*/

9976

9977 /*

9978 This indicates the short duration time window

9979 over which Power_Limit_2 value should be

9980 maintained. This field is made up of two numbers

9981 from the following equation. The processor power

9982 consumption will be controlled to the

9983 Power_Limit_2 value over an exponential weighted

9984 moving average of the time window. Time Window =

9985 (float) ((1+(X/4)) * (2 ^ Y)) Where: X =

9986 POWER_LIMIT_2_TIME[55:54] Y =

9987 POWER_LIMIT_2_TIME[53:49] The unit of

9988 measurement for this field is available from

9989 PACKAGE_POWER_SKU_UNIT (MSR 606h).

9990 */

9991 UINT32 Rsvd56 : 7;

9992

9993 /* Bits[62:56], Access Type=RO, default=None*/

9994

9995 /* Reserved */

9996 UINT32 PkgPwrLimLock : 1;

9997

9998 /* Bits[63:63], Access Type=RW_KL, default=0x00000000*/

9999

10000 /*

10001 When set, all settings in this register are

10002 locked and are treated as Read Only. This bit

10003 will typically set by BIOS during boot time or

10004 resume from Sx.

10005 */

10006

10007 } Bits;

10008

10009 UINT32 Uint32;

10010 UINT64 Uint64;

10011

10012 } MSR_PACKAGE_RAPL_LIMIT_REGISTER;

10013 /**

10014 Package energy consumed by the entire CPU (including IA, GT and uncore). The counter will wrap around and continue counting when it reaches its limit.

10015 The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].

10016 **/

10017 #define MSR_PACKAGE_ENERGY_STATUS 0x00000611

10018 /**

10019 Package RAPL Performance Status Register. This register provides information on the performance impact of the RAPL power limit and indicates the duration for processor went below the requested P-state due to package power constraint.

10020 **/

10021 #define MSR_PACKAGE_RAPL_PERF_STATUS 0x00000613

10022

10023 /**

10024 Defines allowed SKU power and timing parameters.

10025 PCODE will update the contents of this register.

10026 **/

10027 #define MSR_PACKAGE_POWER_SKU 0x00000614

10028

10029 typedef union {

10030 ///

10031 /// Individual bit fields

10032 ///

10033 struct {

10034 UINT32 PkgTdp : 15;

10035

10036 /* Bits[14:0], Access Type=RO_V, default=0x00000118*/

10037

10038 /*

10039 The TDP package power setting allowed for this

10040 part. The units for this value are defined in

10041 PACKAGE_POWER_SKU_MSR[PWR_UNIT].

10042 */

10043 UINT32 Rsvd15 : 1;

10044

10045 /* Bits[15:15], Access Type=RO, default=None*/

10046

10047 /* Reserved */

10048 UINT32 PkgMinPwr : 15;

10049

10050 /* Bits[30:16], Access Type=ROS_V, default=0x00000060*/

10051

10052 /*

10053 The minimal package power setting allowed for

10054 this part. Lower values will be clamped to this

10055 value. The minimum setting is typical (not

10056 guaranteed). The units for this value are

10057 defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].

10058 */

10059 UINT32 Rsvd31 : 1;

10060

10061 /* Bits[31:31], Access Type=RO, default=None*/

10062

10063 /* Reserved */

10064 UINT32 PkgMaxPwr : 15;

10065

10066 /* Bits[46:32], Access Type=ROS_V, default=0x00000240*/

10067

10068 /*

10069 The maximal package power setting allowed for

10070 the SKU. Higher values will be clamped to this

10071 value. The maximum setting is typical (not

10072 guaranteed). The units for this value are

10073 defined in PACKAGE_POWER_SKU_MSR[PWR_UNIT].

10074 */

10075 UINT32 Rsvd47 : 1;

10076

10077 /* Bits[47:47], Access Type=RO, default=None*/

10078

10079 /* Reserved */

10080 UINT32 PkgMaxWin : 7;

10081

10082 /* Bits[54:48], Access Type=ROS_V, default=0x00000012*/

10083

10084 /*

10085 The maximal time window allowed for the SKU.

10086 Higher values will be clamped to this value. x =

10087 PKG_MAX_WIN[54:53] y = PKG_MAX_WIN[52:48] The

10088 timing interval window is Floating Point number

10089 given by 1.x * power(2,y). The unit of

10090 measurement is defined in

10091 PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].

10092 */

10093 UINT32 Rsvd55 : 9;

10094

10095 /* Bits[63:55], Access Type=RO, default=None*/

10096

10097 /* Reserved */

10098

10099 } Bits;

10100

10101 UINT32 Uint32;

10102 UINT64 Uint64;

10103

10104 } MSR_PACKAGE_POWER_SKU_REGISTER;

10105

10106 /**

10107 Read/write data from/to pcode through internal mailbox

10108 **/

10109 #define MSR_PL3_CONTROL 0x00000615

10110

10111 typedef union {

10112 ///

10113 /// Individual bit fields

10114 ///

10115 struct {

10116 UINT32 PowerLimit : 15;

10117

10118 /* Bits[14:0], Access Type=RW, default=None*/

10119

10120 /*

10121 PL3 or PAppMax power level. A power reading

10122 above this will be interpreted as a violation

10123 (in increments of 1/8th Watt, U12.3)

10124 */

10125 UINT32 Enable : 1;

10126

10127 /* Bits[15:15], Access Type=RW, default=None*/

10128

10129 /*

10130 0 (default)=>Algorithm Disabled; 1=> Algorithm

10131 Enabled

10132 */

10133 UINT32 Reserved16 : 1;

10134

10135 /* Bits[16:16], Access Type=RW, default=None*/

10136

10137 /* Reserved . #GP if used. */

10138 UINT32 Timewindow : 7;

10139

10140 /* Bits[23:17], Access Type=RW, default=None*/

10141

10142 /*

10143 Duration over which duty cycle control will be

10144 maintained. The time is in the tau

10145 format(xxYYYYY) in milliseconds

10146 */

10147 UINT32 Dutycyle : 7;

10148

10149 /* Bits[30:24], Access Type=RW, default=None*/

10150

10151 /*

10152 Expressed in percentage(U7.0%). Clipped to a max

10153 value of 100%.

10154 */

10155 UINT32 Lock : 1;

10156

10157 /* Bits[31:31], Access Type=RW, default=None*/

10158

10159 /*

10160 0=> Updates to fields allowed; 1=> Interface

10161 locked. Ignore any writes

10162 */

10163

10164 } Bits;

10165

10166 UINT32 Uint32;

10167 UINT64 Uint64;

10168

10169 } MSR_PL3_CONTROL_REGISTER;

10170

10171 /**

10172 Allows software to set power limits for

10173 the DRAM domain and measurement attributes associated with each limit.

10174 **/

10175 #define MSR_DDR_RAPL_LIMIT 0x00000618

10176

10177 typedef union {

10178 ///

10179 /// Individual bit fields

10180 ///

10181 struct {

10182 UINT32 Limit1Power : 15;

10183

10184 /* Bits[14:0], Access Type=RWS_L, default=0x00000000*/

10185

10186 /*

10187 Power Limit[0] for DDR domain. Units=Watts,

10188 Format=11.3, Resolution=0.125W,

10189 Range=0-2047.875W.

10190 */

10191 UINT32 Limit1Enable : 1;

10192

10193 /* Bits[15:15], Access Type=RWS_L, default=0x00000000*/

10194

10195 /* Power Limit[0] enable bit for DDR domain. */

10196 UINT32 Rsvd16 : 1;

10197

10198 /* Bits[16:16], Access Type=RO, default=None*/

10199

10200 /* Reserved */

10201 UINT32 Limit1TimeWindowY : 5;

10202

10203 /* Bits[21:17], Access Type=RWS_L, default=0x00000000*/

10204

10205 /*

10206 Power Limit[0] time window Y value, for DDR

10207 domain. Actual time_window for RAPL is: (1/1024

10208 seconds) * (1+(x/4)) * (2^y)

10209 */

10210 UINT32 Limit1TimeWindowX : 2;

10211

10212 /* Bits[23:22], Access Type=RWS_L, default=0x00000000*/

10213

10214 /*

10215 Power Limit[0] time window X value, for DDR

10216 domain. Actual time_window for RAPL is: (1/1024

10217 seconds) * (1+(x/4)) * (2^y)

10218 */

10219 UINT32 Rsvd24 : 8;

10220

10221 /* Bits[31:24], Access Type=RO, default=None*/

10222

10223 /* Reserved */

10224 UINT32 Limit2Power : 15;

10225

10226 /* Bits[46:32], Access Type=RWS_L, default=0x00000000*/

10227

10228 /*

10229 Power Limit[1] for DDR domain. Units=Watts,

10230 Format=11.3, Resolution=0.125W,

10231 Range=0-2047.875W.

10232 */

10233 UINT32 Limit2Enable : 1;

10234

10235 /* Bits[47:47], Access Type=RWS_L, default=0x00000000*/

10236

10237 /* Power Limit[1] enable bit for DDR domain. */

10238 UINT32 Rsvd48 : 1;

10239

10240 /* Bits[48:48], Access Type=RO, default=None*/

10241

10242 /* Reserved */

10243 UINT32 Limit2TimeWindowY : 5;

10244

10245 /* Bits[53:49], Access Type=RWS_L, default=0x00000000*/

10246

10247 /*

10248 Power Limit[1] time window Y value, for DDR

10249 domain. Actual time_window for RAPL is: (1/1024

10250 seconds) * (1+(x/4)) * (2^y)

10251 */

10252 UINT32 Limit2TimeWindowX : 2;

10253

10254 /* Bits[55:54], Access Type=RWS_L, default=0x00000000*/

10255

10256 /*

10257 Power Limit[1] time window X value, for DDR

10258 domain. Actual time_window for RAPL is: (1/1024

10259 seconds) * (1+(x/4)) * (2^y)

10260 */

10261 UINT32 Rsvd56 : 7;

10262

10263 /* Bits[62:56], Access Type=RO, default=None*/

10264

10265 /* Reserved */

10266 UINT32 Locked : 1;

10267

10268 /* Bits[63:63], Access Type=RWS_KL, default=0x00000000*/

10269

10270 /*

10271 When set, this entire register becomes read-

10272 only. This bit will typically be set by BIOS

10273 during boot.

10274 */

10275

10276 } Bits;

10277

10278 UINT32 Uint32;

10279 UINT64 Uint64;

10280

10281 } MSR_DDR_RAPL_LIMIT_REGISTER;

10282 /**

10283 Accumulates the energy consumed by the DIMMs (summed across all channels).

10284 **/

10285 #define MSR_DDR_ENERGY_STATUS 0x00000619

10286 /**

10287 Memory RAPL performance excursion counter. This register can report the performance impact of power limiting.

10288 **/

10289 #define MSR_DDR_RAPL_PERF_STATUS 0x0000061B

10290

10291 /**

10292

10293 **/

10294 #define MSR_DRAM_POWER_INFO_CFG 0x0000061C

10295

10296 typedef union {

10297 ///

10298 /// Individual bit fields

10299 ///

10300 struct {

10301 UINT32 DramTdp : 15;

10302

10303 /* Bits[14:0], Access Type=RW, default=0x00000118*/

10304

10305 /*

10306 The Spec power allowed for DRAM. The TDP setting

10307 is typical (not guaranteed). The units for this

10308 value are defined in

10309 DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].

10310 */

10311 UINT32 Rsvd15 : 1;

10312

10313 /* Bits[15:15], Access Type=RO, default=None*/

10314

10315 /* Reserved */

10316 UINT32 DramMinPwr : 15;

10317

10318 /* Bits[30:16], Access Type=RW, default=0x00000078*/

10319

10320 /*

10321 The minimal power setting allowed for DRAM.

10322 Lower values will be clamped to this value. The

10323 minimum setting is typical (not guaranteed). The

10324 units for this value are defined in

10325 DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].

10326 */

10327 UINT32 Rsvd31 : 1;

10328

10329 /* Bits[31:31], Access Type=RO, default=None*/

10330

10331 /* Reserved */

10332 UINT32 DramMaxPwr : 15;

10333

10334 /* Bits[46:32], Access Type=RW, default=0x00000258*/

10335

10336 /*

10337 The maximal power setting allowed for DRAM.

10338 Higher values will be clamped to this value. The

10339 maximum setting is typical (not guaranteed). The

10340 units for this value are defined in

10341 DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].

10342 */

10343 UINT32 Rsvd47 : 1;

10344

10345 /* Bits[47:47], Access Type=RO, default=None*/

10346

10347 /* Reserved */

10348 UINT32 DramMaxWin : 7;

10349

10350 /* Bits[54:48], Access Type=RW, default=0x00000028*/

10351

10352 /*

10353 The maximal time window allowed for the DRAM.

10354 Higher values will be clamped to this value. x =

10355 PKG_MAX_WIN[54:53] y = PKG_MAX_WIN[52:48] The

10356 timing interval window is Floating Point number

10357 given by 1.x * power(2,y). The unit of

10358 measurement is defined in

10359 DRAM_POWER_INFO_UNIT_MSR[TIME_UNIT].

10360 */

10361 UINT32 Rsvd55 : 8;

10362

10363 /* Bits[62:55], Access Type=RO, default=None*/

10364

10365 /* Reserved */

10366 UINT32 Lock : 1;

10367

10368 /* Bits[63:63], Access Type=RW, default=0x00000000*/

10369

10370 /* Lock bit to lock the Register */

10371

10372 } Bits;

10373

10374 UINT32 Uint32;

10375 UINT64 Uint64;

10376

10377 } MSR_DRAM_POWER_INFO_CFG_REGISTER;

10378

10379 /**

10380 Time spent with LLC flushed. Count at the same frequency as the TSC

10381 **/

10382 #define MSR_LLC_FLUSHED_RCNTR 0x0000061D

10383

10384 typedef union {

10385 ///

10386 /// Individual bit fields

10387 ///

10388 struct {

10389 UINT32 Data0 : 32;

10390

10391 /* Bits[31:0], Access Type=RW, default=0x00000000*/

10392

10393 /* Counter Value */

10394 UINT32 Data1 : 28;

10395

10396 /* Bits[59:32], Access Type=RW, default=0x00000000*/

10397

10398 /* Counter Value */

10399 UINT32 Rsvd60 : 4;

10400

10401 /* Bits[63:60], Access Type=RO, default=None*/

10402

10403 /* Reserved */

10404

10405 } Bits;

10406

10407 UINT32 Uint32;

10408 UINT64 Uint64;

10409

10410 } MSR_LLC_FLUSHED_RCNTR_REGISTER;

10411

10412 /**

10413 This register provides additional support for BCLK overclocking

10414 **/

10415 #define MSR_LCLK_PLL_RATIO 0x0000061E

10416

10417 typedef union {

10418 ///

10419 /// Individual bit fields

10420 ///

10421 struct {

10422 UINT32 LclkRatio : 2;

10423

10424 /* Bits[1:0], Access Type=RWS, default=0x00000000*/

10425

10426 /*

10427 LCLK Ratio 00 - 100 MHz bclk (5:5 mapping) 01 -

10428 125 MHz bclk (5:4 mapping) 10 - 166 MHz bclk

10429 (5:3 mapping) 11 - 250 MHz bclk (5:2 mapping)

10430 */

10431 UINT32 LcSbSelect : 1;

10432

10433 /* Bits[2:2], Access Type=RWS, default=0x00000000*/

10434

10435 /*

10436 LC vs. SB PLL Selection (0 = LC PLL, 1 = SB

10437 PLL). Default 0x0

10438 */

10439 UINT32 LongReset : 1;

10440

10441 /* Bits[3:3], Access Type=RWS, default=0x00000000*/

10442

10443 /*

10444 If set to 1, wait additional timeout before

10445 relocking Gen2/Gen3/Lclk PLLs

10446 */

10447 UINT32 Rsvd4 : 28;

10448

10449 /* Bits[31:4], Access Type=RO, default=None*/

10450

10451 /* Reserved */

10452 UINT32 Rsvd32 : 32;

10453

10454 /* Bits[63:32], Access Type=RO, default=None*/

10455

10456 /* Reserved */

10457

10458 } Bits;

10459

10460 UINT32 Uint32;

10461 UINT64 Uint64;

10462

10463 } MSR_LCLK_PLL_RATIO_REGISTER;

10464

10465 /**

10466 Min/Max Ratio Limits for Uncore

10467 **/

10468 #define MSR_UNCORE_RATIO_LIMIT 0x00000620

10469

10470 typedef union {

10471 ///

10472 /// Individual bit fields

10473 ///

10474 struct {

10475 UINT32 MaxClrRatio : 7;

10476

10477 /* Bits[6:0], Access Type=RW, default=0x00000000*/

10478

10479 /*

10480 Maximum allowed ratio for the Ring and Last

10481 Level Cache (LLC)

10482 */

10483 UINT32 Rsvd7 : 1;

10484

10485 /* Bits[7:7], Access Type=RO, default=None*/

10486

10487 /* Reserved */

10488 UINT32 MinClrRatio : 7;

10489

10490 /* Bits[14:8], Access Type=RW, default=0x00000000*/

10491

10492 /*

10493 Minimum allowed ratio for the Ring and Last

10494 Level Cache (LLC)

10495 */

10496 UINT32 Rsvd15 : 17;

10497

10498 /* Bits[31:15], Access Type=RO, default=None*/

10499

10500 /* Reserved */

10501

10502 } Bits;

10503

10504 UINT32 Uint32;

10505 UINT64 Uint64;

10506

10507 } MSR_UNCORE_RATIO_LIMIT_REGISTER;

10508

10509 /**

10510 Ring and Last Level Cache Performance Status

10511 **/

10512 #define MSR_UNCORE_PERF_STATUS 0x00000621

10513

10514 typedef union {

10515 ///

10516 /// Individual bit fields

10517 ///

10518 struct {

10519 UINT32 CurrentClrRatio : 7;

10520

10521 /* Bits[6:0], Access Type=RO_V, default=0x00000000*/

10522

10523 /* Current Ring and Last Level Cache Ratio */

10524 UINT32 Rsvd7 : 9;

10525

10526 /* Bits[15:7], Access Type=RO, default=None*/

10527

10528 /* Reserved */

10529 UINT32 LlcRingVoltage : 16;

10530

10531 /* Bits[31:16], Access Type=RO_V, default=0x00000000*/

10532

10533 /*

10534 [p]Indicates the current operating voltage in

10535 3.13 format for Ring and LLC[/p] [p]i.e. current

10536 voltage = float([47:32] / (2^13))[/p]

10537 */

10538

10539 } Bits;

10540

10541 UINT32 Uint32;

10542 UINT64 Uint64;

10543

10544 } MSR_UNCORE_PERF_STATUS_REGISTER;

10545

10546 /**

10547 Gives SW ability to trigger a PMReq through Pcode to put the chipset and other devices

10548 off of the chipset into a low power state.

10549 **/

10550 #define MSR_PCH_EA_CONTROL 0x00000622

10551

10552 typedef union {

10553 ///

10554 /// Individual bit fields

10555 ///

10556 struct {

10557 UINT32 EaValue : 1;

10558

10559 /* Bits[0:0], Access Type=RW, default=0x00000001*/

10560

10561 /*

10562 0x0: Tell PCH that cores are not executing 0x1:

10563 Tell PCH that cores are executing/Disable

10564 Feature

10565 */

10566 UINT32 Rsvd1 : 31;

10567

10568 /* Bits[31:1], Access Type=RO, default=None*/

10569

10570 /* Reserved */

10571

10572 } Bits;

10573

10574 UINT32 Uint32;

10575 UINT64 Uint64;

10576

10577 } MSR_PCH_EA_CONTROL_REGISTER;

10578

10579 /**

10580 Reflect the value of control when PCH has responded to request from PCH_EA_CONTROL.

10581 **/

10582 #define MSR_PCH_EA_STATUS 0x00000623

10583

10584 typedef union {

10585 ///

10586 /// Individual bit fields

10587 ///

10588 struct {

10589 UINT32 EaStatus : 1;

10590

10591 /* Bits[0:0], Access Type=RW_L, default=0x00000001*/

10592

10593 /*

10594 Reflects back the value of control once PCH has

10595 responded to control request.

10596 */

10597 UINT32 Rsvd1 : 31;

10598

10599 /* Bits[31:1], Access Type=RO, default=None*/

10600

10601 /* Reserved */

10602

10603 } Bits;

10604

10605 UINT32 Uint32;

10606 UINT64 Uint64;

10607

10608 } MSR_PCH_EA_STATUS_REGISTER;

10609

10610 /**

10611 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

10612 This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs).

10613 For C2, this value includes any forced or popup time from other states.

10614 For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

10615 **/

10616 #define MSR_PC8_RCNTR 0x00000630

10617

10618 typedef union {

10619 ///

10620 /// Individual bit fields

10621 ///

10622 struct {

10623 UINT32 Data0 : 32;

10624

10625 /* Bits[31:0], Access Type=RW, default=0x00000000*/

10626

10627 /* Counter Value */

10628 UINT32 Data1 : 28;

10629

10630 /* Bits[59:32], Access Type=RW, default=0x00000000*/

10631

10632 /* Counter Value */

10633 UINT32 Rsvd60 : 4;

10634

10635 /* Bits[63:60], Access Type=RO, default=None*/

10636

10637 /* Reserved */

10638

10639 } Bits;

10640

10641 UINT32 Uint32;

10642 UINT64 Uint64;

10643

10644 } MSR_PC8_RCNTR_REGISTER;

10645

10646 /**

10647 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

10648 This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs).

10649 For C2, this value includes any forced or popup time from other states.

10650 For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

10651 **/

10652 #define MSR_PC9_RCNTR 0x00000631

10653

10654 typedef union {

10655 ///

10656 /// Individual bit fields

10657 ///

10658 struct {

10659 UINT32 Data0 : 32;

10660

10661 /* Bits[31:0], Access Type=RW, default=0x00000000*/

10662

10663 /* Counter Value */

10664 UINT32 Data1 : 28;

10665

10666 /* Bits[59:32], Access Type=RW, default=0x00000000*/

10667

10668 /* Counter Value */

10669 UINT32 Rsvd60 : 4;

10670

10671 /* Bits[63:60], Access Type=RO, default=None*/

10672

10673 /* Reserved */

10674

10675 } Bits;

10676

10677 UINT32 Uint32;

10678 UINT64 Uint64;

10679

10680 } MSR_PC9_RCNTR_REGISTER;

10681

10682 /**

10683 Time spent in the Package C-State. It is given in units compatible to P1 clock frequency (Guaranteed / Maximum Core Non-Turbo Frequency).

10684 This time will be updated by PCODE only after the C-State exit (the update of this register has lower priority than actually ensuring that the C-State exit occurs).

10685 For C2, this value includes any forced or popup time from other states.

10686 For C3/C6/C7/C8/C9/C10, this value does not include popup periods, but advances even if VR actions are disabled.

10687 **/

10688 #define MSR_PC10_RCNTR 0x00000632

10689

10690 typedef union {

10691 ///

10692 /// Individual bit fields

10693 ///

10694 struct {

10695 UINT32 Data0 : 32;

10696

10697 /* Bits[31:0], Access Type=RW, default=0x00000000*/

10698

10699 /* Counter Value */

10700 UINT32 Data1 : 28;

10701

10702 /* Bits[59:32], Access Type=RW, default=0x00000000*/

10703

10704 /* Counter Value */

10705 UINT32 Rsvd60 : 4;

10706

10707 /* Bits[63:60], Access Type=RO, default=None*/

10708

10709 /* Reserved */

10710

10711 } Bits;

10712

10713 UINT32 Uint32;

10714 UINT64 Uint64;

10715

10716 } MSR_PC10_RCNTR_REGISTER;

10717

10718 /**

10719 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

10720 **/

10721 #define MSR_C_STATE_LATENCY_CONTROL_3 0x00000633

10722

10723 typedef union {

10724 ///

10725 /// Individual bit fields

10726 ///

10727 struct {

10728 UINT32 Value : 10;

10729

10730 /* Bits[9:0], Access Type=RW, default=0x00000000*/

10731

10732 /*

10733 The Interrupt Response Time Limit is given in

10734 units defined in the Multipler field of this

10735 register.

10736 */

10737 UINT32 Multiplier : 3;

10738

10739 /* Bits[12:10], Access Type=RW, default=0x00000000*/

10740

10741 /*

10742 This field indicates the unit of measurement

10743 that is defined for the Value field in this

10744 register.

10745 */

10746 UINT32 Rsvd13 : 2;

10747

10748 /* Bits[14:13], Access Type=RO, default=None*/

10749

10750 /* Reserved */

10751 UINT32 Valid : 1;

10752

10753 /* Bits[15:15], Access Type=RW, default=0x00000000*/

10754

10755 /*

10756 This field qualifies the validity of the Value

10757 field in this register.

10758 */

10759 UINT32 Rsvd16 : 16;

10760

10761 /* Bits[31:16], Access Type=RO, default=None*/

10762

10763 /* Reserved */

10764

10765 } Bits;

10766

10767 UINT32 Uint32;

10768 UINT64 Uint64;

10769

10770 } MSR_C_STATE_LATENCY_CONTROL_3_REGISTER;

10771

10772 /**

10773 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

10774 **/

10775 #define MSR_C_STATE_LATENCY_CONTROL_4 0x00000634

10776

10777 typedef union {

10778 ///

10779 /// Individual bit fields

10780 ///

10781 struct {

10782 UINT32 Value : 10;

10783

10784 /* Bits[9:0], Access Type=RW, default=0x00000000*/

10785

10786 /*

10787 The Interrupt Response Time Limit is given in

10788 units defined in the Multipler field of this

10789 register.

10790 */

10791 UINT32 Multiplier : 3;

10792

10793 /* Bits[12:10], Access Type=RW, default=0x00000000*/

10794

10795 /*

10796 This field indicates the unit of measurement

10797 that is defined for the Value field in this

10798 register.

10799 */

10800 UINT32 Rsvd13 : 2;

10801

10802 /* Bits[14:13], Access Type=RO, default=None*/

10803

10804 /* Reserved */

10805 UINT32 Valid : 1;

10806

10807 /* Bits[15:15], Access Type=RW, default=0x00000000*/

10808

10809 /*

10810 This field qualifies the validity of the Value

10811 field in this register.

10812 */

10813 UINT32 Rsvd16 : 16;

10814

10815 /* Bits[31:16], Access Type=RO, default=None*/

10816

10817 /* Reserved */

10818

10819 } Bits;

10820

10821 UINT32 Uint32;

10822 UINT64 Uint64;

10823

10824 } MSR_C_STATE_LATENCY_CONTROL_4_REGISTER;

10825

10826 /**

10827 The coordinated Package-Additive (above the core) Interrupt Response Time is used for BIOS runtime control. This setting affects the selected package state.

10828 **/

10829 #define MSR_C_STATE_LATENCY_CONTROL_5 0x00000635

10830

10831 typedef union {

10832 ///

10833 /// Individual bit fields

10834 ///

10835 struct {

10836 UINT32 Value : 10;

10837

10838 /* Bits[9:0], Access Type=RW, default=0x00000000*/

10839

10840 /*

10841 The Interrupt Response Time Limit is given in

10842 units defined in the Multipler field of this

10843 register.

10844 */

10845 UINT32 Multiplier : 3;

10846

10847 /* Bits[12:10], Access Type=RW, default=0x00000000*/

10848

10849 /*

10850 This field indicates the unit of measurement

10851 that is defined for the Value field in this

10852 register.

10853 */

10854 UINT32 Rsvd13 : 2;

10855

10856 /* Bits[14:13], Access Type=RO, default=None*/

10857

10858 /* Reserved */

10859 UINT32 Valid : 1;

10860

10861 /* Bits[15:15], Access Type=RW, default=0x00000000*/

10862

10863 /*

10864 This field qualifies the validity of the Value

10865 field in this register.

10866 */

10867 UINT32 Rsvd16 : 16;

10868

10869 /* Bits[31:16], Access Type=RO, default=None*/

10870

10871 /* Reserved */

10872

10873 } Bits;

10874

10875 UINT32 Uint32;

10876 UINT64 Uint64;

10877

10878 } MSR_C_STATE_LATENCY_CONTROL_5_REGISTER;

10879

10880 /**

10881 Input voltage regulator configuration parameters.

10882 **/

10883 #define MSR_VR_MISC_CONFIG2 0x00000636

10884

10885 typedef union {

10886 ///

10887 /// Individual bit fields

10888 ///

10889 struct {

10890 UINT32 FastRampVoltage : 8;

10891

10892 /* Bits[7:0], Access Type=RW, default=0x00000000*/

10893

10894 /*

10895 This is the maximum voltage that the CPU can

10896 ramp at the fast rate to.

10897 */

10898 UINT32 MinC8Voltage : 8;

10899

10900 /* Bits[15:8], Access Type=RW, default=0x00000000*/

10901

10902 /*

10903 Used to constrain the CPU's minimum voltage

10904 during package C8 C-state. The default setting

10905 of 0x00 will result in full CPU control over the

10906 minimum VID. VID resolution is 10mV / LSB. This

10907 is internally clipped by fuses to the C8 voltage

10908 */

10909 UINT32 Reserved16 : 16;

10910

10911 /* Bits[31:16], Access Type=RW, default=0x00000000*/

10912

10913 /* Reserved */

10914

10915 } Bits;

10916

10917 UINT32 Uint32;

10918 UINT64 Uint64;

10919

10920 } MSR_VR_MISC_CONFIG2_REGISTER;

10921

10922 /**

10923 This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Primary Power Plane.

10924 The overall package turbo power limitation is controlled by PACKAGE_RAPL_LIMIT.

10925 **/

10926 #define MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT 0x00000638

10927

10928 typedef union {

10929 ///

10930 /// Individual bit fields

10931 ///

10932 struct {

10933 UINT32 IaPpPwrLim : 15;

10934

10935 /* Bits[14:0], Access Type=RW_L, default=0x00000000*/

10936

10937 /*

10938 This is the power limitation on the IA cores

10939 power plane. The unit of measurement is defined

10940 in PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].

10941 */

10942 UINT32 PwrLimCtrlEn : 1;

10943

10944 /* Bits[15:15], Access Type=RW_L, default=0x00000000*/

10945

10946 /*

10947 This bit must be set in order to limit the power

10948 of the IA cores power plane. 0b IA cores power

10949 plane power limitation is disabled 1b IA cores

10950 power plane power limitation is enabled

10951 */

10952 UINT32 PpClampLim : 1;

10953

10954 /* Bits[16:16], Access Type=RW_L, default=0x00000000*/

10955

10956 /*

10957 Power Plane Clamping limitation - Allow going

10958 below P1. 0b PBM is limited between P1 and P0.

10959 1b PBM can go below P1.

10960 */

10961 UINT32 CtrlTimeWin : 7;

10962

10963 /* Bits[23:17], Access Type=RW_L, default=0x00000000*/

10964

10965 /*

10966 x = CTRL_TIME_WIN[23:22] y =

10967 CTRL_TIME_WIN[21:17] The timing interval window

10968 is Floating Point number given by 1.x *

10969 power(2,y). The unit of measurement is defined

10970 in PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT]. The

10971 maximal time window is bounded by

10972 PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum

10973 time window is 1 unit of measurement (as defined

10974 above).

10975 */

10976 UINT32 Rsvd24 : 7;

10977

10978 /* Bits[30:24], Access Type=RO, default=None*/

10979

10980 /* Reserved */

10981 UINT32 PpPwrLimLock : 1;

10982

10983 /* Bits[31:31], Access Type=RW_KL, default=0x00000000*/

10984

10985 /*

10986 When set, all settings in this register are

10987 locked and are treated as Read Only.

10988 */

10989

10990 } Bits;

10991

10992 UINT32 Uint32;

10993 UINT64 Uint64;

10994

10995 } MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT_REGISTER;

10996 /**

10997 Reports total energy consumed. The counter will wrap around and continue counting when it reaches its limit.

10998 The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].

10999 SW will read this value and subtract the difference from last value read. The value of this register is updated every 1mSec.

11000 **/

11001 #define MSR_PRIMARY_PLANE_ENERGY_STATUS 0x00000639

11002

11003 /**

11004 The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes.

11005 The power plane with the higher policy will get a higher priority. The default value will aim to maintain same ratio for IA and GT.

11006 **/

11007 #define MSR_PRIMARY_PLANE_TURBO_POWER_POLICY 0x0000063A

11008

11009 typedef union {

11010 ///

11011 /// Individual bit fields

11012 ///

11013 struct {

11014 UINT32 Priptp : 5;

11015

11016 /* Bits[4:0], Access Type=RW, default=0x00000000*/

11017

11018 /*

11019 Priority Level. A higher number implies a higher

11020 priority.

11021 */

11022 UINT32 Rsvd5 : 27;

11023

11024 /* Bits[31:5], Access Type=RO, default=None*/

11025

11026 /* Reserved */

11027

11028 } Bits;

11029

11030 UINT32 Uint32;

11031 UINT64 Uint64;

11032

11033 } MSR_PRIMARY_PLANE_TURBO_POWER_POLICY_REGISTER;

11034 /**

11035 Memory RAPL performance excursion counter. This register can report the performance impact of power limiting.

11036 **/

11037 #define MSR_PRIMARY_PLANE_OVERFLOW_STATUS 0x0000063B

11038

11039 /**

11040 This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the power budget of the Secondary Power Plane.

11041 The overall package turbo power limitation is controlled by PACKAGE_RAPL_LIMIT.

11042 **/

11043 #define MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT 0x00000640

11044

11045 typedef union {

11046 ///

11047 /// Individual bit fields

11048 ///

11049 struct {

11050 UINT32 NonIaPpPwrLim : 15;

11051

11052 /* Bits[14:0], Access Type=RW_L, default=0x00000000*/

11053

11054 /*

11055 This is the power limitation on the Non-IA cores

11056 power plane. The unit of measurement is defined

11057 in PACKAGE_POWER_SKU_UNIT_MSR[PWR_UNIT].

11058 */

11059 UINT32 PwrLimCtrlEn : 1;

11060

11061 /* Bits[15:15], Access Type=RW_L, default=0x00000000*/

11062

11063 /*

11064 This bit must be set in order to limit the power

11065 of the Non-IA cores power plane. 0b Non-IA cores

11066 power plane power limitation is disabled 1b Non-

11067 IA cores power plane power limitation is enabled

11068 */

11069 UINT32 PpClampLim : 1;

11070

11071 /* Bits[16:16], Access Type=RW_L, default=0x00000000*/

11072

11073 /*

11074 Power Plane Clamping limitation - Allow going

11075 below P1. 0b PBM is limited between P1 and P0.

11076 1b PBM can go below P1.

11077 */

11078 UINT32 CtrlTimeWin : 7;

11079

11080 /* Bits[23:17], Access Type=RW_L, default=0x00000000*/

11081

11082 /*

11083 x = CTRL_TIME_WIN[23:22] y =

11084 CTRL_TIME_WIN[21:17] The timing interval window

11085 is Floating Point number given by 1.x *

11086 power(2,y). The unit of measurement is defined

11087 in PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT]. The

11088 maximal time window is bounded by

11089 PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum

11090 time window is 1 unit of measurement (as defined

11091 above).

11092 */

11093 UINT32 Rsvd24 : 7;

11094

11095 /* Bits[30:24], Access Type=RO, default=None*/

11096

11097 /* Reserved */

11098 UINT32 SpPwrLimLock : 1;

11099

11100 /* Bits[31:31], Access Type=RW_KL, default=0x00000000*/

11101

11102 /*

11103 When set, all settings in this register are

11104 locked and are treated as Read Only.

11105 */

11106

11107 } Bits;

11108

11109 UINT32 Uint32;

11110 UINT64 Uint64;

11111

11112 } MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT_REGISTER;

11113 /**

11114 Reports total energy consumed. The counter will wrap around and continue counting when it reaches its limit.

11115 The energy status is reported in units which are defined in PACKAGE_POWER_SKU_UNIT_MSR[ENERGY_UNIT].

11116 SW will read this value and subtract the difference from last value read. The value of this register is updated every 1mSec.

11117 **/

11118 #define MSR_SECONDARY_PLANE_ENERGY_STATUS 0x00000641

11119

11120 /**

11121 The PRIMARY_PLANE_TURBO_POWER_POLICY and SECONDARY_PLANE_TURBO_POWER_POLICY are used together to balance the power budget betwen the two power planes.

11122 The power plane with the higher policy will get a higher priority. The default value will aim to maintain same ratio for IA and GT.

11123 **/

11124 #define MSR_SECONDARY_PLANE_TURBO_POWER_POLICY 0x00000642

11125

11126 typedef union {

11127 ///

11128 /// Individual bit fields

11129 ///

11130 struct {

11131 UINT32 Secptp : 5;

11132

11133 /* Bits[4:0], Access Type=RW, default=0x00000010*/

11134

11135 /*

11136 Priority Level. A higher number implies a higher

11137 priority.

11138 */

11139 UINT32 Rsvd5 : 27;

11140

11141 /* Bits[31:5], Access Type=RO, default=None*/

11142

11143 /* Reserved */

11144

11145 } Bits;

11146

11147 UINT32 Uint32;

11148 UINT64 Uint64;

11149

11150 } MSR_SECONDARY_PLANE_TURBO_POWER_POLICY_REGISTER;

11151

11152 /**

11153 This register is used to indicate the Nominal Configurable TDP ratio available for this

11154 specific sku. System BIOS must use this value while building the _PSS table if the feature is enabled.

11155 **/

11156 #define MSR_CONFIG_TDP_NOMINAL 0x00000648

11157

11158 typedef union {

11159 ///

11160 /// Individual bit fields

11161 ///

11162 struct {

11163 UINT32 TdpRatio : 8;

11164

11165 /* Bits[7:0], Access Type=RO_V, default=0x00000000*/

11166

11167 /*

11168 Nominal TDP level ratio to be used for this

11169 specific processor (in units of 100 MHz). Note:

11170 A value of 0 in this field indicates

11171 invalid/undefined TDP point

11172 */

11173 UINT32 Rsvd8 : 24;

11174

11175 /* Bits[31:8], Access Type=RO, default=None*/

11176

11177 /* Reserved */

11178

11179 } Bits;

11180

11181 UINT32 Uint32;

11182 UINT64 Uint64;

11183

11184 } MSR_CONFIG_TDP_NOMINAL_REGISTER;

11185

11186 /**

11187 Level 1 configurable TDP settings

11188 **/

11189 #define MSR_CONFIG_TDP_LEVEL1 0x00000649

11190

11191 typedef union {

11192 ///

11193 /// Individual bit fields

11194 ///

11195 struct {

11196 UINT32 PkgTdp : 15;

11197

11198 /* Bits[14:0], Access Type=RO_V, default=0x00000000*/

11199

11200 /*

11201 Power for this TDP level. Units defined in

11202 PACKAGE_POWER_SKU_MSR[PWR_UNIT] Similar to

11203 PACKAGE_POWER_SKU[PKG_TDP]

11204 */

11205 UINT32 Rsvd15 : 1;

11206

11207 /* Bits[15:15], Access Type=RO, default=None*/

11208

11209 /* Reserved */

11210 UINT32 TdpRatio : 8;

11211

11212 /* Bits[23:16], Access Type=RO_V, default=0x00000000*/

11213

11214 /* TDP ratio for config tdp level 1. */

11215 UINT32 Rsvd24 : 8;

11216

11217 /* Bits[31:24], Access Type=RO, default=None*/

11218

11219 /* Reserved */

11220 UINT32 PkgMaxPwr : 15;

11221

11222 /* Bits[46:32], Access Type=RO_V, default=0x00000000*/

11223

11224 /*

11225 Max pkg power setting allowed for this config

11226 TDP level1. Higher values will be clamped down

11227 to this value. Units defined in

11228 PACKAGE_POWER_SKU_MSR[PWR_UNIT]. Similar to

11229 PACKAGE_POWER_SKU[PKG_MAX_PWR].

11230 */

11231 UINT32 Rsvd47 : 1;

11232

11233 /* Bits[47:47], Access Type=RO, default=None*/

11234

11235 /* Reserved */

11236 UINT32 PkgMinPwr : 15;

11237

11238 /* Bits[62:48], Access Type=RO_V, default=0x00000000*/

11239

11240 /*

11241 Min pkg power setting allowed for this config

11242 TDP level. Lower values will be clamped up to

11243 this value. Units defined in

11244 PACKAGE_POWER_SKU_MSR[PWR_UNIT]. Similar to

11245 PACKAGE_POWER_SKU[PKG_MIN_PWR].

11246 */

11247 UINT32 Rsvd63 : 1;

11248

11249 /* Bits[63:63], Access Type=RO, default=None*/

11250

11251 /* Reserved */

11252

11253 } Bits;

11254

11255 UINT32 Uint32;

11256 UINT64 Uint64;

11257

11258 } MSR_CONFIG_TDP_LEVEL1_REGISTER;

11259

11260 /**

11261 Level 2 configurable TDP settings

11262 **/

11263 #define MSR_CONFIG_TDP_LEVEL2 0x0000064A

11264

11265 typedef union {

11266 ///

11267 /// Individual bit fields

11268 ///

11269 struct {

11270 UINT32 PkgTdp : 15;

11271

11272 /* Bits[14:0], Access Type=RO_V, default=0x00000000*/

11273

11274 /*

11275 Power for this TDP level. Units defined in

11276 PACKAGE_POWER_SKU_MSR[PWR_UNIT] Similar to

11277 PACKAGE_POWER_SKU[PKG_TDP].

11278 */

11279 UINT32 Rsvd15 : 1;

11280

11281 /* Bits[15:15], Access Type=RO, default=None*/

11282

11283 /* Reserved */

11284 UINT32 TdpRatio : 8;

11285

11286 /* Bits[23:16], Access Type=RO_V, default=0x00000000*/

11287

11288 /* TDP ratio for level 2. */

11289 UINT32 Rsvd24 : 8;

11290

11291 /* Bits[31:24], Access Type=RO, default=None*/

11292

11293 /* Reserved */

11294 UINT32 PkgMaxPwr : 15;

11295

11296 /* Bits[46:32], Access Type=RO_V, default=0x00000000*/

11297

11298 /*

11299 Max pkg power setting allowed for config TDP

11300 level 2. Higher values will be clamped down to

11301 this value. Units defined in

11302 PACKAGE_POWER_SKU_MSR[PWR_UNIT]. Similar to

11303 PACKAGE_POWER_SKU[PKG_MAX_PWR].

11304 */

11305 UINT32 Rsvd47 : 1;

11306

11307 /* Bits[47:47], Access Type=RO, default=None*/

11308

11309 /* Reserved */

11310 UINT32 PkgMinPwr : 15;

11311

11312 /* Bits[62:48], Access Type=RO_V, default=0x00000000*/

11313

11314 /*

11315 Min pkg power setting allowed for this config

11316 TDP level 2. Lower values will be clamped up to

11317 this value. Units defined in

11318 PACKAGE_POWER_SKU_MSR[PWR_UNIT]. Similar to

11319 PACKAGE_POWER_SKU[PKG_MIN_PWR].

11320 */

11321 UINT32 Rsvd63 : 1;

11322

11323 /* Bits[63:63], Access Type=RO, default=None*/

11324

11325 /* Reserved */

11326

11327 } Bits;

11328

11329 UINT32 Uint32;

11330 UINT64 Uint64;

11331

11332 } MSR_CONFIG_TDP_LEVEL2_REGISTER;

11333

11334 /**

11335 Rd/Wr register to allow platform SW to select TDP point and set lock

11336 **/

11337 #define MSR_CONFIG_TDP_CONTROL 0x0000064B

11338

11339 typedef union {

11340 ///

11341 /// Individual bit fields

11342 ///

11343 struct {

11344 UINT32 TdpLevel : 2;

11345

11346 /* Bits[1:0], Access Type=RWS_L, default=0x00000000*/

11347

11348 /*

11349 Config TDP level selected 0 = nominal TDP level

11350 (default) 1 = Level from CONFIG_TDP_LEVEL_1 2 =

11351 Level from CONFIG_TDP_LEVEL_2 3 = reserved

11352 */

11353 UINT32 Rsvd2 : 29;

11354

11355 /* Bits[30:2], Access Type=RO, default=None*/

11356

11357 /* Reserved */

11358 UINT32 ConfigTdpLock : 1;

11359

11360 /* Bits[31:31], Access Type=RWS_KL, default=0x00000000*/

11361

11362 /*

11363 Config TDP level select lock 0 - unlocked. 1 -

11364 locked till next reset.

11365 */

11366

11367 } Bits;

11368

11369 UINT32 Uint32;

11370 UINT64 Uint64;

11371

11372 } MSR_CONFIG_TDP_CONTROL_REGISTER;

11373

11374 /**

11375 indicate the new maximum non-turbo

11376 ratio to be used by the processor. Attempts to write to this MSR when the

11377 PLATFORM_INFO[34:33] ==0, may result in a GP fault#.

11378 **/

11379 #define MSR_TURBO_ACTIVATION_RATIO 0x0000064C

11380

11381 typedef union {

11382 ///

11383 /// Individual bit fields

11384 ///

11385 struct {

11386 UINT32 MaxNonTurboRatio : 8;

11387

11388 /* Bits[7:0], Access Type=RWS_L, default=0x00000000*/

11389

11390 /*

11391 System BIOS can program this field to indicate

11392 the new Max non turbo ratio (in units of 100

11393 MHz). All P state requests above this ratio is

11394 considered as Max Turbo ratio request. Note: A

11395 value of 0 would indicate the feature is

11396 disabled

11397 */

11398 UINT32 Rsvd8 : 23;

11399

11400 /* Bits[30:8], Access Type=RO, default=None*/

11401

11402 /* Reserved */

11403 UINT32 TurboActivationRatioLock : 1;

11404

11405 /* Bits[31:31], Access Type=RWS_KL, default=0x00000000*/

11406

11407 /*

11408 When this bit is set it indicates that the

11409 contents of this register is locked. This bit is

11410 cleared only on a reset.

11411 */

11412

11413 } Bits;

11414

11415 UINT32 Uint32;

11416 UINT64 Uint64;

11417

11418 } MSR_TURBO_ACTIVATION_RATIO_REGISTER;

11419 /**

11420 Reports the actual energy used by the platform

11421 **/

11422 #define MSR_PLATFORM_ENERGY_STATUS 0x0000064D

11423

11424 /**

11425 Interface to allow software to determine what is causing resolved frequency to be clamped

11426 below the requested frequency. Status bits are updated by pcode through the io interface IO_IA_PERF_LIMIT,

11427 log bits are set by hw on a status bit edge dected and cleared by a SW write of '0'.

11428 **/

11429 #define MSR_IA_PERF_LIMIT_REASONS 0x0000064F

11430

11431 typedef union {

11432 ///

11433 /// Individual bit fields

11434 ///

11435 struct {

11436 UINT32 Prochot : 1;

11437

11438 /* Bits[0:0], Access Type=RO, default=0x00000000*/

11439

11440 /*

11441 PROCHOT# Status, RO, When set by PCODE indicates

11442 that PROCHOT# has cause IA frequency clipping

11443 */

11444 UINT32 Thermal : 1;

11445

11446 /* Bits[1:1], Access Type=RO, default=0x00000000*/

11447

11448 /*

11449 Thermal Status, RO, When set by PCODE indicates

11450 that Thermal event has cause IA frequency

11451 clipping

11452 */

11453 UINT32 SpareIa2 : 1;

11454

11455 /* Bits[2:2], Access Type=RO, default=0x00000000*/

11456

11457 /* Reserved */

11458 UINT32 SpareIa3 : 1;

11459

11460 /* Bits[3:3], Access Type=RO, default=0x00000000*/

11461

11462 /* Reserved */

11463 UINT32 RsrLimit : 1;

11464

11465 /* Bits[4:4], Access Type=RO, default=0x00000000*/

11466

11467 /*

11468 Reliability stress Restrictor Status, RO, When

11469 set by PCODE indicates that Reliability stress

11470 restrictor has cause IA frequency clipping

11471 */

11472 UINT32 Ratl : 1;

11473

11474 /* Bits[5:5], Access Type=RO, default=0x00000000*/

11475

11476 /*

11477 Running average thermal limit Status, R0, When

11478 set by PCODE indicates that Running average

11479 thermal limit has cause IA frequency clipping

11480 */

11481 UINT32 VrThermalert : 1;

11482

11483 /* Bits[6:6], Access Type=RO, default=0x00000000*/

11484

11485 /*

11486 Hot VR (any processor VR) Status, RO, When set

11487 by PCODE indicates that Hot VR (any processor

11488 VR) has cause IA frequency clipping

11489 */

11490 UINT32 VrTdc : 1;

11491

11492 /* Bits[7:7], Access Type=RO, default=0x00000000*/

11493

11494 /*

11495 VR TDC (Thermal design current) Status, RO, When

11496 set by PCODE indicates that VR TDC (Thermal

11497 design current has cause IA frequency clipping

11498 */

11499 UINT32 Other : 1;

11500

11501 /* Bits[8:8], Access Type=RO, default=0x00000000*/

11502

11503 /*

11504 Other (IccMax, PL4, etc) Status, RO, When set by

11505 PCODE indicates that other has cause reason IA

11506 frequency clipping

11507 */

11508 UINT32 SpareIa9 : 1;

11509

11510 /* Bits[9:9], Access Type=RO, default=0x00000000*/

11511

11512 /* Reserved */

11513 UINT32 PbmPl1 : 1;

11514

11515 /* Bits[10:10], Access Type=RO, default=0x00000000*/

11516

11517 /*

11518 PBM PL1 (pkg, platform), RO, When set by PCODE

11519 indicates that PBM PL1 (package or platform PL1)

11520 has cause IA frequency clipping

11521 */

11522 UINT32 PbmPl2 : 1;

11523

11524 /* Bits[11:11], Access Type=RO, default=0x00000000*/

11525

11526 /*

11527 PBM PL2, PL3 (pkg, platform) Status, RO, When

11528 set by PCODE indicates that PBM PL2 or

11529 PL3(package or platform PL2 or PL3) has cause IA

11530 frequency clipping

11531 */

11532 UINT32 MaxTurboLimit : 1;

11533

11534 /* Bits[12:12], Access Type=RO, default=0x00000000*/

11535

11536 /*

11537 Max turbo limit Status, RO, When set by PCODE

11538 indicates that Max turbo limit has cause IA

11539 frequency clipping

11540 */

11541 UINT32 TurboAtten : 1;

11542

11543 /* Bits[13:13], Access Type=RO, default=0x00000000*/

11544

11545 /*

11546 Turbo attenuation (multi core turbo) Status, RO,

11547 When set by PCODE indicates that Turbo

11548 attenuation (multi core turbo) has cause IA

11549 frequency clipping

11550 */

11551 UINT32 SpareIa14 : 1;

11552

11553 /* Bits[14:14], Access Type=RO, default=0x00000000*/

11554

11555 /* Reserved */

11556 UINT32 SpareIa15 : 1;

11557

11558 /* Bits[15:15], Access Type=RO, default=0x00000000*/

11559

11560 /* Reserved */

11561 UINT32 ProchotLog : 1;

11562

11563 /* Bits[16:16], Access Type=RW0C_FW, default=0x00000000*/

11564

11565 /*

11566 PROCHOT# Log, RW, When set by PCODE indicates

11567 that PROCHOT# has cause IA frequency clipping.

11568 Software should write to this bit to clear the

11569 status in this bit

11570 */

11571 UINT32 ThermalLog : 1;

11572

11573 /* Bits[17:17], Access Type=RW0C_FW, default=0x00000000*/

11574

11575 /*

11576 Thermal Log, RW, When set by PCODE indicates

11577 that Thermal event has cause IA frequency

11578 clipping. Software should write to this bit to

11579 clear the status in this bit

11580 */

11581 UINT32 SpareIa2Log : 1;

11582

11583 /* Bits[18:18], Access Type=RW0C_FW, default=0x00000000*/

11584

11585 /* Reserved */

11586 UINT32 SpareIa3Log : 1;

11587

11588 /* Bits[19:19], Access Type=RW0C_FW, default=0x00000000*/

11589

11590 /* Reserved */

11591 UINT32 RsrLimitLog : 1;

11592

11593 /* Bits[20:20], Access Type=RW0C_FW, default=0x00000000*/

11594

11595 /*

11596 Reliability stress restrictor Log, RW, When set

11597 by PCODE indicates that Reliability stress

11598 restrictor has cause IA frequency clipping.

11599 Software should write to this bit to clear the

11600 status in this bit

11601 */

11602 UINT32 RatlLog : 1;

11603

11604 /* Bits[21:21], Access Type=RW0C_FW, default=0x00000000*/

11605

11606 /*

11607 Running average thermal limit Log, RW, When set

11608 by PCODE indicates that Running average thermal

11609 limit has cause IA frequency clipping. Software

11610 should write to this bit to clear the status in

11611 this bit

11612 */

11613 UINT32 VrThermalertLog : 1;

11614

11615 /* Bits[22:22], Access Type=RW0C_FW, default=0x00000000*/

11616

11617 /*

11618 Hot VR (any processor VR) Log, RW, When set by

11619 PCODE indicates that Hot VR (any processor VR)

11620 has cause IA frequency clipping. Software should

11621 write to this bit to clear the status in this

11622 bit

11623 */

11624 UINT32 VrTdcLog : 1;

11625

11626 /* Bits[23:23], Access Type=RW0C_FW, default=0x00000000*/

11627

11628 /*

11629 VR TDC (Thermal design current) Log, RW, When

11630 set by PCODE indicates that VR TDC (Thermal

11631 design current has cause IA frequency clipping.

11632 Software should write to this bit to clear the

11633 status in this bit

11634 */

11635 UINT32 OtherLog : 1;

11636

11637 /* Bits[24:24], Access Type=RW0C_FW, default=0x00000000*/

11638

11639 /*

11640 Other (IccMax, PL4, etc) Log, RW, When set by

11641 PCODE indicates that other has cause reason IA

11642 frequency clipping. Software should write to

11643 this bit to clear the status in this bit

11644 */

11645 UINT32 SpareIa9Log : 1;

11646

11647 /* Bits[25:25], Access Type=RW0C_FW, default=0x00000000*/

11648

11649 /* Reserved */

11650 UINT32 PbmPl1Log : 1;

11651

11652 /* Bits[26:26], Access Type=RW0C_FW, default=0x00000000*/

11653

11654 /*

11655 PBM PL1 (pkg, platform) Log, RW, When set by

11656 PCODE indicates that PBM PL1 (package or

11657 platform PL1) has cause IA frequency clipping.

11658 Software should write to this bit to clear the

11659 status in this bit

11660 */

11661 UINT32 PbmPl2Log : 1;

11662

11663 /* Bits[27:27], Access Type=RW0C_FW, default=0x00000000*/

11664

11665 /*

11666 PBM PL2, PL3 (pkg, platform) Log, RW, When set

11667 by PCODE indicates that PBM PL2 or PL3(package

11668 or platform PL2 or PL3) has cause IA frequency

11669 clipping. Software should write to this bit to

11670 clear the status in this bit

11671 */

11672 UINT32 MaxTurboLimitLog : 1;

11673

11674 /* Bits[28:28], Access Type=RW0C_FW, default=0x00000000*/

11675

11676 /*

11677 Max turbo limit Log, RW, When set by PCODE

11678 indicates that Max turbo limit has cause IA

11679 frequency clipping. Software should write to

11680 this bit to clear the status in this bit

11681 */

11682 UINT32 TurboAttenLog : 1;

11683

11684 /* Bits[29:29], Access Type=RW0C_FW, default=0x00000000*/

11685

11686 /*

11687 Turbo attenuation (multi core turbo) Log, RW,

11688 When set by PCODE indicates that Turbo

11689 attenuation (multi core turbo) has cause IA

11690 frequency clipping. Software should write to

11691 this bit to clear the status in this bit

11692 */

11693 UINT32 SpareIa14Log : 1;

11694

11695 /* Bits[30:30], Access Type=RW0C_FW, default=0x00000000*/

11696

11697 /* Reserved */

11698 UINT32 SpareIa15Log : 1;

11699

11700 /* Bits[31:31], Access Type=RW0C_FW, default=0x00000000*/

11701

11702 /* Reserved */

11703

11704 } Bits;

11705

11706 UINT32 Uint32;

11707 UINT64 Uint64;

11708

11709 } MSR_IA_PERF_LIMIT_REASONS_REGISTER;

11710

11711 /**

11712 MSR Name: PKG_HDC_CONFIG_CONTROL,

11713 Enables tune options for the HDC operation.

11714 **/

11715 #define MSR_PKG_SDC_CONFIG_CONTROL 0x00000652

11716

11717 typedef union {

11718 ///

11719 /// Individual bit fields

11720 ///

11721 struct {

11722 UINT32 SdcCxMonitor : 3;

11723

11724 /* Bits[2:0], Access Type=RW, default=0x00000002*/

11725

11726 /*

11727 HDC_CX_MONITOR, Controls the

11728 PKG_HDC_DEEP_RESIDENCY the Cx threshold that >=

11729 counts pkg Cx residency due forced idle Cx

11730 event: 0x0 no-counting, 0x1 PC2R only, 0x2 PC3

11731 and deep, 0x3 PC6 and deep, 0x4 PC7 and deep.

11732 Default=0x0

11733 */

11734 UINT32 SdcMcntCountMethod : 1;

11735

11736 /* Bits[3:3], Access Type=RW, default=0x00000000*/

11737

11738 /*

11739 SDC_MCNT_COUNT_METHOD, Controls if MCNT will

11740 increment or not during HDC forced idle time

11741 (default=0 meaning 'tick')

11742 */

11743 UINT32 SdcRespectOsMin : 1;

11744

11745 /* Bits[4:4], Access Type=RW, default=0x00000000*/

11746

11747 /*

11748 HDC_RESPECT_OS_MIN,HDC Direct control under HWP

11749 Minimal, Direct control, is limited by the ratio

11750 between most efferent frequency to the OS

11751 minimal frequency setting via legacy P state or

11752 HWP interfaces. Set this bit will disable this

11753 control method

11754 */

11755 UINT32 SdcMaxForceIdleDurationTime : 6;

11756

11757 /* Bits[10:5], Access Type=RW, default=0x00000000*/

11758

11759 /*

11760 HDC_MAX_FORCE_IDLE_DURATION_TIME, Limits the HDC

11761 max duration idle time (50usec units). The

11762 default value is 0x0, meaning min HDC duty

11763 cycles idle time default value to be set by

11764 pcode (e.g. 800usec)

11765 */

11766 UINT32 Spare2 : 1;

11767

11768 /* Bits[11:11], Access Type=RW, default=0x00000000*/

11769

11770 /* SPARE2. */

11771 UINT32 SdcDirectControl : 7;

11772

11773 /* Bits[18:12], Access Type=RW, default=0x00000000*/

11774

11775 /*

11776 HDC_DIRECT_CONTRO, overrides the H/W Heuristics

11777 with S/W defined HDC control %. The units are 1/

11778 127 (0x7F=100%). A value of 0x0 means that HDC

11779 is not requested. HDC due to RAPL power

11780 limitation will not be affected by this setting.

11781 */

11782 UINT32 MinActiveTime : 8;

11783

11784 /* Bits[26:19], Access Type=RW, default=0x00000000*/

11785

11786 /*

11787 Limits the forced idle min duration active time

11788 (50usec units) starting 100usec as the lowest

11789 value. The default value is 0x0, means min HDC

11790 duty cycles active time default value to be set

11791 by pcode (e.g. 250usec). Default value is 0x0.

11792 */

11793 UINT32 Spare3 : 5;

11794

11795 /* Bits[31:27], Access Type=RW, default=0x00000000*/

11796

11797 /* SPARE3. */

11798 UINT32 Rsvd32 : 32;

11799

11800 /* Bits[63:32], Access Type=RO, default=None*/

11801

11802 /* Reserved */

11803

11804 } Bits;

11805

11806 UINT32 Uint32;

11807 UINT64 Uint64;

11808

11809 } MSR_PKG_SDC_CONFIG_CONTROL_REGISTER;

11810 /**

11811 Core SDC Residency counter

11812 **/

11813 #define MSR_CORE_SDC_RESIDENCY 0x00000653

11814

11815 /**

11816 Contains software threads information for the current ia_thread.

11817 **/

11818 #define MSR_THREAD_INFO 0x00000654

11819

11820 typedef union {

11821 ///

11822 /// Individual bit fields

11823 ///

11824 struct {

11825 UINT32 ProcessId : 20;

11826

11827 /* Bits[19:0], Access Type=RW, default=0x00000000*/

11828

11829 /*

11830 S/W Process ID (R/W): monitor the process the

11831 current thread belongs to

11832 */

11833 UINT32 ThreadPriority : 4;

11834

11835 /* Bits[23:20], Access Type=RW, default=0x00000000*/

11836

11837 /*

11838 Thread priority: Lowest - 0, priority - 15:

11839 Highest priority

11840 */

11841 UINT32 ThreadProcessType : 8;

11842

11843 /* Bits[31:24], Access Type=RW, default=0x00000000*/

11844

11845 /*

11846 Multi-Threaded: 0x1, Process Uses GFX: 0x2,

11847 Consumer/Producer: 0x3

11848 */

11849 UINT32 SwThreadId : 20;

11850

11851 /* Bits[51:32], Access Type=RW, default=0x00000000*/

11852

11853 /* S/W Thread ID (R/W): monitor the current thread */

11854 UINT32 Spare : 12;

11855

11856 /* Bits[63:52], Access Type=RW, default=0x00000000*/

11857

11858 /* Spare */

11859

11860 } Bits;

11861

11862 UINT32 Uint32;

11863 UINT64 Uint64;

11864

11865 } MSR_THREAD_INFO_REGISTER;

11866 /**

11867 MSR Name: PKG_HDC_SHALLOW_RESIDENCY, PKG shallow CX cycles Residency Counter.

11868 **/

11869 #define MSR_PKG_SDC_SHALLOW_RESIDENCY 0x00000655

11870 /**

11871 MSR Name: PKG_HDC_DEEP_RESIDENCY

11872 PKG Deep CX duty cycles Residency Counter

11873 **/

11874 #define MSR_PKG_SDC_DEEP_RESIDENCY 0x00000656

11875 /**

11876 Sum the cycles per number of active cores

11877 **/

11878 #define MSR_PKG_IA_C0_ANY_SUM 0x00000658

11879 /**

11880 C0.Any - Sum the cycles of any active cores.

11881 **/

11882 #define MSR_PKG_IA_C0_ANY 0x00000659

11883 /**

11884 Sum the cycles of active GT

11885 **/

11886 #define MSR_PKG_GT_C0_ANY 0x0000065A

11887 /**

11888 Sum the cycles of overlap time between any IA cores and GT

11889 **/

11890 #define MSR_PKG_GT_AND_IA_OVERLAP 0x0000065B

11891

11892 /**

11893 Platform power limit

11894 **/

11895 #define MSR_PLATFORM_POWER_LIMIT 0x0000065C

11896

11897 typedef union {

11898 ///

11899 /// Individual bit fields

11900 ///

11901 struct {

11902 UINT32 PowerLimit1 : 15;

11903

11904 /* Bits[14:0], Access Type=RW_L, default=0x00000000*/

11905

11906 /*

11907 Average Power limit value which the Platform

11908 must not exceed over a time window as specified

11909 by Power_Limit_1_TIME field above.

11910 */

11911 UINT32 PowerLimit1En : 1;

11912

11913 /* Bits[15:15], Access Type=RW_L, default=0x00000000*/

11914

11915 /*

11916 When set, enables processor to apply control

11917 policies such that the Platform average power

11918 does not exceed Power_Limit_1 value over an

11919 exponential weighted moving average of the time

11920 window.

11921 */

11922 UINT32 CriticalPowerClamp1 : 1;

11923

11924 /* Bits[16:16], Access Type=RW_L, default=0x00000000*/

11925

11926 /*

11927 When set, allows processor to go below the OS

11928 requested P States in order to maintain the

11929 power below Power_Limit_1 value specified below.

11930 */

11931 UINT32 PowerLimit1Time : 7;

11932

11933 /* Bits[23:17], Access Type=RW_L, default=0x0000000A*/

11934

11935 /*

11936 This indicates the time window over which

11937 Power_Limit_1 value should be maintained.

11938 */

11939 UINT32 Rsvd24 : 8;

11940

11941 /* Bits[31:24], Access Type=RO, default=None*/

11942

11943 /* Reserved */

11944 UINT32 PowerLimit2 : 15;

11945

11946 /* Bits[46:32], Access Type=RW_L, default=0x00000000*/

11947

11948 /*

11949 Duration Power limit value which the Platform

11950 must not exceed. This field is specified in the

11951 units as identified by the

11952 PALTFORM_POWER_SKU_UNIT (MSR606h).

11953 */

11954 UINT32 PowerLimit2En : 1;

11955

11956 /* Bits[47:47], Access Type=RW_L, default=0x00000000*/

11957

11958 /*

11959 When set, enables processor to apply control

11960 policies such that the platform power does not

11961 exceed Power_Limit_2 value.

11962 */

11963 UINT32 CriticalPowerClamp2 : 1;

11964

11965 /* Bits[48:48], Access Type=RW_L, default=0x00000000*/

11966

11967 /*

11968 When set, allows processor to go below the OS

11969 requested P States in order to maintain the

11970 power below Power_Limit_2 value specified below.

11971 */

11972 UINT32 Rsvd49 : 14;

11973

11974 /* Bits[62:49], Access Type=RO, default=None*/

11975

11976 /* Reserved */

11977 UINT32 Lock : 1;

11978

11979 /* Bits[63:63], Access Type=RW_KL, default=0x00000000*/

11980

11981 /* Locks all other fields. */

11982

11983 } Bits;

11984

11985 UINT32 Uint32;

11986 UINT64 Uint64;

11987

11988 } MSR_PLATFORM_POWER_LIMIT_REGISTER;

11989

11990 /**

11991 FAST_UNCORE_MSRS _STATUS, Eanble coplition deliver status report

11992 **/

11993 #define MSR_DISTRIBUTED_STATUS 0x0000065E

11994

11995 typedef union {

11996 ///

11997 /// Individual bit fields

11998 ///

11999 struct {

12000 UINT32 Cr0 : 1;

12001

12002 /* Bits[0:0], Access Type=RO_V, default=0x00000000*/

12003

12004 /*

12005 indicates whether the CPU is in the middle of

12006 distribute the IA32_HWP_REQUEST MSR. 1= the

12007 distribute of the last WRMSR for

12008 IA32_HWP_REQUEST is still ongoing. 0 = the

12009 distribute of the last WRMSR for

12010 IA32_HWP_REQUEST is done or not yet happened

12011 */

12012 UINT32 Cr1 : 1;

12013

12014 /* Bits[1:1], Access Type=RO_V, default=0x00000000*/

12015

12016 /* CR1 Dirty Bit */

12017 UINT32 Cr2 : 1;

12018

12019 /* Bits[2:2], Access Type=RO_V, default=0x00000000*/

12020

12021 /* CR2 Dirty Bit */

12022 UINT32 Cr3 : 1;

12023

12024 /* Bits[3:3], Access Type=RO_V, default=0x00000000*/

12025

12026 /* CR3 Dirty Bit */

12027 UINT32 Rsvd4 : 28;

12028

12029 /* Bits[31:4], Access Type=RO_V, default=0x00000000*/

12030

12031 /* Status CR rsvd Bits */

12032

12033 } Bits;

12034

12035 UINT32 Uint32;

12036 UINT64 Uint64;

12037

12038 } MSR_DISTRIBUTED_STATUS_REGISTER;

12039

12040 /**

12041 Fast wrmsr/rdmsr enumeration MSR. This is read-only MSR. Each bit refers to one MSR and indicate if this MSR is enabled to be use in FAST_UNCORE_MSRS.

12042 **/

12043 #define MSR_FAST_UNCORE_MSRS_CAPABILITY 0x0000065F

12044

12045 typedef union {

12046 ///

12047 /// Individual bit fields

12048 ///

12049 struct {

12050 UINT32 MsrsCapability : 4;

12051

12052 /* Bits[3:0], Access Type=RO_V, default=None*/

12053

12054 /*

12055 Bit 0 - If set (1), HW supports the fast access

12056 mode for IA32_HWP_REQUEST MSR

12057 */

12058 UINT32 Rsvd4 : 28;

12059

12060 /* Bits[31:4], Access Type=RO, default=None*/

12061

12062 /* Reserved */

12063

12064 } Bits;

12065

12066 UINT32 Uint32;

12067 UINT64 Uint64;

12068

12069 } MSR_FAST_UNCORE_MSRS_CAPABILITY_REGISTER;

12070 /**

12071 Core C1 Residency counter

12072 **/

12073 #define MSR_CORE_C1_RESIDENCY 0x00000660

12074

12075 /**

12076 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12077 **/

12078 #define MSR_LBR_FROM_IP_0_0 0x00000680

12079

12080 typedef union {

12081 ///

12082 /// Individual bit fields

12083 ///

12084 struct {

12085 UINT32 Data0 : 32;

12086

12087 /* Bits[31:0], Access Type=RW_V, default=None*/

12088

12089 /* From IP */

12090 UINT32 Data1 : 25;

12091

12092 /* Bits[56:32], Access Type=RW_V, default=None*/

12093

12094 /* From IP */

12095 UINT32 SignExt : 7;

12096

12097 /* Bits[63:57], Access Type=RO_V, default=None*/

12098

12099 /*

12100 sign extension of bit 56 (VAPA fuse-enabled) or

12101 bit 47 (VAPA fuse-disabled)

12102 */

12103

12104 } Bits;

12105

12106 UINT32 Uint32;

12107 UINT64 Uint64;

12108

12109 } MSR_LBR_FROM_IP_0_0_REGISTER;

12110

12111 /**

12112 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12113 **/

12114 #define MSR_LBR_FROM_IP_1_1 0x00000681

12115

12116 typedef union {

12117 ///

12118 /// Individual bit fields

12119 ///

12120 struct {

12121 UINT32 Data0 : 32;

12122

12123 /* Bits[31:0], Access Type=RW_V, default=None*/

12124

12125 /* From IP */

12126 UINT32 Data1 : 25;

12127

12128 /* Bits[56:32], Access Type=RW_V, default=None*/

12129

12130 /* From IP */

12131 UINT32 SignExt : 7;

12132

12133 /* Bits[63:57], Access Type=RO_V, default=None*/

12134

12135 /*

12136 sign extension of bit 56 (VAPA fuse-enabled) or

12137 bit 47 (VAPA fuse-disabled)

12138 */

12139

12140 } Bits;

12141

12142 UINT32 Uint32;

12143 UINT64 Uint64;

12144

12145 } MSR_LBR_FROM_IP_1_1_REGISTER;

12146

12147 /**

12148 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12149 **/

12150 #define MSR_LBR_FROM_IP_2_2 0x00000682

12151

12152 typedef union {

12153 ///

12154 /// Individual bit fields

12155 ///

12156 struct {

12157 UINT32 Data0 : 32;

12158

12159 /* Bits[31:0], Access Type=RW_V, default=None*/

12160

12161 /* From IP */

12162 UINT32 Data1 : 25;

12163

12164 /* Bits[56:32], Access Type=RW_V, default=None*/

12165

12166 /* From IP */

12167 UINT32 SignExt : 7;

12168

12169 /* Bits[63:57], Access Type=RO_V, default=None*/

12170

12171 /*

12172 sign extension of bit 56 (VAPA fuse-enabled) or

12173 bit 47 (VAPA fuse-disabled)

12174 */

12175

12176 } Bits;

12177

12178 UINT32 Uint32;

12179 UINT64 Uint64;

12180

12181 } MSR_LBR_FROM_IP_2_2_REGISTER;

12182

12183 /**

12184 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12185 **/

12186 #define MSR_LBR_FROM_IP_3_3 0x00000683

12187

12188 typedef union {

12189 ///

12190 /// Individual bit fields

12191 ///

12192 struct {

12193 UINT32 Data0 : 32;

12194

12195 /* Bits[31:0], Access Type=RW_V, default=None*/

12196

12197 /* From IP */

12198 UINT32 Data1 : 25;

12199

12200 /* Bits[56:32], Access Type=RW_V, default=None*/

12201

12202 /* From IP */

12203 UINT32 SignExt : 7;

12204

12205 /* Bits[63:57], Access Type=RO_V, default=None*/

12206

12207 /*

12208 sign extension of bit 56 (VAPA fuse-enabled) or

12209 bit 47 (VAPA fuse-disabled)

12210 */

12211

12212 } Bits;

12213

12214 UINT32 Uint32;

12215 UINT64 Uint64;

12216

12217 } MSR_LBR_FROM_IP_3_3_REGISTER;

12218

12219 /**

12220 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12221 **/

12222 #define MSR_LBR_FROM_IP_4_4 0x00000684

12223

12224 typedef union {

12225 ///

12226 /// Individual bit fields

12227 ///

12228 struct {

12229 UINT32 Data0 : 32;

12230

12231 /* Bits[31:0], Access Type=RW_V, default=None*/

12232

12233 /* From IP */

12234 UINT32 Data1 : 25;

12235

12236 /* Bits[56:32], Access Type=RW_V, default=None*/

12237

12238 /* From IP */

12239 UINT32 SignExt : 7;

12240

12241 /* Bits[63:57], Access Type=RO_V, default=None*/

12242

12243 /*

12244 sign extension of bit 56 (VAPA fuse-enabled) or

12245 bit 47 (VAPA fuse-disabled)

12246 */

12247

12248 } Bits;

12249

12250 UINT32 Uint32;

12251 UINT64 Uint64;

12252

12253 } MSR_LBR_FROM_IP_4_4_REGISTER;

12254

12255 /**

12256 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12257 **/

12258 #define MSR_LBR_FROM_IP_5_5 0x00000685

12259

12260 typedef union {

12261 ///

12262 /// Individual bit fields

12263 ///

12264 struct {

12265 UINT32 Data0 : 32;

12266

12267 /* Bits[31:0], Access Type=RW_V, default=None*/

12268

12269 /* From IP */

12270 UINT32 Data1 : 25;

12271

12272 /* Bits[56:32], Access Type=RW_V, default=None*/

12273

12274 /* From IP */

12275 UINT32 SignExt : 7;

12276

12277 /* Bits[63:57], Access Type=RO_V, default=None*/

12278

12279 /*

12280 sign extension of bit 56 (VAPA fuse-enabled) or

12281 bit 47 (VAPA fuse-disabled)

12282 */

12283

12284 } Bits;

12285

12286 UINT32 Uint32;

12287 UINT64 Uint64;

12288

12289 } MSR_LBR_FROM_IP_5_5_REGISTER;

12290

12291 /**

12292 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12293 **/

12294 #define MSR_LBR_FROM_IP_6_6 0x00000686

12295

12296 typedef union {

12297 ///

12298 /// Individual bit fields

12299 ///

12300 struct {

12301 UINT32 Data0 : 32;

12302

12303 /* Bits[31:0], Access Type=RW_V, default=None*/

12304

12305 /* From IP */

12306 UINT32 Data1 : 25;

12307

12308 /* Bits[56:32], Access Type=RW_V, default=None*/

12309

12310 /* From IP */

12311 UINT32 SignExt : 7;

12312

12313 /* Bits[63:57], Access Type=RO_V, default=None*/

12314

12315 /*

12316 sign extension of bit 56 (VAPA fuse-enabled) or

12317 bit 47 (VAPA fuse-disabled)

12318 */

12319

12320 } Bits;

12321

12322 UINT32 Uint32;

12323 UINT64 Uint64;

12324

12325 } MSR_LBR_FROM_IP_6_6_REGISTER;

12326

12327 /**

12328 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12329 **/

12330 #define MSR_LBR_FROM_IP_7_7 0x00000687

12331

12332 typedef union {

12333 ///

12334 /// Individual bit fields

12335 ///

12336 struct {

12337 UINT32 Data0 : 32;

12338

12339 /* Bits[31:0], Access Type=RW_V, default=None*/

12340

12341 /* From IP */

12342 UINT32 Data1 : 25;

12343

12344 /* Bits[56:32], Access Type=RW_V, default=None*/

12345

12346 /* From IP */

12347 UINT32 SignExt : 7;

12348

12349 /* Bits[63:57], Access Type=RO_V, default=None*/

12350

12351 /*

12352 sign extension of bit 56 (VAPA fuse-enabled) or

12353 bit 47 (VAPA fuse-disabled)

12354 */

12355

12356 } Bits;

12357

12358 UINT32 Uint32;

12359 UINT64 Uint64;

12360

12361 } MSR_LBR_FROM_IP_7_7_REGISTER;

12362

12363 /**

12364 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12365 **/

12366 #define MSR_LBR_FROM_IP_8_8 0x00000688

12367

12368 typedef union {

12369 ///

12370 /// Individual bit fields

12371 ///

12372 struct {

12373 UINT32 Data0 : 32;

12374

12375 /* Bits[31:0], Access Type=RW_V, default=None*/

12376

12377 /* From IP */

12378 UINT32 Data1 : 25;

12379

12380 /* Bits[56:32], Access Type=RW_V, default=None*/

12381

12382 /* From IP */

12383 UINT32 SignExt : 7;

12384

12385 /* Bits[63:57], Access Type=RO_V, default=None*/

12386

12387 /*

12388 sign extension of bit 56 (VAPA fuse-enabled) or

12389 bit 47 (VAPA fuse-disabled)

12390 */

12391

12392 } Bits;

12393

12394 UINT32 Uint32;

12395 UINT64 Uint64;

12396

12397 } MSR_LBR_FROM_IP_8_8_REGISTER;

12398

12399 /**

12400 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12401 **/

12402 #define MSR_LBR_FROM_IP_9_9 0x00000689

12403

12404 typedef union {

12405 ///

12406 /// Individual bit fields

12407 ///

12408 struct {

12409 UINT32 Data0 : 32;

12410

12411 /* Bits[31:0], Access Type=RW_V, default=None*/

12412

12413 /* From IP */

12414 UINT32 Data1 : 25;

12415

12416 /* Bits[56:32], Access Type=RW_V, default=None*/

12417

12418 /* From IP */

12419 UINT32 SignExt : 7;

12420

12421 /* Bits[63:57], Access Type=RO_V, default=None*/

12422

12423 /*

12424 sign extension of bit 56 (VAPA fuse-enabled) or

12425 bit 47 (VAPA fuse-disabled)

12426 */

12427

12428 } Bits;

12429

12430 UINT32 Uint32;

12431 UINT64 Uint64;

12432

12433 } MSR_LBR_FROM_IP_9_9_REGISTER;

12434

12435 /**

12436 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12437 **/

12438 #define MSR_LBR_FROM_IP_10_10 0x0000068A

12439

12440 typedef union {

12441 ///

12442 /// Individual bit fields

12443 ///

12444 struct {

12445 UINT32 Data0 : 32;

12446

12447 /* Bits[31:0], Access Type=RW_V, default=None*/

12448

12449 /* From IP */

12450 UINT32 Data1 : 25;

12451

12452 /* Bits[56:32], Access Type=RW_V, default=None*/

12453

12454 /* From IP */

12455 UINT32 SignExt : 7;

12456

12457 /* Bits[63:57], Access Type=RO_V, default=None*/

12458

12459 /*

12460 sign extension of bit 56 (VAPA fuse-enabled) or

12461 bit 47 (VAPA fuse-disabled)

12462 */

12463

12464 } Bits;

12465

12466 UINT32 Uint32;

12467 UINT64 Uint64;

12468

12469 } MSR_LBR_FROM_IP_10_10_REGISTER;

12470

12471 /**

12472 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12473 **/

12474 #define MSR_LBR_FROM_IP_11_11 0x0000068B

12475

12476 typedef union {

12477 ///

12478 /// Individual bit fields

12479 ///

12480 struct {

12481 UINT32 Data0 : 32;

12482

12483 /* Bits[31:0], Access Type=RW_V, default=None*/

12484

12485 /* From IP */

12486 UINT32 Data1 : 25;

12487

12488 /* Bits[56:32], Access Type=RW_V, default=None*/

12489

12490 /* From IP */

12491 UINT32 SignExt : 7;

12492

12493 /* Bits[63:57], Access Type=RO_V, default=None*/

12494

12495 /*

12496 sign extension of bit 56 (VAPA fuse-enabled) or

12497 bit 47 (VAPA fuse-disabled)

12498 */

12499

12500 } Bits;

12501

12502 UINT32 Uint32;

12503 UINT64 Uint64;

12504

12505 } MSR_LBR_FROM_IP_11_11_REGISTER;

12506

12507 /**

12508 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12509 **/

12510 #define MSR_LBR_FROM_IP_18_18 0x00000692

12511

12512 typedef union {

12513 ///

12514 /// Individual bit fields

12515 ///

12516 struct {

12517 UINT32 Data0 : 32;

12518

12519 /* Bits[31:0], Access Type=RW_V, default=None*/

12520

12521 /* From IP */

12522 UINT32 Data1 : 25;

12523

12524 /* Bits[56:32], Access Type=RW_V, default=None*/

12525

12526 /* From IP */

12527 UINT32 SignExt : 7;

12528

12529 /* Bits[63:57], Access Type=RO_V, default=None*/

12530

12531 /*

12532 sign extension of bit 56 (VAPA fuse-enabled) or

12533 bit 47 (VAPA fuse-disabled)

12534 */

12535

12536 } Bits;

12537

12538 UINT32 Uint32;

12539 UINT64 Uint64;

12540

12541 } MSR_LBR_FROM_IP_18_18_REGISTER;

12542

12543 /**

12544 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12545 **/

12546 #define MSR_LBR_FROM_IP_19_19 0x00000693

12547

12548 typedef union {

12549 ///

12550 /// Individual bit fields

12551 ///

12552 struct {

12553 UINT32 Data0 : 32;

12554

12555 /* Bits[31:0], Access Type=RW_V, default=None*/

12556

12557 /* From IP */

12558 UINT32 Data1 : 25;

12559

12560 /* Bits[56:32], Access Type=RW_V, default=None*/

12561

12562 /* From IP */

12563 UINT32 SignExt : 7;

12564

12565 /* Bits[63:57], Access Type=RO_V, default=None*/

12566

12567 /*

12568 sign extension of bit 56 (VAPA fuse-enabled) or

12569 bit 47 (VAPA fuse-disabled)

12570 */

12571

12572 } Bits;

12573

12574 UINT32 Uint32;

12575 UINT64 Uint64;

12576

12577 } MSR_LBR_FROM_IP_19_19_REGISTER;

12578

12579 /**

12580 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12581 **/

12582 #define MSR_LBR_FROM_IP_20_20 0x00000694

12583

12584 typedef union {

12585 ///

12586 /// Individual bit fields

12587 ///

12588 struct {

12589 UINT32 Data0 : 32;

12590

12591 /* Bits[31:0], Access Type=RW_V, default=None*/

12592

12593 /* From IP */

12594 UINT32 Data1 : 25;

12595

12596 /* Bits[56:32], Access Type=RW_V, default=None*/

12597

12598 /* From IP */

12599 UINT32 SignExt : 7;

12600

12601 /* Bits[63:57], Access Type=RO_V, default=None*/

12602

12603 /*

12604 sign extension of bit 56 (VAPA fuse-enabled) or

12605 bit 47 (VAPA fuse-disabled)

12606 */

12607

12608 } Bits;

12609

12610 UINT32 Uint32;

12611 UINT64 Uint64;

12612

12613 } MSR_LBR_FROM_IP_20_20_REGISTER;

12614

12615 /**

12616 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12617 **/

12618 #define MSR_LBR_FROM_IP_21_21 0x00000695

12619

12620 typedef union {

12621 ///

12622 /// Individual bit fields

12623 ///

12624 struct {

12625 UINT32 Data0 : 32;

12626

12627 /* Bits[31:0], Access Type=RW_V, default=None*/

12628

12629 /* From IP */

12630 UINT32 Data1 : 25;

12631

12632 /* Bits[56:32], Access Type=RW_V, default=None*/

12633

12634 /* From IP */

12635 UINT32 SignExt : 7;

12636

12637 /* Bits[63:57], Access Type=RO_V, default=None*/

12638

12639 /*

12640 sign extension of bit 56 (VAPA fuse-enabled) or

12641 bit 47 (VAPA fuse-disabled)

12642 */

12643

12644 } Bits;

12645

12646 UINT32 Uint32;

12647 UINT64 Uint64;

12648

12649 } MSR_LBR_FROM_IP_21_21_REGISTER;

12650

12651 /**

12652 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12653 **/

12654 #define MSR_LBR_FROM_IP_22_22 0x00000696

12655

12656 typedef union {

12657 ///

12658 /// Individual bit fields

12659 ///

12660 struct {

12661 UINT32 Data0 : 32;

12662

12663 /* Bits[31:0], Access Type=RW_V, default=None*/

12664

12665 /* From IP */

12666 UINT32 Data1 : 25;

12667

12668 /* Bits[56:32], Access Type=RW_V, default=None*/

12669

12670 /* From IP */

12671 UINT32 SignExt : 7;

12672

12673 /* Bits[63:57], Access Type=RO_V, default=None*/

12674

12675 /*

12676 sign extension of bit 56 (VAPA fuse-enabled) or

12677 bit 47 (VAPA fuse-disabled)

12678 */

12679

12680 } Bits;

12681

12682 UINT32 Uint32;

12683 UINT64 Uint64;

12684

12685 } MSR_LBR_FROM_IP_22_22_REGISTER;

12686

12687 /**

12688 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12689 **/

12690 #define MSR_LBR_FROM_IP_23_23 0x00000697

12691

12692 typedef union {

12693 ///

12694 /// Individual bit fields

12695 ///

12696 struct {

12697 UINT32 Data0 : 32;

12698

12699 /* Bits[31:0], Access Type=RW_V, default=None*/

12700

12701 /* From IP */

12702 UINT32 Data1 : 25;

12703

12704 /* Bits[56:32], Access Type=RW_V, default=None*/

12705

12706 /* From IP */

12707 UINT32 SignExt : 7;

12708

12709 /* Bits[63:57], Access Type=RO_V, default=None*/

12710

12711 /*

12712 sign extension of bit 56 (VAPA fuse-enabled) or

12713 bit 47 (VAPA fuse-disabled)

12714 */

12715

12716 } Bits;

12717

12718 UINT32 Uint32;

12719 UINT64 Uint64;

12720

12721 } MSR_LBR_FROM_IP_23_23_REGISTER;

12722

12723 /**

12724 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12725 **/

12726 #define MSR_LBR_FROM_IP_24_24 0x00000698

12727

12728 typedef union {

12729 ///

12730 /// Individual bit fields

12731 ///

12732 struct {

12733 UINT32 Data0 : 32;

12734

12735 /* Bits[31:0], Access Type=RW_V, default=None*/

12736

12737 /* From IP */

12738 UINT32 Data1 : 25;

12739

12740 /* Bits[56:32], Access Type=RW_V, default=None*/

12741

12742 /* From IP */

12743 UINT32 SignExt : 7;

12744

12745 /* Bits[63:57], Access Type=RO_V, default=None*/

12746

12747 /*

12748 sign extension of bit 56 (VAPA fuse-enabled) or

12749 bit 47 (VAPA fuse-disabled)

12750 */

12751

12752 } Bits;

12753

12754 UINT32 Uint32;

12755 UINT64 Uint64;

12756

12757 } MSR_LBR_FROM_IP_24_24_REGISTER;

12758

12759 /**

12760 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12761 **/

12762 #define MSR_LBR_FROM_IP_25_25 0x00000699

12763

12764 typedef union {

12765 ///

12766 /// Individual bit fields

12767 ///

12768 struct {

12769 UINT32 Data0 : 32;

12770

12771 /* Bits[31:0], Access Type=RW_V, default=None*/

12772

12773 /* From IP */

12774 UINT32 Data1 : 25;

12775

12776 /* Bits[56:32], Access Type=RW_V, default=None*/

12777

12778 /* From IP */

12779 UINT32 SignExt : 7;

12780

12781 /* Bits[63:57], Access Type=RO_V, default=None*/

12782

12783 /*

12784 sign extension of bit 56 (VAPA fuse-enabled) or

12785 bit 47 (VAPA fuse-disabled)

12786 */

12787

12788 } Bits;

12789

12790 UINT32 Uint32;

12791 UINT64 Uint64;

12792

12793 } MSR_LBR_FROM_IP_25_25_REGISTER;

12794

12795 /**

12796 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12797 **/

12798 #define MSR_LBR_FROM_IP_26_26 0x0000069A

12799

12800 typedef union {

12801 ///

12802 /// Individual bit fields

12803 ///

12804 struct {

12805 UINT32 Data0 : 32;

12806

12807 /* Bits[31:0], Access Type=RW_V, default=None*/

12808

12809 /* From IP */

12810 UINT32 Data1 : 25;

12811

12812 /* Bits[56:32], Access Type=RW_V, default=None*/

12813

12814 /* From IP */

12815 UINT32 SignExt : 7;

12816

12817 /* Bits[63:57], Access Type=RO_V, default=None*/

12818

12819 /*

12820 sign extension of bit 56 (VAPA fuse-enabled) or

12821 bit 47 (VAPA fuse-disabled)

12822 */

12823

12824 } Bits;

12825

12826 UINT32 Uint32;

12827 UINT64 Uint64;

12828

12829 } MSR_LBR_FROM_IP_26_26_REGISTER;

12830

12831 /**

12832 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12833 **/

12834 #define MSR_LBR_FROM_IP_27_27 0x0000069B

12835

12836 typedef union {

12837 ///

12838 /// Individual bit fields

12839 ///

12840 struct {

12841 UINT32 Data0 : 32;

12842

12843 /* Bits[31:0], Access Type=RW_V, default=None*/

12844

12845 /* From IP */

12846 UINT32 Data1 : 25;

12847

12848 /* Bits[56:32], Access Type=RW_V, default=None*/

12849

12850 /* From IP */

12851 UINT32 SignExt : 7;

12852

12853 /* Bits[63:57], Access Type=RO_V, default=None*/

12854

12855 /*

12856 sign extension of bit 56 (VAPA fuse-enabled) or

12857 bit 47 (VAPA fuse-disabled)

12858 */

12859

12860 } Bits;

12861

12862 UINT32 Uint32;

12863 UINT64 Uint64;

12864

12865 } MSR_LBR_FROM_IP_27_27_REGISTER;

12866

12867 /**

12868 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12869 **/

12870 #define MSR_LBR_FROM_IP_28_28 0x0000069C

12871

12872 typedef union {

12873 ///

12874 /// Individual bit fields

12875 ///

12876 struct {

12877 UINT32 Data0 : 32;

12878

12879 /* Bits[31:0], Access Type=RW_V, default=None*/

12880

12881 /* From IP */

12882 UINT32 Data1 : 25;

12883

12884 /* Bits[56:32], Access Type=RW_V, default=None*/

12885

12886 /* From IP */

12887 UINT32 SignExt : 7;

12888

12889 /* Bits[63:57], Access Type=RO_V, default=None*/

12890

12891 /*

12892 sign extension of bit 56 (VAPA fuse-enabled) or

12893 bit 47 (VAPA fuse-disabled)

12894 */

12895

12896 } Bits;

12897

12898 UINT32 Uint32;

12899 UINT64 Uint64;

12900

12901 } MSR_LBR_FROM_IP_28_28_REGISTER;

12902

12903 /**

12904 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12905 **/

12906 #define MSR_LBR_FROM_IP_29_29 0x0000069D

12907

12908 typedef union {

12909 ///

12910 /// Individual bit fields

12911 ///

12912 struct {

12913 UINT32 Data0 : 32;

12914

12915 /* Bits[31:0], Access Type=RW_V, default=None*/

12916

12917 /* From IP */

12918 UINT32 Data1 : 25;

12919

12920 /* Bits[56:32], Access Type=RW_V, default=None*/

12921

12922 /* From IP */

12923 UINT32 SignExt : 7;

12924

12925 /* Bits[63:57], Access Type=RO_V, default=None*/

12926

12927 /*

12928 sign extension of bit 56 (VAPA fuse-enabled) or

12929 bit 47 (VAPA fuse-disabled)

12930 */

12931

12932 } Bits;

12933

12934 UINT32 Uint32;

12935 UINT64 Uint64;

12936

12937 } MSR_LBR_FROM_IP_29_29_REGISTER;

12938

12939 /**

12940 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12941 **/

12942 #define MSR_LBR_FROM_IP_30_30 0x0000069E

12943

12944 typedef union {

12945 ///

12946 /// Individual bit fields

12947 ///

12948 struct {

12949 UINT32 Data0 : 32;

12950

12951 /* Bits[31:0], Access Type=RW_V, default=None*/

12952

12953 /* From IP */

12954 UINT32 Data1 : 25;

12955

12956 /* Bits[56:32], Access Type=RW_V, default=None*/

12957

12958 /* From IP */

12959 UINT32 SignExt : 7;

12960

12961 /* Bits[63:57], Access Type=RO_V, default=None*/

12962

12963 /*

12964 sign extension of bit 56 (VAPA fuse-enabled) or

12965 bit 47 (VAPA fuse-disabled)

12966 */

12967

12968 } Bits;

12969

12970 UINT32 Uint32;

12971 UINT64 Uint64;

12972

12973 } MSR_LBR_FROM_IP_30_30_REGISTER;

12974

12975 /**

12976 LBR MSR that holds the from IP, canonical check for write, see Vol 3A

12977 **/

12978 #define MSR_LBR_FROM_IP_31_31 0x0000069F

12979

12980 typedef union {

12981 ///

12982 /// Individual bit fields

12983 ///

12984 struct {

12985 UINT32 Data0 : 32;

12986

12987 /* Bits[31:0], Access Type=RW_V, default=None*/

12988

12989 /* From IP */

12990 UINT32 Data1 : 25;

12991

12992 /* Bits[56:32], Access Type=RW_V, default=None*/

12993

12994 /* From IP */

12995 UINT32 SignExt : 7;

12996

12997 /* Bits[63:57], Access Type=RO_V, default=None*/

12998

12999 /*

13000 sign extension of bit 56 (VAPA fuse-enabled) or

13001 bit 47 (VAPA fuse-disabled)

13002 */

13003

13004 } Bits;

13005

13006 UINT32 Uint32;

13007 UINT64 Uint64;

13008

13009 } MSR_LBR_FROM_IP_31_31_REGISTER;

13010

13011 /**

13012 LBR MSR that holds the from IP

13013 **/

13014 #define MSR_LBR_TO_IP_0_0 0x000006C0

13015

13016 typedef union {

13017 ///

13018 /// Individual bit fields

13019 ///

13020 struct {

13021 UINT32 Data0 : 32;

13022

13023 /* Bits[31:0], Access Type=RW_V, default=None*/

13024

13025 /* Target IP */

13026 UINT32 Data1 : 25;

13027

13028 /* Bits[56:32], Access Type=RW_V, default=None*/

13029

13030 /* Target IP */

13031 UINT32 SignExt : 7;

13032

13033 /* Bits[63:57], Access Type=RO_V, default=None*/

13034

13035 /*

13036 sign extension of bit 56 (VAPA fuse-enabled) or

13037 bit 47 (VAPA fuse-disabled)

13038 */

13039

13040 } Bits;

13041

13042 UINT32 Uint32;

13043 UINT64 Uint64;

13044

13045 } MSR_LBR_TO_IP_0_0_REGISTER;

13046

13047 /**

13048 LBR MSR that holds the from IP

13049 **/

13050 #define MSR_LBR_TO_IP_1_1 0x000006C1

13051

13052 typedef union {

13053 ///

13054 /// Individual bit fields

13055 ///

13056 struct {

13057 UINT32 Data0 : 32;

13058

13059 /* Bits[31:0], Access Type=RW_V, default=None*/

13060

13061 /* Target IP */

13062 UINT32 Data1 : 25;

13063

13064 /* Bits[56:32], Access Type=RW_V, default=None*/

13065

13066 /* Target IP */

13067 UINT32 SignExt : 7;

13068

13069 /* Bits[63:57], Access Type=RO_V, default=None*/

13070

13071 /*

13072 sign extension of bit 56 (VAPA fuse-enabled) or

13073 bit 47 (VAPA fuse-disabled)

13074 */

13075

13076 } Bits;

13077

13078 UINT32 Uint32;

13079 UINT64 Uint64;

13080

13081 } MSR_LBR_TO_IP_1_1_REGISTER;

13082

13083 /**

13084 LBR MSR that holds the from IP

13085 **/

13086 #define MSR_LBR_TO_IP_2_2 0x000006C2

13087

13088 typedef union {

13089 ///

13090 /// Individual bit fields

13091 ///

13092 struct {

13093 UINT32 Data0 : 32;

13094

13095 /* Bits[31:0], Access Type=RW_V, default=None*/

13096

13097 /* Target IP */

13098 UINT32 Data1 : 25;

13099

13100 /* Bits[56:32], Access Type=RW_V, default=None*/

13101

13102 /* Target IP */

13103 UINT32 SignExt : 7;

13104

13105 /* Bits[63:57], Access Type=RO_V, default=None*/

13106

13107 /*

13108 sign extension of bit 56 (VAPA fuse-enabled) or

13109 bit 47 (VAPA fuse-disabled)

13110 */

13111

13112 } Bits;

13113

13114 UINT32 Uint32;

13115 UINT64 Uint64;

13116

13117 } MSR_LBR_TO_IP_2_2_REGISTER;

13118

13119 /**

13120 LBR MSR that holds the from IP

13121 **/

13122 #define MSR_LBR_TO_IP_3_3 0x000006C3

13123

13124 typedef union {

13125 ///

13126 /// Individual bit fields

13127 ///

13128 struct {

13129 UINT32 Data0 : 32;

13130

13131 /* Bits[31:0], Access Type=RW_V, default=None*/

13132

13133 /* Target IP */

13134 UINT32 Data1 : 25;

13135

13136 /* Bits[56:32], Access Type=RW_V, default=None*/

13137

13138 /* Target IP */

13139 UINT32 SignExt : 7;

13140

13141 /* Bits[63:57], Access Type=RO_V, default=None*/

13142

13143 /*

13144 sign extension of bit 56 (VAPA fuse-enabled) or

13145 bit 47 (VAPA fuse-disabled)

13146 */

13147

13148 } Bits;

13149

13150 UINT32 Uint32;

13151 UINT64 Uint64;

13152

13153 } MSR_LBR_TO_IP_3_3_REGISTER;

13154

13155 /**

13156 LBR MSR that holds the from IP

13157 **/

13158 #define MSR_LBR_TO_IP_4_4 0x000006C4

13159

13160 typedef union {

13161 ///

13162 /// Individual bit fields

13163 ///

13164 struct {

13165 UINT32 Data0 : 32;

13166

13167 /* Bits[31:0], Access Type=RW_V, default=None*/

13168

13169 /* Target IP */

13170 UINT32 Data1 : 25;

13171

13172 /* Bits[56:32], Access Type=RW_V, default=None*/

13173

13174 /* Target IP */

13175 UINT32 SignExt : 7;

13176

13177 /* Bits[63:57], Access Type=RO_V, default=None*/

13178

13179 /*

13180 sign extension of bit 56 (VAPA fuse-enabled) or

13181 bit 47 (VAPA fuse-disabled)

13182 */

13183

13184 } Bits;

13185

13186 UINT32 Uint32;

13187 UINT64 Uint64;

13188

13189 } MSR_LBR_TO_IP_4_4_REGISTER;

13190

13191 /**

13192 LBR MSR that holds the from IP

13193 **/

13194 #define MSR_LBR_TO_IP_5_5 0x000006C5

13195

13196 typedef union {

13197 ///

13198 /// Individual bit fields

13199 ///

13200 struct {

13201 UINT32 Data0 : 32;

13202

13203 /* Bits[31:0], Access Type=RW_V, default=None*/

13204

13205 /* Target IP */

13206 UINT32 Data1 : 25;

13207

13208 /* Bits[56:32], Access Type=RW_V, default=None*/

13209

13210 /* Target IP */

13211 UINT32 SignExt : 7;

13212

13213 /* Bits[63:57], Access Type=RO_V, default=None*/

13214

13215 /*

13216 sign extension of bit 56 (VAPA fuse-enabled) or

13217 bit 47 (VAPA fuse-disabled)

13218 */

13219

13220 } Bits;

13221

13222 UINT32 Uint32;

13223 UINT64 Uint64;

13224

13225 } MSR_LBR_TO_IP_5_5_REGISTER;

13226

13227 /**

13228 LBR MSR that holds the from IP

13229 **/

13230 #define MSR_LBR_TO_IP_6_6 0x000006C6

13231

13232 typedef union {

13233 ///

13234 /// Individual bit fields

13235 ///

13236 struct {

13237 UINT32 Data0 : 32;

13238

13239 /* Bits[31:0], Access Type=RW_V, default=None*/

13240

13241 /* Target IP */

13242 UINT32 Data1 : 25;

13243

13244 /* Bits[56:32], Access Type=RW_V, default=None*/

13245

13246 /* Target IP */

13247 UINT32 SignExt : 7;

13248

13249 /* Bits[63:57], Access Type=RO_V, default=None*/

13250

13251 /*

13252 sign extension of bit 56 (VAPA fuse-enabled) or

13253 bit 47 (VAPA fuse-disabled)

13254 */

13255

13256 } Bits;

13257

13258 UINT32 Uint32;

13259 UINT64 Uint64;

13260

13261 } MSR_LBR_TO_IP_6_6_REGISTER;

13262

13263 /**

13264 LBR MSR that holds the from IP

13265 **/

13266 #define MSR_LBR_TO_IP_7_7 0x000006C7

13267

13268 typedef union {

13269 ///

13270 /// Individual bit fields

13271 ///

13272 struct {

13273 UINT32 Data0 : 32;

13274

13275 /* Bits[31:0], Access Type=RW_V, default=None*/

13276

13277 /* Target IP */

13278 UINT32 Data1 : 25;

13279

13280 /* Bits[56:32], Access Type=RW_V, default=None*/

13281

13282 /* Target IP */

13283 UINT32 SignExt : 7;

13284

13285 /* Bits[63:57], Access Type=RO_V, default=None*/

13286

13287 /*

13288 sign extension of bit 56 (VAPA fuse-enabled) or

13289 bit 47 (VAPA fuse-disabled)

13290 */

13291

13292 } Bits;

13293

13294 UINT32 Uint32;

13295 UINT64 Uint64;

13296

13297 } MSR_LBR_TO_IP_7_7_REGISTER;

13298

13299 /**

13300 LBR MSR that holds the from IP

13301 **/

13302 #define MSR_LBR_TO_IP_8_8 0x000006C8

13303

13304 typedef union {

13305 ///

13306 /// Individual bit fields

13307 ///

13308 struct {

13309 UINT32 Data0 : 32;

13310

13311 /* Bits[31:0], Access Type=RW_V, default=None*/

13312

13313 /* Target IP */

13314 UINT32 Data1 : 25;

13315

13316 /* Bits[56:32], Access Type=RW_V, default=None*/

13317

13318 /* Target IP */

13319 UINT32 SignExt : 7;

13320

13321 /* Bits[63:57], Access Type=RO_V, default=None*/

13322

13323 /*

13324 sign extension of bit 56 (VAPA fuse-enabled) or

13325 bit 47 (VAPA fuse-disabled)

13326 */

13327

13328 } Bits;

13329

13330 UINT32 Uint32;

13331 UINT64 Uint64;

13332

13333 } MSR_LBR_TO_IP_8_8_REGISTER;

13334

13335 /**

13336 LBR MSR that holds the from IP

13337 **/

13338 #define MSR_LBR_TO_IP_9_9 0x000006C9

13339

13340 typedef union {

13341 ///

13342 /// Individual bit fields

13343 ///

13344 struct {

13345 UINT32 Data0 : 32;

13346

13347 /* Bits[31:0], Access Type=RW_V, default=None*/

13348

13349 /* Target IP */

13350 UINT32 Data1 : 25;

13351

13352 /* Bits[56:32], Access Type=RW_V, default=None*/

13353

13354 /* Target IP */

13355 UINT32 SignExt : 7;

13356

13357 /* Bits[63:57], Access Type=RO_V, default=None*/

13358

13359 /*

13360 sign extension of bit 56 (VAPA fuse-enabled) or

13361 bit 47 (VAPA fuse-disabled)

13362 */

13363

13364 } Bits;

13365

13366 UINT32 Uint32;

13367 UINT64 Uint64;

13368

13369 } MSR_LBR_TO_IP_9_9_REGISTER;

13370

13371 /**

13372 LBR MSR that holds the from IP

13373 **/

13374 #define MSR_LBR_TO_IP_10_10 0x000006CA

13375

13376 typedef union {

13377 ///

13378 /// Individual bit fields

13379 ///

13380 struct {

13381 UINT32 Data0 : 32;

13382

13383 /* Bits[31:0], Access Type=RW_V, default=None*/

13384

13385 /* Target IP */

13386 UINT32 Data1 : 25;

13387

13388 /* Bits[56:32], Access Type=RW_V, default=None*/

13389

13390 /* Target IP */

13391 UINT32 SignExt : 7;

13392

13393 /* Bits[63:57], Access Type=RO_V, default=None*/

13394

13395 /*

13396 sign extension of bit 56 (VAPA fuse-enabled) or

13397 bit 47 (VAPA fuse-disabled)

13398 */

13399

13400 } Bits;

13401

13402 UINT32 Uint32;

13403 UINT64 Uint64;

13404

13405 } MSR_LBR_TO_IP_10_10_REGISTER;

13406

13407 /**

13408 LBR MSR that holds the from IP

13409 **/

13410 #define MSR_LBR_TO_IP_11_11 0x000006CB

13411

13412 typedef union {

13413 ///

13414 /// Individual bit fields

13415 ///

13416 struct {

13417 UINT32 Data0 : 32;

13418

13419 /* Bits[31:0], Access Type=RW_V, default=None*/

13420

13421 /* Target IP */

13422 UINT32 Data1 : 25;

13423

13424 /* Bits[56:32], Access Type=RW_V, default=None*/

13425

13426 /* Target IP */

13427 UINT32 SignExt : 7;

13428

13429 /* Bits[63:57], Access Type=RO_V, default=None*/

13430

13431 /*

13432 sign extension of bit 56 (VAPA fuse-enabled) or

13433 bit 47 (VAPA fuse-disabled)

13434 */

13435

13436 } Bits;

13437

13438 UINT32 Uint32;

13439 UINT64 Uint64;

13440

13441 } MSR_LBR_TO_IP_11_11_REGISTER;

13442

13443 /**

13444 LBR MSR that holds the from IP

13445 **/

13446 #define MSR_LBR_TO_IP_12_12 0x000006CC

13447

13448 typedef union {

13449 ///

13450 /// Individual bit fields

13451 ///

13452 struct {

13453 UINT32 Data0 : 32;

13454

13455 /* Bits[31:0], Access Type=RW_V, default=None*/

13456

13457 /* Target IP */

13458 UINT32 Data1 : 25;

13459

13460 /* Bits[56:32], Access Type=RW_V, default=None*/

13461

13462 /* Target IP */

13463 UINT32 SignExt : 7;

13464

13465 /* Bits[63:57], Access Type=RO_V, default=None*/

13466

13467 /*

13468 sign extension of bit 56 (VAPA fuse-enabled) or

13469 bit 47 (VAPA fuse-disabled)

13470 */

13471

13472 } Bits;

13473

13474 UINT32 Uint32;

13475 UINT64 Uint64;

13476

13477 } MSR_LBR_TO_IP_12_12_REGISTER;

13478

13479 /**

13480 LBR MSR that holds the from IP

13481 **/

13482 #define MSR_LBR_TO_IP_13_13 0x000006CD

13483

13484 typedef union {

13485 ///

13486 /// Individual bit fields

13487 ///

13488 struct {

13489 UINT32 Data0 : 32;

13490

13491 /* Bits[31:0], Access Type=RW_V, default=None*/

13492

13493 /* Target IP */

13494 UINT32 Data1 : 25;

13495

13496 /* Bits[56:32], Access Type=RW_V, default=None*/

13497

13498 /* Target IP */

13499 UINT32 SignExt : 7;

13500

13501 /* Bits[63:57], Access Type=RO_V, default=None*/

13502

13503 /*

13504 sign extension of bit 56 (VAPA fuse-enabled) or

13505 bit 47 (VAPA fuse-disabled)

13506 */

13507

13508 } Bits;

13509

13510 UINT32 Uint32;

13511 UINT64 Uint64;

13512

13513 } MSR_LBR_TO_IP_13_13_REGISTER;

13514

13515 /**

13516 LBR MSR that holds the from IP

13517 **/

13518 #define MSR_LBR_TO_IP_14_14 0x000006CE

13519

13520 typedef union {

13521 ///

13522 /// Individual bit fields

13523 ///

13524 struct {

13525 UINT32 Data0 : 32;

13526

13527 /* Bits[31:0], Access Type=RW_V, default=None*/

13528

13529 /* Target IP */

13530 UINT32 Data1 : 25;

13531

13532 /* Bits[56:32], Access Type=RW_V, default=None*/

13533

13534 /* Target IP */

13535 UINT32 SignExt : 7;

13536

13537 /* Bits[63:57], Access Type=RO_V, default=None*/

13538

13539 /*

13540 sign extension of bit 56 (VAPA fuse-enabled) or

13541 bit 47 (VAPA fuse-disabled)

13542 */

13543

13544 } Bits;

13545

13546 UINT32 Uint32;

13547 UINT64 Uint64;

13548

13549 } MSR_LBR_TO_IP_14_14_REGISTER;

13550

13551 /**

13552 LBR MSR that holds the from IP

13553 **/

13554 #define MSR_LBR_TO_IP_15_15 0x000006CF

13555

13556 typedef union {

13557 ///

13558 /// Individual bit fields

13559 ///

13560 struct {

13561 UINT32 Data0 : 32;

13562

13563 /* Bits[31:0], Access Type=RW_V, default=None*/

13564

13565 /* Target IP */

13566 UINT32 Data1 : 25;

13567

13568 /* Bits[56:32], Access Type=RW_V, default=None*/

13569

13570 /* Target IP */

13571 UINT32 SignExt : 7;

13572

13573 /* Bits[63:57], Access Type=RO_V, default=None*/

13574

13575 /*

13576 sign extension of bit 56 (VAPA fuse-enabled) or

13577 bit 47 (VAPA fuse-disabled)

13578 */

13579

13580 } Bits;

13581

13582 UINT32 Uint32;

13583 UINT64 Uint64;

13584

13585 } MSR_LBR_TO_IP_15_15_REGISTER;

13586

13587 /**

13588 LBR MSR that holds the from IP

13589 **/

13590 #define MSR_LBR_TO_IP_16_16 0x000006D0

13591

13592 typedef union {

13593 ///

13594 /// Individual bit fields

13595 ///

13596 struct {

13597 UINT32 Data0 : 32;

13598

13599 /* Bits[31:0], Access Type=RW_V, default=None*/

13600

13601 /* Target IP */

13602 UINT32 Data1 : 25;

13603

13604 /* Bits[56:32], Access Type=RW_V, default=None*/

13605

13606 /* Target IP */

13607 UINT32 SignExt : 7;

13608

13609 /* Bits[63:57], Access Type=RO_V, default=None*/

13610

13611 /*

13612 sign extension of bit 56 (VAPA fuse-enabled) or

13613 bit 47 (VAPA fuse-disabled)

13614 */

13615

13616 } Bits;

13617

13618 UINT32 Uint32;

13619 UINT64 Uint64;

13620

13621 } MSR_LBR_TO_IP_16_16_REGISTER;

13622

13623 /**

13624 LBR MSR that holds the from IP

13625 **/

13626 #define MSR_LBR_TO_IP_17_17 0x000006D1

13627

13628 typedef union {

13629 ///

13630 /// Individual bit fields

13631 ///

13632 struct {

13633 UINT32 Data0 : 32;

13634

13635 /* Bits[31:0], Access Type=RW_V, default=None*/

13636

13637 /* Target IP */

13638 UINT32 Data1 : 25;

13639

13640 /* Bits[56:32], Access Type=RW_V, default=None*/

13641

13642 /* Target IP */

13643 UINT32 SignExt : 7;

13644

13645 /* Bits[63:57], Access Type=RO_V, default=None*/

13646

13647 /*

13648 sign extension of bit 56 (VAPA fuse-enabled) or

13649 bit 47 (VAPA fuse-disabled)

13650 */

13651

13652 } Bits;

13653

13654 UINT32 Uint32;

13655 UINT64 Uint64;

13656

13657 } MSR_LBR_TO_IP_17_17_REGISTER;

13658

13659 /**

13660 LBR MSR that holds the from IP

13661 **/

13662 #define MSR_LBR_TO_IP_18_18 0x000006D2

13663

13664 typedef union {

13665 ///

13666 /// Individual bit fields

13667 ///

13668 struct {

13669 UINT32 Data0 : 32;

13670

13671 /* Bits[31:0], Access Type=RW_V, default=None*/

13672

13673 /* Target IP */

13674 UINT32 Data1 : 25;

13675

13676 /* Bits[56:32], Access Type=RW_V, default=None*/

13677

13678 /* Target IP */

13679 UINT32 SignExt : 7;

13680

13681 /* Bits[63:57], Access Type=RO_V, default=None*/

13682

13683 /*

13684 sign extension of bit 56 (VAPA fuse-enabled) or

13685 bit 47 (VAPA fuse-disabled)

13686 */

13687

13688 } Bits;

13689

13690 UINT32 Uint32;

13691 UINT64 Uint64;

13692

13693 } MSR_LBR_TO_IP_18_18_REGISTER;

13694

13695 /**

13696 LBR MSR that holds the from IP

13697 **/

13698 #define MSR_LBR_TO_IP_19_19 0x000006D3

13699

13700 typedef union {

13701 ///

13702 /// Individual bit fields

13703 ///

13704 struct {

13705 UINT32 Data0 : 32;

13706

13707 /* Bits[31:0], Access Type=RW_V, default=None*/

13708

13709 /* Target IP */

13710 UINT32 Data1 : 25;

13711

13712 /* Bits[56:32], Access Type=RW_V, default=None*/

13713

13714 /* Target IP */

13715 UINT32 SignExt : 7;

13716

13717 /* Bits[63:57], Access Type=RO_V, default=None*/

13718

13719 /*

13720 sign extension of bit 56 (VAPA fuse-enabled) or

13721 bit 47 (VAPA fuse-disabled)

13722 */

13723

13724 } Bits;

13725

13726 UINT32 Uint32;

13727 UINT64 Uint64;

13728

13729 } MSR_LBR_TO_IP_19_19_REGISTER;

13730

13731 /**

13732 LBR MSR that holds the from IP

13733 **/

13734 #define MSR_LBR_TO_IP_20_20 0x000006D4

13735

13736 typedef union {

13737 ///

13738 /// Individual bit fields

13739 ///

13740 struct {

13741 UINT32 Data0 : 32;

13742

13743 /* Bits[31:0], Access Type=RW_V, default=None*/

13744

13745 /* Target IP */

13746 UINT32 Data1 : 25;

13747

13748 /* Bits[56:32], Access Type=RW_V, default=None*/

13749

13750 /* Target IP */

13751 UINT32 SignExt : 7;

13752

13753 /* Bits[63:57], Access Type=RO_V, default=None*/

13754

13755 /*

13756 sign extension of bit 56 (VAPA fuse-enabled) or

13757 bit 47 (VAPA fuse-disabled)

13758 */

13759

13760 } Bits;

13761

13762 UINT32 Uint32;

13763 UINT64 Uint64;

13764

13765 } MSR_LBR_TO_IP_20_20_REGISTER;

13766

13767 /**

13768 LBR MSR that holds the from IP

13769 **/

13770 #define MSR_LBR_TO_IP_21_21 0x000006D5

13771

13772 typedef union {

13773 ///

13774 /// Individual bit fields

13775 ///

13776 struct {

13777 UINT32 Data0 : 32;

13778

13779 /* Bits[31:0], Access Type=RW_V, default=None*/

13780

13781 /* Target IP */

13782 UINT32 Data1 : 25;

13783

13784 /* Bits[56:32], Access Type=RW_V, default=None*/

13785

13786 /* Target IP */

13787 UINT32 SignExt : 7;

13788

13789 /* Bits[63:57], Access Type=RO_V, default=None*/

13790

13791 /*

13792 sign extension of bit 56 (VAPA fuse-enabled) or

13793 bit 47 (VAPA fuse-disabled)

13794 */

13795

13796 } Bits;

13797

13798 UINT32 Uint32;

13799 UINT64 Uint64;

13800

13801 } MSR_LBR_TO_IP_21_21_REGISTER;

13802

13803 /**

13804 LBR MSR that holds the from IP

13805 **/

13806 #define MSR_LBR_TO_IP_22_22 0x000006D6

13807

13808 typedef union {

13809 ///

13810 /// Individual bit fields

13811 ///

13812 struct {

13813 UINT32 Data0 : 32;

13814

13815 /* Bits[31:0], Access Type=RW_V, default=None*/

13816

13817 /* Target IP */

13818 UINT32 Data1 : 25;

13819

13820 /* Bits[56:32], Access Type=RW_V, default=None*/

13821

13822 /* Target IP */

13823 UINT32 SignExt : 7;

13824

13825 /* Bits[63:57], Access Type=RO_V, default=None*/

13826

13827 /*

13828 sign extension of bit 56 (VAPA fuse-enabled) or

13829 bit 47 (VAPA fuse-disabled)

13830 */

13831

13832 } Bits;

13833

13834 UINT32 Uint32;

13835 UINT64 Uint64;

13836

13837 } MSR_LBR_TO_IP_22_22_REGISTER;

13838

13839 /**

13840 LBR MSR that holds the from IP

13841 **/

13842 #define MSR_LBR_TO_IP_23_23 0x000006D7

13843

13844 typedef union {

13845 ///

13846 /// Individual bit fields

13847 ///

13848 struct {

13849 UINT32 Data0 : 32;

13850

13851 /* Bits[31:0], Access Type=RW_V, default=None*/

13852

13853 /* Target IP */

13854 UINT32 Data1 : 25;

13855

13856 /* Bits[56:32], Access Type=RW_V, default=None*/

13857

13858 /* Target IP */

13859 UINT32 SignExt : 7;

13860

13861 /* Bits[63:57], Access Type=RO_V, default=None*/

13862

13863 /*

13864 sign extension of bit 56 (VAPA fuse-enabled) or

13865 bit 47 (VAPA fuse-disabled)

13866 */

13867

13868 } Bits;

13869

13870 UINT32 Uint32;

13871 UINT64 Uint64;

13872

13873 } MSR_LBR_TO_IP_23_23_REGISTER;

13874

13875 /**

13876 LBR MSR that holds the from IP

13877 **/

13878 #define MSR_LBR_TO_IP_24_24 0x000006D8

13879

13880 typedef union {

13881 ///

13882 /// Individual bit fields

13883 ///

13884 struct {

13885 UINT32 Data0 : 32;

13886

13887 /* Bits[31:0], Access Type=RW_V, default=None*/

13888

13889 /* Target IP */

13890 UINT32 Data1 : 25;

13891

13892 /* Bits[56:32], Access Type=RW_V, default=None*/

13893

13894 /* Target IP */

13895 UINT32 SignExt : 7;

13896

13897 /* Bits[63:57], Access Type=RO_V, default=None*/

13898

13899 /*

13900 sign extension of bit 56 (VAPA fuse-enabled) or

13901 bit 47 (VAPA fuse-disabled)

13902 */

13903

13904 } Bits;

13905

13906 UINT32 Uint32;

13907 UINT64 Uint64;

13908

13909 } MSR_LBR_TO_IP_24_24_REGISTER;

13910

13911 /**

13912 LBR MSR that holds the from IP

13913 **/

13914 #define MSR_LBR_TO_IP_25_25 0x000006D9

13915

13916 typedef union {

13917 ///

13918 /// Individual bit fields

13919 ///

13920 struct {

13921 UINT32 Data0 : 32;

13922

13923 /* Bits[31:0], Access Type=RW_V, default=None*/

13924

13925 /* Target IP */

13926 UINT32 Data1 : 25;

13927

13928 /* Bits[56:32], Access Type=RW_V, default=None*/

13929

13930 /* Target IP */

13931 UINT32 SignExt : 7;

13932

13933 /* Bits[63:57], Access Type=RO_V, default=None*/

13934

13935 /*

13936 sign extension of bit 56 (VAPA fuse-enabled) or

13937 bit 47 (VAPA fuse-disabled)

13938 */

13939

13940 } Bits;

13941

13942 UINT32 Uint32;

13943 UINT64 Uint64;

13944

13945 } MSR_LBR_TO_IP_25_25_REGISTER;

13946

13947 /**

13948 LBR MSR that holds the from IP

13949 **/

13950 #define MSR_LBR_TO_IP_26_26 0x000006DA

13951

13952 typedef union {

13953 ///

13954 /// Individual bit fields

13955 ///

13956 struct {

13957 UINT32 Data0 : 32;

13958

13959 /* Bits[31:0], Access Type=RW_V, default=None*/

13960

13961 /* Target IP */

13962 UINT32 Data1 : 25;

13963

13964 /* Bits[56:32], Access Type=RW_V, default=None*/

13965

13966 /* Target IP */

13967 UINT32 SignExt : 7;

13968

13969 /* Bits[63:57], Access Type=RO_V, default=None*/

13970

13971 /*

13972 sign extension of bit 56 (VAPA fuse-enabled) or

13973 bit 47 (VAPA fuse-disabled)

13974 */

13975

13976 } Bits;

13977

13978 UINT32 Uint32;

13979 UINT64 Uint64;

13980

13981 } MSR_LBR_TO_IP_26_26_REGISTER;

13982

13983 /**

13984 LBR MSR that holds the from IP

13985 **/

13986 #define MSR_LBR_TO_IP_27_27 0x000006DB

13987

13988 typedef union {

13989 ///

13990 /// Individual bit fields

13991 ///

13992 struct {

13993 UINT32 Data0 : 32;

13994

13995 /* Bits[31:0], Access Type=RW_V, default=None*/

13996

13997 /* Target IP */

13998 UINT32 Data1 : 25;

13999

14000 /* Bits[56:32], Access Type=RW_V, default=None*/

14001

14002 /* Target IP */

14003 UINT32 SignExt : 7;

14004

14005 /* Bits[63:57], Access Type=RO_V, default=None*/

14006

14007 /*

14008 sign extension of bit 56 (VAPA fuse-enabled) or

14009 bit 47 (VAPA fuse-disabled)

14010 */

14011

14012 } Bits;

14013

14014 UINT32 Uint32;

14015 UINT64 Uint64;

14016

14017 } MSR_LBR_TO_IP_27_27_REGISTER;

14018

14019 /**

14020 LBR MSR that holds the from IP

14021 **/

14022 #define MSR_LBR_TO_IP_28_28 0x000006DC

14023

14024 typedef union {

14025 ///

14026 /// Individual bit fields

14027 ///

14028 struct {

14029 UINT32 Data0 : 32;

14030

14031 /* Bits[31:0], Access Type=RW_V, default=None*/

14032

14033 /* Target IP */

14034 UINT32 Data1 : 25;

14035

14036 /* Bits[56:32], Access Type=RW_V, default=None*/

14037

14038 /* Target IP */

14039 UINT32 SignExt : 7;

14040

14041 /* Bits[63:57], Access Type=RO_V, default=None*/

14042

14043 /*

14044 sign extension of bit 56 (VAPA fuse-enabled) or

14045 bit 47 (VAPA fuse-disabled)

14046 */

14047

14048 } Bits;

14049

14050 UINT32 Uint32;

14051 UINT64 Uint64;

14052

14053 } MSR_LBR_TO_IP_28_28_REGISTER;

14054

14055 /**

14056 LBR MSR that holds the from IP

14057 **/

14058 #define MSR_LBR_TO_IP_29_29 0x000006DD

14059

14060 typedef union {

14061 ///

14062 /// Individual bit fields

14063 ///

14064 struct {

14065 UINT32 Data0 : 32;

14066

14067 /* Bits[31:0], Access Type=RW_V, default=None*/

14068

14069 /* Target IP */

14070 UINT32 Data1 : 25;

14071

14072 /* Bits[56:32], Access Type=RW_V, default=None*/

14073

14074 /* Target IP */

14075 UINT32 SignExt : 7;

14076

14077 /* Bits[63:57], Access Type=RO_V, default=None*/

14078

14079 /*

14080 sign extension of bit 56 (VAPA fuse-enabled) or

14081 bit 47 (VAPA fuse-disabled)

14082 */

14083

14084 } Bits;

14085

14086 UINT32 Uint32;

14087 UINT64 Uint64;

14088

14089 } MSR_LBR_TO_IP_29_29_REGISTER;

14090

14091 /**

14092 LBR MSR that holds the from IP

14093 **/

14094 #define MSR_LBR_TO_IP_30_30 0x000006DE

14095

14096 typedef union {

14097 ///

14098 /// Individual bit fields

14099 ///

14100 struct {

14101 UINT32 Data0 : 32;

14102

14103 /* Bits[31:0], Access Type=RW_V, default=None*/

14104

14105 /* Target IP */

14106 UINT32 Data1 : 25;

14107

14108 /* Bits[56:32], Access Type=RW_V, default=None*/

14109

14110 /* Target IP */

14111 UINT32 SignExt : 7;

14112

14113 /* Bits[63:57], Access Type=RO_V, default=None*/

14114

14115 /*

14116 sign extension of bit 56 (VAPA fuse-enabled) or

14117 bit 47 (VAPA fuse-disabled)

14118 */

14119

14120 } Bits;

14121

14122 UINT32 Uint32;

14123 UINT64 Uint64;

14124

14125 } MSR_LBR_TO_IP_30_30_REGISTER;

14126

14127 /**

14128 LBR MSR that holds the from IP

14129 **/

14130 #define MSR_LBR_TO_IP_31_31 0x000006DF

14131

14132 typedef union {

14133 ///

14134 /// Individual bit fields

14135 ///

14136 struct {

14137 UINT32 Data0 : 32;

14138

14139 /* Bits[31:0], Access Type=RW_V, default=None*/

14140

14141 /* Target IP */

14142 UINT32 Data1 : 25;

14143

14144 /* Bits[56:32], Access Type=RW_V, default=None*/

14145

14146 /* Target IP */

14147 UINT32 SignExt : 7;

14148

14149 /* Bits[63:57], Access Type=RO_V, default=None*/

14150

14151 /*

14152 sign extension of bit 56 (VAPA fuse-enabled) or

14153 bit 47 (VAPA fuse-disabled)

14154 */

14155

14156 } Bits;

14157

14158 UINT32 Uint32;

14159 UINT64 Uint64;

14160

14161 } MSR_LBR_TO_IP_31_31_REGISTER;

14162

14163 /**

14164 Holds global control fields for the NCU PMON counters.

14165 All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCtrClr] is set to 1b.

14166 **/

14167 #define MSR_NCUPMONCTRLGLCTR 0x00000707

14168

14169 typedef union {

14170 ///

14171 /// Individual bit fields

14172 ///

14173 struct {

14174 UINT32 Threadid : 4;

14175

14176 /* Bits[3:0], Access Type=RW, default=0x00000000*/

14177

14178 /*

14179 The Thread-ID format is given as follows: [0:0]

14180 T0 or T1. For GT Core this bit must be 0. [3:1]

14181 Core ID. When "TID Filter Enable" is clear in

14182 the Counter Control register, then the specified

14183 counter will count all events. Thread-ID value

14184 of 0xE is reserved for non-associated requests

14185 like LLC victims and External Snoops.

14186 */

14187 UINT32 Rsvd4 : 28;

14188

14189 /* Bits[31:4], Access Type=RO, default=None*/

14190

14191 /* Reserved */

14192

14193 } Bits;

14194

14195 UINT32 Uint32;

14196 UINT64 Uint64;

14197

14198 } MSR_NCUPMONCTRLGLCTR_REGISTER;

14199

14200 /**

14201 Ubox local PMON mask for NCDEC events

14202 **/

14203 #define MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL0 0x0000070B

14204

14205 typedef union {

14206 ///

14207 /// Individual bit fields

14208 ///

14209 struct {

14210 UINT32 Mask : 25;

14211

14212 /* Bits[24:0], Access Type=RWS, default=0x00000000*/

14213

14214 /*

14215 event mask bit per ring message decode [ 0]

14216 PMON_NCDEC_MASK_NCB_Int_CBO_IIO [ 1]

14217 PMON_NCDEC_MASK_NCB_Int_UBX_QPI [ 2]

14218 PMON_NCDEC_MASK_NCB_P2PB_IIO [ 3]

14219 PMON_NCDEC_MASK_NCB_P2PB_CBO_UBX_QPI [ 4]

14220 PMON_NCDEC_MASK_NCB_VLW_IIO_CBO [ 5]

14221 PMON_NCDEC_MASK_NCB_VLW_UBX_QPI [ 6]

14222 PMON_NCDEC_MASK_NCB_EOI_CBO [ 7]

14223 PMON_NCDEC_MASK_NCB_EOI_UBX_QPI [ 8]

14224 PMON_NCDEC_MASK_NCB_EOI_IIO [ 9]

14225 PMON_NCDEC_MASK_NCB_STARTREQ234 [10]

14226 PMON_NCDEC_MASK_NCB_PMREQ [11]

14227 PMON_NCDEC_MASK_NCB_RSVD [12]

14228 PMON_NCDEC_MASK_NCS_CfgRd_Wr [13]

14229 PMON_NCDEC_MASK_NCS_IORd_Wr [14]

14230 PMON_NCDEC_MASK_NCS_LTRd [15]

14231 PMON_NCDEC_MASK_NCS_LTWr_IIO_CBO [16]

14232 PMON_NCDEC_MASK_NCS_LTWr_UBX_QPI [17]

14233 PMON_NCDEC_MASK_NCS_FERR [18]

14234 PMON_NCDEC_MASK_NCS_RSVD [19]

14235 PMON_NCDEC_MASK_NCS_SHUTDOWN_CBO [20]

14236 PMON_NCDEC_MASK_NCS_LOCKS_UNLOCK_CBO_IIO [21]

14237 PMON_NCDEC_MASK_NCS_LOCKS_UNLOCK_UBX_QPI [22]

14238 PMON_NCDEC_MASK_NCS_STARTREQ1_STOPREQ1234 [23]

14239 PMON_NCDEC_MASK_NCS_INVD_WBINVD_CBO_IIO [24]

14240 PMON_NCDEC_MASK_NCS_INVD_WBINVD_UBX_QPI

14241 */

14242 UINT32 Rsvd25 : 7;

14243

14244 /* Bits[31:25], Access Type=RO, default=None*/

14245

14246 /* Reserved */

14247

14248 } Bits;

14249

14250 UINT32 Uint32;

14251 UINT64 Uint64;

14252

14253 } MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL0_REGISTER;

14254

14255 /**

14256 Ubox local PMON mask for NCDEC events for subunit target

14257 **/

14258 #define MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL1 0x0000070C

14259

14260 typedef union {

14261 ///

14262 /// Individual bit fields

14263 ///

14264 struct {

14265 UINT32 Mask : 12;

14266

14267 /* Bits[11:0], Access Type=RWS, default=0x00000000*/

14268

14269 /*

14270 event mask bit per sub unit target [ 0] GLOB_INT

14271 [ 1] PMREQ [ 2] RACU [ 3] NCEVENT [ 4] NCLOCK [

14272 5] GLOB_LOCK [ 6] MAST_LOCK [ 7] NCS_SPEC [ 8]

14273 NCB_SPEC [ 9] GLOB_EOI [10] NCEOI [11] DROP

14274 */

14275 UINT32 AddrMask : 16;

14276

14277 /* Bits[27:12], Access Type=RWS, default=0x00000000*/

14278

14279 /* Register address mask for addr[15:0] */

14280 UINT32 Rsvd28 : 4;

14281

14282 /* Bits[31:28], Access Type=RO, default=None*/

14283

14284 /* Reserved */

14285

14286 } Bits;

14287

14288 UINT32 Uint32;

14289 UINT64 Uint64;

14290

14291 } MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL1_REGISTER;

14292

14293 /**

14294 Address offset match value for Ubox match/mask. Will compare bits that are not masked

14295 **/

14296 #define MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR 0x0000070D

14297

14298 typedef union {

14299 ///

14300 /// Individual bit fields

14301 ///

14302 struct {

14303 UINT32 AddrMatch : 16;

14304

14305 /* Bits[15:0], Access Type=RWS, default=0x00000000*/

14306

14307 /* Address offset to match */

14308 UINT32 Rsvd16 : 16;

14309

14310 /* Bits[31:16], Access Type=RO, default=None*/

14311

14312 /* Reserved */

14313

14314 } Bits;

14315

14316 UINT32 Uint32;

14317 UINT64 Uint64;

14318

14319 } MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR_REGISTER;

14320 /**

14321 PMON Global Status register.

14322 All fields in this reigster must be reset when LT_CONTROL_MSR[LTPmonCntClr] is set to 1b.

14323 **/

14324 #define MSR_NCUPMONGLSTS1 0x0000070F

14325

14326 /**

14327

14328 **/

14329 #define MSR_PCUPMONUNITCTRL 0x00000710

14330

14331 typedef union {

14332 ///

14333 /// Individual bit fields

14334 ///

14335 struct {

14336 UINT32 Resetcounterconfigs : 1;

14337

14338 /* Bits[0:0], Access Type=WO, default=0x00000000*/

14339

14340 /*

14341 When this bit is written to, the counter

14342 configuration registers will be reset. This does

14343 not effect the values in the counters. This is a

14344 WO register, and writing to this bit will

14345 trigger a reset for 1 cycle only.

14346 */

14347 UINT32 Resetcounters : 1;

14348

14349 /* Bits[1:1], Access Type=WO, default=0x00000000*/

14350

14351 /*

14352 When this bit is written to, the counters data

14353 fields will be reset. The configuration values

14354 will not be reset. This is a WO register, and

14355 writing to this bit will trigger a reset for 1

14356 cycle only.

14357 */

14358 UINT32 Rsvd2 : 6;

14359

14360 /* Bits[7:2], Access Type=RO, default=None*/

14361

14362 /* Reserved */

14363 UINT32 Freezecounters : 1;

14364

14365 /* Bits[8:8], Access Type=RW_V, default=0x00000000*/

14366

14367 /*

14368 This bit is written to when the counters should

14369 be frozen. If this bit is written to and freeze

14370 is enabled, the counters in the unit will stop

14371 counting. To freeze the counters, this bit need

14372 only be set by one of the unit control

14373 registers.

14374 */

14375 UINT32 Rsvd9 : 7;

14376

14377 /* Bits[15:9], Access Type=RO, default=None*/

14378

14379 /* Reserved */

14380 UINT32 Freezeenable : 1;

14381

14382 /* Bits[16:16], Access Type=RW, default=0x00000001*/

14383

14384 /*

14385 This bit controls what the counters in the unit

14386 will do when they receive a freeze signal. When

14387 set, the counters will be allowed to freeze.

14388 When not set, the counters will ignore the

14389 freeze signal. For freeze to be enabled for a

14390 given unit, all of the unit control registers

14391 must have this bit set.

14392 */

14393 UINT32 Overflowenable : 1;

14394

14395 /* Bits[17:17], Access Type=RW, default=0x00000001*/

14396

14397 /*

14398 This bit controls the behavior of counters when

14399 they overflow. When set, the system will trigger

14400 the overflow handling process throughout the

14401 rest of the uncore, potentially triggering a PMI

14402 and freezing counters. When it is not set, the

14403 counters will simply wrap around and continue to

14404 count. For overflow to be enabled for a given

14405 unit, all of the unit control registers must

14406 have this bit set.

14407 */

14408 UINT32 Rsvd18 : 14;

14409

14410 /* Bits[31:18], Access Type=RO, default=None*/

14411

14412 /* Reserved */

14413

14414 } Bits;

14415

14416 UINT32 Uint32;

14417 UINT64 Uint64;

14418

14419 } MSR_PCUPMONUNITCTRL_REGISTER;

14420

14421 /**

14422 Holds the status information and control the operation of the the PMON Fixed Counter.

14423 **/

14424 #define MSR_PCUPMONCNTRCFG_0 0x00000711

14425

14426 typedef union {

14427 ///

14428 /// Individual bit fields

14429 ///

14430 struct {

14431 UINT32 Filtermask : 7;

14432

14433 /* Bits[6:0], Access Type=RW_V, default=0x00000000*/

14434

14435 /*

14436 This field is used to decode the PerfMon event

14437 which is selected. The encodings for each of the

14438 valid UnCore PerfMon events can be found in the

14439 Perfmon HAS and the individual unit HAS

14440 documents.

14441 */

14442 UINT32 Useoccupancy : 1;

14443

14444 /* Bits[7:7], Access Type=WO, default=0x00000000*/

14445

14446 /*

14447 When enabled, this will pass the output of the

14448 occupancy block through to the counter

14449 (dependent on the event occuring). See the HAS

14450 for more details.

14451 */

14452 UINT32 Rsvd8 : 6;

14453

14454 /* Bits[13:8], Access Type=RO, default=None*/

14455

14456 /* Reserved */

14457 UINT32 Occselect : 2;

14458

14459 /* Bits[15:14], Access Type=WO, default=0x00000000*/

14460

14461 /*

14462 Select which of the four occupancy counters to

14463 use. 00 - Threads in C0 01 - Cores in C0 10 -

14464 Cores in C3 11 - Cores in C6

14465 */

14466 UINT32 Rsvd16 : 1;

14467

14468 /* Bits[16:16], Access Type=RO, default=None*/

14469

14470 /* Reserved */

14471 UINT32 Counterreset : 1;

14472

14473 /* Bits[17:17], Access Type=WO, default=0x00000000*/

14474

14475 /*

14476 When this bit is set, the corresponding counter

14477 will be reset to 0. This allows for a quick

14478 reset of the counter when changing event

14479 encodings.

14480 */

14481 UINT32 Edgedetect : 1;

14482

14483 /* Bits[18:18], Access Type=WO, default=0x00000000*/

14484

14485 /*

14486 Edge Detect allows one to count either 0 to 1 or

14487 1 to 0 transitions of a given event. For

14488 example, we have an event that counts the number

14489 of cycles in L0s mode in Intel UPI. By using

14490 edge detect, one can count the number of times

14491 that we entered L0s mode (by detecting the

14492 rising edge). Edge detect only works in

14493 conjunction with threshholding. This is true

14494 even for events that can only increment by 1 in

14495 a given cycle (like the L0s example above). In

14496 this case, one should set a threshhold of 1. One

14497 can also use Edge Detect with queue occupancy

14498 events. For example, if one wanted to count the

14499 number of times when the TOR occupancy was

14500 larger than 5, one would selet the TOR occupancy

14501 event with a threshold of 5 and set the Edge

14502 Detect bit. Edge detect can also be used with

14503 the invert. This is generally not particularly

14504 useful, as the count of falling edges compared

14505 to rising edges will always on differ by 1.

14506 */

14507 UINT32 Tidfilterenable : 1;

14508

14509 /* Bits[19:19], Access Type=WO, default=0x00000000*/

14510

14511 /*

14512 ThreadID filter enable. This is only used by

14513 Cbo. For other units it is Reserved.

14514 */

14515 UINT32 Overflowenable : 1;

14516

14517 /* Bits[20:20], Access Type=WO, default=0x00000000*/

14518

14519 /*

14520 Setting this bit will enable the counter to send

14521 an overflow signal. If this bit is not set, the

14522 counter will wrap around when it overflows

14523 without triggering anything. If this bit is set

14524 and the Units configuration register has

14525 overflow enabled, tehn a signal will be

14526 transmitted to the Ubox

14527 */

14528 UINT32 Internal : 1;

14529

14530 /* Bits[21:21], Access Type=WO, default=0x00000000*/

14531

14532 /*

14533 This bit needs to be asserted if the event which

14534 needs to be selected is an internal event.

14535 Internal events are events that are only

14536 accessible on unlocked parts. One can basically

14537 think of the internal bit as an extension of the

14538 event select bits [7:0], as it allows the use to

14539 gain access to additional events. It will not be

14540 possible to use these events on locked parts.

14541 For perfmons that exist in MSR space, the MSR

14542 write mask is set on this bit, and the ucode

14543 handler will trigger a GP fault if one attempts

14544 to write to these bits. Writing to these bits is

14545 controlled in other ways in the other units.

14546 */

14547 UINT32 Counterenable : 1;

14548

14549 /* Bits[22:22], Access Type=WO, default=0x00000000*/

14550

14551 /*

14552 This field is the local enable for the PerfMon

14553 Counter. This bit must be asserted in order for

14554 the PerfMon counter to begin counting the events

14555 selected by the event select, unit mask, and

14556 internal the events selected by the event

14557 select, unit mask, and internal if this bit is

14558 set to 1 but the Unit Control Registers have

14559 determined that counting is disabled, then the

14560 counter will not count.

14561 */

14562 UINT32 Invert : 1;

14563

14564 /* Bits[23:23], Access Type=WO, default=0x00000000*/

14565

14566 /*

14567 This bit indicates how the threshold field will

14568 be compared to the incoming event. When 0, the

14569 comparison that will be done is threshold >=

14570 event. When set to 1, the comparison that will

14571 be done is inverted from the case where this bit

14572 is set to 0, i.e., threshold event. The invert

14573 bit only works when Threshhold != 0. So, if one

14574 would like to invert a non-occupancy event (like

14575 LLC Hit), one needs to set the threshhold to 1.

14576 */

14577 UINT32 Threshold : 6;

14578

14579 /* Bits[29:24], Access Type=WO, default=0x00000000*/

14580

14581 /*

14582 This field is compared directly against an

14583 incoming event value for events that can

14584 increment by 1 or more in a given cycle. Since

14585 the widest event from the UnCore is 7bits (queue

14586 occupancy), bit 31 is unused. The result of the

14587 comparison is effectively a 1 bit wide event,

14588 i.e., the counter will be incremented by 1 when

14589 the comparison is true (the type of comparison

14590 depends on the setting of the 'invert' bit - see

14591 bit 23 below) no matter how wide the original

14592 event was. When this field is zero, threshold

14593 comparison is disabled and the event is passed

14594 without modification.

14595 */

14596 UINT32 Occinvert : 1;

14597

14598 /* Bits[30:30], Access Type=WO, default=0x00000000*/

14599

14600 /*

14601 Invert the output of the occupancy threshhold

14602 comparison logic. 0 - "greater than or equal to"

14603 comparison on the threshhold compare 1 - "less

14604 than" comparison on the threshhold compare

14605 */

14606 UINT32 Occedgedetect : 1;

14607

14608 /* Bits[31:31], Access Type=WO, default=0x00000000*/

14609

14610 /*

14611 Enable edge detection on the output of the

14612 occupancy threshhold comparison. When enabled

14613 and used with the Threshhold logic, this will

14614 provide the ability to track the number of times

14615 when an occupancy counter exceed or was equal to

14616 the value in the threshhold. When used with

14617 OccInvert, this will track the number of times

14618 when the value dropped below the threshhold.

14619 */

14620

14621 } Bits;

14622

14623 UINT32 Uint32;

14624 UINT64 Uint64;

14625

14626 } MSR_PCUPMONCNTRCFG_0_REGISTER;

14627

14628 /**

14629 Holds the status information and control the operation of the the PMON Fixed Counter.

14630 **/

14631 #define MSR_PCUPMONCNTRCFG_1 0x00000712

14632

14633 typedef union {

14634 ///

14635 /// Individual bit fields

14636 ///

14637 struct {

14638 UINT32 Filtermask : 7;

14639

14640 /* Bits[6:0], Access Type=RW_V, default=0x00000000*/

14641

14642 /*

14643 This field is used to decode the PerfMon event

14644 which is selected. The encodings for each of the

14645 valid UnCore PerfMon events can be found in the

14646 Perfmon HAS and the individual unit HAS

14647 documents.

14648 */

14649 UINT32 Useoccupancy : 1;

14650

14651 /* Bits[7:7], Access Type=WO, default=0x00000000*/

14652

14653 /*

14654 When enabled, this will pass the output of the

14655 occupancy block through to the counter

14656 (dependent on the event occuring). See the HAS

14657 for more details.

14658 */

14659 UINT32 Rsvd8 : 6;

14660

14661 /* Bits[13:8], Access Type=RO, default=None*/

14662

14663 /* Reserved */

14664 UINT32 Occselect : 2;

14665

14666 /* Bits[15:14], Access Type=WO, default=0x00000000*/

14667

14668 /*

14669 Select which of the four occupancy counters to

14670 use. 00 - Threads in C0 01 - Cores in C0 10 -

14671 Cores in C3 11 - Cores in C6

14672 */

14673 UINT32 Rsvd16 : 1;

14674

14675 /* Bits[16:16], Access Type=RO, default=None*/

14676

14677 /* Reserved */

14678 UINT32 Counterreset : 1;

14679

14680 /* Bits[17:17], Access Type=WO, default=0x00000000*/

14681

14682 /*

14683 When this bit is set, the corresponding counter

14684 will be reset to 0. This allows for a quick

14685 reset of the counter when changing event

14686 encodings.

14687 */

14688 UINT32 Edgedetect : 1;

14689

14690 /* Bits[18:18], Access Type=WO, default=0x00000000*/

14691

14692 /*

14693 Edge Detect allows one to count either 0 to 1 or

14694 1 to 0 transitions of a given event. For

14695 example, we have an event that counts the number

14696 of cycles in L0s mode in Intel UPI. By using

14697 edge detect, one can count the number of times

14698 that we entered L0s mode (by detecting the

14699 rising edge). Edge detect only works in

14700 conjunction with threshholding. This is true

14701 even for events that can only increment by 1 in

14702 a given cycle (like the L0s example above). In

14703 this case, one should set a threshhold of 1. One

14704 can also use Edge Detect with queue occupancy

14705 events. For example, if one wanted to count the

14706 number of times when the TOR occupancy was

14707 larger than 5, one would selet the TOR occupancy

14708 event with a threshold of 5 and set the Edge

14709 Detect bit. Edge detect can also be used with

14710 the invert. This is generally not particularly

14711 useful, as the count of falling edges compared

14712 to rising edges will always on differ by 1.

14713 */

14714 UINT32 Tidfilterenable : 1;

14715

14716 /* Bits[19:19], Access Type=WO, default=0x00000000*/

14717

14718 /*

14719 ThreadID filter enable. This is only used by

14720 Cbo. For other units it is Reserved.

14721 */

14722 UINT32 Overflowenable : 1;

14723

14724 /* Bits[20:20], Access Type=WO, default=0x00000000*/

14725

14726 /*

14727 Setting this bit will enable the counter to send

14728 an overflow signal. If this bit is not set, the

14729 counter will wrap around when it overflows

14730 without triggering anything. If this bit is set

14731 and the Units configuration register has

14732 overflow enabled, tehn a signal will be

14733 transmitted to the Ubox

14734 */

14735 UINT32 Internal : 1;

14736

14737 /* Bits[21:21], Access Type=WO, default=0x00000000*/

14738

14739 /*

14740 This bit needs to be asserted if the event which

14741 needs to be selected is an internal event.

14742 Internal events are events that are only

14743 accessible on unlocked parts. One can basically

14744 think of the internal bit as an extension of the

14745 event select bits [7:0], as it allows the use to

14746 gain access to additional events. It will not be

14747 possible to use these events on locked parts.

14748 For perfmons that exist in MSR space, the MSR

14749 write mask is set on this bit, and the ucode

14750 handler will trigger a GP fault if one attempts

14751 to write to these bits. Writing to these bits is

14752 controlled in other ways in the other units.

14753 */

14754 UINT32 Counterenable : 1;

14755

14756 /* Bits[22:22], Access Type=WO, default=0x00000000*/

14757

14758 /*

14759 This field is the local enable for the PerfMon

14760 Counter. This bit must be asserted in order for

14761 the PerfMon counter to begin counting the events

14762 selected by the event select, unit mask, and

14763 internal the events selected by the event

14764 select, unit mask, and internal if this bit is

14765 set to 1 but the Unit Control Registers have

14766 determined that counting is disabled, then the

14767 counter will not count.

14768 */

14769 UINT32 Invert : 1;

14770

14771 /* Bits[23:23], Access Type=WO, default=0x00000000*/

14772

14773 /*

14774 This bit indicates how the threshold field will

14775 be compared to the incoming event. When 0, the

14776 comparison that will be done is threshold >=

14777 event. When set to 1, the comparison that will

14778 be done is inverted from the case where this bit

14779 is set to 0, i.e., threshold event. The invert

14780 bit only works when Threshhold != 0. So, if one

14781 would like to invert a non-occupancy event (like

14782 LLC Hit), one needs to set the threshhold to 1.

14783 */

14784 UINT32 Threshold : 6;

14785

14786 /* Bits[29:24], Access Type=WO, default=0x00000000*/

14787

14788 /*

14789 This field is compared directly against an

14790 incoming event value for events that can

14791 increment by 1 or more in a given cycle. Since

14792 the widest event from the UnCore is 7bits (queue

14793 occupancy), bit 31 is unused. The result of the

14794 comparison is effectively a 1 bit wide event,

14795 i.e., the counter will be incremented by 1 when

14796 the comparison is true (the type of comparison

14797 depends on the setting of the 'invert' bit - see

14798 bit 23 below) no matter how wide the original

14799 event was. When this field is zero, threshold

14800 comparison is disabled and the event is passed

14801 without modification.

14802 */

14803 UINT32 Occinvert : 1;

14804

14805 /* Bits[30:30], Access Type=WO, default=0x00000000*/

14806

14807 /*

14808 Invert the output of the occupancy threshhold

14809 comparison logic. 0 - "greater than or equal to"

14810 comparison on the threshhold compare 1 - "less

14811 than" comparison on the threshhold compare

14812 */

14813 UINT32 Occedgedetect : 1;

14814

14815 /* Bits[31:31], Access Type=WO, default=0x00000000*/

14816

14817 /*

14818 Enable edge detection on the output of the

14819 occupancy threshhold comparison. When enabled

14820 and used with the Threshhold logic, this will

14821 provide the ability to track the number of times

14822 when an occupancy counter exceed or was equal to

14823 the value in the threshhold. When used with

14824 OccInvert, this will track the number of times

14825 when the value dropped below the threshhold.

14826 */

14827

14828 } Bits;

14829

14830 UINT32 Uint32;

14831 UINT64 Uint64;

14832

14833 } MSR_PCUPMONCNTRCFG_1_REGISTER;

14834

14835 /**

14836 Holds the status information and control the operation of the the PMON Fixed Counter.

14837 **/

14838 #define MSR_PCUPMONCNTRCFG_2 0x00000713

14839

14840 typedef union {

14841 ///

14842 /// Individual bit fields

14843 ///

14844 struct {

14845 UINT32 Filtermask : 7;

14846

14847 /* Bits[6:0], Access Type=RW_V, default=0x00000000*/

14848

14849 /*

14850 This field is used to decode the PerfMon event

14851 which is selected. The encodings for each of the

14852 valid UnCore PerfMon events can be found in the

14853 Perfmon HAS and the individual unit HAS

14854 documents.

14855 */

14856 UINT32 Useoccupancy : 1;

14857

14858 /* Bits[7:7], Access Type=WO, default=0x00000000*/

14859

14860 /*

14861 When enabled, this will pass the output of the

14862 occupancy block through to the counter

14863 (dependent on the event occuring). See the HAS

14864 for more details.

14865 */

14866 UINT32 Rsvd8 : 6;

14867

14868 /* Bits[13:8], Access Type=RO, default=None*/

14869

14870 /* Reserved */

14871 UINT32 Occselect : 2;

14872

14873 /* Bits[15:14], Access Type=WO, default=0x00000000*/

14874

14875 /*

14876 Select which of the four occupancy counters to

14877 use. 00 - Threads in C0 01 - Cores in C0 10 -

14878 Cores in C3 11 - Cores in C6

14879 */

14880 UINT32 Rsvd16 : 1;

14881

14882 /* Bits[16:16], Access Type=RO, default=None*/

14883

14884 /* Reserved */

14885 UINT32 Counterreset : 1;

14886

14887 /* Bits[17:17], Access Type=WO, default=0x00000000*/

14888

14889 /*

14890 When this bit is set, the corresponding counter

14891 will be reset to 0. This allows for a quick

14892 reset of the counter when changing event

14893 encodings.

14894 */

14895 UINT32 Edgedetect : 1;

14896

14897 /* Bits[18:18], Access Type=WO, default=0x00000000*/

14898

14899 /*

14900 Edge Detect allows one to count either 0 to 1 or

14901 1 to 0 transitions of a given event. For

14902 example, we have an event that counts the number

14903 of cycles in L0s mode in Intel UPI. By using

14904 edge detect, one can count the number of times

14905 that we entered L0s mode (by detecting the

14906 rising edge). Edge detect only works in

14907 conjunction with threshholding. This is true

14908 even for events that can only increment by 1 in

14909 a given cycle (like the L0s example above). In

14910 this case, one should set a threshhold of 1. One

14911 can also use Edge Detect with queue occupancy

14912 events. For example, if one wanted to count the

14913 number of times when the TOR occupancy was

14914 larger than 5, one would selet the TOR occupancy

14915 event with a threshold of 5 and set the Edge

14916 Detect bit. Edge detect can also be used with

14917 the invert. This is generally not particularly

14918 useful, as the count of falling edges compared

14919 to rising edges will always on differ by 1.

14920 */

14921 UINT32 Tidfilterenable : 1;

14922

14923 /* Bits[19:19], Access Type=WO, default=0x00000000*/

14924

14925 /*

14926 ThreadID filter enable. This is only used by

14927 Cbo. For other units it is Reserved.

14928 */

14929 UINT32 Overflowenable : 1;

14930

14931 /* Bits[20:20], Access Type=WO, default=0x00000000*/

14932

14933 /*

14934 Setting this bit will enable the counter to send

14935 an overflow signal. If this bit is not set, the

14936 counter will wrap around when it overflows

14937 without triggering anything. If this bit is set

14938 and the Units configuration register has

14939 overflow enabled, tehn a signal will be

14940 transmitted to the Ubox

14941 */

14942 UINT32 Internal : 1;

14943

14944 /* Bits[21:21], Access Type=WO, default=0x00000000*/

14945

14946 /*

14947 This bit needs to be asserted if the event which

14948 needs to be selected is an internal event.

14949 Internal events are events that are only

14950 accessible on unlocked parts. One can basically

14951 think of the internal bit as an extension of the

14952 event select bits [7:0], as it allows the use to

14953 gain access to additional events. It will not be

14954 possible to use these events on locked parts.

14955 For perfmons that exist in MSR space, the MSR

14956 write mask is set on this bit, and the ucode

14957 handler will trigger a GP fault if one attempts

14958 to write to these bits. Writing to these bits is

14959 controlled in other ways in the other units.

14960 */

14961 UINT32 Counterenable : 1;

14962

14963 /* Bits[22:22], Access Type=WO, default=0x00000000*/

14964

14965 /*

14966 This field is the local enable for the PerfMon

14967 Counter. This bit must be asserted in order for

14968 the PerfMon counter to begin counting the events

14969 selected by the event select, unit mask, and

14970 internal the events selected by the event

14971 select, unit mask, and internal if this bit is

14972 set to 1 but the Unit Control Registers have

14973 determined that counting is disabled, then the

14974 counter will not count.

14975 */

14976 UINT32 Invert : 1;

14977

14978 /* Bits[23:23], Access Type=WO, default=0x00000000*/

14979

14980 /*

14981 This bit indicates how the threshold field will

14982 be compared to the incoming event. When 0, the

14983 comparison that will be done is threshold >=

14984 event. When set to 1, the comparison that will

14985 be done is inverted from the case where this bit

14986 is set to 0, i.e., threshold event. The invert

14987 bit only works when Threshhold != 0. So, if one

14988 would like to invert a non-occupancy event (like

14989 LLC Hit), one needs to set the threshhold to 1.

14990 */

14991 UINT32 Threshold : 6;

14992

14993 /* Bits[29:24], Access Type=WO, default=0x00000000*/

14994

14995 /*

14996 This field is compared directly against an

14997 incoming event value for events that can

14998 increment by 1 or more in a given cycle. Since

14999 the widest event from the UnCore is 7bits (queue

15000 occupancy), bit 31 is unused. The result of the

15001 comparison is effectively a 1 bit wide event,

15002 i.e., the counter will be incremented by 1 when

15003 the comparison is true (the type of comparison

15004 depends on the setting of the 'invert' bit - see

15005 bit 23 below) no matter how wide the original

15006 event was. When this field is zero, threshold

15007 comparison is disabled and the event is passed

15008 without modification.

15009 */

15010 UINT32 Occinvert : 1;

15011

15012 /* Bits[30:30], Access Type=WO, default=0x00000000*/

15013

15014 /*

15015 Invert the output of the occupancy threshhold

15016 comparison logic. 0 - "greater than or equal to"

15017 comparison on the threshhold compare 1 - "less

15018 than" comparison on the threshhold compare

15019 */

15020 UINT32 Occedgedetect : 1;

15021

15022 /* Bits[31:31], Access Type=WO, default=0x00000000*/

15023

15024 /*

15025 Enable edge detection on the output of the

15026 occupancy threshhold comparison. When enabled

15027 and used with the Threshhold logic, this will

15028 provide the ability to track the number of times

15029 when an occupancy counter exceed or was equal to

15030 the value in the threshhold. When used with

15031 OccInvert, this will track the number of times

15032 when the value dropped below the threshhold.

15033 */

15034

15035 } Bits;

15036

15037 UINT32 Uint32;

15038 UINT64 Uint64;

15039

15040 } MSR_PCUPMONCNTRCFG_2_REGISTER;

15041

15042 /**

15043 Holds the status information and control the operation of the the PMON Fixed Counter.

15044 **/

15045 #define MSR_PCUPMONCNTRCFG_3 0x00000714

15046

15047 typedef union {

15048 ///

15049 /// Individual bit fields

15050 ///

15051 struct {

15052 UINT32 Filtermask : 7;

15053

15054 /* Bits[6:0], Access Type=RW_V, default=0x00000000*/

15055

15056 /*

15057 This field is used to decode the PerfMon event

15058 which is selected. The encodings for each of the

15059 valid UnCore PerfMon events can be found in the

15060 Perfmon HAS and the individual unit HAS

15061 documents.

15062 */

15063 UINT32 Useoccupancy : 1;

15064

15065 /* Bits[7:7], Access Type=WO, default=0x00000000*/

15066

15067 /*

15068 When enabled, this will pass the output of the

15069 occupancy block through to the counter

15070 (dependent on the event occuring). See the HAS

15071 for more details.

15072 */

15073 UINT32 Rsvd8 : 6;

15074

15075 /* Bits[13:8], Access Type=RO, default=None*/

15076

15077 /* Reserved */

15078 UINT32 Occselect : 2;

15079

15080 /* Bits[15:14], Access Type=WO, default=0x00000000*/

15081

15082 /*

15083 Select which of the four occupancy counters to

15084 use. 00 - Threads in C0 01 - Cores in C0 10 -

15085 Cores in C3 11 - Cores in C6

15086 */

15087 UINT32 Rsvd16 : 1;

15088

15089 /* Bits[16:16], Access Type=RO, default=None*/

15090

15091 /* Reserved */

15092 UINT32 Counterreset : 1;

15093

15094 /* Bits[17:17], Access Type=WO, default=0x00000000*/

15095

15096 /*

15097 When this bit is set, the corresponding counter

15098 will be reset to 0. This allows for a quick

15099 reset of the counter when changing event

15100 encodings.

15101 */

15102 UINT32 Edgedetect : 1;

15103

15104 /* Bits[18:18], Access Type=WO, default=0x00000000*/

15105

15106 /*

15107 Edge Detect allows one to count either 0 to 1 or

15108 1 to 0 transitions of a given event. For

15109 example, we have an event that counts the number

15110 of cycles in L0s mode in Intel UPI. By using

15111 edge detect, one can count the number of times

15112 that we entered L0s mode (by detecting the

15113 rising edge). Edge detect only works in

15114 conjunction with threshholding. This is true

15115 even for events that can only increment by 1 in

15116 a given cycle (like the L0s example above). In

15117 this case, one should set a threshhold of 1. One

15118 can also use Edge Detect with queue occupancy

15119 events. For example, if one wanted to count the

15120 number of times when the TOR occupancy was

15121 larger than 5, one would selet the TOR occupancy

15122 event with a threshold of 5 and set the Edge

15123 Detect bit. Edge detect can also be used with

15124 the invert. This is generally not particularly

15125 useful, as the count of falling edges compared

15126 to rising edges will always on differ by 1.

15127 */

15128 UINT32 Tidfilterenable : 1;

15129

15130 /* Bits[19:19], Access Type=WO, default=0x00000000*/

15131

15132 /*

15133 ThreadID filter enable. This is only used by

15134 Cbo. For other units it is Reserved.

15135 */

15136 UINT32 Overflowenable : 1;

15137

15138 /* Bits[20:20], Access Type=WO, default=0x00000000*/

15139

15140 /*

15141 Setting this bit will enable the counter to send

15142 an overflow signal. If this bit is not set, the

15143 counter will wrap around when it overflows

15144 without triggering anything. If this bit is set

15145 and the Units configuration register has

15146 overflow enabled, tehn a signal will be

15147 transmitted to the Ubox

15148 */

15149 UINT32 Internal : 1;

15150

15151 /* Bits[21:21], Access Type=WO, default=0x00000000*/

15152

15153 /*

15154 This bit needs to be asserted if the event which

15155 needs to be selected is an internal event.

15156 Internal events are events that are only

15157 accessible on unlocked parts. One can basically

15158 think of the internal bit as an extension of the

15159 event select bits [7:0], as it allows the use to

15160 gain access to additional events. It will not be

15161 possible to use these events on locked parts.

15162 For perfmons that exist in MSR space, the MSR

15163 write mask is set on this bit, and the ucode

15164 handler will trigger a GP fault if one attempts

15165 to write to these bits. Writing to these bits is

15166 controlled in other ways in the other units.

15167 */

15168 UINT32 Counterenable : 1;

15169

15170 /* Bits[22:22], Access Type=WO, default=0x00000000*/

15171

15172 /*

15173 This field is the local enable for the PerfMon

15174 Counter. This bit must be asserted in order for

15175 the PerfMon counter to begin counting the events

15176 selected by the event select, unit mask, and

15177 internal the events selected by the event

15178 select, unit mask, and internal if this bit is

15179 set to 1 but the Unit Control Registers have

15180 determined that counting is disabled, then the

15181 counter will not count.

15182 */

15183 UINT32 Invert : 1;

15184

15185 /* Bits[23:23], Access Type=WO, default=0x00000000*/

15186

15187 /*

15188 This bit indicates how the threshold field will

15189 be compared to the incoming event. When 0, the

15190 comparison that will be done is threshold >=

15191 event. When set to 1, the comparison that will

15192 be done is inverted from the case where this bit

15193 is set to 0, i.e., threshold event. The invert

15194 bit only works when Threshhold != 0. So, if one

15195 would like to invert a non-occupancy event (like

15196 LLC Hit), one needs to set the threshhold to 1.

15197 */

15198 UINT32 Threshold : 6;

15199

15200 /* Bits[29:24], Access Type=WO, default=0x00000000*/

15201

15202 /*

15203 This field is compared directly against an

15204 incoming event value for events that can

15205 increment by 1 or more in a given cycle. Since

15206 the widest event from the UnCore is 7bits (queue

15207 occupancy), bit 31 is unused. The result of the

15208 comparison is effectively a 1 bit wide event,

15209 i.e., the counter will be incremented by 1 when

15210 the comparison is true (the type of comparison

15211 depends on the setting of the 'invert' bit - see

15212 bit 23 below) no matter how wide the original

15213 event was. When this field is zero, threshold

15214 comparison is disabled and the event is passed

15215 without modification.

15216 */

15217 UINT32 Occinvert : 1;

15218

15219 /* Bits[30:30], Access Type=WO, default=0x00000000*/

15220

15221 /*

15222 Invert the output of the occupancy threshhold

15223 comparison logic. 0 - "greater than or equal to"

15224 comparison on the threshhold compare 1 - "less

15225 than" comparison on the threshhold compare

15226 */

15227 UINT32 Occedgedetect : 1;

15228

15229 /* Bits[31:31], Access Type=WO, default=0x00000000*/

15230

15231 /*

15232 Enable edge detection on the output of the

15233 occupancy threshhold comparison. When enabled

15234 and used with the Threshhold logic, this will

15235 provide the ability to track the number of times

15236 when an occupancy counter exceed or was equal to

15237 the value in the threshhold. When used with

15238 OccInvert, this will track the number of times

15239 when the value dropped below the threshhold.

15240 */

15241

15242 } Bits;

15243

15244 UINT32 Uint32;

15245 UINT64 Uint64;

15246

15247 } MSR_PCUPMONCNTRCFG_3_REGISTER;

15248 /**

15249

15250 **/

15251 #define MSR_PCUPMONFILTER 0x00000715

15252

15253 /**

15254

15255 **/

15256 #define MSR_PCUPMONUNITSTATUS 0x00000716

15257

15258 typedef union {

15259 ///

15260 /// Individual bit fields

15261 ///

15262 struct {

15263 UINT32 Counteroverflowbitmask : 7;

15264

15265 /* Bits[6:0], Access Type=WO, default=0x00000000*/

15266

15267 /*

15268 This bitmask that specifies which counter(or

15269 counters have overflowed. If the unit has a

15270 fixed counter, it's corresponding bitmask will

15271 be stored at position 0.

15272 */

15273 UINT32 Rsvd7 : 25;

15274

15275 /* Bits[31:7], Access Type=RO, default=None*/

15276

15277 /* Reserved */

15278

15279 } Bits;

15280

15281 UINT32 Uint32;

15282 UINT64 Uint64;

15283

15284 } MSR_PCUPMONUNITSTATUS_REGISTER;

15285

15286 /**

15287 Holds the status information and control the operation of the the PMON Fixed Counter.

15288 **/

15289 #define MSR_PCUPMONCNTR_0 0x00000717

15290

15291 typedef union {

15292 ///

15293 /// Individual bit fields

15294 ///

15295 struct {

15296 UINT32 Countervalue0 : 32;

15297

15298 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

15299

15300 /* The value of the counter */

15301 UINT32 Countervalue1 : 16;

15302

15303 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

15304

15305 /* The value of the counter */

15306 UINT32 Rsvd48 : 16;

15307

15308 /* Bits[63:48], Access Type=RO, default=None*/

15309

15310 /* Reserved */

15311

15312 } Bits;

15313

15314 UINT32 Uint32;

15315 UINT64 Uint64;

15316

15317 } MSR_PCUPMONCNTR_0_REGISTER;

15318

15319 /**

15320 Holds the status information and control the operation of the the PMON Fixed Counter.

15321 **/

15322 #define MSR_PCUPMONCNTR_1 0x00000718

15323

15324 typedef union {

15325 ///

15326 /// Individual bit fields

15327 ///

15328 struct {

15329 UINT32 Countervalue0 : 32;

15330

15331 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

15332

15333 /* The value of the counter */

15334 UINT32 Countervalue1 : 16;

15335

15336 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

15337

15338 /* The value of the counter */

15339 UINT32 Rsvd48 : 16;

15340

15341 /* Bits[63:48], Access Type=RO, default=None*/

15342

15343 /* Reserved */

15344

15345 } Bits;

15346

15347 UINT32 Uint32;

15348 UINT64 Uint64;

15349

15350 } MSR_PCUPMONCNTR_1_REGISTER;

15351

15352 /**

15353 Holds the status information and control the operation of the the PMON Fixed Counter.

15354 **/

15355 #define MSR_PCUPMONCNTR_2 0x00000719

15356

15357 typedef union {

15358 ///

15359 /// Individual bit fields

15360 ///

15361 struct {

15362 UINT32 Countervalue0 : 32;

15363

15364 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

15365

15366 /* The value of the counter */

15367 UINT32 Countervalue1 : 16;

15368

15369 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

15370

15371 /* The value of the counter */

15372 UINT32 Rsvd48 : 16;

15373

15374 /* Bits[63:48], Access Type=RO, default=None*/

15375

15376 /* Reserved */

15377

15378 } Bits;

15379

15380 UINT32 Uint32;

15381 UINT64 Uint64;

15382

15383 } MSR_PCUPMONCNTR_2_REGISTER;

15384

15385 /**

15386 Holds the status information and control the operation of the the PMON Fixed Counter.

15387 **/

15388 #define MSR_PCUPMONCNTR_3 0x0000071A

15389

15390 typedef union {

15391 ///

15392 /// Individual bit fields

15393 ///

15394 struct {

15395 UINT32 Countervalue0 : 32;

15396

15397 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

15398

15399 /* The value of the counter */

15400 UINT32 Countervalue1 : 16;

15401

15402 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

15403

15404 /* The value of the counter */

15405 UINT32 Rsvd48 : 16;

15406

15407 /* Bits[63:48], Access Type=RO, default=None*/

15408

15409 /* Reserved */

15410

15411 } Bits;

15412

15413 UINT32 Uint32;

15414 UINT64 Uint64;

15415

15416 } MSR_PCUPMONCNTR_3_REGISTER;

15417 /**

15418 Spare Virtual MSRs in uncore Creg PLA

15419 **/

15420 #define MSR_RESIDENCY_CTR_SELECT 0x0000071B

15421 /**

15422 Spare Virtual MSRs in uncore Creg PLA

15423 **/

15424 #define MSR_RESIDENCY_CTR_CONFIG 0x0000071C

15425 /**

15426 Spare Virtual MSRs in uncore Creg PLA

15427 **/

15428 #define MSR_RESIDENCY_CTR 0x0000071D

15429

15430 #if 0 // Duplicate with ArchitecturalMsr.h in EDK2.

15431 /**

15432 Contains enable bits for HWP feature

15433 **/

15434 #define MSR_IA32_PM_ENABLE 0x00000770

15435

15436 typedef union {

15437 ///

15438 /// Individual bit fields

15439 ///

15440 struct {

15441 UINT32 HwpEnable : 1;

15442

15443 /* Bits[0:0], Access Type=RW_KL, default=0x00000000*/

15444

15445 /*

15446 Software sets this bit to enable HWP with

15447 autonomous selection. When set, the processor

15448 will disregard input from the legacy performance

15449 control interface (IA32_PERF_CTL). Note this bit

15450 can only be enabled once from the default value.

15451 Once set, writes to the HWP_ENABLE bit are

15452 ignored. Only RESET will clear this bit. Default

15453 = zero (0).

15454 */

15455 UINT32 Rsvd1 : 31;

15456

15457 /* Bits[31:1], Access Type=RO, default=None*/

15458

15459 /* Reserved */

15460

15461 } Bits;

15462

15463 UINT32 Uint32;

15464 UINT64 Uint64;

15465

15466 } MSR_IA32_PM_ENABLE_REGISTER;

15467 #endif

15468

15469 #if 0 // Duplicate with ArchitecturalMsr.h in EDK2.

15470 /**

15471 Contains fields describing the performance and window time borders in which HWP works.

15472 **/

15473 #define MSR_IA32_HWP_CAPABILITIES 0x00000771

15474

15475 typedef union {

15476 ///

15477 /// Individual bit fields

15478 ///

15479 struct {

15480 UINT32 HighestPerformance : 8;

15481

15482 /* Bits[7:0], Access Type=RW_L, default=0x00000000*/

15483

15484 /*

15485 Value for the maximum non-guaranteed performance

15486 level. This value can change dynamically dueover

15487 clocking S/W support

15488 */

15489 UINT32 GuaranteedPerformance : 8;

15490

15491 /* Bits[15:8], Access Type=RW_L, default=0x00000001*/

15492

15493 /*

15494 Current value for the guaranteed performance

15495 level. This value can change dynamically as a

15496 result of Config TDP setting

15497 */

15498 UINT32 MostEfficientPerformance : 8;

15499

15500 /* Bits[23:16], Access Type=RW_L, default=0x00000000*/

15501

15502 /*

15503 Current value of the most efficient performance

15504 level. This value can change dynamically as a

15505 result of workload characteristics.

15506 */

15507 UINT32 LowestLinearPerformance : 8;

15508

15509 /* Bits[31:24], Access Type=RW_L, default=0x00000001*/

15510

15511 /*

15512 Value for the lowest performance level that

15513 software can program to IA32_HWP_REQUEST.

15514 */

15515

15516 } Bits;

15517

15518 UINT32 Uint32;

15519 UINT64 Uint64;

15520

15521 } MSR_IA32_HWP_CAPABILITIES_REGISTER;

15522 #endif

15523

15524 #if 0 // Duplicate with ArchitecturalMsr.h in EDK2.

15525 /**

15526 Contains bits describing the current status of HWP feature work process

15527 **/

15528 #define MSR_IA32_HWP_INTERRUPT 0x00000773

15529

15530 typedef union {

15531 ///

15532 /// Individual bit fields

15533 ///

15534 struct {

15535 UINT32 ChangeToGuaranteed : 1;

15536

15537 /* Bits[0:0], Access Type=RW, default=0x00000000*/

15538

15539 /*

15540 When set (1), an HWP Interrupt will be generated

15541 whenever a change to the Guaranteed Performance

15542 occurs. Default = interrupt disabled (0).

15543 */

15544 UINT32 ExcursionToMinimum : 1;

15545

15546 /* Bits[1:1], Access Type=RW, default=0x00000000*/

15547

15548 /*

15549 When set (1), an HWP Interrupt will be generated

15550 whenever HW is unable to meet the Minimum

15551 Performance. Default = interrupt disabled (0).

15552 */

15553 UINT32 ChangeToHighest : 1;

15554

15555 /* Bits[2:2], Access Type=RW, default=0x00000000*/

15556

15557 /*

15558 When set (1), an HWP Interrupt will be generated

15559 whenever a change to the Highest Performance

15560 occurs. Default = interrupt disabled (0).

15561 */

15562 UINT32 PeciOverride : 1;

15563

15564 /* Bits[3:3], Access Type=RW, default=0x00000000*/

15565

15566 /*

15567 When set(1), an HWP interrupt will be generated

15568 whenever a management controller supersedes one

15569 or more of the OS control hints (min, max, EPP)

15570 specified in IA32_HWP_REQUEST or

15571 IA32_HWP_REQUEST_PKG

15572 */

15573 UINT32 Rsvd4 : 28;

15574

15575 /* Bits[31:4], Access Type=RO, default=None*/

15576

15577 /* Reserved */

15578

15579 } Bits;

15580

15581 UINT32 Uint32;

15582 UINT64 Uint64;

15583

15584 } MSR_IA32_HWP_INTERRUPT_REGISTER;

15585 #endif

15586

15587 #if 0 // Duplicate with ArchitecturalMsr.h in EDK2.

15588 /**

15589 Power Management Control Hints to a Logical Processor

15590 **/

15591 #define MSR_IA32_HWP_REQUEST 0x00000774

15592

15593 typedef union {

15594 ///

15595 /// Individual bit fields

15596 ///

15597 struct {

15598 UINT32 MinimumPerformance : 8;

15599

15600 /* Bits[7:0], Access Type=RW, default=0x00000001*/

15601

15602 /*

15603 Conveys a hint to the HWP hardware. The OS

15604 programs the minimum performance hint to achieve

15605 the required quality of service (QOS) or to meet

15606 a service level agreement (SLA) as needed. Note

15607 that an excursion below the level specified is

15608 possible due to hardware constraints. The

15609 default value of this field is

15610 IA32_HWP_CAPABILITIES.Lowest_Performance.

15611 */

15612 UINT32 MaximumPerformance : 8;

15613

15614 /* Bits[15:8], Access Type=RW, default=0x000000FF*/

15615

15616 /*

15617 Conveys a hint to the HWP hardware. The OS

15618 programs this field to limit the maximum

15619 performance that is expected to be supplied by

15620 the HWP hardware. Excursions above the limit

15621 requested by OS are possible due to hardware

15622 coordination between the processor cores and

15623 other components in the package. The default

15624 value of this field is

15625 IA32_HWP_CAPABILITIES.Highest_Performance.

15626 */

15627 UINT32 DesiredPerformance : 8;

15628

15629 /* Bits[23:16], Access Type=RW, default=0x00000000*/

15630

15631 /*

15632 Conveys a hint to the HWP hardware. When set to

15633 zero, hardware autonomous selection determines

15634 the performance target. When set to a non-zero

15635 value (between the range of Lowest_Performance

15636 and Highest_Performance of

15637 IA32_HWP_CAPABILITIES) conveys an explicit

15638 performance request hint to the hardware;

15639 effectively disabling HW Autonomous selection.

15640 The Desired_Performance input is non-

15641 constraining in terms of Performance and Energy

15642 Efficiency optimizations, which are

15643 independently controlled. The default value of

15644 this field is 0.

15645 */

15646 UINT32 EnergyPerformancePreference : 8;

15647

15648 /* Bits[31:24], Access Type=RW, default=0x00000080*/

15649

15650 /*

15651 Conveys a hint to the HWP hardware. The OS may

15652 write a range of values from 0 (performance

15653 preference) to 0FFH (energy efficiency

15654 preference) to influence the rate of performance

15655 increase /decrease and the result of the

15656 hardware's energy efficiency and performance

15657 optimizations. The default value of this field

15658 is 80H. Note: If CPUID.06H:EAX[bit 10] indicates

15659 that this field is not supported, HWP uses the

15660 value of the IA32_ENERGY_PERF_BIAS MSR to

15661 determine the energy efficiency / performance

15662 preference.

15663 */

15664 UINT32 ActivityWindow : 10;

15665

15666 /* Bits[41:32], Access Type=RW, default=0x00000000*/

15667

15668 /*

15669 Conveys a hint to the HWP hardware specifying a

15670 moving workload history observation window for

15671 performance/frequency optimizations. If 0, the

15672 hardware will determine the appropriate window

15673 size. When writing a non-zero value to this

15674 field, this field is encoded in the format of

15675 bits 38:32 as a 7-bit mantissa and bits 41:39 as

15676 a 3-bit exponent value in powers of 10. The

15677 resultant value is in microseconds. Thus, the

15678 minimal/maximum activity window size is 1

15679 microsecond/1270 seconds. Combined with the

15680 Energy_Performance_Preference input,

15681 Activity_Window influences the rate of

15682 performance increase / decrease. This non-zero

15683 hint only has meaning when Desired_Performance =

15684 0. The default value of this field is 0

15685 */

15686 UINT32 PackageControl : 1;

15687

15688 /* Bits[42:42], Access Type=RW, default=0x00000000*/

15689

15690 /*

15691 When set causes thread IA32_HWP_REQUEST control

15692 inputs to be derived from IA32_HWP_REQUEST_PKG

15693 */

15694 UINT32 Rsvd43 : 16;

15695

15696 /* Bits[58:43], Access Type=RO, default=0x00000000*/

15697

15698 /* Reserved Bits */

15699 UINT32 ActivityWindowsValid : 1;

15700

15701 /* Bits[59:59], Access Type=RW, default=0x00000000*/

15702

15703 /*

15704 When set 1 means that if the package control bit

15705 is set, takes active windows value from this MSR

15706 */

15707 UINT32 EppValid : 1;

15708

15709 /* Bits[60:60], Access Type=RW, default=0x00000000*/

15710

15711 /*

15712 When set 1 means that if the package control bit

15713 is set, takes EPP value from the the this MSR

15714 */

15715 UINT32 DesiredValid : 1;

15716

15717 /* Bits[61:61], Access Type=RW, default=0x00000000*/

15718

15719 /*

15720 When set 1 means that if the package control bit

15721 is set, takes Desired Performance value from the

15722 the this MSR

15723 */

15724 UINT32 MaximumValid : 1;

15725

15726 /* Bits[62:62], Access Type=RW, default=0x00000000*/

15727

15728 /*

15729 When set 1 means that if the package control bit

15730 is set, takes Maximum Performance value from the

15731 the this MSR

15732 */

15733 UINT32 MinimumValid : 1;

15734

15735 /* Bits[63:63], Access Type=RW, default=0x00000000*/

15736

15737 /*

15738 When set 1 means that if the package control bit

15739 is set, takes Minimum Performance value from the

15740 the this MSR

15741 */

15742

15743 } Bits;

15744

15745 UINT32 Uint32;

15746 UINT64 Uint64;

15747

15748 } MSR_IA32_HWP_REQUEST_REGISTER;

15749 #endif

15750

15751 #if 0 // Duplicate with ArchitecturalMsr.h in EDK2.

15752 /**

15753 Contains bits describing the current status of HWP feature work process

15754 **/

15755 #define MSR_IA32_HWP_STATUS 0x00000777

15756

15757 typedef union {

15758 ///

15759 /// Individual bit fields

15760 ///

15761 struct {

15762 UINT32 ChangeToGuaranteed : 1;

15763

15764 /* Bits[0:0], Access Type=RW0C_FW, default=0x00000000*/

15765

15766 /*

15767 If set (1), a change to Guaranteed Performance

15768 has occurred. SW should query

15769 IA32_HWP_CAPABILITIES to ascertain the new

15770 Guaranteed Performance value. SW must clear this

15771 bit by writing a zero (0).

15772 */

15773 UINT32 Rsvd1 : 1;

15774

15775 /* Bits[1:1], Access Type=RO, default=None*/

15776

15777 /* Reserved */

15778 UINT32 ExcursionToMinimum : 1;

15779

15780 /* Bits[2:2], Access Type=RW0C_FW, default=0x00000000*/

15781

15782 /*

15783 If set (1), an excursion to Minimum Performance

15784 has occurred. SW must clear this bit by writing

15785 a zero (0).

15786 */

15787 UINT32 HighestChange : 1;

15788

15789 /* Bits[3:3], Access Type=RW0C_FW, default=0x00000000*/

15790

15791 /*

15792 If set (1), a change to Highest Performance has

15793 occurred. SW should query IA32_HWP_CAPABILITIES

15794 to ascertain the new Highest Performance value.

15795 SW must clear this bit by writing a zero (0).

15796 */

15797 UINT32 PeciOverrideEnter : 1;

15798

15799 /* Bits[4:4], Access Type=RW0C_FW, default=0x00000000*/

15800

15801 /*

15802 If set (1), a management controller has started

15803 a PECI override of one or more OS control hints

15804 (min, max, EPP) specified in IA32_HWP_REQUEST or

15805 IA32_HWP_REQUEST_PKG. SW must clear this bit

15806 */

15807 UINT32 PeciOverrideExit : 1;

15808

15809 /* Bits[5:5], Access Type=RW0C_FW, default=0x00000000*/

15810

15811 /*

15812 If set (1), a management controller has stopped

15813 a PECI override of all OS control hints (min,

15814 max, EPP) specified in IA32_HWP_REQUEST or

15815 IA32_HWP_REQUEST_PKG. SW must clear this bit by

15816 writing a zero (0).

15817 */

15818 UINT32 Rsvd6 : 26;

15819

15820 /* Bits[31:6], Access Type=RO, default=None*/

15821

15822 /* Reserved */

15823

15824 } Bits;

15825

15826 UINT32 Uint32;

15827 UINT64 Uint64;

15828

15829 } MSR_IA32_HWP_STATUS_REGISTER;

15830 #endif

15831

15832 /**

15833 This MSR will write the ERRINJLCK bit of IIO, QPI, CBO, MC

15834 **/

15835 #define MSR_ERR_INJ_LCK_UNLOCK_CTL 0x00000790

15836

15837 typedef union {

15838 ///

15839 /// Individual bit fields

15840 ///

15841 struct {

15842 UINT32 ErrInjLckUnlock : 1;

15843

15844 /* Bits[0:0], Access Type=RW, default=0x00000001*/

15845

15846 /*

15847 Bit indicates if error injection is enabled 0 -

15848 unlocked 1 - locked (not enabled). note that

15849 this field actually not used by ucode

15850 */

15851 UINT32 Rsvd1 : 31;

15852

15853 /* Bits[31:1], Access Type=RO, default=None*/

15854

15855 /* Reserved */

15856

15857 } Bits;

15858

15859 UINT32 Uint32;

15860 UINT64 Uint64;

15861

15862 } MSR_ERR_INJ_LCK_UNLOCK_CTL_REGISTER;

15863 /**

15864 Spare Virtual MSRs in uncore Creg PLA

15865 " seq has 2 instances in addresses range 0x791 to 0x792"

15866 **/

15867 #define MSR_UNCORE_SPARE_0_0 0x00000791

15868 /**

15869 Spare Virtual MSRs in uncore Creg PLA

15870 " seq has 2 instances in addresses range 0x791 to 0x792"

15871 **/

15872 #define MSR_UNCORE_SPARE_1_1 0x00000792

15873

15874 /**

15875 Extended MCi Status Pointer

15876 **/

15877 #define MSR_EXTENDED_MCG_PTR 0x00000793

15878

15879 typedef union {

15880 ///

15881 /// Individual bit fields

15882 ///

15883 struct {

15884 UINT32 PhysMemPtr0 : 32;

15885

15886 /* Bits[31:0], Access Type=RW, default=0x00000000*/

15887

15888 /*

15889 Physical memory pointer. Points to the memory

15890 (DRAM or MMIO) containing Extended_MCi_Status

15891 structure.

15892 */

15893 UINT32 PhysMemPtr1 : 30;

15894

15895 /* Bits[61:32], Access Type=RW, default=0x00000000*/

15896

15897 /*

15898 Physical memory pointer. Points to the memory

15899 (DRAM or MMIO) containing Extended_MCi_Status

15900 structure.

15901 */

15902 UINT32 Overflow : 1;

15903

15904 /* Bits[62:62], Access Type=RW, default=0x00000000*/

15905

15906 /* Overflow */

15907 UINT32 Valid : 1;

15908

15909 /* Bits[63:63], Access Type=RW, default=0x00000000*/

15910

15911 /* Valid */

15912

15913 } Bits;

15914

15915 UINT32 Uint32;

15916 UINT64 Uint64;

15917

15918 } MSR_EXTENDED_MCG_PTR_REGISTER;

15919 /**

15920 Spare Virtual MSRs in uncore Creg PLA

15921 " seq has 12 instances in addresses range 0x794 to 0x79F"

15922 **/

15923 #define MSR_UNCORE_SPARE_2_2 0x00000794

15924 /**

15925 Spare Virtual MSRs in uncore Creg PLA

15926 " seq has 12 instances in addresses range 0x794 to 0x79F"

15927 **/

15928 #define MSR_UNCORE_SPARE_3_3 0x00000795

15929 /**

15930 Spare Virtual MSRs in uncore Creg PLA

15931 " seq has 12 instances in addresses range 0x794 to 0x79F"

15932 **/

15933 #define MSR_UNCORE_SPARE_4_4 0x00000796

15934 /**

15935 Spare Virtual MSRs in uncore Creg PLA

15936 " seq has 12 instances in addresses range 0x794 to 0x79F"

15937 **/

15938 #define MSR_UNCORE_SPARE_5_5 0x00000797

15939 /**

15940 Spare Virtual MSRs in uncore Creg PLA

15941 " seq has 12 instances in addresses range 0x794 to 0x79F"

15942 **/

15943 #define MSR_UNCORE_SPARE_6_6 0x00000798

15944 /**

15945 Spare Virtual MSRs in uncore Creg PLA

15946 " seq has 12 instances in addresses range 0x794 to 0x79F"

15947 **/

15948 #define MSR_UNCORE_SPARE_7_7 0x00000799

15949 /**

15950 Spare Virtual MSRs in uncore Creg PLA

15951 " seq has 12 instances in addresses range 0x794 to 0x79F"

15952 **/

15953 #define MSR_UNCORE_SPARE_8_8 0x0000079A

15954 /**

15955 Spare Virtual MSRs in uncore Creg PLA

15956 " seq has 12 instances in addresses range 0x794 to 0x79F"

15957 **/

15958 #define MSR_UNCORE_SPARE_9_9 0x0000079B

15959 /**

15960 Spare Virtual MSRs in uncore Creg PLA

15961 " seq has 12 instances in addresses range 0x794 to 0x79F"

15962 **/

15963 #define MSR_UNCORE_SPARE_10_10 0x0000079C

15964 /**

15965 Spare Virtual MSRs in uncore Creg PLA

15966 " seq has 12 instances in addresses range 0x794 to 0x79F"

15967 **/

15968 #define MSR_UNCORE_SPARE_11_11 0x0000079D

15969 /**

15970 Spare Virtual MSRs in uncore Creg PLA

15971 " seq has 12 instances in addresses range 0x794 to 0x79F"

15972 **/

15973 #define MSR_UNCORE_SPARE_12_12 0x0000079E

15974 /**

15975 Spare Virtual MSRs in uncore Creg PLA

15976 " seq has 12 instances in addresses range 0x794 to 0x79F"

15977 **/

15978 #define MSR_UNCORE_SPARE_13_13 0x0000079F

15979 /**

15980 Virtual APIC MSRs that are modeled by ucode

15981 " seq has 2 instances in addresses range 0x800 to 0x801"

15982 **/

15983 #define MSR_VIRTUAL_APIC_0_0 0x00000800

15984 /**

15985 Virtual APIC MSRs that are modeled by ucode

15986 " seq has 2 instances in addresses range 0x800 to 0x801"

15987 **/

15988 #define MSR_VIRTUAL_APIC_1_1 0x00000801

15989

15990 /**

15991 X2APIC Local APIC ID register

15992 **/

15993 #define MSR_PIC_EXTENDED_LOCAL_APIC_ID 0x00000802

15994

15995 typedef union {

15996 ///

15997 /// Individual bit fields

15998 ///

15999 struct {

16000 UINT32 Tid : 1;

16001

16002 /* Bits[0:0], Access Type=RW, default=0x00000000*/

16003

16004 /* Thread Id */

16005 UINT32 Cid : 3;

16006

16007 /* Bits[3:1], Access Type=RW, default=0x00000000*/

16008

16009 /* Core Id */

16010 UINT32 HighApicId : 11;

16011

16012 /* Bits[14:4], Access Type=RW, default=0x00000000*/

16013

16014 /* HIGH_APIC Id */

16015 UINT32 Rsvd15 : 17;

16016

16017 /* Bits[31:15], Access Type=RO, default=None*/

16018

16019 /* Reserved */

16020

16021 } Bits;

16022

16023 UINT32 Uint32;

16024 UINT64 Uint64;

16025

16026 } MSR_PIC_EXTENDED_LOCAL_APIC_ID_REGISTER;

16027

16028 /**

16029 Local APIC Version register

16030 **/

16031 #define MSR_PIC_LOCAL_UNIT_VERSION 0x00000803

16032

16033 typedef union {

16034 ///

16035 /// Individual bit fields

16036 ///

16037 struct {

16038 UINT32 VersionId : 8;

16039

16040 /* Bits[7:0], Access Type=RO_V, default=0x00000015*/

16041

16042 /* APIC Version ID */

16043 UINT32 Rsvd8 : 8;

16044

16045 /* Bits[15:8], Access Type=RO, default=None*/

16046

16047 /* Reserved */

16048 UINT32 MaxLvtEntry : 8;

16049

16050 /* Bits[23:16], Access Type=RO_V, default=0x00000006*/

16051

16052 /* Index of highest LVT Entry */

16053 UINT32 DirectedEoiSupport : 1;

16054

16055 /* Bits[24:24], Access Type=RO_V, default=0x00000001*/

16056

16057 /*

16058 If 1, this part contains support for Directed

16059 EOI (EOI Broadcast Disable)

16060 */

16061 UINT32 Rsvd25 : 7;

16062

16063 /* Bits[31:25], Access Type=RO, default=None*/

16064

16065 /* Reserved */

16066

16067 } Bits;

16068

16069 UINT32 Uint32;

16070 UINT64 Uint64;

16071

16072 } MSR_PIC_LOCAL_UNIT_VERSION_REGISTER;

16073 /**

16074 Virtual APIC MSRs that are modeled by ucode

16075 " seq has 4 instances in addresses range 0x804 to 0x807"

16076 **/

16077 #define MSR_VIRTUAL_APIC_2_2 0x00000804

16078 /**

16079 Virtual APIC MSRs that are modeled by ucode

16080 " seq has 4 instances in addresses range 0x804 to 0x807"

16081 **/

16082 #define MSR_VIRTUAL_APIC_3_3 0x00000805

16083 /**

16084 Virtual APIC MSRs that are modeled by ucode

16085 " seq has 4 instances in addresses range 0x804 to 0x807"

16086 **/

16087 #define MSR_VIRTUAL_APIC_4_4 0x00000806

16088 /**

16089 Virtual APIC MSRs that are modeled by ucode

16090 " seq has 4 instances in addresses range 0x804 to 0x807"

16091 **/

16092 #define MSR_VIRTUAL_APIC_5_5 0x00000807

16093

16094 /**

16095 APIC Task Priority Register

16096 **/

16097 #define MSR_PIC_TASK_PRIORITY 0x00000808

16098

16099 typedef union {

16100 ///

16101 /// Individual bit fields

16102 ///

16103 struct {

16104 UINT32 TprValue : 8;

16105

16106 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16107

16108 /* Task Priority Register */

16109 UINT32 Rsvd8 : 24;

16110

16111 /* Bits[31:8], Access Type=RO, default=None*/

16112

16113 /* Reserved */

16114

16115 } Bits;

16116

16117 UINT32 Uint32;

16118 UINT64 Uint64;

16119

16120 } MSR_PIC_TASK_PRIORITY_REGISTER;

16121 /**

16122 Virtual APIC MSRs that are modeled by ucode

16123 " seq has 1 instances in addresses range 0x809 to 0x809"

16124 **/

16125 #define MSR_VIRTUAL_APIC_6_6 0x00000809

16126

16127 /**

16128 APIC Processor Priority Register

16129 **/

16130 #define MSR_PIC_PROCESSOR_PRIORITY 0x0000080A

16131

16132 typedef union {

16133 ///

16134 /// Individual bit fields

16135 ///

16136 struct {

16137 UINT32 PprValue : 8;

16138

16139 /* Bits[7:0], Access Type=RO_V, default=0x00000000*/

16140

16141 /* Processor Priority Register */

16142 UINT32 Rsvd8 : 24;

16143

16144 /* Bits[31:8], Access Type=RO, default=None*/

16145

16146 /* Reserved */

16147

16148 } Bits;

16149

16150 UINT32 Uint32;

16151 UINT64 Uint64;

16152

16153 } MSR_PIC_PROCESSOR_PRIORITY_REGISTER;

16154 /**

16155 APIC EOI Register

16156 **/

16157 #define MSR_PIC_EOI 0x0000080B

16158 /**

16159 Virtual APIC MSRs that are modeled by ucode

16160 " seq has 1 instances in addresses range 0x80C to 0x80C"

16161 **/

16162 #define MSR_VIRTUAL_APIC_7_7 0x0000080C

16163

16164 /**

16165 X2APIC Logical Destination register

16166 **/

16167 #define MSR_PIC_EXTENDED_LOGICAL_DESTINATION 0x0000080D

16168

16169 typedef union {

16170 ///

16171 /// Individual bit fields

16172 ///

16173 struct {

16174 UINT32 ExtendedCidTid : 16;

16175

16176 /* Bits[15:0], Access Type=RW, default=0x00000000*/

16177

16178 /* Logical ID 15:0 */

16179 UINT32 HighApicId : 11;

16180

16181 /* Bits[26:16], Access Type=RW, default=0x00000000*/

16182

16183 /* Logical ID 26:16 */

16184 UINT32 Rsvd27 : 5;

16185

16186 /* Bits[31:27], Access Type=RO, default=None*/

16187

16188 /* Reserved */

16189

16190 } Bits;

16191

16192 UINT32 Uint32;

16193 UINT64 Uint64;

16194

16195 } MSR_PIC_EXTENDED_LOGICAL_DESTINATION_REGISTER;

16196 /**

16197 Virtual APIC MSRs that are modeled by ucode

16198 " seq has 1 instances in addresses range 0x80E to 0x80E"

16199 **/

16200 #define MSR_VIRTUAL_APIC_8_8 0x0000080E

16201

16202 /**

16203 Spurious Interrupt Vector register

16204 **/

16205 #define MSR_PIC_SPURIOUS_INTERRUPT 0x0000080F

16206

16207 typedef union {

16208 ///

16209 /// Individual bit fields

16210 ///

16211 struct {

16212 UINT32 SpuriousVector : 8;

16213

16214 /* Bits[7:0], Access Type=RW, default=0x000000FF*/

16215

16216 /* Spurious Interrupt Vector */

16217 UINT32 SoftwareEnable : 1;

16218

16219 /* Bits[8:8], Access Type=RW, default=0x00000000*/

16220

16221 /* Software Enable Bit */

16222 UINT32 Rsvd9 : 3;

16223

16224 /* Bits[11:9], Access Type=RO, default=None*/

16225

16226 /* Reserved */

16227 UINT32 Directedeoien : 1;

16228

16229 /* Bits[12:12], Access Type=RW, default=0x00000000*/

16230

16231 /* EOI Suppression Bit */

16232 UINT32 Rsvd13 : 19;

16233

16234 /* Bits[31:13], Access Type=RO, default=None*/

16235

16236 /* Reserved */

16237

16238 } Bits;

16239

16240 UINT32 Uint32;

16241 UINT64 Uint64;

16242

16243 } MSR_PIC_SPURIOUS_INTERRUPT_REGISTER;

16244 /**

16245 APIC In-Service register bits

16246 " seq has 1 instances in addresses range 0x810 to 0x810"

16247 **/

16248 #define MSR_PIC_ISR_DWORD_0_0 0x00000810

16249 /**

16250 APIC In-Service register bits

16251 " seq has 7 instances in addresses range 0x811 to 0x817"

16252 **/

16253 #define MSR_PIC_ISR_DWORD_1_1 0x00000811

16254 /**

16255 APIC In-Service register bits

16256 " seq has 7 instances in addresses range 0x811 to 0x817"

16257 **/

16258 #define MSR_PIC_ISR_DWORD_2_2 0x00000812

16259 /**

16260 APIC In-Service register bits

16261 " seq has 7 instances in addresses range 0x811 to 0x817"

16262 **/

16263 #define MSR_PIC_ISR_DWORD_3_3 0x00000813

16264 /**

16265 APIC In-Service register bits

16266 " seq has 7 instances in addresses range 0x811 to 0x817"

16267 **/

16268 #define MSR_PIC_ISR_DWORD_4_4 0x00000814

16269 /**

16270 APIC In-Service register bits

16271 " seq has 7 instances in addresses range 0x811 to 0x817"

16272 **/

16273 #define MSR_PIC_ISR_DWORD_5_5 0x00000815

16274 /**

16275 APIC In-Service register bits

16276 " seq has 7 instances in addresses range 0x811 to 0x817"

16277 **/

16278 #define MSR_PIC_ISR_DWORD_6_6 0x00000816

16279 /**

16280 APIC In-Service register bits

16281 " seq has 7 instances in addresses range 0x811 to 0x817"

16282 **/

16283 #define MSR_PIC_ISR_DWORD_7_7 0x00000817

16284 /**

16285 APIC Trigger Mode register bits

16286 " seq has 1 instances in addresses range 0x818 to 0x818"

16287 **/

16288 #define MSR_PIC_TMR_DWORD_0_0 0x00000818

16289 /**

16290 APIC Trigger Mode register bits

16291 " seq has 7 instances in addresses range 0x819 to 0x81F"

16292 **/

16293 #define MSR_PIC_TMR_DWORD_1_1 0x00000819

16294 /**

16295 APIC Trigger Mode register bits

16296 " seq has 7 instances in addresses range 0x819 to 0x81F"

16297 **/

16298 #define MSR_PIC_TMR_DWORD_2_2 0x0000081A

16299 /**

16300 APIC Trigger Mode register bits

16301 " seq has 7 instances in addresses range 0x819 to 0x81F"

16302 **/

16303 #define MSR_PIC_TMR_DWORD_3_3 0x0000081B

16304 /**

16305 APIC Trigger Mode register bits

16306 " seq has 7 instances in addresses range 0x819 to 0x81F"

16307 **/

16308 #define MSR_PIC_TMR_DWORD_4_4 0x0000081C

16309 /**

16310 APIC Trigger Mode register bits

16311 " seq has 7 instances in addresses range 0x819 to 0x81F"

16312 **/

16313 #define MSR_PIC_TMR_DWORD_5_5 0x0000081D

16314 /**

16315 APIC Trigger Mode register bits

16316 " seq has 7 instances in addresses range 0x819 to 0x81F"

16317 **/

16318 #define MSR_PIC_TMR_DWORD_6_6 0x0000081E

16319 /**

16320 APIC Trigger Mode register bits

16321 " seq has 7 instances in addresses range 0x819 to 0x81F"

16322 **/

16323 #define MSR_PIC_TMR_DWORD_7_7 0x0000081F

16324 /**

16325 APIC Interrupt Request register bits

16326 " seq has 1 instances in addresses range 0x820 to 0x820"

16327 **/

16328 #define MSR_PIC_IRR_DWORD_0_0 0x00000820

16329 /**

16330 APIC Interrupt Request register bits

16331 " seq has 7 instances in addresses range 0x821 to 0x827"

16332 **/

16333 #define MSR_PIC_IRR_DWORD_1_1 0x00000821

16334 /**

16335 APIC Interrupt Request register bits

16336 " seq has 7 instances in addresses range 0x821 to 0x827"

16337 **/

16338 #define MSR_PIC_IRR_DWORD_2_2 0x00000822

16339 /**

16340 APIC Interrupt Request register bits

16341 " seq has 7 instances in addresses range 0x821 to 0x827"

16342 **/

16343 #define MSR_PIC_IRR_DWORD_3_3 0x00000823

16344 /**

16345 APIC Interrupt Request register bits

16346 " seq has 7 instances in addresses range 0x821 to 0x827"

16347 **/

16348 #define MSR_PIC_IRR_DWORD_4_4 0x00000824

16349 /**

16350 APIC Interrupt Request register bits

16351 " seq has 7 instances in addresses range 0x821 to 0x827"

16352 **/

16353 #define MSR_PIC_IRR_DWORD_5_5 0x00000825

16354 /**

16355 APIC Interrupt Request register bits

16356 " seq has 7 instances in addresses range 0x821 to 0x827"

16357 **/

16358 #define MSR_PIC_IRR_DWORD_6_6 0x00000826

16359 /**

16360 APIC Interrupt Request register bits

16361 " seq has 7 instances in addresses range 0x821 to 0x827"

16362 **/

16363 #define MSR_PIC_IRR_DWORD_7_7 0x00000827

16364

16365 /**

16366 APIC Error Status register

16367 **/

16368 #define MSR_PIC_ERROR_STATUS 0x00000828

16369

16370 typedef union {

16371 ///

16372 /// Individual bit fields

16373 ///

16374 struct {

16375 UINT32 Rsvd0 : 4;

16376

16377 /* Bits[3:0], Access Type=RO, default=None*/

16378

16379 /* Reserved */

16380 UINT32 RedirectableIpi : 1;

16381

16382 /* Bits[4:4], Access Type=RO_V, default=0x00000000*/

16383

16384 /*

16385 IPI with illegal Low Priority delivery mode

16386 attempted from ICR write

16387 */

16388 UINT32 SendIllegalVector : 1;

16389

16390 /* Bits[5:5], Access Type=RO_V, default=0x00000000*/

16391

16392 /* IPI with illegal vector attempted from ICR write */

16393 UINT32 RcvIllegalVector : 1;

16394

16395 /* Bits[6:6], Access Type=RO_V, default=0x00000000*/

16396

16397 /* Interrupt received with an illegal vector */

16398 UINT32 IllegalRegAddr : 1;

16399

16400 /* Bits[7:7], Access Type=RO_V, default=0x00000000*/

16401

16402 /*

16403 APIC register access detected with an illegal

16404 address

16405 */

16406 UINT32 Rsvd8 : 24;

16407

16408 /* Bits[31:8], Access Type=RO, default=None*/

16409

16410 /* Reserved */

16411

16412 } Bits;

16413

16414 UINT32 Uint32;

16415 UINT64 Uint64;

16416

16417 } MSR_PIC_ERROR_STATUS_REGISTER;

16418 /**

16419 Virtual APIC MSRs that are modeled by ucode

16420 " seq has 6 instances in addresses range 0x829 to 0x82E"

16421 **/

16422 #define MSR_VIRTUAL_APIC_9_9 0x00000829

16423 /**

16424 Virtual APIC MSRs that are modeled by ucode

16425 " seq has 6 instances in addresses range 0x829 to 0x82E"

16426 **/

16427 #define MSR_VIRTUAL_APIC_10_10 0x0000082A

16428 /**

16429 Virtual APIC MSRs that are modeled by ucode

16430 " seq has 6 instances in addresses range 0x829 to 0x82E"

16431 **/

16432 #define MSR_VIRTUAL_APIC_11_11 0x0000082B

16433 /**

16434 Virtual APIC MSRs that are modeled by ucode

16435 " seq has 6 instances in addresses range 0x829 to 0x82E"

16436 **/

16437 #define MSR_VIRTUAL_APIC_12_12 0x0000082C

16438 /**

16439 Virtual APIC MSRs that are modeled by ucode

16440 " seq has 6 instances in addresses range 0x829 to 0x82E"

16441 **/

16442 #define MSR_VIRTUAL_APIC_13_13 0x0000082D

16443 /**

16444 Virtual APIC MSRs that are modeled by ucode

16445 " seq has 6 instances in addresses range 0x829 to 0x82E"

16446 **/

16447 #define MSR_VIRTUAL_APIC_14_14 0x0000082E

16448

16449 /**

16450 LVT Entry for Correctable MCA Interrupt

16451 **/

16452 #define MSR_PIC_LVT_CMCI 0x0000082F

16453

16454 typedef union {

16455 ///

16456 /// Individual bit fields

16457 ///

16458 struct {

16459 UINT32 Vector : 8;

16460

16461 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16462

16463 /* PIC Correctable MCA Interrupt Vector */

16464 UINT32 DeliveryMode : 3;

16465

16466 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16467

16468 /* PIC Correctable MCA Interrupt Delivery Mode */

16469 UINT32 Rsvd11 : 1;

16470

16471 /* Bits[11:11], Access Type=RO, default=None*/

16472

16473 /* Reserved */

16474 UINT32 DeliveryStatus : 1;

16475

16476 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16477

16478 /* PIC Correctable MCA Interrupt Delivery Status */

16479 UINT32 Rsvd13 : 3;

16480

16481 /* Bits[15:13], Access Type=RO, default=None*/

16482

16483 /* Reserved */

16484 UINT32 Mask : 1;

16485

16486 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16487

16488 /*

16489 PIC Correctable MCA Interrupt Mask Bit -

16490 writeable only when APIC is SW Enabled

16491 */

16492 UINT32 Rsvd17 : 15;

16493

16494 /* Bits[31:17], Access Type=RO, default=None*/

16495

16496 /* Reserved */

16497

16498 } Bits;

16499

16500 UINT32 Uint32;

16501 UINT64 Uint64;

16502

16503 } MSR_PIC_LVT_CMCI_REGISTER;

16504

16505 /**

16506 APIC Interrupt Command register

16507 **/

16508 #define MSR_PIC_INTERRUPT_COMMAND 0x00000830

16509

16510 typedef union {

16511 ///

16512 /// Individual bit fields

16513 ///

16514 struct {

16515 UINT32 Vector : 8;

16516

16517 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16518

16519 /* Interrupt Vector for outgoing IPI */

16520 UINT32 DeliveryMode : 3;

16521

16522 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16523

16524 /* Delivery Mode for outgoing IPI */

16525 UINT32 DestinationMode : 1;

16526

16527 /* Bits[11:11], Access Type=RW, default=0x00000000*/

16528

16529 /* Destination Mode for outgoing IPI */

16530 UINT32 DeliveryStatus : 1;

16531

16532 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16533

16534 /* Delivery Status for outgoing IPI */

16535 UINT32 Rsvd13 : 1;

16536

16537 /* Bits[13:13], Access Type=RO, default=None*/

16538

16539 /* Reserved */

16540 UINT32 Level : 1;

16541

16542 /* Bits[14:14], Access Type=RW, default=0x00000000*/

16543

16544 /* Level Trigger for outgoing IPI */

16545 UINT32 TriggerMode : 1;

16546

16547 /* Bits[15:15], Access Type=RW, default=0x00000000*/

16548

16549 /* Trigger Mode for outgoing IPI */

16550 UINT32 Rsvd16 : 2;

16551

16552 /* Bits[17:16], Access Type=RO, default=None*/

16553

16554 /* Reserved */

16555 UINT32 DestShorthand : 2;

16556

16557 /* Bits[19:18], Access Type=RW, default=0x00000000*/

16558

16559 /* Destination Shorthand for outgoing IPI */

16560 UINT32 Rsvd20 : 12;

16561

16562 /* Bits[31:20], Access Type=RO, default=None*/

16563

16564 /* Reserved */

16565 UINT32 Destination : 27;

16566

16567 /* Bits[58:32], Access Type=RW, default=0x00000000*/

16568

16569 /* Destination for outgoing IPI */

16570 UINT32 Rsvd59 : 5;

16571

16572 /* Bits[63:59], Access Type=RO, default=None*/

16573

16574 /* Reserved */

16575

16576 } Bits;

16577

16578 UINT32 Uint32;

16579 UINT64 Uint64;

16580

16581 } MSR_PIC_INTERRUPT_COMMAND_REGISTER;

16582 /**

16583 Virtual APIC MSRs that are modeled by ucode

16584 " seq has 1 instances in addresses range 0x831 to 0x831"

16585 **/

16586 #define MSR_VIRTUAL_APIC_15_15 0x00000831

16587

16588 /**

16589 LVT Entry for the PIC Timer

16590 **/

16591 #define MSR_PIC_LVT_TIMER 0x00000832

16592

16593 typedef union {

16594 ///

16595 /// Individual bit fields

16596 ///

16597 struct {

16598 UINT32 Vector : 8;

16599

16600 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16601

16602 /* PIC Timer Interrupt Vector */

16603 UINT32 Rsvd8 : 4;

16604

16605 /* Bits[11:8], Access Type=RO, default=None*/

16606

16607 /* Reserved */

16608 UINT32 DeliveryStatus : 1;

16609

16610 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16611

16612 /* PIC Timer Interrupt Delivery Status */

16613 UINT32 Rsvd13 : 3;

16614

16615 /* Bits[15:13], Access Type=RO, default=None*/

16616

16617 /* Reserved */

16618 UINT32 Mask : 1;

16619

16620 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16621

16622 /*

16623 PIC Timer Interrupt Mask Bit - writeable only

16624 when APIC is SW Enabled

16625 */

16626 UINT32 TimerMode : 2;

16627

16628 /* Bits[18:17], Access Type=RW, default=0x00000000*/

16629

16630 /*

16631 timer mode- single (00) periodic (01)

16632 tsc_deadline (10) reserved (11)

16633 */

16634 UINT32 Rsvd19 : 13;

16635

16636 /* Bits[31:19], Access Type=RO, default=None*/

16637

16638 /* Reserved */

16639

16640 } Bits;

16641

16642 UINT32 Uint32;

16643 UINT64 Uint64;

16644

16645 } MSR_PIC_LVT_TIMER_REGISTER;

16646

16647 /**

16648 LVT Entry for the Thermal Interrupt

16649 **/

16650 #define MSR_PIC_LVT_THERM 0x00000833

16651

16652 typedef union {

16653 ///

16654 /// Individual bit fields

16655 ///

16656 struct {

16657 UINT32 Vector : 8;

16658

16659 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16660

16661 /* PIC Thermal Interrupt Vector */

16662 UINT32 DeliveryMode : 3;

16663

16664 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16665

16666 /* PIC Thermal Interrupt Delivery Mode */

16667 UINT32 Rsvd11 : 1;

16668

16669 /* Bits[11:11], Access Type=RO, default=None*/

16670

16671 /* Reserved */

16672 UINT32 DeliveryStatus : 1;

16673

16674 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16675

16676 /* PIC Thermal Interrupt Delivery Status */

16677 UINT32 Rsvd13 : 3;

16678

16679 /* Bits[15:13], Access Type=RO, default=None*/

16680

16681 /* Reserved */

16682 UINT32 Mask : 1;

16683

16684 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16685

16686 /*

16687 PIC Thermal Interrupt Mask Bit - writeable only

16688 when APIC is SW Enabled

16689 */

16690 UINT32 Rsvd17 : 15;

16691

16692 /* Bits[31:17], Access Type=RO, default=None*/

16693

16694 /* Reserved */

16695

16696 } Bits;

16697

16698 UINT32 Uint32;

16699 UINT64 Uint64;

16700

16701 } MSR_PIC_LVT_THERM_REGISTER;

16702

16703 /**

16704 LVT Entry for PerfMon Interrupt

16705 **/

16706 #define MSR_PIC_LVT_PERF 0x00000834

16707

16708 typedef union {

16709 ///

16710 /// Individual bit fields

16711 ///

16712 struct {

16713 UINT32 Vector : 8;

16714

16715 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16716

16717 /* PIC PerfMon Interrupt Vector */

16718 UINT32 DeliveryMode : 3;

16719

16720 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16721

16722 /* PIC PerfMon Interrupt Delivery Mode */

16723 UINT32 Rsvd11 : 1;

16724

16725 /* Bits[11:11], Access Type=RO, default=None*/

16726

16727 /* Reserved */

16728 UINT32 DeliveryStatus : 1;

16729

16730 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16731

16732 /* PIC PerfMon Interrupt Delivery Status */

16733 UINT32 Rsvd13 : 3;

16734

16735 /* Bits[15:13], Access Type=RO, default=None*/

16736

16737 /* Reserved */

16738 UINT32 Mask : 1;

16739

16740 /* Bits[16:16], Access Type=RW_V, default=0x00000001*/

16741

16742 /*

16743 PIC PerfMon Interrupt Mask Bit - writeable only

16744 when APIC is SW Enabled

16745 */

16746 UINT32 Rsvd17 : 15;

16747

16748 /* Bits[31:17], Access Type=RO, default=None*/

16749

16750 /* Reserved */

16751

16752 } Bits;

16753

16754 UINT32 Uint32;

16755 UINT64 Uint64;

16756

16757 } MSR_PIC_LVT_PERF_REGISTER;

16758

16759 /**

16760 LVT Entry for Lint Pin 0 Interrupt

16761 **/

16762 #define MSR_PIC_LVT_LINT0 0x00000835

16763

16764 typedef union {

16765 ///

16766 /// Individual bit fields

16767 ///

16768 struct {

16769 UINT32 Vector : 8;

16770

16771 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16772

16773 /* PIC Lint Pin 0 Interrupt Vector */

16774 UINT32 DeliveryMode : 3;

16775

16776 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16777

16778 /* PIC Lint Pin 0 Interrupt Delivery Mode */

16779 UINT32 Rsvd11 : 1;

16780

16781 /* Bits[11:11], Access Type=RO, default=None*/

16782

16783 /* Reserved */

16784 UINT32 DeliveryStatus : 1;

16785

16786 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16787

16788 /* PIC Lint Pin 0 Interrupt Delivery Status */

16789 UINT32 Polarity : 1;

16790

16791 /* Bits[13:13], Access Type=RW, default=0x00000000*/

16792

16793 /* PIC Lint Pin 0 Polarity */

16794 UINT32 Rirr : 1;

16795

16796 /* Bits[14:14], Access Type=RO_V, default=0x00000000*/

16797

16798 /* PIC Lint Pin 0 Remote IRR Bit */

16799 UINT32 TriggerMode : 1;

16800

16801 /* Bits[15:15], Access Type=RW, default=0x00000000*/

16802

16803 /* PIC Lint Pin 0 Trigger Mode */

16804 UINT32 Mask : 1;

16805

16806 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16807

16808 /*

16809 PIC Lint Pin 0 Interrupt Mask Bit - writeable

16810 only when APIC is SW Enabled

16811 */

16812 UINT32 Rsvd17 : 15;

16813

16814 /* Bits[31:17], Access Type=RO, default=None*/

16815

16816 /* Reserved */

16817

16818 } Bits;

16819

16820 UINT32 Uint32;

16821 UINT64 Uint64;

16822

16823 } MSR_PIC_LVT_LINT0_REGISTER;

16824

16825 /**

16826 LVT Entry for Lint Pin 1 Interrupt

16827 **/

16828 #define MSR_PIC_LVT_LINT1 0x00000836

16829

16830 typedef union {

16831 ///

16832 /// Individual bit fields

16833 ///

16834 struct {

16835 UINT32 Vector : 8;

16836

16837 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16838

16839 /* PIC Lint Pin 1 Interrupt Vector */

16840 UINT32 DeliveryMode : 3;

16841

16842 /* Bits[10:8], Access Type=RW, default=0x00000000*/

16843

16844 /* PIC Lint Pin 1 Interrupt Delivery Mode */

16845 UINT32 Rsvd11 : 1;

16846

16847 /* Bits[11:11], Access Type=RO, default=None*/

16848

16849 /* Reserved */

16850 UINT32 DeliveryStatus : 1;

16851

16852 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16853

16854 /* PIC Lint Pin 1 Interrupt Delivery Status */

16855 UINT32 Polarity : 1;

16856

16857 /* Bits[13:13], Access Type=RW, default=0x00000000*/

16858

16859 /* PIC Lint Pin 1 Polarity */

16860 UINT32 Rirr : 1;

16861

16862 /* Bits[14:14], Access Type=RO_V, default=0x00000000*/

16863

16864 /* PIC Lint Pin 1 Interrupt Remote IRR */

16865 UINT32 TriggerMode : 1;

16866

16867 /* Bits[15:15], Access Type=RW, default=0x00000000*/

16868

16869 /* PIC Lint Pin 1 Trigger Mode */

16870 UINT32 Mask : 1;

16871

16872 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16873

16874 /*

16875 PIC Lint Pin 1 Interrupt Mask Bit - writeable

16876 only when APIC is SW Enabled

16877 */

16878 UINT32 Rsvd17 : 15;

16879

16880 /* Bits[31:17], Access Type=RO, default=None*/

16881

16882 /* Reserved */

16883

16884 } Bits;

16885

16886 UINT32 Uint32;

16887 UINT64 Uint64;

16888

16889 } MSR_PIC_LVT_LINT1_REGISTER;

16890

16891 /**

16892 LVT Entry for Error Interrupt

16893 **/

16894 #define MSR_PIC_LVT_ERROR 0x00000837

16895

16896 typedef union {

16897 ///

16898 /// Individual bit fields

16899 ///

16900 struct {

16901 UINT32 Vector : 8;

16902

16903 /* Bits[7:0], Access Type=RW, default=0x00000000*/

16904

16905 /* PIC Error Interrupt Vector */

16906 UINT32 Rsvd8 : 4;

16907

16908 /* Bits[11:8], Access Type=RO, default=None*/

16909

16910 /* Reserved */

16911 UINT32 DeliveryStatus : 1;

16912

16913 /* Bits[12:12], Access Type=RO_V, default=0x00000000*/

16914

16915 /* PIC Error Interrupt Delivery Status */

16916 UINT32 Rsvd13 : 3;

16917

16918 /* Bits[15:13], Access Type=RO, default=None*/

16919

16920 /* Reserved */

16921 UINT32 Mask : 1;

16922

16923 /* Bits[16:16], Access Type=RW, default=0x00000001*/

16924

16925 /*

16926 PIC Error Interrupt Mask Bit - writeable only

16927 when APIC is SW Enabled

16928 */

16929 UINT32 Rsvd17 : 15;

16930

16931 /* Bits[31:17], Access Type=RO, default=None*/

16932

16933 /* Reserved */

16934

16935 } Bits;

16936

16937 UINT32 Uint32;

16938 UINT64 Uint64;

16939

16940 } MSR_PIC_LVT_ERROR_REGISTER;

16941 /**

16942 APIC Initial Count register

16943 **/

16944 #define MSR_PIC_TIMER_INITIAL_COUNT_REG 0x00000838

16945 /**

16946 APIC Current Count register

16947 **/

16948 #define MSR_PIC_TIMER_CURRENT_COUNT_REG 0x00000839

16949 /**

16950 Virtual APIC MSRs that are modeled by ucode

16951 " seq has 4 instances in addresses range 0x83A to 0x83D"

16952 **/

16953 #define MSR_VIRTUAL_APIC_16_16 0x0000083A

16954 /**

16955 Virtual APIC MSRs that are modeled by ucode

16956 " seq has 4 instances in addresses range 0x83A to 0x83D"

16957 **/

16958 #define MSR_VIRTUAL_APIC_17_17 0x0000083B

16959 /**

16960 Virtual APIC MSRs that are modeled by ucode

16961 " seq has 4 instances in addresses range 0x83A to 0x83D"

16962 **/

16963 #define MSR_VIRTUAL_APIC_18_18 0x0000083C

16964 /**

16965 Virtual APIC MSRs that are modeled by ucode

16966 " seq has 4 instances in addresses range 0x83A to 0x83D"

16967 **/

16968 #define MSR_VIRTUAL_APIC_19_19 0x0000083D

16969

16970 /**

16971 APIC Divide Configuration register

16972 **/

16973 #define MSR_PIC_TIMER_DIVIDE_CONFIG_REG 0x0000083E

16974

16975 typedef union {

16976 ///

16977 /// Individual bit fields

16978 ///

16979 struct {

16980 UINT32 DivideSel : 4;

16981

16982 /* Bits[3:0], Access Type=RW_V, default=0x00000000*/

16983

16984 /* APIC LVT Interrupt Timer Counter Config */

16985 UINT32 Rsvd4 : 28;

16986

16987 /* Bits[31:4], Access Type=RO, default=None*/

16988

16989 /* Reserved */

16990

16991 } Bits;

16992

16993 UINT32 Uint32;

16994 UINT64 Uint64;

16995

16996 } MSR_PIC_TIMER_DIVIDE_CONFIG_REG_REGISTER;

16997

16998 /**

16999 x2APIC Self IPI register

17000 **/

17001 #define MSR_SELF_IPI 0x0000083F

17002

17003 typedef union {

17004 ///

17005 /// Individual bit fields

17006 ///

17007 struct {

17008 UINT32 Vector : 8;

17009

17010 /* Bits[7:0], Access Type=RW, default=0x00000000*/

17011

17012 /* Self IPI Vector */

17013 UINT32 Rsvd8 : 24;

17014

17015 /* Bits[31:8], Access Type=RO, default=None*/

17016

17017 /* Reserved */

17018

17019 } Bits;

17020

17021 UINT32 Uint32;

17022 UINT64 Uint64;

17023

17024 } MSR_SELF_IPI_REGISTER;

17025 /**

17026 Virtual APIC MSRs that are modeled by ucode

17027 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17028 **/

17029 #define MSR_VIRTUAL_APIC_20_20 0x00000840

17030 /**

17031 Virtual APIC MSRs that are modeled by ucode

17032 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17033 **/

17034 #define MSR_VIRTUAL_APIC_21_21 0x00000841

17035 /**

17036 Virtual APIC MSRs that are modeled by ucode

17037 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17038 **/

17039 #define MSR_VIRTUAL_APIC_22_22 0x00000842

17040 /**

17041 Virtual APIC MSRs that are modeled by ucode

17042 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17043 **/

17044 #define MSR_VIRTUAL_APIC_23_23 0x00000843

17045 /**

17046 Virtual APIC MSRs that are modeled by ucode

17047 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17048 **/

17049 #define MSR_VIRTUAL_APIC_24_24 0x00000844

17050 /**

17051 Virtual APIC MSRs that are modeled by ucode

17052 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17053 **/

17054 #define MSR_VIRTUAL_APIC_25_25 0x00000845

17055 /**

17056 Virtual APIC MSRs that are modeled by ucode

17057 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17058 **/

17059 #define MSR_VIRTUAL_APIC_26_26 0x00000846

17060 /**

17061 Virtual APIC MSRs that are modeled by ucode

17062 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17063 **/

17064 #define MSR_VIRTUAL_APIC_27_27 0x00000847

17065 /**

17066 Virtual APIC MSRs that are modeled by ucode

17067 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17068 **/

17069 #define MSR_VIRTUAL_APIC_28_28 0x00000848

17070 /**

17071 Virtual APIC MSRs that are modeled by ucode

17072 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17073 **/

17074 #define MSR_VIRTUAL_APIC_29_29 0x00000849

17075 /**

17076 Virtual APIC MSRs that are modeled by ucode

17077 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17078 **/

17079 #define MSR_VIRTUAL_APIC_30_30 0x0000084A

17080 /**

17081 Virtual APIC MSRs that are modeled by ucode

17082 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17083 **/

17084 #define MSR_VIRTUAL_APIC_31_31 0x0000084B

17085 /**

17086 Virtual APIC MSRs that are modeled by ucode

17087 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17088 **/

17089 #define MSR_VIRTUAL_APIC_32_32 0x0000084C

17090 /**

17091 Virtual APIC MSRs that are modeled by ucode

17092 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17093 **/

17094 #define MSR_VIRTUAL_APIC_33_33 0x0000084D

17095 /**

17096 Virtual APIC MSRs that are modeled by ucode

17097 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17098 **/

17099 #define MSR_VIRTUAL_APIC_34_34 0x0000084E

17100 /**

17101 Virtual APIC MSRs that are modeled by ucode

17102 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17103 **/

17104 #define MSR_VIRTUAL_APIC_35_35 0x0000084F

17105 /**

17106 Virtual APIC MSRs that are modeled by ucode

17107 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17108 **/

17109 #define MSR_VIRTUAL_APIC_36_36 0x00000850

17110 /**

17111 Virtual APIC MSRs that are modeled by ucode

17112 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17113 **/

17114 #define MSR_VIRTUAL_APIC_37_37 0x00000851

17115 /**

17116 Virtual APIC MSRs that are modeled by ucode

17117 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17118 **/

17119 #define MSR_VIRTUAL_APIC_38_38 0x00000852

17120 /**

17121 Virtual APIC MSRs that are modeled by ucode

17122 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17123 **/

17124 #define MSR_VIRTUAL_APIC_39_39 0x00000853

17125 /**

17126 Virtual APIC MSRs that are modeled by ucode

17127 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17128 **/

17129 #define MSR_VIRTUAL_APIC_40_40 0x00000854

17130 /**

17131 Virtual APIC MSRs that are modeled by ucode

17132 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17133 **/

17134 #define MSR_VIRTUAL_APIC_41_41 0x00000855

17135 /**

17136 Virtual APIC MSRs that are modeled by ucode

17137 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17138 **/

17139 #define MSR_VIRTUAL_APIC_42_42 0x00000856

17140 /**

17141 Virtual APIC MSRs that are modeled by ucode

17142 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17143 **/

17144 #define MSR_VIRTUAL_APIC_43_43 0x00000857

17145 /**

17146 Virtual APIC MSRs that are modeled by ucode

17147 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17148 **/

17149 #define MSR_VIRTUAL_APIC_44_44 0x00000858

17150 /**

17151 Virtual APIC MSRs that are modeled by ucode

17152 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17153 **/

17154 #define MSR_VIRTUAL_APIC_45_45 0x00000859

17155 /**

17156 Virtual APIC MSRs that are modeled by ucode

17157 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17158 **/

17159 #define MSR_VIRTUAL_APIC_46_46 0x0000085A

17160 /**

17161 Virtual APIC MSRs that are modeled by ucode

17162 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17163 **/

17164 #define MSR_VIRTUAL_APIC_47_47 0x0000085B

17165 /**

17166 Virtual APIC MSRs that are modeled by ucode

17167 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17168 **/

17169 #define MSR_VIRTUAL_APIC_48_48 0x0000085C

17170 /**

17171 Virtual APIC MSRs that are modeled by ucode

17172 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17173 **/

17174 #define MSR_VIRTUAL_APIC_49_49 0x0000085D

17175 /**

17176 Virtual APIC MSRs that are modeled by ucode

17177 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17178 **/

17179 #define MSR_VIRTUAL_APIC_50_50 0x0000085E

17180 /**

17181 Virtual APIC MSRs that are modeled by ucode

17182 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17183 **/

17184 #define MSR_VIRTUAL_APIC_51_51 0x0000085F

17185 /**

17186 Virtual APIC MSRs that are modeled by ucode

17187 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17188 **/

17189 #define MSR_VIRTUAL_APIC_52_52 0x00000860

17190 /**

17191 Virtual APIC MSRs that are modeled by ucode

17192 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17193 **/

17194 #define MSR_VIRTUAL_APIC_53_53 0x00000861

17195 /**

17196 Virtual APIC MSRs that are modeled by ucode

17197 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17198 **/

17199 #define MSR_VIRTUAL_APIC_54_54 0x00000862

17200 /**

17201 Virtual APIC MSRs that are modeled by ucode

17202 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17203 **/

17204 #define MSR_VIRTUAL_APIC_55_55 0x00000863

17205 /**

17206 Virtual APIC MSRs that are modeled by ucode

17207 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17208 **/

17209 #define MSR_VIRTUAL_APIC_56_56 0x00000864

17210 /**

17211 Virtual APIC MSRs that are modeled by ucode

17212 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17213 **/

17214 #define MSR_VIRTUAL_APIC_57_57 0x00000865

17215 /**

17216 Virtual APIC MSRs that are modeled by ucode

17217 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17218 **/

17219 #define MSR_VIRTUAL_APIC_58_58 0x00000866

17220 /**

17221 Virtual APIC MSRs that are modeled by ucode

17222 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17223 **/

17224 #define MSR_VIRTUAL_APIC_59_59 0x00000867

17225 /**

17226 Virtual APIC MSRs that are modeled by ucode

17227 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17228 **/

17229 #define MSR_VIRTUAL_APIC_60_60 0x00000868

17230 /**

17231 Virtual APIC MSRs that are modeled by ucode

17232 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17233 **/

17234 #define MSR_VIRTUAL_APIC_61_61 0x00000869

17235 /**

17236 Virtual APIC MSRs that are modeled by ucode

17237 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17238 **/

17239 #define MSR_VIRTUAL_APIC_62_62 0x0000086A

17240 /**

17241 Virtual APIC MSRs that are modeled by ucode

17242 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17243 **/

17244 #define MSR_VIRTUAL_APIC_63_63 0x0000086B

17245 /**

17246 Virtual APIC MSRs that are modeled by ucode

17247 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17248 **/

17249 #define MSR_VIRTUAL_APIC_64_64 0x0000086C

17250 /**

17251 Virtual APIC MSRs that are modeled by ucode

17252 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17253 **/

17254 #define MSR_VIRTUAL_APIC_65_65 0x0000086D

17255 /**

17256 Virtual APIC MSRs that are modeled by ucode

17257 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17258 **/

17259 #define MSR_VIRTUAL_APIC_66_66 0x0000086E

17260 /**

17261 Virtual APIC MSRs that are modeled by ucode

17262 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17263 **/

17264 #define MSR_VIRTUAL_APIC_67_67 0x0000086F

17265 /**

17266 Virtual APIC MSRs that are modeled by ucode

17267 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17268 **/

17269 #define MSR_VIRTUAL_APIC_68_68 0x00000870

17270 /**

17271 Virtual APIC MSRs that are modeled by ucode

17272 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17273 **/

17274 #define MSR_VIRTUAL_APIC_69_69 0x00000871

17275 /**

17276 Virtual APIC MSRs that are modeled by ucode

17277 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17278 **/

17279 #define MSR_VIRTUAL_APIC_70_70 0x00000872

17280 /**

17281 Virtual APIC MSRs that are modeled by ucode

17282 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17283 **/

17284 #define MSR_VIRTUAL_APIC_71_71 0x00000873

17285 /**

17286 Virtual APIC MSRs that are modeled by ucode

17287 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17288 **/

17289 #define MSR_VIRTUAL_APIC_72_72 0x00000874

17290 /**

17291 Virtual APIC MSRs that are modeled by ucode

17292 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17293 **/

17294 #define MSR_VIRTUAL_APIC_73_73 0x00000875

17295 /**

17296 Virtual APIC MSRs that are modeled by ucode

17297 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17298 **/

17299 #define MSR_VIRTUAL_APIC_74_74 0x00000876

17300 /**

17301 Virtual APIC MSRs that are modeled by ucode

17302 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17303 **/

17304 #define MSR_VIRTUAL_APIC_75_75 0x00000877

17305 /**

17306 Virtual APIC MSRs that are modeled by ucode

17307 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17308 **/

17309 #define MSR_VIRTUAL_APIC_76_76 0x00000878

17310 /**

17311 Virtual APIC MSRs that are modeled by ucode

17312 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17313 **/

17314 #define MSR_VIRTUAL_APIC_77_77 0x00000879

17315 /**

17316 Virtual APIC MSRs that are modeled by ucode

17317 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17318 **/

17319 #define MSR_VIRTUAL_APIC_78_78 0x0000087A

17320 /**

17321 Virtual APIC MSRs that are modeled by ucode

17322 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17323 **/

17324 #define MSR_VIRTUAL_APIC_79_79 0x0000087B

17325 /**

17326 Virtual APIC MSRs that are modeled by ucode

17327 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17328 **/

17329 #define MSR_VIRTUAL_APIC_80_80 0x0000087C

17330 /**

17331 Virtual APIC MSRs that are modeled by ucode

17332 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17333 **/

17334 #define MSR_VIRTUAL_APIC_81_81 0x0000087D

17335 /**

17336 Virtual APIC MSRs that are modeled by ucode

17337 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17338 **/

17339 #define MSR_VIRTUAL_APIC_82_82 0x0000087E

17340 /**

17341 Virtual APIC MSRs that are modeled by ucode

17342 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17343 **/

17344 #define MSR_VIRTUAL_APIC_83_83 0x0000087F

17345 /**

17346 Virtual APIC MSRs that are modeled by ucode

17347 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17348 **/

17349 #define MSR_VIRTUAL_APIC_84_84 0x00000880

17350 /**

17351 Virtual APIC MSRs that are modeled by ucode

17352 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17353 **/

17354 #define MSR_VIRTUAL_APIC_85_85 0x00000881

17355 /**

17356 Virtual APIC MSRs that are modeled by ucode

17357 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17358 **/

17359 #define MSR_VIRTUAL_APIC_86_86 0x00000882

17360 /**

17361 Virtual APIC MSRs that are modeled by ucode

17362 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17363 **/

17364 #define MSR_VIRTUAL_APIC_87_87 0x00000883

17365 /**

17366 Virtual APIC MSRs that are modeled by ucode

17367 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17368 **/

17369 #define MSR_VIRTUAL_APIC_88_88 0x00000884

17370 /**

17371 Virtual APIC MSRs that are modeled by ucode

17372 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17373 **/

17374 #define MSR_VIRTUAL_APIC_89_89 0x00000885

17375 /**

17376 Virtual APIC MSRs that are modeled by ucode

17377 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17378 **/

17379 #define MSR_VIRTUAL_APIC_90_90 0x00000886

17380 /**

17381 Virtual APIC MSRs that are modeled by ucode

17382 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17383 **/

17384 #define MSR_VIRTUAL_APIC_91_91 0x00000887

17385 /**

17386 Virtual APIC MSRs that are modeled by ucode

17387 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17388 **/

17389 #define MSR_VIRTUAL_APIC_92_92 0x00000888

17390 /**

17391 Virtual APIC MSRs that are modeled by ucode

17392 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17393 **/

17394 #define MSR_VIRTUAL_APIC_93_93 0x00000889

17395 /**

17396 Virtual APIC MSRs that are modeled by ucode

17397 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17398 **/

17399 #define MSR_VIRTUAL_APIC_94_94 0x0000088A

17400 /**

17401 Virtual APIC MSRs that are modeled by ucode

17402 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17403 **/

17404 #define MSR_VIRTUAL_APIC_95_95 0x0000088B

17405 /**

17406 Virtual APIC MSRs that are modeled by ucode

17407 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17408 **/

17409 #define MSR_VIRTUAL_APIC_96_96 0x0000088C

17410 /**

17411 Virtual APIC MSRs that are modeled by ucode

17412 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17413 **/

17414 #define MSR_VIRTUAL_APIC_97_97 0x0000088D

17415 /**

17416 Virtual APIC MSRs that are modeled by ucode

17417 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17418 **/

17419 #define MSR_VIRTUAL_APIC_98_98 0x0000088E

17420 /**

17421 Virtual APIC MSRs that are modeled by ucode

17422 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17423 **/

17424 #define MSR_VIRTUAL_APIC_99_99 0x0000088F

17425 /**

17426 Virtual APIC MSRs that are modeled by ucode

17427 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17428 **/

17429 #define MSR_VIRTUAL_APIC_100_100 0x00000890

17430 /**

17431 Virtual APIC MSRs that are modeled by ucode

17432 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17433 **/

17434 #define MSR_VIRTUAL_APIC_101_101 0x00000891

17435 /**

17436 Virtual APIC MSRs that are modeled by ucode

17437 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17438 **/

17439 #define MSR_VIRTUAL_APIC_102_102 0x00000892

17440 /**

17441 Virtual APIC MSRs that are modeled by ucode

17442 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17443 **/

17444 #define MSR_VIRTUAL_APIC_103_103 0x00000893

17445 /**

17446 Virtual APIC MSRs that are modeled by ucode

17447 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17448 **/

17449 #define MSR_VIRTUAL_APIC_104_104 0x00000894

17450 /**

17451 Virtual APIC MSRs that are modeled by ucode

17452 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17453 **/

17454 #define MSR_VIRTUAL_APIC_105_105 0x00000895

17455 /**

17456 Virtual APIC MSRs that are modeled by ucode

17457 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17458 **/

17459 #define MSR_VIRTUAL_APIC_106_106 0x00000896

17460 /**

17461 Virtual APIC MSRs that are modeled by ucode

17462 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17463 **/

17464 #define MSR_VIRTUAL_APIC_107_107 0x00000897

17465 /**

17466 Virtual APIC MSRs that are modeled by ucode

17467 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17468 **/

17469 #define MSR_VIRTUAL_APIC_108_108 0x00000898

17470 /**

17471 Virtual APIC MSRs that are modeled by ucode

17472 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17473 **/

17474 #define MSR_VIRTUAL_APIC_109_109 0x00000899

17475 /**

17476 Virtual APIC MSRs that are modeled by ucode

17477 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17478 **/

17479 #define MSR_VIRTUAL_APIC_110_110 0x0000089A

17480 /**

17481 Virtual APIC MSRs that are modeled by ucode

17482 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17483 **/

17484 #define MSR_VIRTUAL_APIC_111_111 0x0000089B

17485 /**

17486 Virtual APIC MSRs that are modeled by ucode

17487 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17488 **/

17489 #define MSR_VIRTUAL_APIC_112_112 0x0000089C

17490 /**

17491 Virtual APIC MSRs that are modeled by ucode

17492 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17493 **/

17494 #define MSR_VIRTUAL_APIC_113_113 0x0000089D

17495 /**

17496 Virtual APIC MSRs that are modeled by ucode

17497 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17498 **/

17499 #define MSR_VIRTUAL_APIC_114_114 0x0000089E

17500 /**

17501 Virtual APIC MSRs that are modeled by ucode

17502 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17503 **/

17504 #define MSR_VIRTUAL_APIC_115_115 0x0000089F

17505 /**

17506 Virtual APIC MSRs that are modeled by ucode

17507 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17508 **/

17509 #define MSR_VIRTUAL_APIC_116_116 0x000008A0

17510 /**

17511 Virtual APIC MSRs that are modeled by ucode

17512 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17513 **/

17514 #define MSR_VIRTUAL_APIC_117_117 0x000008A1

17515 /**

17516 Virtual APIC MSRs that are modeled by ucode

17517 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17518 **/

17519 #define MSR_VIRTUAL_APIC_118_118 0x000008A2

17520 /**

17521 Virtual APIC MSRs that are modeled by ucode

17522 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17523 **/

17524 #define MSR_VIRTUAL_APIC_119_119 0x000008A3

17525 /**

17526 Virtual APIC MSRs that are modeled by ucode

17527 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17528 **/

17529 #define MSR_VIRTUAL_APIC_120_120 0x000008A4

17530 /**

17531 Virtual APIC MSRs that are modeled by ucode

17532 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17533 **/

17534 #define MSR_VIRTUAL_APIC_121_121 0x000008A5

17535 /**

17536 Virtual APIC MSRs that are modeled by ucode

17537 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17538 **/

17539 #define MSR_VIRTUAL_APIC_122_122 0x000008A6

17540 /**

17541 Virtual APIC MSRs that are modeled by ucode

17542 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17543 **/

17544 #define MSR_VIRTUAL_APIC_123_123 0x000008A7

17545 /**

17546 Virtual APIC MSRs that are modeled by ucode

17547 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17548 **/

17549 #define MSR_VIRTUAL_APIC_124_124 0x000008A8

17550 /**

17551 Virtual APIC MSRs that are modeled by ucode

17552 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17553 **/

17554 #define MSR_VIRTUAL_APIC_125_125 0x000008A9

17555 /**

17556 Virtual APIC MSRs that are modeled by ucode

17557 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17558 **/

17559 #define MSR_VIRTUAL_APIC_126_126 0x000008AA

17560 /**

17561 Virtual APIC MSRs that are modeled by ucode

17562 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17563 **/

17564 #define MSR_VIRTUAL_APIC_127_127 0x000008AB

17565 /**

17566 Virtual APIC MSRs that are modeled by ucode

17567 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17568 **/

17569 #define MSR_VIRTUAL_APIC_128_128 0x000008AC

17570 /**

17571 Virtual APIC MSRs that are modeled by ucode

17572 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17573 **/

17574 #define MSR_VIRTUAL_APIC_129_129 0x000008AD

17575 /**

17576 Virtual APIC MSRs that are modeled by ucode

17577 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17578 **/

17579 #define MSR_VIRTUAL_APIC_130_130 0x000008AE

17580 /**

17581 Virtual APIC MSRs that are modeled by ucode

17582 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17583 **/

17584 #define MSR_VIRTUAL_APIC_131_131 0x000008AF

17585 /**

17586 Virtual APIC MSRs that are modeled by ucode

17587 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17588 **/

17589 #define MSR_VIRTUAL_APIC_132_132 0x000008B0

17590 /**

17591 Virtual APIC MSRs that are modeled by ucode

17592 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17593 **/

17594 #define MSR_VIRTUAL_APIC_133_133 0x000008B1

17595 /**

17596 Virtual APIC MSRs that are modeled by ucode

17597 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17598 **/

17599 #define MSR_VIRTUAL_APIC_134_134 0x000008B2

17600 /**

17601 Virtual APIC MSRs that are modeled by ucode

17602 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17603 **/

17604 #define MSR_VIRTUAL_APIC_135_135 0x000008B3

17605 /**

17606 Virtual APIC MSRs that are modeled by ucode

17607 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17608 **/

17609 #define MSR_VIRTUAL_APIC_136_136 0x000008B4

17610 /**

17611 Virtual APIC MSRs that are modeled by ucode

17612 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17613 **/

17614 #define MSR_VIRTUAL_APIC_137_137 0x000008B5

17615 /**

17616 Virtual APIC MSRs that are modeled by ucode

17617 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17618 **/

17619 #define MSR_VIRTUAL_APIC_138_138 0x000008B6

17620 /**

17621 Virtual APIC MSRs that are modeled by ucode

17622 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17623 **/

17624 #define MSR_VIRTUAL_APIC_139_139 0x000008B7

17625 /**

17626 Virtual APIC MSRs that are modeled by ucode

17627 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17628 **/

17629 #define MSR_VIRTUAL_APIC_140_140 0x000008B8

17630 /**

17631 Virtual APIC MSRs that are modeled by ucode

17632 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17633 **/

17634 #define MSR_VIRTUAL_APIC_141_141 0x000008B9

17635 /**

17636 Virtual APIC MSRs that are modeled by ucode

17637 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17638 **/

17639 #define MSR_VIRTUAL_APIC_142_142 0x000008BA

17640 /**

17641 Virtual APIC MSRs that are modeled by ucode

17642 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17643 **/

17644 #define MSR_VIRTUAL_APIC_143_143 0x000008BB

17645 /**

17646 Virtual APIC MSRs that are modeled by ucode

17647 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17648 **/

17649 #define MSR_VIRTUAL_APIC_144_144 0x000008BC

17650 /**

17651 Virtual APIC MSRs that are modeled by ucode

17652 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17653 **/

17654 #define MSR_VIRTUAL_APIC_145_145 0x000008BD

17655 /**

17656 Virtual APIC MSRs that are modeled by ucode

17657 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17658 **/

17659 #define MSR_VIRTUAL_APIC_146_146 0x000008BE

17660 /**

17661 Virtual APIC MSRs that are modeled by ucode

17662 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17663 **/

17664 #define MSR_VIRTUAL_APIC_147_147 0x000008BF

17665 /**

17666 Virtual APIC MSRs that are modeled by ucode

17667 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17668 **/

17669 #define MSR_VIRTUAL_APIC_148_148 0x000008C0

17670 /**

17671 Virtual APIC MSRs that are modeled by ucode

17672 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17673 **/

17674 #define MSR_VIRTUAL_APIC_149_149 0x000008C1

17675 /**

17676 Virtual APIC MSRs that are modeled by ucode

17677 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17678 **/

17679 #define MSR_VIRTUAL_APIC_150_150 0x000008C2

17680 /**

17681 Virtual APIC MSRs that are modeled by ucode

17682 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17683 **/

17684 #define MSR_VIRTUAL_APIC_151_151 0x000008C3

17685 /**

17686 Virtual APIC MSRs that are modeled by ucode

17687 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17688 **/

17689 #define MSR_VIRTUAL_APIC_152_152 0x000008C4

17690 /**

17691 Virtual APIC MSRs that are modeled by ucode

17692 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17693 **/

17694 #define MSR_VIRTUAL_APIC_153_153 0x000008C5

17695 /**

17696 Virtual APIC MSRs that are modeled by ucode

17697 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17698 **/

17699 #define MSR_VIRTUAL_APIC_154_154 0x000008C6

17700 /**

17701 Virtual APIC MSRs that are modeled by ucode

17702 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17703 **/

17704 #define MSR_VIRTUAL_APIC_155_155 0x000008C7

17705 /**

17706 Virtual APIC MSRs that are modeled by ucode

17707 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17708 **/

17709 #define MSR_VIRTUAL_APIC_156_156 0x000008C8

17710 /**

17711 Virtual APIC MSRs that are modeled by ucode

17712 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17713 **/

17714 #define MSR_VIRTUAL_APIC_157_157 0x000008C9

17715 /**

17716 Virtual APIC MSRs that are modeled by ucode

17717 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17718 **/

17719 #define MSR_VIRTUAL_APIC_158_158 0x000008CA

17720 /**

17721 Virtual APIC MSRs that are modeled by ucode

17722 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17723 **/

17724 #define MSR_VIRTUAL_APIC_159_159 0x000008CB

17725 /**

17726 Virtual APIC MSRs that are modeled by ucode

17727 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17728 **/

17729 #define MSR_VIRTUAL_APIC_160_160 0x000008CC

17730 /**

17731 Virtual APIC MSRs that are modeled by ucode

17732 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17733 **/

17734 #define MSR_VIRTUAL_APIC_161_161 0x000008CD

17735 /**

17736 Virtual APIC MSRs that are modeled by ucode

17737 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17738 **/

17739 #define MSR_VIRTUAL_APIC_162_162 0x000008CE

17740 /**

17741 Virtual APIC MSRs that are modeled by ucode

17742 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17743 **/

17744 #define MSR_VIRTUAL_APIC_163_163 0x000008CF

17745 /**

17746 Virtual APIC MSRs that are modeled by ucode

17747 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17748 **/

17749 #define MSR_VIRTUAL_APIC_164_164 0x000008D0

17750 /**

17751 Virtual APIC MSRs that are modeled by ucode

17752 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17753 **/

17754 #define MSR_VIRTUAL_APIC_165_165 0x000008D1

17755 /**

17756 Virtual APIC MSRs that are modeled by ucode

17757 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17758 **/

17759 #define MSR_VIRTUAL_APIC_166_166 0x000008D2

17760 /**

17761 Virtual APIC MSRs that are modeled by ucode

17762 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17763 **/

17764 #define MSR_VIRTUAL_APIC_167_167 0x000008D3

17765 /**

17766 Virtual APIC MSRs that are modeled by ucode

17767 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17768 **/

17769 #define MSR_VIRTUAL_APIC_168_168 0x000008D4

17770 /**

17771 Virtual APIC MSRs that are modeled by ucode

17772 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17773 **/

17774 #define MSR_VIRTUAL_APIC_169_169 0x000008D5

17775 /**

17776 Virtual APIC MSRs that are modeled by ucode

17777 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17778 **/

17779 #define MSR_VIRTUAL_APIC_170_170 0x000008D6

17780 /**

17781 Virtual APIC MSRs that are modeled by ucode

17782 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17783 **/

17784 #define MSR_VIRTUAL_APIC_171_171 0x000008D7

17785 /**

17786 Virtual APIC MSRs that are modeled by ucode

17787 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17788 **/

17789 #define MSR_VIRTUAL_APIC_172_172 0x000008D8

17790 /**

17791 Virtual APIC MSRs that are modeled by ucode

17792 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17793 **/

17794 #define MSR_VIRTUAL_APIC_173_173 0x000008D9

17795 /**

17796 Virtual APIC MSRs that are modeled by ucode

17797 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17798 **/

17799 #define MSR_VIRTUAL_APIC_174_174 0x000008DA

17800 /**

17801 Virtual APIC MSRs that are modeled by ucode

17802 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17803 **/

17804 #define MSR_VIRTUAL_APIC_175_175 0x000008DB

17805 /**

17806 Virtual APIC MSRs that are modeled by ucode

17807 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17808 **/

17809 #define MSR_VIRTUAL_APIC_176_176 0x000008DC

17810 /**

17811 Virtual APIC MSRs that are modeled by ucode

17812 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17813 **/

17814 #define MSR_VIRTUAL_APIC_177_177 0x000008DD

17815 /**

17816 Virtual APIC MSRs that are modeled by ucode

17817 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17818 **/

17819 #define MSR_VIRTUAL_APIC_178_178 0x000008DE

17820 /**

17821 Virtual APIC MSRs that are modeled by ucode

17822 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17823 **/

17824 #define MSR_VIRTUAL_APIC_179_179 0x000008DF

17825 /**

17826 Virtual APIC MSRs that are modeled by ucode

17827 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17828 **/

17829 #define MSR_VIRTUAL_APIC_180_180 0x000008E0

17830 /**

17831 Virtual APIC MSRs that are modeled by ucode

17832 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17833 **/

17834 #define MSR_VIRTUAL_APIC_181_181 0x000008E1

17835 /**

17836 Virtual APIC MSRs that are modeled by ucode

17837 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17838 **/

17839 #define MSR_VIRTUAL_APIC_182_182 0x000008E2

17840 /**

17841 Virtual APIC MSRs that are modeled by ucode

17842 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17843 **/

17844 #define MSR_VIRTUAL_APIC_183_183 0x000008E3

17845 /**

17846 Virtual APIC MSRs that are modeled by ucode

17847 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17848 **/

17849 #define MSR_VIRTUAL_APIC_184_184 0x000008E4

17850 /**

17851 Virtual APIC MSRs that are modeled by ucode

17852 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17853 **/

17854 #define MSR_VIRTUAL_APIC_185_185 0x000008E5

17855 /**

17856 Virtual APIC MSRs that are modeled by ucode

17857 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17858 **/

17859 #define MSR_VIRTUAL_APIC_186_186 0x000008E6

17860 /**

17861 Virtual APIC MSRs that are modeled by ucode

17862 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17863 **/

17864 #define MSR_VIRTUAL_APIC_187_187 0x000008E7

17865 /**

17866 Virtual APIC MSRs that are modeled by ucode

17867 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17868 **/

17869 #define MSR_VIRTUAL_APIC_188_188 0x000008E8

17870 /**

17871 Virtual APIC MSRs that are modeled by ucode

17872 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17873 **/

17874 #define MSR_VIRTUAL_APIC_189_189 0x000008E9

17875 /**

17876 Virtual APIC MSRs that are modeled by ucode

17877 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17878 **/

17879 #define MSR_VIRTUAL_APIC_190_190 0x000008EA

17880 /**

17881 Virtual APIC MSRs that are modeled by ucode

17882 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17883 **/

17884 #define MSR_VIRTUAL_APIC_191_191 0x000008EB

17885 /**

17886 Virtual APIC MSRs that are modeled by ucode

17887 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17888 **/

17889 #define MSR_VIRTUAL_APIC_192_192 0x000008EC

17890 /**

17891 Virtual APIC MSRs that are modeled by ucode

17892 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17893 **/

17894 #define MSR_VIRTUAL_APIC_193_193 0x000008ED

17895 /**

17896 Virtual APIC MSRs that are modeled by ucode

17897 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17898 **/

17899 #define MSR_VIRTUAL_APIC_194_194 0x000008EE

17900 /**

17901 Virtual APIC MSRs that are modeled by ucode

17902 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17903 **/

17904 #define MSR_VIRTUAL_APIC_195_195 0x000008EF

17905 /**

17906 Virtual APIC MSRs that are modeled by ucode

17907 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17908 **/

17909 #define MSR_VIRTUAL_APIC_196_196 0x000008F0

17910 /**

17911 Virtual APIC MSRs that are modeled by ucode

17912 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17913 **/

17914 #define MSR_VIRTUAL_APIC_197_197 0x000008F1

17915 /**

17916 Virtual APIC MSRs that are modeled by ucode

17917 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17918 **/

17919 #define MSR_VIRTUAL_APIC_198_198 0x000008F2

17920 /**

17921 Virtual APIC MSRs that are modeled by ucode

17922 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17923 **/

17924 #define MSR_VIRTUAL_APIC_199_199 0x000008F3

17925 /**

17926 Virtual APIC MSRs that are modeled by ucode

17927 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17928 **/

17929 #define MSR_VIRTUAL_APIC_200_200 0x000008F4

17930 /**

17931 Virtual APIC MSRs that are modeled by ucode

17932 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17933 **/

17934 #define MSR_VIRTUAL_APIC_201_201 0x000008F5

17935 /**

17936 Virtual APIC MSRs that are modeled by ucode

17937 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17938 **/

17939 #define MSR_VIRTUAL_APIC_202_202 0x000008F6

17940 /**

17941 Virtual APIC MSRs that are modeled by ucode

17942 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17943 **/

17944 #define MSR_VIRTUAL_APIC_203_203 0x000008F7

17945 /**

17946 Virtual APIC MSRs that are modeled by ucode

17947 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17948 **/

17949 #define MSR_VIRTUAL_APIC_204_204 0x000008F8

17950 /**

17951 Virtual APIC MSRs that are modeled by ucode

17952 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17953 **/

17954 #define MSR_VIRTUAL_APIC_205_205 0x000008F9

17955 /**

17956 Virtual APIC MSRs that are modeled by ucode

17957 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17958 **/

17959 #define MSR_VIRTUAL_APIC_206_206 0x000008FA

17960 /**

17961 Virtual APIC MSRs that are modeled by ucode

17962 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17963 **/

17964 #define MSR_VIRTUAL_APIC_207_207 0x000008FB

17965 /**

17966 Virtual APIC MSRs that are modeled by ucode

17967 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17968 **/

17969 #define MSR_VIRTUAL_APIC_208_208 0x000008FC

17970 /**

17971 Virtual APIC MSRs that are modeled by ucode

17972 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17973 **/

17974 #define MSR_VIRTUAL_APIC_209_209 0x000008FD

17975 /**

17976 Virtual APIC MSRs that are modeled by ucode

17977 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17978 **/

17979 #define MSR_VIRTUAL_APIC_210_210 0x000008FE

17980 /**

17981 Virtual APIC MSRs that are modeled by ucode

17982 " seq has 192 instances in addresses range 0x840 to 0x8FF"

17983 **/

17984 #define MSR_VIRTUAL_APIC_211_211 0x000008FF

17985

17986 /**

17987 Holds XSAVE_AREA "triplet" w/ addition of XCompaction vector for the XMODIFIED optimization.

17988 **/

17989 #define MSR_XRSTOR_INFO 0x00000900

17990

17991 typedef union {

17992 ///

17993 /// Individual bit fields

17994 ///

17995 struct {

17996 UINT32 XsaveAreaCpl : 2;

17997

17998 /* Bits[1:0], Access Type=RW, default=None*/

17999

18000 /* The full CPL from the last XRSTOR instruction. */

18001 UINT32 XsaveAreaVmmHostGuest : 1;

18002

18003 /* Bits[2:2], Access Type=RW, default=None*/

18004

18005 /*

18006 The VMM Host/Guest state from the last XRSTOR

18007 instruction.

18008 */

18009 UINT32 Rsvd3 : 2;

18010

18011 /* Bits[4:3], Access Type=RW, default=None*/

18012

18013 /* Unused bits. */

18014 UINT32 XsaveAreaValid : 1;

18015

18016 /* Bits[5:5], Access Type=RW, default=None*/

18017

18018 /*

18019 The XSAVE_AREA valid bit is effectively an

18020 address bit of the XSAVE_AREA. Since all

18021 XSAVE_AREAs must be 64 byte aligned, setting

18022 this bit forces the misalignment so compare of

18023 this XSAVE_AREA and the XSAVE_AREA specified in

18024 the XSAVE instruction must miscompare. The

18025 miscompare will force all xmodified bits to be

18026 treated as modified.

18027 */

18028 UINT32 XsaveAreaAddress0 : 26;

18029

18030 /* Bits[31:6], Access Type=RW, default=None*/

18031

18032 /*

18033 The XSAVE_AREA linear address from the last

18034 XRSTOR.

18035 */

18036 UINT32 XsaveAreaAddress1 : 25;

18037

18038 /* Bits[56:32], Access Type=RW, default=None*/

18039

18040 /*

18041 The XSAVE_AREA linear address from the last

18042 XRSTOR.

18043 */

18044 UINT32 Rsvd57 : 7;

18045

18046 /* Bits[63:57], Access Type=RW, default=None*/

18047

18048 /* Unused bits. */

18049

18050 } Bits;

18051

18052 UINT32 Uint32;

18053 UINT64 Uint64;

18054

18055 } MSR_XRSTOR_INFO_REGISTER;

18056 /**

18057 Contains Exit Qual used on SMI I/O exits

18058 C6NoSave Candidate

18059 **/

18060 #define MSR_VMX_IO_EXIT_QUAL 0x00000901

18061

18062 /**

18063 Equivalent to architectural DR6 reg. 16 bit.

18064 (Mrm roctlregc/roctlregd/{tmpdr6lowSM306L|tmpdr6hiSM306L})

18065 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

18066 !!! !!!

18067 !!! CAUTION: Adding more bits to this creg or changing the layout of this creg !!!

18068 !!! will require MSR ucode changes. Talk to MSR ucode owner (rpartha on NHM) if!!!

18069 !!! you want to make changes to this creg !!!

18070 !!! !!!

18071 !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

18072 **/

18073 #define MSR_TMPDR6 0x00000902

18074

18075 typedef union {

18076 ///

18077 /// Individual bit fields

18078 ///

18079 struct {

18080 UINT32 B0 : 1;

18081

18082 /* Bits[0:0], Access Type=RW_V, default=0x00000000*/

18083

18084 /* ROBTMPDR6B0 */

18085 UINT32 B1 : 1;

18086

18087 /* Bits[1:1], Access Type=RW_V, default=0x00000000*/

18088

18089 /* ROBTMPDR6B1 */

18090 UINT32 B2 : 1;

18091

18092 /* Bits[2:2], Access Type=RW_V, default=0x00000000*/

18093

18094 /* ROBTMPDR6B2 */

18095 UINT32 B3 : 1;

18096

18097 /* Bits[3:3], Access Type=RW_V, default=0x00000000*/

18098

18099 /* ROBTMPDR6B3 */

18100 UINT32 Rsvd4 : 9;

18101

18102 /* Bits[12:4], Access Type=RO, default=None*/

18103

18104 /* Reserved */

18105 UINT32 Bd : 1;

18106

18107 /* Bits[13:13], Access Type=RW, default=0x00000000*/

18108

18109 /* ROBTMPDR6BD */

18110 UINT32 Bs : 1;

18111

18112 /* Bits[14:14], Access Type=RW_V, default=0x00000000*/

18113

18114 /* ROBTMPDR6BS */

18115 UINT32 Bt : 1;

18116

18117 /* Bits[15:15], Access Type=RW, default=0x00000000*/

18118

18119 /* ROBTMPDR6BT */

18120 UINT32 Hled : 1;

18121

18122 /* Bits[16:16], Access Type=RW_V, default=0x00000000*/

18123

18124 /* ROBTMPDR6HLED */

18125 UINT32 EnclaveInterruption : 1;

18126

18127 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

18128

18129 /*

18130 Enclave interruption indication. Cleared by HW

18131 on retired EOM

18132 */

18133 UINT32 Rsvd18 : 14;

18134

18135 /* Bits[31:18], Access Type=RO, default=None*/

18136

18137 /* Reserved */

18138

18139 } Bits;

18140

18141 UINT32 Uint32;

18142 UINT64 Uint64;

18143

18144 } MSR_TMPDR6_REGISTER;

18145

18146 /**

18147 Millicode MSR used to read/write certain fields of the

18148 Macroalias register.

18149 WRMSR will ignore the undefined bits (63:18, 14:13, 10, 6:2).

18150 WRMSR will not signal fault on any combination of bits, it is

18151 softwares responsiblity to make sure that values programmed

18152 this register are consistent and correct

18153 RDMSR will always return 0 in bits 63:18, 14:13, 10:9, 6:2.

18154 RDMSR will return the last value successfully updated by WRMSR

18155 **/

18156 #define MSR_XU_MACROINSTRUCTION_ALIAS 0x00000903

18157

18158 typedef union {

18159 ///

18160 /// Individual bit fields

18161 ///

18162 struct {

18163 UINT32 Scale : 2;

18164

18165 /* Bits[1:0], Access Type=RW, default=0x00000000*/

18166

18167 /*

18168 Scale: 00 -> scale 1, 01 -> scale 2, 10 -> scale

18169 4, 11 -> scale 8

18170 */

18171 UINT32 Rsvd2 : 5;

18172

18173 /* Bits[6:2], Access Type=RO, default=None*/

18174

18175 /* Reserved */

18176 UINT32 Asize : 3;

18177

18178 /* Bits[9:7], Access Type=RW, default=0x00000000*/

18179

18180 /*

18181 Address size: 000 -> 16-bit, 001 -> 32 bit, 010

18182 -> 64-bit, 011-111 -> Reserved

18183 */

18184 UINT32 Rsvd10 : 1;

18185

18186 /* Bits[10:10], Access Type=RO, default=None*/

18187

18188 /* Reserved */

18189 UINT32 Osize : 2;

18190

18191 /* Bits[12:11], Access Type=RW, default=0x00000000*/

18192

18193 /*

18194 Operand size: 00 -> DSZ16, 01 -> DSZ32, 10 ->

18195 DSZ64, 11 -> Reserved

18196 */

18197 UINT32 Rsvd13 : 2;

18198

18199 /* Bits[14:13], Access Type=RO, default=None*/

18200

18201 /* Reserved */

18202 UINT32 Lseg : 3;

18203

18204 /* Bits[17:15], Access Type=RW, default=0x00000000*/

18205

18206 /*

18207 Logical Segment: 000-> ES, 001-> CS, 010-> SS,

18208 011-> DS, 100-> FS, 101-> GS, 110-111 ->

18209 Reserved

18210 */

18211 UINT32 Rsvd18 : 14;

18212

18213 /* Bits[31:18], Access Type=RO, default=None*/

18214

18215 /* Reserved */

18216 UINT32 Rsvd32 : 32;

18217

18218 /* Bits[63:32], Access Type=RO, default=None*/

18219

18220 /* Reserved */

18221

18222 } Bits;

18223

18224 UINT32 Uint32;

18225 UINT64 Uint64;

18226

18227 } MSR_XU_MACROINSTRUCTION_ALIAS_REGISTER;

18228

18229 /**

18230 Millicode MSR used to update the POST_VMXON and CURRENT_WP_IS_SHADOW_VMCS mode-based branch bits

18231 WRMSR will ignore the undefined bits

18232 RDMSR will always return 0 in undefined bits

18233 **/

18234 #define MSR_XU_VMX_CONTROL 0x00000904

18235

18236 typedef union {

18237 ///

18238 /// Individual bit fields

18239 ///

18240 struct {

18241 UINT32 Rsvd0 : 1;

18242

18243 /* Bits[0:0], Access Type=RO, default=None*/

18244

18245 /* Reserved */

18246 UINT32 PostVmxon : 1;

18247

18248 /* Bits[1:1], Access Type=RW, default=0x00000000*/

18249

18250 /*

18251 Indicates whether the machine is in a post-VMXON

18252 state

18253 */

18254 UINT32 Rsvd2 : 4;

18255

18256 /* Bits[5:2], Access Type=RO, default=None*/

18257

18258 /* Reserved */

18259 UINT32 CurrentWpIsShadowVmcs : 1;

18260

18261 /* Bits[6:6], Access Type=RW, default=0x00000000*/

18262

18263 /*

18264 Indicates whether the current working pointer is

18265 a shadow VMCS

18266 */

18267 UINT32 Rsvd7 : 25;

18268

18269 /* Bits[31:7], Access Type=RO, default=None*/

18270

18271 /* Reserved */

18272 UINT32 Rsvd32 : 32;

18273

18274 /* Bits[63:32], Access Type=RO, default=None*/

18275

18276 /* Reserved */

18277

18278 } Bits;

18279

18280 UINT32 Uint32;

18281 UINT64 Uint64;

18282

18283 } MSR_XU_VMX_CONTROL_REGISTER;

18284 /**

18285 Pause-Loop Exiting: First value

18286 **/

18287 #define MSR_VMX_PLE_FIRST 0x00000905

18288 /**

18289 Pause-Loop Exiting: Last value

18290 **/

18291 #define MSR_VMX_PLE_LAST 0x00000906

18292

18293 /**

18294 Holds address bits [11:0] of a guest load/store access that hit the AVRR range

18295 C6NoSave Candidate

18296 FSCP Crunch: 12:32 Used only 12 bits out of 32

18297 **/

18298 #define MSR_VMX_VMENTRY_AVRR_TBIT_MAILBOX 0x00000907

18299

18300 typedef union {

18301 ///

18302 /// Individual bit fields

18303 ///

18304 struct {

18305 UINT32 MailboxOffset : 12;

18306

18307 /* Bits[11:0], Access Type=RW, default=None*/

18308

18309 /*

18310 Mailbox address bits [11:0] of a guest

18311 load/store access that hit the AVRR range

18312 */

18313 UINT32 Reserved12 : 20;

18314

18315 /* Bits[31:12], Access Type=RW, default=None*/

18316

18317 /* Unused */

18318

18319 } Bits;

18320

18321 UINT32 Uint32;

18322 UINT64 Uint64;

18323

18324 } MSR_VMX_VMENTRY_AVRR_TBIT_MAILBOX_REGISTER;

18325

18326 /**

18327 Millicode MSR used to control SMM states

18328 WRMSR will ignore the undefined bits (63:32, 30:1).

18329 RDMSR will always return 0 in bits 63:32, 30:1.

18330 **/

18331 #define MSR_XU_SMM_STATE 0x00000908

18332

18333 typedef union {

18334 ///

18335 /// Individual bit fields

18336 ///

18337 struct {

18338 UINT32 InSmm : 1;

18339

18340 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18341

18342 /*

18343 Setting/clearing this bit will set/clear

18344 CORE_CR_RR_MODE[IN_SMM] for the current thread

18345 (see GQ1_CR_XU_SMM_STATE for uncore). 0 - Not in

18346 SMM mode, 1 - In SMM mode

18347 */

18348 UINT32 Rsvd1 : 3;

18349

18350 /* Bits[3:1], Access Type=RO, default=None*/

18351

18352 /* Reserved */

18353 UINT32 SmmCodeAccessVioEnable : 1;

18354

18355 /* Bits[4:4], Access Type=RW, default=0x00000000*/

18356

18357 /*

18358 Tied to the following bits.

18359 PMH_CR_RR_MODE[SMM_CODE_RANGE_CHK_EN] and

18360 ROB1_CR_MISC_STATE[EIP_LOGGING].

18361 Setting/clearing this bit will set/clear

18362 PMH_CR_RR_MODE[SMM_CODE_RANGE_CHK_EN] and

18363 ROB1_CR_MISC_STATE[EIP_LOGGING]

18364 */

18365 UINT32 Rsvd5 : 16;

18366

18367 /* Bits[20:5], Access Type=RO, default=None*/

18368

18369 /* Reserved */

18370 UINT32 PsmiBaseLocked : 1;

18371

18372 /* Bits[21:21], Access Type=RW, default=0x00000000*/

18373

18374 /*

18375 RDMSR only bit to report status of

18376 SCP_CR_PSMI_CTRL_PSMI_BASE_LOCKED, ignored on

18377 WRMSR

18378 */

18379 UINT32 Rsvd22 : 9;

18380

18381 /* Bits[30:22], Access Type=RO, default=None*/

18382

18383 /* Reserved */

18384 UINT32 SmmOutsideVmx : 1;

18385

18386 /* Bits[31:31], Access Type=RW, default=0x00000000*/

18387

18388 /*

18389 Setting/clearing this bit will set/clear

18390 FSCP_CR_LT_SMM_OPT_OUT_INFO[SMM_OUTSIDE_VMX]

18391 (bit31) Indicates/controls opt-in to peer SMM

18392 operation

18393 */

18394 UINT32 Rsvd32 : 32;

18395

18396 /* Bits[63:32], Access Type=RO, default=None*/

18397

18398 /* Reserved */

18399

18400 } Bits;

18401

18402 UINT32 Uint32;

18403 UINT64 Uint64;

18404

18405 } MSR_XU_SMM_STATE_REGISTER;

18406 /**

18407 Saved RSI value from IO SMI, used by parallel VMExit and SMI

18408 C6NoSave Candidate

18409 **/

18410 #define MSR_IO_SMI_BACKUP_RSI 0x00000909

18411 /**

18412 Saved RCX value from IO SMI, used by parallel VMExit and SMI

18413 C6NoSave Candidate

18414 **/

18415 #define MSR_IO_SMI_BACKUP_RCX 0x0000090A

18416 /**

18417 Saved RDI value from IO SMI, used by parallel VMExit and SMI

18418 C6NoSave Candidate

18419 **/

18420 #define MSR_IO_SMI_BACKUP_RDI 0x0000090B

18421

18422 /**

18423 Holds VPPR bits [7:4]

18424 FSCP Crunch: 4/32 Used only 4 bits out of 32

18425 **/

18426 #define MSR_VMX_VPPR 0x0000090C

18427

18428 typedef union {

18429 ///

18430 /// Individual bit fields

18431 ///

18432 struct {

18433 UINT32 Vppr74 : 4;

18434

18435 /* Bits[3:0], Access Type=RW, default=None*/

18436

18437 /* VPPR bits [7:4] */

18438 UINT32 Reserved4 : 28;

18439

18440 /* Bits[31:4], Access Type=RW, default=None*/

18441

18442 /* New FSCPs added on HSW */

18443

18444 } Bits;

18445

18446 UINT32 Uint32;

18447 UINT64 Uint64;

18448

18449 } MSR_VMX_VPPR_REGISTER;

18450 /**

18451 Write only MSR for Xucode to write PDM data out to the GDXC

18452 **/

18453 #define MSR_PDM_GDXC_MSG 0x0000090D

18454

18455 /**

18456 This is a Write-Only cmd MSR. A write causes GT to flush outstanding transactions and re-load it's boot context. A Rd will GP Fault.

18457 With the removal of the GT_CREG_ADDR_DIFFERENTIATOR there is no

18458 need for this to be virtual

18459 **/

18460 #define MSR_GT_FLUSH_RELOAD 0x0000090E

18461

18462 typedef union {

18463 ///

18464 /// Individual bit fields

18465 ///

18466 struct {

18467 UINT32 BcldReq : 1;

18468

18469 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18470

18471 /*

18472 GT Boot Context Load Request. Write to this bit

18473 will initiate ?Mcheck Complete Routine? (PPPE

18474 flow).

18475 */

18476 UINT32 Rsvd1 : 31;

18477

18478 /* Bits[31:1], Access Type=RW, default=0x00000000*/

18479

18480 /* reserved */

18481

18482 } Bits;

18483

18484 UINT32 Uint32;

18485 UINT64 Uint64;

18486

18487 } MSR_GT_FLUSH_RELOAD_REGISTER;

18488

18489 /**

18490 GT writes a '1 to this bit to acknowledge PPPE range registers are loaded into GT.

18491 **/

18492 #define MSR_GT_FLUSH_BCLD_ACK 0x0000090F

18493

18494 typedef union {

18495 ///

18496 /// Individual bit fields

18497 ///

18498 struct {

18499 UINT32 Ack : 1;

18500

18501 /* Bits[0:0], Access Type=RW, default=0x00000000*/

18502

18503 /* GT Boot Context Load Ack */

18504 UINT32 Rsvd1 : 31;

18505

18506 /* Bits[31:1], Access Type=RO, default=None*/

18507

18508 /* Reserved */

18509

18510 } Bits;

18511

18512 UINT32 Uint32;

18513 UINT64 Uint64;

18514

18515 } MSR_GT_FLUSH_BCLD_ACK_REGISTER;

18516

18517 /**

18518

18519 **/

18520 #define MSR_XU_STATUS 0x00000910

18521

18522 typedef union {

18523 ///

18524 /// Individual bit fields

18525 ///

18526 struct {

18527 UINT32 C6DramEnabled : 1;

18528

18529 /* Bits[0:0], Access Type=RW, default=None*/

18530

18531 /* C6 DRAM ENABLE FUSE */

18532 UINT32 Rsvd1 : 1;

18533

18534 /* Bits[1:1], Access Type=RW, default=None*/

18535

18536 /* reserved */

18537 UINT32 TagecOnly : 1;

18538

18539 /* Bits[2:2], Access Type=RW, default=None*/

18540

18541 /* reserved */

18542 UINT32 Rsvd3 : 13;

18543

18544 /* Bits[15:3], Access Type=RW, default=None*/

18545

18546 /* reserved */

18547 UINT32 Strap : 4;

18548

18549 /* Bits[19:16], Access Type=RW, default=None*/

18550

18551 /* Straps from PCU_CR_STRAP_SET_DATA2_HIGH.strap */

18552 UINT32 Rsvd20 : 5;

18553

18554 /* Bits[24:20], Access Type=RW, default=None*/

18555

18556 /* reserved */

18557 UINT32 EpcOvDis : 1;

18558

18559 /* Bits[25:25], Access Type=RW, default=None*/

18560

18561 /* EPC_OV Disable fuse */

18562 UINT32 Rsvd26 : 5;

18563

18564 /* Bits[30:26], Access Type=RW, default=None*/

18565

18566 /* reserved */

18567 UINT32 EdmmDis : 1;

18568

18569 /* Bits[31:31], Access Type=RW, default=None*/

18570

18571 /* EDMM Disable fuse */

18572 UINT32 Rsvd32 : 32;

18573

18574 /* Bits[63:32], Access Type=RO, default=None*/

18575

18576 /* Reserved */

18577

18578 } Bits;

18579

18580 UINT32 Uint32;

18581 UINT64 Uint64;

18582

18583 } MSR_XU_STATUS_REGISTER;

18584

18585 /**

18586 Holds XSAVE_AREA XCompaction vector for the XMODIFIED optimization.

18587 **/

18588 #define MSR_XRSTOR_XCOMPACTION_VECTOR 0x00000911

18589

18590 typedef union {

18591 ///

18592 /// Individual bit fields

18593 ///

18594 struct {

18595 UINT32 XcompactionVector : 10;

18596

18597 /* Bits[9:0], Access Type=RW, default=None*/

18598

18599 /*

18600 Bit 0 => FP Bit 1 => SSE Bit 2 => GSSE Bit 3 =>

18601 PL BNDREGS Bit 4 => PL BNDCFS Bit 5 => KMASK Bit

18602 6 => AVX3(15:0) Bit 7 => AVX3(31:16) Bit 8 =>

18603 RTIT (reserved - actual bit in IA_XSS) Bit 9 =>

18604 PKRU

18605 */

18606 UINT32 Rsvd10 : 5;

18607

18608 /* Bits[14:10], Access Type=RW, default=None*/

18609

18610 /* Available for use */

18611 UINT32 XcompInUse : 1;

18612

18613 /* Bits[15:15], Access Type=RW, default=None*/

18614

18615 /*

18616 Save area for XRSTOR_INFO used XCOMPACTION, or

18617 VECTOR in this MSR is valid.

18618 */

18619 UINT32 Rsvd16 : 16;

18620

18621 /* Bits[31:16], Access Type=RW, default=None*/

18622

18623 /* Available for use */

18624 UINT32 Rsvd32 : 32;

18625

18626 /* Bits[63:32], Access Type=RW, default=None*/

18627

18628 /* Available for use */

18629

18630 } Bits;

18631

18632 UINT32 Uint32;

18633 UINT64 Uint64;

18634

18635 } MSR_XRSTOR_XCOMPACTION_VECTOR_REGISTER;

18636

18637 /**

18638 Trusted IO - CAM Filter Info

18639 **/

18640 #define MSR_XU_TIO_CF_INFO 0x00000912

18641

18642 typedef union {

18643 ///

18644 /// Individual bit fields

18645 ///

18646 struct {

18647 UINT32 Numrows : 8;

18648

18649 /* Bits[7:0], Access Type=RO, default=0x00000000*/

18650

18651 /*

18652 Specifies the number of rows in the CAM Filter

18653 table

18654 */

18655 UINT32 Numcols : 8;

18656

18657 /* Bits[15:8], Access Type=RO, default=0x00000000*/

18658

18659 /*

18660 Specifies the number of CRs per row in the CAM

18661 Filter table

18662 */

18663 UINT32 Reserved16 : 16;

18664

18665 /* Bits[31:16], Access Type=RO, default=0x00000000*/

18666

18667 /*

18668 reserved the number of CRs per row in the CAM

18669 Filter table

18670 */

18671 UINT32 Reserved32 : 32;

18672

18673 /* Bits[63:32], Access Type=RO, default=0x00000000*/

18674

18675 /*

18676 reserved the number of CRs per row in the CAM

18677 Filter table

18678 */

18679

18680 } Bits;

18681

18682 UINT32 Uint32;

18683 UINT64 Uint64;

18684

18685 } MSR_XU_TIO_CF_INFO_REGISTER;

18686 /**

18687 MSR used to access the CAM Filter Table

18688 **/

18689 #define MSR_XU_TIO_CF_TABLE 0x00000913

18690 /**

18691 VMX AVRR Remap Addr used in RR assist

18692 **/

18693 #define MSR_VMX_AVRR_REMAP 0x00000915

18694

18695 /**

18696 APIC Virtualization Range Register - Base address of virtual APIC

18697 **/

18698 #define MSR_AVRR_BASE 0x00000916

18699

18700 typedef union {

18701 ///

18702 /// Individual bit fields

18703 ///

18704 struct {

18705 UINT32 Rsvd0 : 11;

18706

18707 /* Bits[10:0], Access Type=RO, default=None*/

18708

18709 /* Reserved */

18710 UINT32 Vld : 1;

18711

18712 /* Bits[11:11], Access Type=RW, default=0x00000000*/

18713

18714 /* Enable bit for the AVRR */

18715 UINT32 Base0 : 20;

18716

18717 /* Bits[31:12], Access Type=RW, default=0x00000000*/

18718

18719 /* AVRR Base Address */

18720 UINT32 Base1 : 20;

18721

18722 /* Bits[51:32], Access Type=RW, default=0x00000000*/

18723

18724 /* AVRR Base Address */

18725 UINT32 Rsvd52 : 12;

18726

18727 /* Bits[63:52], Access Type=RO, default=None*/

18728

18729 /* Reserved */

18730

18731 } Bits;

18732

18733 UINT32 Uint32;

18734 UINT64 Uint64;

18735

18736 } MSR_AVRR_BASE_REGISTER;

18737 /**

18738 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18739 " seq has 4 instances in addresses range 0x917 to 0x91A"

18740 **/

18741 #define MSR_XU_RESERVED_1_1 0x00000917

18742 /**

18743 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18744 " seq has 4 instances in addresses range 0x917 to 0x91A"

18745 **/

18746 #define MSR_XU_RESERVED_2_2 0x00000918

18747 /**

18748 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18749 " seq has 4 instances in addresses range 0x917 to 0x91A"

18750 **/

18751 #define MSR_XU_RESERVED_3_3 0x00000919

18752 /**

18753 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18754 " seq has 4 instances in addresses range 0x917 to 0x91A"

18755 **/

18756 #define MSR_XU_RESERVED_4_4 0x0000091A

18757 /**

18758 PPPE Exception Handling Entrypoint

18759 **/

18760 #define MSR_EM_EXCEPTIONS_HANDLING_EIP 0x0000091B

18761 /**

18762 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18763 " seq has 4 instances in addresses range 0x91C to 0x91F"

18764 **/

18765 #define MSR_XU_RESERVED_5_5 0x0000091C

18766 /**

18767 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18768 " seq has 4 instances in addresses range 0x91C to 0x91F"

18769 **/

18770 #define MSR_XU_RESERVED_6_6 0x0000091D

18771 /**

18772 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18773 " seq has 4 instances in addresses range 0x91C to 0x91F"

18774 **/

18775 #define MSR_XU_RESERVED_7_7 0x0000091E

18776 /**

18777 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

18778 " seq has 4 instances in addresses range 0x91C to 0x91F"

18779 **/

18780 #define MSR_XU_RESERVED_8_8 0x0000091F

18781

18782 /**

18783 The who-am-I register is used by uCode to set up the APIC ID.

18784 This register is initialized by the PCU according to the socket configuration using the NcuPcuWHOAMI register.

18785 The who-am-i register returns a thread specific identifier, however some of the fields of this registers are shared between all threads as indicated by the fields description.

18786 **/

18787 #define MSR_NCUWHOAMI 0x00000920

18788

18789 typedef union {

18790 ///

18791 /// Individual bit fields

18792 ///

18793 struct {

18794 UINT32 Lpid : 3;

18795

18796 /* Bits[2:0], Access Type=RO_V, default=0x00000000*/

18797

18798 /*

18799 3-bit field. UBOX generates contiguous LPIDs for

18800 logical procsesors within an IDI agent. CPUs

18801 with fewer than 8 logical processors per IDI (eg

18802 ICL, ICX) see holes in the WHOAMI space. Ucode

18803 handles this as required (plug holes or live

18804 with it)

18805 */

18806 UINT32 Moduleid : 13;

18807

18808 /* Bits[15:3], Access Type=RO_V, default=0x00000000*/

18809

18810 /* Returns the Module Identification number. */

18811 UINT32 Packageid : 11;

18812

18813 /* Bits[26:16], Access Type=RW_V, default=0x00000000*/

18814

18815 /*

18816 Maps to the socketId straps; Can be programmed

18817 (MSR)

18818 */

18819 UINT32 Rsvd27 : 1;

18820

18821 /* Bits[27:27], Access Type=RO_V, default=0x00000000*/

18822

18823 /* Reserved */

18824 UINT32 Corenum : 3;

18825

18826 /* Bits[30:28], Access Type=RO, default=0x00000000*/

18827

18828 /*

18829 Indicates how many common APIC ID bits there are

18830 in the socket: 000: upto 8 cores 001: upto 16

18831 cores 010: upto 32 cores 011: upto 64 cores 100:

18832 upto 128 cores 101: upto 256 cores 110: upto 512

18833 cores 111: upto 1024 cores This field is used by

18834 uCode for correctly handling the number of

18835 variable bits in PID field.

18836 */

18837 UINT32 Bsp : 1;

18838

18839 /* Bits[31:31], Access Type=RO_V, default=0x00000000*/

18840

18841 /*

18842 Indicates to the core uCode that this thread

18843 should be made the BSP of the socket, .

18844 Selection among multi-socket BSP is done by BIOS

18845 SW. 0 : this thread should not be set as BSP 1 :

18846 this thread should be set as BSP

18847 */

18848

18849 } Bits;

18850

18851 UINT32 Uint32;

18852 UINT64 Uint64;

18853

18854 } MSR_NCUWHOAMI_REGISTER;

18855

18856 /**

18857

18858 **/

18859 #define MSR_RESOLVED_CORES_MASK 0x00000921

18860

18861 typedef union {

18862 ///

18863 /// Individual bit fields

18864 ///

18865 struct {

18866 UINT32 CoreMask : 8;

18867

18868 /* Bits[7:0], Access Type=RWS, default=0x00000000*/

18869

18870 /*

18871 The resolved IA core mask contains the

18872 functional (non fused-down) and non-defeatured

18873 IA cores. The mask is indexed by logical ID. It

18874 is normally contiguous, unless BIOS defeature is

18875 activated on a particular core. Ucode will read

18876 this mask in order to decide on BSP and APIC

18877 IDs. This field is determined by FW based on

18878 CSR_DESIRED_CORES[CORE_OFF_MASK] and

18879 PCU_CR_RESOLVED_CORES_MASK[FUSED_CORE_MASK].

18880 */

18881 UINT32 ThreadMask : 2;

18882

18883 /* Bits[9:8], Access Type=RWS, default=0x00000000*/

18884

18885 /*

18886 Thread Mask indicates which threads are enabled

18887 in the core. The LSB is the enable bit for

18888 Thread 0, whereas the MSB is the enable bit for

18889 Thread 1. This field is determined by FW based

18890 on CSR_DESIRED_CORES[SMT_DISABLE] and

18891 PCU_CR_RESOLVED_CORES_MASK[FUSED_THREAD_MASK].

18892 */

18893 UINT32 Rsvd10 : 6;

18894

18895 /* Bits[15:10], Access Type=RO, default=None*/

18896

18897 /* Reserved */

18898 UINT32 FusedCoreMask : 8;

18899

18900 /* Bits[23:16], Access Type=RWS, default=0x00000000*/

18901

18902 /* Vector of fused enabled IA cores in the package. */

18903 UINT32 FusedSmtCapability : 1;

18904

18905 /* Bits[24:24], Access Type=RWS, default=0x00000000*/

18906

18907 /*

18908 Fuse enabled threads in the package. 0b 1 thread

18909 1b 2 threads This value represents the inverted

18910 value of the HT_DIS fuse.

18911 */

18912 UINT32 Rsvd25 : 7;

18913

18914 /* Bits[31:25], Access Type=RO, default=None*/

18915

18916 /* Reserved */

18917

18918 } Bits;

18919

18920 UINT32 Uint32;

18921 UINT64 Uint64;

18922

18923 } MSR_RESOLVED_CORES_MASK_REGISTER;

18924

18925 /**

18926 Write only MSR for Xucode to modify the PDM header for GDXC messages

18927 **/

18928 #define MSR_PDM_HEADER 0x00000922

18929

18930 typedef union {

18931 ///

18932 /// Individual bit fields

18933 ///

18934 struct {

18935 UINT32 PacketType : 8;

18936

18937 /* Bits[7:0], Access Type=WO, default=0x00000000*/

18938

18939 /* GDXC Packet type */

18940 UINT32 PacketLength : 16;

18941

18942 /* Bits[23:8], Access Type=WO, default=0x00000000*/

18943

18944 /* GDXC Packet length */

18945 UINT32 Rsvd24 : 8;

18946

18947 /* Bits[31:24], Access Type=RO, default=None*/

18948

18949 /* Reserved */

18950 UINT32 Rsvd32 : 32;

18951

18952 /* Bits[63:32], Access Type=RO, default=None*/

18953

18954 /* Reserved */

18955

18956 } Bits;

18957

18958 UINT32 Uint32;

18959 UINT64 Uint64;

18960

18961 } MSR_PDM_HEADER_REGISTER;

18962

18963 /**

18964 Timer control bits for various MLC/APIC Timers

18965 **/

18966 #define MSR_MLC_PWR_MGMT_TIMER_CTRL 0x00000923

18967

18968 typedef union {

18969 ///

18970 /// Individual bit fields

18971 ///

18972 struct {

18973 UINT32 ApicTimerFreeze : 1;

18974

18975 /* Bits[0:0], Access Type=RO_V, default=0x00000000*/

18976

18977 /*

18978 Set to disable APIC Timer InitCnt and CfgCnt

18979 APIC Register updates. Does not directly freeze

18980 the APIC Timer. Supposed to freeze CTC in probe-

18981 mode, but bit is hardwired to 0. This bit is not

18982 used.

18983 */

18984 UINT32 VtTimerFreeze : 1;

18985

18986 /* Bits[1:1], Access Type=RW, default=0x00000000*/

18987

18988 /* Set to freeze VT timer in MLC */

18989 UINT32 AmcntFreeze : 1;

18990

18991 /* Bits[2:2], Access Type=RW, default=0x00000000*/

18992

18993 /* Set to freeze ACNT/MCNT Timers in MLC */

18994 UINT32 McntEnable : 1;

18995

18996 /* Bits[3:3], Access Type=RW, default=0x00000000*/

18997

18998 /*

18999 Set to enable MCNT Timer in MLC when the thread

19000 is asleep. This would be set for conditions like

19001 T-state throttling and P-state transitions where

19002 MCNT is supposed to continue to count even while

19003 the thread is asleep.

19004 */

19005 UINT32 Rsvd4 : 28;

19006

19007 /* Bits[31:4], Access Type=RO, default=None*/

19008

19009 /* Reserved */

19010

19011 } Bits;

19012

19013 UINT32 Uint32;

19014 UINT64 Uint64;

19015

19016 } MSR_MLC_PWR_MGMT_TIMER_CTRL_REGISTER;

19017 /**

19018 Scratch space exposed via MSR in PPPE

19019 **/

19020 #define MSR_PPPE_DOORBELL_EXIT_BITMAP 0x00000924

19021 /**

19022 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19023 " seq has 7 instances in addresses range 0x928 to 0x92E"

19024 **/

19025 #define MSR_XU_RESERVED_9_9 0x00000928

19026 /**

19027 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19028 " seq has 7 instances in addresses range 0x928 to 0x92E"

19029 **/

19030 #define MSR_XU_RESERVED_10_10 0x00000929

19031 /**

19032 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19033 " seq has 7 instances in addresses range 0x928 to 0x92E"

19034 **/

19035 #define MSR_XU_RESERVED_11_11 0x0000092A

19036 /**

19037 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19038 " seq has 7 instances in addresses range 0x928 to 0x92E"

19039 **/

19040 #define MSR_XU_RESERVED_12_12 0x0000092B

19041 /**

19042 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19043 " seq has 7 instances in addresses range 0x928 to 0x92E"

19044 **/

19045 #define MSR_XU_RESERVED_13_13 0x0000092C

19046 /**

19047 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19048 " seq has 7 instances in addresses range 0x928 to 0x92E"

19049 **/

19050 #define MSR_XU_RESERVED_14_14 0x0000092D

19051 /**

19052 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19053 " seq has 7 instances in addresses range 0x928 to 0x92E"

19054 **/

19055 #define MSR_XU_RESERVED_15_15 0x0000092E

19056

19057 /**

19058 Register decription

19059 **/

19060 #define MSR_PIC_LT_DOORBELL 0x0000092F

19061

19062 typedef union {

19063 ///

19064 /// Individual bit fields

19065 ///

19066 struct {

19067 UINT32 SenterEvent : 1;

19068

19069 /* Bits[0:0], Access Type=RW1S, default=0x00000000*/

19070

19071 /* Needs to be updated */

19072 UINT32 SenterContinueEvent : 1;

19073

19074 /* Bits[1:1], Access Type=RW1S, default=0x00000000*/

19075

19076 /* Needs to be updated */

19077 UINT32 SexitEvent : 1;

19078

19079 /* Bits[2:2], Access Type=RW1S, default=0x00000000*/

19080

19081 /* Needs to be updated */

19082 UINT32 SexitContinueEvent : 1;

19083

19084 /* Bits[3:3], Access Type=RW1S, default=0x00000000*/

19085

19086 /* Needs to be updated */

19087 UINT32 WakeupEvent : 1;

19088

19089 /* Bits[4:4], Access Type=RW1S, default=0x00000000*/

19090

19091 /* Needs to be updated */

19092 UINT32 Pppe : 3;

19093

19094 /* Bits[7:5], Access Type=RW1S, default=0x00000000*/

19095

19096 /* LT_DOORBELL[8:5] is reserved for PPPE. */

19097 UINT32 HsxReservedPfatEnter : 1;

19098

19099 /* Bits[8:8], Access Type=RW1S, default=0x00000000*/

19100

19101 /*

19102 LT_DOORBELL[8] is used by Haswell Server as the

19103 multi-socket PFAT ENTER DOORBELL.

19104 */

19105 UINT32 UcodeRsvd : 2;

19106

19107 /* Bits[10:9], Access Type=RW1S, default=0x00000000*/

19108

19109 /* LT_DOORBELL[10:9] is reserved for ucode usage. */

19110 UINT32 PfatWakeup : 1;

19111

19112 /* Bits[11:11], Access Type=RW1S, default=0x00000000*/

19113

19114 /*

19115 LT_DOORBELL[11] is used as the PFAT WAKEUP

19116 DOORBELL.

19117 */

19118 UINT32 RsvdExtLtdb12 : 5;

19119

19120 /* Bits[16:12], Access Type=RW1S, default=0x00000000*/

19121

19122 /* Needs to be updated */

19123 UINT32 NonWbLoadSeen : 1;

19124

19125 /* Bits[17:17], Access Type=RW1S, default=0x00000000*/

19126

19127 /* Needs to be updated */

19128 UINT32 MlcFillOccurred : 1;

19129

19130 /* Bits[18:18], Access Type=RW1S, default=0x00000000*/

19131

19132 /* Needs to be updated */

19133 UINT32 MlcEvictionOccurred : 1;

19134

19135 /* Bits[19:19], Access Type=RW1S, default=0x00000000*/

19136

19137 /* Needs to be updated */

19138 UINT32 HiddenLakeInterrupt : 1;

19139

19140 /* Bits[20:20], Access Type=RW1S, default=0x00000000*/

19141

19142 /* Hidden Lake Interrupt from NCU via serial bus */

19143 UINT32 Rsvd21 : 7;

19144

19145 /* Bits[27:21], Access Type=RW1S, default=0x00000000*/

19146

19147 /* Rsvd */

19148 UINT32 Xucode : 4;

19149

19150 /* Bits[31:28], Access Type=RW1S, default=0x00000000*/

19151

19152 /* Used by millicode */

19153

19154 } Bits;

19155

19156 UINT32 Uint32;

19157 UINT64 Uint64;

19158

19159 } MSR_PIC_LT_DOORBELL_REGISTER;

19160 /**

19161 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19162 " seq has 3 instances in addresses range 0x930 to 0x932"

19163 **/

19164 #define MSR_XU_RESERVED_16_16 0x00000930

19165 /**

19166 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19167 " seq has 3 instances in addresses range 0x930 to 0x932"

19168 **/

19169 #define MSR_XU_RESERVED_17_17 0x00000931

19170 /**

19171 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19172 " seq has 3 instances in addresses range 0x930 to 0x932"

19173 **/

19174 #define MSR_XU_RESERVED_18_18 0x00000932

19175

19176 /**

19177 PPPE will have read/write access to the FSCP_CR_VMCS_CACHE_BASE register for implementing the VMCS cache (i387450).

19178 Can be cut to 32-bits if not used by PPPE

19179 **/

19180 #define MSR_VMCS_CACHE_BASE 0x00000933

19181

19182 typedef union {

19183 ///

19184 /// Individual bit fields

19185 ///

19186 struct {

19187 UINT32 Address : 32;

19188

19189 /* Bits[31:0], Access Type=RW, default=None*/

19190

19191 /* Address of the VMCS cache for this thread */

19192 UINT32 Reserved32 : 32;

19193

19194 /* Bits[63:32], Access Type=RW, default=None*/

19195

19196 /* Unused */

19197

19198 } Bits;

19199

19200 UINT32 Uint32;

19201 UINT64 Uint64;

19202

19203 } MSR_VMCS_CACHE_BASE_REGISTER;

19204 /**

19205 Scratch Pad register BNS_CR_PSMBASE

19206 **/

19207 #define MSR_PSMI_BASE 0x00000934

19208

19209 /**

19210 Holds various SMX state

19211 **/

19212 #define MSR_LT_SMX_STATE 0x00000936

19213

19214 typedef union {

19215 ///

19216 /// Individual bit fields

19217 ///

19218 struct {

19219 UINT32 IlpFlag : 1;

19220

19221 /* Bits[0:0], Access Type=RW, default=None*/

19222

19223 /*

19224 Set during SENTER and SEXIT handshakes for the

19225 ILP thread. Also set during ENTERACCS

19226 */

19227 UINT32 SenterFlag : 1;

19228

19229 /* Bits[1:1], Access Type=RW, default=None*/

19230

19231 /* Set by SENTER for all threads, cleared by SEXIT */

19232 UINT32 AcmodeFlag : 1;

19233

19234 /* Bits[2:2], Access Type=RW, default=None*/

19235

19236 /* Set while AC mode is active */

19237 UINT32 ShutdownFlag : 1;

19238

19239 /* Bits[3:3], Access Type=RW, default=None*/

19240

19241 /*

19242 Setting this caues leacy shutdown to morph to

19243 LT-shutdown

19244 */

19245 UINT32 AuthenticationBypassFlag : 1;

19246

19247 /* Bits[4:4], Access Type=RW, default=None*/

19248

19249 /*

19250 Set to bypass AC-module authentication to speed

19251 up validation

19252 */

19253 UINT32 PsmiEnable : 1;

19254

19255 /* Bits[5:5], Access Type=RW, default=None*/

19256

19257 /* Set to enable PSMI events during AC-mode */

19258 UINT32 CramLoadBypass : 1;

19259

19260 /* Bits[6:6], Access Type=RW, default=None*/

19261

19262 /* Set to bypass CRAM load */

19263 UINT32 EnteraccsMacro : 1;

19264

19265 /* Bits[7:7], Access Type=RW, default=None*/

19266

19267 /* Set during ENTERACCS */

19268 UINT32 SavedGqDisDca : 1;

19269

19270 /* Bits[8:8], Access Type=RW, default=None*/

19271

19272 /* Saved value of the GQ DCA Disable bit */

19273 UINT32 LtAbortFlag : 1;

19274

19275 /* Bits[9:9], Access Type=RW, default=None*/

19276

19277 /* */

19278 UINT32 FitProcessing : 1;

19279

19280 /* Bits[10:10], Access Type=RW, default=None*/

19281

19282 /*

19283 Set during patch load and startup ACM launch

19284 while we're processing the FIT.

19285 */

19286 UINT32 SavedSmrrValid : 1;

19287

19288 /* Bits[11:11], Access Type=RW, default=None*/

19289

19290 /*

19291 Saved value of the SMRR valid bit. Used when

19292 unlocking TSEG.

19293 */

19294 UINT32 SavedSmrr2Valid : 1;

19295

19296 /* Bits[12:12], Access Type=RW, default=None*/

19297

19298 /*

19299 Saved value of the SMRR2 valid bit. Used when

19300 unlocking TSEG.

19301 */

19302 UINT32 SavedBiosDone : 1;

19303

19304 /* Bits[13:13], Access Type=RW, default=None*/

19305

19306 /* */

19307 UINT32 PackageBsp : 1;

19308

19309 /* Bits[14:14], Access Type=RW, default=None*/

19310

19311 /*

19312 Thread that will send the JOIN cycle to the

19313 chipset (RLP BSP) will also set this bit

19314 */

19315 UINT32 SvSenterEn : 1;

19316

19317 /* Bits[15:15], Access Type=RW, default=None*/

19318

19319 /*

19320 Enables extended state saving for SV during

19321 SENTER

19322 */

19323 UINT32 CrashCode : 5;

19324

19325 /* Bits[20:16], Access Type=RW, default=None*/

19326

19327 /*

19328 Holds the crash code for LT-shutdown. Written to

19329 LSBs of LT_CRASH register. Dont change position

19330 without CRASH_ACM_SVN

19331 */

19332 UINT32 CrashCodeValid : 1;

19333

19334 /* Bits[21:21], Access Type=RW, default=None*/

19335

19336 /* Indicates that the crash code is vaild */

19337 UINT32 PppeEnabled : 1;

19338

19339 /* Bits[22:22], Access Type=RW, default=None*/

19340

19341 /*

19342 Indicates whether PPPE was enabled prior to AC-

19343 mode

19344 */

19345 UINT32 SavedTf : 1;

19346

19347 /* Bits[23:23], Access Type=RW, default=None*/

19348

19349 /* Saved value of EFLAGS.TF during SEXIT */

19350 UINT32 TpmBypass : 1;

19351

19352 /* Bits[24:24], Access Type=RW, default=None*/

19353

19354 /* Set to bypass TPM registration during SENTER */

19355 UINT32 Hotadd : 1;

19356

19357 /* Bits[25:25], Access Type=RW, default=None*/

19358

19359 /* */

19360 UINT32 Reserved26 : 5;

19361

19362 /* Bits[30:26], Access Type=RW, default=None*/

19363

19364 /* */

19365 UINT32 LtPatchFlag : 1;

19366

19367 /* Bits[31:31], Access Type=RW, default=None*/

19368

19369 /* */

19370 UINT32 CrashAcmSvn : 8;

19371

19372 /* Bits[39:32], Access Type=RW, default=None*/

19373

19374 /*

19375 Used in case of Crash-Code = 16, otherwise

19376 zeroed. Should be 16 bits shifted left from the

19377 CRASH_CODE field.

19378 */

19379 UINT32 Reserved40 : 24;

19380

19381 /* Bits[63:40], Access Type=RW, default=None*/

19382

19383 /* */

19384

19385 } Bits;

19386

19387 UINT32 Uint32;

19388 UINT64 Uint64;

19389

19390 } MSR_LT_SMX_STATE_REGISTER;

19391 /**

19392 VMX timer current count

19393 **/

19394 #define MSR_MLC_VT_TIMER_COUNT 0x00000937

19395

19396 /**

19397 VMX timer control

19398 **/

19399 #define MSR_MLC_VT_TIMER_CONTROL 0x00000938

19400

19401 typedef union {

19402 ///

19403 /// Individual bit fields

19404 ///

19405 struct {

19406 UINT32 TimerEnable : 1;

19407

19408 /* Bits[0:0], Access Type=RW, default=0x00000000*/

19409

19410 /* Set to enable VT timer */

19411 UINT32 Rsvd1 : 31;

19412

19413 /* Bits[31:1], Access Type=RO, default=None*/

19414

19415 /* Reserved */

19416

19417 } Bits;

19418

19419 UINT32 Uint32;

19420 UINT64 Uint64;

19421

19422 } MSR_MLC_VT_TIMER_CONTROL_REGISTER;

19423

19424 /**

19425 SMM IO MISC INFO Register. 32 bit. (Mrm roctlregc/roapes/roiomiscinfoSM306L)

19426 **/

19427 #define MSR_IOMISCINFO 0x00000939

19428

19429 typedef union {

19430 ///

19431 /// Individual bit fields

19432 ///

19433 struct {

19434 UINT32 Smi : 1;

19435

19436 /* Bits[0:0], Access Type=RW_V, default=0x00000000*/

19437

19438 /* IO_SMI_POS */

19439 UINT32 IoLength : 3;

19440

19441 /* Bits[3:1], Access Type=RW, default=0x00000000*/

19442

19443 /* IO_LENGTH_MSB_POS:IO_LENGTH_LSB_POS */

19444 UINT32 IoType : 4;

19445

19446 /* Bits[7:4], Access Type=RW, default=0x00000000*/

19447

19448 /* IO_TYPE_MSB_POS:IO_TYPE_LSB_POS */

19449 UINT32 Rsvd8 : 8;

19450

19451 /* Bits[15:8], Access Type=RO, default=None*/

19452

19453 /* Reserved */

19454 UINT32 IoPort : 16;

19455

19456 /* Bits[31:16], Access Type=RW, default=0x00000000*/

19457

19458 /* IO_PORT_MSB_POS:IO_PORT_LSB_POS */

19459

19460 } Bits;

19461

19462 UINT32 Uint32;

19463 UINT64 Uint64;

19464

19465 } MSR_IOMISCINFO_REGISTER;

19466 /**

19467 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19468 " seq has 1 instances in addresses range 0x93B to 0x93B"

19469 **/

19470 #define MSR_XU_RESERVED_19_19 0x0000093B

19471 /**

19472 Memory address accessed by the last IO instruction.

19473 Used to communicate between io and SMI/PPPE.

19474 C6NoSave candidate

19475 **/

19476 #define MSR_IO_MEM_ADDR 0x0000093E

19477 /**

19478 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19479 " seq has 1 instances in addresses range 0x93F to 0x93F"

19480 **/

19481 #define MSR_XU_RESERVED_20_20 0x0000093F

19482

19483 /**

19484 Mode C - Protected Mode PagDir Pointers - 0

19485 " seq has 4 instances in addresses range 0x940 to 0x943"

19486 **/

19487 #define MSR_PDPTR_0_0 0x00000940

19488

19489 typedef union {

19490 ///

19491 /// Individual bit fields

19492 ///

19493 struct {

19494 UINT32 P : 1;

19495

19496 /* Bits[0:0], Access Type=RW, default=0x00000000*/

19497

19498 /* Page Directory Pointer Entry 0 - P bit */

19499 UINT32 Rsvd1 : 2;

19500

19501 /* Bits[2:1], Access Type=RO, default=None*/

19502

19503 /* Reserved */

19504 UINT32 Pwt : 1;

19505

19506 /* Bits[3:3], Access Type=RW, default=0x00000000*/

19507

19508 /* CR3 page level cache write through */

19509 UINT32 Pcd : 1;

19510

19511 /* Bits[4:4], Access Type=RW, default=0x00000000*/

19512

19513 /* CR3 page level cache disable */

19514 UINT32 Rsvd5 : 7;

19515

19516 /* Bits[11:5], Access Type=RO, default=None*/

19517

19518 /* Reserved */

19519 UINT32 Pdba0 : 20;

19520

19521 /* Bits[31:12], Access Type=RW, default=0x00000000*/

19522

19523 /* Page Directory Base Address */

19524 UINT32 Pdba1 : 20;

19525

19526 /* Bits[51:32], Access Type=RW, default=0x00000000*/

19527

19528 /* Page Directory Base Address */

19529 UINT32 Rsvd52 : 12;

19530

19531 /* Bits[63:52], Access Type=RO, default=None*/

19532

19533 /* Reserved */

19534

19535 } Bits;

19536

19537 UINT32 Uint32;

19538 UINT64 Uint64;

19539

19540 } MSR_PDPTR_0_0_REGISTER;

19541

19542 /**

19543 Mode C - Protected Mode PagDir Pointers - 0

19544 " seq has 4 instances in addresses range 0x940 to 0x943"

19545 **/

19546 #define MSR_PDPTR_1_1 0x00000941

19547

19548 typedef union {

19549 ///

19550 /// Individual bit fields

19551 ///

19552 struct {

19553 UINT32 P : 1;

19554

19555 /* Bits[0:0], Access Type=RW, default=0x00000000*/

19556

19557 /* Page Directory Pointer Entry 0 - P bit */

19558 UINT32 Rsvd1 : 2;

19559

19560 /* Bits[2:1], Access Type=RO, default=None*/

19561

19562 /* Reserved */

19563 UINT32 Pwt : 1;

19564

19565 /* Bits[3:3], Access Type=RW, default=0x00000000*/

19566

19567 /* CR3 page level cache write through */

19568 UINT32 Pcd : 1;

19569

19570 /* Bits[4:4], Access Type=RW, default=0x00000000*/

19571

19572 /* CR3 page level cache disable */

19573 UINT32 Rsvd5 : 7;

19574

19575 /* Bits[11:5], Access Type=RO, default=None*/

19576

19577 /* Reserved */

19578 UINT32 Pdba0 : 20;

19579

19580 /* Bits[31:12], Access Type=RW, default=0x00000000*/

19581

19582 /* Page Directory Base Address */

19583 UINT32 Pdba1 : 20;

19584

19585 /* Bits[51:32], Access Type=RW, default=0x00000000*/

19586

19587 /* Page Directory Base Address */

19588 UINT32 Rsvd52 : 12;

19589

19590 /* Bits[63:52], Access Type=RO, default=None*/

19591

19592 /* Reserved */

19593

19594 } Bits;

19595

19596 UINT32 Uint32;

19597 UINT64 Uint64;

19598

19599 } MSR_PDPTR_1_1_REGISTER;

19600

19601 /**

19602 Mode C - Protected Mode PagDir Pointers - 0

19603 " seq has 4 instances in addresses range 0x940 to 0x943"

19604 **/

19605 #define MSR_PDPTR_2_2 0x00000942

19606

19607 typedef union {

19608 ///

19609 /// Individual bit fields

19610 ///

19611 struct {

19612 UINT32 P : 1;

19613

19614 /* Bits[0:0], Access Type=RW, default=0x00000000*/

19615

19616 /* Page Directory Pointer Entry 0 - P bit */

19617 UINT32 Rsvd1 : 2;

19618

19619 /* Bits[2:1], Access Type=RO, default=None*/

19620

19621 /* Reserved */

19622 UINT32 Pwt : 1;

19623

19624 /* Bits[3:3], Access Type=RW, default=0x00000000*/

19625

19626 /* CR3 page level cache write through */

19627 UINT32 Pcd : 1;

19628

19629 /* Bits[4:4], Access Type=RW, default=0x00000000*/

19630

19631 /* CR3 page level cache disable */

19632 UINT32 Rsvd5 : 7;

19633

19634 /* Bits[11:5], Access Type=RO, default=None*/

19635

19636 /* Reserved */

19637 UINT32 Pdba0 : 20;

19638

19639 /* Bits[31:12], Access Type=RW, default=0x00000000*/

19640

19641 /* Page Directory Base Address */

19642 UINT32 Pdba1 : 20;

19643

19644 /* Bits[51:32], Access Type=RW, default=0x00000000*/

19645

19646 /* Page Directory Base Address */

19647 UINT32 Rsvd52 : 12;

19648

19649 /* Bits[63:52], Access Type=RO, default=None*/

19650

19651 /* Reserved */

19652

19653 } Bits;

19654

19655 UINT32 Uint32;

19656 UINT64 Uint64;

19657

19658 } MSR_PDPTR_2_2_REGISTER;

19659

19660 /**

19661 Mode C - Protected Mode PagDir Pointers - 0

19662 " seq has 4 instances in addresses range 0x940 to 0x943"

19663 **/

19664 #define MSR_PDPTR_3_3 0x00000943

19665

19666 typedef union {

19667 ///

19668 /// Individual bit fields

19669 ///

19670 struct {

19671 UINT32 P : 1;

19672

19673 /* Bits[0:0], Access Type=RW, default=0x00000000*/

19674

19675 /* Page Directory Pointer Entry 0 - P bit */

19676 UINT32 Rsvd1 : 2;

19677

19678 /* Bits[2:1], Access Type=RO, default=None*/

19679

19680 /* Reserved */

19681 UINT32 Pwt : 1;

19682

19683 /* Bits[3:3], Access Type=RW, default=0x00000000*/

19684

19685 /* CR3 page level cache write through */

19686 UINT32 Pcd : 1;

19687

19688 /* Bits[4:4], Access Type=RW, default=0x00000000*/

19689

19690 /* CR3 page level cache disable */

19691 UINT32 Rsvd5 : 7;

19692

19693 /* Bits[11:5], Access Type=RO, default=None*/

19694

19695 /* Reserved */

19696 UINT32 Pdba0 : 20;

19697

19698 /* Bits[31:12], Access Type=RW, default=0x00000000*/

19699

19700 /* Page Directory Base Address */

19701 UINT32 Pdba1 : 20;

19702

19703 /* Bits[51:32], Access Type=RW, default=0x00000000*/

19704

19705 /* Page Directory Base Address */

19706 UINT32 Rsvd52 : 12;

19707

19708 /* Bits[63:52], Access Type=RO, default=None*/

19709

19710 /* Reserved */

19711

19712 } Bits;

19713

19714 UINT32 Uint32;

19715 UINT64 Uint64;

19716

19717 } MSR_PDPTR_3_3_REGISTER;

19718 /**

19719 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19720 " seq has 10 instances in addresses range 0x944 to 0x94D"

19721 **/

19722 #define MSR_XU_RESERVED_21_21 0x00000944

19723 /**

19724 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19725 " seq has 10 instances in addresses range 0x944 to 0x94D"

19726 **/

19727 #define MSR_XU_RESERVED_22_22 0x00000945

19728 /**

19729 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19730 " seq has 10 instances in addresses range 0x944 to 0x94D"

19731 **/

19732 #define MSR_XU_RESERVED_23_23 0x00000946

19733 /**

19734 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19735 " seq has 10 instances in addresses range 0x944 to 0x94D"

19736 **/

19737 #define MSR_XU_RESERVED_24_24 0x00000947

19738 /**

19739 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19740 " seq has 10 instances in addresses range 0x944 to 0x94D"

19741 **/

19742 #define MSR_XU_RESERVED_25_25 0x00000948

19743 /**

19744 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19745 " seq has 10 instances in addresses range 0x944 to 0x94D"

19746 **/

19747 #define MSR_XU_RESERVED_26_26 0x00000949

19748 /**

19749 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19750 " seq has 10 instances in addresses range 0x944 to 0x94D"

19751 **/

19752 #define MSR_XU_RESERVED_27_27 0x0000094A

19753 /**

19754 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19755 " seq has 10 instances in addresses range 0x944 to 0x94D"

19756 **/

19757 #define MSR_XU_RESERVED_28_28 0x0000094B

19758 /**

19759 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19760 " seq has 10 instances in addresses range 0x944 to 0x94D"

19761 **/

19762 #define MSR_XU_RESERVED_29_29 0x0000094C

19763 /**

19764 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

19765 " seq has 10 instances in addresses range 0x944 to 0x94D"

19766 **/

19767 #define MSR_XU_RESERVED_30_30 0x0000094D

19768

19769 /**

19770

19771 **/

19772 #define MSR_XU_ALL_CORES_POISON 0x0000094E

19773

19774 typedef union {

19775 ///

19776 /// Individual bit fields

19777 ///

19778 struct {

19779 UINT32 PoisonEn : 1;

19780

19781 /* Bits[0:0], Access Type=RW, default=None*/

19782

19783 /* reserved */

19784 UINT32 ViralEn : 1;

19785

19786 /* Bits[1:1], Access Type=RW, default=None*/

19787

19788 /* reserved */

19789 UINT32 RasSgxOptin : 1;

19790

19791 /* Bits[2:2], Access Type=RW, default=None*/

19792

19793 /* reserved */

19794 UINT32 Rsrvd3 : 29;

19795

19796 /* Bits[31:3], Access Type=RW, default=None*/

19797

19798 /* reserved */

19799 UINT32 Rsrvd32 : 32;

19800

19801 /* Bits[63:32], Access Type=RW, default=None*/

19802

19803 /* reserved */

19804

19805 } Bits;

19806

19807 UINT32 Uint32;

19808 UINT64 Uint64;

19809

19810 } MSR_XU_ALL_CORES_POISON_REGISTER;

19811 /**

19812

19813 **/

19814 #define MSR_XU_OPTIN 0x0000094F

19815

19816 /**

19817 Each bit is command from xucode for specific action. Not really a register.

19818 **/

19819 #define MSR_XUCODE_UCODE_COMMAND 0x00000950

19820

19821 typedef union {

19822 ///

19823 /// Individual bit fields

19824 ///

19825 struct {

19826 UINT32 EnableEmxrr : 1;

19827

19828 /* Bits[0:0], Access Type=RW, default=None*/

19829

19830 /* set EMXRR_enable at PMH_CR_RR_MODE[7] */

19831 UINT32 UpdateCurrentSeSvn : 1;

19832

19833 /* Bits[1:1], Access Type=RW, default=None*/

19834

19835 /* Updates CURRENT_SE_SVN */

19836 UINT32 LockSeSvn : 1;

19837

19838 /* Bits[2:2], Access Type=RW, default=None*/

19839

19840 /* Sets and lock R_LAST_PATCH_SVN */

19841 UINT32 SignalMckindEvent : 1;

19842

19843 /* Bits[3:3], Access Type=RW, default=None*/

19844

19845 /*

19846 broadcast the MCKIND to all threads in the

19847 package will not be formally checked

19848 */

19849 UINT32 DisablePdrCopy : 1;

19850

19851 /* Bits[4:4], Access Type=RW, default=None*/

19852

19853 /*

19854 Set FSCP_CR_TAP_MISC.DISABLE_PDR_COPY per

19855 Skylake issue 1350825

19856 */

19857 UINT32 SetSmmDelayed : 1;

19858

19859 /* Bits[5:5], Access Type=RW, default=None*/

19860

19861 /*

19862 invoke set_smm_delayed_bit ucode routine per

19863 Skylake issue 1351518

19864 */

19865 UINT32 ClearSmmDelayed : 1;

19866

19867 /* Bits[6:6], Access Type=RW, default=None*/

19868

19869 /*

19870 invoke clear_smm_delayed_bit ucode routine per

19871 Skylake issue 1351518

19872 */

19873 UINT32 Reserved7 : 24;

19874

19875 /* Bits[30:7], Access Type=RW, default=None*/

19876

19877 /* Reserved */

19878 UINT32 SetSgxSecureEn : 1;

19879

19880 /* Bits[31:31], Access Type=RW, default=None*/

19881

19882 /* For mcheck to set sgx_secure_en */

19883

19884 } Bits;

19885

19886 UINT32 Uint32;

19887 UINT64 Uint64;

19888

19889 } MSR_XUCODE_UCODE_COMMAND_REGISTER;

19890

19891 /**

19892 An uncore register indicating that SE is fully installed. Used by CPUID and preamble need to check the option to cache it for each core

19893 **/

19894 #define MSR_GLOBAL_SE_ENABLE 0x00000951

19895

19896 typedef union {

19897 ///

19898 /// Individual bit fields

19899 ///

19900 struct {

19901 UINT32 SeEnable : 1;

19902

19903 /* Bits[0:0], Access Type=RW, default=None*/

19904

19905 /* enable bit for this thread */

19906 UINT32 Lock : 1;

19907

19908 /* Bits[1:1], Access Type=RW, default=None*/

19909

19910 /* this acts as global SE disable */

19911 UINT32 Reserved2 : 30;

19912

19913 /* Bits[31:2], Access Type=RW, default=None*/

19914

19915 /* */

19916

19917 } Bits;

19918

19919 UINT32 Uint32;

19920 UINT64 Uint64;

19921

19922 } MSR_GLOBAL_SE_ENABLE_REGISTER;

19923

19924 /**

19925

19926 **/

19927 #define MSR_PKG_SE_SVN 0x00000952

19928

19929 typedef union {

19930 ///

19931 /// Individual bit fields

19932 ///

19933 struct {

19934 UINT32 PrResetSvn : 8;

19935

19936 /* Bits[7:0], Access Type=RW, default=None*/

19937

19938 /* Reflection of PR_RESET_SVN for XuCode access */

19939 UINT32 RLastPatchSvn0 : 24;

19940

19941 /* Bits[31:8], Access Type=RW, default=None*/

19942

19943 /*

19944 Reflection of R_LAST_PATCH_SVN[63:8] for XuCode

19945 access

19946 */

19947 UINT32 RLastPatchSvn1 : 32;

19948

19949 /* Bits[63:32], Access Type=RW, default=None*/

19950

19951 /*

19952 Reflection of R_LAST_PATCH_SVN[63:8] for XuCode

19953 access

19954 */

19955

19956 } Bits;

19957

19958 UINT32 Uint32;

19959 UINT64 Uint64;

19960

19961 } MSR_PKG_SE_SVN_REGISTER;

19962

19963 /**

19964 Enclave Linear Space Range Register - Physical Base Control Register

19965 **/

19966 #define MSR_ELSRR_BASE 0x00000955

19967

19968 typedef union {

19969 ///

19970 /// Individual bit fields

19971 ///

19972 struct {

19973 UINT32 Rsvd0 : 12;

19974

19975 /* Bits[11:0], Access Type=RO, default=None*/

19976

19977 /* Reserved */

19978 UINT32 Base0 : 20;

19979

19980 /* Bits[31:12], Access Type=RW, default=0x00000000*/

19981

19982 /* ELSRR Base Address */

19983 UINT32 Base1 : 25;

19984

19985 /* Bits[56:32], Access Type=RW, default=0x00000000*/

19986

19987 /* ELSRR Base Address */

19988 UINT32 Rsvd57 : 7;

19989

19990 /* Bits[63:57], Access Type=RO, default=None*/

19991

19992 /* Reserved */

19993

19994 } Bits;

19995

19996 UINT32 Uint32;

19997 UINT64 Uint64;

19998

19999 } MSR_ELSRR_BASE_REGISTER;

20000

20001 /**

20002 Enclave Linear Space Range Register - Physical Mask Control Register

20003 **/

20004 #define MSR_ELSRR_MASK 0x00000956

20005

20006 typedef union {

20007 ///

20008 /// Individual bit fields

20009 ///

20010 struct {

20011 UINT32 Rsvd0 : 12;

20012

20013 /* Bits[11:0], Access Type=RO, default=None*/

20014

20015 /* Reserved */

20016 UINT32 Mask0 : 20;

20017

20018 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20019

20020 /* ELSRR MASK bits */

20021 UINT32 Mask1 : 25;

20022

20023 /* Bits[56:32], Access Type=RW, default=0x00000000*/

20024

20025 /* ELSRR MASK bits */

20026 UINT32 Rsvd57 : 7;

20027

20028 /* Bits[63:57], Access Type=RO, default=None*/

20029

20030 /* Reserved */

20031

20032 } Bits;

20033

20034 UINT32 Uint32;

20035 UINT64 Uint64;

20036

20037 } MSR_ELSRR_MASK_REGISTER;

20038

20039 /**

20040 TCS Physical Address. Pointer to TCS structure, to be used at ASEX

20041 **/

20042 #define MSR_TCS_PA 0x00000958

20043

20044 typedef union {

20045 ///

20046 /// Individual bit fields

20047 ///

20048 struct {

20049 UINT32 TcsPhysAddr0 : 32;

20050

20051 /* Bits[31:0], Access Type=RW, default=None*/

20052

20053 /* */

20054 UINT32 TcsPhysAddr1 : 20;

20055

20056 /* Bits[51:32], Access Type=RW, default=None*/

20057

20058 /* */

20059 UINT32 RsvdB52 : 12;

20060

20061 /* Bits[63:52], Access Type=RW, default=None*/

20062

20063 /* */

20064

20065 } Bits;

20066

20067 UINT32 Uint32;

20068 UINT64 Uint64;

20069

20070 } MSR_TCS_PA_REGISTER;

20071

20072 /**

20073 Holds SE Active SECS

20074 **/

20075 #define MSR_SECS_SID 0x00000959

20076

20077 typedef union {

20078 ///

20079 /// Individual bit fields

20080 ///

20081 struct {

20082 UINT32 EnclaveMode : 1;

20083

20084 /* Bits[0:0], Access Type=RW, default=0x00000000*/

20085

20086 /* The thread is in Enclave Mode */

20087 UINT32 Rsvd1 : 11;

20088

20089 /* Bits[11:1], Access Type=RO, default=None*/

20090

20091 /* Reserved */

20092 UINT32 ActiveSecs0 : 20;

20093

20094 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20095

20096 /* ACTIVE_SECS */

20097 UINT32 ActiveSecs1 : 20;

20098

20099 /* Bits[51:32], Access Type=RW, default=0x00000000*/

20100

20101 /* ACTIVE_SECS */

20102 UINT32 Rsvd52 : 12;

20103

20104 /* Bits[63:52], Access Type=RO, default=None*/

20105

20106 /* Reserved */

20107

20108 } Bits;

20109

20110 UINT32 Uint32;

20111 UINT64 Uint64;

20112

20113 } MSR_SECS_SID_REGISTER;

20114 /**

20115 This is a Read-Only xucode MSR.

20116 **/

20117 #define MSR_FUSE_KEY1_0 0x00000960

20118 /**

20119 This is a Read-Only xucode MSR.

20120 **/

20121 #define MSR_FUSE_KEY1_1 0x00000961

20122

20123 /**

20124 Millicode Memory Range Register - Physical Base Control Register

20125 **/

20126 #define MSR_EMRR_BASE 0x00000962

20127

20128 typedef union {

20129 ///

20130 /// Individual bit fields

20131 ///

20132 struct {

20133 UINT32 Memtype : 3;

20134

20135 /* Bits[2:0], Access Type=RW, default=0x00000000*/

20136

20137 /* EMRR BASE MemType */

20138 UINT32 Rsvd3 : 9;

20139

20140 /* Bits[11:3], Access Type=RO, default=None*/

20141

20142 /* Reserved */

20143 UINT32 Base0 : 20;

20144

20145 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20146

20147 /* EMRR Base Address */

20148 UINT32 Base1 : 20;

20149

20150 /* Bits[51:32], Access Type=RW, default=0x00000000*/

20151

20152 /* EMRR Base Address */

20153 UINT32 Rsvd52 : 12;

20154

20155 /* Bits[63:52], Access Type=RO, default=None*/

20156

20157 /* Reserved */

20158

20159 } Bits;

20160

20161 UINT32 Uint32;

20162 UINT64 Uint64;

20163

20164 } MSR_EMRR_BASE_REGISTER;

20165

20166 /**

20167 Millicode Memory Range Register - Physical Mask Control Register

20168 **/

20169 #define MSR_EMRR_MASK 0x00000963

20170

20171 typedef union {

20172 ///

20173 /// Individual bit fields

20174 ///

20175 struct {

20176 UINT32 Rsvd0 : 9;

20177

20178 /* Bits[8:0], Access Type=RO, default=None*/

20179

20180 /* Reserved */

20181 UINT32 Assist : 1;

20182

20183 /* Bits[9:9], Access Type=RW, default=0x00000000*/

20184

20185 /*

20186 If set, EMRR is in assist-mode - else in page

20187 abort-mode (defeature only)

20188 */

20189 UINT32 L : 1;

20190

20191 /* Bits[10:10], Access Type=RW, default=0x00000000*/

20192

20193 /* Lock bit for the EMRR */

20194 UINT32 Vld : 1;

20195

20196 /* Bits[11:11], Access Type=RW, default=0x00000000*/

20197

20198 /* Enable bit for the EMRR */

20199 UINT32 Mask0 : 20;

20200

20201 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20202

20203 /* EMRR MASK bits */

20204 UINT32 Mask1 : 20;

20205

20206 /* Bits[51:32], Access Type=RW, default=0x00000000*/

20207

20208 /* EMRR MASK bits */

20209 UINT32 Rsvd52 : 12;

20210

20211 /* Bits[63:52], Access Type=RO, default=None*/

20212

20213 /* Reserved */

20214

20215 } Bits;

20216

20217 UINT32 Uint32;

20218 UINT64 Uint64;

20219

20220 } MSR_EMRR_MASK_REGISTER;

20221

20222 /**

20223 Xucode Memory Range Register - Physical Base Control Register

20224 **/

20225 #define MSR_EMXRR_BASE 0x00000964

20226

20227 typedef union {

20228 ///

20229 /// Individual bit fields

20230 ///

20231 struct {

20232 UINT32 Rsvd0 : 12;

20233

20234 /* Bits[11:0], Access Type=RO, default=None*/

20235

20236 /* Reserved */

20237 UINT32 Base0 : 20;

20238

20239 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20240

20241 /* EMXRR Base Address */

20242 UINT32 Base1 : 20;

20243

20244 /* Bits[51:32], Access Type=RW, default=0x00000000*/

20245

20246 /* EMXRR Base Address */

20247 UINT32 Rsvd52 : 12;

20248

20249 /* Bits[63:52], Access Type=RO, default=None*/

20250

20251 /* Reserved */

20252

20253 } Bits;

20254

20255 UINT32 Uint32;

20256 UINT64 Uint64;

20257

20258 } MSR_EMXRR_BASE_REGISTER;

20259

20260 /**

20261 Xucode Memory Range Register - Physical Mask Control Register

20262 **/

20263 #define MSR_EMXRR_MASK 0x00000965

20264

20265 typedef union {

20266 ///

20267 /// Individual bit fields

20268 ///

20269 struct {

20270 UINT32 Rsvd0 : 10;

20271

20272 /* Bits[9:0], Access Type=RO, default=None*/

20273

20274 /* Reserved */

20275 UINT32 L : 1;

20276

20277 /* Bits[10:10], Access Type=RW, default=0x00000000*/

20278

20279 /* Lock bit for the EMXRR */

20280 UINT32 Rsvd11 : 1;

20281

20282 /* Bits[11:11], Access Type=RO, default=None*/

20283

20284 /* Reserved */

20285 UINT32 Mask0 : 20;

20286

20287 /* Bits[31:12], Access Type=RW, default=0x00000000*/

20288

20289 /* EMXRR MASK bits */

20290 UINT32 Mask1 : 20;

20291

20292 /* Bits[51:32], Access Type=RW, default=0x00000000*/

20293

20294 /* EMXRR MASK bits */

20295 UINT32 Rsvd52 : 12;

20296

20297 /* Bits[63:52], Access Type=RO, default=None*/

20298

20299 /* Reserved */

20300

20301 } Bits;

20302

20303 UINT32 Uint32;

20304 UINT64 Uint64;

20305

20306 } MSR_EMXRR_MASK_REGISTER;

20307 /**

20308 This define is used to reserve some MSR addresses for XuCode. Ucode would have a dedicated handler for these MSRs

20309 " seq has 1 instances in addresses range 0x967 to 0x967"

20310 **/

20311 #define MSR_XU_RESERVED_31_31 0x00000967

20312 /**

20313 This is uncore SCP. RO MSR to provide 128 bits of external entropy used for key derivation.

20314 **/

20315 #define MSR_MEE_SETUP 0x0000096A

20316

20317 /**

20318

20319 **/

20320 #define MSR_PPPE_TAP_STATUS 0x0000096B

20321

20322 typedef union {

20323 ///

20324 /// Individual bit fields

20325 ///

20326 struct {

20327 UINT32 DebugUnlockMode : 1;

20328

20329 /* Bits[0:0], Access Type=RW, default=None*/

20330

20331 /* debug unlock mode */

20332 UINT32 Rsrvd1 : 31;

20333

20334 /* Bits[31:1], Access Type=RW, default=None*/

20335

20336 /* reserved */

20337 UINT32 Rsvd32 : 32;

20338

20339 /* Bits[63:32], Access Type=RO, default=None*/

20340

20341 /* Reserved */

20342

20343 } Bits;

20344

20345 UINT32 Uint32;

20346 UINT64 Uint64;

20347

20348 } MSR_PPPE_TAP_STATUS_REGISTER;

20349

20350 /**

20351 MEE init register

20352 **/

20353 #define MSR_EE_INIT 0x0000096C

20354

20355 typedef union {

20356 ///

20357 /// Individual bit fields

20358 ///

20359 struct {

20360 UINT32 Lock : 1;

20361

20362 /* Bits[0:0], Access Type=RW, default=0x00000000*/

20363

20364 /* Lock bit. */

20365 UINT32 Rsvd1 : 31;

20366

20367 /* Bits[31:1], Access Type=RO, default=None*/

20368

20369 /* Reserved */

20370

20371 } Bits;

20372

20373 UINT32 Uint32;

20374 UINT64 Uint64;

20375

20376 } MSR_EE_INIT_REGISTER;

20377

20378 /**

20379 Holds XCR0 and XSAVE Compaction Vector (used for XMODIFIED optimization check)

20380 **/

20381 #define MSR_XCR0 0x0000096D

20382

20383 typedef union {

20384 ///

20385 /// Individual bit fields

20386 ///

20387 struct {

20388 UINT32 X87 : 1;

20389

20390 /* Bits[0:0], Access Type=RW, default=None*/

20391

20392 /* Bit 0 => FP */

20393 UINT32 Sse : 1;

20394

20395 /* Bits[1:1], Access Type=RW, default=None*/

20396

20397 /* Bit 1 => SSE */

20398 UINT32 Gsse : 1;

20399

20400 /* Bits[2:2], Access Type=RW, default=None*/

20401

20402 /* Bit 2 => GSSE */

20403 UINT32 PlBndregs : 1;

20404

20405 /* Bits[3:3], Access Type=RW, default=None*/

20406

20407 /* Bit 3 => PL BNDREGS */

20408 UINT32 PlBndcfs : 1;

20409

20410 /* Bits[4:4], Access Type=RW, default=None*/

20411

20412 /* Bit 4 => PL BNDCFS */

20413 UINT32 Kmask : 1;

20414

20415 /* Bits[5:5], Access Type=RW, default=None*/

20416

20417 /* Bit 5 => KMASK */

20418 UINT32 Avx3150 : 1;

20419

20420 /* Bits[6:6], Access Type=RW, default=None*/

20421

20422 /* Bit 6 => AVX3(15:0) */

20423 UINT32 Avx33116 : 1;

20424

20425 /* Bits[7:7], Access Type=RW, default=None*/

20426

20427 /* Bit 7 => AVX3(31:16) */

20428 UINT32 RsvdIaXssRtit8 : 1;

20429

20430 /* Bits[8:8], Access Type=RW, default=None*/

20431

20432 /*

20433 Bit 8 is reserved because of use as RTIT bit in

20434 IA_XSS.

20435 */

20436 UINT32 Pkru : 1;

20437

20438 /* Bits[9:9], Access Type=RW, default=None*/

20439

20440 /* Bit 9 => Page Protection Keys User. */

20441 UINT32 Rsvd10 : 22;

20442

20443 /* Bits[31:10], Access Type=RW, default=None*/

20444

20445 /* Unused bits. */

20446 UINT32 Rsvd32 : 32;

20447

20448 /* Bits[63:32], Access Type=RW, default=None*/

20449

20450 /* Unused bits. */

20451

20452 } Bits;

20453

20454 UINT32 Uint32;

20455 UINT64 Uint64;

20456

20457 } MSR_XCR0_REGISTER;

20458 /**

20459 PCHSGXID 0 exposed in PCH by CSME

20460 **/

20461 #define MSR_SGX_RDPCHSGXID_0 0x00000970

20462 /**

20463 PCHSGXID 1 exposed in PCH by CSME

20464 **/

20465 #define MSR_SGX_RDPCHSGXID_1 0x00000971

20466 /**

20467 MCHECK XuCode register that holds address of uncore register to be written

20468 **/

20469 #define MSR_MCHECK_CPU_REGISTER_ADDRESS 0x00000972

20470 /**

20471 Virtual MSR to will write data to an Uncore CR.

20472 The write is invoked by MCHECK flow.

20473 CR address is taken from MSR 0x972

20474 **/

20475 #define MSR_MCHECK_CPU_REGISTER_DATA 0x00000973

20476 /**

20477 MSR to read/write ubox LOW TME EPHEMERAL KEY

20478 **/

20479 #define MSR_BIOS_TME_KEY_0 0x00000992

20480 /**

20481 MSR to read/write ubox HIGH TME EPHEMERAL KEY

20482 **/

20483 #define MSR_BIOS_TME_KEY_1 0x00000993

20484 /**

20485 Virtual MSR to read TME_ACTIVATE[MK_TME_KEYID_BITS] from SoC.

20486 Write with EDX:EAX == 0 will translate the above value into PMH mask register.

20487 **/

20488 #define MSR_CORE_MKTME_ACTIVATION 0x000009FF

20489

20490 /**

20491 Various controls

20492 **/

20493 #define MSR_IO_BW_P_LIMIT_OVERRIDE 0x00000A00

20494

20495 typedef union {

20496 ///

20497 /// Individual bit fields

20498 ///

20499 struct {

20500 UINT32 FloorOffset : 6;

20501

20502 /* Bits[5:0], Access Type=RW_V, default=0x00000000*/

20503

20504 /*

20505 This value specifies the number of bins below P1

20506 at which the freq floor will be set to.

20507 Frequency Floor = P1 - 100 * OVRD_VALUE By

20508 default: Freq floor wil lbe set to P1.

20509 */

20510 UINT32 Rsvd6 : 2;

20511

20512 /* Bits[7:6], Access Type=RW_V, default=0x00000000*/

20513

20514 /* */

20515 UINT32 FloorEnable : 1;

20516

20517 /* Bits[8:8], Access Type=RW_V, default=0x00000000*/

20518

20519 /* Overrides the Frequency Floor */

20520 UINT32 Rsvd9 : 23;

20521

20522 /* Bits[31:9], Access Type=RW_V, default=0x00000000*/

20523

20524 /* */

20525

20526 } Bits;

20527

20528 UINT32 Uint32;

20529 UINT64 Uint64;

20530

20531 } MSR_IO_BW_P_LIMIT_OVERRIDE_REGISTER;

20532

20533 /**

20534 This register effectively governs all major power saving engines and hueristics on the die.

20535 **/

20536 #define MSR_ENERGY_PERF_BIAS_CONFIG 0x00000A01

20537

20538 typedef union {

20539 ///

20540 /// Individual bit fields

20541 ///

20542 struct {

20543 UINT32 WorkldConfig : 3;

20544

20545 /* Bits[2:0], Access Type=RW_V, default=0x00000000*/

20546

20547 /*

20548 This allows optimization for the workload

20549 characterization. The three options for

20550 selection: 000 - UMA - default 001 -NUMA

20551 optimized - use NUMA table for Intel UPI 010 -

20552 I/O sensitive - use IO BW P limit table 011 -

20553 NUMA and I/O - use both Intel UPI and IO BW P

20554 Lmit table This field indicates which table to

20555 use.

20556 */

20557 UINT32 AltEnergyPerfBias : 4;

20558

20559 /* Bits[6:3], Access Type=RW_V, default=0x00000000*/

20560

20561 /* */

20562 UINT32 Rsvd7 : 5;

20563

20564 /* Bits[11:7], Access Type=RO, default=None*/

20565

20566 /* Reserved */

20567 UINT32 P0TotalTimeThresholdHigh : 6;

20568

20569 /* Bits[17:12], Access Type=RW_V, default=0x00000000*/

20570

20571 /*

20572 The HW switching mechanism ENABLES the

20573 performance setting (0) when the total P0 time

20574 is greater than this threshhold.

20575 */

20576 UINT32 P0TotalTimeThresholdLow : 6;

20577

20578 /* Bits[23:18], Access Type=RW_V, default=0x00000000*/

20579

20580 /*

20581 The HW switching mechanism DISABLES the

20582 performance setting (0) when the total P0 time

20583 is less than this threshhold. It hen uses the

20584 over rides when specified, otherwise it uses the

20585 socket_IA32_Performance_Power_Bias.

20586 */

20587 UINT32 AvgTimeWindow : 8;

20588

20589 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

20590

20591 /*

20592 This field is used to control the decay constant

20593 of the EWMA filter that is applied to core C0

20594 and P0 time. The 8-bit value is distributed into

20595 a 4-bit mantissa (M = Bits[7:4]) and 4-bit

20596 exponent (E = Bits[3:0]). The formula for

20597 computing the decay constant is 1-alpha =

20598 (M+17)/pow(2,E+5). The filter is then applied as

20599 follows: Y[n] = alpha*Y[n-1] + (1-alpha)*X[n],

20600 where Y[n] is the output, X[n] is the input, and

20601 n is the time step (in milliseconds).

20602 */

20603

20604 } Bits;

20605

20606 UINT32 Uint32;

20607 UINT64 Uint64;

20608

20609 } MSR_ENERGY_PERF_BIAS_CONFIG_REGISTER;

20610

20611 /**

20612 This register is intended for OS usage. It enables the OS

20613 to write an LTR value if they choose to participate in the LTR process.

20614 This register includes parameters that PCODE will use to override information

20615 received from PCI Express via LTR messages.

20616 Pcode will choose this value, or PCIE_LTR_OVRD, or actual LTR values from IIO

20617 depending on selection function in POWER_CTL uCR

20618 PCODE will sample this register at slow loop.

20619 This register needs to be exposed as MSR - details TBD

20620 **/

20621 #define MSR_SW_LTR_OVRD 0x00000A02

20622

20623 typedef union {

20624 ///

20625 /// Individual bit fields

20626 ///

20627 struct {

20628 UINT32 Nstl : 10;

20629

20630 /* Bits[9:0], Access Type=RW, default=0x00000000*/

20631

20632 /*

20633 Latency requirement for Non-Snoop requests. This

20634 value is multiplied by the MULTIPLIER field to

20635 yield a time value, yielding an expressible

20636 range from 1ns to 34,326.183,936 ns. Setting

20637 this field and the MULTIPLIER to all 0s

20638 indicates that the device will be impacted by

20639 any delay and that the best possible service is

20640 requested.

20641 */

20642 UINT32 Multiplier : 3;

20643

20644 /* Bits[12:10], Access Type=RW, default=0x00000000*/

20645

20646 /*

20647 This field indicates the scale that the NSTL

20648 value is multipled by to yield a time value.

20649 */

20650 UINT32 Rsvd13 : 1;

20651

20652 /* Bits[13:13], Access Type=RO, default=None*/

20653

20654 /* Reserved */

20655 UINT32 ForceNl : 1;

20656

20657 /* Bits[14:14], Access Type=RW, default=0x00000000*/

20658

20659 /*

20660 When this bit is set, PCODE will choose the non-

20661 snoop latency requirement from this register,

20662 regardless of the LTR messages that are recieved

20663 by any of the PCI Express controllers. When this

20664 bit is clear, PCODE will choose the non-snoop

20665 latency requirement as the minimum value taken

20666 between this register and each of the LTR

20667 messages that were received by the PCI Express

20668 controllers with the Requirement bit set to 1b.

20669 */

20670 UINT32 NlV : 1;

20671

20672 /* Bits[15:15], Access Type=RW, default=0x00000000*/

20673

20674 /*

20675 When this bit is set to 0b, PCODE will ignore

20676 the Non- Snoop Latency override value.

20677 */

20678 UINT32 Sxl : 10;

20679

20680 /* Bits[25:16], Access Type=RW, default=0x00000000*/

20681

20682 /*

20683 Latency requirement for Snoop requests. This

20684 value is multiplied by the SXL_MULTIPLIER field

20685 to yield a time value, yielding an expressible

20686 range from 1ns to 34,326.183,936 ns. Setting

20687 this field and the SXL_MULTIPLIER to all 0s

20688 indicates that the device will be impacted by

20689 any delay and that the best possible service is

20690 requested.

20691 */

20692 UINT32 Sxlm : 3;

20693

20694 /* Bits[28:26], Access Type=RW, default=0x00000000*/

20695

20696 /*

20697 This field indicates the scale that the SXL

20698 value is multipled by to yield a time value.

20699 */

20700 UINT32 Rsvd29 : 1;

20701

20702 /* Bits[29:29], Access Type=RO, default=None*/

20703

20704 /* Reserved */

20705 UINT32 ForceSxl : 1;

20706

20707 /* Bits[30:30], Access Type=RW, default=0x00000000*/

20708

20709 /*

20710 When this bit is set, PCODE will choose the

20711 snoop latency requirement from this register,

20712 regardless of the LTR messages that are recieved

20713 by any of the PCI Express controllers. When this

20714 bit is clear, PCODE will choose the snoop

20715 latency requirement as the minimum value taken

20716 between this register and each of the LTR

20717 messages that were received by the PCI Express

20718 controllers with the Requirement bit set to 1b.

20719 */

20720 UINT32 SxlV : 1;

20721

20722 /* Bits[31:31], Access Type=RW, default=0x00000000*/

20723

20724 /*

20725 When this bit is set to 0b, PCODE will ignore

20726 the Snoop Latency override value.

20727 */

20728

20729 } Bits;

20730

20731 UINT32 Uint32;

20732 UINT64 Uint64;

20733

20734 } MSR_SW_LTR_OVRD_REGISTER;

20735

20736 /**

20737 Holds the status information and control the operation of the the PMON Fixed Counter.

20738 **/

20739 #define MSR_M2PPMONCNTRCFG_2 0x00000B18

20740

20741 typedef union {

20742 ///

20743 /// Individual bit fields

20744 ///

20745 struct {

20746 UINT32 Eventselect : 8;

20747

20748 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

20749

20750 /*

20751 This field is used to decode the PerfMon event

20752 which is selected. The encodings for each of the

20753 valid UnCore PerfMon events can be found in the

20754 respective individual unit performance

20755 monitoring documentation.

20756 */

20757 UINT32 Unitmask : 8;

20758

20759 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

20760

20761 /*

20762 This mask selects the sub-events to be selected

20763 for creation of the event. The selected sub-

20764 events are bitwise OR-ed together to create

20765 event. At least one sub-event must be selected

20766 otherwise the PerfMon event signals will not

20767 ever get asserted. Events with no sub-events

20768 listed effectively have only one sub-event

20769 =event -1 bit 8 must be set to 1 in this case.

20770 */

20771 UINT32 Rsvd16 : 1;

20772

20773 /* Bits[16:16], Access Type=RO, default=None*/

20774

20775 /* Reserved */

20776 UINT32 Counterreset : 1;

20777

20778 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

20779

20780 /*

20781 When this bit is set, the corresponding counter

20782 will be reset to 0. This allows for a quick

20783 reset of the counter when changing event

20784 encodings.

20785 */

20786 UINT32 Edgedetect : 1;

20787

20788 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

20789

20790 /*

20791 Edge Detect allows one to count either 0 to 1 or

20792 1 to 0 transitions of a given event. For

20793 example, we have an event that counts the number

20794 of cycles in L1 mode in Intel QPI. By using edge

20795 detect, one can count the number of times that

20796 we entered L1 mode (by detecting the rising

20797 edge).ect only works in conjunction with

20798 threshholding. This is true even for events that

20799 can only increment by 1 in a given cycle (like

20800 the L1 example above). In this case, one should

20801 set a threshhold of 1. One can also use Edge

20802 Detect with queue occupancy events. For example,

20803 if one wanted to count the number of times when

20804 the TOR occupancy was larger than 5, one would

20805 selet the TOR occupancy event with a threshold

20806 of 5 and set the Edge Detect bit. Can also be

20807 used with the invert. This is generally not

20808 particularly useful, as the count of falling

20809 edges compared to rising edges will always on

20810 differ by 1.

20811 */

20812 UINT32 Rsvd19 : 1;

20813

20814 /* Bits[19:19], Access Type=RO, default=None*/

20815

20816 /* Reserved */

20817 UINT32 Overflowenable : 1;

20818

20819 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

20820

20821 /*

20822 Setting this bit will enable the counter to send

20823 an overflow signal. If this bit is not set, the

20824 counter will wrap around when it overflows

20825 without triggering anything. If this bit is set

20826 and the Units configuration register has

20827 Overflow enabled, then a signal will be

20828 transmitted to the Ubox.

20829 */

20830 UINT32 Internal : 1;

20831

20832 /* Bits[21:21], Access Type=RW_V, default=0x00000000*/

20833

20834 /*

20835 This bit needs to be asserted if the event which

20836 needs to be selected is an internal event.

20837 Internal events are only accessible on unlocked

20838 parts. One can think of an internal bit as an

20839 extension of the event select bits 7:0, as it

20840 allows theuse to gain access to additional

20841 events. For perfmons that exist in teh MSR space

20842 , the MSR write mask is set on this bit and teh

20843 ucode handler will trigger a GP fault if one

20844 attempts to write to these bits. Writing to

20845 these bits is controlled in otehr ways in the

20846 other units

20847 */

20848 UINT32 Counterenable : 1;

20849

20850 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

20851

20852 /*

20853 This field is the local enable for the PerfMon

20854 Counter. This bit must be asserted in order for

20855 the PerfMon counter to begin counting the events

20856 selected by the event select, unit mask, and

20857 internal bits (see the fields below). There is

20858 one bit per PerfMon Counter. Note that if this

20859 bit is set to 1 but the Unit Control Registers

20860 have determined that counting is disabled, then

20861 the counter will not count.

20862 */

20863 UINT32 Invert : 1;

20864

20865 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

20866

20867 /*

20868 This bit indicates how the threshold field will

20869 be compared to the incoming event. When 0, the

20870 comparison that will be done is threshold event.

20871 When set to 1, the comparison that will be done

20872 is inverted from the case where this bit is set

20873 to 0, i.e., threshold event. The invert bit only

20874 works when Threshhold != 0. So, if one would

20875 like to invert a non-occupancy event (like LLC

20876 Hit), one needs to set the threshhold to 1.

20877 */

20878 UINT32 ResThreshold : 8;

20879

20880 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

20881

20882 /*

20883 This field is compared directly against an

20884 incoming event value for events that can

20885 increment by 1 or more in a given cycle. Since

20886 the widest event from the ITC/OTC is 10 bits

20887 (queue occupancy), it is 10 bit wide. The result

20888 of the comparison is effectively a 1 bit wide

20889 event, i.e., the counter will be incremented by

20890 1 when the comparison is true (the type of

20891 comparison depends on the setting of the invert

20892 bit - see bit 23 below) no matter how wide the

20893 original event was. When this field is zero,

20894 threshold comparison is disabled and the event

20895 is passed without modification.

20896 */

20897

20898 } Bits;

20899

20900 UINT32 Uint32;

20901 UINT64 Uint64;

20902

20903 } MSR_M2PPMONCNTRCFG_2_REGISTER;

20904

20905 /**

20906 Holds the status information and control the operation of the the PMON Fixed Counter.

20907 **/

20908 #define MSR_M2PPMONCNTRCFG_3 0x00000B19

20909

20910 typedef union {

20911 ///

20912 /// Individual bit fields

20913 ///

20914 struct {

20915 UINT32 Eventselect : 8;

20916

20917 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

20918

20919 /*

20920 This field is used to decode the PerfMon event

20921 which is selected. The encodings for each of the

20922 valid UnCore PerfMon events can be found in the

20923 respective individual unit performance

20924 monitoring documentation.

20925 */

20926 UINT32 Unitmask : 8;

20927

20928 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

20929

20930 /*

20931 This mask selects the sub-events to be selected

20932 for creation of the event. The selected sub-

20933 events are bitwise OR-ed together to create

20934 event. At least one sub-event must be selected

20935 otherwise the PerfMon event signals will not

20936 ever get asserted. Events with no sub-events

20937 listed effectively have only one sub-event

20938 =event -1 bit 8 must be set to 1 in this case.

20939 */

20940 UINT32 Rsvd16 : 1;

20941

20942 /* Bits[16:16], Access Type=RO, default=None*/

20943

20944 /* Reserved */

20945 UINT32 Counterreset : 1;

20946

20947 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

20948

20949 /*

20950 When this bit is set, the corresponding counter

20951 will be reset to 0. This allows for a quick

20952 reset of the counter when changing event

20953 encodings.

20954 */

20955 UINT32 Edgedetect : 1;

20956

20957 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

20958

20959 /*

20960 Edge Detect allows one to count either 0 to 1 or

20961 1 to 0 transitions of a given event. For

20962 example, we have an event that counts the number

20963 of cycles in L1 mode in Intel QPI. By using edge

20964 detect, one can count the number of times that

20965 we entered L1 mode (by detecting the rising

20966 edge).ect only works in conjunction with

20967 threshholding. This is true even for events that

20968 can only increment by 1 in a given cycle (like

20969 the L1 example above). In this case, one should

20970 set a threshhold of 1. One can also use Edge

20971 Detect with queue occupancy events. For example,

20972 if one wanted to count the number of times when

20973 the TOR occupancy was larger than 5, one would

20974 selet the TOR occupancy event with a threshold

20975 of 5 and set the Edge Detect bit. Can also be

20976 used with the invert. This is generally not

20977 particularly useful, as the count of falling

20978 edges compared to rising edges will always on

20979 differ by 1.

20980 */

20981 UINT32 Rsvd19 : 1;

20982

20983 /* Bits[19:19], Access Type=RO, default=None*/

20984

20985 /* Reserved */

20986 UINT32 Overflowenable : 1;

20987

20988 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

20989

20990 /*

20991 Setting this bit will enable the counter to send

20992 an overflow signal. If this bit is not set, the

20993 counter will wrap around when it overflows

20994 without triggering anything. If this bit is set

20995 and the Units configuration register has

20996 Overflow enabled, then a signal will be

20997 transmitted to the Ubox.

20998 */

20999 UINT32 Internal : 1;

21000

21001 /* Bits[21:21], Access Type=RW_V, default=0x00000000*/

21002

21003 /*

21004 This bit needs to be asserted if the event which

21005 needs to be selected is an internal event.

21006 Internal events are only accessible on unlocked

21007 parts. One can think of an internal bit as an

21008 extension of the event select bits 7:0, as it

21009 allows theuse to gain access to additional

21010 events. For perfmons that exist in teh MSR space

21011 , the MSR write mask is set on this bit and teh

21012 ucode handler will trigger a GP fault if one

21013 attempts to write to these bits. Writing to

21014 these bits is controlled in otehr ways in the

21015 other units

21016 */

21017 UINT32 Counterenable : 1;

21018

21019 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

21020

21021 /*

21022 This field is the local enable for the PerfMon

21023 Counter. This bit must be asserted in order for

21024 the PerfMon counter to begin counting the events

21025 selected by the event select, unit mask, and

21026 internal bits (see the fields below). There is

21027 one bit per PerfMon Counter. Note that if this

21028 bit is set to 1 but the Unit Control Registers

21029 have determined that counting is disabled, then

21030 the counter will not count.

21031 */

21032 UINT32 Invert : 1;

21033

21034 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

21035

21036 /*

21037 This bit indicates how the threshold field will

21038 be compared to the incoming event. When 0, the

21039 comparison that will be done is threshold event.

21040 When set to 1, the comparison that will be done

21041 is inverted from the case where this bit is set

21042 to 0, i.e., threshold event. The invert bit only

21043 works when Threshhold != 0. So, if one would

21044 like to invert a non-occupancy event (like LLC

21045 Hit), one needs to set the threshhold to 1.

21046 */

21047 UINT32 ResThreshold : 8;

21048

21049 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

21050

21051 /*

21052 This field is compared directly against an

21053 incoming event value for events that can

21054 increment by 1 or more in a given cycle. Since

21055 the widest event from the ITC/OTC is 10 bits

21056 (queue occupancy), it is 10 bit wide. The result

21057 of the comparison is effectively a 1 bit wide

21058 event, i.e., the counter will be incremented by

21059 1 when the comparison is true (the type of

21060 comparison depends on the setting of the invert

21061 bit - see bit 23 below) no matter how wide the

21062 original event was. When this field is zero,

21063 threshold comparison is disabled and the event

21064 is passed without modification.

21065 */

21066

21067 } Bits;

21068

21069 UINT32 Uint32;

21070 UINT64 Uint64;

21071

21072 } MSR_M2PPMONCNTRCFG_3_REGISTER;

21073

21074 /**

21075 Holds the status information and control the operation of the the PMON Fixed Counter.

21076 **/

21077 #define MSR_IRPPMONCNTRCFG_0 0x00000B1D

21078

21079 typedef union {

21080 ///

21081 /// Individual bit fields

21082 ///

21083 struct {

21084 UINT32 Eventselect : 8;

21085

21086 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

21087

21088 /*

21089 This field is used to decode the PerfMon event

21090 which is selected. The encodings for each of the

21091 valid UnCore PerfMon events can be found in the

21092 respective individual unit performance

21093 monitoring documentation.

21094 */

21095 UINT32 Unitmask : 8;

21096

21097 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

21098

21099 /*

21100 This mask selects the sub-events to be selected

21101 for creation of the event. The selected sub-

21102 events are bitwise OR-ed together to create

21103 event. At least one sub-event must be selected

21104 otherwise the PerfMon event signals will not

21105 ever get asserted. Events with no sub-events

21106 listed effectively have only one sub-event

21107 =event -1 bit 8 must be set to 1 in this case.

21108 */

21109 UINT32 Queueoccupancyreset : 1;

21110

21111 /* Bits[16:16], Access Type=RW_V, default=0x00000000*/

21112

21113 /*

21114 This write only bit causes the queue occupancy

21115 Perf counter for which the event select register

21116 is associated to be clearedto all 0 when a 1 is

21117 written to it. No action is taken when 0 is

21118 written. Note since the queue occupancy counters

21119 will never drop to 0 , it is possible for the

21120 counters to catch up with the real occupancy of

21121 the queuein question when the real occupancy

21122 drops to 0

21123 */

21124 UINT32 Counterreset : 1;

21125

21126 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

21127

21128 /*

21129 When this bit is set, the corresponding counter

21130 will be reset to 0. This allows for a quick

21131 reset of the counter when changing event

21132 encodings.

21133 */

21134 UINT32 Edgedetect : 1;

21135

21136 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

21137

21138 /*

21139 Edge Detect allows one to count either 0 to 1 or

21140 1 to 0 transitions of a given event. For

21141 example, we have an event that counts the number

21142 of cycles in L1 mode in Intel QPI. By using edge

21143 detect, one can count the number of times that

21144 we entered L1 mode (by detecting the rising

21145 edge).ect only works in conjunction with

21146 threshholding. This is true even for events that

21147 can only increment by 1 in a given cycle (like

21148 the L1 example above). In this case, one should

21149 set a threshhold of 1. One can also use Edge

21150 Detect with queue occupancy events. For example,

21151 if one wanted to count the number of times when

21152 the TOR occupancy was larger than 5, one would

21153 selet the TOR occupancy event with a threshold

21154 of 5 and set the Edge Detect bit. Can also be

21155 used with the invert. This is generally not

21156 particularly useful, as the count of falling

21157 edges compared to rising edges will always on

21158 differ by 1.

21159 */

21160 UINT32 Rsvd19 : 1;

21161

21162 /* Bits[19:19], Access Type=RO, default=None*/

21163

21164 /* Reserved */

21165 UINT32 Overflowenable : 1;

21166

21167 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

21168

21169 /*

21170 Setting this bit will enable the counter to send

21171 an overflow signal. If this bit is not set, the

21172 counter will wrap around when it overflows

21173 without triggering anything. If this bit is set

21174 and the Units configuration register has

21175 Overflow enabled, then a signal will be

21176 transmitted to the Ubox.

21177 */

21178 UINT32 Internal : 1;

21179

21180 /* Bits[21:21], Access Type=RW_V, default=0x00000000*/

21181

21182 /*

21183 This bit needs to be asserted if the event which

21184 needs to be selected is an internal event.

21185 Internal events are only accessible on unlocked

21186 parts. One can think of an internal bit as an

21187 extension of the event select bits 7:0, as it

21188 allows theuse to gain access to additional

21189 events. For perfmons that exist in teh MSR space

21190 , the MSR write mask is set on this bit and teh

21191 ucode handler will trigger a GP fault if one

21192 attempts to write to these bits. Writing to

21193 these bits is controlled in otehr ways in the

21194 other units

21195 */

21196 UINT32 Counterenable : 1;

21197

21198 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

21199

21200 /*

21201 This field is the local enable for the PerfMon

21202 Counter. This bit must be asserted in order for

21203 the PerfMon counter to begin counting the events

21204 selected by the event select, unit mask, and

21205 internal bits (see the fields below). There is

21206 one bit per PerfMon Counter. Note that if this

21207 bit is set to 1 but the Unit Control Registers

21208 have determined that counting is disabled, then

21209 the counter will not count.

21210 */

21211 UINT32 Invert : 1;

21212

21213 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

21214

21215 /*

21216 This bit indicates how the threshold field will

21217 be compared to the incoming event. When 0, the

21218 comparison that will be done is threshold event.

21219 When set to 1, the comparison that will be done

21220 is inverted from the case where this bit is set

21221 to 0, i.e., threshold event. The invert bit only

21222 works when Threshhold != 0. So, if one would

21223 like to invert a non-occupancy event (like LLC

21224 Hit), one needs to set the threshhold to 1.

21225 */

21226 UINT32 Threshold : 8;

21227

21228 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

21229

21230 /*

21231 This field is compared directly against an

21232 incoming event value for events that can

21233 increment by 1 or more in a given cycle. Since

21234 the widest event from the ITC/OTC is 10 bits

21235 (queue occupancy), it is 10 bit wide. The result

21236 of the comparison is effectively a 1 bit wide

21237 event, i.e., the counter will be incremented by

21238 1 when the comparison is true (the type of

21239 comparison depends on the setting of the invert

21240 bit - see bit 23 below) no matter how wide the

21241 original event was. When this field is zero,

21242 threshold comparison is disabled and the event

21243 is passed without modification.

21244 */

21245

21246 } Bits;

21247

21248 UINT32 Uint32;

21249 UINT64 Uint64;

21250

21251 } MSR_IRPPMONCNTRCFG_0_REGISTER;

21252

21253 /**

21254 Holds the status information and control the operation of the the PMON Fixed Counter.

21255 **/

21256 #define MSR_IRPPMONCNTRCFG_1 0x00000B1E

21257

21258 typedef union {

21259 ///

21260 /// Individual bit fields

21261 ///

21262 struct {

21263 UINT32 Eventselect : 8;

21264

21265 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

21266

21267 /*

21268 This field is used to decode the PerfMon event

21269 which is selected. The encodings for each of the

21270 valid UnCore PerfMon events can be found in the

21271 respective individual unit performance

21272 monitoring documentation.

21273 */

21274 UINT32 Unitmask : 8;

21275

21276 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

21277

21278 /*

21279 This mask selects the sub-events to be selected

21280 for creation of the event. The selected sub-

21281 events are bitwise OR-ed together to create

21282 event. At least one sub-event must be selected

21283 otherwise the PerfMon event signals will not

21284 ever get asserted. Events with no sub-events

21285 listed effectively have only one sub-event

21286 =event -1 bit 8 must be set to 1 in this case.

21287 */

21288 UINT32 Queueoccupancyreset : 1;

21289

21290 /* Bits[16:16], Access Type=RW_V, default=0x00000000*/

21291

21292 /*

21293 This write only bit causes the queue occupancy

21294 Perf counter for which the event select register

21295 is associated to be clearedto all 0 when a 1 is

21296 written to it. No action is taken when 0 is

21297 written. Note since the queue occupancy counters

21298 will never drop to 0 , it is possible for the

21299 counters to catch up with the real occupancy of

21300 the queuein question when the real occupancy

21301 drops to 0

21302 */

21303 UINT32 Counterreset : 1;

21304

21305 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

21306

21307 /*

21308 When this bit is set, the corresponding counter

21309 will be reset to 0. This allows for a quick

21310 reset of the counter when changing event

21311 encodings.

21312 */

21313 UINT32 Edgedetect : 1;

21314

21315 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

21316

21317 /*

21318 Edge Detect allows one to count either 0 to 1 or

21319 1 to 0 transitions of a given event. For

21320 example, we have an event that counts the number

21321 of cycles in L1 mode in Intel QPI. By using edge

21322 detect, one can count the number of times that

21323 we entered L1 mode (by detecting the rising

21324 edge).ect only works in conjunction with

21325 threshholding. This is true even for events that

21326 can only increment by 1 in a given cycle (like

21327 the L1 example above). In this case, one should

21328 set a threshhold of 1. One can also use Edge

21329 Detect with queue occupancy events. For example,

21330 if one wanted to count the number of times when

21331 the TOR occupancy was larger than 5, one would

21332 selet the TOR occupancy event with a threshold

21333 of 5 and set the Edge Detect bit. Can also be

21334 used with the invert. This is generally not

21335 particularly useful, as the count of falling

21336 edges compared to rising edges will always on

21337 differ by 1.

21338 */

21339 UINT32 Rsvd19 : 1;

21340

21341 /* Bits[19:19], Access Type=RO, default=None*/

21342

21343 /* Reserved */

21344 UINT32 Overflowenable : 1;

21345

21346 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

21347

21348 /*

21349 Setting this bit will enable the counter to send

21350 an overflow signal. If this bit is not set, the

21351 counter will wrap around when it overflows

21352 without triggering anything. If this bit is set

21353 and the Units configuration register has

21354 Overflow enabled, then a signal will be

21355 transmitted to the Ubox.

21356 */

21357 UINT32 Internal : 1;

21358

21359 /* Bits[21:21], Access Type=RW_V, default=0x00000000*/

21360

21361 /*

21362 This bit needs to be asserted if the event which

21363 needs to be selected is an internal event.

21364 Internal events are only accessible on unlocked

21365 parts. One can think of an internal bit as an

21366 extension of the event select bits 7:0, as it

21367 allows theuse to gain access to additional

21368 events. For perfmons that exist in teh MSR space

21369 , the MSR write mask is set on this bit and teh

21370 ucode handler will trigger a GP fault if one

21371 attempts to write to these bits. Writing to

21372 these bits is controlled in otehr ways in the

21373 other units

21374 */

21375 UINT32 Counterenable : 1;

21376

21377 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

21378

21379 /*

21380 This field is the local enable for the PerfMon

21381 Counter. This bit must be asserted in order for

21382 the PerfMon counter to begin counting the events

21383 selected by the event select, unit mask, and

21384 internal bits (see the fields below). There is

21385 one bit per PerfMon Counter. Note that if this

21386 bit is set to 1 but the Unit Control Registers

21387 have determined that counting is disabled, then

21388 the counter will not count.

21389 */

21390 UINT32 Invert : 1;

21391

21392 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

21393

21394 /*

21395 This bit indicates how the threshold field will

21396 be compared to the incoming event. When 0, the

21397 comparison that will be done is threshold event.

21398 When set to 1, the comparison that will be done

21399 is inverted from the case where this bit is set

21400 to 0, i.e., threshold event. The invert bit only

21401 works when Threshhold != 0. So, if one would

21402 like to invert a non-occupancy event (like LLC

21403 Hit), one needs to set the threshhold to 1.

21404 */

21405 UINT32 Threshold : 8;

21406

21407 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

21408

21409 /*

21410 This field is compared directly against an

21411 incoming event value for events that can

21412 increment by 1 or more in a given cycle. Since

21413 the widest event from the ITC/OTC is 10 bits

21414 (queue occupancy), it is 10 bit wide. The result

21415 of the comparison is effectively a 1 bit wide

21416 event, i.e., the counter will be incremented by

21417 1 when the comparison is true (the type of

21418 comparison depends on the setting of the invert

21419 bit - see bit 23 below) no matter how wide the

21420 original event was. When this field is zero,

21421 threshold comparison is disabled and the event

21422 is passed without modification.

21423 */

21424

21425 } Bits;

21426

21427 UINT32 Uint32;

21428 UINT64 Uint64;

21429

21430 } MSR_IRPPMONCNTRCFG_1_REGISTER;

21431

21432 /**

21433

21434 **/

21435 #define MSR_IIOPMONUNITCTRL 0x00000B20

21436

21437 typedef union {

21438 ///

21439 /// Individual bit fields

21440 ///

21441 struct {

21442 UINT32 Resetcounterconfigs : 1;

21443

21444 /* Bits[0:0], Access Type=WO, default=0x00000000*/

21445

21446 /*

21447 When this bit is written to, the counter

21448 configuration registers will be reset. This does

21449 not effect the values in the counters. This is a

21450 WO register, and writing to this bit will

21451 trigger a reset for 1 cycle only.

21452 */

21453 UINT32 Resetcounters : 1;

21454

21455 /* Bits[1:1], Access Type=WO, default=0x00000000*/

21456

21457 /*

21458 When this bit is written to, the counters data

21459 fields will be reset. The configuration values

21460 will not be reset. This is a WO register, and

21461 writing to this bit will trigger a reset for 1

21462 cycle only.

21463 */

21464 UINT32 Rsvd2 : 6;

21465

21466 /* Bits[7:2], Access Type=RO, default=None*/

21467

21468 /* Reserved */

21469 UINT32 Freezecounters : 1;

21470

21471 /* Bits[8:8], Access Type=RW_V, default=0x00000000*/

21472

21473 /*

21474 This bit is written to when the counters should

21475 be frozen. If this bit is written to and freeze

21476 is enabled, the counters in the unit will stop

21477 counting. To freeze the counters, this bit need

21478 only be set by one of the unit control

21479 registers.

21480 */

21481 UINT32 Rsvd9 : 7;

21482

21483 /* Bits[15:9], Access Type=RO, default=None*/

21484

21485 /* Reserved */

21486 UINT32 Freezeenable : 1;

21487

21488 /* Bits[16:16], Access Type=RW, default=0x00000001*/

21489

21490 /*

21491 This bit controls what the counters in the unit

21492 will do when they receive a freeze signal. When

21493 set, the counters will be allowed to freeze.

21494 When not set, the counters will ignore the

21495 freeze signal. For freeze to be enabled for a

21496 given unit, all of the unit control registers

21497 must have this bit set.

21498 */

21499 UINT32 Overflowenable : 1;

21500

21501 /* Bits[17:17], Access Type=RW, default=0x00000001*/

21502

21503 /*

21504 This bit controls the behavior of counters when

21505 they overflow. When set, the system will trigger

21506 the overflow handling process throughout the

21507 rest of the uncore, potentially triggering a PMI

21508 and freezing counters. When it is not set, the

21509 counters will simply wrap around and continue to

21510 count. For overflow to be enabled for a given

21511 unit, all of the unit control registers must

21512 have this bit set.

21513 */

21514 UINT32 Rsvd18 : 14;

21515

21516 /* Bits[31:18], Access Type=RO, default=None*/

21517

21518 /* Reserved */

21519

21520 } Bits;

21521

21522 UINT32 Uint32;

21523 UINT64 Uint64;

21524

21525 } MSR_IIOPMONUNITCTRL_REGISTER;

21526

21527 /**

21528 This register is a perf counter. Software can read it and write it

21529 **/

21530 #define MSR_IIOPMONCNTR_0 0x00000B21

21531

21532 typedef union {

21533 ///

21534 /// Individual bit fields

21535 ///

21536 struct {

21537 UINT32 Countervalue0 : 32;

21538

21539 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

21540

21541 /* The value of the counter */

21542 UINT32 Countervalue1 : 16;

21543

21544 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

21545

21546 /* The value of the counter */

21547 UINT32 Rsvd48 : 16;

21548

21549 /* Bits[63:48], Access Type=RO, default=None*/

21550

21551 /* Reserved */

21552

21553 } Bits;

21554

21555 UINT32 Uint32;

21556 UINT64 Uint64;

21557

21558 } MSR_IIOPMONCNTR_0_REGISTER;

21559

21560 /**

21561 This register is a perf counter. Software can read it and write it

21562 **/

21563 #define MSR_IIOPMONCNTR_1 0x00000B22

21564

21565 typedef union {

21566 ///

21567 /// Individual bit fields

21568 ///

21569 struct {

21570 UINT32 Countervalue0 : 32;

21571

21572 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

21573

21574 /* The value of the counter */

21575 UINT32 Countervalue1 : 16;

21576

21577 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

21578

21579 /* The value of the counter */

21580 UINT32 Rsvd48 : 16;

21581

21582 /* Bits[63:48], Access Type=RO, default=None*/

21583

21584 /* Reserved */

21585

21586 } Bits;

21587

21588 UINT32 Uint32;

21589 UINT64 Uint64;

21590

21591 } MSR_IIOPMONCNTR_1_REGISTER;

21592

21593 /**

21594 This register is a perf counter. Software can read it and write it

21595 **/

21596 #define MSR_IIOPMONCNTR_2 0x00000B23

21597

21598 typedef union {

21599 ///

21600 /// Individual bit fields

21601 ///

21602 struct {

21603 UINT32 Countervalue0 : 32;

21604

21605 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

21606

21607 /* The value of the counter */

21608 UINT32 Countervalue1 : 16;

21609

21610 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

21611

21612 /* The value of the counter */

21613 UINT32 Rsvd48 : 16;

21614

21615 /* Bits[63:48], Access Type=RO, default=None*/

21616

21617 /* Reserved */

21618

21619 } Bits;

21620

21621 UINT32 Uint32;

21622 UINT64 Uint64;

21623

21624 } MSR_IIOPMONCNTR_2_REGISTER;

21625

21626 /**

21627 This register is a perf counter. Software can read it and write it

21628 **/

21629 #define MSR_IIOPMONCNTR_3 0x00000B24

21630

21631 typedef union {

21632 ///

21633 /// Individual bit fields

21634 ///

21635 struct {

21636 UINT32 Countervalue0 : 32;

21637

21638 /* Bits[31:0], Access Type=RW_V, default=0x00000000*/

21639

21640 /* The value of the counter */

21641 UINT32 Countervalue1 : 16;

21642

21643 /* Bits[47:32], Access Type=RW_V, default=0x00000000*/

21644

21645 /* The value of the counter */

21646 UINT32 Rsvd48 : 16;

21647

21648 /* Bits[63:48], Access Type=RO, default=None*/

21649

21650 /* Reserved */

21651

21652 } Bits;

21653

21654 UINT32 Uint32;

21655 UINT64 Uint64;

21656

21657 } MSR_IIOPMONCNTR_3_REGISTER;

21658

21659 /**

21660

21661 **/

21662 #define MSR_IIOPMONFRCNTRCLK 0x00000B25

21663

21664 typedef union {

21665 ///

21666 /// Individual bit fields

21667 ///

21668 struct {

21669 UINT32 Countervalue0 : 32;

21670

21671 /* Bits[31:0], Access Type=WO, default=0x00000000*/

21672

21673 /*

21674 This register is a perfmon counter. Software can

21675 both read it and write it

21676 */

21677 UINT32 Countervalue1 : 4;

21678

21679 /* Bits[35:32], Access Type=WO, default=0x00000000*/

21680

21681 /*

21682 This register is a perfmon counter. Software can

21683 both read it and write it

21684 */

21685 UINT32 Rsvd36 : 28;

21686

21687 /* Bits[63:36], Access Type=RO, default=None*/

21688

21689 /* Reserved */

21690

21691 } Bits;

21692

21693 UINT32 Uint32;

21694 UINT64 Uint64;

21695

21696 } MSR_IIOPMONFRCNTRCLK_REGISTER;

21697

21698 /**

21699

21700 **/

21701 #define MSR_IIOPMONUNITSTATUS 0x00000B27

21702

21703 typedef union {

21704 ///

21705 /// Individual bit fields

21706 ///

21707 struct {

21708 UINT32 Counter0ovf : 1;

21709

21710 /* Bits[0:0], Access Type=WO, default=0x00000000*/

21711

21712 /* counter 0 overflowed */

21713 UINT32 Counter1ovf : 1;

21714

21715 /* Bits[1:1], Access Type=WO, default=0x00000000*/

21716

21717 /* counter 1 overflowed */

21718 UINT32 Counter2ovf : 1;

21719

21720 /* Bits[2:2], Access Type=WO, default=0x00000000*/

21721

21722 /* counter 2 overflowed */

21723 UINT32 Counter3ovf : 1;

21724

21725 /* Bits[3:3], Access Type=WO, default=0x00000000*/

21726

21727 /* counter3 overflowed */

21728 UINT32 Rsvd4 : 28;

21729

21730 /* Bits[31:4], Access Type=RO, default=None*/

21731

21732 /* Reserved */

21733

21734 } Bits;

21735

21736 UINT32 Uint32;

21737 UINT64 Uint64;

21738

21739 } MSR_IIOPMONUNITSTATUS_REGISTER;

21740

21741 /**

21742 Holds the status information and control the operation of the the PMON Fixed Counter.

21743 **/

21744 #define MSR_IOPMONCNTRCFG_0 0x00000B28

21745

21746 typedef union {

21747 ///

21748 /// Individual bit fields

21749 ///

21750 struct {

21751 UINT32 Eventselect : 8;

21752

21753 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

21754

21755 /*

21756 This field is used to decode the PerfMon event

21757 which is selected. The encodings for each of the

21758 valid UnCore PerfMon events can be found in the

21759 respective individual unit performance

21760 monitoring documentation.

21761 */

21762 UINT32 Unitmask : 8;

21763

21764 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

21765

21766 /*

21767 This mask selects the sub-events to be selected

21768 for creation of the event. The selected sub-

21769 events are bitwise OR-ed together to create

21770 event. At least one sub-event must be selected

21771 otherwise the PerfMon event signals will not

21772 ever get asserted. Events with no sub-events

21773 listed effectively have only one sub-event

21774 =event -1 bit 8 must be set to 1 in this case.

21775 */

21776 UINT32 Rsvd16 : 1;

21777

21778 /* Bits[16:16], Access Type=RO, default=None*/

21779

21780 /* Reserved */

21781 UINT32 Counterreset : 1;

21782

21783 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

21784

21785 /*

21786 When this bit is set, the corresponding counter

21787 will be reset to 0. This allows for a quick

21788 reset of the counter when changing event

21789 encodings.

21790 */

21791 UINT32 Edgedetect : 1;

21792

21793 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

21794

21795 /*

21796 Edge Detect allows one to count either 0 to 1 or

21797 1 to 0 transitions of a given event. For

21798 example, we have an event that counts the number

21799 of cycles in L1 mode in Intel QPI. By using edge

21800 detect, one can count the number of times that

21801 we entered L1 mode (by detecting the rising

21802 edge).ect only works in conjunction with

21803 threshholding. This is true even for events that

21804 can only increment by 1 in a given cycle (like

21805 the L1 example above). In this case, one should

21806 set a threshhold of 1. One can also use Edge

21807 Detect with queue occupancy events. For example,

21808 if one wanted to count the number of times when

21809 the TOR occupancy was larger than 5, one would

21810 selet the TOR occupancy event with a threshold

21811 of 5 and set the Edge Detect bit. Can also be

21812 used with the invert. This is generally not

21813 particularly useful, as the count of falling

21814 edges compared to rising edges will always on

21815 differ by 1.

21816 */

21817 UINT32 Rsvd19 : 1;

21818

21819 /* Bits[19:19], Access Type=RO, default=None*/

21820

21821 /* Reserved */

21822 UINT32 Overflowenable : 1;

21823

21824 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

21825

21826 /*

21827 Setting this bit will enable the counter to send

21828 an overflow signal. If this bit is not set, the

21829 counter will wrap around when it overflows

21830 without triggering anything. If this bit is set

21831 and the Units configuration register has

21832 Overflow enabled, then a signal will be

21833 transmitted to the Ubox.

21834 */

21835 UINT32 Rsvd21 : 1;

21836

21837 /* Bits[21:21], Access Type=RO, default=None*/

21838

21839 /* Reserved */

21840 UINT32 Counterenable : 1;

21841

21842 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

21843

21844 /*

21845 This field is the local enable for the PerfMon

21846 Counter. This bit must be asserted in order for

21847 the PerfMon counter to begin counting the events

21848 selected by the event select, unit mask, and

21849 internal bits (see the fields below). There is

21850 one bit per PerfMon Counter. Note that if this

21851 bit is set to 1 but the Unit Control Registers

21852 have determined that counting is disabled, then

21853 the counter will not count.

21854 */

21855 UINT32 Invert : 1;

21856

21857 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

21858

21859 /*

21860 This bit indicates how the threshold field will

21861 be compared to the incoming event. When 0, the

21862 comparison that will be done is threshold event.

21863 When set to 1, the comparison that will be done

21864 is inverted from the case where this bit is set

21865 to 0, i.e., threshold event. The invert bit only

21866 works when Threshhold != 0. So, if one would

21867 like to invert a non-occupancy event (like LLC

21868 Hit), one needs to set the threshhold to 1.

21869 */

21870 UINT32 ResThreshold0 : 8;

21871

21872 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

21873

21874 /*

21875 This field is compared directly against an

21876 incoming event value for events that can

21877 increment by 1 or more in a given cycle. Since

21878 the widest event from the ITC/OTC is 10 bits

21879 (queue occupancy), it is 10 bit wide. The result

21880 of the comparison is effectively a 1 bit wide

21881 event, i.e., the counter will be incremented by

21882 1 when the comparison is true (the type of

21883 comparison depends on the setting of the invert

21884 bit - see bit 23 below) no matter how wide the

21885 original event was. When this field is zero,

21886 threshold comparison is disabled and the event

21887 is passed without modification.

21888 */

21889 UINT32 ResThreshold1 : 4;

21890

21891 /* Bits[35:32], Access Type=RW_V, default=0x00000000*/

21892

21893 /*

21894 This field is compared directly against an

21895 incoming event value for events that can

21896 increment by 1 or more in a given cycle. Since

21897 the widest event from the ITC/OTC is 10 bits

21898 (queue occupancy), it is 10 bit wide. The result

21899 of the comparison is effectively a 1 bit wide

21900 event, i.e., the counter will be incremented by

21901 1 when the comparison is true (the type of

21902 comparison depends on the setting of the invert

21903 bit - see bit 23 below) no matter how wide the

21904 original event was. When this field is zero,

21905 threshold comparison is disabled and the event

21906 is passed without modification.

21907 */

21908 UINT32 Chnlmask : 12;

21909

21910 /* Bits[47:36], Access Type=RW, default=0x00000FFF*/

21911

21912 /*

21913 This one-hot field specifies which PCIE links

21914 should be considered when counting PerfMon

21915 events. For example, if only bit 1 is set, then

21916 only events corresponding to PCIE link 1 will be

21917 counted.

21918 */

21919 UINT32 Fcmask : 3;

21920

21921 /* Bits[50:48], Access Type=RW, default=0x00000007*/

21922

21923 /*

21924 This one-hot field specifies which FCs should be

21925 considered when counting PerfMon events: Bit 0 -

21926 Posted requests Bit 1 - Non-posted requests Bit

21927 2 - Completions

21928 */

21929 UINT32 Rsvd51 : 13;

21930

21931 /* Bits[63:51], Access Type=RO, default=None*/

21932

21933 /* Reserved */

21934

21935 } Bits;

21936

21937 UINT32 Uint32;

21938 UINT64 Uint64;

21939

21940 } MSR_IOPMONCNTRCFG_0_REGISTER;

21941

21942 /**

21943 Holds the status information and control the operation of the the PMON Fixed Counter.

21944 **/

21945 #define MSR_IOPMONCNTRCFG_1 0x00000B29

21946

21947 typedef union {

21948 ///

21949 /// Individual bit fields

21950 ///

21951 struct {

21952 UINT32 Eventselect : 8;

21953

21954 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

21955

21956 /*

21957 This field is used to decode the PerfMon event

21958 which is selected. The encodings for each of the

21959 valid UnCore PerfMon events can be found in the

21960 respective individual unit performance

21961 monitoring documentation.

21962 */

21963 UINT32 Unitmask : 8;

21964

21965 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

21966

21967 /*

21968 This mask selects the sub-events to be selected

21969 for creation of the event. The selected sub-

21970 events are bitwise OR-ed together to create

21971 event. At least one sub-event must be selected

21972 otherwise the PerfMon event signals will not

21973 ever get asserted. Events with no sub-events

21974 listed effectively have only one sub-event

21975 =event -1 bit 8 must be set to 1 in this case.

21976 */

21977 UINT32 Rsvd16 : 1;

21978

21979 /* Bits[16:16], Access Type=RO, default=None*/

21980

21981 /* Reserved */

21982 UINT32 Counterreset : 1;

21983

21984 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

21985

21986 /*

21987 When this bit is set, the corresponding counter

21988 will be reset to 0. This allows for a quick

21989 reset of the counter when changing event

21990 encodings.

21991 */

21992 UINT32 Edgedetect : 1;

21993

21994 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

21995

21996 /*

21997 Edge Detect allows one to count either 0 to 1 or

21998 1 to 0 transitions of a given event. For

21999 example, we have an event that counts the number

22000 of cycles in L1 mode in Intel QPI. By using edge

22001 detect, one can count the number of times that

22002 we entered L1 mode (by detecting the rising

22003 edge).ect only works in conjunction with

22004 threshholding. This is true even for events that

22005 can only increment by 1 in a given cycle (like

22006 the L1 example above). In this case, one should

22007 set a threshhold of 1. One can also use Edge

22008 Detect with queue occupancy events. For example,

22009 if one wanted to count the number of times when

22010 the TOR occupancy was larger than 5, one would

22011 selet the TOR occupancy event with a threshold

22012 of 5 and set the Edge Detect bit. Can also be

22013 used with the invert. This is generally not

22014 particularly useful, as the count of falling

22015 edges compared to rising edges will always on

22016 differ by 1.

22017 */

22018 UINT32 Rsvd19 : 1;

22019

22020 /* Bits[19:19], Access Type=RO, default=None*/

22021

22022 /* Reserved */

22023 UINT32 Overflowenable : 1;

22024

22025 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

22026

22027 /*

22028 Setting this bit will enable the counter to send

22029 an overflow signal. If this bit is not set, the

22030 counter will wrap around when it overflows

22031 without triggering anything. If this bit is set

22032 and the Units configuration register has

22033 Overflow enabled, then a signal will be

22034 transmitted to the Ubox.

22035 */

22036 UINT32 Rsvd21 : 1;

22037

22038 /* Bits[21:21], Access Type=RO, default=None*/

22039

22040 /* Reserved */

22041 UINT32 Counterenable : 1;

22042

22043 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

22044

22045 /*

22046 This field is the local enable for the PerfMon

22047 Counter. This bit must be asserted in order for

22048 the PerfMon counter to begin counting the events

22049 selected by the event select, unit mask, and

22050 internal bits (see the fields below). There is

22051 one bit per PerfMon Counter. Note that if this

22052 bit is set to 1 but the Unit Control Registers

22053 have determined that counting is disabled, then

22054 the counter will not count.

22055 */

22056 UINT32 Invert : 1;

22057

22058 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

22059

22060 /*

22061 This bit indicates how the threshold field will

22062 be compared to the incoming event. When 0, the

22063 comparison that will be done is threshold event.

22064 When set to 1, the comparison that will be done

22065 is inverted from the case where this bit is set

22066 to 0, i.e., threshold event. The invert bit only

22067 works when Threshhold != 0. So, if one would

22068 like to invert a non-occupancy event (like LLC

22069 Hit), one needs to set the threshhold to 1.

22070 */

22071 UINT32 ResThreshold0 : 8;

22072

22073 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

22074

22075 /*

22076 This field is compared directly against an

22077 incoming event value for events that can

22078 increment by 1 or more in a given cycle. Since

22079 the widest event from the ITC/OTC is 10 bits

22080 (queue occupancy), it is 10 bit wide. The result

22081 of the comparison is effectively a 1 bit wide

22082 event, i.e., the counter will be incremented by

22083 1 when the comparison is true (the type of

22084 comparison depends on the setting of the invert

22085 bit - see bit 23 below) no matter how wide the

22086 original event was. When this field is zero,

22087 threshold comparison is disabled and the event

22088 is passed without modification.

22089 */

22090 UINT32 ResThreshold1 : 4;

22091

22092 /* Bits[35:32], Access Type=RW_V, default=0x00000000*/

22093

22094 /*

22095 This field is compared directly against an

22096 incoming event value for events that can

22097 increment by 1 or more in a given cycle. Since

22098 the widest event from the ITC/OTC is 10 bits

22099 (queue occupancy), it is 10 bit wide. The result

22100 of the comparison is effectively a 1 bit wide

22101 event, i.e., the counter will be incremented by

22102 1 when the comparison is true (the type of

22103 comparison depends on the setting of the invert

22104 bit - see bit 23 below) no matter how wide the

22105 original event was. When this field is zero,

22106 threshold comparison is disabled and the event

22107 is passed without modification.

22108 */

22109 UINT32 Chnlmask : 12;

22110

22111 /* Bits[47:36], Access Type=RW, default=0x00000FFF*/

22112

22113 /*

22114 This one-hot field specifies which PCIE links

22115 should be considered when counting PerfMon

22116 events. For example, if only bit 1 is set, then

22117 only events corresponding to PCIE link 1 will be

22118 counted.

22119 */

22120 UINT32 Fcmask : 3;

22121

22122 /* Bits[50:48], Access Type=RW, default=0x00000007*/

22123

22124 /*

22125 This one-hot field specifies which FCs should be

22126 considered when counting PerfMon events: Bit 0 -

22127 Posted requests Bit 1 - Non-posted requests Bit

22128 2 - Completions

22129 */

22130 UINT32 Rsvd51 : 13;

22131

22132 /* Bits[63:51], Access Type=RO, default=None*/

22133

22134 /* Reserved */

22135

22136 } Bits;

22137

22138 UINT32 Uint32;

22139 UINT64 Uint64;

22140

22141 } MSR_IOPMONCNTRCFG_1_REGISTER;

22142

22143 /**

22144 Holds the status information and control the operation of the the PMON Fixed Counter.

22145 **/

22146 #define MSR_IOPMONCNTRCFG_2 0x00000B2A

22147

22148 typedef union {

22149 ///

22150 /// Individual bit fields

22151 ///

22152 struct {

22153 UINT32 Eventselect : 8;

22154

22155 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

22156

22157 /*

22158 This field is used to decode the PerfMon event

22159 which is selected. The encodings for each of the

22160 valid UnCore PerfMon events can be found in the

22161 respective individual unit performance

22162 monitoring documentation.

22163 */

22164 UINT32 Unitmask : 8;

22165

22166 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

22167

22168 /*

22169 This mask selects the sub-events to be selected

22170 for creation of the event. The selected sub-

22171 events are bitwise OR-ed together to create

22172 event. At least one sub-event must be selected

22173 otherwise the PerfMon event signals will not

22174 ever get asserted. Events with no sub-events

22175 listed effectively have only one sub-event

22176 =event -1 bit 8 must be set to 1 in this case.

22177 */

22178 UINT32 Rsvd16 : 1;

22179

22180 /* Bits[16:16], Access Type=RO, default=None*/

22181

22182 /* Reserved */

22183 UINT32 Counterreset : 1;

22184

22185 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

22186

22187 /*

22188 When this bit is set, the corresponding counter

22189 will be reset to 0. This allows for a quick

22190 reset of the counter when changing event

22191 encodings.

22192 */

22193 UINT32 Edgedetect : 1;

22194

22195 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

22196

22197 /*

22198 Edge Detect allows one to count either 0 to 1 or

22199 1 to 0 transitions of a given event. For

22200 example, we have an event that counts the number

22201 of cycles in L1 mode in Intel QPI. By using edge

22202 detect, one can count the number of times that

22203 we entered L1 mode (by detecting the rising

22204 edge).ect only works in conjunction with

22205 threshholding. This is true even for events that

22206 can only increment by 1 in a given cycle (like

22207 the L1 example above). In this case, one should

22208 set a threshhold of 1. One can also use Edge

22209 Detect with queue occupancy events. For example,

22210 if one wanted to count the number of times when

22211 the TOR occupancy was larger than 5, one would

22212 selet the TOR occupancy event with a threshold

22213 of 5 and set the Edge Detect bit. Can also be

22214 used with the invert. This is generally not

22215 particularly useful, as the count of falling

22216 edges compared to rising edges will always on

22217 differ by 1.

22218 */

22219 UINT32 Rsvd19 : 1;

22220

22221 /* Bits[19:19], Access Type=RO, default=None*/

22222

22223 /* Reserved */

22224 UINT32 Overflowenable : 1;

22225

22226 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

22227

22228 /*

22229 Setting this bit will enable the counter to send

22230 an overflow signal. If this bit is not set, the

22231 counter will wrap around when it overflows

22232 without triggering anything. If this bit is set

22233 and the Units configuration register has

22234 Overflow enabled, then a signal will be

22235 transmitted to the Ubox.

22236 */

22237 UINT32 Rsvd21 : 1;

22238

22239 /* Bits[21:21], Access Type=RO, default=None*/

22240

22241 /* Reserved */

22242 UINT32 Counterenable : 1;

22243

22244 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

22245

22246 /*

22247 This field is the local enable for the PerfMon

22248 Counter. This bit must be asserted in order for

22249 the PerfMon counter to begin counting the events

22250 selected by the event select, unit mask, and

22251 internal bits (see the fields below). There is

22252 one bit per PerfMon Counter. Note that if this

22253 bit is set to 1 but the Unit Control Registers

22254 have determined that counting is disabled, then

22255 the counter will not count.

22256 */

22257 UINT32 Invert : 1;

22258

22259 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

22260

22261 /*

22262 This bit indicates how the threshold field will

22263 be compared to the incoming event. When 0, the

22264 comparison that will be done is threshold event.

22265 When set to 1, the comparison that will be done

22266 is inverted from the case where this bit is set

22267 to 0, i.e., threshold event. The invert bit only

22268 works when Threshhold != 0. So, if one would

22269 like to invert a non-occupancy event (like LLC

22270 Hit), one needs to set the threshhold to 1.

22271 */

22272 UINT32 ResThreshold0 : 8;

22273

22274 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

22275

22276 /*

22277 This field is compared directly against an

22278 incoming event value for events that can

22279 increment by 1 or more in a given cycle. Since

22280 the widest event from the ITC/OTC is 10 bits

22281 (queue occupancy), it is 10 bit wide. The result

22282 of the comparison is effectively a 1 bit wide

22283 event, i.e., the counter will be incremented by

22284 1 when the comparison is true (the type of

22285 comparison depends on the setting of the invert

22286 bit - see bit 23 below) no matter how wide the

22287 original event was. When this field is zero,

22288 threshold comparison is disabled and the event

22289 is passed without modification.

22290 */

22291 UINT32 ResThreshold1 : 4;

22292

22293 /* Bits[35:32], Access Type=RW_V, default=0x00000000*/

22294

22295 /*

22296 This field is compared directly against an

22297 incoming event value for events that can

22298 increment by 1 or more in a given cycle. Since

22299 the widest event from the ITC/OTC is 10 bits

22300 (queue occupancy), it is 10 bit wide. The result

22301 of the comparison is effectively a 1 bit wide

22302 event, i.e., the counter will be incremented by

22303 1 when the comparison is true (the type of

22304 comparison depends on the setting of the invert

22305 bit - see bit 23 below) no matter how wide the

22306 original event was. When this field is zero,

22307 threshold comparison is disabled and the event

22308 is passed without modification.

22309 */

22310 UINT32 Chnlmask : 12;

22311

22312 /* Bits[47:36], Access Type=RW, default=0x00000FFF*/

22313

22314 /*

22315 This one-hot field specifies which PCIE links

22316 should be considered when counting PerfMon

22317 events. For example, if only bit 1 is set, then

22318 only events corresponding to PCIE link 1 will be

22319 counted.

22320 */

22321 UINT32 Fcmask : 3;

22322

22323 /* Bits[50:48], Access Type=RW, default=0x00000007*/

22324

22325 /*

22326 This one-hot field specifies which FCs should be

22327 considered when counting PerfMon events: Bit 0 -

22328 Posted requests Bit 1 - Non-posted requests Bit

22329 2 - Completions

22330 */

22331 UINT32 Rsvd51 : 13;

22332

22333 /* Bits[63:51], Access Type=RO, default=None*/

22334

22335 /* Reserved */

22336

22337 } Bits;

22338

22339 UINT32 Uint32;

22340 UINT64 Uint64;

22341

22342 } MSR_IOPMONCNTRCFG_2_REGISTER;

22343

22344 /**

22345 Holds the status information and control the operation of the the PMON Fixed Counter.

22346 **/

22347 #define MSR_IOPMONCNTRCFG_3 0x00000B2B

22348

22349 typedef union {

22350 ///

22351 /// Individual bit fields

22352 ///

22353 struct {

22354 UINT32 Eventselect : 8;

22355

22356 /* Bits[7:0], Access Type=RW_V, default=0x00000000*/

22357

22358 /*

22359 This field is used to decode the PerfMon event

22360 which is selected. The encodings for each of the

22361 valid UnCore PerfMon events can be found in the

22362 respective individual unit performance

22363 monitoring documentation.

22364 */

22365 UINT32 Unitmask : 8;

22366

22367 /* Bits[15:8], Access Type=RW_V, default=0x00000000*/

22368

22369 /*

22370 This mask selects the sub-events to be selected

22371 for creation of the event. The selected sub-

22372 events are bitwise OR-ed together to create

22373 event. At least one sub-event must be selected

22374 otherwise the PerfMon event signals will not

22375 ever get asserted. Events with no sub-events

22376 listed effectively have only one sub-event

22377 =event -1 bit 8 must be set to 1 in this case.

22378 */

22379 UINT32 Rsvd16 : 1;

22380

22381 /* Bits[16:16], Access Type=RO, default=None*/

22382

22383 /* Reserved */

22384 UINT32 Counterreset : 1;

22385

22386 /* Bits[17:17], Access Type=RW_V, default=0x00000000*/

22387

22388 /*

22389 When this bit is set, the corresponding counter

22390 will be reset to 0. This allows for a quick

22391 reset of the counter when changing event

22392 encodings.

22393 */

22394 UINT32 Edgedetect : 1;

22395

22396 /* Bits[18:18], Access Type=RW_V, default=0x00000000*/

22397

22398 /*

22399 Edge Detect allows one to count either 0 to 1 or

22400 1 to 0 transitions of a given event. For

22401 example, we have an event that counts the number

22402 of cycles in L1 mode in Intel QPI. By using edge

22403 detect, one can count the number of times that

22404 we entered L1 mode (by detecting the rising

22405 edge).ect only works in conjunction with

22406 threshholding. This is true even for events that

22407 can only increment by 1 in a given cycle (like

22408 the L1 example above). In this case, one should

22409 set a threshhold of 1. One can also use Edge

22410 Detect with queue occupancy events. For example,

22411 if one wanted to count the number of times when

22412 the TOR occupancy was larger than 5, one would

22413 selet the TOR occupancy event with a threshold

22414 of 5 and set the Edge Detect bit. Can also be

22415 used with the invert. This is generally not

22416 particularly useful, as the count of falling

22417 edges compared to rising edges will always on

22418 differ by 1.

22419 */

22420 UINT32 Rsvd19 : 1;

22421

22422 /* Bits[19:19], Access Type=RO, default=None*/

22423

22424 /* Reserved */

22425 UINT32 Overflowenable : 1;

22426

22427 /* Bits[20:20], Access Type=RW_V, default=0x00000000*/

22428

22429 /*

22430 Setting this bit will enable the counter to send

22431 an overflow signal. If this bit is not set, the

22432 counter will wrap around when it overflows

22433 without triggering anything. If this bit is set

22434 and the Units configuration register has

22435 Overflow enabled, then a signal will be

22436 transmitted to the Ubox.

22437 */

22438 UINT32 Rsvd21 : 1;

22439

22440 /* Bits[21:21], Access Type=RO, default=None*/

22441

22442 /* Reserved */

22443 UINT32 Counterenable : 1;

22444

22445 /* Bits[22:22], Access Type=RW_V, default=0x00000000*/

22446

22447 /*

22448 This field is the local enable for the PerfMon

22449 Counter. This bit must be asserted in order for

22450 the PerfMon counter to begin counting the events

22451 selected by the event select, unit mask, and

22452 internal bits (see the fields below). There is

22453 one bit per PerfMon Counter. Note that if this

22454 bit is set to 1 but the Unit Control Registers

22455 have determined that counting is disabled, then

22456 the counter will not count.

22457 */

22458 UINT32 Invert : 1;

22459

22460 /* Bits[23:23], Access Type=RW_V, default=0x00000000*/

22461

22462 /*

22463 This bit indicates how the threshold field will

22464 be compared to the incoming event. When 0, the

22465 comparison that will be done is threshold event.

22466 When set to 1, the comparison that will be done

22467 is inverted from the case where this bit is set

22468 to 0, i.e., threshold event. The invert bit only

22469 works when Threshhold != 0. So, if one would

22470 like to invert a non-occupancy event (like LLC

22471 Hit), one needs to set the threshhold to 1.

22472 */

22473 UINT32 ResThreshold0 : 8;

22474

22475 /* Bits[31:24], Access Type=RW_V, default=0x00000000*/

22476

22477 /*

22478 This field is compared directly against an

22479 incoming event value for events that can

22480 increment by 1 or more in a given cycle. Since

22481 the widest event from the ITC/OTC is 10 bits

22482 (queue occupancy), it is 10 bit wide. The result

22483 of the comparison is effectively a 1 bit wide

22484 event, i.e., the counter will be incremented by

22485 1 when the comparison is true (the type of

22486 comparison depends on the setting of the invert

22487 bit - see bit 23 below) no matter how wide the

22488 original event was. When this field is zero,

22489 threshold comparison is disabled and the event

22490 is passed without modification.

22491 */

22492 UINT32 ResThreshold1 : 4;

22493

22494 /* Bits[35:32], Access Type=RW_V, default=0x00000000*/

22495

22496 /*

22497 This field is compared directly against an

22498 incoming event value for events that can

22499 increment by 1 or more in a given cycle. Since

22500 the widest event from the ITC/OTC is 10 bits

22501 (queue occupancy), it is 10 bit wide. The result

22502 of the comparison is effectively a 1 bit wide

22503 event, i.e., the counter will be incremented by

22504 1 when the comparison is true (the type of

22505 comparison depends on the setting of the invert

22506 bit - see bit 23 below) no matter how wide the

22507 original event was. When this field is zero,

22508 threshold comparison is disabled and the event

22509 is passed without modification.

22510 */

22511 UINT32 Chnlmask : 12;

22512

22513 /* Bits[47:36], Access Type=RW, default=0x00000FFF*/

22514

22515 /*

22516 This one-hot field specifies which PCIE links

22517 should be considered when counting PerfMon

22518 events. For example, if only bit 1 is set, then

22519 only events corresponding to PCIE link 1 will be

22520 counted.

22521 */

22522 UINT32 Fcmask : 3;

22523

22524 /* Bits[50:48], Access Type=RW, default=0x00000007*/

22525

22526 /*

22527 This one-hot field specifies which FCs should be

22528 considered when counting PerfMon events: Bit 0 -

22529 Posted requests Bit 1 - Non-posted requests Bit

22530 2 - Completions

22531 */

22532 UINT32 Rsvd51 : 13;

22533

22534 /* Bits[63:51], Access Type=RO, default=None*/

22535

22536 /* Reserved */

22537

22538 } Bits;

22539

22540 UINT32 Uint32;

22541 UINT64 Uint64;

22542

22543 } MSR_IOPMONCNTRCFG_3_REGISTER;

22544

22545 /**

22546 This is the foward counter. Software can read and write into it

22547 **/

22548 #define MSR_IIOPMONFRCNTR_0 0x00000B50

22549

22550 typedef union {

22551 ///

22552 /// Individual bit fields

22553 ///

22554 struct {

22555 UINT32 Countervalue0 : 32;

22556

22557 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22558

22559 /* The current value of the counter */

22560 UINT32 Countervalue1 : 4;

22561

22562 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22563

22564 /* The current value of the counter */

22565 UINT32 Rsvd36 : 28;

22566

22567 /* Bits[63:36], Access Type=RO, default=None*/

22568

22569 /* Reserved */

22570

22571 } Bits;

22572

22573 UINT32 Uint32;

22574 UINT64 Uint64;

22575

22576 } MSR_IIOPMONFRCNTR_0_REGISTER;

22577

22578 /**

22579 This is the foward counter. Software can read and write into it

22580 **/

22581 #define MSR_IIOPMONFRCNTR_1 0x00000B51

22582

22583 typedef union {

22584 ///

22585 /// Individual bit fields

22586 ///

22587 struct {

22588 UINT32 Countervalue0 : 32;

22589

22590 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22591

22592 /* The current value of the counter */

22593 UINT32 Countervalue1 : 4;

22594

22595 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22596

22597 /* The current value of the counter */

22598 UINT32 Rsvd36 : 28;

22599

22600 /* Bits[63:36], Access Type=RO, default=None*/

22601

22602 /* Reserved */

22603

22604 } Bits;

22605

22606 UINT32 Uint32;

22607 UINT64 Uint64;

22608

22609 } MSR_IIOPMONFRCNTR_1_REGISTER;

22610

22611 /**

22612 This is the foward counter. Software can read and write into it

22613 **/

22614 #define MSR_IIOPMONFRCNTR_2 0x00000B52

22615

22616 typedef union {

22617 ///

22618 /// Individual bit fields

22619 ///

22620 struct {

22621 UINT32 Countervalue0 : 32;

22622

22623 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22624

22625 /* The current value of the counter */

22626 UINT32 Countervalue1 : 4;

22627

22628 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22629

22630 /* The current value of the counter */

22631 UINT32 Rsvd36 : 28;

22632

22633 /* Bits[63:36], Access Type=RO, default=None*/

22634

22635 /* Reserved */

22636

22637 } Bits;

22638

22639 UINT32 Uint32;

22640 UINT64 Uint64;

22641

22642 } MSR_IIOPMONFRCNTR_2_REGISTER;

22643

22644 /**

22645 This is the foward counter. Software can read and write into it

22646 **/

22647 #define MSR_IIOPMONFRCNTR_3 0x00000B53

22648

22649 typedef union {

22650 ///

22651 /// Individual bit fields

22652 ///

22653 struct {

22654 UINT32 Countervalue0 : 32;

22655

22656 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22657

22658 /* The current value of the counter */

22659 UINT32 Countervalue1 : 4;

22660

22661 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22662

22663 /* The current value of the counter */

22664 UINT32 Rsvd36 : 28;

22665

22666 /* Bits[63:36], Access Type=RO, default=None*/

22667

22668 /* Reserved */

22669

22670 } Bits;

22671

22672 UINT32 Uint32;

22673 UINT64 Uint64;

22674

22675 } MSR_IIOPMONFRCNTR_3_REGISTER;

22676

22677 /**

22678 This is the foward counter. Software can read and write into it

22679 **/

22680 #define MSR_IIOPMONFRCNTR_4 0x00000B54

22681

22682 typedef union {

22683 ///

22684 /// Individual bit fields

22685 ///

22686 struct {

22687 UINT32 Countervalue0 : 32;

22688

22689 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22690

22691 /* The current value of the counter */

22692 UINT32 Countervalue1 : 4;

22693

22694 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22695

22696 /* The current value of the counter */

22697 UINT32 Rsvd36 : 28;

22698

22699 /* Bits[63:36], Access Type=RO, default=None*/

22700

22701 /* Reserved */

22702

22703 } Bits;

22704

22705 UINT32 Uint32;

22706 UINT64 Uint64;

22707

22708 } MSR_IIOPMONFRCNTR_4_REGISTER;

22709

22710 /**

22711 This is the foward counter. Software can read and write into it

22712 **/

22713 #define MSR_IIOPMONFRCNTR_5 0x00000B55

22714

22715 typedef union {

22716 ///

22717 /// Individual bit fields

22718 ///

22719 struct {

22720 UINT32 Countervalue0 : 32;

22721

22722 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22723

22724 /* The current value of the counter */

22725 UINT32 Countervalue1 : 4;

22726

22727 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22728

22729 /* The current value of the counter */

22730 UINT32 Rsvd36 : 28;

22731

22732 /* Bits[63:36], Access Type=RO, default=None*/

22733

22734 /* Reserved */

22735

22736 } Bits;

22737

22738 UINT32 Uint32;

22739 UINT64 Uint64;

22740

22741 } MSR_IIOPMONFRCNTR_5_REGISTER;

22742

22743 /**

22744 This is the foward counter. Software can read and write into it

22745 **/

22746 #define MSR_IIOPMONFRCNTR_6 0x00000B56

22747

22748 typedef union {

22749 ///

22750 /// Individual bit fields

22751 ///

22752 struct {

22753 UINT32 Countervalue0 : 32;

22754

22755 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22756

22757 /* The current value of the counter */

22758 UINT32 Countervalue1 : 4;

22759

22760 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22761

22762 /* The current value of the counter */

22763 UINT32 Rsvd36 : 28;

22764

22765 /* Bits[63:36], Access Type=RO, default=None*/

22766

22767 /* Reserved */

22768

22769 } Bits;

22770

22771 UINT32 Uint32;

22772 UINT64 Uint64;

22773

22774 } MSR_IIOPMONFRCNTR_6_REGISTER;

22775

22776 /**

22777 This is the foward counter. Software can read and write into it

22778 **/

22779 #define MSR_IIOPMONFRCNTR_7 0x00000B57

22780

22781 typedef union {

22782 ///

22783 /// Individual bit fields

22784 ///

22785 struct {

22786 UINT32 Countervalue0 : 32;

22787

22788 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22789

22790 /* The current value of the counter */

22791 UINT32 Countervalue1 : 4;

22792

22793 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22794

22795 /* The current value of the counter */

22796 UINT32 Rsvd36 : 28;

22797

22798 /* Bits[63:36], Access Type=RO, default=None*/

22799

22800 /* Reserved */

22801

22802 } Bits;

22803

22804 UINT32 Uint32;

22805 UINT64 Uint64;

22806

22807 } MSR_IIOPMONFRCNTR_7_REGISTER;

22808

22809 /**

22810 This is the foward counter. Software can read and write into it

22811 **/

22812 #define MSR_IIOPMONFRCNTR_8 0x00000B58

22813

22814 typedef union {

22815 ///

22816 /// Individual bit fields

22817 ///

22818 struct {

22819 UINT32 Countervalue0 : 32;

22820

22821 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22822

22823 /* The current value of the counter */

22824 UINT32 Countervalue1 : 4;

22825

22826 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22827

22828 /* The current value of the counter */

22829 UINT32 Rsvd36 : 28;

22830

22831 /* Bits[63:36], Access Type=RO, default=None*/

22832

22833 /* Reserved */

22834

22835 } Bits;

22836

22837 UINT32 Uint32;

22838 UINT64 Uint64;

22839

22840 } MSR_IIOPMONFRCNTR_8_REGISTER;

22841

22842 /**

22843 This is the foward counter. Software can read and write into it

22844 **/

22845 #define MSR_IIOPMONFRCNTR_9 0x00000B59

22846

22847 typedef union {

22848 ///

22849 /// Individual bit fields

22850 ///

22851 struct {

22852 UINT32 Countervalue0 : 32;

22853

22854 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22855

22856 /* The current value of the counter */

22857 UINT32 Countervalue1 : 4;

22858

22859 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22860

22861 /* The current value of the counter */

22862 UINT32 Rsvd36 : 28;

22863

22864 /* Bits[63:36], Access Type=RO, default=None*/

22865

22866 /* Reserved */

22867

22868 } Bits;

22869

22870 UINT32 Uint32;

22871 UINT64 Uint64;

22872

22873 } MSR_IIOPMONFRCNTR_9_REGISTER;

22874

22875 /**

22876 This is the foward counter. Software can read and write into it

22877 **/

22878 #define MSR_IIOPMONFRCNTR_10 0x00000B5A

22879

22880 typedef union {

22881 ///

22882 /// Individual bit fields

22883 ///

22884 struct {

22885 UINT32 Countervalue0 : 32;

22886

22887 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22888

22889 /* The current value of the counter */

22890 UINT32 Countervalue1 : 4;

22891

22892 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22893

22894 /* The current value of the counter */

22895 UINT32 Rsvd36 : 28;

22896

22897 /* Bits[63:36], Access Type=RO, default=None*/

22898

22899 /* Reserved */

22900

22901 } Bits;

22902

22903 UINT32 Uint32;

22904 UINT64 Uint64;

22905

22906 } MSR_IIOPMONFRCNTR_10_REGISTER;

22907

22908 /**

22909 This is the foward counter. Software can read and write into it

22910 **/

22911 #define MSR_IIOPMONFRCNTR_11 0x00000B5B

22912

22913 typedef union {

22914 ///

22915 /// Individual bit fields

22916 ///

22917 struct {

22918 UINT32 Countervalue0 : 32;

22919

22920 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22921

22922 /* The current value of the counter */

22923 UINT32 Countervalue1 : 4;

22924

22925 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22926

22927 /* The current value of the counter */

22928 UINT32 Rsvd36 : 28;

22929

22930 /* Bits[63:36], Access Type=RO, default=None*/

22931

22932 /* Reserved */

22933

22934 } Bits;

22935

22936 UINT32 Uint32;

22937 UINT64 Uint64;

22938

22939 } MSR_IIOPMONFRCNTR_11_REGISTER;

22940

22941 /**

22942 This is the foward counter. Software can read and write into it

22943 **/

22944 #define MSR_IIOPMONFRCNTR_12 0x00000B5C

22945

22946 typedef union {

22947 ///

22948 /// Individual bit fields

22949 ///

22950 struct {

22951 UINT32 Countervalue0 : 32;

22952

22953 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22954

22955 /* The current value of the counter */

22956 UINT32 Countervalue1 : 4;

22957

22958 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22959

22960 /* The current value of the counter */

22961 UINT32 Rsvd36 : 28;

22962

22963 /* Bits[63:36], Access Type=RO, default=None*/

22964

22965 /* Reserved */

22966

22967 } Bits;

22968

22969 UINT32 Uint32;

22970 UINT64 Uint64;

22971

22972 } MSR_IIOPMONFRCNTR_12_REGISTER;

22973

22974 /**

22975 This is the foward counter. Software can read and write into it

22976 **/

22977 #define MSR_IIOPMONFRCNTR_13 0x00000B5D

22978

22979 typedef union {

22980 ///

22981 /// Individual bit fields

22982 ///

22983 struct {

22984 UINT32 Countervalue0 : 32;

22985

22986 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

22987

22988 /* The current value of the counter */

22989 UINT32 Countervalue1 : 4;

22990

22991 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

22992

22993 /* The current value of the counter */

22994 UINT32 Rsvd36 : 28;

22995

22996 /* Bits[63:36], Access Type=RO, default=None*/

22997

22998 /* Reserved */

22999

23000 } Bits;

23001

23002 UINT32 Uint32;

23003 UINT64 Uint64;

23004

23005 } MSR_IIOPMONFRCNTR_13_REGISTER;

23006

23007 /**

23008 This is the foward counter. Software can read and write into it

23009 **/

23010 #define MSR_IIOPMONFRCNTR_14 0x00000B5E

23011

23012 typedef union {

23013 ///

23014 /// Individual bit fields

23015 ///

23016 struct {

23017 UINT32 Countervalue0 : 32;

23018

23019 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

23020

23021 /* The current value of the counter */

23022 UINT32 Countervalue1 : 4;

23023

23024 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

23025

23026 /* The current value of the counter */

23027 UINT32 Rsvd36 : 28;

23028

23029 /* Bits[63:36], Access Type=RO, default=None*/

23030

23031 /* Reserved */

23032

23033 } Bits;

23034

23035 UINT32 Uint32;

23036 UINT64 Uint64;

23037

23038 } MSR_IIOPMONFRCNTR_14_REGISTER;

23039

23040 /**

23041 This is the foward counter. Software can read and write into it

23042 **/

23043 #define MSR_IIOPMONFRCNTR_15 0x00000B5F

23044

23045 typedef union {

23046 ///

23047 /// Individual bit fields

23048 ///

23049 struct {

23050 UINT32 Countervalue0 : 32;

23051

23052 /* Bits[31:0], Access Type=RO_V, default=0x00000000*/

23053

23054 /* The current value of the counter */

23055 UINT32 Countervalue1 : 4;

23056

23057 /* Bits[35:32], Access Type=RO_V, default=0x00000000*/

23058

23059 /* The current value of the counter */

23060 UINT32 Rsvd36 : 28;

23061

23062 /* Bits[63:36], Access Type=RO, default=None*/

23063

23064 /* Reserved */

23065

23066 } Bits;

23067

23068 UINT32 Uint32;

23069 UINT64 Uint64;

23070

23071 } MSR_IIOPMONFRCNTR_15_REGISTER;

23072

23073 /**

23074 Available only in SMM. SMRAM copy of CR0 saved by SMI

23075 **/

23076 #define MSR_SMRAM_CR0 0x00000C00

23077

23078 typedef union {

23079 ///

23080 /// Individual bit fields

23081 ///

23082 struct {

23083 UINT32 Pe : 1;

23084

23085 /* Bits[0:0], Access Type=RW, default=0x00000000*/

23086

23087 /* Protection Enable */

23088 UINT32 Mp : 1;

23089

23090 /* Bits[1:1], Access Type=RW, default=0x00000000*/

23091

23092 /* Monitor Coprocessor */

23093 UINT32 Em : 1;

23094

23095 /* Bits[2:2], Access Type=RW, default=0x00000000*/

23096

23097 /* Emulation */

23098 UINT32 Ts : 1;

23099

23100 /* Bits[3:3], Access Type=RW, default=0x00000000*/

23101

23102 /* Task Switched */

23103 UINT32 Et : 1;

23104

23105 /* Bits[4:4], Access Type=RO_V, default=None*/

23106

23107 /*

23108 Extension Type (hardware for this bit always

23109 reads as '1...no actual state here)

23110 */

23111 UINT32 Ne : 1;

23112

23113 /* Bits[5:5], Access Type=RW, default=0x00000000*/

23114

23115 /* Numeric Error */

23116 UINT32 Rsvd6 : 10;

23117

23118 /* Bits[15:6], Access Type=RO, default=None*/

23119

23120 /* Reserved */

23121 UINT32 Wp : 1;

23122

23123 /* Bits[16:16], Access Type=RW, default=0x00000000*/

23124

23125 /* Write Protect */

23126 UINT32 Rsvd17 : 1;

23127

23128 /* Bits[17:17], Access Type=RO, default=None*/

23129

23130 /* Reserved */

23131 UINT32 Am : 1;

23132

23133 /* Bits[18:18], Access Type=RW, default=0x00000000*/

23134

23135 /* Alignment Mask */

23136 UINT32 Rsvd19 : 10;

23137

23138 /* Bits[28:19], Access Type=RO, default=None*/

23139

23140 /* Reserved */

23141 UINT32 Nw : 1;

23142

23143 /* Bits[29:29], Access Type=RW, default=0x00000000*/

23144

23145 /*

23146 Not Write-through - During reset ucode the reset

23147 thread will write this value to a '1 for itself,

23148 and a '0 for the other thread

23149 */

23150 UINT32 Cd : 1;

23151

23152 /* Bits[30:30], Access Type=RW, default=0x00000000*/

23153

23154 /*

23155 Cache Disable - During reset ucode the reset

23156 thread will write this value to a '1 for itself,

23157 and a '0 for the other thread

23158 */

23159 UINT32 Pg : 1;

23160

23161 /* Bits[31:31], Access Type=RW, default=0x00000000*/

23162

23163 /* Paging */

23164 UINT32 Rsvd32 : 32;

23165

23166 /* Bits[63:32], Access Type=RO, default=None*/

23167

23168 /* Reserved */

23169

23170 } Bits;

23171

23172 UINT32 Uint32;

23173 UINT64 Uint64;

23174

23175 } MSR_SMRAM_CR0_REGISTER;

23176

23177 /**

23178 Available only in SMM. SMRAM copy of CR3 saved by SMI

23179 **/

23180 #define MSR_SMRAM_CR3 0x00000C01

23181

23182 typedef union {

23183 ///

23184 /// Individual bit fields

23185 ///

23186 struct {

23187 UINT32 Rsv : 3;

23188

23189 /* Bits[2:0], Access Type=RW, default=None*/

23190

23191 /* Reserved bits, reset value T0 = 3'b0, T1=3'b111 */

23192 UINT32 Pwt : 1;

23193

23194 /* Bits[3:3], Access Type=RW, default=None*/

23195

23196 /*

23197 CR3 page level cache write through, reset value

23198 T0 = 0, T1 = 1

23199 */

23200 UINT32 Pcd : 1;

23201

23202 /* Bits[4:4], Access Type=RW, default=None*/

23203

23204 /*

23205 CR3 page level cache disable reset value T0 = 0,

23206 T1 = 1

23207 */

23208 UINT32 PdptrPdb : 7;

23209

23210 /* Bits[11:5], Access Type=RW, default=None*/

23211

23212 /*

23213 PD Pntr Base, extended range for Mode-C paging,

23214 reset val T0 ? 7'h78 : 7'h07

23215 */

23216 UINT32 Pdba0 : 20;

23217

23218 /* Bits[31:12], Access Type=RW, default=None*/

23219

23220 /*

23221 CR3 page directory base address , T0 ? 20'hfffff

23222 : 20'hffff0

23223 */

23224 UINT32 Pdba1 : 21;

23225

23226 /* Bits[52:32], Access Type=RW, default=None*/

23227

23228 /*

23229 CR3 page directory base address , T0 ? 20'hfffff

23230 : 20'hffff0

23231 */

23232 UINT32 Rsvd53 : 11;

23233

23234 /* Bits[63:53], Access Type=RO, default=None*/

23235

23236 /* Reserved */

23237

23238 } Bits;

23239

23240 UINT32 Uint32;

23241 UINT64 Uint64;

23242

23243 } MSR_SMRAM_CR3_REGISTER;

23244

23245 /**

23246 Available only in SMM. SMRAM copy of EFLAGS saved by SMI

23247 **/

23248 #define MSR_SMRAM_EFLAGS 0x00000C02

23249

23250 typedef union {

23251 ///

23252 /// Individual bit fields

23253 ///

23254 struct {

23255 UINT32 Cf : 1;

23256

23257 /* Bits[0:0], Access Type=RW, default=None*/

23258

23259 /* Carry */

23260 UINT32 Rsvd1 : 1;

23261

23262 /* Bits[1:1], Access Type=RO, default=None*/

23263

23264 /* Reserved */

23265 UINT32 Pf : 1;

23266

23267 /* Bits[2:2], Access Type=RW, default=None*/

23268

23269 /* Parity */

23270 UINT32 Rsvd3 : 1;

23271

23272 /* Bits[3:3], Access Type=RO, default=None*/

23273

23274 /* Reserved */

23275 UINT32 Af : 1;

23276

23277 /* Bits[4:4], Access Type=RW, default=None*/

23278

23279 /* AuxCarry */

23280 UINT32 Rsvd5 : 1;

23281

23282 /* Bits[5:5], Access Type=RO, default=None*/

23283

23284 /* Reserved */

23285 UINT32 Zf : 1;

23286

23287 /* Bits[6:6], Access Type=RW, default=None*/

23288

23289 /* Zero */

23290 UINT32 Sf : 1;

23291

23292 /* Bits[7:7], Access Type=RW, default=None*/

23293

23294 /* Stack Fault */

23295 UINT32 Tf : 1;

23296

23297 /* Bits[8:8], Access Type=RW, default=None*/

23298

23299 /* Trap */

23300 UINT32 InterruptFlag : 1;

23301

23302 /* Bits[9:9], Access Type=RW, default=None*/

23303

23304 /* Interrupt Enable */

23305 UINT32 Df : 1;

23306

23307 /* Bits[10:10], Access Type=RW, default=None*/

23308

23309 /* Double-fault Exception */

23310 UINT32 Of : 1;

23311

23312 /* Bits[11:11], Access Type=RW, default=None*/

23313

23314 /* Overflow */

23315 UINT32 Iopl : 2;

23316

23317 /* Bits[13:12], Access Type=RW, default=None*/

23318

23319 /* I/O privilege level */

23320 UINT32 Nt : 1;

23321

23322 /* Bits[14:14], Access Type=RW, default=None*/

23323

23324 /* Nested Task */

23325 UINT32 Rsvd15 : 1;

23326

23327 /* Bits[15:15], Access Type=RO, default=None*/

23328

23329 /* Reserved */

23330 UINT32 Rf : 1;

23331

23332 /* Bits[16:16], Access Type=RW, default=None*/

23333

23334 /* Resume */

23335 UINT32 Vm : 1;

23336

23337 /* Bits[17:17], Access Type=RW, default=None*/

23338

23339 /* Virtual-8086 Mode */

23340 UINT32 Ac : 1;

23341

23342 /* Bits[18:18], Access Type=RW, default=None*/

23343

23344 /* Alignment Check */

23345 UINT32 Vif : 1;

23346

23347 /* Bits[19:19], Access Type=RW, default=None*/

23348

23349 /* Virtual Interrupt */

23350 UINT32 Vip : 1;

23351

23352 /* Bits[20:20], Access Type=RW, default=None*/

23353

23354 /* Virtual Interrupt Pending */

23355 UINT32 Id : 1;

23356

23357 /* Bits[21:21], Access Type=RW, default=None*/

23358

23359 /* Identification */

23360 UINT32 Rsvd22 : 10;

23361

23362 /* Bits[31:22], Access Type=RO, default=None*/

23363

23364 /* Reserved */

23365 UINT32 Rsvd32 : 32;

23366

23367 /* Bits[63:32], Access Type=RO, default=None*/

23368

23369 /* Reserved */

23370

23371 } Bits;

23372

23373 UINT32 Uint32;

23374 UINT64 Uint64;

23375

23376 } MSR_SMRAM_EFLAGS_REGISTER;

23377

23378 /**

23379 Available only in SMM. SMRAM copy of EFER saved by SMI

23380 **/

23381 #define MSR_SMRAM_EFER 0x00000C03

23382

23383 typedef union {

23384 ///

23385 /// Individual bit fields

23386 ///

23387 struct {

23388 UINT32 Sce : 1;

23389

23390 /* Bits[0:0], Access Type=RW, default=None*/

23391

23392 /* System Call Enable Bit */

23393 UINT32 Rsvd1 : 7;

23394

23395 /* Bits[7:1], Access Type=RO, default=None*/

23396

23397 /* Reserved */

23398 UINT32 Lme : 1;

23399

23400 /* Bits[8:8], Access Type=RW, default=None*/

23401

23402 /* Long Mode Enabled */

23403 UINT32 Rsvd9 : 1;

23404

23405 /* Bits[9:9], Access Type=RO, default=None*/

23406

23407 /* Reserved */

23408 UINT32 Lma : 1;

23409

23410 /* Bits[10:10], Access Type=RW, default=None*/

23411

23412 /* Long Mode Active */

23413 UINT32 Nxe : 1;

23414

23415 /* Bits[11:11], Access Type=RW, default=None*/

23416

23417 /* Enable No-Execute Mode */

23418 UINT32 Rsvd12 : 20;

23419

23420 /* Bits[31:12], Access Type=RO, default=None*/

23421

23422 /* Reserved */

23423 UINT32 Rsvd32 : 32;

23424

23425 /* Bits[63:32], Access Type=RO, default=None*/

23426

23427 /* Reserved */

23428

23429 } Bits;

23430

23431 UINT32 Uint32;

23432 UINT64 Uint64;

23433

23434 } MSR_SMRAM_EFER_REGISTER;

23435 /**

23436 Available only in SMM. SMRAM copy of RIP saved by SMI, introduced in HSW

23437 **/

23438 #define MSR_SMRAM_RIP 0x00000C04

23439

23440 /**

23441 Available only in SMM. SMRAM copy of DR6 saved by SMI

23442 **/

23443 #define MSR_SMRAM_DR6 0x00000C05

23444

23445 typedef union {

23446 ///

23447 /// Individual bit fields

23448 ///

23449 struct {

23450 UINT32 B0 : 1;

23451

23452 /* Bits[0:0], Access Type=RW, default=None*/

23453

23454 /* Breakpoint condition detected bit */

23455 UINT32 B1 : 1;

23456

23457 /* Bits[1:1], Access Type=RW, default=None*/

23458

23459 /* Breakpoint condition detected bit */

23460 UINT32 B2 : 1;

23461

23462 /* Bits[2:2], Access Type=RW, default=None*/

23463

23464 /* Breakpoint condition detected bit */

23465 UINT32 B3 : 1;

23466

23467 /* Bits[3:3], Access Type=RW, default=None*/

23468

23469 /* Breakpoint condition detected bit */

23470 UINT32 MustBeOneLow : 8;

23471

23472 /* Bits[11:4], Access Type=RW, default=None*/

23473

23474 /* Bits which are architecturally defined to be 1 */

23475 UINT32 MustBeZero : 1;

23476

23477 /* Bits[12:12], Access Type=RW, default=None*/

23478

23479 /* Bits which are architecturally defined to be 0 */

23480 UINT32 Bd : 1;

23481

23482 /* Bits[13:13], Access Type=RW, default=None*/

23483

23484 /*

23485 Indicates that the next instruction in the

23486 instruction stream will access one of the debug

23487 registers when a debug fault handler is reached.

23488 */

23489 UINT32 Bs : 1;

23490

23491 /* Bits[14:14], Access Type=RW, default=None*/

23492

23493 /*

23494 The debug exception was triggered by a single-

23495 step trap.

23496 */

23497 UINT32 Bt : 1;

23498

23499 /* Bits[15:15], Access Type=RW, default=None*/

23500

23501 /*

23502 The debug exception was triggered by a TSS T-bit

23503 trap.

23504 */

23505 UINT32 MustBeOneHigh : 16;

23506

23507 /* Bits[31:16], Access Type=RW, default=None*/

23508

23509 /* Bits which are architecturally defined to be 1. */

23510 UINT32 Rsvd32 : 32;

23511

23512 /* Bits[63:32], Access Type=RO, default=None*/

23513

23514 /* Reserved */

23515

23516 } Bits;

23517

23518 UINT32 Uint32;

23519 UINT64 Uint64;

23520

23521 } MSR_SMRAM_DR6_REGISTER;

23522

23523 /**

23524 Available only in SMM. SMRAM copy of DR7 saved by SMI

23525 **/

23526 #define MSR_SMRAM_DR7 0x00000C06

23527

23528 typedef union {

23529 ///

23530 /// Individual bit fields

23531 ///

23532 struct {

23533 UINT32 L0 : 1;

23534

23535 /* Bits[0:0], Access Type=RW, default=None*/

23536

23537 /* Local breakpoint enable for DR0 */

23538 UINT32 G0 : 1;

23539

23540 /* Bits[1:1], Access Type=RW, default=None*/

23541

23542 /* Global breakpoint enable for DR0 */

23543 UINT32 L1 : 1;

23544

23545 /* Bits[2:2], Access Type=RW, default=None*/

23546

23547 /* Local breakpoint enable for DR1 */

23548 UINT32 G1 : 1;

23549

23550 /* Bits[3:3], Access Type=RW, default=None*/

23551

23552 /* Global breakpoint enable for DR1 */

23553 UINT32 L2 : 1;

23554

23555 /* Bits[4:4], Access Type=RW, default=None*/

23556

23557 /* Local breakpoint enable for DR2 */

23558 UINT32 G2 : 1;

23559

23560 /* Bits[5:5], Access Type=RW, default=None*/

23561

23562 /* Global breakpoint enable for DR2 */

23563 UINT32 L3 : 1;

23564

23565 /* Bits[6:6], Access Type=RW, default=None*/

23566

23567 /* Local breakpoint enable for DR3 */

23568 UINT32 G3 : 1;

23569

23570 /* Bits[7:7], Access Type=RW, default=None*/

23571

23572 /* Global breakpoint enable for DR3 */

23573 UINT32 Le : 1;

23574

23575 /* Bits[8:8], Access Type=RW, default=None*/

23576

23577 /* Local exact breakpoint enable */

23578 UINT32 Ge : 1;

23579

23580 /* Bits[9:9], Access Type=RW, default=None*/

23581

23582 /* Global exact breakpoint enable */

23583 UINT32 Rsvd10 : 3;

23584

23585 /* Bits[12:10], Access Type=RO, default=None*/

23586

23587 /* Reserved */

23588 UINT32 Gd : 1;

23589

23590 /* Bits[13:13], Access Type=RW, default=None*/

23591

23592 /*

23593 Enables the debug register protection condition

23594 that is flagged by BD of DR6

23595 */

23596 UINT32 Rsvd14 : 2;

23597

23598 /* Bits[15:14], Access Type=RO, default=None*/

23599

23600 /* Reserved */

23601 UINT32 Rw0 : 2;

23602

23603 /* Bits[17:16], Access Type=RW, default=None*/

23604

23605 /* Breakpoint condition for DR0 */

23606 UINT32 Len0 : 2;

23607

23608 /* Bits[19:18], Access Type=RW, default=None*/

23609

23610 /* Size of memory breakpoint location for DR0 */

23611 UINT32 Rw1 : 2;

23612

23613 /* Bits[21:20], Access Type=RW, default=None*/

23614

23615 /* Breakpoint condition for DR1 */

23616 UINT32 Len1 : 2;

23617

23618 /* Bits[23:22], Access Type=RW, default=None*/

23619

23620 /* Size of memory breakpoint location for DR1 */

23621 UINT32 Rw2 : 2;

23622

23623 /* Bits[25:24], Access Type=RW, default=None*/

23624

23625 /* Breakpoint condition for DR2 */

23626 UINT32 Len2 : 2;

23627

23628 /* Bits[27:26], Access Type=RW, default=None*/

23629

23630 /* Size of memory breakpoint location for DR2 */

23631 UINT32 Rw3 : 2;

23632

23633 /* Bits[29:28], Access Type=RW, default=None*/

23634

23635 /* Breakpoint condition for DR3 */

23636 UINT32 Len3 : 2;

23637

23638 /* Bits[31:30], Access Type=RW, default=None*/

23639

23640 /* Size of memory breakpoint location for DR3 */

23641 UINT32 Rsvd32 : 32;

23642

23643 /* Bits[63:32], Access Type=RO, default=None*/

23644

23645 /* Reserved */

23646

23647 } Bits;

23648

23649 UINT32 Uint32;

23650 UINT64 Uint64;

23651

23652 } MSR_SMRAM_DR7_REGISTER;

23653

23654 /**

23655 Available only in SMM. SMRAM copy of TR Sel and LDTR Sel saved by SMI

23656 **/

23657 #define MSR_SMRAM_TR_LDTR 0x00000C07

23658

23659 typedef union {

23660 ///

23661 /// Individual bit fields

23662 ///

23663 struct {

23664 UINT32 LdtrSel : 16;

23665

23666 /* Bits[15:0], Access Type=RW, default=None*/

23667

23668 /* LDTR Selector */

23669 UINT32 Rsvd16 : 16;

23670

23671 /* Bits[31:16], Access Type=RO, default=None*/

23672

23673 /* Reserved */

23674 UINT32 TrSel : 16;

23675

23676 /* Bits[47:32], Access Type=RW, default=None*/

23677

23678 /* TR Selector */

23679 UINT32 Rsvd48 : 16;

23680

23681 /* Bits[63:48], Access Type=RO, default=None*/

23682

23683 /* Reserved */

23684

23685 } Bits;

23686

23687 UINT32 Uint32;

23688 UINT64 Uint64;

23689

23690 } MSR_SMRAM_TR_LDTR_REGISTER;

23691

23692 /**

23693 Available only in SMM. SMRAM copy of GS and FS saved by SMI

23694 **/

23695 #define MSR_SMRAM_GS_FS 0x00000C08

23696

23697 typedef union {

23698 ///

23699 /// Individual bit fields

23700 ///

23701 struct {

23702 UINT32 Fs : 16;

23703

23704 /* Bits[15:0], Access Type=RW, default=None*/

23705

23706 /* FS */

23707 UINT32 Rsvd16 : 16;

23708

23709 /* Bits[31:16], Access Type=RO, default=None*/

23710

23711 /* Reserved */

23712 UINT32 Gs : 16;

23713

23714 /* Bits[47:32], Access Type=RW, default=None*/

23715

23716 /* GS */

23717 UINT32 Rsvd48 : 16;

23718

23719 /* Bits[63:48], Access Type=RO, default=None*/

23720

23721 /* Reserved */

23722

23723 } Bits;

23724

23725 UINT32 Uint32;

23726 UINT64 Uint64;

23727

23728 } MSR_SMRAM_GS_FS_REGISTER;

23729

23730 /**

23731 Available only in SMM. SMRAM copy of DS and SS saved by SMI

23732 **/

23733 #define MSR_SMRAM_DS_SS 0x00000C09

23734

23735 typedef union {

23736 ///

23737 /// Individual bit fields

23738 ///

23739 struct {

23740 UINT32 Ss : 16;

23741

23742 /* Bits[15:0], Access Type=RW, default=None*/

23743

23744 /* FS */

23745 UINT32 Rsvd16 : 16;

23746

23747 /* Bits[31:16], Access Type=RO, default=None*/

23748

23749 /* Reserved */

23750 UINT32 Ds : 16;

23751

23752 /* Bits[47:32], Access Type=RW, default=None*/

23753

23754 /* GS */

23755 UINT32 Rsvd48 : 16;

23756

23757 /* Bits[63:48], Access Type=RO, default=None*/

23758

23759 /* Reserved */

23760

23761 } Bits;

23762

23763 UINT32 Uint32;

23764 UINT64 Uint64;

23765

23766 } MSR_SMRAM_DS_SS_REGISTER;

23767

23768 /**

23769 Available only in SMM. SMRAM copy of CS and ES saved by SMI

23770 **/

23771 #define MSR_SMRAM_CS_ES 0x00000C0A

23772

23773 typedef union {

23774 ///

23775 /// Individual bit fields

23776 ///

23777 struct {

23778 UINT32 Es : 16;

23779

23780 /* Bits[15:0], Access Type=RW, default=None*/

23781

23782 /* FS */

23783 UINT32 Rsvd16 : 16;

23784

23785 /* Bits[31:16], Access Type=RO, default=None*/

23786

23787 /* Reserved */

23788 UINT32 Cs : 16;

23789

23790 /* Bits[47:32], Access Type=RW, default=None*/

23791

23792 /* GS */

23793 UINT32 Rsvd48 : 16;

23794

23795 /* Bits[63:48], Access Type=RO, default=None*/

23796

23797 /* Reserved */

23798

23799 } Bits;

23800

23801 UINT32 Uint32;

23802 UINT64 Uint64;

23803

23804 } MSR_SMRAM_CS_ES_REGISTER;

23805

23806 /**

23807 Available only in SMM. SMRAM copy of IOMISCINFO saved by SMI

23808 **/

23809 #define MSR_SMRAM_IOMISCINFO 0x00000C0B

23810

23811 typedef union {

23812 ///

23813 /// Individual bit fields

23814 ///

23815 struct {

23816 UINT32 Iomiscinfo : 32;

23817

23818 /* Bits[31:0], Access Type=RW, default=None*/

23819

23820 /* Copy of ROB IOMISCINFO */

23821 UINT32 Rsvd32 : 32;

23822

23823 /* Bits[63:32], Access Type=RO, default=None*/

23824

23825 /* Reserved */

23826

23827 } Bits;

23828

23829 UINT32 Uint32;

23830 UINT64 Uint64;

23831

23832 } MSR_SMRAM_IOMISCINFO_REGISTER;

23833 /**

23834 Available only in SMM. SMRAM copy of IO_MEM_ADDR saved by SMI

23835 **/

23836 #define MSR_SMRAM_IO_MEM_ADDR 0x00000C0C

23837 /**

23838 Available only in SMM. SMRAM copy of RDI saved by SMI

23839 **/

23840 #define MSR_SMRAM_RDI 0x00000C0D

23841 /**

23842 Available only in SMM. SMRAM copy of RSI saved by SMI

23843 **/

23844 #define MSR_SMRAM_RSI 0x00000C0E

23845 /**

23846 Available only in SMM. SMRAM copy of RBP saved by SMI

23847 **/

23848 #define MSR_SMRAM_RBP 0x00000C0F

23849 /**

23850 Available only in SMM. SMRAM copy of RSP saved by SMI

23851 **/

23852 #define MSR_SMRAM_RSP 0x00000C10

23853 /**

23854 Available only in SMM. SMRAM copy of RBX saved by SMI

23855 **/

23856 #define MSR_SMRAM_RBX 0x00000C11

23857 /**

23858 Available only in SMM. SMRAM copy of RDX saved by SMI

23859 **/

23860 #define MSR_SMRAM_RDX 0x00000C12

23861 /**

23862 Available only in SMM. SMRAM copy of RCX saved by SMI

23863 **/

23864 #define MSR_SMRAM_RCX 0x00000C13

23865 /**

23866 Available only in SMM. SMRAM copy of RAX saved by SMI

23867 **/

23868 #define MSR_SMRAM_RAX 0x00000C14

23869 /**

23870 Available only in SMM. SMRAM copy of R8 saved by SMI

23871 **/

23872 #define MSR_SMRAM_R8 0x00000C15

23873 /**

23874 Available only in SMM. SMRAM copy of R9 saved by SMI

23875 **/

23876 #define MSR_SMRAM_R9 0x00000C16

23877 /**

23878 Available only in SMM. SMRAM copy of R10 saved by SMI

23879 **/

23880 #define MSR_SMRAM_R10 0x00000C17

23881 /**

23882 Available only in SMM. SMRAM copy of R11 saved by SMI

23883 **/

23884 #define MSR_SMRAM_R11 0x00000C18

23885 /**

23886 Available only in SMM. SMRAM copy of R12 saved by SMI

23887 **/

23888 #define MSR_SMRAM_R12 0x00000C19

23889 /**

23890 Available only in SMM. SMRAM copy of R13 saved by SMI

23891 **/

23892 #define MSR_SMRAM_R13 0x00000C1A

23893 /**

23894 Available only in SMM. SMRAM copy of R14 saved by SMI

23895 **/

23896 #define MSR_SMRAM_R14 0x00000C1B

23897 /**

23898 Available only in SMM. SMRAM copy of RDI saved by SMI

23899 **/

23900 #define MSR_SMRAM_R15 0x00000C1C

23901

23902 /**

23903 Available only in SMM. SMRAM copy of EVENT_CTL, HLT flag and IO flag saved by SMI

23904 **/

23905 #define MSR_SMRAM_EVENT_CTL_HLT_IO 0x00000C1F

23906

23907 typedef union {

23908 ///

23909 /// Individual bit fields

23910 ///

23911 struct {

23912 UINT32 IoFlag : 16;

23913

23914 /* Bits[15:0], Access Type=RW, default=None*/

23915

23916 /* Copy of IO Flag */

23917 UINT32 HltFlag : 16;

23918

23919 /* Bits[31:16], Access Type=RW, default=None*/

23920

23921 /* Copy of HLT Flag */

23922 UINT32 EventCtl : 16;

23923

23924 /* Bits[47:32], Access Type=RW, default=None*/

23925

23926 /* Copy of EVENT_CTL */

23927 UINT32 Rsvd48 : 16;

23928

23929 /* Bits[63:48], Access Type=RO, default=None*/

23930

23931 /* Reserved */

23932

23933 } Bits;

23934

23935 UINT32 Uint32;

23936 UINT64 Uint64;

23937

23938 } MSR_SMRAM_EVENT_CTL_HLT_IO_REGISTER;

23939

23940 /**

23941 Available only in SMM. SMRAM copy of SMBASE saved by SMI

23942 **/

23943 #define MSR_SMRAM_SMBASE 0x00000C20

23944

23945 typedef union {

23946 ///

23947 /// Individual bit fields

23948 ///

23949 struct {

23950 UINT32 Smbase : 32;

23951

23952 /* Bits[31:0], Access Type=RW, default=None*/

23953

23954 /* Copy of SMBASE */

23955 UINT32 Rsvd32 : 32;

23956

23957 /* Bits[63:32], Access Type=RO, default=None*/

23958

23959 /* Reserved */

23960

23961 } Bits;

23962

23963 UINT32 Uint32;

23964 UINT64 Uint64;

23965

23966 } MSR_SMRAM_SMBASE_REGISTER;

23967

23968 /**

23969 Available only in SMM. SMRAM copy of SMM_REVID saved by SMI

23970 **/

23971 #define MSR_SMRAM_SMM_REVID 0x00000C21

23972

23973 typedef union {

23974 ///

23975 /// Individual bit fields

23976 ///

23977 struct {

23978 UINT32 SmmRevid : 32;

23979

23980 /* Bits[31:0], Access Type=RW, default=None*/

23981

23982 /* Copy of SMM_REVID */

23983 UINT32 Rsvd32 : 32;

23984

23985 /* Bits[63:32], Access Type=RO, default=None*/

23986

23987 /* Reserved */

23988

23989 } Bits;

23990

23991 UINT32 Uint32;

23992 UINT64 Uint64;

23993

23994 } MSR_SMRAM_SMM_REVID_REGISTER;

23995

23996 /**

23997 Available only in SMM. SMRAM copy of IEDBASE saved by SMI

23998 **/

23999 #define MSR_SMRAM_IEDBASE 0x00000C22

24000

24001 typedef union {

24002 ///

24003 /// Individual bit fields

24004 ///

24005 struct {

24006 UINT32 Rsvd0 : 32;

24007

24008 /* Bits[31:0], Access Type=RO, default=None*/

24009

24010 /* Reserved */

24011 UINT32 Iedbase : 32;

24012

24013 /* Bits[63:32], Access Type=RW, default=None*/

24014

24015 /* Copy of IEDBASE */

24016

24017 } Bits;

24018

24019 UINT32 Uint32;

24020 UINT64 Uint64;

24021

24022 } MSR_SMRAM_IEDBASE_REGISTER;

24023

24024 /**

24025 Available only in SMM. SMRAM copy of EPTP_ENABLE saved by SMI

24026 **/

24027 #define MSR_SMRAM_EPTP_ENABLE 0x00000C23

24028

24029 typedef union {

24030 ///

24031 /// Individual bit fields

24032 ///

24033 struct {

24034 UINT32 EptpEnable : 1;

24035

24036 /* Bits[0:0], Access Type=RW, default=None*/

24037

24038 /* Copy of EPTP_ENABLE */

24039 UINT32 EnclaveInterruption : 1;

24040

24041 /* Bits[1:1], Access Type=RW, default=None*/

24042

24043 /* Copy of ENCLAVE_INTERRUPTION */

24044 UINT32 Rsvd2 : 30;

24045

24046 /* Bits[31:2], Access Type=RO, default=None*/

24047

24048 /* Reserved */

24049 UINT32 Rsvd32 : 32;

24050

24051 /* Bits[63:32], Access Type=RO, default=None*/

24052

24053 /* Reserved */

24054

24055 } Bits;

24056

24057 UINT32 Uint32;

24058 UINT64 Uint64;

24059

24060 } MSR_SMRAM_EPTP_ENABLE_REGISTER;

24061 /**

24062 Available only in SMM. SMRAM copy of EPTP saved by SMI

24063 **/

24064 #define MSR_SMRAM_EPTP 0x00000C24

24065 /**

24066 Available only in SMM. SMRAM copy of BNDCFGS saved by SMI

24067 **/

24068 #define MSR_SMRAM_BNDCFGS 0x00000C25

24069 /**

24070 Available only in SMM. SMRAM copy of LDTR_BASE saved by SMI

24071 **/

24072 #define MSR_SMRAM_LDTR_BASE 0x00000C2C

24073 /**

24074 Available only in SMM. SMRAM copy of IDTR_BASE saved by SMI

24075 **/

24076 #define MSR_SMRAM_IDTR_BASE 0x00000C2D

24077 /**

24078 Available only in SMM. SMRAM copy of IDTR_BASE saved by SMI

24079 **/

24080 #define MSR_SMRAM_GDTR_BASE 0x00000C2E

24081

24082 /**

24083 Available only in SMM. SMRAM copy of CR0 saved by SMI

24084 **/

24085 #define MSR_SMRAM_CR4 0x00000C37

24086

24087 typedef union {

24088 ///

24089 /// Individual bit fields

24090 ///

24091 struct {

24092 UINT32 Vme : 1;

24093

24094 /* Bits[0:0], Access Type=RW, default=None*/

24095

24096 /* Enables virtual 8086-mode extensions */

24097 UINT32 Pvi : 1;

24098

24099 /* Bits[1:1], Access Type=RW, default=None*/

24100

24101 /* Protected-Mode Virtual Interrupts */

24102 UINT32 Tsd : 1;

24103

24104 /* Bits[2:2], Access Type=RW, default=None*/

24105

24106 /* Time Stamp Disable */

24107 UINT32 De : 1;

24108

24109 /* Bits[3:3], Access Type=RW, default=None*/

24110

24111 /* Debugging Extensions */

24112 UINT32 Pse : 1;

24113

24114 /* Bits[4:4], Access Type=RW, default=None*/

24115

24116 /* Page Size Extensions */

24117 UINT32 Pae : 1;

24118

24119 /* Bits[5:5], Access Type=RW, default=None*/

24120

24121 /* Physical Address Extension */

24122 UINT32 Mce : 1;

24123

24124 /* Bits[6:6], Access Type=RW, default=None*/

24125

24126 /* Machine check Enable */

24127 UINT32 Pge : 1;

24128

24129 /* Bits[7:7], Access Type=RW, default=None*/

24130

24131 /* Page Global Enable */

24132 UINT32 Pce : 1;

24133

24134 /* Bits[8:8], Access Type=RW, default=None*/

24135

24136 /* Performance-monitoring Counter Enable */

24137 UINT32 Osfxsr : 1;

24138

24139 /* Bits[9:9], Access Type=RW, default=None*/

24140

24141 /* Enables the fast FXsave and FXrestore */

24142 UINT32 Xmmexc : 1;

24143

24144 /* Bits[10:10], Access Type=RW, default=None*/

24145

24146 /* Enables the exceptions for Katmia */

24147 UINT32 Umip : 1;

24148

24149 /* Bits[11:11], Access Type=RW, default=None*/

24150

24151 /* UMIP Enable */

24152 UINT32 Rsvd12 : 1;

24153

24154 /* Bits[12:12], Access Type=RO, default=None*/

24155

24156 /* Reserved */

24157 UINT32 VmxEnable : 1;

24158

24159 /* Bits[13:13], Access Type=RW, default=None*/

24160

24161 /* Logic 1 indicates that VMX is enabled */

24162 UINT32 SmxEnable : 1;

24163

24164 /* Bits[14:14], Access Type=RW, default=None*/

24165

24166 /* Logic 1 indicates that SMX is enabled */

24167 UINT32 Slc64 : 1;

24168

24169 /* Bits[15:15], Access Type=RW, default=None*/

24170

24171 /* Logic 1 indicates that SLC64 is enabled */

24172 UINT32 FsGsBase : 1;

24173

24174 /* Bits[16:16], Access Type=RW, default=None*/

24175

24176 /*

24177 Logic 1 indicates that Ring3 Segment Base Access

24178 is enabled. This allows reading/writing the

24179 FS/GS segment bases through instructions

24180 RDFSBASE. WRFSBASE, RDGSBASE or WRGSBASE.

24181 */

24182 UINT32 Pcide : 1;

24183

24184 /* Bits[17:17], Access Type=RW, default=None*/

24185

24186 /* Logic 1 indicates that PCID is enabled */

24187 UINT32 Osxsave : 1;

24188

24189 /* Bits[18:18], Access Type=RW, default=None*/

24190

24191 /* Logic 1 indicates that XSAVE is enabled */

24192 UINT32 Rsvd19 : 4;

24193

24194 /* Bits[22:19], Access Type=RO, default=None*/

24195

24196 /* Reserved */

24197 UINT32 La57 : 1;

24198

24199 /* Bits[23:23], Access Type=RW, default=None*/

24200

24201 /* Logic 1 indicates that VA of 57 width is enabled */

24202 UINT32 Rsvd24 : 8;

24203

24204 /* Bits[31:24], Access Type=RO, default=None*/

24205

24206 /* Reserved */

24207 UINT32 Rsvd32 : 32;

24208

24209 /* Bits[63:32], Access Type=RO, default=None*/

24210

24211 /* Reserved */

24212

24213 } Bits;

24214

24215 UINT32 Uint32;

24216 UINT64 Uint64;

24217

24218 } MSR_SMRAM_CR4_REGISTER;

24219 /**

24220 Available only in SMM. SMRAM copy of IO_RSI saved by SMI

24221 **/

24222 #define MSR_SMRAM_IO_RSI 0x00000C40

24223 /**

24224 Available only in SMM. SMRAM copy of IO_RCX saved by SMI

24225 **/

24226 #define MSR_SMRAM_IO_RCX 0x00000C41

24227 /**

24228 Available only in SMM. SMRAM copy of IO_RIP saved by SMI

24229 **/

24230 #define MSR_SMRAM_IO_RIP 0x00000C42

24231 /**

24232 Available only in SMM. SMRAM copy of IO_RDI saved by SMI

24233 **/

24234 #define MSR_SMRAM_IO_RDI 0x00000C43

24235

24236 /**

24237 CDP enable

24238 **/

24239 #define MSR_PQOS_CDP_ENABLE 0x00000C81

24240

24241 typedef union {

24242 ///

24243 /// Individual bit fields

24244 ///

24245 struct {

24246 UINT32 Cdp : 1;

24247

24248 /* Bits[0:0], Access Type=RW, default=0x00000000*/

24249

24250 /* enable */

24251 UINT32 Rsvd1 : 31;

24252

24253 /* Bits[31:1], Access Type=RO, default=None*/

24254

24255 /* Reserved */

24256

24257 } Bits;

24258

24259 UINT32 Uint32;

24260 UINT64 Uint64;

24261

24262 } MSR_PQOS_CDP_ENABLE_REGISTER;

24263

24264 /**

24265 IO QOS cfg

24266 **/

24267 #define MSR_IO_QOS_CFG 0x00000C83

24268

24269 typedef union {

24270 ///

24271 /// Individual bit fields

24272 ///

24273 struct {

24274 UINT32 IoQosEnf : 1;

24275

24276 /* Bits[0:0], Access Type=RW, default=0x00000000*/

24277

24278 /* IIO qos enf enable */

24279 UINT32 IoQosMon : 1;

24280

24281 /* Bits[1:1], Access Type=RW, default=0x00000000*/

24282

24283 /* IIO qos mon enable - RSVD in ICX */

24284 UINT32 Rsvd2 : 30;

24285

24286 /* Bits[31:2], Access Type=RO, default=None*/

24287

24288 /* Reserved */

24289

24290 } Bits;

24291

24292 UINT32 Uint32;

24293 UINT64 Uint64;

24294

24295 } MSR_IO_QOS_CFG_REGISTER;

24296

24297 /**

24298 MBA (mem bandwidth alloc) cfg

24299 **/

24300 #define MSR_MBA_CFG 0x00000C84

24301

24302 typedef union {

24303 ///

24304 /// Individual bit fields

24305 ///

24306 struct {

24307 UINT32 MinMaxDelay : 1;

24308

24309 /* Bits[0:0], Access Type=RW, default=0x00000000*/

24310

24311 /* Min (0) or Max (1) of per-core CLOS delays */

24312 UINT32 MbaEn : 1;

24313

24314 /* Bits[1:1], Access Type=RW, default=0x00000000*/

24315

24316 /* MBA hardware ctrlr enable */

24317 UINT32 Rsvd2 : 30;

24318

24319 /* Bits[31:2], Access Type=RO, default=None*/

24320

24321 /* Reserved */

24322

24323 } Bits;

24324

24325 UINT32 Uint32;

24326 UINT64 Uint64;

24327

24328 } MSR_MBA_CFG_REGISTER;

24329

24330 /**

24331 way mask for locked LLC ways. If the hit way intersects this mask, LLC to SF migration is disabled

24332 **/

24333 #define MSR_L3_PROTECTED_WAYS 0x00000C85

24334

24335 typedef union {

24336 ///

24337 /// Individual bit fields

24338 ///

24339 struct {

24340 UINT32 Mask : 20;

24341

24342 /* Bits[19:0], Access Type=RW, default=0x00000000*/

24343

24344 /* way mask */

24345 UINT32 Rsvd20 : 12;

24346

24347 /* Bits[31:20], Access Type=RO, default=None*/

24348

24349 /* Reserved */

24350 UINT32 Rsvd32 : 32;

24351

24352 /* Bits[63:32], Access Type=RO, default=None*/

24353

24354 /* Reserved */

24355

24356 } Bits;

24357

24358 UINT32 Uint32;

24359 UINT64 Uint64;

24360

24361 } MSR_L3_PROTECTED_WAYS_REGISTER;

24362

24363 /**

24364 model specific msr to enable maksing of events that MBM counts

24365 **/

24366 #define MSR_MBM_CFG_3DXP 0x00000C86

24367

24368 typedef union {

24369 ///

24370 /// Individual bit fields

24371 ///

24372 struct {

24373 UINT32 Mbmcountnonddrt : 1;

24374

24375 /* Bits[0:0], Access Type=RW, default=0x00000000*/

24376

24377 /* dram bw included in count */

24378 UINT32 Mbmcountddrt : 1;

24379

24380 /* Bits[1:1], Access Type=RW, default=0x00000000*/

24381

24382 /* 3dxp bw included in count */

24383 UINT32 Rsvd2 : 30;

24384

24385 /* Bits[31:2], Access Type=RO, default=None*/

24386

24387 /* Reserved */

24388 UINT32 Rsvd32 : 32;

24389

24390 /* Bits[63:32], Access Type=RO, default=None*/

24391

24392 /* Reserved */

24393

24394 } Bits;

24395

24396 UINT32 Uint32;

24397 UINT64 Uint64;

24398

24399 } MSR_MBM_CFG_3DXP_REGISTER;

24400

24401 /**

24402 uCR: LRU Update values for various opcodes that update the LRU bits.

24403 **/

24404 #define MSR_QLRU_CONFIG 0x00000C8C

24405

24406 typedef union {

24407 ///

24408 /// Individual bit fields

24409 ///

24410 struct {

24411 UINT32 Cr0 : 2;

24412

24413 /* Bits[1:0], Access Type=RW, default=0x00000003*/

24414

24415 /* LRU Age Update value for CRd/Monitor on LLC Hit */

24416 UINT32 Cr1 : 2;

24417

24418 /* Bits[3:2], Access Type=RW, default=0x00000003*/

24419

24420 /*

24421 LRU Age Update value for Prefetch Code (to MLC)

24422 on LLC Hit

24423 */

24424 UINT32 Cr2 : 2;

24425

24426 /* Bits[5:4], Access Type=RW, default=0x00000002*/

24427

24428 /*

24429 LRU Age Update value for Prefetch Code (to LLC)

24430 on LLC Hit

24431 */

24432 UINT32 Cr3 : 2;

24433

24434 /* Bits[7:6], Access Type=RW, default=0x00000002*/

24435

24436 /*

24437 LRU Age Update value for DRd/RFO/DRdPTE/ItoM on

24438 LLC Hit

24439 */

24440 UINT32 Cr4 : 2;

24441

24442 /* Bits[9:8], Access Type=RW, default=0x00000002*/

24443

24444 /*

24445 LRU Age Update value for Prefetch data (to MLC)

24446 on LLC Hit

24447 */

24448 UINT32 Cr5 : 2;

24449

24450 /* Bits[11:10], Access Type=RW, default=0x00000002*/

24451

24452 /*

24453 LRU Age Update value for PrefRFO / PrefData (to

24454 LLC) on LLC Hit

24455 */

24456 UINT32 Cr6 : 2;

24457

24458 /* Bits[13:12], Access Type=RW, default=0x00000003*/

24459

24460 /*

24461 LRU Age Update value for CRd / Monitor on LLC

24462 Miss (Normal Fill)

24463 */

24464 UINT32 Cr7 : 2;

24465

24466 /* Bits[15:14], Access Type=RW, default=0x00000003*/

24467

24468 /*

24469 LRU Age Update value for Prefetch Code (to MLC)

24470 on LLC Miss (Normal Fill)

24471 */

24472 UINT32 Cr8 : 2;

24473

24474 /* Bits[17:16], Access Type=RW, default=0x00000001*/

24475

24476 /*

24477 LRU Age Update value for Prefetch Code (to LLC)

24478 on LLC Miss (Normal Fill)

24479 */

24480 UINT32 Cr9 : 2;

24481

24482 /* Bits[19:18], Access Type=RW, default=0x00000002*/

24483

24484 /*

24485 LRU Age Update value for DRd / RFO / DRdPTE /

24486 ItoM on LLC Miss (Normal Fill)

24487 */

24488 UINT32 CrB : 2;

24489

24490 /* Bits[21:20], Access Type=RW, default=0x00000001*/

24491

24492 /*

24493 LRU Age Update value for Prefetch data (to MLC)

24494 on LLC Miss (Normal Fill)

24495 */

24496 UINT32 CrD : 2;

24497

24498 /* Bits[23:22], Access Type=RW, default=0x00000001*/

24499

24500 /*

24501 LRU Age Update value for PrefRFO / PrefData (to

24502 LLC) on LLC Miss (Normal Fill)

24503 */

24504 UINT32 CrF : 2;

24505

24506 /* Bits[25:24], Access Type=RW, default=0x00000003*/

24507

24508 /*

24509 LRU Age Update value for demand read and MLC

24510 prefetche on LLC Hit, when the current age is

24511 2/3.

24512 */

24513 UINT32 Cr10 : 2;

24514

24515 /* Bits[27:26], Access Type=RW, default=0x00000002*/

24516

24517 /* LRU Age update value for IIO requests on LLC Hit */

24518 UINT32 Cr11 : 2;

24519

24520 /* Bits[29:28], Access Type=RW, default=0x00000001*/

24521

24522 /* LRU Age update for IIO requests on LLC Miss */

24523 UINT32 Cr12 : 2;

24524

24525 /* Bits[31:30], Access Type=RW, default=0x00000001*/

24526

24527 /* LRU Age update for Writebacks */

24528 UINT32 Cr13 : 2;

24529

24530 /* Bits[33:32], Access Type=RW, default=0x00000003*/

24531

24532 /* LRU Age update for WbPushHint */

24533 UINT32 Rsvd34 : 10;

24534

24535 /* Bits[43:34], Access Type=RW, default=0x00000000*/

24536

24537 /* LRU Age update for WbPushHint */

24538 UINT32 Cr6Llc : 2;

24539

24540 /* Bits[45:44], Access Type=RW, default=0x00000001*/

24541

24542 /*

24543 LRU Age Update value for CRd / Monitor on LLC

24544 allocate

24545 */

24546 UINT32 Cr7Llc : 2;

24547

24548 /* Bits[47:46], Access Type=RW, default=0x00000001*/

24549

24550 /*

24551 LRU Age Update value for Prefetch Code (to MLC)

24552 on LLC allocate

24553 */

24554 UINT32 Rsvd48 : 2;

24555

24556 /* Bits[49:48], Access Type=RW, default=0x00000001*/

24557

24558 /* Rserved */

24559 UINT32 Cr9Llc : 2;

24560

24561 /* Bits[51:50], Access Type=RW, default=0x00000001*/

24562

24563 /*

24564 LRU Age Update value for DRd / RFO / DRdPTE /

24565 ItoM on LLC Miss (Vulnerable Fill)

24566 */

24567 UINT32 CrBLlc : 2;

24568

24569 /* Bits[53:52], Access Type=RW, default=0x00000001*/

24570

24571 /*

24572 LRU Age Update value for Prefetch data (to MLC)

24573 on LLC Miss (Vulnerable Fill)

24574 */

24575 UINT32 Cr14 : 2;

24576

24577 /* Bits[55:54], Access Type=RW, default=0x00000000*/

24578

24579 /* LRU Age update for CLCleanse */

24580 UINT32 Cr15 : 2;

24581

24582 /* Bits[57:56], Access Type=RW, default=0x00000003*/

24583

24584 /* LRU Age update for LLC allocation from SF Victim */

24585 UINT32 Cr16 : 2;

24586

24587 /* Bits[59:58], Access Type=RW, default=0x00000000*/

24588

24589 /* LRU Age update for Remote Requests */

24590 UINT32 Rsvd60 : 2;

24591

24592 /* Bits[61:60], Access Type=RW, default=0x00000001*/

24593

24594 /* Rserved */

24595 UINT32 Rsvd62 : 2;

24596

24597 /* Bits[63:62], Access Type=RW, default=0x00000000*/

24598

24599 /* Rserved */

24600

24601 } Bits;

24602

24603 UINT32 Uint32;

24604 UINT64 Uint64;

24605

24606 } MSR_QLRU_CONFIG_REGISTER;

24607

24608 /**

24609 MSR that is used to receive query id from software for which data will be looked up by another MSR

24610 **/

24611 #define MSR_QOSEVTSEL 0x00000C8D

24612

24613 typedef union {

24614 ///

24615 /// Individual bit fields

24616 ///

24617 struct {

24618 UINT32 Evtid : 8;

24619

24620 /* Bits[7:0], Access Type=RW, default=0x00000000*/

24621

24622 /*

24623 0x01 for LLC occupancy monitoring, 0x00 for no

24624 monitoring, remaining for future extensibility

24625 */

24626 UINT32 Rsvd8 : 24;

24627

24628 /* Bits[31:8], Access Type=RO, default=None*/

24629

24630 /* Reserved */

24631 UINT32 Rmid : 10;

24632

24633 /* Bits[41:32], Access Type=RW, default=0x00000000*/

24634

24635 /* 1 = unquiesce initiated */

24636 UINT32 Rsvd42 : 22;

24637

24638 /* Bits[63:42], Access Type=RO, default=None*/

24639

24640 /* Reserved */

24641

24642 } Bits;

24643

24644 UINT32 Uint32;

24645 UINT64 Uint64;

24646

24647 } MSR_QOSEVTSEL_REGISTER;

24648

24649 /**

24650 MSR that is used to convey the counter value for the RMID queried by the QOSEVTSEL MSR. This is a Read only MSR.

24651 **/

24652 #define MSR_QMC 0x00000C8E

24653

24654 typedef union {

24655 ///

24656 /// Individual bit fields

24657 ///

24658 struct {

24659 UINT32 MonitoringData0 : 32;

24660

24661 /* Bits[31:0], Access Type=RW, default=0x00000000*/

24662

24663 /* Data for corresponding RMID is populated in this */

24664 UINT32 MonitoringData1 : 30;

24665

24666 /* Bits[61:32], Access Type=RW, default=0x00000000*/

24667

24668 /* Data for corresponding RMID is populated in this */

24669 UINT32 Availability : 1;

24670

24671 /* Bits[62:62], Access Type=RW, default=0x00000000*/

24672

24673 /* 1 = if data available, 0 if data not available */

24674 UINT32 Error : 1;

24675

24676 /* Bits[63:63], Access Type=RW, default=0x00000000*/

24677

24678 /* 1 = Error, 0 = no error */

24679

24680 } Bits;

24681

24682 UINT32 Uint32;

24683 UINT64 Uint64;

24684

24685 } MSR_QMC_REGISTER;

24686

24687 /**

24688 available ways vectors for class of service of IA core

24689 **/

24690 #define MSR_LLC_QOS_MASK_0 0x00000C90

24691

24692 typedef union {

24693 ///

24694 /// Individual bit fields

24695 ///

24696 struct {

24697 UINT32 CosWaysMask : 20;

24698

24699 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24700

24701 /*

24702 available ways vectors for class of service of

24703 IA core restrictions: Only contiguous 1s are

24704 allowed.

24705 */

24706 UINT32 Rsvd20 : 12;

24707

24708 /* Bits[31:20], Access Type=RO, default=None*/

24709

24710 /* Reserved */

24711

24712 } Bits;

24713

24714 UINT32 Uint32;

24715 UINT64 Uint64;

24716

24717 } MSR_LLC_QOS_MASK_0_REGISTER;

24718

24719 /**

24720 available ways vectors for class of service of IA core

24721 **/

24722 #define MSR_LLC_QOS_MASK_1 0x00000C91

24723

24724 typedef union {

24725 ///

24726 /// Individual bit fields

24727 ///

24728 struct {

24729 UINT32 CosWaysMask : 20;

24730

24731 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24732

24733 /*

24734 available ways vectors for class of service of

24735 IA core restrictions: Only contiguous 1s are

24736 allowed.

24737 */

24738 UINT32 Rsvd20 : 12;

24739

24740 /* Bits[31:20], Access Type=RO, default=None*/

24741

24742 /* Reserved */

24743

24744 } Bits;

24745

24746 UINT32 Uint32;

24747 UINT64 Uint64;

24748

24749 } MSR_LLC_QOS_MASK_1_REGISTER;

24750

24751 /**

24752 available ways vectors for class of service of IA core

24753 **/

24754 #define MSR_LLC_QOS_MASK_2 0x00000C92

24755

24756 typedef union {

24757 ///

24758 /// Individual bit fields

24759 ///

24760 struct {

24761 UINT32 CosWaysMask : 20;

24762

24763 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24764

24765 /*

24766 available ways vectors for class of service of

24767 IA core restrictions: Only contiguous 1s are

24768 allowed.

24769 */

24770 UINT32 Rsvd20 : 12;

24771

24772 /* Bits[31:20], Access Type=RO, default=None*/

24773

24774 /* Reserved */

24775

24776 } Bits;

24777

24778 UINT32 Uint32;

24779 UINT64 Uint64;

24780

24781 } MSR_LLC_QOS_MASK_2_REGISTER;

24782

24783 /**

24784 available ways vectors for class of service of IA core

24785 **/

24786 #define MSR_LLC_QOS_MASK_3 0x00000C93

24787

24788 typedef union {

24789 ///

24790 /// Individual bit fields

24791 ///

24792 struct {

24793 UINT32 CosWaysMask : 20;

24794

24795 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24796

24797 /*

24798 available ways vectors for class of service of

24799 IA core restrictions: Only contiguous 1s are

24800 allowed.

24801 */

24802 UINT32 Rsvd20 : 12;

24803

24804 /* Bits[31:20], Access Type=RO, default=None*/

24805

24806 /* Reserved */

24807

24808 } Bits;

24809

24810 UINT32 Uint32;

24811 UINT64 Uint64;

24812

24813 } MSR_LLC_QOS_MASK_3_REGISTER;

24814

24815 /**

24816 available ways vectors for class of service of IA core

24817 " seq has 12 instances in addresses range 0x94 to 0x9F"

24818 **/

24819 #define MSR_LLC_QOS_MASK_4_4 0x00000C94

24820

24821 typedef union {

24822 ///

24823 /// Individual bit fields

24824 ///

24825 struct {

24826 UINT32 CosWaysMask : 20;

24827

24828 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24829

24830 /*

24831 available ways vectors for class of service of

24832 IA core restrictions: Only contiguous 1s are

24833 allowed.

24834 */

24835 UINT32 Rsvd20 : 12;

24836

24837 /* Bits[31:20], Access Type=RO, default=None*/

24838

24839 /* Reserved */

24840

24841 } Bits;

24842

24843 UINT32 Uint32;

24844 UINT64 Uint64;

24845

24846 } MSR_LLC_QOS_MASK_4_4_REGISTER;

24847

24848 /**

24849 available ways vectors for class of service of IA core

24850 " seq has 12 instances in addresses range 0x94 to 0x9F"

24851 **/

24852 #define MSR_LLC_QOS_MASK_5_5 0x00000C95

24853

24854 typedef union {

24855 ///

24856 /// Individual bit fields

24857 ///

24858 struct {

24859 UINT32 CosWaysMask : 20;

24860

24861 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24862

24863 /*

24864 available ways vectors for class of service of

24865 IA core restrictions: Only contiguous 1s are

24866 allowed.

24867 */

24868 UINT32 Rsvd20 : 12;

24869

24870 /* Bits[31:20], Access Type=RO, default=None*/

24871

24872 /* Reserved */

24873

24874 } Bits;

24875

24876 UINT32 Uint32;

24877 UINT64 Uint64;

24878

24879 } MSR_LLC_QOS_MASK_5_5_REGISTER;

24880

24881 /**

24882 available ways vectors for class of service of IA core

24883 " seq has 12 instances in addresses range 0x94 to 0x9F"

24884 **/

24885 #define MSR_LLC_QOS_MASK_6_6 0x00000C96

24886

24887 typedef union {

24888 ///

24889 /// Individual bit fields

24890 ///

24891 struct {

24892 UINT32 CosWaysMask : 20;

24893

24894 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24895

24896 /*

24897 available ways vectors for class of service of

24898 IA core restrictions: Only contiguous 1s are

24899 allowed.

24900 */

24901 UINT32 Rsvd20 : 12;

24902

24903 /* Bits[31:20], Access Type=RO, default=None*/

24904

24905 /* Reserved */

24906

24907 } Bits;

24908

24909 UINT32 Uint32;

24910 UINT64 Uint64;

24911

24912 } MSR_LLC_QOS_MASK_6_6_REGISTER;

24913

24914 /**

24915 available ways vectors for class of service of IA core

24916 " seq has 12 instances in addresses range 0x94 to 0x9F"

24917 **/

24918 #define MSR_LLC_QOS_MASK_7_7 0x00000C97

24919

24920 typedef union {

24921 ///

24922 /// Individual bit fields

24923 ///

24924 struct {

24925 UINT32 CosWaysMask : 20;

24926

24927 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24928

24929 /*

24930 available ways vectors for class of service of

24931 IA core restrictions: Only contiguous 1s are

24932 allowed.

24933 */

24934 UINT32 Rsvd20 : 12;

24935

24936 /* Bits[31:20], Access Type=RO, default=None*/

24937

24938 /* Reserved */

24939

24940 } Bits;

24941

24942 UINT32 Uint32;

24943 UINT64 Uint64;

24944

24945 } MSR_LLC_QOS_MASK_7_7_REGISTER;

24946

24947 /**

24948 available ways vectors for class of service of IA core

24949 " seq has 12 instances in addresses range 0x94 to 0x9F"

24950 **/

24951 #define MSR_LLC_QOS_MASK_8_8 0x00000C98

24952

24953 typedef union {

24954 ///

24955 /// Individual bit fields

24956 ///

24957 struct {

24958 UINT32 CosWaysMask : 20;

24959

24960 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24961

24962 /*

24963 available ways vectors for class of service of

24964 IA core restrictions: Only contiguous 1s are

24965 allowed.

24966 */

24967 UINT32 Rsvd20 : 12;

24968

24969 /* Bits[31:20], Access Type=RO, default=None*/

24970

24971 /* Reserved */

24972

24973 } Bits;

24974

24975 UINT32 Uint32;

24976 UINT64 Uint64;

24977

24978 } MSR_LLC_QOS_MASK_8_8_REGISTER;

24979

24980 /**

24981 available ways vectors for class of service of IA core

24982 " seq has 12 instances in addresses range 0x94 to 0x9F"

24983 **/

24984 #define MSR_LLC_QOS_MASK_9_9 0x00000C99

24985

24986 typedef union {

24987 ///

24988 /// Individual bit fields

24989 ///

24990 struct {

24991 UINT32 CosWaysMask : 20;

24992

24993 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

24994

24995 /*

24996 available ways vectors for class of service of

24997 IA core restrictions: Only contiguous 1s are

24998 allowed.

24999 */

25000 UINT32 Rsvd20 : 12;

25001

25002 /* Bits[31:20], Access Type=RO, default=None*/

25003

25004 /* Reserved */

25005

25006 } Bits;

25007

25008 UINT32 Uint32;

25009 UINT64 Uint64;

25010

25011 } MSR_LLC_QOS_MASK_9_9_REGISTER;

25012

25013 /**

25014 available ways vectors for class of service of IA core

25015 " seq has 12 instances in addresses range 0x94 to 0x9F"

25016 **/

25017 #define MSR_LLC_QOS_MASK_10_10 0x00000C9A

25018

25019 typedef union {

25020 ///

25021 /// Individual bit fields

25022 ///

25023 struct {

25024 UINT32 CosWaysMask : 20;

25025

25026 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

25027

25028 /*

25029 available ways vectors for class of service of

25030 IA core restrictions: Only contiguous 1s are

25031 allowed.

25032 */

25033 UINT32 Rsvd20 : 12;

25034

25035 /* Bits[31:20], Access Type=RO, default=None*/

25036

25037 /* Reserved */

25038

25039 } Bits;

25040

25041 UINT32 Uint32;

25042 UINT64 Uint64;

25043

25044 } MSR_LLC_QOS_MASK_10_10_REGISTER;

25045

25046 /**

25047 available ways vectors for class of service of IA core

25048 " seq has 12 instances in addresses range 0x94 to 0x9F"

25049 **/

25050 #define MSR_LLC_QOS_MASK_11_11 0x00000C9B

25051

25052 typedef union {

25053 ///

25054 /// Individual bit fields

25055 ///

25056 struct {

25057 UINT32 CosWaysMask : 20;

25058

25059 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

25060

25061 /*

25062 available ways vectors for class of service of

25063 IA core restrictions: Only contiguous 1s are

25064 allowed.

25065 */

25066 UINT32 Rsvd20 : 12;

25067

25068 /* Bits[31:20], Access Type=RO, default=None*/

25069

25070 /* Reserved */

25071

25072 } Bits;

25073

25074 UINT32 Uint32;

25075 UINT64 Uint64;

25076

25077 } MSR_LLC_QOS_MASK_11_11_REGISTER;

25078

25079 /**

25080 available ways vectors for class of service of IA core

25081 " seq has 12 instances in addresses range 0x94 to 0x9F"

25082 **/

25083 #define MSR_LLC_QOS_MASK_12_12 0x00000C9C

25084

25085 typedef union {

25086 ///

25087 /// Individual bit fields

25088 ///

25089 struct {

25090 UINT32 CosWaysMask : 20;

25091

25092 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

25093

25094 /*

25095 available ways vectors for class of service of

25096 IA core restrictions: Only contiguous 1s are

25097 allowed.

25098 */

25099 UINT32 Rsvd20 : 12;

25100

25101 /* Bits[31:20], Access Type=RO, default=None*/

25102

25103 /* Reserved */

25104

25105 } Bits;

25106

25107 UINT32 Uint32;

25108 UINT64 Uint64;

25109

25110 } MSR_LLC_QOS_MASK_12_12_REGISTER;

25111

25112 /**

25113 available ways vectors for class of service of IA core

25114 " seq has 12 instances in addresses range 0x94 to 0x9F"

25115 **/

25116 #define MSR_LLC_QOS_MASK_13_13 0x00000C9D

25117

25118 typedef union {

25119 ///

25120 /// Individual bit fields

25121 ///

25122 struct {

25123 UINT32 CosWaysMask : 20;

25124

25125 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

25126

25127 /*

25128 available ways vectors for class of service of

25129 IA core restrictions: Only contiguous 1s are

25130 allowed.

25131 */

25132 UINT32 Rsvd20 : 12;

25133

25134 /* Bits[31:20], Access Type=RO, default=None*/

25135

25136 /* Reserved */

25137

25138 } Bits;

25139

25140 UINT32 Uint32;

25141 UINT64 Uint64;

25142

25143 } MSR_LLC_QOS_MASK_13_13_REGISTER;

25144

25145 /**

25146 available ways vectors for class of service of IA core

25147 " seq has 12 instances in addresses range 0x94 to 0x9F"

25148 **/

25149 #define MSR_LLC_QOS_MASK_14_14 0x00000C9E

25150

25151 typedef union {

25152 ///

25153 /// Individual bit fields

25154 ///

25155 struct {

25156 UINT32 CosWaysMask : 20;

25157

25158 /* Bits[19:0], Access Type=RW, default=0x000FFFFF*/

25159

25160 /*

25161 available ways vectors for class of service of

25162 IA core restrictions: Only contiguous 1s are

25163 allowed.

25164 */

25165 UINT32 Rsvd20 : 12;

25166

25167 /* Bits[31:20], Access Type=RO, default=None*/

25168

25169 /* Reserved */

25170

25171 } Bits;

25172

25173 UINT32 Uint32;

25174 UINT64 Uint64;

25175

25176 } MSR_LLC_QOS_MASK_14_14_REGISTER;

25177

25178 /**

25179 This MSR is used for Memory BW enforcement

25180 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25181 **/

25182 #define MSR_QOS_EXT_BW_THRTL_0_0 0x00000D50

25183

25184 typedef union {

25185 ///

25186 /// Individual bit fields

25187 ///

25188 struct {

25189 UINT32 RbeEnforcementVal : 16;

25190

25191 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25192

25193 /* The mem bw thrtl value */

25194 UINT32 Reserved16 : 16;

25195

25196 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25197

25198 /* Reserved */

25199 UINT32 Reserved32 : 32;

25200

25201 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25202

25203 /* Reserved */

25204

25205 } Bits;

25206

25207 UINT32 Uint32;

25208 UINT64 Uint64;

25209

25210 } MSR_QOS_EXT_BW_THRTL_0_0_REGISTER;

25211

25212 /**

25213 This MSR is used for Memory BW enforcement

25214 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25215 **/

25216 #define MSR_QOS_EXT_BW_THRTL_1_1 0x00000D51

25217

25218 typedef union {

25219 ///

25220 /// Individual bit fields

25221 ///

25222 struct {

25223 UINT32 RbeEnforcementVal : 16;

25224

25225 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25226

25227 /* The mem bw thrtl value */

25228 UINT32 Reserved16 : 16;

25229

25230 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25231

25232 /* Reserved */

25233 UINT32 Reserved32 : 32;

25234

25235 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25236

25237 /* Reserved */

25238

25239 } Bits;

25240

25241 UINT32 Uint32;

25242 UINT64 Uint64;

25243

25244 } MSR_QOS_EXT_BW_THRTL_1_1_REGISTER;

25245

25246 /**

25247 This MSR is used for Memory BW enforcement

25248 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25249 **/

25250 #define MSR_QOS_EXT_BW_THRTL_2_2 0x00000D52

25251

25252 typedef union {

25253 ///

25254 /// Individual bit fields

25255 ///

25256 struct {

25257 UINT32 RbeEnforcementVal : 16;

25258

25259 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25260

25261 /* The mem bw thrtl value */

25262 UINT32 Reserved16 : 16;

25263

25264 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25265

25266 /* Reserved */

25267 UINT32 Reserved32 : 32;

25268

25269 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25270

25271 /* Reserved */

25272

25273 } Bits;

25274

25275 UINT32 Uint32;

25276 UINT64 Uint64;

25277

25278 } MSR_QOS_EXT_BW_THRTL_2_2_REGISTER;

25279

25280 /**

25281 This MSR is used for Memory BW enforcement

25282 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25283 **/

25284 #define MSR_QOS_EXT_BW_THRTL_3_3 0x00000D53

25285

25286 typedef union {

25287 ///

25288 /// Individual bit fields

25289 ///

25290 struct {

25291 UINT32 RbeEnforcementVal : 16;

25292

25293 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25294

25295 /* The mem bw thrtl value */

25296 UINT32 Reserved16 : 16;

25297

25298 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25299

25300 /* Reserved */

25301 UINT32 Reserved32 : 32;

25302

25303 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25304

25305 /* Reserved */

25306

25307 } Bits;

25308

25309 UINT32 Uint32;

25310 UINT64 Uint64;

25311

25312 } MSR_QOS_EXT_BW_THRTL_3_3_REGISTER;

25313

25314 /**

25315 This MSR is used for Memory BW enforcement

25316 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25317 **/

25318 #define MSR_QOS_EXT_BW_THRTL_4_4 0x00000D54

25319

25320 typedef union {

25321 ///

25322 /// Individual bit fields

25323 ///

25324 struct {

25325 UINT32 RbeEnforcementVal : 16;

25326

25327 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25328

25329 /* The mem bw thrtl value */

25330 UINT32 Reserved16 : 16;

25331

25332 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25333

25334 /* Reserved */

25335 UINT32 Reserved32 : 32;

25336

25337 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25338

25339 /* Reserved */

25340

25341 } Bits;

25342

25343 UINT32 Uint32;

25344 UINT64 Uint64;

25345

25346 } MSR_QOS_EXT_BW_THRTL_4_4_REGISTER;

25347

25348 /**

25349 This MSR is used for Memory BW enforcement

25350 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25351 **/

25352 #define MSR_QOS_EXT_BW_THRTL_5_5 0x00000D55

25353

25354 typedef union {

25355 ///

25356 /// Individual bit fields

25357 ///

25358 struct {

25359 UINT32 RbeEnforcementVal : 16;

25360

25361 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25362

25363 /* The mem bw thrtl value */

25364 UINT32 Reserved16 : 16;

25365

25366 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25367

25368 /* Reserved */

25369 UINT32 Reserved32 : 32;

25370

25371 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25372

25373 /* Reserved */

25374

25375 } Bits;

25376

25377 UINT32 Uint32;

25378 UINT64 Uint64;

25379

25380 } MSR_QOS_EXT_BW_THRTL_5_5_REGISTER;

25381

25382 /**

25383 This MSR is used for Memory BW enforcement

25384 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25385 **/

25386 #define MSR_QOS_EXT_BW_THRTL_6_6 0x00000D56

25387

25388 typedef union {

25389 ///

25390 /// Individual bit fields

25391 ///

25392 struct {

25393 UINT32 RbeEnforcementVal : 16;

25394

25395 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25396

25397 /* The mem bw thrtl value */

25398 UINT32 Reserved16 : 16;

25399

25400 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25401

25402 /* Reserved */

25403 UINT32 Reserved32 : 32;

25404

25405 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25406

25407 /* Reserved */

25408

25409 } Bits;

25410

25411 UINT32 Uint32;

25412 UINT64 Uint64;

25413

25414 } MSR_QOS_EXT_BW_THRTL_6_6_REGISTER;

25415

25416 /**

25417 This MSR is used for Memory BW enforcement

25418 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25419 **/

25420 #define MSR_QOS_EXT_BW_THRTL_7_7 0x00000D57

25421

25422 typedef union {

25423 ///

25424 /// Individual bit fields

25425 ///

25426 struct {

25427 UINT32 RbeEnforcementVal : 16;

25428

25429 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25430

25431 /* The mem bw thrtl value */

25432 UINT32 Reserved16 : 16;

25433

25434 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25435

25436 /* Reserved */

25437 UINT32 Reserved32 : 32;

25438

25439 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25440

25441 /* Reserved */

25442

25443 } Bits;

25444

25445 UINT32 Uint32;

25446 UINT64 Uint64;

25447

25448 } MSR_QOS_EXT_BW_THRTL_7_7_REGISTER;

25449

25450 /**

25451 This MSR is used for Memory BW enforcement

25452 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25453 **/

25454 #define MSR_QOS_EXT_BW_THRTL_8_8 0x00000D58

25455

25456 typedef union {

25457 ///

25458 /// Individual bit fields

25459 ///

25460 struct {

25461 UINT32 RbeEnforcementVal : 16;

25462

25463 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25464

25465 /* The mem bw thrtl value */

25466 UINT32 Reserved16 : 16;

25467

25468 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25469

25470 /* Reserved */

25471 UINT32 Reserved32 : 32;

25472

25473 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25474

25475 /* Reserved */

25476

25477 } Bits;

25478

25479 UINT32 Uint32;

25480 UINT64 Uint64;

25481

25482 } MSR_QOS_EXT_BW_THRTL_8_8_REGISTER;

25483

25484 /**

25485 This MSR is used for Memory BW enforcement

25486 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25487 **/

25488 #define MSR_QOS_EXT_BW_THRTL_9_9 0x00000D59

25489

25490 typedef union {

25491 ///

25492 /// Individual bit fields

25493 ///

25494 struct {

25495 UINT32 RbeEnforcementVal : 16;

25496

25497 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25498

25499 /* The mem bw thrtl value */

25500 UINT32 Reserved16 : 16;

25501

25502 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25503

25504 /* Reserved */

25505 UINT32 Reserved32 : 32;

25506

25507 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25508

25509 /* Reserved */

25510

25511 } Bits;

25512

25513 UINT32 Uint32;

25514 UINT64 Uint64;

25515

25516 } MSR_QOS_EXT_BW_THRTL_9_9_REGISTER;

25517

25518 /**

25519 This MSR is used for Memory BW enforcement

25520 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25521 **/

25522 #define MSR_QOS_EXT_BW_THRTL_10_10 0x00000D5A

25523

25524 typedef union {

25525 ///

25526 /// Individual bit fields

25527 ///

25528 struct {

25529 UINT32 RbeEnforcementVal : 16;

25530

25531 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25532

25533 /* The mem bw thrtl value */

25534 UINT32 Reserved16 : 16;

25535

25536 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25537

25538 /* Reserved */

25539 UINT32 Reserved32 : 32;

25540

25541 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25542

25543 /* Reserved */

25544

25545 } Bits;

25546

25547 UINT32 Uint32;

25548 UINT64 Uint64;

25549

25550 } MSR_QOS_EXT_BW_THRTL_10_10_REGISTER;

25551

25552 /**

25553 This MSR is used for Memory BW enforcement

25554 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25555 **/

25556 #define MSR_QOS_EXT_BW_THRTL_11_11 0x00000D5B

25557

25558 typedef union {

25559 ///

25560 /// Individual bit fields

25561 ///

25562 struct {

25563 UINT32 RbeEnforcementVal : 16;

25564

25565 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25566

25567 /* The mem bw thrtl value */

25568 UINT32 Reserved16 : 16;

25569

25570 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25571

25572 /* Reserved */

25573 UINT32 Reserved32 : 32;

25574

25575 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25576

25577 /* Reserved */

25578

25579 } Bits;

25580

25581 UINT32 Uint32;

25582 UINT64 Uint64;

25583

25584 } MSR_QOS_EXT_BW_THRTL_11_11_REGISTER;

25585

25586 /**

25587 This MSR is used for Memory BW enforcement

25588 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25589 **/

25590 #define MSR_QOS_EXT_BW_THRTL_12_12 0x00000D5C

25591

25592 typedef union {

25593 ///

25594 /// Individual bit fields

25595 ///

25596 struct {

25597 UINT32 RbeEnforcementVal : 16;

25598

25599 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25600

25601 /* The mem bw thrtl value */

25602 UINT32 Reserved16 : 16;

25603

25604 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25605

25606 /* Reserved */

25607 UINT32 Reserved32 : 32;

25608

25609 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25610

25611 /* Reserved */

25612

25613 } Bits;

25614

25615 UINT32 Uint32;

25616 UINT64 Uint64;

25617

25618 } MSR_QOS_EXT_BW_THRTL_12_12_REGISTER;

25619

25620 /**

25621 This MSR is used for Memory BW enforcement

25622 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25623 **/

25624 #define MSR_QOS_EXT_BW_THRTL_13_13 0x00000D5D

25625

25626 typedef union {

25627 ///

25628 /// Individual bit fields

25629 ///

25630 struct {

25631 UINT32 RbeEnforcementVal : 16;

25632

25633 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25634

25635 /* The mem bw thrtl value */

25636 UINT32 Reserved16 : 16;

25637

25638 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25639

25640 /* Reserved */

25641 UINT32 Reserved32 : 32;

25642

25643 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25644

25645 /* Reserved */

25646

25647 } Bits;

25648

25649 UINT32 Uint32;

25650 UINT64 Uint64;

25651

25652 } MSR_QOS_EXT_BW_THRTL_13_13_REGISTER;

25653

25654 /**

25655 This MSR is used for Memory BW enforcement

25656 " seq has 16 instances in addresses range 0xD50 to 0xD5F"

25657 **/

25658 #define MSR_QOS_EXT_BW_THRTL_14_14 0x00000D5E

25659

25660 typedef union {

25661 ///

25662 /// Individual bit fields

25663 ///

25664 struct {

25665 UINT32 RbeEnforcementVal : 16;

25666

25667 /* Bits[15:0], Access Type=RW, default=0x00000000*/

25668

25669 /* The mem bw thrtl value */

25670 UINT32 Reserved16 : 16;

25671

25672 /* Bits[31:16], Access Type=RW, default=0x00000000*/

25673

25674 /* Reserved */

25675 UINT32 Reserved32 : 32;

25676

25677 /* Bits[63:32], Access Type=RW, default=0x00000000*/

25678

25679 /* Reserved */

25680

25681 } Bits;

25682

25683 UINT32 Uint32;

25684 UINT64 Uint64;

25685

25686 } MSR_QOS_EXT_BW_THRTL_14_14_REGISTER;

25687 /**

25688 Accumulates value of THREAD_TSC_SAMPLE_PRE_OPD_ENTER on every OPD_EXIT when transitioning back to C0

25689 **/

25690 #define MSR_THREAD_STALL_COUNTER 0x00000DB2

25691

25692 /**

25693 LBR MSR that holds non-IP information

25694 **/

25695 #define MSR_LBR_INFO_0_0 0x00000DC0

25696

25697 typedef union {

25698 ///

25699 /// Individual bit fields

25700 ///

25701 struct {

25702 UINT32 CycleCount : 16;

25703

25704 /* Bits[15:0], Access Type=RW_V, default=None*/

25705

25706 /* core-clocks elapsed since last LBR array update */

25707 UINT32 Rsvd16 : 16;

25708

25709 /* Bits[31:16], Access Type=RO, default=None*/

25710

25711 /* Reserved */

25712 UINT32 Rsvd32 : 29;

25713

25714 /* Bits[60:32], Access Type=RO, default=None*/

25715

25716 /* Reserved */

25717 UINT32 HleAbort : 1;

25718

25719 /* Bits[61:61], Access Type=RW_V, default=None*/

25720

25721 /* HLE/+ TX Abort occured */

25722 UINT32 InTx : 1;

25723

25724 /* Bits[62:62], Access Type=RW_V, default=None*/

25725

25726 /* Executing in HLE/+ TX */

25727 UINT32 Mispred : 1;

25728

25729 /* Bits[63:63], Access Type=RW_V, default=None*/

25730

25731 /* Misprediction bit */

25732

25733 } Bits;

25734

25735 UINT32 Uint32;

25736 UINT64 Uint64;

25737

25738 } MSR_LBR_INFO_0_0_REGISTER;

25739

25740 /**

25741 LBR MSR that holds non-IP information

25742 **/

25743 #define MSR_LBR_INFO_1_1 0x00000DC1

25744

25745 typedef union {

25746 ///

25747 /// Individual bit fields

25748 ///

25749 struct {

25750 UINT32 CycleCount : 16;

25751

25752 /* Bits[15:0], Access Type=RW_V, default=None*/

25753

25754 /* core-clocks elapsed since last LBR array update */

25755 UINT32 Rsvd16 : 16;

25756

25757 /* Bits[31:16], Access Type=RO, default=None*/

25758

25759 /* Reserved */

25760 UINT32 Rsvd32 : 29;

25761

25762 /* Bits[60:32], Access Type=RO, default=None*/

25763

25764 /* Reserved */

25765 UINT32 HleAbort : 1;

25766

25767 /* Bits[61:61], Access Type=RW_V, default=None*/

25768

25769 /* HLE/+ TX Abort occured */

25770 UINT32 InTx : 1;

25771

25772 /* Bits[62:62], Access Type=RW_V, default=None*/

25773

25774 /* Executing in HLE/+ TX */

25775 UINT32 Mispred : 1;

25776

25777 /* Bits[63:63], Access Type=RW_V, default=None*/

25778

25779 /* Misprediction bit */

25780

25781 } Bits;

25782

25783 UINT32 Uint32;

25784 UINT64 Uint64;

25785

25786 } MSR_LBR_INFO_1_1_REGISTER;

25787

25788 /**

25789 LBR MSR that holds non-IP information

25790 **/

25791 #define MSR_LBR_INFO_2_2 0x00000DC2

25792

25793 typedef union {

25794 ///

25795 /// Individual bit fields

25796 ///

25797 struct {

25798 UINT32 CycleCount : 16;

25799

25800 /* Bits[15:0], Access Type=RW_V, default=None*/

25801

25802 /* core-clocks elapsed since last LBR array update */

25803 UINT32 Rsvd16 : 16;

25804

25805 /* Bits[31:16], Access Type=RO, default=None*/

25806

25807 /* Reserved */

25808 UINT32 Rsvd32 : 29;

25809

25810 /* Bits[60:32], Access Type=RO, default=None*/

25811

25812 /* Reserved */

25813 UINT32 HleAbort : 1;

25814

25815 /* Bits[61:61], Access Type=RW_V, default=None*/

25816

25817 /* HLE/+ TX Abort occured */

25818 UINT32 InTx : 1;

25819

25820 /* Bits[62:62], Access Type=RW_V, default=None*/

25821

25822 /* Executing in HLE/+ TX */

25823 UINT32 Mispred : 1;

25824

25825 /* Bits[63:63], Access Type=RW_V, default=None*/

25826

25827 /* Misprediction bit */

25828

25829 } Bits;

25830

25831 UINT32 Uint32;

25832 UINT64 Uint64;

25833

25834 } MSR_LBR_INFO_2_2_REGISTER;

25835

25836 /**

25837 LBR MSR that holds non-IP information

25838 **/

25839 #define MSR_LBR_INFO_3_3 0x00000DC3

25840

25841 typedef union {

25842 ///

25843 /// Individual bit fields

25844 ///

25845 struct {

25846 UINT32 CycleCount : 16;

25847

25848 /* Bits[15:0], Access Type=RW_V, default=None*/

25849

25850 /* core-clocks elapsed since last LBR array update */

25851 UINT32 Rsvd16 : 16;

25852

25853 /* Bits[31:16], Access Type=RO, default=None*/

25854

25855 /* Reserved */

25856 UINT32 Rsvd32 : 29;

25857

25858 /* Bits[60:32], Access Type=RO, default=None*/

25859

25860 /* Reserved */

25861 UINT32 HleAbort : 1;

25862

25863 /* Bits[61:61], Access Type=RW_V, default=None*/

25864

25865 /* HLE/+ TX Abort occured */

25866 UINT32 InTx : 1;

25867

25868 /* Bits[62:62], Access Type=RW_V, default=None*/

25869

25870 /* Executing in HLE/+ TX */

25871 UINT32 Mispred : 1;

25872

25873 /* Bits[63:63], Access Type=RW_V, default=None*/

25874

25875 /* Misprediction bit */

25876

25877 } Bits;

25878

25879 UINT32 Uint32;

25880 UINT64 Uint64;

25881

25882 } MSR_LBR_INFO_3_3_REGISTER;

25883

25884 /**

25885 LBR MSR that holds non-IP information

25886 **/

25887 #define MSR_LBR_INFO_4_4 0x00000DC4

25888

25889 typedef union {

25890 ///

25891 /// Individual bit fields

25892 ///

25893 struct {

25894 UINT32 CycleCount : 16;

25895

25896 /* Bits[15:0], Access Type=RW_V, default=None*/

25897

25898 /* core-clocks elapsed since last LBR array update */

25899 UINT32 Rsvd16 : 16;

25900

25901 /* Bits[31:16], Access Type=RO, default=None*/

25902

25903 /* Reserved */

25904 UINT32 Rsvd32 : 29;

25905

25906 /* Bits[60:32], Access Type=RO, default=None*/

25907

25908 /* Reserved */

25909 UINT32 HleAbort : 1;

25910

25911 /* Bits[61:61], Access Type=RW_V, default=None*/

25912

25913 /* HLE/+ TX Abort occured */

25914 UINT32 InTx : 1;

25915

25916 /* Bits[62:62], Access Type=RW_V, default=None*/

25917

25918 /* Executing in HLE/+ TX */

25919 UINT32 Mispred : 1;

25920

25921 /* Bits[63:63], Access Type=RW_V, default=None*/

25922

25923 /* Misprediction bit */

25924

25925 } Bits;

25926

25927 UINT32 Uint32;

25928 UINT64 Uint64;

25929

25930 } MSR_LBR_INFO_4_4_REGISTER;

25931

25932 /**

25933 LBR MSR that holds non-IP information

25934 **/

25935 #define MSR_LBR_INFO_5_5 0x00000DC5

25936

25937 typedef union {

25938 ///

25939 /// Individual bit fields

25940 ///

25941 struct {

25942 UINT32 CycleCount : 16;

25943

25944 /* Bits[15:0], Access Type=RW_V, default=None*/

25945

25946 /* core-clocks elapsed since last LBR array update */

25947 UINT32 Rsvd16 : 16;

25948

25949 /* Bits[31:16], Access Type=RO, default=None*/

25950

25951 /* Reserved */

25952 UINT32 Rsvd32 : 29;

25953

25954 /* Bits[60:32], Access Type=RO, default=None*/

25955

25956 /* Reserved */

25957 UINT32 HleAbort : 1;

25958

25959 /* Bits[61:61], Access Type=RW_V, default=None*/

25960

25961 /* HLE/+ TX Abort occured */

25962 UINT32 InTx : 1;

25963

25964 /* Bits[62:62], Access Type=RW_V, default=None*/

25965

25966 /* Executing in HLE/+ TX */

25967 UINT32 Mispred : 1;

25968

25969 /* Bits[63:63], Access Type=RW_V, default=None*/

25970

25971 /* Misprediction bit */

25972

25973 } Bits;

25974

25975 UINT32 Uint32;

25976 UINT64 Uint64;

25977

25978 } MSR_LBR_INFO_5_5_REGISTER;

25979

25980 /**

25981 LBR MSR that holds non-IP information

25982 **/

25983 #define MSR_LBR_INFO_6_6 0x00000DC6

25984

25985 typedef union {

25986 ///

25987 /// Individual bit fields

25988 ///

25989 struct {

25990 UINT32 CycleCount : 16;

25991

25992 /* Bits[15:0], Access Type=RW_V, default=None*/

25993

25994 /* core-clocks elapsed since last LBR array update */

25995 UINT32 Rsvd16 : 16;

25996

25997 /* Bits[31:16], Access Type=RO, default=None*/

25998

25999 /* Reserved */

26000 UINT32 Rsvd32 : 29;

26001

26002 /* Bits[60:32], Access Type=RO, default=None*/

26003

26004 /* Reserved */

26005 UINT32 HleAbort : 1;

26006

26007 /* Bits[61:61], Access Type=RW_V, default=None*/

26008

26009 /* HLE/+ TX Abort occured */

26010 UINT32 InTx : 1;

26011

26012 /* Bits[62:62], Access Type=RW_V, default=None*/

26013

26014 /* Executing in HLE/+ TX */

26015 UINT32 Mispred : 1;

26016

26017 /* Bits[63:63], Access Type=RW_V, default=None*/

26018

26019 /* Misprediction bit */

26020

26021 } Bits;

26022

26023 UINT32 Uint32;

26024 UINT64 Uint64;

26025

26026 } MSR_LBR_INFO_6_6_REGISTER;

26027

26028 /**

26029 LBR MSR that holds non-IP information

26030 **/

26031 #define MSR_LBR_INFO_7_7 0x00000DC7

26032

26033 typedef union {

26034 ///

26035 /// Individual bit fields

26036 ///

26037 struct {

26038 UINT32 CycleCount : 16;

26039

26040 /* Bits[15:0], Access Type=RW_V, default=None*/

26041

26042 /* core-clocks elapsed since last LBR array update */

26043 UINT32 Rsvd16 : 16;

26044

26045 /* Bits[31:16], Access Type=RO, default=None*/

26046

26047 /* Reserved */

26048 UINT32 Rsvd32 : 29;

26049

26050 /* Bits[60:32], Access Type=RO, default=None*/

26051

26052 /* Reserved */

26053 UINT32 HleAbort : 1;

26054

26055 /* Bits[61:61], Access Type=RW_V, default=None*/

26056

26057 /* HLE/+ TX Abort occured */

26058 UINT32 InTx : 1;

26059

26060 /* Bits[62:62], Access Type=RW_V, default=None*/

26061

26062 /* Executing in HLE/+ TX */

26063 UINT32 Mispred : 1;

26064

26065 /* Bits[63:63], Access Type=RW_V, default=None*/

26066

26067 /* Misprediction bit */

26068

26069 } Bits;

26070

26071 UINT32 Uint32;

26072 UINT64 Uint64;

26073

26074 } MSR_LBR_INFO_7_7_REGISTER;

26075

26076 /**

26077 LBR MSR that holds non-IP information

26078 **/

26079 #define MSR_LBR_INFO_8_8 0x00000DC8

26080

26081 typedef union {

26082 ///

26083 /// Individual bit fields

26084 ///

26085 struct {

26086 UINT32 CycleCount : 16;

26087

26088 /* Bits[15:0], Access Type=RW_V, default=None*/

26089

26090 /* core-clocks elapsed since last LBR array update */

26091 UINT32 Rsvd16 : 16;

26092

26093 /* Bits[31:16], Access Type=RO, default=None*/

26094

26095 /* Reserved */

26096 UINT32 Rsvd32 : 29;

26097

26098 /* Bits[60:32], Access Type=RO, default=None*/

26099

26100 /* Reserved */

26101 UINT32 HleAbort : 1;

26102

26103 /* Bits[61:61], Access Type=RW_V, default=None*/

26104

26105 /* HLE/+ TX Abort occured */

26106 UINT32 InTx : 1;

26107

26108 /* Bits[62:62], Access Type=RW_V, default=None*/

26109

26110 /* Executing in HLE/+ TX */

26111 UINT32 Mispred : 1;

26112

26113 /* Bits[63:63], Access Type=RW_V, default=None*/

26114

26115 /* Misprediction bit */

26116

26117 } Bits;

26118

26119 UINT32 Uint32;

26120 UINT64 Uint64;

26121

26122 } MSR_LBR_INFO_8_8_REGISTER;

26123

26124 /**

26125 LBR MSR that holds non-IP information

26126 **/

26127 #define MSR_LBR_INFO_9_9 0x00000DC9

26128

26129 typedef union {

26130 ///

26131 /// Individual bit fields

26132 ///

26133 struct {

26134 UINT32 CycleCount : 16;

26135

26136 /* Bits[15:0], Access Type=RW_V, default=None*/

26137

26138 /* core-clocks elapsed since last LBR array update */

26139 UINT32 Rsvd16 : 16;

26140

26141 /* Bits[31:16], Access Type=RO, default=None*/

26142

26143 /* Reserved */

26144 UINT32 Rsvd32 : 29;

26145

26146 /* Bits[60:32], Access Type=RO, default=None*/

26147

26148 /* Reserved */

26149 UINT32 HleAbort : 1;

26150

26151 /* Bits[61:61], Access Type=RW_V, default=None*/

26152

26153 /* HLE/+ TX Abort occured */

26154 UINT32 InTx : 1;

26155

26156 /* Bits[62:62], Access Type=RW_V, default=None*/

26157

26158 /* Executing in HLE/+ TX */

26159 UINT32 Mispred : 1;

26160

26161 /* Bits[63:63], Access Type=RW_V, default=None*/

26162

26163 /* Misprediction bit */

26164

26165 } Bits;

26166

26167 UINT32 Uint32;

26168 UINT64 Uint64;

26169

26170 } MSR_LBR_INFO_9_9_REGISTER;

26171

26172 /**

26173 LBR MSR that holds non-IP information

26174 **/

26175 #define MSR_LBR_INFO_10_10 0x00000DCA

26176

26177 typedef union {

26178 ///

26179 /// Individual bit fields

26180 ///

26181 struct {

26182 UINT32 CycleCount : 16;

26183

26184 /* Bits[15:0], Access Type=RW_V, default=None*/

26185

26186 /* core-clocks elapsed since last LBR array update */

26187 UINT32 Rsvd16 : 16;

26188

26189 /* Bits[31:16], Access Type=RO, default=None*/

26190

26191 /* Reserved */

26192 UINT32 Rsvd32 : 29;

26193

26194 /* Bits[60:32], Access Type=RO, default=None*/

26195

26196 /* Reserved */

26197 UINT32 HleAbort : 1;

26198

26199 /* Bits[61:61], Access Type=RW_V, default=None*/

26200

26201 /* HLE/+ TX Abort occured */

26202 UINT32 InTx : 1;

26203

26204 /* Bits[62:62], Access Type=RW_V, default=None*/

26205

26206 /* Executing in HLE/+ TX */

26207 UINT32 Mispred : 1;

26208

26209 /* Bits[63:63], Access Type=RW_V, default=None*/

26210

26211 /* Misprediction bit */

26212

26213 } Bits;

26214

26215 UINT32 Uint32;

26216 UINT64 Uint64;

26217

26218 } MSR_LBR_INFO_10_10_REGISTER;

26219

26220 /**

26221 LBR MSR that holds non-IP information

26222 **/

26223 #define MSR_LBR_INFO_11_11 0x00000DCB

26224

26225 typedef union {

26226 ///

26227 /// Individual bit fields

26228 ///

26229 struct {

26230 UINT32 CycleCount : 16;

26231

26232 /* Bits[15:0], Access Type=RW_V, default=None*/

26233

26234 /* core-clocks elapsed since last LBR array update */

26235 UINT32 Rsvd16 : 16;

26236

26237 /* Bits[31:16], Access Type=RO, default=None*/

26238

26239 /* Reserved */

26240 UINT32 Rsvd32 : 29;

26241

26242 /* Bits[60:32], Access Type=RO, default=None*/

26243

26244 /* Reserved */

26245 UINT32 HleAbort : 1;

26246

26247 /* Bits[61:61], Access Type=RW_V, default=None*/

26248

26249 /* HLE/+ TX Abort occured */

26250 UINT32 InTx : 1;

26251

26252 /* Bits[62:62], Access Type=RW_V, default=None*/

26253

26254 /* Executing in HLE/+ TX */

26255 UINT32 Mispred : 1;

26256

26257 /* Bits[63:63], Access Type=RW_V, default=None*/

26258

26259 /* Misprediction bit */

26260

26261 } Bits;

26262

26263 UINT32 Uint32;

26264 UINT64 Uint64;

26265

26266 } MSR_LBR_INFO_11_11_REGISTER;

26267

26268 /**

26269 LBR MSR that holds non-IP information

26270 **/

26271 #define MSR_LBR_INFO_12_12 0x00000DCC

26272

26273 typedef union {

26274 ///

26275 /// Individual bit fields

26276 ///

26277 struct {

26278 UINT32 CycleCount : 16;

26279

26280 /* Bits[15:0], Access Type=RW_V, default=None*/

26281

26282 /* core-clocks elapsed since last LBR array update */

26283 UINT32 Rsvd16 : 16;

26284

26285 /* Bits[31:16], Access Type=RO, default=None*/

26286

26287 /* Reserved */

26288 UINT32 Rsvd32 : 29;

26289

26290 /* Bits[60:32], Access Type=RO, default=None*/

26291

26292 /* Reserved */

26293 UINT32 HleAbort : 1;

26294

26295 /* Bits[61:61], Access Type=RW_V, default=None*/

26296

26297 /* HLE/+ TX Abort occured */

26298 UINT32 InTx : 1;

26299

26300 /* Bits[62:62], Access Type=RW_V, default=None*/

26301

26302 /* Executing in HLE/+ TX */

26303 UINT32 Mispred : 1;

26304

26305 /* Bits[63:63], Access Type=RW_V, default=None*/

26306

26307 /* Misprediction bit */

26308

26309 } Bits;

26310

26311 UINT32 Uint32;

26312 UINT64 Uint64;

26313

26314 } MSR_LBR_INFO_12_12_REGISTER;

26315

26316 /**

26317 LBR MSR that holds non-IP information

26318 **/

26319 #define MSR_LBR_INFO_13_13 0x00000DCD

26320

26321 typedef union {

26322 ///

26323 /// Individual bit fields

26324 ///

26325 struct {

26326 UINT32 CycleCount : 16;

26327

26328 /* Bits[15:0], Access Type=RW_V, default=None*/

26329

26330 /* core-clocks elapsed since last LBR array update */

26331 UINT32 Rsvd16 : 16;

26332

26333 /* Bits[31:16], Access Type=RO, default=None*/

26334

26335 /* Reserved */

26336 UINT32 Rsvd32 : 29;

26337

26338 /* Bits[60:32], Access Type=RO, default=None*/

26339

26340 /* Reserved */

26341 UINT32 HleAbort : 1;

26342

26343 /* Bits[61:61], Access Type=RW_V, default=None*/

26344

26345 /* HLE/+ TX Abort occured */

26346 UINT32 InTx : 1;

26347

26348 /* Bits[62:62], Access Type=RW_V, default=None*/

26349

26350 /* Executing in HLE/+ TX */

26351 UINT32 Mispred : 1;

26352

26353 /* Bits[63:63], Access Type=RW_V, default=None*/

26354

26355 /* Misprediction bit */

26356

26357 } Bits;

26358

26359 UINT32 Uint32;

26360 UINT64 Uint64;

26361

26362 } MSR_LBR_INFO_13_13_REGISTER;

26363

26364 /**

26365 LBR MSR that holds non-IP information

26366 **/

26367 #define MSR_LBR_INFO_14_14 0x00000DCE

26368

26369 typedef union {

26370 ///

26371 /// Individual bit fields

26372 ///

26373 struct {

26374 UINT32 CycleCount : 16;

26375

26376 /* Bits[15:0], Access Type=RW_V, default=None*/

26377

26378 /* core-clocks elapsed since last LBR array update */

26379 UINT32 Rsvd16 : 16;

26380

26381 /* Bits[31:16], Access Type=RO, default=None*/

26382

26383 /* Reserved */

26384 UINT32 Rsvd32 : 29;

26385

26386 /* Bits[60:32], Access Type=RO, default=None*/

26387

26388 /* Reserved */

26389 UINT32 HleAbort : 1;

26390

26391 /* Bits[61:61], Access Type=RW_V, default=None*/

26392

26393 /* HLE/+ TX Abort occured */

26394 UINT32 InTx : 1;

26395

26396 /* Bits[62:62], Access Type=RW_V, default=None*/

26397

26398 /* Executing in HLE/+ TX */

26399 UINT32 Mispred : 1;

26400

26401 /* Bits[63:63], Access Type=RW_V, default=None*/

26402

26403 /* Misprediction bit */

26404

26405 } Bits;

26406

26407 UINT32 Uint32;

26408 UINT64 Uint64;

26409

26410 } MSR_LBR_INFO_14_14_REGISTER;

26411

26412 /**

26413 LBR MSR that holds non-IP information

26414 **/

26415 #define MSR_LBR_INFO_15_15 0x00000DCF

26416

26417 typedef union {

26418 ///

26419 /// Individual bit fields

26420 ///

26421 struct {

26422 UINT32 CycleCount : 16;

26423

26424 /* Bits[15:0], Access Type=RW_V, default=None*/

26425

26426 /* core-clocks elapsed since last LBR array update */

26427 UINT32 Rsvd16 : 16;

26428

26429 /* Bits[31:16], Access Type=RO, default=None*/

26430

26431 /* Reserved */

26432 UINT32 Rsvd32 : 29;

26433

26434 /* Bits[60:32], Access Type=RO, default=None*/

26435

26436 /* Reserved */

26437 UINT32 HleAbort : 1;

26438

26439 /* Bits[61:61], Access Type=RW_V, default=None*/

26440

26441 /* HLE/+ TX Abort occured */

26442 UINT32 InTx : 1;

26443

26444 /* Bits[62:62], Access Type=RW_V, default=None*/

26445

26446 /* Executing in HLE/+ TX */

26447 UINT32 Mispred : 1;

26448

26449 /* Bits[63:63], Access Type=RW_V, default=None*/

26450

26451 /* Misprediction bit */

26452

26453 } Bits;

26454

26455 UINT32 Uint32;

26456 UINT64 Uint64;

26457

26458 } MSR_LBR_INFO_15_15_REGISTER;

26459

26460 /**

26461 LBR MSR that holds non-IP information

26462 **/

26463 #define MSR_LBR_INFO_16_16 0x00000DD0

26464

26465 typedef union {

26466 ///

26467 /// Individual bit fields

26468 ///

26469 struct {

26470 UINT32 CycleCount : 16;

26471

26472 /* Bits[15:0], Access Type=RW_V, default=None*/

26473

26474 /* core-clocks elapsed since last LBR array update */

26475 UINT32 Rsvd16 : 16;

26476

26477 /* Bits[31:16], Access Type=RO, default=None*/

26478

26479 /* Reserved */

26480 UINT32 Rsvd32 : 29;

26481

26482 /* Bits[60:32], Access Type=RO, default=None*/

26483

26484 /* Reserved */

26485 UINT32 HleAbort : 1;

26486

26487 /* Bits[61:61], Access Type=RW_V, default=None*/

26488

26489 /* HLE/+ TX Abort occured */

26490 UINT32 InTx : 1;

26491

26492 /* Bits[62:62], Access Type=RW_V, default=None*/

26493

26494 /* Executing in HLE/+ TX */

26495 UINT32 Mispred : 1;

26496

26497 /* Bits[63:63], Access Type=RW_V, default=None*/

26498

26499 /* Misprediction bit */

26500

26501 } Bits;

26502

26503 UINT32 Uint32;

26504 UINT64 Uint64;

26505

26506 } MSR_LBR_INFO_16_16_REGISTER;

26507

26508 /**

26509 LBR MSR that holds non-IP information

26510 **/

26511 #define MSR_LBR_INFO_17_17 0x00000DD1

26512

26513 typedef union {

26514 ///

26515 /// Individual bit fields

26516 ///

26517 struct {

26518 UINT32 CycleCount : 16;

26519

26520 /* Bits[15:0], Access Type=RW_V, default=None*/

26521

26522 /* core-clocks elapsed since last LBR array update */

26523 UINT32 Rsvd16 : 16;

26524

26525 /* Bits[31:16], Access Type=RO, default=None*/

26526

26527 /* Reserved */

26528 UINT32 Rsvd32 : 29;

26529

26530 /* Bits[60:32], Access Type=RO, default=None*/

26531

26532 /* Reserved */

26533 UINT32 HleAbort : 1;

26534

26535 /* Bits[61:61], Access Type=RW_V, default=None*/

26536

26537 /* HLE/+ TX Abort occured */

26538 UINT32 InTx : 1;

26539

26540 /* Bits[62:62], Access Type=RW_V, default=None*/

26541

26542 /* Executing in HLE/+ TX */

26543 UINT32 Mispred : 1;

26544

26545 /* Bits[63:63], Access Type=RW_V, default=None*/

26546

26547 /* Misprediction bit */

26548

26549 } Bits;

26550

26551 UINT32 Uint32;

26552 UINT64 Uint64;

26553

26554 } MSR_LBR_INFO_17_17_REGISTER;

26555

26556 /**

26557 LBR MSR that holds non-IP information

26558 **/

26559 #define MSR_LBR_INFO_18_18 0x00000DD2

26560

26561 typedef union {

26562 ///

26563 /// Individual bit fields

26564 ///

26565 struct {

26566 UINT32 CycleCount : 16;

26567

26568 /* Bits[15:0], Access Type=RW_V, default=None*/

26569

26570 /* core-clocks elapsed since last LBR array update */

26571 UINT32 Rsvd16 : 16;

26572

26573 /* Bits[31:16], Access Type=RO, default=None*/

26574

26575 /* Reserved */

26576 UINT32 Rsvd32 : 29;

26577

26578 /* Bits[60:32], Access Type=RO, default=None*/

26579

26580 /* Reserved */

26581 UINT32 HleAbort : 1;

26582

26583 /* Bits[61:61], Access Type=RW_V, default=None*/

26584

26585 /* HLE/+ TX Abort occured */

26586 UINT32 InTx : 1;

26587

26588 /* Bits[62:62], Access Type=RW_V, default=None*/

26589

26590 /* Executing in HLE/+ TX */

26591 UINT32 Mispred : 1;

26592

26593 /* Bits[63:63], Access Type=RW_V, default=None*/

26594

26595 /* Misprediction bit */

26596

26597 } Bits;

26598

26599 UINT32 Uint32;

26600 UINT64 Uint64;

26601

26602 } MSR_LBR_INFO_18_18_REGISTER;

26603

26604 /**

26605 LBR MSR that holds non-IP information

26606 **/

26607 #define MSR_LBR_INFO_19_19 0x00000DD3

26608

26609 typedef union {

26610 ///

26611 /// Individual bit fields

26612 ///

26613 struct {

26614 UINT32 CycleCount : 16;

26615

26616 /* Bits[15:0], Access Type=RW_V, default=None*/

26617

26618 /* core-clocks elapsed since last LBR array update */

26619 UINT32 Rsvd16 : 16;

26620

26621 /* Bits[31:16], Access Type=RO, default=None*/

26622

26623 /* Reserved */

26624 UINT32 Rsvd32 : 29;

26625

26626 /* Bits[60:32], Access Type=RO, default=None*/

26627

26628 /* Reserved */

26629 UINT32 HleAbort : 1;

26630

26631 /* Bits[61:61], Access Type=RW_V, default=None*/

26632

26633 /* HLE/+ TX Abort occured */

26634 UINT32 InTx : 1;

26635

26636 /* Bits[62:62], Access Type=RW_V, default=None*/

26637

26638 /* Executing in HLE/+ TX */

26639 UINT32 Mispred : 1;

26640

26641 /* Bits[63:63], Access Type=RW_V, default=None*/

26642

26643 /* Misprediction bit */

26644

26645 } Bits;

26646

26647 UINT32 Uint32;

26648 UINT64 Uint64;

26649

26650 } MSR_LBR_INFO_19_19_REGISTER;

26651

26652 /**

26653 LBR MSR that holds non-IP information

26654 **/

26655 #define MSR_LBR_INFO_20_20 0x00000DD4

26656

26657 typedef union {

26658 ///

26659 /// Individual bit fields

26660 ///

26661 struct {

26662 UINT32 CycleCount : 16;

26663

26664 /* Bits[15:0], Access Type=RW_V, default=None*/

26665

26666 /* core-clocks elapsed since last LBR array update */

26667 UINT32 Rsvd16 : 16;

26668

26669 /* Bits[31:16], Access Type=RO, default=None*/

26670

26671 /* Reserved */

26672 UINT32 Rsvd32 : 29;

26673

26674 /* Bits[60:32], Access Type=RO, default=None*/

26675

26676 /* Reserved */

26677 UINT32 HleAbort : 1;

26678

26679 /* Bits[61:61], Access Type=RW_V, default=None*/

26680

26681 /* HLE/+ TX Abort occured */

26682 UINT32 InTx : 1;

26683

26684 /* Bits[62:62], Access Type=RW_V, default=None*/

26685

26686 /* Executing in HLE/+ TX */

26687 UINT32 Mispred : 1;

26688

26689 /* Bits[63:63], Access Type=RW_V, default=None*/

26690

26691 /* Misprediction bit */

26692

26693 } Bits;

26694

26695 UINT32 Uint32;

26696 UINT64 Uint64;

26697

26698 } MSR_LBR_INFO_20_20_REGISTER;

26699

26700 /**

26701 LBR MSR that holds non-IP information

26702 **/

26703 #define MSR_LBR_INFO_21_21 0x00000DD5

26704

26705 typedef union {

26706 ///

26707 /// Individual bit fields

26708 ///

26709 struct {

26710 UINT32 CycleCount : 16;

26711

26712 /* Bits[15:0], Access Type=RW_V, default=None*/

26713

26714 /* core-clocks elapsed since last LBR array update */

26715 UINT32 Rsvd16 : 16;

26716

26717 /* Bits[31:16], Access Type=RO, default=None*/

26718

26719 /* Reserved */

26720 UINT32 Rsvd32 : 29;

26721

26722 /* Bits[60:32], Access Type=RO, default=None*/

26723

26724 /* Reserved */

26725 UINT32 HleAbort : 1;

26726

26727 /* Bits[61:61], Access Type=RW_V, default=None*/

26728

26729 /* HLE/+ TX Abort occured */

26730 UINT32 InTx : 1;

26731

26732 /* Bits[62:62], Access Type=RW_V, default=None*/

26733

26734 /* Executing in HLE/+ TX */

26735 UINT32 Mispred : 1;

26736

26737 /* Bits[63:63], Access Type=RW_V, default=None*/

26738

26739 /* Misprediction bit */

26740

26741 } Bits;

26742

26743 UINT32 Uint32;

26744 UINT64 Uint64;

26745

26746 } MSR_LBR_INFO_21_21_REGISTER;

26747

26748 /**

26749 LBR MSR that holds non-IP information

26750 **/

26751 #define MSR_LBR_INFO_22_22 0x00000DD6

26752

26753 typedef union {

26754 ///

26755 /// Individual bit fields

26756 ///

26757 struct {

26758 UINT32 CycleCount : 16;

26759

26760 /* Bits[15:0], Access Type=RW_V, default=None*/

26761

26762 /* core-clocks elapsed since last LBR array update */

26763 UINT32 Rsvd16 : 16;

26764

26765 /* Bits[31:16], Access Type=RO, default=None*/

26766

26767 /* Reserved */

26768 UINT32 Rsvd32 : 29;

26769

26770 /* Bits[60:32], Access Type=RO, default=None*/

26771

26772 /* Reserved */

26773 UINT32 HleAbort : 1;

26774

26775 /* Bits[61:61], Access Type=RW_V, default=None*/

26776

26777 /* HLE/+ TX Abort occured */

26778 UINT32 InTx : 1;

26779

26780 /* Bits[62:62], Access Type=RW_V, default=None*/

26781

26782 /* Executing in HLE/+ TX */

26783 UINT32 Mispred : 1;

26784

26785 /* Bits[63:63], Access Type=RW_V, default=None*/

26786

26787 /* Misprediction bit */

26788

26789 } Bits;

26790

26791 UINT32 Uint32;

26792 UINT64 Uint64;

26793

26794 } MSR_LBR_INFO_22_22_REGISTER;

26795

26796 /**

26797 LBR MSR that holds non-IP information

26798 **/

26799 #define MSR_LBR_INFO_23_23 0x00000DD7

26800

26801 typedef union {

26802 ///

26803 /// Individual bit fields

26804 ///

26805 struct {

26806 UINT32 CycleCount : 16;

26807

26808 /* Bits[15:0], Access Type=RW_V, default=None*/

26809

26810 /* core-clocks elapsed since last LBR array update */

26811 UINT32 Rsvd16 : 16;

26812

26813 /* Bits[31:16], Access Type=RO, default=None*/

26814

26815 /* Reserved */

26816 UINT32 Rsvd32 : 29;

26817

26818 /* Bits[60:32], Access Type=RO, default=None*/

26819

26820 /* Reserved */

26821 UINT32 HleAbort : 1;

26822

26823 /* Bits[61:61], Access Type=RW_V, default=None*/

26824

26825 /* HLE/+ TX Abort occured */

26826 UINT32 InTx : 1;

26827

26828 /* Bits[62:62], Access Type=RW_V, default=None*/

26829

26830 /* Executing in HLE/+ TX */

26831 UINT32 Mispred : 1;

26832

26833 /* Bits[63:63], Access Type=RW_V, default=None*/

26834

26835 /* Misprediction bit */

26836

26837 } Bits;

26838

26839 UINT32 Uint32;

26840 UINT64 Uint64;

26841

26842 } MSR_LBR_INFO_23_23_REGISTER;

26843

26844 /**

26845 LBR MSR that holds non-IP information

26846 **/

26847 #define MSR_LBR_INFO_24_24 0x00000DD8

26848

26849 typedef union {

26850 ///

26851 /// Individual bit fields

26852 ///

26853 struct {

26854 UINT32 CycleCount : 16;

26855

26856 /* Bits[15:0], Access Type=RW_V, default=None*/

26857

26858 /* core-clocks elapsed since last LBR array update */

26859 UINT32 Rsvd16 : 16;

26860

26861 /* Bits[31:16], Access Type=RO, default=None*/

26862

26863 /* Reserved */

26864 UINT32 Rsvd32 : 29;

26865

26866 /* Bits[60:32], Access Type=RO, default=None*/

26867

26868 /* Reserved */

26869 UINT32 HleAbort : 1;

26870

26871 /* Bits[61:61], Access Type=RW_V, default=None*/

26872

26873 /* HLE/+ TX Abort occured */

26874 UINT32 InTx : 1;

26875

26876 /* Bits[62:62], Access Type=RW_V, default=None*/

26877

26878 /* Executing in HLE/+ TX */

26879 UINT32 Mispred : 1;

26880

26881 /* Bits[63:63], Access Type=RW_V, default=None*/

26882

26883 /* Misprediction bit */

26884

26885 } Bits;

26886

26887 UINT32 Uint32;

26888 UINT64 Uint64;

26889

26890 } MSR_LBR_INFO_24_24_REGISTER;

26891

26892 /**

26893 LBR MSR that holds non-IP information

26894 **/

26895 #define MSR_LBR_INFO_25_25 0x00000DD9

26896

26897 typedef union {

26898 ///

26899 /// Individual bit fields

26900 ///

26901 struct {

26902 UINT32 CycleCount : 16;

26903

26904 /* Bits[15:0], Access Type=RW_V, default=None*/

26905

26906 /* core-clocks elapsed since last LBR array update */

26907 UINT32 Rsvd16 : 16;

26908

26909 /* Bits[31:16], Access Type=RO, default=None*/

26910

26911 /* Reserved */

26912 UINT32 Rsvd32 : 29;

26913

26914 /* Bits[60:32], Access Type=RO, default=None*/

26915

26916 /* Reserved */

26917 UINT32 HleAbort : 1;

26918

26919 /* Bits[61:61], Access Type=RW_V, default=None*/

26920

26921 /* HLE/+ TX Abort occured */

26922 UINT32 InTx : 1;

26923

26924 /* Bits[62:62], Access Type=RW_V, default=None*/

26925

26926 /* Executing in HLE/+ TX */

26927 UINT32 Mispred : 1;

26928

26929 /* Bits[63:63], Access Type=RW_V, default=None*/

26930

26931 /* Misprediction bit */

26932

26933 } Bits;

26934

26935 UINT32 Uint32;

26936 UINT64 Uint64;

26937

26938 } MSR_LBR_INFO_25_25_REGISTER;

26939

26940 /**

26941 LBR MSR that holds non-IP information

26942 **/

26943 #define MSR_LBR_INFO_26_26 0x00000DDA

26944

26945 typedef union {

26946 ///

26947 /// Individual bit fields

26948 ///

26949 struct {

26950 UINT32 CycleCount : 16;

26951

26952 /* Bits[15:0], Access Type=RW_V, default=None*/

26953

26954 /* core-clocks elapsed since last LBR array update */

26955 UINT32 Rsvd16 : 16;

26956

26957 /* Bits[31:16], Access Type=RO, default=None*/

26958

26959 /* Reserved */

26960 UINT32 Rsvd32 : 29;

26961

26962 /* Bits[60:32], Access Type=RO, default=None*/

26963

26964 /* Reserved */

26965 UINT32 HleAbort : 1;

26966

26967 /* Bits[61:61], Access Type=RW_V, default=None*/

26968

26969 /* HLE/+ TX Abort occured */

26970 UINT32 InTx : 1;

26971

26972 /* Bits[62:62], Access Type=RW_V, default=None*/

26973

26974 /* Executing in HLE/+ TX */

26975 UINT32 Mispred : 1;

26976

26977 /* Bits[63:63], Access Type=RW_V, default=None*/

26978

26979 /* Misprediction bit */

26980

26981 } Bits;

26982

26983 UINT32 Uint32;

26984 UINT64 Uint64;

26985

26986 } MSR_LBR_INFO_26_26_REGISTER;

26987

26988 /**

26989 LBR MSR that holds non-IP information

26990 **/

26991 #define MSR_LBR_INFO_27_27 0x00000DDB

26992

26993 typedef union {

26994 ///

26995 /// Individual bit fields

26996 ///

26997 struct {

26998 UINT32 CycleCount : 16;

26999

27000 /* Bits[15:0], Access Type=RW_V, default=None*/

27001

27002 /* core-clocks elapsed since last LBR array update */

27003 UINT32 Rsvd16 : 16;

27004

27005 /* Bits[31:16], Access Type=RO, default=None*/

27006

27007 /* Reserved */

27008 UINT32 Rsvd32 : 29;

27009

27010 /* Bits[60:32], Access Type=RO, default=None*/

27011

27012 /* Reserved */

27013 UINT32 HleAbort : 1;

27014

27015 /* Bits[61:61], Access Type=RW_V, default=None*/

27016

27017 /* HLE/+ TX Abort occured */

27018 UINT32 InTx : 1;

27019

27020 /* Bits[62:62], Access Type=RW_V, default=None*/

27021

27022 /* Executing in HLE/+ TX */

27023 UINT32 Mispred : 1;

27024

27025 /* Bits[63:63], Access Type=RW_V, default=None*/

27026

27027 /* Misprediction bit */

27028

27029 } Bits;

27030

27031 UINT32 Uint32;

27032 UINT64 Uint64;

27033

27034 } MSR_LBR_INFO_27_27_REGISTER;

27035

27036 /**

27037 LBR MSR that holds non-IP information

27038 **/

27039 #define MSR_LBR_INFO_28_28 0x00000DDC

27040

27041 typedef union {

27042 ///

27043 /// Individual bit fields

27044 ///

27045 struct {

27046 UINT32 CycleCount : 16;

27047

27048 /* Bits[15:0], Access Type=RW_V, default=None*/

27049

27050 /* core-clocks elapsed since last LBR array update */

27051 UINT32 Rsvd16 : 16;

27052

27053 /* Bits[31:16], Access Type=RO, default=None*/

27054

27055 /* Reserved */

27056 UINT32 Rsvd32 : 29;

27057

27058 /* Bits[60:32], Access Type=RO, default=None*/

27059

27060 /* Reserved */

27061 UINT32 HleAbort : 1;

27062

27063 /* Bits[61:61], Access Type=RW_V, default=None*/

27064

27065 /* HLE/+ TX Abort occured */

27066 UINT32 InTx : 1;

27067

27068 /* Bits[62:62], Access Type=RW_V, default=None*/

27069

27070 /* Executing in HLE/+ TX */

27071 UINT32 Mispred : 1;

27072

27073 /* Bits[63:63], Access Type=RW_V, default=None*/

27074

27075 /* Misprediction bit */

27076

27077 } Bits;

27078

27079 UINT32 Uint32;

27080 UINT64 Uint64;

27081

27082 } MSR_LBR_INFO_28_28_REGISTER;

27083

27084 /**

27085 LBR MSR that holds non-IP information

27086 **/

27087 #define MSR_LBR_INFO_29_29 0x00000DDD

27088

27089 typedef union {

27090 ///

27091 /// Individual bit fields

27092 ///

27093 struct {

27094 UINT32 CycleCount : 16;

27095

27096 /* Bits[15:0], Access Type=RW_V, default=None*/

27097

27098 /* core-clocks elapsed since last LBR array update */

27099 UINT32 Rsvd16 : 16;

27100

27101 /* Bits[31:16], Access Type=RO, default=None*/

27102

27103 /* Reserved */

27104 UINT32 Rsvd32 : 29;

27105

27106 /* Bits[60:32], Access Type=RO, default=None*/

27107

27108 /* Reserved */

27109 UINT32 HleAbort : 1;

27110

27111 /* Bits[61:61], Access Type=RW_V, default=None*/

27112

27113 /* HLE/+ TX Abort occured */

27114 UINT32 InTx : 1;

27115

27116 /* Bits[62:62], Access Type=RW_V, default=None*/

27117

27118 /* Executing in HLE/+ TX */

27119 UINT32 Mispred : 1;

27120

27121 /* Bits[63:63], Access Type=RW_V, default=None*/

27122

27123 /* Misprediction bit */

27124

27125 } Bits;

27126

27127 UINT32 Uint32;

27128 UINT64 Uint64;

27129

27130 } MSR_LBR_INFO_29_29_REGISTER;

27131

27132 /**

27133 LBR MSR that holds non-IP information

27134 **/

27135 #define MSR_LBR_INFO_30_30 0x00000DDE

27136

27137 typedef union {

27138 ///

27139 /// Individual bit fields

27140 ///

27141 struct {

27142 UINT32 CycleCount : 16;

27143

27144 /* Bits[15:0], Access Type=RW_V, default=None*/

27145

27146 /* core-clocks elapsed since last LBR array update */

27147 UINT32 Rsvd16 : 16;

27148

27149 /* Bits[31:16], Access Type=RO, default=None*/

27150

27151 /* Reserved */

27152 UINT32 Rsvd32 : 29;

27153

27154 /* Bits[60:32], Access Type=RO, default=None*/

27155

27156 /* Reserved */

27157 UINT32 HleAbort : 1;

27158

27159 /* Bits[61:61], Access Type=RW_V, default=None*/

27160

27161 /* HLE/+ TX Abort occured */

27162 UINT32 InTx : 1;

27163

27164 /* Bits[62:62], Access Type=RW_V, default=None*/

27165

27166 /* Executing in HLE/+ TX */

27167 UINT32 Mispred : 1;

27168

27169 /* Bits[63:63], Access Type=RW_V, default=None*/

27170

27171 /* Misprediction bit */

27172

27173 } Bits;

27174

27175 UINT32 Uint32;

27176 UINT64 Uint64;

27177

27178 } MSR_LBR_INFO_30_30_REGISTER;

27179

27180 /**

27181 LBR MSR that holds non-IP information

27182 **/

27183 #define MSR_LBR_INFO_31_31 0x00000DDF

27184

27185 typedef union {

27186 ///

27187 /// Individual bit fields

27188 ///

27189 struct {

27190 UINT32 CycleCount : 16;

27191

27192 /* Bits[15:0], Access Type=RW_V, default=None*/

27193

27194 /* core-clocks elapsed since last LBR array update */

27195 UINT32 Rsvd16 : 16;

27196

27197 /* Bits[31:16], Access Type=RO, default=None*/

27198

27199 /* Reserved */

27200 UINT32 Rsvd32 : 29;

27201

27202 /* Bits[60:32], Access Type=RO, default=None*/

27203

27204 /* Reserved */

27205 UINT32 HleAbort : 1;

27206

27207 /* Bits[61:61], Access Type=RW_V, default=None*/

27208

27209 /* HLE/+ TX Abort occured */

27210 UINT32 InTx : 1;

27211

27212 /* Bits[62:62], Access Type=RW_V, default=None*/

27213

27214 /* Executing in HLE/+ TX */

27215 UINT32 Mispred : 1;

27216

27217 /* Bits[63:63], Access Type=RW_V, default=None*/

27218

27219 /* Misprediction bit */

27220

27221 } Bits;

27222

27223 UINT32 Uint32;

27224 UINT64 Uint64;

27225

27226 } MSR_LBR_INFO_31_31_REGISTER;

27227

27228 /**

27229 Address Match Range Register - Physical Base Control Register for Hidden Lake

27230 " seq has 1 instances in addresses range 0xF00 to 0xF00"

27231 **/

27232 #define MSR_AMRR_BASE_0_0 0x00000F00

27233

27234 typedef union {

27235 ///

27236 /// Individual bit fields

27237 ///

27238 struct {

27239 UINT32 TmeEn : 1;

27240

27241 /* Bits[0:0], Access Type=RW, default=0x00000000*/

27242

27243 /* Enable TME masking */

27244 UINT32 Rsvd1 : 11;

27245

27246 /* Bits[11:1], Access Type=RO, default=None*/

27247

27248 /* Reserved */

27249 UINT32 Base0 : 20;

27250

27251 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27252

27253 /*

27254 The 4K-aligned platform physical base addresses

27255 of the 3 AMRR registers for debugging. These

27256 registers are programmed like MTRRs with base

27257 and mask. Address matches of an AMRR can be

27258 programmed to cause an "assist" or "abort".

27259 Assists invoke the address match ucode handler

27260 and populate the RR_MATCH_ADDR and

27261 RR_MATCH_RESULT CREGs with useful information

27262 about the access. Aborts force the memory type

27263 to UC and redirect the access to the abort page

27264 (causing it to get garbage data from the

27265 uncore). See AMRR_MASK bits for more information

27266 on how to program. See the PRF register

27267 definition for how to resume AMRR assist

27268 matches. restrictions : Set corresponding

27269 AMRR_MASK appropriately for the address.

27270 */

27271 UINT32 Base1 : 20;

27272

27273 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27274

27275 /*

27276 The 4K-aligned platform physical base addresses

27277 of the 3 AMRR registers for debugging. These

27278 registers are programmed like MTRRs with base

27279 and mask. Address matches of an AMRR can be

27280 programmed to cause an "assist" or "abort".

27281 Assists invoke the address match ucode handler

27282 and populate the RR_MATCH_ADDR and

27283 RR_MATCH_RESULT CREGs with useful information

27284 about the access. Aborts force the memory type

27285 to UC and redirect the access to the abort page

27286 (causing it to get garbage data from the

27287 uncore). See AMRR_MASK bits for more information

27288 on how to program. See the PRF register

27289 definition for how to resume AMRR assist

27290 matches. restrictions : Set corresponding

27291 AMRR_MASK appropriately for the address.

27292 */

27293 UINT32 Rsvd52 : 12;

27294

27295 /* Bits[63:52], Access Type=RO, default=None*/

27296

27297 /* Reserved */

27298

27299 } Bits;

27300

27301 UINT32 Uint32;

27302 UINT64 Uint64;

27303

27304 } MSR_AMRR_BASE_0_0_REGISTER;

27305

27306 /**

27307 Address Match Range Register - Physical Mask Control Register for Hidden Lake

27308 " seq has 1 instances in addresses range 0xF01 to 0xF01"

27309 **/

27310 #define MSR_AMRR_MASK_0_0 0x00000F01

27311

27312 typedef union {

27313 ///

27314 /// Individual bit fields

27315 ///

27316 struct {

27317 UINT32 Rsvd0 : 3;

27318

27319 /* Bits[2:0], Access Type=RO, default=None*/

27320

27321 /* Reserved */

27322 UINT32 IgnorePw : 1;

27323

27324 /* Bits[3:3], Access Type=RW, default=0x00000000*/

27325

27326 /*

27327 If set, hitting the AMRR on a stuffed load will

27328 be ignored and will not cause assist nor abort.

27329 Only the real PA (on redispatch) can cause an

27330 assist if matches. restrictions :

27331 */

27332 UINT32 PhysegOvrd : 1;

27333

27334 /* Bits[4:4], Access Type=RW, default=0x00000000*/

27335

27336 /*

27337 If set, hitting the AMRR with PhySegSupOvr is

27338 allowed, and will not cause assist or abort

27339 restrictions :

27340 */

27341 UINT32 ForceWb : 1;

27342

27343 /* Bits[5:5], Access Type=RW, default=0x00000000*/

27344

27345 /*

27346 If set, hitting AMRR legally (see above bit),

27347 will also force WB memtype. This is subject to

27348 memtype priorities and can be overridden due to

27349 higher priority mem types restrictions :

27350 */

27351 UINT32 Rsvd6 : 2;

27352

27353 /* Bits[7:6], Access Type=RO, default=None*/

27354

27355 /* Reserved */

27356 UINT32 Ifetch : 1;

27357

27358 /* Bits[8:8], Access Type=RW, default=0x00000000*/

27359

27360 /*

27361 If set, allow AMRR assist matches for both

27362 I-side and D-side, else assist match D-side

27363 only. Pagewalk accesses (stuffed loads and

27364 loadpxelocks) always count as D-side. This bit

27365 has no effect on abort matches. restrictions :

27366 Set corresponding AMRR_BASE appropriately for

27367 the address. Set VLD, ASSIST, IFETCH, and MASK.

27368 */

27369 UINT32 Assist : 1;

27370

27371 /* Bits[9:9], Access Type=RW, default=0x00000000*/

27372

27373 /*

27374 If set, AMRR matches to the programmed address

27375 will invoke ucode's address match handler. If

27376 clear, AMRR matches will "abort" and redirect

27377 the access to the abort page and a UC memory

27378 type. restrictions : Set corresponding AMRR_BASE

27379 appropriately for the address. Set VLD, ASSIST,

27380 IFETCH, and MASK.

27381 */

27382 UINT32 L : 1;

27383

27384 /* Bits[10:10], Access Type=RW, default=0x00000000*/

27385

27386 /* Lock bit for the AMRR */

27387 UINT32 Rsvd11 : 1;

27388

27389 /* Bits[11:11], Access Type=RO, default=None*/

27390

27391 /* Reserved */

27392 UINT32 Mask0 : 20;

27393

27394 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27395

27396 /*

27397 The mask value used in MTRR-like address

27398 matching of platform. Minimum granularity for

27399 matches is 4K (aligned), but the ucode handler

27400 can use RR_MATCH_ADDR and the resume capability

27401 (see the PRF register definition) to achieve

27402 narrower checking. restrictions : Set

27403 corresponding AMRR_BASE appropriately for the

27404 address. Set VLD, ASSIST, IFETCH, and MASK.

27405 */

27406 UINT32 Mask1 : 20;

27407

27408 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27409

27410 /*

27411 The mask value used in MTRR-like address

27412 matching of platform. Minimum granularity for

27413 matches is 4K (aligned), but the ucode handler

27414 can use RR_MATCH_ADDR and the resume capability

27415 (see the PRF register definition) to achieve

27416 narrower checking. restrictions : Set

27417 corresponding AMRR_BASE appropriately for the

27418 address. Set VLD, ASSIST, IFETCH, and MASK.

27419 */

27420 UINT32 Rsvd52 : 12;

27421

27422 /* Bits[63:52], Access Type=RO, default=None*/

27423

27424 /* Reserved */

27425

27426 } Bits;

27427

27428 UINT32 Uint32;

27429 UINT64 Uint64;

27430

27431 } MSR_AMRR_MASK_0_0_REGISTER;

27432

27433 /**

27434 Address Match Range Register - Physical Base Control Register for Hidden Lake

27435 " seq has 2 instances in addresses range 0xF02 to 0xF04"

27436 **/

27437 #define MSR_AMRR_BASE_1_1 0x00000F02

27438

27439 typedef union {

27440 ///

27441 /// Individual bit fields

27442 ///

27443 struct {

27444 UINT32 TmeEn : 1;

27445

27446 /* Bits[0:0], Access Type=RW, default=0x00000000*/

27447

27448 /* Enable TME masking */

27449 UINT32 Rsvd1 : 11;

27450

27451 /* Bits[11:1], Access Type=RO, default=None*/

27452

27453 /* Reserved */

27454 UINT32 Base0 : 20;

27455

27456 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27457

27458 /*

27459 The 4K-aligned platform physical base addresses

27460 of the 3 AMRR registers for debugging. These

27461 registers are programmed like MTRRs with base

27462 and mask. Address matches of an AMRR can be

27463 programmed to cause an "assist" or "abort".

27464 Assists invoke the address match ucode handler

27465 and populate the RR_MATCH_ADDR and

27466 RR_MATCH_RESULT CREGs with useful information

27467 about the access. Aborts force the memory type

27468 to UC and redirect the access to the abort page

27469 (causing it to get garbage data from the

27470 uncore). See AMRR_MASK bits for more information

27471 on how to program. See the PRF register

27472 definition for how to resume AMRR assist

27473 matches. restrictions : Set corresponding

27474 AMRR_MASK appropriately for the address.

27475 */

27476 UINT32 Base1 : 20;

27477

27478 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27479

27480 /*

27481 The 4K-aligned platform physical base addresses

27482 of the 3 AMRR registers for debugging. These

27483 registers are programmed like MTRRs with base

27484 and mask. Address matches of an AMRR can be

27485 programmed to cause an "assist" or "abort".

27486 Assists invoke the address match ucode handler

27487 and populate the RR_MATCH_ADDR and

27488 RR_MATCH_RESULT CREGs with useful information

27489 about the access. Aborts force the memory type

27490 to UC and redirect the access to the abort page

27491 (causing it to get garbage data from the

27492 uncore). See AMRR_MASK bits for more information

27493 on how to program. See the PRF register

27494 definition for how to resume AMRR assist

27495 matches. restrictions : Set corresponding

27496 AMRR_MASK appropriately for the address.

27497 */

27498 UINT32 Rsvd52 : 12;

27499

27500 /* Bits[63:52], Access Type=RO, default=None*/

27501

27502 /* Reserved */

27503

27504 } Bits;

27505

27506 UINT32 Uint32;

27507 UINT64 Uint64;

27508

27509 } MSR_AMRR_BASE_1_1_REGISTER;

27510

27511 /**

27512 Address Match Range Register - Physical Mask Control Register for Hidden Lake

27513 " seq has 2 instances in addresses range 0xF03 to 0xF05"

27514 **/

27515 #define MSR_AMRR_MASK_1_1 0x00000F03

27516

27517 typedef union {

27518 ///

27519 /// Individual bit fields

27520 ///

27521 struct {

27522 UINT32 Rsvd0 : 3;

27523

27524 /* Bits[2:0], Access Type=RO, default=None*/

27525

27526 /* Reserved */

27527 UINT32 IgnorePw : 1;

27528

27529 /* Bits[3:3], Access Type=RW, default=0x00000000*/

27530

27531 /*

27532 If set, hitting the AMRR on a stuffed load will

27533 be ignored and will not cause assist nor abort.

27534 Only the real PA (on redispatch) can cause an

27535 assist if matches. restrictions :

27536 */

27537 UINT32 PhysegOvrd : 1;

27538

27539 /* Bits[4:4], Access Type=RW, default=0x00000000*/

27540

27541 /*

27542 If set, hitting the AMRR with PhySegSupOvr is

27543 allowed, and will not cause assist or abort

27544 restrictions :

27545 */

27546 UINT32 ForceWb : 1;

27547

27548 /* Bits[5:5], Access Type=RW, default=0x00000000*/

27549

27550 /*

27551 If set, hitting AMRR legally (see above bit),

27552 will also force WB memtype. This is subject to

27553 memtype priorities and can be overridden due to

27554 higher priority mem types restrictions :

27555 */

27556 UINT32 Rsvd6 : 2;

27557

27558 /* Bits[7:6], Access Type=RO, default=None*/

27559

27560 /* Reserved */

27561 UINT32 Ifetch : 1;

27562

27563 /* Bits[8:8], Access Type=RW, default=0x00000000*/

27564

27565 /*

27566 If set, allow AMRR assist matches for both

27567 I-side and D-side, else assist match D-side

27568 only. Pagewalk accesses (stuffed loads and

27569 loadpxelocks) always count as D-side. This bit

27570 has no effect on abort matches. restrictions :

27571 Set corresponding AMRR_BASE appropriately for

27572 the address. Set VLD, ASSIST, IFETCH, and MASK.

27573 */

27574 UINT32 Assist : 1;

27575

27576 /* Bits[9:9], Access Type=RW, default=0x00000000*/

27577

27578 /*

27579 If set, AMRR matches to the programmed address

27580 will invoke ucode's address match handler. If

27581 clear, AMRR matches will "abort" and redirect

27582 the access to the abort page and a UC memory

27583 type. restrictions : Set corresponding AMRR_BASE

27584 appropriately for the address. Set VLD, ASSIST,

27585 IFETCH, and MASK.

27586 */

27587 UINT32 L : 1;

27588

27589 /* Bits[10:10], Access Type=RW, default=0x00000000*/

27590

27591 /* Lock bit for the AMRR */

27592 UINT32 Rsvd11 : 1;

27593

27594 /* Bits[11:11], Access Type=RO, default=None*/

27595

27596 /* Reserved */

27597 UINT32 Mask0 : 20;

27598

27599 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27600

27601 /*

27602 The mask value used in MTRR-like address

27603 matching of platform. Minimum granularity for

27604 matches is 4K (aligned), but the ucode handler

27605 can use RR_MATCH_ADDR and the resume capability

27606 (see the PRF register definition) to achieve

27607 narrower checking. restrictions : Set

27608 corresponding AMRR_BASE appropriately for the

27609 address. Set VLD, ASSIST, IFETCH, and MASK.

27610 */

27611 UINT32 Mask1 : 20;

27612

27613 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27614

27615 /*

27616 The mask value used in MTRR-like address

27617 matching of platform. Minimum granularity for

27618 matches is 4K (aligned), but the ucode handler

27619 can use RR_MATCH_ADDR and the resume capability

27620 (see the PRF register definition) to achieve

27621 narrower checking. restrictions : Set

27622 corresponding AMRR_BASE appropriately for the

27623 address. Set VLD, ASSIST, IFETCH, and MASK.

27624 */

27625 UINT32 Rsvd52 : 12;

27626

27627 /* Bits[63:52], Access Type=RO, default=None*/

27628

27629 /* Reserved */

27630

27631 } Bits;

27632

27633 UINT32 Uint32;

27634 UINT64 Uint64;

27635

27636 } MSR_AMRR_MASK_1_1_REGISTER;

27637

27638 /**

27639 Address Match Range Register - Physical Base Control Register for Hidden Lake

27640 " seq has 2 instances in addresses range 0xF02 to 0xF04"

27641 **/

27642 #define MSR_AMRR_BASE_2_2 0x00000F04

27643

27644 typedef union {

27645 ///

27646 /// Individual bit fields

27647 ///

27648 struct {

27649 UINT32 TmeEn : 1;

27650

27651 /* Bits[0:0], Access Type=RW, default=0x00000000*/

27652

27653 /* Enable TME masking */

27654 UINT32 Rsvd1 : 11;

27655

27656 /* Bits[11:1], Access Type=RO, default=None*/

27657

27658 /* Reserved */

27659 UINT32 Base0 : 20;

27660

27661 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27662

27663 /*

27664 The 4K-aligned platform physical base addresses

27665 of the 3 AMRR registers for debugging. These

27666 registers are programmed like MTRRs with base

27667 and mask. Address matches of an AMRR can be

27668 programmed to cause an "assist" or "abort".

27669 Assists invoke the address match ucode handler

27670 and populate the RR_MATCH_ADDR and

27671 RR_MATCH_RESULT CREGs with useful information

27672 about the access. Aborts force the memory type

27673 to UC and redirect the access to the abort page

27674 (causing it to get garbage data from the

27675 uncore). See AMRR_MASK bits for more information

27676 on how to program. See the PRF register

27677 definition for how to resume AMRR assist

27678 matches. restrictions : Set corresponding

27679 AMRR_MASK appropriately for the address.

27680 */

27681 UINT32 Base1 : 20;

27682

27683 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27684

27685 /*

27686 The 4K-aligned platform physical base addresses

27687 of the 3 AMRR registers for debugging. These

27688 registers are programmed like MTRRs with base

27689 and mask. Address matches of an AMRR can be

27690 programmed to cause an "assist" or "abort".

27691 Assists invoke the address match ucode handler

27692 and populate the RR_MATCH_ADDR and

27693 RR_MATCH_RESULT CREGs with useful information

27694 about the access. Aborts force the memory type

27695 to UC and redirect the access to the abort page

27696 (causing it to get garbage data from the

27697 uncore). See AMRR_MASK bits for more information

27698 on how to program. See the PRF register

27699 definition for how to resume AMRR assist

27700 matches. restrictions : Set corresponding

27701 AMRR_MASK appropriately for the address.

27702 */

27703 UINT32 Rsvd52 : 12;

27704

27705 /* Bits[63:52], Access Type=RO, default=None*/

27706

27707 /* Reserved */

27708

27709 } Bits;

27710

27711 UINT32 Uint32;

27712 UINT64 Uint64;

27713

27714 } MSR_AMRR_BASE_2_2_REGISTER;

27715

27716 /**

27717 Address Match Range Register - Physical Mask Control Register for Hidden Lake

27718 " seq has 2 instances in addresses range 0xF03 to 0xF05"

27719 **/

27720 #define MSR_AMRR_MASK_2_2 0x00000F05

27721

27722 typedef union {

27723 ///

27724 /// Individual bit fields

27725 ///

27726 struct {

27727 UINT32 Rsvd0 : 3;

27728

27729 /* Bits[2:0], Access Type=RO, default=None*/

27730

27731 /* Reserved */

27732 UINT32 IgnorePw : 1;

27733

27734 /* Bits[3:3], Access Type=RW, default=0x00000000*/

27735

27736 /*

27737 If set, hitting the AMRR on a stuffed load will

27738 be ignored and will not cause assist nor abort.

27739 Only the real PA (on redispatch) can cause an

27740 assist if matches. restrictions :

27741 */

27742 UINT32 PhysegOvrd : 1;

27743

27744 /* Bits[4:4], Access Type=RW, default=0x00000000*/

27745

27746 /*

27747 If set, hitting the AMRR with PhySegSupOvr is

27748 allowed, and will not cause assist or abort

27749 restrictions :

27750 */

27751 UINT32 ForceWb : 1;

27752

27753 /* Bits[5:5], Access Type=RW, default=0x00000000*/

27754

27755 /*

27756 If set, hitting AMRR legally (see above bit),

27757 will also force WB memtype. This is subject to

27758 memtype priorities and can be overridden due to

27759 higher priority mem types restrictions :

27760 */

27761 UINT32 Rsvd6 : 2;

27762

27763 /* Bits[7:6], Access Type=RO, default=None*/

27764

27765 /* Reserved */

27766 UINT32 Ifetch : 1;

27767

27768 /* Bits[8:8], Access Type=RW, default=0x00000000*/

27769

27770 /*

27771 If set, allow AMRR assist matches for both

27772 I-side and D-side, else assist match D-side

27773 only. Pagewalk accesses (stuffed loads and

27774 loadpxelocks) always count as D-side. This bit

27775 has no effect on abort matches. restrictions :

27776 Set corresponding AMRR_BASE appropriately for

27777 the address. Set VLD, ASSIST, IFETCH, and MASK.

27778 */

27779 UINT32 Assist : 1;

27780

27781 /* Bits[9:9], Access Type=RW, default=0x00000000*/

27782

27783 /*

27784 If set, AMRR matches to the programmed address

27785 will invoke ucode's address match handler. If

27786 clear, AMRR matches will "abort" and redirect

27787 the access to the abort page and a UC memory

27788 type. restrictions : Set corresponding AMRR_BASE

27789 appropriately for the address. Set VLD, ASSIST,

27790 IFETCH, and MASK.

27791 */

27792 UINT32 L : 1;

27793

27794 /* Bits[10:10], Access Type=RW, default=0x00000000*/

27795

27796 /* Lock bit for the AMRR */

27797 UINT32 Rsvd11 : 1;

27798

27799 /* Bits[11:11], Access Type=RO, default=None*/

27800

27801 /* Reserved */

27802 UINT32 Mask0 : 20;

27803

27804 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27805

27806 /*

27807 The mask value used in MTRR-like address

27808 matching of platform. Minimum granularity for

27809 matches is 4K (aligned), but the ucode handler

27810 can use RR_MATCH_ADDR and the resume capability

27811 (see the PRF register definition) to achieve

27812 narrower checking. restrictions : Set

27813 corresponding AMRR_BASE appropriately for the

27814 address. Set VLD, ASSIST, IFETCH, and MASK.

27815 */

27816 UINT32 Mask1 : 20;

27817

27818 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27819

27820 /*

27821 The mask value used in MTRR-like address

27822 matching of platform. Minimum granularity for

27823 matches is 4K (aligned), but the ucode handler

27824 can use RR_MATCH_ADDR and the resume capability

27825 (see the PRF register definition) to achieve

27826 narrower checking. restrictions : Set

27827 corresponding AMRR_BASE appropriately for the

27828 address. Set VLD, ASSIST, IFETCH, and MASK.

27829 */

27830 UINT32 Rsvd52 : 12;

27831

27832 /* Bits[63:52], Access Type=RO, default=None*/

27833

27834 /* Reserved */

27835

27836 } Bits;

27837

27838 UINT32 Uint32;

27839 UINT64 Uint64;

27840

27841 } MSR_AMRR_MASK_2_2_REGISTER;

27842

27843 /**

27844 Address Match Range Register - Physical Base Control Register for Hidden Lake

27845 " seq has 2 instances in addresses range 0xF06 to 0xF08"

27846 **/

27847 #define MSR_AMRR_BASE_3_3 0x00000F06

27848

27849 typedef union {

27850 ///

27851 /// Individual bit fields

27852 ///

27853 struct {

27854 UINT32 TmeEn : 1;

27855

27856 /* Bits[0:0], Access Type=RW, default=0x00000000*/

27857

27858 /* Enable TME masking */

27859 UINT32 Rsvd1 : 11;

27860

27861 /* Bits[11:1], Access Type=RO, default=None*/

27862

27863 /* Reserved */

27864 UINT32 Base0 : 20;

27865

27866 /* Bits[31:12], Access Type=RW, default=0x00000000*/

27867

27868 /*

27869 The 4K-aligned platform physical base addresses

27870 of the 3 AMRR registers for debugging. These

27871 registers are programmed like MTRRs with base

27872 and mask. Address matches of an AMRR can be

27873 programmed to cause an "assist" or "abort".

27874 Assists invoke the address match ucode handler

27875 and populate the RR_MATCH_ADDR and

27876 RR_MATCH_RESULT CREGs with useful information

27877 about the access. Aborts force the memory type

27878 to UC and redirect the access to the abort page

27879 (causing it to get garbage data from the

27880 uncore). See AMRR_MASK bits for more information

27881 on how to program. See the PRF register

27882 definition for how to resume AMRR assist

27883 matches. restrictions : Set corresponding

27884 AMRR_MASK appropriately for the address.

27885 */

27886 UINT32 Base1 : 20;

27887

27888 /* Bits[51:32], Access Type=RW, default=0x00000000*/

27889

27890 /*

27891 The 4K-aligned platform physical base addresses

27892 of the 3 AMRR registers for debugging. These

27893 registers are programmed like MTRRs with base

27894 and mask. Address matches of an AMRR can be

27895 programmed to cause an "assist" or "abort".

27896 Assists invoke the address match ucode handler

27897 and populate the RR_MATCH_ADDR and

27898 RR_MATCH_RESULT CREGs with useful information

27899 about the access. Aborts force the memory type

27900 to UC and redirect the access to the abort page

27901 (causing it to get garbage data from the

27902 uncore). See AMRR_MASK bits for more information

27903 on how to program. See the PRF register

27904 definition for how to resume AMRR assist

27905 matches. restrictions : Set corresponding

27906 AMRR_MASK appropriately for the address.

27907 */

27908 UINT32 Rsvd52 : 12;

27909

27910 /* Bits[63:52], Access Type=RO, default=None*/

27911

27912 /* Reserved */

27913

27914 } Bits;

27915

27916 UINT32 Uint32;

27917 UINT64 Uint64;

27918

27919 } MSR_AMRR_BASE_3_3_REGISTER;

27920

27921 /**

27922 Address Match Range Register - Physical Mask Control Register for Hidden Lake

27923 " seq has 2 instances in addresses range 0xF07 to 0xF09"

27924 **/

27925 #define MSR_AMRR_MASK_3_3 0x00000F07

27926

27927 typedef union {

27928 ///

27929 /// Individual bit fields

27930 ///

27931 struct {

27932 UINT32 Rsvd0 : 3;

27933

27934 /* Bits[2:0], Access Type=RO, default=None*/

27935

27936 /* Reserved */

27937 UINT32 IgnorePw : 1;

27938

27939 /* Bits[3:3], Access Type=RW, default=0x00000000*/

27940

27941 /*

27942 If set, hitting the AMRR on a stuffed load will

27943 be ignored and will not cause assist nor abort.

27944 Only the real PA (on redispatch) can cause an

27945 assist if matches. restrictions :

27946 */

27947 UINT32 PhysegOvrd : 1;

27948

27949 /* Bits[4:4], Access Type=RW, default=0x00000000*/

27950

27951 /*

27952 If set, hitting the AMRR with PhySegSupOvr is

27953 allowed, and will not cause assist or abort

27954 restrictions :

27955 */

27956 UINT32 ForceWb : 1;

27957

27958 /* Bits[5:5], Access Type=RW, default=0x00000000*/

27959

27960 /*

27961 If set, hitting AMRR legally (see above bit),

27962 will also force WB memtype. This is subject to

27963 memtype priorities and can be overridden due to

27964 higher priority mem types restrictions :

27965 */

27966 UINT32 Rsvd6 : 2;

27967

27968 /* Bits[7:6], Access Type=RO, default=None*/

27969

27970 /* Reserved */

27971 UINT32 Ifetch : 1;

27972

27973 /* Bits[8:8], Access Type=RW, default=0x00000000*/

27974

27975 /*

27976 If set, allow AMRR assist matches for both

27977 I-side and D-side, else assist match D-side

27978 only. Pagewalk accesses (stuffed loads and

27979 loadpxelocks) always count as D-side. This bit

27980 has no effect on abort matches. restrictions :

27981 Set corresponding AMRR_BASE appropriately for

27982 the address. Set VLD, ASSIST, IFETCH, and MASK.

27983 */

27984 UINT32 Assist : 1;

27985

27986 /* Bits[9:9], Access Type=RW, default=0x00000000*/

27987

27988 /*

27989 If set, AMRR matches to the programmed address

27990 will invoke ucode's address match handler. If

27991 clear, AMRR matches will "abort" and redirect

27992 the access to the abort page and a UC memory

27993 type. restrictions : Set corresponding AMRR_BASE

27994 appropriately for the address. Set VLD, ASSIST,

27995 IFETCH, and MASK.

27996 */

27997 UINT32 L : 1;

27998

27999 /* Bits[10:10], Access Type=RW, default=0x00000000*/

28000

28001 /* Lock bit for the AMRR */

28002 UINT32 Rsvd11 : 1;

28003

28004 /* Bits[11:11], Access Type=RO, default=None*/

28005

28006 /* Reserved */

28007 UINT32 Mask0 : 20;

28008

28009 /* Bits[31:12], Access Type=RW, default=0x00000000*/

28010

28011 /*

28012 The mask value used in MTRR-like address

28013 matching of platform. Minimum granularity for

28014 matches is 4K (aligned), but the ucode handler

28015 can use RR_MATCH_ADDR and the resume capability

28016 (see the PRF register definition) to achieve

28017 narrower checking. restrictions : Set

28018 corresponding AMRR_BASE appropriately for the

28019 address. Set VLD, ASSIST, IFETCH, and MASK.

28020 */

28021 UINT32 Mask1 : 20;

28022

28023 /* Bits[51:32], Access Type=RW, default=0x00000000*/

28024

28025 /*

28026 The mask value used in MTRR-like address

28027 matching of platform. Minimum granularity for

28028 matches is 4K (aligned), but the ucode handler

28029 can use RR_MATCH_ADDR and the resume capability

28030 (see the PRF register definition) to achieve

28031 narrower checking. restrictions : Set

28032 corresponding AMRR_BASE appropriately for the

28033 address. Set VLD, ASSIST, IFETCH, and MASK.

28034 */

28035 UINT32 Rsvd52 : 12;

28036

28037 /* Bits[63:52], Access Type=RO, default=None*/

28038

28039 /* Reserved */

28040

28041 } Bits;

28042

28043 UINT32 Uint32;

28044 UINT64 Uint64;

28045

28046 } MSR_AMRR_MASK_3_3_REGISTER;

28047

28048 /**

28049 Address Match Range Register - Physical Base Control Register for Hidden Lake

28050 " seq has 2 instances in addresses range 0xF06 to 0xF08"

28051 **/

28052 #define MSR_AMRR_BASE_4_4 0x00000F08

28053

28054 typedef union {

28055 ///

28056 /// Individual bit fields

28057 ///

28058 struct {

28059 UINT32 TmeEn : 1;

28060

28061 /* Bits[0:0], Access Type=RW, default=0x00000000*/

28062

28063 /* Enable TME masking */

28064 UINT32 Rsvd1 : 11;

28065

28066 /* Bits[11:1], Access Type=RO, default=None*/

28067

28068 /* Reserved */

28069 UINT32 Base0 : 20;

28070

28071 /* Bits[31:12], Access Type=RW, default=0x00000000*/

28072

28073 /*

28074 The 4K-aligned platform physical base addresses

28075 of the 3 AMRR registers for debugging. These

28076 registers are programmed like MTRRs with base

28077 and mask. Address matches of an AMRR can be

28078 programmed to cause an "assist" or "abort".

28079 Assists invoke the address match ucode handler

28080 and populate the RR_MATCH_ADDR and

28081 RR_MATCH_RESULT CREGs with useful information

28082 about the access. Aborts force the memory type

28083 to UC and redirect the access to the abort page

28084 (causing it to get garbage data from the

28085 uncore). See AMRR_MASK bits for more information

28086 on how to program. See the PRF register

28087 definition for how to resume AMRR assist

28088 matches. restrictions : Set corresponding

28089 AMRR_MASK appropriately for the address.

28090 */

28091 UINT32 Base1 : 20;

28092

28093 /* Bits[51:32], Access Type=RW, default=0x00000000*/

28094

28095 /*

28096 The 4K-aligned platform physical base addresses

28097 of the 3 AMRR registers for debugging. These

28098 registers are programmed like MTRRs with base

28099 and mask. Address matches of an AMRR can be

28100 programmed to cause an "assist" or "abort".

28101 Assists invoke the address match ucode handler

28102 and populate the RR_MATCH_ADDR and

28103 RR_MATCH_RESULT CREGs with useful information

28104 about the access. Aborts force the memory type

28105 to UC and redirect the access to the abort page

28106 (causing it to get garbage data from the

28107 uncore). See AMRR_MASK bits for more information

28108 on how to program. See the PRF register

28109 definition for how to resume AMRR assist

28110 matches. restrictions : Set corresponding

28111 AMRR_MASK appropriately for the address.

28112 */

28113 UINT32 Rsvd52 : 12;

28114

28115 /* Bits[63:52], Access Type=RO, default=None*/

28116

28117 /* Reserved */

28118

28119 } Bits;

28120

28121 UINT32 Uint32;

28122 UINT64 Uint64;

28123

28124 } MSR_AMRR_BASE_4_4_REGISTER;

28125

28126 /**

28127 Address Match Range Register - Physical Mask Control Register for Hidden Lake

28128 " seq has 2 instances in addresses range 0xF07 to 0xF09"

28129 **/

28130 #define MSR_AMRR_MASK_4_4 0x00000F09

28131

28132 typedef union {

28133 ///

28134 /// Individual bit fields

28135 ///

28136 struct {

28137 UINT32 Rsvd0 : 3;

28138

28139 /* Bits[2:0], Access Type=RO, default=None*/

28140

28141 /* Reserved */

28142 UINT32 IgnorePw : 1;

28143

28144 /* Bits[3:3], Access Type=RW, default=0x00000000*/

28145

28146 /*

28147 If set, hitting the AMRR on a stuffed load will

28148 be ignored and will not cause assist nor abort.

28149 Only the real PA (on redispatch) can cause an

28150 assist if matches. restrictions :

28151 */

28152 UINT32 PhysegOvrd : 1;

28153

28154 /* Bits[4:4], Access Type=RW, default=0x00000000*/

28155

28156 /*

28157 If set, hitting the AMRR with PhySegSupOvr is

28158 allowed, and will not cause assist or abort

28159 restrictions :

28160 */

28161 UINT32 ForceWb : 1;

28162

28163 /* Bits[5:5], Access Type=RW, default=0x00000000*/

28164

28165 /*

28166 If set, hitting AMRR legally (see above bit),

28167 will also force WB memtype. This is subject to

28168 memtype priorities and can be overridden due to

28169 higher priority mem types restrictions :

28170 */

28171 UINT32 Rsvd6 : 2;

28172

28173 /* Bits[7:6], Access Type=RO, default=None*/

28174

28175 /* Reserved */

28176 UINT32 Ifetch : 1;

28177

28178 /* Bits[8:8], Access Type=RW, default=0x00000000*/

28179

28180 /*

28181 If set, allow AMRR assist matches for both

28182 I-side and D-side, else assist match D-side

28183 only. Pagewalk accesses (stuffed loads and

28184 loadpxelocks) always count as D-side. This bit

28185 has no effect on abort matches. restrictions :

28186 Set corresponding AMRR_BASE appropriately for

28187 the address. Set VLD, ASSIST, IFETCH, and MASK.

28188 */

28189 UINT32 Assist : 1;

28190

28191 /* Bits[9:9], Access Type=RW, default=0x00000000*/

28192

28193 /*

28194 If set, AMRR matches to the programmed address

28195 will invoke ucode's address match handler. If

28196 clear, AMRR matches will "abort" and redirect

28197 the access to the abort page and a UC memory

28198 type. restrictions : Set corresponding AMRR_BASE

28199 appropriately for the address. Set VLD, ASSIST,

28200 IFETCH, and MASK.

28201 */

28202 UINT32 L : 1;

28203

28204 /* Bits[10:10], Access Type=RW, default=0x00000000*/

28205

28206 /* Lock bit for the AMRR */

28207 UINT32 Rsvd11 : 1;

28208

28209 /* Bits[11:11], Access Type=RO, default=None*/

28210

28211 /* Reserved */

28212 UINT32 Mask0 : 20;

28213

28214 /* Bits[31:12], Access Type=RW, default=0x00000000*/

28215

28216 /*

28217 The mask value used in MTRR-like address

28218 matching of platform. Minimum granularity for

28219 matches is 4K (aligned), but the ucode handler

28220 can use RR_MATCH_ADDR and the resume capability

28221 (see the PRF register definition) to achieve

28222 narrower checking. restrictions : Set

28223 corresponding AMRR_BASE appropriately for the

28224 address. Set VLD, ASSIST, IFETCH, and MASK.

28225 */

28226 UINT32 Mask1 : 20;

28227

28228 /* Bits[51:32], Access Type=RW, default=0x00000000*/

28229

28230 /*

28231 The mask value used in MTRR-like address

28232 matching of platform. Minimum granularity for

28233 matches is 4K (aligned), but the ucode handler

28234 can use RR_MATCH_ADDR and the resume capability

28235 (see the PRF register definition) to achieve

28236 narrower checking. restrictions : Set

28237 corresponding AMRR_BASE appropriately for the

28238 address. Set VLD, ASSIST, IFETCH, and MASK.

28239 */

28240 UINT32 Rsvd52 : 12;

28241

28242 /* Bits[63:52], Access Type=RO, default=None*/

28243

28244 /* Reserved */

28245

28246 } Bits;

28247

28248 UINT32 Uint32;

28249 UINT64 Uint64;

28250

28251 } MSR_AMRR_MASK_4_4_REGISTER;

28252 /**

28253 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28254 " seq has 3 instances in addresses range 0x1001 to 0x1003"

28255 **/

28256 #define MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0 0x00001001

28257 /**

28258 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28259 " seq has 3 instances in addresses range 0x1001 to 0x1003"

28260 **/

28261 #define MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1 0x00001002

28262 /**

28263 Spare core MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28264 " seq has 3 instances in addresses range 0x1001 to 0x1003"

28265 **/

28266 #define MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2 0x00001003

28267 /**

28268 Spare Thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28269 " seq has 3 instances in addresses range 0x1004 to 0x1006"

28270 **/

28271 #define MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0 0x00001004

28272 /**

28273 Spare Thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28274 " seq has 3 instances in addresses range 0x1004 to 0x1006"

28275 **/

28276 #define MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1 0x00001005

28277 /**

28278 Spare Thread MSRs supported by the cregpla. Ucode (instead of the PLA) will signal #GP on access. CNL issue 1351559

28279 " seq has 3 instances in addresses range 0x1004 to 0x1006"

28280 **/

28281 #define MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2 0x00001006

28282 #endif /* _COMMONMSR_h */

MSR_TURBO_RATIO_LIMIT_REGISTER

MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT.

Definition: CpuRegs.h:74

Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
ConfigBlock.h File Reference

Header file for Config Block Lib implementation. More...

#include <Uefi/UefiBaseType.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
Include dependency graph for ConfigBlock.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _CONFIG_BLOCK_HEADER
Config Block Header. More...
struct | _CONFIG_BLOCK
Config Block. More...
struct | _CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header. More...

Typedefs

typedef struct _CONFIG_BLOCK_HEADER | CONFIG_BLOCK_HEADER
Config Block Header.
typedef struct _CONFIG_BLOCK | CONFIG_BLOCK
Config Block.
typedef struct _CONFIG_BLOCK_TABLE_STRUCT | CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlock.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
ConfigBlock.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_H_
18 #define _CONFIG_BLOCK_H_
19
20 #include <Uefi/UefiBaseType.h>
21 #include <Uefi/UefiMultiPhase.h>
22 #include <Pi/PiBootMode.h>
23 #include <Pi/PiHob.h>
24
25 #pragma pack (push,1)
26
27 ///
28 /// Config Block Header
29 ///
30 typedef struct _CONFIG_BLOCK_HEADER {
31 EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
32 UINT8 Revision; ///< Offset 24 Revision of this config block
33 UINT8 Attributes; ///< Offset 25 The main revision for config block
34 UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
35 } CONFIG_BLOCK_HEADER;
36
37 ///
38 /// Config Block
39 ///
40 typedef struct _CONFIG_BLOCK {
41 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
42 //
43 // Config Block Data
44 //
45 } CONFIG_BLOCK;
46
47 ///
48 /// Config Block Table Header
49 ///
50 typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
51 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
52 UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
53 UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
54 UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
55 ///
56 /// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
57 ///
58 } CONFIG_BLOCK_TABLE_HEADER;
59 #pragma pack (pop)
60
61 #endif // _CONFIG_BLOCK_H_
62
CONFIG_BLOCK_HEADER
struct _CONFIG_BLOCK_HEADER CONFIG_BLOCK_HEADER
Config Block Header.
CONFIG_BLOCK
struct _CONFIG_BLOCK CONFIG_BLOCK
Config Block.
_CONFIG_BLOCK_HEADER::Reserved
UINT8 Reserved[2]
Offset 26-27 Reserved for future use.
Definition: ConfigBlock.h:34
_CONFIG_BLOCK_TABLE_STRUCT::NumberOfBlocks
UINT16 NumberOfBlocks
Offset 30-31 Number of config blocks (N)
Definition: ConfigBlock.h:53
_CONFIG_BLOCK_HEADER::Revision
UINT8 Revision
Offset 24 Revision of this config block.
Definition: ConfigBlock.h:32
_CONFIG_BLOCK_TABLE_STRUCT::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 GUID number for main entry of config block.
Definition: ConfigBlock.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CONFIG_BLOCK_TABLE_HEADER
struct _CONFIG_BLOCK_TABLE_STRUCT CONFIG_BLOCK_TABLE_HEADER
Config Block Table Header.
_CONFIG_BLOCK::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Header of config block.
Definition: ConfigBlock.h:41
_CONFIG_BLOCK_HEADER::Attributes
UINT8 Attributes
Offset 25 The main revision for config block.
Definition: ConfigBlock.h:33
_CONFIG_BLOCK
Config Block.
Definition: ConfigBlock.h:40
_CONFIG_BLOCK_TABLE_STRUCT::Rsvd0
UINT8 Rsvd0[2]
Offset 28-29 Reserved for future use.
Definition: ConfigBlock.h:52
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_CONFIG_BLOCK_TABLE_STRUCT::AvailableSize
UINT32 AvailableSize
Offset 32-35 Current config block table size.
Definition: ConfigBlock.h:54
_CONFIG_BLOCK_HEADER::GuidHob
EFI_HOB_GUID_TYPE GuidHob
Offset 0-23 GUID extension HOB header.
Definition: ConfigBlock.h:31
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlockLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ConfigBlockLib.h File Reference

Header file for Config Block Lib implementation. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

EFI_STATUS | CreateConfigBlockTable (IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table. More...
EFI_STATUS | AddConfigBlock (IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure. More...
EFI_STATUS | GetConfigBlock (IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID. More...

Detailed Description

Header file for Config Block Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConfigBlockLib.h.

Function Documentation

◆ AddConfigBlock()

EFI_STATUS AddConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Add config block into config block table structure.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_OUT_OF_RESOURCES | - Config Block Table is full and cannot add new Config Block or Config Block Offset Table is full and cannot add new Config Block.
EFI_SUCCESS | - Successfully added Config Block

◆ CreateConfigBlockTable()

EFI_STATUS CreateConfigBlockTable | ( | IN UINT16 | TotalSize,
 |  | OUT VOID ** | ConfigBlockTableAddress
 | ) |  |

Create config block table.

Parameters
[in] | TotalSize | - Max size to be allocated for the Config Block Table
[out] | ConfigBlockTableAddress | - On return, points to a pointer to the beginning of Config Block Table Address
Return values
EFI_INVALID_PARAMETER | - Invalid Parameter
EFI_OUT_OF_RESOURCES | - Out of resources
EFI_SUCCESS | - Successfully created Config Block Table at ConfigBlockTableAddress

◆ GetConfigBlock()

EFI_STATUS GetConfigBlock | ( | IN VOID * | ConfigBlockTableAddress,
 |  | IN EFI_GUID * | ConfigBlockGuid,
 |  | OUT VOID ** | ConfigBlockAddress
 | ) |  |

Retrieve a specific Config Block data by GUID.

Parameters
[in] | ConfigBlockTableAddress | - A pointer to the beginning of Config Block Table Address
[in] | ConfigBlockGuid | - A pointer to the GUID uses to search specific Config Block
[out] | ConfigBlockAddress | - On return, points to a pointer to the beginning of Config Block Address
Return values
EFI_NOT_FOUND | - Could not find the Config Block
EFI_SUCCESS | - Config Block found and return
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlockLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ConfigBlockLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Config Block Lib implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _CONFIG_BLOCK_LIB_H_
18 #define _CONFIG_BLOCK_LIB_H_
19
20 /**
21 Create config block table
22
23 @param[in] TotalSize - Max size to be allocated for the Config Block Table
24 @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
25
26 @retval EFI_INVALID_PARAMETER - Invalid Parameter
27 @retval EFI_OUT_OF_RESOURCES - Out of resources
28 @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
29 **/
30 EFI_STATUS
31 EFIAPI
32 CreateConfigBlockTable (
33 IN UINT16 TotalSize,
34 OUT VOID **ConfigBlockTableAddress
35 );
36
37 /**
38 Add config block into config block table structure
39
40 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
41 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
42
43 @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
44 Config Block Offset Table is full and cannot add new Config Block.
45 @retval EFI_SUCCESS - Successfully added Config Block
46 **/
47 EFI_STATUS
48 EFIAPI
49 AddConfigBlock (
50 IN VOID *ConfigBlockTableAddress,
51 OUT VOID **ConfigBlockAddress
52 );
53
54 /**
55 Retrieve a specific Config Block data by GUID
56
57 @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
58 @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
59 @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
60
61 @retval EFI_NOT_FOUND - Could not find the Config Block
62 @retval EFI_SUCCESS - Config Block found and return
63 **/
64 EFI_STATUS
65 EFIAPI
66 GetConfigBlock (
67 IN VOID *ConfigBlockTableAddress,
68 IN EFI_GUID *ConfigBlockGuid,
69 OUT VOID **ConfigBlockAddress
70 );
71
72 #endif // _CONFIG_BLOCK_LIB_H_
73
AddConfigBlock
EFI_STATUS AddConfigBlock(IN VOID *ConfigBlockTableAddress, OUT VOID **ConfigBlockAddress)
Add config block into config block table structure.
GetConfigBlock
EFI_STATUS GetConfigBlock(IN VOID *ConfigBlockTableAddress, IN EFI_GUID *ConfigBlockGuid, OUT VOID **ConfigBlockAddress)
Retrieve a specific Config Block data by GUID.
CreateConfigBlockTable
EFI_STATUS CreateConfigBlockTable(IN UINT16 TotalSize, OUT VOID **ConfigBlockTableAddress)
Create config block table.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConsoleOutDevice.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
ConsoleOutDevice.h File Reference

This GUID can be installed to the device handle to specify that the device is the console-out device. More...

Go to the source code of this file.

Detailed Description

This GUID can be installed to the device handle to specify that the device is the console-out device.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ConsoleOutDevice.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConsoleOutDevice.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
ConsoleOutDevice.h
Go to the documentation of this file.
1 /** @file
2 This GUID can be installed to the device handle to specify that the device is the console-out device.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef __CONSOLE_OUT_DEVICE_H__
18 #define __CONSOLE_OUT_DEVICE_H__
19
20 #define EFI_CONSOLE_OUT_DEVICE_GUID \
21 { 0xd3b36f2c, 0xd551, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } }
22
23 extern EFI_GUID gEfiConsoleOutDeviceGuid;
24
25 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CoreBiosMsg.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
CoreBiosMsg.h File Reference

Core BIOS Messages. More...

#include <MkhiMsgs.h>
Include dependency graph for CoreBiosMsg.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | CBM_RESET_REQ_DATA
Reset request message data. More...
struct | CBM_RESET_REQ
Reset request MKHI message. More...
struct | CBM_RESET_ACK
Reset request MKHI ack message. More...

Macros

#define | BIOS_FIXED_HOST_ADDR 0
Host Address of Fixed Address MEI Header - This is the logical address of the Host client of the message. More...
#define | BIOS_ASF_HOST_ADDR 1
Statically allocated for host AMT/ASF message.
#define | HECI_HBM_MESSAGE_ADDR 0x00
ME Address of Fixed Address MEI Header - This is the logical address of the Intel(R) ME client of the message. More...
#define | HECI_MAX_ME_FIXED_ADDR 0x1F
Max ME address for fixed clients.

Detailed Description

Core BIOS Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2008 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CoreBiosMsg.h.

Macro Definition Documentation

◆ BIOS_FIXED_HOST_ADDR

#define BIOS_FIXED_HOST_ADDR 0

Host Address of Fixed Address MEI Header - This is the logical address of the Host client of the message.

This address is assigned when the host client registers itself with the Host MEI driver. Address 0 is statically allocated for MEI bus message protocol that assists in MEI bus enumeration, power management, error and other bus control functionality.

Definition at line 51 of file CoreBiosMsg.h.

◆ HECI_HBM_MESSAGE_ADDR

#define HECI_HBM_MESSAGE_ADDR 0x00

ME Address of Fixed Address MEI Header - This is the logical address of the Intel(R) ME client of the message.

This address is assigned during ME firmware initialization.

Definition at line 59 of file CoreBiosMsg.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CoreBiosMsg.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
CoreBiosMsg.h
Go to the documentation of this file.
1 /** @file
2 Core BIOS Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2008 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef CORE_BIOS_MSG_H
36 #define CORE_BIOS_MSG_H
37
38 #include <MkhiMsgs.h>
39
40 #pragma pack(1)
41
42 ///
43 /// Host Address of Fixed Address MEI Header -
44 /// This is the logical address of the Host client of the message. This address
45 /// is assigned when the host client registers itself with the Host MEI driver.
46
47 /**
48 Address 0 is statically allocated for MEI bus message protocol that assists in MEI bus
49 enumeration, power management, error and other bus control functionality.
50 **/
51 #define BIOS_FIXED_HOST_ADDR 0
52 #define BIOS_ASF_HOST_ADDR 1 ///< Statically allocated for host AMT/ASF message
53
54 ///
55 /// ME Address of Fixed Address MEI Header -
56 /// This is the logical address of the Intel(R) ME client
57 /// of the message. This address is assigned during ME firmware initialization.
58 ///
59 #define HECI_HBM_MESSAGE_ADDR 0x00
60 #define HECI_ASF_MESSAGE_ADDR 0x02
61 #define HECI_ISH_SERVICE_MESSAGE_ADDR 0x03
62 #define HECI_PSR_MESSAGE_ADDR 0x04
63 #define HECI_MKHI_MESSAGE_ADDR 0x07
64 #define HECI_ICC_MESSAGE_ADDR 0x08
65 #define HECI_MCHI_MESSAGE_ADDR 0x09
66 #define HECI_HWA_MESSAGE_ADDR 0x0B
67 #define HECI_UPID_MESSAGE_ADDR 0x0D
68 #define HECI_MAX_ME_FIXED_ADDR 0x1F ///< Max ME address for fixed clients
69
70 //
71 // MKHI_CBM_GROUP_ID = 0x00
72 //
73
74 ///
75 /// Reset request message data
76 ///
77 typedef struct {
78 UINT8 RequestOrigin;
79 UINT8 ResetType;
80 } CBM_RESET_REQ_DATA;
81
82 ///
83 /// Reset request MKHI message
84 ///
85 typedef struct {
86 MKHI_MESSAGE_HEADER MkhiHeader;
87 CBM_RESET_REQ_DATA Data;
88 } CBM_RESET_REQ;
89
90 ///
91 /// Reset request MKHI ack message
92 ///
93 typedef struct {
94 MKHI_MESSAGE_HEADER MkhiHeader;
95 } CBM_RESET_ACK;
96
97 //
98 // Enumerations used in Core BIOS Messages
99 //
100
101 //
102 // Reset Request Origin Codes.
103 //
104 #define CBM_RR_REQ_ORIGIN_BIOS_MEMORY_INIT 0x01
105 #define CBM_RR_REQ_ORIGIN_BIOS_POST 0x02
106 #define CBM_RR_REQ_ORIGIN_MEBX 0x03
107
108 //
109 // Reset Type Codes.
110 //
111 #define CBM_HRR_GLOBAL_RESET 0x01
112 #define CBM_HRR_HOST_RESET 0x02
113 #define CBM_HRR_CSME_RESET 0x03
114
115 //
116 // Reset Response Codes.
117 //
118 #define CBM_HRR_RES_REQ_NOT_ACCEPTED 0x01
119
120 #pragma pack()
121
122 #endif
CBM_RESET_ACK
Reset request MKHI ack message.
Definition: CoreBiosMsg.h:93
CBM_RESET_REQ
Reset request MKHI message.
Definition: CoreBiosMsg.h:85
MkhiMsgs.h
MKHI Messages.
MKHI_MESSAGE_HEADER
MKHI host message header.
Definition: MkhiMsgs.h:46
CBM_RESET_REQ_DATA
Reset request message data.
Definition: CoreBiosMsg.h:77
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuConfig.h File Reference

CPU Config Block. More...

Go to the source code of this file.

Classes

struct CPU_CONFIG
CPU Configuration Structure. More...

Detailed Description

CPU Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_CONFIG_H_
36 #define _CPU_CONFIG_H_
37
38 #define CPU_CONFIG_REVISION 5
39
40 extern EFI_GUID gCpuConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Add SmbiosType4MaxSpeedOverride.
51 <b>Revision 3</b>:
52 - Add AvxDisable & Avx3Disable.
53 <b>Revision 4</b>:
54 - Add X2ApicSupport.
55 <b>Revision 5</b>:
56 - Deprecate Avx3Disable
57 **/
58 typedef struct {
59 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
60 UINT32 MicrocodePatchRegionSize;
61 EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
62 /**
63 Enable or Disable Advanced Encryption Standard (AES) feature.
64 For some countries, this should be disabled for legal reasons.
65 - 0: Disable
66 - <b>1: Enable</b>
67 **/
68 UINT32 AesEnable : 1;
69 /**
70 Enable or Disable Trusted Execution Technology (TXT) feature.
71 - 0: Disable
72 - <b>1: Enable</b>
73 **/
74 UINT32 TxtEnable : 1;
75 UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
76 /**
77 Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.
78 - <b>0: Disable</b>
79 - 1: Enable
80 - 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If EOM is set, it is disabled.
81 **/
82 UINT32 PpinSupport : 2;
83 /**
84 Enable or Disable #AC machine check on split lock.
85 - <b>0: Disable</b>
86 - 1: Enable
87 **/
88 UINT32 AcSplitLock : 1;
89 /**
90 Enable or Disable Avx.
91 - 1: Disable
92 - <b> 0: Enable</b>
93 **/
94 UINT32 AvxDisable : 1;
95 /**
96 @deprecated
97 Enable or Disable Avx3.
98 - <b> 1: Disable</b>
99 - 0: Enable
100 **/
101 UINT32 Avx3Disable : 1;
102 /**
103 Enable or Disable X2APIC Support.
104 - <b>0: Disable</b>
105 - 1: Enable
106 **/
107 UINT32 X2ApicSupport : 1;
108 UINT32 RsvdBits : 23; ///< Reserved for future use
109 /**
110 Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
111 Value 4000 means 4000MHz.
112 If this value is not zero, it dominates the field.
113 If this value is zero, CPU RC will update the field according to the max radio.
114 <b>default is 0.</b>
115 **/
116 UINT16 SmbiosType4MaxSpeedOverride;
117 UINT8 Reserved0[2]; ///< Reserved for future use
118 } CPU_CONFIG;
119
120 #pragma pack (pop)
121
122 #endif // _CPU_CONFIG_H_
CPU_CONFIG::AvxDisable
UINT32 AvxDisable
Enable or Disable Avx.
Definition: CpuConfig.h:94
CPU_CONFIG::PpinSupport
UINT32 PpinSupport
Enable or Disable or Auto for PPIN Support to view Protected Processor Inventory Number.
Definition: CpuConfig.h:82
CPU_CONFIG::AcSplitLock
UINT32 AcSplitLock
Enable or Disable #AC machine check on split lock.
Definition: CpuConfig.h:88
CPU_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuConfig.h:59
CPU_CONFIG::SkipMpInit
UINT32 SkipMpInit
For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled....
Definition: CpuConfig.h:75
CPU_CONFIG::MicrocodePatchAddress
EFI_PHYSICAL_ADDRESS MicrocodePatchAddress
Pointer to microcode patch that is suitable for this processor.
Definition: CpuConfig.h:61
CPU_CONFIG::TxtEnable
UINT32 TxtEnable
Enable or Disable Trusted Execution Technology (TXT) feature.
Definition: CpuConfig.h:74
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_CONFIG::X2ApicSupport
UINT32 X2ApicSupport
Enable or Disable X2APIC Support.
Definition: CpuConfig.h:107
CPU_CONFIG::AesEnable
UINT32 AesEnable
Enable or Disable Advanced Encryption Standard (AES) feature.
Definition: CpuConfig.h:68
CPU_CONFIG
CPU Configuration Structure.
Definition: CpuConfig.h:58
CPU_CONFIG::SmbiosType4MaxSpeedOverride
UINT16 SmbiosType4MaxSpeedOverride
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
Definition: CpuConfig.h:116
CPU_CONFIG::Avx3Disable
UINT32 Avx3Disable
Definition: CpuConfig.h:101
CPU_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuConfig.h:108
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuConfigLibPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuConfigLibPreMemConfig.h File Reference

CPU Security PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_CONFIG_LIB_PREMEM_CONFIG
CPU Config Library PreMemory Configuration Structure. More...

Detailed Description

CPU Security PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2015 - 2021 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification Reference:

Definition in file CpuConfigLibPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuConfigLibPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuConfigLibPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Security PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2015 - 2021 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 @par Specification Reference:
21 **/
22 #ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
23 #define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
24
25 #define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 11
26
27 extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
28
29 #define BOOT_FREQUENCY_MAX_BATTERY_PERF 0
30 #define BOOT_FREQUENCY_MAX_NON_TURBO_PERF 1
31 #define BOOT_FREQUENCY_TURBO_PERF 2
32
33 #pragma pack (push,1)
34
35 /**
36 CPU Config Library PreMemory Configuration Structure.
37
38 <b>Revision 1</b>:
39 - Initial version.
40 <b>Revision 2</b>:
41 - Expand the supported number of processor cores (ActiveCoreCount1).
42 <b>Revision 3</b>:
43 - Added PECI Sx and C10 Reset.
44 <b>Revision 4</b>:
45 - Added ActiveSmallCoreCount.
46 <b>Revision 5</b>:
47 - Added CrashLogGprs
48 <b>Revision 6</b>:
49 - Added ActiveSocNorthAtomCoreCount
50 <b>Revision 7</b>:
51 - Added ComputeDieSscEnable, SocDieSscEnable, ComputeDieSscValue, and SocDieSscValue
52 <b>Revision 8</b>:
53 - Added BclkSource.
54 <b>Revision 9</b>:
55 - Removed Elixir Springs Patch
56 <b>Revision 10</b>
57 - Add InfDfxPwrEnable
58 <b>Revision 11</b>
59 - Add ConfigTdpLevel, CustomPowerLimit1
60 **/
61 typedef struct {
62 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
63 UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
64 /**
65 Sets the boot frequency starting from reset vector.
66 - 0: Maximum battery performance.
67 - 1: Maximum non-turbo performance
68 -<b>2: Turbo performance</b>.
69 @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
70 **/
71 UINT32 BootFrequency : 2;
72 /**
73 Number of processor cores to enable.
74 - <b> 0: All cores</b>
75 - 1: 1 core
76 - 2: 2 cores
77 - 3: 3 cores
78 **/
79 UINT32 ActiveCoreCount : 3; ///< @deprecated due to core active number limitaion.
80 UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power states for debug purpose. <b>0: False<\b>; 1: True.
81 UINT32 BistOnReset : 1; ///< <b>(Test)</b> Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
82 /**
83 Enable or Disable Virtual Machine Extensions (VMX) feature.
84 - 0: Disable
85 - <b>1: Enable</b>
86 **/
87 UINT32 VmxEnable : 1;
88 /**
89 Processor Early Power On Configuration FCLK setting.
90 - <b>0: 800 MHz (ULT/ULX)</b>.
91 - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
92 - 2: 400 MHz.
93 - 3: Reserved.
94 **/
95 UINT32 FClkFrequency : 2;
96 /**
97 Enable or Disable CrashLog feature
98 - 0: Disable
99 - <b>1: Enable</b>
100 **/
101 UINT32 CrashLogEnable : 1;
102
103 /**
104 Enable or Disable Total Memory Encryption (TME) feature.
105 - 0: Disable
106 - <b>1: Enable</b>
107 **/
108 UINT32 TmeEnable : 1;
109
110 UINT32 DebugInterfaceEnable : 2; ///< Enable or Disable processor debug features; 0: Disable; 1: Enable; <b>2: No Change</b>.
111 UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
112
113 /**
114 Number of big cores in processor to enable.
115 And support up to 15 cores.
116 - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 16).
117 - 1: 1 core
118 - 2: 2 cores
119 - 3: 3 cores
120 **/
121 UINT32 ActiveCoreCount1 : 4;
122
123 /**
124 Enables a mailbox command to resolve rare PECI related Sx issues.
125 @note This should only be used on systems that observe PECI Sx issues.
126 - <b>0: Disable</b>
127 - 1: Enable
128 **/
129 UINT32 PeciSxReset : 1;
130
131 /**
132 Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
133 If Enabled, BIOS will send the CPU message to disable peci reset on C10 exit.
134 The default value <b>0: Disable</b> for CPU's
135 - 0: Disable
136 - 1: Enable
137 **/
138 UINT32 PeciC10Reset : 1; ///< @deprecated no longer used.
139
140 /**
141 Number of small cores in processor to enable.
142 And support up to 63 cores.
143 - 0: Disable all cores for Hybrid CPU; Active all cores for Non-Hybrid CPU (MAX 64).
144 - 1: 1 core
145 - 2: 2 cores
146 - 3: 3 cores
147 **/
148 UINT32 ActiveSmallCoreCount : 6;
149
150 /**
151 Enable or Disable CrashLog GPRs dump
152 - <b>0: Disable</b>
153 - 1: Gprs Enabled, Smm Gprs Enabled
154 2: Gprs Enabled, Smm Gprs Disabled
155 **/
156 UINT32 CrashLogGprs : 2;
157
158 /**
159 Enable or Disable Compute Die SSC configuration.
160 - <b>0: Disable</b>
161 - 1: Enable
162 **/
163 UINT32 ComputeDieSscEnable : 1;
164
165 /**
166 Enable or Disable Soc Die SSC configuration.
167 - <b>0: Disable</b>
168 - 1: Enable
169 **/
170 UINT32 SocDieSscEnable : 1;
171
172 /**
173 CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio. <b>0: Disabled</b> If disabled, doesn't override max-non turbo ratio.
174 **/
175 UINT8 CpuRatio;
176
177 /**
178 Number of enabled atom cores on SoC.
179 Default is set to supported core number.
180 - 0 - all core disabled
181 - 1 - enable 1 core
182 - 2 - enable 2 cores
183 - others - reserved for future use
184 **/
185 UINT8 ActiveSocNorthAtomCoreCount;
186
187 /**
188 SSC configuration value of Compute Die.
189 SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.
190 - <b>0 : invalid</b>
191 - 1 : 0.01%
192 - 2 : 0.02%
193 - 100 : 1%
194 **/
195 UINT8 ComputeDieSscValue;
196
197 /**
198 SSC configuration value of Soc Die.
199 SSC downspread field encoding. Downspread in percent = SSC_DOWNSPREAD / 100.
200 - <b>0 : invalid</b>
201 - 1 : 0.01%
202 - 2 : 0.02%
203 - 100 : 1%
204 **/
205 UINT8 SocDieSscValue;
206
207 /**
208 Clock source of BCLK OC Frequency
209 - 0: SOC
210 - <b>1: CPU</b>
211 - 2: PCH
212 - 3: Ext. Clock (optional)
213 **/
214 UINT32 BclkSource : 2;
215 UINT32 RsvdBits : 30;
216 /**
217 Determine whether to keep or shutdown INF_DFX power rail. INF_DFX power is up from cold boot.
218 - <b>0 : INF_DFX shutdown</b>
219 - 1 : INF_DFX power up </b>
220 **/
221 UINT8 InfDfxPwrEnable;
222 /**
223 Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up.
224 **/
225 UINT8 ConfigTdpLevel;
226 UINT8 RsvdByte[2];
227 UINT32 CustomPowerLimit1;
228
229 } CPU_CONFIG_LIB_PREMEM_CONFIG;
230
231 #pragma pack (pop)
232
233 #endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
CPU_CONFIG_LIB_PREMEM_CONFIG::DebugInterfaceLockEnable
UINT32 DebugInterfaceLockEnable
Lock or Unlock debug interface features; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:111
CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogEnable
UINT32 CrashLogEnable
Enable or Disable CrashLog feature.
Definition: CpuConfigLibPreMemConfig.h:101
CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscEnable
UINT32 ComputeDieSscEnable
Enable or Disable Compute Die SSC configuration.
Definition: CpuConfigLibPreMemConfig.h:163
CPU_CONFIG_LIB_PREMEM_CONFIG::ConfigTdpLevel
UINT8 ConfigTdpLevel
Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up.
Definition: CpuConfigLibPreMemConfig.h:225
CPU_CONFIG_LIB_PREMEM_CONFIG
CPU Config Library PreMemory Configuration Structure.
Definition: CpuConfigLibPreMemConfig.h:61
CPU_CONFIG_LIB_PREMEM_CONFIG::VmxEnable
UINT32 VmxEnable
Enable or Disable Virtual Machine Extensions (VMX) feature.
Definition: CpuConfigLibPreMemConfig.h:87
CPU_CONFIG_LIB_PREMEM_CONFIG::BootFrequency
UINT32 BootFrequency
Sets the boot frequency starting from reset vector.
Definition: CpuConfigLibPreMemConfig.h:71
CPU_CONFIG_LIB_PREMEM_CONFIG::BclkSource
UINT32 BclkSource
Clock source of BCLK OC Frequency.
Definition: CpuConfigLibPreMemConfig.h:214
CPU_CONFIG_LIB_PREMEM_CONFIG::PeciC10Reset
UINT32 PeciC10Reset
Enables the mailbox command to resolve PECI reset issues during Pkg-C10 exit.
Definition: CpuConfigLibPreMemConfig.h:138
CPU_CONFIG_LIB_PREMEM_CONFIG::BistOnReset
UINT32 BistOnReset
(Test) Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:81
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount
UINT32 ActiveCoreCount
Number of processor cores to enable.
Definition: CpuConfigLibPreMemConfig.h:79
CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscEnable
UINT32 SocDieSscEnable
Enable or Disable Soc Die SSC configuration.
Definition: CpuConfigLibPreMemConfig.h:170
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_CONFIG_LIB_PREMEM_CONFIG::TmeEnable
UINT32 TmeEnable
Enable or Disable Total Memory Encryption (TME) feature.
Definition: CpuConfigLibPreMemConfig.h:108
CPU_CONFIG_LIB_PREMEM_CONFIG::CrashLogGprs
UINT32 CrashLogGprs
Enable or Disable CrashLog GPRs dump.
Definition: CpuConfigLibPreMemConfig.h:156
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSmallCoreCount
UINT32 ActiveSmallCoreCount
Number of small cores in processor to enable.
Definition: CpuConfigLibPreMemConfig.h:148
CPU_CONFIG_LIB_PREMEM_CONFIG::PeciSxReset
UINT32 PeciSxReset
Enables a mailbox command to resolve rare PECI related Sx issues.
Definition: CpuConfigLibPreMemConfig.h:129
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveCoreCount1
UINT32 ActiveCoreCount1
Number of big cores in processor to enable.
Definition: CpuConfigLibPreMemConfig.h:121
CPU_CONFIG_LIB_PREMEM_CONFIG::ComputeDieSscValue
UINT8 ComputeDieSscValue
SSC configuration value of Compute Die.
Definition: CpuConfigLibPreMemConfig.h:195
CPU_CONFIG_LIB_PREMEM_CONFIG::DebugInterfaceEnable
UINT32 DebugInterfaceEnable
Enable or Disable processor debug features; 0: Disable; 1: Enable; 2: No Change.
Definition: CpuConfigLibPreMemConfig.h:110
CPU_CONFIG_LIB_PREMEM_CONFIG::CpuRatio
UINT8 CpuRatio
CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
Definition: CpuConfigLibPreMemConfig.h:175
CPU_CONFIG_LIB_PREMEM_CONFIG::HyperThreading
UINT32 HyperThreading
Enable or Disable Hyper Threading; 0: Disable; 1: Enable.
Definition: CpuConfigLibPreMemConfig.h:63
CPU_CONFIG_LIB_PREMEM_CONFIG::InfDfxPwrEnable
UINT8 InfDfxPwrEnable
Determine whether to keep or shutdown INF_DFX power rail.
Definition: CpuConfigLibPreMemConfig.h:221
CPU_CONFIG_LIB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuConfigLibPreMemConfig.h:62
CPU_CONFIG_LIB_PREMEM_CONFIG::ActiveSocNorthAtomCoreCount
UINT8 ActiveSocNorthAtomCoreCount
Number of enabled atom cores on SoC.
Definition: CpuConfigLibPreMemConfig.h:185
CPU_CONFIG_LIB_PREMEM_CONFIG::SocDieSscValue
UINT8 SocDieSscValue
SSC configuration value of Soc Die.
Definition: CpuConfigLibPreMemConfig.h:205
CPU_CONFIG_LIB_PREMEM_CONFIG::FClkFrequency
UINT32 FClkFrequency
Processor Early Power On Configuration FCLK setting.
Definition: CpuConfigLibPreMemConfig.h:95
CPU_CONFIG_LIB_PREMEM_CONFIG::JtagC10PowerGateDisable
UINT32 JtagC10PowerGateDisable
False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 and deeper power st...
Definition: CpuConfigLibPreMemConfig.h:80
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
CpuDataHob.h File Reference

The GUID definition for CpuDataHob. More...

#include <VoltageRegulatorCommands.h>
Include dependency graph for CpuDataHob.h:

Go to the source code of this file.

Classes

struct CPU_DATA_HOB
CPU Data Hob. More...

Detailed Description

The GUID definition for CpuDataHob.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDataHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
CpuDataHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for CpuDataHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_DATA_HOB_H_
36 #define _CPU_DATA_HOB_H_
37
38 #include <VoltageRegulatorCommands.h>
39
40 extern EFI_GUID gCpuDataHobGuid;
41
42
43 ///
44 /// CPU Data Hob
45 ///
46 typedef struct {
47 UINT8 SvidEnabled; ///< Svid Enabled\Disabled according to various VR domains. Refer to the definition in Fru.
48 UINT8 MaxVrIndex;
49 UINT8 MinVrIndex;
50 UINT8 Reserved0;
51 UINT8 VrAddress[MAX_VR_INDEX]; ///< VR address according to various VR domains.
52 UINT8 Reserved1[(4 - (MAX_VR_INDEX % 4)) % 4]; ///< Padding for CPU Data Hon alignment.
53 } CPU_DATA_HOB;
54
55 #endif // _CPU_DATA_HOB_H_
CPU_DATA_HOB
CPU Data Hob.
Definition: CpuDataHob.h:46
CPU_DATA_HOB::SvidEnabled
UINT8 SvidEnabled
Svid Enabled\Disabled according to various VR domains. Refer to the definition in Fru.
Definition: CpuDataHob.h:47
VoltageRegulatorCommands.h
Header file containing Voltage Regulator initialization common definitions.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDataStruct.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Classes
CpuDataStruct.h File Reference

This file declares various data structures used in CPU reference code. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct BIST_HOB_DATA
Store BIST data for BSP. More...

Detailed Description

This file declares various data structures used in CPU reference code.

Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDataStruct.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDataStruct.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
CpuDataStruct.h
Go to the documentation of this file.
1 /** @file
2 This file declares various data structures used in CPU reference code.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2004 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_DATA_STRUCT_H
37 #define _CPU_DATA_STRUCT_H
38
39 #pragma pack(1)
40 ///
41 /// Store BIST data for BSP.
42 ///
43 typedef struct {
44 UINT32 ApicId; ///< APIC ID
45 UINT32 Health; ///< BIST result
46 } BIST_HOB_DATA;
47
48 #pragma pack()
49
50 #endif
BIST_HOB_DATA::Health
UINT32 Health
BIST result.
Definition: CpuDataStruct.h:45
BIST_HOB_DATA
Store BIST data for BSP.
Definition: CpuDataStruct.h:43
BIST_HOB_DATA::ApicId
UINT32 ApicId
APIC ID.
Definition: CpuDataStruct.h:44
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
CpuDmiHob.h File Reference

The GUID definition for CpuDmiHob. More...

#include <Base.h>
Include dependency graph for CpuDmiHob.h:

Go to the source code of this file.

Classes

struct CPU_DMI_HOB
The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi. More...

Detailed Description

The GUID definition for CpuDmiHob.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDmiHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
CpuDmiHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for CpuDmiHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_DMI_HOB_H_
36 #define _CPU_DMI_HOB_H_
37
38 #include <Base.h>
39
40 #define CPU_DMI_HWEQ_COEFFS_MAX 8
41
42 extern EFI_GUID gCpuDmiHobGuid;
43 #pragma pack (push,1)
44
45 /**
46 The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi
47 **/
48 typedef struct {
49 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuDmieHobGuid
50
51 ///
52 /// These members describe the configuration of each CPU Dmi root port.
53 ///
54 UINT8 CmGen3[CPU_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C-1 for Gen3
55 UINT8 CpGen3[CPU_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C+1 for Gen3
56 UINT8 CmGen4[CPU_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C-1 for Gen4
57 UINT8 CpGen4[CPU_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C+1 for Gen4
58 } CPU_DMI_HOB;
59 #pragma pack (pop)
60 #endif
CPU_DMI_HOB
The CPU_DMI_HOB block describes the expected configuration of Cpu Dmi.
Definition: CpuDmiHob.h:48
CPU_DMI_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gCpuDmieHobGuid.
Definition: CpuDmiHob.h:49
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
CpuDmiInfoLib.h File Reference

Header file for CpuDmiInfoLib. More...

Go to the source code of this file.

Functions

BOOLEAN | IsPchLinkDmi (VOID)
Determine if PCH Link is DMI/OPI. More...
UINT8 | GetMaxDmiLanes ()
Returns the number of DMI lanes for current CPU. More...
UINT8 | GetMaxDmiBundles ()
Returns the number of DMI bundles for current CPU. More...
BOOLEAN | IsCpuDmiEnabled (VOID)
Checks if Cpu Dmi is Enabled. More...
BOOLEAN | IsDmiGen4Supported (VOID)
Checks if Cpu Dmi Gen4 is Enabled. More...

Detailed Description

Header file for CpuDmiInfoLib.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDmiInfoLib.h.

Function Documentation

◆ GetMaxDmiBundles()

UINT8 GetMaxDmiBundles ( )

Returns the number of DMI bundles for current CPU.

Return values
UINT8 Number of DMI bundles

◆ GetMaxDmiLanes()

UINT8 GetMaxDmiLanes ( )

Returns the number of DMI lanes for current CPU.

Return values
UINT8 Number of DMI lanes

◆ IsCpuDmiEnabled()

BOOLEAN IsCpuDmiEnabled ( VOID )

Checks if Cpu Dmi is Enabled.

Return values
TRUE | Cpu Dmi is Enabled
FALSE | Cpu Dmi is not Enabled

◆ IsDmiGen4Supported()

BOOLEAN IsDmiGen4Supported ( VOID )

Checks if Cpu Dmi Gen4 is Enabled.

Return values
TRUE | Cpu Dmi Gen4 is Enabled
FALSE | Cpu Dmi Gen4 is not Enabled

◆ IsPchLinkDmi()

BOOLEAN IsPchLinkDmi ( VOID )

Determine if PCH Link is DMI/OPI.

Return values
TRUE | DMI
FALSE | OPI
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
CpuDmiInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for CpuDmiInfoLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef CPU_DMI_INFO_LIB_H_
36 #define CPU_DMI_INFO_LIB_H_
37
38 #define LANE_MULTIPLIER 0x1000
39
40 /**
41 Determine if PCH Link is DMI/OPI
42
43 @retval TRUE DMI
44 @retval FALSE OPI
45 **/
46 BOOLEAN
47 IsPchLinkDmi (
48 VOID
49 );
50
51 /**
52 Returns the number of DMI lanes for current CPU
53
54 @retval UINT8 Number of DMI lanes
55 **/
56 UINT8
57 GetMaxDmiLanes (
58 );
59
60 /**
61 Returns the number of DMI bundles for current CPU
62
63 @retval UINT8 Number of DMI bundles
64 **/
65 UINT8
66 GetMaxDmiBundles (
67 );
68 /**
69 Checks if Cpu Dmi is Enabled
70
71 @retval TRUE Cpu Dmi is Enabled
72 @retval FALSE Cpu Dmi is not Enabled
73 **/
74 BOOLEAN
75 IsCpuDmiEnabled (
76 VOID
77 );
78 /**
79 Checks if Cpu Dmi Gen4 is Enabled
80
81 @retval TRUE Cpu Dmi Gen4 is Enabled
82 @retval FALSE Cpu Dmi Gen4 is not Enabled
83 **/
84 BOOLEAN
85 IsDmiGen4Supported (
86 VOID
87 );
88
89 #endif // CPU_DMI_INFO_LIB_H_
IsDmiGen4Supported
BOOLEAN IsDmiGen4Supported(VOID)
Checks if Cpu Dmi Gen4 is Enabled.
GetMaxDmiBundles
UINT8 GetMaxDmiBundles()
Returns the number of DMI bundles for current CPU.
IsCpuDmiEnabled
BOOLEAN IsCpuDmiEnabled(VOID)
Checks if Cpu Dmi is Enabled.
GetMaxDmiLanes
UINT8 GetMaxDmiLanes()
Returns the number of DMI lanes for current CPU.
IsPchLinkDmi
BOOLEAN IsPchLinkDmi(VOID)
Determine if PCH Link is DMI/OPI.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
Classes | Enumerations
CpuDmiPreMemConfig.h File Reference

DMI policy. More...

#include <ConfigBlock.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for CpuDmiPreMemConfig.h:

Go to the source code of this file.

Classes

struct | CPU_DMI_EQ_PARAM
Represent lane specific Dmi Gen3 equalization parameters. More...
struct | CPU_DMI_PREMEM_CONFIG
The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI. More...

Enumerations

enum DMI_ASPM
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.

Detailed Description

DMI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuDmiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
CpuDmiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 DMI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_DMI_PREMEM_CONFIG_H_
36 #define _CPU_DMI_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <Register/SaRegsHostBridge.h>
40
41 #define CPU_DMI_PREMEM_CONFIG_REVISION 4
42
43 #define CPU_DMI_HWEQ_COEFFS_MAX 8
44
45 #pragma pack (push,1)
46 ///
47 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
48 ///
49 typedef enum {
50 DmiAspmDisabled,
51 DmiAspmL0s,
52 DmiAspmL1,
53 DmiAspmL0sL1,
54 DmiAspmAutoConfig,
55 DmiAspmMax
56 } DMI_ASPM;
57
58 /**
59 Represent lane specific Dmi Gen3 equalization parameters.
60 **/
61 typedef struct {
62 UINT8 Cm; ///< Coefficient C-1
63 UINT8 Cp; ///< Coefficient C+1
64 UINT8 Rsvd0[2]; ///< Reserved bytes
65 } CPU_DMI_EQ_PARAM;
66
67 /**
68 The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.
69 <b>Revision 1</b>:
70 - Initial version.
71 <b>Revision 2</b>:
72 - Added Policies for Dmi Higer Speed Training.
73 <b>Revision 3</b>:
74 - Added DmiCdrRelock Policy.
75 **/
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78
79 /**
80 - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
81 - Gen1 (0x1) : Limit Link to Gen1 Speed
82 - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig
83 - Gen3 (0x3) : Limit Link to Gen3 Speed
84 **/
85 UINT8 DmiMaxLinkSpeed;
86 /**
87 <b>(Test)</b> DMI Equalization Phase 2 Enable Control
88 - Disabled (0x0) : Disable phase 2
89 - Enabled (0x1) : Enable phase 2
90 - <b>Auto</b> (0x2) : Use the current default method (Default)
91 **/
92 UINT8 DmiGen3EqPh2Enable;
93 /**
94 <b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
95 - <b>Auto</b> (0x0) : Use the current default method (Default)
96 - HwEq (0x1) : Use Adaptive Hardware Equalization
97 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
98 - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
99 - Disabled (0x4) : Bypass Equalization Phase 3
100 **/
101 UINT8 DmiGen3EqPh3Method;
102 /**
103 <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
104 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
105 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
106 **/
107 UINT8 DmiGen3ProgramStaticEq;
108 UINT8 DmiDeEmphasis; ///< DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
109 UINT8 DmiAspm;
110 UINT8 DmiAspmCtrl; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
111 UINT8 DmiAspmL1ExitLatency; ///< ASPM configuration on the CPU side of the DMI/OPI Link. Default is <b>DmiAspmAutoConfig</b>
112 UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
113 UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
114 UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
115
116 /**
117 DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
118 has to be specified based upon platform design and must follow the guideline. Default is 12.
119 **/
120
121 UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
122 UINT8 DmiGen3DsPortRxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
123 UINT8 DmiGen3DsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
124 UINT8 DmiGen3UsPortRxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
125 UINT8 DmiGen3UsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
126 UINT8 Gen3EqPhase23Bypass;
127 UINT8 Gen3EqPhase3Bypass;
128 UINT8 Gen3LtcoEnable;
129 UINT8 Gen3RtcoRtpoEnable;
130 UINT8 DmiGen3Ltcpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
131 UINT8 DmiGen3Ltcpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
132 UINT8 DmiGen3RtcoCpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
133 UINT8 DmiGen3RtcoCpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
134 CPU_DMI_EQ_PARAM DmiHwEqGen3CoeffList[CPU_DMI_HWEQ_COEFFS_MAX];
135 UINT8 DmiHweq;
136 UINT8 DmiGen3DsPresetEnable;
137 UINT8 DmiGen3UsPresetEnable;
138 UINT8 Rsvd0[1]; ///< Reserved bytes
139 CPU_DMI_EQ_PARAM DmiHwEqGen4CoeffList[CPU_DMI_HWEQ_COEFFS_MAX];
140 UINT8 Gen4EqPhase23Bypass;
141 UINT8 Gen4EqPhase3Bypass;
142 UINT8 DmiGen4DsPresetEnable;
143 UINT8 DmiGen4UsPresetEnable;
144 UINT8 Gen4RtcoRtpoEnable;
145 UINT8 Gen4LtcoEnable;
146 UINT8 DmiGen4Ltcpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
147 UINT8 DmiGen4Ltcpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
148 UINT8 DmiGen4DsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
149 UINT8 DmiGen4UsPortTxPreset[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
150 UINT8 DmiGen4RtcoCpre[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
151 UINT8 DmiGen4RtcoCpo[SA_DMI_MAX_LANE]; ///< Used for programming DMI Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
152 UINT8 DmiNewFom; ///< Used for programming DMI New FOM
153 UINT8 DmiCdrRelock; ///< Used for programming DMI CDR Relock
154 } CPU_DMI_PREMEM_CONFIG;
155
156 #pragma pack (pop)
157
158 #endif // _CPU_DMI_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
CPU_DMI_PREMEM_CONFIG::DmiGen3ProgramStaticEq
UINT8 DmiGen3ProgramStaticEq
(Test) Program DMI Gen3 EQ Phase1 Static Presets
Definition: CpuDmiPreMemConfig.h:107
CPU_DMI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuDmiPreMemConfig.h:77
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_DMI_PREMEM_CONFIG
The CPU_DMI_CONFIG block describes the expected configuration of the CPU for DMI.
Definition: CpuDmiPreMemConfig.h:76
CPU_DMI_PREMEM_CONFIG::DmiAspmCtrl
UINT8 DmiAspmCtrl
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
Definition: CpuDmiPreMemConfig.h:110
CPU_DMI_PREMEM_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
Definition: CpuDmiPreMemConfig.h:108
DMI_ASPM
DMI_ASPM
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: CpuDmiPreMemConfig.h:49
CPU_DMI_PREMEM_CONFIG::DmiCdrRelock
UINT8 DmiCdrRelock
Used for programming DMI CDR Relock.
Definition: CpuDmiPreMemConfig.h:153
CPU_DMI_PREMEM_CONFIG::DmiAspmL1ExitLatency
UINT8 DmiAspmL1ExitLatency
ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiAspmAutoConfig
Definition: CpuDmiPreMemConfig.h:111
CPU_DMI_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: CpuDmiPreMemConfig.h:62
CPU_DMI_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: CpuDmiPreMemConfig.h:63
CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh2Enable
UINT8 DmiGen3EqPh2Enable
(Test) DMI Equalization Phase 2 Enable Control
Definition: CpuDmiPreMemConfig.h:92
CPU_DMI_PREMEM_CONFIG::DmiNewFom
UINT8 DmiNewFom
Used for programming DMI New FOM.
Definition: CpuDmiPreMemConfig.h:152
CPU_DMI_PREMEM_CONFIG::DmiGen3EqPh3Method
UINT8 DmiGen3EqPh3Method
(Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI
Definition: CpuDmiPreMemConfig.h:101
CPU_DMI_EQ_PARAM
Represent lane specific Dmi Gen3 equalization parameters.
Definition: CpuDmiPreMemConfig.h:61
CPU_DMI_PREMEM_CONFIG::DmiMaxLinkSpeed
UINT8 DmiMaxLinkSpeed
Definition: CpuDmiPreMemConfig.h:85
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuInfo.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
Classes
CpuInfo.h File Reference

Protocol used to report CPU information. More...

#include <CpuDataStruct.h>
#include <CpuLimits.h>
Include dependency graph for CpuInfo.h:

Go to the source code of this file.

Classes

struct | CACHE_DESCRIPTOR_INFO
Cache descriptor information. More...
struct | CPU_INFO
Processor information. More...
struct | SMRAM_CPU_INFO
This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA. More...
struct | SGX_INFO
struct | _CPU_INFO_PROTOCOL
This protocol provides information about the common features available in this CPU. More...

Detailed Description

Protocol used to report CPU information.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuInfo.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuInfo.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
CpuInfo.h
Go to the documentation of this file.
1 /** @file
2 Protocol used to report CPU information
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_INFO_H_
36 #define _CPU_INFO_H_
37
38 #include <CpuDataStruct.h>
39 #include <CpuLimits.h>
40
41 typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL;
42
43
44 extern EFI_GUID gCpuInfoProtocolGuid;
45
46 //
47 // DXE_CPU_INFO_PROTOCOL revisions
48 //
49 #define CPU_INFO_PROTOCOL_REVISION 6
50
51 #define CORE_TYPE_NON_HYBRID 0
52
53 #define SMALL_CORE 0
54 #define BIG_CORE 1
55 #define CORE_TYPE_NUM 2
56
57 //
58 // Processor feature definitions.
59 //
60 #define TXT_SUPPORT BIT0
61 #define VMX_SUPPORT BIT1
62 #define XD_SUPPORT BIT2
63 #define DCA_SUPPORT BIT3
64 #define X2APIC_SUPPORT BIT4
65 #define AES_SUPPORT BIT5
66 #define HT_SUPPORT BIT6
67 #define DEBUG_SUPPORT BIT7
68 #define DEBUG_LOCK_SUPPORT BIT8
69 #define PROC_TRACE_SUPPORT BIT9
70 #define HDC_SUPPORT BIT10
71
72 //
73 // Max number of VF point offset
74 //
75 #ifndef CPU_OC_MAX_VF_POINTS
76 #define CPU_OC_MAX_VF_POINTS 0xF
77 #endif
78
79 #pragma pack(push, 1)
80 ///
81 /// Cache descriptor information
82 ///
83 typedef struct {
84 UINT8 Desc; ///< Cache Descriptor
85 UINT8 Level; ///< Cache Level
86 UINT8 Type; ///< Cache Type. 0: Data, 1: Instruction, 3: Unified
87 UINT32 Size; ///< Cache Size.
88 UINT16 Associativity; ///< Cache Ways of Associativity.
89 } CACHE_DESCRIPTOR_INFO;
90
91 ///
92 /// Processor information
93 ///
94 typedef struct {
95 UINT32 CpuSignature; ///< Processor signature and version information.
96 UINT64 Features; ///< Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
97 CHAR8 *BrandString; ///< Processor Brand String.
98 UINT8 NumSupportedCores; ///< Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
99 UINT8 NumSupportedThreadsPerCore; ///< Number of Supported Threads per Core.
100 UINT8 NumCores; ///< Number of Enabled or Active Cores.
101 UINT8 NumHts; ///< Max Number of Enabled Threads per Core. This will be 1 or 2.
102 UINT32 IntendedFreq; ///< Maximum non turbo ratio or Config TDP ratio in MHz
103 UINT32 ActualFreq; ///< Actual frequency in MHz
104 UINT32 Voltage; ///< Current operating voltage.
105 CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor information.
106 UINT8 MaxCacheSupported; ///< Maximum cache supported.
107 UINT8 SmmbaseSwSmiNumber; ///< Software SMI Number from Smbase. @Note: This is unused.
108 UINT16 NumberOfPStates; ///< Number of P-States.
109 UINT16 NumEnabledThreads; ///< Enabled number of threads.
110 UINT8 CoreVfPointCount; ///< The number of Core VF Point.
111 UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< OC Ratio for each Core VF Point.
112 UINT8 PerCoreRatioOverride; ///< Enable or disable Per Core PState OC supported.
113 UINT8 PerCoreRatio[CPU_MAX_BIG_CORES]; ///< Array used to specific max ratio applied to each selected Core.
114 UINT8 RingVfPointCount; ///< The number of Ring VF Point.
115 UINT8 RingVfPointRatio[CPU_OC_MAX_VF_POINTS]; ///< OC Ratio for Ring VF Point.
116 } CPU_INFO;
117
118 ///
119 /// This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA.
120 ///
121 typedef struct {
122 EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRAM CPU DATA.
123 EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMRAM CPU DATA.
124 UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA.
125 } SMRAM_CPU_INFO;
126
127 ///
128 /// @deprecated due to Non-POR feature
129 /// SGX Information
130 ///
131 typedef struct {
132 UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed back in next boot
133 } SGX_INFO;
134
135 #pragma pack(pop)
136
137 ///
138 /// This protocol provides information about the common features available in this CPU.
139 ///
140 struct _CPU_INFO_PROTOCOL {
141 /**
142 Revision for the protocol structure.
143 Any backwards compatible changes to this protocol will result in an update in the revision number.
144 Major changes will require publication of a new protocol
145
146 <b>Revision 1</b>:
147 - Initial version
148 <b>Revision 2</b>:
149 - Add number of enabled threads to CPU_INFO.
150 <b>Revision 3</b>:
151 - Extend CPU_INFO to support Small Core and Big Core.
152 <b>Revision 4</b>:
153 - Add Per Core PState OC supported
154 New PerCoreRatioOverride and PerCoreRatio
155 <b>Revision 5</b>:
156 - Add Ring VF point support.
157 New RingVfPointCount and Ring per VF Point Ratio.
158 <b>Revision 6</b>:
159 - Deprecated SGx
160 **/
161 UINT8 Revision;
162 /**
163 CPU Supported Feature.
164 - BIT0: If set then processor supports TXT.
165 - BIT1: If set then processor supports virtual mode extensions.
166 - BIT2: If set then processor supports execute disable bit.
167 - BIT3: If set then processor supports DCA.
168 - BIT4: If set then processor supports X2APIC.
169 - BIT5: If set then processor supports Advanced Encryption Standard.
170 - BIT6: If set then processor supports hyperthreading.
171 - BIT7: If set then processor supports debug interface.
172 - BIT8: If set then processor supports debug interface lock.
173 - BIT9: If set then processor supports processor trace.
174 - BIT10: If Set then processor supports supports HDC.
175 **/
176 UINT64 CpuCommonFeatures;
177 CPU_INFO *CpuInfo; ///< Processor Basic Information Contains Big Core and Small Core
178 SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information
179 SGX_INFO *SgxInfo; ///< @deprecated due to Non-POR feature.
180 };
181
182 #endif
_CPU_INFO_PROTOCOL::CpuInfo
CPU_INFO * CpuInfo
Processor Basic Information Contains Big Core and Small Core.
Definition: CpuInfo.h:177
CPU_INFO::BrandString
CHAR8 * BrandString
Processor Brand String.
Definition: CpuInfo.h:97
CPU_INFO::NumEnabledThreads
UINT16 NumEnabledThreads
Enabled number of threads.
Definition: CpuInfo.h:109
SMRAM_CPU_INFO::SmramCpuData
EFI_PHYSICAL_ADDRESS SmramCpuData
Second location (Address) of SMRAM CPU DATA.
Definition: CpuInfo.h:123
CpuDataStruct.h
This file declares various data structures used in CPU reference code.
CPU_INFO::SmmbaseSwSmiNumber
UINT8 SmmbaseSwSmiNumber
Software SMI Number from Smbase. @Note: This is unused.
Definition: CpuInfo.h:107
CPU_INFO::PerCoreRatioOverride
UINT8 PerCoreRatioOverride
Enable or disable Per Core PState OC supported.
Definition: CpuInfo.h:112
CPU_INFO::Features
UINT64 Features
Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
Definition: CpuInfo.h:96
CACHE_DESCRIPTOR_INFO::Level
UINT8 Level
Cache Level.
Definition: CpuInfo.h:85
CPU_INFO::NumSupportedThreadsPerCore
UINT8 NumSupportedThreadsPerCore
Number of Supported Threads per Core.
Definition: CpuInfo.h:99
CACHE_DESCRIPTOR_INFO
Cache descriptor information.
Definition: CpuInfo.h:83
CPU_INFO::IntendedFreq
UINT32 IntendedFreq
Maximum non turbo ratio or Config TDP ratio in MHz.
Definition: CpuInfo.h:102
_CPU_INFO_PROTOCOL::CpuCommonFeatures
UINT64 CpuCommonFeatures
CPU Supported Feature.
Definition: CpuInfo.h:176
CPU_INFO::NumberOfPStates
UINT16 NumberOfPStates
Number of P-States.
Definition: CpuInfo.h:108
CACHE_DESCRIPTOR_INFO::Desc
UINT8 Desc
Cache Descriptor.
Definition: CpuInfo.h:84
SMRAM_CPU_INFO
This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DAT...
Definition: CpuInfo.h:121
SGX_INFO
Definition: CpuInfo.h:131
CpuLimits.h
This file declares CPU limitated definition.
CACHE_DESCRIPTOR_INFO::Associativity
UINT16 Associativity
Cache Ways of Associativity.
Definition: CpuInfo.h:88
CPU_INFO::RingVfPointCount
UINT8 RingVfPointCount
The number of Ring VF Point.
Definition: CpuInfo.h:114
CPU_INFO::MaxCacheSupported
UINT8 MaxCacheSupported
Maximum cache supported.
Definition: CpuInfo.h:106
CPU_INFO::CoreVfPointCount
UINT8 CoreVfPointCount
The number of Core VF Point.
Definition: CpuInfo.h:110
CPU_INFO::ActualFreq
UINT32 ActualFreq
Actual frequency in MHz.
Definition: CpuInfo.h:103
CPU_INFO::NumSupportedCores
UINT8 NumSupportedCores
Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
Definition: CpuInfo.h:98
CPU_INFO::NumCores
UINT8 NumCores
Number of Enabled or Active Cores.
Definition: CpuInfo.h:100
SMRAM_CPU_INFO::LockBoxSize
UINT64 LockBoxSize
Size of SMRAM CPU DATA.
Definition: CpuInfo.h:124
CPU_INFO::CpuSignature
UINT32 CpuSignature
Processor signature and version information.
Definition: CpuInfo.h:95
CPU_INFO::Voltage
UINT32 Voltage
Current operating voltage.
Definition: CpuInfo.h:104
CPU_INFO::NumHts
UINT8 NumHts
Max Number of Enabled Threads per Core. This will be 1 or 2.
Definition: CpuInfo.h:101
CPU_INFO
Processor information.
Definition: CpuInfo.h:94
_CPU_INFO_PROTOCOL::SgxInfo
SGX_INFO * SgxInfo
Definition: CpuInfo.h:179
CACHE_DESCRIPTOR_INFO::Size
UINT32 Size
Cache Size.
Definition: CpuInfo.h:87
SGX_INFO::SgxSinitNvsData
UINT64 SgxSinitNvsData
Sinit SE SVN Version saved and passed back in next boot.
Definition: CpuInfo.h:132
SMRAM_CPU_INFO::LockBoxData
EFI_PHYSICAL_ADDRESS LockBoxData
First location (address) of SMRAM CPU DATA.
Definition: CpuInfo.h:122
CACHE_DESCRIPTOR_INFO::Type
UINT8 Type
Cache Type. 0: Data, 1: Instruction, 3: Unified.
Definition: CpuInfo.h:86
_CPU_INFO_PROTOCOL::Revision
UINT8 Revision
Revision for the protocol structure.
Definition: CpuInfo.h:161
_CPU_INFO_PROTOCOL
This protocol provides information about the common features available in this CPU.
Definition: CpuInfo.h:140
CPU_INFO::CacheInfo
CACHE_DESCRIPTOR_INFO * CacheInfo
Cache descriptor information.
Definition: CpuInfo.h:105
_CPU_INFO_PROTOCOL::SmramCpuInfo
SMRAM_CPU_INFO * SmramCpuInfo
SMRAM CPU Information.
Definition: CpuInfo.h:178
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuLimits.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
CpuLimits.h File Reference

This file declares CPU limitated definition. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

This file declares CPU limitated definition.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuLimits.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuLimits.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
CpuLimits.h
Go to the documentation of this file.
1 /** @file
2 This file declares CPU limitated definition.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_LIMITS_H_
37 #define _CPU_LIMITS_H_
38
39 //
40 // Max number of Big Cores
41 //
42 #define CPU_MAX_BIG_CORES 8
43
44 //
45 // Max number of Atom Cores
46 //
47 #define CPU_MAX_ATOM_CORES 16
48
49 //
50 // Max number of Atom Clusters
51 //
52 #define CPU_MAX_ATOM_CLUSTERS 4
53
54 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuMailboxLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Classes | Macros | Typedefs | Functions
CpuMailboxLib.h File Reference

Header file for Cpu Mailbox Lib. More...

Go to the source code of this file.

Classes

union | _OC_MAILBOX_INTERFACE
Expanded Overclocking Mailbox interface defintion, contains command id/completion code, input parameters and the run/busy bit. More...
struct | _OC_MAILBOX_FULL
Consolidated OC mailbox command structure containing both data and interface information. More...
union | _PCODE_MAILBOX_INTERFACE
Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit. More...
struct | _PCODE_MAILBOX_FULL
Consolidated Pcode mailbox command structure containing both data and interface information. More...

Macros

#define | V_MAILBOX_INF_DFX_PWROFF_REQ_DIS 0
INF_DFX will keep up.
#define | V_MAILBOX_INF_DFX_PWROFF_REQ_EN 1
INF_DFX will shutdown.
#define | MAILBOX_WAIT_TIMEOUT 1000
1 millisecond
#define | MAILBOX_WAIT_STALL 1
1 microsecond
#define | MAILBOX_READ_TIMEOUT 10
10 microseconds

Typedefs

typedef union _OC_MAILBOX_INTERFACE | OC_MAILBOX_INTERFACE
Expanded Overclocking Mailbox interface defintion, contains command id/completion code, input parameters and the run/busy bit.
typedef struct _OC_MAILBOX_FULL | OC_MAILBOX_FULL
Consolidated OC mailbox command structure containing both data and interface information.
typedef union _PCODE_MAILBOX_INTERFACE | PCODE_MAILBOX_INTERFACE
Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit.
typedef struct _PCODE_MAILBOX_FULL | PCODE_MAILBOX_FULL
Consolidated Pcode mailbox command structure containing both data and interface information.

Functions

EFI_STATUS | MailboxWrite (IN UINT32 MailboxType, IN UINT32 MailboxCommand, IN UINT32 MailboxData, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox write commands. More...
EFI_STATUS | MailboxRead (IN UINT32 MailboxType, IN UINT32 MailboxCommand, OUT UINT32 *MailboxDataPtr, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox read commands. More...
EFI_STATUS | PollMailboxReady (IN UINT32 MailboxType)
Poll the run/busy bit of the mailbox until available or timeout expires. More...

Detailed Description

Header file for Cpu Mailbox Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuMailboxLib.h.

Function Documentation

◆ MailboxRead()

EFI_STATUS MailboxRead | ( | IN UINT32 | MailboxType,
 |  | IN UINT32 | MailboxCommand,
 |  | OUT UINT32 * | MailboxDataPtr,
 |  | OUT UINT32 * | MailboxStatus
 | ) |  |

Generic Mailbox function for mailbox read commands.

This function will write the read request from MailboxType, and populate the read results in the MailboxDataPtr.

Parameters
[in] | MailboxType | The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
[in] | MailboxCommand | Overclocking mailbox command data
[out] | *MailboxDataPtr | Pointer to the overclocking mailbox interface data
[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status are
  • SUCCESS (0) Command succeeded.
  • OC_LOCKED (1) Overclocking is locked. Service is read-only.
  • INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
  • MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
  • MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
  • OC_NOT_SUPPORTED (5) Domain does not support overclocking.
Return values
EFI_STATUS
  • EFI_SUCCESS Command succeeded.
  • EFI_INVALID_PARAMETER Invalid read data detected from pcode.
  • EFI_UNSUPPORTED Unsupported MailboxType parameter.

◆ MailboxWrite()

EFI_STATUS MailboxWrite | ( | IN UINT32 | MailboxType,
 |  | IN UINT32 | MailboxCommand,
 |  | IN UINT32 | MailboxData,
 |  | OUT UINT32 * | MailboxStatus
 | ) |  |

Generic Mailbox function for mailbox write commands.

This function will poll the mailbox interface for control, issue the write request, poll for completion, and verify the write was succussful.

Parameters
[in] | MailboxType | The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
[in] | MailboxCommand | Overclocking mailbox command data
[in] | MailboxData | Overclocking mailbox interface data
[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status values are:
  • SUCCESS (0) Command succeeded.
  • OC_LOCKED (1) Overclocking is locked. Service is read-only.
  • INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
  • MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
  • MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
  • OC_NOT_SUPPORTED (5) Domain does not support overclocking.
Return values
EFI_STATUS
  • EFI_SUCCESS Command succeeded.
  • EFI_INVALID_PARAMETER Invalid read data detected from pcode.
  • EFI_UNSUPPORTED Unsupported MailboxType parameter.

◆ PollMailboxReady()

EFI_STATUS PollMailboxReady ( IN UINT32 MailboxType )

Poll the run/busy bit of the mailbox until available or timeout expires.

Parameters
[in] MailboxType
Return values
EFI_STATUS
  • EFI_SUCCESS Command succeeded.
  • EFI_TIMEOUT Command timeout.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuMailboxLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
CpuMailboxLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Cpu Mailbox Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_MAILBOX_LIB_H_
37 #define _CPU_MAILBOX_LIB_H_
38
39 //
40 // Mailbox Related Definitions
41 //
42 #define MAILBOX_TYPE_PCODE 0x00000001
43 #define MAILBOX_TYPE_OC 0x00000002
44 #define MAILBOX_TYPE_VR_MSR 0x00000003
45 #define PCODE_MAILBOX_INTERFACE_OFFSET 0x5DA4
46 #define PCODE_MAILBOX_DATA_OFFSET 0x5DA0
47 #define PCU_CR_BCLK_FREQ_MCHBAR 0x00005F60
48 #define OC_MAILBOX_MSR 0x00000150
49 #define VR_MAILBOX_MSR_INTERFACE 0x00000607
50 #define VR_MAILBOX_MSR_DATA 0x00000608
51
52 #define MAILBOX_PCODE_CMD_READ_PEG_CRIO_CR 0x00000029
53 #define MAILBOX_PCODE_CMD_WRITE_PEG_CRIO_CR 0x0000002A
54 #define N_MAILBOX_TARGET_IO_BLOCK_OFFSET 0x18
55
56 #define MAILBOX_PCODE_CMD_READ_C6DRAM_CONFIG 0x0000001C
57 #define B_MAILBOX_BIOS_ALLOW_C6DRAM BIT0
58 #define B_MAILBOX_C6DRAM_SUPPORTED BIT1
59 #define MAILBOX_PCODE_CMD_WRITE_C6DRAM_CONFIG 0x0000001D
60 #define MAILBOX_OC_CMD_BCLK_FREQUENCY_CMD 0x00000005
61
62 #define MAILBOX_PCODE_CMD_BCLK_CONFIG 0x0000003F
63 #define MAILBOX_PCODE_BCLK_CONFIG_SET_SSC_CONTROL_SUBCOMMAND 0x00000004
64 #define MAILBOX_PCODE_BCLK_CONFIG_GET_SSC_CONTROL_SUBCOMMAND 0x00000003
65
66 //
67 // Inform Graphics Memory Config
68 //
69 #define BIOS_MAILBOX_INFORM_GRAPHICS_MEMORY_CONFIG 0x55
70 #define SELECT_ALTERNATE_DID2 0x0
71
72 //
73 // HwP Misc Functions
74 //
75 #define MAILBOX_PCODE_CMD_READ_AUTONOMOUS_PARAMS 0x00000010
76 #define MAILBOX_PCODE_CMD_WRITE_AUTONOMOUS_PARAMS 0x00000011
77 #define MAILBOX_PCODE_CMD_READ_PCU_MISC_CONFIG 0x00000005
78 #define MAILBOX_PCODE_CMD_WRITE_PCU_MISC_CONFIG 0x00000006
79 #define MAILBOX_OC_CMD_READ_PER_CORE_RATIO_LIMITS_CMD 0x0000001C
80 #define MAILBOX_OC_CMD_WRITE_PER_CORE_RATIO_LIMITS_CMD 0x0000001D
81
82 //
83 // MAILBOX_BIOS_CMD_MISC_ALG_CONFIG_INTERFACE command set
84 //
85 #define MAILBOX_PCODE_CMD_MISC_ALG_CONFIG_INTERFACE 0x2B
86 #define MAILBOX_PCODE_SUBCMD_READ_HDC_DIS_WHEN_OSREQ_ABOVE_PE_SUBCOMMAND 0x00
87 #define MAILBOX_PCODE_SUBCMD_WRITE_HDC_DIS_WHEN_OSREQ_ABOVE_PE_SUBCOMMAND 0x01
88 #define MAILBOX_PCODE_SUBCMD_READ_EPB_PECI_CONTROL_SUBCOMMAND 0x02
89 #define MAILBOX_PCODE_SUBCMD_WRITE_EPB_PECI_CONTROL_SUBCOMMAND 0x03
90 #define MAILBOX_PCODE_SUBCMD_READ_RING_DISTRESS_DISABLE_SUBCOMMAND 0x04
91 #define MAILBOX_PCODE_SUBCMD_WRITE_RING_DISTRESS_DISABLE_SUBCOMMAND 0x05
92 #define MAILBOX_PCODE_SUBCMD_READ_RING_AUTOGV_DISABLE_SUBCOMMAND 0x08
93 #define MAILBOX_PCODE_SUBCMD_WRITE_RING_AUTOGV_DISABLE_SUBCOMMAND 0x09
94
95 #define MAILBOX_BIOS_CMD_WRITE_HSPHY_CONFIG 0x0000002D
96 #define B_MAILBOX_BIOS_ALLOW_HSPHY_1 BIT0
97
98 //
99 // MAILBOX_BIOS_POWER_RAIL_SHUTDOWN_POLICY
100 //
101 #define MAILBOX_PCODE_CMD_BIOS_WRITE_POWER_RAIL_SHUTDOWN_POLICY 0x42
102 #define B_MAILBOX_INF_DFX_PWROFF_REQ BIT0
103 #define V_MAILBOX_INF_DFX_PWROFF_REQ_DIS 0 ///< INF_DFX will keep up
104 #define V_MAILBOX_INF_DFX_PWROFF_REQ_EN 1 ///< INF_DFX will shutdown
105 #define MAILBOX_PCODE_CMD_BIOS_READ_POWER_RAIL_SHUTDOWN_POLICY 0x43
106
107 #ifndef MAILBOX_WAIT_TIMEOUT
108 #define MAILBOX_WAIT_TIMEOUT 1000 ///< 1 millisecond
109 #endif
110 #ifndef MAILBOX_WAIT_STALL
111 #define MAILBOX_WAIT_STALL 1 ///< 1 microsecond
112 #endif
113 #ifndef MAILBOX_READ_TIMEOUT
114 #define MAILBOX_READ_TIMEOUT 10 ///< 10 microseconds
115 #endif
116
117
118
119 //
120 // Pcode Mailbox completion codes
121 //
122 #define PCODE_MAILBOX_CC_SUCCESS 0x0
123 #define PCODE_MAILBOX_CC_ILLEGAL_CMD 0x1
124 #define PCODE_MAILBOX_CC_TIMEOUT 0x2
125 #define PCODE_MAILBOX_CC_ILLEGAL_DATA 0x3
126 #define PCODE_MAILBOX_CC_EDRAM_NOT_FUNCTIONAL 0x4
127 #define PCODE_MAILBOX_CC_ILLEGAL_VR_ID 0x5
128 #define PCODE_MAILBOX_CC_LOCKED 0x6
129 #define PCODE_MAILBOX_CC_VR_ERROR 0x7
130 #define PCODE_MAILBOX_CC_ILLEGAL_SUBCOMMAND 0x8
131 #define PCODE_MAILBOX_CC_EDRAM_CURRENTLY_UNAVAILABLE 0xA
132
133 #define MAILBOX_PARAM_1_OFFSET 8
134 #define MAILBOX_PARAM_2_OFFSET 16
135
136 ///
137 /// Expanded Overclocking Mailbox interface defintion, contains command id/completion code,
138 /// input parameters and the run/busy bit
139 ///
140 typedef union _OC_MAILBOX_INTERFACE {
141 UINT32 InterfaceData; ///< All bit fields as a 32-bit value.
142 ///
143 /// Individual bit fields.
144 ///
145 struct {
146 UINT8 CommandCompletion : 8; ///< Command ID and completion code
147 UINT8 Param1 : 8; ///< Parameter 1, generally used to specify the CPU Domain ID
148 UINT8 Param2 : 8; ///< Parameter 2, only current usage is as a core index for ratio limits message
149 UINT8 Reserved : 7; ///< Reserved for future use
150 UINT8 RunBusy : 1; ///< Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
151 } Fields;
152 } OC_MAILBOX_INTERFACE;
153
154 ///
155 /// Consolidated OC mailbox command structure containing both data and interface information
156 ///
157 typedef struct _OC_MAILBOX_FULL {
158 UINT32 Data; ///< OC Mailbox read/write data
159 OC_MAILBOX_INTERFACE Interface; ///< OC mailbox interface
160 } OC_MAILBOX_FULL;
161
162 ///
163 /// Expanded Pcode Mailbox interface defintion, contains command id, param1, param2,
164 /// and the run/busy bit
165 ///
166 typedef union _PCODE_MAILBOX_INTERFACE {
167 UINT32 InterfaceData; ///< All bit fields as a 32-bit value.
168 ///
169 /// Individual bit fields.
170 ///
171 struct {
172 UINT32 Command : 8; ///< Pcode mailbox command
173 UINT32 Param1 : 8; ///< This field contains parameter 1, used by sub-commands.
174 UINT32 Param2 : 13; ///< This field contains parameter 2.
175 UINT32 Reserved : 2; ///< Reserved for future use
176 UINT32 RunBusy : 1; ///< Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this bit after the message is consumed.
177 } Fields;
178 } PCODE_MAILBOX_INTERFACE;
179
180 ///
181 /// Consolidated Pcode mailbox command structure containing both data and interface information
182 ///
183 typedef struct _PCODE_MAILBOX_FULL {
184 PCODE_MAILBOX_INTERFACE Interface; ///< Pcode mailbox interface
185 UINT32 Data; ///< Pcode mailbox read/write data
186 } PCODE_MAILBOX_FULL;
187
188 /**
189 Generic Mailbox function for mailbox write commands. This function will
190 poll the mailbox interface for control, issue the write request, poll
191 for completion, and verify the write was succussful.
192
193 @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
194 @param[in] MailboxCommand Overclocking mailbox command data
195 @param[in] MailboxData Overclocking mailbox interface data
196 @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status values are:
197 - SUCCESS (0) Command succeeded.
198 - OC_LOCKED (1) Overclocking is locked. Service is read-only.
199 - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
200 - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
201 - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
202 - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
203
204 @retval EFI_STATUS
205 - EFI_SUCCESS Command succeeded.
206 - EFI_INVALID_PARAMETER Invalid read data detected from pcode.
207 - EFI_UNSUPPORTED Unsupported MailboxType parameter.
208 **/
209 EFI_STATUS
210 EFIAPI
211 MailboxWrite (
212 IN UINT32 MailboxType,
213 IN UINT32 MailboxCommand,
214 IN UINT32 MailboxData,
215 OUT UINT32 *MailboxStatus
216 );
217
218 /**
219 Generic Mailbox function for mailbox read commands. This function will write
220 the read request from MailboxType, and populate the read results in the MailboxDataPtr.
221
222 @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
223 @param[in] MailboxCommand Overclocking mailbox command data
224 @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interface data
225 @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status are
226 - SUCCESS (0) Command succeeded.
227 - OC_LOCKED (1) Overclocking is locked. Service is read-only.
228 - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
229 - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
230 - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
231 - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
232
233 @retval EFI_STATUS
234 - EFI_SUCCESS Command succeeded.
235 - EFI_INVALID_PARAMETER Invalid read data detected from pcode.
236 - EFI_UNSUPPORTED Unsupported MailboxType parameter.
237
238 **/
239 EFI_STATUS
240 EFIAPI
241 MailboxRead (
242 IN UINT32 MailboxType,
243 IN UINT32 MailboxCommand,
244 OUT UINT32 *MailboxDataPtr,
245 OUT UINT32 *MailboxStatus
246 );
247
248 /**
249 Poll the run/busy bit of the mailbox until available or timeout expires.
250
251 @param[in] MailboxType
252
253 @retval EFI_STATUS
254 - EFI_SUCCESS Command succeeded.
255 - EFI_TIMEOUT Command timeout.
256 **/
257 EFI_STATUS
258 EFIAPI
259 PollMailboxReady (
260 IN UINT32 MailboxType
261 );
262 #endif
MailboxRead
EFI_STATUS MailboxRead(IN UINT32 MailboxType, IN UINT32 MailboxCommand, OUT UINT32 *MailboxDataPtr, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox read commands.
_PCODE_MAILBOX_INTERFACE
Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit...
Definition: CpuMailboxLib.h:166
_OC_MAILBOX_INTERFACE::RunBusy
UINT8 RunBusy
Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this ...
Definition: CpuMailboxLib.h:150
OC_MAILBOX_INTERFACE
union _OC_MAILBOX_INTERFACE OC_MAILBOX_INTERFACE
Expanded Overclocking Mailbox interface defintion, contains command id/completion code,...
_OC_MAILBOX_INTERFACE
Expanded Overclocking Mailbox interface defintion, contains command id/completion code,...
Definition: CpuMailboxLib.h:140
_PCODE_MAILBOX_INTERFACE::Command
UINT32 Command
Pcode mailbox command.
Definition: CpuMailboxLib.h:172
_PCODE_MAILBOX_FULL
Consolidated Pcode mailbox command structure containing both data and interface information.
Definition: CpuMailboxLib.h:183
PCODE_MAILBOX_INTERFACE
union _PCODE_MAILBOX_INTERFACE PCODE_MAILBOX_INTERFACE
Expanded Pcode Mailbox interface defintion, contains command id, param1, param2, and the run/busy bit...
PCODE_MAILBOX_FULL
struct _PCODE_MAILBOX_FULL PCODE_MAILBOX_FULL
Consolidated Pcode mailbox command structure containing both data and interface information.
_PCODE_MAILBOX_FULL::Interface
PCODE_MAILBOX_INTERFACE Interface
Pcode mailbox interface.
Definition: CpuMailboxLib.h:184
_OC_MAILBOX_FULL
Consolidated OC mailbox command structure containing both data and interface information.
Definition: CpuMailboxLib.h:157
_OC_MAILBOX_INTERFACE::Param2
UINT8 Param2
Parameter 2, only current usage is as a core index for ratio limits message.
Definition: CpuMailboxLib.h:148
_PCODE_MAILBOX_INTERFACE::Reserved
UINT32 Reserved
Reserved for future use.
Definition: CpuMailboxLib.h:175
_OC_MAILBOX_INTERFACE::InterfaceData
UINT32 InterfaceData
All bit fields as a 32-bit value.
Definition: CpuMailboxLib.h:141
_OC_MAILBOX_INTERFACE::Fields
struct _OC_MAILBOX_INTERFACE::@0 Fields
Individual bit fields.
_OC_MAILBOX_INTERFACE::CommandCompletion
UINT8 CommandCompletion
Command ID and completion code.
Definition: CpuMailboxLib.h:146
_PCODE_MAILBOX_FULL::Data
UINT32 Data
Pcode mailbox read/write data.
Definition: CpuMailboxLib.h:185
PollMailboxReady
EFI_STATUS PollMailboxReady(IN UINT32 MailboxType)
Poll the run/busy bit of the mailbox until available or timeout expires.
_OC_MAILBOX_INTERFACE::Reserved
UINT8 Reserved
Reserved for future use.
Definition: CpuMailboxLib.h:149
_OC_MAILBOX_FULL::Data
UINT32 Data
OC Mailbox read/write data.
Definition: CpuMailboxLib.h:158
_PCODE_MAILBOX_INTERFACE::InterfaceData
UINT32 InterfaceData
All bit fields as a 32-bit value.
Definition: CpuMailboxLib.h:167
_PCODE_MAILBOX_INTERFACE::Fields
struct _PCODE_MAILBOX_INTERFACE::@1 Fields
Individual bit fields.
_OC_MAILBOX_INTERFACE::Param1
UINT8 Param1
Parameter 1, generally used to specify the CPU Domain ID.
Definition: CpuMailboxLib.h:147
_PCODE_MAILBOX_INTERFACE::Param2
UINT32 Param2
This field contains parameter 2.
Definition: CpuMailboxLib.h:174
_PCODE_MAILBOX_INTERFACE::Param1
UINT32 Param1
This field contains parameter 1, used by sub-commands.
Definition: CpuMailboxLib.h:173
_PCODE_MAILBOX_INTERFACE::RunBusy
UINT32 RunBusy
Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is ready. pcode will clear this ...
Definition: CpuMailboxLib.h:176
OC_MAILBOX_FULL
struct _OC_MAILBOX_FULL OC_MAILBOX_FULL
Consolidated OC mailbox command structure containing both data and interface information.
_OC_MAILBOX_FULL::Interface
OC_MAILBOX_INTERFACE Interface
OC mailbox interface.
Definition: CpuMailboxLib.h:159
MailboxWrite
EFI_STATUS MailboxWrite(IN UINT32 MailboxType, IN UINT32 MailboxCommand, IN UINT32 MailboxData, OUT UINT32 *MailboxStatus)
Generic Mailbox function for mailbox write commands.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4
Classes | Macros | Enumerations
CpuPcieConfig.h File Reference

Pcie root port policy. More...

#include <Library/GpioLib.h>
#include <Library/CpuPcieInfoFruLib.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for CpuPcieConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCIE_PEI_PREMEM_CONFIG
PCI Express and DMI controller configuration
. More...
struct | CPU_PCIE_RP_PREMEM_CONFIG
CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: - Initial version. More...
struct | CPU_PCIE_EQ_LANE_PARAM
Represent lane specific PCIe Gen3 equalization parameters. More...
struct | CPU_PCIE_ROOT_PORT_CONFIG
The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port. More...
struct | CPU_PCIE_CONFIG
The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Revision 1< / b>: -Initial version. More...

Macros

#define CPU_PCIE_CONFIG_REVISION 10
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...

Enumerations

enum | CPU_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.
enum | CPU_PCIE_L1SUBSTATES_CONTROL
Refer to SA EDS for the SA implementation values corresponding to below PCI-E spec defined ranges.
enum | CPU_PCIE_EQ_METHOD

Detailed Description

Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPcieConfig.h.

Macro Definition Documentation

◆ CPU_PCIE_CONFIG_REVISION

#define CPU_PCIE_CONFIG_REVISION 10

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 2: - Add Gen3TxOverride and Gen4TxOverride Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable Revision 4: - Add FOMS Control Policy Setup Variable Revision 5: - Add Gen3HwEqOverride and Gen4HwEqOverride Revision 6: - Align revision with CPU_PCIE_CONFIG_REVISION value Revision 7:

  • Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection Revision 8 :
    • Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
    • Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG Revision 10: - Add Port0 Link Disable Setup Variable to CPU_PCIE_ROOT_PORT_CONFIG2

Definition at line 70 of file CpuPcieConfig.h.

Enumeration Type Documentation

◆ CPU_PCIE_EQ_METHOD

enum CPU_PCIE_EQ_METHOD
Enumerator
CpuPcieEqDefault
Deprecated:
since revision 3. Behaves as PchPcieEqHardware.
CpuPcieEqHardware

Hardware equalization.

CpuPcieEqStaticCoeff

Fixed equalization (requires Coefficient settings per lane)

Definition at line 278 of file CpuPcieConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4
CpuPcieConfig.h
Go to the documentation of this file.
1 /** @file
2 Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_PCIE_CONFIG_H_
37 #define _CPU_PCIE_CONFIG_H_
38
39 #include <Library/GpioLib.h>
40 #include <Library/CpuPcieInfoFruLib.h>
41 #include <PcieConfig.h>
42 #include <ConfigBlock.h>
43 #include <Register/SaRegsHostBridge.h>
44
45 #pragma pack(push, 1)
46
47 #define PCIE_PEI_PREMEM_CONFIG_REVISION 1
48 #define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 5
49
50 /**
51 Making any setup structure change after code frozen
52 will need to maintain backward compatibility, bump up
53 structure revision and update below history table\n
54 <b>Revision 1</b>: - Initial version.
55 <b>Revision 2</b>: - Add Gen3TxOverride and Gen4TxOverride
56 <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
57 <b>Revision 4</b>: - Add FOMS Control Policy Setup Variable
58 <b>Revision 5</b>: - Add Gen3HwEqOverride and Gen4HwEqOverride
59 <b>Revision 6</b>: - Align revision with CPU_PCIE_CONFIG_REVISION value
60 <b>Revision 7</b>:
61 - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
62 <b>Revision 8 </b>:
63 - Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
64 - Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
65 - Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
66 - Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
67 <b>Revision 10</b>: - Add Port0 Link Disable Setup Variable to CPU_PCIE_ROOT_PORT_CONFIG2
68 **/
69
70 #define CPU_PCIE_CONFIG_REVISION 10
71
72 #define L0_SET BIT0
73 #define L1_SET BIT1
74
75
76
77
78 /**
79 PCI Express and DMI controller configuration\n
80 @note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
81 <b>Revision 1</b>:
82 - Initial version.
83 **/
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
86 /**
87 Offset 28:0 :
88 <b>(Test)</b> DMI Link Speed Control
89 - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
90 - Gen1 (0x1) : Limit Link to Gen1 Speed
91 - Gen2 (0x2) : Limit Link to Gen2 Speed
92 - Gen3 (0x3) : Limit Link to Gen3 Speed
93 **/
94 UINT32 DmiMaxLinkSpeed : 2;
95 /**
96 Offset 28:2 :
97 <b>(Test)</b> DMI Equalization Phase 2 Enable Control
98 - Disabled (0x0) : Disable phase 2
99 - Enabled (0x1) : Enable phase 2
100 - <b>Auto</b> (0x2) : Use the current default method (Default)
101 **/
102 UINT32 DmiGen3EqPh2Enable : 2;
103 /**
104 Offset 28:4 :
105 <b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
106 - <b>Auto</b> (0x0) : Use the current default method (Default)
107 - HwEq (0x1) : Use Adaptive Hardware Equalization
108 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
109 - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
110 - Disabled (0x4) : Bypass Equalization Phase 3
111 **/
112 UINT32 DmiGen3EqPh3Method : 3;
113 /**
114 Offset 28:7 :
115 <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
116 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
117 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
118 **/
119 UINT32 DmiGen3ProgramStaticEq : 1;
120 UINT32 RsvdBits0 : 24; ///< Offset 28:8 :Reserved for future use
121
122 /**
123 Offset 32:0 :
124 Select when PCIe ASPM programming will happen in relation to the Oprom
125 - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
126 - After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.
127 **/
128 UINT32 InitPcieAspmAfterOprom : 1;
129 UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved for future use
130
131 UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///< Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
132 UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///< Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
133 UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///< Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
134 /**
135 Offset 48/60 :
136 DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
137 has to be specified based upon platform design and must follow the guideline. Default is 12.
138 **/
139
140 UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];
141
142 UINT8 DmiDeEmphasis; ///< Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
143 UINT8 Rsvd0[3]; ///< Offset 65
144 } PCIE_PEI_PREMEM_CONFIG;
145
146
147 /**
148 CPU PCIe Root Port Pre-Memory Configuration
149 Contains Root Port settings and capabilities
150 <b>Revision 1</b>: - Initial version.
151 <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
152 <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
153 <b>Revision 4</b>: - Adding New FOM Setup Variable
154 <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
155 **/
156 typedef struct {
157 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
158 /**
159 Root Port enabling mask.
160 Bit0 presents RP1, Bit1 presents RP2, and so on.
161 0: Disable; <b>1: Enable</b>.
162 **/
163 UINT32 RpEnabledMask;
164 /**
165 Assertion on Link Down GPIOs
166 - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
167 - Enabled (0x1) : Enable assertion on Link Down GPIOs
168 **/
169 UINT8 LinkDownGpios;
170 /**
171 Enable ClockReq Messaging
172 - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
173 - Enabled (0x1) : Enable ClockReq Messaging
174 **/
175 UINT8 ClkReqMsgEnable;
176 /**
177 Dekel Recipe Workaround
178 <b>2</b>
179 1=Minimal, 9=Maximum,
180 **/
181 UINT8 DekelSquelchWa; // Deprecated variable
182 UINT8 Rsvd0[1];
183 /**
184 Determines each PCIE Port speed capability.
185 <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
186 **/
187 UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
188
189 /**
190 Enable ClockReq Messaging Policy is for all Rootports
191 - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
192 - Enabled (0x1) : Enable ClockReq Messaging
193 **/
194 UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
195 /**
196 To Enable/Disable New FOM
197 <b>0: Disable</b>; 1: Enable
198 **/
199 UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
200 /**
201 To Enable/Disable CDR Relock
202 <b>0: Disable</b>; 1: Enable
203 **/
204 UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
205 } CPU_PCIE_RP_PREMEM_CONFIG;
206
207 typedef enum {
208 CpuPcieOverrideDisabled = 0,
209 CpuPcieL1L2Override = 0x01,
210 CpuPcieL1SubstatesOverride = 0x02,
211 CpuPcieL1L2AndL1SubstatesOverride = 0x03,
212 CpuPcieLtrOverride = 0x04
213 } CPU_PCIE_OVERRIDE_CONFIG;
214
215 enum CPU_PCIE_SPEED {
216 CpuPcieAuto,
217 CpuPcieGen1,
218 CpuPcieGen2,
219 CpuPcieGen3,
220 CpuPcieGen4,
221 CpuPcieGen5
222 };
223
224 ///
225 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
226 ///
227 typedef enum {
228 CpuPcieAspmDisabled,
229 CpuPcieAspmL0s,
230 CpuPcieAspmL1,
231 CpuPcieAspmL0sL1,
232 CpuPcieAspmAutoConfig,
233 CpuPcieAspmMax
234 } CPU_PCIE_ASPM_CONTROL;
235
236 /**
237 Refer to SA EDS for the SA implementation values corresponding
238 to below PCI-E spec defined ranges
239 **/
240 typedef enum {
241 CpuPcieL1SubstatesDisabled,
242 CpuPcieL1SubstatesL1_1,
243 CpuPcieL1SubstatesL1_1_2,
244 CpuPcieL1SubstatesMax
245 } CPU_PCIE_L1SUBSTATES_CONTROL;
246
247 enum CPU_PCIE_MAX_PAYLOAD {
248 CpuPcieMaxPayload128 = 0,
249 CpuPcieMaxPayload256,
250 CpuPcieMaxPayload512,
251 CpuPcieMaxPayloadMax
252 };
253
254 enum CPU_PCIE_COMPLETION_TIMEOUT {
255 CpuPcieCompletionTO_Default,
256 CpuPcieCompletionTO_50_100us,
257 CpuPcieCompletionTO_1_10ms,
258 CpuPcieCompletionTO_16_55ms,
259 CpuPcieCompletionTO_65_210ms,
260 CpuPcieCompletionTO_260_900ms,
261 CpuPcieCompletionTO_1_3P5s,
262 CpuPcieCompletionTO_4_13s,
263 CpuPcieCompletionTO_17_64s,
264 CpuPcieCompletionTO_Disabled
265 };
266
267
268 enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION {
269 CpuPcieGen3PresetSelection,
270 CpuPcieGen3CoefficientSelection
271 };
272
273 enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION {
274 CpuPcieGen4PresetSelection,
275 CpuPcieGen4CoefficientSelection
276 };
277
278 typedef enum {
279 CpuPcieEqDefault = 0, ///< @deprecated since revision 3. Behaves as PchPcieEqHardware.
280 CpuPcieEqHardware = 1, ///< Hardware equalization
281 CpuPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
282 } CPU_PCIE_EQ_METHOD;
283
284
285 /**
286 Represent lane specific PCIe Gen3 equalization parameters.
287 **/
288 typedef struct {
289 UINT8 Cm; ///< Coefficient C-1
290 UINT8 Cp; ///< Coefficient C+1
291 UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
292 UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
293 UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
294 UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
295 UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
296 UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
297 } CPU_PCIE_EQ_LANE_PARAM;
298
299 /**
300 The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
301 **/
302 typedef struct {
303
304 UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
305 UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
306 UINT32 RsvdBits0 : 30; ///< Reserved bits
307 /**
308 PCIe Gen4 Equalization Method
309 - HwEq (0x1) : Hardware Equalization (Default)
310 - StaticEq (0x2) : Static Equalization
311 **/
312 UINT8 Gen4EqPh3Method;
313 UINT8 FomsCp; ///< FOM Score Board Control Policy
314 UINT8 RsvdBytes0[2]; ///< Reserved bytes
315
316 //
317 // Gen3 Equalization settings
318 //
319 UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
320 UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
321 //
322 // Gen4 Equalization settings
323 //
324 UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
325 UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
326 //
327 // Gen5 Equalization settings
328 //
329 UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
330 UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
331 UINT32 RsvdBits1 : 8; ///< Reserved Bits
332
333 PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
334
335 } CPU_PCIE_ROOT_PORT_CONFIG;
336
337 typedef struct {
338 UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
339 UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
340 UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
341 UINT8 Func0LinkDisable; ///< Disable Func0 Port
342 } CPU_PCIE_ROOT_PORT_CONFIG2;
343
344 /**
345 The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
346 <b>Revision 1< / b>:
347 -Initial version.
348 <b>Revision 2</b>:
349 - SlotSelection policy added
350 <b>Revision 3</b>
351 - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
352 <b>Revision 4</b>:
353 - Deprecating SetSecuredRegisterLock
354 <b>Revision 5</b>:
355 - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
356 - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
357 - Deprecate VcEnabled policy
358 <b>Revision 7</b>:
359 - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
360 <b>Revision 8</b>:
361 - Added Serl policy
362 <b>Revision 9</b>:
363 - Align revision with CPU_PCIE_CONFIG_REVISION value
364 <b>Revision 10</b>:
365 - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
366 **/
367 typedef struct {
368 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
369 ///
370 /// These members describe the configuration of each SA PCIe root port.
371 ///
372 CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
373 ///
374 /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
375 /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
376 ///
377 CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
378 ///
379 /// List of coefficients used during equalization (applicable to both software and hardware EQ)
380 ///
381 PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
382
383 PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
384
385 UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
386 // Deprecated Policy
387 /**
388 <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
389 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
390 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
391 **/
392 UINT32 PegGen3ProgramStaticEq : 1;
393
394 // Deprecated Policy
395 /**
396 <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
397 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
398 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
399 **/
400 UINT32 PegGen4ProgramStaticEq : 1;
401 /**
402 <b>(Test)</b> Cpu Pcie Secure Register Lock
403 - Disabled (0x0)
404 - <b>Enabled</b> (0x1)
405 **/
406 UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
407 ///
408 /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
409 ///
410 UINT32 SlotSelection : 1;
411
412 UINT32 Serl : 1;
413
414 UINT32 RsvdBits0 : 26;
415
416 /**
417 PCIe device override table
418 The PCIe device table is being used to override PCIe device ASPM settings.
419 This is a pointer points to a 32bit address. And it's only used in PostMem phase.
420 Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
421 Last entry VendorId must be 0.
422 The prototype of this policy is:
423 PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
424 **/
425 UINT32 PcieDeviceOverrideTablePtr;
426 CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
427 PCIE_COMMON_CONFIG2 PcieCommonConfig2;
428 } CPU_PCIE_CONFIG;
429
430 #pragma pack (pop)
431
432 #endif // _CPU_PCIE_CONFIG_H_
GpioLib.h
Header file for GpioLib.
PCIE_PEI_PREMEM_CONFIG::RsvdBits1
UINT32 RsvdBits1
Offset 32:1 :Reserved for future use.
Definition: CpuPcieConfig.h:129
ConfigBlock.h
Header file for Config Block Lib implementation.
CPU_PCIE_ROOT_PORT_CONFIG::Gen3Uptp
UINT32 Gen3Uptp
(Test) Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:319
PCIE_PEI_PREMEM_CONFIG::DmiMaxLinkSpeed
UINT32 DmiMaxLinkSpeed
Offset 28:0 : (Test) DMI Link Speed Control.
Definition: CpuPcieConfig.h:94
CPU_PCIE_EQ_LANE_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: CpuPcieConfig.h:289
CPU_PCIE_EQ_LANE_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: CpuPcieConfig.h:288
CPU_PCIE_CONFIG::FiaProgramming
UINT32 FiaProgramming
< (Test) Includes policies which are common to both SA and PCH PCIe
Definition: CpuPcieConfig.h:385
CPU_PCIE_CONFIG::PcieDeviceOverrideTablePtr
UINT32 PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.
Definition: CpuPcieConfig.h:425
CPU_PCIE_ROOT_PORT_CONFIG::Gen4Uptp
UINT32 Gen4Uptp
(Test) Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:324
CPU_PCIE_EQ_LANE_PARAM::PegGen4EndPointPreset
UINT8 PegGen4EndPointPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
Definition: CpuPcieConfig.h:295
PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: PcieConfig.h:76
CPU_PCIE_EQ_LANE_PARAM::PegGen3RootPortPreset
UINT8 PegGen3RootPortPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
Definition: CpuPcieConfig.h:291
CPU_PCIE_ROOT_PORT_CONFIG::ExtSync
UINT32 ExtSync
Indicate whether the extended synch is enabled. 0: Disable; 1: Enable.
Definition: CpuPcieConfig.h:304
CPU_PCIE_CONFIG::PegGen4ProgramStaticEq
UINT32 PegGen4ProgramStaticEq
(Test) Program PEG Gen4 EQ Phase1 Static Presets
Definition: CpuPcieConfig.h:400
CPU_PCIE_CONFIG
The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers Rev...
Definition: CpuPcieConfig.h:367
PCIE_PEI_PREMEM_CONFIG::InitPcieAspmAfterOprom
UINT32 InitPcieAspmAfterOprom
Offset 32:0 : Select when PCIe ASPM programming will happen in relation to the Oprom.
Definition: CpuPcieConfig.h:128
PCIE_PEI_PREMEM_CONFIG::DmiGen3ProgramStaticEq
UINT32 DmiGen3ProgramStaticEq
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.
Definition: CpuPcieConfig.h:119
CPU_PCIE_RP_PREMEM_CONFIG::RpEnabledMask
UINT32 RpEnabledMask
Root Port enabling mask.
Definition: CpuPcieConfig.h:163
CPU_PCIE_EQ_LANE_PARAM::PegGen3EndPointHint
UINT8 PegGen3EndPointHint
(Test) Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
Definition: CpuPcieConfig.h:293
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_PCIE_ROOT_PORT_CONFIG::FomsCp
UINT8 FomsCp
FOM Score Board Control Policy.
Definition: CpuPcieConfig.h:313
CPU_PCIE_RP_PREMEM_CONFIG::ClkReqMsgEnable
UINT8 ClkReqMsgEnable
Enable ClockReq Messaging.
Definition: CpuPcieConfig.h:175
CPU_PCIE_L1SUBSTATES_CONTROL
CPU_PCIE_L1SUBSTATES_CONTROL
Refer to SA EDS for the SA implementation values corresponding to below PCI-E spec defined ranges.
Definition: CpuPcieConfig.h:240
CPU_PCIE_RP_PREMEM_CONFIG
CPU PCIe Root Port Pre-Memory Configuration Contains Root Port settings and capabilities Revision 1: ...
Definition: CpuPcieConfig.h:156
CPU_PCIE_RP_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPcieConfig.h:157
CPU_PCIE_ROOT_PORT_CONFIG::Gen4Dptp
UINT32 Gen4Dptp
(Test) Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:325
CPU_PCIE_EQ_LANE_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: CpuPcieConfig.h:290
CPU_PCIE_ROOT_PORT_CONFIG::Gen5Dptp
UINT32 Gen5Dptp
(Test) Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:330
CpuPcieEqDefault
@ CpuPcieEqDefault
Definition: CpuPcieConfig.h:279
PCIE_PEI_PREMEM_CONFIG
PCI Express and DMI controller configuration .
Definition: CpuPcieConfig.h:84
PCIE_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: CpuPcieConfig.h:85
CPU_PCIE_ROOT_PORT_CONFIG::MultiVcEnabled
UINT32 MultiVcEnabled
Multiple Virtual Channel. 0: Disable; 1: Enable
Definition: CpuPcieConfig.h:305
CPU_PCIE_ROOT_PORT_CONFIG::Gen3Dptp
UINT32 Gen3Dptp
(Test) Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:320
PCIE_PEI_PREMEM_CONFIG::DmiDeEmphasis
UINT8 DmiDeEmphasis
Offset 64 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3....
Definition: CpuPcieConfig.h:142
CPU_PCIE_CONFIG::SetSecuredRegisterLock
UINT32 SetSecuredRegisterLock
(Test) Cpu Pcie Secure Register Lock
Definition: CpuPcieConfig.h:406
PCIE_PEI_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 28:8 :Reserved for future use.
Definition: CpuPcieConfig.h:120
CPU_PCIE_ROOT_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: CpuPcieConfig.h:306
CPU_PCIE_ROOT_PORT_CONFIG::PcieRpCommonConfig
PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig
(Test) Includes policies which are common to both SA and PCH RootPort
Definition: CpuPcieConfig.h:333
PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh3Method
UINT32 DmiGen3EqPh3Method
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.
Definition: CpuPcieConfig.h:112
CPU_PCIE_EQ_LANE_PARAM::PegGen4EndPointHint
UINT8 PegGen4EndPointHint
(Test) Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
Definition: CpuPcieConfig.h:296
CPU_PCIE_CONFIG::PegGen3ProgramStaticEq
UINT32 PegGen3ProgramStaticEq
< Skip Fia Configuration and lock if enable
Definition: CpuPcieConfig.h:392
CPU_PCIE_ROOT_PORT_CONFIG::Gen4EqPh3Method
UINT8 Gen4EqPh3Method
PCIe Gen4 Equalization Method.
Definition: CpuPcieConfig.h:312
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PcieConfig.h
PCIe Config Block.
CPU_PCIE_RP_PREMEM_CONFIG::LinkDownGpios
UINT8 LinkDownGpios
Assertion on Link Down GPIOs.
Definition: CpuPcieConfig.h:169
CPU_PCIE_ROOT_PORT_CONFIG
The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
Definition: CpuPcieConfig.h:302
CPU_PCIE_EQ_LANE_PARAM::PegGen4RootPortPreset
UINT8 PegGen4RootPortPreset
(Test) Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
Definition: CpuPcieConfig.h:294
CPU_PCIE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPcieConfig.h:368
CPU_PCIE_EQ_LANE_PARAM::PegGen3EndPointPreset
UINT8 PegGen3EndPointPreset
(Test) Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
Definition: CpuPcieConfig.h:292
CPU_PCIE_ROOT_PORT_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved Bits.
Definition: CpuPcieConfig.h:331
CPU_PCIE_ASPM_CONTROL
CPU_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: CpuPcieConfig.h:227
CPU_PCIE_CONFIG::SlotSelection
UINT32 SlotSelection
This member allows to select between the PCI Express M2 or CEMx4 slot 1: PCIe M2; 0: CEMx4 slot.
Definition: CpuPcieConfig.h:410
PCIE_PEI_PREMEM_CONFIG::DmiGen3EqPh2Enable
UINT32 DmiGen3EqPh2Enable
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.
Definition: CpuPcieConfig.h:102
CPU_PCIE_ROOT_PORT_CONFIG::Gen5Uptp
UINT32 Gen5Uptp
(Test) Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes....
Definition: CpuPcieConfig.h:329
CpuPcieEqHardware
@ CpuPcieEqHardware
Hardware equalization.
Definition: CpuPcieConfig.h:280
CPU_PCIE_RP_PREMEM_CONFIG::DekelSquelchWa
UINT8 DekelSquelchWa
Dekel Recipe Workaround 2 1=Minimal, 9=Maximum,.
Definition: CpuPcieConfig.h:181
CpuPcieEqStaticCoeff
@ CpuPcieEqStaticCoeff
Fixed equalization (requires Coefficient settings per lane)
Definition: CpuPcieConfig.h:281
CPU_PCIE_EQ_METHOD
CPU_PCIE_EQ_METHOD
Definition: CpuPcieConfig.h:278
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieConfigGen3.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3
Classes
CpuPcieConfigGen3.h File Reference

Pcie root port policy. More...

#include <Library/GpioLib.h>
#include <Library/CpuPcieInfoFruLib.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for CpuPcieConfigGen3.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SA_GPIO_INFO_PCIE
SA GPIO Data Structure. More...
struct | PEG_GPIO_DATA
SA Board PEG GPIO Info. More...
struct | PCIE_PEI_PREMEM_CONFIG_GEN3
PCI Express and DMI controller configuration
. More...

Detailed Description

Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPcieConfigGen3.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieConfigGen3.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3
CpuPcieConfigGen3.h
Go to the documentation of this file.
1 /** @file
2 Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_PCIE_CONFIG_GEN3_H_
37 #define _CPU_PCIE_CONFIG_GEN3_H_
38
39 #include <Library/GpioLib.h>
40 #include <Library/CpuPcieInfoFruLib.h>
41 #include <PcieConfig.h>
42 #include <ConfigBlock.h>
43 #include <Register/SaRegsHostBridge.h>
44
45 #pragma pack(push, 1)
46
47 #define PCIE_PEI_PREMEM_CONFIG_GEN3_REVISION 1
48
49 #define L0_SET BIT0
50 #define L1_SET BIT1
51
52
53 ///
54 /// SA GPIO Data Structure
55 ///
56 typedef struct {
57 GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
58 UINT8 Value; ///< Offset 4: GPIO Value
59 UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
60 UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
61 UINT32 RsvdBits0 : 31;
62 } SA_GPIO_INFO_PCIE;
63
64 ///
65 /// SA Board PEG GPIO Info
66 ///
67 typedef struct {
68 SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
69 SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
70 BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
71 UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
72 } PEG_GPIO_DATA;
73
74 /**
75 PCI Express and DMI controller configuration\n
76 @note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
77 <b>Revision 1</b>:
78 - Initial version.
79 **/
80 typedef struct {
81 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
82 /**
83 Offset 28:0 :
84 <b>(Test)</b> DMI Link Speed Control
85 - <b>Auto</b> (0x0) : Maximum possible link speed (Default)
86 - Gen1 (0x1) : Limit Link to Gen1 Speed
87 - Gen2 (0x2) : Limit Link to Gen2 Speed
88 - Gen3 (0x3) : Limit Link to Gen3 Speed
89 **/
90 UINT8 DmiMaxLinkSpeed;
91 /**
92 Offset 28:2 :
93 <b>(Test)</b> DMI Equalization Phase 2 Enable Control
94 - Disabled (0x0) : Disable phase 2
95 - Enabled (0x1) : Enable phase 2
96 - <b>Auto</b> (0x2) : Use the current default method (Default)
97 **/
98 UINT8 DmiGen3EqPh2Enable;
99 /**
100 Offset 28:4 :
101 <b>(Test)</b> Selects the method for performing Phase3 of Gen3 Equalization on DMI
102 - <b>Auto</b> (0x0) : Use the current default method (Default)
103 - HwEq (0x1) : Use Adaptive Hardware Equalization
104 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
105 - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
106 - Disabled (0x4) : Bypass Equalization Phase 3
107 **/
108 UINT8 DmiGen3EqPh3Method;
109 /**
110 Offset 28:7 :
111 <b>(Test)</b> Program DMI Gen3 EQ Phase1 Static Presets
112 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
113 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
114 **/
115 UINT8 DmiGen3ProgramStaticEq;
116
117 /**
118 Offset 28:8 to 28:15 :
119 <b>(Test)</b> PEG Enable Control
120 - Disabled (0x0) : Disable PEG Port
121 - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it)
122 - <b>Auto</b> (0x2) : If an endpoint is present, enable the PEG Port, Disable otherwise (Default)
123 **/
124 UINT8 Peg0Enable; ///< Enable/Disable PEG 0:1:0 Root Port
125 UINT8 Peg1Enable; ///< <b>(Test)</b> Enable/Disable PEG 0:1:1 Root Port
126 UINT8 Peg2Enable; ///< <b>(Test)</b> Enable/Disable PEG 0:1:2 Root Port
127 UINT8 Peg3Enable; ///< <b>(Test)</b> Enable/Disable PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
128
129 /**
130 Offset 28:16 :
131 <b>(Test)</b> PCIe Link Speed Control
132 - <b>Auto</b> (0x0) : Maximum possible Link speed (Default)
133 - Gen1 (0x1) : Limit Link to Gen1 Speed
134 - Gen2 (0x2) : Limit Link to Gen2 Speed
135 - Gen3 (0x3) : Limit Link to Gen3 Speed
136 **/
137 UINT8 Peg0MaxLinkSpeed; ///< PCIe Link Speed Control for PEG 0:1:0 Root Port.
138 UINT8 Peg1MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:1 Root Port.
139 UINT8 Peg2MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:1:2 Root Port.
140 UINT8 Peg3MaxLinkSpeed; ///< <b>(Test)</b> PCIe Link Speed Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
141
142 /**
143 Offset 32:0 :
144 <b>(Test)</b> PCIe Link Width Control
145 - <b>Auto</b> (0x0) : Maximum possible Link width (Default)
146 - X1 (0x1) : Limit Link to X1 Width
147 - X2 (0x2) : Limit Link to X2 Width
148 - X4 (0x3) : Limit Link to X4 Width
149 - X8 (0x4) : Limit Link to X8 Width
150 **/
151 UINT8 Peg0MaxLinkWidth; ///< PCIe Link Width Control for PEG 0:1:0 Root Port.
152 UINT8 Peg1MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:1:1 Root Port.
153 UINT8 Peg2MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:1:2 Root Port.
154 UINT8 Peg3MaxLinkWidth; ///< <b>(Test)</b> PCIe Link Width Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
155 /**
156 Offset 32:12 to 32:15 :
157 Power down unused lanes on the PEG Root Port.
158 - Disabled (0x0) : No power saving.
159 - <b>Auto</b> (0x1) : Bios will power down unused lanes based on the max possible link width
160 **/
161 UINT8 Peg0PowerDownUnusedLanes; ///< Power down unused lanes on the PEG 0:1:0 Root Port.
162 UINT8 Peg1PowerDownUnusedLanes; ///< Power down unused lanes on the PEG 0:1:1 Root Port.
163 UINT8 Peg2PowerDownUnusedLanes; ///< Power down unused lanes on the PEG 0:1:2 Root Port.
164 UINT8 Peg3PowerDownUnusedLanes; ///< Power down unused lanes on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
165
166 /**
167 Offset 32:16 to 32:23 :
168 <b>(Test)</b> PCIe Equalization Phase 2 Enable Control
169 - Disabled (0x0) : Disable phase 2
170 - Enabled (0x1) : Enable phase 2
171 - <b>Auto</b> (0x2) : Use the current default method (Default)
172 **/
173 UINT8 Peg0Gen3EqPh2Enable; ///< Phase2 EQ enable on the PEG 0:1:0 Root Port.
174 UINT8 Peg1Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:1 Root Port.
175 UINT8 Peg2Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:1:2 Root Port.
176 UINT8 Peg3Gen3EqPh2Enable; ///< <b>(Test)</b> Phase2 EQ enable on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
177
178 /**
179 Offset 36:0 to 36:11 :
180 <b>(Test)</b> Select the method for performing Phase3 of Gen3 Equalization.
181 - <b>Auto</b> (0x0) : Use the current default method (Default)
182 - HwEq (0x1) : Use Adaptive Hardware Equalization
183 - SwEq (0x2) : Use Adaptive Software Equalization (Implemented in BIOS Reference Code)
184 - Static (0x3) : Use the Static EQs provided in PegGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just Phase1)
185 - Disabled (0x4) : Bypass Equalization Phase 3
186 **/
187 UINT8 Peg0Gen3EqPh3Method; ///< Phase3 EQ method on the PEG 0:1:0 Root Port.
188 UINT8 Peg1Gen3EqPh3Method; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:1:1 Root Port.
189 UINT8 Peg2Gen3EqPh3Method; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:1:2 Root Port.
190 UINT8 Peg3Gen3EqPh3Method; ///< <b>(Test)</b> Phase3 EQ method on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
191 /**
192 Offset 36:12 :
193 <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
194 - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
195 - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
196 **/
197 UINT8 PegGen3ProgramStaticEq;
198 /**
199 Offset 36:13 :
200 <b>(Test)</b> Always Attempt Gen3 Software Equalization
201
202 When enabled, Gen3 Software Equalization will be executed every boot. When disabled, it will be only executed if the CPU
203 or EP is changed, otherwise it is skipped and the previous EQ value will be re-used.
204
205 This setting will only have an effect if Software Equalization is enabled and OEM Platform Code implements
206 save/restore of the PegDataPtr data (see below). If PegDataPtr is not saved/restored RC forces this to be enabled.
207
208 - <b>Disabled</b> (0x0) : Reuse EQ settings saved/restored from NVRAM whenever possible (Default)
209 - Enabled (0x1) : Re-test and generate new EQ values every boot, not recommended
210 **/
211 UINT8 Gen3SwEqAlwaysAttempt;
212 /**
213 Offset 36:14 to 36:16 :
214 <b>(Test)</b> Select number of TxEq presets to test in the PCIe/DMI Software Equalization Algorithm
215 - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8
216 - P0-P9 (0x1) : Test Presets 0-9
217 - <b>Auto</b> (0x2) : Use the current default method (Default)
218 Auto will test Presets 7, 3, 5, and 8. It is possible for this default to change over time;
219 using "Auto" will ensure Reference Code always uses the latest default settings.
220 @warning Do not change from the default. Hard to detect issues are likely.
221 **/
222 UINT8 Gen3SwEqNumberOfPresets;
223 /**
224 Offset 36:17 to 36:18:
225 <b>(Test)</b> Offset 36 Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm
226 - Disabled (0x0) : Disable VOC Test
227 - Enabled (0x1) : Enable VOC Test
228 - <b>Auto</b> (0x2) : Use the current default (Default)
229 **/
230 UINT8 Gen3SwEqEnableVocTest;
231 /**
232 Offset 36:19 :
233 Select when PCIe ASPM programming will happen in relation to the Oprom
234 - <b>Before</b> (0x0) : Do PCIe ASPM programming before Oprom. (Default)
235 - After (0x1) : Do PCIe ASPM programming after Oprom. This will require an SMI handler to save/restore ASPM settings.
236 **/
237 UINT8 InitPcieAspmAfterOprom;
238 /**
239 Offset 36:20 :
240 <b>(Test)</b> PCIe Rx Compliance Testing Mode
241 - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe Rx Compliance testing (Default)
242 - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing
243 **/
244 UINT8 PegRxCemTestingMode;
245
246 /**
247 Offset 36:21 to 36:24 :
248 <b>(Test)</b> PCIe Rx Compliance Loopback Lane
249
250 When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) will be
251 used for RxCEMLoopback.
252
253 Default is Lane 0.
254 **/
255 UINT8 PegRxCemLoopbackLane;
256 /**
257 Offset 36:25 to 36:28 :
258 <b>(Test)</b> Generate PCIe BDAT Margin Table. Set this policy to enable the generation and addition of PCIe margin data to the BDAT table.
259 - <b>Disabled</b> (0x0) : Normal Operation - Disable PCIe BDAT margin data generation (Default)
260 - PortData (0x1) : Port Data - Generate PCIe BDAT margin data
261 **/
262 UINT8 PegGenerateBdatMarginTable;
263 /**
264 Offset 36:29 :
265 <b>(Test)</b> PCIe Non-Protocol Awareness for Rx Compliance Testing
266 - <b>Disabled</b> (0x0) : Normal Operation - Disable non-protocol awareness (Default)
267 - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-protocol awareness for compliance testing
268 **/
269 UINT8 PegRxCemNonProtocolAwareness;
270 /**
271 Offset 36:30 :
272 <b>(Test)</b> PCIe Disable Spread Spectrum Clocking. This feature should be TRUE only for compliance testing
273 - <b>False</b> (0x0) : Normal Operation - SSC enabled (Default)
274 - True (0x1) : Disable SSC - Disable SSC for compliance testing
275 **/
276 UINT8 PegDisableSpreadSpectrumClocking;
277
278 UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE_VER1]; ///< Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
279 UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE_VER1]; ///< Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
280 UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE_VER1]; ///< Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default for each lane
281 /**
282 Offset 48/60 :
283 DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
284 has to be specified based upon platform design and must follow the guideline. Default is 12.
285 **/
286
287 UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE_VER1];
288
289 UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE_GEN3]; ///< Offset 54 <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
290 UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE_GEN3]; ///< Offset 70 <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
291 UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE_GEN3]; ///< Offset 86 <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
292 /**
293 Offset 102:
294 PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15). This setting
295 has to be specified based upon platform design and must follow the guideline. Default is 12.
296 **/
297 UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE_GEN3];
298 /**
299 Offset 110:
300 <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 1000.
301 @warning Do not change from the default. Hard to detect issues are likely.
302 @note An attack on this policy could result in an apparent hang,
303 but the system will eventually boot. This variable should be protected.
304 **/
305 UINT16 Gen3SwEqJitterDwellTime;
306 /**
307 Offset 112:
308 This is a memory data pointer for saved preset search results. The reference code will store
309 the Gen3 Preset Search results in the SaPegHob. In order to skip the Gen3
310 preset search on boots where the PEG card configuration has not changed since the previous boot,
311 platform code can save the contents of the SaPegHob in DXE (When it present and for size reported by Header.HobLength)
312 and provide a pointer to a restored copy of that data. Default value is NULL, which results in a full
313 preset search every boot.
314
315 @note An attack on this policy could prevent the PCIe display from working until a boot when
316 PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable used to save the
317 preset search results should be protected in a way that it can only be modified by the
318 platform manufacturer.
319 **/
320 UINT8 Rsvd0[2];
321 VOID *PegDataPtr;
322 /**
323 Offset 116:
324 <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 1.
325 @warning Do not change from the default. Hard to detect issues are likely.
326 **/
327 UINT16 Gen3SwEqJitterErrorTarget;
328
329 /**
330 Offset 118:
331 <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 10000.
332 @warning Do not change from the default. Hard to detect issues are likely.
333 @note An attack on this policy could result in an apparent hang,
334 but the system will eventually boot. This variable should be protected.
335 **/
336 UINT16 Gen3SwEqVocDwellTime;
337
338 /**
339 Offset 120:
340 <b>(Test)</b>Used for PCIe Gen3 Software Equalization. Range: 0-65535, default is 2.
341 @warning Do not change from the default. Hard to detect issues are likely.
342 **/
343 UINT16 Gen3SwEqVocErrorTarget;
344 /**
345 Offset 122:
346 PCIe Hot Plug Enable/Disable. It has 2 policies.
347 - Disabled (0x0) : No hotplug.
348 - Enabled (0x1) : Bios assist hotplug.
349 **/
350 UINT8 PegRootPortHPE[SA_PEG_MAX_FUN_GEN3];
351 UINT8 DmiDeEmphasis; ///< Offset 125 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)
352 UINT8 Rsvd1[2];
353 /**
354 Offset 128:
355 This contains the PCIe PERST# GPIO information. This structure is required
356 for PCIe Gen3 operation. The reference code will use the information in this structure in
357 order to reset PCIe Gen3 devices during equalization, if necessary. Refer to the Platform
358 Developer's Guide (PDG) for additional details.
359 **/
360 PEG_GPIO_DATA PegGpioData;
361
362 /**
363 Offset 156
364 <b>(Test)</b> PCIe Override RxCTLE. This feature should only be true to disable RxCTLE adaptive behavior for compliance testing
365 - <b>False</b> (0x0) : Normal Operation - RxCTLE adaptive behavior enabled (Default)
366 - True (0x1) : Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified
367 From CFL onwards, modularity is introduced to this setup option so that the RxCTLE adaptive behavior could be controlled at the controller level.
368 Making this variable a UINT8 to accomodate the values of all controllers as bit definition
369 **/
370 UINT8 PegGen3RxCtleOverride;
371 UINT8 Rsvd2[3];
372
373 } PCIE_PEI_PREMEM_CONFIG_GEN3;
374
375 #pragma pack (pop)
376
377 #endif // _CPU_PCIE_CONFIG_GEN3_H_
GpioLib.h
Header file for GpioLib.
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3Gen3EqPh2Enable
UINT8 Peg3Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon...
Definition: CpuPcieConfigGen3.h:176
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1Gen3EqPh2Enable
UINT8 Peg1Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:1:1 Root Port.
Definition: CpuPcieConfigGen3.h:174
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0PowerDownUnusedLanes
UINT8 Peg0PowerDownUnusedLanes
Offset 32:12 to 32:15 : Power down unused lanes on the PEG Root Port.
Definition: CpuPcieConfigGen3.h:161
ConfigBlock.h
Header file for Config Block Lib implementation.
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3PowerDownUnusedLanes
UINT8 Peg3PowerDownUnusedLanes
Power down unused lanes on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon...
Definition: CpuPcieConfigGen3.h:164
PEG_GPIO_DATA::GpioSupport
BOOLEAN GpioSupport
Offset 24: 1=Supported; 0=Not Supported.
Definition: CpuPcieConfigGen3.h:70
PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemNonProtocolAwareness
UINT8 PegRxCemNonProtocolAwareness
Offset 36:29 : (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing.
Definition: CpuPcieConfigGen3.h:269
PCIE_PEI_PREMEM_CONFIG_GEN3::PegGen3ProgramStaticEq
UINT8 PegGen3ProgramStaticEq
Offset 36:12 : (Test) Program PEG Gen3 EQ Phase1 Static Presets.
Definition: CpuPcieConfigGen3.h:197
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2Gen3EqPh3Method
UINT8 Peg2Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:1:2 Root Port.
Definition: CpuPcieConfigGen3.h:189
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1MaxLinkWidth
UINT8 Peg1MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:1:1 Root Port.
Definition: CpuPcieConfigGen3.h:152
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1Gen3EqPh3Method
UINT8 Peg1Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:1:1 Root Port.
Definition: CpuPcieConfigGen3.h:188
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqJitterErrorTarget
UINT16 Gen3SwEqJitterErrorTarget
Offset 116: (Test)Used for PCIe Gen3 Software Equalization.
Definition: CpuPcieConfigGen3.h:327
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0MaxLinkWidth
UINT8 Peg0MaxLinkWidth
Offset 32:0 : (Test) PCIe Link Width Control.
Definition: CpuPcieConfigGen3.h:151
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2MaxLinkWidth
UINT8 Peg2MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:1:2 Root Port.
Definition: CpuPcieConfigGen3.h:153
SA_GPIO_INFO_PCIE::GpioPad
GPIO_PAD GpioPad
Offset 0: GPIO Pad.
Definition: CpuPcieConfigGen3.h:57
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0MaxLinkSpeed
UINT8 Peg0MaxLinkSpeed
Offset 28:16 : (Test) PCIe Link Speed Control.
Definition: CpuPcieConfigGen3.h:137
PCIE_PEI_PREMEM_CONFIG_GEN3::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: CpuPcieConfigGen3.h:81
PCIE_PEI_PREMEM_CONFIG_GEN3::PegGpioData
PEG_GPIO_DATA PegGpioData
Offset 128: This contains the PCIe PERST# GPIO information.
Definition: CpuPcieConfigGen3.h:360
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2Enable
UINT8 Peg2Enable
(Test) Enable/Disable PEG 0:1:2 Root Port
Definition: CpuPcieConfigGen3.h:126
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:47
PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3EqPh2Enable
UINT8 DmiGen3EqPh2Enable
Offset 28:2 : (Test) DMI Equalization Phase 2 Enable Control.
Definition: CpuPcieConfigGen3.h:98
PEG_GPIO_DATA
SA Board PEG GPIO Info.
Definition: CpuPcieConfigGen3.h:67
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3Enable
UINT8 Peg3Enable
(Test) Enable/Disable PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon.
Definition: CpuPcieConfigGen3.h:127
PCIE_PEI_PREMEM_CONFIG_GEN3::DmiDeEmphasis
UINT8 DmiDeEmphasis
Offset 125 This field is used to describe the DeEmphasis control for DMI (-6 dB and -3....
Definition: CpuPcieConfigGen3.h:351
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemLoopbackLane
UINT8 PegRxCemLoopbackLane
Offset 36:21 to 36:24 : (Test) PCIe Rx Compliance Loopback Lane.
Definition: CpuPcieConfigGen3.h:255
PCIE_PEI_PREMEM_CONFIG_GEN3::PegDisableSpreadSpectrumClocking
UINT8 PegDisableSpreadSpectrumClocking
Offset 36:30 : (Test) PCIe Disable Spread Spectrum Clocking.
Definition: CpuPcieConfigGen3.h:276
PCIE_PEI_PREMEM_CONFIG_GEN3::DmiMaxLinkSpeed
UINT8 DmiMaxLinkSpeed
Offset 28:0 : (Test) DMI Link Speed Control.
Definition: CpuPcieConfigGen3.h:90
PCIE_PEI_PREMEM_CONFIG_GEN3::PegGenerateBdatMarginTable
UINT8 PegGenerateBdatMarginTable
Offset 36:25 to 36:28 : (Test) Generate PCIe BDAT Margin Table.
Definition: CpuPcieConfigGen3.h:262
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2PowerDownUnusedLanes
UINT8 Peg2PowerDownUnusedLanes
Power down unused lanes on the PEG 0:1:2 Root Port.
Definition: CpuPcieConfigGen3.h:163
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3MaxLinkSpeed
UINT8 Peg3MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer sil...
Definition: CpuPcieConfigGen3.h:140
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Gen3EqPh3Method
UINT8 Peg0Gen3EqPh3Method
Offset 36:0 to 36:11 : (Test) Select the method for performing Phase3 of Gen3 Equalization.
Definition: CpuPcieConfigGen3.h:187
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3MaxLinkWidth
UINT8 Peg3MaxLinkWidth
(Test) PCIe Link Width Control for PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer sil...
Definition: CpuPcieConfigGen3.h:154
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1PowerDownUnusedLanes
UINT8 Peg1PowerDownUnusedLanes
Power down unused lanes on the PEG 0:1:1 Root Port.
Definition: CpuPcieConfigGen3.h:162
PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3EqPh3Method
UINT8 DmiGen3EqPh3Method
Offset 28:4 : (Test) Selects the method for performing Phase3 of Gen3 Equalization on DMI.
Definition: CpuPcieConfigGen3.h:108
PCIE_PEI_PREMEM_CONFIG_GEN3::DmiGen3ProgramStaticEq
UINT8 DmiGen3ProgramStaticEq
Offset 28:7 : (Test) Program DMI Gen3 EQ Phase1 Static Presets.
Definition: CpuPcieConfigGen3.h:115
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqVocDwellTime
UINT16 Gen3SwEqVocDwellTime
Offset 118: (Test)Used for PCIe Gen3 Software Equalization.
Definition: CpuPcieConfigGen3.h:336
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqJitterDwellTime
UINT16 Gen3SwEqJitterDwellTime
Offset 110: (Test)Used for PCIe Gen3 Software Equalization.
Definition: CpuPcieConfigGen3.h:305
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Enable
UINT8 Peg0Enable
Offset 28:8 to 28:15 : (Test) PEG Enable Control.
Definition: CpuPcieConfigGen3.h:124
PCIE_PEI_PREMEM_CONFIG_GEN3::InitPcieAspmAfterOprom
UINT8 InitPcieAspmAfterOprom
Offset 36:19 : Select when PCIe ASPM programming will happen in relation to the Oprom.
Definition: CpuPcieConfigGen3.h:237
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqVocErrorTarget
UINT16 Gen3SwEqVocErrorTarget
Offset 120: (Test)Used for PCIe Gen3 Software Equalization.
Definition: CpuPcieConfigGen3.h:343
PCIE_PEI_PREMEM_CONFIG_GEN3::PegGen3RxCtleOverride
UINT8 PegGen3RxCtleOverride
Offset 156 (Test) PCIe Override RxCTLE.
Definition: CpuPcieConfigGen3.h:370
SA_GPIO_INFO_PCIE::Active
UINT32 Active
Offset 8: 0=Active Low; 1=Active High.
Definition: CpuPcieConfigGen3.h:60
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg3Gen3EqPh3Method
UINT8 Peg3Gen3EqPh3Method
(Test) Phase3 EQ method on the PEG 0:6:0 Root Port. Applicable on certain CNL- SKUs and newer silicon...
Definition: CpuPcieConfigGen3.h:190
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqEnableVocTest
UINT8 Gen3SwEqEnableVocTest
Offset 36:17 to 36:18: (Test) Offset 36 Enable use of the Voltage Offset and Centering Test in the PC...
Definition: CpuPcieConfigGen3.h:230
SA_GPIO_INFO_PCIE
SA GPIO Data Structure.
Definition: CpuPcieConfigGen3.h:56
PcieConfig.h
PCIe Config Block.
PCIE_PEI_PREMEM_CONFIG_GEN3::PegRxCemTestingMode
UINT8 PegRxCemTestingMode
Offset 36:20 : (Test) PCIe Rx Compliance Testing Mode.
Definition: CpuPcieConfigGen3.h:244
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqNumberOfPresets
UINT8 Gen3SwEqNumberOfPresets
Offset 36:14 to 36:16 : (Test) Select number of TxEq presets to test in the PCIe/DMI Software Equaliz...
Definition: CpuPcieConfigGen3.h:222
PCIE_PEI_PREMEM_CONFIG_GEN3::Gen3SwEqAlwaysAttempt
UINT8 Gen3SwEqAlwaysAttempt
Offset 36:13 : (Test) Always Attempt Gen3 Software Equalization.
Definition: CpuPcieConfigGen3.h:211
SA_GPIO_INFO_PCIE::Value
UINT8 Value
Offset 4: GPIO Value.
Definition: CpuPcieConfigGen3.h:58
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1MaxLinkSpeed
UINT8 Peg1MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:1:1 Root Port.
Definition: CpuPcieConfigGen3.h:138
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2Gen3EqPh2Enable
UINT8 Peg2Gen3EqPh2Enable
(Test) Phase2 EQ enable on the PEG 0:1:2 Root Port.
Definition: CpuPcieConfigGen3.h:175
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg0Gen3EqPh2Enable
UINT8 Peg0Gen3EqPh2Enable
Offset 32:16 to 32:23 : (Test) PCIe Equalization Phase 2 Enable Control.
Definition: CpuPcieConfigGen3.h:173
PEG_GPIO_DATA::SaPeg3ResetGpio
SA_GPIO_INFO_PCIE SaPeg3ResetGpio
Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin.
Definition: CpuPcieConfigGen3.h:69
PEG_GPIO_DATA::SaPeg0ResetGpio
SA_GPIO_INFO_PCIE SaPeg0ResetGpio
Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin.
Definition: CpuPcieConfigGen3.h:68
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg1Enable
UINT8 Peg1Enable
(Test) Enable/Disable PEG 0:1:1 Root Port
Definition: CpuPcieConfigGen3.h:125
PCIE_PEI_PREMEM_CONFIG_GEN3
PCI Express and DMI controller configuration .
Definition: CpuPcieConfigGen3.h:80
PCIE_PEI_PREMEM_CONFIG_GEN3::Peg2MaxLinkSpeed
UINT8 Peg2MaxLinkSpeed
(Test) PCIe Link Speed Control for PEG 0:1:2 Root Port.
Definition: CpuPcieConfigGen3.h:139
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
CpuPcieHob.h File Reference

The GUID definition for CpuPcieHob. More...

#include <Base.h>
#include <CpuPcieInfo.h>
#include <CpuPcieConfig.h>
Include dependency graph for CpuPcieHob.h:

Go to the source code of this file.

Classes

struct CPU_PCIE_HOB
The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers. More...

Detailed Description

The GUID definition for CpuPcieHob.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPcieHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
CpuPcieHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for CpuPcieHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_PCIE_HOB_H_
36 #define _CPU_PCIE_HOB_H_
37
38 #include <Base.h>
39 #include <CpuPcieInfo.h>
40 #include <CpuPcieConfig.h>
41
42 extern EFI_GUID gCpuPcieHobGuid;
43 #pragma pack (push,1)
44
45 /**
46 The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
47 **/
48 typedef struct {
49 ///
50 /// These members describe the configuration of each CPU PCIe root port.
51 ///
52 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
53 CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
54 UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
55
56 UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
57 UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
58 BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
59 UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
60 UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
61 UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
62 UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
63 BOOLEAN ComplianceTest; ///< Compliance Test based on policy
64 UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
65 UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
66 UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
67 UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
68 UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
69 UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
70 UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
71 UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
72 UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
73 } CPU_PCIE_HOB;
74 #pragma pack (pop)
75 #endif
CPU_PCIE_HOB::HsPhyRecipeVersionMinor
UINT32 HsPhyRecipeVersionMinor
HS-Phy Recipe Minor Version.
Definition: CpuPcieHob.h:65
CPU_PCIE_HOB::HsPhyFwHotFix
UINT32 HsPhyFwHotFix
HS-Phy Firmware Hot Fix Version.
Definition: CpuPcieHob.h:68
CPU_PCIE_HOB::ComplianceTest
BOOLEAN ComplianceTest
Compliance Test based on policy.
Definition: CpuPcieHob.h:63
CpuPcieConfig.h
Pcie root port policy.
CPU_PCIE_HOB::RpEnMaskFromDevEn
UINT32 RpEnMaskFromDevEn
Rootport enabled mask based on Device Id.
Definition: CpuPcieHob.h:60
CPU_PCIE_HOB::DekelFwVersionMinor
UINT32 DekelFwVersionMinor
Dekel Firmware Minor Version.
Definition: CpuPcieHob.h:56
CPU_PCIE_HOB::HsPhyRecipeVersionMajor
UINT32 HsPhyRecipeVersionMajor
HS-Phy Recipe Major Version.
Definition: CpuPcieHob.h:64
CPU_PCIE_HOB::SlotSelection
UINT8 SlotSelection
1=M2 slot, 0=CEMx4 slot
Definition: CpuPcieHob.h:62
CPU_PCIE_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
These members describe the configuration of each CPU PCIe root port.
Definition: CpuPcieHob.h:52
CPU_PCIE_HOB::HsPhyFwEvBitProgMajor
UINT32 HsPhyFwEvBitProgMajor
HS-Phy Firmware EV Bit Prog Major.
Definition: CpuPcieHob.h:70
CPU_PCIE_HOB
The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers.
Definition: CpuPcieHob.h:48
CPU_PCIE_HOB::HsPhyFwEvBitProgMinor
UINT32 HsPhyFwEvBitProgMinor
HS-Phy Firmware EV Bit Prog Minor.
Definition: CpuPcieHob.h:71
CPU_PCIE_HOB::HsPhyFwProdMinor
UINT32 HsPhyFwProdMinor
HS-Phy Firmware Product Minor Verison.
Definition: CpuPcieHob.h:67
CPU_PCIE_ROOT_PORT_CONFIG
The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
Definition: CpuPcieConfig.h:302
CPU_PCIE_HOB::RpEnabledMask
UINT32 RpEnabledMask
Rootport enabled mask based on DEVEN register.
Definition: CpuPcieHob.h:59
CPU_PCIE_HOB::HsPhyFwBuild
UINT32 HsPhyFwBuild
HS-Phy Firmware Build version.
Definition: CpuPcieHob.h:69
CPU_PCIE_HOB::DekelFwVersionMajor
UINT32 DekelFwVersionMajor
Dekel Firmware Major Version.
Definition: CpuPcieHob.h:57
CPU_PCIE_HOB::InitPcieAspmAfterOprom
BOOLEAN InitPcieAspmAfterOprom
1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
Definition: CpuPcieHob.h:58
CPU_PCIE_HOB::HsPhyMap
UINT32 HsPhyMap
HS-Phy Mapping Based on HS-Py supported ports.
Definition: CpuPcieHob.h:72
CPU_PCIE_HOB::HsPhyFwProdMajor
UINT32 HsPhyFwProdMajor
HS-Phy Firmware Product Major Verison.
Definition: CpuPcieHob.h:66
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieHobGen3.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
CpuPcieHobGen3.h File Reference

The GUID definition for CpuPcieHob. More...

#include <Base.h>
#include <CpuPcieInfo.h>
#include <CpuPcieConfigGen3.h>
Include dependency graph for CpuPcieHobGen3.h:

Go to the source code of this file.

Classes

struct | SA_PEG_DATA
PEG data definition This structure can be saved in non-volatile memory to be re-used in the following boot. More...
struct | SA_PEG_HOB
System Agent PEG NVS Hob. More...

Detailed Description

The GUID definition for CpuPcieHob.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPcieHobGen3.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieHobGen3.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
CpuPcieHobGen3.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for CpuPcieHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_PCIE_HOB_GEN3_H_
36 #define _CPU_PCIE_HOB_GEN3_H_
37
38 #include <Base.h>
39 #include <CpuPcieInfo.h>
40 #include <CpuPcieConfigGen3.h>
41
42 extern EFI_GUID gSaPegHobGuid;
43 #pragma pack (push,1)
44 /**
45 PEG data definition
46 This structure can be saved in non-volatile memory to be re-used in the following boot.
47 By this way reference code will not re-do PCIe Preset Search and save POST time
48 SI_POLICY_PPI can be used to pass the pointer of pre-saved SA_PEG_DATA by platform code
49 **/
50 typedef struct {
51 UINT32 EndPointVendorIdDeviceId[SA_PEG_MAX_FUN_GEN3]; ///< Offset 0 - 11: VID/DID for each PEG controller
52 UINT8 BestPreset[SA_PEG_MAX_LANE_GEN3]; ///< Offset 12 - 27: Best preset value for each lane
53 UINT8 PegGen3PresetSearch; ///< Offset 28: Preset search value
54 UINT8 PegLinkFailMask; ///< Offset 29: Mask of PEG controllers to ignore
55 UINT8 Rsvd0[2]; ///< Offset 30: Reserved for future use.
56 } SA_PEG_DATA;
57
58 ///
59 /// System Agent PEG NVS Hob
60 ///
61 typedef struct {
62 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gSaPegHobGuid
63 BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
64 SA_PEG_DATA PegData; ///< Offset 24 (Move to FSP NVS Hob) PEG data definition
65 UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN_GEN3]; ///< PCIe power down unused bundles support
66 BOOLEAN PegPlatformResetRequired; ///< 1=platform code should generate a cold/power cycle reset after saving PEG config data into NVRAM
67 } SA_PEG_HOB;
68 #pragma pack (pop)
69 #endif
SA_PEG_DATA::PegLinkFailMask
UINT8 PegLinkFailMask
Offset 29: Mask of PEG controllers to ignore.
Definition: CpuPcieHobGen3.h:54
SA_PEG_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gSaPegHobGuid.
Definition: CpuPcieHobGen3.h:62
SA_PEG_HOB::PegPlatformResetRequired
BOOLEAN PegPlatformResetRequired
1=platform code should generate a cold/power cycle reset after saving PEG config data into NVRAM
Definition: CpuPcieHobGen3.h:66
SA_PEG_DATA
PEG data definition This structure can be saved in non-volatile memory to be re-used in the following...
Definition: CpuPcieHobGen3.h:50
CpuPcieConfigGen3.h
Pcie root port policy.
SA_PEG_HOB
System Agent PEG NVS Hob.
Definition: CpuPcieHobGen3.h:61
SA_PEG_HOB::InitPcieAspmAfterOprom
BOOLEAN InitPcieAspmAfterOprom
1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
Definition: CpuPcieHobGen3.h:63
SA_PEG_DATA::PegGen3PresetSearch
UINT8 PegGen3PresetSearch
Offset 28: Preset search value.
Definition: CpuPcieHobGen3.h:53
SA_PEG_HOB::PegData
SA_PEG_DATA PegData
Offset 24 (Move to FSP NVS Hob) PEG data definition.
Definition: CpuPcieHobGen3.h:64
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPlatformLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
Functions | Variables
CpuPlatformLib.h File Reference

Header file for CpuPlatform Lib. More...

#include <Uefi.h>
#include <CpuRegs.h>
#include <CpuGenInfo.h>
#include <CpuDataStruct.h>
#include <CpuPowerMgmt.h>
Include dependency graph for CpuPlatformLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

CPU_FAMILY | GetCpuFamily (VOID)
Check CPU Type of the platform. More...
CPU_STEPPING | GetCpuStepping (VOID)
Return Cpu stepping type. More...
UINT8 | GetCpuSku (VOID)
Return CPU Sku. More...
BOOLEAN | IsSmxSupported (VOID)
Check on the processor if SMX (Safer Mode Extensions) is supported. More...
UINT32 | GetCpuIdentifier ()
Return CPU Identifier used to identify various CPU types. More...
UINT32 | GetCpuIdentifierWithCtdp (IN UINT16 SelectedCtdpLevel)
Return CPU Identifier used to identify various CPU types. More...
UINT32 | GetCpuUcodeRevision (VOID)
Returns the processor microcode revision of the processor installed in the system. More...
VOID | CpuWriteTraceHubAcpiBase (IN UINT64 TraceHubAcpiBase)
This function is to program Trace Hub ACPI base address to processor's MSR TRACE_HUB_STH_ACPIBAR_BASE. More...
BOOLEAN | IsC6dramSupported (VOID)
Detect if C6DRAM supported or not by reading it from PCODE mailbox. More...
CPU_GENERATION | GetCpuGeneration (VOID)
Get processor generation. More...
UINT16 | GetEnabledCoreCount (VOID)
This function returns Number of enabled cores in the package. More...
UINT16 | GetEnabledThreadCount (VOID)
This function returns Number of enabled Threads in the package. More...
BOOLEAN | IsSecondaryThread (VOID)
Check if this is non-core processor - HT AP thread. More...
BOOLEAN | IsValiduCodeEntry (VOID)
This function checks whether uCode loaded from FIT. More...
BOOLEAN | IsPfatEnabled (VOID)
Return if CPU supports PFAT. More...
BOOLEAN | IsBiosGuardEnabled (VOID)
Is BIOS GUARD enabled. More...
BOOLEAN | IsItbmSupported (VOID)
Determine if CPU supports Intel Turbo Boost Max Technology 3.0 (ITBM). More...
BOOLEAN | IsOcSupported (VOID)
Determine if CPU supports Overclocking by reading the number of bins in MSR FLEX_RATIO (194h) More...
BOOLEAN | IsCoreRatioLimitSupported (VOID)
Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode. More...
BOOLEAN | IsXETdcTdpLimitSupported (VOID)
Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode. More...
BOOLEAN | IsTurboModeSupported (VOID)
Determine if CPU supports Turbo mode. More...
UINT32 | NumberOfCpuSocketsPopulated (VOID)
Returns number of CPUSockets.
BOOLEAN | IsPpinFeatureAvailable (VOID)
Determine if CPU supports PPIN (Protected Processor Inventory Number) More...
BOOLEAN | IsHwpSupported (VOID)
Determine if CPU supports Hardware P-States. More...
BOOLEAN | IsTimedMwaitSupported (VOID)
Determine if CPU supports Mwait. More...
BOOLEAN | IsLpmSupported (VOID)
Determine if CPU supports LPM. More...
BOOLEAN | IsConfigTdpSupported (VOID)
Determine if CPU supports ConfigTdp. More...
BOOLEAN | IsEnergyEfficientTurboSupported (VOID)
Determine if CPU supports Turbo mode. More...
BOOLEAN | IsHyperThreadingSupported (VOID)
Determine if CPU supports Hyper-Threading. More...
VOID | GetConfigTdpLevelsSupported (IN UINT8 *CtdpDownSupported, IN UINT8 *CtdpUpSupported)
Determines what Ctdp levels are supported on the silicon. More...
VOID | GetSubCStateSupported (IN UINT32 *MwaitEcx, IN UINT32 *MwaitEdx)
Determines what Ctdp levels are supported on the silicon. More...
UINT8 | GetCpuNumberofCores (VOID)
Determine Number of system supported cores. More...
EFI_STATUS | GetCpuSupportedCoresAndAtomCores (OUT UINT8 *NumberOfSupportedCores, OPTIONAL OUT UINT8 *NumberOfSupportedAtomCores OPTIONAL)
Determine Number of system supported cores. More...
EFI_STATUS | GetSupportedSocNorthAtomCores (OUT UINT8 *NumberOfSocNorthSupportedAtomCores)
Determine Number of system supported cores for Soc-North. More...
UINT8 | GetActiveSocNorthAtomCoreCount (VOID)
This function gets number of SOC Atom cores enabled in the platform. More...
VOID | GetSupportedCpuFeatures (IN UINT32 *CpuEcx)
Detect Supported CPU Features. More...
BOOLEAN | IsIntelProcessorTraceSupported (VOID)
Detect if Processor Trace supported or not. More...
CONST CHAR8 * | GetGenerationString (VOID)
Returns Generation string of the respective CPU. More...
CONST CHAR8 * | GetRevisionTable (VOID)
Returns Revision Table. More...
CONST CHAR8 * | GetSkuString (VOID)
Returns Sku String. More...
UINT8 | NiftyRockSupportLevel (VOID)
Returns PPAM version details to support Nifty Rock feature based on SKU. More...
VOID | GetBusRatio (OUT UINT8 *MaxBusRatio, OPTIONAL OUT UINT8 *MinBusRatio OPTIONAL)
This function return max and min bus ratio. More...
UINT8 | GetMaxEfficiencyRatio (VOID)
This function return max Efficiency Ratio. More...
UINT8 | GetMaxNonTurboRatio (VOID)
This function return max Non-Turbo Ratio. More...
UINT8 | GetConfigTdpLevels (VOID)
This function return the supported Config TDP Levels. More...
UINT32 | GetMaxSupportedPrmrrSize (VOID)
This function return the supported Prmmr Size. More...
UINT8 | GetMaxPhysicalAddressSize (VOID)
This function returns the supported Physical Address Size. More...
BOOLEAN | IsEdramEnable (VOID)
Return if Edram Enable. More...
BOOLEAN | IsSaVrSupport (VOID)
This function is used to detect if SA VR Support. More...
BOOLEAN | IsTmeSupported (VOID)
This function return if TME is supported. More...
BOOLEAN | IsSamplePart (VOID)
Return if the processor is a preproduction sample. More...
UINT16 | GetPackageTdp (VOID)
This function return Package TDP. More...

Variables

GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mSecondsToMsrValueMapTable [][2]
Table to convert Seconds into equivalent MSR values This table is used for PL1, Pl2 and RATL TDP Time Window programming.

Detailed Description

Header file for CpuPlatform Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPlatformLib.h.

Function Documentation

◆ CpuWriteTraceHubAcpiBase()

VOID CpuWriteTraceHubAcpiBase ( IN UINT64 TraceHubAcpiBase )

This function is to program Trace Hub ACPI base address to processor's MSR TRACE_HUB_STH_ACPIBAR_BASE.

Parameters
[in] TraceHubAcpiBase - Base address of Trace Hub ACPI Base address

◆ GetActiveSocNorthAtomCoreCount()

UINT8 GetActiveSocNorthAtomCoreCount ( VOID )

This function gets number of SOC Atom cores enabled in the platform.

Return values
Number of active soc atom core.

◆ GetBusRatio()

VOID GetBusRatio | ( | OUT UINT8 * | MaxBusRatio,
 |  | OPTIONAL OUT UINT8 *MinBusRatio | OPTIONAL
 | ) |  |

This function return max and min bus ratio.

Parameters
[out] | MaxBusRatio
[out] | MinBusRatio

◆ GetConfigTdpLevels()

UINT8 GetConfigTdpLevels ( VOID )

This function return the supported Config TDP Levels.

Return values
number of config TDP levels

◆ GetConfigTdpLevelsSupported()

VOID GetConfigTdpLevelsSupported | ( | IN UINT8 * | CtdpDownSupported,
 |  | IN UINT8 * | CtdpUpSupported
 | ) |  |

Determines what Ctdp levels are supported on the silicon.

Parameters
[in] | CtdpDownSupported | - Pointer to CtdpDownSupported
[in] | CtdpUpSupported | - Pointer to CtdpUpSupported
Return values
VOID

◆ GetCpuFamily()

CPU_FAMILY GetCpuFamily ( VOID )

Check CPU Type of the platform.

Return values
CPU_FAMILY CPU type

◆ GetCpuGeneration()

CPU_GENERATION GetCpuGeneration ( VOID )

Get processor generation.

Return values
CPU_GENERATION Returns the executing thread's processor generation.

◆ GetCpuIdentifier()

UINT32 GetCpuIdentifier ( )

Return CPU Identifier used to identify various CPU types.

Return values
CPU_IDENTIFIER CPU Identifier

◆ GetCpuIdentifierWithCtdp()

UINT32 GetCpuIdentifierWithCtdp ( IN UINT16 SelectedCtdpLevel )

Return CPU Identifier used to identify various CPU types.

Parameters
[in] SelectedCtdpLevel - Ctdp Level Selected in BIOS
Return values
CPU_IDENTIFIER CPU Identifier

◆ GetCpuNumberofCores()

UINT8 GetCpuNumberofCores ( VOID )

Determine Number of system supported cores.

Note: It's not suitable for the hybrid CPU platform.

Return values
Number of system supported cores.

◆ GetCpuSku()

UINT8 GetCpuSku ( VOID )

Return CPU Sku.

Return values
UINT8 CPU Sku

◆ GetCpuStepping()

CPU_STEPPING GetCpuStepping ( VOID )

Return Cpu stepping type.

Return values
CPU_STEPPING Cpu stepping type

◆ GetCpuSupportedCoresAndAtomCores()

EFI_STATUS GetCpuSupportedCoresAndAtomCores | ( | OUT UINT8 * | NumberOfSupportedCores,
 |  | OPTIONAL OUT UINT8 *NumberOfSupportedAtomCores | OPTIONAL
 | ) |  |

Determine Number of system supported cores.

Note: It's suitable for both hybrid CPU and Non-hybrid platform.

Parameters
[out] | *NumberOfSupportedCores | - variable that will store Maximum supported cores.
[out] | *NumberOfSupportedAtomCores | - variable that will store Maximum supported Atom cores.
Return values
EFI_SUCCESS | Get the supported core & atom cores.
EFI_UNSUPPORTED | Doesn't support to get the supported core & atom cores.

◆ GetCpuUcodeRevision()

UINT32 GetCpuUcodeRevision ( VOID )

Returns the processor microcode revision of the processor installed in the system.

Return values
Processor Microcode Revision

◆ GetEnabledCoreCount()

UINT16 GetEnabledCoreCount ( VOID )

This function returns Number of enabled cores in the package.

Return values
Number of enabled cores in the package.

◆ GetEnabledThreadCount()

UINT16 GetEnabledThreadCount ( VOID )

This function returns Number of enabled Threads in the package.

Return values
Number of enabled threads in the package.

◆ GetGenerationString()

CONST CHAR8* GetGenerationString ( VOID )

Returns Generation string of the respective CPU.

Return values
Character pointer of Generation string

◆ GetMaxEfficiencyRatio()

UINT8 GetMaxEfficiencyRatio ( VOID )

This function return max Efficiency Ratio.

Return values
Max efficiency ratio

◆ GetMaxNonTurboRatio()

UINT8 GetMaxNonTurboRatio ( VOID )

This function return max Non-Turbo Ratio.

Return values
Max Non-Turbo Ratio

◆ GetMaxPhysicalAddressSize()

UINT8 GetMaxPhysicalAddressSize ( VOID )

This function returns the supported Physical Address Size.

Return values
supported Physical Address Size.

◆ GetMaxSupportedPrmrrSize()

UINT32 GetMaxSupportedPrmrrSize ( VOID )

This function return the supported Prmmr Size.

Return values
Supported Prmrr Size

◆ GetPackageTdp()

UINT16 GetPackageTdp ( VOID )

This function return Package TDP.

Return values
Package TDP

◆ GetRevisionTable()

CONST CHAR8* GetRevisionTable ( VOID )

Returns Revision Table.

Return values
Character pointer of Revision Table String

◆ GetSkuString()

CONST CHAR8* GetSkuString ( VOID )

Returns Sku String.

Return values
Character pointer of Sku String

◆ GetSubCStateSupported()

VOID GetSubCStateSupported | ( | IN UINT32 * | MwaitEcx,
 |  | IN UINT32 * | MwaitEdx
 | ) |  |

Determines what Ctdp levels are supported on the silicon.

Parameters
[in] | MwaitEcx | - Pointer to MwaitEcx (CPUID_MONITOR_MWAIT_ECX)
[in] | MwaitEdx | - Pointer to MwaitEdx (CPUID_MONITOR_MWAIT_EDX)
Return values
VOID

◆ GetSupportedCpuFeatures()

VOID GetSupportedCpuFeatures ( IN UINT32 * CpuEcx )

Detect Supported CPU Features.

Parameters
[InOut] CpuEcx Pointer to CpuEcx (CPUID_VERSION_INFO_ECX).

◆ GetSupportedSocNorthAtomCores()

EFI_STATUS GetSupportedSocNorthAtomCores ( OUT UINT8 * NumberOfSocNorthSupportedAtomCores )

Determine Number of system supported cores for Soc-North.

Parameters
[out] *NumberOfSocNorthSupportedAtomCores - variable that will store Maximum supported Soc-North Atom cores.
Return values
EFI_SUCCESS | Get the supported core & atom cores.
EFI_UNSUPPORTED | Doesn't support to get the supported core & atom cores.

◆ IsBiosGuardEnabled()

BOOLEAN IsBiosGuardEnabled ( VOID )

Is BIOS GUARD enabled.

Return values
TRUE | BIOS GUARD is supported and enabled.
FALSE | BIOS GUARD is disabled.

◆ IsC6dramSupported()

BOOLEAN IsC6dramSupported ( VOID )

Detect if C6DRAM supported or not by reading it from PCODE mailbox.

Return values
TRUE | - Supported
FALSE | - Not Supported

◆ IsConfigTdpSupported()

BOOLEAN IsConfigTdpSupported ( VOID )

Determine if CPU supports ConfigTdp.

Return values
TRUE | ConfigTdp is supported and enabled.
FALSE | ConfigTdp is disabled.

◆ IsCoreRatioLimitSupported()

BOOLEAN IsCoreRatioLimitSupported ( VOID )

Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.

Return values
TRUE | Core Ratio Limit for the Turbo mode is supported and enabled.
FALSE | Core Ratio Limit for the Turbo mode is disabled.

◆ IsEdramEnable()

BOOLEAN IsEdramEnable ( VOID )

Return if Edram Enable.

Return values
TRUE | If Edram Enable
FALSE | If Edram Disable

◆ IsEnergyEfficientTurboSupported()

BOOLEAN IsEnergyEfficientTurboSupported ( VOID )

Determine if CPU supports Turbo mode.

Return values
TRUE | Efficiency Turbo mode is supported and enabled.
FALSE | Efficiency Turbo mode is disabled.

◆ IsHwpSupported()

BOOLEAN IsHwpSupported ( VOID )

Determine if CPU supports Hardware P-States.

Return values
TRUE | Hardware P-States is supported and enabled.
FALSE | Hardware P-States is disabled.

◆ IsHyperThreadingSupported()

BOOLEAN IsHyperThreadingSupported ( VOID )

Determine if CPU supports Hyper-Threading.

Return values
TRUE | Hyper-Threading is supported and enabled.
FALSE | Hyper-Threading is disabled.

◆ IsIntelProcessorTraceSupported()

BOOLEAN IsIntelProcessorTraceSupported ( VOID )

Detect if Processor Trace supported or not.

Return values
TRUE | IntelProcessorTrace is supported and enabled.
FALSE | IntelProcessorTrace is disabled.

◆ IsItbmSupported()

BOOLEAN IsItbmSupported ( VOID )

Determine if CPU supports Intel Turbo Boost Max Technology 3.0 (ITBM).

Return values
TRUE | ITBM is supported and enabled.
FALSE | ITBM is disabled.

◆ IsLpmSupported()

BOOLEAN IsLpmSupported ( VOID )

Determine if CPU supports LPM.

Return values
TRUE | LPM is supported and enabled.
FALSE | LPM is disabled.

◆ IsOcSupported()

BOOLEAN IsOcSupported ( VOID )

Determine if CPU supports Overclocking by reading the number of bins in MSR FLEX_RATIO (194h)

Return values
TRUE | OC is supported and enabled.
FALSE | OC is disabled.

◆ IsPfatEnabled()

BOOLEAN IsPfatEnabled ( VOID )

Return if CPU supports PFAT.

Return values
TRUE | If CPU Supports
FALSE | If CPU doesn't Supports

◆ IsPpinFeatureAvailable()

BOOLEAN IsPpinFeatureAvailable ( VOID )

Determine if CPU supports PPIN (Protected Processor Inventory Number)

Return values
TRUE | PPIN feature is available.
FALSE | PPIN feature is not available.

◆ IsSamplePart()

BOOLEAN IsSamplePart ( VOID )

Return if the processor is a preproduction sample.

Return values
TRUE | If the processor is a preproduction sample
FALSE | If the part is intended for production

◆ IsSaVrSupport()

BOOLEAN IsSaVrSupport ( VOID )

This function is used to detect if SA VR Support.

Return values
TRUE | SA VR Support
FALSE | Not Support

◆ IsSecondaryThread()

BOOLEAN IsSecondaryThread ( VOID )

Check if this is non-core processor - HT AP thread.

Return values
TRUE | if this is HT AP thread
FALSE | if this is core thread

◆ IsSmxSupported()

BOOLEAN IsSmxSupported ( VOID )

Check on the processor if SMX (Safer Mode Extensions) is supported.

Return values
TRUE | CPU supports SMX.
FALSE | CPU do not support SMX.

◆ IsTimedMwaitSupported()

BOOLEAN IsTimedMwaitSupported ( VOID )

Determine if CPU supports Mwait.

Return values
TRUE | Mwait is supported and enabled.
FALSE | Mwait is disabled.

◆ IsTmeSupported()

BOOLEAN IsTmeSupported ( VOID )

This function return if TME is supported.

Return values
TRUE | If TME is supported
FALSE | If TME is not supported

◆ IsTurboModeSupported()

BOOLEAN IsTurboModeSupported ( VOID )

Determine if CPU supports Turbo mode.

Return values
TRUE | Turbo mode is supported and enabled.
FALSE | Turbo mode is disabled.

◆ IsValiduCodeEntry()

BOOLEAN IsValiduCodeEntry ( VOID )

This function checks whether uCode loaded from FIT.

Return values
TRUE | - uCode loaded from FIT successful
FALSE | - Failed on FIT to load uCode

◆ IsXETdcTdpLimitSupported()

BOOLEAN IsXETdcTdpLimitSupported ( VOID )

Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.

Return values
TRUE | TDC/TDP Limit is supported and enabled.
FALSE | TDC/TDP Limit is disabled.

◆ NiftyRockSupportLevel()

UINT8 NiftyRockSupportLevel ( VOID )

Returns PPAM version details to support Nifty Rock feature based on SKU.

Return values
0 | Nifty Rock feature is not supported, No need to load PPAM.
11 | Nifty Rock feature is supported with PPAM Version 1.1.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPlatformLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
CpuPlatformLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for CpuPlatform Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _CPU_PLATFORM_LIB_H_
37 #define _CPU_PLATFORM_LIB_H_
38
39 #include <Uefi.h>
40 #include <CpuRegs.h>
41 #include <CpuGenInfo.h>
42 #include <CpuDataStruct.h>
43 #include <CpuPowerMgmt.h>
44
45 #define NO_NR_PPAM_SUPPORT 0
46 #define NR_PPAM_10_SUPPORT 10
47 #define NR_PPAM_11_SUPPORT 11
48 #define END_OF_TIMETABLE 0x3FF
49 #define ATOM_QUANTITY_IN_CLUSTER 4
50
51 ///
52 /// Table to convert Seconds into equivalent MSR values
53 /// This table is used for PL1, Pl2 and RATL TDP Time Window programming
54 ///
55 extern GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mSecondsToMsrValueMapTable[][2];
56
57 /**
58 Check CPU Type of the platform
59
60 @retval CPU_FAMILY CPU type
61 **/
62 CPU_FAMILY
63 EFIAPI
64 GetCpuFamily (
65 VOID
66 );
67
68 /**
69 Return Cpu stepping type
70
71 @retval CPU_STEPPING Cpu stepping type
72 **/
73 CPU_STEPPING
74 EFIAPI
75 GetCpuStepping (
76 VOID
77 );
78
79 /**
80 Return CPU Sku
81
82 @retval UINT8 CPU Sku
83 **/
84 UINT8
85 EFIAPI
86 GetCpuSku (
87 VOID
88 );
89
90 /**
91 Check on the processor if SMX (Safer Mode Extensions) is supported.
92
93 @retval TRUE CPU supports SMX.
94 @retval FALSE CPU do not support SMX.
95 **/
96 BOOLEAN
97 IsSmxSupported (
98 VOID
99 );
100
101 /**
102 Return CPU Identifier used to identify various CPU types
103
104 @retval CPU_IDENTIFIER CPU Identifier
105 **/
106 UINT32
107 GetCpuIdentifier (
108 );
109
110 /**
111 Return CPU Identifier used to identify various CPU types
112
113 @param[in] SelectedCtdpLevel - Ctdp Level Selected in BIOS
114
115 @retval CPU_IDENTIFIER CPU Identifier
116 **/
117 UINT32
118 GetCpuIdentifierWithCtdp (
119 IN UINT16 SelectedCtdpLevel
120 );
121
122 /**
123 Returns the processor microcode revision of the processor installed in the system.
124
125 @retval Processor Microcode Revision
126 **/
127 UINT32
128 GetCpuUcodeRevision (
129 VOID
130 );
131
132 /**
133 This function is to program Trace Hub ACPI base address to processor's MSR TRACE_HUB_STH_ACPIBAR_BASE.
134
135 @param[in] TraceHubAcpiBase - Base address of Trace Hub ACPI Base address
136 **/
137 VOID
138 EFIAPI
139 CpuWriteTraceHubAcpiBase (
140 IN UINT64 TraceHubAcpiBase
141 );
142
143 /**
144 Detect if C6DRAM supported or not by reading it from PCODE mailbox.
145
146 @retval TRUE - Supported
147 @retval FALSE - Not Supported
148 **/
149 BOOLEAN
150 IsC6dramSupported (
151 VOID
152 );
153
154 /**
155 Get processor generation
156
157 @retval CPU_GENERATION Returns the executing thread's processor generation.
158 **/
159 CPU_GENERATION
160 GetCpuGeneration (
161 VOID
162 );
163
164 /**
165 This function returns Number of enabled cores in the package.
166
167 @retval Number of enabled cores in the package.
168 **/
169 UINT16
170 GetEnabledCoreCount (
171 VOID
172 );
173
174 /**
175 This function returns Number of enabled Threads in the package.
176
177 @retval Number of enabled threads in the package.
178 **/
179 UINT16
180 GetEnabledThreadCount (
181 VOID
182 );
183
184 /**
185 Check if this is non-core processor - HT AP thread
186
187 @retval TRUE if this is HT AP thread
188 @retval FALSE if this is core thread
189 **/
190 BOOLEAN
191 IsSecondaryThread (
192 VOID
193 );
194
195 /**
196 This function checks whether uCode loaded from FIT.
197
198 @retval TRUE - uCode loaded from FIT successful
199 @retval FALSE - Failed on FIT to load uCode
200 **/
201 BOOLEAN
202 IsValiduCodeEntry (
203 VOID
204 );
205
206 /**
207 Return if CPU supports PFAT
208
209 @retval TRUE If CPU Supports
210 @retval FALSE If CPU doesn't Supports
211 **/
212 BOOLEAN
213 IsPfatEnabled (
214 VOID
215 );
216
217 /**
218 Is BIOS GUARD enabled.
219
220 @retval TRUE BIOS GUARD is supported and enabled.
221 @retval FALSE BIOS GUARD is disabled.
222 **/
223 BOOLEAN
224 IsBiosGuardEnabled (
225 VOID
226 );
227
228 /**
229 Determine if CPU supports Intel Turbo Boost Max Technology 3.0 (ITBM).
230
231 @retval TRUE ITBM is supported and enabled.
232 @retval FALSE ITBM is disabled.
233 **/
234 BOOLEAN
235 IsItbmSupported (
236 VOID
237 );
238
239 /**
240 Determine if CPU supports Overclocking by reading the number of bins in MSR FLEX_RATIO (194h)
241
242 @retval TRUE OC is supported and enabled.
243 @retval FALSE OC is disabled.
244 **/
245 BOOLEAN
246 IsOcSupported (
247 VOID
248 );
249
250 /**
251 Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.
252
253 @retval TRUE Core Ratio Limit for the Turbo mode is supported and enabled.
254 @retval FALSE Core Ratio Limit for the Turbo mode is disabled.
255 **/
256 BOOLEAN
257 IsCoreRatioLimitSupported (
258 VOID
259 );
260
261 /**
262 Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.
263
264 @retval TRUE TDC/TDP Limit is supported and enabled.
265 @retval FALSE TDC/TDP Limit is disabled.
266 **/
267 BOOLEAN
268 IsXETdcTdpLimitSupported (
269 VOID
270 );
271
272 /**
273 Determine if CPU supports Turbo mode.
274
275 @retval TRUE Turbo mode is supported and enabled.
276 @retval FALSE Turbo mode is disabled.
277 **/
278 BOOLEAN
279 IsTurboModeSupported (
280 VOID
281 );
282
283 /**
284 Returns number of CPUSockets.
285 **/
286 UINT32
287 NumberOfCpuSocketsPopulated (
288 VOID
289 );
290
291 /**
292 Determine if CPU supports PPIN (Protected Processor Inventory Number)
293
294 @retval TRUE PPIN feature is available.
295 @retval FALSE PPIN feature is not available.
296 **/
297 BOOLEAN
298 IsPpinFeatureAvailable (
299 VOID
300 );
301
302 /**
303 Determine if CPU supports Hardware P-States.
304
305 @retval TRUE Hardware P-States is supported and enabled.
306 @retval FALSE Hardware P-States is disabled.
307 **/
308 BOOLEAN
309 IsHwpSupported (
310 VOID
311 );
312
313 /**
314 Determine if CPU supports Mwait.
315
316 @retval TRUE Mwait is supported and enabled.
317 @retval FALSE Mwait is disabled.
318 **/
319 BOOLEAN
320 IsTimedMwaitSupported (
321 VOID
322 );
323
324 /**
325 Determine if CPU supports LPM.
326
327 @retval TRUE LPM is supported and enabled.
328 @retval FALSE LPM is disabled.
329 **/
330 BOOLEAN
331 IsLpmSupported (
332 VOID
333 );
334
335 /**
336 Determine if CPU supports ConfigTdp.
337
338 @retval TRUE ConfigTdp is supported and enabled.
339 @retval FALSE ConfigTdp is disabled.
340 **/
341 BOOLEAN
342 IsConfigTdpSupported (
343 VOID
344 );
345
346 /**
347 Determine if CPU supports Turbo mode.
348
349 @retval TRUE Efficiency Turbo mode is supported and enabled.
350 @retval FALSE Efficiency Turbo mode is disabled.
351 **/
352 BOOLEAN
353 IsEnergyEfficientTurboSupported (
354 VOID
355 );
356
357 /**
358 Determine if CPU supports Hyper-Threading
359
360 @retval TRUE Hyper-Threading is supported and enabled.
361 @retval FALSE Hyper-Threading is disabled.
362 **/
363 BOOLEAN
364 IsHyperThreadingSupported (
365 VOID
366 );
367
368 /**
369 Determines what Ctdp levels are supported on the silicon.
370
371 @param[in] CtdpDownSupported - Pointer to CtdpDownSupported
372 @param[in] CtdpUpSupported - Pointer to CtdpUpSupported
373
374 @retval VOID
375 **/
376 VOID GetConfigTdpLevelsSupported (
377 IN UINT8 *CtdpDownSupported,
378 IN UINT8 *CtdpUpSupported
379 );
380
381 /**
382 Determines what Ctdp levels are supported on the silicon.
383
384 @param[in] MwaitEcx - Pointer to MwaitEcx (CPUID_MONITOR_MWAIT_ECX)
385 @param[in] MwaitEdx - Pointer to MwaitEdx (CPUID_MONITOR_MWAIT_EDX)
386
387 @retval VOID
388 **/
389 VOID GetSubCStateSupported (
390 IN UINT32 *MwaitEcx,
391 IN UINT32 *MwaitEdx
392 );
393
394 /**
395 Determine Number of system supported cores.
396 Note: It's not suitable for the hybrid CPU platform.
397
398 @retval Number of system supported cores.
399 **/
400 UINT8
401 GetCpuNumberofCores (
402 VOID
403 );
404
405 /**
406 Determine Number of system supported cores.
407 Note: It's suitable for both hybrid CPU and Non-hybrid platform.
408
409 @param[out] *NumberOfSupportedCores - variable that will store Maximum supported cores.
410 @param[out] *NumberOfSupportedAtomCores - variable that will store Maximum supported Atom cores.
411
412 @retval EFI_SUCCESS Get the supported core & atom cores.
413 @retval EFI_UNSUPPORTED Doesn't support to get the supported core & atom cores.
414 **/
415 EFI_STATUS
416 GetCpuSupportedCoresAndAtomCores (
417 OUT UINT8 *NumberOfSupportedCores, OPTIONAL
418 OUT UINT8 *NumberOfSupportedAtomCores OPTIONAL
419 );
420
421 /**
422 Determine Number of system supported cores for Soc-North.
423
424 @param[out] *NumberOfSocNorthSupportedAtomCores - variable that will store Maximum supported Soc-North Atom cores.
425
426 @retval EFI_SUCCESS Get the supported core & atom cores.
427 @retval EFI_UNSUPPORTED Doesn't support to get the supported core & atom cores.
428 **/
429 EFI_STATUS
430 GetSupportedSocNorthAtomCores (
431 OUT UINT8 *NumberOfSocNorthSupportedAtomCores
432 );
433
434 /**
435 This function gets number of SOC Atom cores enabled in the platform.
436
437 @retval Number of active soc atom core.
438 **/
439 UINT8
440 GetActiveSocNorthAtomCoreCount (
441 VOID
442 );
443
444 /**
445 Detect Supported CPU Features
446
447 @param[InOut] CpuEcx Pointer to CpuEcx (CPUID_VERSION_INFO_ECX).
448 **/
449 VOID
450 GetSupportedCpuFeatures (
451 IN UINT32 *CpuEcx
452 );
453
454 /**
455 Detect if Processor Trace supported or not
456
457 @retval TRUE IntelProcessorTrace is supported and enabled.
458 @retval FALSE IntelProcessorTrace is disabled.
459 **/
460 BOOLEAN
461 IsIntelProcessorTraceSupported (
462 VOID
463 );
464
465
466 /**
467 Returns Generation string of the respective CPU
468
469 @retval Character pointer of Generation string
470 **/
471 CONST CHAR8*
472 GetGenerationString (
473 VOID
474 );
475
476 /**
477 Returns Revision Table
478
479 @retval Character pointer of Revision Table String
480 **/
481 CONST CHAR8*
482 GetRevisionTable (
483 VOID
484 );
485
486 /**
487 Returns Sku String
488
489 @retval Character pointer of Sku String
490 **/
491 CONST CHAR8*
492 GetSkuString (
493 VOID
494 );
495
496 /**
497 Returns PPAM version details to support Nifty Rock feature based on SKU.
498
499 @retval 0 Nifty Rock feature is not supported, No need to load PPAM.
500 @retval 11 Nifty Rock feature is supported with PPAM Version 1.1.
501 **/
502 UINT8
503 NiftyRockSupportLevel (
504 VOID
505 );
506
507 /**
508 This function return max and min bus ratio.
509
510 @param[out] MaxBusRatio
511 @param[out] MinBusRatio
512 **/
513 VOID
514 GetBusRatio (
515 OUT UINT8 *MaxBusRatio, OPTIONAL
516 OUT UINT8 *MinBusRatio OPTIONAL
517 );
518
519 /**
520 This function return max Efficiency Ratio.
521
522 @retval Max efficiency ratio
523 **/
524 UINT8
525 GetMaxEfficiencyRatio (
526 VOID
527 );
528
529 /**
530 This function return max Non-Turbo Ratio.
531
532 @retval Max Non-Turbo Ratio
533 **/
534 UINT8
535 GetMaxNonTurboRatio (
536 VOID
537 );
538
539 /**
540 This function return the supported Config TDP Levels.
541
542 @retval number of config TDP levels
543 **/
544 UINT8
545 GetConfigTdpLevels (
546 VOID
547 );
548
549 /**
550 This function return the supported Prmmr Size
551
552 @retval Supported Prmrr Size
553 **/
554 UINT32
555 GetMaxSupportedPrmrrSize (
556 VOID
557 );
558
559 /**
560 This function returns the supported Physical Address Size
561
562 @retval supported Physical Address Size.
563 **/
564 UINT8
565 GetMaxPhysicalAddressSize (
566 VOID
567 );
568
569 /**
570 Return if Edram Enable
571
572 @retval TRUE If Edram Enable
573 @retval FALSE If Edram Disable
574 **/
575 BOOLEAN
576 IsEdramEnable (
577 VOID
578 );
579
580 /**
581 This function is used to detect if SA VR Support
582
583 @retval TRUE SA VR Support
584 @retval FALSE Not Support
585 **/
586 BOOLEAN
587 IsSaVrSupport (
588 VOID
589 );
590
591 /**
592 This function return if TME is supported
593
594 @retval TRUE If TME is supported
595 @retval FALSE If TME is not supported
596 **/
597 BOOLEAN
598 IsTmeSupported (
599 VOID
600 );
601
602 /**
603 Return if the processor is a preproduction sample
604
605 @retval TRUE If the processor is a preproduction sample
606 @retval FALSE If the part is intended for production
607 **/
608 BOOLEAN
609 IsSamplePart (
610 VOID
611 );
612
613 /**
614 This function return Package TDP
615
616 @retval Package TDP
617 **/
618 UINT16
619 GetPackageTdp (
620 VOID
621 );
622
623 #endif
IsSaVrSupport
BOOLEAN IsSaVrSupport(VOID)
This function is used to detect if SA VR Support.
GetCpuNumberofCores
UINT8 GetCpuNumberofCores(VOID)
Determine Number of system supported cores.
GetCpuIdentifier
UINT32 GetCpuIdentifier()
Return CPU Identifier used to identify various CPU types.
GetConfigTdpLevelsSupported
VOID GetConfigTdpLevelsSupported(IN UINT8 *CtdpDownSupported, IN UINT8 *CtdpUpSupported)
Determines what Ctdp levels are supported on the silicon.
IsBiosGuardEnabled
BOOLEAN IsBiosGuardEnabled(VOID)
Is BIOS GUARD enabled.
mSecondsToMsrValueMapTable
GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mSecondsToMsrValueMapTable[][2]
Table to convert Seconds into equivalent MSR values This table is used for PL1, Pl2 and RATL TDP Time...
GetCpuSku
UINT8 GetCpuSku(VOID)
Return CPU Sku.
GetRevisionTable
CONST CHAR8 * GetRevisionTable(VOID)
Returns Revision Table.
IsEnergyEfficientTurboSupported
BOOLEAN IsEnergyEfficientTurboSupported(VOID)
Determine if CPU supports Turbo mode.
IsPpinFeatureAvailable
BOOLEAN IsPpinFeatureAvailable(VOID)
Determine if CPU supports PPIN (Protected Processor Inventory Number)
IsValiduCodeEntry
BOOLEAN IsValiduCodeEntry(VOID)
This function checks whether uCode loaded from FIT.
GetSubCStateSupported
VOID GetSubCStateSupported(IN UINT32 *MwaitEcx, IN UINT32 *MwaitEdx)
Determines what Ctdp levels are supported on the silicon.
IsSecondaryThread
BOOLEAN IsSecondaryThread(VOID)
Check if this is non-core processor - HT AP thread.
CpuDataStruct.h
This file declares various data structures used in CPU reference code.
IsIntelProcessorTraceSupported
BOOLEAN IsIntelProcessorTraceSupported(VOID)
Detect if Processor Trace supported or not.
CpuWriteTraceHubAcpiBase
VOID CpuWriteTraceHubAcpiBase(IN UINT64 TraceHubAcpiBase)
This function is to program Trace Hub ACPI base address to processor's MSR TRACE_HUB_STH_ACPIBAR_BASE...
GetEnabledCoreCount
UINT16 GetEnabledCoreCount(VOID)
This function returns Number of enabled cores in the package.
CpuPowerMgmt.h
This file contains define definitions specific to processor.
GetMaxEfficiencyRatio
UINT8 GetMaxEfficiencyRatio(VOID)
This function return max Efficiency Ratio.
GetCpuFamily
CPU_FAMILY GetCpuFamily(VOID)
Check CPU Type of the platform.
GetCpuSupportedCoresAndAtomCores
EFI_STATUS GetCpuSupportedCoresAndAtomCores(OUT UINT8 *NumberOfSupportedCores, OPTIONAL OUT UINT8 *NumberOfSupportedAtomCores OPTIONAL)
Determine Number of system supported cores.
IsHwpSupported
BOOLEAN IsHwpSupported(VOID)
Determine if CPU supports Hardware P-States.
IsTimedMwaitSupported
BOOLEAN IsTimedMwaitSupported(VOID)
Determine if CPU supports Mwait.
IsSamplePart
BOOLEAN IsSamplePart(VOID)
Return if the processor is a preproduction sample.
IsHyperThreadingSupported
BOOLEAN IsHyperThreadingSupported(VOID)
Determine if CPU supports Hyper-Threading.
GetSupportedCpuFeatures
VOID GetSupportedCpuFeatures(IN UINT32 *CpuEcx)
Detect Supported CPU Features.
CPU_GENERATION
CPU_GENERATION
Enums for CPU Generation.
Definition: CpuRegs.h:290
IsTmeSupported
BOOLEAN IsTmeSupported(VOID)
This function return if TME is supported.
GetMaxSupportedPrmrrSize
UINT32 GetMaxSupportedPrmrrSize(VOID)
This function return the supported Prmmr Size.
GetMaxNonTurboRatio
UINT8 GetMaxNonTurboRatio(VOID)
This function return max Non-Turbo Ratio.
CpuRegs.h
Register names for CPU registers.
IsCoreRatioLimitSupported
BOOLEAN IsCoreRatioLimitSupported(VOID)
Determine if CPU supports Programmable Core Ratio Limit for the Turbo mode.
GetCpuIdentifierWithCtdp
UINT32 GetCpuIdentifierWithCtdp(IN UINT16 SelectedCtdpLevel)
Return CPU Identifier used to identify various CPU types.
IsXETdcTdpLimitSupported
BOOLEAN IsXETdcTdpLimitSupported(VOID)
Determine if CPU supports Programmable TDC/TDP Limit for the Turbo mode.
IsItbmSupported
BOOLEAN IsItbmSupported(VOID)
Determine if CPU supports Intel Turbo Boost Max Technology 3.0 (ITBM).
IsSmxSupported
BOOLEAN IsSmxSupported(VOID)
Check on the processor if SMX (Safer Mode Extensions) is supported.
GetSupportedSocNorthAtomCores
EFI_STATUS GetSupportedSocNorthAtomCores(OUT UINT8 *NumberOfSocNorthSupportedAtomCores)
Determine Number of system supported cores for Soc-North.
GetBusRatio
VOID GetBusRatio(OUT UINT8 *MaxBusRatio, OPTIONAL OUT UINT8 *MinBusRatio OPTIONAL)
This function return max and min bus ratio.
IsOcSupported
BOOLEAN IsOcSupported(VOID)
Determine if CPU supports Overclocking by reading the number of bins in MSR FLEX_RATIO (194h)
GetCpuUcodeRevision
UINT32 GetCpuUcodeRevision(VOID)
Returns the processor microcode revision of the processor installed in the system.
GetActiveSocNorthAtomCoreCount
UINT8 GetActiveSocNorthAtomCoreCount(VOID)
This function gets number of SOC Atom cores enabled in the platform.
GetMaxPhysicalAddressSize
UINT8 GetMaxPhysicalAddressSize(VOID)
This function returns the supported Physical Address Size.
IsLpmSupported
BOOLEAN IsLpmSupported(VOID)
Determine if CPU supports LPM.
IsPfatEnabled
BOOLEAN IsPfatEnabled(VOID)
Return if CPU supports PFAT.
IsEdramEnable
BOOLEAN IsEdramEnable(VOID)
Return if Edram Enable.
IsTurboModeSupported
BOOLEAN IsTurboModeSupported(VOID)
Determine if CPU supports Turbo mode.
NumberOfCpuSocketsPopulated
UINT32 NumberOfCpuSocketsPopulated(VOID)
Returns number of CPUSockets.
NiftyRockSupportLevel
UINT8 NiftyRockSupportLevel(VOID)
Returns PPAM version details to support Nifty Rock feature based on SKU.
GetSkuString
CONST CHAR8 * GetSkuString(VOID)
Returns Sku String.
GetConfigTdpLevels
UINT8 GetConfigTdpLevels(VOID)
This function return the supported Config TDP Levels.
GetCpuStepping
CPU_STEPPING GetCpuStepping(VOID)
Return Cpu stepping type.
GetEnabledThreadCount
UINT16 GetEnabledThreadCount(VOID)
This function returns Number of enabled Threads in the package.
IsC6dramSupported
BOOLEAN IsC6dramSupported(VOID)
Detect if C6DRAM supported or not by reading it from PCODE mailbox.
GetCpuGeneration
CPU_GENERATION GetCpuGeneration(VOID)
Get processor generation.
GetGenerationString
CONST CHAR8 * GetGenerationString(VOID)
Returns Generation string of the respective CPU.
GetPackageTdp
UINT16 GetPackageTdp(VOID)
This function return Package TDP.
IsConfigTdpSupported
BOOLEAN IsConfigTdpSupported(VOID)
Determine if CPU supports ConfigTdp.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
Functions
CpuPolicyLib.h File Reference

Prototype of the CpuPolicy library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for CpuPolicyLib.h:

Go to the source code of this file.

Functions

VOID | CpuPreMemPrintPolicy (IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial out. More...
UINT16 | CpuGetPreMemConfigBlockTotalSize (VOID)
Get CPU PREMEM config block table total size. More...
EFI_STATUS | CpuAddPreMemConfigBlocks (IN VOID *ConfigBlockTableAddress)
CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks. More...
VOID | CpuPrintPolicy (IN SI_POLICY_PPI *SiPolicyPpi)
Print whole CPU config blocks of SiPolicyPpi and serial out. More...
UINT16 | CpuGetConfigBlockTotalSize (VOID)
Get CPU config block table total size. More...
EFI_STATUS | CpuAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
CpuAddConfigBlocks add all Cpu config blocks. More...

Detailed Description

Prototype of the CpuPolicy library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file CpuPolicyLib.h.

Function Documentation

◆ CpuAddConfigBlocks()

EFI_STATUS CpuAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

CpuAddConfigBlocks add all Cpu config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add CPU config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ CpuAddPreMemConfigBlocks()

EFI_STATUS CpuAddPreMemConfigBlocks ( IN VOID * ConfigBlockTableAddress )

CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add CPU PREMEM config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ CpuGetConfigBlockTotalSize()

UINT16 CpuGetConfigBlockTotalSize ( VOID )

Get CPU config block table total size.

Return values
Size of CPU config block table

◆ CpuGetPreMemConfigBlockTotalSize()

UINT16 CpuGetPreMemConfigBlockTotalSize ( VOID )

Get CPU PREMEM config block table total size.

Return values
Size of CPU PREMEM config block table

◆ CpuPreMemPrintPolicy()

VOID CpuPreMemPrintPolicy ( IN SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial out.

Parameters
[in] SiPreMemPolicyPpi The Si PreMem Policy PPI instance

◆ CpuPrintPolicy()

VOID CpuPrintPolicy ( IN SI_POLICY_PPI * SiPolicyPpi )

Print whole CPU config blocks of SiPolicyPpi and serial out.

Parameters
[in] SiPolicyPpi The SI Policy PPI instance
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
CpuPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the CpuPolicy library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _CPU_POLICY_LIB_H_
36 #define _CPU_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39
40 /**
41 Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial out.
42
43 @param[in] SiPreMemPolicyPpi The Si PreMem Policy PPI instance
44 **/
45 VOID
46 CpuPreMemPrintPolicy (
47 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
48 );
49
50 /**
51 Get CPU PREMEM config block table total size.
52
53 @retval Size of CPU PREMEM config block table
54 **/
55 UINT16
56 EFIAPI
57 CpuGetPreMemConfigBlockTotalSize (
58 VOID
59 );
60
61 /**
62 CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.
63
64 @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM config blocks
65
66 @retval EFI_SUCCESS The policy default is initialized.
67 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
68 **/
69 EFI_STATUS
70 EFIAPI
71 CpuAddPreMemConfigBlocks (
72 IN VOID *ConfigBlockTableAddress
73 );
74
75 /**
76 Print whole CPU config blocks of SiPolicyPpi and serial out.
77
78 @param[in] SiPolicyPpi The SI Policy PPI instance
79 **/
80 VOID
81 CpuPrintPolicy (
82 IN SI_POLICY_PPI *SiPolicyPpi
83 );
84
85 /**
86 Get CPU config block table total size.
87
88 @retval Size of CPU config block table
89 **/
90 UINT16
91 EFIAPI
92 CpuGetConfigBlockTotalSize (
93 VOID
94 );
95
96 /**
97 CpuAddConfigBlocks add all Cpu config blocks.
98
99 @param[in] ConfigBlockTableAddress The pointer to add CPU config blocks
100
101 @retval EFI_SUCCESS The policy default is initialized.
102 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
103 **/
104 EFI_STATUS
105 EFIAPI
106 CpuAddConfigBlocks (
107 IN VOID *ConfigBlockTableAddress
108 );
109
110 #endif // _PEI_CPU_POLICY_LIB_H_
CpuAddConfigBlocks
EFI_STATUS CpuAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
CpuAddConfigBlocks add all Cpu config blocks.
CpuGetConfigBlockTotalSize
UINT16 CpuGetConfigBlockTotalSize(VOID)
Get CPU config block table total size.
CpuGetPreMemConfigBlockTotalSize
UINT16 CpuGetPreMemConfigBlockTotalSize(VOID)
Get CPU PREMEM config block table total size.
CpuPreMemPrintPolicy
VOID CpuPreMemPrintPolicy(IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial out.
CpuAddPreMemConfigBlocks
EFI_STATUS CpuAddPreMemConfigBlocks(IN VOID *ConfigBlockTableAddress)
CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.
CpuPrintPolicy
VOID CpuPrintPolicy(IN SI_POLICY_PPI *SiPolicyPpi)
Print whole CPU config blocks of SiPolicyPpi and serial out.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPolicyProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
Classes
CpuPolicyProtocol.h File Reference

Protocol used for specifying platform related CPU information and policy setting. More...

Go to the source code of this file.

Classes

struct DXE_CPU_POLICY_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure the processor in the DXE phase. More...

Detailed Description

Protocol used for specifying platform related CPU information and policy setting.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file CpuPolicyProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPolicyProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
CpuPolicyProtocol.h
Go to the documentation of this file.
1 /** @file
2 Protocol used for specifying platform related CPU information and policy setting.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _CPU_POLICY_PROTOCOL_H_
36 #define _CPU_POLICY_PROTOCOL_H_
37
38 //
39 // DXE_CPU_POLICY_PROTOCOL revisions
40 //
41 #define DXE_CPU_POLICY_PROTOCOL_REVISION 7
42
43 extern EFI_GUID gDxeCpuPolicyProtocolGuid;
44
45 #pragma pack (push,1)
46
47 /**
48 The protocol allows the platform code to publish a set of configuration information that the
49 CPU drivers will use to configure the processor in the DXE phase.
50 This Policy Protocol needs to be initialized for CPU configuration.
51 @note The Protocol has to be published before processor DXE drivers are dispatched.
52
53 This member specifies the revision of the Cpu Policy protocol. This field is used to indicate backward
54 compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.
55
56 <b>Revision 1</b>:
57 - Initial version
58 <b>Revision 2</b>:
59 - Added DgrEnable to obtain DGR status from setup option.
60 <b>Revision 3</b>:
61 - Add SmmMsrSaveStateEnable, SmmUseDelayIndication, SmmUseBlockIndication, SmmUseSmmEnableIndication, SmmProcTraceEnable.
62 <b>Revision 4</b>:
63 - Added DgrSpaEnable to obtain DGR-SPA status from setup option.
64 <b>Revision 5</b>:
65 - Added DgrStateSaveProtect to obtain DGR State Save status from setup option.
66 <b>Revision 6</b>:
67 - Added DgrSkipOemExceptionHandler to Obtain DGR Skip OEM Exception Handler status from setup option.
68 <b>Revision 7</b>:
69 - Removed EnableDts.
70 **/
71 typedef struct {
72 /**
73 Policy to obtain DGR status from setup option.
74 - <b>0: DGR is disabled</b>.
75 - 1: DGR is enabled.
76 **/
77 UINT32 DgrEnable : 1;
78 /**
79 Policy to obtain DGR-SPA status from setup option.
80 - <b>0: DGR-SPA is disabled</b>.
81 - 1: DGR-SPA is enabled.
82 **/
83 UINT32 DgrSpaEnable : 1;
84 /**
85 Policy to obtain DGR State Save support status from setup option.
86 - <b>0: SMM can have Read/Write access to SMM State Save region </b>.
87 - 1: SMM State Save region access is protected.
88 **/
89 UINT32 DgrStateSaveProtect : 1;
90 /**
91 Policy to obtain DGR Skip OEM Exception Handler from setup option.
92 - <b>0: OEM exception handler will execute normal way in case of resource access violation</b>.
93 - 1: OEM Exception handler will be skipped and exceution continues in case of resource access volation.
94 **/
95 UINT32 DgrSkipOemExceptionHandler : 1;
96 UINT32 RsvdBit : 26; ///< Reserved bits, align to multiple 32;
97
98 UINT8 Revision; ///< Current revision of policy.
99 /**
100 Indidates if SMM Save State saved in MSRs.
101 if enabled, SMM Save State will use the MSRs instead of the memory.
102 - <b>0: FALSE</b> - SMM Save State will use the memory.
103 - 1: TRUE - SMM Save State will use the MSRs.
104 **/
105 UINT8 SmmMsrSaveStateEnable;
106 /**
107 Indidates if SMM Delay feature is supported.
108 - 0: FALSE - SMM Delay feature is not supported.
109 - <b>1: TRUE</b> - SMM Delay feature is supported.
110 **/
111 UINT8 SmmUseDelayIndication;
112 /**
113 Indidates if SMM Block feature is supported.
114 - 0: FALSE - SMM Block feature is not supported.
115 - <b>1: TRUE</b> - SMM Block feature is supported.
116 **/
117 UINT8 SmmUseBlockIndication;
118 /**
119 Indidates if SMM Enable/Disable feature is supported.
120 - 0: FALSE - SMM Enable/Disable feature is not supported.
121 - <b>1: TRUE</b> - SMM Enable/Disable feature is supported.
122 **/
123 UINT8 SmmUseSmmEnableIndication;
124 /**
125 Specifies if SMM Proccessor Trace will be Enabled.
126 - <b>0: FALSE</b> - SMM Proccessor Trace will be disabled.<BR>
127 - 1: TRUE - SMM Proccessor Trace will be enabled.<BR>
128 **/
129 UINT8 SmmProcTraceEnable;
130 UINT8 ReservedByte[6]; ///< Reserved bytes, align to multiple 8.
131 } DXE_CPU_POLICY_PROTOCOL;
132
133 #pragma pack (pop)
134
135 #endif
DXE_CPU_POLICY_PROTOCOL::RsvdBit
UINT32 RsvdBit
Reserved bits, align to multiple 32;.
Definition: CpuPolicyProtocol.h:96
DXE_CPU_POLICY_PROTOCOL::DgrEnable
UINT32 DgrEnable
Policy to obtain DGR status from setup option.
Definition: CpuPolicyProtocol.h:77
DXE_CPU_POLICY_PROTOCOL::SmmProcTraceEnable
UINT8 SmmProcTraceEnable
Specifies if SMM Proccessor Trace will be Enabled.
Definition: CpuPolicyProtocol.h:129
DXE_CPU_POLICY_PROTOCOL::DgrSpaEnable
UINT32 DgrSpaEnable
Policy to obtain DGR-SPA status from setup option.
Definition: CpuPolicyProtocol.h:83
DXE_CPU_POLICY_PROTOCOL::SmmMsrSaveStateEnable
UINT8 SmmMsrSaveStateEnable
Indidates if SMM Save State saved in MSRs.
Definition: CpuPolicyProtocol.h:105
DXE_CPU_POLICY_PROTOCOL::Revision
UINT8 Revision
Current revision of policy.
Definition: CpuPolicyProtocol.h:98
DXE_CPU_POLICY_PROTOCOL::SmmUseDelayIndication
UINT8 SmmUseDelayIndication
Indidates if SMM Delay feature is supported.
Definition: CpuPolicyProtocol.h:111
DXE_CPU_POLICY_PROTOCOL::DgrStateSaveProtect
UINT32 DgrStateSaveProtect
Policy to obtain DGR State Save support status from setup option.
Definition: CpuPolicyProtocol.h:89
DXE_CPU_POLICY_PROTOCOL::DgrSkipOemExceptionHandler
UINT32 DgrSkipOemExceptionHandler
Policy to obtain DGR Skip OEM Exception Handler from setup option.
Definition: CpuPolicyProtocol.h:95
DXE_CPU_POLICY_PROTOCOL::SmmUseSmmEnableIndication
UINT8 SmmUseSmmEnableIndication
Indidates if SMM Enable/Disable feature is supported.
Definition: CpuPolicyProtocol.h:123
DXE_CPU_POLICY_PROTOCOL::SmmUseBlockIndication
UINT8 SmmUseBlockIndication
Indidates if SMM Block feature is supported.
Definition: CpuPolicyProtocol.h:117
DXE_CPU_POLICY_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the CPU driv...
Definition: CpuPolicyProtocol.h:71
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmt.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Macros
CpuPowerMgmt.h File Reference

This file contains define definitions specific to processor. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | PPM_EIST BIT0
Enhanced Intel Speed Step Technology.
#define | PPM_C1 BIT1
C1 enabled, supported.
#define | PPM_C1E BIT2
C1E enabled.
#define | PPM_C6 BIT4
C6 enabled, supported.
#define | PPM_C7 BIT5
C7 enabled, supported.
#define | PPM_C7S BIT6
C7S enabled, supported.
#define | PPM_TM BIT7
Adaptive Thermal Monitor.
#define | PPM_TURBO BIT8
Long duration turbo mode.
#define | PPM_CMP BIT9
CMP.
#define | PPM_TSTATES BIT10
CPU throttling states.
#define | PPM_MWAIT_EXT BIT11
MONITIOR/MWAIT Extensions supported.
#define | PPM_EEPST BIT12
Energy efficient P-State Feature enabled.
#define | PPM_TSTATE_FINE_GRAINED BIT13
Fine grained CPU Throttling states.
#define | PPM_CD BIT14
Deep Cstate - C8/C9/C10.
#define | PPM_TIMED_MWAIT BIT15
Timed Mwait support.
#define | C6_LONG_LATENCY_ENABLE BIT16
1=C6 Long and Short,0=C6 Short only
#define | C7_LONG_LATENCY_ENABLE BIT17
1=C7 Long and Short,0=C7 Short only
#define | C7s_LONG_LATENCY_ENABLE BIT18
1=C7s Long and Short,0=C7s Short only
#define | PPM_C8 BIT19
1= C8 enabled/supported
#define | PPM_C9 BIT20
1= C9 enabled/supported
#define | PPM_C10 BIT21
1= C10 enabled/supported
#define | PPM_HWP BIT22
1= HWP enabled/supported
#define | PPM_OC_UNLOCKED BIT24
1= Overclocking fully unlocked
#define | PPM_TURBO_BOOST_MAX BIT25
1= Intel Turbo Boost Max Technology 3.0
#define | PPM_C_STATES 0x72
PPM_C1 + PPM_C6 + PPM_C7 + PPM_C7S.
#define | MB_POWER_LIMIT1_TIME_DEFAULT 28
For Mobile and Halo, default PL1 time window value is 28 seconds.
#define | DT_POWER_LIMIT1_TIME_DEFAULT 28
For Desktop, default PL1 time window value is 28 second.
#define | TPSS_FVID_MAX_STATES 40
Limit the number of P-states for different generation OS.
#define | N_HDC_SUPPORT 0
HDC Definitions.

Detailed Description

This file contains define definitions specific to processor.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmt.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmt.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
CpuPowerMgmt.h
Go to the documentation of this file.
1 /** @file
2 This file contains define definitions specific to processor
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _POWER_MGMT_DEFINITIONS_H_
36 #define _POWER_MGMT_DEFINITIONS_H_
37
38 #define CSTATE_SUPPORTED 0x1
39 #define ENHANCED_CSTATE_SUPPORTED 0x2
40 #define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
41 #define C6_C7_LONG_LATENCY_SUPPORTED 0x02
42 #define C7s_SHORT_LATENCY_SUPPORTED 0x03
43 #define C7s_LONG_LATENCY_SUPPORTED 0x04
44 //
45 // Voltage offset definitions
46 //
47 #define OC_LIB_OFFSET_ADAPTIVE 0
48 #define OC_LIB_OFFSET_OVERRIDE 1
49 //
50 // Platform Power Management Flags Bit Definitions:
51 // These defines are also used in CPU0CST.ASL to check platform configuration
52 // and build C-state table accordingly.
53 //
54 #ifdef __GNUC__
55 //
56 // @todo Add workaround for GCC build, In GCC build the BIT can not be changed to value by GCC (ex: BIT0 can not be changed to 0x1)
57 //
58 #define PPM_EIST 0x1 ///< BIT 0 : Enhanced Intel Speed Step Technology.
59 #define PPM_C1 0x2 ///< BIT 1 : C1 enabled, supported.
60 #define PPM_C1E 0x4 ///< BIT 2 : C1E enabled.
61 #define PPM_C6 0x10 ///< BIT 4 : C6 enabled, supported.
62 #define PPM_C7 0x20 ///< BIT 5 : C7 enabled, supported.
63 #define PPM_C7S 0x40 ///< BIT 6 : C7S enabled, supported
64 #define PPM_TM 0x80 ///< BIT 7 : Adaptive Thermal Monitor.
65 #define PPM_TURBO 0x100 ///< BIT 8 : Long duration turbo mode
66 #define PPM_CMP 0x200 ///< BIT 9 : CMP.
67 #define PPM_TSTATES 0x400 ///< BIT 10: CPU throttling states
68 #define PPM_MWAIT_EXT 0x800 ///< BIT 11: MONITIOR/MWAIT Extensions supported.
69 #define PPM_EEPST 0x1000 ///< BIT 12: Energy efficient P-State Feature enabled
70 #define PPM_TSTATE_FINE_GRAINED 0x2000 ///< BIT 13: Fine grained CPU Throttling states
71 #define PPM_CD 0x4000 ///< BIT 14: Deep Cstate - C8/C9/C10
72 #define PPM_TIMED_MWAIT 0x8000 ///< BIT 15: Timed Mwait support
73 #define C6_LONG_LATENCY_ENABLE 0x10000 ///< BIT 16: 1=C6 Long and Short,0=C6 Short only
74 #define C7_LONG_LATENCY_ENABLE 0x20000 ///< BIT 17: 1=C7 Long and Short,0=C7 Short only
75 #define C7s_LONG_LATENCY_ENABLE 0x40000 ///< BIT 18: 1=C7s Long and Short,0=C7s Short only
76 #define PPM_C8 0x80000 ///< Bit 19: 1= C8 enabled/supported
77 #define PPM_C9 0x100000 ///< Bit 20: 1= C9 enabled/supported
78 #define PPM_C10 0x200000 ///< Bit 21: 1= C10 enabled/supported
79 #define PPM_HWP 0x400000 ///< Bit 22: 1= HWP enabled/supported
80 #define PPM_OC_UNLOCKED 0x1000000 ///< Bit 24: 1= Overclocking fully uncloked
81 #define PPM_TURBO_BOOST_MAX 0x2000000 ///< Bit 25: 1= Intel Turbo Boost Max Technology 3.0.
82 #else
83 #define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Technology.
84 #define PPM_C1 BIT1 ///< C1 enabled, supported.
85 #define PPM_C1E BIT2 ///< C1E enabled.
86 #define PPM_C6 BIT4 ///< C6 enabled, supported.
87 #define PPM_C7 BIT5 ///< C7 enabled, supported.
88 #define PPM_C7S BIT6 ///< C7S enabled, supported
89 #define PPM_TM BIT7 ///< Adaptive Thermal Monitor.
90 #define PPM_TURBO BIT8 ///< Long duration turbo mode
91 #define PPM_CMP BIT9 ///< CMP.
92 #define PPM_TSTATES BIT10 ///< CPU throttling states
93 #define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supported.
94 #define PPM_EEPST BIT12 ///< Energy efficient P-State Feature enabled
95 #define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling states
96 #define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10
97 #define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support
98 #define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=C6 Long and Short,0=C6 Short only
99 #define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=C7 Long and Short,0=C7 Short only
100 #define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=C7s Long and Short,0=C7s Short only
101 #define PPM_C8 BIT19 ///< 1= C8 enabled/supported
102 #define PPM_C9 BIT20 ///< 1= C9 enabled/supported
103 #define PPM_C10 BIT21 ///< 1= C10 enabled/supported
104 #define PPM_HWP BIT22 ///< 1= HWP enabled/supported
105 #define PPM_OC_UNLOCKED BIT24 ///< 1= Overclocking fully unlocked
106 #define PPM_TURBO_BOOST_MAX BIT25 ///< 1= Intel Turbo Boost Max Technology 3.0
107 #endif
108
109 #define PPM_C_STATES 0x72 ///< PPM_C1 + PPM_C6 + PPM_C7 + PPM_C7S
110
111
112 //
113 // The following definitions are based on assumed location for the ACPI
114 // Base Address. Modify as necessary base on platform-specific requirements.
115 //
116 #define PCH_ACPI_PBLK 0x1810
117 #define PCH_ACPI_LV2 0x1814
118 #define PCH_ACPI_LV3 0x1815
119 #define PCH_ACPI_LV4 0x1816
120 #define PCH_ACPI_LV6 0x1818
121 #define PCH_ACPI_LV5 0x1817
122 #define PCH_ACPI_LV7 0x1819
123
124 //
125 // C-State Latency (us):
126 // Though _CST object is core level, it is recommended that System BIOS report the
127 // Package level C state latencies, so that Operating System can account for worst case
128 // latency before using a specific C state. Unlike legacy platforms,
129 // BIOS is no longer required to program the C_STATE_LATENCYCONTROL_n MSRs (0x60B, 0x60C, 0x633, 0x634, 0x635).
130 //
131 #define C1_LATENCY 1
132 #define C6_LATENCY 127
133 #define C7_LATENCY 253
134 #define C8_LATENCY 260
135 #define C9_LATENCY 487
136 #define C10_LATENCY 1048
137
138 //
139 // C-State Power (mW)
140 //
141 #define C1_POWER 0x3E8
142 #define C3_POWER 0x1F4
143 #define C6_POWER 0x15E
144 #define C7_POWER 0xC8
145 #define C8_POWER 0xC8
146 #define C9_POWER 0xC8
147 #define C10_POWER 0xC8
148
149 #define MAX_POWER_LIMIT_1_TIME_IN_SECONDS 32767
150 #ifndef AUTO
151 #define AUTO 0
152 #endif
153 #define END_OF_TABLE 0xFF
154
155 #define CONFIG_TDP_DOWN 1
156 #define CONFIG_TDP_UP 2
157 #define CONFIG_TDP_DEACTIVATE 0xFF
158 //
159 // MMIO definitions
160 //
161 #define MMIO_DDR_RAPL_LIMIT 0x58E0
162 #define MMIO_TURBO_POWER_LIMIT 0x59A0
163 #define MMIO_TURBO_POWER_LIMIT_HIGH 0x59A4
164
165 #define MAX_OVERCLOCKING_BINS 0x7
166
167 ///
168 /// For Mobile and Halo, default PL1 time window value is 28 seconds.
169 ///
170 #define MB_POWER_LIMIT1_TIME_DEFAULT 28
171 ///
172 /// For Desktop, default PL1 time window value is 28 second
173 ///
174 #define DT_POWER_LIMIT1_TIME_DEFAULT 28
175
176 #define POWER_LIMIT1_TIME_56_SEC 56
177
178 #define PROCESSOR_FLAVOR_MOBILE 0x04
179 #define PROCESSOR_FLAVOR_DESKTOP 0x00
180 #define PROCESSOR_FLAVOR_MASK (BIT3 | BIT2)
181
182 //
183 // Power definitions (Based on EMTS V1.0 for standard voltage 2.4-2.6 GHz dual-core parts.)
184 //
185 #define FVID_MAX_POWER 35000
186 #define FVID_TURBO_POWER 35000
187 #define FVID_SUPERLFM_POWER 12000
188 //
189 // Power definitions for LFM and Turbo mode TBD.
190 //
191 #define FVID_MIN_POWER 15000
192
193 ///
194 /// Limit the number of P-states for different generation OS.
195 ///
196 #define TPSS_FVID_MAX_STATES 40
197 #define LPSS_FVID_MAX_STATES 16
198
199 #define READ_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000015
200 #define WRITE_PL1_DUTY_CYCLE_CLAMP_ENABLE 0x00000016
201
202 #define SVID_GET_REGISTER 0x80001018
203 #define SVID_SET_REGISTER 0x80001118
204 #define SVID_SET_EXCLUSIVE 0x80001218
205 #define SVID_READ_REG_WHITELIST 0x80001518
206 #define SVID_WRITE_REG_WHITELIST 0x80001618
207
208
209 #define SVID_REGISTER_VR_ID_OFFSET 16
210 #define SVID_REGISTER_VR_ID_VIRTUAL_0 4
211 #define SVID_REGISTER_VR_ID_VIRTUAL_1 5
212 #define SVID_REGISTER_ADDR_OFFSET 20
213 #define SVID_WHITELIST_DWORD_OFFSET 20
214
215 #define SVID_EXCLUSIVE_DISABLE 0
216 #define SVID_EXCLUSIVE_ENABLE 1
217
218 #define CPU_TDP_5_WATTS 500
219 #define CPU_TDP_6_WATTS 600
220 #define CPU_TDP_7_WATTS 700
221 #define CPU_TDP_9_WATTS 900
222 #define CPU_TDP_15_WATTS 1500
223 #define CPU_TDP_10_WATTS 1000
224 #define CPU_TDP_11_WATTS 1100
225 #define CPU_TDP_12_WATTS 1200
226 #define CPU_TDP_13_WATTS 1300
227 #define CPU_TDP_25_WATTS 2500
228 #define CPU_TDP_28_WATTS 2800
229 #define CPU_TDP_35_WATTS 3500
230 #define CPU_TDP_45_WATTS 4500
231 #define CPU_TDP_46_WATTS 4600
232 #define CPU_TDP_55_WATTS 5500
233 #define CPU_TDP_58_WATTS 5800
234 #define CPU_TDP_60_WATTS 6000
235 #define CPU_TDP_63_WATTS 6300
236 #define CPU_TDP_65_WATTS 6500
237 #define CPU_TDP_80_WATTS 8000
238 #define CPU_TDP_91_WATTS 9100
239 #define CPU_TDP_95_WATTS 9500
240 #define CPU_TDP_120_WATTS 12000
241 #define CPU_TDP_125_WATTS 12500
242 #define CPU_TDP_150_WATTS 15000
243
244
245 ///
246 /// HDC Definitions
247 ///
248 #define N_HDC_SUPPORT 0
249 #define B_HDC_SUPPORT BIT0
250
251 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtBasicConfig.h File Reference

  • Intel
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Classes
CpuPowerMgmtBasicConfig.h File Reference

CPU Power Management Basic Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_BASIC_CONFIG
CPU Power Management Basic Configuration Structure. More...

Detailed Description

CPU Power Management Basic Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtBasicConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtBasicConfig.h Source File

  • Intel
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  • Include
  • ConfigBlock
CpuPowerMgmtBasicConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Basic Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_
36 #define _CPU_POWER_MGMT_BASIC_CONFIG_H_
37
38 #define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 6
39
40 extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;
41
42 #ifndef TURBO_RATIO_LIMIT_ARRAY_SIZE
43 #define TURBO_RATIO_LIMIT_ARRAY_SIZE 8
44 #endif
45
46 #pragma pack (push,1)
47
48 /**
49 CPU Power Management Basic Configuration Structure.
50
51 <b>Revision 1</b>:
52 - Initial version.
53 <b>Revision 2</b>:
54 - Changed EnableItbm default to be disable
55 - Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driver
56 <b>Revision 3</b>:
57 - Add ApplyConfigTdp for TDP initialization settings based on non-cTDP or cTDP
58 <b>Revision 4</b>:
59 - Add Hwp Lock support
60 <b>Revision 5</b>:
61 - Add TurboRatioLimitRatio, TurboRatioLimitNumCore, AtomTurboRatioLimitRatio and AtomTurboRatioLimitNumCore
62 <b>Revision 6</b>:
63 - Add DualTauBoost
64 <b>Revision 7</b>:
65 - Changed EnableItbm default to be enable
66 **/
67 typedef struct {
68 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
69 /**
70 Sets the boot frequency starting from reset vector.
71 - 0: Maximum battery performance.
72 - 1: Maximum non-turbo performance.
73 - <b>2: Turbo performance.</b>
74 @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
75 **/
76 UINT32 BootFrequency : 2; //@deprecated
77 UINT32 SkipSetBootPState : 1; ///< Choose whether to skip SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
78 /**
79 Enable or Disable Intel Speed Shift Technology.
80 Enabling allows for processor control of P-state transitions.
81 0: Disable; <b>1: Enable;</b> Bit 1 is ignored.
82 @note Currently this feature is recommended to be enabled only on win10
83 **/
84 UINT32 Hwp : 2;
85 /**
86 Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
87 HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency.
88 This allows for increased package level C6 residency.
89 @note Currently this feature is recommended to be enabled only on win10
90 **/
91 UINT32 HdcControl : 2;
92 UINT32 PowerLimit2 : 1; ///< Enable or Disable short duration Power Limit (PL2). 0: Disable; <b>1: Enable</b>
93 UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; <b>0: Disable</b>; 1: Enable (Lock).
94 UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. <b>Default: 0</b>.
95 UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615h lock; <b>0: Disable</b>; 1: Enable (Lock).
96 UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601h lock; <b>0: Disable</b>; 1: Enable (Lock).
97 /**
98 Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
99 For Y SKU, the recommended default for this policy is <b>1: Enabled</b>, which indicates throttling below P1 is allowed.
100 For all other SKUs the recommended default are <b>0: Disabled</b>.
101 **/
102 UINT32 TccOffsetClamp : 1;
103 UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: Disabled; <b>1: Enabled (Lock)</b>.
104 UINT32 TurboMode : 1; ///< Enable or Disable Turbo Mode. Disable; <b>1: Enable</b>
105 UINT32 HwpInterruptControl : 1; ///< Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; <b>0: Disable</b>; 1: Enable.
106 UINT32 ApplyConfigTdp : 1; ///< Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; <b>1: cTDP</b>.
107 UINT32 HwpLock : 1; ///< HWP Lock in MISC PWR MGMT MSR 1AAh; <b>0: Disable</b>; 1: Enable (Lock).
108 /**
109 Dual Tau Base Performance Boost support. This will improve platform performance for desktop sku.
110 When enabled, it exposes 2 MMIO PL1 and MMIO Tau registers, and also provides the default value.
111 @note: This is only applicable for Desktop 35W/65W/125W sku.
112 @note: When this is enabled, it will override the settings in policys PowerLimit1, PowerLimit1Time, PowerLimit2Power.
113 <b>0: Disable</b>; 1: Enable
114 **/
115 UINT32 DualTauBoost : 1;
116 UINT32 RsvdBits : 6; ///< Reserved for future use.
117
118 /**
119 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins.
120 Default value is from hardware register MSR 0x1AD.
121 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
122 - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
123 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
124 **/
125 UINT8 OneCoreRatioLimit;
126 /**
127 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.
128 Default value is from hardware register MSR 0x1AD.
129 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
130 - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
131 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
132 **/
133 UINT8 TwoCoreRatioLimit;
134 /**
135 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.
136 Default value is from hardware register MSR 0x1AD.
137 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
138 - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
139 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
140 **/
141 UINT8 ThreeCoreRatioLimit;
142 /**
143 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.
144 Default value is from hardware register MSR 0x1AD.
145 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
146 - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
147 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
148 **/
149 UINT8 FourCoreRatioLimit;
150 /**
151 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.
152 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
153 - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
154 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
155 **/
156 UINT8 FiveCoreRatioLimit;
157 /**
158 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.
159 Default value is from hardware register MSR 0x1AD.
160 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
161 - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
162 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
163 **/
164 UINT8 SixCoreRatioLimit;
165 /**
166 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.
167 Default value is from hardware register MSR 0x1AD.
168 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
169 - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
170 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
171 **/
172 UINT8 SevenCoreRatioLimit;
173 /**
174 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.
175 Default value is from hardware register MSR 0x1AD.
176 Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
177 - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
178 - This policy is for platforms only support MSR 0x1AD without MSR 0x1AE support.
179 **/
180 UINT8 EightCoreRatioLimit;
181 /**
182 TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated.
183 TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius.
184 For Y SKU, the recommended default for this policy is <b>10</b>
185 For all other SKUs the recommended default are <b>0</b>, causing TCC to activate at TCC Activation temperature.
186 @note The policy is recommended for validation purpose only.
187 **/
188 UINT8 TccActivationOffset;
189 /**
190 Intel Turbo Boost Max Technology 3.0
191 Enabling it on processors with OS support will allow OS to exploit the diversity in max turbo frequency of the cores.
192 <b>0: Disable</b>; 1: Enable;
193 **/
194 UINT8 EnableItbm : 1;
195 /**
196 @deprecated: Platform doesn't have Intel Turbo Boost Max Technology 3.0 Driver
197 Enabling it will load the driver upon ACPI device with HID = INT3510.
198 <b> 0: Disable;</b> 1: Enable;
199 **/
200 UINT8 EnableItbmDriver : 1;
201 /**
202 Per Core P State OS control mode
203 Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1. When set, the highest core request is used for all other core requests.
204 0: Disable;<b> 1: Enable;</b>
205 **/
206 UINT8 EnablePerCorePState : 1;
207 /**
208 HwP Autonomous Per Core P State
209 Disabling will set Bit 30 = 1, command 0x11. When set, autonomous will request the same value
210 for all cores all the time.
211 0: Disable;<b> 1: Enable;</b>
212 **/
213 UINT8 EnableHwpAutoPerCorePstate : 1;
214 /**
215 HwP Autonomous EPP grouping.
216 Disabling will set Bit 29 = 1, command 0x11. When set, autonomous will not necesarrily request the same value
217 for all cores with same EPP.
218 Enabling will clean Bit 29 = 0, command 0x11. Autonomous will request same values for all cores with same EPP.
219 0: Disable;<b> 1: Enable;</b>
220 **/
221 UINT8 EnableHwpAutoEppGrouping : 1;
222 /**
223 EPB override over PECI
224 Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
225 This will allow OOB EPB PECI override control.
226 <b>0: Disable;</b> 1: Enable;
227 **/
228 UINT8 EnableEpbPeciOverride : 1;
229 /**
230 Support for Fast MSR for IA32_HWP_REQUEST.
231 On systems with HwP enabled, if this feature is available as indicated by MSR 0x65F[0] = 1,
232 set MSR 0x657[0] = 1.
233 0: Disable; <b> 1: Enable;</b>
234 **/
235 UINT8 EnableFastMsrHwpReq : 1;
236 UINT8 ReservedBits1 : 1; ///< Reserved for future use.
237 UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
238 UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default
239 /**
240 Package Long duration turbo mode power limit (PL1).
241 Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
242 **/
243 UINT16 PowerLimit1;
244 /**
245 Package Short duration turbo mode power limit (PL2). Allows for short excursions above TDP power limit.
246 Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
247 **/
248 UINT16 PowerLimit2Power;
249 /**
250 Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.
251 <b>Default: 0</b>. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
252 **/
253 UINT16 PowerLimit3;
254 /**
255 Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded.
256 Power is premptively lowered before limit is reached. <b>Default: 0</b>. Range 0-65535.
257 Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
258 **/
259 UINT16 PowerLimit4;
260 /**
261 Package Long duration turbo mode power limit (PL1) time window in seconds.
262 Used in calculating the average power over time.
263 Mobile: <b> 28s</b>
264 Desktop: <b> 8s</b>
265 Range: 0 - 128s
266 **/
267 UINT32 PowerLimit1Time;
268 UINT32 PowerLimit3Time; ///< Package PL3 time window. Range from 3ms to 64ms.
269 /**
270 Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
271 For Y SKU, the recommended default for this policy is <b>5000: 5 seconds</b>, For all other SKUs the recommended default are <b>0: Disabled</b>
272 **/
273 UINT32 TccOffsetTimeWindowForRatl;
274 /**
275 Turbo Ratio Limit Ratio array, TurboRatioLimitRatio[7-0] will pair with TurboRatioLimitNumCore[7-0]
276 to determine the active core ranges for each frequency point.
277 Default value is from hardware register MSR 0x1AD.
278 Note:
279 - These policies are for platforms support MSR pair 0x1AD and 0x1AE.
280 **/
281 UINT8 TurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
282 /**
283 Turbo Ratio Limit Num Core array, TurboRatioLimitNumCore[7-0] will pair with TurboRatioLimitRatio[7-0]
284 to determine the active core ranges for each frequency point.
285 Default value is from hardware register MSR 0x1AE.
286 Note:
287 - These policies are for platforms support MSR pair 0x1AD and 0x1AE.
288 **/
289 UINT8 TurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
290 /**
291 ATOM Turbo Ratio Limit Ratio array, AtomTurboRatioLimitRatio[7-0] will pair with AtomTurboRatioLimitNumCore[7-0]
292 to determine the active core ranges for each frequency point.
293 Default value is from hardware register MSR 0x650.
294 Note:
295 - These policies are for platforms support ATOM MSR pair 0x650 and 0x651.
296 **/
297 UINT8 AtomTurboRatioLimitRatio[TURBO_RATIO_LIMIT_ARRAY_SIZE];
298 /**
299 ATOM Turbo Ratio Limit Num Core array, AtomTurboRatioLimitNumCore[7-0] will pair with AtomTurboRatioLimitRatio[7-0]
300 to determine the active core ranges for each frequency point.
301 Default value is from hardware register MSR 0x651.
302 Note:
303 - These policies are for platforms support ATOM MSR pair 0x650 and 0x651.
304 **/
305 UINT8 AtomTurboRatioLimitNumCore[TURBO_RATIO_LIMIT_ARRAY_SIZE];
306 } CPU_POWER_MGMT_BASIC_CONFIG;
307
308 #pragma pack (pop)
309
310 #endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_
CPU_POWER_MGMT_BASIC_CONFIG::OneCoreRatioLimit
UINT8 OneCoreRatioLimit
1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit.
Definition: CpuPowerMgmtBasicConfig.h:125
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3DutyCycle
UINT32 PowerLimit3DutyCycle
Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0.
Definition: CpuPowerMgmtBasicConfig.h:94
CPU_POWER_MGMT_BASIC_CONFIG::EnableFastMsrHwpReq
UINT8 EnableFastMsrHwpReq
Support for Fast MSR for IA32_HWP_REQUEST.
Definition: CpuPowerMgmtBasicConfig.h:235
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetLock
UINT32 TccOffsetLock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; 0: ...
Definition: CpuPowerMgmtBasicConfig.h:103
CPU_POWER_MGMT_BASIC_CONFIG
CPU Power Management Basic Configuration Structure.
Definition: CpuPowerMgmtBasicConfig.h:67
CPU_POWER_MGMT_BASIC_CONFIG::MinRingRatioLimit
UINT8 MinRingRatioLimit
Minimum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
Definition: CpuPowerMgmtBasicConfig.h:237
CPU_POWER_MGMT_BASIC_CONFIG::EightCoreRatioLimit
UINT8 EightCoreRatioLimit
8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:180
CPU_POWER_MGMT_BASIC_CONFIG::FiveCoreRatioLimit
UINT8 FiveCoreRatioLimit
5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:156
CPU_POWER_MGMT_BASIC_CONFIG::SkipSetBootPState
UINT32 SkipSetBootPState
Choose whether to skip SetBootPState function for all APs; 0: Do not skip; 1: Skip.
Definition: CpuPowerMgmtBasicConfig.h:77
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3Time
UINT32 PowerLimit3Time
Package PL3 time window. Range from 3ms to 64ms.
Definition: CpuPowerMgmtBasicConfig.h:268
CPU_POWER_MGMT_BASIC_CONFIG::Hwp
UINT32 Hwp
Enable or Disable Intel Speed Shift Technology.
Definition: CpuPowerMgmtBasicConfig.h:84
CPU_POWER_MGMT_BASIC_CONFIG::MaxRingRatioLimit
UINT8 MaxRingRatioLimit
Maximum Ring Ratio Limit. Range from 0 to Max Turbo Ratio. 0 = AUTO/HW Default.
Definition: CpuPowerMgmtBasicConfig.h:238
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetClamp
UINT32 TccOffsetClamp
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
Definition: CpuPowerMgmtBasicConfig.h:102
CPU_POWER_MGMT_BASIC_CONFIG::ReservedBits1
UINT8 ReservedBits1
Reserved for future use.
Definition: CpuPowerMgmtBasicConfig.h:236
CPU_POWER_MGMT_BASIC_CONFIG::HwpLock
UINT32 HwpLock
HWP Lock in MISC PWR MGMT MSR 1AAh; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:107
CPU_POWER_MGMT_BASIC_CONFIG::TccOffsetTimeWindowForRatl
UINT32 TccOffsetTimeWindowForRatl
Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
Definition: CpuPowerMgmtBasicConfig.h:273
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2Power
UINT16 PowerLimit2Power
Package Short duration turbo mode power limit (PL2).
Definition: CpuPowerMgmtBasicConfig.h:248
CPU_POWER_MGMT_BASIC_CONFIG::SixCoreRatioLimit
UINT8 SixCoreRatioLimit
6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:164
CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoEppGrouping
UINT8 EnableHwpAutoEppGrouping
HwP Autonomous EPP grouping.
Definition: CpuPowerMgmtBasicConfig.h:221
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4
UINT16 PowerLimit4
Package PL4 power limit.
Definition: CpuPowerMgmtBasicConfig.h:259
CPU_POWER_MGMT_BASIC_CONFIG::EnableEpbPeciOverride
UINT8 EnableEpbPeciOverride
EPB override over PECI Enable by sending pcode command 0x2b , subcommand 0x3 to 1.
Definition: CpuPowerMgmtBasicConfig.h:228
CPU_POWER_MGMT_BASIC_CONFIG::EnablePerCorePState
UINT8 EnablePerCorePState
Per Core P State OS control mode Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 = 1.
Definition: CpuPowerMgmtBasicConfig.h:206
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1Time
UINT32 PowerLimit1Time
Package Long duration turbo mode power limit (PL1) time window in seconds.
Definition: CpuPowerMgmtBasicConfig.h:267
CPU_POWER_MGMT_BASIC_CONFIG::TurboPowerLimitLock
UINT32 TurboPowerLimitLock
MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable; 1: Enable...
Definition: CpuPowerMgmtBasicConfig.h:93
CPU_POWER_MGMT_BASIC_CONFIG::HdcControl
UINT32 HdcControl
Hardware Duty Cycle Control configuration.
Definition: CpuPowerMgmtBasicConfig.h:91
CPU_POWER_MGMT_BASIC_CONFIG::EnableHwpAutoPerCorePstate
UINT8 EnableHwpAutoPerCorePstate
HwP Autonomous Per Core P State Disabling will set Bit 30 = 1, command 0x11.
Definition: CpuPowerMgmtBasicConfig.h:213
CPU_POWER_MGMT_BASIC_CONFIG::DualTauBoost
UINT32 DualTauBoost
Dual Tau Base Performance Boost support.
Definition: CpuPowerMgmtBasicConfig.h:115
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit4Lock
UINT32 PowerLimit4Lock
Package PL4 MSR 601h lock; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:96
CPU_POWER_MGMT_BASIC_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtBasicConfig.h:116
CPU_POWER_MGMT_BASIC_CONFIG::HwpInterruptControl
UINT32 HwpInterruptControl
Set HW P-State Interrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtBasicConfig.h:105
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit2
UINT32 PowerLimit2
Enable or Disable short duration Power Limit (PL2). 0: Disable; 1: Enable
Definition: CpuPowerMgmtBasicConfig.h:92
CPU_POWER_MGMT_BASIC_CONFIG::FourCoreRatioLimit
UINT8 FourCoreRatioLimit
4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:149
CPU_POWER_MGMT_BASIC_CONFIG::ApplyConfigTdp
UINT32 ApplyConfigTdp
Switch TDP applied setting based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP.
Definition: CpuPowerMgmtBasicConfig.h:106
CPU_POWER_MGMT_BASIC_CONFIG::BootFrequency
UINT32 BootFrequency
Sets the boot frequency starting from reset vector.
Definition: CpuPowerMgmtBasicConfig.h:76
CPU_POWER_MGMT_BASIC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtBasicConfig.h:68
CPU_POWER_MGMT_BASIC_CONFIG::EnableItbm
UINT8 EnableItbm
Intel Turbo Boost Max Technology 3.0 Enabling it on processors with OS support will allow OS to explo...
Definition: CpuPowerMgmtBasicConfig.h:194
CPU_POWER_MGMT_BASIC_CONFIG::TccActivationOffset
UINT8 TccActivationOffset
TCC Activation Offset.
Definition: CpuPowerMgmtBasicConfig.h:188
CPU_POWER_MGMT_BASIC_CONFIG::TurboMode
UINT32 TurboMode
Enable or Disable Turbo Mode. Disable; 1: Enable
Definition: CpuPowerMgmtBasicConfig.h:104
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3Lock
UINT32 PowerLimit3Lock
Package PL3 MSR 615h lock; 0: Disable; 1: Enable (Lock).
Definition: CpuPowerMgmtBasicConfig.h:95
CPU_POWER_MGMT_BASIC_CONFIG::EnableItbmDriver
UINT8 EnableItbmDriver
Definition: CpuPowerMgmtBasicConfig.h:200
CPU_POWER_MGMT_BASIC_CONFIG::ThreeCoreRatioLimit
UINT8 ThreeCoreRatioLimit
3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:141
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit1
UINT16 PowerLimit1
Package Long duration turbo mode power limit (PL1).
Definition: CpuPowerMgmtBasicConfig.h:243
CPU_POWER_MGMT_BASIC_CONFIG::TwoCoreRatioLimit
UINT8 TwoCoreRatioLimit
2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:133
CPU_POWER_MGMT_BASIC_CONFIG::SevenCoreRatioLimit
UINT8 SevenCoreRatioLimit
7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio...
Definition: CpuPowerMgmtBasicConfig.h:172
CPU_POWER_MGMT_BASIC_CONFIG::PowerLimit3
UINT16 PowerLimit3
Package PL3 power limit.
Definition: CpuPowerMgmtBasicConfig.h:253
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtCustomConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes | Macros | Typedefs
CpuPowerMgmtCustomConfig.h File Reference

CPU Power Managment Custom Config Block. More...

Go to the source code of this file.

Classes

struct | PPM_CUSTOM_RATIO_TABLE
This structure is used to describe the custom processor ratio table desired by the platform. More...
struct | _PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings. More...
struct | CPU_POWER_MGMT_CUSTOM_CONFIG
CPU Power Management Custom Configuration Structure. More...

Macros

#define | MAX_CUSTOM_RATIO_TABLE_ENTRIES 40
Defines the maximum number of custom ratio states supported.
#define | MAX_CUSTOM_CTDP_ENTRIES 3
Defines the maximum number of custom ConfigTdp entries supported. More...

Typedefs

typedef struct _PPM_CUSTOM_CTDP_TABLE PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.

Detailed Description

CPU Power Managment Custom Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtCustomConfig.h.

Macro Definition Documentation

◆ MAX_CUSTOM_CTDP_ENTRIES

#define MAX_CUSTOM_CTDP_ENTRIES 3

Defines the maximum number of custom ConfigTdp entries supported.

Warning
: Changing this define would cause DWORD alignment issues in policy structures.

Definition at line 54 of file CpuPowerMgmtCustomConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtCustomConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuPowerMgmtCustomConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Managment Custom Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
36 #define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
37
38 #define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuPowerMgmtCustomConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// Defines the maximum number of custom ratio states supported.
46 ///
47 #define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40
48 #define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16
49
50 ///
51 /// Defines the maximum number of custom ConfigTdp entries supported.
52 /// @warning: Changing this define would cause DWORD alignment issues in policy structures.
53 ///
54 #define MAX_CUSTOM_CTDP_ENTRIES 3
55
56 ///
57 /// This structure is used to describe the custom processor ratio table desired by the platform.
58 ///
59 typedef struct {
60 UINT8 MaxRatio; ///< The maximum ratio of the custom ratio table.
61 UINT8 NumberOfEntries; ///< The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
62 UINT8 Rsvd0[2]; ///< Reserved for DWORD alignment.
63 UINT32 Cpuid; ///< The CPU ID for which this custom ratio table applies.
64 UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table.
65 ///
66 /// If there are more than 16 total entries in the StateRatio table, then use these 16 entries to fill max 16 table.
67 /// @note If NumberOfEntries is 16 or less, or the first entry of this table is 0, then this table is ignored,
68 /// and up to the top 16 values from the StateRatio table is used instead.
69 ///
70 UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES];
71 #if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)
72 UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) % 4)]; ///< If needed, add padding for dword alignment.
73 #endif
74 } PPM_CUSTOM_RATIO_TABLE;
75
76 ///
77 /// PPM Custom ConfigTdp Settings
78 ///
79 typedef struct _PPM_CUSTOM_CTDP_TABLE {
80 UINT32 CustomPowerLimit1Time : 8; ///< Short term Power Limit time window value for custom cTDP level.
81 UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation Ratio for custom cTDP level.
82 UINT32 RsvdBits : 16; ///< Bits reserved for DWORD alignment.
83 UINT16 CustomPowerLimit1; ///< Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
84 UINT16 CustomPowerLimit2; ///< Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
85 } PPM_CUSTOM_CTDP_TABLE;
86
87 /**
88 CPU Power Management Custom Configuration Structure.
89
90 <b>Revision 1</b>:
91 - Initial version.
92 **/
93 typedef struct {
94 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
95 PPM_CUSTOM_RATIO_TABLE CustomRatioTable; ///< Custom Processor Ratio Table Instance
96 PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; ///< Custom ConfigTdp Settings Instance
97 UINT32 ConfigTdpLock : 1; ///< Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable.
98 UINT32 ConfigTdpBios : 1; ///< Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
99 UINT32 RsvdBits : 30; ///< Reserved for future use
100 } CPU_POWER_MGMT_CUSTOM_CONFIG;
101
102 #pragma pack (pop)
103
104 #endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
PPM_CUSTOM_RATIO_TABLE
This structure is used to describe the custom processor ratio table desired by the platform.
Definition: CpuPowerMgmtCustomConfig.h:59
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit1Time
UINT32 CustomPowerLimit1Time
Short term Power Limit time window value for custom cTDP level.
Definition: CpuPowerMgmtCustomConfig.h:80
_PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.
Definition: CpuPowerMgmtCustomConfig.h:79
PPM_CUSTOM_RATIO_TABLE::NumberOfEntries
UINT8 NumberOfEntries
The number of custom ratio state entries, ranges from 2 to 40 for a valid custom ratio table.
Definition: CpuPowerMgmtCustomConfig.h:61
PPM_CUSTOM_CTDP_TABLE
struct _PPM_CUSTOM_CTDP_TABLE PPM_CUSTOM_CTDP_TABLE
PPM Custom ConfigTdp Settings.
CPU_POWER_MGMT_CUSTOM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtCustomConfig.h:94
MAX_CUSTOM_RATIO_TABLE_ENTRIES
#define MAX_CUSTOM_RATIO_TABLE_ENTRIES
Defines the maximum number of custom ratio states supported.
Definition: CpuPowerMgmtCustomConfig.h:47
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit1
UINT16 CustomPowerLimit1
Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG....
Definition: CpuPowerMgmtCustomConfig.h:83
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PPM_CUSTOM_RATIO_TABLE::Cpuid
UINT32 Cpuid
The CPU ID for which this custom ratio table applies.
Definition: CpuPowerMgmtCustomConfig.h:63
CPU_POWER_MGMT_CUSTOM_CONFIG::ConfigTdpBios
UINT32 ConfigTdpBios
Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtCustomConfig.h:98
CPU_POWER_MGMT_CUSTOM_CONFIG::CustomRatioTable
PPM_CUSTOM_RATIO_TABLE CustomRatioTable
Custom Processor Ratio Table Instance.
Definition: CpuPowerMgmtCustomConfig.h:95
CPU_POWER_MGMT_CUSTOM_CONFIG::ConfigTdpLock
UINT32 ConfigTdpLock
Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtCustomConfig.h:97
MAX_CUSTOM_CTDP_ENTRIES
#define MAX_CUSTOM_CTDP_ENTRIES
Defines the maximum number of custom ConfigTdp entries supported.
Definition: CpuPowerMgmtCustomConfig.h:54
_PPM_CUSTOM_CTDP_TABLE::CustomPowerLimit2
UINT16 CustomPowerLimit2
Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG....
Definition: CpuPowerMgmtCustomConfig.h:84
_PPM_CUSTOM_CTDP_TABLE::RsvdBits
UINT32 RsvdBits
Bits reserved for DWORD alignment.
Definition: CpuPowerMgmtCustomConfig.h:82
CPU_POWER_MGMT_CUSTOM_CONFIG
CPU Power Management Custom Configuration Structure.
Definition: CpuPowerMgmtCustomConfig.h:93
CPU_POWER_MGMT_CUSTOM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtCustomConfig.h:99
_PPM_CUSTOM_CTDP_TABLE::CustomTurboActivationRatio
UINT32 CustomTurboActivationRatio
Turbo Activation Ratio for custom cTDP level.
Definition: CpuPowerMgmtCustomConfig.h:81
PPM_CUSTOM_RATIO_TABLE::MaxRatio
UINT8 MaxRatio
The maximum ratio of the custom ratio table.
Definition: CpuPowerMgmtCustomConfig.h:60
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtPsysConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuPowerMgmtPsysConfig.h File Reference

CPU Power Management Psys(Platform) Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_PSYS_CONFIG
CPU Power Management Psys(Platform) Configuration Structure. More...

Detailed Description

CPU Power Management Psys(Platform) Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtPsysConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtPsysConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuPowerMgmtPsysConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Psys(Platform) Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_
36 #define _CPU_POWER_MGMT_PSYS_CONFIG_H_
37
38 #define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Power Management Psys(Platform) Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 **/
50 typedef struct {
51 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
52 UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power
53 UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: PL1 timewindow in seconds.
54 UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power
55 UINT32 RsvdBits : 22; ///< Reserved for future use.
56 UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
57 UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
58 UINT16 PsysPmax; ///< PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
59 UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
60 } CPU_POWER_MGMT_PSYS_CONFIG;
61
62 #pragma pack (pop)
63
64 #endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit2Power
UINT16 PsysPowerLimit2Power
MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Definition: CpuPowerMgmtPsysConfig.h:57
CPU_POWER_MGMT_PSYS_CONFIG::PsysPmax
UINT16 PsysPmax
PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments....
Definition: CpuPowerMgmtPsysConfig.h:58
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1
UINT32 PsysPowerLimit1
MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power.
Definition: CpuPowerMgmtPsysConfig.h:52
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1Time
UINT32 PsysPowerLimit1Time
MSR 0x65C[23:17]: PL1 timewindow in seconds.
Definition: CpuPowerMgmtPsysConfig.h:53
CPU_POWER_MGMT_PSYS_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtPsysConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit1Power
UINT16 PsysPowerLimit1Power
MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
Definition: CpuPowerMgmtPsysConfig.h:56
CPU_POWER_MGMT_PSYS_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtPsysConfig.h:51
CPU_POWER_MGMT_PSYS_CONFIG
CPU Power Management Psys(Platform) Configuration Structure.
Definition: CpuPowerMgmtPsysConfig.h:50
CPU_POWER_MGMT_PSYS_CONFIG::PsysPowerLimit2
UINT32 PsysPowerLimit2
MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power.
Definition: CpuPowerMgmtPsysConfig.h:54
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtTestConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes | Enumerations
CpuPowerMgmtTestConfig.h File Reference

CPU Power Management Test Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_TEST_CONFIG
CPU Power Management Test Configuration Structure. More...

Enumerations

enum | MAX_PKG_C_STATE
PPM Package C State Limit.
enum | C_STATE_TIME_UNIT
PPM Package C State Time Limit.
enum | CUSTOM_POWER_UNIT
Custom Power Units. More...
enum | PPM_IRM_SETTING
PPM Interrupt Redirection Mode Selection.

Detailed Description

CPU Power Management Test Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtTestConfig.h.

Enumeration Type Documentation

◆ CUSTOM_POWER_UNIT

enum CUSTOM_POWER_UNIT

Custom Power Units.

User can choose to enter in watts or 125 milliwatt increments.

Enumerator
PowerUnitWatts | in Watts.
PowerUnit125MilliWatts | in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.

Definition at line 78 of file CpuPowerMgmtTestConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtTestConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuPowerMgmtTestConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management Test Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_
36 #define _CPU_POWER_MGMT_TEST_CONFIG_H_
37
38 #define CPU_POWER_MGMT_TEST_CONFIG_REVISION 7
39
40 extern EFI_GUID gCpuPowerMgmtTestConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// PPM Package C State Limit
46 ///
47 typedef enum {
48 PkgC0C1 = 0,
49 PkgC2,
50 PkgC3,
51 PkgC6,
52 PkgC7,
53 PkgC7s,
54 PkgC8,
55 PkgC9,
56 PkgC10,
57 PkgCMax,
58 PkgCpuDefault = 254,
59 PkgAuto = 255
60 } MAX_PKG_C_STATE;
61
62 ///
63 /// PPM Package C State Time Limit
64 ///
65 typedef enum {
66 TimeUnit1ns = 0,
67 TimeUnit32ns,
68 TimeUnit1024ns,
69 TimeUnit32768ns,
70 TimeUnit1048576ns,
71 TimeUnit33554432ns,
72 TimeUnitMax
73 } C_STATE_TIME_UNIT;
74
75 ///
76 /// Custom Power Units. User can choose to enter in watts or 125 milliwatt increments.
77 ///
78 typedef enum {
79 PowerUnitWatts = 0, ///< in Watts.
80 PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
81 PowerUnitMax
82 } CUSTOM_POWER_UNIT;
83
84 ///
85 /// PPM Interrupt Redirection Mode Selection
86 ///
87 typedef enum {
88 PpmIrmFixedPriority = 0,
89 PpmIrmRoundRobin,
90 PpmIrmHashVector,
91 PpmIrmReserved1,
92 PpmIrmReserved2,
93 PpmIrmReserved3,
94 PpmIrmReserved4,
95 PpmIrmNoChange
96 } PPM_IRM_SETTING;
97
98 /**
99 CPU Power Management Test Configuration Structure.
100
101 <b>Revision 1</b>:
102 - Initial version.
103 <b>Revision 2</b>:
104 - Add CstateLatencyControl0TimeUnit for WHL only
105 - Add CstateLatencyControl0Irtl for WHL only
106 <b>Revision 3</b>:
107 - Change C State LatencyContol to Auto as default.
108 <b>Revision 4</b>:
109 - Add CstateLatencyControl0TimeUnit and CstateLatencyControl0Irtl.
110 <b>Revision 5</b>:
111 - Change EnergyEfficientTurbo to Disable as default.
112 <b>Revision 6</b>:
113 - Change ProcHotResponse and ProcHotLock to Enable as default.
114 <b>Revision 7</b>:
115 - Deprecate ConfigTdpLevel. Move to premem.
116 **/
117 typedef struct {
118 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
119 UINT32 Eist : 1; ///< Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
120 UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; <b>1: Enable</b>
121 UINT32 EnergyEfficientTurbo : 1; ///< Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. <b>0: Disable</b>; 1: Enable.
122 UINT32 TStates : 1; ///< Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
123 UINT32 BiProcHot : 1; ///< Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
124 UINT32 DisableProcHotOut : 1; ///< Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
125 UINT32 ProcHotResponse : 1; ///< Enable or Disable PROCHOT# Response; 0: Disable; <b>1: Enable</b>.
126 UINT32 DisableVrThermalAlert : 1; ///< Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
127 UINT32 EnableAllThermalFunctions : 1; ///< Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
128 UINT32 ThermalMonitor : 1; ///< Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>.
129 UINT32 Cx : 1; ///< Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
130 UINT32 PmgCstCfgCtrlLock : 1; ///< If enabled, sets MSR 0xE2[15]; 0: Disable; <b>1: Enable</b>.
131 UINT32 C1e : 1; ///< Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
132 UINT32 C1AutoDemotion : 1; ///< Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>
133 UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>
134 UINT32 C3AutoDemotion : 1; ///< @deprecated no longer used
135 UINT32 C3UnDemotion : 1; ///< @deprecated no longer used
136 UINT32 PkgCStateDemotion : 1; ///< Enable or Disable Package Cstate Demotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
137 UINT32 PkgCStateUnDemotion : 1; ///< Enable or Disable Package Cstate UnDemotion. Disable; <b>1: Enable</b> [WhiskeyLake] <b>Disable</b>; 1: Enable
138 UINT32 CStatePreWake : 1; ///< Enable or Disable CState-Pre wake. Disable; <b>1: Enable</b>
139 UINT32 TimedMwait : 1; ///< Enable or Disable TimedMwait Support. <b>Disable</b>; 1: Enable
140 UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
141 UINT32 ProcHotLock : 1; ///< If enabled, sets MSR 0x1FC[23]; 0: Disable; <b>1: Enable</b>.
142 UINT32 RaceToHalt : 1; ///< Enable or Disable Race To Halt feature; 0: Disable; <b>1: Enable </b>. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
143 UINT32 ConfigTdpLevel : 8; ///< @deprecated Move to premem phase.
144 UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].<b>0 is Auto</b>.
145 UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].<b>0 is Auto</b>.
146 UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].<b>0 is Auto</b>.
147 UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].<b>0 is Auto</b>.
148 UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].<b>0 is Auto</b>.
149 UINT16 CstateLatencyControl0Irtl; ///< Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].<b>0 is Auto</b>.
150 MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
151 /**
152 @todo: The following enums have to be replaced with policies.
153 **/
154 C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; <b>2: 1024ns</b>.
155 C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; <b>2: 1024ns</b>.
156 C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; <b>2: 1024ns</b>.
157 C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; <b>2: 1024ns</b>.
158 C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; <b>2: 1024ns</b>.
159 C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; <b>2: 1024ns</b>.
160 /**
161 Offset 51 Default power unit in watts or in 125 milliwatt increments.
162 - 0: PowerUnitWatts.
163 - <b>1: PowerUnit125MilliWatts</b>.
164 **/
165 CUSTOM_POWER_UNIT CustomPowerUnit;
166 /**
167 Offset 52 Interrupt Redirection Mode Select.
168 - 0: Fixed priority. //Default under CNL.
169 - 1: Round robin.
170 - 2: Hash vector.
171 - 4: PAIR with fixed priority. //Default under KBL, not available under CNL.
172 - 5: PAIR with round robin. //Not available under CNL.
173 - 6: PAIR with hash vector. //Not available under CNL.
174 - 7: No change.
175 **/
176 PPM_IRM_SETTING PpmIrmSetting;
177 // Move the padding to previous offset to align the structure at 32-bit address.
178 UINT8 Rsvd[4]; ///< Offset 53-56 Reserved for future use and config block alignment
179 } CPU_POWER_MGMT_TEST_CONFIG;
180
181 #pragma pack (pop)
182
183 #endif // _CPU_POWER_MGMT_TEST_CONFIG_H_
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl2Irtl
UINT16 CstateLatencyControl2Irtl
Offset 34-35 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:145
CPU_POWER_MGMT_TEST_CONFIG::CStatePreWake
UINT32 CStatePreWake
Enable or Disable CState-Pre wake. Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:138
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl4Irtl
UINT16 CstateLatencyControl4Irtl
Offset 38-39 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:147
CPU_POWER_MGMT_TEST_CONFIG::C3AutoDemotion
UINT32 C3AutoDemotion
Definition: CpuPowerMgmtTestConfig.h:134
CPU_POWER_MGMT_TEST_CONFIG::TimedMwait
UINT32 TimedMwait
Enable or Disable TimedMwait Support. Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:139
CPU_POWER_MGMT_TEST_CONFIG::C3UnDemotion
UINT32 C3UnDemotion
Definition: CpuPowerMgmtTestConfig.h:135
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl4TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit
Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:158
PowerUnit125MilliWatts
@ PowerUnit125MilliWatts
in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
Definition: CpuPowerMgmtTestConfig.h:80
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateDemotion
UINT32 PkgCStateDemotion
Enable or Disable Package Cstate Demotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:136
CPU_POWER_MGMT_TEST_CONFIG::RaceToHalt
UINT32 RaceToHalt
Enable or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will dynamically increase CPU fre...
Definition: CpuPowerMgmtTestConfig.h:142
CPU_POWER_MGMT_TEST_CONFIG::EnergyEfficientTurbo
UINT32 EnergyEfficientTurbo
Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:121
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl1Irtl
UINT16 CstateLatencyControl1Irtl
Offset 32-33 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:144
PPM_IRM_SETTING
PPM_IRM_SETTING
PPM Interrupt Redirection Mode Selection.
Definition: CpuPowerMgmtTestConfig.h:87
PowerUnitWatts
@ PowerUnitWatts
in Watts.
Definition: CpuPowerMgmtTestConfig.h:79
CPU_POWER_MGMT_TEST_CONFIG::ConfigTdpLevel
UINT32 ConfigTdpLevel
Definition: CpuPowerMgmtTestConfig.h:143
C_STATE_TIME_UNIT
C_STATE_TIME_UNIT
PPM Package C State Time Limit.
Definition: CpuPowerMgmtTestConfig.h:65
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl5TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit
Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:159
CPU_POWER_MGMT_TEST_CONFIG::DisableProcHotOut
UINT32 DisableProcHotOut
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:124
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl2TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit
Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:156
CPU_POWER_MGMT_TEST_CONFIG::BiProcHot
UINT32 BiProcHot
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:123
CPU_POWER_MGMT_TEST_CONFIG::Cx
UINT32 Cx
Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:129
CPU_POWER_MGMT_TEST_CONFIG::CustomPowerUnit
CUSTOM_POWER_UNIT CustomPowerUnit
Offset 51 Default power unit in watts or in 125 milliwatt increments.
Definition: CpuPowerMgmtTestConfig.h:165
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateUnDemotion
UINT32 PkgCStateUnDemotion
Enable or Disable Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyLake] Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:137
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MAX_PKG_C_STATE
MAX_PKG_C_STATE
PPM Package C State Limit.
Definition: CpuPowerMgmtTestConfig.h:47
CPU_POWER_MGMT_TEST_CONFIG
CPU Power Management Test Configuration Structure.
Definition: CpuPowerMgmtTestConfig.h:117
CPU_POWER_MGMT_TEST_CONFIG::PpmIrmSetting
PPM_IRM_SETTING PpmIrmSetting
Offset 52 Interrupt Redirection Mode Select.
Definition: CpuPowerMgmtTestConfig.h:176
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit
Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:154
CPU_POWER_MGMT_TEST_CONFIG::PkgCStateLimit
MAX_PKG_C_STATE PkgCStateLimit
Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg ...
Definition: CpuPowerMgmtTestConfig.h:150
CPU_POWER_MGMT_TEST_CONFIG::Eist
UINT32 Eist
Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:119
CPU_POWER_MGMT_TEST_CONFIG::PmgCstCfgCtrlLock
UINT32 PmgCstCfgCtrlLock
If enabled, sets MSR 0xE2[15]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:130
CPU_POWER_MGMT_TEST_CONFIG::EnableAllThermalFunctions
UINT32 EnableAllThermalFunctions
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:127
CPU_POWER_MGMT_TEST_CONFIG::C1UnDemotion
UINT32 C1UnDemotion
Enable or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion
Definition: CpuPowerMgmtTestConfig.h:133
CPU_POWER_MGMT_TEST_CONFIG::EnergyEfficientPState
UINT32 EnergyEfficientPState
Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:120
CPU_POWER_MGMT_TEST_CONFIG::ProcHotLock
UINT32 ProcHotLock
If enabled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:141
CPU_POWER_MGMT_TEST_CONFIG::C1AutoDemotion
UINT32 C1AutoDemotion
Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion
Definition: CpuPowerMgmtTestConfig.h:132
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl5Irtl
UINT16 CstateLatencyControl5Irtl
Offset 40-41 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:148
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl3TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit
Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:157
CUSTOM_POWER_UNIT
CUSTOM_POWER_UNIT
Custom Power Units.
Definition: CpuPowerMgmtTestConfig.h:78
CPU_POWER_MGMT_TEST_CONFIG::ProcHotResponse
UINT32 ProcHotResponse
Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:125
CPU_POWER_MGMT_TEST_CONFIG::C1e
UINT32 C1e
Enable or Disable Enhanced C-states. 0: Disable; 1: Enable
Definition: CpuPowerMgmtTestConfig.h:131
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl0Irtl
UINT16 CstateLatencyControl0Irtl
Offset 42-43 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:149
CPU_POWER_MGMT_TEST_CONFIG::DisableVrThermalAlert
UINT32 DisableVrThermalAlert
Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:126
CPU_POWER_MGMT_TEST_CONFIG::CstCfgCtrIoMwaitRedirection
UINT32 CstCfgCtrIoMwaitRedirection
Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:140
CPU_POWER_MGMT_TEST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: CpuPowerMgmtTestConfig.h:118
CPU_POWER_MGMT_TEST_CONFIG::ThermalMonitor
UINT32 ThermalMonitor
Enable or Disable Thermal Monitor; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:128
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl1TimeUnit
C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit
Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns.
Definition: CpuPowerMgmtTestConfig.h:155
CPU_POWER_MGMT_TEST_CONFIG::TStates
UINT32 TStates
Enable or Disable T states; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtTestConfig.h:122
CPU_POWER_MGMT_TEST_CONFIG::CstateLatencyControl3Irtl
UINT16 CstateLatencyControl3Irtl
Offset 36-37 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto.
Definition: CpuPowerMgmtTestConfig.h:146
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtVrConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
Classes | Macros
CpuPowerMgmtVrConfig.h File Reference

CPU Power Management VR Config Block. More...

Go to the source code of this file.

Classes

struct CPU_POWER_MGMT_VR_CONFIG
CPU Power Management VR Configuration Structure. More...

Macros

#define MAX_NUM_VRS 5
Defines the maximum number of VR domains supported. More...

Detailed Description

CPU Power Management VR Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuPowerMgmtVrConfig.h.

Macro Definition Documentation

◆ MAX_NUM_VRS

#define MAX_NUM_VRS 5

Defines the maximum number of VR domains supported.

Warning
: Changing this define would cause DWORD alignment issues in policy structures.

Definition at line 48 of file CpuPowerMgmtVrConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPowerMgmtVrConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
CpuPowerMgmtVrConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Power Management VR Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
36 #define _CPU_POWER_MGMT_VR_CONFIG_H_
37
38 #define CPU_POWER_MGMT_VR_CONFIG_REVISION 16
39
40 extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
41
42 #pragma pack (push,1)
43
44 ///
45 /// Defines the maximum number of VR domains supported.
46 /// @warning: Changing this define would cause DWORD alignment issues in policy structures.
47 ///
48 #define MAX_NUM_VRS 5
49
50 /**
51 CPU Power Management VR Configuration Structure.
52
53 <b>Revision 1</b>:
54 - Initial version.
55 <b>Revision 2</b>:
56 - Updated Acoustic Noise Mitigation.
57 <b>Revision 3</b>:
58 - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction
59 <b>Revision 4</b>:
60 - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time
61 Added Irms support.
62 <b>Revision 5</b>:
63 - Add RfiMitigation.
64 <b>Revision 6</b>:
65 - Add Dynamic Periodicity Alteration (DPA) tuning feature
66 <b>Revision 7</b>:
67 - Add VccIn Aux Imon feature
68 <b>Revision 8</b>:
69 - Deprecate SendVrMbxCmd
70 <b>Revision 9</b>:
71 - Added an option to Enable/Disable FIVR Spread Spectrum
72 <b>Revision 10</b>:
73 - Add DlvrRfiEnable, DlvrSpreadSpectrumPercentage and DlvrRfiFrequency for RFI control.
74 <b>Revision 11</b>:
75 - Added an option to Enable/Disable PS1 to PS0/PS2 to PS1 dynamic cutoff
76 <b>Revision 12</b>:
77 - Added an option for Vr Power Delivery design
78 <b>Revision 13</b>:
79 - Add VccInDemotionEnable, VccInDemotionQuiescentPowerInMw and VccInDemotionCapacitanceInUf
80 <b>Revision 14</b>:
81 - Add EnableVsysCritical, VsysFullScale,VsysCriticalThreshold, VsysAssertionDeglitchMantissa
82 - VsysAssertionDeglitchExponent, VsysDeassertionDeglitchMantissa, VsysDeassertionDeglitchExponent
83 <b>Revision 15</b>:
84 - Add Voltage Regulator Fast Vmode ICC Limit
85 <b>Revision 16</b>:
86 - Modified IccMax range up to 512A
87 **/
88 typedef struct {
89 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
90 UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
91
92 UINT32 SendVrMbxCmd : 2; ///< Deprecated
93 UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8. <b>0: Disabled</b> 1: Enabled.
94 UINT32 RfiMitigation : 1; ///< Enable or Disable RFI Mitigation. <b>0: Disable - DCM is the IO_N default</b>; 1: Enable - Enable IO_N DCM/CCM switching as RFI mitigation.
95 UINT32 RsvdBits : 27; ///< Reserved for future use.
96 UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform Psys slope correction. <b>0: Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
97 UINT8 PsysOffset; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset. Deprecated
98 /**
99 PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.
100 <b>1.5%</b>
101 Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%.
102 Each Range is translated to an encoded value for FIVR register.
103 0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
104 **/
105 UINT8 FivrSpreadSpectrum;
106 UINT8 RsvdBytes0;
107 /**
108 PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
109 <b>0: Auto</b>
110 Range varies based on XTAL clock:
111 - 0-1918 (Up to 191.8HMz) for 24MHz clock.
112 - 0-1535 (Up to 153.5MHz) for 19MHz clock.
113 **/
114 UINT16 FivrRfiFrequency;
115 UINT8 RsvdBytes1[2];
116 /** @name VR Settings
117 The VR related settings are sorted in an array where each index maps to the VR domain as defined below:
118 - 0 = System Agent VR
119 - 1 = IA Core VR
120 - 2 = Ring Vr
121 - 3 = GT VR
122 - 4 = FIVR VR
123
124 The VR settings for a given domain must be populated in the appropriate index.
125 **/
126 ///@{
127 UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
128 UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</b>
129 UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
130 UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
131 UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
132 UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
133 INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
134 UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Icc Max limit. 0-512A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no override</b>
135 UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
136 UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
137 UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
138 UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
139 UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS configuration of VR; 0: Disable; <b>1: Enable.</b>
140 UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
141 UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
142 UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
143 UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew Rate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
144 UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configuration for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
145 ///@}
146 UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 .Range 0 to 1999mV. <b> 0: 0mV </b>
147 UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1. Range 0 to 1999mV. <b> 0: 0mV </b>
148 UINT16 PsysOffset1; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0: Auto</b> Units 1/1000, Range 0-63999. For an offset of 25.348, enter 25348.
149 UINT8 RsvdBytes2[2];
150 UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
151 UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Current root mean square. <b>0: Disable</b>; 1: Enable.
152 UINT8 FivrSpectrumEnable; ///< Enable or Disable FIVR Spread Spectrum 0: Disable; <b> 1: Enable.</b>
153 UINT8 DlvrSpreadSpectrumPercentage; ///< PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7.75%.
154 UINT8 DlvrRfiEnable; ///< PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. <b>0: Disable.</b> 1:Disable
155 UINT8 PreWake; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max pre-wake randomization time in micro ticks. Range is 0-255.
156 UINT8 RampUp; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp up randomization time in micro ticks. Range is 0-255.
157 UINT8 RampDown; ///< PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMitigation is enabled.<b>Default Value = 0 micro ticks</b> Defines the max ramp down randomization time in micro ticks. Range is 0-255.
158 UINT8 Rsvd2[1];
159 UINT16 VccInAuxImonIccImax; ///< PCODE MMIO Mailbox: VccIn Aux Imon IccMax. <b>0 - Auto</b> Values are in 1/4 Amp increments. Range is 0-128A8.
160 UINT16 VccInAuxImonSlope; ///< PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
161 INT16 VccInAuxImonOffset; ///< PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
162 UINT16 DlvrRfiFrequency; ///< PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
163 UINT8 PS1toPS0DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable PS1 to PS0 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
164 UINT8 PS2toPS1DynamicCutoffEnable[MAX_NUM_VRS];///< Enable/Disable:PS2 to PS1 Dynamic Cutoff; <b>0: Disable</b>; 1: Enable.
165 UINT16 PS1toPS0MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
166 INT16 PS1toPS0CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS1 to PS0 C Coef. This number is in C*100 units. <b>Default: 2000</b> Range: 0-4096.
167 UINT16 PS2toPS1MCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 M Coef. This number is in M*100 units. <b>Default: 100</b> Range: 0-4096.
168 INT16 PS2toPS1CCoef[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: PS2 to PS1 C Coef. This number is in C*100 units. <b>Default: 500</b> Range: 0-4096.
169 /**
170 This field is required to be non-zero on Desktop platforms.
171
172 Used to communicate the power delivery design capability of the board. This value is an
173 enum of the available power delivery segments that are defined in the Platform Design Guide.
174 This is required due to CPU socket compatibility across different board designs. Without
175 this field populated, the system may experience VR OCP/OVP shutdowns, hangs, thermal and
176 performance loss.
177 <b> 0 - Disable </b>
178 **/
179 UINT8 VrPowerDeliveryDesign;
180 UINT8 Rsvd4[1];
181 /**
182 Enable VCC Demotion.
183 0: Disable;
184 <b>1: Enable with default threshold</b>;
185 2: Enable with user configured threshold.
186 **/
187 UINT8 VccInDemotionEnable[MAX_NUM_VRS];
188 /**
189 User configured platform quiescent threshold in milli-watt
190 when VCC Demotion is enabled with user configured threshold.
191 Range: 0-255.
192 **/
193 UINT8 VccInDemotionQuiescentPowerInMw[MAX_NUM_VRS];
194 UINT8 Rsvd5[2]; ///< Make next field 4-byte aligned.
195 /**
196 User configured VR's quiescent power threshold in micro-farad
197 when VCC Demotion is enabled with user configured threshold.
198 Range: 0-2000.
199 **/
200 UINT32 VccInDemotionCapacitanceInUf[MAX_NUM_VRS];
201
202 UINT8 EnableVsysCritical; ///< PCODE MMIO Mailbox: Enable/Disable Vsys Critical; <b>0: Disable</b>; 1: Enable.
203 /**
204 Set VSYS Critical [0x4A]
205 Write to 0x4A to program Vsys Critical Threshold which is a linear fractional value of the Vsys input full scale voltage
206 where minimun is 0 and maximum is 255. Default 0
207 For example: Vsys_Crit (0x4A) = (Critical Threshold/Full Scale) * 0xFF
208 **/
209 UINT8 VsysFullScale;
210 UINT8 VsysCriticalThreshold;
211 /**
212 Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49]
213 Provide 2 fields in BIOS Menu for Assertion/De-Assertion Deglitch: Mantissa and Exponent.
214 The format for Assertion/De-Assertion Deglitch: 0.002ms * Mantissa * 2^(Exponent).
215 **/
216 UINT8 VsysAssertionDeglitchMantissa;
217 UINT8 VsysAssertionDeglitchExponent;
218 UINT8 VsysDeassertionDeglitchMantissa;
219 UINT8 VsysDeassertionDeglitchExponent;
220 UINT8 Rsvd6[1];
221 /**
222 PCODE VR Mailbox: Voltage Regulator Fast Vmode ICC Limit.
223 This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
224 A value of 0 corresponds to feature disabled (no reactive protection).
225 <b>Default: 0 - Disable, no override</b>
226 **/
227 UINT16 IccLimit[MAX_NUM_VRS];
228 UINT8 RsvdBytes3[2];
229 } CPU_POWER_MGMT_VR_CONFIG;
230
231 #pragma pack (pop)
232
233 #endif // _CPU_POWER_MGMT_VR_CONFIG_H_
CPU_POWER_MGMT_VR_CONFIG::DlvrRfiFrequency
UINT16 DlvrRfiFrequency
PCODE MMIO Mailbox: DLVR clock frequency in MHz. Default is 0x55A MHz.
Definition: CpuPowerMgmtVrConfig.h:162
CPU_POWER_MGMT_VR_CONFIG::RampUp
UINT8 RampUp
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:156
CPU_POWER_MGMT_VR_CONFIG::PsysOffset
UINT8 PsysOffset
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255....
Definition: CpuPowerMgmtVrConfig.h:97
CPU_POWER_MGMT_VR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuPowerMgmtVrConfig.h:89
CPU_POWER_MGMT_VR_CONFIG::VsysFullScale
UINT8 VsysFullScale
Set VSYS Critical [0x4A] Write to 0x4A to program Vsys Critical Threshold which is a linear fractiona...
Definition: CpuPowerMgmtVrConfig.h:209
CPU_POWER_MGMT_VR_CONFIG
CPU Power Management VR Configuration Structure.
Definition: CpuPowerMgmtVrConfig.h:88
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonIccImax
UINT16 VccInAuxImonIccImax
PCODE MMIO Mailbox: VccIn Aux Imon IccMax. 0 - Auto Values are in 1/4 Amp increments....
Definition: CpuPowerMgmtVrConfig.h:159
CPU_POWER_MGMT_VR_CONFIG::PreWake
UINT8 PreWake
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:155
CPU_POWER_MGMT_VR_CONFIG::DlvrSpreadSpectrumPercentage
UINT8 DlvrSpreadSpectrumPercentage
PCODE MMIO Mailbox: Encoded DLVR SSC value. 0x0 = Disabled. u3.2 value from 0% - 7....
Definition: CpuPowerMgmtVrConfig.h:153
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_POWER_MGMT_VR_CONFIG::MinVoltageC8
UINT16 MinVoltageC8
PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = 1....
Definition: CpuPowerMgmtVrConfig.h:147
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonOffset
INT16 VccInAuxImonOffset
PCODE MMIO Mailbox: VccinAuxImon offset correction. Value is a 2's complement signed integer....
Definition: CpuPowerMgmtVrConfig.h:161
MAX_NUM_VRS
#define MAX_NUM_VRS
Defines the maximum number of VR domains supported.
Definition: CpuPowerMgmtVrConfig.h:48
CPU_POWER_MGMT_VR_CONFIG::RfiMitigation
UINT32 RfiMitigation
Enable or Disable RFI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Enable IO_N DCM/C...
Definition: CpuPowerMgmtVrConfig.h:94
CPU_POWER_MGMT_VR_CONFIG::EnableVsysCritical
UINT8 EnableVsysCritical
PCODE MMIO Mailbox: Enable/Disable Vsys Critical; 0: Disable; 1: Enable.
Definition: CpuPowerMgmtVrConfig.h:202
CPU_POWER_MGMT_VR_CONFIG::PsysSlope
UINT8 PsysSlope
PCODE MMIO Mailbox: Platform Psys slope correction. 0: Auto Specified in 1/100 increment values....
Definition: CpuPowerMgmtVrConfig.h:96
CPU_POWER_MGMT_VR_CONFIG::FivrRfiFrequency
UINT16 FivrRfiFrequency
PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
Definition: CpuPowerMgmtVrConfig.h:114
CPU_POWER_MGMT_VR_CONFIG::SendVrMbxCmd
UINT32 SendVrMbxCmd
Deprecated.
Definition: CpuPowerMgmtVrConfig.h:92
CPU_POWER_MGMT_VR_CONFIG::PsysOffset1
UINT16 PsysOffset1
PCODE MMIO Mailbox: Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-63999....
Definition: CpuPowerMgmtVrConfig.h:148
CPU_POWER_MGMT_VR_CONFIG::EnableMinVoltageOverride
UINT32 EnableMinVoltageOverride
Enable or disable Minimum Voltage override for minimum voltage runtime and minimum voltage C8....
Definition: CpuPowerMgmtVrConfig.h:93
CPU_POWER_MGMT_VR_CONFIG::MinVoltageRuntime
UINT16 MinVoltageRuntime
PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride = 1 ....
Definition: CpuPowerMgmtVrConfig.h:146
CPU_POWER_MGMT_VR_CONFIG::DlvrRfiEnable
UINT8 DlvrRfiEnable
PCODE MMIO Mailbox: Enable/Disable RFI frequency hopping. 0: Disable. 1:Disable.
Definition: CpuPowerMgmtVrConfig.h:154
CPU_POWER_MGMT_VR_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuPowerMgmtVrConfig.h:95
CPU_POWER_MGMT_VR_CONFIG::FivrSpectrumEnable
UINT8 FivrSpectrumEnable
Enable or Disable FIVR Spread Spectrum 0: Disable; 1: Enable.
Definition: CpuPowerMgmtVrConfig.h:152
CPU_POWER_MGMT_VR_CONFIG::RampDown
UINT8 RampDown
PCODE MMIO Mailbox: Acoustic Noise Mitigation Range. This can be programmed only if AcousticNoiseMiti...
Definition: CpuPowerMgmtVrConfig.h:157
CPU_POWER_MGMT_VR_CONFIG::VccInAuxImonSlope
UINT16 VccInAuxImonSlope
PCODE MMIO Mailbox: VccInAuxImon slope correction. Specified in 1/100 increment values....
Definition: CpuPowerMgmtVrConfig.h:160
CPU_POWER_MGMT_VR_CONFIG::AcousticNoiseMitigation
UINT32 AcousticNoiseMitigation
Enable or Disable Acoustic Noise Mitigation feature. 0: Disabled; 1: Enabled.
Definition: CpuPowerMgmtVrConfig.h:90
CPU_POWER_MGMT_VR_CONFIG::VrPowerDeliveryDesign
UINT8 VrPowerDeliveryDesign
This field is required to be non-zero on Desktop platforms.
Definition: CpuPowerMgmtVrConfig.h:179
CPU_POWER_MGMT_VR_CONFIG::FivrSpreadSpectrum
UINT8 FivrSpreadSpectrum
PCODE MMIO Mailbox: FIVR RFI Spread Spectrum Range.
Definition: CpuPowerMgmtVrConfig.h:105
CPU_POWER_MGMT_VR_CONFIG::VsysAssertionDeglitchMantissa
UINT8 VsysAssertionDeglitchMantissa
Set Assertion Deglitch [0x4F] and De-Assertion Deglitch [0x49] Provide 2 fields in BIOS Menu for Asse...
Definition: CpuPowerMgmtVrConfig.h:216
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuRegbarAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
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Functions
CpuRegbarAccessLib.h File Reference

Header file for CPU REGBAR ACCESS library. More...

Go to the source code of this file.

Functions

UINT64 | CpuRegbarRead64 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register. More...
UINT32 | CpuRegbarRead32 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset)
Read REGBAR register. More...
UINT16 | CpuRegbarRead16 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register. More...
UINT8 | CpuRegbarRead8 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register. More...
UINT64 | CpuRegbarWrite64 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT64 Data)
Write REGBAR register. More...
UINT32 | CpuRegbarWrite32 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 Data)
Write REGBAR register. More...
UINT16 | CpuRegbarWrite16 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 Data)
Write REGBAR register. More...
UINT8 | CpuRegbarWrite8 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 Data)
Write REGBAR register. More...
UINT32 | CpuRegbarOr32 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 OrData)
Write REGBAR register. More...
UINT16 | CpuRegbarOr16 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 OrData)
Write REGBAR register. More...
UINT8 | CpuRegbarOr8 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 OrData)
Write REGBAR register. More...
UINT32 | CpuRegbarAnd32 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 AndData)
Performs a bitwise AND of a 32-bit data. More...
UINT16 | CpuRegbarAnd16 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 AndData)
Performs a bitwise AND of a 16-bit data. More...
UINT8 | CpuRegbarAnd8 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 AndData)
Performs a bitwise AND of a 8-bit data. More...
UINT32 | CpuRegbarAndThenOr32 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write REGBAR register. More...
UINT16 | CpuRegbarAndThenOr16 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 AndData, IN UINT16 OrData)
Write REGBAR register. More...
UINT8 | CpuRegbarAndThenOr8 (IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 AndData, IN UINT8 OrData)
Write REGBAR register. More...

Detailed Description

Header file for CPU REGBAR ACCESS library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuRegbarAccessLib.h.

Function Documentation

◆ CpuRegbarAnd16()

UINT16 CpuRegbarAnd16 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT16 | AndData
 | ) |  |

Performs a bitwise AND of a 16-bit data.

It programs REGBAR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevice | CPU SB Device
[in] | Offset | Register offset of Port ID.
[in] | AndData | And Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ CpuRegbarAnd32()

UINT32 CpuRegbarAnd32 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | AndData
 | ) |  |

Performs a bitwise AND of a 32-bit data.

It programs REGBAR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevice | CPU SB Device
[in] | Offset | Register offset of Port ID.
[in] | AndData | And Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ CpuRegbarAnd8()

UINT8 CpuRegbarAnd8 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT8 | AndData
 | ) |  |

Performs a bitwise AND of a 8-bit data.

It programs REGBAR register and size in 1byte. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevice | CPU SB Device
[in] | Offset | Register offset of Port ID.
[in] | AndData | And Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register

◆ CpuRegbarAndThenOr16()

UINT16 CpuRegbarAndThenOr16 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT16 | AndData,
 |  | IN UINT16 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ CpuRegbarAndThenOr32()

UINT32 CpuRegbarAndThenOr32 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | AndData,
 |  | IN UINT32 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ CpuRegbarAndThenOr8()

UINT8 CpuRegbarAndThenOr8 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT8 | AndData,
 |  | IN UINT8 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register

◆ CpuRegbarOr16()

UINT16 CpuRegbarOr16 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT16 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ CpuRegbarOr32()

UINT32 CpuRegbarOr32 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ CpuRegbarOr8()

UINT8 CpuRegbarOr8 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT8 | OrData
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register

◆ CpuRegbarRead16()

UINT16 CpuRegbarRead16 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset
 | ) |  |

Read REGBAR register.

It returns REGBAR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT16 REGBAR register value.

◆ CpuRegbarRead32()

UINT32 CpuRegbarRead32 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT32 | Offset
 | ) |  |

Read REGBAR register.

It returns REGBAR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT32 REGBAR register value.

◆ CpuRegbarRead64()

UINT64 CpuRegbarRead64 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset
 | ) |  |

Read REGBAR register.

It returns REGBAR register and size in 8bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT64 REGBAR register value.

◆ CpuRegbarRead8()

UINT8 CpuRegbarRead8 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset
 | ) |  |

Read REGBAR register.

It returns REGBAR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT8 REGBAR regsiter value

◆ CpuRegbarWrite16()

UINT16 CpuRegbarWrite16 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT16 | Data
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ CpuRegbarWrite32()

UINT32 CpuRegbarWrite32 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | Data
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ CpuRegbarWrite64()

UINT64 CpuRegbarWrite64 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT64 | Data
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 8bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT64 Value written to register

◆ CpuRegbarWrite8()

UINT8 CpuRegbarWrite8 | ( | IN CPU_SB_DEVICE_PID | CpuSbDevicePid,
 |  | IN UINT16 | Offset,
 |  | IN UINT8 | Data
 | ) |  |

Write REGBAR register.

It programs REGBAR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | CpuSbDevicePid | CPU SB Device Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuRegbarAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
CpuRegbarAccessLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for CPU REGBAR ACCESS library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_REGBAR_ACCESS_LIB_H_
36 #define _CPU_REGBAR_ACCESS_LIB_H_
37
38 #define INVALID_DATA_64 0xFFFFFFFFFFFFFFFF
39 #define INVALID_DATA_32 0xFFFFFFFF
40 #define INVALID_DATA_16 0xFFFF
41 #define INVALID_DATA_8 0xFF
42 #define INVALID_PID 0xFF
43
44 typedef UINT8 CPU_SB_DEVICE_PID;
45
46 /**
47 Read REGBAR register.
48 It returns REGBAR register and size in 8bytes.
49 The Offset should not exceed 0xFFFF and must be aligned with size.
50
51 @param[in] CpuSbDevicePid CPU SB Device Port ID
52 @param[in] Offset Register offset of this Port ID
53
54 @retval UINT64 REGBAR register value.
55 **/
56 UINT64
57 CpuRegbarRead64 (
58 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
59 IN UINT16 Offset
60 );
61
62
63 /**
64 Read REGBAR register.
65 It returns REGBAR register and size in 4bytes.
66 The Offset should not exceed 0xFFFF and must be aligned with size.
67
68 @param[in] CpuSbDevicePid CPU SB Device Port ID
69 @param[in] Offset Register offset of this Port ID
70
71 @retval UINT32 REGBAR register value.
72 **/
73 UINT32
74 CpuRegbarRead32 (
75 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
76 IN UINT32 Offset
77 );
78
79 /**
80 Read REGBAR register.
81 It returns REGBAR register and size in 2bytes.
82 The Offset should not exceed 0xFFFF and must be aligned with size.
83
84 @param[in] CpuSbDevicePid CPU SB Device Port ID
85 @param[in] Offset Register offset of this Port ID
86
87 @retval UINT16 REGBAR register value.
88 **/
89 UINT16
90 CpuRegbarRead16 (
91 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
92 IN UINT16 Offset
93 );
94
95 /**
96 Read REGBAR register.
97 It returns REGBAR register and size in 1bytes.
98 The Offset should not exceed 0xFFFF and must be aligned with size.
99
100 @param[in] CpuSbDevicePid CPU SB Device Port ID
101 @param[in] Offset Register offset of this Port ID
102
103 @retval UINT8 REGBAR regsiter value
104 **/
105 UINT8
106 CpuRegbarRead8 (
107 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
108 IN UINT16 Offset
109 );
110
111 /**
112 Write REGBAR register.
113 It programs REGBAR register and size in 8bytes.
114 The Offset should not exceed 0xFFFF and must be aligned with size.
115
116 @param[in] CpuSbDevicePid CPU SB Device Port ID
117 @param[in] Offset Register offset of Port ID.
118 @param[in] Data Input Data. Must be the same size as Size parameter.
119
120 @retval UINT64 Value written to register
121 **/
122 UINT64
123 CpuRegbarWrite64 (
124 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
125 IN UINT16 Offset,
126 IN UINT64 Data
127 );
128
129
130 /**
131 Write REGBAR register.
132 It programs REGBAR register and size in 4bytes.
133 The Offset should not exceed 0xFFFF and must be aligned with size.
134
135 @param[in] CpuSbDevicePid CPU SB Device Port ID
136 @param[in] Offset Register offset of Port ID.
137 @param[in] Data Input Data. Must be the same size as Size parameter.
138
139 @retval UINT32 Value written to register
140 **/
141 UINT32
142 CpuRegbarWrite32 (
143 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
144 IN UINT32 Offset,
145 IN UINT32 Data
146 );
147
148 /**
149 Write REGBAR register.
150 It programs REGBAR register and size in 2bytes.
151 The Offset should not exceed 0xFFFF and must be aligned with size.
152
153 @param[in] CpuSbDevicePid CPU SB Device Port ID
154 @param[in] Offset Register offset of Port ID.
155 @param[in] Data Input Data. Must be the same size as Size parameter.
156
157 @retval UINT16 Value written to register
158 **/
159 UINT16
160 CpuRegbarWrite16 (
161 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
162 IN UINT16 Offset,
163 IN UINT16 Data
164 );
165
166 /**
167 Write REGBAR register.
168 It programs REGBAR register and size in 1bytes.
169 The Offset should not exceed 0xFFFF and must be aligned with size.
170
171 @param[in] CpuSbDevicePid CPU SB Device Port ID
172 @param[in] Offset Register offset of Port ID.
173 @param[in] Data Input Data. Must be the same size as Size parameter.
174
175 @retval UINT8 Value written to register
176 **/
177 UINT8
178 CpuRegbarWrite8 (
179 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
180 IN UINT16 Offset,
181 IN UINT8 Data
182 );
183
184 /**
185 Write REGBAR register.
186 It programs REGBAR register and size in 4bytes.
187 The Offset should not exceed 0xFFFF and must be aligned with size.
188
189 @param[in] CpuSbDevicePid CPU SB Device Port ID
190 @param[in] Offset Register offset of Port ID.
191 @param[in] OrData OR Data. Must be the same size as Size parameter.
192
193 @retval UINT32 Value written to register
194
195 **/
196 UINT32
197 CpuRegbarOr32 (
198 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
199 IN UINT32 Offset,
200 IN UINT32 OrData
201 );
202
203 /**
204 Write REGBAR register.
205 It programs REGBAR register and size in 2bytes.
206 The Offset should not exceed 0xFFFF and must be aligned with size.
207
208 @param[in] CpuSbDevicePid CPU SB Device Port ID
209 @param[in] Offset Register offset of Port ID.
210 @param[in] OrData OR Data. Must be the same size as Size parameter.
211
212 @retval UINT16 Value written to register
213
214 **/
215 UINT16
216 CpuRegbarOr16 (
217 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
218 IN UINT16 Offset,
219 IN UINT16 OrData
220 );
221
222 /**
223 Write REGBAR register.
224 It programs REGBAR register and size in 1bytes.
225 The Offset should not exceed 0xFFFF and must be aligned with size.
226
227 @param[in] CpuSbDevicePid CPU SB Device Port ID
228 @param[in] Offset Register offset of Port ID.
229 @param[in] OrData OR Data. Must be the same size as Size parameter.
230
231 @retval UINT8 Value written to register
232
233 **/
234 UINT8
235 CpuRegbarOr8 (
236 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
237 IN UINT16 Offset,
238 IN UINT8 OrData
239 );
240
241 /**
242 Performs a bitwise AND of a 32-bit data.
243 It programs REGBAR register and size in 4bytes.
244 The Offset should not exceed 0xFFFF and must be aligned with size.
245
246 @param[in] CpuSbDevice CPU SB Device
247 @param[in] Offset Register offset of Port ID.
248 @param[in] AndData And Data. Must be the same size as Size parameter.
249
250 @retval UINT32 Value written to register
251
252 **/
253 UINT32
254 CpuRegbarAnd32 (
255 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
256 IN UINT32 Offset,
257 IN UINT32 AndData
258 );
259
260 /**
261 Performs a bitwise AND of a 16-bit data.
262 It programs REGBAR register and size in 2bytes.
263 The Offset should not exceed 0xFFFF and must be aligned with size.
264
265 @param[in] CpuSbDevice CPU SB Device
266 @param[in] Offset Register offset of Port ID.
267 @param[in] AndData And Data. Must be the same size as Size parameter.
268
269 @retval UINT16 Value written to register
270
271 **/
272 UINT16
273 CpuRegbarAnd16 (
274 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
275 IN UINT16 Offset,
276 IN UINT16 AndData
277 );
278
279 /**
280 Performs a bitwise AND of a 8-bit data.
281 It programs REGBAR register and size in 1byte.
282 The Offset should not exceed 0xFFFF and must be aligned with size.
283
284 @param[in] CpuSbDevice CPU SB Device
285 @param[in] Offset Register offset of Port ID.
286 @param[in] AndData And Data. Must be the same size as Size parameter.
287
288 @retval UINT8 Value written to register
289
290 **/
291 UINT8
292 CpuRegbarAnd8 (
293 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
294 IN UINT16 Offset,
295 IN UINT8 AndData
296 );
297 /**
298 Write REGBAR register.
299 It programs REGBAR register and size in 4bytes.
300 The Offset should not exceed 0xFFFF and must be aligned with size.
301
302 @param[in] CpuSbDevicePid CPU SB Device Port ID
303 @param[in] Offset Register offset of Port ID.
304 @param[in] AndData AND Data. Must be the same size as Size parameter.
305 @param[in] OrData OR Data. Must be the same size as Size parameter.
306
307 @retval UINT32 Value written to register
308
309 **/
310 UINT32
311 CpuRegbarAndThenOr32 (
312 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
313 IN UINT32 Offset,
314 IN UINT32 AndData,
315 IN UINT32 OrData
316 );
317
318 /**
319 Write REGBAR register.
320 It programs REGBAR register and size in 2bytes.
321 The Offset should not exceed 0xFFFF and must be aligned with size.
322
323 @param[in] CpuSbDevicePid CPU SB Device Port ID
324 @param[in] Offset Register offset of Port ID.
325 @param[in] AndData AND Data. Must be the same size as Size parameter.
326 @param[in] OrData OR Data. Must be the same size as Size parameter.
327
328 @retval UINT16 Value written to register
329
330 **/
331 UINT16
332 CpuRegbarAndThenOr16 (
333 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
334 IN UINT16 Offset,
335 IN UINT16 AndData,
336 IN UINT16 OrData
337 );
338
339 /**
340 Write REGBAR register.
341 It programs REGBAR register and size in 1bytes.
342 The Offset should not exceed 0xFFFF and must be aligned with size.
343
344 @param[in] CpuSbDevicePid CPU SB Device Port ID
345 @param[in] Offset Register offset of Port ID.
346 @param[in] AndData AND Data. Must be the same size as Size parameter.
347 @param[in] OrData OR Data. Must be the same size as Size parameter.
348
349 @retval UINT8 Value written to register
350
351 **/
352 UINT8
353 CpuRegbarAndThenOr8 (
354 IN CPU_SB_DEVICE_PID CpuSbDevicePid,
355 IN UINT16 Offset,
356 IN UINT8 AndData,
357 IN UINT8 OrData
358 );
359
360 #endif
CpuRegbarOr8
UINT8 CpuRegbarOr8(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 OrData)
Write REGBAR register.
CpuRegbarAnd16
UINT16 CpuRegbarAnd16(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 AndData)
Performs a bitwise AND of a 16-bit data.
CpuRegbarWrite32
UINT32 CpuRegbarWrite32(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 Data)
Write REGBAR register.
CpuRegbarOr16
UINT16 CpuRegbarOr16(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 OrData)
Write REGBAR register.
CpuRegbarRead32
UINT32 CpuRegbarRead32(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset)
Read REGBAR register.
CpuRegbarAndThenOr16
UINT16 CpuRegbarAndThenOr16(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 AndData, IN UINT16 OrData)
Write REGBAR register.
CpuRegbarAndThenOr8
UINT8 CpuRegbarAndThenOr8(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 AndData, IN UINT8 OrData)
Write REGBAR register.
CpuRegbarOr32
UINT32 CpuRegbarOr32(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 OrData)
Write REGBAR register.
CpuRegbarWrite16
UINT16 CpuRegbarWrite16(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT16 Data)
Write REGBAR register.
CpuRegbarRead8
UINT8 CpuRegbarRead8(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register.
CpuRegbarAnd32
UINT32 CpuRegbarAnd32(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 AndData)
Performs a bitwise AND of a 32-bit data.
CpuRegbarRead16
UINT16 CpuRegbarRead16(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register.
CpuRegbarRead64
UINT64 CpuRegbarRead64(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset)
Read REGBAR register.
CpuRegbarAndThenOr32
UINT32 CpuRegbarAndThenOr32(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write REGBAR register.
CpuRegbarWrite8
UINT8 CpuRegbarWrite8(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 Data)
Write REGBAR register.
CpuRegbarAnd8
UINT8 CpuRegbarAnd8(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT8 AndData)
Performs a bitwise AND of a 8-bit data.
CpuRegbarWrite64
UINT64 CpuRegbarWrite64(IN CPU_SB_DEVICE_PID CpuSbDevicePid, IN UINT16 Offset, IN UINT64 Data)
Write REGBAR register.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Classes | Macros | Enumerations
CpuRegs.h File Reference

Register names for CPU registers. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union MSR_TURBO_RATIO_LIMIT_REGISTER
MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT. More...

Macros

#define | MSR_TURBO_RATIO_LIMIT 0x000001AD
Package. More...
#define | V_IO_CAPT_LVL2 0x0
C3.
#define | V_IO_CAPT_LVL3 0x1
C6.
#define | V_IO_CAPT_LVL4 0x2
C7.
#define | V_IO_CAPT_LVL5 0x3
C8.
#define | V_IO_CAPT_LVL6 0x4
C9.
#define | V_IO_CAPT_LVL7 0x5
C10.
#define | CPU_FEATURE_DISABLE 0
Other defines.
#define | BIT(Pos, Value) (1 << (Pos) & (Value))
Notes : More...

Enumerations

enum | CPU_SKU
Enums for CPU SKU IDs.
enum | CPU_GENERATION
Enums for CPU Generation.

Detailed Description

Register names for CPU registers.

Conventions

  • Definitions beginning with "MSR_" are MSRs
  • Definitions beginning with "R_" are registers
  • Definitions beginning with "B_" are bits within registers
  • Definitions beginning with "V_" are meaningful values of bits within the registers
  • Definitions beginning with "S_" are register sizes
  • Definitions beginning with "N_" are the bit position
Copyright
INTEL CONFIDENTIAL Copyright 2004 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuRegs.h.

Macro Definition Documentation

◆ BIT

#define BIT | ( | Pos,
 |  | Value
 | ) | (1 << (Pos) & (Value))

Notes :

  1. Bit position always starts at 0.
  2. Following macros are applicable only for Word aligned integers.

Definition at line 272 of file CpuRegs.h.

◆ MSR_TURBO_RATIO_LIMIT

#define MSR_TURBO_RATIO_LIMIT 0x000001AD

Package.

Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies Maximum Ratio Limit for each Core Group. Max ratio for groups with more cores must decrease monotonically. For groups with less than 4 cores, the max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must be 22 or less. For groups with more than 5 cores, the max ratio must be 16 or less..

Parameters
ECX | MSR_TURBO_RATIO_LIMIT (0x000001AD)
EAX | Lower 32-bits of MSR value. Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.
EDX | Upper 32-bits of MSR value. Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.

Example usage

MSR_TURBO_RATIO_LIMIT_REGISTER Msr;
Msr.Uint64 = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT);
AsmWriteMsr64 (MSR_TURBO_RATIO_LIMIT, Msr.Uint64);

Definition at line 69 of file CpuRegs.h.

MSR_TURBO_RATIO_LIMIT_REGISTER::Uint64
UINT64 Uint64
All bit fields as a 64-bit value.
Definition: CpuRegs.h:131
MSR_TURBO_RATIO_LIMIT_REGISTER
MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT.
Definition: CpuRegs.h:74
MSR_TURBO_RATIO_LIMIT
#define MSR_TURBO_RATIO_LIMIT
Package.
Definition: CpuRegs.h:69
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
CpuRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for CPU registers
3
4 <b>Conventions</b>
5 - Definitions beginning with "MSR_" are MSRs
6 - Definitions beginning with "R_" are registers
7 - Definitions beginning with "B_" are bits within registers
8 - Definitions beginning with "V_" are meaningful values of bits within the registers
9 - Definitions beginning with "S_" are register sizes
10 - Definitions beginning with "N_" are the bit position
11
12 @copyright
13 INTEL CONFIDENTIAL
14 Copyright 2004 - 2021 Intel Corporation.
15
16 The source code contained or described herein and all documents related to the
17 source code ("Material") are owned by Intel Corporation or its suppliers or
18 licensors. Title to the Material remains with Intel Corporation or its suppliers
19 and licensors. The Material may contain trade secrets and proprietary and
20 confidential information of Intel Corporation and its suppliers and licensors,
21 and is protected by worldwide copyright and trade secret laws and treaty
22 provisions. No part of the Material may be used, copied, reproduced, modified,
23 published, uploaded, posted, transmitted, distributed, or disclosed in any way
24 without Intel's prior express written permission.
25
26 No license under any patent, copyright, trade secret or other intellectual
27 property right is granted to or conferred upon you by disclosure or delivery
28 of the Materials, either expressly, by implication, inducement, estoppel or
29 otherwise. Any license under such intellectual property rights must be
30 express and approved by Intel in writing.
31
32 Unless otherwise agreed by Intel in writing, you may not remove or alter
33 this notice or any other notice embedded in Materials by Intel or
34 Intel's suppliers or licensors in any way.
35
36 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
37 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
38 the terms of your license agreement with Intel or your vendor. This file may
39 be modified by the user, subject to additional terms of the license agreement.
40
41 @par Specification Reference:
42 **/
43 #ifndef _CPU_REGS_H_
44 #define _CPU_REGS_H_
45
46
47 /**
48 Package. Maximum Ratio Limit of Turbo Mode by Core Groups (RW) Specifies
49 Maximum Ratio Limit for each Core Group. Max ratio for groups with more
50 cores must decrease monotonically. For groups with less than 4 cores, the
51 max ratio must be 32 or less. For groups with 4-5 cores, the max ratio must
52 be 22 or less. For groups with more than 5 cores, the max ratio must be 16
53 or less..
54
55 @param ECX MSR_TURBO_RATIO_LIMIT (0x000001AD)
56 @param EAX Lower 32-bits of MSR value.
57 Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.
58 @param EDX Upper 32-bits of MSR value.
59 Described by the type MSR_TURBO_RATIO_LIMIT_REGISTER.
60
61 <b>Example usage</b>
62 @code
63 MSR_TURBO_RATIO_LIMIT_REGISTER Msr;
64
65 Msr.Uint64 = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT);
66 AsmWriteMsr64 (MSR_TURBO_RATIO_LIMIT, Msr.Uint64);
67 @endcode
68 **/
69 #define MSR_TURBO_RATIO_LIMIT 0x000001AD
70
71 /**
72 MSR information returned for MSR index #MSR_TURBO_RATIO_LIMIT
73 **/
74 typedef union {
75 ///
76 /// Individual bit fields
77 ///
78 struct {
79 ///
80 /// [Bits 7:0] Package. Maximum Ratio Limit for Active cores in MaxTurbo 1Core
81 /// Maximum turbo ratio limit when number of active cores is less or equal
82 /// to MaxTurbo 1Core threshold.
83 ///
84 UINT32 MaxTurbo1Core:8;
85 ///
86 /// [Bits 15:8] Package. Maximum Ratio Limit for Active cores in MaxTurbo 2Core
87 /// Maximum turbo ratio limit when number of active cores is less or equal
88 /// to MaxTurbo 2Core threshold and greater than MaxTurbo 1Core threshold.
89 ///
90 UINT32 MaxTurbo2Core:8;
91 ///
92 /// [Bits 23:16] Package. Maximum Ratio Limit for Active cores in MaxTurbo 3Core
93 /// Maximum turbo ratio limit when number of active cores is less or equal
94 /// to MaxTurbo 3Core threshold and greater than MaxTurbo 2Core threshold.
95 ///
96 UINT32 MaxTurbo3Core:8;
97 ///
98 /// [Bits 31:24] Package. Maximum Ratio Limit for Active cores in MaxTurbo 4Core
99 /// Maximum turbo ratio limit when number of active cores is less or equal
100 /// to MaxTurbo 4Core threshold and greater than MaxTurbo 3Core threshold.
101 ///
102 UINT32 MaxTurbo4Core:8;
103 ///
104 /// [Bits 39:32] Package. Maximum Ratio Limit for Active cores in MaxTurbo 5Core
105 /// Maximum turbo ratio limit when number of active cores is less or equal
106 /// to MaxTurbo 5Core and greater than MaxTurbo 4Core threshold.
107 ///
108 UINT32 MaxTurbo5Core:8;
109 ///
110 /// [Bits 47:40] Package. Maximum Ratio Limit for Active cores in MaxTurbo 6Core
111 /// Maximum turbo ratio limit when number of active cores is less or equal
112 /// to MaxTurbo 6Core threshold and greater than MaxTurbo 5Core threshold.
113 ///
114 UINT32 MaxTurbo6Core:8;
115 ///
116 /// [Bits 55:48] Package. Maximum Ratio Limit for Active cores in MaxTurbo 7Core
117 /// Maximum turbo ratio limit when number of active cores is less or equal
118 /// to Group 7 threshold and greater than MaxTurbo 6Core threshold.
119 ///
120 UINT32 MaxTurbo7Core:8;
121 ///
122 /// [Bits 63:56] Package. Maximum Ratio Limit for Active cores in MaxTurbo 8Core
123 /// Maximum turbo ratio limit when number of active cores is less or equal
124 /// to MaxTurbo 8Core threshold and greater than MaxTurbo 7Core threshold.
125 ///
126 UINT32 MaxTurbo8Core:8;
127 } Bits;
128 ///
129 /// All bit fields as a 64-bit value
130 ///
131 UINT64 Uint64;
132 } MSR_TURBO_RATIO_LIMIT_REGISTER;
133
134 #define PRMRR_MAX_SIZE 0x10000000
135
136 #define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_19_MHZ 0x2FBA2E26
137 #define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_24_MHZ 0x262E8B52
138 #define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_CORRECTION_FACTOR_38_MHZ 0x17DD1713
139 #define V_BIOS_UCODE_PM_TMR_EMULATION_CFG_DELAY_VALUE 0x13
140
141 // @todo. Move the definitions to CoreMsrCommon.h
142 #define MSR_UNCORE_PRMRR_PHYS_BASE 0x000002F4
143 #define MSR_UNCORE_PRMRR_PHYS_MASK 0x000002F5
144 #define B_MSR_PRMRR_PHYS_MASK_LOCK BIT10
145 #define B_MSR_PRMRR_VALID_BIT BIT11
146
147 //. @todo. this alternate msr need to move under fru
148 #define MSR_PRMRR_PHYS_BASE_ALT 0x000001F4
149 #define MSR_PRMRR_PHYS_MASK_ALT 0x000001F5
150 #define B_MSR_PRMRR_BASE_0_CONFIGURED_MASK BIT3
151
152
153 #define B_CRASHLOG_DUMP_DISABLE BIT0
154
155 #define V_TME_ACTIVATE_TME_POLICY_AES_XTS 0x00
156 #define V_TME_ACTIVATE_TME_POLICY_AES_XTS_256 0x02
157
158 #define MSR_BOOT_GUARD_SACM_INFO 0x0000013A
159 #define B_BOOT_GUARD_SACM_INFO_NEM_ENABLED BIT0
160 #define V_TPM_PRESENT_MASK 0x06
161 #define B_BOOT_GUARD_SACM_INFO_TPM_SUCCESS BIT3
162 #define B_BOOT_GUARD_SACM_INFO_MEASURED_BOOT BIT5
163 #define B_BOOT_GUARD_SACM_INFO_VERIFIED_BOOT BIT6
164 #define B_BOOT_GUARD_SACM_INFO_CAPABILITY BIT32
165
166 #define V_CSTATE_LIMIT_C1 0x01
167 #define V_CSTATE_LIMIT_C3 0x02
168 #define V_CSTATE_LIMIT_C6 0x03
169 #define V_CSTATE_LIMIT_C7 0x04
170 #define V_CSTATE_LIMIT_C7S 0x05
171 #define V_CSTATE_LIMIT_C8 0x06
172 #define V_CSTATE_LIMIT_C9 0x07
173 #define V_CSTATE_LIMIT_C10 0x08
174
175 #define V_IO_CAPT_LVL2 0x0 ///< C3
176 #define V_IO_CAPT_LVL3 0x1 ///< C6
177 #define V_IO_CAPT_LVL4 0x2 ///< C7
178 #define V_IO_CAPT_LVL5 0x3 ///< C8
179 #define V_IO_CAPT_LVL6 0x4 ///< C9
180 #define V_IO_CAPT_LVL7 0x5 ///< C10
181
182 #define B_CAP_MSR_HWP_REQ BIT0
183
184 #define MSR_FAST_UNCORE_MSR_CTL_MASK BIT0
185
186 // @todo. use XXX_MSR_FIT_BIOS_ERROR in each generation.
187 #define MSR_FIT_BIOS_ERROR 0x000000A5
188 #define B_MSR_FIT_BIOS_ERROR_ERROR_CODE_MASK 0x000000FF
189 #define N_MSR_FIT_BIOS_ERROR_ENTRY_TYPE_OFFSET 8
190 #define B_MSR_FIT_BIOS_ERROR_ENTRY_TYPE_MASK 0x0000FF00
191
192 #define FIT_HEADER_ENTRY 0x0
193 #define FIT_SUCCESSFUL 0x0
194 #define FIT_SIZE_CHECK 0x1
195 #define FIT_RESERVED_FIELD_CHECK 0x2
196 #define FIT_VERSION_AND_TYPE_CHECK 0x3
197
198 #define FIT_MICROCODE_UPDATE_ENTRY 0x1
199 #define FIT_NO_MICROCODE_UPDATE 0x1
200 #define FIT_MICROCODE_UPDATE_FAIL 0x2
201
202 #define FIT_STARTUP_ACM_ENTRY 0x2
203 #define FIT_STARTUP_ACM_NOT_SUPPORTED 0x1
204 #define FIT_FATAL_ERROR_DURING_ACM 0x2
205 #define FIT_CPU_DOES_NOT_SUPPORT_LT 0x3
206 #define FIT_BIST_ERRORS 0x4
207 #define FIT_BEYOND_END_OF_FIT 0x5
208 #define FIT_NO_FIT_ACM_TYPE_MISMATCH 0x6
209 #define FIT_ACM_BASE_SIZE_AND_CHECKS 0x7
210
211 #define FIT_GENERAL_CHECKS 0x7F
212 #define FIT_DISABLED_BY_CPU 0x1
213 #define FIT_POINTER_ERROR 0x2
214 #define FIT_FIRST_FIT_ENTRY_MISMATCH 0x3
215
216
217 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_OFFSET 0
218 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_STATUS_MASK 0x000000000000FFFF
219 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_OFFSET 16
220 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_DATA_MASK 0x000000000000FFFF
221 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_OFFSET 32
222 #define V_MSR_PLAT_FRMW_PROT_TRIG_PARAM_TERMINAL_MASK 0x000000000000FFFF
223 #define B_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE BIT62
224 #define N_MSR_PLAT_FRMW_PROT_TRIG_PARAM_SE_OFFSET 62
225
226 ///
227 /// Other defines
228 ///
229
230 #ifndef CPU_FEATURE_DISABLE
231 #define CPU_FEATURE_DISABLE 0
232 #endif
233 #ifndef CPU_FEATURE_ENABLE
234 #define CPU_FEATURE_ENABLE 1
235 #endif
236
237 #define CACHE_UNCACHEABLE 0
238 #define CACHE_WRITEBACK 6
239
240 #define TXT_PUBLIC_BASE 0xFED30000
241 #define R_CPU_BOOT_GUARD_BOOTSTATUS 0xA0
242 #define R_CPU_BOOT_GUARD_ACM_STATUS 0x328
243 #define R_CPU_ACM_POLICY_STATUS 0x378
244 #define MMIO_ACM_POLICY_STATUS (TXT_PUBLIC_BASE + R_CPU_ACM_POLICY_STATUS)
245 #define V_CPU_BOOT_GUARD_LOAD_ACM_SUCCESS 0x8000000000000000
246 #define B_BOOT_GUARD_ACM_ERRORCODE_MASK 0x00007FF0
247 #define B_CPU_BOOT_GUARD_BOOTSTATUS_BLOCK_BOOT_ENABLED BIT0
248 #define V_CPU_BOOT_GUARD_BOOTSTATUS_BLOCK_BOOT_ENABLED 0x01
249 #define B_CPU_BOOT_GUARD_BOOTSTATUS_S3_TPM_STARTUP_FAILED BIT46
250 #define R_CPU_BOOT_GUARD_NEM_MAP_STRUCTURE_ADDRESS 0x320
251
252 //
253 // Processor Definitions
254 //
255 #define CPUID_FULL_STEPPING 0x0000000F
256 #define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
257 #define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF
258 #ifndef STALL_ONE_MICRO_SECOND
259 #define STALL_ONE_MICRO_SECOND 1
260 #endif
261 #ifndef STALL_ONE_MILLI_SECOND
262 #define STALL_ONE_MILLI_SECOND 1000
263 #endif
264
265 #define BITS(x) (1 << (x))
266
267 /**
268 Notes :
269 1. Bit position always starts at 0.
270 2. Following macros are applicable only for Word aligned integers.
271 **/
272 #define BIT(Pos, Value) (1 << (Pos) & (Value))
273
274 typedef UINT32 CPU_FAMILY;
275
276 ///
277 /// Enums for CPU SKU IDs
278 ///
279 typedef enum {
280 EnumCpuUlt = 0,
281 EnumCpuTrad,
282 EnumCpuUlx,
283 EnumCpuHalo,
284 EnumCpuUnknown
285 } CPU_SKU;
286
287 ///
288 /// Enums for CPU Generation
289 ///
290 typedef enum {
291 EnumAdlCpu = 0,
292 EnumMtlCpu,
293 EnumCpuUnknownGeneration = 255
294 } CPU_GENERATION;
295 #endif
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo2Core
UINT32 MaxTurbo2Core
[Bits 15:8] Package.
Definition: CpuRegs.h:90
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo8Core
UINT32 MaxTurbo8Core
[Bits 63:56] Package.
Definition: CpuRegs.h:126
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo4Core
UINT32 MaxTurbo4Core
[Bits 31:24] Package.
Definition: CpuRegs.h:102
MSR_TURBO_RATIO_LIMIT_REGISTER::Uint64
UINT64 Uint64
All bit fields as a 64-bit value.
Definition: CpuRegs.h:131
CPU_GENERATION
CPU_GENERATION
Enums for CPU Generation.
Definition: CpuRegs.h:290
MSR_TURBO_RATIO_LIMIT_REGISTER
MSR information returned for MSR index MSR_TURBO_RATIO_LIMIT.
Definition: CpuRegs.h:74
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo3Core
UINT32 MaxTurbo3Core
[Bits 23:16] Package.
Definition: CpuRegs.h:96
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo6Core
UINT32 MaxTurbo6Core
[Bits 47:40] Package.
Definition: CpuRegs.h:114
CPU_SKU
CPU_SKU
Enums for CPU SKU IDs.
Definition: CpuRegs.h:279
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo7Core
UINT32 MaxTurbo7Core
[Bits 55:48] Package.
Definition: CpuRegs.h:120
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo1Core
UINT32 MaxTurbo1Core
[Bits 7:0] Package.
Definition: CpuRegs.h:84
MSR_TURBO_RATIO_LIMIT_REGISTER::MaxTurbo5Core
UINT32 MaxTurbo5Core
[Bits 39:32] Package.
Definition: CpuRegs.h:108
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuSecurityPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuSecurityPreMemConfig.h File Reference

CPU Security PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_SECURITY_PREMEM_CONFIG
CPU Security PreMemory Configuration Structure. More...

Detailed Description

CPU Security PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuSecurityPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuSecurityPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuSecurityPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Security PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_SECURITY_PREMEM_CONFIG_H_
36 #define _CPU_SECURITY_PREMEM_CONFIG_H_
37
38 #define CPU_SECURITY_PREMEM_CONFIG_REVISION 2
39
40 extern EFI_GUID gCpuSecurityPreMemConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Security PreMemory Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Deprecated SGx
51 **/
52 typedef struct {
53 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
54 UINT32 PrmrrSize; ///< PRMRR Size.<b>Software Control: 0x0</b> 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000, 256 MB: 0x10000000, 512 MB: 0x20000000
55 UINT16 BiosSize; ///< Flash information for BIOS Guard: BIOS Size in KB.
56 UINT8 Reserved[2]; ///< Reserved for future use
57 /**
58 Enable or Disable BIOS Guard; 0: Disable; <b>1: Enable</b>.
59 - This is an optional feature and can be opted out.
60 - If this policy is set to Disabled, the policies in the BIOS_GUARD_CONFIG will be ignored.
61 - If PeiBiosGuardLibNull is used, this policy will have no effect.
62 **/
63 UINT32 BiosGuard : 1;
64 UINT32 BiosGuardToolsInterface : 1; ///< BIOS Guard Tools Interface; <b>0: Disable</b>, 1:Enable
65 /**
66 Enable or Disable Software Guard Extensions; <b>0: Disable</b>; 1: Enable.
67 - This is an optional feature and can be opted out.
68 - If this policy is set to Disabled, the policies in the CPU_SGX_CONFIG will be ignored.
69 - If BaseSoftwareGuardLibNull is used, this policy will have no effect.
70 **/
71 UINT32 EnableSgx : 1; ///< @deprecated due to Non-POR feature.
72 /**
73 Enable or Disable Trusted Execution Technology; <b>0: Disable</b>; 1: Enable.
74 - This is an optional feature and can be opted out.
75 - If this policy is set to Disabled, the policies in the CPU_TXT_PREMEM_CONFIG will be ignored.
76 - If PeiTxtLibNull is used, this policy will have no effect.
77 **/
78 UINT32 Txt : 1;
79 UINT32 SkipStopPbet : 1; ///< <b>(Test)</b> Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable.
80 ///
81 /// <b>(Test)</b> This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.
82 /// - 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.
83 /// - <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
84 ///
85 UINT32 EnableC6Dram : 1;
86 UINT32 ResetAux : 1; ///< <b>(Test)</b> Reset Auxiliary content, <b>0: Disabled</b>, 1: Enabled
87 UINT32 TxtAcheckRequest : 1; ///< <b>(Test)</b> AcheckRequest <b>0: Disabled</b>, 1: Enabled. When Enabled, it will call Acheck regardless of crashcode value
88 UINT32 RsvdBits : 24; ///< Reserved for future use
89 } CPU_SECURITY_PREMEM_CONFIG;
90
91 #pragma pack (pop)
92
93 #endif // _CPU_SECURITY_CONFIG_H_
CPU_SECURITY_PREMEM_CONFIG::SkipStopPbet
UINT32 SkipStopPbet
(Test) Skip Stop PBET Timer; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:79
CPU_SECURITY_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuSecurityPreMemConfig.h:88
CPU_SECURITY_PREMEM_CONFIG::EnableSgx
UINT32 EnableSgx
Enable or Disable Software Guard Extensions; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:71
CPU_SECURITY_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuSecurityPreMemConfig.h:53
CPU_SECURITY_PREMEM_CONFIG::BiosGuardToolsInterface
UINT32 BiosGuardToolsInterface
BIOS Guard Tools Interface; 0: Disable, 1:Enable.
Definition: CpuSecurityPreMemConfig.h:64
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_SECURITY_PREMEM_CONFIG::BiosGuard
UINT32 BiosGuard
Enable or Disable BIOS Guard; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:63
CPU_SECURITY_PREMEM_CONFIG::TxtAcheckRequest
UINT32 TxtAcheckRequest
(Test) AcheckRequest 0: Disabled, 1: Enabled. When Enabled, it will call Acheck regardless of crashco...
Definition: CpuSecurityPreMemConfig.h:87
CPU_SECURITY_PREMEM_CONFIG::ResetAux
UINT32 ResetAux
(Test) Reset Auxiliary content, 0: Disabled, 1: Enabled
Definition: CpuSecurityPreMemConfig.h:86
CPU_SECURITY_PREMEM_CONFIG::Txt
UINT32 Txt
Enable or Disable Trusted Execution Technology; 0: Disable; 1: Enable.
Definition: CpuSecurityPreMemConfig.h:78
CPU_SECURITY_PREMEM_CONFIG::EnableC6Dram
UINT32 EnableC6Dram
(Test) This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating...
Definition: CpuSecurityPreMemConfig.h:85
CPU_SECURITY_PREMEM_CONFIG
CPU Security PreMemory Configuration Structure.
Definition: CpuSecurityPreMemConfig.h:52
CPU_SECURITY_PREMEM_CONFIG::BiosSize
UINT16 BiosSize
Flash information for BIOS Guard: BIOS Size in KB.
Definition: CpuSecurityPreMemConfig.h:55
CPU_SECURITY_PREMEM_CONFIG::PrmrrSize
UINT32 PrmrrSize
PRMRR Size.Software Control: 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000,...
Definition: CpuSecurityPreMemConfig.h:54
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuTestConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuTestConfig.h File Reference

CPU Test Config Block. More...

Go to the source code of this file.

Classes

struct CPU_TEST_CONFIG
CPU Test Configuration Structure. More...

Detailed Description

CPU Test Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuTestConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuTestConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuTestConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU Test Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_TEST_CONFIG_H_
36 #define _CPU_TEST_CONFIG_H_
37
38 #define CPU_TEST_CONFIG_REVISION 3
39
40 extern EFI_GUID gCpuTestConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU Test Configuration Structure.
46
47 <b>Revision 1</b>:
48 - Initial version.
49 <b>Revision 2</b>:
50 - Removed Voltage Optimization feature.
51 <b>Revision 3</b>:
52 - Add PostedInterruptCapability
53 **/
54 typedef struct {
55 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
56 UINT32 MlcStreamerPrefetcher : 1; ///< Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
57 UINT32 MlcSpatialPrefetcher : 1; ///< Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
58 UINT32 MonitorMwaitEnable : 1; ///< Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
59 UINT32 MachineCheckEnable : 1; ///< Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
60 UINT32 ProcessorTraceOutputScheme : 1; ///< Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
61 UINT32 ProcessorTraceEnable : 1; ///< Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
62 UINT32 ThreeStrikeCounterDisable : 1; ///< Disable Three strike counter; <b>0: FALSE</b>; 1: TRUE.
63 UINT32 RsvdBits : 25; ///< Reserved for future use
64 /**
65 Memory size per thread for Processor Trace.
66 Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB.
67 - <b>0: Disable</b>
68 **/
69 UINT32 ProcessorTraceMemSize;
70 } CPU_TEST_CONFIG;
71
72 #pragma pack (pop)
73
74 #endif // _CPU_TEST_CONFIG_H_
CPU_TEST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuTestConfig.h:55
CPU_TEST_CONFIG::MonitorMwaitEnable
UINT32 MonitorMwaitEnable
Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:58
CPU_TEST_CONFIG::MlcStreamerPrefetcher
UINT32 MlcStreamerPrefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:56
CPU_TEST_CONFIG::MlcSpatialPrefetcher
UINT32 MlcSpatialPrefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_TEST_CONFIG::ThreeStrikeCounterDisable
UINT32 ThreeStrikeCounterDisable
Disable Three strike counter; 0: FALSE; 1: TRUE.
Definition: CpuTestConfig.h:62
CPU_TEST_CONFIG::MachineCheckEnable
UINT32 MachineCheckEnable
Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:59
CPU_TEST_CONFIG::ProcessorTraceEnable
UINT32 ProcessorTraceEnable
Enable or Disable Processor Trace feature; 0: Disable; 1: Enable.
Definition: CpuTestConfig.h:61
CPU_TEST_CONFIG::ProcessorTraceOutputScheme
UINT32 ProcessorTraceOutputScheme
Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output.
Definition: CpuTestConfig.h:60
CPU_TEST_CONFIG::ProcessorTraceMemSize
UINT32 ProcessorTraceMemSize
Memory size per thread for Processor Trace.
Definition: CpuTestConfig.h:69
CPU_TEST_CONFIG
CPU Test Configuration Structure.
Definition: CpuTestConfig.h:54
CPU_TEST_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use.
Definition: CpuTestConfig.h:63
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuTxtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
Classes
CpuTxtConfig.h File Reference

CPU TXT PreMemory Config Block. More...

Go to the source code of this file.

Classes

struct CPU_TXT_PREMEM_CONFIG
CPU TXT PreMemory Configuration Structure. More...

Detailed Description

CPU TXT PreMemory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file CpuTxtConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuTxtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
CpuTxtConfig.h
Go to the documentation of this file.
1 /** @file
2 CPU TXT PreMemory Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _CPU_TXT_CONFIG_H_
36 #define _CPU_TXT_CONFIG_H_
37
38 #define CPU_TXT_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gCpuTxtPreMemConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 CPU TXT PreMemory Configuration Structure.
46 @note <b>Optional.</b> These policies will be ignored if CPU_SECURITY_PREMEM_CONFIG -> Txt is disabled, or PeiTxtLibNull is used.
47
48 <b>Revision 1</b>:
49 - Initial version.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 UINT32 SinitMemorySize; ///< Size of SINIT module if installed in flash part. Zero otherwise.
54 UINT32 TxtHeapMemorySize; ///< Size of memory reserved for TXT Heap. This memory is used by MLE.
55 UINT32 TxtDprMemorySize; ///< Size of DPR protected memory reserved for Intel TXT component.
56 EFI_PHYSICAL_ADDRESS TxtDprMemoryBase; ///< Base address of DPR protected memory reserved for Intel TXT component.
57 UINT64 TxtLcpPdSize; ///< Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
58 EFI_PHYSICAL_ADDRESS TxtLcpPdBase; ///< Base address of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
59 EFI_PHYSICAL_ADDRESS ApStartupBase; ///< Base address of TXT AP Startup code
60 EFI_PHYSICAL_ADDRESS BiosAcmBase; ///< Base address of BIOS ACM in flash part
61 UINT32 BiosAcmSize; ///< Size of ACM Binary.
62 UINT32 TgaSize; ///< Size of Trusted Graphics Aperture if supported by chipset.
63 UINT32 IsTPMPresence;
64 UINT8 Reserved[4];
65 } CPU_TXT_PREMEM_CONFIG;
66
67 #pragma pack (pop)
68
69 #endif // _CPU_TXT_CONFIG_H_
CPU_TXT_PREMEM_CONFIG::BiosAcmSize
UINT32 BiosAcmSize
Size of ACM Binary.
Definition: CpuTxtConfig.h:61
CPU_TXT_PREMEM_CONFIG::TgaSize
UINT32 TgaSize
Size of Trusted Graphics Aperture if supported by chipset.
Definition: CpuTxtConfig.h:62
CPU_TXT_PREMEM_CONFIG::BiosAcmBase
EFI_PHYSICAL_ADDRESS BiosAcmBase
Base address of BIOS ACM in flash part.
Definition: CpuTxtConfig.h:60
CPU_TXT_PREMEM_CONFIG::ApStartupBase
EFI_PHYSICAL_ADDRESS ApStartupBase
Base address of TXT AP Startup code.
Definition: CpuTxtConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
CPU_TXT_PREMEM_CONFIG
CPU TXT PreMemory Configuration Structure.
Definition: CpuTxtConfig.h:51
CPU_TXT_PREMEM_CONFIG::TxtDprMemorySize
UINT32 TxtDprMemorySize
Size of DPR protected memory reserved for Intel TXT component.
Definition: CpuTxtConfig.h:55
CPU_TXT_PREMEM_CONFIG::TxtDprMemoryBase
EFI_PHYSICAL_ADDRESS TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
Definition: CpuTxtConfig.h:56
CPU_TXT_PREMEM_CONFIG::TxtHeapMemorySize
UINT32 TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
Definition: CpuTxtConfig.h:54
CPU_TXT_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: CpuTxtConfig.h:52
CPU_TXT_PREMEM_CONFIG::SinitMemorySize
UINT32 SinitMemorySize
Size of SINIT module if installed in flash part. Zero otherwise.
Definition: CpuTxtConfig.h:53
CPU_TXT_PREMEM_CONFIG::TxtLcpPdSize
UINT64 TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in flash part. Zero otherwise.
Definition: CpuTxtConfig.h:57
CPU_TXT_PREMEM_CONFIG::TxtLcpPdBase
EFI_PHYSICAL_ADDRESS TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in flash part....
Definition: CpuTxtConfig.h:58
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DciConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Classes
DciConfig.h File Reference

Dci policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI) More...

Detailed Description

Dci policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DciConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DciConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
DciConfig.h
Go to the documentation of this file.
1 /** @file
2 Dci policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DCI_CONFIG_H_
36 #define _DCI_CONFIG_H_
37
38 #define PCH_DCI_PREMEM_CONFIG_REVISION 3
39 extern EFI_GUID gDciPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 typedef enum {
44 DciDbcDisabled = 0x0,
45 DciDbcUsb2 = 0x1,
46 DciDbcUsb3 = 0x2,
47 DciDbcBoth = 0x3,
48 DciDbcNoChange = 0x4,
49 DciDbcMax
50 } DCI_DBC_MODE;
51
52 typedef enum {
53 Usb3TcDbgDisabled = 0x0,
54 Usb3TcDbgEnabled = 0x1,
55 Usb3TcDbgNoChange = 0x2,
56 Usb3TcDbgMax
57 } DCI_USB3_TYPE_C_DEBUG_MODE;
58
59 /**
60 The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
61
62 <b>Revision 1</b>:
63 - Initial version.
64 <b>Revision 2</b>:
65 - Added DciModphyPg
66 - change to use data in byte unit rather than bit-field
67 <b>Revision 3</b>:
68 - Deprecated DciModphyPg
69 - Added DciClkEnable, KeepEarlyTrace
70 **/
71 typedef struct {
72 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
73 /**
74 DCI enable.
75 Determine if to enable DCI debug from host.
76 <b>0:Disabled</b>; 1:Enabled
77 **/
78 UINT8 DciEn;
79 /**
80 USB DbC enable mode.
81 Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3DBCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value
82 Refer to definition of DCI_USB_DBC_MODE for supported settings.
83 0:Disabled; 1:USB2; 2:USB3; 3:Both; <b>4:No Change</b>
84 **/
85 UINT8 DciDbcMode;
86 UINT8 DciModphyPg; ///< Deprecated
87 /**
88 USB3 Type-C UFP2DFP kenel / platform debug support. No change will do nothing to UFP2DFP configuration.
89 When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP (downstream-facing port) for first connection.
90 It must be enabled for USB3 kernel(kernel mode debug) and platform debug(DFx, DMA, Trace) over UFP Type-C receptacle.
91 Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported settings.
92 0:Disabled; 1:Enabled; <b>2:No Change</b>
93 **/
94 UINT8 DciUsb3TypecUfpDbg;
95 /**
96 Determine if to enable or disable DCI clock request in lowest power state.
97 0:Disabled; <b>1:Enabled</b>
98 **/
99 UINT8 DciClkEnable;
100 /**
101 Early trace is activated by default.
102 Enable to keep early trace data and keep tracing; disable to stop tracing;
103 When debug probe is connected and granted, force to no change, let host tool to set it.
104 <b>0: Disable</b>; 1: Enable early trace; 2:No Change;
105 **/
106 UINT8 KeepEarlyTrace;
107 UINT8 ReservedBytes[2];
108 } PCH_DCI_PREMEM_CONFIG;
109
110 #pragma pack (pop)
111
112 #endif // _DCI_CONFIG_H_
PCH_DCI_PREMEM_CONFIG::DciEn
UINT8 DciEn
DCI enable.
Definition: DciConfig.h:78
PCH_DCI_PREMEM_CONFIG::KeepEarlyTrace
UINT8 KeepEarlyTrace
Early trace is activated by default.
Definition: DciConfig.h:106
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DCI_PREMEM_CONFIG::DciDbcMode
UINT8 DciDbcMode
USB DbC enable mode.
Definition: DciConfig.h:85
PCH_DCI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: DciConfig.h:72
PCH_DCI_PREMEM_CONFIG::DciClkEnable
UINT8 DciClkEnable
Determine if to enable or disable DCI clock request in lowest power state.
Definition: DciConfig.h:99
PCH_DCI_PREMEM_CONFIG::DciModphyPg
UINT8 DciModphyPg
Deprecated.
Definition: DciConfig.h:86
PCH_DCI_PREMEM_CONFIG::DciUsb3TypecUfpDbg
UINT8 DciUsb3TypecUfpDbg
USB3 Type-C UFP2DFP kenel / platform debug support.
Definition: DciConfig.h:94
PCH_DCI_PREMEM_CONFIG
The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Connection Interface (DCI)
Definition: DciConfig.h:71
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DebugTokenDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
DebugTokenDataHob.h File Reference

The HOB definition for DebugTokenDataHob. More...

Go to the source code of this file.

Detailed Description

The HOB definition for DebugTokenDataHob.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DebugTokenDataHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DebugTokenDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
DebugTokenDataHob.h
Go to the documentation of this file.
1 /** @file
2 The HOB definition for DebugTokenDataHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _DEBUG_TOKEN_DATA_HOB_H_
37 #define _DEBUG_TOKEN_DATA_HOB_H_
38
39 extern EFI_GUID gDebugTokenDataHobGuid;
40
41 typedef struct {
42 EFI_HOB_GUID_TYPE EfiHobGuidType;
43 UINT32 DebugTokenData;
44 } DEBUG_TOKEN_DATA_HOB;
45
46 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DpInPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
DpInPreMemConfig.h File Reference

DPIN PreMem policy. More...

#include <ConfigBlock.h>
Include dependency graph for DpInPreMemConfig.h:

Go to the source code of this file.

Classes

struct DPIN_PREMEM_CONFIG
This configuration block describes DPIN settings. More...

Detailed Description

DPIN PreMem policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DpInPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DpInPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
DpInPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 DPIN PreMem policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DPIN_PREMEM_CONFIG_H_
36 #define _DPIN_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define DPIN_PREMEM_CONFIG_REVISION 1
41 extern EFI_GUID gDpInPreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 This configuration block describes DPIN settings.\n
47 <b>Revision 1</b>:
48 - Initial version.
49 **/
50 typedef struct {
51 ///< Header: Struct Header Offset 0-27 Config Block Header
52 CONFIG_BLOCK_HEADER Header;
53 ///< DpInExternalEn: 00 = <b>Dp-In Port is Internal Only</b>, 01 = Dp-In Port is External First.
54 UINT8 DpInExternalEn;
55 ///< NumberOfDpInPort: Total number of DpIn Port present on Board.
56 UINT8 NumberOfDpInPort;
57 ///< DpInPortConnectMap: Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port.
58 UINT8 DpInPortConnectMap;
59 ///< Reserved bytes for future use, align to DWORD
60 UINT8 Rsvd[1];
61 } DPIN_PREMEM_CONFIG;
62
63 #pragma pack (pop)
64
65 #endif /* _DPIN_PREMEM_CONFIG_H_ */
ConfigBlock.h
Header file for Config Block Lib implementation.
DPIN_PREMEM_CONFIG
This configuration block describes DPIN settings.
Definition: DpInPreMemConfig.h:50
DPIN_PREMEM_CONFIG::DpInPortConnectMap
UINT8 DpInPortConnectMap
Reserved bytes for future use, align to DWORD.
Definition: DpInPreMemConfig.h:58
DPIN_PREMEM_CONFIG::DpInExternalEn
UINT8 DpInExternalEn
NumberOfDpInPort: Total number of DpIn Port present on Board.
Definition: DpInPreMemConfig.h:54
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
DPIN_PREMEM_CONFIG::NumberOfDpInPort
UINT8 NumberOfDpInPort
DpInPortConnectMap: Indicate which Dp-In port connection detected. Each BIT stand for one Dp-In port.
Definition: DpInPreMemConfig.h:56
DPIN_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
< Header: Struct Header Offset 0-27 Config Block Header
Definition: DpInPreMemConfig.h:52
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAmtHeciLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeAmtHeciLib.h File Reference

Header file for AMT functionality. More...

#include <AsfMsgs.h>
#include <WifiProfileSyncAsfMsgs.h>
Include dependency graph for DxeAmtHeciLib.h:

Go to the source code of this file.

Functions

VOID | AsfStopWatchDog (VOID)
Stop ASF Watch Dog Timer HECI message.
VOID | AsfStartWatchDog (IN UINT8 WatchDogType)
Start ASF Watch Dog Timer. More...
EFI_STATUS | AmtSetActiveLanInterface (IN UINT8 ActiveInterface)
This message is sent to switch active LAN interface. More...
EFI_STATUS | AmtGetActiveLanInterface (OUT UINT8 *ActiveInterface)
This message is sent to get active LAN interface. More...
EFI_STATUS | AmtQueryKvm (IN UINT32 QueryType, OUT UINT32 *ResponseCode)
This is used to send KVM request message to Intel ME. More...
EFI_STATUS | AmtSetMacPassthrough (IN UINT8 Enabled, IN UINT8 *MacAddress)
This message is sent by the BIOS in order to pass MAC Address which should be used for LAN in a dock. More...
EFI_STATUS | SendRsePetAlert (IN EFI_STATUS OperationResult)
Send secure erase operation status using PET. More...
EFI_STATUS | SendRpePetAlert (IN UINT8 RpeOperationCode, IN UINT8 RpeDevice, IN UINT8 RpeOperationStatus)
Send Remote Platform Erase operation status using PET. More...
EFI_STATUS | GetRsePassword (IN OUT CHAR16 *Password)
This function is deprecated. More...
EFI_STATUS | GetRsePasswordV2 (IN OUT CHAR8 *Password)
Use GetRsePassword to get disk password from the FW. More...
EFI_STATUS | AsfSetUefiBootOptionsState (IN AMT_BOOT_CONTROL AmtBootControl)
Set UEFI Boot Options States that are available for AMT to use by sending ASF command through HECI. More...
EFI_STATUS | AsfGetUefiBootOptionsState (OUT AMT_BOOT_CONTROL *AmtBootControl)
Get UEFI Boot Options States that are available for AMT use by sending ASF proper HECI Command. More...
EFI_STATUS | AsfUpdateUefiBootOptions (IN UEFI_BOOT_OPTION *UefiBootOptions, IN UINT16 NumOfUefiBootOptions)
Update UEFI Boot Options available to ASF by sending proper HECI Command. More...
EFI_STATUS | AsfGetUefiBootParameters (OUT UEFI_BOOT_OPTION_PARAMETER *UefiBootOptionWithParm)
Get Boot Option with Parameters that being requested from ASF by sending proper HECI Command. More...
EFI_STATUS | AsfGetRootCaCertificate (IN UINT32 Index, OUT ROOT_CA_CERTIFICATE *Cert)
Get Root Certificate Authority(CA) Certificate from ASF at specified Index by sending proper HECI Command. More...
EFI_STATUS | SendOcrPetAlert (IN UINT8 EventType, IN UINT8 LoadOptionType)
This function is deprecated. More...
EFI_STATUS | SendOcrPetEvent (IN UINT8 EventOffset, IN UINT8 EventData3, IN UINT8 EventData4)
Send One Click Recovery progress or error event using PET. More...
EFI_STATUS | AsfWifiGetProfileName (IN OUT WIFI_PROFILE_DATA *Profile)
Get the wireless profile name. More...
EFI_STATUS | AsfWifiGetProfileData (IN OUT WIFI_PROFILE_DATA *Profile)
Get the wireless profile data. More...
EFI_STATUS | AsfWifiGetClientCertificate (IN OUT WIFI_PROFILE *Profile)
Get the wireless profile specific 8021X client certificate. More...
EFI_STATUS | AsfWifiGetClientKey (IN OUT WIFI_PROFILE *Profile)
Get the wireless profile specific 8021X client key. More...

Detailed Description

Header file for AMT functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeAmtHeciLib.h.

Function Documentation

◆ AmtGetActiveLanInterface()

EFI_STATUS AmtGetActiveLanInterface ( OUT UINT8 * ActiveInterface )

This message is sent to get active LAN interface.

Parameters
[out] ActiveInterface Active Lan Interface 0: As defined in FIT 1: Integrated LAN 2: Discrete LAN
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ AmtQueryKvm()

EFI_STATUS AmtQueryKvm | ( | IN UINT32 | QueryType,
 |  | OUT UINT32 * | ResponseCode
 | ) |  |

This is used to send KVM request message to Intel ME.

When Bootoptions indicate that a KVM session is requested then BIOS will send this message before any graphical display output to ensure that FW is ready for KVM session.

Parameters
[in] | QueryType | 0 - Query Request 1 - Cancel Request
[out] | ResponseCode | 1h - Continue, KVM session established. 2h - Continue, KVM session cancelled.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ AmtSetActiveLanInterface()

EFI_STATUS AmtSetActiveLanInterface ( IN UINT8 ActiveInterface )

This message is sent to switch active LAN interface.

Parameters
[in] ActiveInterface Active Lan Interface 0: As defined in FIT 1: Integrated LAN 2: Discrete LAN
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ AmtSetMacPassthrough()

EFI_STATUS AmtSetMacPassthrough | ( | IN UINT8 | Enabled,
 |  | IN UINT8 * | MacAddress
 | ) |  |

This message is sent by the BIOS in order to pass MAC Address which should be used for LAN in a dock.

Parameters
[in] | Enabled | Determines if MAC Passthrough should be used
[in] | Mac | Address MAC Address to be used
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ AsfGetRootCaCertificate()

EFI_STATUS AsfGetRootCaCertificate | ( | IN UINT32 | Index,
 |  | OUT ROOT_CA_CERTIFICATE * | Cert
 | ) |  |

Get Root Certificate Authority(CA) Certificate from ASF at specified Index by sending proper HECI Command.

Parameters
[in] | Index | Index
[out] | Cert | Root CA Certificate
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid Boot Options State
EFI_NOT_FOUND | HECI Communication failed
EFI_DEVICE_ERROR | ASF Response is invalid

◆ AsfGetUefiBootOptionsState()

EFI_STATUS AsfGetUefiBootOptionsState ( OUT AMT_BOOT_CONTROL * AmtBootControl )

Get UEFI Boot Options States that are available for AMT use by sending ASF proper HECI Command.

Parameters
[out] AmtBootControl AMT boot control
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid Boot Options State
EFI_NOT_FOUND | HECI Communication failed
EFI_DEVICE_ERROR | ASF Response is invalid

◆ AsfGetUefiBootParameters()

EFI_STATUS AsfGetUefiBootParameters ( OUT UEFI_BOOT_OPTION_PARAMETER * UefiBootOptionWithParm )

Get Boot Option with Parameters that being requested from ASF by sending proper HECI Command.

Parameters
[out] UefiBootOptionWithParm UEFI Boot Option with parameters
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid Boot Options State
EFI_NOT_FOUND | HECI Communication failed
EFI_DEVICE_ERROR | ASF Response is invalid

◆ AsfSetUefiBootOptionsState()

EFI_STATUS AsfSetUefiBootOptionsState ( IN AMT_BOOT_CONTROL AmtBootControl )

Set UEFI Boot Options States that are available for AMT to use by sending ASF command through HECI.

Parameters
[in] AmtBootControl AMT boot control
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid Boot Options State
EFI_NOT_FOUND | HECI Communication failed
EFI_DEVICE_ERROR | ASF Response is invalid

◆ AsfStartWatchDog()

VOID AsfStartWatchDog ( IN UINT8 WatchDogType )

Start ASF Watch Dog Timer.

Parameters
[in] WatchDogType Which kind of WatchDog, ASF OS WatchDog Timer setting or ASF BIOS WatchDog Timer setting

◆ AsfUpdateUefiBootOptions()

EFI_STATUS AsfUpdateUefiBootOptions | ( | IN UEFI_BOOT_OPTION * | UefiBootOptions,
 |  | IN UINT16 | NumOfUefiBootOptions
 | ) |  |

Update UEFI Boot Options available to ASF by sending proper HECI Command.

Parameters
[in] | UefiBootOptions | UEFI Boot Options
[in] | NumOfUefiBootOptions | Number of UEFI Boot Options
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid Boot Options State
EFI_NOT_FOUND | HECI Communication failed
EFI_OUT_OF_RESOURCES | Ran out of resources
EFI_DEVICE_ERROR | ASF Response is invalid

◆ AsfWifiGetClientCertificate()

EFI_STATUS AsfWifiGetClientCertificate ( IN OUT WIFI_PROFILE * Profile )

Get the wireless profile specific 8021X client certificate.

Parameters
[in,out] Profile Profile data defined in wifi profile protocol
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
Returns
Others Error happened

◆ AsfWifiGetClientKey()

EFI_STATUS AsfWifiGetClientKey ( IN OUT WIFI_PROFILE * Profile )

Get the wireless profile specific 8021X client key.

Parameters
[in,out] Profile Profile data defined in wifi profile protocol
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
Returns
Others Error happened

◆ AsfWifiGetProfileData()

EFI_STATUS AsfWifiGetProfileData ( IN OUT WIFI_PROFILE_DATA * Profile )

Get the wireless profile data.

Parameters
[in,out] Profile Profile data defined in wifi profile protocol
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
Returns
Others Error happened

◆ AsfWifiGetProfileName()

EFI_STATUS AsfWifiGetProfileName ( IN OUT WIFI_PROFILE_DATA * Profile )

Get the wireless profile name.

Parameters
[in,out] Profile Profile where name will be held and used to aquire profile data, cert and key
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
Returns
Others Error happened

◆ GetRsePassword()

EFI_STATUS GetRsePassword ( IN OUT CHAR16 * Password )

This function is deprecated.

Use ASF_GetRsePassword to get disk password from the FW

Parameters
[in,out] Password Preallocated buffer to save c string password to. It has to be at least 32 characters wide.
Return values
EFI_SUCCESS | Buffer Password contains returned password
EFI_NOT_FOUND | Either there is no password in AMT memory or Heci communication failed
EFI_DEVICE_ERROR | Failed to initialize HECI
EFI_TIMEOUT | HECI is not ready for communication
EFI_UNSUPPORTED | Current ME mode doesn't support send this function

◆ GetRsePasswordV2()

EFI_STATUS GetRsePasswordV2 ( IN OUT CHAR8 * Password )

Use GetRsePassword to get disk password from the FW.

Parameters
[in,out] Password Preallocated buffer to save string password to. It has to be at least 32 characters wide.
Return values
EFI_SUCCESS | Buffer Password contains returned password
EFI_NOT_FOUND | Either there is no password in AMT memory or Heci communication failed
EFI_DEVICE_ERROR | Failed to initialize HECI
EFI_TIMEOUT | HECI is not ready for communication
EFI_UNSUPPORTED | Current ME mode doesn't support send this function

◆ SendOcrPetAlert()

EFI_STATUS SendOcrPetAlert | ( | IN UINT8 | EventType,
 |  | IN UINT8 | LoadOptionType
 | ) |  |

This function is deprecated.

Send One Click Recovery status using PET

Parameters
[in] | EventType | OCR Event Type
[in] | LoadOptionType | OCR Load Option Type
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded

◆ SendOcrPetEvent()

EFI_STATUS SendOcrPetEvent | ( | IN UINT8 | EventOffset,
 |  | IN UINT8 | EventData3,
 |  | IN UINT8 | EventData4
 | ) |  |

Send One Click Recovery progress or error event using PET.

Parameters
[in] | EventOffset | ASF Event Data Codes for OCR Fw Progress/Error Events
[in] | EventData3 | OCR Additional Event Data 3
[in] | EventData4 | OCR Additional Event Data 4
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded

◆ SendRpePetAlert()

EFI_STATUS SendRpePetAlert | ( | IN UINT8 | RpeOperationCode,
 |  | IN UINT8 | RpeDevice,
 |  | IN UINT8 | RpeOperationStatus
 | ) |  |

Send Remote Platform Erase operation status using PET.

Parameters
[in] | RpeOperationCode | PET Alert Code for the RPE Operation.
[in] | RpeDevice | Device for which the RPE OperationCode is reported.
[in] | RpeOperationStatus | Reports if RPE Operation is in progress or failure.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ SendRsePetAlert()

EFI_STATUS SendRsePetAlert ( IN EFI_STATUS OperationResult )

Send secure erase operation status using PET.

Parameters
[in] OperationResult Status of secure erase operation
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAmtHeciLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeAmtHeciLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for AMT functionality
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_AMT_HECI_LIB_H_
36 #define _DXE_AMT_HECI_LIB_H_
37
38 #include <AsfMsgs.h>
39 #include <WifiProfileSyncAsfMsgs.h>
40
41 /**
42 Stop ASF Watch Dog Timer HECI message.
43
44 **/
45 VOID
46 AsfStopWatchDog (
47 VOID
48 );
49
50 /**
51 Start ASF Watch Dog Timer
52
53 @param[in] WatchDogType Which kind of WatchDog, ASF OS WatchDog Timer setting or ASF BIOS WatchDog Timer setting
54
55 **/
56 VOID
57 AsfStartWatchDog (
58 IN UINT8 WatchDogType
59 );
60
61 /**
62 This message is sent to switch active LAN interface.
63
64 @param[in] ActiveInterface Active Lan Interface
65 0: As defined in FIT
66 1: Integrated LAN
67 2: Discrete LAN
68
69 @retval EFI_SUCCESS Command succeeded
70 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
71 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
72 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
73 **/
74 EFI_STATUS
75 AmtSetActiveLanInterface (
76 IN UINT8 ActiveInterface
77 );
78
79 /**
80 This message is sent to get active LAN interface.
81
82 @param[out] ActiveInterface Active Lan Interface
83 0: As defined in FIT
84 1: Integrated LAN
85 2: Discrete LAN
86
87 @retval EFI_SUCCESS Command succeeded
88 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
89 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
90 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
91 **/
92 EFI_STATUS
93 AmtGetActiveLanInterface (
94 OUT UINT8 *ActiveInterface
95 );
96
97 /**
98 This is used to send KVM request message to Intel ME. When
99 Bootoptions indicate that a KVM session is requested then BIOS
100 will send this message before any graphical display output to
101 ensure that FW is ready for KVM session.
102
103 @param[in] QueryType 0 - Query Request
104 1 - Cancel Request
105 @param[out] ResponseCode 1h - Continue, KVM session established.
106 2h - Continue, KVM session cancelled.
107
108 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
109 @retval EFI_SUCCESS Command succeeded
110 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
111 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
112 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
113 **/
114 EFI_STATUS
115 AmtQueryKvm (
116 IN UINT32 QueryType,
117 OUT UINT32 *ResponseCode
118 );
119
120 /**
121 This message is sent by the BIOS in order to pass MAC Address
122 which should be used for LAN in a dock.
123
124 @param[in] Enabled Determines if MAC Passthrough should be used
125 @param[in] Mac Address MAC Address to be used
126
127 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
128 @retval EFI_SUCCESS Command succeeded
129 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
130 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
131 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
132 **/
133 EFI_STATUS
134 AmtSetMacPassthrough (
135 IN UINT8 Enabled,
136 IN UINT8 *MacAddress
137 );
138
139 /**
140 Send secure erase operation status using PET
141
142 @param[in] OperationResult Status of secure erase operation
143
144 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
145 @retval EFI_SUCCESS Command succeeded
146 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
147 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
148 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
149 **/
150 EFI_STATUS
151 SendRsePetAlert (
152 IN EFI_STATUS OperationResult
153 );
154
155 /**
156 Send Remote Platform Erase operation status using PET
157
158 @param[in] RpeOperationCode PET Alert Code for the RPE Operation.
159 @param[in] RpeDevice Device for which the RPE OperationCode is reported.
160 @param[in] RpeOperationStatus Reports if RPE Operation is in progress or failure.
161
162 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
163 @retval EFI_SUCCESS Command succeeded
164 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
165 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
166 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
167 **/
168 EFI_STATUS
169 SendRpePetAlert (
170 IN UINT8 RpeOperationCode,
171 IN UINT8 RpeDevice,
172 IN UINT8 RpeOperationStatus
173 );
174
175 /**
176 This function is deprecated.
177 Use ASF_GetRsePassword to get disk password from the FW
178
179 @param[in,out] Password Preallocated buffer to save c string
180 password to. It has to be at least 32
181 characters wide.
182
183 @retval EFI_SUCCESS Buffer Password contains returned password
184 @retval EFI_NOT_FOUND Either there is no password in AMT memory
185 or Heci communication failed
186 @retval EFI_DEVICE_ERROR Failed to initialize HECI
187 @retval EFI_TIMEOUT HECI is not ready for communication
188 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this function
189 **/
190 EFI_STATUS
191 GetRsePassword (
192 IN OUT CHAR16 *Password
193 );
194
195 /**
196 Use GetRsePassword to get disk password from the FW
197
198 @param[in,out] Password Preallocated buffer to save string password to.
199 It has to be at least 32 characters wide.
200
201 @retval EFI_SUCCESS Buffer Password contains returned password
202 @retval EFI_NOT_FOUND Either there is no password in AMT memory or Heci communication failed
203 @retval EFI_DEVICE_ERROR Failed to initialize HECI
204 @retval EFI_TIMEOUT HECI is not ready for communication
205 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this function
206 **/
207 EFI_STATUS
208 GetRsePasswordV2 (
209 IN OUT CHAR8 *Password
210 );
211
212 /**
213 Set UEFI Boot Options States that are available for AMT to use by sending ASF
214 command through HECI
215
216 @param[in] AmtBootControl AMT boot control
217
218 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
219 @retval EFI_SUCCESS Command succeeded
220 @retval EFI_INVALID_PARAMETER Invalid Boot Options State
221 @retval EFI_NOT_FOUND HECI Communication failed
222 @retval EFI_DEVICE_ERROR ASF Response is invalid
223 **/
224 EFI_STATUS
225 AsfSetUefiBootOptionsState (
226 IN AMT_BOOT_CONTROL AmtBootControl
227 );
228
229 /**
230 Get UEFI Boot Options States that are available for AMT use by sending ASF
231 proper HECI Command.
232
233 @param[out] AmtBootControl AMT boot control
234
235 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
236 @retval EFI_SUCCESS Command succeeded
237 @retval EFI_INVALID_PARAMETER Invalid Boot Options State
238 @retval EFI_NOT_FOUND HECI Communication failed
239 @retval EFI_DEVICE_ERROR ASF Response is invalid
240 **/
241 EFI_STATUS
242 AsfGetUefiBootOptionsState (
243 OUT AMT_BOOT_CONTROL *AmtBootControl
244 );
245
246 /**
247 Update UEFI Boot Options available to ASF by sending proper HECI Command
248
249 @param[in] UefiBootOptions UEFI Boot Options
250 @param[in] NumOfUefiBootOptions Number of UEFI Boot Options
251
252 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
253 @retval EFI_SUCCESS Command succeeded
254 @retval EFI_INVALID_PARAMETER Invalid Boot Options State
255 @retval EFI_NOT_FOUND HECI Communication failed
256 @retval EFI_OUT_OF_RESOURCES Ran out of resources
257 @retval EFI_DEVICE_ERROR ASF Response is invalid
258 **/
259 EFI_STATUS
260 AsfUpdateUefiBootOptions (
261 IN UEFI_BOOT_OPTION *UefiBootOptions,
262 IN UINT16 NumOfUefiBootOptions
263 );
264
265 /**
266 Get Boot Option with Parameters that being requested from ASF by sending proper
267 HECI Command
268
269 @param[out] UefiBootOptionWithParm UEFI Boot Option with parameters
270
271 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
272 @retval EFI_SUCCESS Command succeeded
273 @retval EFI_INVALID_PARAMETER Invalid Boot Options State
274 @retval EFI_NOT_FOUND HECI Communication failed
275 @retval EFI_DEVICE_ERROR ASF Response is invalid
276 **/
277 EFI_STATUS
278 AsfGetUefiBootParameters (
279 OUT UEFI_BOOT_OPTION_PARAMETER *UefiBootOptionWithParm
280 );
281
282 /**
283 Get Root Certificate Authority(CA) Certificate from ASF at specified Index by sending
284 proper HECI Command
285
286 @param[in] Index Index
287 @param[out] Cert Root CA Certificate
288
289 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
290 @retval EFI_SUCCESS Command succeeded
291 @retval EFI_INVALID_PARAMETER Invalid Boot Options State
292 @retval EFI_NOT_FOUND HECI Communication failed
293 @retval EFI_DEVICE_ERROR ASF Response is invalid
294 **/
295 EFI_STATUS
296 AsfGetRootCaCertificate (
297 IN UINT32 Index,
298 OUT ROOT_CA_CERTIFICATE *Cert
299 );
300
301 /**
302 This function is deprecated.
303 Send One Click Recovery status using PET
304
305 @param[in] EventType OCR Event Type
306 @param[in] LoadOptionType OCR Load Option Type
307
308 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
309 @retval EFI_SUCCESS Command succeeded
310 **/
311 EFI_STATUS
312 SendOcrPetAlert (
313 IN UINT8 EventType,
314 IN UINT8 LoadOptionType
315 );
316
317 /**
318 Send One Click Recovery progress or error event using PET
319
320 @param[in] EventOffset ASF Event Data Codes for OCR Fw Progress/Error Events
321 @param[in] EventData3 OCR Additional Event Data 3
322 @param[in] EventData4 OCR Additional Event Data 4
323
324 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
325 @retval EFI_SUCCESS Command succeeded
326 **/
327 EFI_STATUS
328 SendOcrPetEvent (
329 IN UINT8 EventOffset,
330 IN UINT8 EventData3,
331 IN UINT8 EventData4
332 );
333
334 /**
335 Get the wireless profile name
336
337 @param[in, out] Profile Profile where name will be held and used to aquire profile data, cert and key
338
339 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
340 @retval EFI_SUCCESS Command succeeded
341 @return Others Error happened
342 **/
343 EFI_STATUS
344 AsfWifiGetProfileName (
345 IN OUT WIFI_PROFILE_DATA *Profile
346 );
347
348 /**
349 Get the wireless profile data
350
351 @param[in, out] Profile Profile data defined in wifi profile protocol
352
353 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
354 @retval EFI_SUCCESS Command succeeded
355 @return Others Error happened
356 **/
357 EFI_STATUS
358 AsfWifiGetProfileData (
359 IN OUT WIFI_PROFILE_DATA *Profile
360 );
361
362 /**
363 Get the wireless profile specific 8021X client certificate
364
365 @param[in, out] Profile Profile data defined in wifi profile protocol
366
367 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
368 @retval EFI_SUCCESS Command succeeded
369 @return Others Error happened
370 **/
371 EFI_STATUS
372 AsfWifiGetClientCertificate (
373 IN OUT WIFI_PROFILE *Profile
374 );
375
376 /**
377 Get the wireless profile specific 8021X client key
378
379 @param[in, out] Profile Profile data defined in wifi profile protocol
380
381 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
382 @retval EFI_SUCCESS Command succeeded
383 @return Others Error happened
384 **/
385 EFI_STATUS
386 AsfWifiGetClientKey (
387 IN OUT WIFI_PROFILE *Profile
388 );
389
390 #endif
AsfGetRootCaCertificate
EFI_STATUS AsfGetRootCaCertificate(IN UINT32 Index, OUT ROOT_CA_CERTIFICATE *Cert)
Get Root Certificate Authority(CA) Certificate from ASF at specified Index by sending proper HECI Com...
AsfWifiGetClientKey
EFI_STATUS AsfWifiGetClientKey(IN OUT WIFI_PROFILE *Profile)
Get the wireless profile specific 8021X client key.
AsfMsgs.h
AMT/ASF Messages.
AsfStopWatchDog
VOID AsfStopWatchDog(VOID)
Stop ASF Watch Dog Timer HECI message.
AsfStartWatchDog
VOID AsfStartWatchDog(IN UINT8 WatchDogType)
Start ASF Watch Dog Timer.
SendOcrPetAlert
EFI_STATUS SendOcrPetAlert(IN UINT8 EventType, IN UINT8 LoadOptionType)
This function is deprecated.
WifiProfileSyncAsfMsgs.h
Supporting functions for profile sync driver ASF communication.
SendRpePetAlert
EFI_STATUS SendRpePetAlert(IN UINT8 RpeOperationCode, IN UINT8 RpeDevice, IN UINT8 RpeOperationStatus)
Send Remote Platform Erase operation status using PET.
AmtSetActiveLanInterface
EFI_STATUS AmtSetActiveLanInterface(IN UINT8 ActiveInterface)
This message is sent to switch active LAN interface.
AsfGetUefiBootOptionsState
EFI_STATUS AsfGetUefiBootOptionsState(OUT AMT_BOOT_CONTROL *AmtBootControl)
Get UEFI Boot Options States that are available for AMT use by sending ASF proper HECI Command.
AmtQueryKvm
EFI_STATUS AmtQueryKvm(IN UINT32 QueryType, OUT UINT32 *ResponseCode)
This is used to send KVM request message to Intel ME.
AsfWifiGetClientCertificate
EFI_STATUS AsfWifiGetClientCertificate(IN OUT WIFI_PROFILE *Profile)
Get the wireless profile specific 8021X client certificate.
GetRsePasswordV2
EFI_STATUS GetRsePasswordV2(IN OUT CHAR8 *Password)
Use GetRsePassword to get disk password from the FW.
AsfGetUefiBootParameters
EFI_STATUS AsfGetUefiBootParameters(OUT UEFI_BOOT_OPTION_PARAMETER *UefiBootOptionWithParm)
Get Boot Option with Parameters that being requested from ASF by sending proper HECI Command.
AmtGetActiveLanInterface
EFI_STATUS AmtGetActiveLanInterface(OUT UINT8 *ActiveInterface)
This message is sent to get active LAN interface.
SendOcrPetEvent
EFI_STATUS SendOcrPetEvent(IN UINT8 EventOffset, IN UINT8 EventData3, IN UINT8 EventData4)
Send One Click Recovery progress or error event using PET.
AmtSetMacPassthrough
EFI_STATUS AmtSetMacPassthrough(IN UINT8 Enabled, IN UINT8 *MacAddress)
This message is sent by the BIOS in order to pass MAC Address which should be used for LAN in a dock.
GetRsePassword
EFI_STATUS GetRsePassword(IN OUT CHAR16 *Password)
This function is deprecated.
AsfWifiGetProfileData
EFI_STATUS AsfWifiGetProfileData(IN OUT WIFI_PROFILE_DATA *Profile)
Get the wireless profile data.
WIFI_PROFILE_DATA
Get Wifi profile data response from ASF.
Definition: WifiProfileSyncAsfMsgs.h:86
SendRsePetAlert
EFI_STATUS SendRsePetAlert(IN EFI_STATUS OperationResult)
Send secure erase operation status using PET.
AsfUpdateUefiBootOptions
EFI_STATUS AsfUpdateUefiBootOptions(IN UEFI_BOOT_OPTION *UefiBootOptions, IN UINT16 NumOfUefiBootOptions)
Update UEFI Boot Options available to ASF by sending proper HECI Command.
AsfWifiGetProfileName
EFI_STATUS AsfWifiGetProfileName(IN OUT WIFI_PROFILE_DATA *Profile)
Get the wireless profile name.
AsfSetUefiBootOptionsState
EFI_STATUS AsfSetUefiBootOptionsState(IN AMT_BOOT_CONTROL AmtBootControl)
Set UEFI Boot Options States that are available for AMT to use by sending ASF command through HECI.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAmtPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeAmtPolicyLib.h File Reference

Prototype of the DxeAmtPolicyLib library. More...

#include <Protocol/AmtPolicy.h>
Include dependency graph for DxeAmtPolicyLib.h:

Go to the source code of this file.

Functions

VOID | AmtPrintPolicyProtocol (IN AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function prints the AMT DXE phase policy. More...
EFI_STATUS | AmtCreatePolicyDefaults (IN OUT AMT_POLICY_PROTOCOL **DxeAmtPolicy)
AmtCreatePolicyDefaults creates the default setting of Amt Policy. More...
EFI_STATUS | AmtInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN AMT_POLICY_PROTOCOL *DxeAmtPolicy)
AmtInstallPolicyProtocol installs Amt Policy. More...

Detailed Description

Prototype of the DxeAmtPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeAmtPolicyLib.h.

Function Documentation

◆ AmtCreatePolicyDefaults()

EFI_STATUS AmtCreatePolicyDefaults ( IN OUT AMT_POLICY_PROTOCOL ** DxeAmtPolicy )

AmtCreatePolicyDefaults creates the default setting of Amt Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[in,out] DxeAmtPolicy The pointer to get Amt Policy protocol instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ AmtInstallPolicyProtocol()

EFI_STATUS AmtInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN AMT_POLICY_PROTOCOL * | DxeAmtPolicy
 | ) |  |

AmtInstallPolicyProtocol installs Amt Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | DxeAmtPolicy | The pointer to Amt Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ AmtPrintPolicyProtocol()

VOID AmtPrintPolicyProtocol ( IN AMT_POLICY_PROTOCOL * DxeAmtPolicy )

This function prints the AMT DXE phase policy.

Parameters
[in] DxeAmtPolicy - AMT DXE Policy protocol
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAmtPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeAmtPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the DxeAmtPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_AMT_POLICY_LIB_H_
36 #define _DXE_AMT_POLICY_LIB_H_
37
38 #include <Protocol/AmtPolicy.h>
39
40 /**
41 This function prints the AMT DXE phase policy.
42
43 @param[in] DxeAmtPolicy - AMT DXE Policy protocol
44 **/
45 VOID
46 AmtPrintPolicyProtocol (
47 IN AMT_POLICY_PROTOCOL *DxeAmtPolicy
48 );
49
50 /**
51 AmtCreatePolicyDefaults creates the default setting of Amt Policy.
52 It allocates and zero out buffer, and fills in the Intel default settings.
53
54 @param[in, out] DxeAmtPolicy The pointer to get Amt Policy protocol instance
55
56 @retval EFI_SUCCESS The policy default is initialized.
57 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
58
59 **/
60 EFI_STATUS
61 EFIAPI
62 AmtCreatePolicyDefaults (
63 IN OUT AMT_POLICY_PROTOCOL **DxeAmtPolicy
64 );
65
66 /**
67 AmtInstallPolicyProtocol installs Amt Policy.
68 While installed, RC assumes the Policy is ready and finalized. So please update and override
69 any setting before calling this function.
70
71 @param[in] ImageHandle Image handle of this driver.
72 @param[in] DxeAmtPolicy The pointer to Amt Policy Protocol instance
73
74 @retval EFI_SUCCESS The policy is installed.
75 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
76
77 **/
78 EFI_STATUS
79 EFIAPI
80 AmtInstallPolicyProtocol (
81 IN EFI_HANDLE ImageHandle,
82 IN AMT_POLICY_PROTOCOL *DxeAmtPolicy
83 );
84
85 #endif // _DXE_AMT_POLICY_LIB_H_
AmtInstallPolicyProtocol
EFI_STATUS AmtInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN AMT_POLICY_PROTOCOL *DxeAmtPolicy)
AmtInstallPolicyProtocol installs Amt Policy.
AmtPolicy.h
Interface definition details between AMT and platform drivers during DXE phase.
AmtCreatePolicyDefaults
EFI_STATUS AmtCreatePolicyDefaults(IN OUT AMT_POLICY_PROTOCOL **DxeAmtPolicy)
AmtCreatePolicyDefaults creates the default setting of Amt Policy.
AmtPrintPolicyProtocol
VOID AmtPrintPolicyProtocol(IN AMT_POLICY_PROTOCOL *DxeAmtPolicy)
This function prints the AMT DXE phase policy.
_AMT_POLICY_PROTOCOL
AMT DXE Policy This protocol is initialized by Policy driver.
Definition: AmtPolicy.h:64
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAsfHeciLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeAsfHeciLib.h File Reference

Header file for ASF functionality. More...

#include <AsfMsgs.h>
Include dependency graph for DxeAsfHeciLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | ClearBootOptions (VOID)
Clears boot options by sending a proper ASF command through HECI. More...
EFI_STATUS | GetBootOptions (OUT ASF_BOOT_OPTIONS *AsfBootOptions)
Get boot options by sending a proper ASF command through HECI. More...
EFI_STATUS | ReportBiosStatus (IN UINT32 BiosStatus)
Send ASF_ReportBiosStatus message. More...

Detailed Description

Header file for ASF functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeAsfHeciLib.h.

Function Documentation

◆ ClearBootOptions()

EFI_STATUS ClearBootOptions ( VOID )

Clears boot options by sending a proper ASF command through HECI.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ GetBootOptions()

EFI_STATUS GetBootOptions ( OUT ASF_BOOT_OPTIONS * AsfBootOptions )

Get boot options by sending a proper ASF command through HECI.

Parameters
[out] AsfBootOptions Boot Options returned from HECI
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_INVALID_PARAMETER | BootOptionsResponse is a NULL pointer

◆ ReportBiosStatus()

EFI_STATUS ReportBiosStatus ( IN UINT32 BiosStatus )

Send ASF_ReportBiosStatus message.

Parameters
[in] BiosStatus Current bios status
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAsfHeciLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeAsfHeciLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for ASF functionality
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_ASF_HECI_LIB_H_
36 #define _DXE_ASF_HECI_LIB_H_
37
38 #include <AsfMsgs.h>
39
40 /**
41 Clears boot options by sending a proper ASF command through HECI
42
43 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
44 @retval EFI_SUCCESS Command succeeded
45 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
46 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
47 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
48 **/
49 EFI_STATUS
50 ClearBootOptions (
51 VOID
52 );
53
54 /**
55 Get boot options by sending a proper ASF command through HECI
56
57 @param[out] AsfBootOptions Boot Options returned from HECI
58
59 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
60 @retval EFI_SUCCESS Command succeeded
61 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
62 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
63 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
64 @retval EFI_INVALID_PARAMETER BootOptionsResponse is a NULL pointer
65 **/
66 EFI_STATUS
67 GetBootOptions (
68 OUT ASF_BOOT_OPTIONS *AsfBootOptions
69 );
70
71 /**
72 Send ASF_ReportBiosStatus message
73
74 @param[in] BiosStatus Current bios status
75
76 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
77 @retval EFI_SUCCESS Command succeeded
78 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
79 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
80 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
81 **/
82 EFI_STATUS
83 ReportBiosStatus (
84 IN UINT32 BiosStatus
85 );
86 #endif
ClearBootOptions
EFI_STATUS ClearBootOptions(VOID)
Clears boot options by sending a proper ASF command through HECI.
AsfMsgs.h
AMT/ASF Messages.
ASF_BOOT_OPTIONS
Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message.
Definition: AsfMsgs.h:136
GetBootOptions
EFI_STATUS GetBootOptions(OUT ASF_BOOT_OPTIONS *AsfBootOptions)
Get boot options by sending a proper ASF command through HECI.
ReportBiosStatus
EFI_STATUS ReportBiosStatus(IN UINT32 BiosStatus)
Send ASF_ReportBiosStatus message.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAsfLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeAsfLib.h File Reference

Header file for ASF functionality. More...

Go to the source code of this file.

Functions

BOOLEAN | AsfIsIndustryIanaId (VOID)
Check if LANA ID of ASF boot options is Industry ID. More...
UINT8 | AsfGetSpecialCommand (VOID)
Get Special Commands of Intel ASF boot options. More...
UINT8 | AsfGetSpecialCmdParamHighByte (VOID)
Get Parameters of Special Commands High Byte in Intel ASF boot options. More...
UINT8 | AsfGetSpecialCmdParamLowByte (VOID)
Get Parameters of Special Commands Low Byte in Intel ASF boot options. More...
BOOLEAN | AsfIsStorageRedirectionEnabled (VOID)
This will return Storage Redirection Boot Option. More...
UINT8 | AsfGetStorageRedirectionBootDevice (VOID)
This will return Storage Redirection boot device number/type. More...
BOOLEAN | AsfIsEnforceSecureBootEnabled (VOID)
This will return Enforce Secure Boot over Storage Redirection Boot Option. More...
BOOLEAN | AsfGetRemoteFlashState (VOID)
This will return Remote Flash Boot Option. More...
BOOLEAN | AsfIsEnterSetupEnabled (VOID)
This will return BIOS Setup Boot Option. More...
BOOLEAN | AsfIsPauseBootEnabled (VOID)
This will return BIOS Pause Boot Option. More...
BOOLEAN | AsfIsKvmEnabled (VOID)
This will return KVM Boot Option. More...
BOOLEAN | AsfIsSecureEraseEnabled (VOID)
This will return Secure Erase Boot Option. More...
BOOLEAN | AsfIsSolEnabled (VOID)
This will return Serial-over-Lan Boot Option. More...
BOOLEAN | AsfIsConsoleLocked (VOID)
This will return Console Lock Boot Option. More...
BOOLEAN | AsfIsFwProgressEnabled (VOID)
This will return Progress Event Option. More...
BOOLEAN | AsfIsBootOptionsPresent (VOID)
Check if ASF boot options is present. More...
BOOLEAN | AsfIsRemotePlatformEraseEnabled (VOID)
This will return Remote Platform Erase Boot Option. More...
BOOLEAN | AsfIsConfigurationDataResetEnabled (VOID)
This will return Configuration data reset. More...

Detailed Description

Header file for ASF functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeAsfLib.h.

Function Documentation

◆ AsfGetRemoteFlashState()

BOOLEAN AsfGetRemoteFlashState ( VOID )

This will return Remote Flash Boot Option.

True if the option is enabled.

Return values
True | Remote Flash is enabled.
False | Remote Flash is disabled.

◆ AsfGetSpecialCmdParamHighByte()

UINT8 AsfGetSpecialCmdParamHighByte ( VOID )

Get Parameters of Special Commands High Byte in Intel ASF boot options.

Return values
UINT8 Parameters of Special Commands High Byte.

◆ AsfGetSpecialCmdParamLowByte()

UINT8 AsfGetSpecialCmdParamLowByte ( VOID )

Get Parameters of Special Commands Low Byte in Intel ASF boot options.

Return values
UINT8 Parameters of Special Commands Low Byte.

◆ AsfGetSpecialCommand()

UINT8 AsfGetSpecialCommand ( VOID )

Get Special Commands of Intel ASF boot options.

Return values
UINT8 Special Commands.

◆ AsfGetStorageRedirectionBootDevice()

UINT8 AsfGetStorageRedirectionBootDevice ( VOID )

This will return Storage Redirection boot device number/type.

Return values
UINT8 Return the boot device number to boot Bit 1 Bit0 0 0 USBr is connected to CD/DVD device 0 1 USBr is connected to floppy device Bits 2-7: Reserved set to 0

◆ AsfIsBootOptionsPresent()

BOOLEAN AsfIsBootOptionsPresent ( VOID )

Check if ASF boot options is present.

Return values
True | ASF boot option is present.
False | ASF boot option is not present

◆ AsfIsConfigurationDataResetEnabled()

BOOLEAN AsfIsConfigurationDataResetEnabled ( VOID )

This will return Configuration data reset.

True if the option is enabled.

Return values
True | Configuration data reset is enabled.
False | Configuration data reset is disabled.

◆ AsfIsConsoleLocked()

BOOLEAN AsfIsConsoleLocked ( VOID )

This will return Console Lock Boot Option.

True if the option is enabled.

Return values
True | Console Lock is enabled.
False | Console Lock is disabled.

◆ AsfIsEnforceSecureBootEnabled()

BOOLEAN AsfIsEnforceSecureBootEnabled ( VOID )

This will return Enforce Secure Boot over Storage Redirection Boot Option.

True if the option is enabled.

Return values
True | Enforce Secure Boot is enabled.
False | Enforce Secure Boot is disabled.

◆ AsfIsEnterSetupEnabled()

BOOLEAN AsfIsEnterSetupEnabled ( VOID )

This will return BIOS Setup Boot Option.

True if the option is enabled.

Return values
True | BIOS Setup is enabled.
False | BIOS Setup is disabled.

◆ AsfIsFwProgressEnabled()

BOOLEAN AsfIsFwProgressEnabled ( VOID )

This will return Progress Event Option.

True if the option is enabled.

Return values
True | Progress event is enabled.
False | Progress event is disabled.

◆ AsfIsIndustryIanaId()

BOOLEAN AsfIsIndustryIanaId ( VOID )

Check if LANA ID of ASF boot options is Industry ID.

Return values
True | IANA ID of ASF boot options is Industry ID.
False | IANA ID of ASF boot options is not Industry ID.

◆ AsfIsKvmEnabled()

BOOLEAN AsfIsKvmEnabled ( VOID )

This will return KVM Boot Option.

True if the option is enabled.

Return values
True | KVM is enabled.
False | KVM is disabled.

◆ AsfIsPauseBootEnabled()

BOOLEAN AsfIsPauseBootEnabled ( VOID )

This will return BIOS Pause Boot Option.

True if the option is enabled.

Return values
True | BIOS Pause is enabled.
False | BIOS Pause is disabled.

◆ AsfIsRemotePlatformEraseEnabled()

BOOLEAN AsfIsRemotePlatformEraseEnabled ( VOID )

This will return Remote Platform Erase Boot Option.

Return values
True | Remote Platform Erase is enabled.
False | Remote Platform Erase is disabled.

◆ AsfIsSecureEraseEnabled()

BOOLEAN AsfIsSecureEraseEnabled ( VOID )

This will return Secure Erase Boot Option.

True if the option is enabled.

Return values
True | Secure Erase is enabled.
False | Secure Erase is disabled.

◆ AsfIsSolEnabled()

BOOLEAN AsfIsSolEnabled ( VOID )

This will return Serial-over-Lan Boot Option.

True if the option is enabled.

Return values
True | Serial-over-Lan is enabled.
False | Serial-over-Lan is disabled.

◆ AsfIsStorageRedirectionEnabled()

BOOLEAN AsfIsStorageRedirectionEnabled ( VOID )

This will return Storage Redirection Boot Option.

True if the option is enabled.

Return values
True | Storage Redirection boot option is enabled.
False | Storage Redirection boot option is disabled.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeAsfLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeAsfLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for ASF functionality
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_ASF_LIB_H_
36 #define _DXE_ASF_LIB_H_
37
38 //
39 // Prototype for Alert Standard Format
40 //
41
42 /**
43 Check if LANA ID of ASF boot options is Industry ID.
44
45 @retval True IANA ID of ASF boot options is Industry ID.
46 @retval False IANA ID of ASF boot options is not Industry ID.
47 **/
48 BOOLEAN
49 AsfIsIndustryIanaId (
50 VOID
51 );
52
53 /**
54 Get Special Commands of Intel ASF boot options
55
56 @retval UINT8 Special Commands.
57 **/
58 UINT8
59 AsfGetSpecialCommand (
60 VOID
61 );
62
63 /**
64 Get Parameters of Special Commands High Byte in Intel ASF boot options
65
66 @retval UINT8 Parameters of Special Commands High Byte.
67 **/
68 UINT8
69 AsfGetSpecialCmdParamHighByte (
70 VOID
71 );
72
73 /**
74 Get Parameters of Special Commands Low Byte in Intel ASF boot options
75
76 @retval UINT8 Parameters of Special Commands Low Byte.
77 **/
78 UINT8
79 AsfGetSpecialCmdParamLowByte (
80 VOID
81 );
82
83 /**
84 This will return Storage Redirection Boot Option.
85 True if the option is enabled.
86
87 @retval True Storage Redirection boot option is enabled.
88 @retval False Storage Redirection boot option is disabled.
89 **/
90 BOOLEAN
91 AsfIsStorageRedirectionEnabled (
92 VOID
93 );
94
95 /**
96 This will return Storage Redirection boot device number/type
97
98 @retval UINT8 Return the boot device number to boot
99 Bit 1 Bit0
100 0 0 USBr is connected to CD/DVD device
101 0 1 USBr is connected to floppy device
102 Bits 2-7: Reserved set to 0
103 **/
104 UINT8
105 AsfGetStorageRedirectionBootDevice (
106 VOID
107 );
108
109 /**
110 This will return Enforce Secure Boot over Storage Redirection Boot Option.
111 True if the option is enabled.
112
113 @retval True Enforce Secure Boot is enabled.
114 @retval False Enforce Secure Boot is disabled.
115 **/
116 BOOLEAN
117 AsfIsEnforceSecureBootEnabled (
118 VOID
119 );
120
121 /**
122 This will return Remote Flash Boot Option.
123 True if the option is enabled.
124
125 @retval True Remote Flash is enabled.
126 @retval False Remote Flash is disabled.
127 **/
128 BOOLEAN
129 AsfGetRemoteFlashState (
130 VOID
131 );
132
133 /**
134 This will return BIOS Setup Boot Option.
135 True if the option is enabled.
136
137 @retval True BIOS Setup is enabled.
138 @retval False BIOS Setup is disabled.
139 **/
140 BOOLEAN
141 AsfIsEnterSetupEnabled (
142 VOID
143 );
144
145 /**
146 This will return BIOS Pause Boot Option.
147 True if the option is enabled.
148
149 @retval True BIOS Pause is enabled.
150 @retval False BIOS Pause is disabled.
151 **/
152 BOOLEAN
153 AsfIsPauseBootEnabled (
154 VOID
155 );
156
157 /**
158 This will return KVM Boot Option.
159 True if the option is enabled.
160
161 @retval True KVM is enabled.
162 @retval False KVM is disabled.
163 **/
164 BOOLEAN
165 AsfIsKvmEnabled (
166 VOID
167 );
168
169 /**
170 This will return Secure Erase Boot Option.
171 True if the option is enabled.
172
173 @retval True Secure Erase is enabled.
174 @retval False Secure Erase is disabled.
175 **/
176 BOOLEAN
177 AsfIsSecureEraseEnabled (
178 VOID
179 );
180
181 /**
182 This will return Serial-over-Lan Boot Option.
183 True if the option is enabled.
184
185 @retval True Serial-over-Lan is enabled.
186 @retval False Serial-over-Lan is disabled.
187 **/
188 BOOLEAN
189 AsfIsSolEnabled (
190 VOID
191 );
192
193 /**
194 This will return Console Lock Boot Option.
195 True if the option is enabled.
196
197 @retval True Console Lock is enabled.
198 @retval False Console Lock is disabled.
199 **/
200 BOOLEAN
201 AsfIsConsoleLocked (
202 VOID
203 );
204
205 /**
206 This will return Progress Event Option.
207 True if the option is enabled.
208
209 @retval True Progress event is enabled.
210 @retval False Progress event is disabled.
211 **/
212 BOOLEAN
213 AsfIsFwProgressEnabled (
214 VOID
215 );
216
217 /**
218 Check if ASF boot options is present.
219
220 @retval True ASF boot option is present.
221 @retval False ASF boot option is not present
222 **/
223 BOOLEAN
224 AsfIsBootOptionsPresent (
225 VOID
226 );
227
228 /**
229 This will return Remote Platform Erase Boot Option.
230
231 @retval True Remote Platform Erase is enabled.
232 @retval False Remote Platform Erase is disabled.
233 **/
234 BOOLEAN
235 AsfIsRemotePlatformEraseEnabled (
236 VOID
237 );
238
239 /**
240 This will return Configuration data reset.
241 True if the option is enabled.
242
243 @retval True Configuration data reset is enabled.
244 @retval False Configuration data reset is disabled.
245 **/
246 BOOLEAN
247 AsfIsConfigurationDataResetEnabled (
248 VOID
249 );
250
251 #endif
AsfGetSpecialCmdParamHighByte
UINT8 AsfGetSpecialCmdParamHighByte(VOID)
Get Parameters of Special Commands High Byte in Intel ASF boot options.
AsfIsStorageRedirectionEnabled
BOOLEAN AsfIsStorageRedirectionEnabled(VOID)
This will return Storage Redirection Boot Option.
AsfIsEnforceSecureBootEnabled
BOOLEAN AsfIsEnforceSecureBootEnabled(VOID)
This will return Enforce Secure Boot over Storage Redirection Boot Option.
AsfIsBootOptionsPresent
BOOLEAN AsfIsBootOptionsPresent(VOID)
Check if ASF boot options is present.
AsfIsFwProgressEnabled
BOOLEAN AsfIsFwProgressEnabled(VOID)
This will return Progress Event Option.
AsfGetSpecialCommand
UINT8 AsfGetSpecialCommand(VOID)
Get Special Commands of Intel ASF boot options.
AsfGetRemoteFlashState
BOOLEAN AsfGetRemoteFlashState(VOID)
This will return Remote Flash Boot Option.
AsfIsIndustryIanaId
BOOLEAN AsfIsIndustryIanaId(VOID)
Check if LANA ID of ASF boot options is Industry ID.
AsfIsRemotePlatformEraseEnabled
BOOLEAN AsfIsRemotePlatformEraseEnabled(VOID)
This will return Remote Platform Erase Boot Option.
AsfGetSpecialCmdParamLowByte
UINT8 AsfGetSpecialCmdParamLowByte(VOID)
Get Parameters of Special Commands Low Byte in Intel ASF boot options.
AsfIsSecureEraseEnabled
BOOLEAN AsfIsSecureEraseEnabled(VOID)
This will return Secure Erase Boot Option.
AsfIsSolEnabled
BOOLEAN AsfIsSolEnabled(VOID)
This will return Serial-over-Lan Boot Option.
AsfIsKvmEnabled
BOOLEAN AsfIsKvmEnabled(VOID)
This will return KVM Boot Option.
AsfIsConfigurationDataResetEnabled
BOOLEAN AsfIsConfigurationDataResetEnabled(VOID)
This will return Configuration data reset.
AsfIsEnterSetupEnabled
BOOLEAN AsfIsEnterSetupEnabled(VOID)
This will return BIOS Setup Boot Option.
AsfGetStorageRedirectionBootDevice
UINT8 AsfGetStorageRedirectionBootDevice(VOID)
This will return Storage Redirection boot device number/type.
AsfIsPauseBootEnabled
BOOLEAN AsfIsPauseBootEnabled(VOID)
This will return BIOS Pause Boot Option.
AsfIsConsoleLocked
BOOLEAN AsfIsConsoleLocked(VOID)
This will return Console Lock Boot Option.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeITbtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Classes | Typedefs
DxeITbtConfig.h File Reference

Headr file for iTBT DXE Policy. More...

#include <ConfigBlock.h>
#include <TcssInfo.h>
#include <DxeTbtCommonDefinition.h>
Include dependency graph for DxeITbtConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _DXE_ITBT_GENERIC_CONFIG
ITBT Generic Data Structure to be used cross to RP and controller in DXE phase. More...
struct | _DXE_ITBT_CONFIG
ITBT DXE configuration
Revision 1: More...

Typedefs

typedef struct _DXE_ITBT_GENERIC_CONFIG | DXE_ITBT_GENERIC_CONFIG
ITBT Generic Data Structure to be used cross to RP and controller in DXE phase.
typedef struct _DXE_ITBT_CONFIG | DXE_ITBT_CONFIG
ITBT DXE configuration
Revision 1: More...

Detailed Description

Headr file for iTBT DXE Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeITbtConfig.h.

Typedef Documentation

◆ DXE_ITBT_CONFIG

typedef struct _DXE_ITBT_CONFIG DXE_ITBT_CONFIG

ITBT DXE configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtVproDockSupport in DXE_ITBT_GENERIC_CONFIG structure.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeITbtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
DxeITbtConfig.h
Go to the documentation of this file.
1 /** @file
2 Headr file for iTBT DXE Policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _DXE_ITBT_CONFIG_H_
37 #define _DXE_ITBT_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #include <TcssInfo.h>
41 #include <DxeTbtCommonDefinition.h>
42
43 #pragma pack(push, 1)
44
45 #define DXE_ITBT_CONFIG_REVISION 2
46
47 ///
48 /// ITBT Generic Data Structure to be used cross to RP and controller in DXE phase
49 ///
50 typedef struct _DXE_ITBT_GENERIC_CONFIG{
51 UINT8 ITbtRtd3; ///< ITBT RTD3. - 0: Disable; <b>1: Enable</b>.
52 UINT8 ITbtVproDockSupport; ///< ITBT vPro Dock support. - <b>0: not support</b>; 1: supported.
53 UINT16 ITbtRtd3ExitDelay; ///< ITBT RTD3 delay before exit, unit is ms <b>0</b>.
54 } DXE_ITBT_GENERIC_CONFIG;
55
56 /**
57 ITBT DXE configuration\n
58 <b>Revision 1</b>:
59 - Initial version.
60 <b>Revision 2</b>:
61 - Add ITbtVproDockSupport in DXE_ITBT_GENERIC_CONFIG structure.
62 **/
63 typedef struct _DXE_ITBT_CONFIG {
64 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
65 TBT_COMMON_CONFIG TbtCommonConfig; ///< Tbt Common Information
66 DXE_ITBT_GENERIC_CONFIG ITbtGenericConfig; ///< ITbt Generic Information
67 TBT_RESOURCE_CONFIG ITbtResourceConfig[MAX_ITBT_PCIE_PORT]; ///< iTbt Resource Configuration
68 UINT8 OsNativeResourceBalance;
69 UINT8 Reserved[3];
70 } DXE_ITBT_CONFIG;
71
72 #pragma pack(pop)
73
74 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
DxeTbtCommonDefinition.h
TBT DXE Common Definition.
_DXE_ITBT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: DxeITbtConfig.h:64
_DXE_ITBT_CONFIG
ITBT DXE configuration Revision 1:
Definition: DxeITbtConfig.h:63
DXE_ITBT_GENERIC_CONFIG
struct _DXE_ITBT_GENERIC_CONFIG DXE_ITBT_GENERIC_CONFIG
ITBT Generic Data Structure to be used cross to RP and controller in DXE phase.
_DXE_ITBT_GENERIC_CONFIG::ITbtVproDockSupport
UINT8 ITbtVproDockSupport
ITBT vPro Dock support. - 0: not support; 1: supported.
Definition: DxeITbtConfig.h:52
_DXE_ITBT_CONFIG::ITbtGenericConfig
DXE_ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Generic Information.
Definition: DxeITbtConfig.h:66
_DXE_ITBT_CONFIG::TbtCommonConfig
TBT_COMMON_CONFIG TbtCommonConfig
Tbt Common Information.
Definition: DxeITbtConfig.h:65
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
_DXE_ITBT_GENERIC_CONFIG::ITbtRtd3ExitDelay
UINT16 ITbtRtd3ExitDelay
ITBT RTD3 delay before exit, unit is ms 0.
Definition: DxeITbtConfig.h:53
_DXE_ITBT_GENERIC_CONFIG
ITBT Generic Data Structure to be used cross to RP and controller in DXE phase.
Definition: DxeITbtConfig.h:50
_DXE_ITBT_GENERIC_CONFIG::ITbtRtd3
UINT8 ITbtRtd3
ITBT RTD3. - 0: Disable; 1: Enable.
Definition: DxeITbtConfig.h:51
_DXE_ITBT_CONFIG::ITbtResourceConfig
TBT_RESOURCE_CONFIG ITbtResourceConfig[MAX_ITBT_PCIE_PORT]
iTbt Resource Configuration
Definition: DxeITbtConfig.h:67
DXE_ITBT_CONFIG
struct _DXE_ITBT_CONFIG DXE_ITBT_CONFIG
ITBT DXE configuration Revision 1:
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeITbtPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeITbtPolicyLib.h File Reference

Prototype of the DxeITbtPolicyLib library. More...

#include <Protocol/ITbtPolicy.h>
Include dependency graph for DxeITbtPolicyLib.h:

Go to the source code of this file.

Functions

VOID | ITbtPrintDxePolicyConfig (IN ITBT_POLICY_PROTOCOL *ITbtPolicy)
Print DXE ITBT Policy. More...
EFI_STATUS | CreateITbtDxeConfigBlocks (IN OUT ITBT_POLICY_PROTOCOL **ITbtPolicy)
CreateITbtDxeConfigBlocks generates the config blocksg of iTBT DXE Policy. More...
EFI_STATUS | ITbtInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN ITBT_POLICY_PROTOCOL *ITbtPolicy)
ITbtInstallPolicyProtocol installs iTBT Policy. More...

Detailed Description

Prototype of the DxeITbtPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeITbtPolicyLib.h.

Function Documentation

◆ CreateITbtDxeConfigBlocks()

EFI_STATUS CreateITbtDxeConfigBlocks ( IN OUT ITBT_POLICY_PROTOCOL ** ITbtPolicy )

CreateITbtDxeConfigBlocks generates the config blocksg of iTBT DXE Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[out] ITbtPolicy The pointer to get iTBT DXE Protocol instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ ITbtInstallPolicyProtocol()

EFI_STATUS ITbtInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN ITBT_POLICY_PROTOCOL * | ITbtPolicy
 | ) |  |

ITbtInstallPolicyProtocol installs iTBT Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | ITbtPolicy | The pointer to TBT Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ ITbtPrintDxePolicyConfig()

VOID ITbtPrintDxePolicyConfig ( IN ITBT_POLICY_PROTOCOL * ITbtPolicy )

Print DXE ITBT Policy.

Parameters
[in] ITbtPolicy The pointer to get iTBT DXE Protocol instance
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeITbtPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeITbtPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the DxeITbtPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_ITBT_POLICY_LIB_H_
36 #define _DXE_ITBT_POLICY_LIB_H_
37
38 #include <Protocol/ITbtPolicy.h>
39 /**
40 Print DXE ITBT Policy
41
42 @param[in] ITbtPolicy The pointer to get iTBT DXE Protocol instance
43 **/
44 VOID
45 ITbtPrintDxePolicyConfig (
46 IN ITBT_POLICY_PROTOCOL *ITbtPolicy
47 );
48
49 /**
50 CreateITbtDxeConfigBlocks generates the config blocksg of iTBT DXE Policy.
51 It allocates and zero out buffer, and fills in the Intel default settings.
52
53 @param[out] ITbtPolicy The pointer to get iTBT DXE Protocol instance
54
55 @retval EFI_SUCCESS The policy default is initialized.
56 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
57 **/
58 EFI_STATUS
59 EFIAPI
60 CreateITbtDxeConfigBlocks (
61 IN OUT ITBT_POLICY_PROTOCOL **ITbtPolicy
62 );
63
64 /**
65 ITbtInstallPolicyProtocol installs iTBT Policy.
66 While installed, RC assumes the Policy is ready and finalized. So please update and override
67 any setting before calling this function.
68
69 @param[in] ImageHandle Image handle of this driver.
70 @param[in] ITbtPolicy The pointer to TBT Policy Protocol instance
71
72 @retval EFI_SUCCESS The policy is installed.
73 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
74
75 **/
76 EFI_STATUS
77 EFIAPI
78 ITbtInstallPolicyProtocol (
79 IN EFI_HANDLE ImageHandle,
80 IN ITBT_POLICY_PROTOCOL *ITbtPolicy
81 )
82 ;
83
84 #endif // _DXE_ITBT_POLICY_LIB_H_
ITbtPolicy.h
Interface definition details between TBT and platform drivers during DXE phase.
ITbtInstallPolicyProtocol
EFI_STATUS ITbtInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN ITBT_POLICY_PROTOCOL *ITbtPolicy)
ITbtInstallPolicyProtocol installs iTBT Policy.
ITBT_POLICY_PROTOCOL
ITBT DXE Policy.
Definition: ITbtPolicy.h:69
ITbtPrintDxePolicyConfig
VOID ITbtPrintDxePolicyConfig(IN ITBT_POLICY_PROTOCOL *ITbtPolicy)
Print DXE ITBT Policy.
CreateITbtDxeConfigBlocks
EFI_STATUS CreateITbtDxeConfigBlocks(IN OUT ITBT_POLICY_PROTOCOL **ITbtPolicy)
CreateITbtDxeConfigBlocks generates the config blocksg of iTBT DXE Policy.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeJhiSupportLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeJhiSupportLib.h File Reference

Header file for JHI helper functionality. More...

#include <Protocol/SimpleFileSystem.h>
#include <Guid/FileInfo.h>
#include <Library/PrintLib.h>
Include dependency graph for DxeJhiSupportLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | FileOpen (IN CHAR16 *Filename, OUT EFI_FILE **FileHandle)
Open file. More...
EFI_STATUS | FileClose (IN EFI_FILE *FileHandle)
Close file and relase all allocated resource. More...
EFI_STATUS | FileRead (IN EFI_FILE *FileHandle, OUT VOID **Buffer, OUT UINTN *BufferSize)
Read file contents to the buffer. More...
CHAR8 | InternalAsciiToUpper (IN CHAR8 c)
Convert ASCII character to upper case. More...
CHAR8 | AsciiToLower (IN CHAR8 c)
Convert ASCII character to lower case. More...
BOOLEAN | AsciiIsDigit (IN CHAR8 c)
Check the ASCII character is digital or not. More...
BOOLEAN | AsciiIsAlphabet (IN CHAR8 c)
Check the ASCII character is alphabet or not. More...
UINT8 | AsciiChar2Hex (IN CHAR8 c)
Convert ASCII character to hex value. More...
CHAR8 | AsciiHex2Char (UINT8 h)
Convert hex value to ASCII character. More...
BOOLEAN | AsciiStrIsUuid1 (IN CONST CHAR8 *str)
Check the ASCII string is UUID format#1 or not. More...
BOOLEAN | AsciiStrIsUuid2 (IN CONST CHAR8 *str)
Check the ASCII string is UUID format#2 or not. More...
BOOLEAN | AsciiStr2Uuid (IN CONST CHAR8 *str, OUT UINT8 *uuid)
Convert the ASCII string to UUID format. More...
BOOLEAN | AsciiUuid2Str (IN UINT8 *uuid, OUT CHAR8 *str)
Convert the UUID format to ASCII string. More...

Detailed Description

Header file for JHI helper functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeJhiSupportLib.h.

Function Documentation

◆ AsciiChar2Hex()

UINT8 AsciiChar2Hex ( IN CHAR8 c )

Convert ASCII character to hex value.

Parameters
[in] c The ASCII character to be converted.
Return values
The hex value of this ASCII character.

◆ AsciiHex2Char()

CHAR8 AsciiHex2Char ( UINT8 h )

Convert hex value to ASCII character.

Parameters
[in] h The hex value to be converted.
Return values
The ASCII character of this hex value.

◆ AsciiIsAlphabet()

BOOLEAN AsciiIsAlphabet ( IN CHAR8 c )

Check the ASCII character is alphabet or not.

Parameters
[in] c The ASCII character to be checked.
Return values
TRUE | The ASCII character is alphabet.
FALSE | The ASCII character is not alphabet.

◆ AsciiIsDigit()

BOOLEAN AsciiIsDigit ( IN CHAR8 c )

Check the ASCII character is digital or not.

Parameters
[in] c The ASCII character to be checked.
Return values
TRUE | The ASCII character is digital.
FALSE | The ASCII character is not digital.

◆ AsciiStr2Uuid()

BOOLEAN AsciiStr2Uuid | ( | IN CONST CHAR8 * | str,
 |  | OUT UINT8 * | uuid
 | ) |  |

Convert the ASCII string to UUID format.

Parameters
[in] | str | The ASCII string to be converted.
[out] | uuid | The pointer of buffer to store UUID format.
Return values
TRUE | The conversion is successful.
FALSE | The conversion is failed.

◆ AsciiStrIsUuid1()

BOOLEAN AsciiStrIsUuid1 ( IN CONST CHAR8 * str )

Check the ASCII string is UUID format#1 or not.

EX: UUID format#1: "A9AB50A7222C434D943BEBB886186BF0"

Parameters
[in] str The ASCII string to be checked.
Return values
TRUE | The ASCII string is UUID format.
FALSE | The ASCII string is not UUID format.

◆ AsciiStrIsUuid2()

BOOLEAN AsciiStrIsUuid2 ( IN CONST CHAR8 * str )

Check the ASCII string is UUID format#2 or not.

EX: UUID format#2: "A9AB50A7-222C-434D-943B-EBB886186BF0"

Parameters
[in] str The ASCII string to be checked.
Return values
TRUE | The ASCII string is UUID format.
FALSE | The ASCII string is not UUID format.

◆ AsciiToLower()

CHAR8 AsciiToLower ( IN CHAR8 c )

Convert ASCII character to lower case.

Parameters
[in] c The ASCII character to be converted.
Return values
The lower case of this ASCII character.

◆ AsciiUuid2Str()

BOOLEAN AsciiUuid2Str | ( | IN UINT8 * | uuid,
 |  | OUT CHAR8 * | str
 | ) |  |

Convert the UUID format to ASCII string.

Parameters
[in] | uuid | The pointer to the UUID format to be converted.
[out] | str | The pointer to the converted ASCII string.
Return values
TRUE | The conversion is successful.
FALSE | The conversion is failed.

◆ FileClose()

EFI_STATUS FileClose ( IN EFI_FILE * FileHandle )

Close file and relase all allocated resource.

Parameters
[in] FileHandle Pointer to the file handle.
Return values
EFI_SUCCESS | File close successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
Others | for error status code of Close function.

◆ FileOpen()

EFI_STATUS FileOpen | ( | IN CHAR16 * | Filename,
 |  | OUT EFI_FILE ** | FileHandle
 | ) |  |

Open file.

Parameters
[in] | Filename | The file to be opened. Filename should be absolute path+filename, ie: L"\\Jhi\\TestApplet.sign"
[out] | FileHandle | Pointer to the file handle.
Return values
EFI_SUCCESS | File open successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
Others | for error status code of LocateHandleBuffer, HandleProtocol, OpenVolume, and Open functions.

◆ FileRead()

EFI_STATUS FileRead | ( | IN EFI_FILE * | FileHandle,
 |  | OUT VOID ** | Buffer,
 |  | OUT UINTN * | BufferSize
 | ) |  |

Read file contents to the buffer.

Parameters
[in] | FileHandle | Pointer to the file handle.
[out] | Buffer | Pointer to the buffer for read.
[out] | BufferSize | Pointer to the buffer size for read.
Return values
EFI_SUCCESS | File read successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
EFI_OUT_OF_RESOURCES | Memory allocation fail.
Others | for error status code of GetInfo, and Read functions.

◆ InternalAsciiToUpper()

CHAR8 InternalAsciiToUpper ( IN CHAR8 c )

Convert ASCII character to upper case.

Parameters
[in] c The ASCII character to be converted.
Return values
The upper case of this ASCII character.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeJhiSupportLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeJhiSupportLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for JHI helper functionality.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __DXE_JHI_SUPPORT_LIB_H__
37 #define __DXE_JHI_SUPPORT_LIB_H__
38
39
40 //
41 // File
42 //
43 #include <Protocol/SimpleFileSystem.h>
44 #include <Guid/FileInfo.h>
45
46
47 /**
48 Open file.
49
50 @param[in] Filename The file to be opened.
51 Filename should be absolute path+filename, ie: L"\\Jhi\\TestApplet.sign"
52 @param[out] FileHandle Pointer to the file handle.
53
54 @retval EFI_SUCCESS File open successfully.
55 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
56 @retval Others for error status code of LocateHandleBuffer, HandleProtocol, OpenVolume, and Open functions.
57 **/
58 EFI_STATUS
59 FileOpen (
60 IN CHAR16 *Filename,
61 OUT EFI_FILE **FileHandle
62 );
63
64 /**
65 Close file and relase all allocated resource.
66
67 @param[in] FileHandle Pointer to the file handle.
68
69 @retval EFI_SUCCESS File close successfully.
70 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
71 @retval Others for error status code of Close function.
72 **/
73 EFI_STATUS
74 FileClose (
75 IN EFI_FILE *FileHandle
76 );
77
78 /**
79 Read file contents to the buffer.
80
81 @param[in] FileHandle Pointer to the file handle.
82 @param[out] Buffer Pointer to the buffer for read.
83 @param[out] BufferSize Pointer to the buffer size for read.
84
85 @retval EFI_SUCCESS File read successfully.
86 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
87 @retval EFI_OUT_OF_RESOURCES Memory allocation fail.
88 @retval Others for error status code of GetInfo, and Read functions.
89 **/
90 EFI_STATUS
91 FileRead (
92 IN EFI_FILE *FileHandle,
93 OUT VOID **Buffer,
94 OUT UINTN *BufferSize
95 );
96
97 //
98 // StrHelper
99 //
100 /**
101 Convert ASCII character to upper case.
102
103 @param[in] c The ASCII character to be converted.
104
105 @retval The upper case of this ASCII character.
106 **/
107 CHAR8
108 InternalAsciiToUpper (
109 IN CHAR8 c
110 );
111
112 /**
113 Convert ASCII character to lower case.
114
115 @param[in] c The ASCII character to be converted.
116
117 @retval The lower case of this ASCII character.
118 **/
119 CHAR8
120 AsciiToLower (
121 IN CHAR8 c
122 );
123
124 /**
125 Check the ASCII character is digital or not.
126
127 @param[in] c The ASCII character to be checked.
128
129 @retval TRUE The ASCII character is digital.
130 @retval FALSE The ASCII character is not digital.
131 **/
132 BOOLEAN
133 AsciiIsDigit (
134 IN CHAR8 c
135 );
136
137 /**
138 Check the ASCII character is alphabet or not.
139
140 @param[in] c The ASCII character to be checked.
141
142 @retval TRUE The ASCII character is alphabet.
143 @retval FALSE The ASCII character is not alphabet.
144 **/
145 BOOLEAN
146 AsciiIsAlphabet (
147 IN CHAR8 c
148 );
149
150 /**
151 Convert ASCII character to hex value.
152
153 @param[in] c The ASCII character to be converted.
154
155 @retval The hex value of this ASCII character.
156 **/
157 UINT8
158 AsciiChar2Hex (
159 IN CHAR8 c
160 );
161
162 /**
163 Convert hex value to ASCII character.
164
165 @param[in] h The hex value to be converted.
166
167 @retval The ASCII character of this hex value.
168 **/
169 CHAR8
170 AsciiHex2Char (
171 UINT8 h
172 );
173
174 /**
175 Check the ASCII string is UUID format#1 or not.
176 EX: UUID format#1: "A9AB50A7222C434D943BEBB886186BF0"
177
178 @param[in] str The ASCII string to be checked.
179
180 @retval TRUE The ASCII string is UUID format.
181 @retval FALSE The ASCII string is not UUID format.
182 **/
183 BOOLEAN
184 AsciiStrIsUuid1 (
185 IN CONST CHAR8 *str
186 );
187
188 /**
189 Check the ASCII string is UUID format#2 or not.
190 EX: UUID format#2: "A9AB50A7-222C-434D-943B-EBB886186BF0"
191
192 @param[in] str The ASCII string to be checked.
193
194 @retval TRUE The ASCII string is UUID format.
195 @retval FALSE The ASCII string is not UUID format.
196 **/
197 BOOLEAN
198 AsciiStrIsUuid2 (
199 IN CONST CHAR8 *str
200 );
201
202 /**
203 Convert the ASCII string to UUID format.
204
205 @param[in] str The ASCII string to be converted.
206 @param[out] uuid The pointer of buffer to store UUID format.
207
208 @retval TRUE The conversion is successful.
209 @retval FALSE The conversion is failed.
210 **/
211 BOOLEAN
212 AsciiStr2Uuid (
213 IN CONST CHAR8 *str,
214 OUT UINT8 *uuid
215 );
216
217 /**
218 Convert the UUID format to ASCII string.
219
220 @param[in] uuid The pointer to the UUID format to be converted.
221 @param[out] str The pointer to the converted ASCII string.
222
223 @retval TRUE The conversion is successful.
224 @retval FALSE The conversion is failed.
225 **/
226 BOOLEAN
227 AsciiUuid2Str ( // uuid_to_string
228 IN UINT8 *uuid,
229 OUT CHAR8 *str
230 );
231
232
233 //
234 // MsgPrint
235 //
236 #include <Library/PrintLib.h>
237
238 #define MSGPRINTF(s) Print s
239 #ifndef _T
240 #define _T(x) L##x
241 #endif
242 #define MSGRAWDUMP(s) RawdataDump s
243
244 #define RAWDATADUMP_COLNUM_PER_ROW 16
245
246 VOID
247 RawdataDump (
248 IN VOID *buff,
249 IN UINTN size
250 );
251
252 VOID
253 DbgRawdataDump (
254 IN VOID *buff,
255 IN UINTN size
256 );
257
258 #endif // __DXE_JHI_SUPPORT_LIB_H__
259
FileRead
EFI_STATUS FileRead(IN EFI_FILE *FileHandle, OUT VOID **Buffer, OUT UINTN *BufferSize)
Read file contents to the buffer.
AsciiIsAlphabet
BOOLEAN AsciiIsAlphabet(IN CHAR8 c)
Check the ASCII character is alphabet or not.
AsciiHex2Char
CHAR8 AsciiHex2Char(UINT8 h)
Convert hex value to ASCII character.
AsciiToLower
CHAR8 AsciiToLower(IN CHAR8 c)
Convert ASCII character to lower case.
AsciiStrIsUuid1
BOOLEAN AsciiStrIsUuid1(IN CONST CHAR8 *str)
Check the ASCII string is UUID format#1 or not.
FileOpen
EFI_STATUS FileOpen(IN CHAR16 *Filename, OUT EFI_FILE **FileHandle)
Open file.
InternalAsciiToUpper
CHAR8 InternalAsciiToUpper(IN CHAR8 c)
Convert ASCII character to upper case.
AsciiIsDigit
BOOLEAN AsciiIsDigit(IN CHAR8 c)
Check the ASCII character is digital or not.
AsciiUuid2Str
BOOLEAN AsciiUuid2Str(IN UINT8 *uuid, OUT CHAR8 *str)
Convert the UUID format to ASCII string.
AsciiChar2Hex
UINT8 AsciiChar2Hex(IN CHAR8 c)
Convert ASCII character to hex value.
FileClose
EFI_STATUS FileClose(IN EFI_FILE *FileHandle)
Close file and relase all allocated resource.
AsciiStrIsUuid2
BOOLEAN AsciiStrIsUuid2(IN CONST CHAR8 *str)
Check the ASCII string is UUID format#2 or not.
AsciiStr2Uuid
BOOLEAN AsciiStr2Uuid(IN CONST CHAR8 *str, OUT UINT8 *uuid)
Convert the ASCII string to UUID format.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMebxDisplayWrapperLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeMebxDisplayWrapperLib.h File Reference

Wrapper functions for MEBx display protocol functions. More...

#include <Protocol/MebxDisplayProtocol.h>
Include dependency graph for DxeMebxDisplayWrapperLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | MebxConfigureScreen (IN BOOLEAN ScreenType)
This function configures screen. More...
EFI_STATUS | MebxDisplayText (IN MEBX_MSG_ID Token)
This function prints MEBx information string to screen. More...
EFI_STATUS | MebxDisplayError (IN MEBX_MSG_ID MsgId)
This function prints MEBx error string to screen and to console. More...
EFI_STATUS | MebxDisplayErrorId (IN UINT16 ModuleId, IN UINT16 VariableId)
This function prints MEBx error string with information about corrupted data entry. More...
EFI_STATUS | MebxReadUserInput (OUT MEBX_USER_INPUT *UserInput)
This function gets user input. More...
EFI_STATUS | MebxClearScreen (VOID)
This function clears a screen's content. More...

Detailed Description

Wrapper functions for MEBx display protocol functions.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeMebxDisplayWrapperLib.h.

Function Documentation

◆ MebxClearScreen()

EFI_STATUS MebxClearScreen ( VOID )

This function clears a screen's content.

Return values
EFI_SUCCESS | The function succeeded
Others | Error has occurred

◆ MebxConfigureScreen()

EFI_STATUS MebxConfigureScreen ( IN BOOLEAN ScreenType )

This function configures screen.

Parameters
[in] ScreenType Screen type, the value can indicate the BIOS screen or MEBx screen.
Return values
EFI_SUCCESS | Screen was initialized successfully
Others | Error has occured during screen initialization

◆ MebxDisplayError()

EFI_STATUS MebxDisplayError ( IN MEBX_MSG_ID MsgId )

This function prints MEBx error string to screen and to console.

Parameters
[in] MsgId Message Id which will be displayed
Return values
EFI_SUCCESS | Text was displayed successfully
EFI_NOT_FOUND | The string specified by Token isn't present

◆ MebxDisplayErrorId()

EFI_STATUS MebxDisplayErrorId | ( | IN UINT16 | ModuleId,
 |  | IN UINT16 | VariableId
 | ) |  |

This function prints MEBx error string with information about corrupted data entry.

Parameters
[in] | ModuleId | Module id
[in] | VariableId | Variable id
Return values
EFI_SUCCESS | Text was displayed successfully
Others | Error has occurred during displaying text

◆ MebxDisplayText()

EFI_STATUS MebxDisplayText ( IN MEBX_MSG_ID Token )

This function prints MEBx information string to screen.

Parameters
[in] MsgId Message id
Return values
EFI_SUCCESS | Screen was initialized successfully
Others | Error has occured during screen initialization

◆ MebxReadUserInput()

EFI_STATUS MebxReadUserInput ( OUT MEBX_USER_INPUT * UserInput )

This function gets user input.

Parameters
[out] UserInput User input
Return values
EFI_SUCCESS | Successfully read user input
EFI_NOT_READY | There was no input from an user.
EFI_INVALID_PARAMETER | Invalid parameter
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMebxDisplayWrapperLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeMebxDisplayWrapperLib.h
Go to the documentation of this file.
1 /** @file
2 Wrapper functions for MEBx display protocol functions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _DISPLAY_WRAPPER_H_
37 #define _DISPLAY_WRAPPER_H_
38
39 #include <Protocol/MebxDisplayProtocol.h>
40
41 /**
42 This function configures screen.
43
44 @param[in] ScreenType Screen type, the value can indicate the BIOS screen or MEBx screen.
45
46 @retval EFI_SUCCESS Screen was initialized successfully
47 @retval Others Error has occured during screen initialization
48 **/
49 EFI_STATUS
50 MebxConfigureScreen (
51 IN BOOLEAN ScreenType
52 );
53
54 /**
55 This function prints MEBx information string to screen.
56
57 @param[in] MsgId Message id
58
59 @retval EFI_SUCCESS Screen was initialized successfully
60 @retval Others Error has occured during screen initialization
61 **/
62 EFI_STATUS
63 MebxDisplayText (
64 IN MEBX_MSG_ID Token
65 );
66
67 /**
68 This function prints MEBx error string to screen and to console.
69
70 @param[in] MsgId Message Id which will be displayed
71
72 @retval EFI_SUCCESS Text was displayed successfully
73 @retval EFI_NOT_FOUND The string specified by Token isn't present
74 **/
75 EFI_STATUS
76 MebxDisplayError (
77 IN MEBX_MSG_ID MsgId
78 );
79
80 /**
81 This function prints MEBx error string with information about corrupted data entry.
82
83 @param[in] ModuleId Module id
84 @param[in] VariableId Variable id
85
86 @retval EFI_SUCCESS Text was displayed successfully
87 @retval Others Error has occurred during displaying text
88 **/
89 EFI_STATUS
90 MebxDisplayErrorId (
91 IN UINT16 ModuleId,
92 IN UINT16 VariableId
93 );
94
95 /**
96 This function gets user input.
97
98 @param[out] UserInput User input
99
100 @retval EFI_SUCCESS Successfully read user input
101 @retval EFI_NOT_READY There was no input from an user.
102 @retval EFI_INVALID_PARAMETER Invalid parameter
103 **/
104 EFI_STATUS
105 MebxReadUserInput (
106 OUT MEBX_USER_INPUT *UserInput
107 );
108
109 /**
110 This function clears a screen's content.
111
112 @retval EFI_SUCCESS The function succeeded
113 @retval Others Error has occurred
114 **/
115 EFI_STATUS
116 MebxClearScreen (
117 VOID
118 );
119
120 #endif // _DISPLAY_WRAPPER_H_
MebxDisplayErrorId
EFI_STATUS MebxDisplayErrorId(IN UINT16 ModuleId, IN UINT16 VariableId)
This function prints MEBx error string with information about corrupted data entry.
MebxClearScreen
EFI_STATUS MebxClearScreen(VOID)
This function clears a screen's content.
MebxReadUserInput
EFI_STATUS MebxReadUserInput(OUT MEBX_USER_INPUT *UserInput)
This function gets user input.
MebxDisplayProtocol.h
MEBx Display Protocol definitions.
MebxConfigureScreen
EFI_STATUS MebxConfigureScreen(IN BOOLEAN ScreenType)
This function configures screen.
MEBX_MSG_ID
MEBX_MSG_ID
MEBx Message ID.
Definition: MebxDisplayProtocol.h:60
MebxDisplayError
EFI_STATUS MebxDisplayError(IN MEBX_MSG_ID MsgId)
This function prints MEBx error string to screen and to console.
MebxDisplayText
EFI_STATUS MebxDisplayText(IN MEBX_MSG_ID Token)
This function prints MEBx information string to screen.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMebxWrapperLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeMebxWrapperLib.h File Reference

Header file for MEBx Wrapper Library. More...

#include <AmthiMsgs.h>
#include <Protocol/GraphicsOutput.h>
Include dependency graph for DxeMebxWrapperLib.h:

Go to the source code of this file.

Functions

BOOLEAN | MebxIsAmthiInterfaceVersionSupported (VOID)
Check if BIOS supports the currently used AMTHI Interface version. More...
EFI_STATUS | MebxGetIpv4Params (IN UINT32 Interface, IN BOOLEAN GetDynamicIpAddress, OUT UINT8 *IsLanlessPlatform, OUT IMB_TCPIP_PARAMS *Ipv4Cfg)
Retrieve current IPV4 TCPIP Parameters. More...
EFI_STATUS | MebxSetIpv4Params (IN IMB_TCPIP_PARAMS *NewIpv4Cfg)
Update current IPV4 TCPIP Parameters. More...
EFI_STATUS | MebxPerformUnprovisioning (IN UINT8 UnprovisionType)
Performs Intel(R) AMT full and partial unprovisioning flows. More...
EFI_STATUS | MebxGetProvisioningState (OUT UINT32 *ProvisioningState)
Retrieve current provisioning state. More...
EFI_STATUS | MebxSetSolStorageRedir (IN UINT16 NewSolStatus, IN UINT16 NewStorageRedirStatus)
Update current SOL and Storage Redirection state. More...
EFI_STATUS | MebxGetEndOfPostState (OUT CFG_EOP_STATE *State)
Retrieve current EoP state. More...
EFI_STATUS | MebxGetHashedCertificates (OUT UINT32 *CertQuantity, OUT UINT32 *CertHandle, OUT CERT_HASH_ENTRY *CertHashEntry)
Retrieve available Hashed Certificates. More...
EFI_STATUS | MebxSetPkiFqdnSuffix (IN FQDN_SUFFIX_ANSI_STRING *NewPkiDns)
Update current PKI FQDN DNS Suffix. More...
EFI_STATUS | MebxGetZtcEnabledStatus (OUT UINT32 *ZtcEnabledStatus)
Retrieve ZTC State. More...
EFI_STATUS | MebxGetIdleTimeout (OUT UINT16 *AmtIdleTimeout)
Retrieve current AMT Idle Timeout. More...
EFI_STATUS | MebxSetIdleTimeout (IN UINT16 AmtIdleTimeout)
Update current AMT Idle Timeout. More...
EFI_STATUS | MebxGetPkiFqdnSuffix (OUT FQDN_SUFFIX_ANSI_STRING *CurrentPkiDns)
Retrieve current PKI DNS Data. More...
EFI_STATUS | MebxSetCertificateHashState (IN UINT32 *Handle, IN UINT32 IsActive)
Update Certificate Hash State. More...
EFI_STATUS | MebxSetZeroTouchEnabled (IN UINT32 NewZtcStatus)
Update Zero Touch Enabled State. More...
EFI_STATUS | MebxOpenUserInitiatedConnection (OUT UINT32 *AmtStatus)
Request a User Connection for CIRA. More...
EFI_STATUS | MebxCloseUserInitiatedConnection (VOID)
Close a User Connection for CIRA. More...
EFI_STATUS | MebxGetConnectionStatus (OUT REMOTE_ACCESS_CONNECTION_STRUCT *ConnectionData)
Query the status of CIRA Connection. More...
EFI_STATUS | MebxSetMebxPwdPolicy (IN UINT32 PwdPolicy)
Update current MEBx password change policy. More...
EFI_STATUS | MebxGetMebxPwdPolicy (OUT UINT32 *PwdPolicy)
Retrieve current MEBx password change policy. More...
EFI_STATUS | MebxGetConfigServerData (OUT UINT16 *ServerPort, OUT UINT8 *ServerAddr, OUT FQDN_ANSI_STRING *Fqdn)
Retrieve current AMT Config Server data. More...
EFI_STATUS | MebxSetConfigServerData (IN UINT16 ServerPort, IN UINT8 *ServerAddr, IN FQDN_ANSI_STRING *Fqdn)
This message is sent by the BIOS to update current AMT Config Server data. More...
EFI_STATUS | MebxGetMeSetupAuditRecord (OUT ME_ADMIN_AUDIT_RECORD *Audit)
Retrieve current AMT FW Audit Record which Holds Info about Last Provisioning Attempt. More...
EFI_STATUS | MebxCfgGetIPv6LanIntStatus (IN UINT32 ConnectionType, OUT IPV6_LAN_INTERACE_STRUC *Ipv6LanIntfStrc)
This message is sent by the BIOS to retrieve current AMT IPV6 LAN Settings. More...
EFI_STATUS | MebxGetFqdn (OUT FQDN_DATA *FqdnData)
Retrieve current FQDN Data. More...
EFI_STATUS | MebxSetFqdn (IN FQDN_DATA *FqdnData)
Update current FQDN Data. More...
EFI_STATUS | MebxGetRedirectionState (OUT REDIRECTION_FEATURES_STATE *FeaturesState)
Retrieve current Redirection features state. More...
EFI_STATUS | MebxCompleteConfigurationRequest (OUT UINT32 *AmtStatus)
Complete configuration and transition to the post provisioning state. More...
EFI_STATUS | MebxStopRemoteConfiguration (OUT UINT32 *ProvisioningState)
Stop the remote configuration process. More...
EFI_STATUS | MebxActivateRemoteConfiguration (OUT UINT32 *ProvisioningState)
Start the remote configuration process. More...
EFI_STATUS | MebxSetMebxState (IN AMT_MEBX_STATE MebxState)
Set MEBx state and verify if KVM session is not active during MEBx UI. More...
EFI_STATUS | MebxGetPlatformOptInPolicy (OUT UINT32 *OptInConfigExposure, OUT UINT32 *RemoteItOptInConfigExposure, OUT UINT32 *UserOptIn, OUT UINT32 *RemoteItOptInConfig)
This function retrieves platform settings regarding Opt-in policies. More...
EFI_STATUS | MebxSetOptInState (IN UINT32 OptInState, IN UINT32 RemoteOptInState)
This message is sent by the BIOS to update current state of User Consent for AMT Features: KVM / USB-R and Boot Parameters. More...
EFI_STATUS | MebxSetKvmEnabled (IN UINT32 KvmState)
Update current state of KVM Feature. More...
EFI_STATUS | MebxGetKvmEnabled (OUT UINT8 *KvmState)
Retrieve current state of KVM Feature. More...
EFI_STATUS | MebxGetAmtPrivacyLevel (OUT UINT8 *PrivacyLevel)
This message is sent by the BIOS to retrieve current AMT Privacy Level. More...
EFI_STATUS | MebxGetPowerControlSettings (OUT UINT8 *NumberOfPowerPkgs, OUT UINT8 *CurrentMeOnHostSlpState, OUT IMB_ANSI_STRING *PackageDescription)
Retrieve ME Power Policy configuration. More...
EFI_STATUS | MebxUpdatePowerPolicy (IN UINT8 MeOnHostSlpStates)
Update ME Power Policy. More...
EFI_STATUS | MebxSetAmtState (IN UINT8 AmtState)
Update Amt State. More...

Detailed Description

Header file for MEBx Wrapper Library.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeMebxWrapperLib.h.

Function Documentation

◆ MebxActivateRemoteConfiguration()

EFI_STATUS MebxActivateRemoteConfiguration ( OUT UINT32 * ProvisioningState )

Start the remote configuration process.

Parameters
[out] AmtStatus Amt Error Status
Return values
EFI_SUCCESS | Remote Configuration Activated
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_NOT_READY | Certificate not ready yet

◆ MebxCfgGetIPv6LanIntStatus()

EFI_STATUS MebxCfgGetIPv6LanIntStatus | ( | IN UINT32 | ConnectionType,
 |  | OUT IPV6_LAN_INTERACE_STRUC * | Ipv6LanIntfStrc
 | ) |  |

This message is sent by the BIOS to retrieve current AMT IPV6 LAN Settings.

Parameters
[in] | ConnectionType | Interface type: 0 - WIRED 1 - WIRELESS
[out] | Ipv6LanIntfStrc | Current LAN Settings Structure
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge or too many IPV6 addresses

◆ MebxCloseUserInitiatedConnection()

EFI_STATUS MebxCloseUserInitiatedConnection ( VOID )

Close a User Connection for CIRA.

Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxCompleteConfigurationRequest()

EFI_STATUS MebxCompleteConfigurationRequest ( OUT UINT32 * AmtStatus )

Complete configuration and transition to the post provisioning state.

Parameters
[out] AmtStatus Amt Error Status
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetAmtPrivacyLevel()

EFI_STATUS MebxGetAmtPrivacyLevel ( OUT UINT8 * PrivacyLevel )

This message is sent by the BIOS to retrieve current AMT Privacy Level.

Parameters
[out] PrivacyLevel Current Privacy Level 1 - Default 2 - Enhanced 3 - Extreme
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetConfigServerData()

EFI_STATUS MebxGetConfigServerData | ( | OUT UINT16 * | ServerPort,
 |  | OUT UINT8 * | ServerAddr,
 |  | OUT FQDN_ANSI_STRING * | Fqdn
 | ) |  |

Retrieve current AMT Config Server data.

Parameters
[out] | ServerPort | Current Configuration Server Port
[out] | ServerAddr | Current Configuration Server Address
[out] | Fqdn | Current Fqdn Value
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetConnectionStatus()

EFI_STATUS MebxGetConnectionStatus ( OUT REMOTE_ACCESS_CONNECTION_STRUCT * ConnectionData )

Query the status of CIRA Connection.

Parameters
[out] ConnectionData Connection Data
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge or Fqdn too long

◆ MebxGetEndOfPostState()

EFI_STATUS MebxGetEndOfPostState ( OUT CFG_EOP_STATE * State )

Retrieve current EoP state.

Parameters
[out] State Current End of Post State:
See also
CFG_EOP_STATE
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetFqdn()

EFI_STATUS MebxGetFqdn ( OUT FQDN_DATA * FqdnData )

Retrieve current FQDN Data.

Parameters
[out] FqdnData Current FQDN data
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetHashedCertificates()

EFI_STATUS MebxGetHashedCertificates | ( | OUT UINT32 * | CertQuantity,
 |  | OUT UINT32 * | CertHandle,
 |  | OUT CERT_HASH_ENTRY * | CertHashEntry
 | ) |  |

Retrieve available Hashed Certificates.

Parameters
[out] | CertQuantity | Number of available Hashed Certificates entries
[out] | CertHandle | Array with available Hashed Certificates list
[out] | CertHashEntry | Pointer to the structure containing info regarding all the available Hashed Certificates
See also
CERT_HASH_ENTRY
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetIdleTimeout()

EFI_STATUS MebxGetIdleTimeout ( OUT UINT16 * AmtIdleTimeout )

Retrieve current AMT Idle Timeout.

Parameters
[out] AmtIdleTimeout Current AMT Idle Timeout
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetIpv4Params()

EFI_STATUS MebxGetIpv4Params | ( | IN UINT32 | Interface,
 |  | IN BOOLEAN | GetDynamicIpAddress,
 |  | OUT UINT8 * | IsLanlessPlatform,
 |  | OUT IMB_TCPIP_PARAMS * | Ipv4Cfg
 | ) |  |

Retrieve current IPV4 TCPIP Parameters.

Parameters
[in] | Interface | Interface type: 0 - WIRED 1 - WIRELESS
[in] | GetDynamicIpAddress | If TRUE, then the function will return IPV4 Address obtained from DHCP if DHCP is enabled
[out] | IsLanlessPlatform | Indicates if Interface LAN is available
[out] | Ipv4Cfg | IPV4 TCPIP Parameters. Returned only if Interface LAN Interface is available
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetKvmEnabled()

EFI_STATUS MebxGetKvmEnabled ( OUT UINT8 * KvmState )

Retrieve current state of KVM Feature.

Parameters
[out] KvmState Current KVM State
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetMebxPwdPolicy()

EFI_STATUS MebxGetMebxPwdPolicy ( OUT UINT32 * PwdPolicy )

Retrieve current MEBx password change policy.

Parameters
[out] PwdPolicy Current MEBx password change policy:
See also
CFG_MEBX_PWD_CHANGE_POLICY
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetMeSetupAuditRecord()

EFI_STATUS MebxGetMeSetupAuditRecord ( OUT ME_ADMIN_AUDIT_RECORD * Audit )

Retrieve current AMT FW Audit Record which Holds Info about Last Provisioning Attempt.

Parameters
[out] Audit AMT's Current Audit Record
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetPkiFqdnSuffix()

EFI_STATUS MebxGetPkiFqdnSuffix ( OUT FQDN_SUFFIX_ANSI_STRING * CurrentPkiDns )

Retrieve current PKI DNS Data.

Parameters
[out] CurrentPkiDns Current PKI DNS Data
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetPlatformOptInPolicy()

EFI_STATUS MebxGetPlatformOptInPolicy | ( | OUT UINT32 * | OptInConfigExposure,
 |  | OUT UINT32 * | RemoteItOptInConfigExposure,
 |  | OUT UINT32 * | UserOptIn,
 |  | OUT UINT32 * | RemoteItOptInConfig
 | ) |  |

This function retrieves platform settings regarding Opt-in policies.

Parameters
[out] | OptInConfigExposure | Determines if user should be able to change User Opt-In configuration
[out] | RemoteItOptInConfigExpoure | Determines if user should be able to change Remote IT Opt-In configuration
[out] | UserOptIn | Determines list of features that require User Consent
[out] | RemoteItOptInConfig | Determines whether user consent policy can be modified from remote
Return values
EFI_SUCCESS | Function succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetPowerControlSettings()

EFI_STATUS MebxGetPowerControlSettings | ( | OUT UINT8 * | NumberOfPowerPkgs,
 |  | OUT UINT8 * | CurrentMeOnHostSlpState,
 |  | OUT IMB_ANSI_STRING * | PackageDescription
 | ) |  |

Retrieve ME Power Policy configuration.

This function retrieves the maximum number of available power packages for the given platform. Power packages are described by a list of GUIDs and each GUID has it's own text description.

Parameters
[out] | NumberOfPowerPkgs | Number of available power packages GUIDs
[out] | CurrentMeOnHostSlpState | Index of the currently used power package GUID
[out] | PackageDescription | Array with the text decriptions for available GUIDs
Return values
EFI_SUCCESS | Function succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetProvisioningState()

EFI_STATUS MebxGetProvisioningState ( OUT UINT32 * ProvisioningState )

Retrieve current provisioning state.

Parameters
[out] ProvisioningState Current provisioning state:
See also
PT_PROVISIONING_STATE
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetRedirectionState()

EFI_STATUS MebxGetRedirectionState ( OUT REDIRECTION_FEATURES_STATE * FeaturesState )

Retrieve current Redirection features state.

Parameters
[out] FeaturesState Current Redirection features state
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxGetZtcEnabledStatus()

EFI_STATUS MebxGetZtcEnabledStatus ( OUT UINT32 * ZtcEnabledStatus )

Retrieve ZTC State.

Parameters
[out] ZtcEnabledStatus Current ZTC Enabled Status
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxIsAmthiInterfaceVersionSupported()

BOOLEAN MebxIsAmthiInterfaceVersionSupported ( VOID )

Check if BIOS supports the currently used AMTHI Interface version.

Return values
TRUE | AMTHI Interface version supported
FALSE | AMTHI Interface version not supported

◆ MebxOpenUserInitiatedConnection()

EFI_STATUS MebxOpenUserInitiatedConnection ( OUT UINT32 * AmtStatus )

Request a User Connection for CIRA.

Parameters
[out] AmtStatus Amt Error Status
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxPerformUnprovisioning()

EFI_STATUS MebxPerformUnprovisioning ( IN UINT8 UnprovisionType )

Performs Intel(R) AMT full and partial unprovisioning flows.

Performs unprovisiong, re-initializes AMTHI, and if full unprovision, resets the MEBx password to AMT.

Parameters
[in] UnprovisionType Specifies Unprovisioning Type: 0 - partial unprovision 1 - full unprovision
Return values
EFI_SUCCESS | Unprovisioning successful
EFI_TIMEOUT | Timeout has occured
Others | Other error has occured

◆ MebxSetAmtState()

EFI_STATUS MebxSetAmtState ( IN UINT8 AmtState )

Update Amt State.

Parameters
[in] AmtState New AMT State
Return values
EFI_SUCCESS | Function succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetCertificateHashState()

EFI_STATUS MebxSetCertificateHashState | ( | IN UINT32 * | Handle,
 |  | IN UINT32 | IsActive
 | ) |  |

Update Certificate Hash State.

Parameters
[in] | Handle | Handle to Hash to Update State for
[in] | IsActive | New User Defined State for Certificate Hash State (Active/Not Active)
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetConfigServerData()

EFI_STATUS MebxSetConfigServerData | ( | IN UINT16 | ServerPort,
 |  | IN UINT8 * | ServerAddr,
 |  | IN FQDN_ANSI_STRING * | Fqdn
 | ) |  |

This message is sent by the BIOS to update current AMT Config Server data.

Parameters
[in] | ServerPort | New Configuration Server Port Value
[in] | ServerAddr | New Configuration Server Address
[in] | Fqdn | New Fqdn Value
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetFqdn()

EFI_STATUS MebxSetFqdn ( IN FQDN_DATA * FqdnData )

Update current FQDN Data.

Parameters
[in] FqdnData New FQDN data
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetIdleTimeout()

EFI_STATUS MebxSetIdleTimeout ( IN UINT16 AmtIdleTimeout )

Update current AMT Idle Timeout.

Parameters
[in] AmtIdleTimeout New AMT Idle Timeout
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetIpv4Params()

EFI_STATUS MebxSetIpv4Params ( IN IMB_TCPIP_PARAMS * NewIpv4Cfg )

Update current IPV4 TCPIP Parameters.

Parameters
[in] NewIpv4Cfg IPV4 TCPIP Parameters
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetKvmEnabled()

EFI_STATUS MebxSetKvmEnabled ( IN UINT32 KvmState )

Update current state of KVM Feature.

Parameters
[in] KvmState New KVM State
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetMebxPwdPolicy()

EFI_STATUS MebxSetMebxPwdPolicy ( IN UINT32 PwdPolicy )

Update current MEBx password change policy.

Parameters
[in] PwdPolicy New MEBx password change policy:
See also
CFG_MEBX_PWD_CHANGE_POLICY
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetMebxState()

EFI_STATUS MebxSetMebxState ( IN AMT_MEBX_STATE MebxState )

Set MEBx state and verify if KVM session is not active during MEBx UI.

Parameters
[in] MebxState New MEBx state
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetOptInState()

EFI_STATUS MebxSetOptInState | ( | IN UINT32 | OptInState,
 |  | IN UINT32 | RemoteOptInState
 | ) |  |

This message is sent by the BIOS to update current state of User Consent for AMT Features: KVM / USB-R and Boot Parameters.

Parameters
[in] | OptInState | Current OptInState 0 - None 1 - KVM 0xFFFFFFFF - All
[in] | RemoteOptInState | Enable / Disable Remote OptIn: 0 - Enabled 1 - Disabled
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetPkiFqdnSuffix()

EFI_STATUS MebxSetPkiFqdnSuffix ( IN FQDN_SUFFIX_ANSI_STRING * NewPkiDns )

Update current PKI FQDN DNS Suffix.

Attention
Fuction is not allowed in POST_PROVISION State
Parameters
[in] NewPkiDns New Fqdn Pki Dns suffix
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetSolStorageRedir()

EFI_STATUS MebxSetSolStorageRedir | ( | IN UINT16 | NewSolStatus,
 |  | IN UINT16 | NewStorageRedirStatus
 | ) |  |

Update current SOL and Storage Redirection state.

Parameters
[in] | NewSolStatus | New SOL state
[in] | NewStorageRedirStatus | New Storage Redirection state
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxSetZeroTouchEnabled()

EFI_STATUS MebxSetZeroTouchEnabled ( IN UINT32 NewZtcStatus )

Update Zero Touch Enabled State.

Parameters
[in] NewZtcStatus New ZTC Enabled Status
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxStopRemoteConfiguration()

EFI_STATUS MebxStopRemoteConfiguration ( OUT UINT32 * ProvisioningState )

Stop the remote configuration process.

Parameters
[out] ProvisioningState Platform provisioning state
Return values
EFI_SUCCESS | Remote Configuration stopped
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ MebxUpdatePowerPolicy()

EFI_STATUS MebxUpdatePowerPolicy ( IN UINT8 MeOnHostSlpStates )

Update ME Power Policy.

Parameters
[in] MeOnHostSlpStates Index of the GUID previously retrieved by XXX function to be set
Return values
EFI_SUCCESS | Function succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMebxWrapperLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeMebxWrapperLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for MEBx Wrapper Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_MEBX_WRAPPER_LIB_H_
36 #define _DXE_MEBX_WRAPPER_LIB_H_
37
38 #include <AmthiMsgs.h>
39 #include <Protocol/GraphicsOutput.h>
40
41 /**
42 Check if BIOS supports the currently used AMTHI Interface version.
43
44 @retval TRUE AMTHI Interface version supported
45 @retval FALSE AMTHI Interface version not supported
46 **/
47 BOOLEAN
48 MebxIsAmthiInterfaceVersionSupported (
49 VOID
50 );
51
52 /**
53 Retrieve current IPV4 TCPIP Parameters.
54
55 @param[in] Interface Interface type:
56 0 - WIRED
57 1 - WIRELESS
58 @param[in] GetDynamicIpAddress If TRUE, then the function will return
59 IPV4 Address obtained from DHCP if DHCP
60 is enabled
61 @param[out] IsLanlessPlatform Indicates if Interface LAN is available
62 @param[out] Ipv4Cfg IPV4 TCPIP Parameters. Returned only
63 if Interface LAN Interface is available
64
65 @retval EFI_SUCCESS Command succeeded
66 @retval EFI_INVALID_PARAMETER NULL parameter
67 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
68 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
69 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
70 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
71 **/
72 EFI_STATUS
73 MebxGetIpv4Params (
74 IN UINT32 Interface,
75 IN BOOLEAN GetDynamicIpAddress,
76 OUT UINT8 *IsLanlessPlatform,
77 OUT IMB_TCPIP_PARAMS *Ipv4Cfg
78 );
79
80 /**
81 Update current IPV4 TCPIP Parameters.
82
83 @param[in] NewIpv4Cfg IPV4 TCPIP Parameters
84
85 @retval EFI_SUCCESS Command succeeded
86 @retval EFI_INVALID_PARAMETER NULL parameter
87 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
88 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
89 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
90 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
91 **/
92 EFI_STATUS
93 MebxSetIpv4Params (
94 IN IMB_TCPIP_PARAMS *NewIpv4Cfg
95 );
96
97 typedef enum {
98 UnprovisionTypePartial,
99 UnprovisionTypeFull
100 } UNPROVISION_TYPE;
101
102 /**
103 Performs Intel(R) AMT full and partial unprovisioning flows.
104 Performs unprovisiong, re-initializes AMTHI, and if full unprovision, resets the
105 MEBx password to AMT.
106
107 @param[in] UnprovisionType Specifies Unprovisioning Type:
108 0 - partial unprovision
109 1 - full unprovision
110
111 @retval EFI_SUCCESS Unprovisioning successful
112 @retval EFI_TIMEOUT Timeout has occured
113 @retval Others Other error has occured
114 **/
115 EFI_STATUS
116 MebxPerformUnprovisioning (
117 IN UINT8 UnprovisionType
118 );
119
120 /**
121 Retrieve current provisioning state.
122
123 @param[out] ProvisioningState Current provisioning state:
124 @see PT_PROVISIONING_STATE
125
126 @retval EFI_SUCCESS Command succeeded
127 @retval EFI_INVALID_PARAMETER NULL parameter
128 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
129 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
130 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
131 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
132 **/
133 EFI_STATUS
134 MebxGetProvisioningState (
135 OUT UINT32 *ProvisioningState
136 );
137
138 /**
139 Update current SOL and Storage Redirection state.
140
141 @param[in] NewSolStatus New SOL state
142 @param[in] NewStorageRedirStatus New Storage Redirection state
143
144 @retval EFI_SUCCESS Command succeeded
145 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
146 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
147 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
148 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
149 **/
150 EFI_STATUS
151 MebxSetSolStorageRedir (
152 IN UINT16 NewSolStatus,
153 IN UINT16 NewStorageRedirStatus
154 );
155
156 /**
157 Retrieve current EoP state.
158
159 @param[out] State Current End of Post State:
160 @see CFG_EOP_STATE
161
162 @retval EFI_SUCCESS Command succeeded
163 @retval EFI_INVALID_PARAMETER NULL parameter
164 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
165 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
166 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
167 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
168 **/
169 EFI_STATUS
170 MebxGetEndOfPostState (
171 OUT CFG_EOP_STATE *State
172 );
173
174 /**
175 Retrieve available Hashed Certificates.
176
177 @param[out] CertQuantity Number of available Hashed Certificates entries
178 @param[out] CertHandle Array with available Hashed Certificates list
179 @param[out] CertHashEntry Pointer to the structure containing info regarding
180 all the available Hashed Certificates
181 @see CERT_HASH_ENTRY
182
183 @retval EFI_SUCCESS Command succeeded
184 @retval EFI_INVALID_PARAMETER NULL parameter
185 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
186 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
187 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
188 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
189 **/
190 EFI_STATUS
191 MebxGetHashedCertificates (
192 OUT UINT32 *CertQuantity,
193 OUT UINT32 *CertHandle,
194 OUT CERT_HASH_ENTRY *CertHashEntry
195 );
196
197 /**
198 Update current PKI FQDN DNS Suffix.
199
200 @attention Fuction is not allowed in POST_PROVISION State
201
202 @param[in] NewPkiDns New Fqdn Pki Dns suffix
203
204 @retval EFI_SUCCESS Command succeeded
205 @retval EFI_INVALID_PARAMETER NULL parameter
206 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
207 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
208 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
209 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
210 **/
211 EFI_STATUS
212 MebxSetPkiFqdnSuffix (
213 IN FQDN_SUFFIX_ANSI_STRING *NewPkiDns
214 );
215
216 /**
217 Retrieve ZTC State.
218
219 @param[out] ZtcEnabledStatus Current ZTC Enabled Status
220
221 @retval EFI_SUCCESS Command succeeded
222 @retval EFI_INVALID_PARAMETER NULL parameter
223 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
224 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
225 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
226 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
227 **/
228 EFI_STATUS
229 MebxGetZtcEnabledStatus (
230 OUT UINT32 *ZtcEnabledStatus
231 );
232
233 /**
234 Retrieve current AMT Idle Timeout.
235
236 @param[out] AmtIdleTimeout Current AMT Idle Timeout
237
238 @retval EFI_SUCCESS Command succeeded
239 @retval EFI_INVALID_PARAMETER NULL parameter
240 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
241 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
242 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
243 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
244 **/
245 EFI_STATUS
246 MebxGetIdleTimeout (
247 OUT UINT16 *AmtIdleTimeout
248 );
249
250 /**
251 Update current AMT Idle Timeout.
252
253 @param[in] AmtIdleTimeout New AMT Idle Timeout
254
255 @retval EFI_SUCCESS Command succeeded
256 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
257 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
258 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
259 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
260 **/
261 EFI_STATUS
262 MebxSetIdleTimeout (
263 IN UINT16 AmtIdleTimeout
264 );
265
266 /**
267 Retrieve current PKI DNS Data.
268
269 @param[out] CurrentPkiDns Current PKI DNS Data
270
271 @retval EFI_SUCCESS Command succeeded
272 @retval EFI_INVALID_PARAMETER NULL parameter
273 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
274 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
275 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
276 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
277 **/
278 EFI_STATUS
279 MebxGetPkiFqdnSuffix (
280 OUT FQDN_SUFFIX_ANSI_STRING *CurrentPkiDns
281 );
282
283 /**
284 Update Certificate Hash State.
285
286 @param[in] Handle Handle to Hash to Update State for
287 @param[in] IsActive New User Defined State for Certificate Hash State
288 (Active/Not Active)
289
290 @retval EFI_SUCCESS Command succeeded
291 @retval EFI_INVALID_PARAMETER NULL parameter
292 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
293 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
294 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
295 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
296 **/
297 EFI_STATUS
298 MebxSetCertificateHashState (
299 IN UINT32 *Handle,
300 IN UINT32 IsActive
301 );
302
303 /**
304 Update Zero Touch Enabled State.
305
306 @param[in] NewZtcStatus New ZTC Enabled Status
307
308 @retval EFI_SUCCESS Command succeeded
309 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
310 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
311 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
312 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
313 **/
314 EFI_STATUS
315 MebxSetZeroTouchEnabled (
316 IN UINT32 NewZtcStatus
317 );
318
319 /**
320 Request a User Connection for CIRA.
321
322 @param[out] AmtStatus Amt Error Status
323
324 @retval EFI_SUCCESS Command succeeded
325 @retval EFI_INVALID_PARAMETER NULL parameter
326 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
327 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
328 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
329 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
330 **/
331 EFI_STATUS
332 MebxOpenUserInitiatedConnection (
333 OUT UINT32 *AmtStatus
334 );
335
336 /**
337 Close a User Connection for CIRA.
338
339 @retval EFI_SUCCESS Command succeeded
340 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
341 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
342 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
343 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
344 **/
345 EFI_STATUS
346 MebxCloseUserInitiatedConnection (
347 VOID
348 );
349
350 /**
351 Query the status of CIRA Connection.
352
353 @param[out] ConnectionData Connection Data
354
355 @retval EFI_SUCCESS Command succeeded
356 @retval EFI_INVALID_PARAMETER NULL parameter
357 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
358 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
359 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
360 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge or Fqdn too long
361 **/
362 EFI_STATUS
363 MebxGetConnectionStatus (
364 OUT REMOTE_ACCESS_CONNECTION_STRUCT *ConnectionData
365 );
366
367 /**
368 Update current MEBx password change policy.
369
370 @param[in] PwdPolicy New MEBx password change policy:
371 @see CFG_MEBX_PWD_CHANGE_POLICY
372
373 @retval EFI_SUCCESS Command succeeded
374 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
375 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
376 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
377 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
378 **/
379 EFI_STATUS
380 MebxSetMebxPwdPolicy (
381 IN UINT32 PwdPolicy
382 );
383
384 /**
385 Retrieve current MEBx password change policy.
386
387 @param[out] PwdPolicy Current MEBx password change policy:
388 @see CFG_MEBX_PWD_CHANGE_POLICY
389
390 @retval EFI_SUCCESS Command succeeded
391 @retval EFI_INVALID_PARAMETER NULL parameter
392 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
393 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
394 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
395 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
396 **/
397 EFI_STATUS
398 MebxGetMebxPwdPolicy (
399 OUT UINT32 *PwdPolicy
400 );
401
402 /**
403 Retrieve current AMT Config Server data.
404
405 @param[out] ServerPort Current Configuration Server Port
406 @param[out] ServerAddr Current Configuration Server Address
407 @param[out] Fqdn Current Fqdn Value
408
409 @retval EFI_SUCCESS Command succeeded
410 @retval EFI_INVALID_PARAMETER NULL parameter
411 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
412 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
413 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
414 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
415 **/
416 EFI_STATUS
417 MebxGetConfigServerData (
418 OUT UINT16 *ServerPort,
419 OUT UINT8 *ServerAddr,
420 OUT FQDN_ANSI_STRING *Fqdn
421 );
422
423 /**
424 This message is sent by the BIOS to update current AMT Config Server data.
425
426 @param[in] ServerPort New Configuration Server Port Value
427 @param[in] ServerAddr New Configuration Server Address
428 @param[in] Fqdn New Fqdn Value
429
430 @retval EFI_SUCCESS Command succeeded
431 @retval EFI_INVALID_PARAMETER NULL parameter
432 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
433 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
434 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
435 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
436 **/
437 EFI_STATUS
438 MebxSetConfigServerData (
439 IN UINT16 ServerPort,
440 IN UINT8 *ServerAddr,
441 IN FQDN_ANSI_STRING *Fqdn
442 );
443
444 /**
445 Retrieve current AMT FW Audit Record which Holds Info about Last Provisioning Attempt.
446
447 @param[out] Audit AMT's Current Audit Record
448
449 @retval EFI_SUCCESS Command succeeded
450 @retval EFI_INVALID_PARAMETER NULL parameter
451 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
452 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
453 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
454 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
455 **/
456 EFI_STATUS
457 MebxGetMeSetupAuditRecord (
458 OUT ME_ADMIN_AUDIT_RECORD *Audit
459 );
460
461 /**
462 This message is sent by the BIOS to retrieve current AMT IPV6 LAN Settings.
463
464 @param[in] ConnectionType Interface type:
465 0 - WIRED
466 1 - WIRELESS
467 @param[out] Ipv6LanIntfStrc Current LAN Settings Structure
468
469 @retval EFI_SUCCESS Command succeeded
470 @retval EFI_INVALID_PARAMETER NULL parameter
471 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
472 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
473 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
474 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
475 or too many IPV6 addresses
476 **/
477 EFI_STATUS
478 MebxCfgGetIPv6LanIntStatus (
479 IN UINT32 ConnectionType,
480 OUT IPV6_LAN_INTERACE_STRUC *Ipv6LanIntfStrc
481 );
482
483 /**
484 Retrieve current FQDN Data.
485
486 @param[out] FqdnData Current FQDN data
487
488 @retval EFI_SUCCESS Command succeeded
489 @retval EFI_INVALID_PARAMETER NULL parameter
490 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
491 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
492 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
493 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
494 **/
495 EFI_STATUS
496 MebxGetFqdn (
497 OUT FQDN_DATA *FqdnData
498 );
499
500 /**
501 Update current FQDN Data.
502
503 @param[in] FqdnData New FQDN data
504
505 @retval EFI_SUCCESS Command succeeded
506 @retval EFI_INVALID_PARAMETER NULL parameter
507 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
508 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
509 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
510 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
511 **/
512 EFI_STATUS
513 MebxSetFqdn (
514 IN FQDN_DATA *FqdnData
515 );
516
517 /**
518 Retrieve current Redirection features state.
519
520 @param[out] FeaturesState Current Redirection features state
521
522 @retval EFI_SUCCESS Command succeeded
523 @retval EFI_INVALID_PARAMETER NULL parameter
524 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
525 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
526 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
527 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
528 **/
529
530 EFI_STATUS
531 MebxGetRedirectionState (
532 OUT REDIRECTION_FEATURES_STATE *FeaturesState
533 );
534
535 /**
536 Complete configuration and transition to the post provisioning state.
537
538 @param[out] AmtStatus Amt Error Status
539
540 @retval EFI_SUCCESS Command succeeded
541 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
542 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
543 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
544 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
545 **/
546 EFI_STATUS
547 MebxCompleteConfigurationRequest (
548 OUT UINT32 *AmtStatus
549 );
550
551 /**
552 Stop the remote configuration process.
553
554 @param[out] ProvisioningState Platform provisioning state
555
556 @retval EFI_SUCCESS Remote Configuration stopped
557 @retval EFI_INVALID_PARAMETER NULL parameter
558 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
559 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
560 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
561 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
562 **/
563 EFI_STATUS
564 MebxStopRemoteConfiguration (
565 OUT UINT32 *ProvisioningState
566 );
567
568 /**
569 Start the remote configuration process.
570
571 @param[out] AmtStatus Amt Error Status
572
573 @retval EFI_SUCCESS Remote Configuration Activated
574 @retval EFI_INVALID_PARAMETER NULL parameter
575 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
576 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
577 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
578 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
579 @retval EFI_NOT_READY Certificate not ready yet
580 **/
581 EFI_STATUS
582 MebxActivateRemoteConfiguration (
583 OUT UINT32 *ProvisioningState
584 );
585
586 /**
587 Set MEBx state and verify if KVM session is not active during MEBx UI.
588
589 @param[in] MebxState New MEBx state
590
591 @retval EFI_SUCCESS Command succeeded
592 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
593 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
594 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
595 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
596 **/
597 EFI_STATUS
598 MebxSetMebxState (
599 IN AMT_MEBX_STATE MebxState
600 );
601
602 /**
603 This function retrieves platform settings regarding Opt-in policies.
604
605 @param[out] OptInConfigExposure Determines if user should be able to change
606 User Opt-In configuration
607 @param[out] RemoteItOptInConfigExpoure Determines if user should be able to change
608 Remote IT Opt-In configuration
609 @param[out] UserOptIn Determines list of features that require User Consent
610 @param[out] RemoteItOptInConfig Determines whether user consent policy can be modified from remote
611
612
613 @retval EFI_SUCCESS Function succeeded
614 @retval EFI_INVALID_PARAMETER NULL parameter
615 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
616 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
617 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
618 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
619 **/
620 EFI_STATUS
621 MebxGetPlatformOptInPolicy (
622 OUT UINT32 *OptInConfigExposure,
623 OUT UINT32 *RemoteItOptInConfigExposure,
624 OUT UINT32 *UserOptIn,
625 OUT UINT32 *RemoteItOptInConfig
626 );
627
628 /**
629 This message is sent by the BIOS to update current state of User Consent for AMT Features:
630 KVM / USB-R and Boot Parameters.
631
632 @param[in] OptInState Current OptInState
633 0 - None
634 1 - KVM
635 0xFFFFFFFF - All
636 @param[in] RemoteOptInState Enable / Disable Remote OptIn:
637 0 - Enabled
638 1 - Disabled
639
640 @retval EFI_SUCCESS Command succeeded
641 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
642 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
643 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
644 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
645 **/
646 EFI_STATUS
647 MebxSetOptInState (
648 IN UINT32 OptInState,
649 IN UINT32 RemoteOptInState
650 );
651
652 /**
653 Update current state of KVM Feature.
654
655 @param[in] KvmState New KVM State
656
657 @retval EFI_SUCCESS Command succeeded
658 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
659 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
660 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
661 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
662 **/
663 EFI_STATUS
664 MebxSetKvmEnabled (
665 IN UINT32 KvmState
666 );
667
668 /**
669 Retrieve current state of KVM Feature.
670
671 @param[out] KvmState Current KVM State
672
673 @retval EFI_SUCCESS Command succeeded
674 @retval EFI_INVALID_PARAMETER NULL parameter
675 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
676 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
677 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
678 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
679 **/
680 EFI_STATUS
681 MebxGetKvmEnabled (
682 OUT UINT8 *KvmState
683 );
684
685 /**
686 This message is sent by the BIOS to retrieve current AMT Privacy Level.
687
688 @param[out] PrivacyLevel Current Privacy Level
689 1 - Default
690 2 - Enhanced
691 3 - Extreme
692
693 @retval EFI_SUCCESS Command succeeded
694 @retval EFI_INVALID_PARAMETER NULL parameter
695 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
696 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
697 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
698 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
699 **/
700 EFI_STATUS
701 MebxGetAmtPrivacyLevel (
702 OUT UINT8 *PrivacyLevel
703 );
704
705 /**
706 Retrieve ME Power Policy configuration.
707
708 This function retrieves the maximum number of available power packages for the given platform.
709 Power packages are described by a list of GUIDs and each GUID has it's own text description.
710
711 @param[out] NumberOfPowerPkgs Number of available power packages GUIDs
712 @param[out] CurrentMeOnHostSlpState Index of the currently used power package GUID
713 @param[out] PackageDescription Array with the text decriptions for available GUIDs
714
715 @retval EFI_SUCCESS Function succeeded
716 @retval EFI_INVALID_PARAMETER NULL parameter
717 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
718 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
719 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
720 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
721 **/
722 EFI_STATUS
723 MebxGetPowerControlSettings (
724 OUT UINT8 *NumberOfPowerPkgs,
725 OUT UINT8 *CurrentMeOnHostSlpState,
726 OUT IMB_ANSI_STRING *PackageDescription
727 );
728
729 /**
730 Update ME Power Policy.
731
732 @param[in] MeOnHostSlpStates Index of the GUID previously retrieved by XXX function
733 to be set
734
735 @retval EFI_SUCCESS Function succeeded
736 @retval EFI_INVALID_PARAMETER NULL parameter
737 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
738 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
739 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
740 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
741 **/
742 EFI_STATUS
743 MebxUpdatePowerPolicy (
744 IN UINT8 MeOnHostSlpStates
745 );
746
747 typedef enum {
748 AmtDisabled,
749 AmtPartiallyDisabled,
750 AmtEnabled
751 } AMT_STATE;
752
753 /**
754 Update Amt State.
755
756 @param[in] AmtState New AMT State
757
758 @retval EFI_SUCCESS Function succeeded
759 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
760 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
761 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
762 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
763 **/
764 EFI_STATUS
765 MebxSetAmtState (
766 IN UINT8 AmtState
767 );
768
769 #endif
AmthiMsgs.h
AMTHI Messages.
MebxSetMebxPwdPolicy
EFI_STATUS MebxSetMebxPwdPolicy(IN UINT32 PwdPolicy)
Update current MEBx password change policy.
MebxSetKvmEnabled
EFI_STATUS MebxSetKvmEnabled(IN UINT32 KvmState)
Update current state of KVM Feature.
MebxCfgGetIPv6LanIntStatus
EFI_STATUS MebxCfgGetIPv6LanIntStatus(IN UINT32 ConnectionType, OUT IPV6_LAN_INTERACE_STRUC *Ipv6LanIntfStrc)
This message is sent by the BIOS to retrieve current AMT IPV6 LAN Settings.
AMT_MEBX_STATE
AMT_MEBX_STATE
Set MEBx state.
Definition: AmthiMsgs.h:950
MebxSetIdleTimeout
EFI_STATUS MebxSetIdleTimeout(IN UINT16 AmtIdleTimeout)
Update current AMT Idle Timeout.
MebxSetZeroTouchEnabled
EFI_STATUS MebxSetZeroTouchEnabled(IN UINT32 NewZtcStatus)
Update Zero Touch Enabled State.
MebxSetPkiFqdnSuffix
EFI_STATUS MebxSetPkiFqdnSuffix(IN FQDN_SUFFIX_ANSI_STRING *NewPkiDns)
Update current PKI FQDN DNS Suffix.
MebxGetPowerControlSettings
EFI_STATUS MebxGetPowerControlSettings(OUT UINT8 *NumberOfPowerPkgs, OUT UINT8 *CurrentMeOnHostSlpState, OUT IMB_ANSI_STRING *PackageDescription)
Retrieve ME Power Policy configuration.
MebxGetIpv4Params
EFI_STATUS MebxGetIpv4Params(IN UINT32 Interface, IN BOOLEAN GetDynamicIpAddress, OUT UINT8 *IsLanlessPlatform, OUT IMB_TCPIP_PARAMS *Ipv4Cfg)
Retrieve current IPV4 TCPIP Parameters.
MebxGetFqdn
EFI_STATUS MebxGetFqdn(OUT FQDN_DATA *FqdnData)
Retrieve current FQDN Data.
MebxSetMebxState
EFI_STATUS MebxSetMebxState(IN AMT_MEBX_STATE MebxState)
Set MEBx state and verify if KVM session is not active during MEBx UI.
MebxSetCertificateHashState
EFI_STATUS MebxSetCertificateHashState(IN UINT32 *Handle, IN UINT32 IsActive)
Update Certificate Hash State.
MebxSetConfigServerData
EFI_STATUS MebxSetConfigServerData(IN UINT16 ServerPort, IN UINT8 *ServerAddr, IN FQDN_ANSI_STRING *Fqdn)
This message is sent by the BIOS to update current AMT Config Server data.
MebxGetHashedCertificates
EFI_STATUS MebxGetHashedCertificates(OUT UINT32 *CertQuantity, OUT UINT32 *CertHandle, OUT CERT_HASH_ENTRY *CertHashEntry)
Retrieve available Hashed Certificates.
MebxGetMeSetupAuditRecord
EFI_STATUS MebxGetMeSetupAuditRecord(OUT ME_ADMIN_AUDIT_RECORD *Audit)
Retrieve current AMT FW Audit Record which Holds Info about Last Provisioning Attempt.
MebxGetConfigServerData
EFI_STATUS MebxGetConfigServerData(OUT UINT16 *ServerPort, OUT UINT8 *ServerAddr, OUT FQDN_ANSI_STRING *Fqdn)
Retrieve current AMT Config Server data.
MebxSetAmtState
EFI_STATUS MebxSetAmtState(IN UINT8 AmtState)
Update Amt State.
MebxGetProvisioningState
EFI_STATUS MebxGetProvisioningState(OUT UINT32 *ProvisioningState)
Retrieve current provisioning state.
MebxGetZtcEnabledStatus
EFI_STATUS MebxGetZtcEnabledStatus(OUT UINT32 *ZtcEnabledStatus)
Retrieve ZTC State.
MebxSetFqdn
EFI_STATUS MebxSetFqdn(IN FQDN_DATA *FqdnData)
Update current FQDN Data.
MebxSetOptInState
EFI_STATUS MebxSetOptInState(IN UINT32 OptInState, IN UINT32 RemoteOptInState)
This message is sent by the BIOS to update current state of User Consent for AMT Features: KVM / USB-...
MebxGetRedirectionState
EFI_STATUS MebxGetRedirectionState(OUT REDIRECTION_FEATURES_STATE *FeaturesState)
Retrieve current Redirection features state.
MebxGetPkiFqdnSuffix
EFI_STATUS MebxGetPkiFqdnSuffix(OUT FQDN_SUFFIX_ANSI_STRING *CurrentPkiDns)
Retrieve current PKI DNS Data.
MebxGetKvmEnabled
EFI_STATUS MebxGetKvmEnabled(OUT UINT8 *KvmState)
Retrieve current state of KVM Feature.
MebxIsAmthiInterfaceVersionSupported
BOOLEAN MebxIsAmthiInterfaceVersionSupported(VOID)
Check if BIOS supports the currently used AMTHI Interface version.
MebxStopRemoteConfiguration
EFI_STATUS MebxStopRemoteConfiguration(OUT UINT32 *ProvisioningState)
Stop the remote configuration process.
MebxSetIpv4Params
EFI_STATUS MebxSetIpv4Params(IN IMB_TCPIP_PARAMS *NewIpv4Cfg)
Update current IPV4 TCPIP Parameters.
MebxCompleteConfigurationRequest
EFI_STATUS MebxCompleteConfigurationRequest(OUT UINT32 *AmtStatus)
Complete configuration and transition to the post provisioning state.
MebxGetEndOfPostState
EFI_STATUS MebxGetEndOfPostState(OUT CFG_EOP_STATE *State)
Retrieve current EoP state.
MebxPerformUnprovisioning
EFI_STATUS MebxPerformUnprovisioning(IN UINT8 UnprovisionType)
Performs Intel(R) AMT full and partial unprovisioning flows.
CFG_EOP_STATE
CFG_EOP_STATE
Get Eop State.
Definition: AmthiMsgs.h:343
MebxUpdatePowerPolicy
EFI_STATUS MebxUpdatePowerPolicy(IN UINT8 MeOnHostSlpStates)
Update ME Power Policy.
MebxGetIdleTimeout
EFI_STATUS MebxGetIdleTimeout(OUT UINT16 *AmtIdleTimeout)
Retrieve current AMT Idle Timeout.
MebxGetAmtPrivacyLevel
EFI_STATUS MebxGetAmtPrivacyLevel(OUT UINT8 *PrivacyLevel)
This message is sent by the BIOS to retrieve current AMT Privacy Level.
MebxSetSolStorageRedir
EFI_STATUS MebxSetSolStorageRedir(IN UINT16 NewSolStatus, IN UINT16 NewStorageRedirStatus)
Update current SOL and Storage Redirection state.
MebxActivateRemoteConfiguration
EFI_STATUS MebxActivateRemoteConfiguration(OUT UINT32 *ProvisioningState)
Start the remote configuration process.
MebxGetMebxPwdPolicy
EFI_STATUS MebxGetMebxPwdPolicy(OUT UINT32 *PwdPolicy)
Retrieve current MEBx password change policy.
MebxGetPlatformOptInPolicy
EFI_STATUS MebxGetPlatformOptInPolicy(OUT UINT32 *OptInConfigExposure, OUT UINT32 *RemoteItOptInConfigExposure, OUT UINT32 *UserOptIn, OUT UINT32 *RemoteItOptInConfig)
This function retrieves platform settings regarding Opt-in policies.
MebxOpenUserInitiatedConnection
EFI_STATUS MebxOpenUserInitiatedConnection(OUT UINT32 *AmtStatus)
Request a User Connection for CIRA.
MebxGetConnectionStatus
EFI_STATUS MebxGetConnectionStatus(OUT REMOTE_ACCESS_CONNECTION_STRUCT *ConnectionData)
Query the status of CIRA Connection.
MebxCloseUserInitiatedConnection
EFI_STATUS MebxCloseUserInitiatedConnection(VOID)
Close a User Connection for CIRA.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Classes | Enumerations | Functions
DxeMeLib.h File Reference

Header file for functions to get Intel ME information. More...

#include <Protocol/HeciProtocol.h>
#include <Protocol/PlatformMeHook.h>
#include <Protocol/MePolicy.h>
#include <CoreBiosMsg.h>
#include <BupMsgs.h>
#include <IshMsgs.h>
#include <MeiBusMsg.h>
#include <MkhiMsgs.h>
#include <IccMsgs.h>
#include <UpidMsgs.h>
#include <PsrMsgs.h>
Include dependency graph for DxeMeLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | HWA_MESSAGE_HEADER
Definitions for Hardware Asset Header. More...
struct | HWA_PUSH_TABLES_MSG
Asset Update Table Message. More...

Enumerations

enum HWA_TABLE_TYPE_INDEX
Hardware Asset Table Index.

Functions

EFI_STATUS | HbmHostVersion (IN HECI_DEVICE HeciDev)
Checks if CSME supports HBM protocol version 2.2. More...
EFI_STATUS | HbmHostStop (IN HECI_DEVICE HeciDev)
Instructs CSME to stop all communication on given Heci device. More...
EFI_STATUS | HbmHostEnumRequest (IN HECI_DEVICE HeciDevice, OUT UINT8 *ValidAddresses)
Checks at which CSME addresses there are any clients. More...
EFI_STATUS | HbmGetClientProperties (IN HECI_DEVICE HeciDevice, IN UINT8 ClientAddr, OUT EFI_GUID *ProtocolGuid)
Retrieves GUID of a single CSME client. More...
EFI_STATUS | HbmHostClientConnect (IN HECI_DEVICE HeciDev, IN UINT8 MeAddress, IN UINT8 HostAddress)
Creates a connection between given host and CSME addresses. More...
EFI_STATUS | HbmClientDisconnect (IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Disconnects an established connection between a Host and CSME clients. More...
EFI_STATUS | HbmSendFlowControlToken (IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Sends a flow control token from BIOS to CSME that allows CSME to send one message over connection identified by host:Me address pair. More...
EFI_STATUS | HbmGetFlowControlToken (IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Attempts to receive a flow control token from CSME. More...
EFI_STATUS | HbmCapabilitiesRequest (IN HECI_DEVICE HeciDev, IN OUT HBM_CAPS_DATA *HbmCaps)
Informs about Host and CSME capabilities over HBM. More...
EFI_STATUS | HbmMapRequest (IN HECI_DEVICE HeciDev, IN UINT8 ClientDmaBufferId, IN UINT32 AddressLow, IN UINT32 AddressHigh, IN UINT32 Size)
Requests mapping CSME HECI client MMIO to the given physcial memory addresses. More...
EFI_STATUS | HbmUnmapRequest (IN HECI_DEVICE HeciDev, IN UINT8 ClientDmaBufferId)
Requests unmapping CSME HECI client MMIO from the given physcial memory addresses. More...
EFI_STATUS | HeciPdtUnlockMsg (IN CONST CHAR8 *FileName)
This message is sent by the BIOS when it wants to send PDT Unlock Message to ISH. More...
EFI_STATUS | HeciPdtUpdateMsg (IN CONST CHAR8 *FileName, IN UINT8 *PdtFileBuffer, IN UINT16 PdtBufferSize)
This message is sent by the BIOS when it wants to send PDT Update Message. More...
EFI_STATUS | HeciGetPsrRecord (IN OUT PSR_DATA *PsrData)
Get Platform Service Record from CSME. More...
EFI_STATUS | HeciSendChassisIntrDetEvent (VOID)
Inform CSME of Chassis Intrusion Detected Event. More...
EFI_STATUS | HeciSendCbmResetRequest (IN UINT8 ResetOrigin, IN UINT8 ResetType)
Send Core BIOS Reset Request Message through HECI to reset the system. More...
EFI_STATUS | HeciGetInvocationCode (OUT UINT32 *InvocationCode)
Retrieve invocation codes from Firmware. More...
EFI_STATUS | HeciSetInvocationCode (IN UINT32 InvocationCode)
Set invocation codes in Firmware. More...
EFI_STATUS | HeciClearInvocationCode (IN UINT32 InvocationCode)
Clear invocation codes in Firmware. More...
ME_PWD_STATUS | HeciModifyMebxPassword (IN UINT8 OldPwdSize, IN UINT8 *OldPwd, IN UINT8 NewPwdSize, IN UINT8 *NewPwd)
This function logs in with current password and updates to new password. More...
EFI_STATUS | HeciValidateMebxPassword (IN UINT8 PasswordSize, IN UINT8 *Password, OUT BOOLEAN *MaxRetries)
This function uses the User entered password to login into FW. More...
EFI_STATUS | HeciIsMebxPasswordModified (OUT UINT32 *Modified)
Checks if password was modified. More...
EFI_STATUS | HeciFwCapsGetRuleData (IN UINT32 RuleId, OUT UINT32 *RuleData)
Send Get Rule Data Request to CSME. More...
EFI_STATUS | HeciGetFwCapsSkuMsg (OUT MEFWCAPS_SKU *RuleData)
Send Get Firmware SKU Request to ME. More...
EFI_STATUS | HeciGetFwUpdateState (OUT UINT8 *RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to query the local firmware update interface status. More...
EFI_STATUS | HeciGetUserCapabilitiesState (OUT MEFWCAPS_SKU *RuleData)
Send Get User Capabilities State Request to ME. More...
EFI_STATUS | HeciGetPlatformTypeMsg (OUT PLATFORM_TYPE_RULE_DATA *RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to get Ibex Peak platform type. More...
EFI_STATUS | HeciGetFwFeatureStateMsg (OUT MEFWCAPS_SKU *RuleData)
The Get FW Feature Status message is based on MKHI interface. More...
EFI_STATUS | HeciGetSouthClinkState (OUT UINT32 *SouthClinkState)
Get value of South Clink State from ME. More...
EFI_STATUS | HeciGetFwAvailableFeatures (OUT UINT32 *FwFeatures)
Get available ME features. More...
EFI_STATUS | HeciGetMoffOverrideState (OUT UINT32 *MOffOverrideState)
Get Override Capability State for M3 to Moff Transitions. More...
EFI_STATUS | HeciGetOemTagMsg (OUT UINT32 *RuleData)
The firmware will respond to GET OEM TAG message even after the End of Post (EOP). More...
EFI_STATUS | HeciGetUnconfigOnRtcClearDisableMsg (OUT UINT32 *RuleData)
This message is sent by the BIOS when it wants to query ME Unconfig on RTC Clear Disable state. More...
EFI_STATUS | HeciGetAmtBiosSyncInfo (OUT AMT_BIOS_SYNC_INFO *RuleData)
This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state. More...
EFI_STATUS | HeciGetIsUserConsentRequired (OUT BOOLEAN *IsUserConsentRequired)
Get User Consent requirement. More...
BOOLEAN | IsCiraAvailable (VOID)
Return information if Client Initiated Remote Access (CIRA) is available. More...
EFI_STATUS | HeciFwCapsSetRuleData (IN UINT32 RuleId, IN UINT8 RuleDataLength, IN UINT32 RuleData)
Send Set Rule Data Request to CSME. More...
EFI_STATUS | HeciSetMeDisableMsg (VOID)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to disable the ME State. More...
EFI_STATUS | HeciSetFwUpdateState (IN UINT8 RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to enable or disable the local firmware update interface. More...
EFI_STATUS | HeciSetUserCapabilitiesState (IN MEFWCAPS_SKU RuleData)
Send Set User Capabilities State Request to ME. More...
EFI_STATUS | HeciSetFwEnabledFeatures (IN UINT32 NewFeatures, IN UINT32 FeaturesMask)
Set FW Enabled Features. More...
EFI_STATUS | HeciSetSouthClinkState (IN UINT32 SouthClinkState)
Set South Clink State. More...
EFI_STATUS | HeciSetMoffOverrideState (IN UINT32 MoffOverrideState)
Set Moff Override State. More...
EFI_STATUS | HeciSetAcmTpmData (IN UINT8 TpmDeactivate)
This message is sent by the BIOS to inform ME FW whether or not to take the TPM 1.2 Deactivate flow. More...
EFI_STATUS | HeciSetUnconfigOnRtcClearDisableMsg (IN UINT32 RuleData)
This message is sent by the BIOS when it wants to set ME Unconfig on RTC Clear Disable state. More...
EFI_STATUS | HeciHmrfpoEnable (OUT UINT8 *Result)
Sends a message to ME to unlock a specified SPI Flash region for writing and receiving a response message. More...
EFI_STATUS | HeciHmrfpoLock (OUT UINT8 *Result)
Sends a message to ME to lock a specified SPI Flash region for writing and receiving a response message. More...
EFI_STATUS | HeciHmrfpoGetStatus (OUT UINT8 *Result)
System BIOS sends this message to get status for HMRFPO_LOCK message. More...
EFI_STATUS | HeciReadFileExMsg (IN UINT32 FileId, IN UINT32 Offset, IN OUT UINT32 *DataSize, IN UINT8 Flags, OUT UINT8 *DataBuffer)
This message is sent by the BIOS to retrieve file stored in ME firmware NVM. More...
EFI_STATUS | HeciGetDamState (OUT UINT8 *DamState)
Read Delayed Authentication Mode from ME NVM. More...
EFI_STATUS | HeciGetPlatIdSupportedState (OUT UINT8 *PlatIdSupported)
Read UPID Platform Id feature supported state from ME NVM. More...
EFI_STATUS | HeciSetFileExMsg (IN UINT32 FileId, IN UINT32 Offset, IN UINT32 DataSize, IN UINT8 Flags, IN UINT8 *DataBuffer)
This message is sent by the BIOS to save data in a file stored in ME firmware NVM. More...
EFI_STATUS | HeciSetDamState (IN UINT8 DamState)
Set Delayed Authentication Mode in ME NVM. More...
EFI_STATUS | HeciCommitFilesMsg (VOID)
This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit previously set files. More...
EFI_STATUS | HeciCoreBiosDoneMsg (VOID)
This message is sent by the BIOS to notify ME firmware that the BIOS is starting to run 3rd party code. More...
EFI_STATUS | HeciGetRpmcStatus (OUT RP_STATUS_2 *RpStatus)
This message is sent by the BIOS to retrieve RPMC status data from CSME. More...
EFI_STATUS | HeciArbSvnCommitMsg (VOID)
This command indicates to the FW that it shall commit ARBSVN to fuse. More...
EFI_STATUS | HeciArbSvnGetInfoMsg (IN OUT UINT32 *Entries, IN OUT ARB_SVN_INFO_ENTRY *ArbSvnInfo)
The command retrieves anti-replay SVN information. More...
EFI_STATUS | HeciDnxReqClear (IN UINT32 Flag)
Send Dnx Request Clear message. More...
EFI_STATUS | HeciSetMeEnableMsg (VOID)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to enable the ME State. More...
EFI_STATUS | HeciHmrfpoDisable (VOID)
Send HMRFPO disable MKHI to CSME. More...
EFI_STATUS | HeciGetErLog (OUT UINT8 *EventLogBuffer, IN UINT32 RemainingBufSize, IN OUT UINT32 *ReceivedLogSize, IN OUT UINT8 *LogEntryIndex, OUT UINT8 *RemainingEntries)
This function sends a command to CSME to get Log information of Measurements provided in CSME Extend Registers for BIOS to extend to TPM-PCR registers. More...
EFI_STATUS | HeciGetMkhiVersion (OUT MKHI_VERSION *MkhiVersion)
Get MKHI (Management Engine Kernel Host Interface) Version. More...
EFI_STATUS | HeciGetFwVersionMsg (OUT GET_FW_VER_ACK_DATA *GetFwVersionAckData)
Send Get Firmware Version Request to ME. More...
EFI_STATUS | HeciSendCpuBrandClassFuse (IN UINT8 CpuBrandClass)
Send CPU brand class fuse to the CSME (only for corporate SKU). More...
EFI_STATUS | HeciGetCpuTypeChange (OUT GEN_GET_CPU_TYPE_CHANGE_DATA *CpuTypeChangeInfo)
Get CPU Type Change User Message. More...
EFI_STATUS | HeciSetCpuTypeChangeUserResponse (IN UINT8 UserResponse)
Send CPU Type Change User Response. More...
EFI_STATUS | HeciUnconfigWithouPwd (VOID)
Unconfigure ME without password. More...
EFI_STATUS | HeciGetUnconfigureStatus (OUT UINT8 *UnconfigStatus)
Get ME Unconfiguration Status. More...
EFI_STATUS | HeciSetManufacturingMeResetAndHalt (VOID)
Send Set Manufacturing Me Reset and Halt Request to ME. More...
EFI_STATUS | HeciFwFeatureStateOverride (IN UINT32 EnableBitmask, IN UINT32 DisableBitmask)
Sends the MKHI Enable/Disable FW Features. More...
EFI_STATUS | HeciGetImageFwVersionMsg (IN UINT32 PartitionId, OUT FLASH_PARTITION_DATA *PartitionIdData)
Send Get Image Firmware Version Request to ME. More...
EFI_STATUS | HeciSetFipsMode (IN UINT32 FipsMode)
Send Set FIPS Mode to Enabled or Disabled. More...
EFI_STATUS | HeciGetFipsMode (OUT GET_FIPS_MODE_DATA *GetFipsModeData)
Send Get Current FIPS Mode and Crypto Driver version. More...
EFI_STATUS | HeciSetMeasuredBootState (IN UINT8 SetMeasuredBootState)
Send Set Measured Boot State to Enable or Disable CSME Measurement. More...
EFI_STATUS | HeciGetMeasuredBootState (OUT UINT8 *GetMeasuredBootState)
Send Get Current CSME Measured Boot State. More...
EFI_STATUS | HeciGetIccProfile (OUT UINT8 *Profile, OUT UINT8 *NumProfiles, OUT UINT8 *IccSelectAllowed, OUT ICC_PROFILE_DESC *ProfileDescriptions)
Retrieves the number of currently used ICC clock profile. More...
EFI_STATUS | HeciSetIccProfile (IN UINT8 Profile)
Sets ICC clock profile to be used on next and following boots. More...
EFI_STATUS | HeciGetIccClockSettings (IN OUT ICC_CLOCK_SETTINGS *IccClockSettings)
Retrieves the current settings of ICC. More...
EFI_STATUS | HeciSetIccClockSettings (IN ICC_CLOCK_SETTINGS *IccClockSettings)
Sets ICC clock profile to be used on next and following boots. More...
EFI_STATUS | HeciAssetUpdateFwMsg (IN HWA_TABLE *AssetTableData, IN UINT16 TableDataSize)
Send Hardware Asset Tables to Firmware. More...
EFI_STATUS | HeciGetUpidFeatureState (IN UINT32 UpidFeature, OUT UINT8 *UpidFeatureState)
This message is sent by the BIOS to check if given UPID feature is enabled in CSME. More...
EFI_STATUS | HeciSetUpidFeatureState (IN UINT32 UpidFeature, IN UINT8 UpidFeatureState)
This message is sent by the BIOS to set given UPID feature state in CSME. More...
EFI_STATUS | HeciGetUpidOsControlState (IN UINT32 UpidFeature, OUT UINT8 *UpidFeatureOsControlState)
This message is sent by the BIOS to check if given UPID feature state can be modified by the OS. More...
EFI_STATUS | HeciSetUpidOsControlState (IN UINT32 UpidFeature, IN UINT8 UpidFeatureOsControlState)
This message is sent by the BIOS to set if given UPID feature state can be modified by the OS. More...
EFI_STATUS | HeciGetUpidPlatformId (OUT UINT32 *OemPlatformIdType, OUT UINT8 *OemPlatformId, OUT UINT8 *CsmePlatformId)
This message is sent by the BIOS to read the Platform Id. More...
EFI_STATUS | HeciGetUpidRefurbishCounter (OUT UINT8 *PlatformIdRefurbishCounter)
This message is sent by the BIOS to read the current Platform Id Refurbish Counter. More...
EFI_STATUS | HeciUpdateUpidOemPlatformId (IN UINT32 OemPlatformIdType, IN UINT8 *OemPlatformId, IN UINT8 ManufacturingType)
This message is sent by the BIOS to update the OEM Platform Id. More...
BOOLEAN | MeEndOfPostEnabled (VOID)
Check if End of Post Message is enabled in setup options. More...
BOOLEAN | MeHeci2Enabled (VOID)
Check if HECI2 should be removed from PCI space or not. More...
BOOLEAN | MeHeciMessageCheckEnabled (VOID)
Read the ME policy to see if HECI message check is enabled for Bios Boot Path. More...
VOID | MeReportError (IN ME_ERROR_MSG_ID MsgId)
Show Me Error message. More...
BOOLEAN | MeFwDowngradeSupported (VOID)
Check if MeFwDowngrade is enabled in setup options. More...
BOOLEAN | IsExtendedMeasuredBootEnabled (VOID)
Check if Extended CSME Measured Boot is enabled from BIOS side. More...
BOOLEAN | MeCoreBiosDoneEnabled (VOID)
Check if Core Bios Done Message is enabled in setup options. More...
BOOLEAN | MeHeciTimeoutsEnabled (VOID)
Read the ME policy to see if HECI timeouts are enabled. More...
BOOLEAN | MeHeciFullTrace (VOID)
Read the ME policy to see if Heci Full Trace are enabled. More...
BOOLEAN | MeHeciD0I3Enabled (VOID)
Read the ME policy to see if D0I3 for HECI devices are enabled. More...
BOOLEAN | MeIsAfterEndOfPost (VOID)
Checks if EndOfPost event already happened. More...
VOID | MeSetEndOfPostDone (VOID)
Set EndOfPost done.

Detailed Description

Header file for functions to get Intel ME information.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeMeLib.h.

Function Documentation

◆ HbmCapabilitiesRequest()

EFI_STATUS HbmCapabilitiesRequest | ( | IN HECI_DEVICE | HeciDev,
 |  | IN OUT HBM_CAPS_DATA * | HbmCaps
 | ) |  |

Informs about Host and CSME capabilities over HBM.

Parameters
[in] | HeciDev | HECI device number
[in,out] | HbmCaps | On input: Host HBM capabilities On output: CSME HBM capabilities
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | NULL parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmClientDisconnect()

EFI_STATUS HbmClientDisconnect | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | HostAddr,
 |  | IN UINT8 | MeAddr
 | ) |  |

Disconnects an established connection between a Host and CSME clients.

Parameters
[in] | HeciDev | HECI device number
[in] | HostAddr | Host Address of the connection
[in] | MeAddr | CSME Address of the connection
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmGetClientProperties()

EFI_STATUS HbmGetClientProperties | ( | IN HECI_DEVICE | HeciDevice,
 |  | IN UINT8 | ClientAddr,
 |  | OUT EFI_GUID * | ProtocolGuid
 | ) |  |

Retrieves GUID of a single CSME client.

Parameters
[in] | HeciDevice | HECI device number
[in] | ClientAddr | Address of the CSME client
[out] | ProtocolGuid | GUID of the client
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmGetFlowControlToken()

EFI_STATUS HbmGetFlowControlToken | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | HostAddr,
 |  | IN UINT8 | MeAddr
 | ) |  |

Attempts to receive a flow control token from CSME.

This token allows BIOS to send one message over commection identified by Host:Me address pair

Parameters
[in] | HeciDev | HECI device number
[in] | HostAddr | Address of the Host client
[in] | MeAddr | Address of the CSME client
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HbmHostClientConnect()

EFI_STATUS HbmHostClientConnect | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | MeAddress,
 |  | IN UINT8 | HostAddress
 | ) |  |

Creates a connection between given host and CSME addresses.

Parameters
[in] | HeciDev | HECI device number
[in] | MeAddress | Address of the CSME client
[in] | HostAddress | Address of the Host client
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmHostEnumRequest()

EFI_STATUS HbmHostEnumRequest | ( | IN HECI_DEVICE | HeciDevice,
 |  | OUT UINT8 * | ValidAddresses
 | ) |  |

Checks at which CSME addresses there are any clients.

Parameters
[in] | HeciDevice | HECI device number
[out] | ValidAddresses | Mask of addresses that have a client behind them
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmHostStop()

EFI_STATUS HbmHostStop ( IN HECI_DEVICE HeciDev )

Instructs CSME to stop all communication on given Heci device.

Parameters
[in] HeciDev HECI device number
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HbmHostVersion()

EFI_STATUS HbmHostVersion ( IN HECI_DEVICE HeciDev )

Checks if CSME supports HBM protocol version 2.2.

Parameters
[in] HeciDev HECI device number
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received
EFI_INCOMPATIBLE_VERSION | CSME does not support protocol version required by BIOS

◆ HbmMapRequest()

EFI_STATUS HbmMapRequest | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | ClientDmaBufferId,
 |  | IN UINT32 | AddressLow,
 |  | IN UINT32 | AddressHigh,
 |  | IN UINT32 | Size
 | ) |  |

Requests mapping CSME HECI client MMIO to the given physcial memory addresses.

Parameters
[in] | HeciDev | HECI device number
[in] | ClientDmaBufferId | Identifies Client Id to which physical address should be mapped
[in] | AddressLow | Physical address for DMA buffer (Low DWORD)
[in] | AddressHigh | Physical address for DMA buffer (High DWORD)
[in] | Size | Size of the physical memory to be mapped
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HbmSendFlowControlToken()

EFI_STATUS HbmSendFlowControlToken | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | HostAddr,
 |  | IN UINT8 | MeAddr
 | ) |  |

Sends a flow control token from BIOS to CSME that allows CSME to send one message over connection identified by host:Me address pair.

Parameters
[in] | HeciDev | HECI device number
[in] | HostAddr | Address of the Host client
[in] | MeAddr | Address of the CSME client
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HbmUnmapRequest()

EFI_STATUS HbmUnmapRequest | ( | IN HECI_DEVICE | HeciDev,
 |  | IN UINT8 | ClientDmaBufferId
 | ) |  |

Requests unmapping CSME HECI client MMIO from the given physcial memory addresses.

Parameters
[in] | HeciDev | HECI device number
[in] | ClientDmaBufferId | Identifies Client Id from which physical address should be unampped
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ABORTED | Wrong response was received

◆ HeciArbSvnCommitMsg()

EFI_STATUS HeciArbSvnCommitMsg ( VOID )

This command indicates to the FW that it shall commit ARBSVN to fuse.

Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally

◆ HeciArbSvnGetInfoMsg()

EFI_STATUS HeciArbSvnGetInfoMsg | ( | IN OUT UINT32 * | Entries,
 |  | IN OUT ARB_SVN_INFO_ENTRY * | ArbSvnInfo
 | ) |  |

The command retrieves anti-replay SVN information.

Caller can set Entries as 0 to get the correct number of entries CSME contains.

Parameters
[in,out] | Entries | On input, it is the number of entries caller expects. On output, it indicates the number of entries CSME contains.
[in,out] | ArbSvnInfo | Anti-Rollback SVN Information
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_OUT_OF_RESOURCES | Unable to allocate required resources
EFI_BUFFER_TOO_SMALL | The Entries is too small for the result

◆ HeciAssetUpdateFwMsg()

EFI_STATUS HeciAssetUpdateFwMsg | ( | IN HWA_TABLE * | AssetTableData,
 |  | IN UINT16 | TableDataSize
 | ) |  |

Send Hardware Asset Tables to Firmware.

Parameters
[in] | AssetTableData | Hardware Asset Table Data
[in] | TableDataSize | Size of Asset table
Return values
EFI_SUCCESS | Table sent
EFI_ABORTED | Could not allocate Memory

◆ HeciClearInvocationCode()

EFI_STATUS HeciClearInvocationCode ( IN UINT32 InvocationCode )

Clear invocation codes in Firmware.

Parameters
[in] InvocationCode Bitmask of invocation codes to be cleared by Firmware.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciCommitFilesMsg()

EFI_STATUS HeciCommitFilesMsg ( VOID )

This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit previously set files.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciCoreBiosDoneMsg()

EFI_STATUS HeciCoreBiosDoneMsg ( VOID )

This message is sent by the BIOS to notify ME firmware that the BIOS is starting to run 3rd party code.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function or EOP was sent
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally

◆ HeciDnxReqClear()

EFI_STATUS HeciDnxReqClear ( IN UINT32 Flag )

Send Dnx Request Clear message.

Parameters
[in] Flag Flag indicating the type of clear operation: 0 - cancel DNX Operation 1 - Global reset 2 - CSE reset 3 - Cold reset
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciFwCapsGetRuleData()

EFI_STATUS HeciFwCapsGetRuleData | ( | IN UINT32 | RuleId,
 |  | OUT UINT32 * | RuleData
 | ) |  |

Send Get Rule Data Request to CSME.

Parameters
[in] | RuleId | Identifies the rule which data is requested.
[out] | *RuleData | Pointer to requested rule data.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_INVALID_PARAMETER | Parameter invalid.

◆ HeciFwCapsSetRuleData()

EFI_STATUS HeciFwCapsSetRuleData | ( | IN UINT32 | RuleId,
 |  | IN UINT8 | RuleDataLength,
 |  | IN UINT32 | RuleData
 | ) |  |

Send Set Rule Data Request to CSME.

Parameters
[in] | RuleId | Identifies the rule which data needs to be changed.
[in] | RuleDataLength | Rule Data Length.
[in] | RuleData | Pointer to new rule data.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciFwFeatureStateOverride()

EFI_STATUS HeciFwFeatureStateOverride | ( | IN UINT32 | EnableBitmask,
 |  | IN UINT32 | DisableBitmask
 | ) |  |

Sends the MKHI Enable/Disable FW Features.

Parameters
[in] | EnableBitMask | Bitmask of features to enable
[in] | DisableBitMask | Bitmask of features to disable
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_ACCESS_DENIED | Command request is rejected

◆ HeciGetAmtBiosSyncInfo()

EFI_STATUS HeciGetAmtBiosSyncInfo ( OUT AMT_BIOS_SYNC_INFO * RuleData )

This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state.

The firmware will respond to AMT BIOS SYNC INFO message even after the End of Post.

Parameters
[out] RuleData
See also
AMT_BIOS_SYNC_INFO
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetCpuTypeChange()

EFI_STATUS HeciGetCpuTypeChange ( OUT GEN_GET_CPU_TYPE_CHANGE_DATA * CpuTypeChangeInfo )

Get CPU Type Change User Message.

Parameters
[in] CpuTypeChangeInfo CPU Type Change User Message
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetDamState()

EFI_STATUS HeciGetDamState ( OUT UINT8 * DamState )

Read Delayed Authentication Mode from ME NVM.

Parameters
[out] *DamState Delayed Authentication Mode State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetErLog()

EFI_STATUS HeciGetErLog | ( | OUT UINT8 * | EventLogBuffer,
 |  | IN UINT32 | RemainingBufSize,
 |  | IN OUT UINT32 * | ReceivedLogSize,
 |  | IN OUT UINT8 * | LogEntryIndex,
 |  | OUT UINT8 * | RemainingEntries
 | ) |  |

This function sends a command to CSME to get Log information of Measurements provided in CSME Extend Registers for BIOS to extend to TPM-PCR registers.

Parameters
[out] | EventLogBuffer | Pointer to received Event log buffer
[in] | RemainingBufSize | Size of available buffer to collect event log
[out] | ReceivedLogSize | Size of received event log
[in,out] | LogEntryIndex | On input - Index of first / starting log entry in the buffer. On output - Index of last log entry returned
[out] | RemainingEntries | Pointer to Remaining Entries (0 - no more entries in a log; 1 - additional iteration(s) is(are) required)
Return values
EFI_SUCCESS | Log received successfully
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout or transition failed within allowed time limit

◆ HeciGetFipsMode()

EFI_STATUS HeciGetFipsMode ( OUT GET_FIPS_MODE_DATA * GetFipsModeData )

Send Get Current FIPS Mode and Crypto Driver version.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetFwAvailableFeatures()

EFI_STATUS HeciGetFwAvailableFeatures ( OUT UINT32 * FwFeatures )

Get available ME features.

Parameters
[out] FwFeatures Mask of available ME Features
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetFwCapsSkuMsg()

EFI_STATUS HeciGetFwCapsSkuMsg ( OUT MEFWCAPS_SKU * RuleData )

Send Get Firmware SKU Request to ME.

Parameters
[out] *FwCapsSku Firmware Capabilities
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetFwFeatureStateMsg()

EFI_STATUS HeciGetFwFeatureStateMsg ( OUT MEFWCAPS_SKU * RuleData )

The Get FW Feature Status message is based on MKHI interface.

This command is used by BIOS/IntelR MEBX to get firmware runtime status. The GET FW RUNTIME STATUS message doesn't need to check the HFS.FWInitComplete value before sending the command. It means this message can be sent regardless of HFS.FWInitComplete.

Parameters
[out] *RuleData MEFWCAPS_SKU message
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetFwUpdateState()

EFI_STATUS HeciGetFwUpdateState ( OUT UINT8 * RuleData )

This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to query the local firmware update interface status.

Parameters
[out] RuleData 1 - local firmware update interface enable 0 - local firmware update interface disable
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetFwVersionMsg()

EFI_STATUS HeciGetFwVersionMsg ( OUT GET_FW_VER_ACK_DATA * GetFwVersionAckData )

Send Get Firmware Version Request to ME.

Parameters
[out] *GetFwVersionAckData Return the message of FW version
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetIccClockSettings()

EFI_STATUS HeciGetIccClockSettings ( IN OUT ICC_CLOCK_SETTINGS * IccClockSettings )

Retrieves the current settings of ICC.

Parameters
[in,out] IccClockSettings Current settings of ICC
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_NOT_READY | Heci device hasn't ready yet
EFI_INVALID_PARAMETER | IccClockSettings is a NULL pointer
EFI_SUCCESS | Command succeeded

◆ HeciGetIccProfile()

EFI_STATUS HeciGetIccProfile | ( | OUT UINT8 * | Profile,
 |  | OUT UINT8 * | NumProfiles,
 |  | OUT UINT8 * | IccSelectAllowed,
 |  | OUT ICC_PROFILE_DESC * | ProfileDescriptions
 | ) |  |

Retrieves the number of currently used ICC clock profile.

Parameters
[out] | Profile | Number of current ICC clock profile
[out] | NumProfiles | Number of supported motherboard profiles
[out] | IccSelectAllowed | Allow ICC profile changeable
[out] | ProfileDescriptions | Pointer of Profile Descriptions
Return values
EFI_UNSUPPORTED | ICC clock profile doesn't support
EFI_NOT_READY | Heci device hasn't ready yet
EFI_SUCCESS | Command succeeded

◆ HeciGetImageFwVersionMsg()

EFI_STATUS HeciGetImageFwVersionMsg | ( | IN UINT32 | PartitionId,
 |  | OUT FLASH_PARTITION_DATA * | PartitionIdData
 | ) |  |

Send Get Image Firmware Version Request to ME.

Parameters
[in] | PartitionId | Partition ID
[out] | PartitionIdData | Return the version of the Partition ID
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetInvocationCode()

EFI_STATUS HeciGetInvocationCode ( OUT UINT32 * InvocationCode )

Retrieve invocation codes from Firmware.

Parameters
[out] InvocationCode Bitmask of invocation codes set by Firmware.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetIsUserConsentRequired()

EFI_STATUS HeciGetIsUserConsentRequired ( OUT BOOLEAN * IsUserConsentRequired )

Get User Consent requirement.

Parameters
[out] IsUserConsentRequired User consent requirement: TRUE - User Consent required FALSE - User Consent not required
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetMeasuredBootState()

EFI_STATUS HeciGetMeasuredBootState ( OUT UINT8 * GetMeasuredBootState )

Send Get Current CSME Measured Boot State.

Parameters
[out] GetMeasuredBootState Pointer to get CSME Measured boot status.
Return values
EFI_UNSUPPORTED | Current (CS)ME mode/version doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetMkhiVersion()

EFI_STATUS HeciGetMkhiVersion ( OUT MKHI_VERSION * MkhiVersion )

Get MKHI (Management Engine Kernel Host Interface) Version.

Parameters
[out] MkhiVersion MKHI Version
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetMoffOverrideState()

EFI_STATUS HeciGetMoffOverrideState ( OUT UINT32 * MOffOverrideState )

Get Override Capability State for M3 to Moff Transitions.

Parameters
[out] MOffOverrideState ME MOFF Override State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetOemTagMsg()

EFI_STATUS HeciGetOemTagMsg ( OUT UINT32 * RuleData )

The firmware will respond to GET OEM TAG message even after the End of Post (EOP).

Parameters
[out] RuleData Default is zero. Tool can create the OEM specific OEM TAG data.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetPlatformTypeMsg()

EFI_STATUS HeciGetPlatformTypeMsg ( OUT PLATFORM_TYPE_RULE_DATA * RuleData )

This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to get Ibex Peak platform type.

One of usages is to utilize this command to determine if the platform runs in Consumer or Corporate SKU size firmware.

Parameters
[out] RuleData PlatformBrand, IntelMeFwImageType, SuperSku, PlatformTargetUsageType
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetPlatIdSupportedState()

EFI_STATUS HeciGetPlatIdSupportedState ( OUT UINT8 * PlatIdSupported )

Read UPID Platform Id feature supported state from ME NVM.

Parameters
[out] PlatIdSupported Platform Id feature supported State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetPsrRecord()

EFI_STATUS HeciGetPsrRecord ( IN OUT PSR_DATA * PsrData )

Get Platform Service Record from CSME.

Parameters
[in,out] PsrData Pointer to PSR data struct
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current CSME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetRpmcStatus()

EFI_STATUS HeciGetRpmcStatus ( OUT RP_STATUS_2 * RpStatus )

This message is sent by the BIOS to retrieve RPMC status data from CSME.

Parameters
[out] RpStatus RPMC status data
Return values
EFI_SUCCESS | Command succeeded
EFI_NOT_FOUND | Couldn't locate HeciPpi
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI
EFI_INVALID_PARAMETER | Parameter invalid

◆ HeciGetSouthClinkState()

EFI_STATUS HeciGetSouthClinkState ( OUT UINT32 * SouthClinkState )

Get value of South Clink State from ME.

Parameters
[out] SouthClinkState South Clink State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUnconfigOnRtcClearDisableMsg()

EFI_STATUS HeciGetUnconfigOnRtcClearDisableMsg ( OUT UINT32 * RuleData )

This message is sent by the BIOS when it wants to query ME Unconfig on RTC Clear Disable state.

Parameters
[out] RuleData 1 - Unconfig on RTC clear is disabled 0 - Unconfig on RTC clear is not disabled
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUnconfigureStatus()

EFI_STATUS HeciGetUnconfigureStatus ( OUT UINT8 * UnconfigStatus )

Get ME Unconfiguration Status.

Parameters
[out] UnconfigStatus Unconfiguration Status: 0x01 - Unconfiguration in progress 0x02 - No unconfigure w/o password to be processed 0x03 - CSME finished processing unconfigure w/o password 0x80 - Error encountered by CSME during unconfigure w/o password
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUpidFeatureState()

EFI_STATUS HeciGetUpidFeatureState | ( | IN UINT32 | UpidFeature,
 |  | OUT UINT8 * | UpidFeatureState
 | ) |  |

This message is sent by the BIOS to check if given UPID feature is enabled in CSME.

Parameters
[in] | UpidFeature | UPID feature
[out] | UpidFeatureState | Determines if feature is enabled
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUpidOsControlState()

EFI_STATUS HeciGetUpidOsControlState | ( | IN UINT32 | UpidFeature,
 |  | OUT UINT8 * | UpidFeatureOsControlState
 | ) |  |

This message is sent by the BIOS to check if given UPID feature state can be modified by the OS.

Parameters
[in] | UpidFeature | UPID feature
[out] | UpidFeatureOsControlState | Determines if OS can modify the feature state
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUpidPlatformId()

EFI_STATUS HeciGetUpidPlatformId | ( | OUT UINT32 * | OemPlatformIdType,
 |  | OUT UINT8 * | OemPlatformId,
 |  | OUT UINT8 * | CsmePlatformId
 | ) |  |

This message is sent by the BIOS to read the Platform Id.

Parameters
[out] | OemPlatformIdType | Determines format of the OemPlatformId field
[out] | OemPlatformId | Platform Id set by the OEM
[out] | CsmePlatformId | CSME Platfrom Id generated from CSME fuses
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUpidRefurbishCounter()

EFI_STATUS HeciGetUpidRefurbishCounter ( OUT UINT8 * PlatformIdRefurbishCounter )

This message is sent by the BIOS to read the current Platform Id Refurbish Counter.

Parameters
[out] PlatformIdRefurbishCounter Current value of the Refurbish Counter
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciGetUserCapabilitiesState()

EFI_STATUS HeciGetUserCapabilitiesState ( OUT MEFWCAPS_SKU * RuleData )

Send Get User Capabilities State Request to ME.

Parameters
[out] RuleData User Capabilities State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciHmrfpoDisable()

EFI_STATUS HeciHmrfpoDisable ( VOID )

Send HMRFPO disable MKHI to CSME.

Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ HeciHmrfpoEnable()

EFI_STATUS HeciHmrfpoEnable ( OUT UINT8 * Result )

Sends a message to ME to unlock a specified SPI Flash region for writing and receiving a response message.

It is recommended that HMRFPO_ENABLE MEI message needs to be sent after all OPROMs finish their initialization.

Parameters
[out] Result HMRFPO_ENABLE response
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciHmrfpoGetStatus()

EFI_STATUS HeciHmrfpoGetStatus ( OUT UINT8 * Result )

System BIOS sends this message to get status for HMRFPO_LOCK message.

Parameters
[out] Result HMRFPO_GET_STATUS response
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciHmrfpoLock()

EFI_STATUS HeciHmrfpoLock ( OUT UINT8 * Result )

Sends a message to ME to lock a specified SPI Flash region for writing and receiving a response message.

Parameters
[out] Result Status report
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_NOT_READY | HECI Device hasn't ready yet
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciIsMebxPasswordModified()

EFI_STATUS HeciIsMebxPasswordModified ( OUT UINT32 * Modified )

Checks if password was modified.

Parameters
[out] Modified Password modification status
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_INVALID_PARAMETER | Parameter invalid

◆ HeciModifyMebxPassword()

ME_PWD_STATUS HeciModifyMebxPassword | ( | IN UINT8 | OldPwdSize,
 |  | IN UINT8 * | OldPwd,
 |  | IN UINT8 | NewPwdSize,
 |  | IN UINT8 * | NewPwd
 | ) |  |

This function logs in with current password and updates to new password.

Parameters
[in] | OldPwdSize | Size of the old password
[in] | OldPwd | Buffer holding old password
[in] | NewPwdSize | Size of the new password
[in] | NewPwd | Buffer holding new password
Return values
ME_PWD_STATUS Password management Status Code:
See also
ME_PWD_STATUS

◆ HeciPdtUnlockMsg()

EFI_STATUS HeciPdtUnlockMsg ( IN CONST CHAR8 * FileName )

This message is sent by the BIOS when it wants to send PDT Unlock Message to ISH.

Parameters
[in] FileName File name of bios2ish file.
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function or EOP was sent
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_BAD_BUFFER_SIZE | The size of FileName is larger than maximum allowed value

◆ HeciPdtUpdateMsg()

EFI_STATUS HeciPdtUpdateMsg | ( | IN CONST CHAR8 * | FileName,
 |  | IN UINT8 * | PdtFileBuffer,
 |  | IN UINT16 | PdtBufferSize
 | ) |  |

This message is sent by the BIOS when it wants to send PDT Update Message.

Parameters
[in] | FileName | File name of bios2ish file.
[in] | PdtFileBuffer | Contains ISH PDT file
[in] | PdtBufferSize | Size of PDT file
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function or EOP was sent
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_ABBORTED | Unable to allocate memory
EFI_BAD_BUFFER_SIZE | The size of FileName is larger than maximum allowed value

◆ HeciReadFileExMsg()

EFI_STATUS HeciReadFileExMsg | ( | IN UINT32 | FileId,
 |  | IN UINT32 | Offset,
 |  | IN OUT UINT32 * | DataSize,
 |  | IN UINT8 | Flags,
 |  | OUT UINT8 * | DataBuffer
 | ) |  |

This message is sent by the BIOS to retrieve file stored in ME firmware NVM.

Parameters
[in] | FileId | Id number of file to read
[in] | Offset | File offset
[in,out] | DataSize | On input - size of data to read, on output - size of read data
[in] | Flags | Flags
[out] | *Buffer | Pointer to the data buffer
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSendCbmResetRequest()

EFI_STATUS HeciSendCbmResetRequest | ( | IN UINT8 | ResetOrigin,
 |  | IN UINT8 | ResetType
 | ) |  |

Send Core BIOS Reset Request Message through HECI to reset the system.

Parameters
[in] | ResetOrigin | Reset source
[in] | ResetType | Global or Host reset
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ HeciSendChassisIntrDetEvent()

EFI_STATUS HeciSendChassisIntrDetEvent ( VOID )

Inform CSME of Chassis Intrusion Detected Event.

Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current CSME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ HeciSendCpuBrandClassFuse()

EFI_STATUS HeciSendCpuBrandClassFuse ( IN UINT8 CpuBrandClass )

Send CPU brand class fuse to the CSME (only for corporate SKU).

This message is required for BIOS running on CPUs don't support SID message to obtain CPU information.

Parameters
[in] CpuBrandClass CPU brand class
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetAcmTpmData()

EFI_STATUS HeciSetAcmTpmData ( IN UINT8 TpmDeactivate )

This message is sent by the BIOS to inform ME FW whether or not to take the TPM 1.2 Deactivate flow.

Parameters
[in] TpmDeactivate 0 - ME FW should not take the deactivate flow. 1 - ME FW should take the deactivate flow.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetCpuTypeChangeUserResponse()

EFI_STATUS HeciSetCpuTypeChangeUserResponse ( IN UINT8 UserResponse )

Send CPU Type Change User Response.

Parameters
[in] UserResponse CPU Type Change User Response: 0 - Change Rejected 1 - Change Accepted
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetDamState()

EFI_STATUS HeciSetDamState ( IN UINT8 DamState )

Set Delayed Authentication Mode in ME NVM.

Parameters
[in] DamState New Delayed Authentication Mode State: 0 - DAM Disable 1 - DAM Enable
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetFileExMsg()

EFI_STATUS HeciSetFileExMsg | ( | IN UINT32 | FileId,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | DataSize,
 |  | IN UINT8 | Flags,
 |  | IN UINT8 * | DataBuffer
 | ) |  |

This message is sent by the BIOS to save data in a file stored in ME firmware NVM.

Parameters
[in] | FileId | Id Number of file to write
[in] | Offset | File offset
[in] | DataSize | Size of data to write
[in] | Flags | Flags
[in] | *DataBuffer | Pointer to the data buffer
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_ABORTED | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetFipsMode()

EFI_STATUS HeciSetFipsMode ( IN UINT32 FipsMode )

Send Set FIPS Mode to Enabled or Disabled.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetFwEnabledFeatures()

EFI_STATUS HeciSetFwEnabledFeatures | ( | IN UINT32 | NewFeatures,
 |  | IN UINT32 | FeaturesMask
 | ) |  |

Set FW Enabled Features.

Parameters
[in] | NewFeatures | New Fw Enabled Features
[in] | FeaturesMask | Bitmask with new Fw Enabled Features
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetFwUpdateState()

EFI_STATUS HeciSetFwUpdateState ( IN UINT8 RuleData )

This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to enable or disable the local firmware update interface.

The firmware allows a single update once it receives the enable command

Parameters
[in] RuleData 1 - local firmware update interface enable 0 - local firmware update interface disable
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetIccClockSettings()

EFI_STATUS HeciSetIccClockSettings ( IN ICC_CLOCK_SETTINGS * IccClockSettings )

Sets ICC clock profile to be used on next and following boots.

Parameters
[in] IccClockSettings Pointer for requested ICC Clock Settings
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | Wrong response
EFI_NOT_READY | Heci device hasn't ready yet
EFI_INVALID_PARAMETER | IccClockSettings is a NULL pointer
EFI_SUCCESS | Command succeeded

◆ HeciSetIccProfile()

EFI_STATUS HeciSetIccProfile ( IN UINT8 Profile )

Sets ICC clock profile to be used on next and following boots.

Parameters
[in] Profile Number of profile to be used
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | Wrong response
EFI_NOT_READY | Heci device hasn't ready yet
EFI_SUCCESS | Command succeeded

◆ HeciSetInvocationCode()

EFI_STATUS HeciSetInvocationCode ( IN UINT32 InvocationCode )

Set invocation codes in Firmware.

Parameters
[in] InvocationCode Bitmask of invocation codes to be set by Firmware.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetManufacturingMeResetAndHalt()

EFI_STATUS HeciSetManufacturingMeResetAndHalt ( VOID )

Send Set Manufacturing Me Reset and Halt Request to ME.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetMeasuredBootState()

EFI_STATUS HeciSetMeasuredBootState ( IN UINT8 SetMeasuredBootState )

Send Set Measured Boot State to Enable or Disable CSME Measurement.

Parameters
[in] SetMeasuredBootState Set Measured boot state to Enable/Disable CSME Extended Measured boot
Return values
EFI_UNSUPPORTED | Current CSME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetMeDisableMsg()

EFI_STATUS HeciSetMeDisableMsg ( VOID )

This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to disable the ME State.

The firmware allows a single update once it receives the disable command Once firmware receives this message, the firmware will work in "Soft Temporary Disable" mode (HFS[19:16] = 3) after a global reset. Note, this message is not allowed when AT firmware is enrolled/configured.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetMeEnableMsg()

EFI_STATUS HeciSetMeEnableMsg ( VOID )

This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host wants to enable the ME State.

The firmware allows a single update once it receives the enable command. Once firmware receives this message, the firmware will be in normal mode after a global reset.

Return values
EFI_SUCCESS | ME enabled message sent
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout or transition failed within allowed time limit

◆ HeciSetMoffOverrideState()

EFI_STATUS HeciSetMoffOverrideState ( IN UINT32 MoffOverrideState )

Set Moff Override State.

Parameters
[in] SouthClinkState New Override Capability State for M3 to Moff Transitions
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetSouthClinkState()

EFI_STATUS HeciSetSouthClinkState ( IN UINT32 SouthClinkState )

Set South Clink State.

Parameters
[in] SouthClinkState New South Clink State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetUnconfigOnRtcClearDisableMsg()

EFI_STATUS HeciSetUnconfigOnRtcClearDisableMsg ( IN UINT32 RuleData )

This message is sent by the BIOS when it wants to set ME Unconfig on RTC Clear Disable state.

Parameters
[in] RuleData 1 - Disable Unconfig on RTC clear 0 - Enable Unconfig on RTC clear
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function or EOP was sent
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetUpidFeatureState()

EFI_STATUS HeciSetUpidFeatureState | ( | IN UINT32 | UpidFeature,
 |  | IN UINT8 | UpidFeatureState
 | ) |  |

This message is sent by the BIOS to set given UPID feature state in CSME.

Parameters
[in] | UpidFeature | UPID feature
[in] | UpidFeatureState | New UPID feature state
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetUpidOsControlState()

EFI_STATUS HeciSetUpidOsControlState | ( | IN UINT32 | UpidFeature,
 |  | IN UINT8 | UpidFeatureOsControlState
 | ) |  |

This message is sent by the BIOS to set if given UPID feature state can be modified by the OS.

Parameters
[in] | UpidFeature | UPID feature
[in] | UpidFeatureOsControlState | Determines if OS can modify the feature state
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciSetUserCapabilitiesState()

EFI_STATUS HeciSetUserCapabilitiesState ( IN MEFWCAPS_SKU RuleData )

Send Set User Capabilities State Request to ME.

Parameters
[in] MEFWCAPS_SKU User Capabilities State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciUnconfigWithouPwd()

EFI_STATUS HeciUnconfigWithouPwd ( VOID )

Unconfigure ME without password.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciUpdateUpidOemPlatformId()

EFI_STATUS HeciUpdateUpidOemPlatformId | ( | IN UINT32 | OemPlatformIdType,
 |  | IN UINT8 * | OemPlatformId,
 |  | IN UINT8 | ManufacturingType
 | ) |  |

This message is sent by the BIOS to update the OEM Platform Id.

Parameters
[in] | OemPlatformIdType | Determines format of the OemPlatformId field
[in] | OemPlatformId | OEM Platform Id to be set, up to 32 bytes
[in] | ManufacturingType | Update reason
Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ HeciValidateMebxPassword()

EFI_STATUS HeciValidateMebxPassword | ( | IN UINT8 | PasswordSize,
 |  | IN UINT8 * | Password,
 |  | OUT BOOLEAN * | MaxRetries
 | ) |  |

This function uses the User entered password to login into FW.

Parameters
[in] | PasswordSize | Size of the user entered password
[in] | Password | Buffer holding user enetered password
[out] | MaxRetries | Informs if maximum number of login retries have been reached
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Null buffer
EFI_DEVICE_ERROR | Command failed

◆ IsCiraAvailable()

BOOLEAN IsCiraAvailable ( VOID )

Return information if Client Initiated Remote Access (CIRA) is available.

Return values
TRUE | CIRA is available
FALSE | CIRA isn't available or cannot get infomation

◆ IsExtendedMeasuredBootEnabled()

BOOLEAN IsExtendedMeasuredBootEnabled ( VOID )

Check if Extended CSME Measured Boot is enabled from BIOS side.

Return values
FALSE | Extend CSME Measured Boot is disabled.
TRUE | Extend CSME Measured Boot is enabled.

◆ MeCoreBiosDoneEnabled()

BOOLEAN MeCoreBiosDoneEnabled ( VOID )

Check if Core Bios Done Message is enabled in setup options.

Return values
FALSE | Core Bios Done is disabled.
TRUE | Core Bios Done is enabled.

◆ MeEndOfPostEnabled()

BOOLEAN MeEndOfPostEnabled ( VOID )

Check if End of Post Message is enabled in setup options.

Return values
FALSE | EndOfPost is disabled.
TRUE | EndOfPost is enabled.

◆ MeFwDowngradeSupported()

BOOLEAN MeFwDowngradeSupported ( VOID )

Check if MeFwDowngrade is enabled in setup options.

Return values
FALSE | MeFwDowngrade is disabled.
TRUE | MeFwDowngrade is enabled.

◆ MeHeci2Enabled()

BOOLEAN MeHeci2Enabled ( VOID )

Check if HECI2 should be removed from PCI space or not.

Return values
FALSE | HECI2 should be Disabled and removed from PCI space
TRUE | HECI2 should be enabled and not removed from PCI space

◆ MeHeciD0I3Enabled()

BOOLEAN MeHeciD0I3Enabled ( VOID )

Read the ME policy to see if D0I3 for HECI devices are enabled.

Return values
TRUE | D0I3 for HECI devices are enabled
FALSE | D0I3 for HECI devices are disabled

◆ MeHeciFullTrace()

BOOLEAN MeHeciFullTrace ( VOID )

Read the ME policy to see if Heci Full Trace are enabled.

Return values
TRUE | HECI full trace in the log is enabled
FALSE | HECI full trace in the log is disabled

◆ MeHeciMessageCheckEnabled()

BOOLEAN MeHeciMessageCheckEnabled ( VOID )

Read the ME policy to see if HECI message check is enabled for Bios Boot Path.

Return values
TRUE | HECI message check is enabled
FALSE | HECI message check is disabled

◆ MeHeciTimeoutsEnabled()

BOOLEAN MeHeciTimeoutsEnabled ( VOID )

Read the ME policy to see if HECI timeouts are enabled.

Return values
FALSE | HECI timeouts is disabled.
TRUE | HECI timeouts is enabled.

◆ MeIsAfterEndOfPost()

BOOLEAN MeIsAfterEndOfPost ( VOID )

Checks if EndOfPost event already happened.

Return values
TRUE | End of post already happened
FALSE | End of post did not happen yet

◆ MeReportError()

VOID MeReportError ( IN ME_ERROR_MSG_ID MsgId )

Show Me Error message.

This is used to support display error message on the screen for localization description

Parameters
[in] MsgId Me error message ID for displaying on screen message
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeMeLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for functions to get Intel ME information
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_ME_LIB_H_
36 #define _DXE_ME_LIB_H_
37
38 #include <Protocol/HeciProtocol.h>
39 #include <Protocol/PlatformMeHook.h>
40 #include <Protocol/MePolicy.h>
41 #include <CoreBiosMsg.h>
42 #include <BupMsgs.h>
43 #include <IshMsgs.h>
44 #include <MeiBusMsg.h>
45 #include <MkhiMsgs.h>
46 #include <IccMsgs.h>
47 #include <UpidMsgs.h>
48 #include <PsrMsgs.h>
49
50 #define MAX_ASSET_TABLE_ALLOCATED_SIZE 0x3000
51 #define HWA_TABLE_PUSH_CMD 0
52
53 #pragma pack(push, 1)
54
55 ///
56 /// Definitions for Hardware Asset Header
57 ///
58 typedef union {
59 UINT32 Data;
60 struct {
61 UINT32 MessageLength : 16;
62 UINT32 Command : 4; ///< only supported command would be HWA_TABLE_PUSH_CMD =0;
63 UINT32 PciFruTablePresent : 1;
64 UINT32 MediaTablePresent : 1;
65 UINT32 SmbiosTablePresent : 1;
66 UINT32 AsfTablePresent : 1;
67 UINT32 Reserved : 8;
68 } Fields;
69 } HWA_MESSAGE_HEADER;
70
71 ///
72 /// Hardware Asset Table Index
73 ///
74 typedef enum {
75 HWA_TABLE_TYPE_INDEX_FRU_DEVICE = 0,
76 HWA_TABLE_TYPE_INDEX_MEDIA_DEVICE,
77 HWA_TABLE_TYPE_INDEX_SMBIOS,
78 HWA_TABLE_TYPE_INDEX_ASF,
79 HWA_TABLE_TYPE_INDEX_MAX
80 } HWA_TABLE_TYPE_INDEX;
81
82 typedef struct {
83 UINT16 Offset;
84 UINT16 Length;
85 } SINGLE_TABLE_POSITION;
86
87 typedef struct {
88 SINGLE_TABLE_POSITION Table[HWA_TABLE_TYPE_INDEX_MAX];
89 UINT8 TableData[0];
90 } HWA_TABLE;
91
92 ///
93 /// Asset Update Table Message
94 ///
95 typedef struct {
96 HWA_MESSAGE_HEADER Header;
97 HWA_TABLE Data;
98 } HWA_PUSH_TABLES_MSG;
99
100 #pragma pack(pop)
101
102 //
103 // FW Feature Shipment Time State Override bitmasks definitions
104 //
105 #define CLEAR_FEATURES_BITMASK 0x00000000
106 #define AMT_BITMASK BIT2
107 #define ISH_BITMASK BIT10
108 #define PTT_BITMASK BIT29
109
110 //
111 // Prototype for HECI message DXE phase
112 //
113
114 //
115 // ME Client - HBM
116 //
117
118 /**
119 Checks if CSME supports HBM protocol version 2.2.
120
121 @param[in] HeciDev HECI device number
122
123 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
124 @retval EFI_SUCCESS Command succeeded
125 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
126 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
127 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
128 @retval EFI_ABORTED Wrong response was received
129 @retval EFI_INCOMPATIBLE_VERSION CSME does not support protocol version required by BIOS
130 **/
131 EFI_STATUS
132 HbmHostVersion (
133 IN HECI_DEVICE HeciDev
134 );
135
136 /**
137 Instructs CSME to stop all communication on given Heci device
138
139 @param[in] HeciDev HECI device number
140
141 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
142 @retval EFI_SUCCESS Command succeeded
143 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
144 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
145 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
146 **/
147 EFI_STATUS
148 HbmHostStop (
149 IN HECI_DEVICE HeciDev
150 );
151
152 /**
153 Checks at which CSME addresses there are any clients
154
155 @param[in] HeciDevice HECI device number
156 @param[out] ValidAddresses Mask of addresses that have a client behind them
157
158 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
159 @retval EFI_SUCCESS Command succeeded
160 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
161 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
162 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
163 @retval EFI_ABORTED Wrong response was received
164 **/
165 EFI_STATUS
166 HbmHostEnumRequest (
167 IN HECI_DEVICE HeciDevice,
168 OUT UINT8 *ValidAddresses
169 );
170
171 /**
172 Retrieves GUID of a single CSME client
173
174 @param[in] HeciDevice HECI device number
175 @param[in] ClientAddr Address of the CSME client
176 @param[out] ProtocolGuid GUID of the client
177
178 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
179 @retval EFI_SUCCESS Command succeeded
180 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
181 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
182 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
183 @retval EFI_ABORTED Wrong response was received
184 **/
185 EFI_STATUS
186 HbmGetClientProperties (
187 IN HECI_DEVICE HeciDevice,
188 IN UINT8 ClientAddr,
189 OUT EFI_GUID* ProtocolGuid
190 );
191
192 /**
193 Creates a connection between given host and CSME addresses
194
195 @param[in] HeciDev HECI device number
196 @param[in] MeAddress Address of the CSME client
197 @param[in] HostAddress Address of the Host client
198
199 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
200 @retval EFI_SUCCESS Command succeeded
201 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
202 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
203 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
204 @retval EFI_ABORTED Wrong response was received
205 **/
206 EFI_STATUS
207 HbmHostClientConnect (
208 IN HECI_DEVICE HeciDev,
209 IN UINT8 MeAddress,
210 IN UINT8 HostAddress
211 );
212
213 /**
214 Disconnects an established connection between a Host and CSME clients
215
216 @param[in] HeciDev HECI device number
217 @param[in] HostAddr Host Address of the connection
218 @param[in] MeAddr CSME Address of the connection
219
220 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
221 @retval EFI_SUCCESS Command succeeded
222 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
223 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
224 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
225 @retval EFI_ABORTED Wrong response was received
226 **/
227 EFI_STATUS
228 HbmClientDisconnect (
229 IN HECI_DEVICE HeciDev,
230 IN UINT8 HostAddr,
231 IN UINT8 MeAddr
232 );
233
234 /**
235 Sends a flow control token from BIOS to CSME that allows CSME to send one message over connection
236 identified by host:Me address pair
237
238 @param[in] HeciDev HECI device number
239 @param[in] HostAddr Address of the Host client
240 @param[in] MeAddr Address of the CSME client
241
242 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
243 @retval EFI_SUCCESS Command succeeded
244 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
245 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
246 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
247 **/
248 EFI_STATUS
249 HbmSendFlowControlToken (
250 IN HECI_DEVICE HeciDev,
251 IN UINT8 HostAddr,
252 IN UINT8 MeAddr
253 );
254
255 /**
256 Attempts to receive a flow control token from CSME. This token allows BIOS to send one message over commection
257 identified by Host:Me address pair
258
259 @param[in] HeciDev HECI device number
260 @param[in] HostAddr Address of the Host client
261 @param[in] MeAddr Address of the CSME client
262
263 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
264 @retval EFI_SUCCESS Command succeeded
265 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
266 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
267 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
268 **/
269 EFI_STATUS
270 HbmGetFlowControlToken (
271 IN HECI_DEVICE HeciDev,
272 IN UINT8 HostAddr,
273 IN UINT8 MeAddr
274 );
275
276 /**
277 Informs about Host and CSME capabilities over HBM
278
279 @param[in] HeciDev HECI device number
280 @param[in, out] HbmCaps On input: Host HBM capabilities
281 On output: CSME HBM capabilities
282
283 @retval EFI_SUCCESS Command succeeded
284 @retval EFI_INVALID_PARAMETER NULL parameter
285 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
286 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
287 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
288 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
289 @retval EFI_ABORTED Wrong response was received
290 **/
291 EFI_STATUS
292 HbmCapabilitiesRequest (
293 IN HECI_DEVICE HeciDev,
294 IN OUT HBM_CAPS_DATA *HbmCaps
295 );
296
297 /**
298 Requests mapping CSME HECI client MMIO to the given physcial memory addresses.
299
300 @param[in] HeciDev HECI device number
301 @param[in] ClientDmaBufferId Identifies Client Id to which physical address should be mapped
302 @param[in] AddressLow Physical address for DMA buffer (Low DWORD)
303 @param[in] AddressHigh Physical address for DMA buffer (High DWORD)
304 @param[in] Size Size of the physical memory to be mapped
305
306 @retval EFI_SUCCESS Command succeeded
307 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
308 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
309 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
310 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
311 @retval EFI_ABORTED Wrong response was received
312 **/
313 EFI_STATUS
314 HbmMapRequest (
315 IN HECI_DEVICE HeciDev,
316 IN UINT8 ClientDmaBufferId,
317 IN UINT32 AddressLow,
318 IN UINT32 AddressHigh,
319 IN UINT32 Size
320 );
321
322 /**
323 Requests unmapping CSME HECI client MMIO from the given physcial memory addresses.
324
325 @param[in] HeciDev HECI device number
326 @param[in] ClientDmaBufferId Identifies Client Id from which physical address should be unampped
327
328 @retval EFI_SUCCESS Command succeeded
329 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
330 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
331 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
332 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
333 @retval EFI_ABORTED Wrong response was received
334 **/
335 EFI_STATUS
336 HbmUnmapRequest (
337 IN HECI_DEVICE HeciDev,
338 IN UINT8 ClientDmaBufferId
339 );
340
341 //
342 // ME Client - ISH Service
343 //
344
345 /**
346 This message is sent by the BIOS when it wants to send
347 PDT Unlock Message to ISH.
348
349 @param[in] FileName File name of bios2ish file.
350
351 @retval EFI_SUCCESS Command succeeded
352 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function or EOP was sent
353 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
354 @retval EFI_BAD_BUFFER_SIZE The size of FileName is larger than maximum allowed value
355 **/
356 EFI_STATUS
357 HeciPdtUnlockMsg (
358 IN CONST CHAR8* FileName
359 );
360
361 /**
362 This message is sent by the BIOS when it wants to send
363 PDT Update Message
364
365 @param[in] FileName File name of bios2ish file.
366 @param[in] PdtFileBuffer Contains ISH PDT file
367 @param[in] PdtBufferSize Size of PDT file
368
369 @retval EFI_SUCCESS Command succeeded
370 @retval EFI_INVALID_PARAMETER Invalid input parameter
371 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function or EOP was sent
372 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
373 @retval EFI_ABBORTED Unable to allocate memory
374 @retval EFI_BAD_BUFFER_SIZE The size of FileName is larger than maximum allowed value
375 **/
376 EFI_STATUS
377 HeciPdtUpdateMsg (
378 IN CONST CHAR8* FileName,
379 IN UINT8 *PdtFileBuffer,
380 IN UINT16 PdtBufferSize
381 );
382
383 //
384 // ME Client - PSR
385 //
386
387 /**
388 Get Platform Service Record from CSME
389
390 @param[in, out] PsrData Pointer to PSR data struct
391
392 @retval EFI_SUCCESS Command succeeded
393 @retval EFI_UNSUPPORTED Current CSME mode doesn't support this function
394 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
395 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
396 @retval EFI_ABORTED Cannot allocate memory
397 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
398 **/
399 EFI_STATUS
400 HeciGetPsrRecord (
401 IN OUT PSR_DATA *PsrData
402 );
403
404 /**
405 Inform CSME of Chassis Intrusion Detected Event
406
407 @retval EFI_SUCCESS Command succeeded
408 @retval EFI_UNSUPPORTED Current CSME mode doesn't support this function
409 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
410 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
411 **/
412 EFI_STATUS
413 HeciSendChassisIntrDetEvent (
414 VOID
415 );
416
417
418 //
419 // ME Client - MKHI
420 //
421
422 //
423 // MKHI_CBM_GROUP_ID = 0x00
424 //
425
426 /**
427 Send Core BIOS Reset Request Message through HECI to reset the system.
428
429 @param[in] ResetOrigin Reset source
430 @param[in] ResetType Global or Host reset
431
432 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
433 @retval EFI_SUCCESS Command succeeded
434 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
435 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
436 **/
437 EFI_STATUS
438 HeciSendCbmResetRequest (
439 IN UINT8 ResetOrigin,
440 IN UINT8 ResetType
441 );
442
443 /**
444 Retrieve invocation codes from Firmware.
445
446 @param[out] InvocationCode Bitmask of invocation codes set by Firmware.
447
448 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
449 @retval EFI_SUCCESS Command succeeded
450 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
451 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
452 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
453 **/
454 EFI_STATUS
455 HeciGetInvocationCode (
456 OUT UINT32 *InvocationCode
457 );
458
459 /**
460 Set invocation codes in Firmware.
461
462 @param[in] InvocationCode Bitmask of invocation codes to be set by Firmware.
463
464 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
465 @retval EFI_SUCCESS Command succeeded
466 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
467 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
468 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
469 **/
470 EFI_STATUS
471 HeciSetInvocationCode (
472 IN UINT32 InvocationCode
473 );
474
475 /**
476 Clear invocation codes in Firmware.
477
478 @param[in] InvocationCode Bitmask of invocation codes to be cleared by Firmware.
479
480 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
481 @retval EFI_SUCCESS Command succeeded
482 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
483 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
484 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
485 **/
486 EFI_STATUS
487 HeciClearInvocationCode (
488 IN UINT32 InvocationCode
489 );
490
491 //
492 // MKHI_PWD_GROUP_ID = 0x02
493 //
494
495 /**
496 This function logs in with current password and updates to new password.
497
498 @param[in] OldPwdSize Size of the old password
499 @param[in] OldPwd Buffer holding old password
500 @param[in] NewPwdSize Size of the new password
501 @param[in] NewPwd Buffer holding new password
502
503 @retval ME_PWD_STATUS Password management Status Code:
504 @see ME_PWD_STATUS
505 **/
506 ME_PWD_STATUS
507 HeciModifyMebxPassword (
508 IN UINT8 OldPwdSize,
509 IN UINT8 *OldPwd,
510 IN UINT8 NewPwdSize,
511 IN UINT8 *NewPwd
512 );
513
514 /**
515 This function uses the User entered password to login into FW.
516
517 @param[in] PasswordSize Size of the user entered password
518 @param[in] Password Buffer holding user enetered password
519 @param[out] MaxRetries Informs if maximum number of login retries have been reached
520
521 @retval EFI_SUCCESS Command succeeded
522 @retval EFI_INVALID_PARAMETER Null buffer
523 @retval EFI_DEVICE_ERROR Command failed
524 **/
525 EFI_STATUS
526 HeciValidateMebxPassword (
527 IN UINT8 PasswordSize,
528 IN UINT8 *Password,
529 OUT BOOLEAN *MaxRetries
530 );
531
532 /**
533 Checks if password was modified.
534
535 @param[out] Modified Password modification status
536
537 @retval EFI_SUCCESS Command succeeded
538 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
539 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
540 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
541 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
542 @retval EFI_INVALID_PARAMETER Parameter invalid
543 **/
544 EFI_STATUS
545 HeciIsMebxPasswordModified (
546 OUT UINT32 *Modified
547 );
548
549 //
550 // MKHI_FWCAPS_GROUP_ID = 0x03
551 //
552
553 /**
554 Send Get Rule Data Request to CSME
555
556 @param[in] RuleId Identifies the rule which data is requested.
557 @param[out] *RuleData Pointer to requested rule data.
558
559 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
560 @retval EFI_SUCCESS Command succeeded
561 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
562 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
563 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
564 @retval EFI_INVALID_PARAMETER Parameter invalid.
565 **/
566 EFI_STATUS
567 HeciFwCapsGetRuleData (
568 IN UINT32 RuleId,
569 OUT UINT32 *RuleData
570 );
571
572 /**
573 Send Get Firmware SKU Request to ME
574
575 @param[out] *FwCapsSku Firmware Capabilities
576
577 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
578 @retval EFI_SUCCESS Command succeeded
579 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
580 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
581 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
582 **/
583 EFI_STATUS
584 HeciGetFwCapsSkuMsg (
585 OUT MEFWCAPS_SKU *RuleData
586 );
587
588 /**
589 This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot
590 where host wants to query the local firmware update interface status.
591
592 @param[out] RuleData 1 - local firmware update interface enable
593 0 - local firmware update interface disable
594
595 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
596 @retval EFI_SUCCESS Command succeeded
597 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
598 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
599 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
600 **/
601 EFI_STATUS
602 HeciGetFwUpdateState (
603 OUT UINT8 *RuleData
604 );
605
606 /**
607 Send Get User Capabilities State Request to ME.
608
609 @param[out] RuleData User Capabilities State
610
611 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
612 @retval EFI_SUCCESS Command succeeded
613 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
614 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
615 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
616 **/
617 EFI_STATUS
618 HeciGetUserCapabilitiesState (
619 OUT MEFWCAPS_SKU *RuleData
620 );
621
622 /**
623 This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP)
624 on the boot where host wants to get Ibex Peak platform type.
625 One of usages is to utilize this command to determine if the platform runs in
626 Consumer or Corporate SKU size firmware.
627
628 @param[out] RuleData PlatformBrand,
629 IntelMeFwImageType,
630 SuperSku,
631 PlatformTargetUsageType
632
633 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
634 @retval EFI_SUCCESS Command succeeded
635 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
636 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
637 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
638 **/
639 EFI_STATUS
640 HeciGetPlatformTypeMsg (
641 OUT PLATFORM_TYPE_RULE_DATA *RuleData
642 );
643
644 /**
645 The Get FW Feature Status message is based on MKHI interface.
646 This command is used by BIOS/IntelR MEBX to get firmware runtime status.
647 The GET FW RUNTIME STATUS message doesn't need to check the HFS.FWInitComplete
648 value before sending the command.
649 It means this message can be sent regardless of HFS.FWInitComplete.
650
651 @param[out] *RuleData MEFWCAPS_SKU message
652
653 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
654 @retval EFI_SUCCESS Command succeeded
655 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
656 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
657 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
658 **/
659 EFI_STATUS
660 HeciGetFwFeatureStateMsg (
661 OUT MEFWCAPS_SKU *RuleData
662 );
663
664 /**
665 Get value of South Clink State from ME.
666
667 @param[out] SouthClinkState South Clink State
668
669 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
670 @retval EFI_SUCCESS Command succeeded
671 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
672 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
673 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
674 **/
675 EFI_STATUS
676 HeciGetSouthClinkState (
677 OUT UINT32 *SouthClinkState
678 );
679
680 /**
681 Get available ME features.
682
683 @param[out] FwFeatures Mask of available ME Features
684
685 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
686 @retval EFI_SUCCESS Command succeeded
687 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
688 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
689 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
690 **/
691 EFI_STATUS
692 HeciGetFwAvailableFeatures (
693 OUT UINT32 *FwFeatures
694 );
695
696 /**
697 Get Override Capability State for M3 to Moff Transitions.
698
699 @param[out] MOffOverrideState ME MOFF Override State
700
701 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
702 @retval EFI_SUCCESS Command succeeded
703 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
704 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
705 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
706 **/
707 EFI_STATUS
708 HeciGetMoffOverrideState (
709 OUT UINT32 *MOffOverrideState
710 );
711
712 /**
713 The firmware will respond to GET OEM TAG message even after the End of Post (EOP).
714
715 @param[out] RuleData Default is zero. Tool can create the OEM specific OEM TAG data.
716
717 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
718 @retval EFI_SUCCESS Command succeeded
719 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
720 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
721 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
722 **/
723 EFI_STATUS
724 HeciGetOemTagMsg (
725 OUT UINT32 *RuleData
726 );
727
728 /**
729 This message is sent by the BIOS when it wants to query
730 ME Unconfig on RTC Clear Disable state.
731
732 @param[out] RuleData 1 - Unconfig on RTC clear is disabled
733 0 - Unconfig on RTC clear is not disabled
734
735 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
736 @retval EFI_SUCCESS Command succeeded
737 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
738 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
739 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
740 **/
741 EFI_STATUS
742 HeciGetUnconfigOnRtcClearDisableMsg (
743 OUT UINT32 *RuleData
744 );
745
746 /**
747 This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state.
748 The firmware will respond to AMT BIOS SYNC INFO message even after the End of Post.
749
750 @param[out] RuleData @see AMT_BIOS_SYNC_INFO
751
752 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
753 @retval EFI_SUCCESS Command succeeded
754 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
755 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
756 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
757 **/
758 EFI_STATUS
759 HeciGetAmtBiosSyncInfo (
760 OUT AMT_BIOS_SYNC_INFO *RuleData
761 );
762
763 /**
764 Get User Consent requirement.
765
766 @param[out] IsUserConsentRequired User consent requirement:
767 TRUE - User Consent required
768 FALSE - User Consent not required
769
770 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
771 @retval EFI_SUCCESS Command succeeded
772 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
773 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
774 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
775 **/
776 EFI_STATUS
777 HeciGetIsUserConsentRequired (
778 OUT BOOLEAN *IsUserConsentRequired
779 );
780
781 /**
782 Return information if Client Initiated Remote Access (CIRA) is available.
783
784 @retval TRUE CIRA is available
785 @retval FALSE CIRA isn't available or cannot get infomation
786 **/
787 BOOLEAN
788 IsCiraAvailable (
789 VOID
790 );
791
792 /**
793 Send Set Rule Data Request to CSME
794
795 @param[in] RuleId Identifies the rule which data needs to be changed.
796 @param[in] RuleDataLength Rule Data Length.
797 @param[in] RuleData Pointer to new rule data.
798
799 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
800 @retval EFI_SUCCESS Command succeeded
801 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
802 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
803 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
804 **/
805 EFI_STATUS
806 HeciFwCapsSetRuleData (
807 IN UINT32 RuleId,
808 IN UINT8 RuleDataLength,
809 IN UINT32 RuleData
810 );
811
812 /**
813 This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP)
814 on the boot where host wants to disable the ME State. The firmware allows a single
815 update once it receives the disable command Once firmware receives this message,
816 the firmware will work in "Soft Temporary Disable" mode (HFS[19:16] = 3) after a
817 global reset. Note, this message is not allowed when AT firmware is enrolled/configured.
818
819 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
820 @retval EFI_SUCCESS Command succeeded
821 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
822 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
823 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
824 **/
825 EFI_STATUS
826 HeciSetMeDisableMsg (
827 VOID
828 );
829
830 /**
831 This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot
832 where host wants to enable or disable the local firmware update interface.
833 The firmware allows a single update once it receives the enable command
834
835 @param[in] RuleData 1 - local firmware update interface enable
836 0 - local firmware update interface disable
837
838 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
839 @retval EFI_SUCCESS Command succeeded
840 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
841 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
842 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
843 **/
844 EFI_STATUS
845 HeciSetFwUpdateState (
846 IN UINT8 RuleData
847 );
848
849 /**
850 Send Set User Capabilities State Request to ME.
851
852 @param[in] MEFWCAPS_SKU User Capabilities State
853
854 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
855 @retval EFI_SUCCESS Command succeeded
856 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
857 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
858 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
859 **/
860 EFI_STATUS
861 HeciSetUserCapabilitiesState (
862 IN MEFWCAPS_SKU RuleData
863 );
864
865 /**
866 Set FW Enabled Features.
867
868 @param[in] NewFeatures New Fw Enabled Features
869 @param[in] FeaturesMask Bitmask with new Fw Enabled Features
870
871 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
872 @retval EFI_SUCCESS Command succeeded
873 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
874 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
875 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
876 **/
877 EFI_STATUS
878 HeciSetFwEnabledFeatures (
879 IN UINT32 NewFeatures,
880 IN UINT32 FeaturesMask
881 );
882
883 /**
884 Set South Clink State.
885
886 @param[in] SouthClinkState New South Clink State
887
888 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
889 @retval EFI_SUCCESS Command succeeded
890 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
891 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
892 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
893 **/
894 EFI_STATUS
895 HeciSetSouthClinkState (
896 IN UINT32 SouthClinkState
897 );
898
899 /**
900 Set Moff Override State.
901
902 @param[in] SouthClinkState New Override Capability State for M3 to Moff Transitions
903
904 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
905 @retval EFI_SUCCESS Command succeeded
906 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
907 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
908 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
909 **/
910 EFI_STATUS
911 HeciSetMoffOverrideState (
912 IN UINT32 MoffOverrideState
913 );
914
915 /**
916 This message is sent by the BIOS to inform ME FW whether or not to take the
917 TPM 1.2 Deactivate flow
918
919 @param[in] TpmDeactivate 0 - ME FW should not take the deactivate flow.
920 1 - ME FW should take the deactivate flow.
921
922 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
923 @retval EFI_SUCCESS Command succeeded
924 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
925 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
926 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
927 **/
928 EFI_STATUS
929 HeciSetAcmTpmData (
930 IN UINT8 TpmDeactivate
931 );
932
933 /**
934 This message is sent by the BIOS when it wants to set
935 ME Unconfig on RTC Clear Disable state.
936
937 @param[in] RuleData 1 - Disable Unconfig on RTC clear
938 0 - Enable Unconfig on RTC clear
939
940 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function or EOP was sent
941 @retval EFI_SUCCESS Command succeeded
942 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
943 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
944 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
945 **/
946 EFI_STATUS
947 HeciSetUnconfigOnRtcClearDisableMsg (
948 IN UINT32 RuleData
949 );
950
951
952 //
953 // MKHI_HMRFPO_GROUP_ID = 0x05
954 //
955
956 /**
957 Sends a message to ME to unlock a specified SPI Flash region for writing and receiving a response message.
958 It is recommended that HMRFPO_ENABLE MEI message needs to be sent after all OPROMs finish their initialization.
959
960 @param[out] Result HMRFPO_ENABLE response
961
962 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
963 @retval EFI_SUCCESS Command succeeded
964 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
965 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
966 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
967 **/
968 EFI_STATUS
969 HeciHmrfpoEnable (
970 OUT UINT8 *Result
971 );
972
973 /**
974 Sends a message to ME to lock a specified SPI Flash region for writing and receiving a response message.
975
976 @param[out] Result Status report
977
978 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
979 @retval EFI_SUCCESS Command succeeded
980 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
981 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
982 @retval EFI_NOT_READY HECI Device hasn't ready yet
983 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
984 **/
985 EFI_STATUS
986 HeciHmrfpoLock (
987 OUT UINT8 *Result
988 );
989
990 /**
991 System BIOS sends this message to get status for HMRFPO_LOCK message.
992
993 @param[out] Result HMRFPO_GET_STATUS response
994
995 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
996 @retval EFI_SUCCESS Command succeeded
997 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
998 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
999 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1000 **/
1001 EFI_STATUS
1002 HeciHmrfpoGetStatus (
1003 OUT UINT8 *Result
1004 );
1005
1006 /**
1007 This message is sent by the BIOS to retrieve file stored in ME firmware NVM.
1008
1009 @param[in] FileId Id number of file to read
1010 @param[in] Offset File offset
1011 @param[in, out] DataSize On input - size of data to read, on output - size of read data
1012 @param[in] Flags Flags
1013 @param[out] *Buffer Pointer to the data buffer
1014
1015 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1016 @retval EFI_SUCCESS Command succeeded
1017 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1018 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1019 @retval EFI_ABORTED Cannot allocate memory
1020 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1021 **/
1022 EFI_STATUS
1023 HeciReadFileExMsg (
1024 IN UINT32 FileId,
1025 IN UINT32 Offset,
1026 IN OUT UINT32 *DataSize,
1027 IN UINT8 Flags,
1028 OUT UINT8 *DataBuffer
1029 );
1030
1031 /**
1032 Read Delayed Authentication Mode from ME NVM
1033
1034 @param[out] *DamState Delayed Authentication Mode State
1035
1036 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1037 @retval EFI_SUCCESS Command succeeded
1038 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1039 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1040 @retval EFI_ABORTED Cannot allocate memory
1041 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1042 **/
1043 EFI_STATUS
1044 HeciGetDamState (
1045 OUT UINT8 *DamState
1046 );
1047
1048 /**
1049 Read UPID Platform Id feature supported state from ME NVM
1050
1051 @param[out] PlatIdSupported Platform Id feature supported State
1052
1053 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1054 @retval EFI_SUCCESS Command succeeded
1055 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1056 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1057 @retval EFI_ABORTED Cannot allocate memory
1058 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1059 **/
1060 EFI_STATUS
1061 HeciGetPlatIdSupportedState (
1062 OUT UINT8 *PlatIdSupported
1063 );
1064
1065 /**
1066 This message is sent by the BIOS to save data in a file stored in ME firmware NVM.
1067
1068 @param[in] FileId Id Number of file to write
1069 @param[in] Offset File offset
1070 @param[in] DataSize Size of data to write
1071 @param[in] Flags Flags
1072 @param[in] *DataBuffer Pointer to the data buffer
1073
1074 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1075 @retval EFI_SUCCESS Command succeeded
1076 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1077 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1078 @retval EFI_ABORTED Cannot allocate memory
1079 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1080 **/
1081 EFI_STATUS
1082 HeciSetFileExMsg (
1083 IN UINT32 FileId,
1084 IN UINT32 Offset,
1085 IN UINT32 DataSize,
1086 IN UINT8 Flags,
1087 IN UINT8 *DataBuffer
1088 );
1089
1090 /**
1091 Set Delayed Authentication Mode in ME NVM
1092
1093 @param[in] DamState New Delayed Authentication Mode State:
1094 0 - DAM Disable
1095 1 - DAM Enable
1096
1097 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1098 @retval EFI_SUCCESS Command succeeded
1099 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1100 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1101 @retval EFI_ABORTED Cannot allocate memory
1102 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1103 **/
1104 EFI_STATUS
1105 HeciSetDamState (
1106 IN UINT8 DamState
1107 );
1108
1109 /**
1110 This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to
1111 commit previously set files.
1112
1113 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1114 @retval EFI_SUCCESS Command succeeded
1115 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1116 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1117 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1118 **/
1119 EFI_STATUS
1120 HeciCommitFilesMsg (
1121 VOID
1122 );
1123
1124 //
1125 // MKHI_MCA_GROUP_ID = 0x0A
1126 //
1127
1128 /**
1129 This message is sent by the BIOS to notify ME firmware that the BIOS is starting
1130 to run 3rd party code.
1131
1132 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function or EOP was sent
1133 @retval EFI_SUCCESS Command succeeded
1134 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1135 **/
1136 EFI_STATUS
1137 HeciCoreBiosDoneMsg (
1138 VOID
1139 );
1140
1141 /**
1142 This message is sent by the BIOS to retrieve RPMC status data from CSME.
1143
1144 @param[out] RpStatus RPMC status data
1145
1146 @retval EFI_SUCCESS Command succeeded
1147 @retval EFI_NOT_FOUND Couldn't locate HeciPpi
1148 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1149 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1150 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
1151 @retval EFI_INVALID_PARAMETER Parameter invalid
1152 **/
1153 EFI_STATUS
1154 HeciGetRpmcStatus (
1155 OUT RP_STATUS_2 *RpStatus
1156 );
1157
1158 /**
1159 This command indicates to the FW that it shall commit ARBSVN to fuse.
1160
1161 @retval EFI_SUCCESS Command succeeded
1162 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1163 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1164 **/
1165 EFI_STATUS
1166 HeciArbSvnCommitMsg (
1167 VOID
1168 );
1169
1170 /**
1171 The command retrieves anti-replay SVN information.
1172 Caller can set Entries as 0 to get the correct number of entries CSME contains.
1173
1174 @param[in, out] Entries On input, it is the number of entries caller expects.
1175 On output, it indicates the number of entries CSME contains.
1176 @param[in, out] ArbSvnInfo Anti-Rollback SVN Information
1177
1178 @retval EFI_SUCCESS Command succeeded
1179 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1180 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1181 @retval EFI_OUT_OF_RESOURCES Unable to allocate required resources
1182 @retval EFI_BUFFER_TOO_SMALL The Entries is too small for the result
1183 **/
1184 EFI_STATUS
1185 HeciArbSvnGetInfoMsg (
1186 IN OUT UINT32 *Entries,
1187 IN OUT ARB_SVN_INFO_ENTRY *ArbSvnInfo
1188 );
1189
1190 //
1191 // MKHI_DNX_GROUP_ID = 0x0D
1192 //
1193
1194 /**
1195 Send Dnx Request Clear message.
1196
1197 @param[in] Flag Flag indicating the type of clear operation:
1198 0 - cancel DNX Operation
1199 1 - Global reset
1200 2 - CSE reset
1201 3 - Cold reset
1202
1203 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1204 @retval EFI_SUCCESS Command succeeded
1205 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1206 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1207 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1208 **/
1209 EFI_STATUS
1210 HeciDnxReqClear (
1211 IN UINT32 Flag
1212 );
1213
1214 //
1215 // MKHI_GEN_GROUP_ID = 0xF0
1216 //
1217
1218 /**
1219 This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP)
1220 on the boot where host wants to enable the ME State. The firmware allows a single
1221 update once it receives the enable command. Once firmware receives this message,
1222 the firmware will be in normal mode after a global reset.
1223
1224 @retval EFI_SUCCESS ME enabled message sent
1225 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1226 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1227 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1228 @retval EFI_TIMEOUT HECI does not return the buffer before timeout or transition failed
1229 within allowed time limit
1230 **/
1231 EFI_STATUS
1232 HeciSetMeEnableMsg (
1233 VOID
1234 );
1235
1236 /**
1237 Send HMRFPO disable MKHI to CSME.
1238
1239 @retval EFI_SUCCESS Command succeeded
1240 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1241 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1242 **/
1243 EFI_STATUS
1244 HeciHmrfpoDisable (
1245 VOID
1246 );
1247
1248 /**
1249 This function sends a command to CSME to get Log information of Measurements provided in
1250 CSME Extend Registers for BIOS to extend to TPM-PCR registers.
1251
1252 @param[out] EventLogBuffer Pointer to received Event log buffer
1253 @param[in] RemainingBufSize Size of available buffer to collect event log
1254 @param[out] ReceivedLogSize Size of received event log
1255 @param[in, out] LogEntryIndex On input - Index of first / starting log entry in the buffer. On output - Index of last log entry returned
1256 @param[out] RemainingEntries Pointer to Remaining Entries (0 - no more entries in a log; 1 - additional iteration(s) is(are) required)
1257
1258 @retval EFI_SUCCESS Log received successfully
1259 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1260 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1261 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1262 @retval EFI_TIMEOUT HECI does not return the buffer before timeout or transition failed
1263 within allowed time limit
1264 **/
1265 EFI_STATUS
1266 HeciGetErLog (
1267 OUT UINT8 *EventLogBuffer,
1268 IN UINT32 RemainingBufSize,
1269 IN OUT UINT32 *ReceivedLogSize,
1270 IN OUT UINT8 *LogEntryIndex,
1271 OUT UINT8 *RemainingEntries
1272 );
1273
1274 //
1275 // MKHI_GEN_GROUP_ID = 0xFF
1276 //
1277
1278 /**
1279 Get MKHI (Management Engine Kernel Host Interface) Version.
1280
1281 @param[out] MkhiVersion MKHI Version
1282
1283 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1284 @retval EFI_SUCCESS Command succeeded
1285 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1286 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1287 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1288 **/
1289 EFI_STATUS
1290 HeciGetMkhiVersion (
1291 OUT MKHI_VERSION *MkhiVersion
1292 );
1293
1294 /**
1295 Send Get Firmware Version Request to ME
1296
1297 @param[out] *GetFwVersionAckData Return the message of FW version
1298
1299 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1300 @retval EFI_SUCCESS Command succeeded
1301 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1302 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1303 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1304 **/
1305 EFI_STATUS
1306 HeciGetFwVersionMsg (
1307 OUT GET_FW_VER_ACK_DATA *GetFwVersionAckData
1308 );
1309
1310 /**
1311 Send CPU brand class fuse to the CSME (only for corporate SKU).
1312
1313 This message is required for BIOS running on CPUs don't support SID message to obtain CPU information.
1314
1315 @param[in] CpuBrandClass CPU brand class
1316
1317 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1318 @retval EFI_SUCCESS Command succeeded
1319 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1320 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1321 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1322 **/
1323 EFI_STATUS
1324 HeciSendCpuBrandClassFuse (
1325 IN UINT8 CpuBrandClass
1326 );
1327
1328 /**
1329 Get CPU Type Change User Message.
1330
1331 @param[in] CpuTypeChangeInfo CPU Type Change User Message
1332
1333 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1334 @retval EFI_SUCCESS Command succeeded
1335 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1336 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1337 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1338 **/
1339 EFI_STATUS
1340 HeciGetCpuTypeChange (
1341 OUT GEN_GET_CPU_TYPE_CHANGE_DATA *CpuTypeChangeInfo
1342 );
1343
1344 /**
1345 Send CPU Type Change User Response.
1346
1347 @param[in] UserResponse CPU Type Change User Response:
1348 0 - Change Rejected
1349 1 - Change Accepted
1350
1351 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1352 @retval EFI_SUCCESS Command succeeded
1353 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1354 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1355 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1356 **/
1357 EFI_STATUS
1358 HeciSetCpuTypeChangeUserResponse (
1359 IN UINT8 UserResponse
1360 );
1361
1362 /**
1363 Unconfigure ME without password
1364
1365 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1366 @retval EFI_SUCCESS Command succeeded
1367 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1368 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1369 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1370 **/
1371 EFI_STATUS
1372 HeciUnconfigWithouPwd (
1373 VOID
1374 );
1375
1376 /**
1377 Get ME Unconfiguration Status.
1378
1379 @param[out] UnconfigStatus Unconfiguration Status:
1380 0x01 - Unconfiguration in progress
1381 0x02 - No unconfigure w/o password to be processed
1382 0x03 - CSME finished processing unconfigure w/o password
1383 0x80 - Error encountered by CSME during unconfigure w/o password
1384
1385 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1386 @retval EFI_SUCCESS Command succeeded
1387 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1388 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1389 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1390 **/
1391 EFI_STATUS
1392 HeciGetUnconfigureStatus (
1393 OUT UINT8* UnconfigStatus
1394 );
1395
1396 /**
1397 Send Set Manufacturing Me Reset and Halt Request to ME
1398
1399 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1400 @retval EFI_SUCCESS Command succeeded
1401 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1402 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1403 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1404 **/
1405 EFI_STATUS
1406 HeciSetManufacturingMeResetAndHalt (
1407 VOID
1408 );
1409
1410 /**
1411 Sends the MKHI Enable/Disable FW Features.
1412
1413 @param[in] EnableBitMask Bitmask of features to enable
1414 @param[in] DisableBitMask Bitmask of features to disable
1415
1416 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1417 @retval EFI_SUCCESS Command succeeded
1418 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1419 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1420 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1421 @retval EFI_ACCESS_DENIED Command request is rejected
1422 **/
1423 EFI_STATUS
1424 HeciFwFeatureStateOverride (
1425 IN UINT32 EnableBitmask,
1426 IN UINT32 DisableBitmask
1427 );
1428
1429 /**
1430 Send Get Image Firmware Version Request to ME
1431
1432 @param[in] PartitionId Partition ID
1433 @param[out] PartitionIdData Return the version of the Partition ID
1434
1435 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1436 @retval EFI_SUCCESS Command succeeded
1437 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1438 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1439 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1440 **/
1441 EFI_STATUS
1442 HeciGetImageFwVersionMsg (
1443 IN UINT32 PartitionId,
1444 OUT FLASH_PARTITION_DATA *PartitionIdData
1445 );
1446
1447 /**
1448 Send Set FIPS Mode to Enabled or Disabled
1449
1450 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1451 @retval EFI_SUCCESS Command succeeded
1452 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1453 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1454 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1455 **/
1456 EFI_STATUS
1457 HeciSetFipsMode (
1458 IN UINT32 FipsMode
1459 );
1460
1461 /**
1462 Send Get Current FIPS Mode and Crypto Driver version
1463
1464 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1465 @retval EFI_SUCCESS Command succeeded
1466 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1467 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1468 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1469 **/
1470 EFI_STATUS
1471 HeciGetFipsMode (
1472 OUT GET_FIPS_MODE_DATA *GetFipsModeData
1473 );
1474
1475 /**
1476 Send Set Measured Boot State to Enable or Disable CSME Measurement
1477
1478 @param[in] SetMeasuredBootState Set Measured boot state to Enable/Disable CSME Extended Measured boot
1479
1480 @retval EFI_UNSUPPORTED Current CSME mode doesn't support this function
1481 @retval EFI_SUCCESS Command succeeded
1482 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1483 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1484 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1485 **/
1486 EFI_STATUS
1487 HeciSetMeasuredBootState (
1488 IN UINT8 SetMeasuredBootState
1489 );
1490
1491 /**
1492 Send Get Current CSME Measured Boot State
1493
1494 @param[out] GetMeasuredBootState Pointer to get CSME Measured boot status.
1495
1496 @retval EFI_UNSUPPORTED Current (CS)ME mode/version doesn't support this function
1497 @retval EFI_SUCCESS Command succeeded
1498 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1499 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1500 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1501 **/
1502 EFI_STATUS
1503 HeciGetMeasuredBootState (
1504 OUT UINT8 *GetMeasuredBootState
1505 );
1506
1507 //
1508 // ME Client - Integrated Clock Chip (ICC)
1509 //
1510
1511 /**
1512 Retrieves the number of currently used ICC clock profile
1513
1514 @param[out] Profile Number of current ICC clock profile
1515 @param[out] NumProfiles Number of supported motherboard profiles
1516 @param[out] IccSelectAllowed Allow ICC profile changeable
1517 @param[out] ProfileDescriptions Pointer of Profile Descriptions
1518
1519 @retval EFI_UNSUPPORTED ICC clock profile doesn't support
1520 @retval EFI_NOT_READY Heci device hasn't ready yet
1521 @retval EFI_SUCCESS Command succeeded
1522 **/
1523 EFI_STATUS
1524 HeciGetIccProfile (
1525 OUT UINT8 *Profile,
1526 OUT UINT8 *NumProfiles,
1527 OUT UINT8 *IccSelectAllowed,
1528 OUT ICC_PROFILE_DESC *ProfileDescriptions
1529 );
1530
1531 /**
1532 Sets ICC clock profile to be used on next and following boots
1533
1534 @param[in] Profile Number of profile to be used
1535
1536 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1537 @retval EFI_DEVICE_ERROR Wrong response
1538 @retval EFI_NOT_READY Heci device hasn't ready yet
1539 @retval EFI_SUCCESS Command succeeded
1540 **/
1541 EFI_STATUS
1542 HeciSetIccProfile (
1543 IN UINT8 Profile
1544 );
1545
1546 /**
1547 Retrieves the current settings of ICC
1548
1549 @param[in, out] IccClockSettings Current settings of ICC
1550
1551 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1552 @retval EFI_NOT_READY Heci device hasn't ready yet
1553 @retval EFI_INVALID_PARAMETER IccClockSettings is a NULL pointer
1554 @retval EFI_SUCCESS Command succeeded
1555 **/
1556 EFI_STATUS
1557 HeciGetIccClockSettings (
1558 IN OUT ICC_CLOCK_SETTINGS *IccClockSettings
1559 );
1560
1561 /**
1562 Sets ICC clock profile to be used on next and following boots
1563
1564 @param[in] IccClockSettings Pointer for requested ICC Clock Settings
1565
1566 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1567 @retval EFI_DEVICE_ERROR Wrong response
1568 @retval EFI_NOT_READY Heci device hasn't ready yet
1569 @retval EFI_INVALID_PARAMETER IccClockSettings is a NULL pointer
1570 @retval EFI_SUCCESS Command succeeded
1571 **/
1572 EFI_STATUS
1573 HeciSetIccClockSettings (
1574 IN ICC_CLOCK_SETTINGS *IccClockSettings
1575 );
1576
1577 //
1578 // ME Client - Hardware Asset
1579 //
1580
1581 /**
1582 Send Hardware Asset Tables to Firmware
1583
1584 @param[in] AssetTableData Hardware Asset Table Data
1585 @param[in] TableDataSize Size of Asset table
1586
1587 @retval EFI_SUCCESS Table sent
1588 @retval EFI_ABORTED Could not allocate Memory
1589 **/
1590 EFI_STATUS
1591 HeciAssetUpdateFwMsg (
1592 IN HWA_TABLE *AssetTableData,
1593 IN UINT16 TableDataSize
1594 );
1595
1596 //
1597 // ME Client - Unique Platform Id (UPID)
1598 //
1599
1600 /**
1601 This message is sent by the BIOS to check if given UPID feature is enabled in CSME
1602
1603 @param[in] UpidFeature UPID feature
1604 @param[out] UpidFeatureState Determines if feature is enabled
1605
1606 @retval EFI_SUCCESS Command succeeded
1607 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1608 @retval EFI_INVALID_PARAMETER Invalid input parameter
1609 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1610 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1611 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1612 **/
1613 EFI_STATUS
1614 HeciGetUpidFeatureState (
1615 IN UINT32 UpidFeature,
1616 OUT UINT8 *UpidFeatureState
1617 );
1618
1619 /**
1620 This message is sent by the BIOS to set given UPID feature state in CSME
1621
1622 @param[in] UpidFeature UPID feature
1623 @param[in] UpidFeatureState New UPID feature state
1624
1625 @retval EFI_SUCCESS Command succeeded
1626 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1627 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1628 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1629 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1630 **/
1631 EFI_STATUS
1632 HeciSetUpidFeatureState (
1633 IN UINT32 UpidFeature,
1634 IN UINT8 UpidFeatureState
1635 );
1636
1637 /**
1638 This message is sent by the BIOS to check if given UPID feature state can be
1639 modified by the OS
1640
1641 @param[in] UpidFeature UPID feature
1642 @param[out] UpidFeatureOsControlState Determines if OS can modify the feature state
1643
1644 @retval EFI_SUCCESS Command succeeded
1645 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1646 @retval EFI_INVALID_PARAMETER Invalid input parameter
1647 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1648 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1649 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1650 **/
1651 EFI_STATUS
1652 HeciGetUpidOsControlState (
1653 IN UINT32 UpidFeature,
1654 OUT UINT8 *UpidFeatureOsControlState
1655 );
1656
1657 /**
1658 This message is sent by the BIOS to set if given UPID feature state can be
1659 modified by the OS
1660
1661 @param[in] UpidFeature UPID feature
1662 @param[in] UpidFeatureOsControlState Determines if OS can modify the feature state
1663
1664 @retval EFI_SUCCESS Command succeeded
1665 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1666 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1667 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1668 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1669 **/
1670 EFI_STATUS
1671 HeciSetUpidOsControlState (
1672 IN UINT32 UpidFeature,
1673 IN UINT8 UpidFeatureOsControlState
1674 );
1675
1676 /**
1677 This message is sent by the BIOS to read the Platform Id
1678
1679 @param[out] OemPlatformIdType Determines format of the OemPlatformId field
1680 @param[out] OemPlatformId Platform Id set by the OEM
1681 @param[out] CsmePlatformId CSME Platfrom Id generated from CSME fuses
1682
1683 @retval EFI_SUCCESS Command succeeded
1684 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1685 @retval EFI_INVALID_PARAMETER Invalid input parameter
1686 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1687 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1688 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1689 **/
1690 EFI_STATUS
1691 HeciGetUpidPlatformId (
1692 OUT UINT32 *OemPlatformIdType,
1693 OUT UINT8 *OemPlatformId,
1694 OUT UINT8 *CsmePlatformId
1695 );
1696
1697 /**
1698 This message is sent by the BIOS to read the current Platform Id Refurbish Counter
1699
1700 @param[out] PlatformIdRefurbishCounter Current value of the Refurbish Counter
1701
1702
1703 @retval EFI_SUCCESS Command succeeded
1704 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1705 @retval EFI_INVALID_PARAMETER Invalid input parameter
1706 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1707 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1708 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1709 **/
1710 EFI_STATUS
1711 HeciGetUpidRefurbishCounter (
1712 OUT UINT8 *PlatformIdRefurbishCounter
1713 );
1714
1715 /**
1716 This message is sent by the BIOS to update the OEM Platform Id
1717
1718 @param[in] OemPlatformIdType Determines format of the OemPlatformId field
1719 @param[in] OemPlatformId OEM Platform Id to be set, up to 32 bytes
1720 @param[in] ManufacturingType Update reason
1721
1722 @retval EFI_SUCCESS Command succeeded
1723 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
1724 @retval EFI_INVALID_PARAMETER Invalid input parameter
1725 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
1726 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
1727 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
1728 **/
1729 EFI_STATUS
1730 HeciUpdateUpidOemPlatformId (
1731 IN UINT32 OemPlatformIdType,
1732 IN UINT8 *OemPlatformId,
1733 IN UINT8 ManufacturingType
1734 );
1735
1736 //
1737 // Prototype for ME Policy DXE phase
1738 //
1739
1740 /**
1741 Check if End of Post Message is enabled in setup options.
1742
1743 @retval FALSE EndOfPost is disabled.
1744 @retval TRUE EndOfPost is enabled.
1745 **/
1746 BOOLEAN
1747 MeEndOfPostEnabled (
1748 VOID
1749 );
1750
1751 /**
1752 Check if HECI2 should be removed from PCI space or not
1753
1754 @retval FALSE HECI2 should be Disabled and removed from PCI space
1755 @retval TRUE HECI2 should be enabled and not removed from PCI space
1756 **/
1757 BOOLEAN
1758 MeHeci2Enabled (
1759 VOID
1760 );
1761
1762 /**
1763 Read the ME policy to see if HECI message check is enabled for Bios Boot Path.
1764
1765 @retval TRUE HECI message check is enabled
1766 @retval FALSE HECI message check is disabled
1767 **/
1768 BOOLEAN
1769 MeHeciMessageCheckEnabled (
1770 VOID
1771 );
1772
1773 /**
1774 Show Me Error message. This is used to support display error message on the screen for localization
1775 description
1776
1777 @param[in] MsgId Me error message ID for displaying on screen message
1778 **/
1779 VOID
1780 MeReportError (
1781 IN ME_ERROR_MSG_ID MsgId
1782 );
1783
1784 /**
1785 Check if MeFwDowngrade is enabled in setup options.
1786
1787 @retval FALSE MeFwDowngrade is disabled.
1788 @retval TRUE MeFwDowngrade is enabled.
1789 **/
1790 BOOLEAN
1791 MeFwDowngradeSupported (
1792 VOID
1793 );
1794
1795 /**
1796 Check if Extended CSME Measured Boot is enabled from BIOS side.
1797
1798 @retval FALSE Extend CSME Measured Boot is disabled.
1799 @retval TRUE Extend CSME Measured Boot is enabled.
1800 **/
1801 BOOLEAN
1802 IsExtendedMeasuredBootEnabled (
1803 VOID
1804 );
1805
1806 /**
1807 Check if Core Bios Done Message is enabled in setup options.
1808
1809 @retval FALSE Core Bios Done is disabled.
1810 @retval TRUE Core Bios Done is enabled.
1811 **/
1812 BOOLEAN
1813 MeCoreBiosDoneEnabled (
1814 VOID
1815 );
1816
1817 /**
1818 Read the ME policy to see if HECI timeouts are enabled.
1819
1820 @retval FALSE HECI timeouts is disabled.
1821 @retval TRUE HECI timeouts is enabled.
1822 **/
1823 BOOLEAN
1824 MeHeciTimeoutsEnabled (
1825 VOID
1826 );
1827
1828 /**
1829 Read the ME policy to see if Heci Full Trace are enabled.
1830
1831 @retval TRUE HECI full trace in the log is enabled
1832 @retval FALSE HECI full trace in the log is disabled
1833 **/
1834 BOOLEAN
1835 MeHeciFullTrace (
1836 VOID
1837 );
1838
1839 /**
1840 Read the ME policy to see if D0I3 for HECI devices are enabled.
1841
1842 @retval TRUE D0I3 for HECI devices are enabled
1843 @retval FALSE D0I3 for HECI devices are disabled
1844 **/
1845 BOOLEAN
1846 MeHeciD0I3Enabled (
1847 VOID
1848 );
1849
1850 /**
1851 Checks if EndOfPost event already happened
1852
1853 @retval TRUE End of post already happened
1854 @retval FALSE End of post did not happen yet
1855 **/
1856 BOOLEAN
1857 MeIsAfterEndOfPost (
1858 VOID
1859 );
1860
1861 /**
1862 Set EndOfPost done
1863 **/
1864 VOID
1865 MeSetEndOfPostDone (
1866 VOID
1867 );
1868
1869
1870 #endif
HbmHostEnumRequest
EFI_STATUS HbmHostEnumRequest(IN HECI_DEVICE HeciDevice, OUT UINT8 *ValidAddresses)
Checks at which CSME addresses there are any clients.
HeciGetFwCapsSkuMsg
EFI_STATUS HeciGetFwCapsSkuMsg(OUT MEFWCAPS_SKU *RuleData)
Send Get Firmware SKU Request to ME.
HeciGetSouthClinkState
EFI_STATUS HeciGetSouthClinkState(OUT UINT32 *SouthClinkState)
Get value of South Clink State from ME.
HeciSetInvocationCode
EFI_STATUS HeciSetInvocationCode(IN UINT32 InvocationCode)
Set invocation codes in Firmware.
MeHeciD0I3Enabled
BOOLEAN MeHeciD0I3Enabled(VOID)
Read the ME policy to see if D0I3 for HECI devices are enabled.
HeciGetPlatIdSupportedState
EFI_STATUS HeciGetPlatIdSupportedState(OUT UINT8 *PlatIdSupported)
Read UPID Platform Id feature supported state from ME NVM.
HeciGetDamState
EFI_STATUS HeciGetDamState(OUT UINT8 *DamState)
Read Delayed Authentication Mode from ME NVM.
HeciSetUpidFeatureState
EFI_STATUS HeciSetUpidFeatureState(IN UINT32 UpidFeature, IN UINT8 UpidFeatureState)
This message is sent by the BIOS to set given UPID feature state in CSME.
HeciSetFwUpdateState
EFI_STATUS HeciSetFwUpdateState(IN UINT8 RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host...
HeciSetMeDisableMsg
EFI_STATUS HeciSetMeDisableMsg(VOID)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host...
HeciGetImageFwVersionMsg
EFI_STATUS HeciGetImageFwVersionMsg(IN UINT32 PartitionId, OUT FLASH_PARTITION_DATA *PartitionIdData)
Send Get Image Firmware Version Request to ME.
HbmHostVersion
EFI_STATUS HbmHostVersion(IN HECI_DEVICE HeciDev)
Checks if CSME supports HBM protocol version 2.2.
HeciGetCpuTypeChange
EFI_STATUS HeciGetCpuTypeChange(OUT GEN_GET_CPU_TYPE_CHANGE_DATA *CpuTypeChangeInfo)
Get CPU Type Change User Message.
MeSetEndOfPostDone
VOID MeSetEndOfPostDone(VOID)
Set EndOfPost done.
HbmHostStop
EFI_STATUS HbmHostStop(IN HECI_DEVICE HeciDev)
Instructs CSME to stop all communication on given Heci device.
HeciGetIsUserConsentRequired
EFI_STATUS HeciGetIsUserConsentRequired(OUT BOOLEAN *IsUserConsentRequired)
Get User Consent requirement.
IccMsgs.h
ICC Messages.
HeciSetFipsMode
EFI_STATUS HeciSetFipsMode(IN UINT32 FipsMode)
Send Set FIPS Mode to Enabled or Disabled.
HeciGetUpidPlatformId
EFI_STATUS HeciGetUpidPlatformId(OUT UINT32 *OemPlatformIdType, OUT UINT8 *OemPlatformId, OUT UINT8 *CsmePlatformId)
This message is sent by the BIOS to read the Platform Id.
HbmGetClientProperties
EFI_STATUS HbmGetClientProperties(IN HECI_DEVICE HeciDevice, IN UINT8 ClientAddr, OUT EFI_GUID *ProtocolGuid)
Retrieves GUID of a single CSME client.
HbmGetFlowControlToken
EFI_STATUS HbmGetFlowControlToken(IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Attempts to receive a flow control token from CSME.
HeciHmrfpoLock
EFI_STATUS HeciHmrfpoLock(OUT UINT8 *Result)
Sends a message to ME to lock a specified SPI Flash region for writing and receiving a response messa...
HeciSendChassisIntrDetEvent
EFI_STATUS HeciSendChassisIntrDetEvent(VOID)
Inform CSME of Chassis Intrusion Detected Event.
HeciGetErLog
EFI_STATUS HeciGetErLog(OUT UINT8 *EventLogBuffer, IN UINT32 RemainingBufSize, IN OUT UINT32 *ReceivedLogSize, IN OUT UINT8 *LogEntryIndex, OUT UINT8 *RemainingEntries)
This function sends a command to CSME to get Log information of Measurements provided in CSME Extend ...
HeciReadFileExMsg
EFI_STATUS HeciReadFileExMsg(IN UINT32 FileId, IN UINT32 Offset, IN OUT UINT32 *DataSize, IN UINT8 Flags, OUT UINT8 *DataBuffer)
This message is sent by the BIOS to retrieve file stored in ME firmware NVM.
UpidMsgs.h
Definitions for Unique Platform ID messages support.
HeciPdtUnlockMsg
EFI_STATUS HeciPdtUnlockMsg(IN CONST CHAR8 *FileName)
This message is sent by the BIOS when it wants to send PDT Unlock Message to ISH.
HeciPdtUpdateMsg
EFI_STATUS HeciPdtUpdateMsg(IN CONST CHAR8 *FileName, IN UINT8 *PdtFileBuffer, IN UINT16 PdtBufferSize)
This message is sent by the BIOS when it wants to send PDT Update Message.
IsExtendedMeasuredBootEnabled
BOOLEAN IsExtendedMeasuredBootEnabled(VOID)
Check if Extended CSME Measured Boot is enabled from BIOS side.
HeciSendCbmResetRequest
EFI_STATUS HeciSendCbmResetRequest(IN UINT8 ResetOrigin, IN UINT8 ResetType)
Send Core BIOS Reset Request Message through HECI to reset the system.
HeciGetPlatformTypeMsg
EFI_STATUS HeciGetPlatformTypeMsg(OUT PLATFORM_TYPE_RULE_DATA *RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host...
IsCiraAvailable
BOOLEAN IsCiraAvailable(VOID)
Return information if Client Initiated Remote Access (CIRA) is available.
HeciGetFipsMode
EFI_STATUS HeciGetFipsMode(OUT GET_FIPS_MODE_DATA *GetFipsModeData)
Send Get Current FIPS Mode and Crypto Driver version.
HeciGetUpidRefurbishCounter
EFI_STATUS HeciGetUpidRefurbishCounter(OUT UINT8 *PlatformIdRefurbishCounter)
This message is sent by the BIOS to read the current Platform Id Refurbish Counter.
HeciGetMoffOverrideState
EFI_STATUS HeciGetMoffOverrideState(OUT UINT32 *MOffOverrideState)
Get Override Capability State for M3 to Moff Transitions.
CoreBiosMsg.h
Core BIOS Messages.
HeciIsMebxPasswordModified
EFI_STATUS HeciIsMebxPasswordModified(OUT UINT32 *Modified)
Checks if password was modified.
HeciSetDamState
EFI_STATUS HeciSetDamState(IN UINT8 DamState)
Set Delayed Authentication Mode in ME NVM.
HeciClearInvocationCode
EFI_STATUS HeciClearInvocationCode(IN UINT32 InvocationCode)
Clear invocation codes in Firmware.
HWA_PUSH_TABLES_MSG
Asset Update Table Message.
Definition: DxeMeLib.h:95
HWA_TABLE_TYPE_INDEX
HWA_TABLE_TYPE_INDEX
Hardware Asset Table Index.
Definition: DxeMeLib.h:74
ICC_CLOCK_SETTINGS
Structure for Clock Settings.
Definition: IccMsgs.h:354
HeciFwFeatureStateOverride
EFI_STATUS HeciFwFeatureStateOverride(IN UINT32 EnableBitmask, IN UINT32 DisableBitmask)
Sends the MKHI Enable/Disable FW Features.
HeciCommitFilesMsg
EFI_STATUS HeciCommitFilesMsg(VOID)
This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit...
ME_ERROR_MSG_ID
ME_ERROR_MSG_ID
ME Error Message ID.
Definition: MeDxeConfig.h:54
HeciCoreBiosDoneMsg
EFI_STATUS HeciCoreBiosDoneMsg(VOID)
This message is sent by the BIOS to notify ME firmware that the BIOS is starting to run 3rd party cod...
HeciGetIccClockSettings
EFI_STATUS HeciGetIccClockSettings(IN OUT ICC_CLOCK_SETTINGS *IccClockSettings)
Retrieves the current settings of ICC.
IshMsgs.h
ISH Messages.
HbmUnmapRequest
EFI_STATUS HbmUnmapRequest(IN HECI_DEVICE HeciDev, IN UINT8 ClientDmaBufferId)
Requests unmapping CSME HECI client MMIO from the given physcial memory addresses.
HeciSetMoffOverrideState
EFI_STATUS HeciSetMoffOverrideState(IN UINT32 MoffOverrideState)
Set Moff Override State.
HeciSetFileExMsg
EFI_STATUS HeciSetFileExMsg(IN UINT32 FileId, IN UINT32 Offset, IN UINT32 DataSize, IN UINT8 Flags, IN UINT8 *DataBuffer)
This message is sent by the BIOS to save data in a file stored in ME firmware NVM.
MeHeciMessageCheckEnabled
BOOLEAN MeHeciMessageCheckEnabled(VOID)
Read the ME policy to see if HECI message check is enabled for Bios Boot Path.
MkhiMsgs.h
MKHI Messages.
HeciGetRpmcStatus
EFI_STATUS HeciGetRpmcStatus(OUT RP_STATUS_2 *RpStatus)
This message is sent by the BIOS to retrieve RPMC status data from CSME.
MeCoreBiosDoneEnabled
BOOLEAN MeCoreBiosDoneEnabled(VOID)
Check if Core Bios Done Message is enabled in setup options.
MeiBusMsg.h
Definitions for MEI Bus message support.
PsrMsgs.h
Definitions for querying PSR message.
HeciGetFwVersionMsg
EFI_STATUS HeciGetFwVersionMsg(OUT GET_FW_VER_ACK_DATA *GetFwVersionAckData)
Send Get Firmware Version Request to ME.
HeciSetAcmTpmData
EFI_STATUS HeciSetAcmTpmData(IN UINT8 TpmDeactivate)
This message is sent by the BIOS to inform ME FW whether or not to take the TPM 1....
MeHeciTimeoutsEnabled
BOOLEAN MeHeciTimeoutsEnabled(VOID)
Read the ME policy to see if HECI timeouts are enabled.
HeciSetMeEnableMsg
EFI_STATUS HeciSetMeEnableMsg(VOID)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host...
HeciGetUpidFeatureState
EFI_STATUS HeciGetUpidFeatureState(IN UINT32 UpidFeature, OUT UINT8 *UpidFeatureState)
This message is sent by the BIOS to check if given UPID feature is enabled in CSME.
MeIsAfterEndOfPost
BOOLEAN MeIsAfterEndOfPost(VOID)
Checks if EndOfPost event already happened.
MeFwDowngradeSupported
BOOLEAN MeFwDowngradeSupported(VOID)
Check if MeFwDowngrade is enabled in setup options.
HeciSetMeasuredBootState
EFI_STATUS HeciSetMeasuredBootState(IN UINT8 SetMeasuredBootState)
Send Set Measured Boot State to Enable or Disable CSME Measurement.
HeciModifyMebxPassword
ME_PWD_STATUS HeciModifyMebxPassword(IN UINT8 OldPwdSize, IN UINT8 *OldPwd, IN UINT8 NewPwdSize, IN UINT8 *NewPwd)
This function logs in with current password and updates to new password.
HeciGetUserCapabilitiesState
EFI_STATUS HeciGetUserCapabilitiesState(OUT MEFWCAPS_SKU *RuleData)
Send Get User Capabilities State Request to ME.
HeciGetUnconfigureStatus
EFI_STATUS HeciGetUnconfigureStatus(OUT UINT8 *UnconfigStatus)
Get ME Unconfiguration Status.
HeciGetUpidOsControlState
EFI_STATUS HeciGetUpidOsControlState(IN UINT32 UpidFeature, OUT UINT8 *UpidFeatureOsControlState)
This message is sent by the BIOS to check if given UPID feature state can be modified by the OS.
HeciSetIccProfile
EFI_STATUS HeciSetIccProfile(IN UINT8 Profile)
Sets ICC clock profile to be used on next and following boots.
HbmSendFlowControlToken
EFI_STATUS HbmSendFlowControlToken(IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Sends a flow control token from BIOS to CSME that allows CSME to send one message over connection ide...
HeciGetIccProfile
EFI_STATUS HeciGetIccProfile(OUT UINT8 *Profile, OUT UINT8 *NumProfiles, OUT UINT8 *IccSelectAllowed, OUT ICC_PROFILE_DESC *ProfileDescriptions)
Retrieves the number of currently used ICC clock profile.
HeciAssetUpdateFwMsg
EFI_STATUS HeciAssetUpdateFwMsg(IN HWA_TABLE *AssetTableData, IN UINT16 TableDataSize)
Send Hardware Asset Tables to Firmware.
HeciSetSouthClinkState
EFI_STATUS HeciSetSouthClinkState(IN UINT32 SouthClinkState)
Set South Clink State.
MeEndOfPostEnabled
BOOLEAN MeEndOfPostEnabled(VOID)
Check if End of Post Message is enabled in setup options.
HeciFwCapsGetRuleData
EFI_STATUS HeciFwCapsGetRuleData(IN UINT32 RuleId, OUT UINT32 *RuleData)
Send Get Rule Data Request to CSME.
HeciSetUpidOsControlState
EFI_STATUS HeciSetUpidOsControlState(IN UINT32 UpidFeature, IN UINT8 UpidFeatureOsControlState)
This message is sent by the BIOS to set if given UPID feature state can be modified by the OS.
HeciHmrfpoEnable
EFI_STATUS HeciHmrfpoEnable(OUT UINT8 *Result)
Sends a message to ME to unlock a specified SPI Flash region for writing and receiving a response mes...
HeciGetPsrRecord
EFI_STATUS HeciGetPsrRecord(IN OUT PSR_DATA *PsrData)
Get Platform Service Record from CSME.
HeciSetManufacturingMeResetAndHalt
EFI_STATUS HeciSetManufacturingMeResetAndHalt(VOID)
Send Set Manufacturing Me Reset and Halt Request to ME.
HeciGetFwUpdateState
EFI_STATUS HeciGetFwUpdateState(OUT UINT8 *RuleData)
This message is sent by the BIOS or IntelR MEBX prior to the End of Post (EOP) on the boot where host...
HeciArbSvnGetInfoMsg
EFI_STATUS HeciArbSvnGetInfoMsg(IN OUT UINT32 *Entries, IN OUT ARB_SVN_INFO_ENTRY *ArbSvnInfo)
The command retrieves anti-replay SVN information.
HeciSetFwEnabledFeatures
EFI_STATUS HeciSetFwEnabledFeatures(IN UINT32 NewFeatures, IN UINT32 FeaturesMask)
Set FW Enabled Features.
HeciSetCpuTypeChangeUserResponse
EFI_STATUS HeciSetCpuTypeChangeUserResponse(IN UINT8 UserResponse)
Send CPU Type Change User Response.
HeciSendCpuBrandClassFuse
EFI_STATUS HeciSendCpuBrandClassFuse(IN UINT8 CpuBrandClass)
Send CPU brand class fuse to the CSME (only for corporate SKU).
HeciFwCapsSetRuleData
EFI_STATUS HeciFwCapsSetRuleData(IN UINT32 RuleId, IN UINT8 RuleDataLength, IN UINT32 RuleData)
Send Set Rule Data Request to CSME.
HeciGetUnconfigOnRtcClearDisableMsg
EFI_STATUS HeciGetUnconfigOnRtcClearDisableMsg(OUT UINT32 *RuleData)
This message is sent by the BIOS when it wants to query ME Unconfig on RTC Clear Disable state.
HeciUpdateUpidOemPlatformId
EFI_STATUS HeciUpdateUpidOemPlatformId(IN UINT32 OemPlatformIdType, IN UINT8 *OemPlatformId, IN UINT8 ManufacturingType)
This message is sent by the BIOS to update the OEM Platform Id.
MePolicy.h
Interface definition details between ME and platform drivers during DXE phase.
HeciGetMkhiVersion
EFI_STATUS HeciGetMkhiVersion(OUT MKHI_VERSION *MkhiVersion)
Get MKHI (Management Engine Kernel Host Interface) Version.
HeciArbSvnCommitMsg
EFI_STATUS HeciArbSvnCommitMsg(VOID)
This command indicates to the FW that it shall commit ARBSVN to fuse.
HeciGetMeasuredBootState
EFI_STATUS HeciGetMeasuredBootState(OUT UINT8 *GetMeasuredBootState)
Send Get Current CSME Measured Boot State.
MeReportError
VOID MeReportError(IN ME_ERROR_MSG_ID MsgId)
Show Me Error message.
HeciHmrfpoDisable
EFI_STATUS HeciHmrfpoDisable(VOID)
Send HMRFPO disable MKHI to CSME.
HbmHostClientConnect
EFI_STATUS HbmHostClientConnect(IN HECI_DEVICE HeciDev, IN UINT8 MeAddress, IN UINT8 HostAddress)
Creates a connection between given host and CSME addresses.
HeciUnconfigWithouPwd
EFI_STATUS HeciUnconfigWithouPwd(VOID)
Unconfigure ME without password.
MEFWCAPS_SKU
Get Firmware Capability.
Definition: MkhiMsgs.h:404
HeciGetInvocationCode
EFI_STATUS HeciGetInvocationCode(OUT UINT32 *InvocationCode)
Retrieve invocation codes from Firmware.
ME_PWD_STATUS
ME_PWD_STATUS
Definition: MkhiMsgs.h:252
HeciGetFwAvailableFeatures
EFI_STATUS HeciGetFwAvailableFeatures(OUT UINT32 *FwFeatures)
Get available ME features.
HeciProtocol.h
HECI Protocol.
BupMsgs.h
BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW.
HeciValidateMebxPassword
EFI_STATUS HeciValidateMebxPassword(IN UINT8 PasswordSize, IN UINT8 *Password, OUT BOOLEAN *MaxRetries)
This function uses the User entered password to login into FW.
HeciSetUserCapabilitiesState
EFI_STATUS HeciSetUserCapabilitiesState(IN MEFWCAPS_SKU RuleData)
Send Set User Capabilities State Request to ME.
HeciSetUnconfigOnRtcClearDisableMsg
EFI_STATUS HeciSetUnconfigOnRtcClearDisableMsg(IN UINT32 RuleData)
This message is sent by the BIOS when it wants to set ME Unconfig on RTC Clear Disable state.
HWA_MESSAGE_HEADER
Definitions for Hardware Asset Header.
Definition: DxeMeLib.h:58
MeHeciFullTrace
BOOLEAN MeHeciFullTrace(VOID)
Read the ME policy to see if Heci Full Trace are enabled.
MeHeci2Enabled
BOOLEAN MeHeci2Enabled(VOID)
Check if HECI2 should be removed from PCI space or not.
HeciGetFwFeatureStateMsg
EFI_STATUS HeciGetFwFeatureStateMsg(OUT MEFWCAPS_SKU *RuleData)
The Get FW Feature Status message is based on MKHI interface.
HbmMapRequest
EFI_STATUS HbmMapRequest(IN HECI_DEVICE HeciDev, IN UINT8 ClientDmaBufferId, IN UINT32 AddressLow, IN UINT32 AddressHigh, IN UINT32 Size)
Requests mapping CSME HECI client MMIO to the given physcial memory addresses.
HeciGetAmtBiosSyncInfo
EFI_STATUS HeciGetAmtBiosSyncInfo(OUT AMT_BIOS_SYNC_INFO *RuleData)
This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning st...
HeciDnxReqClear
EFI_STATUS HeciDnxReqClear(IN UINT32 Flag)
Send Dnx Request Clear message.
PlatformMeHook.h
Interface definition details for platform hook support to ME module during DXE phase.
HWA_MESSAGE_HEADER::Command
UINT32 Command
only supported command would be HWA_TABLE_PUSH_CMD =0;
Definition: DxeMeLib.h:62
HeciGetOemTagMsg
EFI_STATUS HeciGetOemTagMsg(OUT UINT32 *RuleData)
The firmware will respond to GET OEM TAG message even after the End of Post (EOP).
HbmClientDisconnect
EFI_STATUS HbmClientDisconnect(IN HECI_DEVICE HeciDev, IN UINT8 HostAddr, IN UINT8 MeAddr)
Disconnects an established connection between a Host and CSME clients.
HeciHmrfpoGetStatus
EFI_STATUS HeciHmrfpoGetStatus(OUT UINT8 *Result)
System BIOS sends this message to get status for HMRFPO_LOCK message.
HbmCapabilitiesRequest
EFI_STATUS HbmCapabilitiesRequest(IN HECI_DEVICE HeciDev, IN OUT HBM_CAPS_DATA *HbmCaps)
Informs about Host and CSME capabilities over HBM.
HeciSetIccClockSettings
EFI_STATUS HeciSetIccClockSettings(IN ICC_CLOCK_SETTINGS *IccClockSettings)
Sets ICC clock profile to be used on next and following boots.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMePolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeMePolicyLib.h File Reference

Prototype of the DxeMePolicyLib library. More...

#include <Protocol/MePolicy.h>
Include dependency graph for DxeMePolicyLib.h:

Go to the source code of this file.

Functions

VOID | MePrintPolicyProtocol (IN ME_POLICY_PROTOCOL *DxeMePolicy)
This function prints the ME DXE phase policy. More...
EFI_STATUS | MeCreatePolicyDefaults (IN OUT ME_POLICY_PROTOCOL **DxeMePolicy)
MeCreatePolicyDefaults creates the default setting of ME Policy. More...
EFI_STATUS | MeInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN ME_POLICY_PROTOCOL *DxeMePolicy)
MeInstallPolicyProtocol installs ME Policy. More...

Detailed Description

Prototype of the DxeMePolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeMePolicyLib.h.

Function Documentation

◆ MeCreatePolicyDefaults()

EFI_STATUS MeCreatePolicyDefaults ( IN OUT ME_POLICY_PROTOCOL ** DxeMePolicy )

MeCreatePolicyDefaults creates the default setting of ME Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[in,out] DxeMePolicy The pointer to get ME Policy protocol instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MeInstallPolicyProtocol()

EFI_STATUS MeInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN ME_POLICY_PROTOCOL * | DxeMePolicy
 | ) |  |

MeInstallPolicyProtocol installs ME Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | DxeMePolicy | The pointer to ME Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MePrintPolicyProtocol()

VOID MePrintPolicyProtocol ( IN ME_POLICY_PROTOCOL * DxeMePolicy )

This function prints the ME DXE phase policy.

Parameters
[in] DxeMePolicy - ME DXE Policy protocol
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeMePolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeMePolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the DxeMePolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_ME_POLICY_LIB_H_
36 #define _DXE_ME_POLICY_LIB_H_
37
38 #include <Protocol/MePolicy.h>
39
40 /**
41 This function prints the ME DXE phase policy.
42
43 @param[in] DxeMePolicy - ME DXE Policy protocol
44 **/
45 VOID
46 MePrintPolicyProtocol (
47 IN ME_POLICY_PROTOCOL *DxeMePolicy
48 );
49
50 /**
51 MeCreatePolicyDefaults creates the default setting of ME Policy.
52 It allocates and zero out buffer, and fills in the Intel default settings.
53
54 @param[in, out] DxeMePolicy The pointer to get ME Policy protocol instance
55
56 @retval EFI_SUCCESS The policy default is initialized.
57 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
58
59 **/
60 EFI_STATUS
61 EFIAPI
62 MeCreatePolicyDefaults (
63 IN OUT ME_POLICY_PROTOCOL **DxeMePolicy
64 );
65
66 /**
67 MeInstallPolicyProtocol installs ME Policy.
68 While installed, RC assumes the Policy is ready and finalized. So please update and override
69 any setting before calling this function.
70
71 @param[in] ImageHandle Image handle of this driver.
72 @param[in] DxeMePolicy The pointer to ME Policy Protocol instance
73
74 @retval EFI_SUCCESS The policy is installed.
75 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
76
77 **/
78 EFI_STATUS
79 EFIAPI
80 MeInstallPolicyProtocol (
81 IN EFI_HANDLE ImageHandle,
82 IN ME_POLICY_PROTOCOL *DxeMePolicy
83 );
84
85 #endif // _DXE_ME_POLICY_LIB_H_
_ME_POLICY_PROTOCOL
ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Conf...
Definition: MePolicy.h:59
MeInstallPolicyProtocol
EFI_STATUS MeInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN ME_POLICY_PROTOCOL *DxeMePolicy)
MeInstallPolicyProtocol installs ME Policy.
MePolicy.h
Interface definition details between ME and platform drivers during DXE phase.
MeCreatePolicyDefaults
EFI_STATUS MeCreatePolicyDefaults(IN OUT ME_POLICY_PROTOCOL **DxeMePolicy)
MeCreatePolicyDefaults creates the default setting of ME Policy.
MePrintPolicyProtocol
VOID MePrintPolicyProtocol(IN ME_POLICY_PROTOCOL *DxeMePolicy)
This function prints the ME DXE phase policy.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxePchPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Functions
DxePchPolicyLib.h File Reference

Prototype of the DxePchPolicyLib library. More...

#include <Protocol/PchPolicy.h>
Include dependency graph for DxePchPolicyLib.h:

Go to the source code of this file.

Functions

VOID | PchPrintPolicyProtocol (IN PCH_POLICY_PROTOCOL *PchPolicy)
This function prints the DXE phase policy. More...
EFI_STATUS | CreatePchDxeConfigBlocks (IN OUT PCH_POLICY_PROTOCOL **PchPolicy)
CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy. More...
EFI_STATUS | PchInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN PCH_POLICY_PROTOCOL *PchPolicy)
PchInstallPolicyProtocol installs PCH Policy. More...

Detailed Description

Prototype of the DxePchPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxePchPolicyLib.h.

Function Documentation

◆ CreatePchDxeConfigBlocks()

EFI_STATUS CreatePchDxeConfigBlocks ( IN OUT PCH_POLICY_PROTOCOL ** PchPolicy )

CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[out] PchPolicy The pointer to get PCH Policy Protocol instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ PchInstallPolicyProtocol()

EFI_STATUS PchInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN PCH_POLICY_PROTOCOL * | PchPolicy
 | ) |  |

PchInstallPolicyProtocol installs PCH Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | PchPolicy | The pointer to PCH Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ PchPrintPolicyProtocol()

VOID PchPrintPolicyProtocol ( IN PCH_POLICY_PROTOCOL * PchPolicy )

This function prints the DXE phase policy.

Parameters
[in] PchPolicy - PCH DXE Policy protocol
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxePchPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
DxePchPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the DxePchPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_PCH_POLICY_LIB_H_
36 #define _DXE_PCH_POLICY_LIB_H_
37
38 #include <Protocol/PchPolicy.h>
39
40 /**
41 This function prints the DXE phase policy.
42
43 @param[in] PchPolicy - PCH DXE Policy protocol
44 **/
45 VOID
46 PchPrintPolicyProtocol (
47 IN PCH_POLICY_PROTOCOL *PchPolicy
48 );
49
50 /**
51 CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.
52 It allocates and zero out buffer, and fills in the Intel default settings.
53
54 @param[out] PchPolicy The pointer to get PCH Policy Protocol instance
55
56 @retval EFI_SUCCESS The policy default is initialized.
57 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
58 **/
59 EFI_STATUS
60 EFIAPI
61 CreatePchDxeConfigBlocks(
62 IN OUT PCH_POLICY_PROTOCOL **PchPolicy
63 );
64
65 /**
66 PchInstallPolicyProtocol installs PCH Policy.
67 While installed, RC assumes the Policy is ready and finalized. So please update and override
68 any setting before calling this function.
69
70 @param[in] ImageHandle Image handle of this driver.
71 @param[in] PchPolicy The pointer to PCH Policy Protocol instance
72
73 @retval EFI_SUCCESS The policy is installed.
74 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
75
76 **/
77 EFI_STATUS
78 EFIAPI
79 PchInstallPolicyProtocol (
80 IN EFI_HANDLE ImageHandle,
81 IN PCH_POLICY_PROTOCOL *PchPolicy
82 );
83
84 #endif // _DXE_PCH_POLICY_LIB_H_
CreatePchDxeConfigBlocks
EFI_STATUS CreatePchDxeConfigBlocks(IN OUT PCH_POLICY_PROTOCOL **PchPolicy)
CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.
PchInstallPolicyProtocol
EFI_STATUS PchInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN PCH_POLICY_PROTOCOL *PchPolicy)
PchInstallPolicyProtocol installs PCH Policy.
PchPrintPolicyProtocol
VOID PchPrintPolicyProtocol(IN PCH_POLICY_PROTOCOL *PchPolicy)
This function prints the DXE phase policy.
PchPolicy.h
Interface definition details between Pch and platform drivers during DXE phase.
PCH_POLICY_PROTOCOL
PCH DXE Policy.
Definition: PchPolicy.h:62
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeSaPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
Functions
DxeSaPolicyLib.h File Reference

Prototype of the DxeSaPolicyLib library. More...

#include <Protocol/SaPolicy.h>
Include dependency graph for DxeSaPolicyLib.h:

Go to the source code of this file.

Functions

VOID | SaPrintPolicyProtocol (IN SA_POLICY_PROTOCOL *SaPolicy)
This function prints the DXE phase policy. More...
EFI_STATUS | CreateSaDxeConfigBlocks (IN OUT SA_POLICY_PROTOCOL **SaPolicy)
CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. More...
EFI_STATUS | SaInstallPolicyProtocol (IN EFI_HANDLE ImageHandle, IN SA_POLICY_PROTOCOL *SaPolicy)
SaInstallPolicyProtocol installs SA Policy. More...

Detailed Description

Prototype of the DxeSaPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeSaPolicyLib.h.

Function Documentation

◆ CreateSaDxeConfigBlocks()

EFI_STATUS CreateSaDxeConfigBlocks ( IN OUT SA_POLICY_PROTOCOL ** SaPolicy )

CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[out] SaPolicy The pointer to get SA Policy Protocol instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SaInstallPolicyProtocol()

EFI_STATUS SaInstallPolicyProtocol | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN SA_POLICY_PROTOCOL * | SaPolicy
 | ) |  |

SaInstallPolicyProtocol installs SA Policy.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SaPolicy | The pointer to SA Policy Protocol instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SaPrintPolicyProtocol()

VOID SaPrintPolicyProtocol ( IN SA_POLICY_PROTOCOL * SaPolicy )

This function prints the DXE phase policy.

Parameters
[in] SaPolicy - SA DXE Policy protocol
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeSaPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
DxeSaPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the DxeSaPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_SA_POLICY_LIB_H_
36 #define _DXE_SA_POLICY_LIB_H_
37
38 #include <Protocol/SaPolicy.h>
39
40 /**
41 This function prints the DXE phase policy.
42
43 @param[in] SaPolicy - SA DXE Policy protocol
44 **/
45 VOID
46 SaPrintPolicyProtocol (
47 IN SA_POLICY_PROTOCOL *SaPolicy
48 )
49 ;
50
51 /**
52 CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
53 It allocates and zero out buffer, and fills in the Intel default settings.
54
55 @param[out] SaPolicy The pointer to get SA Policy Protocol instance
56
57 @retval EFI_SUCCESS The policy default is initialized.
58 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
59 **/
60 EFI_STATUS
61 EFIAPI
62 CreateSaDxeConfigBlocks(
63 IN OUT SA_POLICY_PROTOCOL **SaPolicy
64 );
65
66 /**
67 SaInstallPolicyProtocol installs SA Policy.
68 While installed, RC assumes the Policy is ready and finalized. So please update and override
69 any setting before calling this function.
70
71 @param[in] ImageHandle Image handle of this driver.
72 @param[in] SaPolicy The pointer to SA Policy Protocol instance
73
74 @retval EFI_SUCCESS The policy is installed.
75 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
76
77 **/
78 EFI_STATUS
79 EFIAPI
80 SaInstallPolicyProtocol (
81 IN EFI_HANDLE ImageHandle,
82 IN SA_POLICY_PROTOCOL *SaPolicy
83 )
84 ;
85
86 #endif // _DXE_SA_POLICY_LIB_H_
CreateSaDxeConfigBlocks
EFI_STATUS CreateSaDxeConfigBlocks(IN OUT SA_POLICY_PROTOCOL **SaPolicy)
CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy.
SA_POLICY_PROTOCOL
SA DXE Policy.
Definition: SaPolicy.h:82
SaInstallPolicyProtocol
EFI_STATUS SaInstallPolicyProtocol(IN EFI_HANDLE ImageHandle, IN SA_POLICY_PROTOCOL *SaPolicy)
SaInstallPolicyProtocol installs SA Policy.
SaPrintPolicyProtocol
VOID SaPrintPolicyProtocol(IN SA_POLICY_PROTOCOL *SaPolicy)
This function prints the DXE phase policy.
SaPolicy.h
Interface definition details between System Agent and platform drivers during DXE phase.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeTbtCommonDefinition.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
DxeTbtCommonDefinition.h File Reference

TBT DXE Common Definition. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

TBT DXE Common Definition.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeTbtCommonDefinition.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeTbtCommonDefinition.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
DxeTbtCommonDefinition.h
Go to the documentation of this file.
1 /** @file
2 TBT DXE Common Definition
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _DXE_TBT_COMMON_DEFINITION_H_
37 #define _DXE_TBT_COMMON_DEFINITION_H_
38
39 //
40 // TBT Common Data Structure
41 //
42 typedef struct _TBT_COMMON_CONFIG{
43 /**
44 Tbt Vtd Base Security for disable BME from TBT tree.
45 <b>0: Disabled</b>, 1: Enabled
46 **/
47 UINT8 TbtVtdBaseSecurity;
48 UINT8 Reserved[3]; ///< Reserved bits
49 } TBT_COMMON_CONFIG;
50
51 //
52 // TBT Resource Data Structure
53 //
54 typedef struct _TBT_RESOURCE_CONFIG{
55 UINT8 TbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP
56 UINT8 TbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource for PCIe RP
57 UINT16 TbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP
58 UINT16 TbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP
59 UINT8 TbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resource for PCIe RP
60 UINT8 Reserved[1]; ///< Reserved for DWORD alignment
61 } TBT_RESOURCE_CONFIG;
62
63 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeTbtDisBmeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
DxeTbtDisBmeLib.h File Reference

Disable BME on TBT Hierarchy Lib. More...

#include <Uefi.h>
#include <PcieRegs.h>
#include <PeiITbtGenericStructure.h>
#include <IndustryStandard/Pci.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/PciSegmentLib.h>
#include <Library/UefiLib.h>
#include <Library/BaseLib.h>
#include <Library/PcieHelperLib.h>
Include dependency graph for DxeTbtDisBmeLib.h:

Go to the source code of this file.

Functions

VOID RecursiveTbtHierarchyConfiguration (IN SBDF Sbdf)
Recursive Tbt Hierarchy Configuration. More...

Detailed Description

Disable BME on TBT Hierarchy Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file DxeTbtDisBmeLib.h.

Function Documentation

◆ RecursiveTbtHierarchyConfiguration()

VOID RecursiveTbtHierarchyConfiguration ( IN SBDF Sbdf )

Recursive Tbt Hierarchy Configuration.

Parameters
[in] Sbdf device's segment:bus:device:function coordinates
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): DxeTbtDisBmeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
DxeTbtDisBmeLib.h
Go to the documentation of this file.
1 /** @file
2 Disable BME on TBT Hierarchy Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TBT_SECURITY_LIB_H_
36 #define _TBT_SECURITY_LIB_H_
37
38 #include <Uefi.h>
39 #include <PcieRegs.h>
40 #include <PeiITbtGenericStructure.h>
41 #include <IndustryStandard/Pci.h>
42 #include <Library/BaseMemoryLib.h>
43 #include <Library/DebugLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <Library/UefiLib.h>
46 #include <Library/BaseLib.h>
47 #include <Library/PcieHelperLib.h>
48
49 typedef struct {
50 UINT32 Seg : 8;
51 UINT32 Bus : 8;
52 UINT32 Dev : 5;
53 UINT32 Func : 3;
54 UINT32 PcieCap : 8;
55 } SBDF;
56
57 typedef enum {
58 DevTypePci,
59 DevTypePcieEndpoint,
60 DevTypePcieUpstream,
61 DevTypePcieDownstream,
62 DevTypeMax
63 } PCI_DEV_TYPE;
64
65 /**
66 Recursive Tbt Hierarchy Configuration
67
68 @param[in] Sbdf device's segment:bus:device:function coordinates
69 **/
70 VOID
71 RecursiveTbtHierarchyConfiguration (
72 IN SBDF Sbdf
73 );
74
75 #endif
PcieRegs.h
Register names for PCIE standard register.
RecursiveTbtHierarchyConfiguration
VOID RecursiveTbtHierarchyConfiguration(IN SBDF Sbdf)
Recursive Tbt Hierarchy Configuration.
PeiITbtGenericStructure.h
ITBT Policy definition to be referred in both PEI and DXE phase.
PcieHelperLib.h
Header file for PCI Express helpers base library.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): EspiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Classes
EspiConfig.h File Reference

Espi policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_ESPI_CONFIG
This structure contains the policies which are related to ESPI. More...

Detailed Description

Espi policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file EspiConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): EspiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
EspiConfig.h
Go to the documentation of this file.
1 /** @file
2 Espi policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ESPI_CONFIG_H_
36 #define _ESPI_CONFIG_H_
37
38 #define PCH_ESPI_CONFIG_REVISION 2
39 extern EFI_GUID gEspiConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to ESPI.
45
46 <b>Revision 1</b>:
47 - Initial revision
48 <b>Revision 2</b>:
49 - Added LockLinkConfiguration field to config block
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range
55 specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).
56 <b>0: FALSE</b>, 1: TRUE
57 **/
58 UINT32 LgmrEnable : 1;
59 /**
60 eSPI host and device BME settings.
61 When TRUE, then the BME bit enabled in eSPI host and device.
62 0: FALSE, <b>1: TRUE </b>
63 **/
64 UINT32 BmeMasterSlaveEnabled : 1;
65 /**
66 Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE)
67 <b>0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ignored)</b>
68 1b: Enable HOST_C10 reporting to device via eSPI Virtual Wire (upon receiving a HOST_C10 indication from PMC)
69 **/
70 UINT32 HostC10ReportEnable : 1;
71 /**
72 eSPI Link Configuration Lock (SBLCL)
73 If set to TRUE then communication through SET_CONFIG/GET_CONFIG
74 to eSPI device addresses from range 0x0 - 0x7FF
75 <b>1: TRUE</b>, 0: FALSE
76 **/
77 UINT32 LockLinkConfiguration : 1;
78 /**
79 Hardware Autonomous Enable (HAE)
80 If set to TRUE, then the IP may request a PG whenever it is idle
81 **/
82 UINT32 EspiPmHAE : 1;
83 UINT32 RsvdBits : 27; ///< Reserved bits
84 } PCH_ESPI_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _ESPI_CONFIG_H_
89
PCH_ESPI_CONFIG::LgmrEnable
UINT32 LgmrEnable
LPC (eSPI) Memory Range Decode Enable.
Definition: EspiConfig.h:58
PCH_ESPI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits.
Definition: EspiConfig.h:83
PCH_ESPI_CONFIG::LockLinkConfiguration
UINT32 LockLinkConfiguration
eSPI Link Configuration Lock (SBLCL) If set to TRUE then communication through SET_CONFIG/GET_CONFIG ...
Definition: EspiConfig.h:77
PCH_ESPI_CONFIG::HostC10ReportEnable
UINT32 HostC10ReportEnable
Host HOST_C10 (Virtual Wire) to device Enable (VWHC10OE) 0b: Disable HOST_C10 reporting (HOST_C10 ind...
Definition: EspiConfig.h:70
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_ESPI_CONFIG::EspiPmHAE
UINT32 EspiPmHAE
Hardware Autonomous Enable (HAE) If set to TRUE, then the IP may request a PG whenever it is idle.
Definition: EspiConfig.h:82
PCH_ESPI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: EspiConfig.h:52
PCH_ESPI_CONFIG
This structure contains the policies which are related to ESPI.
Definition: EspiConfig.h:51
PCH_ESPI_CONFIG::BmeMasterSlaveEnabled
UINT32 BmeMasterSlaveEnabled
eSPI host and device BME settings.
Definition: EspiConfig.h:64
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): EspiLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
EspiLib.h File Reference

Header file for PchEspiLib. More...

Go to the source code of this file.

Functions

BOOLEAN | IsEspiSecondSlaveSupported (VOID)
Checks if there's second device connected under CS#1. More...
BOOLEAN | IsEspiSlaveChannelSupported (UINT8 SlaveId, UINT8 ChannelNumber)
Checks in device General Capabilities register if it supports channel with requested number. More...
BOOLEAN | IsEspiEnabled (VOID)
Is eSPI enabled in strap. More...
EFI_STATUS | PchEspiSlaveGetConfig (IN UINT32 SlaveId, IN UINT32 SlaveAddress, OUT UINT32 *OutData)
Get configuration from eSPI device. More...
EFI_STATUS | PchEspiSlaveSetConfig (IN UINT32 SlaveId, IN UINT32 SlaveAddress, IN UINT32 InData)
Set eSP device configuration. More...
EFI_STATUS | PchEspiSlaveGetStatus (IN UINT32 SlaveId, OUT UINT16 *OutData)
Get status from eSPI device. More...
EFI_STATUS | PchEspiSlaveInBandReset (IN UINT32 SlaveId)
eSPI device in-band reset More...
EFI_STATUS | PchEspiSlaveChannelReset (IN UINT8 SlaveId, IN UINT8 ChannelNumber)
eSPI Device channel reset helper function More...

Detailed Description

Header file for PchEspiLib.

All function in this library is available for PEI, DXE, and SMM,

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file EspiLib.h.

Function Documentation

◆ IsEspiEnabled()

BOOLEAN IsEspiEnabled ( VOID )

Is eSPI enabled in strap.

Return values
TRUE | Espi is enabled in strap
FALSE | Espi is disabled in strap

◆ IsEspiSecondSlaveSupported()

BOOLEAN IsEspiSecondSlaveSupported ( VOID )

Checks if there's second device connected under CS#1.

Return values
TRUE | There's second device
FALSE | There's no second device

◆ IsEspiSlaveChannelSupported()

BOOLEAN IsEspiSlaveChannelSupported | ( | UINT8 | SlaveId,
 |  | UINT8 | ChannelNumber
 | ) |  |

Checks in device General Capabilities register if it supports channel with requested number.

Parameters
[in] | SlaveId | Id of device to check
[in] | ChannelNumber | Number of channel of which to check
Return values
TRUE | Channel with requested number is supported by device
FALSE | Channel with requested number is not supported by device

◆ PchEspiSlaveChannelReset()

EFI_STATUS PchEspiSlaveChannelReset | ( | IN UINT8 | SlaveId,
 |  | IN UINT8 | ChannelNumber
 | ) |  |

eSPI Device channel reset helper function

Parameters
[in] | SlaveId | eSPI device ID
[in] | ChannelNumber | Number of channel to reset
Return values
EFI_SUCCESS | Operation succeeded
EFI_UNSUPPORTED | Device doesn't support that channel or invalid number specified
EFI_TIMEOUT | Operation has timeouted

◆ PchEspiSlaveGetConfig()

EFI_STATUS PchEspiSlaveGetConfig | ( | IN UINT32 | SlaveId,
 |  | IN UINT32 | SlaveAddress,
 |  | OUT UINT32 * | OutData
 | ) |  |

Get configuration from eSPI device.

Parameters
[in] | SlaveId | eSPI device ID
[in] | SlaveAddress | device Configuration Register Address
[out] | OutData | Configuration data read
Return values
EFI_SUCCESS | Operation succeed
EFI_INVALID_PARAMETER | device ID is not supported
EFI_INVALID_PARAMETER | device ID is not supported or SlaveId 1 is used in PchLp
EFI_INVALID_PARAMETER | device configuration register address exceed maximum allowed
EFI_INVALID_PARAMETER | device configuration register address is not DWord aligned
EFI_DEVICE_ERROR | Error in SCRS during polling stage of operation

◆ PchEspiSlaveGetStatus()

EFI_STATUS PchEspiSlaveGetStatus | ( | IN UINT32 | SlaveId,
 |  | OUT UINT16 * | OutData
 | ) |  |

Get status from eSPI device.

Parameters
[in] | SlaveId | eSPI device ID
[out] | OutData | Configuration data read
Return values
EFI_SUCCESS | Operation succeed
EFI_INVALID_PARAMETER | Device ID is not supported or SlaveId 1 is used in PchLp
EFI_DEVICE_ERROR | Error in SCRS during polling stage of operation

◆ PchEspiSlaveInBandReset()

EFI_STATUS PchEspiSlaveInBandReset ( IN UINT32 SlaveId )

eSPI device in-band reset

Parameters
[in] SlaveId eSPI device ID
Return values
EFI_SUCCESS | Operation succeed
EFI_INVALID_PARAMETER | Device ID is not supported or SlaveId 1 is used in PchLp
EFI_DEVICE_ERROR | Error in SCRS during polling stage of operation

◆ PchEspiSlaveSetConfig()

EFI_STATUS PchEspiSlaveSetConfig | ( | IN UINT32 | SlaveId,
 |  | IN UINT32 | SlaveAddress,
 |  | IN UINT32 | InData
 | ) |  |

Set eSP device configuration.

Note: A Set_Configuration must always be followed by a Get_Configuration in order to ensure that the internal state of the eSPI-MC is consistent with the device register settings.

Parameters
[in] | SlaveId | eSPI device ID
[in] | SlaveAddress | Device Configuration Register Address
[in] | InData | Configuration data to write
Return values
EFI_SUCCESS | Operation succeed
EFI_INVALID_PARAMETER | Device ID is not supported or SlaveId 1 is used in PchLp
EFI_INVALID_PARAMETER | Device configuration register address exceed maximum allowed
EFI_INVALID_PARAMETER | Device configuration register address is not DWord aligned
EFI_ACCESS_DENIED | eSPI device write to address range 0 to 0x7FF has been locked
EFI_DEVICE_ERROR | Error in SCRS during polling stage of operation
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): EspiLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
EspiLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchEspiLib.
3 All function in this library is available for PEI, DXE, and SMM,
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2014 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _ESPI_LIB_H_
38 #define _ESPI_LIB_H_
39
40 /**
41 Checks if there's second device connected under CS#1
42
43 @retval TRUE There's second device
44 @retval FALSE There's no second device
45 **/
46 BOOLEAN
47 IsEspiSecondSlaveSupported (
48 VOID
49 );
50
51 /**
52 Checks in device General Capabilities register if it supports channel with requested number
53
54 @param[in] SlaveId Id of device to check
55 @param[in] ChannelNumber Number of channel of which to check
56
57 @retval TRUE Channel with requested number is supported by device
58 @retval FALSE Channel with requested number is not supported by device
59 **/
60 BOOLEAN
61 IsEspiSlaveChannelSupported (
62 UINT8 SlaveId,
63 UINT8 ChannelNumber
64 );
65
66 /**
67 Is eSPI enabled in strap.
68
69 @retval TRUE Espi is enabled in strap
70 @retval FALSE Espi is disabled in strap
71 **/
72 BOOLEAN
73 IsEspiEnabled (
74 VOID
75 );
76
77 /**
78 Get configuration from eSPI device
79
80 @param[in] SlaveId eSPI device ID
81 @param[in] SlaveAddress device Configuration Register Address
82 @param[out] OutData Configuration data read
83
84 @retval EFI_SUCCESS Operation succeed
85 @retval EFI_INVALID_PARAMETER device ID is not supported
86 @retval EFI_INVALID_PARAMETER device ID is not supported or SlaveId 1 is used in PchLp
87 @retval EFI_INVALID_PARAMETER device configuration register address exceed maximum allowed
88 @retval EFI_INVALID_PARAMETER device configuration register address is not DWord aligned
89 @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
90 **/
91 EFI_STATUS
92 PchEspiSlaveGetConfig (
93 IN UINT32 SlaveId,
94 IN UINT32 SlaveAddress,
95 OUT UINT32 *OutData
96 );
97
98 /**
99 Set eSP device configuration
100
101 Note: A Set_Configuration must always be followed by a Get_Configuration in order to ensure
102 that the internal state of the eSPI-MC is consistent with the device register settings.
103
104 @param[in] SlaveId eSPI device ID
105 @param[in] SlaveAddress Device Configuration Register Address
106 @param[in] InData Configuration data to write
107
108 @retval EFI_SUCCESS Operation succeed
109 @retval EFI_INVALID_PARAMETER Device ID is not supported or SlaveId 1 is used in PchLp
110 @retval EFI_INVALID_PARAMETER Device configuration register address exceed maximum allowed
111 @retval EFI_INVALID_PARAMETER Device configuration register address is not DWord aligned
112 @retval EFI_ACCESS_DENIED eSPI device write to address range 0 to 0x7FF has been locked
113 @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
114 **/
115 EFI_STATUS
116 PchEspiSlaveSetConfig (
117 IN UINT32 SlaveId,
118 IN UINT32 SlaveAddress,
119 IN UINT32 InData
120 );
121
122 /**
123 Get status from eSPI device
124
125 @param[in] SlaveId eSPI device ID
126 @param[out] OutData Configuration data read
127
128 @retval EFI_SUCCESS Operation succeed
129 @retval EFI_INVALID_PARAMETER Device ID is not supported or SlaveId 1 is used in PchLp
130 @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
131 **/
132 EFI_STATUS
133 PchEspiSlaveGetStatus (
134 IN UINT32 SlaveId,
135 OUT UINT16 *OutData
136 );
137
138 /**
139 eSPI device in-band reset
140
141 @param[in] SlaveId eSPI device ID
142
143 @retval EFI_SUCCESS Operation succeed
144 @retval EFI_INVALID_PARAMETER Device ID is not supported or SlaveId 1 is used in PchLp
145 @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
146 **/
147 EFI_STATUS
148 PchEspiSlaveInBandReset (
149 IN UINT32 SlaveId
150 );
151
152 /**
153 eSPI Device channel reset helper function
154
155 @param[in] SlaveId eSPI device ID
156 @param[in] ChannelNumber Number of channel to reset
157
158 @retval EFI_SUCCESS Operation succeeded
159 @retval EFI_UNSUPPORTED Device doesn't support that channel or invalid number specified
160 @retval EFI_TIMEOUT Operation has timeouted
161 **/
162 EFI_STATUS
163 PchEspiSlaveChannelReset (
164 IN UINT8 SlaveId,
165 IN UINT8 ChannelNumber
166 );
167
168 #endif // _ESPI_LIB_H_
PchEspiSlaveSetConfig
EFI_STATUS PchEspiSlaveSetConfig(IN UINT32 SlaveId, IN UINT32 SlaveAddress, IN UINT32 InData)
Set eSP device configuration.
IsEspiEnabled
BOOLEAN IsEspiEnabled(VOID)
Is eSPI enabled in strap.
PchEspiSlaveGetConfig
EFI_STATUS PchEspiSlaveGetConfig(IN UINT32 SlaveId, IN UINT32 SlaveAddress, OUT UINT32 *OutData)
Get configuration from eSPI device.
PchEspiSlaveChannelReset
EFI_STATUS PchEspiSlaveChannelReset(IN UINT8 SlaveId, IN UINT8 ChannelNumber)
eSPI Device channel reset helper function
IsEspiSecondSlaveSupported
BOOLEAN IsEspiSecondSlaveSupported(VOID)
Checks if there's second device connected under CS#1.
PchEspiSlaveGetStatus
EFI_STATUS PchEspiSlaveGetStatus(IN UINT32 SlaveId, OUT UINT16 *OutData)
Get status from eSPI device.
PchEspiSlaveInBandReset
EFI_STATUS PchEspiSlaveInBandReset(IN UINT32 SlaveId)
eSPI device in-band reset
IsEspiSlaveChannelSupported
BOOLEAN IsEspiSlaveChannelSupported(UINT8 SlaveId, UINT8 ChannelNumber)
Checks in device General Capabilities register if it supports channel with requested number.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FiaAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
FiaAccessLib.h File Reference

Header file for FiaAccessLib. More...

Go to the source code of this file.

Enumerations

enum FIA_INDEX
This enumartion contains all of the FIA instances which can be accessed with this library. More...

Functions

UINT32 | FiaGetMaxLosRegister (FIA_INDEX FiaIndex)
Returns number of FIA LOS registers used. More...
UINT32 | FiaGetLos (FIA_INDEX FiaIndex, UINT32 LosIndex)
Get FIA LOS register value. More...

Detailed Description

Header file for FiaAccessLib.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FiaAccessLib.h.

Enumeration Type Documentation

◆ FIA_INDEX

enum FIA_INDEX

This enumartion contains all of the FIA instances which can be accessed with this library.

Note that some systems might not contain particular FIA instance and the return value of the function might be invalid if called with such index.

Definition at line 46 of file FiaAccessLib.h.

Function Documentation

◆ FiaGetLos()

UINT32 FiaGetLos | ( | FIA_INDEX | FiaIndex,
 |  | UINT32 | LosIndex
 | ) |  |

Get FIA LOS register value.

Parameters
[in] | FiaIndex | FIA index to specify FIA instance
[in] | LosIndex | LOS FIA register index
Returns
LOS FIA register value

◆ FiaGetMaxLosRegister()

UINT32 FiaGetMaxLosRegister ( FIA_INDEX FiaIndex )

Returns number of FIA LOS registers used.

Parameters
[in] FiaIndex FIA index to specify FIA instance
Returns
Number of FIA LOS registers used
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FiaAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
FiaAccessLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for FiaAccessLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FIA_ACCESS_LIB_H_
36 #define _FIA_ACCESS_LIB_H_
37
38 /**
39 This enumartion contains all of the
40 FIA instances which can be accessed with
41 this library. Note that some systems might
42 not contain particular FIA instance and the
43 return value of the function might be invalid
44 if called with such index.
45 **/
46 typedef enum {
47 FiaIndexFia,
48 FiaIndexFiaU,
49 FiaIndexFiaPgs,
50 FiaIndexFiaPd,
51 FiaIndexFiaX
52 } FIA_INDEX;
53
54 /**
55 Returns number of FIA LOS registers used
56
57 @param[in] FiaIndex FIA index to specify FIA instance
58
59 @return Number of FIA LOS registers used
60 **/
61 UINT32
62 FiaGetMaxLosRegister (
63 FIA_INDEX FiaIndex
64 );
65
66 /**
67 Get FIA LOS register value
68
69 @param[in] FiaIndex FIA index to specify FIA instance
70 @param[in] LosIndex LOS FIA register index
71
72 @return LOS FIA register value
73 **/
74 UINT32
75 FiaGetLos (
76 FIA_INDEX FiaIndex,
77 UINT32 LosIndex
78 );
79
80 #endif // _FIA_ACCESS_LIB_H_
FiaGetMaxLosRegister
UINT32 FiaGetMaxLosRegister(FIA_INDEX FiaIndex)
Returns number of FIA LOS registers used.
FIA_INDEX
FIA_INDEX
This enumartion contains all of the FIA instances which can be accessed with this library.
Definition: FiaAccessLib.h:46
FiaGetLos
UINT32 FiaGetLos(FIA_INDEX FiaIndex, UINT32 LosIndex)
Get FIA LOS register value.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FivrConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Classes | Macros | Enumerations
FivrConfig.h File Reference

PCH FIVR policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration. More...
struct | FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration. More...
struct | PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings. More...

Macros

#define PCH_FIVR_CONFIG_REVISION 2
Revision 1: - Initial version. More...

Enumerations

enum FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.

Detailed Description

PCH FIVR policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FivrConfig.h.

Macro Definition Documentation

◆ PCH_FIVR_CONFIG_REVISION

#define PCH_FIVR_CONFIG_REVISION 2

Revision 1: - Initial version.

Revision 2: - Added BypassFivrConfig

Definition at line 42 of file FivrConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FivrConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
FivrConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH FIVR policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FIVR_CONFIG_H_
36 #define _FIVR_CONFIG_H_
37
38 /**
39 <b>Revision 1</b>: - Initial version.
40 <b>Revision 2</b>: - Added BypassFivrConfig
41 **/
42 #define PCH_FIVR_CONFIG_REVISION 2
43 extern EFI_GUID gFivrConfigGuid;
44
45 #pragma pack (push,1)
46
47 /**
48 Rail support in S0ix and Sx
49 Settings other than FivrRailDisabled can be OR'ed
50 **/
51 typedef enum {
52 FivrRailDisabled = 0,
53 FivrRailInS0i1S0i2 = BIT0,
54 FivrRailInS0i3 = BIT1,
55 FivrRailInS3 = BIT2,
56 FivrRailInS4 = BIT3,
57 FivrRailInS5 = BIT4,
58 FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
59 FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
60 FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
61 } FIVR_RAIL_SX_STATE;
62
63 typedef enum {
64 FivrRetentionActive = BIT0,
65 FivrNormActive = BIT1,
66 FivrMinActive = BIT2,
67 FivrMinRetention = BIT3
68 } FIVR_RAIL_SUPPORTED_VOLTAGE;
69
70 /**
71 Structure for V1p05/Vnn VR rail configuration
72 **/
73 typedef struct {
74 /**
75 Mask to enable the usage of external VR rail in specific S0ix or Sx states
76 Use values from FIVR_RAIL_SX_STATE
77 The default is <b>FivrRailDisabled</b>.
78 **/
79 UINT32 EnabledStates : 6;
80
81 /**
82 VR rail voltage value that will be used in S0i2/S0i3 states.
83 This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
84 The default for Vnn is set to <b>420 - 1050 mV</b>.
85 **/
86 UINT32 Voltage : 11;
87 /**
88 @deprecated
89 THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
90 VR rail Icc Max Value
91 Granularity of this setting is 1mA and maximal possible value is 500mA
92 The default is <b> 0mA </b>.
93 **/
94 UINT32 IccMax : 8;
95 /**
96 UINT32 Alignement
97 **/
98 UINT32 RsvdBits1 : 7;
99 /**
100 This register holds the control hold off values to be used when
101 changing the rail control for external bypass value in us
102 **/
103 UINT32 CtrlRampTmr : 8;
104
105 /**
106 Mask to set the supported configuration in VR rail.
107 Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
108 **/
109 UINT32 SupportedVoltageStates : 4;
110
111 /**
112 VR rail Icc Maximum Value
113 Granularity of this setting is 1mA and maximal possible value is 500mA
114 The default is <b> 0mA </b>.
115 **/
116 UINT32 IccMaximum : 16;
117 /**
118 UINT32 Alignment
119 **/
120 UINT32 RsvdBits2 : 4;
121
122 } FIVR_EXT_RAIL_CONFIG;
123
124
125 /**
126 Structure for VCCIN_AUX voltage rail configuration
127 **/
128 typedef struct {
129 /**
130 Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
131 Voltage transition time required by motherboard voltage regulator when PCH changes
132 the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
133 This field has 1us resolution.
134 When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
135 The default is <b> 0xC </b>.
136 **/
137 UINT8 LowToHighCurModeVolTranTime;
138
139 /**
140 Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
141 Voltage transition time required by motherboard voltage regulator when PCH changes
142 the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
143 This field has 1us resolution.
144 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
145 The default is <b> 0x36 </b>.
146 **/
147 UINT8 RetToHighCurModeVolTranTime;
148
149 /**
150 Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
151 Voltage transition time required by motherboard voltage regulator when PCH changes
152 the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
153 This field has 1us resolution.
154 When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
155 The default is <b> 0x2B </b>.
156 **/
157 UINT8 RetToLowCurModeVolTranTime;
158 UINT8 RsvdByte1;
159 /**
160 Transition time in microseconds from Off (0V) to High Current Mode Voltage.
161 Voltage transition time required by motherboard voltage regulator when PCH changes
162 the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
163 This field has 1us resolution.
164 0 = Transition to 0V is disabled
165 Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
166 in all S0 & Sx power states after initial start up on G3 exit
167 The default is <b> 0x96 </b>.
168 **/
169 UINT32 OffToHighCurModeVolTranTime : 11;
170 UINT32 RsvdBits1 : 21;
171 } FIVR_VCCIN_AUX_CONFIG;
172
173 /**
174 The PCH_FIVR_CONFIG block describes FIVR settings.
175 **/
176 typedef struct {
177 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
178 /**
179 External V1P05 VR rail configuration.
180 **/
181 FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
182 /**
183 External Vnn VR rail configuration.
184 **/
185 FIVR_EXT_RAIL_CONFIG ExtVnnRail;
186 /**
187 Additional External Vnn VR rail configuration that will get applied
188 in Sx entry SMI callback. Required only if External Vnn VR
189 needs different settings for Sx than those specified in ExtVnnRail.
190 **/
191 FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
192 /**
193 VCCIN_AUX voltage rail configuration.
194 **/
195 FIVR_VCCIN_AUX_CONFIG VccinAux;
196
197 /**
198 Enable/Disable FIVR Dynamic Power Management
199 Default is <b> 1 </b>.
200 **/
201 UINT32 FivrDynPm : 1;
202 /**
203 Enable/Disable Bypass of FIVR configuration
204 Default is <b> 0 </b>.
205 **/
206 UINT32 BypassFivrConfig : 1;
207 UINT32 RsvdBits2 : 30;
208 } PCH_FIVR_CONFIG;
209
210 #pragma pack (pop)
211
212 #endif // _FIVR_CONFIG_H_
PCH_FIVR_CONFIG::BypassFivrConfig
UINT32 BypassFivrConfig
Enable/Disable Bypass of FIVR configuration Default is 0 .
Definition: FivrConfig.h:206
FIVR_EXT_RAIL_CONFIG::IccMaximum
UINT32 IccMaximum
VR rail Icc Maximum Value Granularity of this setting is 1mA and maximal possible value is 500mA The ...
Definition: FivrConfig.h:116
PCH_FIVR_CONFIG
The PCH_FIVR_CONFIG block describes FIVR settings.
Definition: FivrConfig.h:176
FIVR_EXT_RAIL_CONFIG
Structure for V1p05/Vnn VR rail configuration.
Definition: FivrConfig.h:73
FIVR_VCCIN_AUX_CONFIG::OffToHighCurModeVolTranTime
UINT32 OffToHighCurModeVolTranTime
Transition time in microseconds from Off (0V) to High Current Mode Voltage.
Definition: FivrConfig.h:169
PCH_FIVR_CONFIG::ExtV1p05Rail
FIVR_EXT_RAIL_CONFIG ExtV1p05Rail
External V1P05 VR rail configuration.
Definition: FivrConfig.h:181
PCH_FIVR_CONFIG::VccinAux
FIVR_VCCIN_AUX_CONFIG VccinAux
VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:195
PCH_FIVR_CONFIG::ExtVnnRail
FIVR_EXT_RAIL_CONFIG ExtVnnRail
External Vnn VR rail configuration.
Definition: FivrConfig.h:185
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
FIVR_VCCIN_AUX_CONFIG::RetToLowCurModeVolTranTime
UINT8 RetToLowCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
Definition: FivrConfig.h:157
FIVR_RAIL_SX_STATE
FIVR_RAIL_SX_STATE
Rail support in S0ix and Sx Settings other than FivrRailDisabled can be OR'ed.
Definition: FivrConfig.h:51
FIVR_EXT_RAIL_CONFIG::Voltage
UINT32 Voltage
VR rail voltage value that will be used in S0i2/S0i3 states.
Definition: FivrConfig.h:86
PCH_FIVR_CONFIG::FivrDynPm
UINT32 FivrDynPm
Enable/Disable FIVR Dynamic Power Management Default is 1 .
Definition: FivrConfig.h:201
FIVR_EXT_RAIL_CONFIG::CtrlRampTmr
UINT32 CtrlRampTmr
This register holds the control hold off values to be used when changing the rail control for externa...
Definition: FivrConfig.h:103
FIVR_EXT_RAIL_CONFIG::SupportedVoltageStates
UINT32 SupportedVoltageStates
Mask to set the supported configuration in VR rail.
Definition: FivrConfig.h:109
PCH_FIVR_CONFIG::ExtVnnRailSx
FIVR_EXT_RAIL_CONFIG ExtVnnRailSx
Additional External Vnn VR rail configuration that will get applied in Sx entry SMI callback.
Definition: FivrConfig.h:191
FIVR_EXT_RAIL_CONFIG::EnabledStates
UINT32 EnabledStates
Mask to enable the usage of external VR rail in specific S0ix or Sx states Use values from FIVR_RAIL_...
Definition: FivrConfig.h:79
FIVR_VCCIN_AUX_CONFIG
Structure for VCCIN_AUX voltage rail configuration.
Definition: FivrConfig.h:128
FIVR_VCCIN_AUX_CONFIG::LowToHighCurModeVolTranTime
UINT8 LowToHighCurModeVolTranTime
Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:137
FIVR_EXT_RAIL_CONFIG::IccMax
UINT32 IccMax
Definition: FivrConfig.h:94
FIVR_VCCIN_AUX_CONFIG::RetToHighCurModeVolTranTime
UINT8 RetToHighCurModeVolTranTime
Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
Definition: FivrConfig.h:147
PCH_FIVR_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FivrConfig.h:177
FIVR_EXT_RAIL_CONFIG::RsvdBits2
UINT32 RsvdBits2
UINT32 Alignment.
Definition: FivrConfig.h:120
FIVR_EXT_RAIL_CONFIG::RsvdBits1
UINT32 RsvdBits1
UINT32 Alignement.
Definition: FivrConfig.h:98
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashProtectionConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
Classes
FlashProtectionConfig.h File Reference

FlashProtection policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PROTECTED_RANGE
Protected Flash Range. More...
struct | PCH_FLASH_PROTECTION_CONFIG
The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the Protected Ranges are enabled. More...

Detailed Description

FlashProtection policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FlashProtectionConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashProtectionConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
FlashProtectionConfig.h
Go to the documentation of this file.
1 /** @file
2 FlashProtection policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FLASH_PROTECTION_CONFIG_H_
36 #define _FLASH_PROTECTION_CONFIG_H_
37
38 #define PCH_FLASH_PROTECTION_CONFIG_REVISION 1
39 extern EFI_GUID gFlashProtectionConfigGuid;
40
41 #pragma pack (push,1)
42
43 //
44 // Flash Protection Range Register
45 //
46 #define PCH_FLASH_PROTECTED_RANGES 5
47
48 /**
49 Protected Flash Range
50 **/
51 typedef struct {
52 UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
53 UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
54 UINT32 RsvdBits : 30; ///< Reserved
55 /**
56 The address of the upper limit of protection
57 This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
58 **/
59 UINT16 ProtectedRangeLimit;
60 /**
61 The address of the upper limit of protection
62 This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
63 **/
64 UINT16 ProtectedRangeBase;
65 } PROTECTED_RANGE;
66
67 /**
68 The PCH provides a method for blocking writes and reads to specific ranges
69 in the SPI flash when the Protected Ranges are enabled.
70 PROTECTED_RANGE is used to specify if flash protection are enabled,
71 the write protection enable bit and the read protection enable bit,
72 and to specify the upper limit and lower base for each register
73 Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
74 and set the limit and base accordingly.
75 **/
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78 PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
79 } PCH_FLASH_PROTECTION_CONFIG;
80
81 #pragma pack (pop)
82
83 #endif // _FLASH_PROTECTION_CONFIG_H_
PROTECTED_RANGE::ReadProtectionEnable
UINT32 ReadProtectionEnable
Read is blocked by hardware. 0: Disable; 1: Enable.
Definition: FlashProtectionConfig.h:53
PROTECTED_RANGE::RsvdBits
UINT32 RsvdBits
Reserved.
Definition: FlashProtectionConfig.h:54
PROTECTED_RANGE
Protected Flash Range.
Definition: FlashProtectionConfig.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PROTECTED_RANGE::ProtectedRangeBase
UINT16 ProtectedRangeBase
The address of the upper limit of protection This is a left shifted address by 12 bits with address b...
Definition: FlashProtectionConfig.h:64
PROTECTED_RANGE::WriteProtectionEnable
UINT32 WriteProtectionEnable
Write or erase is blocked by hardware. 0: Disable; 1: Enable.
Definition: FlashProtectionConfig.h:52
PCH_FLASH_PROTECTION_CONFIG
The PCH provides a method for blocking writes and reads to specific ranges in the SPI flash when the ...
Definition: FlashProtectionConfig.h:76
PCH_FLASH_PROTECTION_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FlashProtectionConfig.h:77
PROTECTED_RANGE::ProtectedRangeLimit
UINT16 ProtectedRangeLimit
The address of the upper limit of protection This is a left shifted address by 12 bits with address b...
Definition: FlashProtectionConfig.h:59
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
FlashRegs.h File Reference

Register names for Flash registers. More...

Go to the source code of this file.

Macros

#define | B_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27)
Read ID and Read Status Clock Frequency.
#define | B_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24)
Write and Erase Clock Frequency.
#define | B_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21)
Fast Read Clock Frequency.
#define | B_FLASH_FLCOMP_FR_SUP BIT20
Fast Read Support.
#define | R_FLASH_FDBAR_FLVALSIG 0x00
Flash Valid Signature.
#define | B_FLASH_FDBAR_FCBA 0x000000FF
Flash Component Base Address.
#define | B_FLASH_FDBAR_NC 0x00000300
Number Of Components.
#define | N_FLASH_FDBAR_NC 8
Number Of Components.
#define | B_FLASH_FDBAR_FRBA 0x00FF0000
Flash Region Base Address.
#define | B_FLASH_FDBAR_NR 0x07000000
Number Of Regions.
#define | B_FLASH_FDBAR_FMBA 0x000000FF
Flash Primary Base Address.
#define | B_FLASH_FDBAR_NM 0x00000700
Number Of Masters.
#define | B_FLASH_FDBAR_FPSBA 0x00FF0000
PCH Strap Base Address, [23:16] represents [11:4].
#define | N_FLASH_FDBAR_FPSBA 16
PCH Strap base Address bit position.
#define | N_FLASH_FDBAR_FPSBA_REPR 4
PCH Strap base Address bit represents position.
#define | B_FLASH_FDBAR_PCHSL 0xFF000000
PCH Strap Length, [31:24] represents number of Dwords.
#define | N_FLASH_FDBAR_PCHSL 24
PCH Strap Length bit position.
#define | B_FLASH_FDBAR_FCPUSBA 0x00000FFC
CPU Strap Base Address [11:2].
#define | N_FLASH_FDBAR_FCPUSBA 2
CPU Strap Base Address bit position.
#define | B_FLASH_FDBAR_CPUSL 0x00FF0000
CPU Strap Length, [23:16] represents number of Dwords.
#define | N_FLASH_FDBAR_CPUSL 16
CPU Strap Length bit position.
#define | R_FLASH_FCBA_FLCOMP 0x00
Flash Components Register.
#define | B_FLASH_FLCOMP_COMP1_MASK 0xF0
Flash Component 1 Size MASK.
#define | N_FLASH_FLCOMP_COMP1 4
Flash Component 1 Size bit position.
#define | B_FLASH_FLCOMP_COMP0_MASK 0x0F
Flash Component 0 Size MASK.
#define | R_FLASH_UMAP1 0xEFC
Flash Upper Map 1.
#define | B_FLASH_UMAP1_VTBA 0x000000FF
VSCC Table Base Address.
#define | B_FLASH_UMAP1_VTL 0x0000FF00
VSCC Table Length.
#define | B_FLASH_UMAP1_MDTBA 0xFF000000
MIP Descriptor Table Base Address.
#define | N_FLASH_UMAP1_MDTBA 24
MDTBA bits position.
#define | N_FLASH_UMAP1_MDTBA_REPR 4
MDTBA address representation position.
#define | R_FLASH_STRAP_MMP0 0xC4
MMP0 Soft strap offset.
#define | B_FLASH_STRAP_MMP0 0x10
MMP0 Soft strap bit.
#define | R_FLASH_STRAP_SFDP 0xF0
PCH Soft Strap SFDP.
#define | B_FLASH_STRAP_SFDP_QIORE BIT3
Quad IO Read Enable.
#define | B_FLASH_STRAP_SFDP_QORE BIT2
Quad Output Read Enable.
#define | B_FLASH_STRAP_SFDP_DIORE BIT1
Dual IO Read Enable.
#define | B_FLASH_STRAP_SFDP_DORE BIT0
Dual Output Read Enable.
#define | R_FLASH_STRAP_DSCR_0 0x00
PCH Soft Strap 0.
#define | B_FLASH_STRAP_DSCR_0_PTT_SUPP BIT22
PTT Supported.
#define | R_PCH_SPI_STRP_GBETSN_DIS 0xC18
GBETSN_DIS strap offset.
#define | B_PCH_SPI_STRP_GBETSN_DIS BIT3
GBETSN_DIS Start Bit.
#define | R_PCH_SPI_STRP_THC_DIS 0xC20
THC_DIS strap offset.
#define | B_PCH_SPI_STRP_THC0_DIS BIT25
THC0_DIS Start Bit.
#define | B_PCH_SPI_STRP_THC1_DIS BIT26
THC1_DIS Start Bit.

Detailed Description

Register names for Flash registers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FlashRegs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
FlashRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Flash registers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2018 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _FLASH_REGS_H_
65 #define _FLASH_REGS_H_
66
67 #define B_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) ///< Read ID and Read Status Clock Frequency
68 #define N_FLASH_FLCOMP_RIDS_FREQ 27
69 #define B_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) ///< Write and Erase Clock Frequency
70 #define N_FLASH_FLCOMP_WE_FREQ 24
71 #define B_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) ///< Fast Read Clock Frequency
72 #define N_FLASH_FLCOMP_FRCF_FREQ 21
73 #define B_FLASH_FLCOMP_FR_SUP BIT20 ///< Fast Read Support.
74
75 //
76 // Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
77 //
78 #define R_FLASH_FDBAR_FLVALSIG 0x00 ///< Flash Valid Signature
79 #define V_FLASH_FDBAR_FLVALSIG 0x0FF0A55A
80 #define R_FLASH_FDBAR_FLASH_MAP0 0x04
81 #define B_FLASH_FDBAR_FCBA 0x000000FF ///< Flash Component Base Address
82 #define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
83 #define N_FLASH_FDBAR_NC 8 ///< Number Of Components
84 #define V_FLASH_FDBAR_NC_1 0x00000000
85 #define V_FLASH_FDBAR_NC_2 0x00000100
86 #define B_FLASH_FDBAR_FRBA 0x00FF0000 ///< Flash Region Base Address
87 #define B_FLASH_FDBAR_NR 0x07000000 ///< Number Of Regions
88 #define R_FLASH_FDBAR_FLASH_MAP1 0x08
89 #define B_FLASH_FDBAR_FMBA 0x000000FF ///< Flash Primary Base Address
90 #define B_FLASH_FDBAR_NM 0x00000700 ///< Number Of Masters
91 #define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
92 #define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
93 #define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
94 #define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
95 #define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
96 #define R_FLASH_FDBAR_FLASH_MAP2 0x0C
97 #define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
98 #define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
99 #define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
100 #define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
101
102 //
103 // Flash Component Base Address (FCBA) from Flash Region 0
104 //
105 #define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
106 #define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
107 #define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
108 #define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
109 #define V_FLASH_FLCOMP_COMP_512KB 0x80000
110 //
111 // Descriptor Upper Map Section from Flash Region 0
112 //
113 #define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
114 #define B_FLASH_UMAP1_VTBA 0x000000FF ///< VSCC Table Base Address
115 #define B_FLASH_UMAP1_VTL 0x0000FF00 ///< VSCC Table Length
116 #define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
117 #define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
118 #define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
119
120 //
121 // Straps location definitions
122 //
123
124 //
125 // MMP0
126 //
127 #define R_FLASH_STRAP_MMP0 0xC4 ///< MMP0 Soft strap offset
128 #define B_FLASH_STRAP_MMP0 0x10 ///< MMP0 Soft strap bit
129
130 #define R_FLASH_STRAP_SFDP 0xF0 ///< PCH Soft Strap SFDP
131 #define B_FLASH_STRAP_SFDP_QIORE BIT3 ///< Quad IO Read Enable
132 #define B_FLASH_STRAP_SFDP_QORE BIT2 ///< Quad Output Read Enable
133 #define B_FLASH_STRAP_SFDP_DIORE BIT1 ///< Dual IO Read Enable
134 #define B_FLASH_STRAP_SFDP_DORE BIT0 ///< Dual Output Read Enable
135
136 //
137 // Descriptor Record 0
138 //
139 #define R_FLASH_STRAP_DSCR_0 0x00 ///< PCH Soft Strap 0
140 #define B_FLASH_STRAP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported
141
142 #define R_PCH_SPI_STRP_GBETSN_DIS 0xC18 ///< GBETSN_DIS strap offset.
143 #define B_PCH_SPI_STRP_GBETSN_DIS BIT3 ///< GBETSN_DIS Start Bit
144
145 #define R_PCH_SPI_STRP_THC_DIS 0xC20 ///< THC_DIS strap offset.
146 #define B_PCH_SPI_STRP_THC0_DIS BIT25 ///< THC0_DIS Start Bit
147 #define B_PCH_SPI_STRP_THC1_DIS BIT26 ///< THC1_DIS Start Bit
148
149 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashRegsVer2.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
FlashRegsVer2.h File Reference

Register names for Flash registers. More...

Go to the source code of this file.

Detailed Description

Register names for Flash registers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FlashRegsVer2.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FlashRegsVer2.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
FlashRegsVer2.h
Go to the documentation of this file.
1 /** @file
2 Register names for Flash registers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2019 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _FLASH_REGS_VER2_H_
65 #define _FLASH_REGS_VER2_H_
66
67 #define V_FLASH_FLCOMP_FREQ_100MHZ 0x00
68 #define V_FLASH_FLCOMP_FREQ_50MHZ 0x01
69 #define V_FLASH_FLCOMP_FREQ_25MHZ 0x04
70 #define V_FLASH_FLCOMP_FREQ_14MHZ 0x06
71
72 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspErrorInfo.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Classes | Macros
FspErrorInfo.h File Reference

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios. More...

Go to the source code of this file.

Classes

struct FSP_ERROR_INFO_HOB
FSP Error Information Block. More...

Macros

#define FSP_ERROR_INFO_HOB_GUID
GUID value indicating the FSP error information.

Detailed Description

FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FspErrorInfo.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspErrorInfo.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
FspErrorInfo.h
Go to the documentation of this file.
1 /** @file
2 FSP Error Information HOB to describe errors inside FSP that bootloader may
3 take some actions to handle those error scenarios.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _FSP_ERROR_INFO_H_
38 #define _FSP_ERROR_INFO_H_
39
40 ///
41 /// GUID value indicating the FSP error information.
42 ///
43 #define FSP_ERROR_INFO_HOB_GUID \
44 { \
45 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
46 }
47 #define STATUS_CODE_DATA_TYPE_FSP_ERROR_GUID \
48 { \
49 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } \
50 }
51
52 #define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
53 #define FSP_ERROR_INFO_STATUS_CODE_VALUE 0
54 #define FSP_ERROR_INFO_STATUS_CODE_INSTANCE 0
55
56 ///
57 /// FSP Error Information Block.
58 ///
59 #pragma pack(1)
60 typedef struct {
61 ///
62 /// GUID HOB header.
63 ///
64 EFI_HOB_GUID_TYPE GuidHob;
65
66 ///
67 /// ReportStatusCode () type identifier.
68 ///
69 EFI_STATUS_CODE_TYPE Type;
70
71 ///
72 /// ReportStatusCode () value.
73 ///
74 EFI_STATUS_CODE_VALUE Value;
75
76 ///
77 /// ReportStatusCode () Instance number.
78 ///
79 UINT32 Instance;
80
81 ///
82 /// Optional GUID which may be used to identify
83 /// which internal component of the FSP was
84 /// executing at the time of the error.
85 ///
86 EFI_GUID CallerId;
87
88 ///
89 /// GUID identifying the nature of the fatal error.
90 ///
91 EFI_GUID ErrorType;
92
93 ///
94 /// EFI_STATUS code describing the error encountered.
95 ///
96 UINT32 Status;
97 } FSP_ERROR_INFO_HOB;
98
99 typedef struct {
100 ///
101 /// A GUID identifying the nature of the fatal error.
102 /// This GUID is platform speciic.
103 ///
104 EFI_GUID ErrorType;
105
106 ///
107 /// A code describing the error encountered.
108 ///
109 EFI_STATUS Status;
110 } FSP_ERROR_INFO;
111
112 #pragma pack()
113
114 extern GUID gFspErrorInfoHobGuid;
115
116 #endif //_FSP_ERROR_INFO_H_
FSP_ERROR_INFO_HOB::Value
EFI_STATUS_CODE_VALUE Value
ReportStatusCode () value.
Definition: FspErrorInfo.h:74
FSP_ERROR_INFO_HOB::CallerId
EFI_GUID CallerId
Optional GUID which may be used to identify which internal component of the FSP was executing at the ...
Definition: FspErrorInfo.h:86
FSP_ERROR_INFO_HOB::Instance
UINT32 Instance
ReportStatusCode () Instance number.
Definition: FspErrorInfo.h:79
FSP_ERROR_INFO_HOB::Status
UINT32 Status
EFI_STATUS code describing the error encountered.
Definition: FspErrorInfo.h:96
FSP_ERROR_INFO_HOB
FSP Error Information Block.
Definition: FspErrorInfo.h:60
FSP_ERROR_INFO_HOB::GuidHob
EFI_HOB_GUID_TYPE GuidHob
GUID HOB header.
Definition: FspErrorInfo.h:64
FSP_ERROR_INFO_HOB::Type
EFI_STATUS_CODE_TYPE Type
ReportStatusCode () type identifier.
Definition: FspErrorInfo.h:69
FSP_ERROR_INFO_HOB::ErrorType
EFI_GUID ErrorType
GUID identifying the nature of the fatal error.
Definition: FspErrorInfo.h:91
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspErrorInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
FspErrorInfoLib.h File Reference

Library to provide service for sending FSP error information to bootloader. More...

Go to the source code of this file.

Functions

EFI_STATUS | SendFspErrorInfo (IN EFI_GUID CallerId, IN EFI_GUID ErrorType, IN UINT32 Status)
Function attempts to send FSP error information to bootloader by both FSP_ERROR_INFO_HOB and ReportStatusCode service. More...
EFI_STATUS | SendFspErrorInfoStatusCode (IN EFI_GUID CallerId, IN EFI_GUID ErrorType, IN EFI_STATUS Status)
Function attempts to send FSP error information to bootloader by ReportStatusCode service. More...
EFI_STATUS | DumpFspErrorInfo (IN VOID *HobList)
Function attempts to dump all FSP error information hobs. More...
EFI_STATUS | FspErrorStatusCodeReportWorker (IN EFI_STATUS_CODE_TYPE CodeType, IN EFI_STATUS_CODE_VALUE Value, IN UINT32 Instance, IN CONST EFI_GUID *CallerId, IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL)
ReportStatusCode worker for FSP Error Information. More...

Detailed Description

Library to provide service for sending FSP error information to bootloader.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FspErrorInfoLib.h.

Function Documentation

◆ DumpFspErrorInfo()

EFI_STATUS DumpFspErrorInfo ( IN VOID * HobList )

Function attempts to dump all FSP error information hobs.

Parameters
[in] HobList - Pointer to the HOB data structure.
Return values
EFI_SUCCESS | - No FSP_ERROR_INFO_HOB found.
EFI_DEVICE_ERROR | - At least one FSP_ERROR_INFO_HOB found.

◆ FspErrorStatusCodeReportWorker()

EFI_STATUS FspErrorStatusCodeReportWorker | ( | IN EFI_STATUS_CODE_TYPE | CodeType,
 |  | IN EFI_STATUS_CODE_VALUE | Value,
 |  | IN UINT32 | Instance,
 |  | IN CONST EFI_GUID * | CallerId,
 |  | IN CONST EFI_STATUS_CODE_DATA *Data | OPTIONAL
 | ) |  |

ReportStatusCode worker for FSP Error Information.

Parameters
CodeType | Always (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
Value | Always 0
Instance | Always 0
CallerId | This optional parameter may be used to identify the caller. It may be used to identify which internal component of the FSP was executing at the time of the error.
Data | This data contains FSP error type and status code.
Return values
EFI_SUCCESS | Show error status sent by FSP successfully.
RETURN_ABORTED | Function skipped as unrelated.

◆ SendFspErrorInfo()

EFI_STATUS SendFspErrorInfo | ( | IN EFI_GUID | CallerId,
 |  | IN EFI_GUID | ErrorType,
 |  | IN UINT32 | Status
 | ) |  |

Function attempts to send FSP error information to bootloader by both FSP_ERROR_INFO_HOB and ReportStatusCode service.

Parameters
[in] | CallerId | - GUID indicates which component is executing.
[in] | ErrorType | - GUID indicates what error was encountered.
[in] | Status | - EFI_STATUS code for the error.
Return values
EFI_SUCCESS - The function always return EFI_SUCCESS.

◆ SendFspErrorInfoStatusCode()

EFI_STATUS SendFspErrorInfoStatusCode | ( | IN EFI_GUID | CallerId,
 |  | IN EFI_GUID | ErrorType,
 |  | IN EFI_STATUS | Status
 | ) |  |

Function attempts to send FSP error information to bootloader by ReportStatusCode service.

This typically is used by DXE drivers inside FSP which cannot create hob.

Parameters
[in] | CallerId | - GUID indicates which component is executing.
[in] | ErrorType | - GUID indicates what error was encountered.
[in] | Status | - EFI_STATUS code for the error.
Return values
EFI_SUCCESS - The function always return EFI_SUCCESS.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspErrorInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
FspErrorInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Library to provide service for sending FSP error information to bootloader.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_DXE_FSP_ERROR_INFO_LIB_H_
36 #define _PEI_DXE_FSP_ERROR_INFO_LIB_H_
37
38 /**
39 Function attempts to send FSP error information to bootloader
40 by both FSP_ERROR_INFO_HOB and ReportStatusCode service.
41
42 @param[in] CallerId - GUID indicates which component is executing.
43 @param[in] ErrorType - GUID indicates what error was encountered.
44 @param[in] Status - EFI_STATUS code for the error.
45
46 @retval EFI_SUCCESS - The function always return EFI_SUCCESS.
47 **/
48 EFI_STATUS
49 EFIAPI
50 SendFspErrorInfo (
51 IN EFI_GUID CallerId,
52 IN EFI_GUID ErrorType,
53 IN UINT32 Status
54 );
55
56 /**
57 Function attempts to send FSP error information to bootloader
58 by ReportStatusCode service.
59 This typically is used by DXE drivers inside FSP which cannot
60 create hob.
61
62 @param[in] CallerId - GUID indicates which component is executing.
63 @param[in] ErrorType - GUID indicates what error was encountered.
64 @param[in] Status - EFI_STATUS code for the error.
65
66 @retval EFI_SUCCESS - The function always return EFI_SUCCESS.
67 **/
68 EFI_STATUS
69 EFIAPI
70 SendFspErrorInfoStatusCode (
71 IN EFI_GUID CallerId,
72 IN EFI_GUID ErrorType,
73 IN EFI_STATUS Status
74 );
75
76 /**
77 Function attempts to dump all FSP error information hobs.
78
79 @param[in] HobList - Pointer to the HOB data structure.
80
81 @retval EFI_SUCCESS - No FSP_ERROR_INFO_HOB found.
82 @retval EFI_DEVICE_ERROR - At least one FSP_ERROR_INFO_HOB found.
83 **/
84 EFI_STATUS
85 EFIAPI
86 DumpFspErrorInfo (
87 IN VOID *HobList
88 );
89
90 /**
91 ReportStatusCode worker for FSP Error Information.
92
93 @param CodeType Always (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
94 @param Value Always 0
95 @param Instance Always 0
96 @param CallerId This optional parameter may be used to identify the caller.
97 It may be used to identify which internal component of the FSP
98 was executing at the time of the error.
99 @param Data This data contains FSP error type and status code.
100
101 @retval EFI_SUCCESS Show error status sent by FSP successfully.
102 @retval RETURN_ABORTED Function skipped as unrelated.
103
104 **/
105 EFI_STATUS
106 EFIAPI
107 FspErrorStatusCodeReportWorker (
108 IN EFI_STATUS_CODE_TYPE CodeType,
109 IN EFI_STATUS_CODE_VALUE Value,
110 IN UINT32 Instance,
111 IN CONST EFI_GUID *CallerId,
112 IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL
113 );
114 #endif //_PEI_DXE_FSP_ERROR_INFO_LIB_H_
DumpFspErrorInfo
EFI_STATUS DumpFspErrorInfo(IN VOID *HobList)
Function attempts to dump all FSP error information hobs.
SendFspErrorInfoStatusCode
EFI_STATUS SendFspErrorInfoStatusCode(IN EFI_GUID CallerId, IN EFI_GUID ErrorType, IN EFI_STATUS Status)
Function attempts to send FSP error information to bootloader by ReportStatusCode service.
SendFspErrorInfo
EFI_STATUS SendFspErrorInfo(IN EFI_GUID CallerId, IN EFI_GUID ErrorType, IN UINT32 Status)
Function attempts to send FSP error information to bootloader by both FSP_ERROR_INFO_HOB and ReportSt...
FspErrorStatusCodeReportWorker
EFI_STATUS FspErrorStatusCodeReportWorker(IN EFI_STATUS_CODE_TYPE CodeType, IN EFI_STATUS_CODE_VALUE Value, IN UINT32 Instance, IN CONST EFI_GUID *CallerId, IN CONST EFI_STATUS_CODE_DATA *Data OPTIONAL)
ReportStatusCode worker for FSP Error Information.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspmArchConfigPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros
FspmArchConfigPpi.h File Reference

Header file for FSP-M Arch Config PPI. More...

Go to the source code of this file.

Classes

struct FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI. More...

Macros

#define FSPM_ARCH_CONFIG_GUID
Global ID for the FSPM_ARCH_CONFIG_PPI.

Detailed Description

Header file for FSP-M Arch Config PPI.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file FspmArchConfigPpi.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FspmArchConfigPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
FspmArchConfigPpi.h
Go to the documentation of this file.
1 /** @file
2 Header file for FSP-M Arch Config PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
7
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License which accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef _FSPM_ARCH_CONFIG_PPI_H_
19 #define _FSPM_ARCH_CONFIG_PPI_H_
20
21 ///
22 /// Global ID for the FSPM_ARCH_CONFIG_PPI.
23 ///
24 #define FSPM_ARCH_CONFIG_GUID \
25 { \
26 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
27 }
28
29 ///
30 /// This PPI provides FSP-M Arch Config PPI.
31 ///
32 typedef struct {
33 UINT8 Revision;
34 UINT8 Reserved[3];
35 VOID *NvsBufferPtr;
36 UINT32 BootLoaderTolumSize;
37 UINT8 Reserved1[4];
38 } FSPM_ARCH_CONFIG_PPI;
39
40 extern EFI_GUID gFspmArchConfigPpiGuid;
41
42 #endif // _FSPM_ARCH_CONFIG_PPI_H_
FSPM_ARCH_CONFIG_PPI
This PPI provides FSP-M Arch Config PPI.
Definition: FspmArchConfigPpi.h:32
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FusaConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fusa
Classes | Macros
FusaConfig.h File Reference

Functional Safety policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct FUSA_CONFIG
The FUSA_CONFIG block describes the expected configuration of Functional Safety. More...

Macros

#define | FUSA_CONFIG_REVISION 3
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version. More...
#define | MSR_ENABLE_LSM 0x000002D8
LOCKSTEP ENABLE.

Detailed Description

Functional Safety policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019-2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FusaConfig.h.

Macro Definition Documentation

◆ FUSA_CONFIG_REVISION

#define FUSA_CONFIG_REVISION 3

Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Revision 3: - Add FusaConfigEnable switch, BIST scan and locksteps for module.

Definition at line 47 of file FusaConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FusaConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fusa
FusaConfig.h
Go to the documentation of this file.
1 /** @file
2 Functional Safety policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019-2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _FUSA_CONFIG_H_
37 #define _FUSA_CONFIG_H_
38
39 /**
40 Making any setup structure change after code frozen
41 will need to maintain backward compatibility, bump up
42 structure revision and update below history table\n
43 <b>Revision 1</b>: - Initial version.
44 <b>Revision 3</b>: - Add FusaConfigEnable switch, BIST scan and locksteps for module.
45 **/
46
47 #define FUSA_CONFIG_REVISION 3
48
49 extern EFI_GUID gFusaConfigGuid;
50
51 #pragma pack (push,1)
52
53 /**
54 The FUSA_CONFIG block describes the expected configuration of Functional Safety
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
58 /**
59 Enable/Disable Fusa feature on Display
60 Fusa configuration on Display <b>0: Disable</b>; 1: Enable.
61 Enable/Disable Fusa feature on IOP MCA Check
62 Fusa configuration on IOP MCA Check <b>0: Disable</b>; 1: Enable.
63 **/
64 UINT32 DisplayFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on DE: 0=Disable, 1=Enable
65 UINT32 GraphicFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on GT: 0=Disable, 1=Enable
66 UINT32 OpioFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on OPIO: 0=Disable, 1=Enable
67 UINT32 PsfFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on PSF: 0=Disable, 1=Enable
68 UINT32 IopFusaConfigEnable : 1; ///< Enable/Disable FuSa feature on IOP: 0=Disable, 1=Enable
69 UINT32 IopFusaMcaCheckEnable : 1; ///< Enable/Disable FuSa feature on IOP MCA Check Enable: 0=Disable, 1=Enable
70 UINT32 FusaConfigEnable : 1; ///< Enable/Disable FuSa feature: 0=Disable, 1=Enable
71 UINT32 FusaRunStartupArrayBist : 1; ///< Enabling this will execute startup array test during boot
72 UINT32 FusaRunStartupScanBist : 1; ///< Enabling this will execute startup scan test during boot
73 UINT32 FusaRunPeriodicScanBist : 1; ///< Enabling this will execute periodic scan test during boot
74 UINT32 Module0Lockstep : 2; ///< Enable/Disable Lockstep for Atom module 1, which has 4 cores;
75 ///< 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3;
76 ///< 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3
77 UINT32 Module1Lockstep : 2; ///< Enable/Disable Lockstep for Atom module 1, which has 4 cores;
78 ///< 0: Disable lockstep; 1: Enable lockstep for Core 0 with Core 1, Core 2 with Core 3;
79 ///< 2: Enable lockstep for Core 0 with Core 1; 3: Enable lockstep for Core 2 with Core 3
80 UINT32 RsvdBits0 : 18; ///< Reserved bits
81 } FUSA_CONFIG;
82
83 #pragma pack (pop)
84
85 /**
86
87 **/
88 #define MSR_FUSA_CONFIG 0x000002D1
89 #define MSR_TRIGGER_STARTUP_MEM_BIST 0x000002D4
90 #define MSR_STARTUP_MEM_BIST_STATUS 0x000002D5
91 #define MSR_FUSA_CAPABILITIES_A 0x000002D9
92
93 #define B_MSR_FUSA_CAP_STARTUP_SCAN_DIAGNOGSIS_MASK BIT0
94 #define B_MSR_FUSA_CAP_STARTUP_ARRAY_DIAGNOGSIS_MASK BIT1
95 #define B_MSR_FUSA_CAP_PERIODIC_ARRAY_DIAGNOGSIS_MASK BIT2
96 #define B_MSR_FUSA_CAP_LOCKSTEP_MODE_MASK BIT3
97 #define B_MSR_FUSA_CAP_PERIODIC_SCAN_DIAGNOGSIS_MASK BIT4
98
99 #define MAX_AP_COUNT 24
100
101 typedef union {
102 BOOLEAN GlobalApEnable;
103 UINT8 CurrProcessor;
104 BOOLEAN LockStepEn[MAX_AP_COUNT];
105 } LOCKSTEP_CONFIG;
106
107 /**
108 LOCKSTEP ENABLE
109 **/
110 #define MSR_ENABLE_LSM 0x000002D8
111
112 typedef enum {
113 LockstepDisabled = 0x0,
114 LockstepC0C1_C2C3 = 0x1,
115 LockstepC0C1 = 0x2,
116 LockstepC2C3 = 0x3
117 } LOCKSTEP_MODE;
118
119 #define GRT_MOD8_LPID0_APIC_ID 0x40
120 #define GRT_MOD8_LPID1_APIC_ID 0x42
121 #define GRT_MOD8_LPID2_APIC_ID 0x44
122 #define GRT_MOD8_LPID3_APIC_ID 0x46
123 #define GRT_MOD9_LPID0_APIC_ID 0x48
124 #define GRT_MOD9_LPID1_APIC_ID 0x4A
125 #define GRT_MOD9_LPID2_APIC_ID 0x4C
126 #define GRT_MOD9_LPID3_APIC_ID 0x4E
127
128 #endif // _FUSA_CONFIG_H_
FUSA_CONFIG::IopFusaMcaCheckEnable
UINT32 IopFusaMcaCheckEnable
Enable/Disable FuSa feature on IOP MCA Check Enable: 0=Disable, 1=Enable.
Definition: FusaConfig.h:69
FUSA_CONFIG::FusaRunStartupScanBist
UINT32 FusaRunStartupScanBist
Enabling this will execute startup scan test during boot.
Definition: FusaConfig.h:72
FUSA_CONFIG::Module0Lockstep
UINT32 Module0Lockstep
Enable/Disable Lockstep for Atom module 1, which has 4 cores; 0: Disable lockstep; 1: Enable lockstep...
Definition: FusaConfig.h:74
FUSA_CONFIG::OpioFusaConfigEnable
UINT32 OpioFusaConfigEnable
Enable/Disable FuSa feature on OPIO: 0=Disable, 1=Enable.
Definition: FusaConfig.h:66
FUSA_CONFIG::DisplayFusaConfigEnable
UINT32 DisplayFusaConfigEnable
Enable/Disable Fusa feature on Display Fusa configuration on Display 0: Disable; 1: Enable.
Definition: FusaConfig.h:64
FUSA_CONFIG::FusaConfigEnable
UINT32 FusaConfigEnable
Enable/Disable FuSa feature: 0=Disable, 1=Enable.
Definition: FusaConfig.h:70
FUSA_CONFIG::GraphicFusaConfigEnable
UINT32 GraphicFusaConfigEnable
Enable/Disable FuSa feature on GT: 0=Disable, 1=Enable.
Definition: FusaConfig.h:65
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
FUSA_CONFIG::FusaRunStartupArrayBist
UINT32 FusaRunStartupArrayBist
Enabling this will execute startup array test during boot.
Definition: FusaConfig.h:71
FUSA_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: FusaConfig.h:80
FUSA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: FusaConfig.h:57
FUSA_CONFIG::FusaRunPeriodicScanBist
UINT32 FusaRunPeriodicScanBist
Enabling this will execute periodic scan test during boot.
Definition: FusaConfig.h:73
FUSA_CONFIG::IopFusaConfigEnable
UINT32 IopFusaConfigEnable
Enable/Disable FuSa feature on IOP: 0=Disable, 1=Enable.
Definition: FusaConfig.h:68
FUSA_CONFIG
The FUSA_CONFIG block describes the expected configuration of Functional Safety.
Definition: FusaConfig.h:56
FUSA_CONFIG::PsfFusaConfigEnable
UINT32 PsfFusaConfigEnable
Enable/Disable FuSa feature on PSF: 0=Disable, 1=Enable.
Definition: FusaConfig.h:67
FUSA_CONFIG::Module1Lockstep
UINT32 Module1Lockstep
Enable/Disable Lockstep for Atom module 1, which has 4 cores; 0: Disable lockstep; 1: Enable lockstep...
Definition: FusaConfig.h:77
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FwStsSmbiosTable.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
FwStsSmbiosTable.h File Reference

Header file for Firmware Status Smbios Table Interface implementation. More...

#include <IndustryStandard/SmBios.h>
#include <Register/MeRegs.h>
Include dependency graph for FwStsSmbiosTable.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | MEI_DEV_STRING
MEI Device Structure. More...
struct | FWSTS_SET_RECORD
FWSTS element structure. More...
struct | FWSTS_SMBIOS_RECORD
FWSTS SMBIOS Record Structure. More...

Macros

#define MAX_FWSTS_REG 6
BIOS FWSTS Structure SMBIOS Table DEF for OEM Type FWSTS structure is defined as SMBIOS OEM type structure (from 128(0x80) through 255 (0xFF)). More...

Detailed Description

Header file for Firmware Status Smbios Table Interface implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file FwStsSmbiosTable.h.

Macro Definition Documentation

◆ MAX_FWSTS_REG

#define MAX_FWSTS_REG 6

BIOS FWSTS Structure SMBIOS Table DEF for OEM Type FWSTS structure is defined as SMBIOS OEM type structure (from 128(0x80) through 255 (0xFF)).

OEM structure type is dynamic type extracted from the "Type 14 - Group Associations Structure" to avoid conflicts introduced by hardcode OEM type. The structure can have multiple instance with the same type, each table can specify the name string (or PFA) to indicate the FWSTS for any HECI device specified for extension consideration. Version 1 - The Type14 defined in SMBIOS Specification provides OEMs to specify the arrangement or hierarchy of certain components. FWSTS Structure SMBIOS Table type can be extracted from the Type 14 "Item Type" field if the "Group Name" is "$MEI". There shall be only one Type14 structure with Group Name "$MEI".

The following is the definition for the SMBIOS table entry Type14 that will contain the

BIOS FWSTS Structure SMBIOS Table.

Offset Name Length Description

00h Type BYTE 14, Group Associations Indicator

01h Length BYTE Computed as 5 + (3 bytes for each item in the group). The user of this structure determines the number of

items as (Length -5)/3

02h Handle WORD Specify the handle of the structure, a unique 16-bit number in the range 0 to 0FFFEh (for version 2.0) or 0 to 0FEFFh

(for version 2.1 and later).

04h Group name BYTE String number of the string (L "$MEI")

describing the group

05h Item Type BYTE Item (Structure) Type of this member. The default value is 0xDB, it can be overrided

by gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType.

06h Item Handle WORD Handle corresponding to this structure

The following is the definition for the BIOS FWSTS Structure SMBIOS Table that will contain

the FWSTS values.

Offset Name Length Description

00h Type BYTE Specify the type of the structure Value is defined in SMBIOS Type 14 - Group Associations

Structure

01h Length BYTE Specify the length of the structure, starting

at the Type field. Length 6 + (25 * N)

02h Handle WORD Specify the handle of the structure, a unique 16-bit number in the range 0 to 0FFFEh (for version 2.0) or 0 to 0FEFFh

(for version 2.1 and later).

04h Version BYTE Version of implemented structure.

Current version is 1.

05h Count BYTE Number of MEI device blocks included (n).

N =1 - One set of FWSTS registers exposed

06h + 25 Component Name BYTE Number of Null terminated string. (n-1) N = 1 - One set of FWSTS registers exposed (L "MEI1" for 0:22:0, L"MEI2" for 0:22:1,

L"MEI3" for 0:22:4, L"MEI4" for 0:22:5)

07h + 25 FWSTS1 DWORD The value of 0:22:x PCI offset 0x40

(n-1) X : 0, 1, 4, 5

0Bh + 25 FWSTS2 DWORD The value of 0:22:x PCI offset 0x48

(n-1) X : 0, 1, 4, 5

0Fh + 25 FWSTS3 DWORD The value of 0:22:x PCI offset 0x60

(n-1) X : 0, 1, 4, 5

13h + 25 FWSTS4 DWORD The value of 0:22:x PCI offset 0x64

(n-1) X : 0, 1, 4, 5

17h + 25 FWSTS5 DWORD The value of 0:22:x PCI offset 0x68

(n-1) X : 0, 1, 4, 5

18h + 25 FWSTS6 DWORD The value of 0:22:x PCI offset 0x6C

(n-1) X : 0, 1, 4, 5

Definition at line 129 of file FwStsSmbiosTable.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): FwStsSmbiosTable.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
FwStsSmbiosTable.h
Go to the documentation of this file.
1 /** @file
2 Header file for Firmware Status Smbios Table Interface implementation
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FW_STS_SMBIOS_TABLE_H_
36 #define _FW_STS_SMBIOS_TABLE_H_
37
38 #include <IndustryStandard/SmBios.h>
39 #include <Register/MeRegs.h>
40
41 /**
42 BIOS FWSTS Structure SMBIOS Table DEF for OEM Type
43 FWSTS structure is defined as SMBIOS OEM type structure (from 128(0x80) through 255 (0xFF)).
44 OEM structure type is dynamic type extracted from the "Type 14 - Group Associations Structure"
45 to avoid conflicts introduced by hardcode OEM type.
46 The structure can have multiple instance with the same type, each table can specify the name string
47 (or PFA) to indicate the FWSTS for any HECI device specified for extension consideration.
48 Version 1 -
49 The Type14 defined in SMBIOS Specification provides OEMs to specify the arrangement or hierarchy
50 of certain components. FWSTS Structure SMBIOS Table type can be extracted from the
51 Type 14 "Item Type" field if the "Group Name" is "$MEI". There shall be only one Type14 structure
52 with Group Name "$MEI".
53
54 The following is the definition for the SMBIOS table entry Type14 that will contain the
55 BIOS FWSTS Structure SMBIOS Table.
56 -------------------------------------------------------------------------------------------------
57 Offset Name Length Description
58 -------------------------------------------------------------------------------------------------
59 00h Type BYTE 14, Group Associations Indicator
60 -------------------------------------------------------------------------------------------------
61 01h Length BYTE Computed as 5 + (3 bytes for each item in the group).
62 The user of this structure determines the number of
63 items as (Length -5)/3
64 -------------------------------------------------------------------------------------------------
65 02h Handle WORD Specify the handle of the structure, a unique
66 16-bit number in the range 0 to 0FFFEh
67 (for version 2.0) or 0 to 0FEFFh
68 (for version 2.1 and later).
69 -------------------------------------------------------------------------------------------------
70 04h Group name BYTE String number of the string (L "$MEI")
71 describing the group
72 -------------------------------------------------------------------------------------------------
73 05h Item Type BYTE Item (Structure) Type of this member.
74 The default value is 0xDB, it can be overrided
75 by gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType.
76 -------------------------------------------------------------------------------------------------
77 06h Item Handle WORD Handle corresponding to this structure
78 -------------------------------------------------------------------------------------------------
79
80
81 The following is the definition for the BIOS FWSTS Structure SMBIOS Table that will contain
82 the FWSTS values.
83 -------------------------------------------------------------------------------------------------
84 Offset Name Length Description
85 -------------------------------------------------------------------------------------------------
86 00h Type BYTE Specify the type of the structure Value is
87 defined in SMBIOS Type 14 - Group Associations
88 Structure
89 -------------------------------------------------------------------------------------------------
90 01h Length BYTE Specify the length of the structure, starting
91 at the Type field. Length 6 + (25 * N)
92 -------------------------------------------------------------------------------------------------
93 02h Handle WORD Specify the handle of the structure, a unique
94 16-bit number in the range 0 to 0FFFEh
95 (for version 2.0) or 0 to 0FEFFh
96 (for version 2.1 and later).
97 -------------------------------------------------------------------------------------------------
98 04h Version BYTE Version of implemented structure.
99 Current version is 1.
100 -------------------------------------------------------------------------------------------------
101 05h Count BYTE Number of MEI device blocks included (n).
102 N =1 - One set of FWSTS registers exposed
103 -------------------------------------------------------------------------------------------------
104 06h + 25 Component Name BYTE Number of Null terminated string.
105 * (n-1) N = 1 - One set of FWSTS registers exposed
106 (L "MEI1" for 0:22:0, L"MEI2" for 0:22:1,
107 L"MEI3" for 0:22:4, L"MEI4" for 0:22:5)
108 -------------------------------------------------------------------------------------------------
109 07h + 25 FWSTS1 DWORD The value of 0:22:x PCI offset 0x40
110 * (n-1) X : 0, 1, 4, 5
111 -------------------------------------------------------------------------------------------------
112 0Bh + 25 FWSTS2 DWORD The value of 0:22:x PCI offset 0x48
113 * (n-1) X : 0, 1, 4, 5
114 -------------------------------------------------------------------------------------------------
115 0Fh + 25 FWSTS3 DWORD The value of 0:22:x PCI offset 0x60
116 * (n-1) X : 0, 1, 4, 5
117 -------------------------------------------------------------------------------------------------
118 13h + 25 FWSTS4 DWORD The value of 0:22:x PCI offset 0x64
119 * (n-1) X : 0, 1, 4, 5
120 -------------------------------------------------------------------------------------------------
121 17h + 25 FWSTS5 DWORD The value of 0:22:x PCI offset 0x68
122 * (n-1) X : 0, 1, 4, 5
123 -------------------------------------------------------------------------------------------------
124 18h + 25 FWSTS6 DWORD The value of 0:22:x PCI offset 0x6C
125 * (n-1) X : 0, 1, 4, 5
126 -------------------------------------------------------------------------------------------------
127
128 **/
129 #define MAX_FWSTS_REG 6
130 #define T14_FWSTS_STRING "$MEI"
131 #define MEI1_FWSTS_STRING "MEI1"
132 #define MEI2_FWSTS_STRING "MEI2"
133 #define MEI3_FWSTS_STRING "MEI3"
134 #define MEI4_FWSTS_STRING "MEI4"
135
136 #pragma pack(1)
137
138 ///
139 /// MEI Device Structure
140 ///
141 typedef struct {
142 HECI_DEVICE HeciDev;
143 CHAR8 *String;
144 } MEI_DEV_STRING;
145
146 ///
147 /// FWSTS element structure
148 ///
149 typedef struct {
150 /**
151 Number of Null terminated string.
152 N = 1 - One set of FWSTS registers exposed
153 (L"MEI1" for 0:22:0, L"MEI2" for 0:22:1, L"MEI3" for 0:22:4)
154 **/
155 UINT8 ComponentName;
156 /**
157 The value of 0:22:x PCI offset 0x40
158 The value of 0:22:X PCI offset 0x48
159 The value of 0:22:X PCI offset 0x60
160 The value of 0:22:X PCI offset 0x64
161 The value of 0:22:X PCI offset 0x68
162 The value of 0:22:X PCI offset 0x6C
163 **/
164 UINT32 Reg[MAX_FWSTS_REG];
165 } FWSTS_SET_RECORD;
166
167 ///
168 /// FWSTS SMBIOS Record Structure
169 ///
170 typedef struct {
171 SMBIOS_STRUCTURE SmbiosHeader;
172 UINT8 Version; ///< Version of implemented structure, current version is 1
173 UINT8 Count; ///< Number of MEI device groups included
174 FWSTS_SET_RECORD Group[1];
175 } FWSTS_SMBIOS_RECORD;
176
177 #pragma pack()
178
179 #endif
FWSTS_SET_RECORD::ComponentName
UINT8 ComponentName
Number of Null terminated string.
Definition: FwStsSmbiosTable.h:155
FWSTS_SMBIOS_RECORD
FWSTS SMBIOS Record Structure.
Definition: FwStsSmbiosTable.h:170
FWSTS_SMBIOS_RECORD::Count
UINT8 Count
Number of MEI device groups included.
Definition: FwStsSmbiosTable.h:173
MeRegs.h
Register definition for ME Devices.
FWSTS_SET_RECORD
FWSTS element structure.
Definition: FwStsSmbiosTable.h:149
MEI_DEV_STRING
MEI Device Structure.
Definition: FwStsSmbiosTable.h:141
FWSTS_SMBIOS_RECORD::Version
UINT8 Version
Version of implemented structure, current version is 1.
Definition: FwStsSmbiosTable.h:172
MAX_FWSTS_REG
#define MAX_FWSTS_REG
BIOS FWSTS Structure SMBIOS Table DEF for OEM Type FWSTS structure is defined as SMBIOS OEM type stru...
Definition: FwStsSmbiosTable.h:129
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GbeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Classes
GbeConfig.h File Reference

Gigabit Ethernet policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct GBE_CONFIG
PCH intergrated GBE controller configuration settings. More...

Detailed Description

Gigabit Ethernet policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GbeConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GbeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
GbeConfig.h
Go to the documentation of this file.
1 /** @file
2 Gigabit Ethernet policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GBE_CONFIG_H_
36 #define _GBE_CONFIG_H_
37
38 #define GBE_CONFIG_REVISION 1
39 extern EFI_GUID gGbeConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 PCH intergrated GBE controller configuration settings.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 Determines if enable PCH internal GBE, 0: Disable; <b>1: Enable</b>.
50 When Enable is changed (from disabled to enabled or from enabled to disabled),
51 it needs to set LAN Disable regsiter, which might be locked by FDSWL register.
52 So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.
53 **/
54 UINT32 Enable : 1;
55 UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty of PCH internal LAN.
56 UINT32 RsvdBits0 : 30; ///< Reserved bits
57 } GBE_CONFIG;
58
59 #pragma pack (pop)
60
61 #endif // _GBE_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GBE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: GbeConfig.h:47
GBE_CONFIG::Enable
UINT32 Enable
Determines if enable PCH internal GBE, 0: Disable; 1: Enable.
Definition: GbeConfig.h:54
GBE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: GbeConfig.h:56
GBE_CONFIG
PCH intergrated GBE controller configuration settings.
Definition: GbeConfig.h:46
GBE_CONFIG::LtrEnable
UINT32 LtrEnable
0: Disable; 1: Enable LTR capabilty of PCH internal LAN.
Definition: GbeConfig.h:55
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GbeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
GbeLib.h File Reference

Header file for GbeLib. More...

Go to the source code of this file.

Functions

BOOLEAN | IsGbeRegionValid (VOID)
Check whether GbE region is valid Check SPI region directly since GbE might be disabled in SW. More...
BOOLEAN | IsGbePresent (VOID)
Check whether GBE controller is enabled in the platform. More...
BOOLEAN | IsGbeEnabled (VOID)
Checks if Gbe is Enabled or Disabled. More...
UINT8 | GbeDevNumber (VOID)
Returns Gigabit Ethernet PCI Device Number. More...
UINT8 | GbeFuncNumber (VOID)
Returns Gigabit Ethernet PCI Function Number. More...
EFI_STATUS | GbeGetLanPhyRevision (OUT UINT16 *LanPhyRevision)
Gets Phy Revision and Model Number. More...

Detailed Description

Header file for GbeLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GbeLib.h.

Function Documentation

◆ GbeDevNumber()

UINT8 GbeDevNumber ( VOID )

Returns Gigabit Ethernet PCI Device Number.

Return values
GbE device number

◆ GbeFuncNumber()

UINT8 GbeFuncNumber ( VOID )

Returns Gigabit Ethernet PCI Function Number.

Return values
GbE function number

◆ GbeGetLanPhyRevision()

EFI_STATUS GbeGetLanPhyRevision ( OUT UINT16 * LanPhyRevision )

Gets Phy Revision and Model Number.

Parameters
[out] LanPhyRevision Return Value
Returns
EFI_SUCCESS Phy Revision was obtained EFI_NOT_FOUND Gbe is disabled or not present EFI_DEVICE_ERROR Gbe class code check failed EFI_INVALID_PARAMETER When GbeBar is incorrect When Phy register or address is out of bounds

◆ IsGbeEnabled()

BOOLEAN IsGbeEnabled ( VOID )

Checks if Gbe is Enabled or Disabled.

Return values
BOOLEAN TRUE if device is enabled, FALSE otherwise.

◆ IsGbePresent()

BOOLEAN IsGbePresent ( VOID )

Check whether GBE controller is enabled in the platform.

Return values
TRUE | GbE is enabled
FALSE | GbE is disabled

◆ IsGbeRegionValid()

BOOLEAN IsGbeRegionValid ( VOID )

Check whether GbE region is valid Check SPI region directly since GbE might be disabled in SW.

Return values
TRUE | Gbe Region is valid
FALSE | Gbe Region is invalid
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GbeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GbeLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for GbeLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GBE_LIB_H_
36 #define _GBE_LIB_H_
37
38 /**
39 Check whether GbE region is valid
40 Check SPI region directly since GbE might be disabled in SW.
41
42 @retval TRUE Gbe Region is valid
43 @retval FALSE Gbe Region is invalid
44 **/
45 BOOLEAN
46 IsGbeRegionValid (
47 VOID
48 );
49
50 /**
51 Check whether GBE controller is enabled in the platform.
52
53 @retval TRUE GbE is enabled
54 @retval FALSE GbE is disabled
55 **/
56 BOOLEAN
57 IsGbePresent (
58 VOID
59 );
60
61 /**
62 Checks if Gbe is Enabled or Disabled
63
64 @retval BOOLEAN TRUE if device is enabled, FALSE otherwise.
65 **/
66 BOOLEAN
67 IsGbeEnabled (
68 VOID
69 );
70
71 /**
72 Returns Gigabit Ethernet PCI Device Number
73
74 @retval GbE device number
75 **/
76 UINT8
77 GbeDevNumber (
78 VOID
79 );
80
81 /**
82 Returns Gigabit Ethernet PCI Function Number
83
84 @retval GbE function number
85 **/
86 UINT8
87 GbeFuncNumber (
88 VOID
89 );
90
91 /**
92 Gets Phy Revision and Model Number
93
94 @param [out] LanPhyRevision Return Value
95
96 @return EFI_SUCCESS Phy Revision was obtained
97 EFI_NOT_FOUND Gbe is disabled or not present
98 EFI_DEVICE_ERROR Gbe class code check failed
99 EFI_INVALID_PARAMETER When GbeBar is incorrect
100 When Phy register or address is out of bounds
101 **/
102 EFI_STATUS
103 GbeGetLanPhyRevision (
104 OUT UINT16 *LanPhyRevision
105 );
106
107 #endif // _GBE_LIB_H_
IsGbeRegionValid
BOOLEAN IsGbeRegionValid(VOID)
Check whether GbE region is valid Check SPI region directly since GbE might be disabled in SW.
GbeDevNumber
UINT8 GbeDevNumber(VOID)
Returns Gigabit Ethernet PCI Device Number.
GbeFuncNumber
UINT8 GbeFuncNumber(VOID)
Returns Gigabit Ethernet PCI Function Number.
GbeGetLanPhyRevision
EFI_STATUS GbeGetLanPhyRevision(OUT UINT16 *LanPhyRevision)
Gets Phy Revision and Model Number.
IsGbeEnabled
BOOLEAN IsGbeEnabled(VOID)
Checks if Gbe is Enabled or Disabled.
IsGbePresent
BOOLEAN IsGbePresent(VOID)
Check whether GBE controller is enabled in the platform.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GetFsptApiParameter.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
GetFsptApiParameter.h File Reference

Library to get FSP-T API parameter. More...

Go to the source code of this file.

Functions

UINT32 SecGetFsptApiParameter (VOID)
This function gets Fspt API parameter. More...

Detailed Description

Library to get FSP-T API parameter.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GetFsptApiParameter.h.

Function Documentation

◆ SecGetFsptApiParameter()

UINT32 SecGetFsptApiParameter ( VOID )

This function gets Fspt API parameter.

Returns
The value of Fspt API parameter.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GetFsptApiParameter.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GetFsptApiParameter.h
Go to the documentation of this file.
1 /** @file
2 Library to get FSP-T API parameter.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GET_FSP_API_PARAMETER_H_
36 #define _GET_FSP_API_PARAMETER_H_
37
38 /**
39 This function gets Fspt API parameter
40
41 @return The value of Fspt API parameter.
42
43 **/
44 UINT32
45 SecGetFsptApiParameter (
46 VOID
47 );
48
49 #endif //_GET_FSP_API_PARAMETER_H_
SecGetFsptApiParameter
UINT32 SecGetFsptApiParameter(VOID)
This function gets Fspt API parameter.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GnaConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Classes
GnaConfig.h File Reference

Policy definition for GNA Config Block. More...

Go to the source code of this file.

Classes

struct GNA_CONFIG
GNA config block for configuring GNA. More...

Detailed Description

Policy definition for GNA Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GnaConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GnaConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
GnaConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for GNA Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GNA_CONFIG_H_
36 #define _GNA_CONFIG_H_
37 #pragma pack(push, 1)
38
39 #define GNA_CONFIG_REVISION 1
40 /**
41 GNA config block for configuring GNA.\n
42 <b>Revision 1</b>:
43 - Initial version.
44 **/
45 typedef struct {
46 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
47 /**
48 Offset 28:0
49 This policy enables the GNA Device (SA Device 8) if supported.
50 If FALSE, all other policies in this config block will be ignored.
51 <b>1=TRUE</b>;
52 0=FALSE.
53 **/
54 UINT32 GnaEnable : 1;
55 UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved for future use
56 } GNA_CONFIG;
57 #pragma pack(pop)
58
59 #endif // _GNA_CONFIG_H_
GNA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GnaConfig.h:46
GNA_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 28:1 :Reserved for future use.
Definition: GnaConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GNA_CONFIG::GnaEnable
UINT32 GnaEnable
Offset 28:0 This policy enables the GNA Device (SA Device 8) if supported.
Definition: GnaConfig.h:54
GNA_CONFIG
GNA config block for configuring GNA.
Definition: GnaConfig.h:45
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GnaInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
GnaInfoLib.h File Reference

This file provides GNA Public Library. More...

Go to the source code of this file.

Functions

UINT64 | GetGnaBusNumber (VOID)
GetGnaBusNumber: Get GNA Bus Number. More...
UINT64 | GetGnaDevNumber (VOID)
GetGnaDevNumber: Get Gna Dev Number. More...
UINT64 | GetGnaFuncNumber (VOID)
GetGnaFunNumber: Get Gna Fun Number. More...

Detailed Description

This file provides GNA Public Library.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GnaInfoLib.h.

Function Documentation

◆ GetGnaBusNumber()

UINT64 GetGnaBusNumber ( VOID )

GetGnaBusNumber: Get GNA Bus Number.

Return values
PCI bus number for GNA

◆ GetGnaDevNumber()

UINT64 GetGnaDevNumber ( VOID )

GetGnaDevNumber: Get Gna Dev Number.

Return values
PCI dev number for Gna

◆ GetGnaFuncNumber()

UINT64 GetGnaFuncNumber ( VOID )

GetGnaFunNumber: Get Gna Fun Number.

Return values
PCI fun number for Gna
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GnaInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GnaInfoLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides GNA Public Library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GNA_INFO_LIB_H_
36 #define _GNA_INFO_LIB_H_
37
38
39 /**
40 GetGnaBusNumber: Get GNA Bus Number
41
42 @retval PCI bus number for GNA
43 **/
44 UINT64
45 GetGnaBusNumber (
46 VOID
47 );
48
49 /**
50 GetGnaDevNumber: Get Gna Dev Number
51
52 @retval PCI dev number for Gna
53 **/
54 UINT64
55 GetGnaDevNumber (
56 VOID
57 );
58
59 /**
60 GetGnaFunNumber: Get Gna Fun Number
61
62 @retval PCI fun number for Gna
63 **/
64 UINT64
65 GetGnaFuncNumber (
66 VOID
67 );
68
69 #endif // _GNA_INFO_LIB_H_
GetGnaFuncNumber
UINT64 GetGnaFuncNumber(VOID)
GetGnaFunNumber: Get Gna Fun Number.
GetGnaBusNumber
UINT64 GetGnaBusNumber(VOID)
GetGnaBusNumber: Get GNA Bus Number.
GetGnaDevNumber
UINT64 GetGnaDevNumber(VOID)
GetGnaDevNumber: Get Gna Dev Number.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GopComponentName2.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
GopComponentName2.h File Reference

Protocol to retrieve the GOP driver version. More...

Go to the source code of this file.

Classes

struct _GOP_COMPONENT_NAME2_PROTOCOL
GOP Component protocol
This protocol will be installed by GOP driver and can be used to retrieve GOP information. More...

Typedefs

typedef EFI_STATUS(* | GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN CHAR8 *Language, OUT CHAR16 **DriverName)
GOP Component protocol for retrieving driver name.
typedef EFI_STATUS(* | GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN EFI_HANDLE ControllerHandle, IN EFI_HANDLE ChildHandle OPTIONAL, IN CHAR8 *Language, OUT CHAR16 **ControllerName)
GOP Component protocol for retrieving controller name.
typedef EFI_STATUS(* | GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN CHAR8 *Language, OUT CHAR16 **DriverVersion)
GOP Component protocol for retrieving driver version.

Detailed Description

Protocol to retrieve the GOP driver version.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GopComponentName2.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GopComponentName2.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
GopComponentName2.h
Go to the documentation of this file.
1 /** @file
2 Protocol to retrieve the GOP driver version
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GOP_COMPONENT_NAME2_H_
36 #define _GOP_COMPONENT_NAME2_H_
37
38
39 typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL;
40
41 ///
42 /// GOP Component protocol for retrieving driver name
43 ///
44 typedef
45 EFI_STATUS
46 (EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (
47 IN GOP_COMPONENT_NAME2_PROTOCOL * This,
48 IN CHAR8 *Language,
49 OUT CHAR16 **DriverName
50 );
51
52 ///
53 /// GOP Component protocol for retrieving controller name
54 ///
55 typedef
56 EFI_STATUS
57 (EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (
58 IN GOP_COMPONENT_NAME2_PROTOCOL * This,
59 IN EFI_HANDLE ControllerHandle,
60 IN EFI_HANDLE ChildHandle OPTIONAL,
61 IN CHAR8 *Language,
62 OUT CHAR16 **ControllerName
63 );
64
65 ///
66 /// GOP Component protocol for retrieving driver version
67 ///
68 typedef
69 EFI_STATUS
70 (EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (
71 IN GOP_COMPONENT_NAME2_PROTOCOL * This,
72 IN CHAR8 *Language,
73 OUT CHAR16 **DriverVersion
74 );
75
76 /**
77 GOP Component protocol\n
78 This protocol will be installed by GOP driver and can be used to retrieve GOP information.
79 **/
80 struct _GOP_COMPONENT_NAME2_PROTOCOL {
81 GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Protocol function to get driver name
82 GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Protocol function to get driver version
83 GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Protocol function to get controller name
84 CHAR8 *SupportedLanguages; ///< Number of Supported languages.
85 };
86
87 extern EFI_GUID gGopComponentName2ProtocolGuid;
88
89 #endif
_GOP_COMPONENT_NAME2_PROTOCOL::GetDriverName
GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName
Protocol function to get driver name.
Definition: GopComponentName2.h:81
GOP_COMPONENT_NAME2_GET_DRIVER_VERSION
EFI_STATUS(* GOP_COMPONENT_NAME2_GET_DRIVER_VERSION)(IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN CHAR8 *Language, OUT CHAR16 **DriverVersion)
GOP Component protocol for retrieving driver version.
Definition: GopComponentName2.h:70
GOP_COMPONENT_NAME2_GET_DRIVER_NAME
EFI_STATUS(* GOP_COMPONENT_NAME2_GET_DRIVER_NAME)(IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN CHAR8 *Language, OUT CHAR16 **DriverName)
GOP Component protocol for retrieving driver name.
Definition: GopComponentName2.h:46
GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME
EFI_STATUS(* GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME)(IN GOP_COMPONENT_NAME2_PROTOCOL *This, IN EFI_HANDLE ControllerHandle, IN EFI_HANDLE ChildHandle OPTIONAL, IN CHAR8 *Language, OUT CHAR16 **ControllerName)
GOP Component protocol for retrieving controller name.
Definition: GopComponentName2.h:57
_GOP_COMPONENT_NAME2_PROTOCOL::GetDriverVersion
GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion
Protocol function to get driver version.
Definition: GopComponentName2.h:82
_GOP_COMPONENT_NAME2_PROTOCOL
GOP Component protocol This protocol will be installed by GOP driver and can be used to retrieve GOP ...
Definition: GopComponentName2.h:80
_GOP_COMPONENT_NAME2_PROTOCOL::GetControllerName
GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName
Protocol function to get controller name.
Definition: GopComponentName2.h:83
_GOP_COMPONENT_NAME2_PROTOCOL::SupportedLanguages
CHAR8 * SupportedLanguages
Number of Supported languages.
Definition: GopComponentName2.h:84
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GopPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
GopPolicy.h File Reference

Interface definition for GopPolicy Protocol. More...

Go to the source code of this file.

Classes

struct GOP_POLICY_PROTOCOL
System Agent Graphics Output Protocol (GOP) - Policy Protocol
Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot
When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization
All functions in this protocol should be initialized by platform code basing on platform implementation
. More...

Typedefs

typedef EFI_STATUS(* | GET_PLATFORM_LID_STATUS) (OUT LID_STATUS *CurrentLidStatus)
Function to retrieve LID status.
typedef EFI_STATUS(* | GET_PLATFORM_DOCK_STATUS) (OUT DOCK_STATUS *CurrentDockStatus)
Function to retrieve Dock status.
typedef EFI_STATUS(* | GET_VBT_DATA) (OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
Function to retrieve VBT table address and size.

Detailed Description

Interface definition for GopPolicy Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GopPolicy.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GopPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
GopPolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition for GopPolicy Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GOP_POLICY_PROTOCOL_H_
36 #define _GOP_POLICY_PROTOCOL_H_
37
38
39 #define GOP_POLICY_PROTOCOL_REVISION_01 0x01
40 #define GOP_POLICY_PROTOCOL_REVISION_03 0x03
41
42 typedef enum {
43 LidClosed,
44 LidOpen,
45 LidStatusMax
46 } LID_STATUS;
47
48 typedef enum {
49 Docked,
50 UnDocked,
51 DockStatusMax
52 } DOCK_STATUS;
53
54 ///
55 /// Function to retrieve LID status
56 ///
57 typedef
58 EFI_STATUS
59 (EFIAPI *GET_PLATFORM_LID_STATUS) (
60 OUT LID_STATUS *CurrentLidStatus
61 );
62
63 ///
64 /// Function to retrieve Dock status
65 ///
66 typedef
67 EFI_STATUS
68 (EFIAPI *GET_PLATFORM_DOCK_STATUS) (
69 OUT DOCK_STATUS *CurrentDockStatus
70 );
71
72 ///
73 /// Function to retrieve VBT table address and size
74 ///
75 typedef
76 EFI_STATUS
77 (EFIAPI *GET_VBT_DATA) (
78 OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
79 OUT UINT32 *VbtSize
80 );
81
82 /**
83 System Agent Graphics Output Protocol (GOP) - Policy Protocol\n
84 Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot\n
85 When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization\n
86 All functions in this protocol should be initialized by platform code basing on platform implementation\n
87 **/
88 typedef struct {
89 UINT32 Revision; ///< Protocol revision
90 GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function to get Lid Status. Platform code should provide this function basing on design.
91 GET_VBT_DATA GetVbtData; ///< Protocol function to get Vbt Data address and size. Platform code should provide this function basing on design.
92 GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer for get platform dock status.
93 EFI_GUID GopOverrideGuid; ///< A GUID provided by BIOS in case GOP is to be overridden.
94 } GOP_POLICY_PROTOCOL;
95
96 extern EFI_GUID gGopPolicyProtocolGuid;
97 extern EFI_GUID gIntelGraphicsVbtGuid;
98
99 #endif
GET_VBT_DATA
EFI_STATUS(* GET_VBT_DATA)(OUT EFI_PHYSICAL_ADDRESS *VbtAddress, OUT UINT32 *VbtSize)
Function to retrieve VBT table address and size.
Definition: GopPolicy.h:77
GOP_POLICY_PROTOCOL::GetVbtData
GET_VBT_DATA GetVbtData
Protocol function to get Vbt Data address and size. Platform code should provide this function basing...
Definition: GopPolicy.h:91
GOP_POLICY_PROTOCOL::GetPlatformDockStatus
GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus
Function pointer for get platform dock status.
Definition: GopPolicy.h:92
GOP_POLICY_PROTOCOL::GopOverrideGuid
EFI_GUID GopOverrideGuid
A GUID provided by BIOS in case GOP is to be overridden.
Definition: GopPolicy.h:93
GOP_POLICY_PROTOCOL::GetPlatformLidStatus
GET_PLATFORM_LID_STATUS GetPlatformLidStatus
Protocol function to get Lid Status. Platform code should provide this function basing on design.
Definition: GopPolicy.h:90
GOP_POLICY_PROTOCOL::Revision
UINT32 Revision
Protocol revision.
Definition: GopPolicy.h:89
GET_PLATFORM_LID_STATUS
EFI_STATUS(* GET_PLATFORM_LID_STATUS)(OUT LID_STATUS *CurrentLidStatus)
Function to retrieve LID status.
Definition: GopPolicy.h:59
GET_PLATFORM_DOCK_STATUS
EFI_STATUS(* GET_PLATFORM_DOCK_STATUS)(OUT DOCK_STATUS *CurrentDockStatus)
Function to retrieve Dock status.
Definition: GopPolicy.h:68
GOP_POLICY_PROTOCOL
System Agent Graphics Output Protocol (GOP) - Policy Protocol Graphics Output Protocol (GOP) is a UEF...
Definition: GopPolicy.h:88
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Classes | Macros | Typedefs | Enumerations
GpioConfig.h File Reference

Header file for GpioConfig structure used by GPIO library. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct GPIO_CONFIG
GPIO configuration structure used for pin programming. More...

Macros

#define | B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F
Mask for GPIO_INT_CONFIG for interrupt source.
#define | B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0
Mask for GPIO_INT_CONFIG for interrupt type.
#define | B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F
Mask for GPIO_ELECTRICAL_CONFIG for termination value.
#define | B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3
Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock.
#define | B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC
Mask for GPIO_LOCK_CONFIG for Pad Output Lock.
#define | B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3
Mask for GPIO_OTHER_CONFIG for RxRaw1 setting.

Typedefs

typedef UINT32 | GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
typedef UINT32 | GPIO_NATIVE_PAD
GpioPad with additional native function information. More...
typedef UINT32 | GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.

Enumerations

enum | GPIO_HARDWARE_DEFAULT
enum | GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad. More...
enum | GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers. More...
enum | GPIO_DIRECTION
GPIO Direction. More...
enum | GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled. More...
enum | GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled. More...
enum | GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings. More...
enum | GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Configuration options for GPIO termination setting. More...
enum | GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock. More...
enum | GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings: More...
enum | VGPIO_CS_CONFIG
Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1. More...

Detailed Description

Header file for GpioConfig structure used by GPIO library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Note
The APIs in this file are designed to be backward compatible with previous versions. Any change in behavior of these APIs will result in newer version of the API.
Specification Reference:

Definition in file GpioConfig.h.

Typedef Documentation

◆ GPIO_NATIVE_PAD

typedef UINT32 GPIO_NATIVE_PAD

GpioPad with additional native function information.

This type is used to represent signal muxing alternatives. Platform will provide such value to identify muxing selection for given signal on a specific SOC. Please refer to the board layout

Definition at line 55 of file GpioConfig.h.

Enumeration Type Documentation

◆ GPIO_DIRECTION

enum GPIO_DIRECTION

GPIO Direction.

Enumerator
GpioDirDefault | Leave pad direction setting unmodified.
GpioDirInOut | Set pad for both output and input.
GpioDirInInvOut | Set pad for both output and input with inversion.
GpioDirIn | Set pad for input only.
GpioDirInInv | Set pad for input with inversion.
GpioDirOut | Set pad for output only.
GpioDirNone | Disable both output and input.

Definition at line 191 of file GpioConfig.h.

◆ GPIO_ELECTRICAL_CONFIG

enum GPIO_ELECTRICAL_CONFIG

GPIO Electrical Configuration Configuration options for GPIO termination setting.

Enumerator
GpioTermDefault | Leave termination setting unmodified.
GpioTermNone | none
GpioTermWpd5K | 5kOhm weak pull-down
GpioTermWpd20K | 20kOhm weak pull-down
GpioTermWpu1K | 1kOhm weak pull-up
GpioTermWpu2K | 2kOhm weak pull-up
GpioTermWpu5K | 5kOhm weak pull-up
GpioTermWpu20K | 20kOhm weak pull-up
GpioTermWpu1K2K | 1kOhm & 2kOhm weak pull-up
GpioTermNative | Native function controls pads termination This setting is applicable only to some native modes. Please check EDS to determine which native functionality can control pads termination

Definition at line 318 of file GpioConfig.h.

◆ GPIO_HARDWARE_DEFAULT

enum GPIO_HARDWARE_DEFAULT
Enumerator
GpioHardwareDefault

Leave setting unmodified.

Definition at line 138 of file GpioConfig.h.

◆ GPIO_HOSTSW_OWN

enum GPIO_HOSTSW_OWN

Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.

Depending on chosen ownership some GPIO Interrupt status register get updated and other masked. Please refer to EDS for HOSTSW_OWN register description.

Enumerator
GpioHostOwnDefault | Leave ownership value unmodified.
GpioHostOwnAcpi | Set HOST ownership to ACPI. Use this setting if pad is not going to be used by GPIO OS driver. If GPIO is configured to generate SCI/SMI/NMI then this setting must be used for interrupts to work
GpioHostOwnGpio | Set HOST ownership to GPIO Driver mode. Use this setting only if GPIO pad should be controlled by GPIO OS Driver. GPIO OS Driver will be able to control the pad if appropriate entry in ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)

Definition at line 170 of file GpioConfig.h.

◆ GPIO_INT_CONFIG

enum GPIO_INT_CONFIG

GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input enabled.

GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in EDS for details on this settings. Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge to describe an interrupt e.g. GpioIntApic | GpioIntLevel If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad. If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad. Not all GPIO are capable of generating an SMI or NMI interrupt. When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this interrupt cannot be shared and its IRQn number is not configurable. Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge). This type of GPIO Driver interrupt doesn't have any additional routing setting required to be set by BIOS. Interrupt is handled by GPIO OS Driver.

Enumerator
GpioIntDefault | Leave value of interrupt routing unmodified.
GpioIntDis | Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
GpioIntNmi | Enable NMI interrupt only.
GpioIntSmi | Enable SMI interrupt only.
GpioIntSci | Enable SCI interrupt only.
GpioIntApic | Enable IOxAPIC interrupt only.
GpioIntLevel | Set interrupt as level triggered.
GpioIntEdge | Set interrupt as edge triggered (type of edge depends on input inversion)
GpioIntLvlEdgDis | Disable interrupt trigger.
GpioIntBothEdge | Set interrupt as both edge triggered.

Definition at line 231 of file GpioConfig.h.

◆ GPIO_LOCK_CONFIG

enum GPIO_LOCK_CONFIG

GPIO LockConfiguration Set GPIO configuration lock and output state lock.

GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. By default GPIO pads will be locked unless GPIO lib is explicitly informed that certain pad is to be left unlocked. Lock settings reset is in Powergood domain. Care must be taken when using this setting as fields it locks may be reset by a different signal and can be controlled by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock an already locked pad upon request for reconfiguration

Enumerator
GpioLockDefault

Perform default action.

  • if pad is an GPO, lock configuration but leave output unlocked
  • if pad is an GPI, lock everything
  • if pad is in native, lock everything
GpioPadConfigUnlock

Leave Pad configuration unlocked.

GpioPadConfigLock

Lock Pad configuration.

GpioOutputStateUnlock

Leave Pad output control unlocked.

GpioPadUnlock

Leave both Pad configuration and output control unlocked.

GpioPadLock

Lock both Pad configuration and output control.

GpioLockTxLockCfgUnLock

Below statuses are used for return from GpioGetPadConfig function.

Tx State locked, Pad Configuration unlocked

GpioLockTxUnLockCfgLock

Tx State unlocked, Pad Configuration locked.

Definition at line 351 of file GpioConfig.h.

◆ GPIO_OTHER_CONFIG

enum GPIO_OTHER_CONFIG

Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions Supported settings:

  • RX raw override to '1' - allows to override input value to '1' This setting is applicable only if in input mode (both in GPIO and native usage). The override takes place at the internal pad state directly from buffer and before the RXINV.
Enumerator
GpioRxRaw1Default | Use default input override value.
GpioRxRaw1Dis | Don't override input.
GpioRxRaw1En | Override input to '1'.

Definition at line 383 of file GpioConfig.h.

◆ GPIO_OUTPUT_STATE

enum GPIO_OUTPUT_STATE

GPIO Output State This field is relevant only if output is enabled.

Enumerator
GpioOutDefault | Leave output value unmodified.
GpioOutLow | Set output to low.
GpioOutHigh | Set output to high.

Definition at line 205 of file GpioConfig.h.

◆ GPIO_PAD_MODE

enum GPIO_PAD_MODE

GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.

If GPIO is set to one of NativeX modes then following settings are not applicable and can be skipped:

  • Interrupt related settings
  • Host Software Ownership
  • Output/Input enabling/disabling
  • Output lock

Definition at line 152 of file GpioConfig.h.

◆ GPIO_RESET_CONFIG

enum GPIO_RESET_CONFIG

GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will be used to reset certain GPIO settings.

Refer to EDS for settings that are controllable by PadRstCfg.

Enumerator
GpioResetDefault

Leave value of pad reset unmodified.

GpioResumeReset

Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad setting will reset on:

  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
GpioHostDeepReset

Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:

  • Warm/Cold/Global reset
  • DeepSx transition
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
GpioPlatformReset

Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:

  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
  • G3
GpioDswReset

Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings will reset on:

  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold/Global reset
  • DeepSx transition
GpioGlobalReset

Global reset.

Server chipsets only. PadRstCfg = 11b = "Global reset" Pad settings will reset on:

  • Global reset
  • G3 Pad settings will not reset on:
  • S3/S4/S5 transition
  • Warm/Cold reset
  • DeepSx transition

Definition at line 253 of file GpioConfig.h.

◆ VGPIO_CS_CONFIG

enum VGPIO_CS_CONFIG

Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1.

Supported settings:

  • Chipselect CS0 and CS1
Enumerator
VgpioCs0 | Chipselect CS0.
VgpioCs1 | Chipselect CS1.

Definition at line 395 of file GpioConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
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  • Library
GpioConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioConfig structure used by GPIO library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @note
34 The APIs in this file are designed to be backward compatible with previous versions.
35 Any change in behavior of these APIs will result in newer version of the API.
36
37 @par Specification Reference:
38 **/
39 #ifndef _GPIO_CONFIG_H_
40 #define _GPIO_CONFIG_H_
41
42 #pragma pack(push, 1)
43
44 ///
45 /// For any GpioPad usage in code use GPIO_PAD type
46 ///
47 typedef UINT32 GPIO_PAD;
48
49 ///
50 /// GpioPad with additional native function information.
51 /// This type is used to represent signal muxing alternatives. Platform will provide such value to
52 /// identify muxing selection for given signal on a specific SOC.
53 /// Please refer to the board layout
54 ///
55 typedef UINT32 GPIO_NATIVE_PAD;
56
57
58 ///
59 /// For any GpioGroup usage in code use GPIO_GROUP type
60 ///
61 typedef UINT32 GPIO_GROUP;
62
63 /**
64 GPIO configuration structure used for pin programming.
65 Structure contains fields that can be used to configure pad.
66 **/
67 typedef struct {
68 /**
69 Pad Mode
70 Pad can be set as GPIO or one of its native functions.
71 When in native mode setting Direction (except Inversion), OutputState,
72 InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
73 Refer to definition of GPIO_PAD_MODE.
74 Refer to EDS for each native mode according to the pad.
75 **/
76 UINT32 PadMode : 5;
77 /**
78 Host Software Pad Ownership
79 Set pad to ACPI mode or GPIO Driver Mode.
80 Refer to definition of GPIO_HOSTSW_OWN.
81 **/
82 UINT32 HostSoftPadOwn : 2;
83 /**
84 GPIO Direction
85 Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
86 Refer to definition of GPIO_DIRECTION for supported settings.
87 **/
88 UINT32 Direction : 6;
89 /**
90 Output State
91 Set Pad output value.
92 Refer to definition of GPIO_OUTPUT_STATE for supported settings.
93 This setting takes place when output is enabled.
94 **/
95 UINT32 OutputState : 2;
96 /**
97 GPIO Interrupt Configuration
98 Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
99 This setting is applicable only if GPIO is in GpioMode with input enabled.
100 Refer to definition of GPIO_INT_CONFIG for supported settings.
101 **/
102 UINT32 InterruptConfig : 9;
103 /**
104 GPIO Power Configuration.
105 This setting controls Pad Reset Configuration.
106 Refer to definition of GPIO_RESET_CONFIG for supported settings.
107 **/
108 UINT32 PowerConfig : 8;
109 /**
110 GPIO Electrical Configuration
111 This setting controls pads termination.
112 Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
113 **/
114 UINT32 ElectricalConfig : 9;
115 /**
116 GPIO Lock Configuration
117 This setting controls pads lock.
118 Refer to definition of GPIO_LOCK_CONFIG for supported settings.
119 **/
120 UINT32 LockConfig : 4;
121 /**
122 Additional GPIO configuration
123 Refer to definition of GPIO_OTHER_CONFIG for supported settings.
124 **/
125 UINT32 OtherSettings : 9;
126
127 /**
128 Virtual GPIO eSPI Chip Select configuration
129 This setting selects between CS0 and CS1.
130 Refer to definition of VGPIO_CS_CONFIG for supported settings.
131 **/
132 UINT32 VgpioCs : 2;
133
134 UINT32 RsvdBits : 8; ///< Reserved bits for future extension
135 } GPIO_CONFIG;
136
137
138 typedef enum {
139 GpioHardwareDefault = 0x0 ///< Leave setting unmodified
140 } GPIO_HARDWARE_DEFAULT;
141
142 /**
143 GPIO Pad Mode
144 Refer to GPIO documentation on native functions available for certain pad.
145 If GPIO is set to one of NativeX modes then following settings are not applicable
146 and can be skipped:
147 - Interrupt related settings
148 - Host Software Ownership
149 - Output/Input enabling/disabling
150 - Output lock
151 **/
152 typedef enum {
153 GpioPadModeHwDefault = 0x0,
154 GpioPadModeGpio = 0x1,
155 GpioPadModeNative1 = 0x3,
156 GpioPadModeNative2 = 0x5,
157 GpioPadModeNative3 = 0x7,
158 GpioPadModeNative4 = 0x9,
159 GpioPadModeNative5 = 0xB,
160 GpioPadModeNative6 = 0xD,
161 GpioPadModeNative7 = 0xF
162 } GPIO_PAD_MODE;
163
164 /**
165 Host Software Pad Ownership modes
166 This setting affects GPIO interrupt status registers. Depending on chosen ownership
167 some GPIO Interrupt status register get updated and other masked.
168 Please refer to EDS for HOSTSW_OWN register description.
169 **/
170 typedef enum {
171 GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
172 /**
173 Set HOST ownership to ACPI.
174 Use this setting if pad is not going to be used by GPIO OS driver.
175 If GPIO is configured to generate SCI/SMI/NMI then this setting must be
176 used for interrupts to work
177 **/
178 GpioHostOwnAcpi = 0x1,
179 /**
180 Set HOST ownership to GPIO Driver mode.
181 Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
182 GPIO OS Driver will be able to control the pad if appropriate entry in
183 ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
184 **/
185 GpioHostOwnGpio = 0x3
186 } GPIO_HOSTSW_OWN;
187
188 ///
189 /// GPIO Direction
190 ///
191 typedef enum {
192 GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
193 GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
194 GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
195 GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
196 GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
197 GpioDirOut = 0x5, ///< Set pad for output only
198 GpioDirNone = 0x7 ///< Disable both output and input
199 } GPIO_DIRECTION;
200
201 /**
202 GPIO Output State
203 This field is relevant only if output is enabled
204 **/
205 typedef enum {
206 GpioOutDefault = 0x0, ///< Leave output value unmodified
207 GpioOutLow = 0x1, ///< Set output to low
208 GpioOutHigh = 0x3 ///< Set output to high
209 } GPIO_OUTPUT_STATE;
210
211 /**
212 GPIO interrupt configuration
213 This setting is applicable only if pad is in GPIO mode and has input enabled.
214 GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
215 and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
216 EDS for details on this settings.
217 Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
218 to describe an interrupt e.g. GpioIntApic | GpioIntLevel
219 If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
220 If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
221 Not all GPIO are capable of generating an SMI or NMI interrupt.
222 When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
223 interrupt cannot be shared and its IRQn number is not configurable.
224 Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
225 If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
226 exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
227 This type of GPIO Driver interrupt doesn't have any additional routing setting
228 required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
229 **/
230
231 typedef enum {
232 GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
233 GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
234 GpioIntNmi = 0x3, ///< Enable NMI interrupt only
235 GpioIntSmi = 0x5, ///< Enable SMI interrupt only
236 GpioIntSci = 0x9, ///< Enable SCI interrupt only
237 GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
238 GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
239 GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
240 GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
241 GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
242 } GPIO_INT_CONFIG;
243
244 #define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
245 #define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
246
247 /**
248 GPIO Power Configuration
249 GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
250 be used to reset certain GPIO settings.
251 Refer to EDS for settings that are controllable by PadRstCfg.
252 **/
253 typedef enum {
254 GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
255 /**
256 Resume Reset (RSMRST)
257 GPP: PadRstCfg = 00b = "Powergood"
258 GPD: PadRstCfg = 11b = "Resume Reset"
259 Pad setting will reset on:
260 - DeepSx transition
261 - G3
262 Pad settings will not reset on:
263 - S3/S4/S5 transition
264 - Warm/Cold/Global reset
265 **/
266 GpioResumeReset = 0x01,
267 /**
268 Host Deep Reset
269 PadRstCfg = 01b = "Deep GPIO Reset"
270 Pad settings will reset on:
271 - Warm/Cold/Global reset
272 - DeepSx transition
273 - G3
274 Pad settings will not reset on:
275 - S3/S4/S5 transition
276 **/
277 GpioHostDeepReset = 0x03,
278 /**
279 Platform Reset (PLTRST)
280 PadRstCfg = 10b = "GPIO Reset"
281 Pad settings will reset on:
282 - S3/S4/S5 transition
283 - Warm/Cold/Global reset
284 - DeepSx transition
285 - G3
286 **/
287 GpioPlatformReset = 0x05,
288 /**
289 Deep Sleep Well Reset (DSW_PWROK)
290 GPP: not applicable
291 GPD: PadRstCfg = 00b = "Powergood"
292 Pad settings will reset on:
293 - G3
294 Pad settings will not reset on:
295 - S3/S4/S5 transition
296 - Warm/Cold/Global reset
297 - DeepSx transition
298 **/
299 GpioDswReset = 0x07,
300 /**
301 Global reset. Server chipsets only.
302 PadRstCfg = 11b = "Global reset"
303 Pad settings will reset on:
304 - Global reset
305 - G3
306 Pad settings will not reset on:
307 - S3/S4/S5 transition
308 - Warm/Cold reset
309 - DeepSx transition
310 **/
311 GpioGlobalReset = 0x09
312 } GPIO_RESET_CONFIG;
313
314 /**
315 GPIO Electrical Configuration
316 Configuration options for GPIO termination setting
317 **/
318 typedef enum {
319 GpioTermDefault = 0x0, ///< Leave termination setting unmodified
320 GpioTermNone = 0x1, ///< none
321 GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
322 GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
323 GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
324 GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
325 GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
326 GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
327 GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
328 /**
329 Native function controls pads termination
330 This setting is applicable only to some native modes.
331 Please check EDS to determine which native functionality
332 can control pads termination
333 **/
334 GpioTermNative = 0x1F
335 } GPIO_ELECTRICAL_CONFIG;
336
337 #define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
338
339 /**
340 GPIO LockConfiguration
341 Set GPIO configuration lock and output state lock.
342 GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
343 By default GPIO pads will be locked unless GPIO lib is explicitly
344 informed that certain pad is to be left unlocked.
345 Lock settings reset is in Powergood domain. Care must be taken when using this setting
346 as fields it locks may be reset by a different signal and can be controlled
347 by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
348 functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
349 an already locked pad upon request for reconfiguration
350 **/
351 typedef enum {
352 /**
353 Perform default action
354 - if pad is an GPO, lock configuration but leave output unlocked
355 - if pad is an GPI, lock everything
356 - if pad is in native, lock everything
357 **/
358 GpioLockDefault = 0x0,
359 GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
360 GpioPadConfigLock = 0x1, ///< Lock Pad configuration
361 GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
362 GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
363 GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
364 /**
365 Below statuses are used for
366 return from GpioGetPadConfig function
367 **/
368 GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
369 GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
370 } GPIO_LOCK_CONFIG;
371
372 #define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
373 #define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
374
375 /**
376 Other GPIO Configuration
377 GPIO_OTHER_CONFIG is used for less often settings and for future extensions
378 Supported settings:
379 - RX raw override to '1' - allows to override input value to '1'
380 This setting is applicable only if in input mode (both in GPIO and native usage).
381 The override takes place at the internal pad state directly from buffer and before the RXINV.
382 **/
383 typedef enum {
384 GpioRxRaw1Default = 0x0, ///< Use default input override value
385 GpioRxRaw1Dis = 0x1, ///< Don't override input
386 GpioRxRaw1En = 0x3 ///< Override input to '1'
387 } GPIO_OTHER_CONFIG;
388
389 /**
390 Virtual GPIO eSPI Chip Select configuration
391 This setting selects between CS0 and CS1.
392 Supported settings:
393 - Chipselect CS0 and CS1
394 **/
395 typedef enum {
396 VgpioCs0 = 0x0, ///< Chipselect CS0
397 VgpioCs1 = 0x1, ///< Chipselect CS1
398 } VGPIO_CS_CONFIG;
399
400 #define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
401
402 #pragma pack(pop)
403
404 #endif //_GPIO_CONFIG_H_
GpioTermWpu5K
@ GpioTermWpu5K
5kOhm weak pull-up
Definition: GpioConfig.h:325
GpioOutDefault
@ GpioOutDefault
Leave output value unmodified.
Definition: GpioConfig.h:206
VgpioCs0
@ VgpioCs0
Chipselect CS0.
Definition: GpioConfig.h:396
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0....
Definition: GpioConfig.h:253
GpioRxRaw1Default
@ GpioRxRaw1Default
Use default input override value.
Definition: GpioConfig.h:384
GpioLockTxLockCfgUnLock
@ GpioLockTxLockCfgUnLock
Below statuses are used for return from GpioGetPadConfig function.
Definition: GpioConfig.h:368
GpioDirInInv
@ GpioDirInInv
Set pad for input with inversion.
Definition: GpioConfig.h:196
GpioOutLow
@ GpioOutLow
Set output to low.
Definition: GpioConfig.h:207
GPIO_CONFIG::Direction
UINT32 Direction
GPIO Direction Can choose between In, In with inversion, Out, both In and Out, both In with inversion...
Definition: GpioConfig.h:88
GPIO_CONFIG::PadMode
UINT32 PadMode
Pad Mode Pad can be set as GPIO or one of its native functions.
Definition: GpioConfig.h:76
GpioPadConfigUnlock
@ GpioPadConfigUnlock
Leave Pad configuration unlocked.
Definition: GpioConfig.h:359
GPIO_CONFIG::OutputState
UINT32 OutputState
Output State Set Pad output value.
Definition: GpioConfig.h:95
GpioTermWpu1K
@ GpioTermWpu1K
1kOhm weak pull-up
Definition: GpioConfig.h:323
GPIO_CONFIG::PowerConfig
UINT32 PowerConfig
GPIO Power Configuration.
Definition: GpioConfig.h:108
GPIO_CONFIG::LockConfig
UINT32 LockConfig
GPIO Lock Configuration This setting controls pads lock.
Definition: GpioConfig.h:120
GpioDirOut
@ GpioDirOut
Set pad for output only.
Definition: GpioConfig.h:197
GpioIntEdge
@ GpioIntEdge
Set interrupt as edge triggered (type of edge depends on input inversion)
Definition: GpioConfig.h:239
GpioLockTxUnLockCfgLock
@ GpioLockTxUnLockCfgLock
Tx State unlocked, Pad Configuration locked.
Definition: GpioConfig.h:369
GpioTermWpu2K
@ GpioTermWpu2K
2kOhm weak pull-up
Definition: GpioConfig.h:324
VGPIO_CS_CONFIG
VGPIO_CS_CONFIG
Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1.
Definition: GpioConfig.h:395
GpioTermNative
@ GpioTermNative
Native function controls pads termination This setting is applicable only to some native modes.
Definition: GpioConfig.h:334
GpioDirDefault
@ GpioDirDefault
Leave pad direction setting unmodified.
Definition: GpioConfig.h:192
GpioTermWpu20K
@ GpioTermWpu20K
20kOhm weak pull-up
Definition: GpioConfig.h:326
GpioTermWpd20K
@ GpioTermWpd20K
20kOhm weak pull-down
Definition: GpioConfig.h:322
GpioDirIn
@ GpioDirIn
Set pad for input only.
Definition: GpioConfig.h:195
GpioRxRaw1En
@ GpioRxRaw1En
Override input to '1'.
Definition: GpioConfig.h:386
GpioRxRaw1Dis
@ GpioRxRaw1Dis
Don't override input.
Definition: GpioConfig.h:385
GpioPadUnlock
@ GpioPadUnlock
Leave both Pad configuration and output control unlocked.
Definition: GpioConfig.h:362
GPIO_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits for future extension.
Definition: GpioConfig.h:134
GpioTermNone
@ GpioTermNone
none
Definition: GpioConfig.h:320
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:47
GPIO_OTHER_CONFIG
GPIO_OTHER_CONFIG
Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often settings and for future extensions ...
Definition: GpioConfig.h:383
GPIO_HARDWARE_DEFAULT
GPIO_HARDWARE_DEFAULT
Definition: GpioConfig.h:138
GpioIntApic
@ GpioIntApic
Enable IOxAPIC interrupt only.
Definition: GpioConfig.h:237
GPIO_DIRECTION
GPIO_DIRECTION
GPIO Direction.
Definition: GpioConfig.h:191
GpioTermWpu1K2K
@ GpioTermWpu1K2K
1kOhm & 2kOhm weak pull-up
Definition: GpioConfig.h:327
GPIO_CONFIG::ElectricalConfig
UINT32 ElectricalConfig
GPIO Electrical Configuration This setting controls pads termination.
Definition: GpioConfig.h:114
GpioTermWpd5K
@ GpioTermWpd5K
5kOhm weak pull-down
Definition: GpioConfig.h:321
GpioIntDefault
@ GpioIntDefault
Leave value of interrupt routing unmodified.
Definition: GpioConfig.h:232
GPIO_CONFIG::InterruptConfig
UINT32 InterruptConfig
GPIO Interrupt Configuration Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
Definition: GpioConfig.h:102
VgpioCs1
@ VgpioCs1
Chipselect CS1.
Definition: GpioConfig.h:397
GpioIntLevel
@ GpioIntLevel
Set interrupt as level triggered.
Definition: GpioConfig.h:238
GpioLockDefault
@ GpioLockDefault
Perform default action.
Definition: GpioConfig.h:358
GpioTermDefault
@ GpioTermDefault
Leave termination setting unmodified.
Definition: GpioConfig.h:319
GpioResumeReset
@ GpioResumeReset
Resume Reset (RSMRST) GPP: PadRstCfg = 00b = "Powergood" GPD: PadRstCfg = 11b = "Resume Reset" Pad se...
Definition: GpioConfig.h:266
GpioPadLock
@ GpioPadLock
Lock both Pad configuration and output control.
Definition: GpioConfig.h:363
GpioDswReset
@ GpioDswReset
Deep Sleep Well Reset (DSW_PWROK) GPP: not applicable GPD: PadRstCfg = 00b = "Powergood" Pad settings...
Definition: GpioConfig.h:299
GpioIntSmi
@ GpioIntSmi
Enable SMI interrupt only.
Definition: GpioConfig.h:235
GPIO_LOCK_CONFIG
GPIO_LOCK_CONFIG
GPIO LockConfiguration Set GPIO configuration lock and output state lock.
Definition: GpioConfig.h:351
GpioIntDis
@ GpioIntDis
Disable IOxAPIC/SCI/SMI/NMI interrupt generation.
Definition: GpioConfig.h:233
GPIO_PAD_MODE
GPIO_PAD_MODE
GPIO Pad Mode Refer to GPIO documentation on native functions available for certain pad.
Definition: GpioConfig.h:152
GpioHostDeepReset
@ GpioHostDeepReset
Host Deep Reset PadRstCfg = 01b = "Deep GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:277
GPIO_CONFIG::OtherSettings
UINT32 OtherSettings
Additional GPIO configuration Refer to definition of GPIO_OTHER_CONFIG for supported settings.
Definition: GpioConfig.h:125
GPIO_NATIVE_PAD
UINT32 GPIO_NATIVE_PAD
GpioPad with additional native function information.
Definition: GpioConfig.h:55
GpioGlobalReset
@ GpioGlobalReset
Global reset.
Definition: GpioConfig.h:311
GpioResetDefault
@ GpioResetDefault
Leave value of pad reset unmodified.
Definition: GpioConfig.h:254
GpioIntNmi
@ GpioIntNmi
Enable NMI interrupt only.
Definition: GpioConfig.h:234
GpioIntSci
@ GpioIntSci
Enable SCI interrupt only.
Definition: GpioConfig.h:236
GpioOutputStateUnlock
@ GpioOutputStateUnlock
Leave Pad output control unlocked.
Definition: GpioConfig.h:361
GpioHostOwnDefault
@ GpioHostOwnDefault
Leave ownership value unmodified.
Definition: GpioConfig.h:171
GpioDirInOut
@ GpioDirInOut
Set pad for both output and input.
Definition: GpioConfig.h:193
GpioHardwareDefault
@ GpioHardwareDefault
Leave setting unmodified.
Definition: GpioConfig.h:139
GPIO_HOSTSW_OWN
GPIO_HOSTSW_OWN
Host Software Pad Ownership modes This setting affects GPIO interrupt status registers.
Definition: GpioConfig.h:170
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:231
GpioPlatformReset
@ GpioPlatformReset
Platform Reset (PLTRST) PadRstCfg = 10b = "GPIO Reset" Pad settings will reset on:
Definition: GpioConfig.h:287
GPIO_OUTPUT_STATE
GPIO_OUTPUT_STATE
GPIO Output State This field is relevant only if output is enabled.
Definition: GpioConfig.h:205
GpioPadConfigLock
@ GpioPadConfigLock
Lock Pad configuration.
Definition: GpioConfig.h:360
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Configuration options for GPIO termination setting.
Definition: GpioConfig.h:318
GpioOutHigh
@ GpioOutHigh
Set output to high.
Definition: GpioConfig.h:208
GpioIntBothEdge
@ GpioIntBothEdge
Set interrupt as both edge triggered.
Definition: GpioConfig.h:241
GpioHostOwnGpio
@ GpioHostOwnGpio
Set HOST ownership to GPIO Driver mode.
Definition: GpioConfig.h:185
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:61
GPIO_CONFIG::HostSoftPadOwn
UINT32 HostSoftPadOwn
Host Software Pad Ownership Set pad to ACPI mode or GPIO Driver Mode.
Definition: GpioConfig.h:82
GpioDirInInvOut
@ GpioDirInInvOut
Set pad for both output and input with inversion.
Definition: GpioConfig.h:194
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:67
GpioDirNone
@ GpioDirNone
Disable both output and input.
Definition: GpioConfig.h:198
GPIO_CONFIG::VgpioCs
UINT32 VgpioCs
Virtual GPIO eSPI Chip Select configuration This setting selects between CS0 and CS1.
Definition: GpioConfig.h:132
GpioHostOwnAcpi
@ GpioHostOwnAcpi
Set HOST ownership to ACPI.
Definition: GpioConfig.h:178
GpioIntLvlEdgDis
@ GpioIntLvlEdgDis
Disable interrupt trigger.
Definition: GpioConfig.h:240
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioDevConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gpio
Classes
GpioDevConfig.h File Reference

GPIO device policy. More...

Go to the source code of this file.

Classes

struct GPIO_DXE_CONFIG
This structure contains the DXE policies which are related to GPIO device. More...

Detailed Description

GPIO device policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioDevConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioDevConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gpio
GpioDevConfig.h
Go to the documentation of this file.
1 /** @file
2 GPIO device policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_DEV_CONFIG_H_
36 #define _GPIO_DEV_CONFIG_H_
37
38 extern EFI_GUID gGpioDxeConfigGuid;
39
40 #define GPIO_DXE_CONFIG_REVISION 1
41
42 #pragma pack (push,1)
43
44 /**
45 This structure contains the DXE policies which are related to GPIO device.
46
47 <b>Revision 1:</b>
48 - Inital version.
49 **/
50 typedef struct {
51 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
52 /**
53 If GPIO ACPI device is not used by OS it can be hidden. In such case
54 no other device exposed to the system can reference GPIO device in one
55 of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
56 <b>0: Disable</b>; 1: Enable
57 **/
58 UINT32 HideGpioAcpiDevice : 1;
59 UINT32 RsvdBits : 31; ///< Reserved bits
60
61 } GPIO_DXE_CONFIG;
62
63 #pragma pack (pop)
64
65 #endif // _GPIO_DEV_CONFIG_H_
GPIO_DXE_CONFIG::HideGpioAcpiDevice
UINT32 HideGpioAcpiDevice
If GPIO ACPI device is not used by OS it can be hidden.
Definition: GpioDevConfig.h:58
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GPIO_DXE_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits.
Definition: GpioDevConfig.h:59
GPIO_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: GpioDevConfig.h:51
GPIO_DXE_CONFIG
This structure contains the DXE policies which are related to GPIO device.
Definition: GpioDevConfig.h:50
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
GpioLib.h File Reference

Header file for GpioLib. More...

#include <Library/GpioConfig.h>
Include dependency graph for GpioLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Enumerations

enum GPIO_PAD_OWN
Possible values of Pad Ownership If Pad is not under Host ownership then GPIO registers are not accessible by host (e.g. More...

Functions

EFI_STATUS | GpioConfigurePads (IN UINT32 NumberOfItems, IN GPIO_INIT_CONFIG *GpioInitTableAddress)
This procedure will initialize multiple GPIO pins. More...
EFI_STATUS | GpioGetPadConfig (IN GPIO_PAD GpioPad, OUT GPIO_CONFIG *GpioData)
This procedure will read multiple GPIO settings. More...
EFI_STATUS | GpioSetPadConfig (IN GPIO_PAD GpioPad, IN GPIO_CONFIG *GpioData)
This procedure will configure multiple GPIO settings. More...
EFI_STATUS | GpioSetOutputValue (IN GPIO_PAD GpioPad, IN UINT32 Value)
This procedure will set GPIO output level. More...
EFI_STATUS | GpioGetOutputValue (IN GPIO_PAD GpioPad, OUT UINT32 *OutputVal)
This procedure will get GPIO output level. More...
EFI_STATUS | GpioGetInputValue (IN GPIO_PAD GpioPad, OUT UINT32 *InputVal)
This procedure will get GPIO input level. More...
EFI_STATUS | GpioGetPadIoApicIrqNumber (IN GPIO_PAD GpioPad, OUT UINT32 *IrqNum)
This procedure will get GPIO IOxAPIC interrupt number. More...
EFI_STATUS | GpioSetInputInversion (IN GPIO_PAD GpioPad, IN UINT32 Value)
This procedure will configure GPIO input inversion. More...
EFI_STATUS | GpioGetInputInversion (IN GPIO_PAD GpioPad, OUT UINT32 *InvertState)
This procedure will get GPIO pad input inversion value. More...
EFI_STATUS | GpioSetPadInterruptConfig (IN GPIO_PAD GpioPad, IN GPIO_INT_CONFIG Value)
This procedure will set GPIO interrupt settings. More...
EFI_STATUS | GpioSetPadElectricalConfig (IN GPIO_PAD GpioPad, IN GPIO_ELECTRICAL_CONFIG Value)
This procedure will set GPIO electrical settings. More...
EFI_STATUS | GpioSetPadResetConfig (IN GPIO_PAD GpioPad, IN GPIO_RESET_CONFIG Value)
This procedure will set GPIO Reset settings. More...
EFI_STATUS | GpioGetPadResetConfig (IN GPIO_PAD GpioPad, IN GPIO_RESET_CONFIG *Value)
This procedure will get GPIO Reset settings. More...
EFI_STATUS | GpioGetHostSwOwnershipForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *HostSwRegVal)
This procedure will get GPIO Host Software Pad Ownership for certain group. More...
EFI_STATUS | GpioSetHostSwOwnershipForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 HostSwRegVal)
This procedure will get GPIO Host Software Pad Ownership for certain group. More...
EFI_STATUS | GpioGetHostSwOwnershipForPad (IN GPIO_PAD GpioPad, OUT UINT32 *PadHostSwOwn)
This procedure will get Gpio Pad Host Software Ownership. More...
EFI_STATUS | GpioSetHostSwOwnershipForPad (IN GPIO_PAD GpioPad, IN UINT32 PadHostSwOwn)
This procedure will set Gpio Pad Host Software Ownership. More...
EFI_STATUS | GpioGetPadOwnership (IN GPIO_PAD GpioPad, OUT GPIO_PAD_OWN *PadOwnVal)
This procedure will get Gpio Pad Ownership. More...
EFI_STATUS | GpioGetPadCfgLockForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockRegVal)
This procedure will check state of Pad Config Lock for pads within one group. More...
EFI_STATUS | GpioGetPadCfgLock (IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLock)
This procedure will check state of Pad Config Lock for selected pad. More...
EFI_STATUS | GpioGetPadCfgLockTxForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockTxRegVal)
This procedure will check state of Pad Config Tx Lock for pads within one group. More...
EFI_STATUS | GpioGetPadCfgLockTx (IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLockTx)
This procedure will check state of Pad Config Tx Lock for selected pad. More...
EFI_STATUS | GpioUnlockPadCfgForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToUnlock)
This procedure will clear PadCfgLock for selected pads within one group. More...
EFI_STATUS | GpioUnlockPadCfg (IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLock for selected pad. More...
EFI_STATUS | GpioLockPadCfgForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToLock)
This procedure will set PadCfgLock for selected pads within one group. More...
EFI_STATUS | GpioLockPadCfg (IN GPIO_PAD GpioPad)
This procedure will set PadCfgLock for selected pad. More...
EFI_STATUS | GpioUnlockPadCfgTxForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToUnlockTx)
This procedure will clear PadCfgLockTx for selected pads within one group. More...
EFI_STATUS | GpioUnlockPadCfgTx (IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLockTx for selected pad. More...
EFI_STATUS | GpioLockPadCfgTxForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToLockTx)
This procedure will set PadCfgLockTx for selected pads within one group. More...
EFI_STATUS | GpioLockPadCfgTx (IN GPIO_PAD GpioPad)
This procedure will set PadCfgLockTx for selected pad. More...
EFI_STATUS | GpioGetGroupToGpeDwX (IN GPIO_GROUP *GroupToGpeDw0, IN GPIO_GROUP *GroupToGpeDw1, IN GPIO_GROUP *GroupToGpeDw2)
This procedure will get Group to GPE mapping. More...
EFI_STATUS | GpioGetGroupDwToGpeDwX (OUT GPIO_GROUP *GroupToGpeDw0, OUT UINT32 *GroupDwForGpeDw0, OUT GPIO_GROUP *GroupToGpeDw1, OUT UINT32 *GroupDwForGpeDw1, OUT GPIO_GROUP *GroupToGpeDw2, OUT UINT32 *GroupDwForGpeDw2)
This procedure will get Group to GPE mapping. More...
EFI_STATUS | GpioSetGroupToGpeDwX (IN GPIO_GROUP GroupToGpeDw0, IN GPIO_GROUP GroupToGpeDw1, IN GPIO_GROUP GroupToGpeDw2)
This procedure will set Group to GPE mapping. More...
EFI_STATUS | GpioSetGroupDwToGpeDwX (IN GPIO_GROUP GroupToGpeDw0, IN UINT32 GroupDwForGpeDw0, IN GPIO_GROUP GroupToGpeDw1, IN UINT32 GroupDwForGpeDw1, IN GPIO_GROUP GroupToGpeDw2, IN UINT32 GroupDwForGpeDw2)
This procedure will set Group to GPE mapping. More...
EFI_STATUS | GpioGetGpeNumber (IN GPIO_PAD GpioPad, OUT UINT32 *GpeNumber)
This procedure will get GPE number for provided GpioPad. More...
EFI_STATUS | GpioClearGpiSmiSts (IN GPIO_PAD GpioPad)
This procedure is used to clear SMI STS for a specified Pad. More...
EFI_STATUS | GpioClearAllGpiSmiSts (VOID)
This procedure is used by Smi Dispatcher and will clear all GPI SMI Status bits. More...
EFI_STATUS | GpioDisableAllGpiSmi (VOID)
This procedure is used to disable all GPI SMI. More...
EFI_STATUS | GpioGetGpiSmiNum (IN GPIO_PAD GpioPad, OUT UINTN *GpiNum)
This procedure is used to register GPI SMI dispatch function. More...
BOOLEAN | GpioCheckFor2Tier (IN GPIO_PAD GpioPad)
This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture. More...
EFI_STATUS | GpioClearGpiGpeSts (IN GPIO_PAD GpioPad)
This procedure is used to clear GPE STS for a specified GpioPad. More...
EFI_STATUS | GpioGetGpiGpeSts (IN GPIO_PAD GpioPad, OUT BOOLEAN *GpeSts)
This procedure is used to read GPE STS for a specified Pad. More...
EFI_STATUS | GpioGetGpiSmiSts (IN GPIO_PAD GpioPad, OUT BOOLEAN *SmiSts)
This procedure is used to get SMI STS for a specified Pad. More...
EFI_STATUS | GpioLockPads (VOID)
This procedure is used to lock all GPIO pads except the ones which were requested during their configuration to be left unlocked. More...
CHAR8 * | GpioGetPadName (IN GPIO_PAD GpioPad, OUT CHAR8 *GpioNameBuffer, IN UINT32 GpioNameBufferSize)
Generates GPIO name from GpioPad. More...
CONST CHAR8 * | GpioGetGroupName (IN UINT32 GroupIndex)
Generates GPIO group name from GroupIndex. More...
EFI_STATUS | GpioMinGetPadCfgLockForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockRegVal)
Gpio Minimum Set. More...
EFI_STATUS | GpioMinGetPadCfgLockTxForGroupDw (IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockTxRegVal)
This procedure will check state of Pad Config Tx Lock for pads within one group Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTxForGroupDw), but to decrese memory footprint it was stripped from any GpioPad validation. More...
EFI_STATUS | GpioMinUnlockPadCfg (IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLock for selected pad. More...
EFI_STATUS | GpioMinGetPadCfgLockTx (IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLockTx)
This procedure will check state of Pad Config Tx Lock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTx), but to decrese memory footprint it was stripped from any GpioPad validation. More...
EFI_STATUS | GpioMinUnlockPadCfgTx (IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLockTx for selected pad. More...
EFI_STATUS | GpioMinGetPadCfgLock (IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLock)
This procedure will check state of Pad Config Lock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLock), but to decrese memory footprint it was stripped from any GpioPad validation. More...
EFI_STATUS | GpioMinLockPadCfg (IN GPIO_PAD GpioPad)
This procedure will set PadCfgLock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfg), but to decrese memory footprint it was stripped from any GpioPad validation. More...
EFI_STATUS | GpioMinLockPadCfgTx (IN GPIO_PAD GpioPad)
This procedure will set PadCfgLockTx for selected pad Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfgTx), but to decrese memory footprint it was stripped from any GpioPad validation. More...
CHAR8 * | GpioGetNativeSignalName (IN UINT32 PadFunction, OUT CHAR8 *PadFunctionNameBuffer, IN UINT32 PadFunctionBufferSize)
This function returns native signal name from PadFunction. More...

Detailed Description

Header file for GpioLib.

All function in this library is available for PEI, DXE, and SMM

Note
: When GPIO pads are owned by ME Firmware, BIOS/host should not attempt to access these GPIO Pads registers, registers value returned in this case will be 0xFF.
Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioLib.h.

Enumeration Type Documentation

◆ GPIO_PAD_OWN

enum GPIO_PAD_OWN

Possible values of Pad Ownership If Pad is not under Host ownership then GPIO registers are not accessible by host (e.g.

BIOS) and reading them will return 0xFFs.

Definition at line 350 of file GpioLib.h.

Function Documentation

◆ GpioCheckFor2Tier()

BOOLEAN GpioCheckFor2Tier ( IN GPIO_PAD GpioPad )

This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture.

Parameters
[in] GpioPad GPIO pad
Return values
Data 0 means 1-tier, 1 means 2-tier

◆ GpioClearAllGpiSmiSts()

EFI_STATUS GpioClearAllGpiSmiSts ( VOID )

This procedure is used by Smi Dispatcher and will clear all GPI SMI Status bits.

Return values
EFI_SUCCESS The function completed successfully

◆ GpioClearGpiGpeSts()

EFI_STATUS GpioClearGpiGpeSts ( IN GPIO_PAD GpioPad )

This procedure is used to clear GPE STS for a specified GpioPad.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioClearGpiSmiSts()

EFI_STATUS GpioClearGpiSmiSts ( IN GPIO_PAD GpioPad )

This procedure is used to clear SMI STS for a specified Pad.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioConfigurePads()

EFI_STATUS GpioConfigurePads | ( | IN UINT32 | NumberOfItems,
 |  | IN GPIO_INIT_CONFIG * | GpioInitTableAddress
 | ) |  |

This procedure will initialize multiple GPIO pins.

Use GPIO_INIT_CONFIG structure. Structure contains fields that can be used to configure each pad. Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values. Separate fields could be set to hardware default if it does not matter, except GpioPad and PadMode. Function will work in most efficient way if pads which belong to the same group are placed in adjacent records of the table. Although function can enable pads for Native mode, such programming is done by reference code when enabling related silicon feature.

Parameters
[in] | NumberofItem | Number of GPIO pads to be updated
[in] | GpioInitTableAddress | GPIO initialization table
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioDisableAllGpiSmi()

EFI_STATUS GpioDisableAllGpiSmi ( VOID )

This procedure is used to disable all GPI SMI.

Return values
EFI_SUCCESS The function completed successfully

◆ GpioGetGpeNumber()

EFI_STATUS GpioGetGpeNumber | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | GpeNumber
 | ) |  |

This procedure will get GPE number for provided GpioPad.

PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX()) what results in the fact that certain Pad can cause different General Purpose Event. Only three GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common event (GPE_111 for 2-tier).

1-tier: Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used to determine what _LXX ACPI method would be called on event on selected GPIO pad

2-tier: Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE will be under one Primary GPE_111 which is linked to _L6F ACPI method. If it is needed to determine what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN registers for all GPIO groups not mapped to 1-tier GPE.

Parameters
[in] | GpioPad | GPIO pad
[out] | GpeNumber | GPE number
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetGpiGpeSts()

EFI_STATUS GpioGetGpiGpeSts | ( | IN GPIO_PAD | GpioPad,
 |  | OUT BOOLEAN * | GpeSts
 | ) |  |

This procedure is used to read GPE STS for a specified Pad.

Parameters
[in] | GpioPad | GPIO pad
[out] | GpeSts | Gpe status for given pad The GpeSts is true if the status register is set for given Pad number
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetGpiSmiNum()

EFI_STATUS GpioGetGpiSmiNum | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINTN * | GpiNum
 | ) |  |

This procedure is used to register GPI SMI dispatch function.

Parameters
[in] | GpioPad | GPIO pad
[out] | GpiNum | GPI number
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetGpiSmiSts()

EFI_STATUS GpioGetGpiSmiSts | ( | IN GPIO_PAD | GpioPad,
 |  | OUT BOOLEAN * | SmiSts
 | ) |  |

This procedure is used to get SMI STS for a specified Pad.

Parameters
[in] | GpioPad | GPIO pad
[out] | SmiSts | Smi status for given pad The SmiSts is true if the status register is set for given Pad number
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetGroupDwToGpeDwX()

EFI_STATUS GpioGetGroupDwToGpeDwX | ( | OUT GPIO_GROUP * | GroupToGpeDw0,
 |  | OUT UINT32 * | GroupDwForGpeDw0,
 |  | OUT GPIO_GROUP * | GroupToGpeDw1,
 |  | OUT UINT32 * | GroupDwForGpeDw1,
 |  | OUT GPIO_GROUP * | GroupToGpeDw2,
 |  | OUT UINT32 * | GroupDwForGpeDw2
 | ) |  |

This procedure will get Group to GPE mapping.

If group has more than 32 bits it is possible to map only single DW of pins (e.g. 0-31, 32-63) because ACPI GPE_DWx register is 32 bits large.

Parameters
[out] | GroupToGpeDw0 | GPIO group mapped to GPE_DW0
[out] | GroupDwForGpeDw0 | DW of pins mapped to GPE_DW0
[out] | GroupToGpeDw1 | GPIO group mapped to GPE_DW1
[out] | GroupDwForGpeDw1 | DW of pins mapped to GPE_DW1
[out] | GroupToGpeDw2 | GPIO group mapped to GPE_DW2
[out] | GroupDwForGpeDw2 | DW of pins mapped to GPE_DW2
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioGetGroupName()

CONST CHAR8* GpioGetGroupName ( IN UINT32 GroupIndex )

Generates GPIO group name from GroupIndex.

Parameters
[in] GroupIndex Gpio GroupIndex
Return values
CHAR8* Pointer to the GPIO group name

◆ GpioGetGroupToGpeDwX()

EFI_STATUS GpioGetGroupToGpeDwX | ( | IN GPIO_GROUP * | GroupToGpeDw0,
 |  | IN GPIO_GROUP * | GroupToGpeDw1,
 |  | IN GPIO_GROUP * | GroupToGpeDw2
 | ) |  |

This procedure will get Group to GPE mapping.

It will assume that only first 32 pads can be mapped to GPE. To handle cases where groups have more than 32 pads and higher part of group can be mapped please refer to GpioGetGroupDwToGpeDwX()

Parameters
[out] | GroupToGpeDw0 | GPIO group to be mapped to GPE_DW0
[out] | GroupToGpeDw1 | GPIO group to be mapped to GPE_DW1
[out] | GroupToGpeDw2 | GPIO group to be mapped to GPE_DW2
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioGetHostSwOwnershipForGroupDw()

EFI_STATUS GpioGetHostSwOwnershipForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | OUT UINT32 * | HostSwRegVal
 | ) |  |

This procedure will get GPIO Host Software Pad Ownership for certain group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | Host Ownership register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | HostSwRegVal | Value of Host Software Pad Ownership register Bit position - PadNumber Bit value - 0: ACPI Mode, 1: GPIO Driver mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioGetHostSwOwnershipForPad()

EFI_STATUS GpioGetHostSwOwnershipForPad | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | PadHostSwOwn
 | ) |  |

This procedure will get Gpio Pad Host Software Ownership.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadHostSwOwn | Value of Host Software Pad Owner 0: ACPI Mode, 1: GPIO Driver mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetInputInversion()

EFI_STATUS GpioGetInputInversion | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | InvertState
 | ) |  |

This procedure will get GPIO pad input inversion value.

Parameters
[in] | GpioPad | GPIO pad
[out] | InvertState | GPIO inversion state 0: No input inversion, 1: Inverted input
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetInputValue()

EFI_STATUS GpioGetInputValue | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | InputVal
 | ) |  |

This procedure will get GPIO input level.

Parameters
[in] | GpioPad | GPIO pad
[out] | InputVal | GPIO Input value 0: InputLow, 1: InputHigh
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetNativeSignalName()

CHAR8* GpioGetNativeSignalName | ( | IN UINT32 | PadFunction,
 |  | OUT CHAR8 * | PadFunctionNameBuffer,
 |  | IN UINT32 | PadFunctionBufferSize
 | ) |  |

This function returns native signal name from PadFunction.

Parameters
[in] | PadFunction | PadFunction for a specific native signal. Please refer to GpioNativePads.h
[out] | PadFunctionNameBuffer | Caller allocated buffer of GPIO_NAME_LENGTH_MAX size
[in] | PadFunctionBufferSize | Size of the buffer
Return values
CHAR8* Pointer to the native signal name

◆ GpioGetOutputValue()

EFI_STATUS GpioGetOutputValue | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | OutputVal
 | ) |  |

This procedure will get GPIO output level.

Parameters
[in] | GpioPad | GPIO pad
[out] | OutputVal | GPIO Output value 0: OutputLow, 1: OutputHigh
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadCfgLock()

EFI_STATUS GpioGetPadCfgLock | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | PadCfgLock
 | ) |  |

This procedure will check state of Pad Config Lock for selected pad.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadCfgLock | PadCfgLock for selected pad 0: NotLocked, 1: Locked
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadCfgLockForGroupDw()

EFI_STATUS GpioGetPadCfgLockForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | OUT UINT32 * | PadCfgLockRegVal
 | ) |  |

This procedure will check state of Pad Config Lock for pads within one group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | PadCfgLockRegVal | Value of PadCfgLock register Bit position - PadNumber Bit value - 0: NotLocked, 1: Locked
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioGetPadCfgLockTx()

EFI_STATUS GpioGetPadCfgLockTx | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | PadCfgLockTx
 | ) |  |

This procedure will check state of Pad Config Tx Lock for selected pad.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadCfgLock | PadCfgLockTx for selected pad 0: NotLockedTx, 1: LockedTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadCfgLockTxForGroupDw()

EFI_STATUS GpioGetPadCfgLockTxForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | OUT UINT32 * | PadCfgLockTxRegVal
 | ) |  |

This procedure will check state of Pad Config Tx Lock for pads within one group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLockTx register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | PadCfgLockTxRegVal | Value of PadCfgLockTx register Bit position - PadNumber Bit value - 0: NotLockedTx, 1: LockedTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioGetPadConfig()

EFI_STATUS GpioGetPadConfig | ( | IN GPIO_PAD | GpioPad,
 |  | OUT GPIO_CONFIG * | GpioData
 | ) |  |

This procedure will read multiple GPIO settings.

Parameters
[in] | GpioPad | GPIO Pad
[out] | GpioData | GPIO data structure
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadIoApicIrqNumber()

EFI_STATUS GpioGetPadIoApicIrqNumber | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | IrqNum
 | ) |  |

This procedure will get GPIO IOxAPIC interrupt number.

Parameters
[in] | GpioPad | GPIO pad
[out] | IrqNum | IRQ number
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadName()

CHAR8* GpioGetPadName | ( | IN GPIO_PAD | GpioPad,
 |  | OUT CHAR8 * | GpioNameBuffer,
 |  | IN UINT32 | GpioNameBufferSize
 | ) |  |

Generates GPIO name from GpioPad.

Parameters
[in] | GpioPad | GpioPad
[out] | GpioNameBuffer | Caller allocated buffer for GPIO name of GPIO_NAME_LENGTH_MAX size
[in] | GpioNameBufferSize | Size of the buffer
Return values
CHAR8* Pointer to the GPIO name

◆ GpioGetPadOwnership()

EFI_STATUS GpioGetPadOwnership | ( | IN GPIO_PAD | GpioPad,
 |  | OUT GPIO_PAD_OWN * | PadOwnVal
 | ) |  |

This procedure will get Gpio Pad Ownership.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadOwnVal | Value of Pad Ownership
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioGetPadResetConfig()

EFI_STATUS GpioGetPadResetConfig | ( | IN GPIO_PAD | GpioPad,
 |  | IN GPIO_RESET_CONFIG * | Value
 | ) |  |

This procedure will get GPIO Reset settings.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Value of Pad Reset Configuration based on GPIO_RESET_CONFIG
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioLockPadCfg()

EFI_STATUS GpioLockPadCfg ( IN GPIO_PAD GpioPad )

This procedure will set PadCfgLock for selected pad.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioLockPadCfgForGroupDw()

EFI_STATUS GpioLockPadCfgForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | IN UINT32 | PadsToLock
 | ) |  |

This procedure will set PadCfgLock for selected pads within one group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[in] | PadsToLock | Bitmask for pads which are going to be locked, Bit position - PadNumber Bit value - 0: DoNotLock, 1: Lock
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioLockPadCfgTx()

EFI_STATUS GpioLockPadCfgTx ( IN GPIO_PAD GpioPad )

This procedure will set PadCfgLockTx for selected pad.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioLockPadCfgTxForGroupDw()

EFI_STATUS GpioLockPadCfgTxForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | IN UINT32 | PadsToLockTx
 | ) |  |

This procedure will set PadCfgLockTx for selected pads within one group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[in] | PadsToLockTx | Bitmask for pads which are going to be locked, Bit position - PadNumber Bit value - 0: DoNotLockTx, 1: LockTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioLockPads()

EFI_STATUS GpioLockPads ( VOID )

This procedure is used to lock all GPIO pads except the ones which were requested during their configuration to be left unlocked.

This function must be called before BIOS_DONE - before POSTBOOT_SAI is enabled. FSP - call this function from wrapper before transition to FSP-S UEFI/EDK - call this function before EndOfPei event

Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioMinGetPadCfgLock()

EFI_STATUS GpioMinGetPadCfgLock | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | PadCfgLock
 | ) |  |

This procedure will check state of Pad Config Lock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLock), but to decrese memory footprint it was stripped from any GpioPad validation.

Function intended to be used in Pre Mem phase.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadCfgLock | PadCfgLock for selected pad 0: NotLocked, 1: Locked
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioMinGetPadCfgLockForGroupDw()

EFI_STATUS GpioMinGetPadCfgLockForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | OUT UINT32 * | PadCfgLockRegVal
 | ) |  |

Gpio Minimum Set.

This procedure will check state of Pad Config Lock for pads within one group Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockForGroupDw), but to decrese memory footprint it was stripped from any GpioPad validation.

Set of Gpio Minimum function to use in Pre Mem phase. To optimise execution and reduce memory footprint thse minimum version of 'full' functions are stripped from:

  • GpioPad PCH validation
  • GpioPad Group belonging validation
  • GpioPad Host ownership validation
  • IoStandbyState configuration The use of below functions has to be careful and with full understanding of all pros and cons. Please refer to GpioPrivateLib.c to familiarize with details of implementation. This procedure will check state of Pad Config Lock for pads within one group
Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | PadCfgLockRegVal | Value of PadCfgLock register Bit position - PadNumber Bit value - 0: NotLocked, 1: Locked
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

Function intended to be used in Pre Mem phase.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | PadCfgLockRegVal | Value of PadCfgLock register Bit position - PadNumber Bit value - 0: NotLocked, 1: Locked
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioMinGetPadCfgLockTx()

EFI_STATUS GpioMinGetPadCfgLockTx | ( | IN GPIO_PAD | GpioPad,
 |  | OUT UINT32 * | PadCfgLockTx
 | ) |  |

This procedure will check state of Pad Config Tx Lock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTx), but to decrese memory footprint it was stripped from any GpioPad validation.

Function intended to be used in Pre Mem phase.

Parameters
[in] | GpioPad | GPIO pad
[out] | PadCfgLock | PadCfgLockTx for selected pad 0: NotLockedTx, 1: LockedTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioMinGetPadCfgLockTxForGroupDw()

EFI_STATUS GpioMinGetPadCfgLockTxForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | OUT UINT32 * | PadCfgLockTxRegVal
 | ) |  |

This procedure will check state of Pad Config Tx Lock for pads within one group Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTxForGroupDw), but to decrese memory footprint it was stripped from any GpioPad validation.

Function intended to be used in Pre Mem phase.

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLockTx register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[out] | PadCfgLockTxRegVal | Value of PadCfgLockTx register Bit position - PadNumber Bit value - 0: NotLockedTx, 1: LockedTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioMinLockPadCfg()

EFI_STATUS GpioMinLockPadCfg ( IN GPIO_PAD GpioPad )

This procedure will set PadCfgLock for selected pad Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfg), but to decrese memory footprint it was stripped from any GpioPad validation.

Function intended to be used in Pre Mem phase.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioMinLockPadCfgTx()

EFI_STATUS GpioMinLockPadCfgTx ( IN GPIO_PAD GpioPad )

This procedure will set PadCfgLockTx for selected pad Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfgTx), but to decrese memory footprint it was stripped from any GpioPad validation.

Function intended to be used in Pre Mem phase.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioMinUnlockPadCfg()

EFI_STATUS GpioMinUnlockPadCfg ( IN GPIO_PAD GpioPad )

This procedure will clear PadCfgLock for selected pad.

This function should be used only inside SMI. Works exactly as it's counterpart in 'full' library (GpioMinUnlockPadCfg), but to decrese memory footprint it was stripped from any GpioPad validation. Function intended to be used in Pre Mem phase.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioMinUnlockPadCfgTx()

EFI_STATUS GpioMinUnlockPadCfgTx ( IN GPIO_PAD GpioPad )

This procedure will clear PadCfgLockTx for selected pad.

This function should be used only inside SMI. Works exactly as it's counterpart in 'full' library (GpioMinUnlockPadCfgTx), but to decrese memory footprint it was stripped from any GpioPad validation. Function intended to be used in Pre Mem phase.

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioSetGroupDwToGpeDwX()

EFI_STATUS GpioSetGroupDwToGpeDwX | ( | IN GPIO_GROUP | GroupToGpeDw0,
 |  | IN UINT32 | GroupDwForGpeDw0,
 |  | IN GPIO_GROUP | GroupToGpeDw1,
 |  | IN UINT32 | GroupDwForGpeDw1,
 |  | IN GPIO_GROUP | GroupToGpeDw2,
 |  | IN UINT32 | GroupDwForGpeDw2
 | ) |  |

This procedure will set Group to GPE mapping.

If group has more than 32 bits it is possible to map only single DW of pins (e.g. 0-31, 32-63) because ACPI GPE_DWx register is 32 bits large.

Parameters
[in] | GroupToGpeDw0 | GPIO group to be mapped to GPE_DW0
[in] | GroupDwForGpeDw0 | DW of pins to be mapped to GPE_DW0
[in] | GroupToGpeDw1 | GPIO group to be mapped to GPE_DW1
[in] | GroupDwForGpeDw1 | DW of pins to be mapped to GPE_DW1
[in] | GroupToGpeDw2 | GPIO group to be mapped to GPE_DW2
[in] | GroupDwForGpeDw2 | DW of pins to be mapped to GPE_DW2
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioSetGroupToGpeDwX()

EFI_STATUS GpioSetGroupToGpeDwX | ( | IN GPIO_GROUP | GroupToGpeDw0,
 |  | IN GPIO_GROUP | GroupToGpeDw1,
 |  | IN GPIO_GROUP | GroupToGpeDw2
 | ) |  |

This procedure will set Group to GPE mapping.

It will assume that only first 32 pads can be mapped to GPE. To handle cases where groups have more than 32 pads and higher part of group can be mapped please refer to GpioSetGroupDwToGpeDwX()

Parameters
[in] | GroupToGpeDw0 | GPIO group to be mapped to GPE_DW0
[in] | GroupToGpeDw1 | GPIO group to be mapped to GPE_DW1
[in] | GroupToGpeDw2 | GPIO group to be mapped to GPE_DW2
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioSetHostSwOwnershipForGroupDw()

EFI_STATUS GpioSetHostSwOwnershipForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | IN UINT32 | HostSwRegVal
 | ) |  |

This procedure will get GPIO Host Software Pad Ownership for certain group.

Parameters
[in] | Group | GPIO group
[in] | DwNum | Host Ownership register number for current group For group which has less then 32 pads per group DwNum must be 0.
[in] | HostSwRegVal | Value of Host Software Pad Ownership register Bit position - PadNumber Bit value - 0: ACPI Mode, 1: GPIO Driver mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or DwNum parameter number

◆ GpioSetHostSwOwnershipForPad()

EFI_STATUS GpioSetHostSwOwnershipForPad | ( | IN GPIO_PAD | GpioPad,
 |  | IN UINT32 | PadHostSwOwn
 | ) |  |

This procedure will set Gpio Pad Host Software Ownership.

Parameters
[in] | GpioPad | GPIO pad
[in] | PadHostSwOwn | Pad Host Software Owner 0: ACPI Mode, 1: GPIO Driver mode
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetInputInversion()

EFI_STATUS GpioSetInputInversion | ( | IN GPIO_PAD | GpioPad,
 |  | IN UINT32 | Value
 | ) |  |

This procedure will configure GPIO input inversion.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Value for GPIO input inversion 0: No input inversion, 1: Invert input
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetOutputValue()

EFI_STATUS GpioSetOutputValue | ( | IN GPIO_PAD | GpioPad,
 |  | IN UINT32 | Value
 | ) |  |

This procedure will set GPIO output level.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Output value 0: OutputLow, 1: OutputHigh
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetPadConfig()

EFI_STATUS GpioSetPadConfig | ( | IN GPIO_PAD | GpioPad,
 |  | IN GPIO_CONFIG * | GpioData
 | ) |  |

This procedure will configure multiple GPIO settings.

Parameters
[in] | GpioPad | GPIO Pad
[in] | GpioData | GPIO data structure
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetPadElectricalConfig()

EFI_STATUS GpioSetPadElectricalConfig | ( | IN GPIO_PAD | GpioPad,
 |  | IN GPIO_ELECTRICAL_CONFIG | Value
 | ) |  |

This procedure will set GPIO electrical settings.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Value of termination use GPIO_ELECTRICAL_CONFIG as argument
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetPadInterruptConfig()

EFI_STATUS GpioSetPadInterruptConfig | ( | IN GPIO_PAD | GpioPad,
 |  | IN GPIO_INT_CONFIG | Value
 | ) |  |

This procedure will set GPIO interrupt settings.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Value of Level/Edge use GPIO_INT_CONFIG as argument
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioSetPadResetConfig()

EFI_STATUS GpioSetPadResetConfig | ( | IN GPIO_PAD | GpioPad,
 |  | IN GPIO_RESET_CONFIG | Value
 | ) |  |

This procedure will set GPIO Reset settings.

Parameters
[in] | GpioPad | GPIO pad
[in] | Value | Value for Pad Reset Configuration use GPIO_RESET_CONFIG as argument
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioUnlockPadCfg()

EFI_STATUS GpioUnlockPadCfg ( IN GPIO_PAD GpioPad )

This procedure will clear PadCfgLock for selected pad.

Unlocking a pad will cause an SMI (if enabled)

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioUnlockPadCfgForGroupDw()

EFI_STATUS GpioUnlockPadCfgForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | IN UINT32 | PadsToUnlock
 | ) |  |

This procedure will clear PadCfgLock for selected pads within one group.

Unlocking a pad will cause an SMI (if enabled)

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLock register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[in] | PadsToUnlock | Bitmask for pads which are going to be unlocked, Bit position - PadNumber Bit value - 0: DoNotUnlock, 1: Unlock
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number

◆ GpioUnlockPadCfgTx()

EFI_STATUS GpioUnlockPadCfgTx ( IN GPIO_PAD GpioPad )

This procedure will clear PadCfgLockTx for selected pad.

Unlocking a pad will cause an SMI (if enabled)

Parameters
[in] GpioPad GPIO pad
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid GpioPad

◆ GpioUnlockPadCfgTxForGroupDw()

EFI_STATUS GpioUnlockPadCfgTxForGroupDw | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | DwNum,
 |  | IN UINT32 | PadsToUnlockTx
 | ) |  |

This procedure will clear PadCfgLockTx for selected pads within one group.

Unlocking a pad will cause an SMI (if enabled)

Parameters
[in] | Group | GPIO group
[in] | DwNum | PadCfgLockTx register number for current group. For group which has less then 32 pads per group DwNum must be 0.
[in] | PadsToUnlockTx | Bitmask for pads which are going to be unlocked, Bit position - PadNumber Bit value - 0: DoNotUnLockTx, 1: LockTx
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Invalid group or pad number
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GpioLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioLib.
3 All function in this library is available for PEI, DXE, and SMM
4
5 @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
6 attempt to access these GPIO Pads registers, registers value
7 returned in this case will be 0xFF.
8
9 @copyright
10 INTEL CONFIDENTIAL
11 Copyright 2013 - 2021 Intel Corporation.
12
13 The source code contained or described herein and all documents related to the
14 source code ("Material") are owned by Intel Corporation or its suppliers or
15 licensors. Title to the Material remains with Intel Corporation or its suppliers
16 and licensors. The Material may contain trade secrets and proprietary and
17 confidential information of Intel Corporation and its suppliers and licensors,
18 and is protected by worldwide copyright and trade secret laws and treaty
19 provisions. No part of the Material may be used, copied, reproduced, modified,
20 published, uploaded, posted, transmitted, distributed, or disclosed in any way
21 without Intel's prior express written permission.
22
23 No license under any patent, copyright, trade secret or other intellectual
24 property right is granted to or conferred upon you by disclosure or delivery
25 of the Materials, either expressly, by implication, inducement, estoppel or
26 otherwise. Any license under such intellectual property rights must be
27 express and approved by Intel in writing.
28
29 Unless otherwise agreed by Intel in writing, you may not remove or alter
30 this notice or any other notice embedded in Materials by Intel or
31 Intel's suppliers or licensors in any way.
32
33 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
34 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
35 the terms of your license agreement with Intel or your vendor. This file may
36 be modified by the user, subject to additional terms of the license agreement.
37
38 @par Specification Reference:
39 **/
40 #ifndef _GPIO_LIB_H_
41 #define _GPIO_LIB_H_
42
43 #include <Library/GpioConfig.h>
44
45 #define GPIO_NAME_LENGTH_MAX 32
46
47 typedef struct {
48 GPIO_PAD GpioPad;
49 GPIO_CONFIG GpioConfig;
50 } GPIO_INIT_CONFIG;
51
52 /**
53 This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
54 Structure contains fields that can be used to configure each pad.
55 Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
56 Separate fields could be set to hardware default if it does not matter, except
57 GpioPad and PadMode.
58 Function will work in most efficient way if pads which belong to the same group are
59 placed in adjacent records of the table.
60 Although function can enable pads for Native mode, such programming is done
61 by reference code when enabling related silicon feature.
62
63 @param[in] NumberofItem Number of GPIO pads to be updated
64 @param[in] GpioInitTableAddress GPIO initialization table
65
66 @retval EFI_SUCCESS The function completed successfully
67 @retval EFI_INVALID_PARAMETER Invalid group or pad number
68 **/
69 EFI_STATUS
70 GpioConfigurePads (
71 IN UINT32 NumberOfItems,
72 IN GPIO_INIT_CONFIG *GpioInitTableAddress
73 );
74
75 //
76 // Functions for setting/getting multiple GpioPad settings
77 //
78
79 /**
80 This procedure will read multiple GPIO settings
81
82 @param[in] GpioPad GPIO Pad
83 @param[out] GpioData GPIO data structure
84
85 @retval EFI_SUCCESS The function completed successfully
86 @retval EFI_INVALID_PARAMETER Invalid GpioPad
87 **/
88 EFI_STATUS
89 GpioGetPadConfig (
90 IN GPIO_PAD GpioPad,
91 OUT GPIO_CONFIG *GpioData
92 );
93
94 /**
95 This procedure will configure multiple GPIO settings
96
97 @param[in] GpioPad GPIO Pad
98 @param[in] GpioData GPIO data structure
99
100 @retval EFI_SUCCESS The function completed successfully
101 @retval EFI_INVALID_PARAMETER Invalid GpioPad
102 **/
103 EFI_STATUS
104 GpioSetPadConfig (
105 IN GPIO_PAD GpioPad,
106 IN GPIO_CONFIG *GpioData
107 );
108
109 //
110 // Functions for setting/getting single GpioPad properties
111 //
112
113 /**
114 This procedure will set GPIO output level
115
116 @param[in] GpioPad GPIO pad
117 @param[in] Value Output value
118 0: OutputLow, 1: OutputHigh
119
120 @retval EFI_SUCCESS The function completed successfully
121 @retval EFI_INVALID_PARAMETER Invalid GpioPad
122 **/
123 EFI_STATUS
124 GpioSetOutputValue (
125 IN GPIO_PAD GpioPad,
126 IN UINT32 Value
127 );
128
129 /**
130 This procedure will get GPIO output level
131
132 @param[in] GpioPad GPIO pad
133 @param[out] OutputVal GPIO Output value
134 0: OutputLow, 1: OutputHigh
135
136 @retval EFI_SUCCESS The function completed successfully
137 @retval EFI_INVALID_PARAMETER Invalid GpioPad
138 **/
139 EFI_STATUS
140 GpioGetOutputValue (
141 IN GPIO_PAD GpioPad,
142 OUT UINT32 *OutputVal
143 );
144
145 /**
146 This procedure will get GPIO input level
147
148 @param[in] GpioPad GPIO pad
149 @param[out] InputVal GPIO Input value
150 0: InputLow, 1: InputHigh
151
152 @retval EFI_SUCCESS The function completed successfully
153 @retval EFI_INVALID_PARAMETER Invalid GpioPad
154 **/
155 EFI_STATUS
156 GpioGetInputValue (
157 IN GPIO_PAD GpioPad,
158 OUT UINT32 *InputVal
159 );
160
161 /**
162 This procedure will get GPIO IOxAPIC interrupt number
163
164 @param[in] GpioPad GPIO pad
165 @param[out] IrqNum IRQ number
166
167 @retval EFI_SUCCESS The function completed successfully
168 @retval EFI_INVALID_PARAMETER Invalid GpioPad
169 **/
170 EFI_STATUS
171 GpioGetPadIoApicIrqNumber (
172 IN GPIO_PAD GpioPad,
173 OUT UINT32 *IrqNum
174 );
175
176 /**
177 This procedure will configure GPIO input inversion
178
179 @param[in] GpioPad GPIO pad
180 @param[in] Value Value for GPIO input inversion
181 0: No input inversion, 1: Invert input
182
183 @retval EFI_SUCCESS The function completed successfully
184 @retval EFI_INVALID_PARAMETER Invalid GpioPad
185 **/
186 EFI_STATUS
187 GpioSetInputInversion (
188 IN GPIO_PAD GpioPad,
189 IN UINT32 Value
190 );
191
192 /**
193 This procedure will get GPIO pad input inversion value
194
195 @param[in] GpioPad GPIO pad
196 @param[out] InvertState GPIO inversion state
197 0: No input inversion, 1: Inverted input
198
199 @retval EFI_SUCCESS The function completed successfully
200 @retval EFI_INVALID_PARAMETER Invalid GpioPad
201 **/
202 EFI_STATUS
203 GpioGetInputInversion (
204 IN GPIO_PAD GpioPad,
205 OUT UINT32 *InvertState
206 );
207
208 /**
209 This procedure will set GPIO interrupt settings
210
211 @param[in] GpioPad GPIO pad
212 @param[in] Value Value of Level/Edge
213 use GPIO_INT_CONFIG as argument
214
215 @retval EFI_SUCCESS The function completed successfully
216 @retval EFI_INVALID_PARAMETER Invalid GpioPad
217 **/
218 EFI_STATUS
219 GpioSetPadInterruptConfig (
220 IN GPIO_PAD GpioPad,
221 IN GPIO_INT_CONFIG Value
222 );
223
224 /**
225 This procedure will set GPIO electrical settings
226
227 @param[in] GpioPad GPIO pad
228 @param[in] Value Value of termination
229 use GPIO_ELECTRICAL_CONFIG as argument
230
231 @retval EFI_SUCCESS The function completed successfully
232 @retval EFI_INVALID_PARAMETER Invalid GpioPad
233 **/
234 EFI_STATUS
235 GpioSetPadElectricalConfig (
236 IN GPIO_PAD GpioPad,
237 IN GPIO_ELECTRICAL_CONFIG Value
238 );
239
240 /**
241 This procedure will set GPIO Reset settings
242
243 @param[in] GpioPad GPIO pad
244 @param[in] Value Value for Pad Reset Configuration
245 use GPIO_RESET_CONFIG as argument
246
247 @retval EFI_SUCCESS The function completed successfully
248 @retval EFI_INVALID_PARAMETER Invalid GpioPad
249 **/
250 EFI_STATUS
251 GpioSetPadResetConfig (
252 IN GPIO_PAD GpioPad,
253 IN GPIO_RESET_CONFIG Value
254 );
255
256 /**
257 This procedure will get GPIO Reset settings
258
259 @param[in] GpioPad GPIO pad
260 @param[in] Value Value of Pad Reset Configuration
261 based on GPIO_RESET_CONFIG
262
263 @retval EFI_SUCCESS The function completed successfully
264 @retval EFI_INVALID_PARAMETER Invalid GpioPad
265 **/
266 EFI_STATUS
267 GpioGetPadResetConfig (
268 IN GPIO_PAD GpioPad,
269 IN GPIO_RESET_CONFIG *Value
270 );
271
272 /**
273 This procedure will get GPIO Host Software Pad Ownership for certain group
274
275 @param[in] Group GPIO group
276 @param[in] DwNum Host Ownership register number for current group.
277 For group which has less then 32 pads per group DwNum must be 0.
278 @param[out] HostSwRegVal Value of Host Software Pad Ownership register
279 Bit position - PadNumber
280 Bit value - 0: ACPI Mode, 1: GPIO Driver mode
281
282 @retval EFI_SUCCESS The function completed successfully
283 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
284 **/
285 EFI_STATUS
286 GpioGetHostSwOwnershipForGroupDw (
287 IN GPIO_GROUP Group,
288 IN UINT32 DwNum,
289 OUT UINT32 *HostSwRegVal
290 );
291
292 /**
293 This procedure will get GPIO Host Software Pad Ownership for certain group
294
295 @param[in] Group GPIO group
296 @param[in] DwNum Host Ownership register number for current group
297 For group which has less then 32 pads per group DwNum must be 0.
298 @param[in] HostSwRegVal Value of Host Software Pad Ownership register
299 Bit position - PadNumber
300 Bit value - 0: ACPI Mode, 1: GPIO Driver mode
301
302 @retval EFI_SUCCESS The function completed successfully
303 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
304 **/
305 EFI_STATUS
306 GpioSetHostSwOwnershipForGroupDw (
307 IN GPIO_GROUP Group,
308 IN UINT32 DwNum,
309 IN UINT32 HostSwRegVal
310 );
311
312 /**
313 This procedure will get Gpio Pad Host Software Ownership
314
315 @param[in] GpioPad GPIO pad
316 @param[out] PadHostSwOwn Value of Host Software Pad Owner
317 0: ACPI Mode, 1: GPIO Driver mode
318
319 @retval EFI_SUCCESS The function completed successfully
320 @retval EFI_INVALID_PARAMETER Invalid GpioPad
321 **/
322 EFI_STATUS
323 GpioGetHostSwOwnershipForPad (
324 IN GPIO_PAD GpioPad,
325 OUT UINT32 *PadHostSwOwn
326 );
327
328 /**
329 This procedure will set Gpio Pad Host Software Ownership
330
331 @param[in] GpioPad GPIO pad
332 @param[in] PadHostSwOwn Pad Host Software Owner
333 0: ACPI Mode, 1: GPIO Driver mode
334
335 @retval EFI_SUCCESS The function completed successfully
336 @retval EFI_INVALID_PARAMETER Invalid GpioPad
337 **/
338 EFI_STATUS
339 GpioSetHostSwOwnershipForPad (
340 IN GPIO_PAD GpioPad,
341 IN UINT32 PadHostSwOwn
342 );
343
344 ///
345 /// Possible values of Pad Ownership
346 /// If Pad is not under Host ownership then GPIO registers
347 /// are not accessible by host (e.g. BIOS) and reading them
348 /// will return 0xFFs.
349 ///
350 typedef enum {
351 GpioPadOwnHost = 0x0,
352 GpioPadOwnCsme = 0x1,
353 GpioPadOwnIsh = 0x2,
354 } GPIO_PAD_OWN;
355
356 /**
357 This procedure will get Gpio Pad Ownership
358
359 @param[in] GpioPad GPIO pad
360 @param[out] PadOwnVal Value of Pad Ownership
361
362 @retval EFI_SUCCESS The function completed successfully
363 @retval EFI_INVALID_PARAMETER Invalid GpioPad
364 **/
365 EFI_STATUS
366 GpioGetPadOwnership (
367 IN GPIO_PAD GpioPad,
368 OUT GPIO_PAD_OWN *PadOwnVal
369 );
370
371 /**
372 This procedure will check state of Pad Config Lock for pads within one group
373
374 @param[in] Group GPIO group
375 @param[in] DwNum PadCfgLock register number for current group.
376 For group which has less then 32 pads per group DwNum must be 0.
377 @param[out] PadCfgLockRegVal Value of PadCfgLock register
378 Bit position - PadNumber
379 Bit value - 0: NotLocked, 1: Locked
380
381 @retval EFI_SUCCESS The function completed successfully
382 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
383 **/
384 EFI_STATUS
385 GpioGetPadCfgLockForGroupDw (
386 IN GPIO_GROUP Group,
387 IN UINT32 DwNum,
388 OUT UINT32 *PadCfgLockRegVal
389 );
390
391 /**
392 This procedure will check state of Pad Config Lock for selected pad
393
394 @param[in] GpioPad GPIO pad
395 @param[out] PadCfgLock PadCfgLock for selected pad
396 0: NotLocked, 1: Locked
397
398 @retval EFI_SUCCESS The function completed successfully
399 @retval EFI_INVALID_PARAMETER Invalid GpioPad
400 **/
401 EFI_STATUS
402 GpioGetPadCfgLock (
403 IN GPIO_PAD GpioPad,
404 OUT UINT32 *PadCfgLock
405 );
406
407 /**
408 This procedure will check state of Pad Config Tx Lock for pads within one group
409
410 @param[in] Group GPIO group
411 @param[in] DwNum PadCfgLockTx register number for current group.
412 For group which has less then 32 pads per group DwNum must be 0.
413 @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
414 Bit position - PadNumber
415 Bit value - 0: NotLockedTx, 1: LockedTx
416
417 @retval EFI_SUCCESS The function completed successfully
418 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
419 **/
420 EFI_STATUS
421 GpioGetPadCfgLockTxForGroupDw (
422 IN GPIO_GROUP Group,
423 IN UINT32 DwNum,
424 OUT UINT32 *PadCfgLockTxRegVal
425 );
426
427 /**
428 This procedure will check state of Pad Config Tx Lock for selected pad
429
430 @param[in] GpioPad GPIO pad
431 @param[out] PadCfgLock PadCfgLockTx for selected pad
432 0: NotLockedTx, 1: LockedTx
433
434 @retval EFI_SUCCESS The function completed successfully
435 @retval EFI_INVALID_PARAMETER Invalid GpioPad
436 **/
437 EFI_STATUS
438 GpioGetPadCfgLockTx (
439 IN GPIO_PAD GpioPad,
440 OUT UINT32 *PadCfgLockTx
441 );
442
443 /**
444 This procedure will clear PadCfgLock for selected pads within one group.
445 Unlocking a pad will cause an SMI (if enabled)
446
447 @param[in] Group GPIO group
448 @param[in] DwNum PadCfgLock register number for current group.
449 For group which has less then 32 pads per group DwNum must be 0.
450 @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
451 Bit position - PadNumber
452 Bit value - 0: DoNotUnlock, 1: Unlock
453
454 @retval EFI_SUCCESS The function completed successfully
455 @retval EFI_INVALID_PARAMETER Invalid group or pad number
456 **/
457 EFI_STATUS
458 GpioUnlockPadCfgForGroupDw (
459 IN GPIO_GROUP Group,
460 IN UINT32 DwNum,
461 IN UINT32 PadsToUnlock
462 );
463
464 /**
465 This procedure will clear PadCfgLock for selected pad.
466 Unlocking a pad will cause an SMI (if enabled)
467
468 @param[in] GpioPad GPIO pad
469
470 @retval EFI_SUCCESS The function completed successfully
471 @retval EFI_INVALID_PARAMETER Invalid GpioPad
472 **/
473 EFI_STATUS
474 GpioUnlockPadCfg (
475 IN GPIO_PAD GpioPad
476 );
477
478 /**
479 This procedure will set PadCfgLock for selected pads within one group
480
481 @param[in] Group GPIO group
482 @param[in] DwNum PadCfgLock register number for current group.
483 For group which has less then 32 pads per group DwNum must be 0.
484 @param[in] PadsToLock Bitmask for pads which are going to be locked,
485 Bit position - PadNumber
486 Bit value - 0: DoNotLock, 1: Lock
487
488 @retval EFI_SUCCESS The function completed successfully
489 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
490 **/
491 EFI_STATUS
492 GpioLockPadCfgForGroupDw (
493 IN GPIO_GROUP Group,
494 IN UINT32 DwNum,
495 IN UINT32 PadsToLock
496 );
497
498 /**
499 This procedure will set PadCfgLock for selected pad
500
501 @param[in] GpioPad GPIO pad
502
503 @retval EFI_SUCCESS The function completed successfully
504 @retval EFI_INVALID_PARAMETER Invalid GpioPad
505 **/
506 EFI_STATUS
507 GpioLockPadCfg (
508 IN GPIO_PAD GpioPad
509 );
510
511 /**
512 This procedure will clear PadCfgLockTx for selected pads within one group.
513 Unlocking a pad will cause an SMI (if enabled)
514
515 @param[in] Group GPIO group
516 @param[in] DwNum PadCfgLockTx register number for current group.
517 For group which has less then 32 pads per group DwNum must be 0.
518 @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
519 Bit position - PadNumber
520 Bit value - 0: DoNotUnLockTx, 1: LockTx
521
522 @retval EFI_SUCCESS The function completed successfully
523 @retval EFI_INVALID_PARAMETER Invalid group or pad number
524 **/
525 EFI_STATUS
526 GpioUnlockPadCfgTxForGroupDw (
527 IN GPIO_GROUP Group,
528 IN UINT32 DwNum,
529 IN UINT32 PadsToUnlockTx
530 );
531
532 /**
533 This procedure will clear PadCfgLockTx for selected pad.
534 Unlocking a pad will cause an SMI (if enabled)
535
536 @param[in] GpioPad GPIO pad
537
538 @retval EFI_SUCCESS The function completed successfully
539 @retval EFI_INVALID_PARAMETER Invalid GpioPad
540 **/
541 EFI_STATUS
542 GpioUnlockPadCfgTx (
543 IN GPIO_PAD GpioPad
544 );
545
546 /**
547 This procedure will set PadCfgLockTx for selected pads within one group
548
549 @param[in] Group GPIO group
550 @param[in] DwNum PadCfgLock register number for current group.
551 For group which has less then 32 pads per group DwNum must be 0.
552 @param[in] PadsToLockTx Bitmask for pads which are going to be locked,
553 Bit position - PadNumber
554 Bit value - 0: DoNotLockTx, 1: LockTx
555
556 @retval EFI_SUCCESS The function completed successfully
557 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
558 **/
559 EFI_STATUS
560 GpioLockPadCfgTxForGroupDw (
561 IN GPIO_GROUP Group,
562 IN UINT32 DwNum,
563 IN UINT32 PadsToLockTx
564 );
565
566 /**
567 This procedure will set PadCfgLockTx for selected pad
568
569 @param[in] GpioPad GPIO pad
570
571 @retval EFI_SUCCESS The function completed successfully
572 @retval EFI_INVALID_PARAMETER Invalid GpioPad
573 **/
574 EFI_STATUS
575 GpioLockPadCfgTx (
576 IN GPIO_PAD GpioPad
577 );
578
579 /**
580 This procedure will get Group to GPE mapping.
581 It will assume that only first 32 pads can be mapped to GPE.
582 To handle cases where groups have more than 32 pads and higher part of group
583 can be mapped please refer to GpioGetGroupDwToGpeDwX()
584
585 @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
586 @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
587 @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
588
589 @retval EFI_SUCCESS The function completed successfully
590 @retval EFI_INVALID_PARAMETER Invalid group or pad number
591 **/
592 EFI_STATUS
593 GpioGetGroupToGpeDwX (
594 IN GPIO_GROUP *GroupToGpeDw0,
595 IN GPIO_GROUP *GroupToGpeDw1,
596 IN GPIO_GROUP *GroupToGpeDw2
597 );
598
599 /**
600 This procedure will get Group to GPE mapping. If group has more than 32 bits
601 it is possible to map only single DW of pins (e.g. 0-31, 32-63) because
602 ACPI GPE_DWx register is 32 bits large.
603
604 @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0
605 @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0
606 @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1
607 @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1
608 @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2
609 @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2
610
611 @retval EFI_SUCCESS The function completed successfully
612 @retval EFI_INVALID_PARAMETER Invalid group or pad number
613 **/
614 EFI_STATUS
615 GpioGetGroupDwToGpeDwX (
616 OUT GPIO_GROUP *GroupToGpeDw0,
617 OUT UINT32 *GroupDwForGpeDw0,
618 OUT GPIO_GROUP *GroupToGpeDw1,
619 OUT UINT32 *GroupDwForGpeDw1,
620 OUT GPIO_GROUP *GroupToGpeDw2,
621 OUT UINT32 *GroupDwForGpeDw2
622 );
623
624 /**
625 This procedure will set Group to GPE mapping.
626 It will assume that only first 32 pads can be mapped to GPE.
627 To handle cases where groups have more than 32 pads and higher part of group
628 can be mapped please refer to GpioSetGroupDwToGpeDwX()
629
630 @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
631 @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
632 @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
633
634 @retval EFI_SUCCESS The function completed successfully
635 @retval EFI_INVALID_PARAMETER Invalid group or pad number
636 **/
637 EFI_STATUS
638 GpioSetGroupToGpeDwX (
639 IN GPIO_GROUP GroupToGpeDw0,
640 IN GPIO_GROUP GroupToGpeDw1,
641 IN GPIO_GROUP GroupToGpeDw2
642 );
643
644 /**
645 This procedure will set Group to GPE mapping. If group has more than 32 bits
646 it is possible to map only single DW of pins (e.g. 0-31, 32-63) because
647 ACPI GPE_DWx register is 32 bits large.
648
649 @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
650 @param[in] GroupDwForGpeDw0 DW of pins to be mapped to GPE_DW0
651 @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
652 @param[in] GroupDwForGpeDw1 DW of pins to be mapped to GPE_DW1
653 @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
654 @param[in] GroupDwForGpeDw2 DW of pins to be mapped to GPE_DW2
655
656 @retval EFI_SUCCESS The function completed successfully
657 @retval EFI_INVALID_PARAMETER Invalid group or pad number
658 **/
659 EFI_STATUS
660 GpioSetGroupDwToGpeDwX (
661 IN GPIO_GROUP GroupToGpeDw0,
662 IN UINT32 GroupDwForGpeDw0,
663 IN GPIO_GROUP GroupToGpeDw1,
664 IN UINT32 GroupDwForGpeDw1,
665 IN GPIO_GROUP GroupToGpeDw2,
666 IN UINT32 GroupDwForGpeDw2
667 );
668
669 /**
670 This procedure will get GPE number for provided GpioPad.
671 PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX())
672 what results in the fact that certain Pad can cause different General Purpose Event. Only three
673 GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common
674 event (GPE_111 for 2-tier).
675
676 1-tier:
677 Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used
678 to determine what _LXX ACPI method would be called on event on selected GPIO pad
679
680 2-tier:
681 Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE
682 will be under one Primary GPE_111 which is linked to _L6F ACPI method. If it is needed to determine
683 what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN
684 registers for all GPIO groups not mapped to 1-tier GPE.
685
686 @param[in] GpioPad GPIO pad
687 @param[out] GpeNumber GPE number
688
689 @retval EFI_SUCCESS The function completed successfully
690 @retval EFI_INVALID_PARAMETER Invalid GpioPad
691 **/
692 EFI_STATUS
693 GpioGetGpeNumber (
694 IN GPIO_PAD GpioPad,
695 OUT UINT32 *GpeNumber
696 );
697
698 /**
699 This procedure is used to clear SMI STS for a specified Pad
700
701 @param[in] GpioPad GPIO pad
702
703 @retval EFI_SUCCESS The function completed successfully
704 @retval EFI_INVALID_PARAMETER Invalid GpioPad
705 **/
706 EFI_STATUS
707 GpioClearGpiSmiSts (
708 IN GPIO_PAD GpioPad
709 );
710
711 /**
712 This procedure is used by Smi Dispatcher and will clear
713 all GPI SMI Status bits
714
715 @retval EFI_SUCCESS The function completed successfully
716 **/
717 EFI_STATUS
718 GpioClearAllGpiSmiSts (
719 VOID
720 );
721
722 /**
723 This procedure is used to disable all GPI SMI
724
725 @retval EFI_SUCCESS The function completed successfully
726 **/
727 EFI_STATUS
728 GpioDisableAllGpiSmi (
729 VOID
730 );
731
732 /**
733 This procedure is used to register GPI SMI dispatch function.
734
735 @param[in] GpioPad GPIO pad
736 @param[out] GpiNum GPI number
737
738 @retval EFI_SUCCESS The function completed successfully
739 @retval EFI_INVALID_PARAMETER Invalid GpioPad
740 **/
741 EFI_STATUS
742 GpioGetGpiSmiNum (
743 IN GPIO_PAD GpioPad,
744 OUT UINTN *GpiNum
745 );
746
747 /**
748 This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture
749
750 @param[in] GpioPad GPIO pad
751
752 @retval Data 0 means 1-tier, 1 means 2-tier
753 **/
754 BOOLEAN
755 GpioCheckFor2Tier (
756 IN GPIO_PAD GpioPad
757 );
758
759 /**
760 This procedure is used to clear GPE STS for a specified GpioPad
761
762 @param[in] GpioPad GPIO pad
763
764 @retval EFI_SUCCESS The function completed successfully
765 @retval EFI_INVALID_PARAMETER Invalid GpioPad
766 **/
767 EFI_STATUS
768 GpioClearGpiGpeSts (
769 IN GPIO_PAD GpioPad
770 );
771
772 /**
773 This procedure is used to read GPE STS for a specified Pad
774
775 @param[in] GpioPad GPIO pad
776 @param[out] GpeSts Gpe status for given pad
777 The GpeSts is true if the status register is set for given Pad number
778
779 @retval EFI_SUCCESS The function completed successfully
780 @retval EFI_INVALID_PARAMETER Invalid GpioPad
781 **/
782 EFI_STATUS
783 GpioGetGpiGpeSts (
784 IN GPIO_PAD GpioPad,
785 OUT BOOLEAN *GpeSts
786 );
787
788 /**
789 This procedure is used to get SMI STS for a specified Pad
790
791 @param[in] GpioPad GPIO pad
792 @param[out] SmiSts Smi status for given pad
793 The SmiSts is true if the status register is set for given Pad number
794
795 @retval EFI_SUCCESS The function completed successfully
796 @retval EFI_INVALID_PARAMETER Invalid GpioPad
797 **/
798 EFI_STATUS
799 GpioGetGpiSmiSts (
800 IN GPIO_PAD GpioPad,
801 OUT BOOLEAN *SmiSts
802 );
803
804 /**
805 This procedure is used to lock all GPIO pads except the ones
806 which were requested during their configuration to be left unlocked.
807 This function must be called before BIOS_DONE - before POSTBOOT_SAI is enabled.
808 FSP - call this function from wrapper before transition to FSP-S
809 UEFI/EDK - call this function before EndOfPei event
810
811 @retval EFI_SUCCESS The function completed successfully
812 @retval EFI_INVALID_PARAMETER Invalid group or pad number
813 **/
814 EFI_STATUS
815 GpioLockPads (
816 VOID
817 );
818
819 /**
820 Generates GPIO name from GpioPad
821
822 @param[in] GpioPad GpioPad
823 @param[out] GpioNameBuffer Caller allocated buffer for GPIO name of GPIO_NAME_LENGTH_MAX size
824 @param[in] GpioNameBufferSize Size of the buffer
825
826 @retval CHAR8* Pointer to the GPIO name
827 **/
828 CHAR8*
829 GpioGetPadName (
830 IN GPIO_PAD GpioPad,
831 OUT CHAR8* GpioNameBuffer,
832 IN UINT32 GpioNameBufferSize
833 );
834
835 /**
836 Generates GPIO group name from GroupIndex
837
838 @param[in] GroupIndex Gpio GroupIndex
839
840 @retval CHAR8* Pointer to the GPIO group name
841 **/
842 CONST
843 CHAR8*
844 GpioGetGroupName (
845 IN UINT32 GroupIndex
846 );
847
848 /**
849 Gpio Minimum Set
850
851 Set of Gpio Minimum function to use in Pre Mem phase.
852 To optimise execution and reduce memory footprint thse minimum version
853 of 'full' functions are stripped from:
854 - GpioPad PCH validation
855 - GpioPad Group belonging validation
856 - GpioPad Host ownership validation
857 - IoStandbyState configuration
858 The use of below functions has to be careful and with full
859 understanding of all pros and cons. Please refer to GpioPrivateLib.c
860 to familiarize with details of implementation.
861 **/
862 /**
863 This procedure will check state of Pad Config Lock for pads within one group
864
865 @param[in] Group GPIO group
866 @param[in] DwNum PadCfgLock register number for current group.
867 For group which has less then 32 pads per group DwNum must be 0.
868 @param[out] PadCfgLockRegVal Value of PadCfgLock register
869 Bit position - PadNumber
870 Bit value - 0: NotLocked, 1: Locked
871
872 @retval EFI_SUCCESS The function completed successfully
873 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
874 **/
875 EFI_STATUS
876 GpioMinGetPadCfgLockForGroupDw (
877 IN GPIO_GROUP Group,
878 IN UINT32 DwNum,
879 OUT UINT32 *PadCfgLockRegVal
880 );
881
882 /**
883 This procedure will check state of Pad Config Tx Lock for pads within one group
884 Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTxForGroupDw),
885 but to decrese memory footprint it was stripped from any GpioPad validation.
886 Function intended to be used in Pre Mem phase.
887
888 @param[in] Group GPIO group
889 @param[in] DwNum PadCfgLockTx register number for current group.
890 For group which has less then 32 pads per group DwNum must be 0.
891 @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
892 Bit position - PadNumber
893 Bit value - 0: NotLockedTx, 1: LockedTx
894
895 @retval EFI_SUCCESS The function completed successfully
896 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
897 **/
898 EFI_STATUS
899 GpioMinGetPadCfgLockTxForGroupDw (
900 IN GPIO_GROUP Group,
901 IN UINT32 DwNum,
902 OUT UINT32 *PadCfgLockTxRegVal
903 );
904
905 /**
906 This procedure will check state of Pad Config Lock for pads within one group
907 Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockForGroupDw),
908 but to decrese memory footprint it was stripped from any GpioPad validation.
909 Function intended to be used in Pre Mem phase.
910
911 @param[in] Group GPIO group
912 @param[in] DwNum PadCfgLock register number for current group.
913 For group which has less then 32 pads per group DwNum must be 0.
914 @param[out] PadCfgLockRegVal Value of PadCfgLock register
915 Bit position - PadNumber
916 Bit value - 0: NotLocked, 1: Locked
917
918 @retval EFI_SUCCESS The function completed successfully
919 @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
920 **/
921 EFI_STATUS
922 GpioMinGetPadCfgLockForGroupDw (
923 IN GPIO_GROUP Group,
924 IN UINT32 DwNum,
925 OUT UINT32 *PadCfgLockRegVal
926 );
927
928 /**
929 This procedure will clear PadCfgLock for selected pad.
930 This function should be used only inside SMI.
931 Works exactly as it's counterpart in 'full' library (GpioMinUnlockPadCfg),
932 but to decrese memory footprint it was stripped from any GpioPad validation.
933 Function intended to be used in Pre Mem phase.
934
935 @param[in] GpioPad GPIO pad
936
937 @retval EFI_SUCCESS The function completed successfully
938 @retval EFI_INVALID_PARAMETER Invalid group or pad number
939 **/
940 EFI_STATUS
941 GpioMinUnlockPadCfg (
942 IN GPIO_PAD GpioPad
943 );
944
945 /**
946 This procedure will check state of Pad Config Tx Lock for selected pad
947 Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLockTx),
948 but to decrese memory footprint it was stripped from any GpioPad validation.
949 Function intended to be used in Pre Mem phase.
950
951 @param[in] GpioPad GPIO pad
952 @param[out] PadCfgLock PadCfgLockTx for selected pad
953 0: NotLockedTx, 1: LockedTx
954
955 @retval EFI_SUCCESS The function completed successfully
956 @retval EFI_INVALID_PARAMETER Invalid GpioPad
957 **/
958 EFI_STATUS
959 GpioMinGetPadCfgLockTx (
960 IN GPIO_PAD GpioPad,
961 OUT UINT32 *PadCfgLockTx
962 );
963
964 /**
965 This procedure will clear PadCfgLockTx for selected pad.
966 This function should be used only inside SMI.
967 Works exactly as it's counterpart in 'full' library (GpioMinUnlockPadCfgTx),
968 but to decrese memory footprint it was stripped from any GpioPad validation.
969 Function intended to be used in Pre Mem phase.
970
971 @param[in] GpioPad GPIO pad
972
973 @retval EFI_SUCCESS The function completed successfully
974 @retval EFI_INVALID_PARAMETER Invalid group or pad number
975 **/
976 EFI_STATUS
977 GpioMinUnlockPadCfgTx (
978 IN GPIO_PAD GpioPad
979 );
980
981 /**
982 This procedure will check state of Pad Config Lock for selected pad
983 Works exactly as it's counterpart in 'full' library (GpioMinGetPadCfgLock),
984 but to decrese memory footprint it was stripped from any GpioPad validation.
985 Function intended to be used in Pre Mem phase.
986
987 @param[in] GpioPad GPIO pad
988 @param[out] PadCfgLock PadCfgLock for selected pad
989 0: NotLocked, 1: Locked
990
991 @retval EFI_SUCCESS The function completed successfully
992 @retval EFI_INVALID_PARAMETER Invalid GpioPad
993 **/
994 EFI_STATUS
995 GpioMinGetPadCfgLock (
996 IN GPIO_PAD GpioPad,
997 OUT UINT32 *PadCfgLock
998 );
999
1000 /**
1001 This procedure will set PadCfgLock for selected pad
1002 Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfg),
1003 but to decrese memory footprint it was stripped from any GpioPad validation.
1004 Function intended to be used in Pre Mem phase.
1005
1006 @param[in] GpioPad GPIO pad
1007
1008 @retval EFI_SUCCESS The function completed successfully
1009 @retval EFI_INVALID_PARAMETER Invalid group or pad number
1010 **/
1011 EFI_STATUS
1012 GpioMinLockPadCfg (
1013 IN GPIO_PAD GpioPad
1014 );
1015
1016 /**
1017 This procedure will set PadCfgLockTx for selected pad
1018 Works exactly as it's counterpart in 'full' library (GpioMinLockPadCfgTx),
1019 but to decrese memory footprint it was stripped from any GpioPad validation.
1020 Function intended to be used in Pre Mem phase.
1021
1022 @param[in] GpioPad GPIO pad
1023
1024 @retval EFI_SUCCESS The function completed successfully
1025 @retval EFI_INVALID_PARAMETER Invalid group or pad number
1026 **/
1027 EFI_STATUS
1028 GpioMinLockPadCfgTx (
1029 IN GPIO_PAD GpioPad
1030 );
1031
1032 /**
1033 This function returns native signal name from PadFunction
1034
1035 @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
1036 @param[out] PadFunctionNameBuffer Caller allocated buffer of GPIO_NAME_LENGTH_MAX size
1037 @param[in] PadFunctionBufferSize Size of the buffer
1038
1039 @retval CHAR8* Pointer to the native signal name
1040 **/
1041 CHAR8*
1042 GpioGetNativeSignalName (
1043 IN UINT32 PadFunction,
1044 OUT CHAR8* PadFunctionNameBuffer,
1045 IN UINT32 PadFunctionBufferSize
1046 );
1047
1048 #endif // _GPIO_LIB_H_
GpioGetInputInversion
EFI_STATUS GpioGetInputInversion(IN GPIO_PAD GpioPad, OUT UINT32 *InvertState)
This procedure will get GPIO pad input inversion value.
GpioGetPadResetConfig
EFI_STATUS GpioGetPadResetConfig(IN GPIO_PAD GpioPad, IN GPIO_RESET_CONFIG *Value)
This procedure will get GPIO Reset settings.
GpioGetHostSwOwnershipForPad
EFI_STATUS GpioGetHostSwOwnershipForPad(IN GPIO_PAD GpioPad, OUT UINT32 *PadHostSwOwn)
This procedure will get Gpio Pad Host Software Ownership.
GpioSetOutputValue
EFI_STATUS GpioSetOutputValue(IN GPIO_PAD GpioPad, IN UINT32 Value)
This procedure will set GPIO output level.
GPIO_RESET_CONFIG
GPIO_RESET_CONFIG
GPIO Power Configuration GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0....
Definition: GpioConfig.h:253
GpioSetPadConfig
EFI_STATUS GpioSetPadConfig(IN GPIO_PAD GpioPad, IN GPIO_CONFIG *GpioData)
This procedure will configure multiple GPIO settings.
GpioGetHostSwOwnershipForGroupDw
EFI_STATUS GpioGetHostSwOwnershipForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *HostSwRegVal)
This procedure will get GPIO Host Software Pad Ownership for certain group.
GpioMinGetPadCfgLockTx
EFI_STATUS GpioMinGetPadCfgLockTx(IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLockTx)
This procedure will check state of Pad Config Tx Lock for selected pad Works exactly as it's counterp...
GpioSetPadInterruptConfig
EFI_STATUS GpioSetPadInterruptConfig(IN GPIO_PAD GpioPad, IN GPIO_INT_CONFIG Value)
This procedure will set GPIO interrupt settings.
GpioSetPadResetConfig
EFI_STATUS GpioSetPadResetConfig(IN GPIO_PAD GpioPad, IN GPIO_RESET_CONFIG Value)
This procedure will set GPIO Reset settings.
GPIO_PAD_OWN
GPIO_PAD_OWN
Possible values of Pad Ownership If Pad is not under Host ownership then GPIO registers are not acces...
Definition: GpioLib.h:350
GpioGetPadCfgLockForGroupDw
EFI_STATUS GpioGetPadCfgLockForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockRegVal)
This procedure will check state of Pad Config Lock for pads within one group.
GpioClearGpiSmiSts
EFI_STATUS GpioClearGpiSmiSts(IN GPIO_PAD GpioPad)
This procedure is used to clear SMI STS for a specified Pad.
GpioSetHostSwOwnershipForPad
EFI_STATUS GpioSetHostSwOwnershipForPad(IN GPIO_PAD GpioPad, IN UINT32 PadHostSwOwn)
This procedure will set Gpio Pad Host Software Ownership.
GpioConfig.h
Header file for GpioConfig structure used by GPIO library.
GpioGetGroupToGpeDwX
EFI_STATUS GpioGetGroupToGpeDwX(IN GPIO_GROUP *GroupToGpeDw0, IN GPIO_GROUP *GroupToGpeDw1, IN GPIO_GROUP *GroupToGpeDw2)
This procedure will get Group to GPE mapping.
GpioGetGroupName
CONST CHAR8 * GpioGetGroupName(IN UINT32 GroupIndex)
Generates GPIO group name from GroupIndex.
GpioLockPadCfgTx
EFI_STATUS GpioLockPadCfgTx(IN GPIO_PAD GpioPad)
This procedure will set PadCfgLockTx for selected pad.
GpioMinLockPadCfg
EFI_STATUS GpioMinLockPadCfg(IN GPIO_PAD GpioPad)
This procedure will set PadCfgLock for selected pad Works exactly as it's counterpart in 'full' libra...
GpioGetPadOwnership
EFI_STATUS GpioGetPadOwnership(IN GPIO_PAD GpioPad, OUT GPIO_PAD_OWN *PadOwnVal)
This procedure will get Gpio Pad Ownership.
GpioGetOutputValue
EFI_STATUS GpioGetOutputValue(IN GPIO_PAD GpioPad, OUT UINT32 *OutputVal)
This procedure will get GPIO output level.
GpioMinGetPadCfgLockForGroupDw
EFI_STATUS GpioMinGetPadCfgLockForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockRegVal)
Gpio Minimum Set.
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:47
GpioCheckFor2Tier
BOOLEAN GpioCheckFor2Tier(IN GPIO_PAD GpioPad)
This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture.
GpioLockPadCfgForGroupDw
EFI_STATUS GpioLockPadCfgForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToLock)
This procedure will set PadCfgLock for selected pads within one group.
GpioUnlockPadCfgForGroupDw
EFI_STATUS GpioUnlockPadCfgForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToUnlock)
This procedure will clear PadCfgLock for selected pads within one group.
GpioMinUnlockPadCfgTx
EFI_STATUS GpioMinUnlockPadCfgTx(IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLockTx for selected pad.
GpioDisableAllGpiSmi
EFI_STATUS GpioDisableAllGpiSmi(VOID)
This procedure is used to disable all GPI SMI.
GpioSetInputInversion
EFI_STATUS GpioSetInputInversion(IN GPIO_PAD GpioPad, IN UINT32 Value)
This procedure will configure GPIO input inversion.
GpioGetPadName
CHAR8 * GpioGetPadName(IN GPIO_PAD GpioPad, OUT CHAR8 *GpioNameBuffer, IN UINT32 GpioNameBufferSize)
Generates GPIO name from GpioPad.
GpioGetPadConfig
EFI_STATUS GpioGetPadConfig(IN GPIO_PAD GpioPad, OUT GPIO_CONFIG *GpioData)
This procedure will read multiple GPIO settings.
GpioGetInputValue
EFI_STATUS GpioGetInputValue(IN GPIO_PAD GpioPad, OUT UINT32 *InputVal)
This procedure will get GPIO input level.
GpioUnlockPadCfgTxForGroupDw
EFI_STATUS GpioUnlockPadCfgTxForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToUnlockTx)
This procedure will clear PadCfgLockTx for selected pads within one group.
GpioGetPadIoApicIrqNumber
EFI_STATUS GpioGetPadIoApicIrqNumber(IN GPIO_PAD GpioPad, OUT UINT32 *IrqNum)
This procedure will get GPIO IOxAPIC interrupt number.
GpioMinUnlockPadCfg
EFI_STATUS GpioMinUnlockPadCfg(IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLock for selected pad.
GpioGetGpiSmiNum
EFI_STATUS GpioGetGpiSmiNum(IN GPIO_PAD GpioPad, OUT UINTN *GpiNum)
This procedure is used to register GPI SMI dispatch function.
GpioUnlockPadCfg
EFI_STATUS GpioUnlockPadCfg(IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLock for selected pad.
GpioSetGroupDwToGpeDwX
EFI_STATUS GpioSetGroupDwToGpeDwX(IN GPIO_GROUP GroupToGpeDw0, IN UINT32 GroupDwForGpeDw0, IN GPIO_GROUP GroupToGpeDw1, IN UINT32 GroupDwForGpeDw1, IN GPIO_GROUP GroupToGpeDw2, IN UINT32 GroupDwForGpeDw2)
This procedure will set Group to GPE mapping.
GpioLockPadCfg
EFI_STATUS GpioLockPadCfg(IN GPIO_PAD GpioPad)
This procedure will set PadCfgLock for selected pad.
GpioSetHostSwOwnershipForGroupDw
EFI_STATUS GpioSetHostSwOwnershipForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 HostSwRegVal)
This procedure will get GPIO Host Software Pad Ownership for certain group.
GpioGetPadCfgLock
EFI_STATUS GpioGetPadCfgLock(IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLock)
This procedure will check state of Pad Config Lock for selected pad.
GpioLockPads
EFI_STATUS GpioLockPads(VOID)
This procedure is used to lock all GPIO pads except the ones which were requested during their config...
GpioMinLockPadCfgTx
EFI_STATUS GpioMinLockPadCfgTx(IN GPIO_PAD GpioPad)
This procedure will set PadCfgLockTx for selected pad Works exactly as it's counterpart in 'full' lib...
GpioClearAllGpiSmiSts
EFI_STATUS GpioClearAllGpiSmiSts(VOID)
This procedure is used by Smi Dispatcher and will clear all GPI SMI Status bits.
GpioGetPadCfgLockTxForGroupDw
EFI_STATUS GpioGetPadCfgLockTxForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockTxRegVal)
This procedure will check state of Pad Config Tx Lock for pads within one group.
GpioClearGpiGpeSts
EFI_STATUS GpioClearGpiGpeSts(IN GPIO_PAD GpioPad)
This procedure is used to clear GPE STS for a specified GpioPad.
GpioSetGroupToGpeDwX
EFI_STATUS GpioSetGroupToGpeDwX(IN GPIO_GROUP GroupToGpeDw0, IN GPIO_GROUP GroupToGpeDw1, IN GPIO_GROUP GroupToGpeDw2)
This procedure will set Group to GPE mapping.
GPIO_INT_CONFIG
GPIO_INT_CONFIG
GPIO interrupt configuration This setting is applicable only if pad is in GPIO mode and has input ena...
Definition: GpioConfig.h:231
GpioGetGroupDwToGpeDwX
EFI_STATUS GpioGetGroupDwToGpeDwX(OUT GPIO_GROUP *GroupToGpeDw0, OUT UINT32 *GroupDwForGpeDw0, OUT GPIO_GROUP *GroupToGpeDw1, OUT UINT32 *GroupDwForGpeDw1, OUT GPIO_GROUP *GroupToGpeDw2, OUT UINT32 *GroupDwForGpeDw2)
This procedure will get Group to GPE mapping.
GPIO_ELECTRICAL_CONFIG
GPIO_ELECTRICAL_CONFIG
GPIO Electrical Configuration Configuration options for GPIO termination setting.
Definition: GpioConfig.h:318
GpioGetGpiSmiSts
EFI_STATUS GpioGetGpiSmiSts(IN GPIO_PAD GpioPad, OUT BOOLEAN *SmiSts)
This procedure is used to get SMI STS for a specified Pad.
GpioGetGpeNumber
EFI_STATUS GpioGetGpeNumber(IN GPIO_PAD GpioPad, OUT UINT32 *GpeNumber)
This procedure will get GPE number for provided GpioPad.
GpioMinGetPadCfgLockTxForGroupDw
EFI_STATUS GpioMinGetPadCfgLockTxForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, OUT UINT32 *PadCfgLockTxRegVal)
This procedure will check state of Pad Config Tx Lock for pads within one group Works exactly as it's...
GpioSetPadElectricalConfig
EFI_STATUS GpioSetPadElectricalConfig(IN GPIO_PAD GpioPad, IN GPIO_ELECTRICAL_CONFIG Value)
This procedure will set GPIO electrical settings.
GpioUnlockPadCfgTx
EFI_STATUS GpioUnlockPadCfgTx(IN GPIO_PAD GpioPad)
This procedure will clear PadCfgLockTx for selected pad.
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:61
GpioMinGetPadCfgLock
EFI_STATUS GpioMinGetPadCfgLock(IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLock)
This procedure will check state of Pad Config Lock for selected pad Works exactly as it's counterpart...
GpioGetNativeSignalName
CHAR8 * GpioGetNativeSignalName(IN UINT32 PadFunction, OUT CHAR8 *PadFunctionNameBuffer, IN UINT32 PadFunctionBufferSize)
This function returns native signal name from PadFunction.
GPIO_CONFIG
GPIO configuration structure used for pin programming.
Definition: GpioConfig.h:67
GpioLockPadCfgTxForGroupDw
EFI_STATUS GpioLockPadCfgTxForGroupDw(IN GPIO_GROUP Group, IN UINT32 DwNum, IN UINT32 PadsToLockTx)
This procedure will set PadCfgLockTx for selected pads within one group.
GpioGetGpiGpeSts
EFI_STATUS GpioGetGpiGpeSts(IN GPIO_PAD GpioPad, OUT BOOLEAN *GpeSts)
This procedure is used to read GPE STS for a specified Pad.
GpioConfigurePads
EFI_STATUS GpioConfigurePads(IN UINT32 NumberOfItems, IN GPIO_INIT_CONFIG *GpioInitTableAddress)
This procedure will initialize multiple GPIO pins.
GpioGetPadCfgLockTx
EFI_STATUS GpioGetPadCfgLockTx(IN GPIO_PAD GpioPad, OUT UINT32 *PadCfgLockTx)
This procedure will check state of Pad Config Tx Lock for selected pad.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioNativeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
GpioNativeLib.h File Reference

Header file for GpioLib for native and Si specific usage. More...

#include <Library/GpioConfig.h>
Include dependency graph for GpioNativeLib.h:

Go to the source code of this file.

Functions

UINT32 | GpioGetPadPerGroup (IN GPIO_GROUP Group)
This procedure will get number of pads for certain GPIO group. More...
UINT32 | GpioGetNumberOfGroups (VOID)
This procedure will get number of groups. More...
GPIO_GROUP | GpioGetLowestGroup (VOID)
This procedure will get lowest group. More...
GPIO_GROUP | GpioGetHighestGroup (VOID)
This procedure will get highest group. More...
GPIO_GROUP | GpioGetGroupFromGpioPad (IN GPIO_PAD GpioPad)
This procedure will get group. More...
UINT32 | GpioGetGroupIndexFromGpioPad (IN GPIO_PAD GpioPad)
This procedure will get group index (0 based) from GpioPad. More...
UINT32 | GpioGetGroupIndexFromGroup (IN GPIO_GROUP GpioGroup)
This procedure will get group index (0 based) from group. More...
GPIO_GROUP | GpioGetGroupFromGroupIndex (IN UINT32 GroupIndex)
This procedure will get group from group index (0 based) More...
UINT32 | GpioGetPadNumberFromGpioPad (IN GPIO_PAD GpioPad)
This procedure will get pad number (0 based) from Gpio Pad. More...
GPIO_PAD | GpioGetGpioPadFromGroupAndPadNumber (IN GPIO_GROUP Group, IN UINT32 PadNumber)
This procedure will return GpioPad from Group and PadNumber. More...
GPIO_PAD | GpioGetGpioPadFromGroupIndexAndPadNumber (IN UINT32 GroupIndex, IN UINT32 PadNumber)
This procedure will return GpioPad from GroupIndex and PadNumber. More...
BOOLEAN | GpioIsSataGpEnabled (IN UINT32 SataCtrlIndex, IN UINTN SataPort)
This function checks if SATA GP pin is enabled. More...

Detailed Description

Header file for GpioLib for native and Si specific usage.

All function in this library is available for PEI, DXE, and SMM,

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioNativeLib.h.

Function Documentation

◆ GpioGetGpioPadFromGroupAndPadNumber()

GPIO_PAD GpioGetGpioPadFromGroupAndPadNumber | ( | IN GPIO_GROUP | Group,
 |  | IN UINT32 | PadNumber
 | ) |  |

This procedure will return GpioPad from Group and PadNumber.

Parameters
[in] | Group | GPIO group
[in] | PadNumber | GPIO PadNumber
Return values
GpioPad GpioPad

◆ GpioGetGpioPadFromGroupIndexAndPadNumber()

GPIO_PAD GpioGetGpioPadFromGroupIndexAndPadNumber | ( | IN UINT32 | GroupIndex,
 |  | IN UINT32 | PadNumber
 | ) |  |

This procedure will return GpioPad from GroupIndex and PadNumber.

Parameters
[in] | GroupIndex | GPIO GroupIndex
[in] | PadNumber | GPIO PadNumber
Return values
GpioPad GpioPad

◆ GpioGetGroupFromGpioPad()

GPIO_GROUP GpioGetGroupFromGpioPad ( IN GPIO_PAD GpioPad )

This procedure will get group.

Parameters
[in] GpioPad Gpio Pad
Return values
Value Group

◆ GpioGetGroupFromGroupIndex()

GPIO_GROUP GpioGetGroupFromGroupIndex ( IN UINT32 GroupIndex )

This procedure will get group from group index (0 based)

Parameters
[in] GroupIndex Group Index
Return values
GpioGroup Gpio Group

◆ GpioGetGroupIndexFromGpioPad()

UINT32 GpioGetGroupIndexFromGpioPad ( IN GPIO_PAD GpioPad )

This procedure will get group index (0 based) from GpioPad.

Parameters
[in] GpioPad Gpio Pad
Return values
Value Group Index

◆ GpioGetGroupIndexFromGroup()

UINT32 GpioGetGroupIndexFromGroup ( IN GPIO_GROUP GpioGroup )

This procedure will get group index (0 based) from group.

Parameters
[in] GpioGroup Gpio Group
Return values
Value Group Index

◆ GpioGetHighestGroup()

GPIO_GROUP GpioGetHighestGroup ( VOID )

This procedure will get highest group.

Parameters
[in] none
Return values
Value Highest Group

◆ GpioGetLowestGroup()

GPIO_GROUP GpioGetLowestGroup ( VOID )

This procedure will get lowest group.

Parameters
[in] none
Return values
Value Lowest Group

◆ GpioGetNumberOfGroups()

UINT32 GpioGetNumberOfGroups ( VOID )

This procedure will get number of groups.

Parameters
[in] none
Return values
Value Group number

◆ GpioGetPadNumberFromGpioPad()

UINT32 GpioGetPadNumberFromGpioPad ( IN GPIO_PAD GpioPad )

This procedure will get pad number (0 based) from Gpio Pad.

Parameters
[in] GpioPad Gpio Pad
Return values
Value Pad Number

◆ GpioGetPadPerGroup()

UINT32 GpioGetPadPerGroup ( IN GPIO_GROUP Group )

This procedure will get number of pads for certain GPIO group.

Parameters
[in] Group GPIO group number
Return values
Value Pad number for group If illegal group number then return 0

◆ GpioIsSataGpEnabled()

BOOLEAN GpioIsSataGpEnabled | ( | IN UINT32 | SataCtrlIndex,
 |  | IN UINTN | SataPort
 | ) |  |

This function checks if SATA GP pin is enabled.

Parameters
[in] | SataCtrlIndex | SATA Controller Index
[in] | SataPort | SATA port number
Return values
TRUE SATA GPx is enabled (pad is in required native mode) FALSE SATA GPx is not enabled
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioNativeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GpioNativeLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for GpioLib for native and Si specific usage.
3 All function in this library is available for PEI, DXE, and SMM,
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2014 - 2018 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _GPIO_NATIVE_LIB_H_
37 #define _GPIO_NATIVE_LIB_H_
38
39 #include <Library/GpioConfig.h>
40
41 /**
42 This procedure will get number of pads for certain GPIO group
43
44 @param[in] Group GPIO group number
45
46 @retval Value Pad number for group
47 If illegal group number then return 0
48 **/
49 UINT32
50 GpioGetPadPerGroup (
51 IN GPIO_GROUP Group
52 );
53
54 /**
55 This procedure will get number of groups
56
57 @param[in] none
58
59 @retval Value Group number
60 **/
61 UINT32
62 GpioGetNumberOfGroups (
63 VOID
64 );
65 /**
66 This procedure will get lowest group
67
68 @param[in] none
69
70 @retval Value Lowest Group
71 **/
72 GPIO_GROUP
73 GpioGetLowestGroup (
74 VOID
75 );
76
77 /**
78 This procedure will get highest group
79
80 @param[in] none
81
82 @retval Value Highest Group
83 **/
84 GPIO_GROUP
85 GpioGetHighestGroup (
86 VOID
87 );
88
89 /**
90 This procedure will get group
91
92 @param[in] GpioPad Gpio Pad
93
94 @retval Value Group
95 **/
96 GPIO_GROUP
97 GpioGetGroupFromGpioPad (
98 IN GPIO_PAD GpioPad
99 );
100
101 /**
102 This procedure will get group index (0 based) from GpioPad
103
104 @param[in] GpioPad Gpio Pad
105
106 @retval Value Group Index
107 **/
108 UINT32
109 GpioGetGroupIndexFromGpioPad (
110 IN GPIO_PAD GpioPad
111 );
112
113 /**
114 This procedure will get group index (0 based) from group
115
116 @param[in] GpioGroup Gpio Group
117
118 @retval Value Group Index
119 **/
120 UINT32
121 GpioGetGroupIndexFromGroup (
122 IN GPIO_GROUP GpioGroup
123 );
124
125 /**
126 This procedure will get group from group index (0 based)
127
128 @param[in] GroupIndex Group Index
129
130 @retval GpioGroup Gpio Group
131 **/
132 GPIO_GROUP
133 GpioGetGroupFromGroupIndex (
134 IN UINT32 GroupIndex
135 );
136
137 /**
138 This procedure will get pad number (0 based) from Gpio Pad
139
140 @param[in] GpioPad Gpio Pad
141
142 @retval Value Pad Number
143 **/
144 UINT32
145 GpioGetPadNumberFromGpioPad (
146 IN GPIO_PAD GpioPad
147 );
148
149 /**
150 This procedure will return GpioPad from Group and PadNumber
151
152 @param[in] Group GPIO group
153 @param[in] PadNumber GPIO PadNumber
154
155 @retval GpioPad GpioPad
156 **/
157 GPIO_PAD
158 GpioGetGpioPadFromGroupAndPadNumber (
159 IN GPIO_GROUP Group,
160 IN UINT32 PadNumber
161 );
162
163 /**
164 This procedure will return GpioPad from GroupIndex and PadNumber
165
166 @param[in] GroupIndex GPIO GroupIndex
167 @param[in] PadNumber GPIO PadNumber
168
169 @retval GpioPad GpioPad
170 **/
171 GPIO_PAD
172 GpioGetGpioPadFromGroupIndexAndPadNumber (
173 IN UINT32 GroupIndex,
174 IN UINT32 PadNumber
175 );
176
177 /**
178 This function checks if SATA GP pin is enabled
179
180 @param[in] SataCtrlIndex SATA Controller Index
181 @param[in] SataPort SATA port number
182
183 @retval TRUE SATA GPx is enabled (pad is in required native mode)
184 FALSE SATA GPx is not enabled
185 **/
186 BOOLEAN
187 GpioIsSataGpEnabled (
188 IN UINT32 SataCtrlIndex,
189 IN UINTN SataPort
190 );
191
192 #endif // _GPIO_NATIVE_LIB_H_
GpioGetPadPerGroup
UINT32 GpioGetPadPerGroup(IN GPIO_GROUP Group)
This procedure will get number of pads for certain GPIO group.
GpioConfig.h
Header file for GpioConfig structure used by GPIO library.
GpioGetGroupIndexFromGpioPad
UINT32 GpioGetGroupIndexFromGpioPad(IN GPIO_PAD GpioPad)
This procedure will get group index (0 based) from GpioPad.
GpioGetPadNumberFromGpioPad
UINT32 GpioGetPadNumberFromGpioPad(IN GPIO_PAD GpioPad)
This procedure will get pad number (0 based) from Gpio Pad.
GpioGetNumberOfGroups
UINT32 GpioGetNumberOfGroups(VOID)
This procedure will get number of groups.
GPIO_PAD
UINT32 GPIO_PAD
For any GpioPad usage in code use GPIO_PAD type.
Definition: GpioConfig.h:47
GpioGetLowestGroup
GPIO_GROUP GpioGetLowestGroup(VOID)
This procedure will get lowest group.
GpioGetGroupFromGroupIndex
GPIO_GROUP GpioGetGroupFromGroupIndex(IN UINT32 GroupIndex)
This procedure will get group from group index (0 based)
GpioGetGpioPadFromGroupIndexAndPadNumber
GPIO_PAD GpioGetGpioPadFromGroupIndexAndPadNumber(IN UINT32 GroupIndex, IN UINT32 PadNumber)
This procedure will return GpioPad from GroupIndex and PadNumber.
GpioGetGpioPadFromGroupAndPadNumber
GPIO_PAD GpioGetGpioPadFromGroupAndPadNumber(IN GPIO_GROUP Group, IN UINT32 PadNumber)
This procedure will return GpioPad from Group and PadNumber.
GpioGetGroupIndexFromGroup
UINT32 GpioGetGroupIndexFromGroup(IN GPIO_GROUP GpioGroup)
This procedure will get group index (0 based) from group.
GPIO_GROUP
UINT32 GPIO_GROUP
For any GpioGroup usage in code use GPIO_GROUP type.
Definition: GpioConfig.h:61
GpioIsSataGpEnabled
BOOLEAN GpioIsSataGpEnabled(IN UINT32 SataCtrlIndex, IN UINTN SataPort)
This function checks if SATA GP pin is enabled.
GpioGetGroupFromGpioPad
GPIO_GROUP GpioGetGroupFromGpioPad(IN GPIO_PAD GpioPad)
This procedure will get group.
GpioGetHighestGroup
GPIO_GROUP GpioGetHighestGroup(VOID)
This procedure will get highest group.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer2H.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
Macros
GpioPinsVer2H.h File Reference

GPIO pins for TGL-PCH-H,. More...

Go to the source code of this file.

Macros

#define | GPIO_VER2_H_CHIPSET_ID 0x8
This header file should be used together with PCH GPIO lib in C and ASL. More...
#define | GPIO_VER2_H_GROUP_GPP_A 0x0800
TGL LP GPIO Groups Use below for functions from PCH GPIO Lib which require GpioGroup as argument.
#define | GPIO_VER2_H_SPI0_IO_2 0x08000000
TGL H GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument. More...

Detailed Description

GPIO pins for TGL-PCH-H,.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioPinsVer2H.h.

Macro Definition Documentation

◆ GPIO_VER2_H_CHIPSET_ID

#define GPIO_VER2_H_CHIPSET_ID 0x8

This header file should be used together with PCH GPIO lib in C and ASL.

All defines used must match both ASL/C syntax Unique ID used in GpioPad defines

Definition at line 46 of file GpioPinsVer2H.h.

◆ GPIO_VER2_H_SPI0_IO_2

#define GPIO_VER2_H_SPI0_IO_2 0x08000000

TGL H GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument.

Encoding used here has all information required by library functions

Definition at line 79 of file GpioPinsVer2H.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer2H.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
GpioPinsVer2H.h
Go to the documentation of this file.
1 /** @file
2 GPIO pins for TGL-PCH-H,
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_PINS_VER2_H_H_
36 #define _GPIO_PINS_VER2_H_H_
37 ///
38 /// This header file should be used together with
39 /// PCH GPIO lib in C and ASL. All defines used
40 /// must match both ASL/C syntax
41 ///
42
43 ///
44 /// Unique ID used in GpioPad defines
45 ///
46 #define GPIO_VER2_H_CHIPSET_ID 0x8
47
48 ///
49 /// TGL LP GPIO Groups
50 /// Use below for functions from PCH GPIO Lib which
51 /// require GpioGroup as argument
52 ///
53 #define GPIO_VER2_H_GROUP_GPP_A 0x0800
54 #define GPIO_VER2_H_GROUP_GPP_R 0x0801
55 #define GPIO_VER2_H_GROUP_GPP_B 0x0802
56 #define GPIO_VER2_H_GROUP_VGPIO_0 0x0803
57 #define GPIO_VER2_H_GROUP_GPP_D 0x0804
58 #define GPIO_VER2_H_GROUP_GPP_C 0x0805
59 #define GPIO_VER2_H_GROUP_GPP_S 0x0806
60 #define GPIO_VER2_H_GROUP_GPP_G 0x0807
61 #define GPIO_VER2_H_GROUP_VGPIO 0x0808
62 #define GPIO_VER2_H_GROUP_GPD 0x0809
63 #define GPIO_VER2_H_GROUP_GPP_E 0x080A
64 #define GPIO_VER2_H_GROUP_GPP_F 0x080B
65 #define GPIO_VER2_H_GROUP_VGPIO_3 0x080C
66 #define GPIO_VER2_H_GROUP_GPP_H 0x080D
67 #define GPIO_VER2_H_GROUP_GPP_J 0x080E
68 #define GPIO_VER2_H_GROUP_GPP_K 0x080F
69 #define GPIO_VER2_H_GROUP_GPP_I 0x0810
70 #define GPIO_VER2_H_GROUP_JTAG 0x0811
71 #define GPIO_VER2_H_GROUP_CPU 0x0812
72
73 ///
74 /// TGL H GPIO pins
75 /// Use below for functions from PCH GPIO Lib which
76 /// require GpioPad as argument. Encoding used here
77 /// has all information required by library functions
78 ///
79 #define GPIO_VER2_H_SPI0_IO_2 0x08000000
80 #define GPIO_VER2_H_SPI0_IO_3 0x08000001
81 #define GPIO_VER2_H_SPI0_MOSI_IO_0 0x08000002
82 #define GPIO_VER2_H_SPI0_MISO_IO_1 0x08000003
83 #define GPIO_VER2_H_SPI0_TPM_CSB 0x08000004
84 #define GPIO_VER2_H_SPI0_FLASH_0_CSB 0x08000005
85 #define GPIO_VER2_H_SPI0_FLASH_1_CSB 0x08000006
86 #define GPIO_VER2_H_SPI0_CLK 0x08000007
87 #define GPIO_VER2_H_GPP_A0 0x08000008
88 #define GPIO_VER2_H_GPP_A1 0x08000009
89 #define GPIO_VER2_H_GPP_A2 0x0800000A
90 #define GPIO_VER2_H_GPP_A3 0x0800000B
91 #define GPIO_VER2_H_GPP_A4 0x0800000C
92 #define GPIO_VER2_H_GPP_A5 0x0800000D
93 #define GPIO_VER2_H_GPP_A6 0x0800000E
94 #define GPIO_VER2_H_GPP_A7 0x0800000F
95 #define GPIO_VER2_H_GPP_A8 0x08000010
96 #define GPIO_VER2_H_GPP_A9 0x08000011
97 #define GPIO_VER2_H_GPP_A10 0x08000012
98 #define GPIO_VER2_H_GPP_A11 0x08000013
99 #define GPIO_VER2_H_GPP_A12 0x08000014
100 #define GPIO_VER2_H_GPP_A13 0x08000015
101 #define GPIO_VER2_H_GPP_A14 0x08000016
102 #define GPIO_VER2_H_SPI0_CLK_LOOPBK 0x08000017
103 #define GPIO_VER2_H_ESPI_CLK_LOOPBK 0x08000018
104
105 #define GPIO_VER2_H_GPP_R0 0x08010000
106 #define GPIO_VER2_H_GPP_R1 0x08010001
107 #define GPIO_VER2_H_GPP_R2 0x08010002
108 #define GPIO_VER2_H_GPP_R3 0x08010003
109 #define GPIO_VER2_H_GPP_R4 0x08010004
110 #define GPIO_VER2_H_GPP_R5 0x08010005
111 #define GPIO_VER2_H_GPP_R6 0x08010006
112 #define GPIO_VER2_H_GPP_R7 0x08010007
113 #define GPIO_VER2_H_GPP_R8 0x08010008
114 #define GPIO_VER2_H_GPP_R9 0x08010009
115 #define GPIO_VER2_H_GPP_R10 0x0801000A
116 #define GPIO_VER2_H_GPP_R11 0x0801000B
117 #define GPIO_VER2_H_GPP_R12 0x0801000C
118 #define GPIO_VER2_H_GPP_R13 0x0801000D
119 #define GPIO_VER2_H_GPP_R14 0x0801000E
120 #define GPIO_VER2_H_GPP_R15 0x0801000F
121 #define GPIO_VER2_H_GPP_R16 0x08010010
122 #define GPIO_VER2_H_GPP_R17 0x08010011
123 #define GPIO_VER2_H_GPP_R18 0x08010012
124 #define GPIO_VER2_H_GPP_R19 0x08010013
125
126 #define GPIO_VER2_H_GPP_B0 0x08020000
127 #define GPIO_VER2_H_GPP_B1 0x08020001
128 #define GPIO_VER2_H_GPP_B2 0x08020002
129 #define GPIO_VER2_H_GPP_B3 0x08020003
130 #define GPIO_VER2_H_GPP_B4 0x08020004
131 #define GPIO_VER2_H_GPP_B5 0x08020005
132 #define GPIO_VER2_H_GPP_B6 0x08020006
133 #define GPIO_VER2_H_GPP_B7 0x08020007
134 #define GPIO_VER2_H_GPP_B8 0x08020008
135 #define GPIO_VER2_H_GPP_B9 0x08020009
136 #define GPIO_VER2_H_GPP_B10 0x0802000A
137 #define GPIO_VER2_H_GPP_B11 0x0802000B
138 #define GPIO_VER2_H_GPP_B12 0x0802000C
139 #define GPIO_VER2_H_GPP_B13 0x0802000D
140 #define GPIO_VER2_H_GPP_B14 0x0802000E
141 #define GPIO_VER2_H_GPP_B15 0x0802000F
142 #define GPIO_VER2_H_GPP_B16 0x08020010
143 #define GPIO_VER2_H_GPP_B17 0x08020011
144 #define GPIO_VER2_H_GPP_B18 0x08020012
145 #define GPIO_VER2_H_GPP_B19 0x08020013
146 #define GPIO_VER2_H_GPP_B20 0x08020014
147 #define GPIO_VER2_H_GPP_B21 0x08020015
148 #define GPIO_VER2_H_GPP_B22 0x08020016
149 #define GPIO_VER2_H_GPP_B23 0x08020017
150 #define GPIO_VER2_H_GSPI0_CLK_LOOPBK 0x08020018
151 #define GPIO_VER2_H_GSPI1_CLK_LOOPBK 0x08020019
152
153 #define GPIO_VER2_H_VGPIO_USB_0 0x08030000
154 #define GPIO_VER2_H_VGPIO_USB_1 0x08030001
155 #define GPIO_VER2_H_VGPIO_USB_2 0x08030002
156 #define GPIO_VER2_H_VGPIO_USB_3 0x08030003
157 #define GPIO_VER2_H_VGPIO_USB_8 0x08030004
158 #define GPIO_VER2_H_VGPIO_USB_9 0x08030005
159 #define GPIO_VER2_H_VGPIO_USB_10 0x08030006
160 #define GPIO_VER2_H_VGPIO_USB_11 0x08030007
161
162 #define GPIO_VER2_H_GPP_D0 0x08040000
163 #define GPIO_VER2_H_GPP_D1 0x08040001
164 #define GPIO_VER2_H_GPP_D2 0x08040002
165 #define GPIO_VER2_H_GPP_D3 0x08040003
166 #define GPIO_VER2_H_GPP_D4 0x08040004
167 #define GPIO_VER2_H_GPP_D5 0x08040005
168 #define GPIO_VER2_H_GPP_D6 0x08040006
169 #define GPIO_VER2_H_GPP_D7 0x08040007
170 #define GPIO_VER2_H_GPP_D8 0x08040008
171 #define GPIO_VER2_H_GPP_D9 0x08040009
172 #define GPIO_VER2_H_GPP_D10 0x0804000A
173 #define GPIO_VER2_H_GPP_D11 0x0804000B
174 #define GPIO_VER2_H_GPP_D12 0x0804000C
175 #define GPIO_VER2_H_GPP_D13 0x0804000D
176 #define GPIO_VER2_H_GPP_D14 0x0804000E
177 #define GPIO_VER2_H_GPP_D15 0x0804000F
178 #define GPIO_VER2_H_GPP_D16 0x08040010
179 #define GPIO_VER2_H_GPP_D17 0x08040011
180 #define GPIO_VER2_H_GPP_D18 0x08040012
181 #define GPIO_VER2_H_GPP_D19 0x08040013
182 #define GPIO_VER2_H_GPP_D20 0x08040014
183 #define GPIO_VER2_H_GPP_D21 0x08040015
184 #define GPIO_VER2_H_GPP_D22 0x08040016
185 #define GPIO_VER2_H_GPP_D23 0x08040017
186 #define GPIO_VER2_H_SPI1_THC0_CLK_LOOPBK 0x08040018
187 #define GPIO_VER2_H_GPI3_THC1_CLK_LOOPBK 0x08040019
188
189 #define GPIO_VER2_H_GPP_C0 0x08050000
190 #define GPIO_VER2_H_GPP_C1 0x08050001
191 #define GPIO_VER2_H_GPP_C2 0x08050002
192 #define GPIO_VER2_H_GPP_C3 0x08050003
193 #define GPIO_VER2_H_GPP_C4 0x08050004
194 #define GPIO_VER2_H_GPP_C5 0x08050005
195 #define GPIO_VER2_H_GPP_C6 0x08050006
196 #define GPIO_VER2_H_GPP_C7 0x08050007
197 #define GPIO_VER2_H_GPP_C8 0x08050008
198 #define GPIO_VER2_H_GPP_C9 0x08050009
199 #define GPIO_VER2_H_GPP_C10 0x0805000A
200 #define GPIO_VER2_H_GPP_C11 0x0805000B
201 #define GPIO_VER2_H_GPP_C12 0x0805000C
202 #define GPIO_VER2_H_GPP_C13 0x0805000D
203 #define GPIO_VER2_H_GPP_C14 0x0805000E
204 #define GPIO_VER2_H_GPP_C15 0x0805000F
205 #define GPIO_VER2_H_GPP_C16 0x08050010
206 #define GPIO_VER2_H_GPP_C17 0x08050011
207 #define GPIO_VER2_H_GPP_C18 0x08050012
208 #define GPIO_VER2_H_GPP_C19 0x08050013
209 #define GPIO_VER2_H_GPP_C20 0x08050014
210 #define GPIO_VER2_H_GPP_C21 0x08050015
211 #define GPIO_VER2_H_GPP_C22 0x08050016
212 #define GPIO_VER2_H_GPP_C23 0x08050017
213
214 #define GPIO_VER2_H_GPP_S0 0x08060000
215 #define GPIO_VER2_H_GPP_S1 0x08060001
216 #define GPIO_VER2_H_GPP_S2 0x08060002
217 #define GPIO_VER2_H_GPP_S3 0x08060003
218 #define GPIO_VER2_H_GPP_S4 0x08060004
219 #define GPIO_VER2_H_GPP_S5 0x08060005
220 #define GPIO_VER2_H_GPP_S6 0x08060006
221 #define GPIO_VER2_H_GPP_S7 0x08060007
222
223 #define GPIO_VER2_H_GPP_G0 0x08070000
224 #define GPIO_VER2_H_GPP_G1 0x08070001
225 #define GPIO_VER2_H_GPP_G2 0x08070002
226 #define GPIO_VER2_H_GPP_G3 0x08070003
227 #define GPIO_VER2_H_GPP_G4 0x08070004
228 #define GPIO_VER2_H_GPP_G5 0x08070005
229 #define GPIO_VER2_H_GPP_G6 0x08070006
230 #define GPIO_VER2_H_GPP_G7 0x08070007
231 #define GPIO_VER2_H_GPP_G8 0x08070008
232 #define GPIO_VER2_H_GPP_G9 0x08070009
233 #define GPIO_VER2_H_GPP_G10 0x0807000A
234 #define GPIO_VER2_H_GPP_G11 0x0807000B
235 #define GPIO_VER2_H_GPP_G12 0x0807000C
236 #define GPIO_VER2_H_GPP_G13 0x0807000D
237 #define GPIO_VER2_H_GPP_G14 0x0807000E
238 #define GPIO_VER2_H_GPP_G15 0x0807000F
239
240 #define GPIO_VER2_H_VGPIO0 0x08080000
241 #define GPIO_VER2_H_VGPIO4 0x08080001
242 #define GPIO_VER2_H_VGPIO5 0x08080002
243 #define GPIO_VER2_H_VGPIO6 0x08080003
244 #define GPIO_VER2_H_VGPIO7 0x08080004
245 #define GPIO_VER2_H_VGPIO8 0x08080005
246 #define GPIO_VER2_H_VGPIO9 0x08080006
247 #define GPIO_VER2_H_VGPIO10 0x08080007
248 #define GPIO_VER2_H_VGPIO11 0x08080008
249 #define GPIO_VER2_H_VGPIO12 0x08080009
250 #define GPIO_VER2_H_VGPIO13 0x0808000A
251 #define GPIO_VER2_H_VGPIO18 0x0808000B
252 #define GPIO_VER2_H_VGPIO19 0x0808000C
253 #define GPIO_VER2_H_VGPIO20 0x0808000D
254 #define GPIO_VER2_H_VGPIO21 0x0808000E
255 #define GPIO_VER2_H_VGPIO22 0x0808000F
256 #define GPIO_VER2_H_VGPIO23 0x08080010
257 #define GPIO_VER2_H_VGPIO24 0x08080011
258 #define GPIO_VER2_H_VGPIO25 0x08080012
259 #define GPIO_VER2_H_VGPIO30 0x08080013
260 #define GPIO_VER2_H_VGPIO31 0x08080014
261 #define GPIO_VER2_H_VGPIO32 0x08080015
262 #define GPIO_VER2_H_VGPIO33 0x08080016
263 #define GPIO_VER2_H_VGPIO34 0x08080017
264 #define GPIO_VER2_H_VGPIO35 0x08080018
265 #define GPIO_VER2_H_VGPIO36 0x08080019
266 #define GPIO_VER2_H_VGPIO37 0x0808001A
267
268 #define GPIO_VER2_H_GPD0 0x08090000
269 #define GPIO_VER2_H_GPD1 0x08090001
270 #define GPIO_VER2_H_GPD2 0x08090002
271 #define GPIO_VER2_H_GPD3 0x08090003
272 #define GPIO_VER2_H_GPD4 0x08090004
273 #define GPIO_VER2_H_GPD5 0x08090005
274 #define GPIO_VER2_H_GPD6 0x08090006
275 #define GPIO_VER2_H_GPD7 0x08090007
276 #define GPIO_VER2_H_GPD8 0x08090008
277 #define GPIO_VER2_H_GPD9 0x08090009
278 #define GPIO_VER2_H_GPD10 0x0809000A
279 #define GPIO_VER2_H_GPD11 0x0809000B
280 #define GPIO_VER2_H_GPD12 0x0809000C
281 #define GPIO_VER2_H_SLP_LANB 0x0809000D
282 #define GPIO_VER2_H_SLP_SUSB 0x0809000E
283 #define GPIO_VER2_H_WAKEB 0x0809000F
284 #define GPIO_VER2_H_DRAM_RESETB 0x08090010
285
286 #define GPIO_VER2_H_GPP_E0 0x080A0000
287 #define GPIO_VER2_H_GPP_E1 0x080A0001
288 #define GPIO_VER2_H_GPP_E2 0x080A0002
289 #define GPIO_VER2_H_GPP_E3 0x080A0003
290 #define GPIO_VER2_H_GPP_E4 0x080A0004
291 #define GPIO_VER2_H_GPP_E5 0x080A0005
292 #define GPIO_VER2_H_GPP_E6 0x080A0006
293 #define GPIO_VER2_H_GPP_E7 0x080A0007
294 #define GPIO_VER2_H_GPP_E8 0x080A0008
295 #define GPIO_VER2_H_GPP_E9 0x080A0009
296 #define GPIO_VER2_H_GPP_E10 0x080A000A
297 #define GPIO_VER2_H_GPP_E11 0x080A000B
298 #define GPIO_VER2_H_GPP_E12 0x080A000C
299
300 #define GPIO_VER2_H_GPP_F0 0x080B0000
301 #define GPIO_VER2_H_GPP_F1 0x080B0001
302 #define GPIO_VER2_H_GPP_F2 0x080B0002
303 #define GPIO_VER2_H_GPP_F3 0x080B0003
304 #define GPIO_VER2_H_GPP_F4 0x080B0004
305 #define GPIO_VER2_H_GPP_F5 0x080B0005
306 #define GPIO_VER2_H_GPP_F6 0x080B0006
307 #define GPIO_VER2_H_GPP_F7 0x080B0007
308 #define GPIO_VER2_H_GPP_F8 0x080B0008
309 #define GPIO_VER2_H_GPP_F9 0x080B0009
310 #define GPIO_VER2_H_GPP_F10 0x080B000A
311 #define GPIO_VER2_H_GPP_F11 0x080B000B
312 #define GPIO_VER2_H_GPP_F12 0x080B000C
313 #define GPIO_VER2_H_GPP_F13 0x080B000D
314 #define GPIO_VER2_H_GPP_F14 0x080B000E
315 #define GPIO_VER2_H_GPP_F15 0x080B000F
316 #define GPIO_VER2_H_GPP_F16 0x080B0010
317 #define GPIO_VER2_H_GPP_F17 0x080B0011
318 #define GPIO_VER2_H_GPP_F18 0x080B0012
319 #define GPIO_VER2_H_GPP_F19 0x080B0013
320 #define GPIO_VER2_H_GPP_F20 0x080B0014
321 #define GPIO_VER2_H_GPP_F21 0x080B0015
322 #define GPIO_VER2_H_GPP_F22 0x080B0016
323 #define GPIO_VER2_H_GPP_F23 0x080B0017
324
325 #define GPIO_VER2_H_VGPIO_PCIE_0 0x080C0000
326 #define GPIO_VER2_H_VGPIO_PCIE_1 0x080C0001
327 #define GPIO_VER2_H_VGPIO_PCIE_2 0x080C0002
328 #define GPIO_VER2_H_VGPIO_PCIE_3 0x080C0003
329 #define GPIO_VER2_H_VGPIO_PCIE_4 0x080C0004
330 #define GPIO_VER2_H_VGPIO_PCIE_5 0x080C0005
331 #define GPIO_VER2_H_VGPIO_PCIE_6 0x080C0006
332 #define GPIO_VER2_H_VGPIO_PCIE_7 0x080C0007
333 #define GPIO_VER2_H_VGPIO_PCIE_8 0x080C0008
334 #define GPIO_VER2_H_VGPIO_PCIE_9 0x080C0009
335 #define GPIO_VER2_H_VGPIO_PCIE_10 0x080C000A
336 #define GPIO_VER2_H_VGPIO_PCIE_11 0x080C000B
337 #define GPIO_VER2_H_VGPIO_PCIE_12 0x080C000C
338 #define GPIO_VER2_H_VGPIO_PCIE_13 0x080C000D
339 #define GPIO_VER2_H_VGPIO_PCIE_14 0x080C000E
340 #define GPIO_VER2_H_VGPIO_PCIE_15 0x080C000F
341 #define GPIO_VER2_H_VGPIO_PCIE_16 0x080C0010
342 #define GPIO_VER2_H_VGPIO_PCIE_17 0x080C0011
343 #define GPIO_VER2_H_VGPIO_PCIE_18 0x080C0012
344 #define GPIO_VER2_H_VGPIO_PCIE_19 0x080C0013
345 #define GPIO_VER2_H_VGPIO_PCIE_20 0x080C0014
346 #define GPIO_VER2_H_VGPIO_PCIE_21 0x080C0015
347 #define GPIO_VER2_H_VGPIO_PCIE_22 0x080C0016
348 #define GPIO_VER2_H_VGPIO_PCIE_23 0x080C0017
349 #define GPIO_VER2_H_VGPIO_PCIE_24 0x080C0018
350 #define GPIO_VER2_H_VGPIO_PCIE_25 0x080C0019
351 #define GPIO_VER2_H_VGPIO_PCIE_26 0x080C001A
352 #define GPIO_VER2_H_VGPIO_PCIE_27 0x080C001B
353 #define GPIO_VER2_H_VGPIO_PCIE_28 0x080C001C
354 #define GPIO_VER2_H_VGPIO_PCIE_29 0x080C001D
355 #define GPIO_VER2_H_VGPIO_PCIE_30 0x080C001E
356 #define GPIO_VER2_H_VGPIO_PCIE_31 0x080C001F
357 #define GPIO_VER2_H_VGPIO_PCIE_32 0x080C0020
358 #define GPIO_VER2_H_VGPIO_PCIE_33 0x080C0021
359 #define GPIO_VER2_H_VGPIO_PCIE_34 0x080C0022
360 #define GPIO_VER2_H_VGPIO_PCIE_35 0x080C0023
361 #define GPIO_VER2_H_VGPIO_PCIE_36 0x080C0024
362 #define GPIO_VER2_H_VGPIO_PCIE_37 0x080C0025
363 #define GPIO_VER2_H_VGPIO_PCIE_38 0x080C0026
364 #define GPIO_VER2_H_VGPIO_PCIE_39 0x080C0027
365 #define GPIO_VER2_H_VGPIO_PCIE_40 0x080C0028
366 #define GPIO_VER2_H_VGPIO_PCIE_41 0x080C0029
367 #define GPIO_VER2_H_VGPIO_PCIE_42 0x080C002A
368 #define GPIO_VER2_H_VGPIO_PCIE_43 0x080C002B
369 #define GPIO_VER2_H_VGPIO_PCIE_44 0x080C002C
370 #define GPIO_VER2_H_VGPIO_PCIE_45 0x080C002D
371 #define GPIO_VER2_H_VGPIO_PCIE_46 0x080C002E
372 #define GPIO_VER2_H_VGPIO_PCIE_47 0x080C002F
373 #define GPIO_VER2_H_VGPIO_PCIE_48 0x080C0030
374 #define GPIO_VER2_H_VGPIO_PCIE_49 0x080C0031
375 #define GPIO_VER2_H_VGPIO_PCIE_50 0x080C0032
376 #define GPIO_VER2_H_VGPIO_PCIE_51 0x080C0033
377 #define GPIO_VER2_H_VGPIO_PCIE_52 0x080C0034
378 #define GPIO_VER2_H_VGPIO_PCIE_53 0x080C0035
379 #define GPIO_VER2_H_VGPIO_PCIE_54 0x080C0036
380 #define GPIO_VER2_H_VGPIO_PCIE_55 0x080C0037
381 #define GPIO_VER2_H_VGPIO_PCIE_56 0x080C0038
382 #define GPIO_VER2_H_VGPIO_PCIE_57 0x080C0039
383 #define GPIO_VER2_H_VGPIO_PCIE_58 0x080C003A
384 #define GPIO_VER2_H_VGPIO_PCIE_59 0x080C003B
385 #define GPIO_VER2_H_VGPIO_PCIE_60 0x080C003C
386 #define GPIO_VER2_H_VGPIO_PCIE_61 0x080C003D
387 #define GPIO_VER2_H_VGPIO_PCIE_62 0x080C003E
388 #define GPIO_VER2_H_VGPIO_PCIE_63 0x080C003F
389 #define GPIO_VER2_H_VGPIO_PCIE_64 0x080C0040
390 #define GPIO_VER2_H_VGPIO_PCIE_65 0x080C0041
391 #define GPIO_VER2_H_VGPIO_PCIE_66 0x080C0042
392 #define GPIO_VER2_H_VGPIO_PCIE_67 0x080C0043
393 #define GPIO_VER2_H_VGPIO_PCIE_68 0x080C0044
394 #define GPIO_VER2_H_VGPIO_PCIE_69 0x080C0045
395 #define GPIO_VER2_H_VGPIO_PCIE_70 0x080C0046
396 #define GPIO_VER2_H_VGPIO_PCIE_71 0x080C0047
397 #define GPIO_VER2_H_VGPIO_PCIE_72 0x080C0048
398 #define GPIO_VER2_H_VGPIO_PCIE_73 0x080C0049
399 #define GPIO_VER2_H_VGPIO_PCIE_74 0x080C004A
400 #define GPIO_VER2_H_VGPIO_PCIE_75 0x080C004B
401 #define GPIO_VER2_H_VGPIO_PCIE_76 0x080C004C
402 #define GPIO_VER2_H_VGPIO_PCIE_77 0x080C004D
403 #define GPIO_VER2_H_VGPIO_PCIE_78 0x080C004E
404 #define GPIO_VER2_H_VGPIO_PCIE_79 0x080C004F
405 #define GPIO_VER2_H_VGPIO_PCIE_80 0x080C0050
406 #define GPIO_VER2_H_VGPIO_PCIE_81 0x080C0051
407 #define GPIO_VER2_H_VGPIO_PCIE_82 0x080C0052
408 #define GPIO_VER2_H_VGPIO_PCIE_83 0x080C0053
409
410 #define GPIO_VER2_H_GPP_H0 0x080D0000
411 #define GPIO_VER2_H_GPP_H1 0x080D0001
412 #define GPIO_VER2_H_GPP_H2 0x080D0002
413 #define GPIO_VER2_H_GPP_H3 0x080D0003
414 #define GPIO_VER2_H_GPP_H4 0x080D0004
415 #define GPIO_VER2_H_GPP_H5 0x080D0005
416 #define GPIO_VER2_H_GPP_H6 0x080D0006
417 #define GPIO_VER2_H_GPP_H7 0x080D0007
418 #define GPIO_VER2_H_GPP_H8 0x080D0008
419 #define GPIO_VER2_H_GPP_H9 0x080D0009
420 #define GPIO_VER2_H_GPP_H10 0x080D000A
421 #define GPIO_VER2_H_GPP_H11 0x080D000B
422 #define GPIO_VER2_H_GPP_H12 0x080D000C
423 #define GPIO_VER2_H_GPP_H13 0x080D000D
424 #define GPIO_VER2_H_GPP_H14 0x080D000E
425 #define GPIO_VER2_H_GPP_H15 0x080D000F
426 #define GPIO_VER2_H_GPP_H16 0x080D0010
427 #define GPIO_VER2_H_GPP_H17 0x080D0011
428 #define GPIO_VER2_H_GPP_H18 0x080D0012
429 #define GPIO_VER2_H_GPP_H19 0x080D0013
430 #define GPIO_VER2_H_GPP_H20 0x080D0014
431 #define GPIO_VER2_H_GPP_H21 0x080D0015
432 #define GPIO_VER2_H_GPP_H22 0x080D0016
433 #define GPIO_VER2_H_GPP_H23 0x080D0017
434
435 #define GPIO_VER2_H_GPP_J0 0x080E0000
436 #define GPIO_VER2_H_GPP_J1 0x080E0001
437 #define GPIO_VER2_H_GPP_J2 0x080E0002
438 #define GPIO_VER2_H_GPP_J3 0x080E0003
439 #define GPIO_VER2_H_GPP_J4 0x080E0004
440 #define GPIO_VER2_H_GPP_J5 0x080E0005
441 #define GPIO_VER2_H_GPP_J6 0x080E0006
442 #define GPIO_VER2_H_GPP_J7 0x080E0007
443 #define GPIO_VER2_H_GPP_J8 0x080E0008
444 #define GPIO_VER2_H_GPP_J9 0x080E0009
445
446 #define GPIO_VER2_H_GPP_K0 0x080F0000
447 #define GPIO_VER2_H_GPP_K1 0x080F0001
448 #define GPIO_VER2_H_GPP_K2 0x080F0002
449 #define GPIO_VER2_H_GPP_K3 0x080F0003
450 #define GPIO_VER2_H_GPP_K4 0x080F0004
451 #define GPIO_VER2_H_GPP_K5 0x080F0005
452 #define GPIO_VER2_H_GPP_K6 0x080F0006
453 #define GPIO_VER2_H_GPP_K7 0x080F0007
454 #define GPIO_VER2_H_GPP_K8 0x080F0008
455 #define GPIO_VER2_H_GPP_K9 0x080F0009
456 #define GPIO_VER2_H_GPP_K10 0x080F000A
457 #define GPIO_VER2_H_GPP_K11 0x080F000B
458 #define GPIO_VER2_H_SYS_PWROK 0x080F000C
459 #define GPIO_VER2_H_SYS_RESETB 0x080F000D
460 #define GPIO_VER2_H_MLK_RSTB 0x080F000E
461
462 #define GPIO_VER2_H_GPP_I0 0x08100000
463 #define GPIO_VER2_H_GPP_I1 0x08100001
464 #define GPIO_VER2_H_GPP_I2 0x08100002
465 #define GPIO_VER2_H_GPP_I3 0x08100003
466 #define GPIO_VER2_H_GPP_I4 0x08100004
467 #define GPIO_VER2_H_GPP_I5 0x08100005
468 #define GPIO_VER2_H_GPP_I6 0x08100006
469 #define GPIO_VER2_H_GPP_I7 0x08100007
470 #define GPIO_VER2_H_GPP_I8 0x08100008
471 #define GPIO_VER2_H_GPP_I9 0x08100009
472 #define GPIO_VER2_H_GPP_I10 0x0810000A
473 #define GPIO_VER2_H_GPP_I11 0x0810000B
474 #define GPIO_VER2_H_GPP_I12 0x0810000C
475 #define GPIO_VER2_H_GPP_I13 0x0810000D
476 #define GPIO_VER2_H_GPP_I14 0x0810000E
477
478 #define GPIO_VER2_H_JTAG_TDO 0x08110000
479 #define GPIO_VER2_H_JTAGX 0x08110001
480 #define GPIO_VER2_H_PRDYB 0x08110002
481 #define GPIO_VER2_H_PREQB 0x08110003
482 #define GPIO_VER2_H_CPU_TRSTB 0x08110004
483 #define GPIO_VER2_H_JTAG_TDI 0x08110005
484 #define GPIO_VER2_H_JTAG_TMS 0x08110006
485 #define GPIO_VER2_H_JTAG_TCK 0x08110007
486 #define GPIO_VER2_H_DBG_PMODE 0x08110008
487 #define GPIO_VER2_H_MLK 0x08110009
488
489 #define GPIO_VER2_H_HDACPU_SDI 0x08120000
490 #define GPIO_VER2_H_HDACPU_SDO 0x08120001
491 #define GPIO_VER2_H_HDACPU_BCLK 0x08120002
492 #define GPIO_VER2_H_PM_SYNC 0x08120003
493 #define GPIO_VER2_H_PECI 0x08120004
494 #define GPIO_VER2_H_CPUPWRGD 0x08120005
495 #define GPIO_VER2_H_THRMTRIPB 0x08120006
496 #define GPIO_VER2_H_PLTRST_CPUB 0x08120007
497 #define GPIO_VER2_H_PM_DOWN 0x08120008
498 #define GPIO_VER2_H_TRIGGER_IN 0x08120009
499 #define GPIO_VER2_H_TRIGGER_OUT 0x0812000A
500 #define GPIO_VER2_H_CLKOUT_CPURTC 0x0812000B
501 #define GPIO_VER2_H_VCCST_OVERRIDE 0x0812000C
502 #define GPIO_VER2_H_C10_WAKE 0x0812000D
503
504 //
505 // GPIO Pin Muxing
506 // Determines a selection of physical pad for a given signal.
507 // Please refer to GPIO_NATIVE_PAD type.
508 // If certain signal is not listed below it means that it can be enabled
509 // only on a single pad and musing setting is not needed.
510 //
511 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_RXD_GPP_C8 0x18050208
512 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_RXD_GPP_J3 0x280E0203
513 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_TXD_GPP_C9 0x18051209
514 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_TXD_GPP_J4 0x280E1204
515 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_RTS_GPP_C10 0x1805220A
516 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_RTS_GPP_J2 0x280E2202
517 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_CTS_GPP_C11 0x1805320B
518 #define GPIO_VER2_H_MUXING_SERIALIO_UART0_CTS_GPP_J5 0x280E3205
519
520 #endif // _GPIO_PINS_VER2_H_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer2Lp.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
Macros
GpioPinsVer2Lp.h File Reference

GPIO pins for TGL-PCH-LP,. More...

Go to the source code of this file.

Macros

#define | GPIO_VER2_LP_CHIPSET_ID 0x9
This header file should be used together with PCH GPIO lib in C and ASL. More...
#define | GPIO_VER2_LP_GROUP_GPP_B 0x0900
TGL LP GPIO Groups Use below for functions from PCH GPIO Lib which require GpioGroup as argument.
#define | GPIO_VER2_LP_GPP_B0 0x09000000
TGL LP GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument. More...

Detailed Description

GPIO pins for TGL-PCH-LP,.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioPinsVer2Lp.h.

Macro Definition Documentation

◆ GPIO_VER2_LP_CHIPSET_ID

#define GPIO_VER2_LP_CHIPSET_ID 0x9

This header file should be used together with PCH GPIO lib in C and ASL.

All defines used must match both ASL/C syntax Unique ID used in GpioPad defines

Definition at line 46 of file GpioPinsVer2Lp.h.

◆ GPIO_VER2_LP_GPP_B0

#define GPIO_VER2_LP_GPP_B0 0x09000000

TGL LP GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument.

Encoding used here has all information required by library functions

Definition at line 86 of file GpioPinsVer2Lp.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer2Lp.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
GpioPinsVer2Lp.h
Go to the documentation of this file.
1 /** @file
2 GPIO pins for TGL-PCH-LP,
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_PINS_VER2_LP_H_
36 #define _GPIO_PINS_VER2_LP_H_
37 ///
38 /// This header file should be used together with
39 /// PCH GPIO lib in C and ASL. All defines used
40 /// must match both ASL/C syntax
41 ///
42
43 ///
44 /// Unique ID used in GpioPad defines
45 ///
46 #define GPIO_VER2_LP_CHIPSET_ID 0x9
47
48 ///
49 /// TGL LP GPIO Groups
50 /// Use below for functions from PCH GPIO Lib which
51 /// require GpioGroup as argument
52 ///
53 #define GPIO_VER2_LP_GROUP_GPP_B 0x0900
54 #define GPIO_VER2_LP_GROUP_GPP_T 0x0901
55 #define GPIO_VER2_LP_GROUP_GPP_A 0x0902
56 #define GPIO_VER2_LP_GROUP_GPP_R 0x0903
57 #define GPIO_VER2_LP_GROUP_SPI 0x0904
58 #define GPIO_VER2_LP_GROUP_GPD 0x0905
59 #define GPIO_VER2_LP_GROUP_GPP_S 0x0906
60 #define GPIO_VER2_LP_GROUP_GPP_H 0x0907
61 #define GPIO_VER2_LP_GROUP_GPP_D 0x0908
62 #define GPIO_VER2_LP_GROUP_GPP_U 0x0909
63 #define GPIO_VER2_LP_GROUP_VGPIO 0x090A
64 #define GPIO_VER2_LP_GROUP_GPP_C 0x090B
65 #define GPIO_VER2_LP_GROUP_GPP_F 0x090C
66 #define GPIO_VER2_LP_GROUP_HVCMOS 0x090D
67 #define GPIO_VER2_LP_GROUP_GPP_E 0x090E
68 #define GPIO_VER2_LP_GROUP_JTAG 0x090F
69 #define GPIO_VER2_LP_GROUP_CPU 0x0910
70 #define GPIO_VER2_LP_GROUP_VGPIO_3 0x0911
71 /*
72 Following group is used only for PCH_N
73 Other GPIO Group Defines are same keeping
74 Macro in sync with earlier PCH in case there
75 is usage outside IP Block
76 */
77 #define GPIO_VER2_LP_GROUP_GPP_I 0x0909
78
79
80 ///
81 /// TGL LP GPIO pins
82 /// Use below for functions from PCH GPIO Lib which
83 /// require GpioPad as argument. Encoding used here
84 /// has all information required by library functions
85 ///
86 #define GPIO_VER2_LP_GPP_B0 0x09000000
87 #define GPIO_VER2_LP_GPP_B1 0x09000001
88 #define GPIO_VER2_LP_GPP_B2 0x09000002
89 #define GPIO_VER2_LP_GPP_B3 0x09000003
90 #define GPIO_VER2_LP_GPP_B4 0x09000004
91 #define GPIO_VER2_LP_GPP_B5 0x09000005
92 #define GPIO_VER2_LP_GPP_B6 0x09000006
93 #define GPIO_VER2_LP_GPP_B7 0x09000007
94 #define GPIO_VER2_LP_GPP_B8 0x09000008
95 #define GPIO_VER2_LP_GPP_B9 0x09000009
96 #define GPIO_VER2_LP_GPP_B10 0x0900000A
97 #define GPIO_VER2_LP_GPP_B11 0x0900000B
98 #define GPIO_VER2_LP_GPP_B12 0x0900000C
99 #define GPIO_VER2_LP_GPP_B13 0x0900000D
100 #define GPIO_VER2_LP_GPP_B14 0x0900000E
101 #define GPIO_VER2_LP_GPP_B15 0x0900000F
102 #define GPIO_VER2_LP_GPP_B16 0x09000010
103 #define GPIO_VER2_LP_GPP_B17 0x09000011
104 #define GPIO_VER2_LP_GPP_B18 0x09000012
105 #define GPIO_VER2_LP_GPP_B19 0x09000013
106 #define GPIO_VER2_LP_GPP_B20 0x09000014
107 #define GPIO_VER2_LP_GPP_B21 0x09000015
108 #define GPIO_VER2_LP_GPP_B22 0x09000016
109 #define GPIO_VER2_LP_GPP_B23 0x09000017
110 #define GPIO_VER2_LP_GSPI0_CLK_LOOPBK 0x09000018
111 #define GPIO_VER2_LP_GSPI1_CLK_LOOPBK 0x09000019
112
113 #define GPIO_VER2_LP_GPP_T0 0x09010000
114 #define GPIO_VER2_LP_GPP_T1 0x09010001
115 #define GPIO_VER2_LP_GPP_T2 0x09010002
116 #define GPIO_VER2_LP_GPP_T3 0x09010003
117 #define GPIO_VER2_LP_GPP_T4 0x09010004
118 #define GPIO_VER2_LP_GPP_T5 0x09010005
119 #define GPIO_VER2_LP_GPP_T6 0x09010006
120 #define GPIO_VER2_LP_GPP_T7 0x09010007
121 #define GPIO_VER2_LP_GPP_T8 0x09010008
122 #define GPIO_VER2_LP_GPP_T9 0x09010009
123 #define GPIO_VER2_LP_GPP_T10 0x0901000A
124 #define GPIO_VER2_LP_GPP_T11 0x0901000B
125 #define GPIO_VER2_LP_GPP_T12 0x0901000C
126 #define GPIO_VER2_LP_GPP_T13 0x0901000D
127 #define GPIO_VER2_LP_GPP_T14 0x0901000E
128 #define GPIO_VER2_LP_GPP_T15 0x0901000F
129
130 #define GPIO_VER2_LP_GPP_A0 0x09020000
131 #define GPIO_VER2_LP_GPP_A1 0x09020001
132 #define GPIO_VER2_LP_GPP_A2 0x09020002
133 #define GPIO_VER2_LP_GPP_A3 0x09020003
134 #define GPIO_VER2_LP_GPP_A4 0x09020004
135 #define GPIO_VER2_LP_GPP_A5 0x09020005
136 #define GPIO_VER2_LP_GPP_A6 0x09020006
137 #define GPIO_VER2_LP_GPP_A7 0x09020007
138 #define GPIO_VER2_LP_GPP_A8 0x09020008
139 #define GPIO_VER2_LP_GPP_A9 0x09020009
140 #define GPIO_VER2_LP_GPP_A10 0x0902000A
141 #define GPIO_VER2_LP_GPP_A11 0x0902000B
142 #define GPIO_VER2_LP_GPP_A12 0x0902000C
143 #define GPIO_VER2_LP_GPP_A13 0x0902000D
144 #define GPIO_VER2_LP_GPP_A14 0x0902000E
145 #define GPIO_VER2_LP_GPP_A15 0x0902000F
146 #define GPIO_VER2_LP_GPP_A16 0x09020010
147 #define GPIO_VER2_LP_GPP_A17 0x09020011
148 #define GPIO_VER2_LP_GPP_A18 0x09020012
149 #define GPIO_VER2_LP_GPP_A19 0x09020013
150 #define GPIO_VER2_LP_GPP_A20 0x09020014
151 #define GPIO_VER2_LP_GPP_A21 0x09020015
152 #define GPIO_VER2_LP_GPP_A22 0x09020016
153 #define GPIO_VER2_LP_GPP_A23 0x09020017
154 #define GPIO_VER2_LP_ESPI_CLK_LOOPBK 0x09020018
155
156 #define GPIO_VER2_LP_GPP_R0 0x09030000
157 #define GPIO_VER2_LP_GPP_R1 0x09030001
158 #define GPIO_VER2_LP_GPP_R2 0x09030002
159 #define GPIO_VER2_LP_GPP_R3 0x09030003
160 #define GPIO_VER2_LP_GPP_R4 0x09030004
161 #define GPIO_VER2_LP_GPP_R5 0x09030005
162 #define GPIO_VER2_LP_GPP_R6 0x09030006
163 #define GPIO_VER2_LP_GPP_R7 0x09030007
164
165 #define GPIO_VER2_LP_SPI0_IO_2 0x09040000
166 #define GPIO_VER2_LP_SPI0_IO_3 0x09040001
167 #define GPIO_VER2_LP_SPI0_MOSI_IO_0 0x09040002
168 #define GPIO_VER2_LP_SPI0_MISO_IO_1 0x09040003
169 #define GPIO_VER2_LP_SPI0_TPM_CSB 0x09040004
170 #define GPIO_VER2_LP_SPI0_FLASH_0_CSB 0x09040005
171 #define GPIO_VER2_LP_SPI0_FLASH_1_CSB 0x09040006
172 #define GPIO_VER2_LP_SPI0_CLK 0x09040007
173 #define GPIO_VER2_LP_SPI0_CLK_LOOPBK 0x09040008
174
175 #define GPIO_VER2_LP_GPD0 0x09050000
176 #define GPIO_VER2_LP_GPD1 0x09050001
177 #define GPIO_VER2_LP_GPD2 0x09050002
178 #define GPIO_VER2_LP_GPD3 0x09050003
179 #define GPIO_VER2_LP_GPD4 0x09050004
180 #define GPIO_VER2_LP_GPD5 0x09050005
181 #define GPIO_VER2_LP_GPD6 0x09050006
182 #define GPIO_VER2_LP_GPD7 0x09050007
183 #define GPIO_VER2_LP_GPD8 0x09050008
184 #define GPIO_VER2_LP_GPD9 0x09050009
185 #define GPIO_VER2_LP_GPD10 0x0905000A
186 #define GPIO_VER2_LP_GPD11 0x0905000B
187 #define GPIO_VER2_LP_INPUT3VSEL 0x0905000C
188 #define GPIO_VER2_LP_SLP_LANB 0x0905000D
189 #define GPIO_VER2_LP_SLP_SUSB 0x0905000E
190 #define GPIO_VER2_LP_WAKEB 0x0905000F
191 #define GPIO_VER2_LP_DRAM_RESETB 0x09050010
192
193 #define GPIO_VER2_LP_GPP_S0 0x09060000
194 #define GPIO_VER2_LP_GPP_S1 0x09060001
195 #define GPIO_VER2_LP_GPP_S2 0x09060002
196 #define GPIO_VER2_LP_GPP_S3 0x09060003
197 #define GPIO_VER2_LP_GPP_S4 0x09060004
198 #define GPIO_VER2_LP_GPP_S5 0x09060005
199 #define GPIO_VER2_LP_GPP_S6 0x09060006
200 #define GPIO_VER2_LP_GPP_S7 0x09060007
201
202 #define GPIO_VER2_LP_GPP_H0 0x09070000
203 #define GPIO_VER2_LP_GPP_H1 0x09070001
204 #define GPIO_VER2_LP_GPP_H2 0x09070002
205 #define GPIO_VER2_LP_GPP_H3 0x09070003
206 #define GPIO_VER2_LP_GPP_H4 0x09070004
207 #define GPIO_VER2_LP_GPP_H5 0x09070005
208 #define GPIO_VER2_LP_GPP_H6 0x09070006
209 #define GPIO_VER2_LP_GPP_H7 0x09070007
210 #define GPIO_VER2_LP_GPP_H8 0x09070008
211 #define GPIO_VER2_LP_GPP_H9 0x09070009
212 #define GPIO_VER2_LP_GPP_H10 0x0907000A
213 #define GPIO_VER2_LP_GPP_H11 0x0907000B
214 #define GPIO_VER2_LP_GPP_H12 0x0907000C
215 #define GPIO_VER2_LP_GPP_H13 0x0907000D
216 #define GPIO_VER2_LP_GPP_H14 0x0907000E
217 #define GPIO_VER2_LP_GPP_H15 0x0907000F
218 #define GPIO_VER2_LP_GPP_H16 0x09070010
219 #define GPIO_VER2_LP_GPP_H17 0x09070011
220 #define GPIO_VER2_LP_GPP_H18 0x09070012
221 #define GPIO_VER2_LP_GPP_H19 0x09070013
222 #define GPIO_VER2_LP_GPP_H20 0x09070014
223 #define GPIO_VER2_LP_GPP_H21 0x09070015
224 #define GPIO_VER2_LP_GPP_H22 0x09070016
225 #define GPIO_VER2_LP_GPP_H23 0x09070017
226
227 #define GPIO_VER2_LP_GPP_D0 0x09080000
228 #define GPIO_VER2_LP_GPP_D1 0x09080001
229 #define GPIO_VER2_LP_GPP_D2 0x09080002
230 #define GPIO_VER2_LP_GPP_D3 0x09080003
231 #define GPIO_VER2_LP_GPP_D4 0x09080004
232 #define GPIO_VER2_LP_GPP_D5 0x09080005
233 #define GPIO_VER2_LP_GPP_D6 0x09080006
234 #define GPIO_VER2_LP_GPP_D7 0x09080007
235 #define GPIO_VER2_LP_GPP_D8 0x09080008
236 #define GPIO_VER2_LP_GPP_D9 0x09080009
237 #define GPIO_VER2_LP_GPP_D10 0x0908000A
238 #define GPIO_VER2_LP_GPP_D11 0x0908000B
239 #define GPIO_VER2_LP_GPP_D12 0x0908000C
240 #define GPIO_VER2_LP_GPP_D13 0x0908000D
241 #define GPIO_VER2_LP_GPP_D14 0x0908000E
242 #define GPIO_VER2_LP_GPP_D15 0x0908000F
243 #define GPIO_VER2_LP_GPP_D16 0x09080010
244 #define GPIO_VER2_LP_GPP_D17 0x09080011
245 #define GPIO_VER2_LP_GPP_D18 0x09080012
246 #define GPIO_VER2_LP_GPP_D19 0x09080013
247 #define GPIO_VER2_LP_GSPI2_CLK_LOOPBK 0x09080014
248
249 #define GPIO_VER2_LP_GPP_U0 0x09090000
250 #define GPIO_VER2_LP_GPP_U1 0x09090001
251 #define GPIO_VER2_LP_GPP_U2 0x09090002
252 #define GPIO_VER2_LP_GPP_U3 0x09090003
253 #define GPIO_VER2_LP_GPP_U4 0x09090004
254 #define GPIO_VER2_LP_GPP_U5 0x09090005
255 #define GPIO_VER2_LP_GPP_U6 0x09090006
256 #define GPIO_VER2_LP_GPP_U7 0x09090007
257 #define GPIO_VER2_LP_GPP_U8 0x09090008
258 #define GPIO_VER2_LP_GPP_U9 0x09090009
259 #define GPIO_VER2_LP_GPP_U10 0x0909000A
260 #define GPIO_VER2_LP_GPP_U11 0x0909000B
261 #define GPIO_VER2_LP_GPP_U12 0x0909000C
262 #define GPIO_VER2_LP_GPP_U13 0x0909000D
263 #define GPIO_VER2_LP_GPP_U14 0x0909000E
264 #define GPIO_VER2_LP_GPP_U15 0x0909000F
265 #define GPIO_VER2_LP_GPP_U16 0x09090010
266 #define GPIO_VER2_LP_GPP_U17 0x09090011
267 #define GPIO_VER2_LP_GPP_U18 0x09090012
268 #define GPIO_VER2_LP_GPP_U19 0x09090013
269 #define GPIO_VER2_LP_GSPI3_CLK_LOOPBK 0x09090014
270 #define GPIO_VER2_LP_GSPI4_CLK_LOOPBK 0x09090015
271 #define GPIO_VER2_LP_GSPI5_CLK_LOOPBK 0x09090016
272 #define GPIO_VER2_LP_GSPI6_CLK_LOOPBK 0x09090017
273
274 #define GPIO_VER2_LP_VGPIO0 0x090A0000
275 #define GPIO_VER2_LP_VGPIO4 0x090A0001
276 #define GPIO_VER2_LP_VGPIO5 0x090A0002
277 #define GPIO_VER2_LP_VGPIO6 0x090A0003
278 #define GPIO_VER2_LP_VGPIO7 0x090A0004
279 #define GPIO_VER2_LP_VGPIO8 0x090A0005
280 #define GPIO_VER2_LP_VGPIO9 0x090A0006
281 #define GPIO_VER2_LP_VGPIO10 0x090A0007
282 #define GPIO_VER2_LP_VGPIO11 0x090A0008
283 #define GPIO_VER2_LP_VGPIO12 0x090A0009
284 #define GPIO_VER2_LP_VGPIO13 0x090A000A
285 #define GPIO_VER2_LP_VGPIO18 0x090A000B
286 #define GPIO_VER2_LP_VGPIO19 0x090A000C
287 #define GPIO_VER2_LP_VGPIO20 0x090A000D
288 #define GPIO_VER2_LP_VGPIO21 0x090A000E
289 #define GPIO_VER2_LP_VGPIO22 0x090A000F
290 #define GPIO_VER2_LP_VGPIO23 0x090A0010
291 #define GPIO_VER2_LP_VGPIO24 0x090A0011
292 #define GPIO_VER2_LP_VGPIO25 0x090A0012
293 #define GPIO_VER2_LP_VGPIO30 0x090A0013
294 #define GPIO_VER2_LP_VGPIO31 0x090A0014
295 #define GPIO_VER2_LP_VGPIO32 0x090A0015
296 #define GPIO_VER2_LP_VGPIO33 0x090A0016
297 #define GPIO_VER2_LP_VGPIO34 0x090A0017
298 #define GPIO_VER2_LP_VGPIO35 0x090A0018
299 #define GPIO_VER2_LP_VGPIO36 0x090A0019
300 #define GPIO_VER2_LP_VGPIO37 0x090A001A
301 #define GPIO_VER2_LP_VGPIO_THC0 0x090A001B
302 #define GPIO_VER2_LP_VGPIO_THC1 0x090A001C
303
304 #define GPIO_VER2_LP_GPP_C0 0x090B0000
305 #define GPIO_VER2_LP_GPP_C1 0x090B0001
306 #define GPIO_VER2_LP_GPP_C2 0x090B0002
307 #define GPIO_VER2_LP_GPP_C3 0x090B0003
308 #define GPIO_VER2_LP_GPP_C4 0x090B0004
309 #define GPIO_VER2_LP_GPP_C5 0x090B0005
310 #define GPIO_VER2_LP_GPP_C6 0x090B0006
311 #define GPIO_VER2_LP_GPP_C7 0x090B0007
312 #define GPIO_VER2_LP_GPP_C8 0x090B0008
313 #define GPIO_VER2_LP_GPP_C9 0x090B0009
314 #define GPIO_VER2_LP_GPP_C10 0x090B000A
315 #define GPIO_VER2_LP_GPP_C11 0x090B000B
316 #define GPIO_VER2_LP_GPP_C12 0x090B000C
317 #define GPIO_VER2_LP_GPP_C13 0x090B000D
318 #define GPIO_VER2_LP_GPP_C14 0x090B000E
319 #define GPIO_VER2_LP_GPP_C15 0x090B000F
320 #define GPIO_VER2_LP_GPP_C16 0x090B0010
321 #define GPIO_VER2_LP_GPP_C17 0x090B0011
322 #define GPIO_VER2_LP_GPP_C18 0x090B0012
323 #define GPIO_VER2_LP_GPP_C19 0x090B0013
324 #define GPIO_VER2_LP_GPP_C20 0x090B0014
325 #define GPIO_VER2_LP_GPP_C21 0x090B0015
326 #define GPIO_VER2_LP_GPP_C22 0x090B0016
327 #define GPIO_VER2_LP_GPP_C23 0x090B0017
328
329
330 #define GPIO_VER2_LP_GPP_F0 0x090C0000
331 #define GPIO_VER2_LP_GPP_F1 0x090C0001
332 #define GPIO_VER2_LP_GPP_F2 0x090C0002
333 #define GPIO_VER2_LP_GPP_F3 0x090C0003
334 #define GPIO_VER2_LP_GPP_F4 0x090C0004
335 #define GPIO_VER2_LP_GPP_F5 0x090C0005
336 #define GPIO_VER2_LP_GPP_F6 0x090C0006
337 #define GPIO_VER2_LP_GPP_F7 0x090C0007
338 #define GPIO_VER2_LP_GPP_F8 0x090C0008
339 #define GPIO_VER2_LP_GPP_F9 0x090C0009
340 #define GPIO_VER2_LP_GPP_F10 0x090C000A
341 #define GPIO_VER2_LP_GPP_F11 0x090C000B
342 #define GPIO_VER2_LP_GPP_F12 0x090C000C
343 #define GPIO_VER2_LP_GPP_F13 0x090C000D
344 #define GPIO_VER2_LP_GPP_F14 0x090C000E
345 #define GPIO_VER2_LP_GPP_F15 0x090C000F
346 #define GPIO_VER2_LP_GPP_F16 0x090C0010
347 #define GPIO_VER2_LP_GPP_F17 0x090C0011
348 #define GPIO_VER2_LP_GPP_F18 0x090C0012
349 #define GPIO_VER2_LP_GPP_F19 0x090C0013
350 #define GPIO_VER2_LP_GPP_F20 0x090C0014
351 #define GPIO_VER2_LP_GPP_F21 0x090C0015
352 #define GPIO_VER2_LP_GPP_F22 0x090C0016
353 #define GPIO_VER2_LP_GPP_F23 0x090C0017
354 #define GPIO_VER2_LP_GPPF_CLK_LOOPBK 0x090C0018
355
356 #define GPIO_VER2_LP_L_BKLTEN 0x090D0000
357 #define GPIO_VER2_LP_L_BKLTCTL 0x090D0001
358 #define GPIO_VER2_LP_L_VDDEN 0x090D0002
359 #define GPIO_VER2_LP_SYS_PWROK 0x090D0003
360 #define GPIO_VER2_LP_SYS_RESETB 0x090D0004
361 #define GPIO_VER2_LP_MLK_RSTB 0x090D0005
362
363 #define GPIO_VER2_LP_GPP_E0 0x090E0000
364 #define GPIO_VER2_LP_GPP_E1 0x090E0001
365 #define GPIO_VER2_LP_GPP_E2 0x090E0002
366 #define GPIO_VER2_LP_GPP_E3 0x090E0003
367 #define GPIO_VER2_LP_GPP_E4 0x090E0004
368 #define GPIO_VER2_LP_GPP_E5 0x090E0005
369 #define GPIO_VER2_LP_GPP_E6 0x090E0006
370 #define GPIO_VER2_LP_GPP_E7 0x090E0007
371 #define GPIO_VER2_LP_GPP_E8 0x090E0008
372 #define GPIO_VER2_LP_GPP_E9 0x090E0009
373 #define GPIO_VER2_LP_GPP_E10 0x090E000A
374 #define GPIO_VER2_LP_GPP_E11 0x090E000B
375 #define GPIO_VER2_LP_GPP_E12 0x090E000C
376 #define GPIO_VER2_LP_GPP_E13 0x090E000D
377 #define GPIO_VER2_LP_GPP_E14 0x090E000E
378 #define GPIO_VER2_LP_GPP_E15 0x090E000F
379 #define GPIO_VER2_LP_GPP_E16 0x090E0010
380 #define GPIO_VER2_LP_GPP_E17 0x090E0011
381 #define GPIO_VER2_LP_GPP_E18 0x090E0012
382 #define GPIO_VER2_LP_GPP_E19 0x090E0013
383 #define GPIO_VER2_LP_GPP_E20 0x090E0014
384 #define GPIO_VER2_LP_GPP_E21 0x090E0015
385 #define GPIO_VER2_LP_GPP_E22 0x090E0016
386 #define GPIO_VER2_LP_GPP_E23 0x090E0017
387 #define GPIO_VER2_LP_GPPE_CLK_LOOPBK 0x090E0018
388
389 #define GPIO_VER2_LP_JTAG_TDO 0x090F0000
390 #define GPIO_VER2_LP_JTAGX 0x090F0001
391 #define GPIO_VER2_LP_PRDYB 0x090F0002
392 #define GPIO_VER2_LP_PREQB 0x090F0003
393 #define GPIO_VER2_LP_CPU_TRSTB 0x090F0004
394 #define GPIO_VER2_LP_JTAG_TDI 0x090F0005
395 #define GPIO_VER2_LP_JTAG_TMS 0x090F0006
396 #define GPIO_VER2_LP_JTAG_TCK 0x090F0007
397 #define GPIO_VER2_LP_DBG_PMODE 0x090F0008
398 #define GPIO_VER2_LP_MLK 0x090F0009
399
400 #define GPIO_VER2_LP_HDACPU_SDI 0x09100000
401 #define GPIO_VER2_LP_HDACPU_SDO 0x09100001
402 #define GPIO_VER2_LP_HDACPU_SCLK 0x09100002
403 #define GPIO_VER2_LP_PM_SYNC 0x09100003
404 #define GPIO_VER2_LP_PECI 0x09100004
405 #define GPIO_VER2_LP_CPUPWRGD 0x09100005
406 #define GPIO_VER2_LP_THRMTRIPB 0x09100006
407 #define GPIO_VER2_LP_PLTRST_CPUB 0x09100007
408 #define GPIO_VER2_LP_PM_DOWN 0x09100008
409 #define GPIO_VER2_LP_TRIGGER_IN 0x09100009
410 #define GPIO_VER2_LP_TRIGGER_OUT 0x0910000A
411 #define GPIO_VER2_LP_UFS_RESETB 0x0910000B
412 #define GPIO_VER2_LP_CLKOUT_CPURTC 0x0910000C
413 #define GPIO_VER2_LP_VCCST_OVERRIDE 0x0910000D
414 #define GPIO_VER2_LP_C10_WAKE 0x0910000E
415
416 #define GPIO_VER2_LP_VGPIO_PCIE_0 0x09110000
417 #define GPIO_VER2_LP_VGPIO_PCIE_1 0x09110001
418 #define GPIO_VER2_LP_VGPIO_PCIE_2 0x09110002
419 #define GPIO_VER2_LP_VGPIO_PCIE_3 0x09110003
420 #define GPIO_VER2_LP_VGPIO_PCIE_4 0x09110004
421 #define GPIO_VER2_LP_VGPIO_PCIE_5 0x09110005
422 #define GPIO_VER2_LP_VGPIO_PCIE_6 0x09110006
423 #define GPIO_VER2_LP_VGPIO_PCIE_7 0x09110007
424 #define GPIO_VER2_LP_VGPIO_PCIE_8 0x09110008
425 #define GPIO_VER2_LP_VGPIO_PCIE_9 0x09110009
426 #define GPIO_VER2_LP_VGPIO_PCIE_10 0x0911000A
427 #define GPIO_VER2_LP_VGPIO_PCIE_11 0x0911000B
428 #define GPIO_VER2_LP_VGPIO_PCIE_12 0x0911000C
429 #define GPIO_VER2_LP_VGPIO_PCIE_13 0x0911000D
430 #define GPIO_VER2_LP_VGPIO_PCIE_14 0x0911000E
431 #define GPIO_VER2_LP_VGPIO_PCIE_15 0x0911000F
432 #define GPIO_VER2_LP_VGPIO_PCIE_16 0x09110010
433 #define GPIO_VER2_LP_VGPIO_PCIE_17 0x09110011
434 #define GPIO_VER2_LP_VGPIO_PCIE_18 0x09110012
435 #define GPIO_VER2_LP_VGPIO_PCIE_19 0x09110013
436 #define GPIO_VER2_LP_VGPIO_PCIE_20 0x09110014
437 #define GPIO_VER2_LP_VGPIO_PCIE_21 0x09110015
438 #define GPIO_VER2_LP_VGPIO_PCIE_22 0x09110016
439 #define GPIO_VER2_LP_VGPIO_PCIE_23 0x09110017
440 #define GPIO_VER2_LP_VGPIO_PCIE_24 0x09110018
441 #define GPIO_VER2_LP_VGPIO_PCIE_25 0x09110019
442 #define GPIO_VER2_LP_VGPIO_PCIE_26 0x0911001A
443 #define GPIO_VER2_LP_VGPIO_PCIE_27 0x0911001B
444 #define GPIO_VER2_LP_VGPIO_PCIE_28 0x0911001C
445 #define GPIO_VER2_LP_VGPIO_PCIE_29 0x0911001D
446 #define GPIO_VER2_LP_VGPIO_PCIE_30 0x0911001E
447 #define GPIO_VER2_LP_VGPIO_PCIE_31 0x0911001F
448 #define GPIO_VER2_LP_VGPIO_PCIE_32 0x09110020
449 #define GPIO_VER2_LP_VGPIO_PCIE_33 0x09110021
450 #define GPIO_VER2_LP_VGPIO_PCIE_34 0x09110022
451 #define GPIO_VER2_LP_VGPIO_PCIE_35 0x09110023
452 #define GPIO_VER2_LP_VGPIO_PCIE_36 0x09110024
453 #define GPIO_VER2_LP_VGPIO_PCIE_37 0x09110025
454 #define GPIO_VER2_LP_VGPIO_PCIE_38 0x09110026
455 #define GPIO_VER2_LP_VGPIO_PCIE_39 0x09110027
456 #define GPIO_VER2_LP_VGPIO_PCIE_40 0x09110028
457 #define GPIO_VER2_LP_VGPIO_PCIE_41 0x09110029
458 #define GPIO_VER2_LP_VGPIO_PCIE_42 0x0911002A
459 #define GPIO_VER2_LP_VGPIO_PCIE_43 0x0911002B
460 #define GPIO_VER2_LP_VGPIO_PCIE_44 0x0911002C
461 #define GPIO_VER2_LP_VGPIO_PCIE_45 0x0911002D
462 #define GPIO_VER2_LP_VGPIO_PCIE_46 0x0911002E
463 #define GPIO_VER2_LP_VGPIO_PCIE_47 0x0911002F
464 #define GPIO_VER2_LP_VGPIO_PCIE_48 0x09110030
465 #define GPIO_VER2_LP_VGPIO_PCIE_49 0x09110031
466 #define GPIO_VER2_LP_VGPIO_PCIE_50 0x09110032
467 #define GPIO_VER2_LP_VGPIO_PCIE_51 0x09110033
468 #define GPIO_VER2_LP_VGPIO_PCIE_52 0x09110034
469 #define GPIO_VER2_LP_VGPIO_PCIE_53 0x09110035
470 #define GPIO_VER2_LP_VGPIO_PCIE_54 0x09110036
471 #define GPIO_VER2_LP_VGPIO_PCIE_55 0x09110037
472 #define GPIO_VER2_LP_VGPIO_PCIE_56 0x09110038
473 #define GPIO_VER2_LP_VGPIO_PCIE_57 0x09110039
474 #define GPIO_VER2_LP_VGPIO_PCIE_58 0x0911003A
475 #define GPIO_VER2_LP_VGPIO_PCIE_59 0x0911003B
476 #define GPIO_VER2_LP_VGPIO_PCIE_60 0x0911003C
477 #define GPIO_VER2_LP_VGPIO_PCIE_61 0x0911003D
478 #define GPIO_VER2_LP_VGPIO_PCIE_62 0x0911003E
479 #define GPIO_VER2_LP_VGPIO_PCIE_63 0x0911003F
480 #define GPIO_VER2_LP_VGPIO_PCIE_64 0x09110040
481 #define GPIO_VER2_LP_VGPIO_PCIE_65 0x09110041
482 #define GPIO_VER2_LP_VGPIO_PCIE_66 0x09110042
483 #define GPIO_VER2_LP_VGPIO_PCIE_67 0x09110043
484 #define GPIO_VER2_LP_VGPIO_PCIE_68 0x09110044
485 #define GPIO_VER2_LP_VGPIO_PCIE_69 0x09110045
486 #define GPIO_VER2_LP_VGPIO_PCIE_70 0x09110046
487 #define GPIO_VER2_LP_VGPIO_PCIE_71 0x09110047
488 #define GPIO_VER2_LP_VGPIO_PCIE_72 0x09110048
489 #define GPIO_VER2_LP_VGPIO_PCIE_73 0x09110049
490 #define GPIO_VER2_LP_VGPIO_PCIE_74 0x0911004A
491 #define GPIO_VER2_LP_VGPIO_PCIE_75 0x0911004B
492 #define GPIO_VER2_LP_VGPIO_PCIE_76 0x0911004C
493 #define GPIO_VER2_LP_VGPIO_PCIE_77 0x0911004D
494 #define GPIO_VER2_LP_VGPIO_PCIE_78 0x0911004E
495 #define GPIO_VER2_LP_VGPIO_PCIE_79 0x0911004F
496 #define GPIO_VER2_LP_VGPIO_USB_0 0x09110050
497 #define GPIO_VER2_LP_VGPIO_USB_1 0x09110051
498 #define GPIO_VER2_LP_VGPIO_USB_2 0x09110052
499 #define GPIO_VER2_LP_VGPIO_USB_3 0x09110053
500 #define GPIO_VER2_LP_VGPIO_USB_4 0x09110054
501 #define GPIO_VER2_LP_VGPIO_USB_5 0x09110055
502 #define GPIO_VER2_LP_VGPIO_USB_6 0x09110056
503 #define GPIO_VER2_LP_VGPIO_USB_7 0x09110057
504 #define GPIO_VER2_LP_VGPIO_PCIE_80 0x09110058
505 #define GPIO_VER2_LP_VGPIO_PCIE_81 0x09110059
506 #define GPIO_VER2_LP_VGPIO_PCIE_82 0x0911005A
507 #define GPIO_VER2_LP_VGPIO_PCIE_83 0x0911005B
508
509 /*
510 Following group is used only for PCH_N
511 Other GPIO Group Defines are same keeping
512 Macro in sync with earlier PCH in case there
513 is usage outside IP Block
514 */
515 #define GPIO_VER2_LP_GPP_I0 0x09090000
516 #define GPIO_VER2_LP_GPP_I1 0x09090001
517 #define GPIO_VER2_LP_GPP_I2 0x09090002
518 #define GPIO_VER2_LP_GPP_I3 0x09090003
519 #define GPIO_VER2_LP_GPP_I4 0x09090004
520 #define GPIO_VER2_LP_GPP_I5 0x09090005
521 #define GPIO_VER2_LP_GPP_I6 0x09090006
522 #define GPIO_VER2_LP_GPP_I7 0x09090007
523 #define GPIO_VER2_LP_GPP_I8 0x09090008
524 #define GPIO_VER2_LP_GPP_I9 0x09090009
525 #define GPIO_VER2_LP_GPP_I10 0x0909000A
526 #define GPIO_VER2_LP_GPP_I11 0x0909000B
527 #define GPIO_VER2_LP_GPP_I12 0x0909000C
528 #define GPIO_VER2_LP_GPP_I13 0x0909000D
529 #define GPIO_VER2_LP_GPP_I14 0x0909000E
530 #define GPIO_VER2_LP_GPP_I15 0x0909000F
531 #define GPIO_VER2_LP_GPP_I16 0x09090010
532 #define GPIO_VER2_LP_GPP_I17 0x09090011
533 #define GPIO_VER2_LP_GPP_I18 0x09090012
534 #define GPIO_VER2_LP_GPP_I19 0x09090013
535
536 //
537 // GPIO Pin Muxing
538 // Determines a selection of physical pad for a given signal.
539 // Please refer to GPIO_NATIVE_PAD type.
540 // If certain signal is not listed below it means that it can be enabled
541 // only on a single pad and muxing setting is not needed.
542 //
543 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_C8 0x190B0208
544 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_F1 0x290C0201
545 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_C9 0x190B1209
546 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_F2 0x290C1202
547 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_C10 0x190B220A
548 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_F0 0x290C2200
549 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_C11 0x190B320B
550 #define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_F3 0x290C3203
551
552 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_RXD_GPP_H10 0x2907020B
553 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_RXD_GPP_F0 0x390C0200
554 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_TXD_GPP_H11 0x2907120C
555 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_TXD_GPP_F1 0x390C1201
556 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_RTS_GPP_H12 0x2907220D
557 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_RTS_GPP_F2 0x390C2202
558 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_CTS_GPP_H13 0x2907320E
559 #define GPIO_VER2_P_MUXING_SERIALIO_UART0_CTS_GPP_F3 0x390C3203
560
561 #define GPIO_VER2_P_MUXING_ISH_UART1_RXD_GPP_C12 0x292b220c
562 #define GPIO_VER2_P_MUXING_ISH_UART1_RXD_GPP_D17 0x29282211
563 #define GPIO_VER2_P_MUXING_ISH_UART1_TXD_GPP_C13 0x292b320d
564 #define GPIO_VER2_P_MUXING_ISH_UART1_TXD_GPP_D18 0x29283212
565
566 #define GPIO_VER2_P_MUXING_SERIALIO_I2C0_SDA_GPP_H4 0x1947c404
567 #define GPIO_VER2_P_MUXING_SERIALIO_I2C0_SDA_GPP_E12 0x594ec40c
568 #define GPIO_VER2_P_MUXING_SERIALIO_I2C1_SDA_GPP_H6 0x1947c606
569 #define GPIO_VER2_P_MUXING_SERIALIO_I2C1_SDA_GPP_F13 0x594cc60d
570 #define GPIO_VER2_P_MUXING_SERIALIO_I2C7_SDA_GPP_H12 0x1947d20c
571 #define GPIO_VER2_P_MUXING_SERIALIO_I2C7_SDA_GPP_D15 0x4948d20f
572
573 #define GPIO_VER2_P_MUXING_SERIALIO_I2C0_SCL_GPP_H5 0x1947a405
574 #define GPIO_VER2_P_MUXING_SERIALIO_I2C0_SCL_GPP_E13 0x594ea40d
575 #define GPIO_VER2_P_MUXING_SERIALIO_I2C1_SCL_GPP_H7 0x1947a607
576 #define GPIO_VER2_P_MUXING_SERIALIO_I2C1_SCL_GPP_F12 0x594ca60c
577 #define GPIO_VER2_P_MUXING_SERIALIO_I2C7_SCL_GPP_H13 0x1947b20d
578 #define GPIO_VER2_P_MUXING_SERIALIO_I2C7_SCL_GPP_D16 0x4948b210
579
580 #define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6 0x29460C06
581 #define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_A7 0x59420C07
582 #define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2 0x29461402
583 #define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_A13 0x5942140D
584 #define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7 0x29460407
585 #define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_A8 0x59420408
586 #define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4 0x29460E04
587 #define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_A9 0x59420E09
588 #define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3 0x29461603
589 #define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_A14 0x5942160E
590 #define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5 0x29460605
591 #define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_A10 0x5942060A
592 #define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S2 0x29460c02
593 #define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S6 0x29460e06
594 #define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S4 0x29461404
595 #define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S5 0x29461605
596 #define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S3 0x29460403
597 #define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S7 0x29460607
598 #define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_R4 0x39460c04
599 #define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_R6 0x39460e06
600 #define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_R0 0x39461400
601 #define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_R1 0x39461601
602 #define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_R5 0x39460405
603 #define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_R7 0x39460607
604
605 #define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_A8 0x2942E408
606 #define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_F4 0x194CE404
607
608 #define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_A9 0x2942E609
609 #define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_A9 0x3942E609
610 #define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_F5 0x294CE605
611 #define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_F5 0x394CE605
612
613 #define GPIO_VER2_P_MUXING_ISH_GP4_GPP_E9 0x490ea809
614 #define GPIO_VER2_P_MUXING_ISH_GP4_GPP_B3 0x4900a803
615 #define GPIO_VER2_P_MUXING_ISH_GP5_GPP_A16 0x4902aa10
616 #define GPIO_VER2_P_MUXING_ISH_GP5_GPP_B4 0x4900aa04
617 #define GPIO_VER2_P_MUXING_ISH_GP6_GPP_B14 0x4900ac0e
618 #define GPIO_VER2_P_MUXING_ISH_GP6_GPP_H12 0x4907ac0c
619 #define GPIO_VER2_P_MUXING_ISH_GP7_GPP_B15 0x4900ae0f
620 #define GPIO_VER2_P_MUXING_ISH_GP7_GPP_H13 0x4907ae0d
621
622 #define GPIO_VER2_P_MUXING_SATA_DEVSLP0_GPP_E4 0x196e3e04
623 #define GPIO_VER2_P_MUXING_SATA_DEVSLP1_GPP_E5 0x196e4005
624 #define GPIO_VER2_P_MUXING_SATA_DEVSLP0_GPP_H12 0x59673e0c
625 #define GPIO_VER2_P_MUXING_SATA_DEVSLP1_GPP_H13 0x5967400d
626
627 #define GPIO_VER2_P_MUXING_PCIE_CLKREQ_9_E0 0x796e9000
628 #define GPIO_VER2_P_MUXING_PCIE_CLKREQ_9_A12 0x4962900c
629
630 #define GPIO_VER2_P_MUXING_ISH_GP_4_E9 0x290ea809
631 #define GPIO_VER2_P_MUXING_ISH_GP_4_B3 0x4900a803
632 #define GPIO_VER2_P_MUXING_ISH_GP_5_A16 0x4902aa10
633 #define GPIO_VER2_P_MUXING_ISH_GP_5_B4 0x4900aa04
634 #define GPIO_VER2_P_MUXING_ISH_GP_6_B14 0x5900ac0e
635 #define GPIO_VER2_P_MUXING_ISH_GP_6_H12 0x4907ac0c
636 #define GPIO_VER2_P_MUXING_ISH_GP_7_B15 0x5900ae0f
637 #define GPIO_VER2_P_MUXING_ISH_GP_7_H13 0x4907ae0d
638
639 #endif // _GPIO_PINS_VER2_LP_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer4S.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
Macros
GpioPinsVer4S.h File Reference

GPIO pins for ADL-PCH-S,. More...

Go to the source code of this file.

Macros

#define | GPIO_VER4_S_CHIPSET_ID 0x8
This header file should be used together with PCH GPIO lib in C and ASL. More...
#define | GPIO_VER4_S_GROUP_GPP_I 0x0800
ADL S GPIO Groups Use below for functions from PCH GPIO Lib which require GpioGroup as argument.
#define | GPIO_VER4_S_GPP_I0 0x08000000
ADL S GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument. More...

Detailed Description

GPIO pins for ADL-PCH-S,.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioPinsVer4S.h.

Macro Definition Documentation

◆ GPIO_VER4_S_CHIPSET_ID

#define GPIO_VER4_S_CHIPSET_ID 0x8

This header file should be used together with PCH GPIO lib in C and ASL.

All defines used must match both ASL/C syntax Unique ID used in GpioPad defines

Definition at line 46 of file GpioPinsVer4S.h.

◆ GPIO_VER4_S_GPP_I0

#define GPIO_VER4_S_GPP_I0 0x08000000

ADL S GPIO pins Use below for functions from PCH GPIO Lib which require GpioPad as argument.

Encoding used here has all information required by library functions

Definition at line 80 of file GpioPinsVer4S.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioPinsVer4S.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
GpioPinsVer4S.h
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1 /** @file
2 GPIO pins for ADL-PCH-S,
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GPIO_PINS_VER4_S_H_
36 #define _GPIO_PINS_VER4_S_H_
37 ///
38 /// This header file should be used together with
39 /// PCH GPIO lib in C and ASL. All defines used
40 /// must match both ASL/C syntax
41 ///
42
43 ///
44 /// Unique ID used in GpioPad defines
45 ///
46 #define GPIO_VER4_S_CHIPSET_ID 0x8
47
48 ///
49 /// ADL S GPIO Groups
50 /// Use below for functions from PCH GPIO Lib which
51 /// require GpioGroup as argument
52 ///
53 #define GPIO_VER4_S_GROUP_GPP_I 0x0800
54 #define GPIO_VER4_S_GROUP_GPP_R 0x0801
55 #define GPIO_VER4_S_GROUP_GPP_J 0x0802
56 #define GPIO_VER4_S_GROUP_VGPIO 0x0803
57 #define GPIO_VER4_S_GROUP_VGPIO_0 0x0804
58 #define GPIO_VER4_S_GROUP_GPP_B 0x0805
59 #define GPIO_VER4_S_GROUP_GPP_G 0x0806
60 #define GPIO_VER4_S_GROUP_GPP_H 0x0807
61 #define GPIO_VER4_S_GROUP_GPD 0x0808
62 #define GPIO_VER4_S_GROUP_SPI 0x0809
63 #define GPIO_VER4_S_GROUP_GPP_A 0x080A
64 #define GPIO_VER4_S_GROUP_GPP_C 0x080B
65 #define GPIO_VER4_S_GROUP_VGPIO_3 0x080C
66 #define GPIO_VER4_S_GROUP_GPP_S 0x080D
67 #define GPIO_VER4_S_GROUP_GPP_E 0x080E
68 #define GPIO_VER4_S_GROUP_GPP_K 0x080F
69 #define GPIO_VER4_S_GROUP_GPP_F 0x0810
70 #define GPIO_VER4_S_GROUP_GPP_D 0x0811
71 #define GPIO_VER4_S_GROUP_JTAG 0x0812
72 #define GPIO_VER4_S_GROUP_CPU 0x0813
73
74 ///
75 /// ADL S GPIO pins
76 /// Use below for functions from PCH GPIO Lib which
77 /// require GpioPad as argument. Encoding used here
78 /// has all information required by library functions
79 ///
80 #define GPIO_VER4_S_GPP_I0 0x08000000
81 #define GPIO_VER4_S_GPP_I1 0x08000001
82 #define GPIO_VER4_S_GPP_I2 0x08000002
83 #define GPIO_VER4_S_GPP_I3 0x08000003
84 #define GPIO_VER4_S_GPP_I4 0x08000004
85 #define GPIO_VER4_S_GPP_I5 0x08000005
86 #define GPIO_VER4_S_GPP_I6 0x08000006
87 #define GPIO_VER4_S_GPP_I7 0x08000007
88 #define GPIO_VER4_S_GPP_I8 0x08000008
89 #define GPIO_VER4_S_GPP_I9 0x08000009
90 #define GPIO_VER4_S_GPP_I10 0x0800000A
91 #define GPIO_VER4_S_GPP_I11 0x0800000B
92 #define GPIO_VER4_S_GPP_I12 0x0800000C
93 #define GPIO_VER4_S_GPP_I13 0x0800000D
94 #define GPIO_VER4_S_GPP_I14 0x0800000E
95 #define GPIO_VER4_S_GPP_I15 0x0800000F
96 #define GPIO_VER4_S_GPP_I16 0x08000010
97 #define GPIO_VER4_S_GPP_I17 0x08000011
98 #define GPIO_VER4_S_GPP_I18 0x08000012
99 #define GPIO_VER4_S_GPP_I19 0x08000013
100 #define GPIO_VER4_S_GPP_I20 0x08000014
101 #define GPIO_VER4_S_GPP_I21 0x08000015
102 #define GPIO_VER4_S_GPP_I22 0x08000016
103 #define GPIO_VER4_S_GSPI0_CLK_LOOPBK 0x08000017
104 #define GPIO_VER4_S_GSPI1_CLK_LOOPBK 0x08000018
105
106 #define GPIO_VER4_S_GPP_R0 0x08010000
107 #define GPIO_VER4_S_GPP_R1 0x08010001
108 #define GPIO_VER4_S_GPP_R2 0x08010002
109 #define GPIO_VER4_S_GPP_R3 0x08010003
110 #define GPIO_VER4_S_GPP_R4 0x08010004
111 #define GPIO_VER4_S_GPP_R5 0x08010005
112 #define GPIO_VER4_S_GPP_R6 0x08010006
113 #define GPIO_VER4_S_GPP_R7 0x08010007
114 #define GPIO_VER4_S_GPP_R8 0x08010008
115 #define GPIO_VER4_S_GPP_R9 0x08010009
116 #define GPIO_VER4_S_GPP_R10 0x0801000A
117 #define GPIO_VER4_S_GPP_R11 0x0801000B
118 #define GPIO_VER4_S_GPP_R12 0x0801000C
119 #define GPIO_VER4_S_GPP_R13 0x0801000D
120 #define GPIO_VER4_S_GPP_R14 0x0801000E
121 #define GPIO_VER4_S_GPP_R15 0x0801000F
122 #define GPIO_VER4_S_GPP_R16 0x08010010
123 #define GPIO_VER4_S_GPP_R17 0x08010011
124 #define GPIO_VER4_S_GPP_R18 0x08010012
125 #define GPIO_VER4_S_GPP_R19 0x08010013
126 #define GPIO_VER4_S_GPP_R20 0x08010014
127 #define GPIO_VER4_S_GPP_R21 0x08010015
128 #define GPIO_VER4_S_GSPI2_CLK_LOOPBK 0x08010016
129
130 #define GPIO_VER4_S_GPP_J0 0x08020000
131 #define GPIO_VER4_S_GPP_J1 0x08020001
132 #define GPIO_VER4_S_GPP_J2 0x08020002
133 #define GPIO_VER4_S_GPP_J3 0x08020003
134 #define GPIO_VER4_S_GPP_J4 0x08020004
135 #define GPIO_VER4_S_GPP_J5 0x08020005
136 #define GPIO_VER4_S_GPP_J6 0x08020006
137 #define GPIO_VER4_S_GPP_J7 0x08020007
138 #define GPIO_VER4_S_GPP_J8 0x08020008
139 #define GPIO_VER4_S_GPP_J9 0x08020009
140 #define GPIO_VER4_S_GPP_J10 0x0802000A
141 #define GPIO_VER4_S_GPP_J11 0x0802000B
142
143 #define GPIO_VER4_S_VGPIO0 0x08030000
144 #define GPIO_VER4_S_VGPIO4 0x08030001
145 #define GPIO_VER4_S_VGPIO5 0x08030002
146 #define GPIO_VER4_S_VGPIO6 0x08030003
147 #define GPIO_VER4_S_VGPIO7 0x08030004
148 #define GPIO_VER4_S_VGPIO8 0x08030005
149 #define GPIO_VER4_S_VGPIO9 0x08030006
150 #define GPIO_VER4_S_VGPIO10 0x08030007
151 #define GPIO_VER4_S_VGPIO11 0x08030008
152 #define GPIO_VER4_S_VGPIO12 0x08030009
153 #define GPIO_VER4_S_VGPIO13 0x0803000A
154 #define GPIO_VER4_S_VGPIO18 0x0803000B
155 #define GPIO_VER4_S_VGPIO19 0x0803000C
156 #define GPIO_VER4_S_VGPIO20 0x0803000D
157 #define GPIO_VER4_S_VGPIO21 0x0803000E
158 #define GPIO_VER4_S_VGPIO22 0x0803000F
159 #define GPIO_VER4_S_VGPIO23 0x08030010
160 #define GPIO_VER4_S_VGPIO24 0x08030011
161 #define GPIO_VER4_S_VGPIO25 0x08030012
162 #define GPIO_VER4_S_VGPIO30 0x08030013
163 #define GPIO_VER4_S_VGPIO31 0x08030014
164 #define GPIO_VER4_S_VGPIO32 0x08030015
165 #define GPIO_VER4_S_VGPIO33 0x08030016
166 #define GPIO_VER4_S_VGPIO34 0x08030017
167 #define GPIO_VER4_S_VGPIO35 0x08030018
168 #define GPIO_VER4_S_VGPIO36 0x08030019
169 #define GPIO_VER4_S_VGPIO37 0x0803001A
170
171 #define GPIO_VER4_S_VGPIO_USB_0 0x08040000
172 #define GPIO_VER4_S_VGPIO_USB_1 0x08040001
173 #define GPIO_VER4_S_VGPIO_USB_2 0x08040002
174 #define GPIO_VER4_S_VGPIO_USB_3 0x08040003
175 #define GPIO_VER4_S_VGPIO_USB_8 0x08040004
176 #define GPIO_VER4_S_VGPIO_USB_9 0x08040005
177 #define GPIO_VER4_S_VGPIO_USB_10 0x08040006
178 #define GPIO_VER4_S_VGPIO_USB_11 0x08040007
179
180 #define GPIO_VER4_S_GPP_B0 0x08050000
181 #define GPIO_VER4_S_GPP_B1 0x08050001
182 #define GPIO_VER4_S_GPP_B2 0x08050002
183 #define GPIO_VER4_S_GPP_B3 0x08050003
184 #define GPIO_VER4_S_GPP_B4 0x08050004
185 #define GPIO_VER4_S_GPP_B5 0x08050005
186 #define GPIO_VER4_S_GPP_B6 0x08050006
187 #define GPIO_VER4_S_GPP_B7 0x08050007
188 #define GPIO_VER4_S_GPP_B8 0x08050008
189 #define GPIO_VER4_S_GPP_B9 0x08050009
190 #define GPIO_VER4_S_GPP_B10 0x0805000A
191 #define GPIO_VER4_S_GPP_B11 0x0805000B
192 #define GPIO_VER4_S_GPP_B12 0x0805000C
193 #define GPIO_VER4_S_GPP_B13 0x0805000D
194 #define GPIO_VER4_S_GPP_B14 0x0805000E
195 #define GPIO_VER4_S_GPP_B15 0x0805000F
196 #define GPIO_VER4_S_GPP_B16 0x08050010
197 #define GPIO_VER4_S_GPP_B17 0x08050011
198 #define GPIO_VER4_S_GPP_B18 0x08050012
199 #define GPIO_VER4_S_GPP_B19 0x08050013
200 #define GPIO_VER4_S_GPP_B20 0x08050014
201 #define GPIO_VER4_S_GPP_B21 0x08050015
202 #define GPIO_VER4_S_GPP_B22 0x08050016
203 #define GPIO_VER4_S_GPP_B23 0x08050017
204
205 #define GPIO_VER4_S_GPP_G0 0x08060000
206 #define GPIO_VER4_S_GPP_G1 0x08060001
207 #define GPIO_VER4_S_GPP_G2 0x08060002
208 #define GPIO_VER4_S_GPP_G3 0x08060003
209 #define GPIO_VER4_S_GPP_G4 0x08060004
210 #define GPIO_VER4_S_GPP_G5 0x08060005
211 #define GPIO_VER4_S_GPP_G6 0x08060006
212 #define GPIO_VER4_S_GPP_G7 0x08060007
213
214 #define GPIO_VER4_S_GPP_H0 0x08070000
215 #define GPIO_VER4_S_GPP_H1 0x08070001
216 #define GPIO_VER4_S_GPP_H2 0x08070002
217 #define GPIO_VER4_S_GPP_H3 0x08070003
218 #define GPIO_VER4_S_GPP_H4 0x08070004
219 #define GPIO_VER4_S_GPP_H5 0x08070005
220 #define GPIO_VER4_S_GPP_H6 0x08070006
221 #define GPIO_VER4_S_GPP_H7 0x08070007
222 #define GPIO_VER4_S_GPP_H8 0x08070008
223 #define GPIO_VER4_S_GPP_H9 0x08070009
224 #define GPIO_VER4_S_GPP_H10 0x0807000A
225 #define GPIO_VER4_S_GPP_H11 0x0807000B
226 #define GPIO_VER4_S_GPP_H12 0x0807000C
227 #define GPIO_VER4_S_GPP_H13 0x0807000D
228 #define GPIO_VER4_S_GPP_H14 0x0807000E
229 #define GPIO_VER4_S_GPP_H15 0x0807000F
230 #define GPIO_VER4_S_GPP_H16 0x08070010
231 #define GPIO_VER4_S_GPP_H17 0x08070011
232 #define GPIO_VER4_S_GPP_H18 0x08070012
233 #define GPIO_VER4_S_GPP_H19 0x08070013
234 #define GPIO_VER4_S_GPP_H20 0x08070014
235 #define GPIO_VER4_S_GPP_H21 0x08070015
236 #define GPIO_VER4_S_GPP_H22 0x08070016
237 #define GPIO_VER4_S_GPP_H23 0x08070017
238
239 #define GPIO_VER4_S_GPD0 0x08080000
240 #define GPIO_VER4_S_GPD1 0x08080001
241 #define GPIO_VER4_S_GPD2 0x08080002
242 #define GPIO_VER4_S_GPD3 0x08080003
243 #define GPIO_VER4_S_GPD4 0x08080004
244 #define GPIO_VER4_S_GPD5 0x08080005
245 #define GPIO_VER4_S_GPD6 0x08080006
246 #define GPIO_VER4_S_GPD7 0x08080007
247 #define GPIO_VER4_S_GPD8 0x08080008
248 #define GPIO_VER4_S_GPD9 0x08080009
249 #define GPIO_VER4_S_GPD10 0x0808000A
250 #define GPIO_VER4_S_GPD11 0x0808000B
251 #define GPIO_VER4_S_GPD12 0x0808000C
252 #define GPIO_VER4_S_SLP_LANB 0x0808000D
253 #define GPIO_VER4_S_SLP_SUSB 0x0808000E
254 #define GPIO_VER4_S_WAKEB 0x0808000F
255 #define GPIO_VER4_S_DRAM_RESETB 0x08080010
256
257 #define GPIO_VER4_S_SPI0_IO_2 0x08090000
258 #define GPIO_VER4_S_SPI0_IO_3 0x08090001
259 #define GPIO_VER4_S_SPI0_MOSI_IO_0 0x08090002
260 #define GPIO_VER4_S_SPI0_MISO_IO_1 0x08090003
261 #define GPIO_VER4_S_SPI0_TPM_CSB 0x08090004
262 #define GPIO_VER4_S_SPI0_FLASH_0_CSB 0x08090005
263 #define GPIO_VER4_S_SPI0_FLASH_1_CSB 0x08090006
264 #define GPIO_VER4_S_SPI0_CLK 0x08090007
265 #define GPIO_VER4_S_SPI0_CLK_LOOPBK 0x08090008
266
267 #define GPIO_VER4_S_GPP_A0 0x080A0000
268 #define GPIO_VER4_S_GPP_A1 0x080A0001
269 #define GPIO_VER4_S_GPP_A2 0x080A0002
270 #define GPIO_VER4_S_GPP_A3 0x080A0003
271 #define GPIO_VER4_S_GPP_A4 0x080A0004
272 #define GPIO_VER4_S_GPP_A5 0x080A0005
273 #define GPIO_VER4_S_GPP_A6 0x080A0006
274 #define GPIO_VER4_S_GPP_A7 0x080A0007
275 #define GPIO_VER4_S_GPP_A8 0x080A0008
276 #define GPIO_VER4_S_GPP_A9 0x080A0009
277 #define GPIO_VER4_S_GPP_A10 0x080A000A
278 #define GPIO_VER4_S_GPP_A11 0x080A000B
279 #define GPIO_VER4_S_GPP_A12 0x080A000C
280 #define GPIO_VER4_S_GPP_A13 0x080A000D
281 #define GPIO_VER4_S_GPP_A14 0x080A000E
282 #define GPIO_VER4_S_ESPI_CLK_LOOPBK 0x080A000F
283
284 #define GPIO_VER4_S_GPP_C0 0x080B0000
285 #define GPIO_VER4_S_GPP_C1 0x080B0001
286 #define GPIO_VER4_S_GPP_C2 0x080B0002
287 #define GPIO_VER4_S_GPP_C3 0x080B0003
288 #define GPIO_VER4_S_GPP_C4 0x080B0004
289 #define GPIO_VER4_S_GPP_C5 0x080B0005
290 #define GPIO_VER4_S_GPP_C6 0x080B0006
291 #define GPIO_VER4_S_GPP_C7 0x080B0007
292 #define GPIO_VER4_S_GPP_C8 0x080B0008
293 #define GPIO_VER4_S_GPP_C9 0x080B0009
294 #define GPIO_VER4_S_GPP_C10 0x080B000A
295 #define GPIO_VER4_S_GPP_C11 0x080B000B
296 #define GPIO_VER4_S_GPP_C12 0x080B000C
297 #define GPIO_VER4_S_GPP_C13 0x080B000D
298 #define GPIO_VER4_S_GPP_C14 0x080B000E
299 #define GPIO_VER4_S_GPP_C15 0x080B000F
300 #define GPIO_VER4_S_GPP_C16 0x080B0010
301 #define GPIO_VER4_S_GPP_C17 0x080B0011
302 #define GPIO_VER4_S_GPP_C18 0x080B0012
303 #define GPIO_VER4_S_GPP_C19 0x080B0013
304 #define GPIO_VER4_S_GPP_C20 0x080B0014
305 #define GPIO_VER4_S_GPP_C21 0x080B0015
306 #define GPIO_VER4_S_GPP_C22 0x080B0016
307 #define GPIO_VER4_S_GPP_C23 0x080B0017
308
309 #define GPIO_VER4_S_VGPIO_PCIE_0 0x080C0000
310 #define GPIO_VER4_S_VGPIO_PCIE_1 0x080C0001
311 #define GPIO_VER4_S_VGPIO_PCIE_2 0x080C0002
312 #define GPIO_VER4_S_VGPIO_PCIE_3 0x080C0003
313 #define GPIO_VER4_S_VGPIO_PCIE_4 0x080C0004
314 #define GPIO_VER4_S_VGPIO_PCIE_5 0x080C0005
315 #define GPIO_VER4_S_VGPIO_PCIE_6 0x080C0006
316 #define GPIO_VER4_S_VGPIO_PCIE_7 0x080C0007
317 #define GPIO_VER4_S_VGPIO_PCIE_8 0x080C0008
318 #define GPIO_VER4_S_VGPIO_PCIE_9 0x080C0009
319 #define GPIO_VER4_S_VGPIO_PCIE_10 0x080C000A
320 #define GPIO_VER4_S_VGPIO_PCIE_11 0x080C000B
321 #define GPIO_VER4_S_VGPIO_PCIE_12 0x080C000C
322 #define GPIO_VER4_S_VGPIO_PCIE_13 0x080C000D
323 #define GPIO_VER4_S_VGPIO_PCIE_14 0x080C000E
324 #define GPIO_VER4_S_VGPIO_PCIE_15 0x080C000F
325 #define GPIO_VER4_S_VGPIO_PCIE_16 0x080C0010
326 #define GPIO_VER4_S_VGPIO_PCIE_17 0x080C0011
327 #define GPIO_VER4_S_VGPIO_PCIE_18 0x080C0012
328 #define GPIO_VER4_S_VGPIO_PCIE_19 0x080C0013
329 #define GPIO_VER4_S_VGPIO_PCIE_20 0x080C0014
330 #define GPIO_VER4_S_VGPIO_PCIE_21 0x080C0015
331 #define GPIO_VER4_S_VGPIO_PCIE_22 0x080C0016
332 #define GPIO_VER4_S_VGPIO_PCIE_23 0x080C0017
333 #define GPIO_VER4_S_VGPIO_PCIE_24 0x080C0018
334 #define GPIO_VER4_S_VGPIO_PCIE_25 0x080C0019
335 #define GPIO_VER4_S_VGPIO_PCIE_26 0x080C001A
336 #define GPIO_VER4_S_VGPIO_PCIE_27 0x080C001B
337 #define GPIO_VER4_S_VGPIO_PCIE_28 0x080C001C
338 #define GPIO_VER4_S_VGPIO_PCIE_29 0x080C001D
339 #define GPIO_VER4_S_VGPIO_PCIE_30 0x080C001E
340 #define GPIO_VER4_S_VGPIO_PCIE_31 0x080C001F
341 #define GPIO_VER4_S_VGPIO_PCIE_32 0x080C0020
342 #define GPIO_VER4_S_VGPIO_PCIE_33 0x080C0021
343 #define GPIO_VER4_S_VGPIO_PCIE_34 0x080C0022
344 #define GPIO_VER4_S_VGPIO_PCIE_35 0x080C0023
345 #define GPIO_VER4_S_VGPIO_PCIE_36 0x080C0024
346 #define GPIO_VER4_S_VGPIO_PCIE_37 0x080C0025
347 #define GPIO_VER4_S_VGPIO_PCIE_38 0x080C0026
348 #define GPIO_VER4_S_VGPIO_PCIE_39 0x080C0027
349 #define GPIO_VER4_S_VGPIO_PCIE_40 0x080C0028
350 #define GPIO_VER4_S_VGPIO_PCIE_41 0x080C0029
351 #define GPIO_VER4_S_VGPIO_PCIE_42 0x080C002A
352 #define GPIO_VER4_S_VGPIO_PCIE_43 0x080C002B
353 #define GPIO_VER4_S_VGPIO_PCIE_44 0x080C002C
354 #define GPIO_VER4_S_VGPIO_PCIE_45 0x080C002D
355 #define GPIO_VER4_S_VGPIO_PCIE_46 0x080C002E
356 #define GPIO_VER4_S_VGPIO_PCIE_47 0x080C002F
357 #define GPIO_VER4_S_VGPIO_PCIE_48 0x080C0030
358 #define GPIO_VER4_S_VGPIO_PCIE_49 0x080C0031
359 #define GPIO_VER4_S_VGPIO_PCIE_50 0x080C0032
360 #define GPIO_VER4_S_VGPIO_PCIE_51 0x080C0033
361 #define GPIO_VER4_S_VGPIO_PCIE_52 0x080C0034
362 #define GPIO_VER4_S_VGPIO_PCIE_53 0x080C0035
363 #define GPIO_VER4_S_VGPIO_PCIE_54 0x080C0036
364 #define GPIO_VER4_S_VGPIO_PCIE_55 0x080C0037
365 #define GPIO_VER4_S_VGPIO_PCIE_56 0x080C0038
366 #define GPIO_VER4_S_VGPIO_PCIE_57 0x080C0039
367 #define GPIO_VER4_S_VGPIO_PCIE_58 0x080C003A
368 #define GPIO_VER4_S_VGPIO_PCIE_59 0x080C003B
369 #define GPIO_VER4_S_VGPIO_PCIE_60 0x080C003C
370 #define GPIO_VER4_S_VGPIO_PCIE_61 0x080C003D
371 #define GPIO_VER4_S_VGPIO_PCIE_62 0x080C003E
372 #define GPIO_VER4_S_VGPIO_PCIE_63 0x080C003F
373 #define GPIO_VER4_S_VGPIO_PCIE_64 0x080C0040
374 #define GPIO_VER4_S_VGPIO_PCIE_65 0x080C0041
375 #define GPIO_VER4_S_VGPIO_PCIE_66 0x080C0042
376 #define GPIO_VER4_S_VGPIO_PCIE_67 0x080C0043
377 #define GPIO_VER4_S_VGPIO_PCIE_68 0x080C0044
378 #define GPIO_VER4_S_VGPIO_PCIE_69 0x080C0045
379 #define GPIO_VER4_S_VGPIO_PCIE_70 0x080C0046
380 #define GPIO_VER4_S_VGPIO_PCIE_71 0x080C0047
381 #define GPIO_VER4_S_VGPIO_PCIE_72 0x080C0048
382 #define GPIO_VER4_S_VGPIO_PCIE_73 0x080C0049
383 #define GPIO_VER4_S_VGPIO_PCIE_74 0x080C004A
384 #define GPIO_VER4_S_VGPIO_PCIE_75 0x080C004B
385 #define GPIO_VER4_S_VGPIO_PCIE_76 0x080C004C
386 #define GPIO_VER4_S_VGPIO_PCIE_77 0x080C004D
387 #define GPIO_VER4_S_VGPIO_PCIE_78 0x080C004E
388 #define GPIO_VER4_S_VGPIO_PCIE_79 0x080C004F
389 #define GPIO_VER4_S_VGPIO_PCIE_80 0x080C0050
390 #define GPIO_VER4_S_VGPIO_PCIE_81 0x080C0051
391 #define GPIO_VER4_S_VGPIO_PCIE_82 0x080C0052
392 #define GPIO_VER4_S_VGPIO_PCIE_83 0x080C0053
393
394 #define GPIO_VER4_S_GPP_S0 0x080D0000
395 #define GPIO_VER4_S_GPP_S1 0x080D0001
396 #define GPIO_VER4_S_GPP_S2 0x080D0002
397 #define GPIO_VER4_S_GPP_S3 0x080D0003
398 #define GPIO_VER4_S_GPP_S4 0x080D0004
399 #define GPIO_VER4_S_GPP_S5 0x080D0005
400 #define GPIO_VER4_S_GPP_S6 0x080D0006
401 #define GPIO_VER4_S_GPP_S7 0x080D0007
402
403 #define GPIO_VER4_S_GPP_E0 0x080E0000
404 #define GPIO_VER4_S_GPP_E1 0x080E0001
405 #define GPIO_VER4_S_GPP_E2 0x080E0002
406 #define GPIO_VER4_S_GPP_E3 0x080E0003
407 #define GPIO_VER4_S_GPP_E4 0x080E0004
408 #define GPIO_VER4_S_GPP_E5 0x080E0005
409 #define GPIO_VER4_S_GPP_E6 0x080E0006
410 #define GPIO_VER4_S_GPP_E7 0x080E0007
411 #define GPIO_VER4_S_GPP_E8 0x080E0008
412 #define GPIO_VER4_S_GPP_E9 0x080E0009
413 #define GPIO_VER4_S_GPP_E10 0x080E000A
414 #define GPIO_VER4_S_GPP_E11 0x080E000B
415 #define GPIO_VER4_S_GPP_E12 0x080E000C
416 #define GPIO_VER4_S_GPP_E13 0x080E000D
417 #define GPIO_VER4_S_GPP_E14 0x080E000E
418 #define GPIO_VER4_S_GPP_E15 0x080E000F
419 #define GPIO_VER4_S_GPP_E16 0x080E0010
420 #define GPIO_VER4_S_GPP_E17 0x080E0011
421 #define GPIO_VER4_S_GPP_E18 0x080E0012
422 #define GPIO_VER4_S_GPP_E19 0x080E0013
423 #define GPIO_VER4_S_GPP_E20 0x080E0014
424 #define GPIO_VER4_S_GPP_E21 0x080E0015
425 #define GPIO_VER4_S_SPI1_THC0_CLK_LOOPBK 0x080E0016
426
427 #define GPIO_VER4_S_GPP_K0 0x080F0000
428 #define GPIO_VER4_S_GPP_K1 0x080F0001
429 #define GPIO_VER4_S_GPP_K2 0x080F0002
430 #define GPIO_VER4_S_GPP_K3 0x080F0003
431 #define GPIO_VER4_S_GPP_K4 0x080F0004
432 #define GPIO_VER4_S_GPP_K5 0x080F0005
433 #define GPIO_VER4_S_GPP_K6 0x080F0006
434 #define GPIO_VER4_S_GPP_K7 0x080F0007
435 #define GPIO_VER4_S_GPP_K8 0x080F0008
436 #define GPIO_VER4_S_GPP_K9 0x080F0009
437 #define GPIO_VER4_S_GPP_K10 0x080F000A
438 #define GPIO_VER4_S_GPP_K11 0x080F000B
439 #define GPIO_VER4_S_SYS_PWROK 0x080F000C
440 #define GPIO_VER4_S_SYS_RESETB 0x080F000D
441 #define GPIO_VER4_S_MLK_RSTB 0x080F000E
442
443 #define GPIO_VER4_S_GPP_F0 0x08100000
444 #define GPIO_VER4_S_GPP_F1 0x08100001
445 #define GPIO_VER4_S_GPP_F2 0x08100002
446 #define GPIO_VER4_S_GPP_F3 0x08100003
447 #define GPIO_VER4_S_GPP_F4 0x08100004
448 #define GPIO_VER4_S_GPP_F5 0x08100005
449 #define GPIO_VER4_S_GPP_F6 0x08100006
450 #define GPIO_VER4_S_GPP_F7 0x08100007
451 #define GPIO_VER4_S_GPP_F8 0x08100008
452 #define GPIO_VER4_S_GPP_F9 0x08100009
453 #define GPIO_VER4_S_GPP_F10 0x0810000A
454 #define GPIO_VER4_S_GPP_F11 0x0810000B
455 #define GPIO_VER4_S_GPP_F12 0x0810000C
456 #define GPIO_VER4_S_GPP_F13 0x0810000D
457 #define GPIO_VER4_S_GPP_F14 0x0810000E
458 #define GPIO_VER4_S_GPP_F15 0x0810000F
459 #define GPIO_VER4_S_GPP_F16 0x08100010
460 #define GPIO_VER4_S_GPP_F17 0x08100011
461 #define GPIO_VER4_S_GPP_F18 0x08100012
462 #define GPIO_VER4_S_GPP_F19 0x08100013
463 #define GPIO_VER4_S_GPP_F20 0x08100014
464 #define GPIO_VER4_S_GPP_F21 0x08100015
465 #define GPIO_VER4_S_GPP_F22 0x08100016
466 #define GPIO_VER4_S_GPP_F23 0x08100017
467
468 #define GPIO_VER4_S_GPP_D0 0x08110000
469 #define GPIO_VER4_S_GPP_D1 0x08110001
470 #define GPIO_VER4_S_GPP_D2 0x08110002
471 #define GPIO_VER4_S_GPP_D3 0x08110003
472 #define GPIO_VER4_S_GPP_D4 0x08110004
473 #define GPIO_VER4_S_GPP_D5 0x08110005
474 #define GPIO_VER4_S_GPP_D6 0x08110006
475 #define GPIO_VER4_S_GPP_D7 0x08110007
476 #define GPIO_VER4_S_GPP_D8 0x08110008
477 #define GPIO_VER4_S_GPP_D9 0x08110009
478 #define GPIO_VER4_S_GPP_D10 0x0811000A
479 #define GPIO_VER4_S_GPP_D11 0x0811000B
480 #define GPIO_VER4_S_GPP_D12 0x0811000C
481 #define GPIO_VER4_S_GPP_D13 0x0811000D
482 #define GPIO_VER4_S_GPP_D14 0x0811000E
483 #define GPIO_VER4_S_GPP_D15 0x0811000F
484 #define GPIO_VER4_S_GPP_D16 0x08110010
485 #define GPIO_VER4_S_GPP_D17 0x08110011
486 #define GPIO_VER4_S_GPP_D18 0x08110012
487 #define GPIO_VER4_S_GPP_D19 0x08110013
488 #define GPIO_VER4_S_GPP_D20 0x08110014
489 #define GPIO_VER4_S_GPP_D21 0x08110015
490 #define GPIO_VER4_S_GPP_D22 0x08110016
491 #define GPIO_VER4_S_GPP_D23 0x08110017
492 #define GPIO_VER4_S_GSPI3_THC1_CLK_LOOPBK 0x08110018
493
494 #define GPIO_VER4_S_JTAG_TDO 0x08120000
495 #define GPIO_VER4_S_JTAGX 0x08120001
496 #define GPIO_VER4_S_PRDYB 0x08120002
497 #define GPIO_VER4_S_PREQB 0x08120003
498 #define GPIO_VER4_S_JTAG_TDI 0x08120004
499 #define GPIO_VER4_S_JTAG_TMS 0x08120005
500 #define GPIO_VER4_S_JTAG_TCK 0x08120006
501 #define GPIO_VER4_S_DBG_PMODE 0x08120007
502 #define GPIO_VER4_S_CPU_TRSTB 0x08120008
503
504 #define GPIO_VER4_S_HDACPU_SDI 0x08130000
505 #define GPIO_VER4_S_HDACPU_SDO 0x08130001
506 #define GPIO_VER4_S_HDACPU_SCLK 0x08130002
507 #define GPIO_VER4_S_PM_SYNC 0x08130003
508 #define GPIO_VER4_S_PECI 0x08130004
509 #define GPIO_VER4_S_CPUPWRGD 0x08130005
510 #define GPIO_VER4_S_THRMTRIPB 0x08130006
511 #define GPIO_VER4_S_PLTRST_CPUB 0x08130007
512 #define GPIO_VER4_S_PM_DOWN 0x08130008
513 #define GPIO_VER4_S_TRIGGER_IN 0x08130009
514 #define GPIO_VER4_S_TRIGGER_OUT 0x0813000A
515 #define GPIO_VER4_S_CLKOUT_CPURTC 0x0813000B
516 #define GPIO_VER4_S_VCCST_OVERRIDE 0x0813000C
517 #define GPIO_VER4_S_C10_WAKE 0x0813000D
518
519 //
520 // GPIO Pin Muxing
521 // Determines a selection of physical pad for a given signal.
522 // Please refer to GPIO_NATIVE_PAD type.
523 // If certain signal is not listed below it means that it can be enabled
524 // only on a single pad and muxing setting is not needed.
525 //
526 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_RXD_GPP_J3 0x28020203
527 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_TXD_GPP_J4 0x28021204
528 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_RTS_GPP_J2 0x28022202
529 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_CTS_GPP_J5 0x28023205
530
531 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_RXD_GPP_C8 0x180b0208
532 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_TXD_GPP_C9 0x180b1209
533 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_RTS_GPP_C10 0x180b220a
534 #define GPIO_VER4_S_MUXING_SERIALIO_UART0_CTS_GPP_C11 0x180b320b
535
536 #endif // _GPIO_PINS_VER4_S_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
GpioRegs.h File Reference

Register names for PCH GPIO. More...

Go to the source code of this file.

Macros

#define | PCH_GPIO_NUM_SUPPORTED_GPIS 512
GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL Below defines are to be used internally by PCH SMI dispatcher only.
#define | PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
Groups mapped to 2-tier General Purpose Event will all be under one Primary GPE_111 (0x6F)

Detailed Description

Register names for PCH GPIO.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioRegs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
GpioRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH GPIO
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2013 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _GPIO_REGS_H_
65 #define _GPIO_REGS_H_
66
67 //
68 // GPIO Common Private Configuration Registers
69 //
70 #define R_GPIO_PCR_REV_ID 0x00
71 #define R_GPIO_PCR_CAP_LIST 0x04
72 #define R_GPIO_PCR_FAMBAR 0x08
73 #define R_GPIO_PCR_PADBAR 0x0C
74 #define B_GPIO_PCR_PADBAR 0x0000FFFF
75 #define R_GPIO_PCR_MISCCFG 0x10
76 #define B_GPIO_PCR_MISCCFG_IRQ_ROUTE 0xFF000000
77 #define N_GPIO_PCR_MISCCFG_IRQ_ROUTE 24
78 #define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16)
79 #define N_GPIO_PCR_MISCCFG_GPE0_DW2 16
80 #define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12)
81 #define N_GPIO_PCR_MISCCFG_GPE0_DW1 12
82 #define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8)
83 #define N_GPIO_PCR_MISCCFG_GPE0_DW0 8
84 #define B_GPIO_PCR_MISCCFG_GPVNNREQEN BIT7
85 #define B_GPIO_PCR_MISCCFG_GPPGCBDPCGEN BIT6
86 #define B_GPIO_PCR_MISCCFG_GPSIDEDPCGEN BIT5
87 #define B_GPIO_PCR_MISCCFG_GPRCOMPCDLCGEN BIT4
88 #define B_GPIO_PCR_MISCCFG_GPRTCDLCGEN BIT3
89 #define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1
90 #define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0
91 #define R_GPIO_PCR_MISCSECCFG 0x14
92
93 //
94 // GPIO SerialBlink/PWM registers
95 //
96 #define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200
97 #define R_GPIO_PCR_PWMC 0x0204
98 #define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208
99 #define R_GPIO_PCR_GP_SER_BLINK 0x020C
100 #define B_GPIO_PCR_GP_SER_BLINK 0x1F
101 #define R_GPIO_PCR_GP_SER_CMDSTS 0x0210
102 #define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22)
103 #define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22
104 #define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000
105 #define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16
106 #define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8
107 #define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0
108 #define R_GPIO_PCR_GP_SER_DATA 0x0214
109
110 //
111 // Host Software Pad Ownership modes
112 //
113 #define V_GPIO_PCR_HOSTSW_OWN_ACPI 0x00
114 #define V_GPIO_PCR_HOSTSW_OWN_GPIO 0x01
115
116 //
117 // Pad Ownership modes
118 //
119 #define V_GPIO_PCR_PAD_OWN_HOST 0x00
120 #define V_GPIO_PCR_PAD_OWN_CSME 0x01
121 #define V_GPIO_PCR_PAD_OWN_ISH 0x02
122
123 //
124 // PADCFG register is split into multiple DW registers
125 // S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
126 //
127 #define S_GPIO_PCR_PADCFG 0x10
128
129 //
130 // Pad Configuration Register DW0
131 //
132
133 //Pad Reset Config
134 #define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)
135 #define N_GPIO_PCR_RST_CONF 30
136 #define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00
137 #define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01
138 #define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02
139 #define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group
140 #define V_GPIO_PCR_RST_CONF_GLOBAL_RST 0x03 // Only for server chipsets
141
142 //RX Pad State Select
143 #define B_GPIO_PCR_RX_PAD_STATE BIT29
144 #define N_GPIO_PCR_RX_PAD_STATE 29
145 #define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00
146 #define V_GPIO_PCR_RX_PAD_STATE_INT 0x01
147
148 //RX Raw Override to 1
149 #define B_GPIO_PCR_RX_RAW1 BIT28
150 #define N_GPIO_PCR_RX_RAW1 28
151 #define V_GPIO_PCR_RX_RAW1_DIS 0x00
152 #define V_GPIO_PCR_RX_RAW1_EN 0x01
153
154 //NAF VWE Override to 1
155 #define B_PCH_GPIO_NAF_VWE BIT27
156 #define N_PCH_GPIO_NAF_VWE 27
157 #define V_PCH_GPIO_NAF_VWE_DIS 0x00
158 #define V_PCH_GPIO_NAF_VWE_EN 0x01
159
160 //RX Level/Edge Configuration
161 #define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
162 #define N_GPIO_PCR_RX_LVL_EDG 25
163 #define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00
164 #define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01
165 #define V_GPIO_PCR_RX_LVL_EDG_0 0x02
166 #define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03
167 //RX Level/Edge Configuration for Virtual GPIO
168 #define B_VGPIO_PCR_RX_LVL_EDG (BIT23 | BIT22)
169 #define N_VGPIO_PCR_RX_LVL_EDG 22
170 #define V_VGPIO_PCR_RX_LVL_EDG_LVL 0x00
171 #define V_VGPIO_PCR_RX_LVL_EDG_0 0x02
172
173 //RX Invert
174 #define B_GPIO_PCR_RXINV BIT23
175 #define N_GPIO_PCR_RXINV 23
176 #define V_GPIO_PCR_RXINV_NO 0x00
177 #define V_GPIO_PCR_RXINV_YES 0x01
178
179 //GPIO Input Route IOxAPIC
180 #define B_GPIO_PCR_RX_APIC_ROUTE BIT20
181 #define N_GPIO_PCR_RX_APIC_ROUTE 20
182 #define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00
183 #define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01
184
185 //GPIO Input Route SCI
186 #define B_GPIO_PCR_RX_SCI_ROUTE BIT19
187 #define N_GPIO_PCR_RX_SCI_ROUTE 19
188 #define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00
189 #define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01
190
191 //GPIO Input Route SMI
192 #define B_GPIO_PCR_RX_SMI_ROUTE BIT18
193 #define N_GPIO_PCR_RX_SMI_ROUTE 18
194 #define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00
195 #define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01
196
197 //GPIO Input Route NMI
198 #define B_GPIO_PCR_RX_NMI_ROUTE BIT17
199 #define N_GPIO_PCR_RX_NMI_ROUTE 17
200 #define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00
201 #define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01
202
203 //Virtual GPIO interrupts routing
204 #define B_VGPIO_PCR_INT_TYPE (BIT26 | BIT25 | BIT24)
205 #define N_VGPIO_PCR_INT_TYPE 24
206 #define V_VGPIO_PCR_INT_TYPE_IRQ 0x0
207 #define V_VGPIO_PCR_INT_TYPE_SCI 0x1
208 #define V_VGPIO_PCR_INT_TYPE_SMI 0x2
209 #define V_VGPIO_PCR_INT_TYPE_NMI 0x4
210 #define V_VGPIO_PCR_INT_TYPE_DIS 0x7
211
212 //GPIO Pad Mode
213 #define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
214 #define N_GPIO_PCR_PAD_MODE 10
215 #define V_GPIO_PCR_PAD_MODE_GPIO 0
216 #define V_GPIO_PCR_PAD_MODE_NAT_1 1
217 #define V_GPIO_PCR_PAD_MODE_NAT_2 2
218 #define V_GPIO_PCR_PAD_MODE_NAT_3 3
219 #define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only
220
221 //GPIO RX Disable
222 #define B_GPIO_PCR_RXDIS BIT9
223 #define N_GPIO_PCR_RXDIS 9
224 #define V_GPIO_PCR_RXDIS_EN 0x00
225 #define V_GPIO_PCR_RXDIS_DIS 0x01
226 //GPIO RX Disable for Virtual GPIO
227 #define B_VGPIO_PCR_RXDIS BIT4
228 #define N_VGPIO_PCR_RXDIS 4
229
230 //GPIO TX Disable
231 #define B_GPIO_PCR_TXDIS BIT8
232 #define N_GPIO_PCR_TXDIS 8
233 #define V_GPIO_PCR_TXDIS_EN 0x00
234 #define V_GPIO_PCR_TXDIS_DIS 0x01
235 //GPIO TX Disable for Virtual GPIO
236 #define B_VGPIO_PCR_TXDIS BIT3
237 #define N_VGPIO_PCR_TXDIS 3
238
239 //GPIO RX State
240 #define B_GPIO_PCR_RX_STATE BIT1
241 #define N_GPIO_PCR_RX_STATE 1
242 #define V_GPIO_PCR_RX_STATE_LOW 0x00
243 #define V_GPIO_PCR_RX_STATE_HIGH 0x01
244 //GPIO RX State for Virtual GPIO
245 #define B_VGPIO_PCR_RX_STATE BIT2
246 #define N_VGPIO_PCR_RX_STATE 2
247
248 //GPIO TX State
249 #define B_GPIO_PCR_TX_STATE BIT0
250 #define N_GPIO_PCR_TX_STATE 0
251 #define V_GPIO_PCR_TX_STATE_LOW 0x00
252 #define V_GPIO_PCR_TX_STATE_HIGH 0x01
253 //GPIO TX State for Virtual GPIO
254 #define B_VGPIO_PCR_TX_STATE BIT1
255 #define N_VGPIO_PCR_TX_STATE 1
256
257 // Virtual GPIO Pad Direction
258 #define B_VGPIO_PCR_DIR BIT0
259 #define N_VGPIO_PCR_DIR 0
260
261 // Virtual GPIO Chipselect
262 #define B_VGPIO_PCR_OUT_CS (BIT6 | BIT5)
263 #define N_VGPIO_PCR_OUT_CS 5
264 #define V_VGPIO_PCR_OUT_CS_0 0
265 #define V_VGPIO_PCR_OUT_CS_1 1
266
267 //
268 // Pad Configuration Register DW1
269 //
270
271 //Padtol
272 #define B_GPIO_PCR_PADTOL BIT25
273 #define N_GPIO_PCR_PADTOL 25
274 #define V_GPIO_PCR_PADTOL_NONE 0x00
275 #define V_GPIO_PCR_PADTOL_CLEAR 0x00
276 #define V_GPIO_PCR_PADTOL_SET 0x01
277
278 #define B_GPIO_PCR_STANDBY_STATE (BIT17 | BIT16 | BIT15 | BIT14)
279 #define N_GPIO_PCR_STANDBY_STATE 14
280 #define V_GPIO_PCR_STANDBY_STATE_LATCH_LAST_VALUE 0x00
281 #define V_GPIO_PCR_STANDBY_STATE_TX0_RX0_RXDIS 0x01
282 #define V_GPIO_PCR_STANDBY_STATE_TX0_RX1_RXDIS 0x02
283 #define V_GPIO_PCR_STANDBY_STATE_TX1_RX0_RXDIS 0x03
284 #define V_GPIO_PCR_STANDBY_STATE_TX1_RX1_RXDIS 0x04
285 #define V_GPIO_PCR_STANDBY_STATE_TX0_RXEN 0x05
286 #define V_GPIO_PCR_STANDBY_STATE_TX1_RXEN 0x06
287 #define V_GPIO_PCR_STANDBY_STATE_HIZ_RX0 0x07
288 #define V_GPIO_PCR_STANDBY_STATE_HIZ_RX1 0x08
289 #define V_GPIO_PCR_STANDBY_STATE_TXDIS_RXDIS 0x09
290 #define V_GPIO_PCR_STANDBY_STATE_MASKED 0x0F
291
292 #define B_GPIO_PCR_STANDBY_TERM (BIT9 | BIT8)
293 #define N_GPIO_PCR_STANDBY_TERM 8
294 #define V_GPIO_PCR_STANDBY_TERM_SAME_AS_TERM 0x00
295 #define V_GPIO_PCR_STANDBY_TERM_PUDIS_PDDIS 0x01
296 #define V_GPIO_PCR_STANDBY_TERM_PUDIS_PDEN 0x02
297 #define V_GPIO_PCR_STANDBY_TERM_PUEN_PDDIS 0x03
298
299 //Termination
300 #define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
301 #define N_GPIO_PCR_TERM 10
302 #define V_GPIO_PCR_TERM_WPD_NONE 0x00
303 #define V_GPIO_PCR_TERM_WPD_5K 0x02
304 #define V_GPIO_PCR_TERM_WPD_20K 0x04
305 #define V_GPIO_PCR_TERM_WPU_NONE 0x08
306 #define V_GPIO_PCR_TERM_WPU_1K 0x09
307 #define V_GPIO_PCR_TERM_WPU_2K 0x0B
308 #define V_GPIO_PCR_TERM_WPU_5K 0x0A
309 #define V_GPIO_PCR_TERM_WPU_20K 0x0C
310 #define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D
311 #define V_GPIO_PCR_TERM_NATIVE 0x0F
312
313 //Interrupt number
314 #define B_GPIO_PCR_INTSEL 0x7F
315 #define N_GPIO_PCR_INTSEL 0
316 //Interrupt number
317 #define N_VGPIO_PCR_INTSEL 14
318
319 //
320 // Pad Configuration Register DW2
321 //
322
323 // VCCIOSEL
324 #define B_GPIO_PCR_VCCIOSEL BIT8
325 #define N_GPIO_PCR_VCCIOSEL 8
326
327 //Debounce
328 #define B_GPIO_PCR_DEBOUNCE (BIT4 | BIT3 | BIT2 | BIT1)
329 #define N_GPIO_PCR_DEBOUNCE 1
330
331 //Debounce Enable
332 #define B_GPIO_PCR_DEBEN BIT0
333 #define N_GPIO_PCR_DEBEN 0
334
335 //
336 // Ownership
337 //
338 #define V_GPIO_PCR_OWN_GPIO 0x01
339 #define V_GPIO_PCR_OWN_ACPI 0x00
340
341 //
342 // GPE
343 //
344 #define V_GPIO_PCR_GPE_EN 0x01
345 #define V_GPIO_PCR_GPE_DIS 0x00
346 //
347 // SMI
348 //
349 #define V_GPIO_PCR_SMI_EN 0x01
350 #define V_GPIO_PCR_SMI_DIS 0x00
351 //
352 // NMI
353 //
354 #define V_GPIO_PCR_NMI_EN 0x01
355 #define V_GPIO_PCR_NMI_DIS 0x00
356
357 //
358 // GPIO native features pins data
359 //
360 #define PCH_GPIO_HDA_LINK_NUMBER_OF_PINS 6
361 #define PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS 2
362 #define PCH_GPIO_HDA_SSP_NUMBER_OF_PINS 4
363 #define PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS 2
364 #define PCH_GPIO_SMBUS_NUMBER_OF_PINS 2
365 #define PCH_GPIO_CPU_GP_NUMBER_OF_PINS 4
366 #define PCH_GPIO_EDP_NUMBER_OF_PINS 4
367 #define PCH_GPIO_DDSP_HPD_NUMBER_OF_PINS 4
368 #define PCH_GPIO_DDP_NUMBER_OF_INTERFACES 4
369 #define PCH_GPIO_DDP_NUMBER_OF_PINS 2
370 #define PCH_GPIO_CNVI_UART_NUMBER_OF_PINS 4
371 #define PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS 4
372 #define PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS 4
373
374 //
375 // GSX
376 //
377 #define B_GPIO_PCH_GPIO_GSX_PCR_C0CAP_DW0_NOUT (BIT9 | BIT8 | BIT7 | BIT6 | BIT5)
378 #define B_GPIO_PCH_GPIO_GSX_PCR_C0CAP_DW0_NIN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
379 #define N_GPIO_PCH_GPIO_GSX_PCR_C0CAP_DW0_NOUT 0x5
380 #define B_GPIO_PCH_GPIO_GSX_PCR_C0CMD_BUSY BIT1
381 #define B_GPIO_PCH_GPIO_GSX_PCR_C0CMD_START BIT0
382
383 ///
384 /// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
385 /// Below defines are to be used internally by PCH SMI dispatcher only
386 ///
387 #define PCH_GPIO_NUM_SUPPORTED_GPIS 512
388 #define S_GPIO_PCR_GP_SMI_EN 4
389 #define S_GPIO_PCR_GP_SMI_STS 4
390
391 ///
392 /// Groups mapped to 2-tier General Purpose Event will all be under
393 /// one Primary GPE_111 (0x6F)
394 ///
395 #define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F
396
397 #endif // _GPIO_REGS_H_
398
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegsVer2.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
GpioRegsVer2.h File Reference

Register names for VER2 GPIO. More...

Go to the source code of this file.

Detailed Description

Register names for VER2 GPIO.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioRegsVer2.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegsVer2.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
GpioRegsVer2.h
Go to the documentation of this file.
1 /** @file
2 Register names for VER2 GPIO
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2017 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _GPIO_REGS_VER2_H_
65 #define _GPIO_REGS_VER2_H_
66
67 //
68 // PCH-LP GPIO
69 //
70 #define GPIO_VER2_PCH_LP_GPIO_GROUP_MAX 18
71
72 #define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
73 #define GPIO_VER2_PCH_LP_GPIO_GPP_T_PAD_MAX 16
74 #define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
75 #define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
76 #define GPIO_VER2_PCH_LP_GPIO_SPI_PAD_MAX 9
77 #define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
78 #define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
79 #define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
80 #define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
81 #define GPIO_VER2_PCH_LP_GPIO_GPP_U_PAD_MAX 24
82 #define GPIO_VER2_PCH_LP_GPIO_VGPIO_PAD_MAX 29
83 #define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
84 #define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
85 #define GPIO_VER2_PCH_LP_GPIO_HVCMOS_PAD_MAX 6
86 #define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
87 #define GPIO_VER2_PCH_LP_GPIO_JTAG_PAD_MAX 10
88 #define GPIO_VER2_PCH_LP_GPIO_CPU_PAD_MAX 15
89 #define GPIO_VER2_PCH_LP_GPIO_VGPIO_3_PAD_MAX 91
90 /*
91 Following group is used only for PCH_N
92 Other GPIO Group Defines are same
93 hence change in naming convention only for GPP_I
94 */
95 #define GPIO_VER2_PCH_N_GPIO_GPP_I_PAD_MAX 20
96
97 //
98 // PCH-H GPIO
99 //
100 #define GPIO_VER2_PCH_H_GPIO_GROUP_MAX 19
101
102 #define GPIO_VER2_PCH_H_GPIO_GPP_A_PAD_MAX 25
103 #define GPIO_VER2_PCH_H_GPIO_GPP_R_PAD_MAX 20
104 #define GPIO_VER2_PCH_H_GPIO_GPP_B_PAD_MAX 24
105 #define GPIO_VER2_PCH_H_GPIO_VGPIO_0_PAD_MAX 8 // vGPIO_USB_0
106 #define GPIO_VER2_PCH_H_GPIO_GPP_D_PAD_MAX 24
107 #define GPIO_VER2_PCH_H_GPIO_GPP_C_PAD_MAX 24
108 #define GPIO_VER2_PCH_H_GPIO_GPP_S_PAD_MAX 8
109 #define GPIO_VER2_PCH_H_GPIO_GPP_G_PAD_MAX 16
110 #define GPIO_VER2_PCH_H_GPIO_VGPIO_PAD_MAX 27
111 #define GPIO_VER2_PCH_H_GPIO_GPD_PAD_MAX 13
112 #define GPIO_VER2_PCH_H_GPIO_GPP_E_PAD_MAX 13
113 #define GPIO_VER2_PCH_H_GPIO_GPP_F_PAD_MAX 24
114 #define GPIO_VER2_PCH_H_GPIO_VGPIO_3_PAD_MAX 84 // vGPIO_PCIE
115 #define GPIO_VER2_PCH_H_GPIO_GPP_H_PAD_MAX 24
116 #define GPIO_VER2_PCH_H_GPIO_GPP_J_PAD_MAX 10
117 #define GPIO_VER2_PCH_H_GPIO_GPP_K_PAD_MAX 12
118 #define GPIO_VER2_PCH_H_GPIO_GPP_I_PAD_MAX 15
119 #define GPIO_VER2_PCH_H_GPIO_JTAG_PAD_MAX 9
120 #define GPIO_VER2_PCH_H_GPIO_CPU_PAD_MAX 14
121
122 //
123 // PCH-LP GPIO registers
124 //
125 //
126 // GPIO Community Common Private Configuration Registers
127 //
128 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x0
129 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_T 0x1
130 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x2
131 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_R 0x3
132 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_SPI 0xF
133 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPD 0x4
134 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_S 0x5
135 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_H 0x6
136 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x7
137 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_U 0x8
138 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_VGPIO 0x9
139 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_F 0xA
140 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_C 0xB
141 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_HVCMOS 0xF
142 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_E 0xC
143 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_JTAG 0xF
144 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_CPU 0xF
145 #define V_GPIO_VER2_PCH_LP_GPIO_PCR_MISCCFG_GPE0_VGPIO_3 0xF
146 //
147 // GPIO Community 0 Private Configuration Registers
148 //
149 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
150 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_PAD_OWN 0x30
151 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
152
153 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
154 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
155 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_PADCFGLOCK 0x88
156 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_PADCFGLOCKTX 0x8C
157 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
158 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
159
160 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
161 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_HOSTSW_OWN 0xB4
162 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
163
164 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
165 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_GPI_IS 0x0104
166 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
167
168 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
169 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_GPI_IE 0x0124
170 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
171
172 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
173 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_GPI_GPE_STS 0x0144
174 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
175
176 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
177 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_GPI_GPE_EN 0x0164
178 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
179
180 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
181 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_SMI_STS 0x0184 // Not supported setting for this group
182 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_SMI_STS 0x0188 // Not supported setting for this group
183
184 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
185 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_SMI_EN 0x01A4 // Not supported setting for this group
186 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_SMI_EN 0x01A8 // Not supported setting for this group
187
188 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
189 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_NMI_STS 0x01C4 // Not supported setting for this group
190 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_NMI_STS 0x01C8 // Not supported setting for this group
191
192 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
193 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_NMI_EN 0x01E4 // Not supported setting for this group
194 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_NMI_EN 0x01E8 // Not supported setting for this group
195
196 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
197 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_T_PADCFG_OFFSET 0x8A0
198 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
199
200 //
201 // GPIO Community 1 Private Configuration Registers
202 //
203 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
204 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
205 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
206 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_PAD_OWN 0x3C
207 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_PAD_OWN 0x48
208
209 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
210 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
211 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
212 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
213 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
214 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
215 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_PADCFGLOCK 0x98
216 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_PADCFGLOCKTX 0x9C
217 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_PADCFGLOCK 0xA0
218 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_PADCFGLOCKTX 0xA4
219
220 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
221 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
222 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
223 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_HOSTSW_OWN 0xBC
224 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_HOSTSW_OWN 0xC0
225
226 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
227 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
228 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
229 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_GPI_IS 0x010C
230 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_GPI_IS 0x0110
231
232 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
233 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
234 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
235 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_GPI_IE 0x012C
236 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_GPI_IE 0x0130
237
238 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
239 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
240 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
241 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_GPI_GPE_STS 0x014C
242 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_STS 0x0150
243
244 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
245 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
246 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
247 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_GPI_GPE_EN 0x016C
248 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_EN 0x0170
249
250 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_SMI_STS 0x0180 // Not supported setting for this group
251 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_SMI_STS 0x0184 // Not supported setting for this group
252 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
253 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_SMI_STS 0x018C // Not supported setting for this group
254 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_SMI_STS 0x0190 // Not supported setting for this group
255
256 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_SMI_EN 0x01A0 // Not supported setting for this group
257 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_SMI_EN 0x01A4 // Not supported setting for this group
258 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
259 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_SMI_EN 0x01AC // Not supported setting for this group
260 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_SMI_EN 0x01B0 // Not supported setting for this group
261
262 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_NMI_STS 0x01C0 // Not supported setting for this group
263 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_NMI_STS 0x01C4 // Not supported setting for this group
264 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
265 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_NMI_STS 0x01CC // Not supported setting for this group
266 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_NMI_STS 0x01D0 // Not supported setting for this group
267
268 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_NMI_EN 0x01E0 // Not supported setting for this group
269 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_NMI_EN 0x01E4 // Not supported setting for this group
270 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
271 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_NMI_EN 0x01EC // Not supported setting for this group
272 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_NMI_EN 0x01F0 // Not supported setting for this group
273
274 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
275 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
276 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
277 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_U_PADCFG_OFFSET 0xA50
278 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xBD0
279 //
280 // GPIO Community 2 Private Configuration Registers
281 //
282 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
283
284 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
285 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
286
287 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
288
289 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
290 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
291
292 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
293 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
294
295 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_SMI_STS 0x0180 // Not supported setting for this group
296 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_SMI_EN 0x01A0 // Not supported setting for this group
297
298 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_NMI_STS 0x01C0 // Not supported setting for this group
299 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_NMI_EN 0x01E0 // Not supported setting for this group
300
301 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
302
303 //
304 // GPIO Community 3 Private Configuration Registers
305 //
306 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_PAD_OWN 0x20
307 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_PAD_OWN 0x28
308
309 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_PADCFGLOCK 0x80
310 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_PADCFGLOCKTX 0x84
311 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_PADCFGLOCK 0x88
312 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_PADCFGLOCKTX 0x8C
313
314 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_HOSTSW_OWN 0xB0
315 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_HOSTSW_OWN 0xB4
316
317 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_GPI_IS 0x0100 // Not supported setting for this group
318 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_GPI_IS 0x0104 // Not supported setting for this group
319
320 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_GPI_IE 0x0120 // Not supported setting for this group
321 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_GPI_IE 0x0124 // Not supported setting for this group
322
323 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_GPI_GPE_STS 0x0140 // Not supported setting for this group
324 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_GPI_GPE_STS 0x0144 // Not supported setting for this group
325
326 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_GPI_GPE_EN 0x0160 // Not supported setting for this group
327 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_GPI_GPE_EN 0x0164 // Not supported setting for this group
328
329 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_SMI_STS 0x0180 // Not supported setting for this group
330 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_SMI_STS 0x0184 // Not supported setting for this group
331
332 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_SMI_EN 0x01A0 // Not supported setting for this group
333 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_SMI_EN 0x01A4 // Not supported setting for this group
334
335 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_NMI_STS 0x01C0 // Not supported setting for this group
336 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_NMI_STS 0x01C4 // Not supported setting for this group
337
338 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_NMI_EN 0x01E0 // Not supported setting for this group
339 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_NMI_EN 0x01E4 // Not supported setting for this group
340
341 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_CPU_PADCFG_OFFSET 0x700
342 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_VGPIO_3_PADCFG_OFFSET 0x7F0
343
344 //
345 // GPIO Community 4 Private Configuration Registers
346 //
347 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
348 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
349 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_PAD_OWN 0x3C
350 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
351 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_PAD_OWN 0x50
352
353 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
354 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
355 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
356 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
357 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_PADCFGLOCK 0x90
358 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_PADCFGLOCKTX 0x94
359 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
360 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
361 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCK 0xA0
362 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCKTX 0xA4
363
364 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
365 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
366 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_HOSTSW_OWN 0xB8
367 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
368 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_HOSTSW_OWN 0xC0
369
370 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
371 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
372 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_GPI_IS 0x0108 // Not supported setting for this group
373 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
374 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_GPI_IS 0x0110 // Not supported setting for this group
375
376 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
377 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
378 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_GPI_IE 0x0128 // Not supported setting for this group
379 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
380 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_GPI_IE 0x0130 // Not supported setting for this group
381
382 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
383 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
384 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_GPI_GPE_STS 0x0148 // Not supported setting for this group
385 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
386 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_STS 0x0150 // Not supported setting for this group
387
388 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
389 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
390 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_GPI_GPE_EN 0x0168 // Not supported setting for this group
391 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
392 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_EN 0x0170 // Not supported setting for this group
393
394 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
395 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_SMI_STS 0x0184 // Not supported setting for this group
396 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_SMI_STS 0x0188 // Not supported setting for this group
397 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
398 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_SMI_STS 0x0190 // Not supported setting for this group
399
400 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
401 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_SMI_EN 0x01A4 // Not supported setting for this group
402 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_SMI_EN 0x01A8 // Not supported setting for this group
403 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
404 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_SMI_EN 0x01B0 // Not supported setting for this group
405
406 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
407 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_NMI_STS 0x01C4 // Not supported setting for this group
408 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_NMI_STS 0x01C8 // Not supported setting for this group
409 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
410 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_NMI_STS 0x01D0 // Not supported setting for this group
411
412 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
413 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_NMI_EN 0x01E4 // Not supported setting for this group
414 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_NMI_EN 0x01E8 // Not supported setting for this group
415 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
416 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_NMI_EN 0x01F0 // Not supported setting for this group
417
418 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
419 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
420 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_HVCMOS_PADCFG_OFFSET 0xA10
421 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
422 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_JTAG_PADCFG_OFFSET 0xC00
423
424 //
425 // GPIO Community 5 Private Configuration Registers
426 //
427 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
428 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_PAD_OWN 0x24
429
430 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
431 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
432 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_PADCFGLOCK 0x88
433 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_PADCFGLOCKTX 0x8C
434
435 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
436 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_HOSTSW_OWN 0xB4
437
438 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
439 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_GPI_IS 0x0104 // Not supported setting for this group
440
441 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
442 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_GPI_IE 0x0124 // Not supported setting for this group
443
444 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
445 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_GPI_GPE_STS 0x0144 // Not supported setting for this group
446
447 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
448 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_GPI_GPE_EN 0x0164 // Not supported setting for this group
449
450 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_SMI_STS 0x0180 // Not supported setting for this group
451 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_SMI_STS 0x0184 // Not supported setting for this group
452
453 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_SMI_EN 0x01A0 // Not supported setting for this group
454 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_SMI_EN 0x01A4 // Not supported setting for this group
455
456 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_NMI_STS 0x01C0 // Not supported setting for this group
457 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_NMI_STS 0x01C4 // Not supported setting for this group
458
459 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_NMI_EN 0x01E0 // Not supported setting for this group
460 //#define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_NMI_EN 0x01E4 // Not supported setting for this group
461
462 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
463 #define R_GPIO_VER2_PCH_LP_GPIO_PCR_SPI_PADCFG_OFFSET 0x780
464
465 //
466 // PCH-H GPIO registers
467 //
468 //
469 // GPIO Community Common Private Configuration Registers
470 //
471 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPD 0x0
472 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x1
473 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_R 0x2
474 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x3
475 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO_0 0xF // GPE not supported by this group
476 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x4
477 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_C 0x5
478 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_S 0x6
479 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_G 0x7
480 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO 0x8
481 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_E 0x9
482 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_F 0xA
483 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_H 0xB
484 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_J 0xC
485 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_K 0xD
486 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_I 0xE
487 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO_0 0xF // GPE not supported by this group
488 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO_3 0xF // GPE not supported by this group
489 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_JTAG 0xF // GPE not supported by this group
490 #define V_GPIO_VER2_PCH_H_GPIO_PCR_MISCCFG_GPE0_CPU 0xF // GPE not supported by this group
491
492 //
493 // GPIO Community 0 Private Configuration Registers
494 //
495 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_PAD_OWN 0x00 // Not supported setting for this group
496 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_PAD_OWN 0x20
497 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_PAD_OWN 0x30
498 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_PAD_OWN 0x3C
499 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_PAD_OWN 0x4C // vGPIO_USB_0
500
501 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_PADCFGLOCK 0x00 // Not supported setting for this group
502 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_PADCFGLOCKTX 0x00 // Not supported setting for this group
503 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
504 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
505 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_PADCFGLOCK 0x98
506 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x9C
507 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCK 0xA0
508 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCKTX 0xA4
509 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCK 0xA8 // vGPIO_USB_0
510 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0xAC // vGPIO_USB_0
511
512 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_HOSTSW_OWN 0x00 // Not supported setting for this group
513 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_HOSTSW_OWN 0xC0
514 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_HOSTSW_OWN 0xC4
515 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_HOSTSW_OWN 0xC8
516 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_HOSTSW_OWN 0xCC
517
518 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_GPI_IS 0x00 // Not supported setting for this group
519 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_GPI_IS 0x0100
520 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_GPI_IS 0x0104
521 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_GPI_IS 0x0108
522 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_GPI_IS 0x010C
523
524 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_GPI_IE 0x00 // Not supported setting for this group
525 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_GPI_IE 0x0120
526 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_GPI_IE 0x0124
527 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_GPI_IE 0x0128
528 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_GPI_IE 0x012C
529
530 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_GPI_GPE_STS 0x00 // Not supported setting for this group
531 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0140
532 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0144
533 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0148
534 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_GPI_GPE_STS 0x014C
535
536 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_GPI_GPE_EN 0x00 // Not supported setting for this group
537 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0160
538 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0164
539 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0168
540 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_GPI_GPE_EN 0x016C
541
542 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_SMI_STS 0x00 // Not supported setting for this group
543 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_SMI_STS 0x0180
544 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_SMI_STS 0x0184
545 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_SMI_STS 0x0188
546 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_SMI_STS 0x018C // Not supported setting for this group
547
548 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_SMI_EN 0x00 // Not supported setting for this group
549 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_SMI_EN 0x01A0
550 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_SMI_EN 0x01A4
551 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_SMI_EN 0x01A8
552 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_SMI_EN 0x01AC
553
554 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_NMI_STS 0x00 // Not supported setting for this group
555 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_NMI_STS 0x01C0
556 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_NMI_STS 0x01C4
557 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_NMI_STS 0x01C8
558 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_NMI_STS 0x01CC
559
560 //#define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_NMI_EN 0x00 // Not supported setting for this group
561 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_NMI_EN 0x01E0
562 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_NMI_EN 0x01E4
563 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_NMI_EN 0x01E8
564 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_NMI_EN 0x01EC
565
566 #define R_GPIO_VER2_PCH_H_GPIO_PCR_SPI_PADCFG_OFFSET 0x600
567 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x680
568 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x790
569 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x8D0
570 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_0_PADCFG_OFFSET 0xA70 // vGPIO_USB_0
571
572 //
573 // GPIO Community 1 Private Configuration Registers
574 //
575 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_PAD_OWN 0x20
576 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_PAD_OWN 0x30
577 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_PAD_OWN 0x3C
578 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_PAD_OWN 0x40
579 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_PAD_OWN 0x4C
580
581 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
582 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
583 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCK 0x98
584 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x9C
585 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_PADCFGLOCK 0xA0
586 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_PADCFGLOCKTX 0xA4
587 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCK 0xA8
588 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCKTX 0xAC
589 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_PADCFGLOCK 0xB0
590 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_PADCFGLOCKTX 0xB4
591
592 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_HOSTSW_OWN 0xC0
593 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_HOSTSW_OWN 0xC4
594 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_HOSTSW_OWN 0xC8
595 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_HOSTSW_OWN 0xCC
596 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_HOSTSW_OWN 0xD0
597
598 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_GPI_IS 0x0100
599 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_GPI_IS 0x0104
600 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_GPI_IS 0x0108
601 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_GPI_IS 0x010C
602 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_GPI_IS 0x0110
603
604 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_GPI_IE 0x0120
605 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_GPI_IE 0x0124
606 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_GPI_IE 0x0128
607 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_GPI_IE 0x012C
608 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_GPI_IE 0x0130
609
610 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0140
611 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0144
612 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0148
613 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_STS 0x014C
614 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_STS 0x0150
615
616 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0160
617 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0164
618 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0168
619 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_EN 0x016C
620 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_EN 0x0170
621
622 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_SMI_STS 0x0180
623 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_SMI_STS 0x0184
624 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_SMI_STS 0x0188
625 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_SMI_STS 0x018C
626 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_SMI_STS 0x0190
627
628 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_SMI_EN 0x01A0
629 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_SMI_EN 0x01A4
630 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_SMI_EN 0x01A8
631 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_SMI_EN 0x01AC
632 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_SMI_EN 0x01B0
633
634 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_NMI_STS 0x01C0
635 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_NMI_STS 0x01C4
636 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_NMI_STS 0x01C8
637 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_NMI_STS 0x01CC
638 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_NMI_STS 0x01D0
639
640 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_NMI_EN 0x01E0
641 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_NMI_EN 0x01E4
642 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_NMI_EN 0x01E8
643 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_NMI_EN 0x01EC
644 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_NMI_EN 0x01F0
645
646 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x600
647 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x7A0
648 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x920
649 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x9A0
650 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xAB0
651
652 //
653 // GPIO Community 2 Private Configuration Registers
654 //
655 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_PAD_OWN 0x20
656
657 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_PADCFGLOCK 0x90
658 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_PADCFGLOCKTX 0x94
659
660 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_HOSTSW_OWN 0xC0
661
662 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_GPI_IS 0x0100
663 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_GPI_IE 0x0120
664
665 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
666 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
667
668 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_SMI_STS 0x0180
669 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_SMI_EN 0x01A0
670
671 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_NMI_STS 0x01C0
672 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_NMI_EN 0x01E0
673
674 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPD_PADCFG_OFFSET 0x600
675
676 //
677 // GPIO Community 3 Private Configuration Registers
678 //
679 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_PAD_OWN 0x20
680 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_PAD_OWN 0x28
681 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_PAD_OWN 0x34
682
683 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCK 0x90
684 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x94
685 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCK 0x98
686 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x9C
687 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_PADCFGLOCK 0xA0
688 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_PADCFGLOCKTX 0xA4
689
690 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_HOSTSW_OWN 0xC0
691 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_HOSTSW_OWN 0xC4
692 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_HOSTSW_OWN 0xC8
693
694 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_GPI_IS 0x0100
695 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_GPI_IS 0x0104
696 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_GPI_IS 0x0108
697
698 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_GPI_IE 0x0120
699 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_GPI_IE 0x0124
700 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_GPI_IE 0x0128
701
702 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0140
703 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
704 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_GPI_GPE_STS 0x0148
705
706 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0160
707 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
708 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_GPI_GPE_EN 0x0168
709
710 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_SMI_STS 0x0180
711 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_SMI_STS 0x0184
712 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_SMI_STS 0x0188
713
714 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_SMI_EN 0x01A0
715 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_SMI_EN 0x01A4
716 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_SMI_EN 0x01A8
717
718 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_NMI_STS 0x01C0
719 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_NMI_STS 0x01C4
720 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_NMI_STS 0x01C8
721
722 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_NMI_EN 0x01E0
723 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_NMI_EN 0x01E4
724 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_NMI_EN 0x01E8
725
726 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x600
727 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x6D0
728 #define R_GPIO_VER2_PCH_H_GPIO_PCR_VGPIO_3_PADCFG_OFFSET 0x850
729
730 //
731 // GPIO Community 4 Private Configuration Registers
732 //
733 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_PAD_OWN 0x20
734 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_PAD_OWN 0x2C
735 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_PAD_OWN 0x34
736
737 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCK 0x90
738 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x94
739 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCK 0x98
740 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCKTX 0x9C
741 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCK 0xA0
742 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCKTX 0xA4
743
744 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_HOSTSW_OWN 0xC0
745 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_HOSTSW_OWN 0xC4
746 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_HOSTSW_OWN 0xC8
747
748 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_GPI_IS 0x0100
749 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_GPI_IS 0x0104
750 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_GPI_IS 0x0108
751
752 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_GPI_IE 0x0120
753 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_GPI_IE 0x0124
754 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_GPI_IE 0x0128
755
756 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0140
757 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_STS 0x0144
758 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_STS 0x0148
759
760 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0160
761 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_EN 0x0164
762 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_EN 0x0168
763
764 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_SMI_STS 0x0180
765 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_SMI_STS 0x0184
766 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_SMI_STS 0x0188
767
768 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_SMI_EN 0x01A0
769 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_SMI_EN 0x01A4
770 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_SMI_EN 0x01A8
771
772 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_NMI_STS 0x01C0
773 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_NMI_STS 0x01C4
774 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_NMI_STS 0x01C8
775
776 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_NMI_EN 0x01E0
777 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_NMI_EN 0x01E4
778 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_NMI_EN 0x01E8
779
780 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x600
781 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_J_PADCFG_OFFSET 0x780
782 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_K_PADCFG_OFFSET 0x820
783
784 //
785 // GPIO Community 5 Private Configuration Registers
786 //
787 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_PAD_OWN 0x20
788 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_PAD_OWN 0x28
789 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_PAD_OWN 0x30
790
791 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCK 0x90
792 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCKTX 0x94
793 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_PADCFGLOCK 0x98
794 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_PADCFGLOCKTX 0x9C
795 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_PADCFGLOCK 0xA0
796 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_PADCFGLOCKTX 0xA4
797
798 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_HOSTSW_OWN 0xC0
799 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_HOSTSW_OWN 0xC4
800 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_HOSTSW_OWN 0xC8
801
802 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_GPI_IS 0x0100
803 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_GPI_IS 0x0104
804 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_GPI_IS 0x0108
805
806 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_GPI_IE 0x0120
807 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_GPI_IE 0x0124
808 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_GPI_IE 0x0128
809
810 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_STS 0x0140
811 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_GPI_GPE_STS 0x0144
812 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_GPI_GPE_STS 0x0148
813
814 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_EN 0x0160
815 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_GPI_GPE_EN 0x0164
816 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_GPI_GPE_EN 0x0168
817
818 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_SMI_STS 0x0180
819 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_SMI_STS 0x0184
820 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_SMI_STS 0x0188
821
822 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_SMI_EN 0x01A0
823 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_SMI_EN 0x01A4
824 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_SMI_EN 0x01A8
825
826 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_NMI_STS 0x01C0
827 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_NMI_STS 0x01C4
828 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_NMI_STS 0x01C8
829
830 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_NMI_EN 0x01E0
831 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_NMI_EN 0x01E4
832 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_NMI_EN 0x01E8
833
834 #define R_GPIO_VER2_PCH_H_GPIO_PCR_GPP_I_PADCFG_OFFSET 0x600
835 #define R_GPIO_VER2_PCH_H_GPIO_PCR_JTAG_PADCFG_OFFSET 0x6F0
836 #define R_GPIO_VER2_PCH_H_GPIO_PCR_CPU_PADCFG_OFFSET 0x780
837
838 #endif // _GPIO_REGS_VER2_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegsVer4.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
GpioRegsVer4.h File Reference

Register names for VER4 GPIO. More...

Go to the source code of this file.

Detailed Description

Register names for VER4 GPIO.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GpioRegsVer4.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GpioRegsVer4.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
GpioRegsVer4.h
Go to the documentation of this file.
1 /** @file
2 Register names for VER4 GPIO
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _GPIO_REGS_VER4_H_
65 #define _GPIO_REGS_VER4_H_
66
67 //
68 // PCH-S GPIO
69 //
70 #define GPIO_VER4_PCH_S_GPIO_GROUP_MAX 19
71
72 #define GPIO_VER4_PCH_S_GPIO_GPP_I_PAD_MAX 25
73 #define GPIO_VER4_PCH_S_GPIO_GPP_R_PAD_MAX 23
74 #define GPIO_VER4_PCH_S_GPIO_GPP_J_PAD_MAX 12
75 #define GPIO_VER4_PCH_S_GPIO_VGPIO_PAD_MAX 27
76 #define GPIO_VER4_PCH_S_GPIO_VGPIO_0_PAD_MAX 8 // vGPIO_USB_0
77 #define GPIO_VER4_PCH_S_GPIO_GPP_B_PAD_MAX 24
78 #define GPIO_VER4_PCH_S_GPIO_GPP_G_PAD_MAX 8
79 #define GPIO_VER4_PCH_S_GPIO_GPP_H_PAD_MAX 24
80 #define GPIO_VER4_PCH_S_GPIO_GPD_PAD_MAX 17
81 #define GPIO_VER4_PCH_S_GPIO_SPI_PAD_MAX 9
82 #define GPIO_VER4_PCH_S_GPIO_GPP_A_PAD_MAX 16
83 #define GPIO_VER4_PCH_S_GPIO_GPP_C_PAD_MAX 24
84 #define GPIO_VER4_PCH_S_GPIO_VGPIO_3_PAD_MAX 84 // vGPIO_PCIE
85 #define GPIO_VER4_PCH_S_GPIO_GPP_S_PAD_MAX 8
86 #define GPIO_VER4_PCH_S_GPIO_GPP_E_PAD_MAX 23
87 #define GPIO_VER4_PCH_S_GPIO_GPP_K_PAD_MAX 15
88 #define GPIO_VER4_PCH_S_GPIO_GPP_F_PAD_MAX 24
89 #define GPIO_VER4_PCH_S_GPIO_GPP_D_PAD_MAX 25
90 #define GPIO_VER4_PCH_S_GPIO_JTAG_PAD_MAX 9
91 #define GPIO_VER4_PCH_S_GPIO_CPU_PAD_MAX 14
92
93 //
94 // PCH-S GPIO registers
95 //
96 //
97 // GPIO Community Common Private Configuration Registers
98 //
99 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_I 0x0
100 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_R 0x1
101 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_J 0x2
102 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_VGPIO 0x3
103 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPD 0x4
104 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x5
105 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_S 0x6
106 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_E 0x7
107 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_K 0x8
108 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_F 0x9
109 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_A 0xA
110 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_C 0xB
111 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_B 0xC
112 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_G 0xD
113 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_GPP_H 0xE
114 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_VGPIO_0 0xF // GPE not supported by this group
115 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_VGPIO_3 0xF // GPE not supported by this group
116 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_JTAG 0xF // GPE not supported by this group
117 #define V_GPIO_VER4_PCH_S_GPIO_PCR_MISCCFG_GPE0_CPU 0xF // GPE not supported by this group
118
119 //
120 // GPIO Community 0 Private Configuration Registers
121 //
122 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_PAD_OWN 0x00A0
123 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_PAD_OWN 0x00B0
124 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_PAD_OWN 0x00BC
125 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_PAD_OWN 0x00C4
126 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_PAD_OWN 0x00D4 // vGPIO_USB_0
127
128 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_PADCFGLOCK 0x0110
129 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_PADCFGLOCKTX 0x0114
130 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_PADCFGLOCK 0x0118
131 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x011C
132 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_PADCFGLOCK 0x0120
133 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_PADCFGLOCKTX 0x0124
134 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_PADCFGLOCK 0x0128
135 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_PADCFGLOCKTX 0x012C
136 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_PADCFGLOCK 0x0130 // vGPIO_USB_0
137 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0x0134 // vGPIO_USB_0
138
139 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_HOSTSW_OWN 0x0150
140 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_HOSTSW_OWN 0x0154
141 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_HOSTSW_OWN 0x0158
142 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_HOSTSW_OWN 0x015C
143 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_HOSTSW_OWN 0x0160
144
145 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_GPI_IS 0x0200
146 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_GPI_IS 0x0204
147 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_GPI_IS 0x0208
148 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_GPI_IS 0x020C
149 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_GPI_IS 0x0210
150
151 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_GPI_IE 0x0220
152 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_GPI_IE 0x0224
153 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_GPI_IE 0x0228
154 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_GPI_IE 0x022C
155 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_GPI_IE 0x0230
156
157 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_GPI_GPE_STS 0x0240
158 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0244
159 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_GPI_GPE_STS 0x0248
160 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_GPI_GPE_STS 0x024C
161 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_GPI_GPE_STS 0x0250
162
163 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_GPI_GPE_EN 0x0260
164 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0264
165 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_GPI_GPE_EN 0x0268
166 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_GPI_GPE_EN 0x026C
167 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_GPI_GPE_EN 0x0270
168
169 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_SMI_STS 0x0280
170 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_SMI_STS 0x0284
171 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_SMI_STS 0x0288
172 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_SMI_STS 0x028C
173 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_SMI_STS 0x0290
174
175 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_SMI_EN 0x02A0
176 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_SMI_EN 0x02A4
177 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_SMI_EN 0x02A8
178 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_SMI_EN 0x02AC
179 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_SMI_EN 0x02B0
180
181 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_NMI_STS 0x02C0
182 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_NMI_STS 0x02C4
183 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_NMI_STS 0x02C8
184 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_NMI_STS 0x02CC
185 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_NMI_STS 0x02D0
186
187 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_NMI_EN 0x02E0
188 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_NMI_EN 0x02E4
189 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_NMI_EN 0x02E8
190 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_NMI_EN 0x02EC
191 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_NMI_EN 0x02F0
192
193 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_I_PADCFG_OFFSET 0x0700
194 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x0890
195 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_J_PADCFG_OFFSET 0x0A00
196 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_PADCFG_OFFSET 0x0AC0
197 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_0_PADCFG_OFFSET 0x0C70
198
199 //
200 // GPIO Community 1 Private Configuration Registers
201 //
202 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_PAD_OWN 0x00A0
203 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_PAD_OWN 0x00AC
204 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_PAD_OWN 0x00B0
205
206 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_PADCFGLOCK 0x0110
207 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x0114
208 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_PADCFGLOCK 0x0118
209 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_PADCFGLOCKTX 0x011C
210 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_PADCFGLOCK 0x0120
211 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x0124
212
213 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_HOSTSW_OWN 0x0150
214 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_HOSTSW_OWN 0x0154
215 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_HOSTSW_OWN 0x0158
216
217 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_GPI_IS 0x0200
218 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_GPI_IS 0x0204
219 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_GPI_IS 0x0208
220
221 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_GPI_IE 0x0220
222 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_GPI_IE 0x0224
223 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_GPI_IE 0x0228
224
225 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0240
226 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_GPI_GPE_STS 0x0244
227 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0248
228
229 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0260
230 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_GPI_GPE_EN 0x0264
231 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0268
232
233 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_SMI_STS 0x0280
234 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_SMI_STS 0x0284
235 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_SMI_STS 0x0288
236
237 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_SMI_EN 0x02A0
238 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_SMI_EN 0x02A4
239 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_SMI_EN 0x02A8
240
241 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_NMI_STS 0x02C0
242 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_NMI_STS 0x02C4
243 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_NMI_STS 0x02C8
244
245 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_NMI_EN 0x02E0
246 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_NMI_EN 0x02E4
247 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_NMI_EN 0x02E8
248
249 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x0700
250 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x0880
251 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x0900
252
253 //
254 // GPIO Community 2 Private Configuration Registers
255 //
256 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_PAD_OWN 0x00A0
257
258 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_PADCFGLOCK 0x0110
259 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_PADCFGLOCKTX 0x0114
260
261 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_HOSTSW_OWN 0x0150
262
263 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_GPI_IS 0x0200
264 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_GPI_IE 0x0220
265
266 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_GPI_GPE_STS 0x0240
267 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_GPI_GPE_EN 0x0260
268
269 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_SMI_STS 0x0280
270 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_SMI_EN 0x02A0
271
272 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_NMI_STS 0x02C0
273 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_NMI_EN 0x02E0
274
275 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
276
277 //
278 // GPIO Community 3 Private Configuration Registers
279 //
280 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_PAD_OWN 0x00A0
281 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_PAD_OWN 0x00A8
282 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_PAD_OWN 0x00B0
283 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_PAD_OWN 0x00BC
284
285 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_PADCFGLOCK 0x0110
286 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_PADCFGLOCKTX 0x0114
287 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_PADCFGLOCK 0x0118
288 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x011C
289 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_PADCFGLOCK 0x0120
290 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x0124
291 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_PADCFGLOCK 0x0128
292 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_PADCFGLOCKTX 0x012C
293
294 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_HOSTSW_OWN 0x0150
295 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_HOSTSW_OWN 0x0154
296 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_HOSTSW_OWN 0x0158
297 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_HOSTSW_OWN 0x015C
298
299 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_GPI_IS 0x0200
300 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_GPI_IS 0x0204
301 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_GPI_IS 0x0208
302 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_GPI_IS 0x020C
303
304 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_GPI_IE 0x0220
305 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_GPI_IE 0x0224
306 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_GPI_IE 0x0228
307 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_GPI_IE 0x022C
308
309 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_GPI_GPE_STS 0x0240
310 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0244
311 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0248
312 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_GPI_GPE_STS 0x024C
313
314 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_GPI_GPE_EN 0x0260
315 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0264
316 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0268
317 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_GPI_GPE_EN 0x026C
318
319 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_SMI_STS 0x0280
320 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_SMI_STS 0x0284
321 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_SMI_STS 0x0288
322 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_SMI_STS 0x028C
323
324 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_SMI_EN 0x02A0
325 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_SMI_EN 0x02A4
326 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_SMI_EN 0x02A8
327 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_SMI_EN 0x02AC
328
329 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_NMI_STS 0x02C0
330 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_NMI_STS 0x02C4
331 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_NMI_STS 0x02C8
332 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_NMI_STS 0x02CC
333
334 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_NMI_EN 0x02E0
335 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_NMI_EN 0x02E4
336 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_NMI_EN 0x02E8
337 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_NMI_EN 0x02EC
338
339 #define R_GPIO_VER4_PCH_S_GPIO_PCR_SPI_PADCFG_OFFSET 0x0700
340 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x0790
341 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x0890
342 #define R_GPIO_VER4_PCH_S_GPIO_PCR_VGPIO_3_PADCFG_OFFSET 0x0A10
343
344 //
345 // GPIO Community 4 Private Configuration Registers
346 //
347 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_PAD_OWN 0x00A0
348 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_PAD_OWN 0x00A4
349 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_PAD_OWN 0x00B0
350 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_PAD_OWN 0x00B8
351
352 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_PADCFGLOCK 0x0110
353 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x0114
354 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_PADCFGLOCK 0x0118
355 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x011C
356 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_PADCFGLOCK 0x0120
357 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_PADCFGLOCKTX 0x0124
358 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_PADCFGLOCK 0x0128
359 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x012C
360
361 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_HOSTSW_OWN 0x0150
362 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_HOSTSW_OWN 0x0154
363 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_HOSTSW_OWN 0x0158
364 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_HOSTSW_OWN 0x015C
365
366 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_GPI_IS 0x0200
367 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_GPI_IS 0x0204
368 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_GPI_IS 0x0208
369 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_GPI_IS 0x020C
370
371 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_GPI_IE 0x0220
372 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_GPI_IE 0x0224
373 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_GPI_IE 0x0228
374 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_GPI_IE 0x022C
375
376 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0240
377 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0244
378 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_GPI_GPE_STS 0x0248
379 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_GPI_GPE_STS 0x024C
380
381 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0260
382 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0264
383 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_GPI_GPE_EN 0x0268
384 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_GPI_GPE_EN 0x026C
385
386 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_SMI_STS 0x0280
387 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_SMI_STS 0x0284
388 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_SMI_STS 0x0288
389 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_SMI_STS 0x028C
390
391 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_SMI_EN 0x02A0
392 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_SMI_EN 0x02A4
393 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_SMI_EN 0x02A8
394 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_SMI_EN 0x02AC
395
396 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_NMI_STS 0x02C0
397 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_NMI_STS 0x02C4
398 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_NMI_STS 0x02C8
399 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_NMI_STS 0x02CC
400
401 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_NMI_EN 0x02E0
402 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_NMI_EN 0x02E4
403 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_NMI_EN 0x02E8
404 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_NMI_EN 0x02EC
405
406 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x0700
407 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x0780
408 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_K_PADCFG_OFFSET 0x08F0
409 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x09E0
410
411 //
412 // GPIO Community 5 Private Configuration Registers
413 //
414 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_PAD_OWN 0x00A0
415 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_PAD_OWN 0x00B0
416 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_PAD_OWN 0x00B8
417
418 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_PADCFGLOCK 0x0110
419 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x0114
420 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_PADCFGLOCK 0x0118
421 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_PADCFGLOCKTX 0x0118
422 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_PADCFGLOCK 0x0120
423 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_PADCFGLOCKTX 0x0124
424
425 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_HOSTSW_OWN 0x0150
426 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_HOSTSW_OWN 0x0154
427 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_HOSTSW_OWN 0x0158
428
429 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_GPI_IS 0x0200
430 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_GPI_IS 0x0204
431 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_GPI_IS 0x0208
432
433 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_GPI_IE 0x0220
434 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_GPI_IE 0x0224
435 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_GPI_IE 0x0228
436
437 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0240
438 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_GPI_GPE_STS 0x0244
439 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_GPI_GPE_STS 0x0248
440
441 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0260
442 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_GPI_GPE_EN 0x0264
443 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_GPI_GPE_EN 0x0268
444
445 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_SMI_STS 0x0280
446 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_SMI_STS 0x0284
447 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_SMI_STS 0x0288
448
449 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_SMI_EN 0x02A0
450 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_SMI_EN 0x02A4
451 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_SMI_EN 0x02A8
452
453 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_NMI_STS 0x02C0
454 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_NMI_STS 0x02C4
455 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_NMI_STS 0x02C8
456
457 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_NMI_EN 0x02E0
458 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_NMI_EN 0x02E4
459 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_NMI_EN 0x02E8
460
461 #define R_GPIO_VER4_PCH_S_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x0700
462 #define R_GPIO_VER4_PCH_S_GPIO_PCR_JTAG_PADCFG_OFFSET 0x0890
463 #define R_GPIO_VER4_PCH_S_GPIO_PCR_CPU_PADCFG_OFFSET 0x0920
464
465 #endif // _GPIO_REGS_VER4_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
Classes
GraphicsConfig.h File Reference

Policy definition for Internal Graphics Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | DDI_CONFIGURATION
This structure configures the Native GPIOs for DDI port per VBT settings. More...
struct | GRAPHICS_PEI_PREMEM_CONFIG
This Configuration block is to configure GT related PreMem data/variables. More...
struct | GRAPHICS_PEI_CONFIG
This configuration block is to configure IGD related variables used in PostMem PEI. More...
struct | GRAPHICS_DXE_CONFIG
This configuration block is to configure IGD related variables used in DXE. More...

Detailed Description

Policy definition for Internal Graphics Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GraphicsConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
GraphicsConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for Internal Graphics Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _GRAPHICS_CONFIG_H_
36 #define _GRAPHICS_CONFIG_H_
37 #pragma pack(push, 1)
38
39 #define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 7
40 #define GRAPHICS_PEI_CONFIG_REVISION 8
41 #define GRAPHICS_DXE_CONFIG_REVISION 2
42
43 #define DDI_DEVICE_NUMBER 4
44 #define MAX_BCLM_ENTRIES 20
45
46
47 //
48 // DDI defines
49 //
50 typedef enum {
51 DdiDisable = 0x00,
52 DdiDdcEnable = 0x01,
53 } DDI_DDC_TBT_VAL;
54
55 typedef enum {
56 DdiHpdDisable = 0x00,
57 DdiHpdEnable = 0x01,
58 } DDI_HPD_VAL;
59
60 typedef enum {
61 DdiPortDisabled = 0x00,
62 DdiPortEdp = 0x01,
63 DdiPortMipiDsi = 0x02,
64 } DDI_PORT_SETTINGS;
65
66 /**
67 This structure configures the Native GPIOs for DDI port per VBT settings.
68 **/
69 typedef struct {
70 UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
71 UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
72 UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
73 UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
74 UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
75 UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
76 UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
77 UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
78 UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
79 UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
80 UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
81 UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
82 UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
83 UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
84 UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
85 UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
86 } DDI_CONFIGURATION;
87
88 /**
89 This Configuration block is to configure GT related PreMem data/variables.\n
90 <b>Revision 1</b>:
91 - Initial version.
92 <b>Revision 2</b>:
93 - Added DfdRestoreEnable.
94 <b>Revision 3</b>:
95 - Added DdiConfiguration.
96 <b>Revision 4</b>:
97 - Added GmAdr64 and made GmAdr obselete
98 <b>Revision 5</b>:
99 - Added DeltaT12PowerCycleDelay
100 <b>Revision 6</b>:
101 - Added DisplayAudioLink
102 <b>Revision 7</b>:
103 - Added OemT12DelayOverride
104 **/
105 typedef struct {
106 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
107 /**
108 Offset 28
109 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
110 When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
111 **/
112 UINT8 PrimaryDisplay;
113 /**
114 Offset 29
115 Intel Gfx Support. It controls enabling/disabling iGfx device.
116 When AUTO mode selected, iGFX will be turned off when external graphics detected.
117 If FALSE, all other polices can be ignored.
118 <b>2 = AUTO</b>;
119 0 = FALSE;
120 1 = TRUE.
121 **/
122 UINT8 InternalGraphics;
123 /**
124 Offset 30
125 Pre-allocated memory for iGFX\n
126 0 = 0MB,1 or 247 = 32MB,\n
127 2 = 64MB,\n
128 240 = 4MB, 241 = 8MB,\n
129 242 = 12MB, 243 = 16MB,\n
130 244 = 20MB, 245 = 24MB,\n
131 246 = 28MB, 248 = 36MB,\n
132 249 = 40MB, 250 = 44MB,\n
133 251 = 48MB, 252 = 52MB,\n
134 253 = 56MB,<b> 254 = 60MB</b>,\n
135 <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
136 **/
137 UINT16 IgdDvmt50PreAlloc;
138 UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
139 UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
140 UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
141 UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
142 UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
143 UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
144 UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
145 /**
146 Offset 40
147 Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
148 **/
149 UINT32 GttMmAdr;
150 UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
151 DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
152
153 UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
154 UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
155 /**
156 Offset 58
157 Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
158 **/
159 UINT64 GmAdr64;
160 UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
161 UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
162 UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
163 UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
164 } GRAPHICS_PEI_PREMEM_CONFIG;
165
166 /**
167 This configuration block is to configure IGD related variables used in PostMem PEI.
168 If Intel Gfx Device is not supported, all policies can be ignored.
169 <b>Revision 1</b>:
170 - Initial version.
171 <b>Revision 2</b>:
172 - Removed DfdRestoreEnable.
173 <b>Revision 3</b>:
174 - Removed DdiConfiguration.
175 <b>Revision 4</b>:
176 - Added new CdClock frequency
177 <b>Revision 5</b>:
178 - Added GT Chicket bits
179 <b>Revision 6</b>:
180 - Added LogoPixelHeight and LogoPixelWidth
181 <b>Revision 7</b>:
182 - Added SkipFspGop
183 <b>Revision 8</b>:
184 - Added VerticalResolution and HorizontalResolution
185
186 **/
187 typedef struct {
188 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
189 UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
190 UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
191 /**
192 Offset 30
193 CdClock Frequency select\n
194 <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
195 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
196
197 **/
198 UINT16 CdClock;
199 UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
200 UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
201 UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
202 UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
203 UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
204 UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
205 UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
206 VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
207 UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
208 VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
209 VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
210 UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
211 UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
212 UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
213 UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
214 UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
215 UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
216 UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
217 UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
218 } GRAPHICS_PEI_CONFIG;
219
220 /**
221 This configuration block is to configure IGD related variables used in DXE.
222 If Intel Gfx Device is not supported or disabled, all policies will be ignored.
223 The data elements should be initialized by a Platform Module.\n
224 <b>Revision 1</b>:
225 - Initial version.
226 <b>Revision 2</b>:
227 - Removed IgdDvmtMemSize.
228 **/
229 typedef struct {
230 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
231 UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
232 EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
233 UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
234 UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
235 UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
236 UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
237 UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
238 CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
239 /**
240 Offset 80: IGD Panel Type CMOS option\n
241 <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
242 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
243 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
244 **/
245 UINT8 IgdPanelType;
246 UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
247 UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
248 UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
249 UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
250 UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
251 UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
252 } GRAPHICS_DXE_CONFIG;
253 #pragma pack(pop)
254
255 #endif // _GRAPHICS_CONFIG_H_
GRAPHICS_PEI_CONFIG::DisableTurboGt
UINT8 DisableTurboGt
Offset 36 : This policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:202
DDI_CONFIGURATION::DdiPortCHpd
UINT8 DdiPortCHpd
The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:74
GRAPHICS_DXE_CONFIG::BacklightControlSupport
UINT8 BacklightControlSupport
Offset 42: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
Definition: GraphicsConfig.h:235
DDI_CONFIGURATION::DdiPort2Hpd
UINT8 DdiPort2Hpd
The HPD setting of DDI Port 1, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:76
GRAPHICS_PEI_PREMEM_CONFIG
This Configuration block is to configure GT related PreMem data/variables.
Definition: GraphicsConfig.h:105
GRAPHICS_PEI_PREMEM_CONFIG::GttSize
UINT16 GttSize
Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, 3=8MB
Definition: GraphicsConfig.h:144
GRAPHICS_PEI_CONFIG::BltBufferSize
UINT32 BltBufferSize
Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI...
Definition: GraphicsConfig.h:210
GRAPHICS_PEI_CONFIG::PavpEnable
UINT8 PavpEnable
Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, 1=TRUE
Definition: GraphicsConfig.h:205
GRAPHICS_DXE_CONFIG::VbtAddress
EFI_PHYSICAL_ADDRESS VbtAddress
Offset 32 - 39: This field points to the GOP VBT data buffer.
Definition: GraphicsConfig.h:232
DDI_CONFIGURATION::DdiPort1Ddc
UINT8 DdiPort1Ddc
The DDC setting of DDI Port C, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:82
GRAPHICS_PEI_PREMEM_CONFIG::DisplayAudioLink
UINT8 DisplayAudioLink
Offset 68 Enable/Disable Display Audio Links in Pre-OS.0- Disable, 1- Enable.
Definition: GraphicsConfig.h:161
DDI_CONFIGURATION::DdiPort3Hpd
UINT8 DdiPort3Hpd
The HPD setting of DDI Port 2, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:77
GRAPHICS_DXE_CONFIG::IgdBootType
UINT8 IgdBootType
Offset 43: IGD Boot Type CMOS option: 0=Default, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3,...
Definition: GraphicsConfig.h:236
GRAPHICS_PEI_CONFIG::LogoPtr
VOID * LogoPtr
Offset 40 Address of Intel Gfx PEIM Logo to be displayed.
Definition: GraphicsConfig.h:206
GRAPHICS_DXE_CONFIG::IgdPanelScaling
UINT8 IgdPanelScaling
Offset 81: IGD Panel Scaling: 0=AUTO, 1=OFF, 6=Force scaling.
Definition: GraphicsConfig.h:246
GRAPHICS_PEI_PREMEM_CONFIG::GtClosEnable
UINT8 GtClosEnable
Offset 50 Gt ClOS.
Definition: GraphicsConfig.h:153
GRAPHICS_PEI_PREMEM_CONFIG::PsmiRegionSize
UINT8 PsmiRegionSize
Offset 35 :Psmi region size: 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1056MB.
Definition: GraphicsConfig.h:141
GRAPHICS_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
Definition: GraphicsConfig.h:230
GRAPHICS_PEI_CONFIG::PmSupport
UINT8 PmSupport
Offset 29 :(Test) Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, 1=TRUE
Definition: GraphicsConfig.h:190
GRAPHICS_DXE_CONFIG::IgdBlcConfig
UINT8 IgdBlcConfig
Offset 82: Backlight Control Support: 0=PWM Inverted, 2=PWM Normal
Definition: GraphicsConfig.h:247
GRAPHICS_PEI_PREMEM_CONFIG::DeltaT12PowerCycleDelay
UINT16 DeltaT12PowerCycleDelay
Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, 0xFFFF - Auto calculate t...
Definition: GraphicsConfig.h:160
GRAPHICS_PEI_CONFIG::ProgramGtChickenBits
UINT8 ProgramGtChickenBits
Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
Definition: GraphicsConfig.h:211
GRAPHICS_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GraphicsConfig.h:106
GRAPHICS_PEI_PREMEM_CONFIG::PrimaryDisplay
UINT8 PrimaryDisplay
Offset 28 Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH,...
Definition: GraphicsConfig.h:112
GRAPHICS_DXE_CONFIG
This configuration block is to configure IGD related variables used in DXE.
Definition: GraphicsConfig.h:229
GRAPHICS_PEI_PREMEM_CONFIG::DismSize
UINT8 DismSize
Offset 36 :DiSM Size for 2LM Sku: 0=0GB, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB,...
Definition: GraphicsConfig.h:142
GRAPHICS_PEI_CONFIG::CdynmaxClampEnable
UINT8 CdynmaxClampEnable
Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable,...
Definition: GraphicsConfig.h:200
GRAPHICS_DXE_CONFIG::IgdPanelType
UINT8 IgdPanelType
Offset 80: IGD Panel Type CMOS option 0=Default, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS,...
Definition: GraphicsConfig.h:245
GRAPHICS_PEI_PREMEM_CONFIG::IgdDvmt50PreAlloc
UINT16 IgdDvmt50PreAlloc
Offset 30 Pre-allocated memory for iGFX 0 = 0MB,1 or 247 = 32MB, 2 = 64MB, 240 = 4MB,...
Definition: GraphicsConfig.h:137
DDI_CONFIGURATION::DdiPortAHpd
UINT8 DdiPortAHpd
The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is...
Definition: GraphicsConfig.h:72
GRAPHICS_DXE_CONFIG::GfxTurboIMON
UINT8 GfxTurboIMON
Offset 84: IMON Current Value: 14=Minimal, 31=Maximum
Definition: GraphicsConfig.h:249
GRAPHICS_PEI_PREMEM_CONFIG::GmAdr
UINT32 GmAdr
Offset 44 Obsolete not to be used, use GmAdr64.
Definition: GraphicsConfig.h:150
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
GRAPHICS_DXE_CONFIG::AlsEnable
UINT8 AlsEnable
Offset 41: Ambient Light Sensor Enable: 0=Disable, 2=Enable.
Definition: GraphicsConfig.h:234
GRAPHICS_PEI_PREMEM_CONFIG::DdiConfiguration
DDI_CONFIGURATION DdiConfiguration
Offset 48 DDI configuration, need to match with VBT settings.
Definition: GraphicsConfig.h:151
DDI_CONFIGURATION::DdiPortBConfig
UINT8 DdiPortBConfig
The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is...
Definition: GraphicsConfig.h:71
GRAPHICS_PEI_PREMEM_CONFIG::GmAdr64
UINT64 GmAdr64
Offset 58 Temp Address of System Agent GMADR: Default is 0xB0000000
Definition: GraphicsConfig.h:159
GRAPHICS_PEI_CONFIG::RenderStandby
UINT8 RenderStandby
Offset 28 :(Test) This field is used to enable or disable RC6 (Render Standby): 0=FALSE,...
Definition: GraphicsConfig.h:189
DDI_CONFIGURATION::DdiPort3Ddc
UINT8 DdiPort3Ddc
The DDC setting of DDI Port 2, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:84
GRAPHICS_DXE_CONFIG::IgdDvmtMemSize
UINT8 IgdDvmtMemSize
Offset 83:
Definition: GraphicsConfig.h:248
DDI_CONFIGURATION::DdiPortADdc
UINT8 DdiPortADdc
The HPD setting of DDI Port 4, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:79
DDI_CONFIGURATION::DdiPortCDdc
UINT8 DdiPortCDdc
The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:81
DDI_CONFIGURATION
This structure configures the Native GPIOs for DDI port per VBT settings.
Definition: GraphicsConfig.h:69
GRAPHICS_PEI_CONFIG
This configuration block is to configure IGD related variables used in PostMem PEI.
Definition: GraphicsConfig.h:187
GRAPHICS_PEI_CONFIG::RC1pFreqEnable
UINT8 RC1pFreqEnable
Offset 38 : This policy is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:204
GRAPHICS_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: GraphicsConfig.h:188
DDI_CONFIGURATION::DdiPort1Hpd
UINT8 DdiPort1Hpd
The HPD setting of DDI Port C, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:75
GRAPHICS_PEI_CONFIG::LogoPixelWidth
UINT32 LogoPixelWidth
Offset 68 Address of LogoPixelWidth for PEIM Logo use.
Definition: GraphicsConfig.h:215
GRAPHICS_PEI_CONFIG::CdClock
UINT16 CdClock
Offset 30 CdClock Frequency select 0xFF = Auto.
Definition: GraphicsConfig.h:198
GRAPHICS_PEI_PREMEM_CONFIG::GttMmAdr
UINT32 GttMmAdr
Offset 40 Temp Address of System Agent GTTMMADR: Default is 0xAF000000
Definition: GraphicsConfig.h:149
GRAPHICS_PEI_PREMEM_CONFIG::OemT12DelayOverride
UINT8 OemT12DelayOverride
Offset 69 :Oem T12 Delay Override Disable< >,Enable-Enable T12 Time.
Definition: GraphicsConfig.h:162
GRAPHICS_PEI_PREMEM_CONFIG::InternalGraphics
UINT8 InternalGraphics
Offset 29 Intel Gfx Support.
Definition: GraphicsConfig.h:122
GRAPHICS_DXE_CONFIG::Size
UINT32 Size
Offset 28 - 31: This field gives the size of the GOP VBT Data buffer.
Definition: GraphicsConfig.h:231
GRAPHICS_PEI_PREMEM_CONFIG::GtPsmiSupport
UINT8 GtPsmiSupport
Offset 34 :PSMI support On/Off: 0=FALSE, 1=TRUE.
Definition: GraphicsConfig.h:140
GRAPHICS_DXE_CONFIG::PlatformConfig
UINT8 PlatformConfig
Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for UL...
Definition: GraphicsConfig.h:233
GRAPHICS_PEI_CONFIG::GtFreqMax
UINT16 GtFreqMax
Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value which indica...
Definition: GraphicsConfig.h:201
DDI_CONFIGURATION::DdiPortBHpd
UINT8 DdiPortBHpd
The HPD setting of DDI Port A, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:73
DDI_CONFIGURATION::DdiPort4Hpd
UINT8 DdiPort4Hpd
The HPD setting of DDI Port 3, this settings must match VBT's settings. DdiHpdDisable - Disable HPD,...
Definition: GraphicsConfig.h:78
GRAPHICS_PEI_CONFIG::SkipCdClockInit
UINT8 SkipCdClockInit
Offset 37 : SKip full CD clock initialization. 0- Disable, 1- Enable.
Definition: GraphicsConfig.h:203
GRAPHICS_PEI_PREMEM_CONFIG::PanelPowerEnable
UINT8 PanelPowerEnable
Offset 32 :(Test) Control for enabling/disabling VDD force bit (Required only for early enabling of e...
Definition: GraphicsConfig.h:138
GRAPHICS_PEI_CONFIG::HorizontalResolution
UINT32 HorizontalResolution
Offset 76 Address of HorizontalResolution for PEIM Logo use.
Definition: GraphicsConfig.h:217
DDI_CONFIGURATION::DdiPort4Ddc
UINT8 DdiPort4Ddc
The DDC setting of DDI Port 3, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:85
GRAPHICS_PEI_CONFIG::LogoPixelHeight
UINT32 LogoPixelHeight
Offset 64 Address of LogoPixelHeight for PEIM Logo use.
Definition: GraphicsConfig.h:214
GRAPHICS_PEI_CONFIG::GraphicsConfigPtr
VOID * GraphicsConfigPtr
Offset 48 Address of the Graphics Configuration Table.
Definition: GraphicsConfig.h:208
GRAPHICS_PEI_CONFIG::SkipFspGop
UINT8 SkipFspGop
Offset 61 This policy is used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver,...
Definition: GraphicsConfig.h:212
GRAPHICS_PEI_PREMEM_CONFIG::ApertureSize
UINT8 ApertureSize
Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB,...
Definition: GraphicsConfig.h:139
GRAPHICS_PEI_PREMEM_CONFIG::DfdRestoreEnable
UINT8 DfdRestoreEnable
Offset 37 :(Deprecated) Display memory map programming for DFD Restore 0- Disable,...
Definition: GraphicsConfig.h:143
GRAPHICS_PEI_CONFIG::BltBufferAddress
VOID * BltBufferAddress
Offset 52 Address of Blt buffer for PEIM Logo use.
Definition: GraphicsConfig.h:209
GRAPHICS_PEI_CONFIG::LogoSize
UINT32 LogoSize
Offset 44 Intel Gfx PEIM Logo Size.
Definition: GraphicsConfig.h:207
GRAPHICS_DXE_CONFIG::IuerStatusVal
UINT32 IuerStatusVal
Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (...
Definition: GraphicsConfig.h:237
GRAPHICS_PEI_CONFIG::VerticalResolution
UINT32 VerticalResolution
Offset 72 Address of VerticalResolution for PEIM Logo use.
Definition: GraphicsConfig.h:216
GRAPHICS_PEI_CONFIG::PeiGraphicsPeimInit
UINT8 PeiGraphicsPeimInit
Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable.
Definition: GraphicsConfig.h:199
DDI_CONFIGURATION::DdiPortBDdc
UINT8 DdiPortBDdc
The DDC setting of DDI Port A, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:80
DDI_CONFIGURATION::DdiPort2Ddc
UINT8 DdiPort2Ddc
The DDC setting of DDI Port 1, this settings must match VBT's settings. DdiDisable - Disable DDC,...
Definition: GraphicsConfig.h:83
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsInfoFruLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
GraphicsInfoFruLib.h File Reference

Header file for Graphics Info Fru Lib implementation. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciSegmentLib.h>
#include <IndustryStandard/Pci22.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for GraphicsInfoFruLib.h:

Go to the source code of this file.

Functions

BOOLEAN | IsDisplayOnlySku (VOID)
Checks if SKU is DisplayOnly. More...
EFI_STATUS | EnablePowerWell2 (IN UINT32 GttMmAdr)
Program the Display Power 2 Wells supported by platform. More...
EFI_STATUS | EnablePowerWell3 (IN UINT32 GttMmAdr)
Program the Display Power Wells 3 supported by platform. More...
BOOLEAN | IsMediaPresent (IN UINTN GttMmAdr)
Checks if Media is Present on 0/2/0 or not. More...
BOOLEAN | IsGtPresent (IN UINTN GttMmAdr)
Checks if GT is present on 0/2/0 or not. More...
BOOLEAN | IsDisplayPresent (IN UINTN GttMmAdr)
Checks if Display is present on 0/2/0 or not. More...
EFI_STATUS | ForceGtRc6 (VOID)
Force keep GT into RC6 state. More...

Detailed Description

Header file for Graphics Info Fru Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GraphicsInfoFruLib.h.

Function Documentation

◆ EnablePowerWell2()

EFI_STATUS EnablePowerWell2 ( IN UINT32 GttMmAdr )

Program the Display Power 2 Wells supported by platform.

Parameters
[in] GttMmAdr - Base Address of IGFX MMIO BAR
Return values
EFI_SUCCESS | - Power well programming finished successfully
EFI_UNSUPPORTED | - Power well programming failed
EFI_TIMEOUT | - Timed out

◆ EnablePowerWell3()

EFI_STATUS EnablePowerWell3 ( IN UINT32 GttMmAdr )

Program the Display Power Wells 3 supported by platform.

Parameters
[in] GttMmAdr - Base Address of IGFX MMIO BAR
Return values
EFI_SUCCESS | - Power well programming finished successfully
EFI_UNSUPPORTED | - Power well programming failed
EFI_TIMEOUT | - Timed out

◆ ForceGtRc6()

EFI_STATUS ForceGtRc6 ( VOID )

Force keep GT into RC6 state.

Return values
EFI_SUCCESS - GT RC6 MSR programmed successfully

◆ IsDisplayOnlySku()

BOOLEAN IsDisplayOnlySku ( VOID )

Checks if SKU is DisplayOnly.

Return values
FALSE | SKU is not DisplayOnly
TRUE | SKU is DisplayOnly

◆ IsDisplayPresent()

BOOLEAN IsDisplayPresent ( IN UINTN GttMmAdr )

Checks if Display is present on 0/2/0 or not.

Return values
FALSE | Display is not present
TRUE | Display is present

◆ IsGtPresent()

BOOLEAN IsGtPresent ( IN UINTN GttMmAdr )

Checks if GT is present on 0/2/0 or not.

Return values
FALSE | GT is not present
TRUE | GT is present

◆ IsMediaPresent()

BOOLEAN IsMediaPresent ( IN UINTN GttMmAdr )

Checks if Media is Present on 0/2/0 or not.

Return values
FALSE | Media is not present
TRUE | Media is present
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsInfoFruLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GraphicsInfoFruLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Graphics Info Fru Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _GRAPHICS_INFO_FRU_LIB_H_
37 #define _GRAPHICS_INFO_FRU_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/IoLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <IndustryStandard/Pci22.h>
46 #include <Register/SaRegsHostBridge.h>
47
48 /**
49 Checks if SKU is DisplayOnly
50
51 @retval FALSE SKU is not DisplayOnly
52 @retval TRUE SKU is DisplayOnly
53 **/
54 BOOLEAN
55 EFIAPI
56 IsDisplayOnlySku (
57 VOID
58 );
59
60 /**
61 Program the Display Power 2 Wells supported by platform
62
63 @param[in] GttMmAdr - Base Address of IGFX MMIO BAR
64
65 @retval EFI_SUCCESS - Power well programming finished successfully
66 @retval EFI_UNSUPPORTED - Power well programming failed
67 @retval EFI_TIMEOUT - Timed out
68 **/
69 EFI_STATUS
70 EnablePowerWell2 (
71 IN UINT32 GttMmAdr
72 );
73
74 /**
75 Program the Display Power Wells 3 supported by platform
76
77 @param[in] GttMmAdr - Base Address of IGFX MMIO BAR
78
79 @retval EFI_SUCCESS - Power well programming finished successfully
80 @retval EFI_UNSUPPORTED - Power well programming failed
81 @retval EFI_TIMEOUT - Timed out
82 **/
83 EFI_STATUS
84 EnablePowerWell3 (
85 IN UINT32 GttMmAdr
86 );
87
88 /**
89 Checks if Media is Present on 0/2/0 or not.
90
91 @retval FALSE Media is not present
92 @retval TRUE Media is present
93 **/
94 BOOLEAN
95 EFIAPI
96 IsMediaPresent (
97 IN UINTN GttMmAdr
98 );
99
100 /**
101 Checks if GT is present on 0/2/0 or not.
102
103 @retval FALSE GT is not present
104 @retval TRUE GT is present
105 **/
106 BOOLEAN
107 EFIAPI
108 IsGtPresent (
109 IN UINTN GttMmAdr
110 );
111
112 /**
113 Checks if Display is present on 0/2/0 or not.
114
115 @retval FALSE Display is not present
116 @retval TRUE Display is present
117 **/
118 BOOLEAN
119 EFIAPI
120 IsDisplayPresent (
121 IN UINTN GttMmAdr
122 );
123
124 /**
125 Force keep GT into RC6 state
126
127 @retval EFI_SUCCESS - GT RC6 MSR programmed successfully
128 **/
129 EFI_STATUS
130 EFIAPI
131 ForceGtRc6 (
132 VOID
133 );
134 #endif
ForceGtRc6
EFI_STATUS ForceGtRc6(VOID)
Force keep GT into RC6 state.
IsMediaPresent
BOOLEAN IsMediaPresent(IN UINTN GttMmAdr)
Checks if Media is Present on 0/2/0 or not.
EnablePowerWell2
EFI_STATUS EnablePowerWell2(IN UINT32 GttMmAdr)
Program the Display Power 2 Wells supported by platform.
IsDisplayOnlySku
BOOLEAN IsDisplayOnlySku(VOID)
Checks if SKU is DisplayOnly.
IsGtPresent
BOOLEAN IsGtPresent(IN UINTN GttMmAdr)
Checks if GT is present on 0/2/0 or not.
IsDisplayPresent
BOOLEAN IsDisplayPresent(IN UINTN GttMmAdr)
Checks if Display is present on 0/2/0 or not.
EnablePowerWell3
EFI_STATUS EnablePowerWell3(IN UINT32 GttMmAdr)
Program the Display Power Wells 3 supported by platform.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Macros | Functions
GraphicsInfoLib.h File Reference

Header file for Graphics Private Info Lib implementation. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciSegmentLib.h>
#include <IndustryStandard/Pci22.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for GraphicsInfoLib.h:

Go to the source code of this file.

Macros

#define GT_WAIT_TIMEOUT 3000000
~3 seconds

Functions

BOOLEAN | IgfxCmdRegEnabled (VOID)
This function will check if Bus Initiator and Memory access on 0:2:0 is enabled or not. More...
UINT8 | GetIgdBusNumber (VOID)
GetIgdBusNumber: Get IGD Bus Number. More...
UINT8 | GetIgdDevNumber (VOID)
GetIgdDevNumber: Get IGD Dev Number. More...
UINT8 | GetIgdFuncNumber (VOID)
GetIgdFunNumber: Get IGD Fun Number. More...
UINT8 | GetGttMmAdrOffset (VOID)
GetGttMmAdrOffset: Get GTTMMADR Offset value. More...
UINT8 | GetGmAdrOffset (VOID)
GetGmAdrOffset: Get GMADR Offset value. More...
UINT8 | GetIgdMsacOffset (VOID)
GetIgdMsacOffset: Get IGD MSAC Offset value. More...
UINT32 | GetIgdDssmRefClockFreqValue (IN UINTN GttMmAdr)
GetIgdDssmRefClockFreqValue: Read DSSM (Display Strap State) register to get display reference clock frequence value. More...
EFI_STATUS | PollGtReady (IN UINT64 Base, IN UINT32 Offset, IN UINT32 Mask, IN UINT32 Result)
"Poll Status" for GT Readiness More...
BOOLEAN | IsIGfxSupported (VOID)
This function will check if Intel Graphics is Enabled or Supported. More...
UINT32 | GetIgdGmsSizeInMb (VOID)
This function will Return the Graphics Memory Stolen Size in MB This API is obsoleted from Ver2 Lib and replaced with GetIgdDsmSizeInMb (). More...
UINT32 | GetIgdDsmSizeInMb (VOID)
This function will Return the Graphics Data Stolen Memory Size in MB. More...
UINT32 | GetIgdGsmSizeInMb (VOID)
This function will Return the Graphics Stolen Memory Size in MB. More...
BOOLEAN | IsRc6Locked (IN UINTN GttMmAdr)
This function will check if RC6 Context Base is locked or not on IGD. More...
BOOLEAN | IsDoorbellRangeValid (IN UINTN GttMmAdr)
This function will check if Doorbell is in Range or not on IGD. More...
BOOLEAN | IsRc6RangeValid (IN UINTN GttMmAdr)
This function will check if RC6 is in Range or not on IGD. More...
BOOLEAN | IsWoPcmRangeValid (IN UINTN GttMmAdr)
This function will check if PAVP is in Range or not on IGD. More...
BOOLEAN | IsWoPcmBaseRegistersConsistent (IN UINTN GttMmAdr)
This function will check if WOPCM base is consistent in different memory scopes. More...
BOOLEAN | IsPavpBitLocked (IN UINTN GttMmAdr)
This function will check if PAVP is locked in different memory scopes. More...
UINT8 | GetIgfxApertureOffset (VOID)
GetIgfxApertureOffset: Get graphics aperture offset value. More...
BOOLEAN | IsDsmBaseAndImrMemoryConsistent (VOID)
This function will check if DSM base is consistent in different memory scopes. More...
BOOLEAN | IsGsmBaseAndImrMemoryConsistent (VOID)
This function will check if GSM base is consistent in different memory scopes. More...
BOOLEAN | IsMediaRc6RangeValid (IN UINTN GttMmAdr)
This function will check if SA Media RC6 is in Range or not on IGD. More...
BOOLEAN | IsGcdRc6RangeValid (IN UINTN GttMmAdr)
This function will check if GCD RC6 is in Range or not on IGD. More...
BOOLEAN | IsMediaRc6Locked (IN UINTN GttMmAdr)
This function will check if Media RC6 Context Base is locked or not on IGD. More...
BOOLEAN | IsGcdRc6Locked (IN UINTN GttMmAdr)
This function will check if GCD RC6 Context Base is locked or not on IGD. More...

Detailed Description

Header file for Graphics Private Info Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file GraphicsInfoLib.h.

Function Documentation

◆ GetGmAdrOffset()

UINT8 GetGmAdrOffset ( VOID )

GetGmAdrOffset: Get GMADR Offset value.

Return values
PCI Offset for GMADR

◆ GetGttMmAdrOffset()

UINT8 GetGttMmAdrOffset ( VOID )

GetGttMmAdrOffset: Get GTTMMADR Offset value.

Return values
PCI Offset for GTTMMADR

◆ GetIgdBusNumber()

UINT8 GetIgdBusNumber ( VOID )

GetIgdBusNumber: Get IGD Bus Number.

Return values
PCI bus number for IGD

◆ GetIgdDevNumber()

UINT8 GetIgdDevNumber ( VOID )

GetIgdDevNumber: Get IGD Dev Number.

Return values
PCI dev number for IGD

◆ GetIgdDsmSizeInMb()

UINT32 GetIgdDsmSizeInMb ( VOID )

This function will Return the Graphics Data Stolen Memory Size in MB.

Return values
GsmSize Graphics Data Stolen Memory Size

◆ GetIgdDssmRefClockFreqValue()

UINT32 GetIgdDssmRefClockFreqValue ( IN UINTN GttMmAdr )

GetIgdDssmRefClockFreqValue: Read DSSM (Display Strap State) register to get display reference clock frequence value.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
IGD Display Reference clock frequency value

◆ GetIgdFuncNumber()

UINT8 GetIgdFuncNumber ( VOID )

GetIgdFunNumber: Get IGD Fun Number.

Return values
PCI fun number for IGD

◆ GetIgdGmsSizeInMb()

UINT32 GetIgdGmsSizeInMb ( VOID )

This function will Return the Graphics Memory Stolen Size in MB This API is obsoleted from Ver2 Lib and replaced with GetIgdDsmSizeInMb ().

Return values
GsmSize Graphics Memory Stolen Size

◆ GetIgdGsmSizeInMb()

UINT32 GetIgdGsmSizeInMb ( VOID )

This function will Return the Graphics Stolen Memory Size in MB.

Return values
GsmSize Graphics Stolen Memory Size

◆ GetIgdMsacOffset()

UINT8 GetIgdMsacOffset ( VOID )

GetIgdMsacOffset: Get IGD MSAC Offset value.

Return values
PCI Offset for IGD Aperture size.

◆ GetIgfxApertureOffset()

UINT8 GetIgfxApertureOffset ( VOID )

GetIgfxApertureOffset: Get graphics aperture offset value.

Return values
PCI Offset for igfx aperture BAR

◆ IgfxCmdRegEnabled()

BOOLEAN IgfxCmdRegEnabled ( VOID )

This function will check if Bus Initiator and Memory access on 0:2:0 is enabled or not.

Return values
TRUE | IGD Bus Initiator Access and Memory Space access is Enabled
FALSE | IGD Bus Initiator Access and Memory Space access is Disable

◆ IsDoorbellRangeValid()

BOOLEAN IsDoorbellRangeValid ( IN UINTN GttMmAdr )

This function will check if Doorbell is in Range or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | Doorbell is in Range
FALSE | Doorbell is not in Range

◆ IsDsmBaseAndImrMemoryConsistent()

BOOLEAN IsDsmBaseAndImrMemoryConsistent ( VOID )

This function will check if DSM base is consistent in different memory scopes.

Return values
TRUE | DSM Base is consistent
FALSE | DSM Base is not consistent

◆ IsGcdRc6Locked()

BOOLEAN IsGcdRc6Locked ( IN UINTN GttMmAdr )

This function will check if GCD RC6 Context Base is locked or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | Gcd RC6 is Locked
FALSE | Gcd RC6 is not locked OR If Igfx is not supported OR GT is not present

◆ IsGcdRc6RangeValid()

BOOLEAN IsGcdRc6RangeValid ( IN UINTN GttMmAdr )

This function will check if GCD RC6 is in Range or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | Gcd RC6 is in Range
FALSE | Gcd RC6 is not in Range OR If Igfx is not supported OR GT is not present.

◆ IsGsmBaseAndImrMemoryConsistent()

BOOLEAN IsGsmBaseAndImrMemoryConsistent ( VOID )

This function will check if GSM base is consistent in different memory scopes.

Return values
TRUE | GSM Base is consistent
FALSE | GSM Base is not consistent

◆ IsIGfxSupported()

BOOLEAN IsIGfxSupported ( VOID )

This function will check if Intel Graphics is Enabled or Supported.

Return values
TRUE | Graphics Enabled or Supported
FALSE | Graphics not Enabled or not Supported

◆ IsMediaRc6Locked()

BOOLEAN IsMediaRc6Locked ( IN UINTN GttMmAdr )

This function will check if Media RC6 Context Base is locked or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | Media RC6 is Locked
FALSE | Media RC6 is not locked OR If Igfx is not supported OR Media is not prsent

◆ IsMediaRc6RangeValid()

BOOLEAN IsMediaRc6RangeValid ( IN UINTN GttMmAdr )

This function will check if SA Media RC6 is in Range or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | Media RC6 is in Range
FALSE | Media RC6 is not in Range OR If Igfx is not supported OR Media is not present

◆ IsPavpBitLocked()

BOOLEAN IsPavpBitLocked ( IN UINTN GttMmAdr )

This function will check if PAVP is locked in different memory scopes.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | PAVP is locked
FALSE | PAVP is not locked

◆ IsRc6Locked()

BOOLEAN IsRc6Locked ( IN UINTN GttMmAdr )

This function will check if RC6 Context Base is locked or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | RC6 is Locked
FALSE | RC6 is not locked

◆ IsRc6RangeValid()

BOOLEAN IsRc6RangeValid ( IN UINTN GttMmAdr )

This function will check if RC6 is in Range or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | RC6 is in Range
FALSE | RC6 is not in Range

◆ IsWoPcmBaseRegistersConsistent()

BOOLEAN IsWoPcmBaseRegistersConsistent ( IN UINTN GttMmAdr )

This function will check if WOPCM base is consistent in different memory scopes.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | WOPCM Base is consistent
FALSE | WOPCM Base is not consistent

◆ IsWoPcmRangeValid()

BOOLEAN IsWoPcmRangeValid ( IN UINTN GttMmAdr )

This function will check if PAVP is in Range or not on IGD.

Parameters
[in] GttMmAdr IGD MMIO Base address value
Return values
TRUE | RC6 is in Range
FALSE | RC6 is not in Range

◆ PollGtReady()

EFI_STATUS PollGtReady | ( | IN UINT64 | Base,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | Mask,
 |  | IN UINT32 | Result
 | ) |  |

"Poll Status" for GT Readiness

Parameters
[in] | Base | - Base address of MMIO
[in] | Offset | - MMIO Offset
[in] | Mask | - Mask
[in] | Result | - Value to wait for
Return values
EFI_SUCCESS | - Wait Bit Successfully set
EFI_TIMEOUT | - Timed out
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): GraphicsInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
GraphicsInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Graphics Private Info Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _GRAPHICS_INFO_LIB_H_
37 #define _GRAPHICS_INFO_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/IoLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <IndustryStandard/Pci22.h>
46 #include <Register/SaRegsHostBridge.h>
47
48 #define GT_WAIT_TIMEOUT 3000000 ///< ~3 seconds
49
50 /**
51 This function will check if Bus Initiator and Memory access on 0:2:0 is enabled or not
52
53 @retval TRUE IGD Bus Initiator Access and Memory Space access is Enabled
54 @retval FALSE IGD Bus Initiator Access and Memory Space access is Disable
55 **/
56 BOOLEAN
57 IgfxCmdRegEnabled (
58 VOID
59 );
60
61
62 /**
63 GetIgdBusNumber: Get IGD Bus Number
64
65 @retval PCI bus number for IGD
66 **/
67 UINT8
68 GetIgdBusNumber (
69 VOID
70 );
71
72 /**
73 GetIgdDevNumber: Get IGD Dev Number
74
75 @retval PCI dev number for IGD
76 **/
77 UINT8
78 GetIgdDevNumber (
79 VOID
80 );
81
82 /**
83 GetIgdFunNumber: Get IGD Fun Number
84
85 @retval PCI fun number for IGD
86 **/
87 UINT8
88 GetIgdFuncNumber (
89 VOID
90 );
91
92
93 /**
94 GetGttMmAdrOffset: Get GTTMMADR Offset value
95
96 @retval PCI Offset for GTTMMADR
97 **/
98 UINT8
99 GetGttMmAdrOffset (
100 VOID
101 );
102
103 /**
104 GetGmAdrOffset: Get GMADR Offset value
105
106 @retval PCI Offset for GMADR
107 **/
108 UINT8
109 GetGmAdrOffset (
110 VOID
111 );
112
113 /**
114 GetIgdMsacOffset: Get IGD MSAC Offset value
115
116 @retval PCI Offset for IGD Aperture size.
117 **/
118 UINT8
119 GetIgdMsacOffset (
120 VOID
121 );
122
123 /**
124 GetIgdDssmRefClockFreqValue: Read DSSM (Display Strap State) register to get display reference clock frequence value
125
126 @param[in] GttMmAdr IGD MMIO Base address value
127
128 @retval IGD Display Reference clock frequency value
129 **/
130 UINT32
131 GetIgdDssmRefClockFreqValue (
132 IN UINTN GttMmAdr
133 );
134
135 /**
136 "Poll Status" for GT Readiness
137
138 @param[in] Base - Base address of MMIO
139 @param[in] Offset - MMIO Offset
140 @param[in] Mask - Mask
141 @param[in] Result - Value to wait for
142
143 @retval EFI_SUCCESS - Wait Bit Successfully set
144 @retval EFI_TIMEOUT - Timed out
145 **/
146 EFI_STATUS
147 PollGtReady (
148 IN UINT64 Base,
149 IN UINT32 Offset,
150 IN UINT32 Mask,
151 IN UINT32 Result
152 );
153
154 /**
155 This function will check if Intel Graphics is Enabled or Supported
156
157 @retval TRUE Graphics Enabled or Supported
158 @retval FALSE Graphics not Enabled or not Supported
159 **/
160 BOOLEAN
161 IsIGfxSupported (
162 VOID
163 );
164
165 /**
166 This function will Return the Graphics Memory Stolen Size in MB
167 This API is obsoleted from Ver2 Lib and replaced with GetIgdDsmSizeInMb ().
168
169 @retval GsmSize Graphics Memory Stolen Size
170 **/
171 UINT32
172 EFIAPI
173 GetIgdGmsSizeInMb (
174 VOID
175 );
176
177 /**
178 This function will Return the Graphics Data Stolen Memory Size in MB
179
180 @retval GsmSize Graphics Data Stolen Memory Size
181 **/
182 UINT32
183 EFIAPI
184 GetIgdDsmSizeInMb (
185 VOID
186 );
187
188 /**
189 This function will Return the Graphics Stolen Memory Size in MB
190
191 @retval GsmSize Graphics Stolen Memory Size
192 **/
193 UINT32
194 EFIAPI
195 GetIgdGsmSizeInMb (
196 VOID
197 );
198
199 /**
200 This function will check if RC6 Context Base is locked or not on IGD
201
202 @param[in] GttMmAdr IGD MMIO Base address value
203
204 @retval TRUE RC6 is Locked
205 @retval FALSE RC6 is not locked
206 **/
207 BOOLEAN
208 IsRc6Locked (
209 IN UINTN GttMmAdr
210 );
211
212 /**
213 This function will check if Doorbell is in Range or not on IGD
214
215 @param[in] GttMmAdr IGD MMIO Base address value
216
217 @retval TRUE Doorbell is in Range
218 @retval FALSE Doorbell is not in Range
219 **/
220 BOOLEAN
221 IsDoorbellRangeValid (
222 IN UINTN GttMmAdr
223 );
224
225 /**
226 This function will check if RC6 is in Range or not on IGD.
227
228 @param[in] GttMmAdr IGD MMIO Base address value
229
230 @retval TRUE RC6 is in Range
231 @retval FALSE RC6 is not in Range
232 **/
233 BOOLEAN
234 IsRc6RangeValid (
235 IN UINTN GttMmAdr
236 );
237
238 /**
239 This function will check if PAVP is in Range or not on IGD.
240
241 @param[in] GttMmAdr IGD MMIO Base address value
242
243 @retval TRUE RC6 is in Range
244 @retval FALSE RC6 is not in Range
245 **/
246 BOOLEAN
247 IsWoPcmRangeValid (
248 IN UINTN GttMmAdr
249 );
250
251 /**
252 This function will check if WOPCM base is consistent in different memory scopes.
253
254 @param[in] GttMmAdr IGD MMIO Base address value
255
256 @retval TRUE WOPCM Base is consistent
257 @retval FALSE WOPCM Base is not consistent
258 **/
259 BOOLEAN
260 IsWoPcmBaseRegistersConsistent (
261 IN UINTN GttMmAdr
262 );
263
264 /**
265 This function will check if PAVP is locked in different memory scopes.
266
267 @param[in] GttMmAdr IGD MMIO Base address value
268
269 @retval TRUE PAVP is locked
270 @retval FALSE PAVP is not locked
271 **/
272 BOOLEAN
273 IsPavpBitLocked (
274 IN UINTN GttMmAdr
275 );
276
277 /**
278 GetIgfxApertureOffset: Get graphics aperture offset value
279
280 @retval PCI Offset for igfx aperture BAR
281 **/
282 UINT8
283 GetIgfxApertureOffset (
284 VOID
285 );
286
287 /**
288 This function will check if DSM base is consistent in different memory scopes.
289
290 @retval TRUE DSM Base is consistent
291 @retval FALSE DSM Base is not consistent
292 **/
293 BOOLEAN
294 IsDsmBaseAndImrMemoryConsistent (
295 VOID
296 );
297
298 /**
299 This function will check if GSM base is consistent in different memory scopes.
300
301 @retval TRUE GSM Base is consistent
302 @retval FALSE GSM Base is not consistent
303 **/
304 BOOLEAN
305 IsGsmBaseAndImrMemoryConsistent (
306 VOID
307 );
308
309 /**
310 This function will check if SA Media RC6 is in Range or not on IGD.
311
312 @param[in] GttMmAdr IGD MMIO Base address value
313
314 @retval TRUE Media RC6 is in Range
315 @retval FALSE Media RC6 is not in Range OR If Igfx is not supported OR Media is not present
316 **/
317 BOOLEAN
318 IsMediaRc6RangeValid (
319 IN UINTN GttMmAdr
320 );
321
322 /**
323 This function will check if GCD RC6 is in Range or not on IGD.
324
325 @param[in] GttMmAdr IGD MMIO Base address value
326
327 @retval TRUE Gcd RC6 is in Range
328 @retval FALSE Gcd RC6 is not in Range OR If Igfx is not supported OR GT is not present.
329 **/
330 BOOLEAN
331 IsGcdRc6RangeValid (
332 IN UINTN GttMmAdr
333 );
334
335 /**
336 This function will check if Media RC6 Context Base is locked or not on IGD
337
338 @param[in] GttMmAdr IGD MMIO Base address value
339
340 @retval TRUE Media RC6 is Locked
341 @retval FALSE Media RC6 is not locked OR If Igfx is not supported OR Media is not prsent
342 **/
343 BOOLEAN
344 IsMediaRc6Locked (
345 IN UINTN GttMmAdr
346 );
347
348 /**
349 This function will check if GCD RC6 Context Base is locked or not on IGD
350
351 @param[in] GttMmAdr IGD MMIO Base address value
352
353 @retval TRUE Gcd RC6 is Locked
354 @retval FALSE Gcd RC6 is not locked OR If Igfx is not supported OR GT is not present
355 **/
356 BOOLEAN
357 IsGcdRc6Locked (
358 IN UINTN GttMmAdr
359 );
360 #endif
GetIgdGsmSizeInMb
UINT32 GetIgdGsmSizeInMb(VOID)
This function will Return the Graphics Stolen Memory Size in MB.
IsIGfxSupported
BOOLEAN IsIGfxSupported(VOID)
This function will check if Intel Graphics is Enabled or Supported.
IsRc6RangeValid
BOOLEAN IsRc6RangeValid(IN UINTN GttMmAdr)
This function will check if RC6 is in Range or not on IGD.
IsRc6Locked
BOOLEAN IsRc6Locked(IN UINTN GttMmAdr)
This function will check if RC6 Context Base is locked or not on IGD.
GetIgdBusNumber
UINT8 GetIgdBusNumber(VOID)
GetIgdBusNumber: Get IGD Bus Number.
IsGsmBaseAndImrMemoryConsistent
BOOLEAN IsGsmBaseAndImrMemoryConsistent(VOID)
This function will check if GSM base is consistent in different memory scopes.
IsMediaRc6RangeValid
BOOLEAN IsMediaRc6RangeValid(IN UINTN GttMmAdr)
This function will check if SA Media RC6 is in Range or not on IGD.
GetGttMmAdrOffset
UINT8 GetGttMmAdrOffset(VOID)
GetGttMmAdrOffset: Get GTTMMADR Offset value.
IsWoPcmBaseRegistersConsistent
BOOLEAN IsWoPcmBaseRegistersConsistent(IN UINTN GttMmAdr)
This function will check if WOPCM base is consistent in different memory scopes.
GetIgdDevNumber
UINT8 GetIgdDevNumber(VOID)
GetIgdDevNumber: Get IGD Dev Number.
IsWoPcmRangeValid
BOOLEAN IsWoPcmRangeValid(IN UINTN GttMmAdr)
This function will check if PAVP is in Range or not on IGD.
IsDoorbellRangeValid
BOOLEAN IsDoorbellRangeValid(IN UINTN GttMmAdr)
This function will check if Doorbell is in Range or not on IGD.
GetGmAdrOffset
UINT8 GetGmAdrOffset(VOID)
GetGmAdrOffset: Get GMADR Offset value.
IsMediaRc6Locked
BOOLEAN IsMediaRc6Locked(IN UINTN GttMmAdr)
This function will check if Media RC6 Context Base is locked or not on IGD.
IsPavpBitLocked
BOOLEAN IsPavpBitLocked(IN UINTN GttMmAdr)
This function will check if PAVP is locked in different memory scopes.
IsDsmBaseAndImrMemoryConsistent
BOOLEAN IsDsmBaseAndImrMemoryConsistent(VOID)
This function will check if DSM base is consistent in different memory scopes.
GetIgdMsacOffset
UINT8 GetIgdMsacOffset(VOID)
GetIgdMsacOffset: Get IGD MSAC Offset value.
GetIgdDsmSizeInMb
UINT32 GetIgdDsmSizeInMb(VOID)
This function will Return the Graphics Data Stolen Memory Size in MB.
GetIgdDssmRefClockFreqValue
UINT32 GetIgdDssmRefClockFreqValue(IN UINTN GttMmAdr)
GetIgdDssmRefClockFreqValue: Read DSSM (Display Strap State) register to get display reference clock ...
GetIgdFuncNumber
UINT8 GetIgdFuncNumber(VOID)
GetIgdFunNumber: Get IGD Fun Number.
IgfxCmdRegEnabled
BOOLEAN IgfxCmdRegEnabled(VOID)
This function will check if Bus Initiator and Memory access on 0:2:0 is enabled or not.
GetIgdGmsSizeInMb
UINT32 GetIgdGmsSizeInMb(VOID)
This function will Return the Graphics Memory Stolen Size in MB This API is obsoleted from Ver2 Lib a...
IsGcdRc6RangeValid
BOOLEAN IsGcdRc6RangeValid(IN UINTN GttMmAdr)
This function will check if GCD RC6 is in Range or not on IGD.
IsGcdRc6Locked
BOOLEAN IsGcdRc6Locked(IN UINTN GttMmAdr)
This function will check if GCD RC6 Context Base is locked or not on IGD.
PollGtReady
EFI_STATUS PollGtReady(IN UINT64 Base, IN UINT32 Offset, IN UINT32 Mask, IN UINT32 Result)
"Poll Status" for GT Readiness
GetIgfxApertureOffset
UINT8 GetIgfxApertureOffset(VOID)
GetIgfxApertureOffset: Get graphics aperture offset value.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Hda.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Hda.h File Reference

Header file for HD Audio configuration. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Header file for HD Audio configuration.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Hda.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Hda.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
Hda.h
Go to the documentation of this file.
1 /** @file
2 Header file for HD Audio configuration.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _HDA_H_
37 #define _HDA_H_
38
39 typedef enum {
40 HdaVc0 = 0,
41 HdaVc1 = 1
42 } HDAUDIO_VC_TYPE;
43
44 typedef enum {
45 HdaLinkFreq6MHz = 0,
46 HdaLinkFreq12MHz = 1,
47 HdaLinkFreq24MHz = 2,
48 HdaLinkFreq48MHz = 3,
49 HdaLinkFreq96MHz = 4,
50 HdaLinkFreqInvalid
51 } HDAUDIO_LINK_FREQUENCY;
52
53 typedef enum {
54 HdaIDispMode2T = 0,
55 HdaIDispMode1T = 1,
56 HdaIDispMode4T = 2,
57 HdaIDispMode8T = 3,
58 HdaIDispMode16T = 4,
59 HdaIDispTModeInvalid
60 } HDAUDIO_IDISP_TMODE;
61
62 typedef enum {
63 HdaLink = 0,
64 HdaIDispLink = 1,
65 HdaDmic = 2,
66 HdaSsp = 3,
67 HdaSndw = 4,
68 HdaLinkUnsupported
69 } HDAUDIO_LINK_TYPE;
70
71 typedef enum {
72 HdaDmicClockSelectBoth = 0,
73 HdaDmicClockSelectClkA = 1,
74 HdaDmicClockSelectClkB = 2,
75 HdaDmicClockSelectInvalid
76 } HDAUDIO_DMIC_CLOCK_SELECT;
77
78 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HdAudioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Classes | Macros
HdAudioConfig.h File Reference

HDAUDIO policy. More...

#include <ConfigBlock.h>
#include <PchLimits.h>
Include dependency graph for HdAudioConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia verb commands. More...
struct | HDA_LINK_HDA
HD Audio Link Policies. More...
struct | HDA_LINK_DMIC
HD Audio DMIC Interface Policies. More...
struct | HDA_LINK_SSP
HD Audio SSP Interface Policies. More...
struct | HDA_LINK_SNDW
HD Audio SNDW Interface Policies. More...
struct | HDAUDIO_CONFIG
This structure contains the policies which are related to HD Audio device (cAVS). More...
struct | HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS). More...
struct | HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS). More...

Macros

#define | HDAUDIO_VERB_TABLE_VIDDID(Vid, Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
#define | HDAUDIO_VERB_TABLE_INIT(Vid, Did, Rid, Sdi, ...)
Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically.

Detailed Description

HDAUDIO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HdAudioConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HdAudioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
HdAudioConfig.h
Go to the documentation of this file.
1 /** @file
2 HDAUDIO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HDAUDIO_CONFIG_H_
36 #define _HDAUDIO_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <PchLimits.h>
40
41 #define HDAUDIO_PREMEM_CONFIG_REVISION 4
42 #define HDAUDIO_CONFIG_REVISION 1
43 #define HDAUDIO_DXE_CONFIG_REVISION 2
44
45 extern EFI_GUID gHdAudioPreMemConfigGuid;
46 extern EFI_GUID gHdAudioConfigGuid;
47 extern EFI_GUID gHdAudioDxeConfigGuid;
48
49 #pragma pack (push,1)
50
51 ///
52 /// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
53 ///
54
55 #define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
56 #define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
57 #define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
58
59 ///
60 /// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically
61 ///
62 #define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
63 { \
64 { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
65 { __VA_ARGS__ } \
66 }
67
68 /**
69 Azalia verb table header
70 Every verb table should contain this defined header and followed by azalia verb commands.
71 **/
72 typedef struct {
73 UINT16 VendorId; ///< Codec Vendor ID
74 UINT16 DeviceId; ///< Codec Device ID
75 UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
76 UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
77 UINT16 DataDwords; ///< Number of data DWORDs following the header.
78 } HDA_VERB_TABLE_HEADER;
79
80 #ifdef _MSC_VER
81 //
82 // Disable "zero-sized array in struct/union" extension warning.
83 // Used for neater verb table definitions.
84 //
85 #pragma warning (push)
86 #pragma warning (disable: 4200)
87 #endif
88 typedef struct {
89 HDA_VERB_TABLE_HEADER Header;
90 UINT32 Data[];
91 } HDAUDIO_VERB_TABLE;
92 #ifdef _MSC_VER
93 #pragma warning (pop)
94 #endif
95
96 typedef struct {
97 UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKA_*
98 UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_CLKB_*
99 UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_MUXING_DMIC*_DATA_*
100 } HDA_DMIC_PIN_MUX;
101
102 /**
103 HD Audio Link Policies
104 **/
105 typedef struct {
106 UINT32 Enable : 1; ///< HDA interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
107 UINT32 RsvdBits0 : 31;
108 UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When enabled related SDI pins will be switched to appropriate native mode: <b>0: Disable</b>; 1: Enable
109 UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI enable table.
110 } HDA_LINK_HDA;
111
112 /**
113 HD Audio DMIC Interface Policies
114 **/
115 typedef struct {
116 UINT32 Enable : 1; ///< HDA DMIC interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
117 UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <b>0: Both</b>, 1: ClkA, 2: ClkB; default is "Both"
118 UINT32 RsvdBits0 : 29;
119 HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.
120 } HDA_LINK_DMIC;
121
122 /**
123 HD Audio SSP Interface Policies
124 **/
125 typedef struct {
126 UINT32 Enable : 1; ///< HDA SSP interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
127 UINT32 RsvdBits0 : 31;
128 } HDA_LINK_SSP;
129
130 /**
131 HD Audio SNDW Interface Policies
132 **/
133 typedef struct {
134 UINT32 Enable : 1; ///< HDA SNDW interface enable. When enabled related pins will be switched to native mode: <b>0: Disable</b>; 1: Enable.
135 UINT32 RsvdBits0 : 31;
136 } HDA_LINK_SNDW;
137
138
139 /**
140 This structure contains the policies which are related to HD Audio device (cAVS).
141
142 <b>Revision 1:</b>
143 - Inital version.
144
145 **/
146 typedef struct {
147 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
148 UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
149 UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initiated by a codec in Sx (eg by modem codec), <b>0: Disable</b>; 1: Enable
150 UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
151 UINT32 RsvdBits0 : 26; ///< Reserved bits 0
152 /**
153 Number of the verb table entry defined in VerbTablePtr.
154 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
155 **/
156 UINT8 VerbTableEntryNum;
157 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
158 /**
159 Pointer to a verb table array.
160 This pointer points to 32bits address, and is only eligible and consumed in post mem phase.
161 Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
162 The prototype of this is:
163 HDAUDIO_VERB_TABLE **VerbTablePtr;
164 **/
165 UINT32 VerbTablePtr;
166 } HDAUDIO_CONFIG;
167
168 /**
169 This structure contains the premem policies which are related to HD Audio device (cAVS).
170
171 <b>Revision 1:</b>
172 - Inital version.
173 <b>Revision 2:</b>
174 - Add DmicClockSelect
175 <b>Revision 3:</b>
176 - Add AudioFpgaSocVer
177 <b>Revision 4:</b>
178 - Remove AudioFpgaSocVer
179 **/
180 typedef struct {
181 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
182 UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enablement: 0: Disable, <b>1: Enable</b>
183 UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
184 UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
185 /**
186 Universal Audio Architecture compliance for DSP enabled system:
187 <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
188 1: UAA Compliant (HDA Inbox driver or SST driver supported)
189 **/
190 UINT32 DspUaaCompliance : 1;
191 UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
192 UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, <b>3: 8T</b>, 4: 16T
193 UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
194 UINT32 PowerGatingSupported : 1; ///< Power Gating supported: <b>0: Not supported</b>, 1: Supported
195 UINT32 RsvdBits : 19; ///< Reserved bits 0
196
197 /**
198 Audio Link Mode configuration bitmask.
199 Allows to configure enablement of the following interfaces: HDA-Link, DMIC, SSP, SoundWire.
200 **/
201
202 HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disable; <b>1: Enable</b>.
203 /**
204 DMIC link enablement: 0: Disable; <b>1: Enable</b>.
205 DMIC0 LKF: Muxed with SNDW2/SNDW4.
206 **/
207 HDA_LINK_DMIC AudioLinkDmic [PCH_MAX_HDA_DMIC_LINK_NUM];
208 /**
209 I2S/SSP link enablement: <b>0: Disable</b>; 1: Enable.
210 SSP0/1 LKF: Muxed with HDA.
211 @note Since the I2S/SSP2 pin set contains pads which are also used for CNVi purpose, enabling AudioLinkSsp2
212 is exclusive with CNVi is present.
213 **/
214 HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];
215 /**
216 SoundWire link enablement: <b>0: Disable</b>; 1: Enable.
217 SNDW2 LKF: Muxed with DMIC0/DMIC1.
218 SNDW3 LKF: Muxed with DMIC1.
219 SNDW4 LKF: Muxed with DMIC0.
220 **/
221 HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM];
222
223 UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
224 UINT8 Rsvd0[2]; ///< Reserved bytes, align to multiple 4
225 UINT32 SubSystemIds; ///< Value for SID and SVID. If its set to 0 then default value is used.
226 } HDAUDIO_PREMEM_CONFIG;
227
228 typedef struct {
229 UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonomous clock stop capability: <b>0: Disable</b>; 1: Enable
230 UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on active interval select 0: 6 clock periods; <b>1: 7 clock periods</b>; 2: 8 clock periods; 3: 11 clock periods
231 UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on delay select 0: 2 clock periods; <b>1: 3 clock periods</b>
232 UINT32 RsvdBits1 : 28; ///< Reserved bits 1
233 } HDAUDIO_SNDW_CONFIG;
234
235 /**
236 This structure contains the DXE policies which are related to HD Audio device (cAVS).
237 <b>Revision 1:</b>
238 - Inital version.
239 <b>Revision 2:</b>
240 - Add IoControlEnabled
241 <b>Revision 3:</b>
242 - Remove IoControlEnabled
243 **/
244 typedef struct {
245 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
246 /**
247 SNDW configuration for exposed via SNDW ACPI tables:
248 **/
249 HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];
250 /**
251 Bitmask of supported DSP features:
252 [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
253 [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
254 Default is <b>zero</b>.
255 **/
256 UINT32 DspFeatureMask;
257 } HDAUDIO_DXE_CONFIG;
258
259 #pragma pack (pop)
260
261 #endif // _HDAUDIO_CONFIG_H_
HDA_VERB_TABLE_HEADER::SdiNum
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
Definition: HdAudioConfig.h:76
HDA_LINK_SSP
HD Audio SSP Interface Policies.
Definition: HdAudioConfig.h:125
ConfigBlock.h
Header file for Config Block Lib implementation.
HDAUDIO_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits 0.
Definition: HdAudioConfig.h:195
HDA_LINK_SNDW::Enable
UINT32 Enable
HDA SNDW interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:134
HDA_LINK_DMIC::PinMux
HDA_DMIC_PIN_MUX PinMux
Pin mux configuration.
Definition: HdAudioConfig.h:119
HDAUDIO_CONFIG::VerbTableEntryNum
UINT8 VerbTableEntryNum
Number of the verb table entry defined in VerbTablePtr.
Definition: HdAudioConfig.h:156
HDA_LINK_HDA
HD Audio Link Policies.
Definition: HdAudioConfig.h:105
HDAUDIO_DXE_CONFIG
This structure contains the DXE policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:244
HDA_VERB_TABLE_HEADER::VendorId
UINT16 VendorId
Codec Vendor ID.
Definition: HdAudioConfig.h:73
HDAUDIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:147
HDAUDIO_PREMEM_CONFIG::DspUaaCompliance
UINT32 DspUaaCompliance
Universal Audio Architecture compliance for DSP enabled system: 0: Not-UAA Compliant (Intel SST drive...
Definition: HdAudioConfig.h:190
HDA_LINK_DMIC::Enable
UINT32 Enable
HDA DMIC interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: ...
Definition: HdAudioConfig.h:116
HDAUDIO_PREMEM_CONFIG::Enable
UINT32 Enable
Intel HD Audio (Azalia) enablement: 0: Disable, 1: Enable
Definition: HdAudioConfig.h:182
HDA_VERB_TABLE_HEADER::RevisionId
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
Definition: HdAudioConfig.h:75
HDAUDIO_CONFIG::HdAudioLinkFrequency
UINT32 HdAudioLinkFrequency
HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz.
Definition: HdAudioConfig.h:150
HDAUDIO_PREMEM_CONFIG::SubSystemIds
UINT32 SubSystemIds
Value for SID and SVID. If its set to 0 then default value is used.
Definition: HdAudioConfig.h:225
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HDAUDIO_PREMEM_CONFIG::AudioLinkHda
HDA_LINK_HDA AudioLinkHda
Audio Link Mode configuration bitmask.
Definition: HdAudioConfig.h:202
HDAUDIO_PREMEM_CONFIG::IDispLinkFrequency
UINT32 IDispLinkFrequency
iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz
Definition: HdAudioConfig.h:191
HDA_LINK_DMIC
HD Audio DMIC Interface Policies.
Definition: HdAudioConfig.h:115
HDAUDIO_PREMEM_CONFIG::DspEnable
UINT32 DspEnable
DSP enablement: 0: Disable; 1: Enable
Definition: HdAudioConfig.h:183
HDAUDIO_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits 0.
Definition: HdAudioConfig.h:151
HDAUDIO_PREMEM_CONFIG::PowerGatingSupported
UINT32 PowerGatingSupported
Power Gating supported: 0: Not supported, 1: Supported.
Definition: HdAudioConfig.h:194
HDA_LINK_DMIC::DmicClockSelect
UINT32 DmicClockSelect
DMIC link clock select: 0: Both, 1: ClkA, 2: ClkB; default is "Both".
Definition: HdAudioConfig.h:117
HDAUDIO_PREMEM_CONFIG::VcType
UINT32 VcType
Virtual Channel Type Select: 0: VC0, 1: VC1.
Definition: HdAudioConfig.h:184
HDAUDIO_CONFIG::VerbTablePtr
UINT32 VerbTablePtr
Pointer to a verb table array.
Definition: HdAudioConfig.h:165
HDA_VERB_TABLE_HEADER::DeviceId
UINT16 DeviceId
Codec Device ID.
Definition: HdAudioConfig.h:74
HDAUDIO_CONFIG::Pme
UINT32 Pme
Azalia wake-on-ring, 0: Disable; 1: Enable.
Definition: HdAudioConfig.h:148
HDAUDIO_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:181
HDAUDIO_CONFIG::CodecSxWakeCapability
UINT32 CodecSxWakeCapability
Capability to detect wake initiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable.
Definition: HdAudioConfig.h:149
HDAUDIO_PREMEM_CONFIG::ResetWaitTimer
UINT16 ResetWaitTimer
(Test) The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
Definition: HdAudioConfig.h:223
HDA_LINK_SSP::Enable
UINT32 Enable
HDA SSP interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: E...
Definition: HdAudioConfig.h:126
HDAUDIO_DXE_CONFIG::DspFeatureMask
UINT32 DspFeatureMask
Bitmask of supported DSP features: [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - B...
Definition: HdAudioConfig.h:256
HDAUDIO_PREMEM_CONFIG::IDispCodecDisconnect
UINT32 IDispCodecDisconnect
iDisplay Audio Codec disconnection, 0: Not disconnected, enumerable; 1: Disconnected SDI,...
Definition: HdAudioConfig.h:193
HDA_VERB_TABLE_HEADER::DataDwords
UINT16 DataDwords
Number of data DWORDs following the header.
Definition: HdAudioConfig.h:77
HDAUDIO_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HdAudioConfig.h:245
HDA_LINK_HDA::Enable
UINT32 Enable
HDA interface enable. When enabled related pins will be switched to native mode: 0: Disable; 1: Enabl...
Definition: HdAudioConfig.h:106
HDAUDIO_CONFIG
This structure contains the policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:146
HDAUDIO_PREMEM_CONFIG
This structure contains the premem policies which are related to HD Audio device (cAVS).
Definition: HdAudioConfig.h:180
HDA_LINK_SNDW
HD Audio SNDW Interface Policies.
Definition: HdAudioConfig.h:133
HDAUDIO_PREMEM_CONFIG::IDispLinkTmode
UINT32 IDispLinkTmode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T
Definition: HdAudioConfig.h:192
HDA_VERB_TABLE_HEADER
Azalia verb table header Every verb table should contain this defined header and followed by azalia v...
Definition: HdAudioConfig.h:72
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciAccessPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Variables
HeciAccessPpi.h File Reference

ME HECI Access PPI - ME-BIOS communication over HECI in PEI. More...

#include <Protocol/HeciAccessProtocol.h>
Include dependency graph for HeciAccessPpi.h:

Go to the source code of this file.

Variables

EFI_GUID gHeciAccessPpiGuid
ME HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.

Detailed Description

ME HECI Access PPI - ME-BIOS communication over HECI in PEI.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file HeciAccessPpi.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciAccessPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
HeciAccessPpi.h
Go to the documentation of this file.
1 /** @file
2 ME HECI Access PPI - ME-BIOS communication over HECI in PEI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 **/
34 #ifndef __HECI_ACCESS_PPI_H__
35 #define __HECI_ACCESS_PPI_H__
36
37 #include <Protocol/HeciAccessProtocol.h>
38
39 /**
40 ME HECI PPI GUID
41 This PPI provides an interface to communicate with Intel ME in PEI phase.
42 **/
43 extern EFI_GUID gHeciAccessPpiGuid;
44
45 #endif // __HECI_ACCESS_PPI_H__
46
HeciAccessProtocol.h
ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
gHeciAccessPpiGuid
EFI_GUID gHeciAccessPpiGuid
ME HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciAccessProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs | Variables
HeciAccessProtocol.h File Reference

ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM. More...

#include <Uefi.h>
#include <Protocol/PciIo.h>
Include dependency graph for HeciAccessProtocol.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _HECI_ACCESS_
PPI/PROTOCOL for ME-UEFI FW HECI Access. More...

Typedefs

typedef struct _HECI_ACCESS_ | HECI_ACCESS
PPI/PROTOCOL for ME-UEFI FW HECI Access. More...
typedef EFI_STATUS(* | HECI_ACCESS_GET_PARAMETER) (IN HECI_ACCESS *This, IN OUT UINTN *HeciAccessParam)
Get HECI Access Parameter. More...
typedef HECI_ACCESS *(* | HECI_ACCESS_GET_NEXT_HECI) (IN HECI_ACCESS *This, IN HECI_ACCESS *HeciAccess)
Get Next HECI Access. More...

Variables

EFI_GUID gHeciAccessProtocolGuid
ME HECI Protocol GUID This Protocol provides an interface to communicate with Intel ME in DXE/SMM phase.

Detailed Description

ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file HeciAccessProtocol.h.

Typedef Documentation

◆ HECI_ACCESS

typedef struct _HECI_ACCESS_ HECI_ACCESS

PPI/PROTOCOL for ME-UEFI FW HECI Access.

This protocol defines operations for HECI (Host Embedded Controller Interface) hardware access.

Definition at line 32 of file HeciAccessProtocol.h.

◆ HECI_ACCESS_GET_NEXT_HECI

typedef HECI_ACCESS*( * HECI_ACCESS_GET_NEXT_HECI) (IN HECI_ACCESS *This, IN HECI_ACCESS *HeciAccess)

Get Next HECI Access.

Parameters
[in] | This | Pointer to HECI Access device context structure
[in] | HeciAccess | Pointer to HECI Access device context structure the next element should be relative to Passing NULL requests first element
Return values
HECI_ACCES Next HeciAccess object

Definition at line 59 of file HeciAccessProtocol.h.

◆ HECI_ACCESS_GET_PARAMETER

typedef EFI_STATUS( * HECI_ACCESS_GET_PARAMETER) (IN HECI_ACCESS *This, IN OUT UINTN *HeciAccessParam)

Get HECI Access Parameter.

Parameters
[in] | This | Pointer to HECI Access device context structure
[in,out] | HeciAccessParam | Pointer to HECI Access parameter
Return values
Operation EFI_STATUS

Definition at line 44 of file HeciAccessProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciAccessProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
HeciAccessProtocol.h
Go to the documentation of this file.
1 /** @file
2 ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 **/
21 #ifndef __HECI_ACCESS_PROTOCOL_H__
22 #define __HECI_ACCESS_PROTOCOL_H__
23
24 #include <Uefi.h>
25 #include <Protocol/PciIo.h>
26
27 /**
28 ME HECI Protocol GUID
29 This Protocol provides an interface to communicate with Intel ME in DXE/SMM phase.
30 **/
31 extern EFI_GUID gHeciAccessProtocolGuid;
32 extern EFI_GUID gHeciAccessSmmProtocolGuid;
33
34 typedef struct _HECI_ACCESS_ HECI_ACCESS;
35
36 /**
37 Get HECI Access Parameter
38
39 @param[in] This Pointer to HECI Access device context structure
40 @param[in,out] HeciAccessParam Pointer to HECI Access parameter
41
42 @retval Operation EFI_STATUS
43 **/
44 typedef EFI_STATUS (EFIAPI *HECI_ACCESS_GET_PARAMETER) (
45 IN HECI_ACCESS *This,
46 IN OUT UINTN *HeciAccessParam
47 );
48
49 /**
50 Get Next HECI Access
51
52 @param[in] This Pointer to HECI Access device context structure
53 @param[in] HeciAccess Pointer to HECI Access device context structure
54 the next element should be relative to
55 Passing NULL requests first element
56
57 @retval HECI_ACCES Next HeciAccess object
58 **/
59 typedef HECI_ACCESS* (EFIAPI *HECI_ACCESS_GET_NEXT_HECI) (
60 IN HECI_ACCESS *This,
61 IN HECI_ACCESS *HeciAccess
62 );
63
64 /**
65 PPI/PROTOCOL for ME-UEFI FW HECI Access.
66
67 This protocol defines operations for HECI (Host Embedded Controller Interface)
68 hardware access.
69 **/
70 typedef struct _HECI_ACCESS_ {
71 EFI_PCI_IO_PROTOCOL PciIo; /// < PciIo R/W HECI PCIe device
72 HECI_ACCESS_GET_NEXT_HECI GetNextHeciAccess; /// < HECI access protocol walker
73 // HECI configuration access
74 HECI_ACCESS_GET_PARAMETER GetHeciPch; /// < What PCH HECI belongs to
75 HECI_ACCESS_GET_PARAMETER GetHeciInterruptMode;/// < Default HECI Interrupt mode to be used
76 } HECI_ACCESS;
77
78 #endif // __HECI_ACCESS_PROTOCOL_H__
HECI_ACCESS
struct _HECI_ACCESS_ HECI_ACCESS
PPI/PROTOCOL for ME-UEFI FW HECI Access.
Definition: HeciAccessProtocol.h:34
_HECI_ACCESS_::GetHeciPch
HECI_ACCESS_GET_PARAMETER GetHeciPch
< HECI access protocol walker
Definition: HeciAccessProtocol.h:74
HECI_ACCESS_GET_NEXT_HECI
HECI_ACCESS *(* HECI_ACCESS_GET_NEXT_HECI)(IN HECI_ACCESS *This, IN HECI_ACCESS *HeciAccess)
Get Next HECI Access.
Definition: HeciAccessProtocol.h:59
HECI_ACCESS_GET_PARAMETER
EFI_STATUS(* HECI_ACCESS_GET_PARAMETER)(IN HECI_ACCESS *This, IN OUT UINTN *HeciAccessParam)
Get HECI Access Parameter.
Definition: HeciAccessProtocol.h:44
_HECI_ACCESS_::GetHeciInterruptMode
HECI_ACCESS_GET_PARAMETER GetHeciInterruptMode
< What PCH HECI belongs to
Definition: HeciAccessProtocol.h:75
_HECI_ACCESS_
PPI/PROTOCOL for ME-UEFI FW HECI Access.
Definition: HeciAccessProtocol.h:70
gHeciAccessProtocolGuid
EFI_GUID gHeciAccessProtocolGuid
ME HECI Protocol GUID This Protocol provides an interface to communicate with Intel ME in DXE/SMM pha...
_HECI_ACCESS_::GetNextHeciAccess
HECI_ACCESS_GET_NEXT_HECI GetNextHeciAccess
< PciIo R/W HECI PCIe device
Definition: HeciAccessProtocol.h:72
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciControlPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Variables
HeciControlPpi.h File Reference

PEI Heci Control PPI - ME-BIOS communication over HECI in PEI. More...

#include <Protocol/HeciControlProtocol.h>
Include dependency graph for HeciControlPpi.h:

Go to the source code of this file.

Variables

EFI_GUID gHeciControlPpiGuid
ME HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.

Detailed Description

PEI Heci Control PPI - ME-BIOS communication over HECI in PEI.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file HeciControlPpi.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciControlPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
HeciControlPpi.h
Go to the documentation of this file.
1 /** @file
2 PEI Heci Control PPI - ME-BIOS communication over HECI in PEI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 **/
34 #ifndef _HECI_CONTROL_PPI_H_
35 #define _HECI_CONTROL_PPI_H_
36
37 #include <Protocol/HeciControlProtocol.h>
38
39 /**
40 ME HECI PPI GUID
41 This PPI provides an interface to communicate with Intel ME in PEI phase.
42 **/
43 extern EFI_GUID gHeciControlPpiGuid;
44
45 #endif // _HECI_CONTROL_PPI_H_
gHeciControlPpiGuid
EFI_GUID gHeciControlPpiGuid
ME HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.
HeciControlProtocol.h
ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciControlProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs | Variables
HeciControlProtocol.h File Reference

ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _HECI_CONTROL_
EFI protocol for ME-UEFI FW communication over HECI. More...

Macros

#define | HECI_DEFAULT_RETRY_NUMBER 3
Default number of retries to be used HeciControl API calls. More...
#define | HECI_DEFAULT_PCH_ID 0xDEFA001D
Default HECI Control PCH ID, leave the decision to HeciControl on how to send the message.

Typedefs

typedef struct _HECI_CONTROL_ | HECI_CONTROL
EFI protocol for ME-UEFI FW communication over HECI. More...
typedef EFI_STATUS(* | HECI_CONTROL_RESET) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout)
Reset HECI queue. More...
typedef EFI_STATUS(* | HECI_CONTROL_SEND_AND_RECEIVE) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 Retries, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *ReqMsg, IN UINT32 ReqLen, OUT UINT32 *RspMsg, IN OUT UINT32 *RspLen, IN OUT EFI_STATUS *SendStatus, IN OUT EFI_STATUS *ReceiveStatus)
Send request message to HECI queue, wait for response if needed. More...
typedef EFI_STATUS(* | HECI_CONTROL_SEND) (IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *MsgBody, IN UINT32 MsgLen)
Write a message to HECI queue, if necessary perform fragmentation. More...
typedef EFI_STATUS(* | HECI_CONTROL_RECEIVE) (IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, OUT UINT8 *HostAddress, OUT UINT8 *EngineAddress, OUT UINT32 *MsgBody, IN OUT UINT32 *MsgLen)
Read a message from HECI queue, if necessary perform reassembly. More...
typedef EFI_STATUS(* | HECI_CONTROL_READ_FIRMWARE_STATUS) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN UINT8 HeciNumber, IN OUT UINT32 *FirmwareStatus)
Read HECI Firmware status. More...

Variables

EFI_GUID gHeciControlProtocolGuid
ME HECI Protocol GUID This protocol provides an interface to communicate with Intel ME over HECI function on PCH ME Device.

Detailed Description

ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file HeciControlProtocol.h.

Macro Definition Documentation

◆ HECI_DEFAULT_RETRY_NUMBER

#define HECI_DEFAULT_RETRY_NUMBER 3

Default number of retries to be used HeciControl API calls.

Retries number

Definition at line 41 of file HeciControlProtocol.h.

Typedef Documentation

◆ HECI_CONTROL

typedef struct _HECI_CONTROL_ HECI_CONTROL

EFI protocol for ME-UEFI FW communication over HECI.

This protocol defines operations for communication with ME using HECI (Host Embedded Controller Interface). There are more HECI functions in ME device on PCI. HECI is designated for ME-UEFI FW boot flow communication.

Definition at line 55 of file HeciControlProtocol.h.

◆ HECI_CONTROL_READ_FIRMWARE_STATUS

typedef EFI_STATUS( * HECI_CONTROL_READ_FIRMWARE_STATUS) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN UINT8 HeciNumber, IN OUT UINT32 *FirmwareStatus)

Read HECI Firmware status.

This function reads HECI firmware status from given PCH and HECI interface

Parameters
[in] | This | HeciControl instance
[in] | HeciNumber | Heci number to firmware status read [1..4]
[in] | FilterFunction | Heci filtering function to be installed
[in,out] | FirmwareStatus | Pointer to returned firmware status
Return values
EFI_SUCCESS | Returned valid firmware status
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_DEVICE_ERROR | Error occurred

Definition at line 221 of file HeciControlProtocol.h.

◆ HECI_CONTROL_RECEIVE

typedef EFI_STATUS( * HECI_CONTROL_RECEIVE) (IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, OUT UINT8 *HostAddress, OUT UINT8 *EngineAddress, OUT UINT32 *MsgBody, IN OUT UINT32 *MsgLen)

Read a message from HECI queue, if necessary perform reassembly.

This function reads one message from HECI queue. If the message is fragmented and timeout is greater than zero the function will wait for subsequent packets (fragments) until full message is completed.

Parameters
[in,out] | This | HeciControl instance
[in] | HeciPchId | PchId we want to communicate with 0..N HECI_DEFAULT_PCH_ID Id is default and HeciControl decides where to route communication
[in,out] | Timeout | On input timeout in us, on exit time left
[out] | HostAddress | Host address
[out] | EngineAddress | Engine (ME/IE) address
[out] | MsgBody | Body of the message to send
[in,out] | MsgLen | On input buffer size, on exit message body size in bytes
Return values
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_WRITE_PROTECTED | Can't find suitable HECI Transport
EFI_DEVICE_ERROR | HECI MBar can't be initialized
EFI_TIMEOUT | Timeout occurs during operation
EFI_BAD_BUFFER_SIZE | Message exceeds buffer size
EFI_SUCCESS | Message has been received successfully

Definition at line 197 of file HeciControlProtocol.h.

◆ HECI_CONTROL_RESET

typedef EFI_STATUS( * HECI_CONTROL_RESET) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout)

Reset HECI queue.

This function triggers HECI queue reset. If timeout is greater than zero it also waits until ME is ready to receive messages. When HeciControl is provided last used HECI transport will be reset When no HeciControl is not valid, reset target is derived from handle

Parameters
[in] | This | HeciControl instance
[in] | HeciPchId | PchId we want to communicate with 0..N HECI_DEFAULT_PCH_ID Id is default and HeciControl decides where to route communication
[in,out] | Timeout | On input timeout in us, on exit time left
Return values
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_WRITE_PROTECTED | Can't find suitable HECI Transport
EFI_DEVICE_ERROR | HECI MBar can't be initialized
EFI_TIMEOUT | Timeout occurs during operation
EFI_SUCCESS | Reset HECI queue succeed

Definition at line 81 of file HeciControlProtocol.h.

◆ HECI_CONTROL_SEND

typedef EFI_STATUS( * HECI_CONTROL_SEND) (IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *MsgBody, IN UINT32 MsgLen)

Write a message to HECI queue, if necessary perform fragmentation.

This function puts one message to HECI queue. If the message is longer than HECI queue size and timeout is greater than zero the function will split the message into several packets and wait for space in the queue to send all packets/fragments. Each packet has HECI packet header added.

Parameters
[in,out] | This | HeciControl instance
[in] | HeciPchId | PchId we want to communicate with 0..N HECI_DEFAULT_PCH_ID Id is default and HeciControl decides where to route communication
[in,out] | Timeout | On input timeout in us, on exit time left
[in] | HostAddress | Host address
[in] | EngineAddress | Engine (ME/IE) address
[in] | MsgBody | Body of the message to send
[in] | MsgLen | Length in bytes of the message to send
Return values
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_WRITE_PROTECTED | Can't find suitable HECI Transport Possible reason: HECI filter active
EFI_DEVICE_ERROR | HECI MBar can't be initialized
EFI_TIMEOUT | Timeout occurs during operation
EFI_BAD_BUFFER_SIZE | Packet is bigger than queue length
EFI_SUCCESS | Message has been sent successfully

Definition at line 163 of file HeciControlProtocol.h.

◆ HECI_CONTROL_SEND_AND_RECEIVE

typedef EFI_STATUS( * HECI_CONTROL_SEND_AND_RECEIVE) (IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 Retries, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *ReqMsg, IN UINT32 ReqLen, OUT UINT32 *RspMsg, IN OUT UINT32 *RspLen, IN OUT EFI_STATUS *SendStatus, IN OUT EFI_STATUS *ReceiveStatus)

Send request message to HECI queue, wait for response if needed.

This function writes one message to HECI queue and - if receive buffer was provided and timeout is greater than zero - waits for response message. The request can be retried if Retries > 0 (0 means one attempt, no retry), but if retries are requested, the pReqMsg and pRspMsg pointers must point to different buffers. This is required to make sure request is unchanged. Size of receive message buffer is given in bytes in (*RspLen) on input. On exit (*RspLen) provides the number of bytes written to the message buffer. If buffer is too short the message is truncated.

Parameters
[in] | This | HeciControl instance
[in] | HeciPchId | PchId we want to communicate with 0..N HECI_DEFAULT_PCH_ID Id is default and HeciControl decides where to route communication
[in,out] | Timeout | On input timeout in us, on exit time left
[in] | Retries | The number of retries requested (0 => no retry)
[in] | HostAddress | Host address
[in] | EngineAddress | Engine (ME/IE) address
[in] | ReqMsg | Request message
[in] | ReqLen | Request message length in bytes
[out] | RspMsg | Buffer for the response message
[in,out] | RspLen | On input buffer size, on exit message, in bytes
[in,out] | SendStatus | Send operation status
[in,out] | ReceiveStatus | Receive operation status
Return values
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_WRITE_PROTECTED | Can't find suitable HECI Transport Possible reason: HECI filter active
EFI_DEVICE_ERROR | HECI MBar can't be initialized
EFI_TIMEOUT | Timeout occurs during operation
EFI_BAD_BUFFER_SIZE | Message is too big
EFI_SUCCESS | Message request has been completed successfully

Definition at line 122 of file HeciControlProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciControlProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
HeciControlProtocol.h
Go to the documentation of this file.
1 /** @file
2 ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 **/
34
35 #ifndef _HECI_CONTROL_PROTOCOL_H_
36 #define _HECI_CONTROL_PROTOCOL_H_
37
38 ///
39 /// Default number of retries to be used HeciControl API calls
40 ///
41 #define HECI_DEFAULT_RETRY_NUMBER 3 ///< Retries number
42
43 /**
44 Default HECI Control PCH ID,
45 leave the decision to HeciControl on how to send the message
46 **/
47 #define HECI_DEFAULT_PCH_ID 0xDEFA001D
48
49 /**
50 ME HECI Protocol GUID
51 This protocol provides an interface to communicate with Intel ME
52 over HECI function on PCH ME Device.
53 **/
54 extern EFI_GUID gHeciControlProtocolGuid;
55 extern EFI_GUID gHeciControlSmmProtocolGuid;
56
57
58 typedef struct _HECI_CONTROL_ HECI_CONTROL;
59
60
61 /**
62 Reset HECI queue.
63
64 This function triggers HECI queue reset. If timeout is greater than zero it
65 also waits until ME is ready to receive messages.
66 When HeciControl is provided last used HECI transport will be reset
67 When no HeciControl is not valid, reset target is derived from handle
68
69 @param[in] This HeciControl instance
70 @param[in] HeciPchId PchId we want to communicate with 0..N
71 HECI_DEFAULT_PCH_ID Id is default and
72 HeciControl decides where to route communication
73 @param[in,out] Timeout On input timeout in us, on exit time left
74
75 @retval EFI_INVALID_PARAMETER Input parameters are invalid
76 @retval EFI_WRITE_PROTECTED Can't find suitable HECI Transport
77 @retval EFI_DEVICE_ERROR HECI MBar can't be initialized
78 @retval EFI_TIMEOUT Timeout occurs during operation
79 @retval EFI_SUCCESS Reset HECI queue succeed
80 **/
81 typedef EFI_STATUS (EFIAPI *HECI_CONTROL_RESET) (
82 IN HECI_CONTROL *This,
83 IN UINT32 HeciPchId,
84 IN OUT UINT32 *Timeout
85 );
86
87 /**
88 Send request message to HECI queue, wait for response if needed.
89
90 This function writes one message to HECI queue and - if receive buffer
91 was provided and timeout is greater than zero - waits for response message.
92 The request can be retried if Retries > 0 (0 means one attempt, no retry),
93 but if retries are requested, the pReqMsg and pRspMsg pointers must point
94 to different buffers. This is required to make sure request is unchanged.
95 Size of receive message buffer is given in bytes in (*RspLen) on input.
96 On exit (*RspLen) provides the number of bytes written to the message
97 buffer. If buffer is too short the message is truncated.
98
99 @param[in] This HeciControl instance
100 @param[in] HeciPchId PchId we want to communicate with 0..N
101 HECI_DEFAULT_PCH_ID Id is default and
102 HeciControl decides where to route communication
103 @param[in,out] Timeout On input timeout in us, on exit time left
104 @param[in] Retries The number of retries requested (0 => no retry)
105 @param[in] HostAddress Host address
106 @param[in] EngineAddress Engine (ME/IE) address
107 @param[in] ReqMsg Request message
108 @param[in] ReqLen Request message length in bytes
109 @param[out] RspMsg Buffer for the response message
110 @param[in,out] RspLen On input buffer size, on exit message, in bytes
111 @param[in,out] SendStatus Send operation status
112 @param[in,out] ReceiveStatus Receive operation status
113
114 @retval EFI_INVALID_PARAMETER Input parameters are invalid
115 @retval EFI_WRITE_PROTECTED Can't find suitable HECI Transport
116 Possible reason: HECI filter active
117 @retval EFI_DEVICE_ERROR HECI MBar can't be initialized
118 @retval EFI_TIMEOUT Timeout occurs during operation
119 @retval EFI_BAD_BUFFER_SIZE Message is too big
120 @retval EFI_SUCCESS Message request has been completed successfully
121 **/
122 typedef EFI_STATUS (EFIAPI *HECI_CONTROL_SEND_AND_RECEIVE) (
123 IN HECI_CONTROL *This,
124 IN UINT32 HeciPchId,
125 IN OUT UINT32 *Timeout,
126 IN UINT8 Retries,
127 IN UINT8 HostAddress,
128 IN UINT8 EngineAddress,
129 IN UINT32 *ReqMsg,
130 IN UINT32 ReqLen,
131 OUT UINT32 *RspMsg,
132 IN OUT UINT32 *RspLen,
133 IN OUT EFI_STATUS *SendStatus,
134 IN OUT EFI_STATUS *ReceiveStatus
135 );
136
137 /**
138 Write a message to HECI queue, if necessary perform fragmentation.
139
140 This function puts one message to HECI queue. If the message is longer than
141 HECI queue size and timeout is greater than zero the function will split
142 the message into several packets and wait for space in the queue to send all
143 packets/fragments. Each packet has HECI packet header added.
144
145 @param[in,out] This HeciControl instance
146 @param[in] HeciPchId PchId we want to communicate with 0..N
147 HECI_DEFAULT_PCH_ID Id is default and
148 HeciControl decides where to route communication
149 @param[in,out] Timeout On input timeout in us, on exit time left
150 @param[in] HostAddress Host address
151 @param[in] EngineAddress Engine (ME/IE) address
152 @param[in] MsgBody Body of the message to send
153 @param[in] MsgLen Length in bytes of the message to send
154
155 @retval EFI_INVALID_PARAMETER Input parameters are invalid
156 @retval EFI_WRITE_PROTECTED Can't find suitable HECI Transport
157 Possible reason: HECI filter active
158 @retval EFI_DEVICE_ERROR HECI MBar can't be initialized
159 @retval EFI_TIMEOUT Timeout occurs during operation
160 @retval EFI_BAD_BUFFER_SIZE Packet is bigger than queue length
161 @retval EFI_SUCCESS Message has been sent successfully
162 **/
163 typedef EFI_STATUS (EFIAPI *HECI_CONTROL_SEND) (
164 IN OUT HECI_CONTROL *This,
165 IN UINT32 HeciPchId,
166 IN OUT UINT32 *Timeout,
167 IN UINT8 HostAddress,
168 IN UINT8 EngineAddress,
169 IN UINT32 *MsgBody,
170 IN UINT32 MsgLen
171 );
172
173 /**
174 Read a message from HECI queue, if necessary perform reassembly.
175
176 This function reads one message from HECI queue. If the message is
177 fragmented and timeout is greater than zero the function will wait for
178 subsequent packets (fragments) until full message is completed.
179
180 @param[in,out] This HeciControl instance
181 @param[in] HeciPchId PchId we want to communicate with 0..N
182 HECI_DEFAULT_PCH_ID Id is default and
183 HeciControl decides where to route communication
184 @param[in,out] Timeout On input timeout in us, on exit time left
185 @param[out] HostAddress Host address
186 @param[out] EngineAddress Engine (ME/IE) address
187 @param[out] MsgBody Body of the message to send
188 @param[in,out] MsgLen On input buffer size, on exit message body size in bytes
189
190 @retval EFI_INVALID_PARAMETER Input parameters are invalid
191 @retval EFI_WRITE_PROTECTED Can't find suitable HECI Transport
192 @retval EFI_DEVICE_ERROR HECI MBar can't be initialized
193 @retval EFI_TIMEOUT Timeout occurs during operation
194 @retval EFI_BAD_BUFFER_SIZE Message exceeds buffer size
195 @retval EFI_SUCCESS Message has been received successfully
196 **/
197 typedef EFI_STATUS (EFIAPI *HECI_CONTROL_RECEIVE) (
198 IN OUT HECI_CONTROL *This,
199 IN UINT32 HeciPchId,
200 IN OUT UINT32 *Timeout,
201 OUT UINT8 *HostAddress,
202 OUT UINT8 *EngineAddress,
203 OUT UINT32 *MsgBody,
204 IN OUT UINT32 *MsgLen
205 );
206
207 /**
208 Read HECI Firmware status
209
210 This function reads HECI firmware status from given PCH and HECI interface
211
212 @param[in] This HeciControl instance
213 @param[in] HeciNumber Heci number to firmware status read [1..4]
214 @param[in] FilterFunction Heci filtering function to be installed
215 @param[in,out] FirmwareStatus Pointer to returned firmware status
216
217 @retval EFI_SUCCESS Returned valid firmware status
218 @retval EFI_INVALID_PARAMETER Input parameters are invalid
219 @retval EFI_DEVICE_ERROR Error occurred
220 **/
221 typedef EFI_STATUS (EFIAPI *HECI_CONTROL_READ_FIRMWARE_STATUS) (
222 IN HECI_CONTROL *This,
223 IN UINT32 HeciPchId,
224 IN UINT8 HeciNumber,
225 IN OUT UINT32 *FirmwareStatus
226 );
227
228 /**
229 EFI protocol for ME-UEFI FW communication over HECI.
230
231 This protocol defines operations for communication with ME using HECI
232 (Host Embedded Controller Interface). There are more HECI functions in
233 ME device on PCI. HECI is designated for ME-UEFI FW boot flow communication.
234 **/
235 typedef struct _HECI_CONTROL_ {
236 HECI_CONTROL_SEND_AND_RECEIVE HeciSendAndReceive; /// < Send HECI message and receive Ack
237 HECI_CONTROL_SEND HeciSend; /// < Send HECI message
238 HECI_CONTROL_RECEIVE HeciReceive; /// < Receive HECI message
239 HECI_CONTROL_RESET HeciReset; /// < Reset HECI interface
240 HECI_CONTROL_READ_FIRMWARE_STATUS HeciFirmwareStatus; /// < Reads HECI Firmware Status
241 } HECI_CONTROL;
242
243 #endif // _HECI_CONTROL_PROTOCOL_H_
244
HECI_CONTROL_RESET
EFI_STATUS(* HECI_CONTROL_RESET)(IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout)
Reset HECI queue.
Definition: HeciControlProtocol.h:81
HECI_CONTROL_READ_FIRMWARE_STATUS
EFI_STATUS(* HECI_CONTROL_READ_FIRMWARE_STATUS)(IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN UINT8 HeciNumber, IN OUT UINT32 *FirmwareStatus)
Read HECI Firmware status.
Definition: HeciControlProtocol.h:221
_HECI_CONTROL_::HeciReceive
HECI_CONTROL_RECEIVE HeciReceive
< Send HECI message
Definition: HeciControlProtocol.h:238
HECI_CONTROL_SEND
EFI_STATUS(* HECI_CONTROL_SEND)(IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *MsgBody, IN UINT32 MsgLen)
Write a message to HECI queue, if necessary perform fragmentation.
Definition: HeciControlProtocol.h:163
_HECI_CONTROL_::HeciReset
HECI_CONTROL_RESET HeciReset
< Receive HECI message
Definition: HeciControlProtocol.h:239
HECI_CONTROL_RECEIVE
EFI_STATUS(* HECI_CONTROL_RECEIVE)(IN OUT HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, OUT UINT8 *HostAddress, OUT UINT8 *EngineAddress, OUT UINT32 *MsgBody, IN OUT UINT32 *MsgLen)
Read a message from HECI queue, if necessary perform reassembly.
Definition: HeciControlProtocol.h:197
gHeciControlProtocolGuid
EFI_GUID gHeciControlProtocolGuid
ME HECI Protocol GUID This protocol provides an interface to communicate with Intel ME over HECI func...
HECI_CONTROL
struct _HECI_CONTROL_ HECI_CONTROL
EFI protocol for ME-UEFI FW communication over HECI.
Definition: HeciControlProtocol.h:58
_HECI_CONTROL_
EFI protocol for ME-UEFI FW communication over HECI.
Definition: HeciControlProtocol.h:235
_HECI_CONTROL_::HeciFirmwareStatus
HECI_CONTROL_READ_FIRMWARE_STATUS HeciFirmwareStatus
< Reset HECI interface
Definition: HeciControlProtocol.h:240
HECI_CONTROL_SEND_AND_RECEIVE
EFI_STATUS(* HECI_CONTROL_SEND_AND_RECEIVE)(IN HECI_CONTROL *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 Retries, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *ReqMsg, IN UINT32 ReqLen, OUT UINT32 *RspMsg, IN OUT UINT32 *RspLen, IN OUT EFI_STATUS *SendStatus, IN OUT EFI_STATUS *ReceiveStatus)
Send request message to HECI queue, wait for response if needed.
Definition: HeciControlProtocol.h:122
_HECI_CONTROL_::HeciSend
HECI_CONTROL_SEND HeciSend
< Send HECI message and receive Ack
Definition: HeciControlProtocol.h:237
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciFlowProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
HeciFlowProtocol.h File Reference

HECI Flow Protocol. More...

Go to the source code of this file.

Detailed Description

HECI Flow Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HeciFlowProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciFlowProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
HeciFlowProtocol.h
Go to the documentation of this file.
1 /** @file
2 HECI Flow Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HECI_FLOW_PROTOCOL_H
36 #define _HECI_FLOW_PROTOCOL_H
37
38 typedef struct _HECI_FLOW_PROTOCOL HECI_FLOW_PROTOCOL;
39
40 typedef
41 EFI_STATUS
42 (EFIAPI *HECI_FLOW_SEND_AND_RECEIVE) (
43 IN HECI_DEVICE HeciDev,
44 IN OUT VOID *Message,
45 IN UINT32 Length,
46 IN OUT UINT32 *RecLength,
47 IN CONST EFI_GUID *Guid
48 );
49
50 typedef
51 EFI_STATUS
52 (EFIAPI *HECI_FLOW_SEND) (
53 IN HECI_DEVICE HeciDev,
54 IN OUT VOID *Message,
55 IN OUT UINT32 Length,
56 IN CONST EFI_GUID *Guid
57 );
58
59 /*
60 This protocol allows sending HECI messages, over a connection with flow control, to CSME clients
61 identified by GUID rather than hardcoded address. This simple API wraps all connection-related complexity,
62 such as search for GUIDs, establishing connections, flow control token management and disconnection.
63 HECI_FLOW_PROTOCOL is an extension of HECI_PROTOCOL. They can be used together, at the same time.
64 Limitation:
65 Except for flow control tokens, no response is expected for Send and only a single response message is expected for
66 SendAndReceive. It is not allowed to use HECI_FLOW_PROTOCOL to create connections that will result in CSME sending
67 more messages than that. Unexpected response message will not be consumed and will jam the underlying HECI_PROTOCOL.
68 */
69 struct _HECI_FLOW_PROTOCOL {
70 HECI_FLOW_SEND_AND_RECEIVE SendAndReceive; ///< Send HECI message with flow control and wait for response
71 HECI_FLOW_SEND Send; ///< Send HECI message with flow control, do not expect response
72 };
73
74 extern EFI_GUID gHeciFlowProtocolGuid;
75
76 #endif // _HECI_FLOW_PROTOCOL_H
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros | Variables
HeciPpi.h File Reference

PEI Heci PPI. More...

#include <Protocol/HeciProtocol.h>
Include dependency graph for HeciPpi.h:

Go to the source code of this file.

Classes

struct _HECI_PPI
HECI PPI The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem in PEI phase. More...

Macros

#define HECI_PPI_REVISION 1
Revision.

Variables

EFI_GUID gHeciPpiGuid
HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.

Detailed Description

PEI Heci PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HeciPpi.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
HeciPpi.h
Go to the documentation of this file.
1 /** @file
2 PEI Heci PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HECI_PPI_H_
36 #define _HECI_PPI_H_
37
38 #include <Protocol/HeciProtocol.h>
39
40 ///
41 /// HECI PPI GUID
42 /// This PPI provides an interface to communicate with Intel ME in PEI phase
43 ///
44
45 extern EFI_GUID gHeciPpiGuid;
46
47 ///
48 /// Revision
49 ///
50 #define HECI_PPI_REVISION 1
51
52 typedef struct _HECI_PPI HECI_PPI;
53
54 ///
55 /// HECI PPI
56 /// The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem
57 /// in PEI phase
58 ///
59 struct _HECI_PPI {
60 HECI_SENDWACK SendwAck; ///< Send HECI message and wait for respond
61 HECI_READ_MESSAGE ReadMsg; ///< Read message from HECI
62 HECI_SEND_MESSAGE SendMsg; ///< Send message to HECI
63 HECI_INIT InitializeHeci; ///< Init HECI
64 HECI_GET_ME_STATUS GetMeStatus; ///< Get Intel ME Status register
65 HECI_GET_ME_MODE GetMeMode; ///< Get Intel ME mode
66 };
67
68 #endif
HECI_GET_ME_STATUS
EFI_STATUS(* HECI_GET_ME_STATUS)(OUT UINT32 *Status)
Get an abstract Intel ME State from Firmware Status Register.
Definition: HeciProtocol.h:216
HECI_GET_ME_MODE
EFI_STATUS(* HECI_GET_ME_MODE)(OUT UINT32 *Mode)
Get an abstract ME operation mode from firmware status register.
Definition: HeciProtocol.h:234
HECI_READ_MESSAGE
EFI_STATUS(* HECI_READ_MESSAGE)(IN HECI_DEVICE HeciDev, IN UINT32 Blocking, IN UINT32 *MessageBody, IN OUT UINT32 *Length)
Read the HECI Message from Intel ME with size in Length into buffer MessageBody.
Definition: HeciProtocol.h:99
_HECI_PPI::ReadMsg
HECI_READ_MESSAGE ReadMsg
Read message from HECI.
Definition: HeciPpi.h:61
_HECI_PPI::GetMeStatus
HECI_GET_ME_STATUS GetMeStatus
Get Intel ME Status register.
Definition: HeciPpi.h:64
_HECI_PPI
HECI PPI The interface functions are for sending/receiving HECI messages between host and Intel ME su...
Definition: HeciPpi.h:59
_HECI_PPI::GetMeMode
HECI_GET_ME_MODE GetMeMode
Get Intel ME mode.
Definition: HeciPpi.h:65
gHeciPpiGuid
EFI_GUID gHeciPpiGuid
HECI PPI GUID This PPI provides an interface to communicate with Intel ME in PEI phase.
_HECI_PPI::InitializeHeci
HECI_INIT InitializeHeci
Init HECI.
Definition: HeciPpi.h:63
HECI_INIT
EFI_STATUS(* HECI_INIT)(IN HECI_DEVICE HeciDev)
Initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host E...
Definition: HeciProtocol.h:160
_HECI_PPI::SendwAck
HECI_SENDWACK SendwAck
Send HECI message and wait for respond.
Definition: HeciPpi.h:60
HECI_SENDWACK
EFI_STATUS(* HECI_SENDWACK)(IN HECI_DEVICE HeciDev, IN OUT UINT32 *Message, IN OUT UINT32 Length, IN OUT UINT32 *RecLength, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message through the HECI circular buffer and waits for the corresponding ACK messa...
Definition: HeciProtocol.h:69
HeciProtocol.h
HECI Protocol.
HECI_SEND_MESSAGE
EFI_STATUS(* HECI_SEND_MESSAGE)(IN HECI_DEVICE HeciDev, IN UINT32 *Message, IN UINT32 Length, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message (of any length) through the HECI circular buffer.
Definition: HeciProtocol.h:122
_HECI_PPI::SendMsg
HECI_SEND_MESSAGE SendMsg
Send message to HECI.
Definition: HeciPpi.h:62
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
HeciProtocol.h File Reference

HECI Protocol. More...

#include <MeState.h>
#include <Register/MeRegs.h>
Include dependency graph for HeciProtocol.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _HECI_PROTOCOL
HECI protocol provided for DXE phase The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem. More...

Typedefs

typedef struct _HECI_PROTOCOL | HECI_PROTOCOL
HECI protocol provided for DXE phase This protocol provides an interface to communicate with Intel ME subsystem via HECI.
typedef EFI_STATUS(* | HECI_SENDWACK) (IN HECI_DEVICE HeciDev, IN OUT UINT32 *Message, IN OUT UINT32 Length, IN OUT UINT32 *RecLength, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message through the HECI circular buffer and waits for the corresponding ACK message. More...
typedef EFI_STATUS(* | HECI_READ_MESSAGE) (IN HECI_DEVICE HeciDev, IN UINT32 Blocking, IN UINT32 *MessageBody, IN OUT UINT32 *Length)
Read the HECI Message from Intel ME with size in Length into buffer MessageBody. More...
typedef EFI_STATUS(* | HECI_SEND_MESSAGE) (IN HECI_DEVICE HeciDev, IN UINT32 *Message, IN UINT32 Length, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message (of any length) through the HECI circular buffer. More...
typedef EFI_STATUS(* | HECI_RESET) (IN HECI_DEVICE HeciDev)
Reset the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host Embedded Controller Interface Hardware Programming Specification (HPS) More...
typedef EFI_STATUS(* | HECI_INIT) (IN HECI_DEVICE HeciDev)
Initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host Embedded Controller Interface Hardware Programming Specification (HPS). More...
typedef EFI_STATUS(* | HECI_REINIT) (IN HECI_DEVICE HeciDev)
Re-initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine. More...
typedef EFI_STATUS(* | HECI_RESET_WAIT) (IN HECI_DEVICE HeciDev, IN UINT32 Delay)
Reset Intel ME and timeout if Ready is not set after Delay timeout. More...
typedef EFI_STATUS(* | HECI_GET_ME_STATUS) (OUT UINT32 *Status)
Get an abstract Intel ME State from Firmware Status Register. More...
typedef EFI_STATUS(* | HECI_GET_ME_MODE) (OUT UINT32 *Mode)
Get an abstract ME operation mode from firmware status register. More...

Detailed Description

HECI Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HeciProtocol.h.

Typedef Documentation

◆ HECI_GET_ME_MODE

typedef EFI_STATUS( * HECI_GET_ME_MODE) (OUT UINT32 *Mode)

Get an abstract ME operation mode from firmware status register.

This is used to control BIOS flow for different Intel ME functions.

Parameters
[out] MeMode Pointer for ME Mode report,
See also
MeState.h - Abstract ME Mode definitions.
Return values
EFI_SUCCESS | MeMode copied
EFI_INVALID_PARAMETER | Pointer of MeMode is invalid

Definition at line 233 of file HeciProtocol.h.

◆ HECI_GET_ME_STATUS

typedef EFI_STATUS( * HECI_GET_ME_STATUS) (OUT UINT32 *Status)

Get an abstract Intel ME State from Firmware Status Register.

This is used to control BIOS flow for different Intel ME functions. The ME status information is obtained by sending HECI messages to Intel ME and is used both by the platform code and reference code. This will optimize boot time because system BIOS only sends each HECI message once. It is recommended to send the HECI messages to Intel ME only when ME mode is normal (Except for HMRFPO Disable Message) and ME State is NORMAL or RECOVERY (Suitable for AT and Kernel Messaging only).

Parameters
[out] MeStatus Pointer for abstract status report
See also
MeState.h - Abstract ME status definitions.
Return values
EFI_SUCCESS | MeStatus copied
EFI_INVALID_PARAMETER | Pointer of MeStatus is invalid

Definition at line 215 of file HeciProtocol.h.

◆ HECI_INIT

typedef EFI_STATUS( * HECI_INIT) (IN HECI_DEVICE HeciDev)

Initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host Embedded Controller Interface Hardware Programming Specification (HPS).

Determines if the HECI device is present and, if present, initializes it for use by the BIOS.

Parameters
[in] HeciDev The HECI device to be accessed.
Return values
EFI_SUCCESS | HECI device is present and initialized
EFI_TIMEOUT | HECI does not return the buffer before timeout

Definition at line 159 of file HeciProtocol.h.

◆ HECI_READ_MESSAGE

typedef EFI_STATUS( * HECI_READ_MESSAGE) (IN HECI_DEVICE HeciDev, IN UINT32 Blocking, IN UINT32 *MessageBody, IN OUT UINT32 *Length)

Read the HECI Message from Intel ME with size in Length into buffer MessageBody.

Set Blocking to BLOCKING and code will wait until one message packet is received. When set to NON_BLOCKING, if the circular buffer is empty at the time, the code will not wait for the message packet. This can only be used after sending a message through HECI first.

Parameters
[in] | HeciDev | The HECI device to be accessed.
[in] | Blocking | Used to determine if the read is BLOCKING or NON_BLOCKING.
[in] | *MessageBody | Pointer to a buffer used to receive a message.
[in,out] | *Length | Pointer to the length of the buffer on input and the length of the message on return. (in bytes)
Return values
EFI_SUCCESS | One message packet read.
EFI_DEVICE_ERROR | Failed to initialize HECI or zero-length message packet read
EFI_TIMEOUT | HECI is not ready for communication
EFI_BUFFER_TOO_SMALL | The caller's buffer was not large enough
EFI_UNSUPPORTED | Current ME mode doesn't support this message through this HECI

Definition at line 98 of file HeciProtocol.h.

◆ HECI_REINIT

typedef EFI_STATUS( * HECI_REINIT) (IN HECI_DEVICE HeciDev)

Re-initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine.

  • Host Embedded Controller Interface Hardware Programming Specification (HPS). Heci Re-initializes it for Host
Parameters
[in] HeciDev The HECI device to be accessed.
Return values
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_STATUS | Status code returned by ResetHeciInterface

Definition at line 175 of file HeciProtocol.h.

◆ HECI_RESET

typedef EFI_STATUS( * HECI_RESET) (IN HECI_DEVICE HeciDev)

Reset the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host Embedded Controller Interface Hardware Programming Specification (HPS)

Parameters
[in] HeciDev The HECI device to be accessed.
Return values
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_SUCCESS | Interface reset

Definition at line 141 of file HeciProtocol.h.

◆ HECI_RESET_WAIT

typedef EFI_STATUS( * HECI_RESET_WAIT) (IN HECI_DEVICE HeciDev, IN UINT32 Delay)

Reset Intel ME and timeout if Ready is not set after Delay timeout.

Parameters
[in] | HeciDev | The HECI device to be accessed.
[in] | Delay | Timeout value in microseconds
Return values
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_SUCCESS | Me is ready

Definition at line 190 of file HeciProtocol.h.

◆ HECI_SEND_MESSAGE

typedef EFI_STATUS( * HECI_SEND_MESSAGE) (IN HECI_DEVICE HeciDev, IN UINT32 *Message, IN UINT32 Length, IN UINT8 HostAddress, IN UINT8 MEAddress)

Function sends one message (of any length) through the HECI circular buffer.

Parameters
[in] | HeciDev | The HECI device to be accessed.
[in] | *Message | Pointer to the message data to be sent.
[in] | Length | Length of the message in bytes.
[in] | HostAddress | The address of the host processor.
[in] | MEAddress | Address of the ME subsystem the message is being sent to.
Return values
EFI_SUCCESS | One message packet sent.
EFI_DEVICE_ERROR | Failed to initialize HECI
EFI_TIMEOUT | HECI is not ready for communication
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI

Definition at line 121 of file HeciProtocol.h.

◆ HECI_SENDWACK

typedef EFI_STATUS( * HECI_SENDWACK) (IN HECI_DEVICE HeciDev, IN OUT UINT32 *Message, IN OUT UINT32 Length, IN OUT UINT32 *RecLength, IN UINT8 HostAddress, IN UINT8 MEAddress)

Function sends one message through the HECI circular buffer and waits for the corresponding ACK message.

Parameters
[in] | HeciDev | The HECI device to be accessed.
[in,out] | *Message | Pointer to the message buffer.
[in] | Length | Length of the message in bytes.
[in,out] | *RecLength | Length of the message response in bytes.
[in] | HostAddress | Address of the sending entity.
[in] | MEAddress | Address of the ME entity that should receive the message.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI

Definition at line 68 of file HeciProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
HeciProtocol.h
Go to the documentation of this file.
1 /** @file
2 HECI Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HECI_PROTOCOL_H
36 #define _HECI_PROTOCOL_H
37
38 #include <MeState.h>
39 #include <Register/MeRegs.h>
40
41 ///
42 /// HECI protocol provided for DXE phase
43 /// This protocol provides an interface to communicate with Intel ME subsystem via HECI
44 ///
45 typedef struct _HECI_PROTOCOL HECI_PROTOCOL;
46
47 #define NON_BLOCKING 0
48 #define BLOCKING 1
49
50 /**
51 Function sends one message through the HECI circular buffer and waits
52 for the corresponding ACK message.
53
54 @param[in] HeciDev The HECI device to be accessed.
55 @param[in, out] *Message Pointer to the message buffer.
56 @param[in] Length Length of the message in bytes.
57 @param[in, out] *RecLength Length of the message response in bytes.
58 @param[in] HostAddress Address of the sending entity.
59 @param[in] MEAddress Address of the ME entity that should receive the message.
60
61 @retval EFI_SUCCESS Command succeeded
62 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
63 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
64 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
65 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
66 **/
67 typedef
68 EFI_STATUS
69 (EFIAPI *HECI_SENDWACK) (
70 IN HECI_DEVICE HeciDev,
71 IN OUT UINT32 *Message,
72 IN OUT UINT32 Length,
73 IN OUT UINT32 *RecLength,
74 IN UINT8 HostAddress,
75 IN UINT8 MEAddress
76 );
77
78 /**
79 Read the HECI Message from Intel ME with size in Length into
80 buffer MessageBody. Set Blocking to BLOCKING and code will
81 wait until one message packet is received. When set to
82 NON_BLOCKING, if the circular buffer is empty at the time, the
83 code will not wait for the message packet.
84 This can only be used after sending a message through HECI first.
85
86 @param[in] HeciDev The HECI device to be accessed.
87 @param[in] Blocking Used to determine if the read is BLOCKING or NON_BLOCKING.
88 @param[in] *MessageBody Pointer to a buffer used to receive a message.
89 @param[in, out] *Length Pointer to the length of the buffer on input and the length of the message on return. (in bytes)
90
91 @retval EFI_SUCCESS One message packet read.
92 @retval EFI_DEVICE_ERROR Failed to initialize HECI or zero-length message packet read
93 @retval EFI_TIMEOUT HECI is not ready for communication
94 @retval EFI_BUFFER_TOO_SMALL The caller's buffer was not large enough
95 @retval EFI_UNSUPPORTED Current ME mode doesn't support this message through this HECI
96 **/
97 typedef
98 EFI_STATUS
99 (EFIAPI *HECI_READ_MESSAGE) (
100 IN HECI_DEVICE HeciDev,
101 IN UINT32 Blocking,
102 IN UINT32 *MessageBody,
103 IN OUT UINT32 *Length
104 );
105
106 /**
107 Function sends one message (of any length) through the HECI circular buffer.
108
109 @param[in] HeciDev The HECI device to be accessed.
110 @param[in] *Message Pointer to the message data to be sent.
111 @param[in] Length Length of the message in bytes.
112 @param[in] HostAddress The address of the host processor.
113 @param[in] MEAddress Address of the ME subsystem the message is being sent to.
114
115 @retval EFI_SUCCESS One message packet sent.
116 @retval EFI_DEVICE_ERROR Failed to initialize HECI
117 @retval EFI_TIMEOUT HECI is not ready for communication
118 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
119 **/
120 typedef
121 EFI_STATUS
122 (EFIAPI *HECI_SEND_MESSAGE) (
123 IN HECI_DEVICE HeciDev,
124 IN UINT32 *Message,
125 IN UINT32 Length,
126 IN UINT8 HostAddress,
127 IN UINT8 MEAddress
128 );
129
130 /**
131 Reset the HECI Controller with algorithm defined in the RS -
132 Intel(R) Management Engine - Host Embedded Controller
133 Interface Hardware Programming Specification (HPS)
134
135 @param[in] HeciDev The HECI device to be accessed.
136
137 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
138 @retval EFI_SUCCESS Interface reset
139 **/
140 typedef
141 EFI_STATUS
142 (EFIAPI *HECI_RESET) (
143 IN HECI_DEVICE HeciDev
144 );
145
146 /**
147 Initialize the HECI Controller with algorithm defined in the
148 RS - Intel(R) Management Engine - Host Embedded Controller
149 Interface Hardware Programming Specification (HPS).
150 Determines if the HECI device is present and, if present,
151 initializes it for use by the BIOS.
152
153 @param[in] HeciDev The HECI device to be accessed.
154
155 @retval EFI_SUCCESS HECI device is present and initialized
156 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
157 **/
158 typedef
159 EFI_STATUS
160 (EFIAPI *HECI_INIT) (
161 IN HECI_DEVICE HeciDev
162 );
163
164 /**
165 Re-initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine
166 - Host Embedded Controller Interface Hardware Programming Specification (HPS).
167 Heci Re-initializes it for Host
168
169 @param[in] HeciDev The HECI device to be accessed.
170
171 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
172 @retval EFI_STATUS Status code returned by ResetHeciInterface
173 **/
174 typedef
175 EFI_STATUS
176 (EFIAPI *HECI_REINIT) (
177 IN HECI_DEVICE HeciDev
178 );
179
180 /**
181 Reset Intel ME and timeout if Ready is not set after Delay timeout
182
183 @param[in] HeciDev The HECI device to be accessed.
184 @param[in] Delay Timeout value in microseconds
185
186 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
187 @retval EFI_SUCCESS Me is ready
188 **/
189 typedef
190 EFI_STATUS
191 (EFIAPI *HECI_RESET_WAIT) (
192 IN HECI_DEVICE HeciDev,
193 IN UINT32 Delay
194 );
195
196 /**
197 Get an abstract Intel ME State from Firmware Status Register.
198 This is used to control BIOS flow for different Intel ME
199 functions.
200 The ME status information is obtained by sending HECI messages
201 to Intel ME and is used both by the platform code and
202 reference code. This will optimize boot time because system
203 BIOS only sends each HECI message once. It is recommended to
204 send the HECI messages to Intel ME only when ME mode is normal
205 (Except for HMRFPO Disable Message) and ME State is NORMAL or
206 RECOVERY (Suitable for AT and Kernel Messaging only).
207
208 @param[out] MeStatus Pointer for abstract status report
209 @see MeState.h - Abstract ME status definitions.
210
211 @retval EFI_SUCCESS MeStatus copied
212 @retval EFI_INVALID_PARAMETER Pointer of MeStatus is invalid
213 **/
214 typedef
215 EFI_STATUS
216 (EFIAPI *HECI_GET_ME_STATUS) (
217 OUT UINT32 *Status
218 )
219 ;
220
221 /**
222 Get an abstract ME operation mode from firmware status
223 register. This is used to control BIOS flow for different
224 Intel ME functions.
225
226 @param[out] MeMode Pointer for ME Mode report,
227 @see MeState.h - Abstract ME Mode definitions.
228
229 @retval EFI_SUCCESS MeMode copied
230 @retval EFI_INVALID_PARAMETER Pointer of MeMode is invalid
231 **/
232 typedef
233 EFI_STATUS
234 (EFIAPI *HECI_GET_ME_MODE) (
235 OUT UINT32 *Mode
236 );
237
238 /**
239 HECI protocol provided for DXE phase
240 The interface functions are for sending/receiving HECI messages between host and Intel ME subsystem.
241 There is also support to control HECI Initialization and get Intel ME status.
242 **/
243 struct _HECI_PROTOCOL {
244 HECI_SENDWACK SendwAck; ///< Send HECI message and wait for respond
245 HECI_READ_MESSAGE ReadMsg; ///< Receive HECI message
246 HECI_SEND_MESSAGE SendMsg; ///< Send HECI message
247 HECI_RESET ResetHeci; ///< Reset HECI device
248 HECI_INIT InitHeci; ///< Initialize HECI device
249 HECI_RESET_WAIT MeResetWait; ///< Intel ME Reset Wait Timer
250 HECI_REINIT ReInitHeci; ///< Re-initialize HECI
251 HECI_GET_ME_STATUS GetMeStatus; ///< Get Intel ME Status register
252 HECI_GET_ME_MODE GetMeMode; ///< Get Intel ME mode
253 };
254
255 extern EFI_GUID gHeciProtocolGuid;
256
257 #endif // _EFI_HECI_H
_HECI_PROTOCOL::ReInitHeci
HECI_REINIT ReInitHeci
Re-initialize HECI.
Definition: HeciProtocol.h:250
HECI_GET_ME_STATUS
EFI_STATUS(* HECI_GET_ME_STATUS)(OUT UINT32 *Status)
Get an abstract Intel ME State from Firmware Status Register.
Definition: HeciProtocol.h:216
HECI_REINIT
EFI_STATUS(* HECI_REINIT)(IN HECI_DEVICE HeciDev)
Re-initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine.
Definition: HeciProtocol.h:176
HECI_GET_ME_MODE
EFI_STATUS(* HECI_GET_ME_MODE)(OUT UINT32 *Mode)
Get an abstract ME operation mode from firmware status register.
Definition: HeciProtocol.h:234
HECI_READ_MESSAGE
EFI_STATUS(* HECI_READ_MESSAGE)(IN HECI_DEVICE HeciDev, IN UINT32 Blocking, IN UINT32 *MessageBody, IN OUT UINT32 *Length)
Read the HECI Message from Intel ME with size in Length into buffer MessageBody.
Definition: HeciProtocol.h:99
_HECI_PROTOCOL::InitHeci
HECI_INIT InitHeci
Initialize HECI device.
Definition: HeciProtocol.h:248
_HECI_PROTOCOL::ResetHeci
HECI_RESET ResetHeci
Reset HECI device.
Definition: HeciProtocol.h:247
HECI_RESET
EFI_STATUS(* HECI_RESET)(IN HECI_DEVICE HeciDev)
Reset the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host Embedd...
Definition: HeciProtocol.h:142
HECI_RESET_WAIT
EFI_STATUS(* HECI_RESET_WAIT)(IN HECI_DEVICE HeciDev, IN UINT32 Delay)
Reset Intel ME and timeout if Ready is not set after Delay timeout.
Definition: HeciProtocol.h:191
_HECI_PROTOCOL::GetMeStatus
HECI_GET_ME_STATUS GetMeStatus
Get Intel ME Status register.
Definition: HeciProtocol.h:251
_HECI_PROTOCOL::SendwAck
HECI_SENDWACK SendwAck
Send HECI message and wait for respond.
Definition: HeciProtocol.h:244
MeRegs.h
Register definition for ME Devices.
_HECI_PROTOCOL::ReadMsg
HECI_READ_MESSAGE ReadMsg
Receive HECI message.
Definition: HeciProtocol.h:245
MeState.h
Register Definitions for Me States.
_HECI_PROTOCOL::GetMeMode
HECI_GET_ME_MODE GetMeMode
Get Intel ME mode.
Definition: HeciProtocol.h:252
HECI_INIT
EFI_STATUS(* HECI_INIT)(IN HECI_DEVICE HeciDev)
Initialize the HECI Controller with algorithm defined in the RS - Intel(R) Management Engine - Host E...
Definition: HeciProtocol.h:160
_HECI_PROTOCOL
HECI protocol provided for DXE phase The interface functions are for sending/receiving HECI messages ...
Definition: HeciProtocol.h:243
HECI_SENDWACK
EFI_STATUS(* HECI_SENDWACK)(IN HECI_DEVICE HeciDev, IN OUT UINT32 *Message, IN OUT UINT32 Length, IN OUT UINT32 *RecLength, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message through the HECI circular buffer and waits for the corresponding ACK messa...
Definition: HeciProtocol.h:69
_HECI_PROTOCOL::SendMsg
HECI_SEND_MESSAGE SendMsg
Send HECI message.
Definition: HeciProtocol.h:246
_HECI_PROTOCOL::MeResetWait
HECI_RESET_WAIT MeResetWait
Intel ME Reset Wait Timer.
Definition: HeciProtocol.h:249
HECI_SEND_MESSAGE
EFI_STATUS(* HECI_SEND_MESSAGE)(IN HECI_DEVICE HeciDev, IN UINT32 *Message, IN UINT32 Length, IN UINT8 HostAddress, IN UINT8 MEAddress)
Function sends one message (of any length) through the HECI circular buffer.
Definition: HeciProtocol.h:122
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciRegs.h File Reference

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Classes | Macros
HeciRegs.h File Reference

Register Definitions for HECI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | HECI_CONTROL_STATUS_REGISTER
Register definitions. More...
union | HECI_FWS_REGISTER
HFSTS1, offset 40h. More...
union | HECI_GS_SHDW_REGISTER
HFSTS2, offset 48h. More...
union | HECI_FW_STS3_REGISTER
HFSTS3, offset 60h. More...
union | HECI_FW_STS4_REGISTER
HFSTS4, offset 64h. More...
union | HECI_FW_STS5_REGISTER
HFSTS5, offset 68h. More...
union | HECI_FW_STS6_REGISTER
HFSTS6, offset 6Ch. More...

Macros

#define | H_CB_WW 0x00
HECIMBAR register definition.
#define | R_HERS 0xCBC
Host side access of CSME Extended Registers. More...
#define | R_HER_BASE 0xC00
Host side access CSME Extended Register Base Address to get SHA384 Data (48 bytes) from DWord registers HECI1_HER1 (0xCC0) to HECI1_HER12 (0xCEC)

Detailed Description

Register Definitions for HECI.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HeciRegs.h.

Macro Definition Documentation

◆ R_HERS

#define R_HERS 0xCBC

Host side access of CSME Extended Registers.

Host side access CSME Extended Register Status

Definition at line 54 of file HeciRegs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HeciRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
HeciRegs.h
Go to the documentation of this file.
1 /** @file
2 Register Definitions for HECI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HECI_REGS_H_
36 #define _HECI_REGS_H_
37
38 #define HECI_BUS ME_BUS
39 #define HECI_DEV ME_DEVICE_NUMBER
40 #define HECI_FUN HECI_FUNCTION_NUMBER
41
42 ///
43 /// HECIMBAR register definition
44 ///
45 #define H_CB_WW 0x00
46 #define H_CSR 0x04
47 #define ME_CB_RW 0x08
48 #define ME_CSR_HA 0x0C
49 #define D0I3C 0x800
50
51 ///
52 /// Host side access of CSME Extended Registers
53 ///
54 #define R_HERS 0xCBC ///< Host side access CSME Extended Register Status
55 #define R_HER_BASE 0xC00 ///< Host side access CSME Extended Register Base Address to get SHA384 Data (48 bytes) from DWord registers HECI1_HER1 (0xCC0) to HECI1_HER12 (0xCEC)
56
57 #pragma pack(1)
58 ///
59 /// Register definitions
60 ///
61
62 ///
63 /// H_CSR - Host Control Status Register, offset 04h
64 /// ME_CSR_HA - ME Control Status Register (Host Access), offset 0Ch
65 ///
66 typedef union {
67 UINT32 Data;
68 struct {
69 UINT32 IntEnable : 1; ///< 0 - Host/ME Interrupt Enable
70 UINT32 IntStatus : 1; ///< 1 - Host/ME Interrupt Status
71 UINT32 IntGenerate : 1; ///< 2 - Host/ME Interrupt Generate
72 UINT32 Ready : 1; ///< 3 - Host/ME Ready
73 UINT32 Reset : 1; ///< 4 - Host/ME Reset
74 UINT32 Reserved : 3; ///< 7:5 - Reserved
75 UINT32 CBReadPointer : 8; ///< 15:8 - Host/ME Circular Buffer Read Pointer
76 UINT32 CBWritePointer : 8; ///< 23:16 - Host/ME Circular Buffer Write Pointer
77 UINT32 CBDepth : 8; ///< 31:24 - Host/ME Circular Buffer Depth
78 } Fields;
79 } HECI_CONTROL_STATUS_REGISTER;
80
81 ///
82 /// HFSTS1, offset 40h
83 ///
84 typedef union {
85 UINT32 ul;
86 struct {
87 UINT32 CurrentState : 4; ///< 0:3 - Current State
88 UINT32 SpiProtectionMode : 1; ///< 4 - SPI Protection Mode, 0 - Protected; 1 - UnProtected
89 UINT32 FptBad : 1; ///< 5 - FPT (Flash Partition Table) Bad
90 UINT32 MeOperationState : 3; ///< 6:8 - ME Operation State
91 UINT32 FwInitComplete : 1; ///< 9 - This bit is set when firmware has fully entered a stable state
92 UINT32 FtBupLdFlr : 1; ///< 10 - This bit is set when firmware is not able to load BRINGUP from the fault tolerant (FT) code
93 UINT32 FwUpdateInprogress : 1; ///< 11 - This bit is set when data migration is required during ME FW update process
94 UINT32 ErrorCode : 4; ///< 12:15 - Error Code
95 UINT32 MeOperationMode : 4; ///< 16:19 - Management Engine Current Operation Mode
96 UINT32 MeRstCnt : 4; ///< 20:23 - Number of ME Resets
97 UINT32 MeBootOptionsPresent : 1; ///< 24 - If this bit is set, an Boot Options is present
98 UINT32 InvokeEDebugMode : 1; ///< 25 - Invoke EDebug Mode
99 UINT32 BistTestState : 1; ///< 26 - This bit informs if BIST is starting or BIST is finished
100 UINT32 BistResetRequest : 1; ///< 27 - This bit informs if BIST Reset Request
101 UINT32 CurrentPowerSource : 2; ///< 28:29 - Current power source selection mode
102 UINT32 D3SupportValid : 1; ///< 30 - D3 support
103 UINT32 D0i3SupportValid : 1; ///< 31 - D0i3 support
104 } r;
105 } HECI_FWS_REGISTER;
106
107 ///
108 /// HFSTS2, offset 48h
109 ///
110 typedef union {
111 UINT32 ul;
112 struct {
113 UINT32 NftpLoadFailure : 1; ///< 0 - NFTP Load Failure Detection Field
114 UINT32 IccProgSts : 2; ///< 1:2 - ICC Prog STS
115 UINT32 InvokeMEBx : 1; ///< 3 - Invoke MEBX
116 UINT32 CpuReplacedSts : 1; ///< 4 - CPU Replaced STS
117 UINT32 Reserved : 1; ///< 5 - Reserved
118 UINT32 MfsFailure : 1; ///< 6 - MFS Failure
119 UINT32 WarmRstReqForDF : 1; ///< 7 - Warm Reset Required for Dynamic Fusing
120 UINT32 CpuReplacedValid : 1; ///< 8 - CPU Replaced Valid
121 UINT32 LowPowerState : 1; ///< 9 - Low Power State
122 UINT32 MePowerGating : 1; ///< 10 - ME Power Gating Indicator
123 UINT32 FwUpdIpu : 1; ///< 11 - FW Update IPU Needed
124 UINT32 FwUpdForcedSB : 1; ///< 12 - FW Update Forced Safe Boot
125 UINT32 Reserved2 : 1; ///< 13 - Reserved
126 UINT32 CseToDisabled : 1; ///< 14 - CSE is on the way to be disabled
127 UINT32 HeciListCh : 1; ///< 15 - HECI Listner Change
128 UINT32 ExtStatCode1 : 8; ///< 16:23 - EXT Status Code 1
129 UINT32 ExtStatCode2 : 4; ///< 24:27 - EXT Status Code 2
130 UINT32 InfPhaseCode : 4; ///< 31:28 - Infra. Phase code
131 } r;
132 } HECI_GS_SHDW_REGISTER;
133
134 ///
135 /// HFSTS3, offset 60h
136 ///
137 typedef union {
138 UINT32 ul;
139 struct {
140 UINT32 Reserved : 4; ///< 3:0 - Reserved
141 UINT32 FwSku : 3; ///< 6:4 - FW Sku
142 UINT32 Reserved2 : 4; ///< 10:7 - Reserved
143 UINT32 RpmcStatus : 3; ///< 13:11 - RPMC Status
144 UINT32 Reserved3 : 18; ///< 31:14 - Reserved
145 } r;
146 } HECI_FW_STS3_REGISTER;
147
148 ///
149 /// HFSTS4, offset 64h
150 ///
151 typedef union {
152 UINT32 ul;
153 struct {
154 UINT32 Reserved : 8; ///< 7:0 - Reserved
155 UINT32 dTpm12Deactivated : 1; ///< 8 - User Has Selected dTPM1.2 Deactivated
156 UINT32 FwInEnfFlow : 1; ///< 9 - FW is in ENF flow
157 UINT32 SxResumeType : 1; ///< 10 - Sx Resume Type, 0- S4, S5 or G3; 1 S3, deep S3 for Intel Rapid Start Tech.
158 UINT32 Reserved2 : 1; ///< 11 - Reserved
159 UINT32 AllTpmDisconnected : 1; ///< 12 - All TPMs Disconnected
160 UINT32 Reserved3 : 1; ///< 13 - Reserved
161 UINT32 BootGuardFwStsValid : 1; ///< 14 - Boot Guard FWSTS Valid
162 UINT32 BootGuardSelfTest : 1; ///< 15 - Boot Guard Self Test
163 UINT32 Reserved4 : 16; ///< 31:16 - Reserved
164 } r;
165 } HECI_FW_STS4_REGISTER;
166
167 ///
168 /// HFSTS5, offset 68h
169 ///
170 typedef union {
171 UINT32 ul;
172 struct {
173 UINT32 AcmActived : 1; ///< 0 - Boot Guard ACM Active STS, 0 - Unknown Boot Guard ACM status; 1 - Boot Guard ACM is active
174 UINT32 VLD : 1; ///< 1 - Valid Bit, 0 - HFSTS#5 Bits [7:2] are invalid, 1 - Valid.
175 UINT32 RCS : 1; ///< 2 - Result Code Source, 0 - Boot Guard ACM; 1 - CPU Microcode
176 UINT32 ESC : 5; ///< 7:3 - Error Status Code
177 UINT32 AcmDone : 1; ///< 8 - Boot Guard ACM DONE STS, 0 - Boot Guard ACM is not done; 1 - Boot Guard ACM is done
178 UINT32 Smtc : 7; ///< 15:9 - Startup Module Timeout Count
179 UINT32 ScrtmIndicator : 1; ///< 16 - S-CRTM Indicator
180 UINT32 Reserved : 14; ///< 30:17 - Reserved
181 UINT32 StartEnforcement : 1; ///< 31 - Start Enforcement, 0 - no action; 1 - PCH starts the error enforcement logic
182 } r;
183 } HECI_FW_STS5_REGISTER;
184
185 ///
186 /// HFSTS6, offset 6Ch
187 ///
188 typedef union {
189 UINT32 ul;
190 struct {
191 UINT32 ForceBootPolicy : 1; ///< 0 - Force Boot Guard ACM Boot Policy
192 UINT32 CpuDebugDisabled : 1; ///< 1 - CPU Debug Disabled
193 UINT32 BspInitDisabled : 1; ///< 2 - BSP Initialization Disabled
194 UINT32 PBE : 1; ///< 3 - Protect BIOS Environment Policy
195 UINT32 Reserved : 2; ///< 5:4 - Reserved
196 UINT32 ENF : 2; ///< 7:6 - Error Enforcement Policy
197 UINT32 MeasuredBootPolicy : 1; ///< 8 - Measured Boot Policy, 0 - Disabled; 1 - Enabled
198 UINT32 VerifiedBootPolicy : 1; ///< 9 - Verified Boot Policy
199 UINT32 Reserved2 :11; ///< 20:10 - Reserved
200 UINT32 ManufacturingLock : 1; ///< 21 - Manufacturing variables lock state, 0 - Not locked; 1 - Locked
201 UINT32 KmId : 4; ///< 25:22 - Key Manifest ID
202 UINT32 ExeStatus : 1; ///< 26 - BSP Boot Policy Manifest Execution Status
203 UINT32 Error : 1; ///< 27 - CPU encountered an unexpected error and is asking FW to start the enforcement logic.
204 UINT32 BootGuardDisable : 1; ///< 28 - Boot Guard Disable
205 UINT32 FpfDisable : 1; ///< 29 - Field Programmable Fuses (FPF) Disable
206 UINT32 FpfSocConfigLock : 1; ///< 30 - Field Programmable Fuses (FPF) SOC Configuration Lock
207 UINT32 TxtSupport : 1; ///< 31 - TXT Support
208 } r;
209 } HECI_FW_STS6_REGISTER;
210
211 //
212 // ME Current State Values
213 //
214 #define ME_STATE_RESET 0x00
215 #define ME_STATE_INIT 0x01
216 #define ME_STATE_RECOVERY 0x02
217 #define ME_STATE_DISABLED 0x04
218 #define ME_STATE_NORMAL 0x05
219 #define ME_STATE_DISABLE_WAIT 0x06
220 #define ME_STATE_TRANSITION 0x07
221 #define ME_STATE_INVALID_CPU 0x08
222 #define ME_STATE_DFX_FW 0x0F
223
224 //
225 // ME Firmware FwInitComplete
226 //
227 #define ME_FIRMWARE_COMPLETED 0x01
228 #define ME_FIRMWARE_INCOMPLETED 0x00
229
230 //
231 // ME Boot Options Present
232 //
233 #define ME_BOOT_OPTIONS_PRESENT 0x01
234 #define ME_BOOT_OPTIONS_NOT_PRESENT 0x00
235
236 //
237 // ME Operation State Values
238 //
239 #define ME_OPERATION_STATE_PREBOOT 0x00
240 #define ME_OPERATION_STATE_M0_UMA 0x01
241 #define ME_OPERATION_STATE_M3 0x04
242 #define ME_OPERATION_STATE_M0 0x05
243 #define ME_OPERATION_STATE_BRINGUP 0x06
244 #define ME_OPERATION_STATE_M0_ERROR 0x07
245
246 //
247 // ME Error Code Values
248 //
249 #define ME_ERROR_CODE_NO_ERROR 0x00
250 #define ME_ERROR_CODE_UNKNOWN 0x01
251 #define ME_ERROR_CODE_DISABLED 0x02
252 #define ME_ERROR_CODE_IMAGE_FAILURE 0x03
253 #define ME_ERROR_CODE_DEBUG_FAILURE 0x04
254
255 //
256 // ME Current Operation Mode
257 //
258 #define ME_OPERATION_MODE_NORMAL 0x00
259 #define ME_OPERATION_MODE_DEBUG 0x02
260 #define ME_OPERATION_MODE_SOFT_TEMP_DISABLE 0x03
261 #define ME_OPERATION_MODE_SECOVR_JMPR 0x04
262 #define ME_OPERATION_MODE_SECOVR_HECI_MSG 0x05
263 #define ME_OPERATION_MODE_ENHANCED_DEBUG 0x07
264 #define ME_OPERATION_MODE_SPS 0x0F // Intel SPS Firmware v4
265
266 //
267 // Management Engine Firmware SKU Values
268 //
269 #define ME_FWSTS3_FW_SKU_IGNITION 0x00
270 #define ME_FWSTS3_FW_SKU_CONSUMER 0x02
271 #define ME_FWSTS3_FW_SKU_CORPORATE 0x03
272 #define ME_FWSTS3_FW_SKU_LITE 0x05
273 #define ME_FWSTS3_FW_SKU_SPS 0x06
274
275 #pragma pack()
276
277 #endif // _HECI_REGS_H_
HECI_GS_SHDW_REGISTER::NftpLoadFailure
UINT32 NftpLoadFailure
0 - NFTP Load Failure Detection Field
Definition: HeciRegs.h:113
HECI_FW_STS6_REGISTER::CpuDebugDisabled
UINT32 CpuDebugDisabled
1 - CPU Debug Disabled
Definition: HeciRegs.h:192
HECI_FW_STS3_REGISTER::FwSku
UINT32 FwSku
6:4 - FW Sku
Definition: HeciRegs.h:141
HECI_FW_STS5_REGISTER::Smtc
UINT32 Smtc
15:9 - Startup Module Timeout Count
Definition: HeciRegs.h:178
HECI_FW_STS5_REGISTER::ScrtmIndicator
UINT32 ScrtmIndicator
16 - S-CRTM Indicator
Definition: HeciRegs.h:179
HECI_CONTROL_STATUS_REGISTER::Reset
UINT32 Reset
4 - Host/ME Reset
Definition: HeciRegs.h:73
HECI_GS_SHDW_REGISTER::MePowerGating
UINT32 MePowerGating
10 - ME Power Gating Indicator
Definition: HeciRegs.h:122
HECI_CONTROL_STATUS_REGISTER::CBDepth
UINT32 CBDepth
31:24 - Host/ME Circular Buffer Depth
Definition: HeciRegs.h:77
HECI_FW_STS6_REGISTER::FpfSocConfigLock
UINT32 FpfSocConfigLock
30 - Field Programmable Fuses (FPF) SOC Configuration Lock
Definition: HeciRegs.h:206
HECI_FW_STS6_REGISTER::BspInitDisabled
UINT32 BspInitDisabled
2 - BSP Initialization Disabled
Definition: HeciRegs.h:193
HECI_FW_STS4_REGISTER::BootGuardFwStsValid
UINT32 BootGuardFwStsValid
14 - Boot Guard FWSTS Valid
Definition: HeciRegs.h:161
HECI_CONTROL_STATUS_REGISTER::CBWritePointer
UINT32 CBWritePointer
23:16 - Host/ME Circular Buffer Write Pointer
Definition: HeciRegs.h:76
HECI_FW_STS6_REGISTER::FpfDisable
UINT32 FpfDisable
29 - Field Programmable Fuses (FPF) Disable
Definition: HeciRegs.h:205
HECI_GS_SHDW_REGISTER::CseToDisabled
UINT32 CseToDisabled
14 - CSE is on the way to be disabled
Definition: HeciRegs.h:126
HECI_CONTROL_STATUS_REGISTER::IntStatus
UINT32 IntStatus
1 - Host/ME Interrupt Status
Definition: HeciRegs.h:70
HECI_GS_SHDW_REGISTER::WarmRstReqForDF
UINT32 WarmRstReqForDF
7 - Warm Reset Required for Dynamic Fusing
Definition: HeciRegs.h:119
HECI_FWS_REGISTER::InvokeEDebugMode
UINT32 InvokeEDebugMode
25 - Invoke EDebug Mode
Definition: HeciRegs.h:98
HECI_FW_STS5_REGISTER::VLD
UINT32 VLD
1 - Valid Bit, 0 - HFSTS#5 Bits [7:2] are invalid, 1 - Valid.
Definition: HeciRegs.h:174
HECI_FW_STS4_REGISTER::Reserved3
UINT32 Reserved3
13 - Reserved
Definition: HeciRegs.h:160
HECI_FW_STS6_REGISTER::Reserved2
UINT32 Reserved2
20:10 - Reserved
Definition: HeciRegs.h:199
HECI_CONTROL_STATUS_REGISTER::Reserved
UINT32 Reserved
7:5 - Reserved
Definition: HeciRegs.h:74
HECI_CONTROL_STATUS_REGISTER::Ready
UINT32 Ready
3 - Host/ME Ready
Definition: HeciRegs.h:72
HECI_FW_STS3_REGISTER::Reserved2
UINT32 Reserved2
10:7 - Reserved
Definition: HeciRegs.h:142
HECI_FW_STS6_REGISTER::ENF
UINT32 ENF
7:6 - Error Enforcement Policy
Definition: HeciRegs.h:196
HECI_FW_STS3_REGISTER::Reserved3
UINT32 Reserved3
31:14 - Reserved
Definition: HeciRegs.h:144
HECI_FW_STS3_REGISTER::RpmcStatus
UINT32 RpmcStatus
13:11 - RPMC Status
Definition: HeciRegs.h:143
HECI_FWS_REGISTER::MeOperationState
UINT32 MeOperationState
6:8 - ME Operation State
Definition: HeciRegs.h:90
HECI_GS_SHDW_REGISTER::Reserved2
UINT32 Reserved2
13 - Reserved
Definition: HeciRegs.h:125
HECI_CONTROL_STATUS_REGISTER::IntGenerate
UINT32 IntGenerate
2 - Host/ME Interrupt Generate
Definition: HeciRegs.h:71
HECI_FW_STS3_REGISTER
HFSTS3, offset 60h.
Definition: HeciRegs.h:137
HECI_GS_SHDW_REGISTER::InvokeMEBx
UINT32 InvokeMEBx
3 - Invoke MEBX
Definition: HeciRegs.h:115
HECI_FWS_REGISTER::CurrentPowerSource
UINT32 CurrentPowerSource
28:29 - Current power source selection mode
Definition: HeciRegs.h:101
HECI_FWS_REGISTER::D3SupportValid
UINT32 D3SupportValid
30 - D3 support
Definition: HeciRegs.h:102
HECI_GS_SHDW_REGISTER::MfsFailure
UINT32 MfsFailure
6 - MFS Failure
Definition: HeciRegs.h:118
HECI_FW_STS6_REGISTER::KmId
UINT32 KmId
25:22 - Key Manifest ID
Definition: HeciRegs.h:201
HECI_FW_STS5_REGISTER::AcmActived
UINT32 AcmActived
0 - Boot Guard ACM Active STS, 0 - Unknown Boot Guard ACM status; 1 - Boot Guard ACM is active
Definition: HeciRegs.h:173
HECI_FWS_REGISTER::FptBad
UINT32 FptBad
5 - FPT (Flash Partition Table) Bad
Definition: HeciRegs.h:89
HECI_FW_STS6_REGISTER::ExeStatus
UINT32 ExeStatus
26 - BSP Boot Policy Manifest Execution Status
Definition: HeciRegs.h:202
HECI_FW_STS4_REGISTER::FwInEnfFlow
UINT32 FwInEnfFlow
9 - FW is in ENF flow
Definition: HeciRegs.h:156
HECI_FWS_REGISTER::ErrorCode
UINT32 ErrorCode
12:15 - Error Code
Definition: HeciRegs.h:94
HECI_FWS_REGISTER
HFSTS1, offset 40h.
Definition: HeciRegs.h:84
HECI_GS_SHDW_REGISTER::ExtStatCode1
UINT32 ExtStatCode1
16:23 - EXT Status Code 1
Definition: HeciRegs.h:128
HECI_GS_SHDW_REGISTER::IccProgSts
UINT32 IccProgSts
1:2 - ICC Prog STS
Definition: HeciRegs.h:114
HECI_FW_STS6_REGISTER
HFSTS6, offset 6Ch.
Definition: HeciRegs.h:188
HECI_FW_STS4_REGISTER::BootGuardSelfTest
UINT32 BootGuardSelfTest
15 - Boot Guard Self Test
Definition: HeciRegs.h:162
HECI_CONTROL_STATUS_REGISTER
Register definitions.
Definition: HeciRegs.h:66
HECI_FW_STS4_REGISTER::AllTpmDisconnected
UINT32 AllTpmDisconnected
12 - All TPMs Disconnected
Definition: HeciRegs.h:159
HECI_FW_STS6_REGISTER::Error
UINT32 Error
27 - CPU encountered an unexpected error and is asking FW to start the enforcement logic.
Definition: HeciRegs.h:203
HECI_FW_STS4_REGISTER::dTpm12Deactivated
UINT32 dTpm12Deactivated
8 - User Has Selected dTPM1.2 Deactivated
Definition: HeciRegs.h:155
HECI_GS_SHDW_REGISTER::HeciListCh
UINT32 HeciListCh
15 - HECI Listner Change
Definition: HeciRegs.h:127
HECI_FW_STS6_REGISTER::Reserved
UINT32 Reserved
5:4 - Reserved
Definition: HeciRegs.h:195
HECI_FW_STS6_REGISTER::MeasuredBootPolicy
UINT32 MeasuredBootPolicy
8 - Measured Boot Policy, 0 - Disabled; 1 - Enabled
Definition: HeciRegs.h:197
HECI_GS_SHDW_REGISTER::ExtStatCode2
UINT32 ExtStatCode2
24:27 - EXT Status Code 2
Definition: HeciRegs.h:129
HECI_FW_STS4_REGISTER::Reserved
UINT32 Reserved
7:0 - Reserved
Definition: HeciRegs.h:154
HECI_FW_STS4_REGISTER::Reserved2
UINT32 Reserved2
11 - Reserved
Definition: HeciRegs.h:158
HECI_GS_SHDW_REGISTER
HFSTS2, offset 48h.
Definition: HeciRegs.h:110
HECI_FW_STS3_REGISTER::Reserved
UINT32 Reserved
3:0 - Reserved
Definition: HeciRegs.h:140
HECI_FWS_REGISTER::MeRstCnt
UINT32 MeRstCnt
20:23 - Number of ME Resets
Definition: HeciRegs.h:96
HECI_FWS_REGISTER::MeBootOptionsPresent
UINT32 MeBootOptionsPresent
24 - If this bit is set, an Boot Options is present
Definition: HeciRegs.h:97
HECI_FW_STS6_REGISTER::VerifiedBootPolicy
UINT32 VerifiedBootPolicy
9 - Verified Boot Policy
Definition: HeciRegs.h:198
HECI_FWS_REGISTER::D0i3SupportValid
UINT32 D0i3SupportValid
31 - D0i3 support
Definition: HeciRegs.h:103
HECI_FWS_REGISTER::SpiProtectionMode
UINT32 SpiProtectionMode
4 - SPI Protection Mode, 0 - Protected; 1 - UnProtected
Definition: HeciRegs.h:88
HECI_GS_SHDW_REGISTER::LowPowerState
UINT32 LowPowerState
9 - Low Power State
Definition: HeciRegs.h:121
HECI_FW_STS4_REGISTER::Reserved4
UINT32 Reserved4
31:16 - Reserved
Definition: HeciRegs.h:163
HECI_FW_STS6_REGISTER::ForceBootPolicy
UINT32 ForceBootPolicy
0 - Force Boot Guard ACM Boot Policy
Definition: HeciRegs.h:191
HECI_FW_STS5_REGISTER::StartEnforcement
UINT32 StartEnforcement
31 - Start Enforcement, 0 - no action; 1 - PCH starts the error enforcement logic
Definition: HeciRegs.h:181
HECI_FW_STS4_REGISTER
HFSTS4, offset 64h.
Definition: HeciRegs.h:151
HECI_FWS_REGISTER::BistResetRequest
UINT32 BistResetRequest
27 - This bit informs if BIST Reset Request
Definition: HeciRegs.h:100
HECI_FW_STS5_REGISTER::RCS
UINT32 RCS
2 - Result Code Source, 0 - Boot Guard ACM; 1 - CPU Microcode
Definition: HeciRegs.h:175
HECI_FWS_REGISTER::CurrentState
UINT32 CurrentState
0:3 - Current State
Definition: HeciRegs.h:87
HECI_GS_SHDW_REGISTER::FwUpdForcedSB
UINT32 FwUpdForcedSB
12 - FW Update Forced Safe Boot
Definition: HeciRegs.h:124
HECI_GS_SHDW_REGISTER::Reserved
UINT32 Reserved
5 - Reserved
Definition: HeciRegs.h:117
HECI_GS_SHDW_REGISTER::CpuReplacedSts
UINT32 CpuReplacedSts
4 - CPU Replaced STS
Definition: HeciRegs.h:116
HECI_GS_SHDW_REGISTER::CpuReplacedValid
UINT32 CpuReplacedValid
8 - CPU Replaced Valid
Definition: HeciRegs.h:120
HECI_CONTROL_STATUS_REGISTER::IntEnable
UINT32 IntEnable
0 - Host/ME Interrupt Enable
Definition: HeciRegs.h:69
HECI_FW_STS6_REGISTER::ManufacturingLock
UINT32 ManufacturingLock
21 - Manufacturing variables lock state, 0 - Not locked; 1 - Locked
Definition: HeciRegs.h:200
HECI_FW_STS6_REGISTER::PBE
UINT32 PBE
3 - Protect BIOS Environment Policy
Definition: HeciRegs.h:194
HECI_FW_STS5_REGISTER::AcmDone
UINT32 AcmDone
8 - Boot Guard ACM DONE STS, 0 - Boot Guard ACM is not done; 1 - Boot Guard ACM is done
Definition: HeciRegs.h:177
HECI_FWS_REGISTER::BistTestState
UINT32 BistTestState
26 - This bit informs if BIST is starting or BIST is finished
Definition: HeciRegs.h:99
HECI_FWS_REGISTER::FwUpdateInprogress
UINT32 FwUpdateInprogress
11 - This bit is set when data migration is required during ME FW update process
Definition: HeciRegs.h:93
HECI_GS_SHDW_REGISTER::FwUpdIpu
UINT32 FwUpdIpu
11 - FW Update IPU Needed
Definition: HeciRegs.h:123
HECI_FWS_REGISTER::FwInitComplete
UINT32 FwInitComplete
9 - This bit is set when firmware has fully entered a stable state
Definition: HeciRegs.h:91
HECI_GS_SHDW_REGISTER::InfPhaseCode
UINT32 InfPhaseCode
31:28 - Infra. Phase code
Definition: HeciRegs.h:130
HECI_FW_STS6_REGISTER::BootGuardDisable
UINT32 BootGuardDisable
28 - Boot Guard Disable
Definition: HeciRegs.h:204
HECI_FW_STS4_REGISTER::SxResumeType
UINT32 SxResumeType
10 - Sx Resume Type, 0- S4, S5 or G3; 1 S3, deep S3 for Intel Rapid Start Tech.
Definition: HeciRegs.h:157
HECI_FW_STS5_REGISTER
HFSTS5, offset 68h.
Definition: HeciRegs.h:170
HECI_FW_STS6_REGISTER::TxtSupport
UINT32 TxtSupport
31 - TXT Support
Definition: HeciRegs.h:207
HECI_FWS_REGISTER::FtBupLdFlr
UINT32 FtBupLdFlr
10 - This bit is set when firmware is not able to load BRINGUP from the fault tolerant (FT) code
Definition: HeciRegs.h:92
HECI_FWS_REGISTER::MeOperationMode
UINT32 MeOperationMode
16:19 - Management Engine Current Operation Mode
Definition: HeciRegs.h:95
HECI_FW_STS5_REGISTER::Reserved
UINT32 Reserved
30:17 - Reserved
Definition: HeciRegs.h:180
HECI_CONTROL_STATUS_REGISTER::CBReadPointer
UINT32 CBReadPointer
15:8 - Host/ME Circular Buffer Read Pointer
Definition: HeciRegs.h:75
HECI_FW_STS5_REGISTER::ESC
UINT32 ESC
7:3 - Error Status Code
Definition: HeciRegs.h:176
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HgInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
HgInfoHob.h File Reference

This file contains information about Hybrid Graphics. More...

#include "HybridGraphicsInfo.h"
Include dependency graph for HgInfoHob.h:

Go to the source code of this file.

Classes

struct | PCIE_GPIO
SA GPIO Data Structure. More...
struct | PCIE_RTD3_GPIO
SA PCIE RTD3 GPIO Data Structure. More...
struct | HG_INFO
HG Info HOB. More...

Detailed Description

This file contains information about Hybrid Graphics.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HgInfoHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HgInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
HgInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains information about Hybrid Graphics.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HG_INFO_HOB_H_
36 #define _HG_INFO_HOB_H_
37
38 #include "HybridGraphicsInfo.h"
39
40 extern EFI_GUID gHybridGraphicsInfoHobGuid;
41
42 #pragma pack (1)
43
44 ///
45 /// SA GPIO Data Structure
46 ///
47 typedef struct {
48 UINT8 ExpanderNo; ///< =Expander No For I2C based GPIO
49 UINT32 GpioNo; ///< GPIO pad
50 BOOLEAN Active; ///< 0=Active Low; 1=Active High
51 } PCIE_GPIO;
52
53 ///
54 /// SA PCIE RTD3 GPIO Data Structure
55 ///
56 typedef struct {
57 UINT8 GpioSupport; ///< 0=Not Supported; 1=PCH based; 2=I2C Based
58 PCIE_GPIO HoldRst; ///< Offset 8 This field contain PCIe HLD RESET GPIO value and level information
59 PCIE_GPIO PwrEnable; ///< This field contain PCIe PWR Enable GPIO value and level information
60 UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 Device Wake GPIO number
61 } PCIE_RTD3_GPIO;
62
63 ///
64 /// HG Info HOB
65 ///
66 typedef struct {
67 HG_MODE HgMode;
68 UINT8 RootPortIndex;
69 PCIE_RTD3_GPIO Rtd3Pcie0Gpio;
70 PCIE_RTD3_GPIO Rtd3Pcie1Gpio;
71 PCIE_RTD3_GPIO Rtd3Pcie2Gpio;
72 PCIE_RTD3_GPIO Rtd3Pcie3Gpio;
73 UINT16 DelayAfterPwrEn;
74 UINT16 DelayAfterHoldReset;
75 UINT8 HgSupport;
76 } HG_INFO;
77
78 //
79 // VMD Info Hob
80 //
81 typedef struct {
82 EFI_HOB_GUID_TYPE EfiHobGuidType;
83 HG_INFO HgInfo;
84 } HG_INFO_HOB;
85
86 #pragma pack ()
87
88
89 #endif
PCIE_RTD3_GPIO::WakeGpioNo
UINT32 WakeGpioNo
This field contain PCIe RTD3 Device Wake GPIO number.
Definition: HgInfoHob.h:60
PCIE_RTD3_GPIO::GpioSupport
UINT8 GpioSupport
0=Not Supported; 1=PCH based; 2=I2C Based
Definition: HgInfoHob.h:57
PCIE_GPIO
SA GPIO Data Structure.
Definition: HgInfoHob.h:47
PCIE_GPIO::Active
BOOLEAN Active
0=Active Low; 1=Active High
Definition: HgInfoHob.h:50
PCIE_GPIO::GpioNo
UINT32 GpioNo
GPIO pad.
Definition: HgInfoHob.h:49
HG_INFO
HG Info HOB.
Definition: HgInfoHob.h:66
PCIE_RTD3_GPIO::PwrEnable
PCIE_GPIO PwrEnable
This field contain PCIe PWR Enable GPIO value and level information.
Definition: HgInfoHob.h:59
PCIE_RTD3_GPIO
SA PCIE RTD3 GPIO Data Structure.
Definition: HgInfoHob.h:56
PCIE_GPIO::ExpanderNo
UINT8 ExpanderNo
=Expander No For I2C based GPIO
Definition: HgInfoHob.h:48
PCIE_RTD3_GPIO::HoldRst
PCIE_GPIO HoldRst
Offset 8 This field contain PCIe HLD RESET GPIO value and level information.
Definition: HgInfoHob.h:58
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HobUsageDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
HobUsageDataHob.h File Reference

Definitions for Hob Usage data HOB. More...

Go to the source code of this file.

Classes

struct HOB_USAGE_DATA_HOB
Hob Usage Data Hob. More...

Detailed Description

Definitions for Hob Usage data HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HobUsageDataHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HobUsageDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
HobUsageDataHob.h
Go to the documentation of this file.
1 /** @file
2 Definitions for Hob Usage data HOB
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _HOB_USAGE_DATA_HOB_H_
37 #define _HOB_USAGE_DATA_HOB_H_
38
39 extern EFI_GUID gHobUsageDataGuid;
40
41 #pragma pack (push, 1)
42
43 /**
44 Hob Usage Data Hob
45
46 <b>Revision 1:</b>
47 - Initial version.
48 **/
49 typedef struct {
50 EFI_PHYSICAL_ADDRESS EfiMemoryTop;
51 EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
52 EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
53 EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
54 UINTN FreeMemory;
55 } HOB_USAGE_DATA_HOB;
56
57 #pragma pack (pop)
58
59 #endif // _HOB_USAGE_DATA_HOB_H_
HOB_USAGE_DATA_HOB
Hob Usage Data Hob.
Definition: HobUsageDataHob.h:49
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HostBridgeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver1
Classes
HostBridgeConfig.h File Reference

Configurations for HostBridge. More...

#include <ConfigBlock.h>
Include dependency graph for HostBridgeConfig.h:

Go to the source code of this file.

Classes

struct | HOST_BRIDGE_PREMEM_CONFIG
This configuration block describes HostBridge settings in PreMem. More...
struct | HOST_BRIDGE_PEI_CONFIG
This configuration block describes HostBridge settings in Post-Mem. More...

Detailed Description

Configurations for HostBridge.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HostBridgeConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HostBridgeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver1
HostBridgeConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for HostBridge
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HOST_BRIDGE_CONFIG_H_
36 #define _HOST_BRIDGE_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define HOST_BRIDGE_PREMEM_CONFIG_REVISION 1
41 #define HOST_BRIDGE_PEI_CONFIG_REVISION 1
42
43 extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
44 extern EFI_GUID gHostBridgePeiConfigGuid;
45
46 #pragma pack (push,1)
47
48 /**
49 This configuration block describes HostBridge settings in PreMem.\n
50 <b>Revision 1</b>:
51 - Initial version.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
55 UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
56 UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
57 UINT32 EpBar; ///< Offset 36 Address of System Agent EPBAR: <b>0xFEDA1000</b>
58 UINT32 GdxcBar; ///< Offset 40 Address of System Agent GDXCBAR: <b>0xFED84000</b>
59 UINT32 RegBar; ///< Offset 44 Address of System Agent REGBAR: <b>0xFB000000</b>
60 UINT32 EdramBar; ///< Offset 48 Address of System Agent EDRAMBAR: <b>0xFED80000</b>
61 /**
62 Offset 52 :
63 Size of reserved MMIO space for PCI devices\n
64 <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
65 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
66 When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
67 **/
68 UINT32 MmioSize;
69 UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
70 UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
71 UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
72 } HOST_BRIDGE_PREMEM_CONFIG;
73
74
75 /**
76 This configuration block describes HostBridge settings in Post-Mem.\n
77 <b>Revision 1</b>:
78 - Initial version.
79 **/
80 typedef struct {
81 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
82 UINT8 Device4Enable; ///< Offser 28 :This policy is used to control enable or disable System Agent Thermal device (0,4,0). <b>0=FALSE</b>, 1=TRUE.
83 UINT8 ChapDeviceEnable; ///< Offset 29 :<b>(Test)</b>This policy is used to control enable or disable System Agent Chap device (0,7,0). <b>0=FALSE</b>, 1=TRUE.
84 UINT8 SkipPamLock; ///< Offset 30 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
85 UINT8 EdramTestMode; ///< Offset 28 :EDRAM Test Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, <b> 2- EDRAM HW Mode</b>
86 } HOST_BRIDGE_PEI_CONFIG;
87
88 #pragma pack (pop)
89
90 #endif
HOST_BRIDGE_PEI_CONFIG::Device4Enable
UINT8 Device4Enable
Offser 28 :This policy is used to control enable or disable System Agent Thermal device (0,...
Definition: HostBridgeConfig.h:82
ConfigBlock.h
Header file for Config Block Lib implementation.
HOST_BRIDGE_PREMEM_CONFIG::RegBar
UINT32 RegBar
Offset 44 Address of System Agent REGBAR: 0xFB000000
Definition: HostBridgeConfig.h:59
HOST_BRIDGE_PREMEM_CONFIG::EnableAbove4GBMmio
UINT8 EnableAbove4GBMmio
Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, 1=Enable
Definition: HostBridgeConfig.h:70
HOST_BRIDGE_PREMEM_CONFIG::MmioSizeAdjustment
UINT32 MmioSizeAdjustment
Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size w...
Definition: HostBridgeConfig.h:69
HOST_BRIDGE_PREMEM_CONFIG::MmioSize
UINT32 MmioSize
Offset 52 : Size of reserved MMIO space for PCI devices 0=AUTO, 512=512MB, 768=768MB,...
Definition: HostBridgeConfig.h:68
HOST_BRIDGE_PREMEM_CONFIG
This configuration block describes HostBridge settings in PreMem.
Definition: HostBridgeConfig.h:53
HOST_BRIDGE_PEI_CONFIG::ChapDeviceEnable
UINT8 ChapDeviceEnable
Offset 29 :(Test)This policy is used to control enable or disable System Agent Chap device (0,...
Definition: HostBridgeConfig.h:83
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HOST_BRIDGE_PREMEM_CONFIG::MchBar
UINT32 MchBar
Offset 28 Address of System Agent MCHBAR: 0xFEDC0000(TGL)/0xFEA80000(JSL)
Definition: HostBridgeConfig.h:55
HOST_BRIDGE_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: HostBridgeConfig.h:81
HOST_BRIDGE_PREMEM_CONFIG::EpBar
UINT32 EpBar
Offset 36 Address of System Agent EPBAR: 0xFEDA1000
Definition: HostBridgeConfig.h:57
HOST_BRIDGE_PEI_CONFIG::SkipPamLock
UINT8 SkipPamLock
Offset 30 :To skip PAM register locking.
Definition: HostBridgeConfig.h:84
HOST_BRIDGE_PREMEM_CONFIG::GdxcBar
UINT32 GdxcBar
Offset 40 Address of System Agent GDXCBAR: 0xFED84000
Definition: HostBridgeConfig.h:58
HOST_BRIDGE_PEI_CONFIG::EdramTestMode
UINT8 EdramTestMode
Offset 28 :EDRAM Test Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable,...
Definition: HostBridgeConfig.h:85
HOST_BRIDGE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: HostBridgeConfig.h:54
HOST_BRIDGE_PEI_CONFIG
This configuration block describes HostBridge settings in Post-Mem.
Definition: HostBridgeConfig.h:80
HOST_BRIDGE_PREMEM_CONFIG::DmiBar
UINT32 DmiBar
Offset 32 Address of System Agent DMIBAR: 0xFEDA0000
Definition: HostBridgeConfig.h:56
HOST_BRIDGE_PREMEM_CONFIG::EdramBar
UINT32 EdramBar
Offset 48 Address of System Agent EDRAMBAR: 0xFED80000
Definition: HostBridgeConfig.h:60
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HostBridgeInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
HostBridgeInfoLib.h File Reference

Header file for Host Bridge Info Lib implementation. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciSegmentLib.h>
#include <IndustryStandard/Pci22.h>
Include dependency graph for HostBridgeInfoLib.h:

Go to the source code of this file.

Functions

BOOLEAN | IsSamEnabled (VOID)
Checks if SAM is enabled or not. More...
UINT32 | GetSamFwInfo (VOID)
GetSamFwInfo - This function performs SAM ready state and get its FW version info. More...
UINT32 | GetRegBarSize (VOID)
Regbar size- This function return RegBar Size. More...
BOOLEAN | IsTsegBaseAndImrMemoryConsistent (VOID)
This function will check if Tseg base is consistent in different memory scopes. More...
BOOLEAN | IsSaDevice4Enable (VOID)
Checks if SaDevice4 is enabled or not. More...

Detailed Description

Header file for Host Bridge Info Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HostBridgeInfoLib.h.

Function Documentation

◆ GetRegBarSize()

UINT32 GetRegBarSize ( VOID )

Regbar size- This function return RegBar Size.

Return values
UINT32 - RegBar Size.

◆ GetSamFwInfo()

UINT32 GetSamFwInfo ( VOID )

GetSamFwInfo - This function performs SAM ready state and get its FW version info.

This function does the following steps: (1) Examines SAM_READY (Register SAM_STATUS_1, bit 30) (2) If 0, retry in SAM_READY_TIMEOUT ms (1ms timeout) (3) Return & print FW version in success, else return 0x0.

Return values
UINT32 - SAM FW Version if SAM is ready, else 0x0.

◆ IsSaDevice4Enable()

BOOLEAN IsSaDevice4Enable ( VOID )

Checks if SaDevice4 is enabled or not.

Return values
FALSE | SaDevice4 is disabled
TRUE | SaDevice4 is enabled

◆ IsSamEnabled()

BOOLEAN IsSamEnabled ( VOID )

Checks if SAM is enabled or not.

Return values
FALSE | SAM is disabled
TRUE | SAM is enabled

◆ IsTsegBaseAndImrMemoryConsistent()

BOOLEAN IsTsegBaseAndImrMemoryConsistent ( VOID )

This function will check if Tseg base is consistent in different memory scopes.

Return values
TRUE | Tseg Base is consistent
FALSE | Tseg Base is not consistent
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HostBridgeInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
HostBridgeInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Host Bridge Info Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _HOST_BRIDGE_INFO_LIB_H_
37 #define _HOST_BRIDGE_INFO_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/IoLib.h>
43 #include <Library/BaseMemoryLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <IndustryStandard/Pci22.h>
46
47 /**
48 Checks if SAM is enabled or not.
49
50 @retval FALSE SAM is disabled
51 @retval TRUE SAM is enabled
52 **/
53 BOOLEAN
54 EFIAPI
55 IsSamEnabled (
56 VOID
57 );
58
59 /**
60 GetSamFwInfo - This function performs SAM ready state and get its FW version info.
61
62 This function does the following steps:
63 (1) Examines SAM_READY (Register SAM_STATUS_1, bit 30)
64 (2) If 0, retry in SAM_READY_TIMEOUT ms (1ms timeout)
65 (3) Return & print FW version in success, else return 0x0.
66
67 @retval UINT32 - SAM FW Version if SAM is ready, else 0x0.
68 **/
69 UINT32
70 EFIAPI
71 GetSamFwInfo (
72 VOID
73 );
74
75 /**
76 Regbar size- This function return RegBar Size.
77
78 @retval UINT32 - RegBar Size.
79 **/
80 UINT32
81 EFIAPI
82 GetRegBarSize (
83 VOID
84 );
85
86 /**
87 This function will check if Tseg base is consistent in different memory scopes.
88
89 @retval TRUE Tseg Base is consistent
90 @retval FALSE Tseg Base is not consistent
91 **/
92 BOOLEAN
93 IsTsegBaseAndImrMemoryConsistent (
94 VOID
95 );
96
97 /**
98 Checks if SaDevice4 is enabled or not.
99
100 @retval FALSE SaDevice4 is disabled
101 @retval TRUE SaDevice4 is enabled
102 **/
103 BOOLEAN
104 EFIAPI
105 IsSaDevice4Enable(
106 VOID
107 );
108 #endif
IsTsegBaseAndImrMemoryConsistent
BOOLEAN IsTsegBaseAndImrMemoryConsistent(VOID)
This function will check if Tseg base is consistent in different memory scopes.
IsSaDevice4Enable
BOOLEAN IsSaDevice4Enable(VOID)
Checks if SaDevice4 is enabled or not.
GetRegBarSize
UINT32 GetRegBarSize(VOID)
Regbar size- This function return RegBar Size.
IsSamEnabled
BOOLEAN IsSamEnabled(VOID)
Checks if SAM is enabled or not.
GetSamFwInfo
UINT32 GetSamFwInfo(VOID)
GetSamFwInfo - This function performs SAM ready state and get its FW version info.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes
HsioConfig.h File Reference

HSIO policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_HSIO_PREMEM_CONFIG
The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings. More...
struct | PCH_HSIO_CONFIG
The PCH_HSIO_CONFIG block provides HSIO message related settings. More...

Detailed Description

HSIO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioConfig.h
Go to the documentation of this file.
1 /** @file
2 HSIO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_CONFIG_H_
36 #define _HSIO_CONFIG_H_
37 #define PCH_HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated
38 extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated
39
40 #define PCH_HSIO_CONFIG_REVISION 3
41 extern EFI_GUID gHsioConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
47 **/
48 typedef struct {
49 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
50
51 /**
52 <b>(Test)</b>
53 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent
54 <b>1- Enable</b> ChipsetInit HECI message
55 **/
56 UINT8 ChipsetInitMessage;
57 /**
58 <b>(Test)</b>
59 <b>0- Disable</b>
60 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI message.
61 **/
62 UINT8 BypassPhySyncReset;
63 UINT8 RsvdBytes[2];
64
65 } PCH_HSIO_PREMEM_CONFIG;
66
67
68 /**
69 The PCH_HSIO_CONFIG block provides HSIO message related settings.
70 **/
71 typedef struct {
72 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
73 /**
74 Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
75 **/
76 UINT32 ChipsetInitBinPtr;
77 /**
78 Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
79 **/
80 UINT32 ChipsetInitBinLen;
81
82 UINT8 EnableIoMargining;
83 UINT8 ReservedBits[3];
84
85 /**
86 Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME
87 **/
88 UINT32 SynpsPhyBinPtr;
89 /**
90 Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME
91 **/
92 UINT32 SynpsPhyBinLen;
93 } PCH_HSIO_CONFIG;
94
95 #pragma pack (pop)
96
97 #endif // _HSIO_CONFIG_H_
PCH_HSIO_CONFIG::SynpsPhyBinLen
UINT32 SynpsPhyBinLen
Policy used to indicate the size of the OEM Synophsys Phy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:92
PCH_HSIO_CONFIG::SynpsPhyBinPtr
UINT32 SynpsPhyBinPtr
Policy used to point to the OEM Synophsys Phy binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:88
PCH_HSIO_CONFIG::ChipsetInitBinLen
UINT32 ChipsetInitBinLen
Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and...
Definition: HsioConfig.h:80
PCH_HSIO_PREMEM_CONFIG
The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
Definition: HsioConfig.h:48
PCH_HSIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioConfig.h:72
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_CONFIG
The PCH_HSIO_CONFIG block provides HSIO message related settings.
Definition: HsioConfig.h:71
PCH_HSIO_PREMEM_CONFIG::BypassPhySyncReset
UINT8 BypassPhySyncReset
(Test) 0- Disable 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI mes...
Definition: HsioConfig.h:62
PCH_HSIO_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioConfig.h:49
PCH_HSIO_CONFIG::ChipsetInitBinPtr
UINT32 ChipsetInitBinPtr
Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME.
Definition: HsioConfig.h:76
PCH_HSIO_PREMEM_CONFIG::ChipsetInitMessage
UINT8 ChipsetInitMessage
(Test) 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from bein...
Definition: HsioConfig.h:56
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioPcieConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes
HsioPcieConfig.h File Reference

HSIO pcie policy. More...

#include <PchLimits.h>
Include dependency graph for HsioPcieConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_HSIO_PCIE_LANE_CONFIG
The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane. More...
struct | PCH_HSIO_PCIE_PREMEM_CONFIG
The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes. More...

Detailed Description

HSIO pcie policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioPcieConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioPcieConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioPcieConfig.h
Go to the documentation of this file.
1 /** @file
2 HSIO pcie policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_PCIE_CONFIG_H_
36 #define _HSIO_PCIE_CONFIG_H_
37
38 #include <PchLimits.h>
39
40 #define PCH_HSIO_PCIE_PREMEM_CONFIG_REVISION 1
41 extern EFI_GUID gHsioPciePreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
47 **/
48 typedef struct {
49 //
50 // HSIO Rx Eq
51 // Refer to the EDS for recommended values.
52 // Note that these setting are per-lane and not per-port
53 //
54 UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value
55 UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value
56 UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
57 UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
58 UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
59 UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
60 UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
61 UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
62 UINT32 RsvdBits0 : 4; ///< Reserved Bits
63
64 UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
65 UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting
66 UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
67 UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting
68 UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
69 UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting
70 UINT32 RsvdBits1 : 11; ///< Reserved Bits
71 } PCH_HSIO_PCIE_LANE_CONFIG;
72
73 ///
74 /// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
75 ///
76 typedef struct {
77 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
78 ///
79 /// These members describe the configuration of HSIO for PCIe lanes.
80 ///
81 PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
82 } PCH_HSIO_PCIE_PREMEM_CONFIG;
83
84 #pragma pack (pop)
85
86 #endif // _HSIO_PCIE_LANE_CONFIG_H_
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph3p5
UINT32 HsioTxGen2DeEmph3p5
PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:67
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen3DownscaleAmp
UINT32 HsioTxGen3DownscaleAmp
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:61
PCH_HSIO_PCIE_LANE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: HsioPcieConfig.h:62
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen3DownscaleAmpEnable
UINT32 HsioTxGen3DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:60
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DownscaleAmpEnable
UINT32 HsioTxGen2DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:58
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DeEmph
UINT32 HsioTxGen1DeEmph
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:65
PCH_HSIO_PCIE_LANE_CONFIG
The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane.
Definition: HsioPcieConfig.h:48
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DownscaleAmp
UINT32 HsioTxGen2DownscaleAmp
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:59
PCH_HSIO_PCIE_PREMEM_CONFIG
The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes.
Definition: HsioPcieConfig.h:76
PCH_HSIO_PCIE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioPcieConfig.h:77
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph6p0
UINT32 HsioTxGen2DeEmph6p0
PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting.
Definition: HsioPcieConfig.h:69
PCH_HSIO_PCIE_LANE_CONFIG::HsioRxSetCtleEnable
UINT32 HsioRxSetCtleEnable
0: Disable; 1: Enable PCH PCIe Gen 3 Set CTLE Value
Definition: HsioPcieConfig.h:54
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DownscaleAmp
UINT32 HsioTxGen1DownscaleAmp
PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value.
Definition: HsioPcieConfig.h:57
PCH_HSIO_PCIE_LANE_CONFIG::HsioRxSetCtle
UINT32 HsioRxSetCtle
PCH PCIe Gen 3 Set CTLE Value.
Definition: HsioPcieConfig.h:55
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DownscaleAmpEnable
UINT32 HsioTxGen1DownscaleAmpEnable
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
Definition: HsioPcieConfig.h:56
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph6p0Enable
UINT32 HsioTxGen2DeEmph6p0Enable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value overr...
Definition: HsioPcieConfig.h:68
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen1DeEmphEnable
UINT32 HsioTxGen1DeEmphEnable
0: Disable; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
Definition: HsioPcieConfig.h:64
PCH_HSIO_PCIE_LANE_CONFIG::HsioTxGen2DeEmph3p5Enable
UINT32 HsioTxGen2DeEmph3p5Enable
0: Disable; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value overr...
Definition: HsioPcieConfig.h:66
PCH_HSIO_PCIE_LANE_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved Bits.
Definition: HsioPcieConfig.h:70
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioSataConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Classes
HsioSataConfig.h File Reference

Hsio Sata policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_HSIO_SATA_PORT_LANE
The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane. More...
struct | PCH_HSIO_SATA_PREMEM_CONFIG
The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller. More...

Detailed Description

Hsio Sata policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HsioSataConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HsioSataConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
HsioSataConfig.h
Go to the documentation of this file.
1 /** @file
2 Hsio Sata policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HSIO_SATA_CONFIG_H_
36 #define _HSIO_SATA_CONFIG_H_
37
38 #define PCH_HSIO_SATA_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gHsioSataPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
45 **/
46 typedef struct {
47 //
48 // HSIO Rx Eq
49 //
50 UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
51 UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
52 UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
53 UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
54 UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
55 UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
56 //
57 // HSIO Tx Eq
58 //
59 UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
60 UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
61 UINT32 RsvdBits0 : 4; ///< Reserved bits
62
63 UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
64 UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
65 UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
66 UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
67 UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
68 UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
69
70 UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
71 UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
72 UINT32 RsvdBits1 : 4; ///< Reserved bits
73
74 UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
75 UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
76 UINT32 RsvdBits2 : 25; ///< Reserved bits
77 } PCH_HSIO_SATA_PORT_LANE;
78
79 ///
80 /// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
81 ///
82 typedef struct {
83 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
84 ///
85 /// These members describe the configuration of HSIO for SATA lanes.
86 ///
87 PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
88 } PCH_HSIO_SATA_PREMEM_CONFIG;
89
90 #pragma pack (pop)
91
92 #endif // _HSIO_SATA_CONFIG_H_
PCH_HSIO_SATA_PORT_LANE
The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane.
Definition: HsioSataConfig.h:46
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DownscaleAmp
UINT32 HsioTxGen2DownscaleAmp
SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment.
Definition: HsioSataConfig.h:64
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DeEmphEnable
UINT32 HsioTxGen2DeEmphEnable
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:70
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DeEmph
UINT32 HsioTxGen3DeEmph
SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override.
Definition: HsioSataConfig.h:75
PCH_HSIO_SATA_PORT_LANE::RsvdBits2
UINT32 RsvdBits2
Reserved bits.
Definition: HsioSataConfig.h:76
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DeEmphEnable
UINT32 HsioTxGen1DeEmphEnable
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:67
PCH_HSIO_SATA_PORT_LANE::HsioRxGen2EqBoostMagEnable
UINT32 HsioRxGen2EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:52
PCH_HSIO_SATA_PORT_LANE::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: HsioSataConfig.h:72
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_HSIO_SATA_PORT_LANE::HsioRxGen3EqBoostMag
UINT32 HsioRxGen3EqBoostMag
SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:55
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DeEmph
UINT32 HsioTxGen1DeEmph
SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
Definition: HsioSataConfig.h:68
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DownscaleAmp
UINT32 HsioTxGen1DownscaleAmp
SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
Definition: HsioSataConfig.h:60
PCH_HSIO_SATA_PORT_LANE::HsioTxGen1DownscaleAmpEnable
UINT32 HsioTxGen1DownscaleAmpEnable
0: Disable; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:59
PCH_HSIO_SATA_PORT_LANE::HsioRxGen1EqBoostMag
UINT32 HsioRxGen1EqBoostMag
SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:51
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DeEmphEnable
UINT32 HsioTxGen3DeEmphEnable
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
Definition: HsioSataConfig.h:74
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DownscaleAmpEnable
UINT32 HsioTxGen2DownscaleAmpEnable
0: Disable; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:63
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DownscaleAmpEnable
UINT32 HsioTxGen3DownscaleAmpEnable
0: Disable; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
Definition: HsioSataConfig.h:65
PCH_HSIO_SATA_PORT_LANE::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: HsioSataConfig.h:61
PCH_HSIO_SATA_PORT_LANE::HsioRxGen1EqBoostMagEnable
UINT32 HsioRxGen1EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:50
PCH_HSIO_SATA_PORT_LANE::HsioRxGen2EqBoostMag
UINT32 HsioRxGen2EqBoostMag
SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value.
Definition: HsioSataConfig.h:53
PCH_HSIO_SATA_PORT_LANE::HsioTxGen2DeEmph
UINT32 HsioTxGen2DeEmph
SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
Definition: HsioSataConfig.h:71
PCH_HSIO_SATA_PORT_LANE::HsioRxGen3EqBoostMagEnable
UINT32 HsioRxGen3EqBoostMagEnable
0: Disable; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
Definition: HsioSataConfig.h:54
PCH_HSIO_SATA_PREMEM_CONFIG
The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
Definition: HsioSataConfig.h:82
PCH_HSIO_SATA_PORT_LANE::HsioTxGen3DownscaleAmp
UINT32 HsioTxGen3DownscaleAmp
SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment.
Definition: HsioSataConfig.h:66
PCH_HSIO_SATA_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HsioSataConfig.h:83
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridGraphicsConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
Classes | Enumerations
HybridGraphicsConfig.h File Reference

Hybrid Graphics policy definitions. More...

Go to the source code of this file.

Classes

struct | CPU_PCIE_GPIO_INFO
CPU PCIe GPIO Data Structure. More...
struct | CPU_PCIE_RTD3_GPIO
CPU PCIE RTD3 GPIO Data Structure. More...
struct | HYBRID_GRAPHICS_CONFIG
This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port. More...

Enumerations

enum GPIO_SUPPORT
GPIO Support.

Detailed Description

Hybrid Graphics policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridGraphicsConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridGraphicsConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphicsConfig.h
Go to the documentation of this file.
1 /** @file
2 Hybrid Graphics policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HYBRID_GRAPHICS_CONFIG_H_
36 #define _HYBRID_GRAPHICS_CONFIG_H_
37
38 #define HYBRID_GRAPHICS_CONFIG_REVISION 4
39
40 #pragma pack(push, 1)
41 ///
42 /// GPIO Support
43 ///
44 typedef enum {
45 NotSupported = 0,
46 PchGpio,
47 I2CGpio,
48 } GPIO_SUPPORT;
49
50 ///
51 /// CPU PCIe GPIO Data Structure
52 ///
53 typedef struct {
54 UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO
55 BOOLEAN Active; ///< Offset 1 0=Active Low; 1=Active High
56 UINT8 Rsvd0[2]; ///< Offset 2 Reserved
57 UINT32 GpioNo; ///< Offset 4 GPIO pad
58 } CPU_PCIE_GPIO_INFO;
59
60 /**
61 CPU PCIE RTD3 GPIO Data Structure
62 **/
63 typedef struct {
64 CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RESET GPIO value and level information
65 CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR Enable GPIO value and level information
66 UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number
67 UINT8 GpioSupport; ///< Offset 20 Depends on board design the GPIO configuration may be different: <b>0=Not Supported</b>, 1=PCH Based, 2=I2C based
68 UINT8 Rsvd0[3]; ///< Offset 21
69 } CPU_PCIE_RTD3_GPIO;
70
71 /**
72 This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.
73 Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.
74 <b>Revision 1</b>:
75 - Initial version.
76 <b>Revision 2</b>:
77 - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics
78 <b>Revision 3</b>:
79 - Removed HgSlot Policy: As there is no selection between PEG or PCH Slot for Hybrid Graphics
80 <b>Revision 4</b>:
81 - Added HgSupport Policy: To support HG support on other PEG ports
82 **/
83 typedef struct {
84 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
85 CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs used for PCIe
86 UINT8 RootPortIndex; ///< Offset 52 Root Port Index number used for HG
87 UINT8 HgMode; ///< Offset 53 HgMode: <b>0=Disabled</b>, 1=HG Muxed, 2=HG Muxless, 3=PEG
88 UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphics Subsystem ID: <b>2212</b>
89 UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum, <b>300=300 microseconds</b>
90 UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum, <b>100=100 microseconds</b>
91 CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs used for PCIe
92 CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs used for PCIe
93 CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs used for PCIe
94 UINT8 HgSupport; ///< Offset 132 HgSupport on specific port
95 UINT8 Rsvd0[3]; ///< Offset 133 Reserved bytes for future use
96 } HYBRID_GRAPHICS_CONFIG;
97 #pragma pack(pop)
98 #endif // _HYBRID_GRAPHICS_CONFIG_H_
HYBRID_GRAPHICS_CONFIG::CpuPcie1Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio
Offset 60 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:91
HYBRID_GRAPHICS_CONFIG
This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & Root Port.
Definition: HybridGraphicsConfig.h:83
HYBRID_GRAPHICS_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: HybridGraphicsConfig.h:84
HYBRID_GRAPHICS_CONFIG::HgSubSystemId
UINT16 HgSubSystemId
Offset 54 Hybrid Graphics Subsystem ID: 2212
Definition: HybridGraphicsConfig.h:88
HYBRID_GRAPHICS_CONFIG::HgDelayAfterHoldReset
UINT16 HgDelayAfterHoldReset
Offset 58 Dgpu Delay after Hold Reset using Setup option: 0=Minimal, 1000=Maximum,...
Definition: HybridGraphicsConfig.h:90
HYBRID_GRAPHICS_CONFIG::HgMode
UINT8 HgMode
Offset 53 HgMode: 0=Disabled, 1=HG Muxed, 2=HG Muxless, 3=PEG.
Definition: HybridGraphicsConfig.h:87
HYBRID_GRAPHICS_CONFIG::CpuPcie2Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio
Offset 84 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:92
CPU_PCIE_RTD3_GPIO::HoldRst
CPU_PCIE_GPIO_INFO HoldRst
Offset 0 This field contain PCIe HLD RESET GPIO value and level information.
Definition: HybridGraphicsConfig.h:64
CPU_PCIE_GPIO_INFO::Active
BOOLEAN Active
Offset 1 0=Active Low; 1=Active High.
Definition: HybridGraphicsConfig.h:55
CPU_PCIE_GPIO_INFO::ExpanderNo
UINT8 ExpanderNo
Offset 0 Expander No For I2C based GPIO.
Definition: HybridGraphicsConfig.h:54
CPU_PCIE_RTD3_GPIO::GpioSupport
UINT8 GpioSupport
Offset 20 Depends on board design the GPIO configuration may be different: 0=Not Supported,...
Definition: HybridGraphicsConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HYBRID_GRAPHICS_CONFIG::HgSupport
UINT8 HgSupport
Offset 132 HgSupport on specific port.
Definition: HybridGraphicsConfig.h:94
CPU_PCIE_RTD3_GPIO::PwrEnable
CPU_PCIE_GPIO_INFO PwrEnable
Offset 8 This field contain PCIe PWR Enable GPIO value and level information.
Definition: HybridGraphicsConfig.h:65
HYBRID_GRAPHICS_CONFIG::CpuPcie0Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio
Offset 28 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:85
HYBRID_GRAPHICS_CONFIG::RootPortIndex
UINT8 RootPortIndex
Offset 52 Root Port Index number used for HG.
Definition: HybridGraphicsConfig.h:86
CPU_PCIE_GPIO_INFO
CPU PCIe GPIO Data Structure.
Definition: HybridGraphicsConfig.h:53
GPIO_SUPPORT
GPIO_SUPPORT
GPIO Support.
Definition: HybridGraphicsConfig.h:44
HYBRID_GRAPHICS_CONFIG::CpuPcie3Rtd3Gpio
CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio
Offset 108 RTD3 GPIOs used for PCIe.
Definition: HybridGraphicsConfig.h:93
CPU_PCIE_RTD3_GPIO
CPU PCIE RTD3 GPIO Data Structure.
Definition: HybridGraphicsConfig.h:63
CPU_PCIE_RTD3_GPIO::WakeGpioNo
UINT32 WakeGpioNo
Offset 16 This field contain PCIe RTD3 Device Wake GPIO Number.
Definition: HybridGraphicsConfig.h:66
HYBRID_GRAPHICS_CONFIG::HgDelayAfterPwrEn
UINT16 HgDelayAfterPwrEn
Offset 56 Dgpu Delay after Power enable using Setup option: 0=Minimal, 1000=Maximum,...
Definition: HybridGraphicsConfig.h:89
CPU_PCIE_GPIO_INFO::GpioNo
UINT32 GpioNo
Offset 4 GPIO pad.
Definition: HybridGraphicsConfig.h:57
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridGraphicsInfoFruLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
HybridGraphicsInfoFruLib.h File Reference

Header file for Hybrid Graphics Info Fru Lib implementation. More...

Go to the source code of this file.

Functions

EFI_STATUS GetHybridGraphicsRpDevFun (IN UINT8 HgSupport, OUT UINT8 *RootPortDev, OUT UINT8 *RootPortFun)
Get Hybrid Graphics Root Port Device and Function Number by Root Port physical Number. More...

Detailed Description

Header file for Hybrid Graphics Info Fru Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridGraphicsInfoFruLib.h.

Function Documentation

◆ GetHybridGraphicsRpDevFun()

EFI_STATUS GetHybridGraphicsRpDevFun | ( | IN UINT8 | HgSupport,
 |  | OUT UINT8 * | RootPortDev,
 |  | OUT UINT8 * | RootPortFun
 | ) |  |

Get Hybrid Graphics Root Port Device and Function Number by Root Port physical Number.

Parameters
[in] | HgSupport | Take policy value to support HG on PEG port.
[out] | RpDev | Return corresponding root port device number.
[out] | RpFun | Return corresponding root port function number.
Return values
EFI_SUCCESS Root port device and function is retrieved
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridGraphicsInfoFruLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
HybridGraphicsInfoFruLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Hybrid Graphics Info Fru Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef HYBRID_GRAPHICS_INFO_FRU_LIB_H_
36 #define HYBRID_GRAPHICS_INFO_FRU_LIB_H_
37
38 /**
39 Get Hybrid Graphics Root Port Device and Function Number by Root Port physical Number
40
41 @param[in] HgSupport Take policy value to support HG on PEG port.
42 @param[out] RpDev Return corresponding root port device number.
43 @param[out] RpFun Return corresponding root port function number.
44
45 @retval EFI_SUCCESS Root port device and function is retrieved
46 **/
47 EFI_STATUS
48 EFIAPI
49 GetHybridGraphicsRpDevFun (
50 IN UINT8 HgSupport,
51 OUT UINT8 *RootPortDev,
52 OUT UINT8 *RootPortFun
53 );
54
55 #endif // HYBRID_GRAPHICS_INFO_FRU_LIB_H_
GetHybridGraphicsRpDevFun
EFI_STATUS GetHybridGraphicsRpDevFun(IN UINT8 HgSupport, OUT UINT8 *RootPortDev, OUT UINT8 *RootPortFun)
Get Hybrid Graphics Root Port Device and Function Number by Root Port physical Number.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridStorageConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
Classes
HybridStorageConfig.h File Reference

Hybrid Storage policy. More...

#include <ConfigBlock.h>
Include dependency graph for HybridStorageConfig.h:
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Classes

struct HYBRID_STORAGE_CONFIG
The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device. More...

Detailed Description

Hybrid Storage policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file HybridStorageConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridStorageConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
HybridStorageConfig.h
Go to the documentation of this file.
1 /** @file
2 Hybrid Storage policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _HYBRID_STORAGE_CONFIG_H_
36 #define _HYBRID_STORAGE_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define HYBRID_STORAGE_CONFIG_REVISION 2
41
42 extern EFI_GUID gHybridStorageConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device
48
49 <b>Revision 1</b>:
50 - Init version
51 <b>Revision 2</b>:
52 - Added support for cpu attached hybrid storage
53 **/
54 typedef struct {
55 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
56 /**
57 Hybrid Storage Mode
58 <b>0: Disable</b>, 1: Enable Dynamic Configuration
59 **/
60 UINT8 HybridStorageMode;
61 UINT8 CpuRootportUsedForHybridStorage;
62 UINT8 PchRootportUsedForCpuAttach;
63 UINT8 RsvdBytes[1];
64 } HYBRID_STORAGE_CONFIG;
65
66 #pragma pack (pop)
67
68 #endif // _HYBRID_STORAGE_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
HYBRID_STORAGE_CONFIG
The HYBRID_STORAGE_CONFIG block describes the expected configuration for Hybrid Storage device.
Definition: HybridStorageConfig.h:54
HYBRID_STORAGE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: HybridStorageConfig.h:55
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HYBRID_STORAGE_CONFIG::HybridStorageMode
UINT8 HybridStorageMode
Hybrid Storage Mode 0: Disable, 1: Enable Dynamic Configuration.
Definition: HybridStorageConfig.h:60
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IccMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
IccMsgs.h File Reference

ICC Messages. More...

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Classes

struct | ICC_GET_CLK_CAPABILITIES_MESSAGE
Get/Set ICC Clock Capabilities. More...
union | ICC_CLOCK_SETTINGS_FLAGS
Get/Set Clock Settings. More...
union | ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Used for the CURRENT FLAGS parameter of Get/Set Clock Settings. More...
union | ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings. More...
union | ICC_CLOCK_MODE
Used for the Clock Mode parameter of Get/Set Clock Settings. More...
struct | ICC_CLOCK_SETTINGS
Structure for Clock Settings. More...
struct | ICC_GETSET_CLOCK_SETTINGS_REQRSP
Combined Request and Response structure for Get/Set Clock Settings. More...
struct | ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
This is only a template. More...
struct | ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ
Get Soft Strap Config. More...

Macros

#define | MAX_NUM_ICC_PROFILES 16
Get/Set ICC Profile.
#define | ICC_PROGRAMMING_TYPE_PERSISTENT 0
definitions for ICC Programming Type More...
#define | ICC_PROGRAMMING_TYPE_DYNAMIC 1
Dynamic. More...
#define | REQUESTED_CLOCK_GEN2_PCIE 0
Requested Clock. More...
#define | ICC_WHITE_MOUNTAIN_PHY_CLK 2
White Mountain Phy.
#define | ICC_CURRENT_SETTINGS 0
Setting Type. More...
#define | ICC_SSC_MODE_DOWN 2
Spread Spectrum Clocking Mode (Up, Down, Center, None), based on the HW register settings. More...

Enumerations

enum | ICC_COMMAND_ID
enum | ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE
ICC Soft Strap Config.

Detailed Description

ICC Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IccMsgs.h.

Macro Definition Documentation

◆ ICC_CURRENT_SETTINGS

#define ICC_CURRENT_SETTINGS 0

Setting Type.

Selects the source of to retrieve the clock settings. If not found it the selected settings, defaults to current settings. Current Settings - Returns the clock frequency/spread based on the currently active HW register values.

Definition at line 382 of file IccMsgs.h.

◆ ICC_PROGRAMMING_TYPE_DYNAMIC

#define ICC_PROGRAMMING_TYPE_DYNAMIC 1

Dynamic.

Will be programmed immediately. And reprogrammed again on S3/S4 exit. Configuration will be lost after global reset/S5/G3. THIS VALUE SHOULD BE USED FOR SPS.

Definition at line 316 of file IccMsgs.h.

◆ ICC_PROGRAMMING_TYPE_PERSISTENT

#define ICC_PROGRAMMING_TYPE_PERSISTENT 0

definitions for ICC Programming Type

Persistent. Save the configuration as a permanent/Persistent. Will be performed for the first time after next global reset.

Definition at line 312 of file IccMsgs.h.

◆ ICC_SSC_MODE_DOWN

#define ICC_SSC_MODE_DOWN 2

Spread Spectrum Clocking Mode (Up, Down, Center, None), based on the HW register settings.

Only Down-spread currently supported. Down

Definition at line 388 of file IccMsgs.h.

◆ REQUESTED_CLOCK_GEN2_PCIE

#define REQUESTED_CLOCK_GEN2_PCIE 0

Requested Clock.

Specifies an index of the clock capabilities to "Get" or "Set".

Definition at line 374 of file IccMsgs.h.

Enumeration Type Documentation

◆ ICC_COMMAND_ID

enum ICC_COMMAND_ID
Enumerator
ICC_READ_FROM_MPHY_CMD

Commands 0-15 except 10 not used.

Definition at line 124 of file IccMsgs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IccMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
IccMsgs.h
Go to the documentation of this file.
1 /** @file
2 ICC Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ICC_MSGS_H
37 #define _ICC_MSGS_H
38
39 #pragma pack(1)
40
41 //
42 // macro for determining length of ICC message buffer
43 //
44 #define ICC_MESSAGE_BUFFER_LENGTH(a) (a-sizeof(ICC_HEADER))
45
46 //
47 // definitions for ICC MEI Messages
48 //
49 #define ICC_API_VERSION 0x00050000
50
51 typedef enum {
52 ICC_STATUS_SUCCESS = 0x0,
53 ICC_STATUS_FAILURE = 0x1,
54 ICC_STATUS_INCORRECT_API_VERSION = 0x2,
55 ICC_STATUS_INVALID_FUNCTION = 0x3,
56 ICC_STATUS_INVALID_BUFFER_LENGTH = 0x4,
57 ICC_STATUS_INVALID_PARAMS = 0x5,
58 ICC_STATUS_FLASH_WEAR_OUT_VIOLATION = 0x6,
59 ICC_STATUS_FLASH_CORRUPTION = 0x7,
60 ICC_STATUS_PROFILE_NOT_SELECTABLE_BY_BIOS = 0x8,
61 ICC_STATUS_TOO_LARGE_PROFILE_INDEX = 0x9,
62 ICC_STATUS_NO_SUCH_PROFILE_IN_FLASH = 0xA,
63 ICC_STATUS_CMD_NOT_SUPPORTED_AFTER_END_OF_POST = 0xB,
64 ICC_STATUS_NO_SUCH_RECORD = 0xC,
65 ICC_STATUS_FILE_NOT_FOUND = 0xD,
66 ICC_STATUS_INVALID_RECORD_FORMAT = 0xE,
67 ICC_STATUS_TOO_LARGE_UOB_RECORD = 0xF,
68 ICC_STATUS_CLOCK_NOT_CONFIGURABLE = 0x10,
69 ICC_STATUS_REGISTER_IS_LOCKED = 0x11,
70 ICC_STATUS_NO_VALID_PRE_UOB = 0x12,
71 ICC_STATUS_NO_VALID_PERM_UOB = 0x13,
72 ICC_STATUS_NO_DATA_FOR_THIS_CLOCK = 0x14,
73 ICC_STATUS_PROFILE_INDEX_IS_CURRENT = 0x15,
74 ICC_STATUS_NO_BCLK_ADJUSTMENT_FOUND = 0x16,
75 ICC_STATUS_WARM_RESET_RAMP_NOT_SUPPORTED = 0x17,
76 ICC_STATUS_UOB_RECORD_IS_ALREADY_INVALID = 0x18,
77 ICC_STATUS_NO_PROFILES_EXIST = 0x19,
78 ICC_STATUS_AUTH_FAILURE = 0x1A,
79 ICC_STATUS_ERROR_READING_FILE = 0x1B,
80 ICC_STATUS_RANGE_VIOLATION_FREQ_TOO_HIGH = 0x1C,
81 ICC_STATUS_HW_VIOLATION_FREQ_TOO_HIGH = 0x1D,
82 ICC_STATUS_PENDING_REVERT_TO_DEFAULT = 0x1E,
83 ICC_STATUS_PENDING_SET_PROFILE = 0x1F,
84 ICC_STATUS_UNVALID_PROFILE = 0x20,
85 ICC_STATUS_UNVALID_OEM_DATA = 0x21,
86 ICC_STATUS_ERROR_READING_DYNAMIC_RECORD = 0x22,
87 ICC_STATUS_RESERVED35 = 0x23,
88 ICC_STATUS_RANGE_VIOLATION_FREQ_TOO_LOW = 0x24,
89 ICC_STATUS_HW_VIOLATION_FREQ_TOO_LOW = 0x25,
90 ICC_STATUS_GET_REGISTER_NO_SUCH_REG = 0x26,
91 ICC_STATUS_RESERVED39 = 0x27,
92 ICC_STATUS_RESERVED40 = 0x28,
93 ICC_STATUS_RESERVED41 = 0x29,
94 ICC_STATUS_RESERVED42 = 0x2A,
95 ICC_STATUS_RESERVED43 = 0x2B,
96 ICC_STATUS_SSC_MODE_CHANGE_NOT_SUPPORTED = 0x2C,
97 ICC_STATUS_RANGE_VIOLATION_SSC_TOO_HIGH = 0x2D,
98 ICC_STATUS_RESERVED46 = 0x2E,
99 ICC_STATUS_RESERVED47 = 0x2F,
100 ICC_STATUS_RESERVED48 = 0x30,
101 ICC_STATUS_RESERVED49 = 0x31,
102 ICC_STATUS_SURVIVABILITY_SYNC_DISABLED = 0x32,
103 ICC_STATUS_WARM_RESET_FREQ_TOO_LOW = 0x33,
104 ICC_STATUS_NO_SUCH_TARGET_ID = 0x34,
105 ICC_STATUS_NO_SUCH_REGISTER = 0x35,
106 ICC_STATUS_INVALIDATE_SUCCESSFUL = 0x36,
107 ICC_STATUS_BUFFER_TOO_SMALL = 0x37,
108 ICC_STATUS_VALID_UOB_ALREADY_PRESENT = 0x38,
109 ICC_STATUS_WAITING_FOR_POWER_CYCLE = 0x39,
110 ICC_STATUS_SURVIVABILITY_TABLE_ACCESS_VIOLATION = 0x3A,
111 ICC_STATUS_SURVIVABILITY_TABLE_TOO_LARGE = 0x3B,
112 ICC_STATUS_NO_SUCH_EID = 0x3C,
113 ICC_STATUS_SUCCESS_TRANSLATE_ONLY = 0x3D,
114 ICC_STATUS_CMD_NOT_SUPPORTED_BEFORE_DID = 0x40,
115 ICC_STATUS_FIA_MUX_CONFIG_SKU_MISMATCH = 0x41,
116 ICC_STATUS_FIA_MUX_NO_CONFIG_FOUND = 0x42,
117 ICC_STATUS_MAX_BUNDLES_PER_RECORD_REACHED = 0x500,
118 ICC_STATUS_PLL_UNSUPPORTED = 0x501,
119 ICC_STATUS_DATA_ITEM_UNSUPPORTED = 0x502,
120 ICC_STATUS_OEM_PROFILE_CRDR_VIOLATION = 0x503,
121 ICC_STATUS_UNSPECIFIED_ERROR = 0xFFFF
122 } ICC_CMD_STATUS;
123
124 typedef enum {
125 ///
126 /// Commands 0-15 except 10 not used.
127 ///
128 ICC_READ_FROM_MPHY_CMD = 0xA,
129 ICC_GET_PROFILE_CMD = 0x10,
130 ICC_SET_PROFILE_CMD = 0x11,
131 ICC_GET_REGISTERS_LOCK_CMD = 0x12,
132 ICC_SET_REGISTERS_LOCK_CMD = 0x13,
133 ICC_GET_CLOCK_CAPABILITIES_CMD = 0x14,
134 ICC_GET_CLOCK_RANGE_DEF_REC_CMD = 0x15,
135 ICC_GET_RECORD_CMD = 0x16,
136 ICC_SET_RECORD_CMD = 0x17,
137 ICC_GET_MPHY_SETTINGS_CMD = 0x18,
138 ICC_SET_MPHY_SETTINGS_CMD = 0x19,
139 ICC_GET_CLOCK_SETTINGS_CMD = 0x1A,
140 ICC_SET_CLOCK_SETTINGS_CMD = 0x1B,
141 ICC_SET_FIA_MUX_CONFIG_CMD = 0x1E,
142 ICC_GET_FIA_MUX_CONFIG_CMD = 0x1F,
143 ICC_OVERRIDE_SOFT_STRAP_CMD = 0x27,
144 ICC_GET_SOFT_STRAP_CONFIG_CMD = 0x28
145 } ICC_COMMAND_ID;
146
147 typedef struct {
148 UINT32 ApiVersion;
149 ICC_COMMAND_ID IccCommand;
150 ICC_CMD_STATUS IccResponse;
151 UINT32 BufferLength;
152 UINT32 Reserved;
153 } ICC_HEADER;
154
155 //
156 // Defines the HECI request buffer format for the ICC_READ_FROM_MPHY_CMD.
157 //
158 typedef struct {
159 ICC_HEADER Header; ///< Standard ICC HECI Header
160 UINT32 Reserved1; ///< Reserved for future use
161 UINT32 Offset; ///< Offset in the mPhy file to start reading from
162 UINT32 Reserved2; ///< Reserved for future use
163 UINT32 NumOfBytes; ///< How many bytes to read. For the entire file specify the mPhy max size
164 } ICC_READ_FROM_MPHY_REQ;
165
166 //
167 // Defines the HECI request buffer format for response to ICC_READ_FROM_MPHY_CMD.
168 //
169 typedef struct {
170 ICC_HEADER Header; ///< Standard ICC HECI Header
171 UINT32 Reserved1; ///< Reserved for future use
172 UINT32 FileSize; ///< mPhy file size. This will be filled regardless of how many bytes the user asked to read (e.g. zero)
173 UINT32 Reserved2; ///< Reserved for future use
174 UINT32 ReadSize; ///< How many bytes were actually read, having less than requested is NOT an error
175 UINT32 Reserved3; ///< Reserved for future use
176 UINT8 Payload[]; ///< The binary content requested (or at least as many bytes as we could read)
177 } ICC_READ_FROM_MPHY_ACK;
178
179 typedef union {
180 ICC_READ_FROM_MPHY_REQ Request;
181 ICC_READ_FROM_MPHY_ACK Response;
182 } ICC_READ_FROM_MPHY_BUFFER;
183
184 ///
185 /// Get/Set ICC Profile
186 ///
187 #define MAX_NUM_ICC_PROFILES 16
188
189 typedef struct {
190 ICC_HEADER Header;
191 } ICC_GET_PROFILE_MESSAGE;
192
193 typedef struct {
194 UINT8 IccProfileName[24];
195 UINT8 IccProfileBase[24];
196 } ICC_PROFILE_DESC;
197
198 typedef struct {
199 ICC_HEADER Header;
200 UINT8 IccNumOfProfiles;
201 union {
202 UINT8 Data;
203 struct {
204 UINT8 IccFailsafeProfile : 4;
205 UINT8 Reserved : 3;
206 UINT8 IccRuntimeSelect : 1;
207 } Fields;
208 } OemParams;
209 UINT8 IccProfileIndex;
210 UINT8 Reserved;
211 ICC_PROFILE_DESC IccProfileDesc[MAX_NUM_ICC_PROFILES];
212 } ICC_GET_PROFILE_RESPONSE;
213
214 typedef union {
215 ICC_GET_PROFILE_MESSAGE Message;
216 ICC_GET_PROFILE_RESPONSE Response;
217 } ICC_GET_PROFILE_BUFFER;
218
219 typedef struct {
220 ICC_HEADER Header;
221 UINT8 BiosIccProfile;
222 UINT8 PaddingA;
223 UINT16 PaddingB;
224 } ICC_SET_PROFILE_MESSAGE;
225
226 typedef struct {
227 ICC_HEADER Header;
228 } ICC_SET_PROFILE_RESPONSE;
229
230 typedef union {
231 ICC_SET_PROFILE_MESSAGE Message;
232 ICC_SET_PROFILE_RESPONSE Response;
233 } ICC_SET_PROFILE_BUFFER;
234
235 ///
236 /// Get/Set ICC Clock Capabilities
237 ///
238 typedef struct {
239 ICC_HEADER Header;
240 } ICC_GET_CLK_CAPABILITIES_MESSAGE;
241
242 typedef struct {
243 ICC_HEADER Header;
244 UINT32 VersionNumber;
245 UINT8 IccHwSku;
246 UINT8 Reserved;
247 UINT16 MaxSusramRecordSize;
248 UINT64 IccSkuEnforcementTable;
249 UINT32 IccBootStatusReport;
250 } ICC_GET_CLK_CAPABILITIES_RESPONSE;
251
252 typedef union {
253 ICC_GET_CLK_CAPABILITIES_MESSAGE Message;
254 ICC_GET_CLK_CAPABILITIES_RESPONSE Response;
255 } ICC_GET_CLK_CAPABILITIES_BUFFER;
256
257 //
258 // Defines the HECI request buffer format for the ICC_HSIO_WRITE_SETTINGS_CMD.
259 //
260 typedef struct {
261 ICC_HEADER Header; ///< Standard ICC HECI Header
262 UINT32 Reserved; ///< Reserved for future use
263 } HSIO_WRITE_SETTINGS_REQ;
264
265 ///
266 /// Get/Set Clock Settings
267 ///
268
269 ///
270 /// Used for the FLAGS parameter of Get/Set Clock Settings
271 ///
272 typedef union {
273 UINT8 u;
274 struct {
275 UINT8 RoundDown : 1;
276 UINT8 Reserved : 7;
277 } Flags;
278 } ICC_CLOCK_SETTINGS_FLAGS;
279
280 ///
281 /// Used for the CURRENT FLAGS parameter of Get/Set Clock Settings
282 ///
283 typedef union {
284 UINT16 u;
285 struct {
286 UINT16 Reserved : 3; ///< Reserved.
287 UINT16 ForcePowerFlow : 1; ///< This indicates that the clock settings will include a power flow, depending on the specific platform.
288 /**
289 Specifies how the settings with associated clock were applied.
290 0 - Persistent
291 1 - Dynamic , indicating a run time ad-hoc change (ramp)
292 2 - Reserved
293 3 - Reserved
294 **/
295 UINT16 Type : 2;
296 UINT16 SetToDefault : 1; ///< Revert this clock to nominal.
297 UINT16 Reserved1 : 3; ///< Reserved.
298 /**
299 New Boot settings applied and power cycle reset pending.
300 Flag cleared once boot settings are consumed.
301 Reserved in Set Clock Settings.
302 **/
303 UINT16 PwrCyclePending : 1;
304 UINT16 Reserved2 : 5;
305 } Flags;
306 } ICC_CLOCK_SETTINGS_CURRENT_FLAGS;
307
308 ///
309 /// definitions for ICC Programming Type
310 ///
311 #define ICC_PROGRAMMING_TYPE_PERSISTENT 0 ///< Persistent. Save the configuration as a permanent/Persistent.
312 ///< Will be performed for the first time after next global reset.
313 #define ICC_PROGRAMMING_TYPE_DYNAMIC 1 ///< Dynamic. Will be programmed immediately.
314 ///< And reprogrammed again on S3/S4 exit.
315 ///< Configuration will be lost after global reset/S5/G3.
316 ///< THIS VALUE SHOULD BE USED FOR SPS.
317
318 ///
319 /// Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings
320 ///
321 typedef union {
322 UINT16 u;
323 struct {
324 UINT16 Reserved : 1; ///< Reserved.
325 UINT16 DownSpread : 1; ///< Down spread SSC supported.
326 UINT16 UpSpread : 1; ///< Up spread SSC supported.
327 UINT16 CenterSpread : 1; ///< Center spread SSC supported.
328 UINT16 ChangeAllowed : 1; ///< Frequency & Spread changes allowed.
329 UINT16 HaltAllowed : 1; ///< Spread can be enabled or disabled.
330 UINT16 PCIe : 1; ///< Clock uses the PCIe clock source
331 UINT16 Bclk : 1; ///< Clock uses the BCLK clock source
332 UINT16 Reserved1 : 8; ///< Reserved.
333 } Flags;
334 } ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS;
335
336 ///
337 /// Used for the Clock Mode parameter of Get/Set Clock Settings
338 ///
339 typedef union {
340 UINT8 u;
341 struct {
342 UINT8 PlatformClockingMode : 4;
343 UINT8 Alternate : 1;
344 UINT8 Reserved : 3;
345 } Flags;
346 } ICC_CLOCK_MODE;
347
348 #define ICC_PLATFORM_CLOCKING_MODE_INTERNAL 0
349 #define ICC_PLATFORM_CLOCKING_MODE_EXTERNAL 2
350
351 ///
352 /// Structure for Clock Settings
353 ///
354 typedef struct {
355 UINT8 ReqClock;
356 UINT8 SettingType;
357 ICC_CLOCK_SETTINGS_FLAGS Flags;
358 ICC_CLOCK_MODE ClockMode;
359 UINT32 Freq;
360 UINT32 UserFreq;
361 UINT32 MaxFreq;
362 UINT32 MinFreq;
363 UINT8 SscMode;
364 UINT8 SscPercent;
365 UINT8 MaxSscPercent;
366 UINT8 Reserved1;
367 ICC_CLOCK_SETTINGS_CURRENT_FLAGS CurrentFlags;
368 ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS SupportFlags;
369 } ICC_CLOCK_SETTINGS;
370
371 ///
372 /// Requested Clock. Specifies an index of the clock capabilities to "Get" or "Set".
373 ///
374 #define REQUESTED_CLOCK_GEN2_PCIE 0
375 #define REQUESTED_CLOCK_IS_CLK_BCLK 1
376 #define ICC_WHITE_MOUNTAIN_PHY_CLK 2 ///< White Mountain Phy
377 ///
378 /// Setting Type. Selects the source of to retrieve the clock settings. If not
379 /// found it the selected settings, defaults to current settings.
380 ///
381 #define ICC_CURRENT_SETTINGS 0 ///< Current Settings - Returns the clock frequency/spread
382 ///< based on the currently active HW register values.
383
384 ///
385 /// Spread Spectrum Clocking Mode (Up, Down, Center, None), based on the HW
386 /// register settings. Only Down-spread currently supported.
387 ///
388 #define ICC_SSC_MODE_DOWN 2 ///< Down
389
390
391 ///
392 /// Combined Request and Response structure for Get/Set Clock Settings
393 ///
394 typedef struct {
395 ICC_HEADER Header;
396 ICC_CLOCK_SETTINGS ClockSettings;
397 } ICC_GETSET_CLOCK_SETTINGS_REQRSP;
398
399 typedef union {
400 ICC_GETSET_CLOCK_SETTINGS_REQRSP Message;
401 ICC_GETSET_CLOCK_SETTINGS_REQRSP Response;
402 } ICC_GET_CLOCK_SETTINGS_BUFFER;
403
404 typedef union {
405 ICC_GETSET_CLOCK_SETTINGS_REQRSP Message;
406 ICC_GETSET_CLOCK_SETTINGS_REQRSP Response;
407 } ICC_SET_CLOCK_SETTINGS_BUFFER;
408
409 //
410 // Defines the HECI request buffer format for the ICC_HSIO_WRITE_SETTINGS_CMD.
411 //
412 typedef struct {
413 ICC_HEADER Header; ///< Standard ICC HECI Header
414 UINT32 Reserved; ///< Reserved for future use
415 UINT8 MphyData[]; ///< Payload
416 } ICC_SET_MPHY_SETTINGS_REQ;
417
418 //
419 // Defines the HECI request buffer format for response to the ICC_HSIO_WRITE_SETTINGS_CMD.
420 //
421 typedef struct {
422 ICC_HEADER Header; ///< Standard ICC HECI Header
423 } ICC_SET_MPHY_SETTINGS_RSP;
424
425 //
426 // Defines the HECI request buffer format for the ICC_HSIO_READ_MPHY_CMD.
427 //
428 typedef struct {
429 ICC_HEADER Header; ///< Standard ICC HECI Header
430 UINT32 Reserved; ///< Reserved for future use
431 UINT32 Offset; ///< Offset in the mPhy file to start reading from
432 UINT32 Reserved2; ///< Reserved for future use
433 UINT32 NumBytesToRead; ///< How many bytes to read. For the entire file specify the mPhy max size
434 } HSIO_READ_MPHY_REQ;
435
436 //
437 // Defines the HECI request buffer format for response to ICC_HSIO_READ_MPHY_CMD.
438 //
439 typedef struct {
440 ICC_HEADER Header; ///< Standard ICC HECI Header
441 UINT32 Reserved; ///< Reserved for future use
442 UINT32 MphyFileSize; ///< mPhy file size. This will be filled regardless of how many bytes the user asked to read (e.g. zero)
443 UINT32 Reserved2; ///< Reserved for future use
444 UINT32 NumBytesActuallyRead; ///< How many bytes were actually read, having less than requested is NOT an error
445 UINT32 Reserved3; ///< Reserved for future use
446 UINT8 Payload[]; ///< The binary content requested (or at least as many bytes as we could read)
447 } HSIO_READ_MPHY_ACK;
448
449 typedef union {
450 HSIO_READ_MPHY_REQ Request;
451 HSIO_READ_MPHY_ACK Response;
452 } HSIO_READ_MPHY_BUFFER;
453
454 ///
455 /// ICC Soft Strap Config
456 ///
457 typedef enum {
458 PcieOverrideNone = 0,
459 PcieOverride1x4 = 1,
460 PcieOverride2x2 = 2,
461 PcieOverride1x2_2x1 = 3,
462 PcieOverride4x1 = 4
463 } ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE;
464
465 ///
466 /// This is only a template. Data should be filled in runtime
467 ///
468 typedef struct {
469 ICC_HEADER Header;
470 /**
471 Number of PCI-E ports to be configured
472 **/
473 UINT16 NumOfControllers;
474 /**
475 Please refer to ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE
476 **/
477 UINT8 ControllerConfig [0];
478 ///
479 /// The ControllerConfig field size varies and it is followed by Reserved field.
480 /// UINT32 Reserved[4];
481 ///
482 } ICC_OVERRIDE_SOFT_STRAP_CMD_REQ;
483
484 typedef struct {
485 ICC_HEADER Header;
486 } ICC_OVERRIDE_SOFT_STRAP_CMD_RESP;
487
488 typedef union {
489 ICC_OVERRIDE_SOFT_STRAP_CMD_REQ Message;
490 ICC_OVERRIDE_SOFT_STRAP_CMD_RESP Response;
491 } ICC_OVERRIDE_PCIE_SOFT_STRAP_CMD_BUFFER;
492 ///
493 /// Get Soft Strap Config
494 ///
495 typedef struct {
496 ICC_HEADER Header;
497 } ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ;
498
499 #define ICC_GET_SOFT_STRAP_CONFIG_CMD_RESP ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
500
501 typedef union {
502 ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ Message;
503 ICC_GET_SOFT_STRAP_CONFIG_CMD_RESP Response;
504 } ICC_GET_SOFT_STRAP_CONFIG_CMD_BUFFER;
505
506 #pragma pack()
507
508 #endif // _ICC_MSGS_H
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::DownSpread
UINT16 DownSpread
Down spread SSC supported.
Definition: IccMsgs.h:325
ICC_CLOCK_SETTINGS_CURRENT_FLAGS
Used for the CURRENT FLAGS parameter of Get/Set Clock Settings.
Definition: IccMsgs.h:283
ICC_GETSET_CLOCK_SETTINGS_REQRSP
Combined Request and Response structure for Get/Set Clock Settings.
Definition: IccMsgs.h:394
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::UpSpread
UINT16 UpSpread
Up spread SSC supported.
Definition: IccMsgs.h:326
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::Bclk
UINT16 Bclk
Clock uses the BCLK clock source.
Definition: IccMsgs.h:331
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::CenterSpread
UINT16 CenterSpread
Center spread SSC supported.
Definition: IccMsgs.h:327
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::Reserved
UINT16 Reserved
Reserved.
Definition: IccMsgs.h:324
ICC_GET_CLK_CAPABILITIES_MESSAGE
Get/Set ICC Clock Capabilities.
Definition: IccMsgs.h:238
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::Type
UINT16 Type
Specifies how the settings with associated clock were applied.
Definition: IccMsgs.h:295
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::Reserved
UINT16 Reserved
Reserved.
Definition: IccMsgs.h:286
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::Reserved1
UINT16 Reserved1
Reserved.
Definition: IccMsgs.h:297
ICC_CLOCK_MODE
Used for the Clock Mode parameter of Get/Set Clock Settings.
Definition: IccMsgs.h:339
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::PCIe
UINT16 PCIe
Clock uses the PCIe clock source.
Definition: IccMsgs.h:330
ICC_CLOCK_SETTINGS
Structure for Clock Settings.
Definition: IccMsgs.h:354
ICC_OVERRIDE_SOFT_STRAP_CMD_REQ::NumOfControllers
UINT16 NumOfControllers
Number of PCI-E ports to be configured.
Definition: IccMsgs.h:473
ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE
ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE
ICC Soft Strap Config.
Definition: IccMsgs.h:457
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::HaltAllowed
UINT16 HaltAllowed
Spread can be enabled or disabled.
Definition: IccMsgs.h:329
ICC_COMMAND_ID
ICC_COMMAND_ID
Definition: IccMsgs.h:124
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS
Used for the SUPPORTED FLAGS parameter of Get/Set Clock Settings.
Definition: IccMsgs.h:321
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::PwrCyclePending
UINT16 PwrCyclePending
New Boot settings applied and power cycle reset pending.
Definition: IccMsgs.h:303
ICC_READ_FROM_MPHY_CMD
@ ICC_READ_FROM_MPHY_CMD
Commands 0-15 except 10 not used.
Definition: IccMsgs.h:128
MAX_NUM_ICC_PROFILES
#define MAX_NUM_ICC_PROFILES
Get/Set ICC Profile.
Definition: IccMsgs.h:187
ICC_OVERRIDE_SOFT_STRAP_CMD_REQ
This is only a template.
Definition: IccMsgs.h:468
ICC_CLOCK_SETTINGS_FLAGS
Get/Set Clock Settings.
Definition: IccMsgs.h:272
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::SetToDefault
UINT16 SetToDefault
Revert this clock to nominal.
Definition: IccMsgs.h:296
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::Reserved1
UINT16 Reserved1
Reserved.
Definition: IccMsgs.h:332
ICC_CLOCK_SETTINGS_SUPPORTED_FLAGS::ChangeAllowed
UINT16 ChangeAllowed
Frequency & Spread changes allowed.
Definition: IccMsgs.h:328
ICC_CLOCK_SETTINGS_CURRENT_FLAGS::ForcePowerFlow
UINT16 ForcePowerFlow
This indicates that the clock settings will include a power flow, depending on the specific platform.
Definition: IccMsgs.h:287
ICC_GET_SOFT_STRAP_CONFIG_CMD_REQ
Get Soft Strap Config.
Definition: IccMsgs.h:495
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IehConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Classes
IehConfig.h File Reference

Integrated Error Handler policy. More...

#include <ConfigBlock.h>
Include dependency graph for IehConfig.h:
This graph shows which files directly or indirectly include this file:

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Classes

struct IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler. More...

Detailed Description

Integrated Error Handler policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IehConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IehConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
IehConfig.h
Go to the documentation of this file.
1 /** @file
2 Integrated Error Handler policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _IEH_CONFIG_H_
37 #define _IEH_CONFIG_H_
38
39 #include <ConfigBlock.h>
40
41 #define IEH_MODE_BYPASS 0
42 #define IEH_MODE_ENABLE 1
43
44 #define IEH_CONFIG_REVISION 1
45 extern EFI_GUID gIehConfigGuid;
46
47 #pragma pack (push,1)
48
49 /**
50 The IEH_CONFIG block describes the expected configuration of the PCH
51 Integrated Error Handler.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
55 /**
56 IEH mode <b>0: Bypass Mode</b>; 1: Enable
57 **/
58 UINT32 Mode : 1;
59 UINT32 RsvdBits0 : 31; ///< Reserved bits
60 } IEH_CONFIG;
61
62 #pragma pack (pop)
63
64 #endif // _IEH_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IEH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: IehConfig.h:59
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IEH_CONFIG
The IEH_CONFIG block describes the expected configuration of the PCH Integrated Error Handler.
Definition: IehConfig.h:53
IEH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IehConfig.h:54
IEH_CONFIG::Mode
UINT32 Mode
IEH mode 0: Bypass Mode; 1: Enable.
Definition: IehConfig.h:58
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IgdOpRegion.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes
IgdOpRegion.h File Reference

This file is part of the IGD OpRegion Implementation. More...

#include <IndustryStandard/IgdOpRegion.h>
Include dependency graph for IgdOpRegion.h:

Go to the source code of this file.

Classes

struct IGD_OPREGION_PROTOCOL
IGD OpRegion Protocol. More...

Detailed Description

This file is part of the IGD OpRegion Implementation.

The IGD OpRegion is an interface between system BIOS, ASL code, and Graphics drivers.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:
  • IGD OpRegion/Software SCI SPEC

Definition in file IgdOpRegion.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IgdOpRegion.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
IgdOpRegion.h
Go to the documentation of this file.
1 /** @file
2 This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
3 an interface between system BIOS, ASL code, and Graphics drivers.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2016 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 - IGD OpRegion/Software SCI SPEC
36 **/
37 #ifndef _IGD_OPREGION_PROTOCOL_H_
38 #define _IGD_OPREGION_PROTOCOL_H_
39
40 #include <IndustryStandard/IgdOpRegion.h>
41
42 extern EFI_GUID gIgdOpRegionProtocolGuid;
43
44 ///
45 /// IGD OpRegion Protocol
46 ///
47 typedef struct {
48 IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
49 } IGD_OPREGION_PROTOCOL;
50
51 #endif
IGD_OPREGION_PROTOCOL::OpRegion
IGD_OPREGION_STRUCTURE * OpRegion
IGD Operation Region Structure.
Definition: IgdOpRegion.h:48
IGD_OPREGION_PROTOCOL
IGD OpRegion Protocol.
Definition: IgdOpRegion.h:47
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IndustryStandardAsf.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
IndustryStandardAsf.h File Reference

Include file for Industry Standard ASF definition. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | BOOT_OPTION_CAPS_STRUC
Boot Options/System Firmware Capabilities Bit Mask. More...
struct | SPECIAL_COMMAND_CAPS_STRUC
Special Commands Bit Mask. More...
struct | SYSTEM_CAPS_STRUC
System Capabilities Bit Mask. More...

Macros

#define | ASF_MESSAGE_COMMAND_SENSOR_DEVICE_SYSTEM_STATE 0x01
ASF Messages Command.
#define | ASF_MESSAGE_SUBCOMMAND_GET_EVENT_DATA 0x11
ASF Messages Sub-Command for Command SENSOR_DEVICE_SYSTEM_STATE (0x01)
#define | ASF_MESSAGE_SUBCOMMAND_START_WATCH_DOG_TIMER 0x13
ASF Messages Sub-Command for Command MANAGEMENT_CONTROL (0x02)
#define | ASF_MESSAGE_SUBCOMMAND_CLEAR_BOOT_OPT 0x15
ASF Messages Sub-Command for Command ASF_CONFIGURATION (0x03)
#define | ASF_MESSAGE_SUBCOMMAND_SET_ALERT_CONFIG 0x11
ASF Messages Sub-Command for Command MESSAGE (0x04)
#define | ASF_EVENT_SENSOR_TYPE_TEMPERATURE 0x01
ASF Event Sensor Type Codes.
#define | ASF_EVENT_TYPE_THRESHOLD_BASED 0x01
ASF Event Type Codes IPMI/PET related definition.
#define | ASF_EVENT_OFFSET_ENTITY_PRESENT 0x00
ASF Event Offset Codes IPMI/PET related definition.
#define | ASF_EVENT_SOURCE_TYPE_PLATFORM_FIRMWARE 0x00
ASF Event Source Type Code IPMI/PET related definition.
#define | ASF_EVENT_SEVERITY_CODE_MONITOR 0x01
ASF Event Severity Codes IPMI/PET related definition.
#define | ASF_SENSOR_DEVICE 0xFF
ASF Sensor Device Codes IPMI/PET related definition.
#define | ASF_SENSOR_NUMBER 0xFF
ASF Sensor Number Codes IPMI/PET related definition.
#define | ASF_ENTITY_UNSPECIFIED 0x00
ASF Entity Codes (IPMI Table 43 - Entity ID Codes) IPMI/PET related definition.
#define | ASF_ENTITY_INSTANCE_UNSPECIFIED 0x00
ASF Entity Instance Codes IPMI/PET related definition.
#define | ASF_FP_EVENT_DATA1 0x40
ASF Event Data Codes for System Firmware Progress Events IPMI/PET related definition.
#define | ASF_FE_EVENT_DATA1 0x40
ASF Event Data Codes for System Firmware Error Events IPMI/PET related definition.
#define | ASF_WD_EVENT_DATA1 0x40
ASF Event Data Codes for Watchdog2 Events IPMI/PET related definition.
#define | ASF_INFO_TYPE 0x00
ACPI ASF! Definition. More...
#define | ASF_RMCP_BOOT_OPTION_SUCCESS 0x00
ACPI ASF_RMCP.
#define | LOCK_POWER_BUTTON BIT1
This structure contains ASF! RMCP Remote Control Capabilities. More...
#define | USER_PASSWORD_BYPASS BIT3
Boot Options Bit Mask Byte2 values.
#define | NOP 0x00
Special Command Definitions.
#define | SUPPORT_FORCE_PXE BIT0
Special Command Bit Mask Byte2 values.
#define | SUPPORT_POWER_CYCLE_RESET BIT0
System Capabilities Bit Mask values. More...
#define | SUPPORT_POWER_DOWN BIT1
Supports Power-Down only on the secure port.
#define | SUPPORT_POWER_UP BIT2
Supports Power-Up only on the secure port.
#define | SUPPORT_RESET BIT3
Supports Reset only on the secure port.
#define | SUPPORT_POWER_CYCLE_RESET_COMBO BIT4
Supports Power Cycle Reset on either the compatibility or secure port.
#define | SUPPORT_POWER_DOWN_COMBO BIT5
Supports Power-Down on either the compatibility or secure port.
#define | SUPPORT_POWER_UP_COMBO BIT6
Supports Power-Up on either the compatibility or secure port.
#define | SUPPORT_RESET_COMBO BIT7
Supports Reset on either the compatibility or secure port.

Detailed Description

Include file for Industry Standard ASF definition.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IndustryStandardAsf.h.

Macro Definition Documentation

◆ ASF_INFO_TYPE

#define ASF_INFO_TYPE 0x00

ACPI ASF! Definition.

This field identifies the type of data present in the record's Variable Data field, as well as an indication as to whether this is the last record in the table: Bit(s) Description 7 Last Record. If this bit is set to 1b, then the record is the last one present in the ASF! table. 6:0 Record Type. Identifies the format of the record's Variable Data field, one of: 00h ASF_INFO 01h ASF_ALRT 02h ASF_RCTL 03h ASF_RMCP 04h ASF_ADDR 05h-7Fh Reserved for future definition by this specification

Definition at line 321 of file IndustryStandardAsf.h.

◆ LOCK_POWER_BUTTON

#define LOCK_POWER_BUTTON BIT1

This structure contains ASF! RMCP Remote Control Capabilities.

Boot Options Bit Mask Byte1 values

Definition at line 342 of file IndustryStandardAsf.h.

◆ SUPPORT_POWER_CYCLE_RESET

#define SUPPORT_POWER_CYCLE_RESET BIT0

System Capabilities Bit Mask values.

Supports Power Cycle Reset only on the secure port

Definition at line 426 of file IndustryStandardAsf.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IndustryStandardAsf.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
IndustryStandardAsf.h
Go to the documentation of this file.
1 /** @file
2 Include file for Industry Standard ASF definition
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _INDUSTRY_STANDARD_ASF_H_
36 #define _INDUSTRY_STANDARD_ASF_H_
37
38 #pragma pack (1)
39
40 #define ASF_VERSION 0x10
41
42 ///
43 /// ASF Messages Command
44 ///
45 #define ASF_MESSAGE_COMMAND_SENSOR_DEVICE_SYSTEM_STATE 0x01
46 #define ASF_MESSAGE_COMMAND_MANAGEMENT_CONTROL 0x02
47 #define ASF_MESSAGE_COMMAND_ASF_CONFIGURATION 0x03
48 #define ASF_MESSAGE_COMMAND_MESSAGE 0x04
49
50 ///
51 /// ASF Messages Sub-Command for Command SENSOR_DEVICE_SYSTEM_STATE (0x01)
52 ///
53 #define ASF_MESSAGE_SUBCOMMAND_GET_EVENT_DATA 0x11
54 #define ASF_MESSAGE_SUBCOMMAND_GET_EVENT_STATUS 0x12
55 #define ASF_MESSAGE_SUBCOMMAND_DEVICE_TYPE_POLL 0x13
56 #define ASF_MESSAGE_SUBCOMMAND_SET_SYSTEM_STATE 0x18
57
58 ///
59 /// ASF Messages Sub-Command for Command MANAGEMENT_CONTROL (0x02)
60 ///
61 #define ASF_MESSAGE_SUBCOMMAND_START_WATCH_DOG_TIMER 0x13
62 #define ASF_MESSAGE_SUBCOMMAND_STOP_WATCH_DOG_TIMER 0x14
63
64 ///
65 /// ASF Messages Sub-Command for Command ASF_CONFIGURATION (0x03)
66 ///
67 #define ASF_MESSAGE_SUBCOMMAND_CLEAR_BOOT_OPT 0x15
68 #define ASF_MESSAGE_SUBCOMMAND_RETURN_BOOT_OPT 0x16
69 #define ASF_MESSAGE_SUBCOMMAND_NO_BOOT_OPT 0x17
70
71 ///
72 /// ASF Messages Sub-Command for Command MESSAGE (0x04)
73 ///
74 #define ASF_MESSAGE_SUBCOMMAND_SET_ALERT_CONFIG 0x11
75 #define ASF_MESSAGE_SUBCOMMAND_GET_ALERT_CONFIG 0x12
76 #define ASF_MESSAGE_SUBCOMMAND_RETRANSMIT 0x15
77 #define ASF_MESSAGE_SUBCOMMAND_NORETRANSMIT 0x16
78
79 ///
80 /// ASF Event Sensor Type Codes
81 ///
82 #define ASF_EVENT_SENSOR_TYPE_TEMPERATURE 0x01
83 #define ASF_EVENT_SENSOR_TYPE_VOLTAGE 0x02
84 #define ASF_EVENT_SENSOR_TYPE_FAN 0x04
85 #define ASF_EVENT_SENSOR_TYPE_CHASSIS_INTRUSION 0x05
86 #define ASF_EVENT_SENSOR_TYPE_SECURITY_VIOLATION 0x06
87 #define ASF_EVENT_SENSOR_TYPE_PROCESSOR 0x07
88 #define ASF_EVENT_SENSOR_TYPE_POWER_SUPPLY 0x08
89 #define ASF_EVENT_SENSOR_TYPE_POWER_UNIT 0x09
90 #define ASF_EVENT_SENSOR_TYPE_SYS_FW_ERR_PROG 0x0F
91 #define ASF_EVENT_SENSOR_TYPE_CHIPSET 0x19
92 #define ASF_EVENT_SENSOR_TYPE_BOOT_ERROR 0x1E
93 #define ASF_EVENT_SENSOR_TYPE_OS_BOOT 0x1F
94 #define ASF_EVENT_SENSOR_TYPE_WATCHDOG2 0x23
95 #define ASF_EVENT_SENSOR_TYPE_ENTITY_PRESENCE 0x25
96 #define ASF_EVENT_SENSOR_TYPE_BATTERY 0x29
97
98 ///
99 /// ASF Event Type Codes
100 /// IPMI/PET related definition
101 ///
102 #define ASF_EVENT_TYPE_THRESHOLD_BASED 0x01
103 #define ASF_EVENT_TYPE_USAGE_STATE 0x02
104 #define ASF_EVENT_TYPE_DISCRETE_EVENT_STATE 0x03
105 #define ASF_EVENT_TYPE_DISCRETE_EVENT_PREDICTIVE_FAIL 0x04
106 #define ASF_EVENT_TYPE_DISCRETE_EVENT_LIMIT 0x05
107 #define ASF_EVENT_TYPE_DISCRETE_EVENT_PERFORMANCE 0x06
108 #define ASF_EVENT_TYPE_SEVERITY_STATE 0x07
109 #define ASF_EVENT_TYPE_AVAILABILITY_STATUS_PRESENT 0x08
110 #define ASF_EVENT_TYPE_AVAILABILITY_STATUS_ENABLE 0x09
111 #define ASF_EVENT_TYPE_AVAILABILITY_STATUS_RUNNING 0x0A
112 #define ASF_EVENT_TYPE_AVAILABILITY_STATUS_OTHER 0x0B
113 #define ASF_EVENT_TYPE_DEVICE_POWER_STATES 0x0C
114 #define ASF_EVENT_TYPE_SENSOR_SPECIFIC 0x6F
115
116 ///
117 /// ASF Event Offset Codes
118 /// IPMI/PET related definition
119 ///
120 #define ASF_EVENT_OFFSET_ENTITY_PRESENT 0x00
121 #define ASF_EVENT_OFFSET_TIMER_EXPIRED 0x00
122
123 #define ASF_EVENT_OFFSET_SYS_FW_ERROR 0x00
124 #define ASF_EVENT_OFFSET_SYS_FW_HANG 0x01
125 #define ASF_EVENT_OFFSET_SYS_FW_PROGRESS 0x02
126
127 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_NONCRITICAL 0x00
128 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_NONCRITICAL_GO_HIGH 0x01
129 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_CRITICAL 0x02
130 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_CRITICAL_GO_HIGH 0x03
131 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_NONRECOVERABLE 0x04
132 #define ASF_EVENT_OFFSET_THRESHOLD_LOWER_NONRECOVERABLE_GO_HIGH 0x05
133 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_NONCRITICAL_GO_LOW 0x06
134 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_NONCRITICAL 0x07
135 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_CRITICAL_GO_LOW 0x08
136 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_CRITICAL 0x09
137 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_NONRECOVERABLE_GO_LOW 0x0A
138 #define ASF_EVENT_OFFSET_THRESHOLD_UPPER_NONRECOVERABLE 0x0B
139
140 #define ASF_EVENT_OFFSET_DISCRETE_EVENT_PREDICTIVE_FAIL_DEASSERT 0x00
141 #define ASF_EVENT_OFFSET_DISCRETE_EVENT_PREDICTIVE_FAIL_ASSERT 0x01
142
143 #define ASF_EVENT_OFFSET_SEVERITY_TO_OK 0x00
144 #define ASF_EVENT_OFFSET_SEVERITY_MORE_NONCRITICAL 0x01
145 #define ASF_EVENT_OFFSET_SEVERITY_MORE_CRITICAL 0x02
146 #define ASF_EVENT_OFFSET_SEVERITY_MORE_NONRECOVERABLE 0x03
147 #define ASF_EVENT_OFFSET_SEVERITY_LESS_NONCRITICAL 0x04
148 #define ASF_EVENT_OFFSET_SEVERITY_LESS_CRITICAL 0x05
149 #define ASF_EVENT_OFFSET_SEVERITY_TO_NONRECOVERABLE 0x06
150 #define ASF_EVENT_OFFSET_SEVERITY_MONITOR 0x07
151 #define ASF_EVENT_OFFSET_SEVERITY_INFORMATIONAL 0x08
152
153 #define ASF_EVENT_OFFSET_CHASSIS_INTRUSION_GENERIC 0x00
154
155 #define ASF_EVENT_OFFSET_PROCESSOR_IERR 0x00
156
157 #define ASF_EVENT_OFFSET_SECURITY_VIOLATION_USER_PASSWORD 0x01
158 #define ASF_EVENT_OFFSET_SECURITY_VIOLATION_SUPERVISOR_PASSWORD 0x02
159 #define ASF_EVENT_OFFSET_SECURITY_VIOLATION_NETWORK_PASSWORD 0x03
160 #define ASF_EVENT_OFFSET_SECURITY_VIOLATION_OTHER_PASSWORD 0x04
161 #define ASF_EVENT_OFFSET_SECURITY_VIOLATION_OUTOFBAND_PASSWORD 0x05
162
163 #define ASF_EVENT_OFFSET_BATTERY_LOW_WARNING 0x00
164 #define ASF_EVENT_OFFSET_BATTERY_LOW_CRITICAL 0x01
165 #define ASF_EVENT_OFFSET_BATTERY_PRESENCE_DETECTED 0x02
166
167 #define ASF_EVENT_OFFSET_POWER_SUPPLY_PRESENCE 0x00
168 #define ASF_EVENT_OFFSET_POWER_SUPPLY_FAILURE 0x01
169 #define ASF_EVENT_OFFSET_POWER_SUPPLY_PREDICTIVE_FAILURE 0x02
170
171 #define ASF_EVENT_OFFSET_POWER_UNIT_DOWN 0x00
172 #define ASF_EVENT_OFFSET_POWER_UNIT_CYCLE 0x01
173 #define ASF_EVENT_OFFSET_POWER_UNIT_240VA_DOWN 0x02
174 #define ASF_EVENT_OFFSET_POWER_UNIT_INTERLOCK_DOWN 0x03
175 #define ASF_EVENT_OFFSET_POWER_UNIT_AC_LOST 0x04
176 #define ASF_EVENT_OFFSET_POWER_UNIT_SOFT_CONTROL_FAILURE 0x05
177 #define ASF_EVENT_OFFSET_POWER_UNIT_FAILURE 0x06
178
179 ///
180 /// ASF Event Source Type Code
181 /// IPMI/PET related definition
182 ///
183 #define ASF_EVENT_SOURCE_TYPE_PLATFORM_FIRMWARE 0x00
184 #define ASF_EVENT_SOURCE_TYPE_OS 0x48
185 #define ASF_EVENT_SOURCE_TYPE_ASF10 0x68
186
187 ///
188 /// ASF Event Severity Codes
189 /// IPMI/PET related definition
190 ///
191 #define ASF_EVENT_SEVERITY_CODE_MONITOR 0x01
192 #define ASF_EVENT_SEVERITY_CODE_INFORMATION 0x02
193 #define ASF_EVENT_SEVERITY_CODE_OK 0x04
194 #define ASF_EVENT_SEVERITY_CODE_NONCRITICAL 0x08
195 #define ASF_EVENT_SEVERITY_CODE_CRITICAL 0x10
196 #define ASF_EVENT_SEVERITY_CODE_NONRECOVERABLE 0x20
197
198 ///
199 /// ASF Sensor Device Codes
200 /// IPMI/PET related definition
201 ///
202 #define ASF_SENSOR_DEVICE 0xFF
203
204 ///
205 /// ASF Sensor Number Codes
206 /// IPMI/PET related definition
207 ///
208 #define ASF_SENSOR_NUMBER 0xFF
209
210 ///
211 /// ASF Entity Codes (IPMI Table 43 - Entity ID Codes)
212 /// IPMI/PET related definition
213 ///
214 #define ASF_ENTITY_UNSPECIFIED 0x00
215 #define ASF_ENTITY_OTHER 0x01
216 #define ASF_ENTITY_UNKNOWN 0x02
217 #define ASF_ENTITY_PROCESSOR 0x03
218 #define ASF_ENTITY_DISK 0x04
219 #define ASF_ENTITY_PERIPHERAL 0x05
220 #define ASF_ENTITY_SYSTEM_MGMT_MOD 0x06
221 #define ASF_ENTITY_SYSTEM_BOARD 0x07
222 #define ASF_ENTITY_POWER_SUPPLY 0x0A
223 #define ASF_ENTITY_ADDIN_CARD 0x0B
224 #define ASF_ENTITY_CHASIS_BACK_PANEL_BOARD 0x16
225 #define ASF_ENTITY_MEMORY 0x20
226 #define ASF_ENTITY_SYSTEM_MGMT_SW 0x21
227 #define ASF_ENTITY_BIOS 0x22
228 #define ASF_ENTITY_OS 0x23
229 #define ASF_ENTITY_REMOTE_OOB_MGMT 0x26
230
231 ///
232 /// ASF Entity Instance Codes
233 /// IPMI/PET related definition
234 ///
235 #define ASF_ENTITY_INSTANCE_UNSPECIFIED 0x00
236
237 ///
238 /// ASF Event Data Codes for System Firmware Progress Events
239 /// IPMI/PET related definition
240 ///
241 #define ASF_FP_EVENT_DATA1 0x40
242
243 #define ASF_FP_UNSPECIFIED 0x00
244 #define ASF_FP_MEMORY_INIT 0x01
245 #define ASF_FP_HDD_INIT 0x02
246 #define ASF_FP_AP_INIT 0x03
247 #define ASF_FP_USER_AUTHENTICATION 0x04
248 #define ASF_FP_USER_SETUP 0x05
249 #define ASF_FP_USB_RESOURCE_CONFIG 0x06
250 #define ASF_FP_PCI_RESOURCE_CONFIG 0x07
251 #define ASF_FP_OPTION_ROM_INIT 0x08
252 #define ASF_FP_VIDEO_INIT 0x09
253 #define ASF_FP_CACHE_INIT 0x0A
254 #define ASF_FP_SMBUS_INIT 0x0B
255 #define ASF_FP_KBC_INIT 0x0C
256 #define ASF_FP_EC_INIT 0x0D
257 #define ASF_FP_ATTACH_DOCK 0x0E
258 #define ASF_FP_ENABLE_DOCK 0x0F
259 #define ASF_FP_EJECT_DOCK 0x10
260 #define ASF_FP_DISABLE_DOCK 0x11
261 #define ASF_FP_WAKE_OS 0x12
262 #define ASF_FP_BOOT_OS 0x13
263 #define ASF_FP_BOARD_INIT 0x14
264 #define ASF_FP_RESERVED 0x15
265 #define ASF_FP_FDC_INIT 0x16
266 #define ASF_FP_KBD_TEST 0x17
267 #define ASF_FP_MOUSE_TEST 0x18
268 #define ASF_FP_BSP_INIT 0x19
269
270 ///
271 /// ASF Event Data Codes for System Firmware Error Events
272 /// IPMI/PET related definition
273 ///
274 #define ASF_FE_EVENT_DATA1 0x40
275
276 #define ASF_FE_UNSPECIFIED 0x00
277 #define ASF_FE_AMTBX_FAILURE 0x00
278 #define ASF_FE_NO_MEMORY 0x01
279 #define ASF_FE_MEMORY_FAILURE 0x02
280 #define ASF_FE_HDD_FAILURE 0x03
281 #define ASF_FE_BOARD_FAILURE 0x04
282 #define ASF_FE_FDC_FAILURE 0x05
283 #define ASF_FE_HDC_FAILURE 0x06
284 #define ASF_FE_KBD_FAILURE 0x07
285 #define ASF_FE_REMOVABLE_BOOT_MEDIA_NOT_FOUND 0x08
286 #define ASF_FE_VIDEO_CONTROLLER_FAILURE 0x09
287 #define ASF_FE_VIDEO_DEVICE_NOT_FOUND 0x0A
288 #define ASF_FE_ROM_CORRUPTED 0x0B
289 #define ASF_FE_CPU_VOLTAGE_FAILURE 0x0C
290 #define ASF_FE_CPU_MISMATCH_FAILURE 0x0D
291
292 ///
293 /// ASF Event Data Codes for Watchdog2 Events
294 /// IPMI/PET related definition
295 ///
296 #define ASF_WD_EVENT_DATA1 0x40
297
298 #define ASF_WD_EVENT_DATA2_BIOS_TIMEOUT 0x02
299 #define ASF_WD_EVENT_DATA2_OS_TIMEOUT 0x04
300
301 ///
302 /// ACPI ASF! Definition
303 ///
304
305 ///
306 /// This field identifies the type of data present in the record's Variable
307 /// Data field, as well as an indication as to whether this is the last
308 /// record in the table:
309 /// Bit(s) Description
310 /// 7 Last Record. If this bit is set to 1b, then the record is the
311 /// last one present in the ASF! table.
312 /// 6:0 Record Type. Identifies the format of the record's Variable
313 /// Data field, one of:
314 /// 00h ASF_INFO
315 /// 01h ASF_ALRT
316 /// 02h ASF_RCTL
317 /// 03h ASF_RMCP
318 /// 04h ASF_ADDR
319 /// 05h-7Fh Reserved for future definition by this specification
320 ///
321 #define ASF_INFO_TYPE 0x00
322 #define ASF_ALRT_TYPE 0x01
323 #define ASF_RCTL_TYPE 0x02
324 #define ASF_RMCP_TYPE 0x03
325 #define ASF_ADDR_TYPE 0x04
326 #define ASF_LAST_RECORD_TYPE 0x80
327
328 ///
329 /// ACPI ASF_RMCP
330 ///
331 #define ASF_RMCP_BOOT_OPTION_SUCCESS 0x00
332 #define ASF_RMCP_NO_BOOT_OPTION 0x01
333 #define ASF_RMCP_BOOT_OPTION_MISMATCH 0x80
334
335 ///
336 /// This structure contains ASF! RMCP Remote Control Capabilities
337 ///
338
339 ///
340 /// Boot Options Bit Mask Byte1 values
341 ///
342 #define LOCK_POWER_BUTTON BIT1
343 #define LOCK_RESET_BUTTON BIT2
344 #define LOCK_KEYBOARD BIT5
345 #define LOCK_SLEEP_BUTTON BIT6
346
347 ///
348 /// Boot Options Bit Mask Byte2 values
349 ///
350 #define USER_PASSWORD_BYPASS BIT3
351 #define FORCE_PROGRESS_EVENTS BIT4
352 #define FIRMWARE_VERBOSITY_MASK (BIT6 | BIT5)
353 #define FIRMWARE_VERBOSITY_QUIET BIT5
354 #define FIRMWARE_VERBOSITY_VERBOSE BIT6
355 #define FIRMWARE_VERBOSITY_BLANK (BIT6 | BIT5)
356 #define CONFIG_DATA_RESET BIT7
357
358 ///
359 /// Boot Options/System Firmware Capabilities Bit Mask
360 ///
361 /// Byte1:
362 /// 7: Reserved for future definition by this specification
363 /// 6: Supports Sleep Button Lock
364 /// 5: Supports Lock Keyboard
365 /// 4:3: Reserved for future definition by this specification
366 /// 2: Supports Reset Button Lock
367 /// 1: Supports Power Button Lock
368 /// 0: Supports Firmware Verbosity/Screen Blank
369 /// Byte2:
370 /// 7: Supports Configuration Data Reset
371 /// 6: Supports Firmware Verbosity/Quiet
372 /// 5: Supports Firmware Verbosity/Verbose
373 /// 4: Supports Forced Progress Events
374 /// 3: Supports User Password Bypass
375 /// 2:0: Reserved for future definition by this specification
376 /// Byte3:
377 /// 7:0: Reserved for future definition by this specification
378 /// Byte4:
379 /// 7:0: Reserved for future definition by this specification
380 typedef struct {
381 UINT8 BootOptionByte1;
382 UINT8 BootOptionByte2;
383 UINT8 BootOptionByte3;
384 UINT8 BootOptionByte4;
385 } BOOT_OPTION_CAPS_STRUC;
386
387 ///
388 /// Special Command Definitions
389 ///
390 #define NOP 0x00
391 #define FORCE_PXE 0x01
392 #define FORCE_HARDDRIVE 0x02
393 #define FORCE_SAFEMODE 0x03
394 #define FORCE_DIAGNOSTICS 0x04
395 #define FORCE_CDDVD 0x05
396
397 ///
398 /// Special Command Bit Mask Byte2 values
399 ///
400 #define SUPPORT_FORCE_PXE BIT0
401 #define SUPPORT_FORCE_HARDDRIVE BIT1
402 #define SUPPORT_FORCE_SAFEMODE BIT2
403 #define SUPPORT_FORCE_DIAGNOSTICS BIT3
404 #define SUPPORT_FORCE_CDDVD BIT4
405
406 ///
407 /// Special Commands Bit Mask
408 ///
409 /// Byte1:
410 /// 7:0: Reserved to identify support for ASF-RMCP Special Commands defined by a future version of this specification
411 /// Byte2:
412 /// 7:5: Reserved to identify support for ASF-RMCP Special Commands defined by a future version of this specification
413 /// 4: Supports Force CD/DVD Boot command
414 /// 3: Supports Force Diagnostic Boot command
415 /// 2: Supports Force Hard-drive Safe-mode Boot command
416 /// 1: Supports Force Hard-drive Boot command
417 /// 0: Supports Force PXE Boot command
418 typedef struct {
419 UINT8 SpecialCmdByte1;
420 UINT8 SpecialCmdByte2;
421 } SPECIAL_COMMAND_CAPS_STRUC;
422
423 ///
424 /// System Capabilities Bit Mask values
425 ///
426 #define SUPPORT_POWER_CYCLE_RESET BIT0 ///< Supports Power Cycle Reset only on the secure port
427 #define SUPPORT_POWER_DOWN BIT1 ///< Supports Power-Down only on the secure port
428 #define SUPPORT_POWER_UP BIT2 ///< Supports Power-Up only on the secure port
429 #define SUPPORT_RESET BIT3 ///< Supports Reset only on the secure port
430 #define SUPPORT_POWER_CYCLE_RESET_COMBO BIT4 ///< Supports Power Cycle Reset on either the compatibility or secure port
431 #define SUPPORT_POWER_DOWN_COMBO BIT5 ///< Supports Power-Down on either the compatibility or secure port
432 #define SUPPORT_POWER_UP_COMBO BIT6 ///< Supports Power-Up on either the compatibility or secure port
433 #define SUPPORT_RESET_COMBO BIT7 ///< Supports Reset on either the compatibility or secure port
434
435 ///
436 /// System Capabilities Bit Mask
437 ///
438 /// Byte1:
439 /// 7: Supports Reset on either the compatibility or secure port
440 /// 6: Supports Power-Up on either the compatibility or secure port
441 /// 5: Supports Power-Down on either the compatibility or secure port
442 /// 4: Supports Power Cycle Reset on either the compatibility or secure port
443 /// 3: Supports Reset only on the secure port
444 /// 2: Supports Power-Up only on the secure port
445 /// 1: Supports Power-Down only on the secure port
446 /// 0: Supports Power Cycle Reset only on the secure port
447 typedef struct {
448 UINT8 SystemByte1;
449 } SYSTEM_CAPS_STRUC;
450
451 typedef struct {
452 BOOT_OPTION_CAPS_STRUC BootOptionCaps;
453 SPECIAL_COMMAND_CAPS_STRUC SpecialCmdCaps;
454 SYSTEM_CAPS_STRUC SystemCaps;
455 } ASF_RMCP_REMOTE_CTRL_CAPS;
456
457 #pragma pack ()
458
459 #endif
SPECIAL_COMMAND_CAPS_STRUC
Special Commands Bit Mask.
Definition: IndustryStandardAsf.h:418
SYSTEM_CAPS_STRUC
System Capabilities Bit Mask.
Definition: IndustryStandardAsf.h:447
BOOT_OPTION_CAPS_STRUC
Boot Options/System Firmware Capabilities Bit Mask.
Definition: IndustryStandardAsf.h:380
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IntelAsfExtensions.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros
IntelAsfExtensions.h File Reference

Include file for Intel Extended ASF definition. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | ASF_MESSAGE_COMMAND_LAN 0x06
Intel extended ASF Messages Command.
#define | ASF_MESSAGE_SUBCOMMAND_GET_RSE_PASSWORD 0x18
Intel extended ASF Messages Sub-Command for Command ASF_CONFIGURATION (0x03)
#define | ASF_MESSAGE_SUBCOMMAND_SET_ACTIVE_LAN 0x01
Intel extended ASF Messages Sub-Command for Command LAN (0x06)
#define | ASF_MESSAGE_SUBCOMMAND_KVM_QUERY 0x01
Intel extended ASF Messages Sub-Command for Command KVM (0x08)
#define | ASF_MESSAGE_SUBCOMMAND_SET_MAC_PASSTHROUGH 0x01
Intel extended ASF Messages Sub-Command for Command MAC (0x0A)
#define | ASF_ENTITY_INTEL_AMT 0x26
Intel extended ASF Entity Codes.
#define | ASF_FP_AMTBX_INIT 0x0D
Intel extended ASF Event Data Codes for System Firmware Progress Events.
#define | ASF_FE_AMTBX_FAILURE 0x00
Intel extended ASF Event Data Codes for System Firmware Error Events.
#define | ASF_EVENT_OFFSET_REMOTE_SECURE_ERASE_FW_ERROR 0x03
Intel extended ASF Event Data Codes for RSE Fw Progress/Error Events.
#define | ASF_RPE_EVENT_OFFSET_PROGRESS 0x05
Intel extended ASF Event Data Codes for RPE Fw Progress/Error Events.
#define | ASF_RBS_BIOS_STATUS_SUCCESS 0x0000
Intel extended ASF Report BIOS Status Additional Data.
#define | ASF_EVENT_OFFSET_ONE_CLICK_RECOVERY_ERROR 0x03
Intel extended ASF Event Data Codes for OCR Fw Progress/Error Events.
#define | ASF_OCR_EVENT_DATA3_BOOT_PARAMETER_RECEIVED 0x00
OCR Fw Progress Events.
#define | ASF_OCR_EVENT_DATA3_SUCCESS 0x00
OCR Fw Error Events.
#define | CU_HP_EC_VID_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000E)
Intel extended StatusCode extension for ASF. More...
#define | PERIPHERAL_EMBEDDED_CONTROLLER (EFI_PERIPHERAL | 0x000D0000)
Intel extended Peripheral Subclass definitions.
#define | CU_CHIPSET_PC_INTRUDER_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
Intel extended Computing Unit Chipset Subclass Progress Code definitions.
#define | SW_DXE_BS_EC_NO_BOOT_MEDIA (EFI_SUBCLASS_SPECIFIC | 0x00000001)
Intel extended Software Class DXE Boot Service Driver Subclass Error Code definitions.

Detailed Description

Include file for Intel Extended ASF definition.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IntelAsfExtensions.h.

Macro Definition Documentation

◆ CU_HP_EC_VID_MISMATCH

#define CU_HP_EC_VID_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000E)

Intel extended StatusCode extension for ASF.

Intel extended Computing Unit Host Processor Subclass Error Code definitions.

Definition at line 290 of file IntelAsfExtensions.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IntelAsfExtensions.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
IntelAsfExtensions.h
Go to the documentation of this file.
1 /** @file
2 Include file for Intel Extended ASF definition
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _INTEL_EXTENDED_ASF_H_
36 #define _INTEL_EXTENDED_ASF_H_
37
38 ///
39 /// Intel extended ASF Messages Command
40 ///
41 #define ASF_MESSAGE_COMMAND_LAN 0x06
42 #define ASF_MESSAGE_COMMAND_KVM 0x08
43 #define ASF_MESSAGE_COMMAND_MAC 0x0A
44
45 ///
46 /// Intel extended ASF Messages Sub-Command for Command ASF_CONFIGURATION (0x03)
47 ///
48 #define ASF_MESSAGE_SUBCOMMAND_GET_RSE_PASSWORD 0x18
49 #define ASF_MESSAGE_SUBCOMMAND_REPORT_BIOS_STATUS 0x19
50 #define ASF_MESSAGE_SUBCOMMAND_SET_UEFI_BOOT_OPTIONS_STATE 0x20
51 #define ASF_MESSAGE_SUBCOMMAND_GET_UEFI_BOOT_OPTIONS_STATE 0x21
52 #define ASF_MESSAGE_SUBCOMMAND_UPDATE_UEFI_BOOT_OPTIONS 0x22
53 #define ASF_MESSAGE_SUBCOMMAND_GET_UEFI_BOOT_PARAMETERS 0x23
54 #define ASF_MESSAGE_SUBCOMMAND_GET_ROOT_CA_CERTIFICATE 0x24
55 #define ASF_MESSAGE_SUBCOMMAND_GET_WIFI_PROFILE_NAME 0x25
56 #define ASF_MESSAGE_SUBCOMMAND_GET_WIFI_PROFILE_DATA 0x26
57 #define ASF_MESSAGE_SUBCOMMAND_GET_WIFI_8021X_CLIENT_CERT 0x27
58 #define ASF_MESSAGE_SUBCOMMAND_GET_WIFI_8021X_CLIENT_KEY 0x28
59
60 ///
61 /// Intel extended ASF Messages Sub-Command for Command LAN (0x06)
62 ///
63 #define ASF_MESSAGE_SUBCOMMAND_SET_ACTIVE_LAN 0x01
64 #define ASF_MESSAGE_SUBCOMMAND_GET_ACTIVE_LAN 0x02
65
66 ///
67 /// Intel extended ASF Messages Sub-Command for Command KVM (0x08)
68 ///
69 #define ASF_MESSAGE_SUBCOMMAND_KVM_QUERY 0x01
70
71 ///
72 /// Intel extended ASF Messages Sub-Command for Command MAC (0x0A)
73 ///
74 #define ASF_MESSAGE_SUBCOMMAND_SET_MAC_PASSTHROUGH 0x01
75
76 ///
77 /// Intel extended ASF Entity Codes
78 ///
79 #define ASF_ENTITY_INTEL_AMT 0x26
80
81 ///
82 /// Intel extended ASF Event Data Codes for System Firmware Progress Events
83 ///
84 #define ASF_FP_AMTBX_INIT 0x0D
85
86 ///
87 /// Intel extended ASF Event Data Codes for System Firmware Error Events
88 ///
89 #define ASF_FE_AMTBX_FAILURE 0x00
90
91 ///
92 /// Intel extended ASF Event Data Codes for RSE Fw Progress/Error Events
93 ///
94 #define ASF_EVENT_OFFSET_REMOTE_SECURE_ERASE_FW_ERROR 0x03
95 #define ASF_EVENT_OFFSET_REMOTE_SECURE_ERASE_FW_PROGRESS 0x05
96
97 #define ASF_RSE_EVENT_DATA0_EVENT_DATA_SET_BY_OEM 0xAA
98
99 #define ASF_RSE_EVENT_DATA1_REMOTE_SECURE_ERASE 0x20
100
101 #define ASF_RSE_EVENT_DATA2_SECURE_ERASE_SUCCESS 0x00
102 #define ASF_RSE_EVENT_DATA2_GENERAL_FAILURE 0x01
103 #define ASF_RSE_EVENT_DATA2_DRIVE_AUTH_FAILURE 0x02
104 #define ASF_RSE_EVENT_DATA2_UNSUPPORTED 0x03
105
106 ///
107 /// Intel extended ASF Event Data Codes for RPE Fw Progress/Error Events
108 ///
109 #define ASF_RPE_EVENT_OFFSET_PROGRESS 0x05
110 #define ASF_RPE_EVENT_OFFSET_FAILURE 0x03
111
112 #define ASF_RPE_EVENT_DATA0_EVENT_DATA_SET_BY_OEM 0xAA
113 #define ASF_RPE_EVENT_DATA2_REMOTE_PLATFORM_ERASE 0x40
114
115 #define ASF_RPE_EVENT_DATA3_BOOT_PARAMETER_RECEIVED 0x00
116 #define ASF_RPE_EVENT_DATA3_STARTED_ERASING_DEVICE 0x01
117 #define ASF_RPE_EVENT_DATA3_DEVICE_ERASED_SUCCESSFULLY 0x02
118 #define ASF_RPE_EVENT_DATA3_BEGINNING_PLATFORM_ERASE 0x03
119 #define ASF_RPE_EVENT_DATA3_CLEAR_RESERVED_PARAMETERS 0x04
120 #define ASF_RPE_EVENT_DATA3_ALL_SETTINGS_DECREMENTED 0x05
121 #define ASF_RPE_EVENT_DATA3_PSID_NOT_RECEIVED 0x06
122
123 #define ASF_RPE_EVENT_DATA3_BOOT_PARAMETER_RECEIVE_FAILED 0x00
124 #define ASF_RPE_EVENT_DATA3_ERROR_ERASING_DEVICE 0x01
125 #define ASF_RPE_EVENT_DATA3_ERASING_DEVICE_UNSUPPORTED 0x02
126 #define ASF_RPE_EVENT_DATA3_REACHED_MAX_RETRY_COUNT 0x03
127 #define ASF_RPE_EVENT_DATA3_INVALID_BOOT_PARAMETERS 0x04
128 #define ASF_RPE_EVENT_DATA3_INVALID_MAX_COUNTER 0x05
129
130 #define ASF_RPE_EVENT_DATA4_PYRITE_ERASE_ACTION 0x01
131 #define ASF_RPE_EVENT_DATA4_SSD_ERASE_ACTION 0x02
132 #define ASF_RPE_EVENT_DATA4_TPM_ERASE_ACTION 0x03
133 #define ASF_RPE_EVENT_DATA4_CLEAR_BIOS_NVM_VARIABLE 0x04
134 #define ASF_RPE_EVENT_DATA4_RELOAD_BIOS_GOLDEN_CONFIG 0x05
135 #define ASF_RPE_EVENT_DATA4_OEM_CUSTOM_ACTIONS 0x06
136 #define ASF_RPE_EVENT_DATA4_CSME_UNCONFIGURE 0x07
137
138 ///
139 /// Intel extended ASF Report BIOS Status Additional Data
140 ///
141 #define ASF_RBS_BIOS_STATUS_SUCCESS 0x0000
142 #define ASF_RBS_BIOS_STATUS_IN_PROGRESS 0x0001
143 #define ASF_RBS_BIOS_STATUS_NOT_REPORTED 0x0002
144 #define ASF_RBS_BIOS_STATUS_FAILED 0xFFFF
145
146 #define ASF_RBS_STATUS_CAUSE_SUCCESS_INPROGRESS 0x0000
147 #define ASF_RBS_STATUS_CAUSE_GENERAL_FAILURE 0x0001
148 #define ASF_RBS_STATUS_CAUSE_AUTHENTICATION_FAILURE 0x0002
149 #define ASF_RBS_STATUS_CAUSE_UNSUPPORTED 0x0003
150
151 typedef enum {
152 AsfRbsSuccess = (ASF_RBS_STATUS_CAUSE_SUCCESS_INPROGRESS << 16) | ASF_RBS_BIOS_STATUS_SUCCESS,
153 AsfRbsInProgress = (ASF_RBS_STATUS_CAUSE_SUCCESS_INPROGRESS << 16) | ASF_RBS_BIOS_STATUS_IN_PROGRESS,
154 AsfRbsGeneralFailure = (ASF_RBS_STATUS_CAUSE_GENERAL_FAILURE << 16) | ASF_RBS_BIOS_STATUS_FAILED,
155 AsfRbsAccessDenied = (ASF_RBS_STATUS_CAUSE_AUTHENTICATION_FAILURE << 16) | ASF_RBS_BIOS_STATUS_FAILED,
156 AsfRbsUnsupported = (ASF_RBS_STATUS_CAUSE_UNSUPPORTED << 16) | ASF_RBS_BIOS_STATUS_FAILED
157 } ASF_REPORT_BIOS_STATUS;
158
159 ///
160 /// Intel extended ASF Event Data Codes for OCR Fw Progress/Error Events
161 ///
162 #define ASF_EVENT_OFFSET_ONE_CLICK_RECOVERY_ERROR 0x03
163 #define ASF_EVENT_OFFSET_ONE_CLICK_RECOVERY_PROGRESS 0x05
164
165 #define ASF_OCR_EVENT_DATA1_EVENT_DATA_SET_BY_OEM 0xAA
166
167 #define ASF_OCR_EVENT_DATA2_EVENT_DATA_REASON 0x30
168
169 ///
170 /// OCR Fw Progress Events
171 ///
172 #define ASF_OCR_EVENT_DATA3_BOOT_PARAMETER_RECEIVED 0x00
173 #define ASF_OCR_EVENT_DATA3_CSME_BOOT_OPTION_ADDED 0x01
174 #define ASF_OCR_EVENT_DATA3_HTTPS_URI_NAME_RESOLVED 0x02
175 #define ASF_OCR_EVENT_DATA3_HTTPS_CONNECTED_SUCCESS 0x03
176 #define ASF_OCR_EVENT_DATA3_HTTPS_BOOT_DOWNLOAD 0x04
177 #define ASF_OCR_EVENT_DATA3_ATTEMPT_TO_BOOT 0x05
178 #define ASF_OCR_EVENT_DATA3_EXIT_BOOT_SERVICES 0x06
179
180 ///
181 /// OCR Fw Error Events
182 ///
183 #define ASF_OCR_EVENT_DATA3_SUCCESS 0x00
184 #define ASF_OCR_EVENT_DATA3_NO_NETWORK_CONNECTION 0x01
185 #define ASF_OCR_EVENT_DATA3_NAME_RESOLUTION_URI_FAILED 0x02
186 #define ASF_OCR_EVENT_DATA3_CONNECT_TO_URI_FAILED 0x03
187 #define ASF_OCR_EVENT_DATA3_FILEPATH_NOT_FOUND 0x04
188 #define ASF_OCR_EVENT_DATA3_HTTPS_TLS_AUTH_FAILED 0x05
189 #define ASF_OCR_EVENT_DATA3_HTTPS_DIGEST_AUTH_FAILED 0x06
190 #define ASF_OCR_EVENT_DATA3_VERIFIED_BOOT_FAILED 0x07
191 #define ASF_OCR_EVENT_DATA3_HTTPS_BOOT_FILE_NOT_FOUND 0x08
192
193 //
194 // AMT BX Software Class DXE Subclass Progress Code definitions.
195 //
196 #define SW_DXE_AMTBX_OPROM_DONE (EFI_OEM_SPECIFIC | 0x00000000)
197 #define SW_DXE_AMTBX_OPROM_NOT_STARTED (EFI_OEM_SPECIFIC | 0x00000001)
198 #define SW_DXE_AMTBX_SLEEP_S4_NOT_TAKEN (EFI_OEM_SPECIFIC | 0x00000002)
199 #define SW_DXE_AMTBX_SLEEP_S5_NOT_TAKEN (EFI_OEM_SPECIFIC | 0x00000003)
200 #define SW_DXE_AMTBX_SLEEP_UNSPECD_NOT_TAKEN (EFI_OEM_SPECIFIC | 0x00000004)
201 #define SW_DXE_AMTBX_ERROR_ACTION_INTF (EFI_OEM_SPECIFIC | 0x00000005)
202 #define SW_DXE_AMTBX_ERROR_ACTION_INV (EFI_OEM_SPECIFIC | 0x00000006)
203 #define SW_DXE_AMTBX_ERROR_ACTION_SETUP (EFI_OEM_SPECIFIC | 0x00000007)
204 #define SW_DXE_AMTBX_ERROR_ACTION_FAIL (EFI_OEM_SPECIFIC | 0x00000008)
205 #define SW_DXE_AMTBX_ERROR_ACTION_UNSPECD (EFI_OEM_SPECIFIC | 0x00000009)
206 #define SW_DXE_AMTBX_OTHER_UNSPECD (EFI_OEM_SPECIFIC | 0x00000009)
207
208 typedef enum {
209 AsfMessageBiosPresent,
210 AsfMessageMemInit,
211 AsfMessageMemInitDone,
212 AsfMessageHddInit,
213 AsfMessageApInit,
214 AsfMessageUserAuthentication,
215 AsfMessageUserInitSetup,
216 AsfMessageUsbResourceConfig,
217 AsfMessagePciResourceConfig,
218 AsfMessageOptionRomInit,
219 AsfMessageVideoInit,
220 AsfMessageCacheInit,
221 AsfMessageSmbusInit,
222 AsfMessageKbcInit,
223 AsfMessageEmControllerInit,
224 AsfMessageDockAttached,
225 AsfMessageEnableDock,
226 AsfMessageDockEject,
227 AsfMessageDisableDock,
228 AsfMessageOSWakeVector,
229 AsfMessageMotherBoardInit,
230 AsfMessageFdcInit,
231 AsfMessageKeyboardTest,
232 AsfMessageMouseTest,
233 AsfMessageBspInit,
234 AsfMessageAmtBxDone,
235 AsfMessageAmtBxNotStarted,
236 AsfMessageAmtBxSleepS4ReportedNotTaken,
237 AsfMessageAmtBxSleepS5ReportedNotTaken,
238 AsfMessageAmtBxSleepUnspecifiedReportedNotTaken,
239 AsfMessageAmtBxErrActionIntF,
240 AsfMessageAmtBxErrActionInv,
241 AsfMessageAmtBxErrActionSetup,
242 AsfMessageAmtBxErrActionFailure,
243 AsfMessageAmtBxErrActionUnspecified,
244 AsfMessageAmtBxOtherUnspecified,
245 AsfMessageNoMemory,
246 AsfMessageMemoryFailure,
247 AsfMessageHddFailure,
248 AsfMessageBoardFailure,
249 AsfMessageFdcFailure,
250 AsfMessageHdcFailure,
251 AsfMessageKbdFailure,
252 AsfMessageNoFdd,
253 AsfMessageVideoControllerFailure,
254 AsfMessageNoVideo,
255 AsfMessageFirmwareCorruption,
256 AsfMessageCpuVidMismatch,
257 AsfMessageCpuSpeedMatchingFailure,
258 AsfMessageUserAuthenticationInvalid,
259 AsfMessageHddAuthenticationInvalid,
260 AsfMessageNoBootMedia,
261 AsfMessageTemperatureGenericCritical,
262 AsfMessageTemperatureGenericWarning,
263 AsfMessageTemperatureOverCritical,
264 AsfMessageTemperatureOverWarning,
265 AsfMessageTemperatureUnderCritical,
266 AsfMessageTemperatureUnderWarning,
267 AsfMessageVoltageGenericCritical,
268 AsfMessageVoltageOverCritical,
269 AsfMessageVoltageUnderCritical,
270 AsfMessageFanGenericCritical,
271 AsfMessageFanPredictiveFailure,
272 AsfMessageFanLowSpeedCritical,
273 AsfMessageFanLowSpeedWarning,
274 AsfMessageBatteryLowWarning,
275 AsfMessageBatteryLowCritical,
276 AsfMessageBatteryPresenceDetected,
277 AsfMessagePowerFailure,
278 AsfMessageChassisIntrusion,
279 AsfMessageTermination = 0xFFFF
280 } ASF_FRAMEWORK_MESSAGE_TYPE;
281
282 ///
283 /// Intel extended StatusCode extension for ASF
284 ///
285
286
287 ///
288 /// Intel extended Computing Unit Host Processor Subclass Error Code definitions.
289 ///
290 #define CU_HP_EC_VID_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000E)
291 #define CU_HP_EC_SPEED_MATCHING_FAILURE (EFI_SUBCLASS_SPECIFIC | 0x0000000F)
292
293 ///
294 /// Intel extended Peripheral Subclass definitions.
295 ///
296 #define PERIPHERAL_EMBEDDED_CONTROLLER (EFI_PERIPHERAL | 0x000D0000)
297 #define PERIPHERAL_DOCK (EFI_PERIPHERAL | 0x000E0000)
298
299 #define PERIPHERAL_BATTERY (EFI_PERIPHERAL | 0x000F0000)
300 #define P_BATTERY_PC_LOW_WARNING (EFI_SUBCLASS_SPECIFIC | 0x00000000)
301 #define P_BATTERY_EC_LOW_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
302
303 #define PERIPHERAL_FAN (EFI_PERIPHERAL | 0x00100000)
304 #define P_FAN_EC_GENERIC_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
305 #define P_FAN_EC_PREDICTIVE_FAILURE (EFI_SUBCLASS_SPECIFIC | 0x00000001)
306 #define P_FAN_EC_LOW_SPEED_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
307 #define P_FAN_PC_LOW_SPEED_WARNING (EFI_SUBCLASS_SPECIFIC | 0x00000002)
308
309 #define PERIPHERAL_TEMPERATURE (EFI_PERIPHERAL | 0x00110000)
310 #define P_TEMERATURE_EC_GENERIC_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
311 #define P_TEMERATURE_PC_GENERIC_WARNING (EFI_SUBCLASS_SPECIFIC | 0x00000000)
312 #define P_TEMERATURE_EC_OVER_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
313 #define P_TEMERATURE_PC_OVER_WARNING (EFI_SUBCLASS_SPECIFIC | 0x00000001)
314 #define P_TEMERATURE_EC_UNDER_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
315 #define P_TEMERATURE_PC_UNDER_WARNING (EFI_SUBCLASS_SPECIFIC | 0x00000002)
316
317 #define PERIPHERAL_VOLTAGE (EFI_PERIPHERAL | 0x00120000)
318 #define P_VOLTAGE_EC_GENERIC_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000000)
319 #define P_VOLTAGE_EC_OVER_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000001)
320 #define P_VOLTAGE_EC_UNDER_CRITICAL (EFI_SUBCLASS_SPECIFIC | 0x00000002)
321
322 #define PERIPHERAL_POWER_SUPPLY (EFI_PERIPHERAL | 0x00130000)
323 #define P_POWER_SUPPLY_EC_FAILURE (EFI_SUBCLASS_SPECIFIC | 0x00000000)
324 #define P_POWER_SUPPLY_EC_PREDICTIVE_FAILURE (EFI_SUBCLASS_SPECIFIC | 0x00000001)
325
326 ///
327 /// Intel extended Computing Unit Chipset Subclass Progress Code definitions.
328 ///
329 #define CU_CHIPSET_PC_INTRUDER_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000)
330
331 ///
332 /// Intel extended Software Class DXE Boot Service Driver Subclass Error Code definitions.
333 ///
334 #define SW_DXE_BS_EC_NO_BOOT_MEDIA (EFI_SUBCLASS_SPECIFIC | 0x00000001)
335 #define SW_DXE_BS_EC_AUTHENTICATE_USER_INVALID (EFI_SUBCLASS_SPECIFIC | 0x00000002)
336 #define SW_DXE_BS_EC_AUTHENTICATE_HDD_INVALID (EFI_SUBCLASS_SPECIFIC | 0x00000003)
337
338 #endif
ASF_RBS_BIOS_STATUS_SUCCESS
#define ASF_RBS_BIOS_STATUS_SUCCESS
Intel extended ASF Report BIOS Status Additional Data.
Definition: IntelAsfExtensions.h:141
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): InterruptConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes | Macros | Enumerations
InterruptConfig.h File Reference

Interrupt policy. More...

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Classes

struct | PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. More...
struct | PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. More...

Macros

#define | PCH_MAX_DEVICE_INTERRUPT_CONFIG 128
Number of all PCH devices.
#define | PCH_MAX_PXRC_CONFIG 8
Number of PXRC registers in ITSS.
#define | PCH_MAX_ITSS_IPC_REGS 4
Number of IPC registers in ITSS.
#define | PCH_MAX_ITSS_IRQ_NUM 120
Maximum number of IRQs.

Enumerations

enum PCH_INT_PIN

Detailed Description

Interrupt policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file InterruptConfig.h.

Enumeration Type Documentation

◆ PCH_INT_PIN

enum PCH_INT_PIN
Enumerator
PchNoInt

No Interrupt Pin.

Definition at line 46 of file InterruptConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): InterruptConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
InterruptConfig.h
Go to the documentation of this file.
1 /** @file
2 Interrupt policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _INTERRUPT_CONFIG_H_
36 #define _INTERRUPT_CONFIG_H_
37
38 #define PCH_INTERRUPT_CONFIG_REVISION 1
39 extern EFI_GUID gInterruptConfigGuid;
40
41 #pragma pack (push,1)
42
43 //
44 // --------------------- Interrupts Config ------------------------------
45 //
46 typedef enum {
47 PchNoInt, ///< No Interrupt Pin
48 PchIntA,
49 PchIntB,
50 PchIntC,
51 PchIntD
52 } PCH_INT_PIN;
53
54 ///
55 /// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
56 ///
57 typedef struct {
58 UINT8 Device; ///< Device number
59 UINT8 Function; ///< Device function
60 UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
61 UINT8 Irq; ///< IRQ to be set for device.
62 } PCH_DEVICE_INTERRUPT_CONFIG;
63
64 #define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH devices
65 #define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
66 #define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC registers in ITSS
67 #define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of IRQs
68
69
70 ///
71 /// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
72 ///
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75 UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
76 UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
77 PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
78 UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
79 UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
80 UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
81 UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
82 } PCH_INTERRUPT_CONFIG;
83
84 #pragma pack (pop)
85
86 #endif // _INTERRUPT_CONFIG_H_
PCH_DEVICE_INTERRUPT_CONFIG::Function
UINT8 Function
Device function.
Definition: InterruptConfig.h:59
PCH_INTERRUPT_CONFIG::TcoIrqEnable
UINT8 TcoIrqEnable
Enable IRQ generation for TCO. 0: Disable; 1: Enable.
Definition: InterruptConfig.h:81
PCH_DEVICE_INTERRUPT_CONFIG::IntX
UINT8 IntX
Interrupt pin: INTA-INTD (see PCH_INT_PIN)
Definition: InterruptConfig.h:60
PCH_INTERRUPT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: InterruptConfig.h:74
PCH_DEVICE_INTERRUPT_CONFIG::Irq
UINT8 Irq
IRQ to be set for device.
Definition: InterruptConfig.h:61
PCH_DEVICE_INTERRUPT_CONFIG::Device
UINT8 Device
Device number.
Definition: InterruptConfig.h:58
PCH_MAX_DEVICE_INTERRUPT_CONFIG
#define PCH_MAX_DEVICE_INTERRUPT_CONFIG
Number of all PCH devices.
Definition: InterruptConfig.h:64
PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
Definition: InterruptConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_INTERRUPT_CONFIG::NumOfDevIntConfig
UINT8 NumOfDevIntConfig
Number of entries in DevIntConfig table.
Definition: InterruptConfig.h:75
PCH_INT_PIN
PCH_INT_PIN
Definition: InterruptConfig.h:46
PCH_INTERRUPT_CONFIG::TcoIrqSelect
UINT8 TcoIrqSelect
Interrupt select for TCO. Default is 9.
Definition: InterruptConfig.h:80
PCH_INTERRUPT_CONFIG::GpioIrqRoute
UINT8 GpioIrqRoute
Interrupt routing for GPIO. Default is 14.
Definition: InterruptConfig.h:78
PchNoInt
@ PchNoInt
No Interrupt Pin.
Definition: InterruptConfig.h:47
PCH_INTERRUPT_CONFIG::SciIrqSelect
UINT8 SciIrqSelect
Interrupt select for SCI. Default is 9.
Definition: InterruptConfig.h:79
PCH_INTERRUPT_CONFIG
The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
Definition: InterruptConfig.h:73
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IoApicConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Classes
IoApicConfig.h File Reference

IoApic policy. More...

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Classes

struct PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is not TRUE. More...

Detailed Description

IoApic policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IoApicConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IoApicConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
IoApicConfig.h
Go to the documentation of this file.
1 /** @file
2 IoApic policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IOAPIC_CONFIG_H_
36 #define _IOAPIC_CONFIG_H_
37
38 #define PCH_IOAPIC_CONFIG_REVISION 1
39 extern EFI_GUID gIoApicConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
45 IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
46 not TRUE. Bus:device:function fields will be programmed to the register
47 P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
48 As the Requester ID when initiating Interrupt Messages to the processor.
49 As the Completer ID when responding to the reads targeting the IOxAPI's
50 Memory-Mapped I/O registers.
51 This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
52 program this field to provide a unique Bus:Device:Function number for the
53 internal IOxAPIC.
54 The address resource range of IOAPIC must be reserved in E820 and ACPI as
55 system resource.
56 **/
57 typedef struct {
58 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
59 UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
60 /**
61 Enable 8254 Static Clock Gating during early POST time. 0: Disable, <b>1: Enable</b>
62 Setting 8254CGE is required to support SLP_S0.
63 Enable this if 8254 timer is not used.
64 However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer.
65 Make sure it is disabled to support legacy OS using 8254 timer.
66 @note:
67 For some OS environment that it needs to set 8254CGE in late state it should
68 set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in SMM later.
69 This is also required during S3 resume.
70 To avoid SMI requirement in S3 reusme path, it can enable the Enable8254ClockGatingOnS3
71 and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_SAI.
72 **/
73 UINT32 Enable8254ClockGating : 1;
74 /**
75 Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, <b>1: Enable</b>
76 This is only applicable when Enable8254ClockGating is disabled.
77 If Enable8254ClockGating is enabled, RC will do the 8254 CGE programming on
78 S3 resume path as well.
79 **/
80 UINT32 Enable8254ClockGatingOnS3 : 1;
81 UINT32 RsvdBits1 : 29; ///< Reserved bits
82 UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
83 UINT8 Rsvd0[3]; ///< Reserved bytes
84 } PCH_IOAPIC_CONFIG;
85
86 #pragma pack (pop)
87
88 #endif // _IOAPIC_CONFIG_H_
PCH_IOAPIC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IoApicConfig.h:58
PCH_IOAPIC_CONFIG::IoApicId
UINT8 IoApicId
This member determines IOAPIC ID. Default is 0x02.
Definition: IoApicConfig.h:82
PCH_IOAPIC_CONFIG::IoApicEntry24_119
UINT32 IoApicEntry24_119
0: Disable; 1: Enable IOAPIC Entry 24-119
Definition: IoApicConfig.h:59
PCH_IOAPIC_CONFIG::Enable8254ClockGating
UINT32 Enable8254ClockGating
Enable 8254 Static Clock Gating during early POST time.
Definition: IoApicConfig.h:73
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_IOAPIC_CONFIG::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: IoApicConfig.h:81
PCH_IOAPIC_CONFIG::Enable8254ClockGatingOnS3
UINT32 Enable8254ClockGatingOnS3
Enable 8254 Static Clock Gating on S3 resume path.
Definition: IoApicConfig.h:80
PCH_IOAPIC_CONFIG
The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH IO APIC,...
Definition: IoApicConfig.h:57
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IoTrapExDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Typedefs | Enumerations
IoTrapExDispatch.h File Reference

PCH IO TrapEx Dispatch Protocol. More...

Go to the source code of this file.

Classes

struct | IO_TRAP_EX_REGISTER_CONTEXT
IO Trap Ex context structure containing information about the IO trap Ex event that should invoke the handler. More...
struct | _IO_TRAP_EX_DISPATCH_PROTOCOL
Interface structure for the IO trap Extention protocol. More...

Typedefs

typedef VOID(* | IO_TRAP_EX_DISPATCH_CALLBACK) (IN UINT16 Address, IN UINT8 ByteEnable, IN BOOLEAN WriteCycle, IN UINT32 WriteData)
Callback function for an PCH IO TRAP EX handler dispatch. More...
typedef EFI_STATUS(* | IO_TRAP_EX_DISPATCH_REGISTER) (IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, OUT EFI_HANDLE *DispatchHandle)
Register a new IO Trap Ex SMI dispatch function. More...
typedef EFI_STATUS(* | IO_TRAP_EX_DISPATCH_UNREGISTER) (IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a SMI source dispatch function. More...

Enumerations

enum IO_TRAP_EX_DISPATCH_TYPE
IO Trap Ex valid types.

Detailed Description

PCH IO TrapEx Dispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IoTrapExDispatch.h.

Typedef Documentation

◆ IO_TRAP_EX_DISPATCH_CALLBACK

typedef VOID( * IO_TRAP_EX_DISPATCH_CALLBACK) (IN UINT16 Address, IN UINT8 ByteEnable, IN BOOLEAN WriteCycle, IN UINT32 WriteData)

Callback function for an PCH IO TRAP EX handler dispatch.

Parameters
[in] | Address | DWord-aligned address of the trapped cycle.
[in] | ByteEnable | This is the DWord-aligned byte enables associated with the trapped cycle. A 1 in any bit location indicates that the corresponding byte is enabled in the cycle.
[in] | WriteCycle | TRUE = Write cycle; FALSE = Read cycle
[in] | WriteData | DWord of I/O write data. This field is undefined after trapping a read cycle. The byte of WriteData is only valid if the corresponding bits in ByteEnable is 1. E.g. If ByteEnable is 0001b, then only first byte of WriteData is valid. If ByteEnable is 0010b, then only second byte of WriteData is valid.

Definition at line 114 of file IoTrapExDispatch.h.

◆ IO_TRAP_EX_DISPATCH_REGISTER

typedef EFI_STATUS( * IO_TRAP_EX_DISPATCH_REGISTER) (IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, OUT EFI_HANDLE *DispatchHandle)

Register a new IO Trap Ex SMI dispatch function.

The caller will provide information of IO trap setting via the context. Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. This is the function to extend the IoTrap capability, and it's expected to handle the special ByteEnable and ByteEnableMask setting. This register function will occupy one IoTrap register if possible. And it only support one handler for one IoTrap event. The Address of context MUST NOT be 0, and MUST be dword alignment. The Length of context MUST not less than 4, and MUST be power of 2. The ByteEnable and ByteEnableMask MUST not be zero at the same time. if the IO Trap handler is not used. It also enable the IO Trap Range to generate SMI. Caller must take care of reserving the IO addresses in ACPI.

Parameters
[in] | This | Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
[in] | DispatchFunction | Pointer to dispatch function to be invoked for this SMI source.
[in] | RegisterContext | Pointer to the dispatch function's context. The caller fills this context in before calling the register function to indicate to the register function the IO trap Ex SMI source for which the dispatch function should be invoked. This MUST not be NULL.
[out] | DispatchHandle | Handle of dispatch function.
Return values
EFI_SUCCESS | The dispatch function has been successfully registered and the SMI source has been enabled.
EFI_OUT_OF_RESOURCES | Insufficient resources are available
EFI_INVALID_PARAMETER | Address requested is already in use.
EFI_ACCESS_DENIED | Return access denied if the SmmReadyToLock event has been triggered

Definition at line 154 of file IoTrapExDispatch.h.

◆ IO_TRAP_EX_DISPATCH_UNREGISTER

typedef EFI_STATUS( * IO_TRAP_EX_DISPATCH_UNREGISTER) (IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

Unregister a SMI source dispatch function.

This function is unsupported.

Parameters
[in] | This | Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
[in] | DispatchHandle | Handle of dispatch function to deregister.
Return values
EFI_UNSUPPORTED The function is unsupported.

Definition at line 172 of file IoTrapExDispatch.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IoTrapExDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
IoTrapExDispatch.h
Go to the documentation of this file.
1 /** @file
2 PCH IO TrapEx Dispatch Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IO_TRAP_EX_DISPATCH_H_
36 #define _IO_TRAP_EX_DISPATCH_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gIoTrapExDispatchProtocolGuid;
42
43 typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL IO_TRAP_EX_DISPATCH_PROTOCOL;
44
45 /**
46 IO Trap Ex valid types
47 **/
48 typedef enum {
49 IoTrapExTypeWrite,
50 IoTrapExTypeRead,
51 IoTrapExTypeReadWrite,
52 IoTrapExTypeMaximum
53 } IO_TRAP_EX_DISPATCH_TYPE;
54
55 /**
56 IO Trap Ex context structure containing information about the
57 IO trap Ex event that should invoke the handler.
58 ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for any byte access.
59
60 Here are some examples for the usage.
61 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with BYTE/WORD/DWORD read/write access:
62 Address = 0x2000
63 Length = 0x100
64 Type = IoTrapExTypeReadWrite
65 ByteEnable = 0x00 (BE is not matter)
66 ByteEnableMask = 0x0F (BEM 0xF for any BYTE/WORD/DWORD access)
67 2. To trigger the TRAP for port 0x61 with BYTE read access:
68 Address = 0x60
69 Length = 4
70 Type = IoTrapExTypeRead
71 ByteEnable = 0x02 (BE is 0010b to trap only second byte of every DWORD)
72 ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)
73 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access:
74 Address = 0x60
75 Length = 8
76 Type = IoTrapExTypeWrite
77 ByteEnable = 0x01 (BE is 0001b to trap only first byte of every DWORD)
78 ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)
79 **/
80 typedef struct {
81 /**
82 The Address must be dword alignment.
83 **/
84 UINT16 Address;
85 UINT16 Length;
86 IO_TRAP_EX_DISPATCH_TYPE Type;
87 /**
88 Bitmap to enable trap for each byte of every dword alignment address.
89 The Io Trap Address must be dword alignment for ByteEnable.
90 E.g. 0001b for first byte, 0010b for second byte, 1100b for third and fourth byte.
91 **/
92 UINT8 ByteEnable;
93 /**
94 ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for any byte access.
95 The Io Trap Address must be dword alignment for ByteEnableMask.
96 **/
97 UINT8 ByteEnableMask;
98 } IO_TRAP_EX_REGISTER_CONTEXT;
99
100 /**
101 Callback function for an PCH IO TRAP EX handler dispatch.
102
103 @param[in] Address DWord-aligned address of the trapped cycle.
104 @param[in] ByteEnable This is the DWord-aligned byte enables associated with the trapped cycle.
105 A 1 in any bit location indicates that the corresponding byte is enabled in the cycle.
106 @param[in] WriteCycle TRUE = Write cycle; FALSE = Read cycle
107 @param[in] WriteData DWord of I/O write data. This field is undefined after trapping a read cycle.
108 The byte of WriteData is only valid if the corresponding bits in ByteEnable is 1.
109 E.g.
110 If ByteEnable is 0001b, then only first byte of WriteData is valid.
111 If ByteEnable is 0010b, then only second byte of WriteData is valid.
112 **/
113 typedef
114 VOID
115 (EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) (
116 IN UINT16 Address,
117 IN UINT8 ByteEnable,
118 IN BOOLEAN WriteCycle,
119 IN UINT32 WriteData
120 );
121
122 /**
123 Register a new IO Trap Ex SMI dispatch function.
124 The caller will provide information of IO trap setting via the context.
125 Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
126 This is the function to extend the IoTrap capability, and it's expected
127 to handle the special ByteEnable and ByteEnableMask setting.
128 This register function will occupy one IoTrap register if possible.
129 And it only support one handler for one IoTrap event.
130 The Address of context MUST NOT be 0, and MUST be dword alignment.
131 The Length of context MUST not less than 4, and MUST be power of 2.
132 The ByteEnable and ByteEnableMask MUST not be zero at the same time.
133 if the IO Trap handler is not used. It also enable the IO Trap Range to generate
134 SMI.
135 Caller must take care of reserving the IO addresses in ACPI.
136
137 @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
138 @param[in] DispatchFunction Pointer to dispatch function to be invoked for
139 this SMI source.
140 @param[in] RegisterContext Pointer to the dispatch function's context.
141 The caller fills this context in before calling
142 the register function to indicate to the register
143 function the IO trap Ex SMI source for which the dispatch
144 function should be invoked. This MUST not be NULL.
145 @param[out] DispatchHandle Handle of dispatch function.
146
147 @retval EFI_SUCCESS The dispatch function has been successfully
148 registered and the SMI source has been enabled.
149 @retval EFI_OUT_OF_RESOURCES Insufficient resources are available
150 @retval EFI_INVALID_PARAMETER Address requested is already in use.
151 @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock event has been triggered
152 **/
153 typedef
154 EFI_STATUS
155 (EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) (
156 IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,
157 IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction,
158 IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext,
159 OUT EFI_HANDLE *DispatchHandle
160 );
161
162 /**
163 Unregister a SMI source dispatch function.
164 This function is unsupported.
165
166 @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
167 @param[in] DispatchHandle Handle of dispatch function to deregister.
168
169 @retval EFI_UNSUPPORTED The function is unsupported.
170 **/
171 typedef
172 EFI_STATUS
173 (EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) (
174 IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,
175 IN EFI_HANDLE DispatchHandle
176 );
177
178 /**
179 Interface structure for the IO trap Extention protocol.
180 This protocol exposes full IO TRAP capability for ByteEnable and ByteEnableMask setting.
181 Platform code should fully control the ByteEnable and ByteEnableMake while using this protocol.
182
183 Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
184 This is the function to extend the IoTrap capability, and it's expected
185 to handle the special ByteEnable and ByteEnableMask setting.
186
187 The protocol is low level, It returns PSTH trapped cycle. This might not be safe for multithread
188 if more than one thread triggers the same IOTRAP at the same time.
189 **/
190 struct _IO_TRAP_EX_DISPATCH_PROTOCOL {
191 /**
192 Register function for PCH IO TRAP EX DISPATCH PROTOCOL.
193 The caller will provide information of IO trap setting via the context.
194 Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
195 This is the function to extend the IoTrap capability, and it's expected
196 to handle the special ByteEnable and ByteEnableMask setting.
197 This register function will occupy one IoTrap register if possible.
198 And it only support one handler for one IoTrap event.
199 The Address of context MUST NOT be 0, and MUST be dword alignment.
200 The Length of context MUST not less than 4, and MUST be power of 2.
201 The ByteEnable and ByteEnableMask MUST not be zero at the same time.
202 if the IO Trap handler is not used. It also enable the IO Trap Range to
203 generate SMI.
204 **/
205 IO_TRAP_EX_DISPATCH_REGISTER Register;
206 /**
207 Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL.
208 **/
209 IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister;
210 };
211
212 #endif
IO_TRAP_EX_DISPATCH_CALLBACK
VOID(* IO_TRAP_EX_DISPATCH_CALLBACK)(IN UINT16 Address, IN UINT8 ByteEnable, IN BOOLEAN WriteCycle, IN UINT32 WriteData)
Callback function for an PCH IO TRAP EX handler dispatch.
Definition: IoTrapExDispatch.h:115
IO_TRAP_EX_REGISTER_CONTEXT::ByteEnable
UINT8 ByteEnable
Bitmap to enable trap for each byte of every dword alignment address.
Definition: IoTrapExDispatch.h:92
_IO_TRAP_EX_DISPATCH_PROTOCOL
Interface structure for the IO trap Extention protocol.
Definition: IoTrapExDispatch.h:190
_IO_TRAP_EX_DISPATCH_PROTOCOL::Register
IO_TRAP_EX_DISPATCH_REGISTER Register
Register function for PCH IO TRAP EX DISPATCH PROTOCOL.
Definition: IoTrapExDispatch.h:205
_IO_TRAP_EX_DISPATCH_PROTOCOL::UnRegister
IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister
Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL.
Definition: IoTrapExDispatch.h:209
IO_TRAP_EX_REGISTER_CONTEXT::Address
UINT16 Address
The Address must be dword alignment.
Definition: IoTrapExDispatch.h:84
IO_TRAP_EX_DISPATCH_TYPE
IO_TRAP_EX_DISPATCH_TYPE
IO Trap Ex valid types.
Definition: IoTrapExDispatch.h:48
IO_TRAP_EX_DISPATCH_REGISTER
EFI_STATUS(* IO_TRAP_EX_DISPATCH_REGISTER)(IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, OUT EFI_HANDLE *DispatchHandle)
Register a new IO Trap Ex SMI dispatch function.
Definition: IoTrapExDispatch.h:155
IO_TRAP_EX_REGISTER_CONTEXT
IO Trap Ex context structure containing information about the IO trap Ex event that should invoke the...
Definition: IoTrapExDispatch.h:80
IO_TRAP_EX_DISPATCH_UNREGISTER
EFI_STATUS(* IO_TRAP_EX_DISPATCH_UNREGISTER)(IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a SMI source dispatch function.
Definition: IoTrapExDispatch.h:173
IO_TRAP_EX_REGISTER_CONTEXT::ByteEnableMask
UINT8 ByteEnableMask
ByteEnableMask bitwise to ignore the ByteEnable setting.
Definition: IoTrapExDispatch.h:97
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
IpuDataHob.h File Reference

This file defines the IPU DATA HOB. More...

#include <Base.h>
Include dependency graph for IpuDataHob.h:

Go to the source code of this file.

Classes

struct IPU_DATA_HOB
This HOB is used to pass IPU related information to DXE phase. More...

Detailed Description

This file defines the IPU DATA HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IpuDataHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
IpuDataHob.h
Go to the documentation of this file.
1 /** @file
2 This file defines the IPU DATA HOB
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IPU_DATA_HOB_H_
36 #define _IPU_DATA_HOB_H_
37
38 #include <Base.h>
39
40 extern EFI_GUID gIpuDataHobGuid;
41 #pragma pack (push,1)
42 ///
43 /// This HOB is used to pass IPU related information to DXE phase
44 ///
45 typedef struct {
46 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gIpuDataHobGuid
47 // @todo this HOB will have revision number.
48 /**
49 IpuSupport - Indicates IPU support status
50 1 - IPU is supported by Silicon and is opted-in to BIOS
51 0 - IPU is either not supported by Silicon or opted out of BIOS or both
52 **/
53 BOOLEAN IpuSupport;
54 } IPU_DATA_HOB;
55 #pragma pack (pop)
56
57 #endif // _IPU_DATA_HOB_H_
IPU_DATA_HOB
This HOB is used to pass IPU related information to DXE phase.
Definition: IpuDataHob.h:45
IPU_DATA_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
GUID Hob type structure for gIpuDataHobGuid.
Definition: IpuDataHob.h:46
IPU_DATA_HOB::IpuSupport
BOOLEAN IpuSupport
IpuSupport - Indicates IPU support status 1 - IPU is supported by Silicon and is opted-in to BIOS 0 -...
Definition: IpuDataHob.h:53
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
IpuLib.h File Reference

This file provides IPU Public Library. More...

Go to the source code of this file.

Functions

UINT64 | GetIpuBusNumber (VOID)
GetIpuBusNumber: Get IPU Bus Number. More...
UINT64 | GetIpuDevNumber (VOID)
GetIpuDevNumber: Get IPU Dev Number. More...
UINT64 | GetIpuFuncNumber (VOID)
GetIpuFunNumber: Get IPU Fun Number. More...

Detailed Description

This file provides IPU Public Library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IpuLib.h.

Function Documentation

◆ GetIpuBusNumber()

UINT64 GetIpuBusNumber ( VOID )

GetIpuBusNumber: Get IPU Bus Number.

Return values
PCI bus number for IPU

◆ GetIpuDevNumber()

UINT64 GetIpuDevNumber ( VOID )

GetIpuDevNumber: Get IPU Dev Number.

Return values
PCI dev number for IPU

◆ GetIpuFuncNumber()

UINT64 GetIpuFuncNumber ( VOID )

GetIpuFunNumber: Get IPU Fun Number.

Return values
PCI fun number for IPU
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
IpuLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides IPU Public Library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IPU_LIB_H_
36 #define _IPU_LIB_H_
37
38
39 /**
40 GetIpuBusNumber: Get IPU Bus Number
41
42 @retval PCI bus number for IPU
43 **/
44 UINT64
45 GetIpuBusNumber (
46 VOID
47 );
48
49 /**
50 GetIpuDevNumber: Get IPU Dev Number
51
52 @retval PCI dev number for IPU
53 **/
54 UINT64
55 GetIpuDevNumber (
56 VOID
57 );
58
59 /**
60 GetIpuFunNumber: Get IPU Fun Number
61
62 @retval PCI fun number for IPU
63 **/
64 UINT64
65 GetIpuFuncNumber (
66 VOID
67 );
68
69 #endif // _IPU_LIB_H_
GetIpuFuncNumber
UINT64 GetIpuFuncNumber(VOID)
GetIpuFunNumber: Get IPU Fun Number.
GetIpuDevNumber
UINT64 GetIpuDevNumber(VOID)
GetIpuDevNumber: Get IPU Dev Number.
GetIpuBusNumber
UINT64 GetIpuBusNumber(VOID)
GetIpuBusNumber: Get IPU Bus Number.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Classes
IpuPreMemConfig.h File Reference

IPU policy definitions. More...

#include <ConfigBlock.h>
Include dependency graph for IpuPreMemConfig.h:

Go to the source code of this file.

Classes

struct IPU_PREMEM_CONFIG
IPU PreMem configuration
Revision 1: More...

Detailed Description

IPU policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IpuPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IpuPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
IpuPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 IPU policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _IPU_CONFIG_PREMEM_H_
36 #define _IPU_CONFIG_PREMEM_H_
37
38 #pragma pack(push, 1)
39 #include <ConfigBlock.h>
40
41 #define IPU_PREMEM_CONFIG_REVISION 4
42
43 //
44 // GPIO native features pins data
45 //
46 #define GPIO_IMGUCLK_NUMBER_OF_PINS 6
47
48 //
49 // Maximum CSI (Camera Serial Interface) Port
50 //
51 #define MAX_CSI_PORT 8
52
53 // @todo file name will be changed to IpuConfig.h.
54
55 extern EFI_GUID gIpuPreMemConfigGuid;
56
57 /**
58 IPU PreMem configuration\n
59 <b>Revision 1</b>:
60 - Initial version.
61 <b>Revision 2</b>:
62 - Change Bit-wise to Byte-wise.
63 <b>Revision 3</b>:
64 - Add LaneUsed and Speed of each Port configuration for Mcd10 support.
65 <b>Revision 4</b>:
66 - Change GPIO_IMGUCLK_NUMBER_OF_PINS to 6
67 <b>Revision 5</b>:
68 - Deprecate IpuImrConfiguration.
69 **/
70 typedef struct {
71 CONFIG_BLOCK_HEADER Header; /// Config Block Header
72 /**
73 <b>(Test)</b> It enables the SA IPU Device if supported and not fused off.
74 If FALSE, all other policies in this config block will be ignored.
75 <b>1=TRUE</b>;
76 0=FALSE.
77 **/
78 UINT8 IpuEnable;
79 /**
80 Deprecate
81 **/
82 UINT8 IpuImrConfiguration;
83 /**
84 It enable the IMGU CLKOUT.
85 <b>TRUE</b>
86 FALSE
87 **/
88 UINT8 ImguClkOutEn[GPIO_IMGUCLK_NUMBER_OF_PINS];
89 UINT8 LaneUsed[MAX_CSI_PORT]; ///< Indicate laneUsed of each CSI port <b>0: Not configured</b>; 1: x1; 2:x2; 3:x3; 4:x4
90 UINT8 CsiSpeed[MAX_CSI_PORT]; ///< Indicate speed of each CSI port <b>0: Sensor default</b>; 1: <416Mbps; 2:<1.5Gbps; 3:<2Gbps; 4:<2.5Gbps; 5:<4Gbps; 6>4Gbps
91 } IPU_PREMEM_CONFIG;
92 #pragma pack(pop)
93
94 #endif // _IPU_PREMEM_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
IPU_PREMEM_CONFIG
IPU PreMem configuration Revision 1:
Definition: IpuPreMemConfig.h:70
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
IPU_PREMEM_CONFIG::IpuEnable
UINT8 IpuEnable
Config Block Header.
Definition: IpuPreMemConfig.h:78
IPU_PREMEM_CONFIG::IpuImrConfiguration
UINT8 IpuImrConfiguration
Deprecate.
Definition: IpuPreMemConfig.h:82
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Classes
IshConfig.h File Reference

ISH policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | ISH_GPIO_CONFIG
ISH GPIO settings. More...
struct | ISH_SPI_PIN_CONFIG
SPI signals settings. More...
struct | ISH_UART_PIN_CONFIG
UART signals settings. More...
struct | ISH_I2C_PIN_CONFIG
I2C signals settings. More...
struct | ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI. More...
struct | ISH_UART
Struct contains GPIO pins assigned and signal settings of UART. More...
struct | ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C. More...
struct | ISH_GP
Struct contains GPIO pins assigned and signal settings of GP. More...
struct | ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device. More...
struct | ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device. More...
struct | ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device. More...

Detailed Description

ISH policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IshConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
IshConfig.h
Go to the documentation of this file.
1 /** @file
2 ISH policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ISH_CONFIG_H_
36 #define _ISH_CONFIG_H_
37
38 #define ISH_PREMEM_CONFIG_REVISION 1
39 #define ISH_CONFIG_REVISION 2
40 #define ISH_I3C_CONFIG_REVISION 1
41 extern EFI_GUID gIshPreMemConfigGuid;
42 extern EFI_GUID gIshConfigGuid;
43 extern EFI_GUID gIshI3cConfigGuid;
44
45 #pragma pack (push,1)
46
47 /**
48 ISH GPIO settings
49 **/
50 typedef struct {
51 /**
52 GPIO signals pin muxing settings. If signal can be enable only on a single pin
53 then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_* in GpioPins*.h
54 for supported settings on a given platform
55 **/
56 UINT32 PinMux; ///< GPIO Pin mux configuration. Refer to GPIO_*_MUXING_ISH_*x_MOSI_*
57 /**
58 GPIO Pads Internal Termination.
59 For more information please see Platform Design Guide.
60 Check GPIO_ELECTRICAL_CONFIG for reference
61 **/
62 UINT32 PadTermination;
63 } ISH_GPIO_CONFIG;
64
65 /**
66 SPI signals settings.
67 **/
68 typedef struct {
69 ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configuration.
70 ISH_GPIO_CONFIG Miso; ///< MISO Pin configuration.
71 ISH_GPIO_CONFIG Clk; ///< CLK Pin configuration.
72 ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin configuration.
73 } ISH_SPI_PIN_CONFIG;
74
75
76 /**
77 UART signals settings.
78 **/
79 typedef struct {
80 ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration.
81 ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration.
82 ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration.
83 ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration.
84 } ISH_UART_PIN_CONFIG;
85
86
87 /**
88 I2C signals settings.
89 **/
90 typedef struct {
91 ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration.
92 ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration.
93 } ISH_I2C_PIN_CONFIG;
94
95
96 /**
97 Struct contains GPIO pins assigned and signal settings of SPI
98 **/
99 typedef struct {
100 UINT8 Enable; ///< ISH SPI GPIO pins assigned: <b>0: False</b> 1: True
101 UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS pins assigned: <b>0: False</b> 1: True
102 UINT16 RsvdField0; ///< Reserved field
103 ISH_SPI_PIN_CONFIG PinConfig;
104 } ISH_SPI;
105
106
107 /**
108 Struct contains GPIO pins assigned and signal settings of UART
109 **/
110 typedef struct {
111 UINT32 Enable : 1; ///< ISH UART GPIO pins assigned: <b>0: False</b> 1: True
112 UINT32 RsvdBits0 : 31; ///< Reserved Bits
113 ISH_UART_PIN_CONFIG PinConfig;
114 } ISH_UART;
115
116 /**
117 Struct contains GPIO pins assigned and signal settings of I2C
118 **/
119 typedef struct {
120 UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned: <b>0: False</b> 1: True
121 UINT32 RsvdBits0 : 31; ///< Reserved Bits
122 ISH_I2C_PIN_CONFIG PinConfig;
123 } ISH_I2C;
124
125 /**
126 Struct contains GPIO pins assigned and signal settings of GP
127 **/
128 typedef struct {
129 UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: <b>0: False</b> 1: True
130 UINT32 RsvdBits0 : 31; ///< Reserved Bits
131 ISH_GPIO_CONFIG PinConfig;
132 } ISH_GP;
133
134 ///
135 /// The ISH_CONFIG block describes Integrated Sensor Hub device.
136 ///
137 typedef struct {
138 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
139 ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS];
140 ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS];
141 ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS];
142 ISH_GP Gp[PCH_MAX_ISH_GP_PINS];
143
144 UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0: False</b> 1: True
145 UINT32 MsiInterrupt : 1; ///< ISH MSI Interrupts: <b>0: False</b> 1: True
146 UINT32 RsvdBits0 : 30; ///< Reserved Bits
147
148 } ISH_CONFIG;
149
150 typedef ISH_I2C ISH_I3C;
151 ///
152 /// The ISH_I3C_CONFIG block describes I3C in ISH device.
153 ///
154 typedef struct {
155 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
156
157 ISH_I3C Controller; ///< ISH I3C Controller
158 } ISH_I3C_CONFIG;
159
160 ///
161 /// Premem Policy for Integrated Sensor Hub device.
162 ///
163 typedef struct {
164 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
165 /**
166 ISH Controler 0: Disable; <b>1: Enable</b>.
167 For Desktop sku, the ISH POR should be disabled. <b> 0:Disable </b>.
168 **/
169 UINT32 Enable : 1;
170 UINT32 RsvdBits0 : 31; ///< Reserved Bits
171 } ISH_PREMEM_CONFIG;
172
173 #pragma pack (pop)
174
175 #endif // _ISH_CONFIG_H_
ISH_PREMEM_CONFIG
Premem Policy for Integrated Sensor Hub device.
Definition: IshConfig.h:163
ISH_I3C_CONFIG
The ISH_I3C_CONFIG block describes I3C in ISH device.
Definition: IshConfig.h:154
ISH_SPI::Enable
UINT8 Enable
ISH SPI GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:100
ISH_UART::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:112
ISH_I2C_PIN_CONFIG::Sda
ISH_GPIO_CONFIG Sda
SDA Pin configuration.
Definition: IshConfig.h:91
ISH_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:146
ISH_I2C
Struct contains GPIO pins assigned and signal settings of I2C.
Definition: IshConfig.h:119
ISH_UART_PIN_CONFIG::Cts
ISH_GPIO_CONFIG Cts
CTS Pin configuration.
Definition: IshConfig.h:83
ISH_GPIO_CONFIG::PadTermination
UINT32 PadTermination
GPIO Pads Internal Termination.
Definition: IshConfig.h:62
ISH_UART_PIN_CONFIG::Rx
ISH_GPIO_CONFIG Rx
RXD Pin configuration.
Definition: IshConfig.h:80
ISH_GP
Struct contains GPIO pins assigned and signal settings of GP.
Definition: IshConfig.h:128
ISH_I2C::Enable
UINT32 Enable
ISH I2C GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:120
ISH_UART_PIN_CONFIG
UART signals settings.
Definition: IshConfig.h:79
ISH_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:138
ISH_GPIO_CONFIG::PinMux
UINT32 PinMux
GPIO signals pin muxing settings.
Definition: IshConfig.h:56
ISH_GP::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:130
ISH_UART::Enable
UINT32 Enable
ISH UART GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:111
ISH_GP::Enable
UINT32 Enable
ISH GP GPIO pins assigned: 0: False 1: True.
Definition: IshConfig.h:129
ISH_I2C::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:121
ISH_SPI::RsvdField0
UINT16 RsvdField0
Reserved field.
Definition: IshConfig.h:102
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ISH_SPI
Struct contains GPIO pins assigned and signal settings of SPI.
Definition: IshConfig.h:99
ISH_SPI_PIN_CONFIG::Clk
ISH_GPIO_CONFIG Clk
CLK Pin configuration.
Definition: IshConfig.h:71
ISH_UART
Struct contains GPIO pins assigned and signal settings of UART.
Definition: IshConfig.h:110
ISH_UART_PIN_CONFIG::Tx
ISH_GPIO_CONFIG Tx
TXD Pin configuration.
Definition: IshConfig.h:81
ISH_I2C_PIN_CONFIG
I2C signals settings.
Definition: IshConfig.h:90
ISH_I3C_CONFIG::Controller
ISH_I3C Controller
ISH I3C Controller.
Definition: IshConfig.h:157
ISH_PREMEM_CONFIG::Enable
UINT32 Enable
ISH Controler 0: Disable; 1: Enable.
Definition: IshConfig.h:169
ISH_SPI_PIN_CONFIG
SPI signals settings.
Definition: IshConfig.h:68
ISH_GPIO_CONFIG
ISH GPIO settings.
Definition: IshConfig.h:50
ISH_I2C_PIN_CONFIG::Scl
ISH_GPIO_CONFIG Scl
SCL Pin configuration.
Definition: IshConfig.h:92
ISH_I3C_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:155
ISH_CONFIG
The ISH_CONFIG block describes Integrated Sensor Hub device.
Definition: IshConfig.h:137
ISH_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: IshConfig.h:170
ISH_CONFIG::PdtUnlock
UINT32 PdtUnlock
ISH PDT Unlock Msg: 0: False 1: True.
Definition: IshConfig.h:144
ISH_UART_PIN_CONFIG::Rts
ISH_GPIO_CONFIG Rts
RTS Pin configuration.
Definition: IshConfig.h:82
ISH_CONFIG::MsiInterrupt
UINT32 MsiInterrupt
ISH MSI Interrupts: 0: False 1: True.
Definition: IshConfig.h:145
ISH_SPI_PIN_CONFIG::Miso
ISH_GPIO_CONFIG Miso
MISO Pin configuration.
Definition: IshConfig.h:70
ISH_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: IshConfig.h:164
ISH_SPI_PIN_CONFIG::Mosi
ISH_GPIO_CONFIG Mosi
MOSI Pin configuration.
Definition: IshConfig.h:69
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
IshInfoLib.h File Reference

Ish Info Library header file. More...

Go to the source code of this file.

Functions

BOOLEAN | IsIshSupported (VOID)
Check if ISH is supported by PCH. More...
BOOLEAN | IsIshPresent (VOID)
Check whether ISH controller is enabled in the Silicon. More...

Detailed Description

Ish Info Library header file.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IshInfoLib.h.

Function Documentation

◆ IsIshPresent()

BOOLEAN IsIshPresent ( VOID )

Check whether ISH controller is enabled in the Silicon.

Return values
TRUE | ISH is enabled
FALSE | ISH is disabled

◆ IsIshSupported()

BOOLEAN IsIshSupported ( VOID )

Check if ISH is supported by PCH.

Return values
TRUE | ISH is supported by PCH
FALSE | ISH is not supported by PCH
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
IshInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Ish Info Library header file.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ISH_INFO_LIB_H_
36 #define _ISH_INFO_LIB_H_
37
38 /**
39 Check if ISH is supported by PCH
40
41 @retval TRUE ISH is supported by PCH
42 @retval FALSE ISH is not supported by PCH
43 **/
44 BOOLEAN
45 IsIshSupported (
46 VOID
47 );
48
49 /**
50 Check whether ISH controller is enabled in the Silicon.
51
52 @retval TRUE ISH is enabled
53 @retval FALSE ISH is disabled
54 **/
55 BOOLEAN
56 IsIshPresent (
57 VOID
58 );
59
60 #endif
IsIshPresent
BOOLEAN IsIshPresent(VOID)
Check whether ISH controller is enabled in the Silicon.
IsIshSupported
BOOLEAN IsIshSupported(VOID)
Check if ISH is supported by PCH.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
IshMsgs.h File Reference

ISH Messages. More...

#include <MkhiMsgs.h>
Include dependency graph for IshMsgs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

ISH Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file IshMsgs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): IshMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
IshMsgs.h
Go to the documentation of this file.
1 /** @file
2 ISH Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ISH_MSGS_H_
36 #define _ISH_MSGS_H_
37
38 #include <MkhiMsgs.h>
39
40 #pragma pack(1)
41
42 #define ISH_SET_FILE_CMD 0x1
43
44 #define PDT_UNLOCK_DATA_DATA_TYPE 0x1
45 #define PDT_UNLOCK_DATA_PAYLOAD_SIZE 0x0
46 #define PDT_UPDATE_DATA_DATA_TYPE 0x2
47
48 typedef struct {
49 UINT16 DataType; // 1 - PDT UNLOCK, 2 - PDT update
50 UINT16 PayloadSize; // Size of Payload file 2 bytes aligned
51 } PDT_DATA;
52
53 typedef struct {
54 UINT16 Command;
55 UINT16 MessageLength;
56 UINT8 FileName[12];
57 UINT16 NumberOfElements;
58 PDT_DATA Data;
59 } PDT_MESSAGE;
60
61 typedef struct {
62 UINT16 Command;
63 UINT16 MessageLength;
64 UINT32 Status;
65 } PDT_MESSAGE_ACK;
66
67 typedef union {
68 PDT_MESSAGE Request;
69 PDT_MESSAGE_ACK Response;
70 } PDT_MESSAGE_BUFFER;
71
72 typedef enum {
73 BiosToIshStatusSuccess = 0x0,
74 BiosToIshStatusFailure = 0xFFFFFFFF
75 } BIOSTOISH_RESPONSE_STATUS;
76
77 #pragma pack()
78
79 #endif // _ISH_MSGS_H_
MkhiMsgs.h
MKHI Messages.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ITbtInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
ITbtInfoHob.h File Reference

HOB definition to be used by iTBT during pre-boot enviornment. More...

#include <PeiITbtGenericStructure.h>
#include <TcssInfo.h>
Include dependency graph for ITbtInfoHob.h:

Go to the source code of this file.

Detailed Description

HOB definition to be used by iTBT during pre-boot enviornment.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ITbtInfoHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ITbtInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
ITbtInfoHob.h
Go to the documentation of this file.
1 /** @file
2 HOB definition to be used by iTBT during pre-boot enviornment.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ITBT_INFO_GUID_H_
36 #define _ITBT_INFO_GUID_H_
37 #include <PeiITbtGenericStructure.h>
38 #include <TcssInfo.h>
39
40 #pragma pack(1)
41 //
42 // ITBT Info HOB
43 //
44 typedef struct _ITBT_INFO_HOB {
45 EFI_HOB_GUID_TYPE EfiHobGuidType;
46 ITBT_ROOTPORT_CONFIG ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]; ///< iTbt Root Port Configuration
47 UINT16 ITbtForcePowerOnTimeoutInMs; ///< Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following mailbox communication.
48 UINT16 ITbtConnectTopologyTimeoutInMs; ///< Timeout value while sending connect topology mailbox command
49 UINT8 Usb4CmMode; ///< USB4 CM mode
50 UINT8 Reserved[3]; ///< Reserved for DWORD alignment
51 } ITBT_INFO_HOB;
52 #pragma pack()
53
54 #endif
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
PeiITbtGenericStructure.h
ITBT Policy definition to be referred in both PEI and DXE phase.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ITbtPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Variables
ITbtPolicy.h File Reference

Interface definition details between TBT and platform drivers during DXE phase. More...

#include <ConfigBlock.h>
#include <Library/ConfigBlockLib.h>
#include <DxeITbtConfig.h>
Include dependency graph for ITbtPolicy.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct ITBT_POLICY_PROTOCOL
ITBT DXE Policy. More...

Macros

#define ITBT_POLICY_PROTOCOL_REVISION 1
Don't change the original TBT_POLICY_PROTOCOL_REVISION macro, external modules maybe have consumed this macro in their source code. More...

Variables

EFI_GUID gITbtPolicyProtocolGuid
Extern the GUID for protocol users.

Detailed Description

Interface definition details between TBT and platform drivers during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ITbtPolicy.h.

Macro Definition Documentation

◆ ITBT_POLICY_PROTOCOL_REVISION

#define ITBT_POLICY_PROTOCOL_REVISION 1

Don't change the original TBT_POLICY_PROTOCOL_REVISION macro, external modules maybe have consumed this macro in their source code.

Directly update the TBT_POLICY_PROTOCOL_REVISION version number may cause those external modules to auto mark themselves wrong version info. Always create new version macro for new Policy protocol interface.

Definition at line 54 of file ITbtPolicy.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ITbtPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
ITbtPolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details between TBT and platform drivers during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ITBT_POLICY_H_
36 #define _ITBT_POLICY_H_
37
38 #include <ConfigBlock.h>
39 #include <Library/ConfigBlockLib.h>
40 #include <DxeITbtConfig.h>
41 ///
42 /// Extern the GUID for protocol users.
43 ///
44 extern EFI_GUID gITbtPolicyProtocolGuid;
45 extern EFI_GUID gDxeITbtConfigGuid;
46
47 /**
48 Don't change the original TBT_POLICY_PROTOCOL_REVISION macro, external
49 modules maybe have consumed this macro in their source code. Directly
50 update the TBT_POLICY_PROTOCOL_REVISION version number may cause those
51 external modules to auto mark themselves wrong version info.
52 Always create new version macro for new Policy protocol interface.
53 **/
54 #define ITBT_POLICY_PROTOCOL_REVISION 1
55
56 /**
57 ITBT DXE Policy
58
59 The ITBT_POLICY_PROTOCOL producer drvier is recommended to
60 set all the ITBT_POLICY_PROTOCOL size buffer zero before init any member parameter,
61 this clear step can make sure no random value for those unknow new version parameters.
62
63 Make sure to update the Revision if any change to the protocol, including the existing
64 internal structure definations.\n
65 Note: Here revision will be bumped up when adding/removing any config block under this structure.\n
66 <b>Revision 1</b>:
67 - Initial version.
68 **/
69 typedef struct {
70 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
71 /*
72 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
73 */
74 } ITBT_POLICY_PROTOCOL;
75
76 #endif
ITBT_POLICY_PROTOCOL::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Offset 0-31.
Definition: ITbtPolicy.h:70
ConfigBlock.h
Header file for Config Block Lib implementation.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
gITbtPolicyProtocolGuid
EFI_GUID gITbtPolicyProtocolGuid
Extern the GUID for protocol users.
ITBT_POLICY_PROTOCOL
ITBT DXE Policy.
Definition: ITbtPolicy.h:69
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
DxeITbtConfig.h
Headr file for iTBT DXE Policy.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ItssLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ItssLib.h File Reference

Header file for ItssLib. More...

Go to the source code of this file.

Functions

EFI_STATUS | ItssGet8254ClockGateState (OUT BOOLEAN *ClockGeteState)
This function gets the 8254CGE bit. More...
EFI_STATUS | ItssSet8254ClockGateState (IN BOOLEAN ClockGateEnable)
This function sets the 8254CGE bit. More...

Detailed Description

Header file for ItssLib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ItssLib.h.

Function Documentation

◆ ItssGet8254ClockGateState()

EFI_STATUS ItssGet8254ClockGateState ( OUT BOOLEAN * ClockGeteState )

This function gets the 8254CGE bit.

Parameters
[out] ClockGateState TRUE : 8254CGE is set, FALSE: 8254CGE is clear.
Return values
EFI_SUCCESS Get 8254CGE status successfully. EFI_UNSUPPORTED Doesn't support 8254CGE get.

◆ ItssSet8254ClockGateState()

EFI_STATUS ItssSet8254ClockGateState ( IN BOOLEAN ClockGateEnable )

This function sets the 8254CGE bit.

Parameters
[in] ClockGateEnable Enable or disable clock gate
Return values
EFI_SUCCESS Set 8254CGE status successfully. EFI_UNSUPPORTED Doesn't support 8254CGE set.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ItssLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ItssLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for ItssLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ITSS_LIB_H_
36 #define _ITSS_LIB_H_
37
38 /**
39 This function gets the 8254CGE bit
40
41 @param[out] ClockGateState TRUE : 8254CGE is set, FALSE: 8254CGE is clear.
42
43 @retval EFI_SUCCESS Get 8254CGE status successfully.
44 EFI_UNSUPPORTED Doesn't support 8254CGE get.
45 **/
46 EFI_STATUS
47 ItssGet8254ClockGateState (
48 OUT BOOLEAN *ClockGeteState
49 );
50
51 /**
52 This function sets the 8254CGE bit
53
54 @param[in] ClockGateEnable Enable or disable clock gate
55
56 @retval EFI_SUCCESS Set 8254CGE status successfully.
57 EFI_UNSUPPORTED Doesn't support 8254CGE set.
58 **/
59 EFI_STATUS
60 ItssSet8254ClockGateState (
61 IN BOOLEAN ClockGateEnable
62 );
63
64 #endif // _ITSS_LIB_H_
ItssGet8254ClockGateState
EFI_STATUS ItssGet8254ClockGateState(OUT BOOLEAN *ClockGeteState)
This function gets the 8254CGE bit.
ItssSet8254ClockGateState
EFI_STATUS ItssSet8254ClockGateState(IN BOOLEAN ClockGateEnable)
This function sets the 8254CGE bit.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): JhiProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
JhiProtocol.h File Reference

Header file for JHI (Intel DAL Host Interface Service) Protocol. More...

Go to the source code of this file.

Classes

struct _ME_JHI_PROTOCOL
JHI protocol provided for DXE phase The interface functions are for JHI APIs to transfer data between host and Intel ME subsystem. More...

Macros

#define | JHI_FILE_MISSING_SRC 0x101
Source File not found in install/uninstall or unable to load file in SendAndRecv.
#define | JHI_FILE_ERROR_AUTH 0x102
Attempted to load the file, but FW returned back a manifest failure check and rejected it.
#define | JHI_FILE_ERROR_DELETE 0x104
Unable to remove file corresponding to the UUID in uninstall Maybe permission issues.
#define | JHI_FILE_INVALID 0x105
Invalid file - bad characters or larger than 64K.
#define | JHI_FILE_ERROR_OPEN 0x106
Unable to open file. Maybe permission issues.
#define | JHI_FILE_UUID_MISMATCH 0x107
UUIDs dont match between applet file and function input.
#define | JHI_FILE_IDENTICAL 0x108
downloaded applet matches existing one in Jom
#define | JHI_INVALID_COMMAND 0x202
invalid JHI interface command
#define | JHI_ILLEGAL_VALUE 0x204
validation failed on input parameters
#define | JHI_COMMS_ERROR 0x300
Communications error due to HECI timeouts or ME auto resets or any other COMMS error.
#define | JHI_SERVICE_INVALID_GUID 0x302
Invalid COM guid (from DLL)
#define | JHI_APPLET_TIMEOUT 0x401
This may be a result of a Java code in VM in an infinite loop. TL will kill applet in JOM and return error code.
#define | JHI_APPID_NOT_EXIST 0x402
If appid is not present in app table.
#define | JHI_JOM_FATAL 0x403
JOM fatal error.
#define | JHI_JOM_OVERFLOW 0x404
exceeds max installed applets or active sessions in JOM
#define | JHI_JOM_ERROR_DOWNLOAD 0x405
JOM download error.
#define | JHI_JOM_ERROR_UNLOAD 0x406
JOM unload error.
#define | JHI_ERROR_LOGGING 0x500
Error in logging.
#define | JHI_UNKNOWN_ERROR 0x600
Any other error.
#define | JHI_SUCCESS 0x00
general success response
#define | JHI_INVALID_HANDLE 0x201
invalid JHI handle
#define | JHI_INVALID_PARAMS 0x203
passed a null pointer to a required argument / illegal arguments passed to API function
#define | JHI_INVALID_APPLET_GUID JHI_ILLEGAL_VALUE
the applet UUID is invalid
#define | JHI_SERVICE_UNAVAILABLE 0x301
there is no connection to JHI service
#define | JHI_ERROR_REGISTRY 0x501
error for any registry based access or registry corruption
#define | JHI_ERROR_REPOSITORY_NOT_FOUND 0x1000
when cannot find applets repository directory
#define | JHI_INTERNAL_ERROR 0x601
an unexpected internal error happened.
#define | JHI_INVALID_BUFFER_SIZE 0x1001
used a buffer that is larger than JHI_BUFFER_MAX
#define | JHI_INVALID_COMM_BUFFER 0x1002
JVM_COMM_BUFFER passed to function is invalid.
#define | JHI_INVALID_INSTALL_FILE 0x1003
the dalp file path is invalid
#define | JHI_READ_FROM_FILE_FAILED 0x1004
failed to read DALP file
#define | JHI_INVALID_PACKAGE_FORMAT 0x1005
dalp file format is not a valid
#define | JHI_FILE_ERROR_COPY 0x103
applet file could not be copied to repository
#define | JHI_INVALID_INIT_BUFFER 0x1006
passed an invalid init buffer to the function
#define | JHI_FILE_NOT_FOUND JHI_FILE_MISSING_SRC
could not find the specified dalp file
#define | JHI_INVALID_FILE_EXTENSION 0x1007
applets package file must end with .dalp extension.
#define | JHI_MAX_INSTALLED_APPLETS_REACHED JHI_JOM_OVERFLOW
exceeds max applets allowed, need to uninstall an applet.
#define | JHI_INSTALL_FAILURE_SESSIONS_EXISTS 0x1008
could not install because there are open sessions.
#define | JHI_INSTALL_FAILED 0x1009
no compatible applet was found in the DALP file
#define | JHI_SVL_CHECK_FAIL 0x1040
install failed due to an svl check
#define | JHI_DELETE_FROM_REPOSITORY_FAILURE JHI_FILE_ERROR_DELETE
unable to delete applet DALP file from repository
#define | JHI_UNINSTALL_FAILURE_SESSIONS_EXISTS 0x100A
for app uninstallation errors
#define | JHI_APPLET_NOT_INSTALLED JHI_APPID_NOT_EXIST
trying to create a session of uninstalled applet
#define | JHI_MAX_SESSIONS_REACHED 0x100C
exceeds max sessions allowed, need to close a session.
#define | JHI_SHARED_SESSION_NOT_SUPPORTED 0x100D
the applet does not support shared sessions.
#define | JHI_MAX_SHARED_SESSION_REACHED 0x100E
failed to get session handle due to maximun handles limit.
#define | JHI_FIRMWARE_OUT_OF_RESOURCES 0x1018
request causes the VM to exceed its memory quota
#define | JHI_INVALID_SESSION_HANDLE 0x100F
the session handle is not of an active session.
#define | JHI_INSUFFICIENT_BUFFER 0x200
buffer overflow - response greater than supplied Rx buffer
#define | JHI_APPLET_FATAL 0x400
This may be a result of uncaught exception or unusual applet error that results in applet being terminated by TL VM.
#define | JHI_SESSION_NOT_REGISTERED 0x1010
trying to unregister a session that is not registered for events.
#define | JHI_SESSION_ALREADY_REGSITERED 0x1011
Registration to an event is done only once.
#define | JHI_EVENTS_NOT_SUPPORTED 0x1012
events are not supported for this type of session
#define | JHI_APPLET_PROPERTY_NOT_SUPPORTED 0x1013
Rerturned when calling GetAppletProperty with invalid property.
#define | JHI_SPOOLER_NOT_FOUND 0x1014
cannot find the spooler file
#define | JHI_INVALID_SPOOLER 0x1015
cannot download spooler / create an instance of the spooler
#define | JHI_NO_CONNECTION_TO_FIRMWARE JHI_COMMS_ERROR
JHI has no connection to the VM.
#define | JHI_VM_DLL_FILE_NOT_FOUND 0x1016
VM DLL is missing from the exe path.
#define | JHI_VM_DLL_VERIFY_FAILED 0x1017
DLL Signature or Publisher name are not valid.
#define | JHI_IAC_SERVER_SESSION_EXIST 0x1020
May occur when trying to create two sessions on an IAC server applet.
#define | JHI_IAC_SERVER_INTERNAL_SESSIONS_EXIST 0x1021
May occur when trying to close an IAC server applet session that has internal sessions.
#define | JHI_APPLET_AUTHENTICATION_FAILURE JHI_FILE_ERROR_AUTH
FW rejected the applet while trying to install it.
#define | APPID_BIN_LENGTH 16
binary length of applet ID
#define | APPID_STR_LENGTH 32
string length of applet ID (without \0 and separators)
#define | JHI_PROTOCOL_REVISION 1
Revision.

Typedefs

typedef JHI_RET(* | JHI_INITIALIZE) (OUT EFI_HANDLE *Handle, IN VOID *Context, IN UINT32 Flags)
Initializes the DAL client programming library by allocating resources, establishing a session with the ME Firmware through the JHI Service installed in the PC client. More...
typedef JHI_RET(* | JHI_UNINIT) (IN EFI_HANDLE Handle)
Uninitializes the DAL client programming library by de-allocating resources and closes the connection with host JHI service. More...
typedef JHI_RET(* | JHI_INSTALL_FILE) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST CHAR16 *SrcFile)
Install an applet file to JHI core. More...
typedef JHI_RET(* | JHI_INSTALL_CONTENT) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST VOID *AppletBlob, IN CONST UINT32 AppletLength)
Install an applet from content to JHI core. More...
typedef JHI_RET(* | JHI_UNINSTALL) (IN EFI_HANDLE Handle, IN CHAR8 *AppId)
Uninstall an applet from JHI core. More...
typedef JHI_RET(* | JHI_GET_APPLET_PROPERTY) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN OUT JVM_COMM_BUFFER *CommBuffer)
Get applet property from JHI core. More...
typedef JHI_RET(* | JHI_CREATE_SESSION) (IN CONST EFI_HANDLE Handle, IN CONST CHAR8 *AppId, IN UINT32 Flags, IN DATA_BUFFER *InitBuffer, OUT EFI_HANDLE *SessionHandle)
Create a session for an applet. More...
typedef JHI_RET(* | JHI_CLOSE_SESSION) (IN EFI_HANDLE Handle, IN EFI_HANDLE *SessionHandle)
Close a session for an applet. More...
typedef JHI_RET(* | JHI_GET_SESSIONS_COUNT) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, OUT UINT32 *SessionsCount)
This function gets number of active sessions of an installed applet. More...
typedef JHI_RET(* | JHI_GET_SESSION_INFO) (IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, OUT JHI_SESSION_INFO *SessionInfo)
Get session information for a session. More...
typedef JHI_RET(* | JHI_GET_VERSION_INFO) (IN CONST EFI_HANDLE Handle, OUT JHI_VERSION_INFO *VersionInfo)
Get version information of JHI core. More...
typedef JHI_RET(* | JHI_SEND_ADN_RECEIVE) (IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, IN INT32 CommandId, IN OUT JVM_COMM_BUFFER *CommBuffer, OUT INT32 *ResponseCode)
Send/Receive data to/from JHI core. More...

Detailed Description

Header file for JHI (Intel DAL Host Interface Service) Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file JhiProtocol.h.

Typedef Documentation

◆ JHI_CLOSE_SESSION

typedef JHI_RET( * JHI_CLOSE_SESSION) (IN EFI_HANDLE Handle, IN EFI_HANDLE *SessionHandle)

Close a session for an applet.

This API function close the session. After the function return, SessionHandle value will be not valid to use.

Parameters
[in] | Handle | The JHI handle.
[in] | SessionHandle | The pointer to the session handle to be closed.
Return values
JHI_SUCCESS | Close session successfully.
others | Error code that return from JHI core.

Definition at line 519 of file JhiProtocol.h.

◆ JHI_CREATE_SESSION

typedef JHI_RET( * JHI_CREATE_SESSION) (IN CONST EFI_HANDLE Handle, IN CONST CHAR8 *AppId, IN UINT32 Flags, IN DATA_BUFFER *InitBuffer, OUT EFI_HANDLE *SessionHandle)

Create a session for an applet.

This API function creates a session to a given applet (represented by appid) and return a session handle to which used to refer to the applet instance that would like to communicate with.

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
[in] | Flags | The flag to create session.

Here lists the flags that used when creating a session:

#define JHI_NO_FLAGS 0 // no flags to be used #define JHI_SHARED_SESSION 1 // create a shared session, or receive a handle for an existing shared session Note: for preboot JHI, we won't support multi-thread mechanism. So, there is no shared session, either. In the other words, JHI_NO_FLAGS(0) is the only value that we support for Flags field.

Parameters
[in] | InitBuffer | The pointer to the buffer for creating session. Some initialization data that will be passed to the applet (the applet onInit() function). It can be set to NULL if no init data is needed by the applet.
[in] | SessionHandle | The pointer to the session handle to be created and returned.
Return values
JHI_SUCCESS | Create session successfully.
others | Error code that return from JHI core.

Definition at line 499 of file JhiProtocol.h.

◆ JHI_GET_APPLET_PROPERTY

typedef JHI_RET( * JHI_GET_APPLET_PROPERTY) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN OUT JVM_COMM_BUFFER *CommBuffer)

Get applet property from JHI core.

This interface used to query one of the following properties of an installed applet: " applet.name " applet.vendor " applet.description " applet.version " security.version " applet.flash.quota " applet.debug.enable " applet.shared.session.support " applet.platform

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
[in] | CommBuffer | The pointer to the buffer for information transfer.
Return values
JHI_SUCCESS | Get applet property from JHI core successfully.
others | Error code that return from JHI core.

Definition at line 465 of file JhiProtocol.h.

◆ JHI_GET_SESSION_INFO

typedef JHI_RET( * JHI_GET_SESSION_INFO) (IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, OUT JHI_SESSION_INFO *SessionInfo)

Get session information for a session.

This API function returns information of a given session. Currently only the session state is available, but this API an be extended later to return more info.

Parameters
[in] | Handle | The JHI handle.
[in] | SessionHandle | The session handle to be queried.
[in] | SessionInfo | The pointer to the buffer of session information.
Return values
JHI_SUCCESS | Get session information successfully.
others | Error code that return from JHI core.

Definition at line 556 of file JhiProtocol.h.

◆ JHI_GET_SESSIONS_COUNT

typedef JHI_RET( * JHI_GET_SESSIONS_COUNT) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, OUT UINT32 *SessionsCount)

This function gets number of active sessions of an installed applet.

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
[in] | SessionsCount | The pointer to the buffer of session count.
Return values
JHI_SUCCESS | Get session count successfully.
others | Error code that return from JHI core.

Definition at line 536 of file JhiProtocol.h.

◆ JHI_GET_VERSION_INFO

typedef JHI_RET( * JHI_GET_VERSION_INFO) (IN CONST EFI_HANDLE Handle, OUT JHI_VERSION_INFO *VersionInfo)

Get version information of JHI core.

This function is used in order to get the versions of the FW, JHI and other general information such as Communication mode.

Parameters
[in] | Handle | The JHI handle.
[in] | VersionInfo | The pointer to the buffer of version information.
Return values
JHI_SUCCESS | Get version information successfully.
others | Error code that return from JHI core.

Definition at line 574 of file JhiProtocol.h.

◆ JHI_INITIALIZE

typedef JHI_RET( * JHI_INITIALIZE) (OUT EFI_HANDLE *Handle, IN VOID *Context, IN UINT32 Flags)

Initializes the DAL client programming library by allocating resources, establishing a session with the ME Firmware through the JHI Service installed in the PC client.

Typically, this is the first function called by the clients of the JHI interface. Context must be NULL and flags set to 0.

Parameters
[out] | Handle | The pointer to JHI handle. Handle returned by the interface for use by the application in future references to maintain application related info.
[in] | Context | The pointer to application related context information that can be returned by interface if necessary.
[in] | Flags | Input parameter used to indicate future conditions.
Return values
JHI_SUCCESS | Initialize JHI core successfully.
others | Error code that return from JHI core.

Definition at line 359 of file JhiProtocol.h.

◆ JHI_INSTALL_CONTENT

typedef JHI_RET( * JHI_INSTALL_CONTENT) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST VOID *AppletBlob, IN CONST UINT32 AppletLength)

Install an applet from content to JHI core.

This is a preboot version of JHI_Install3 API. This API is similar with JHI_PROTOCOL.InstallFile. This function gets the AppID and the contents (AppletBlob and AppletLength) of the application package then sent to JOM through JHI service.

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
[in] | AppletBlob | The raw data of the applet.
[in] | AppletLength | The data length of the applet.
Return values
JHI_SUCCESS | Install an applet to JHI core successfully.
others | Error code that return from JHI core.

Definition at line 419 of file JhiProtocol.h.

◆ JHI_INSTALL_FILE

typedef JHI_RET( * JHI_INSTALL_FILE) (IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST CHAR16 *SrcFile)

Install an applet file to JHI core.

This is a preboot version of JHI_Install2 API. This function gets the AppID and the path where the application package is stored which are then sent to JOM through JHI service. On successful installation, the application along with the manifest is then installed onto the ME through the JHI service.

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
[in] | SrcFile | The file path of the applet.
Return values
JHI_SUCCESS | Install an applet to JHI core successfully.
others | Error code that return from JHI core.

Definition at line 397 of file JhiProtocol.h.

◆ JHI_SEND_ADN_RECEIVE

typedef JHI_RET( * JHI_SEND_ADN_RECEIVE) (IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, IN INT32 CommandId, IN OUT JVM_COMM_BUFFER *CommBuffer, OUT INT32 *ResponseCode)

Send/Receive data to/from JHI core.

This is a preboot version of JHI_SendAndRecv2 API. The interface allows for sending and receiving raw data and in addition a UINT32 response code. This is an atomic operation from the perspective of the calling application.

Parameters
[in] | Handle | The JHI handle.
[in] | SessionHandle | The session handle.
[in] | CommandId | The command id that is sent to the applet.
[in] | CommBuffer | I/O communication buffer for sending/receiving raw data. In case the function returns JHI_INSUFFICIENT_BUFFER the RxBuf->length will hold the buffer size required by the applet for the response.
[in] | ResponseCode | The pointer to the buffer of response code. The response code returned from the applet to the application by using the SetResponseCode() method. It can be NULL.
Return values
JHI_SUCCESS | Data transfer successfully.
others | Error code that return from JHI core.

Definition at line 602 of file JhiProtocol.h.

◆ JHI_UNINIT

typedef JHI_RET( * JHI_UNINIT) (IN EFI_HANDLE Handle)

Uninitializes the DAL client programming library by de-allocating resources and closes the connection with host JHI service.

Typically, this is the last function called by the clients of the JHI interface and is used for cleanup at the end of a session. This is a preboot version of JHI_Deinit API.

Parameters
[in] Handle The JHI handle.
Return values
JHI_SUCCESS | Uninitialize JHI core successfully.
others | Error code that return from JHI core.

Definition at line 378 of file JhiProtocol.h.

◆ JHI_UNINSTALL

typedef JHI_RET( * JHI_UNINSTALL) (IN EFI_HANDLE Handle, IN CHAR8 *AppId)

Uninstall an applet from JHI core.

This is the interface used to uninstall an existing application from the JOM.

Parameters
[in] | Handle | The JHI handle.
[in] | AppId | The applet UUID string without separator characters ('-')
Return values
JHI_SUCCESS | Uninstall an applet to JHI core successfully.
others | Error code that return from JHI core.

Definition at line 438 of file JhiProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): JhiProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
JhiProtocol.h
Go to the documentation of this file.
1 /** @file
2 Header file for JHI (Intel DAL Host Interface Service) Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __JHI_PROTOCOL_H__
37 #define __JHI_PROTOCOL_H__
38
39 typedef UINT32 JHI_RET;
40 typedef VOID* JHI_HANDLE;
41 typedef VOID* JHI_SESSION_HANDLE;
42
43 //------------------------------------------------------------
44 // JHI return codes
45 //------------------------------------------------------------
46 #define JHI_FILE_MISSING_SRC 0x101 ///< Source File not found in install/uninstall or unable to load file in SendAndRecv
47 #define JHI_FILE_ERROR_AUTH 0x102 ///< Attempted to load the file, but FW returned back a manifest failure check and rejected it
48 #define JHI_FILE_ERROR_DELETE 0x104 ///< Unable to remove file corresponding to the UUID in uninstall Maybe permission issues
49 #define JHI_FILE_INVALID 0x105 ///< Invalid file - bad characters or larger than 64K
50 #define JHI_FILE_ERROR_OPEN 0x106 ///< Unable to open file. Maybe permission issues
51 #define JHI_FILE_UUID_MISMATCH 0x107 ///< UUIDs dont match between applet file and function input
52 #define JHI_FILE_IDENTICAL 0x108 ///< downloaded applet matches existing one in Jom
53
54 #define JHI_INVALID_COMMAND 0x202 ///< invalid JHI interface command
55 #define JHI_ILLEGAL_VALUE 0x204 ///< validation failed on input parameters
56
57 #define JHI_COMMS_ERROR 0x300 ///< Communications error due to HECI timeouts or ME auto resets or any other COMMS error
58 #define JHI_SERVICE_INVALID_GUID 0x302 ///< Invalid COM guid (from DLL)
59
60 #define JHI_APPLET_TIMEOUT 0x401 ///< This may be a result of a Java code in VM in an infinite loop. TL will kill applet in JOM and return error code
61 #define JHI_APPID_NOT_EXIST 0x402 ///< If appid is not present in app table
62 #define JHI_JOM_FATAL 0x403 ///< JOM fatal error
63 #define JHI_JOM_OVERFLOW 0x404 ///< exceeds max installed applets or active sessions in JOM
64 #define JHI_JOM_ERROR_DOWNLOAD 0x405 ///< JOM download error
65 #define JHI_JOM_ERROR_UNLOAD 0x406 ///< JOM unload error
66
67 #define JHI_ERROR_LOGGING 0x500 ///< Error in logging
68
69 #define JHI_UNKNOWN_ERROR 0x600 ///< Any other error
70
71 // General JHI Return Code
72 #define JHI_SUCCESS 0x00 ///< general success response
73 #define JHI_INVALID_HANDLE 0x201 ///< invalid JHI handle
74 #define JHI_INVALID_PARAMS 0x203 ///< passed a null pointer to a required argument / illegal arguments passed to API function
75 #define JHI_INVALID_APPLET_GUID JHI_ILLEGAL_VALUE ///< the applet UUID is invalid
76 #define JHI_SERVICE_UNAVAILABLE 0x301 ///< there is no connection to JHI service
77 #define JHI_ERROR_REGISTRY 0x501 ///< error for any registry based access or registry corruption
78 #define JHI_ERROR_REPOSITORY_NOT_FOUND 0x1000 ///< when cannot find applets repository directory
79 #define JHI_INTERNAL_ERROR 0x601 ///< an unexpected internal error happened.
80 #define JHI_INVALID_BUFFER_SIZE 0x1001 ///< used a buffer that is larger than JHI_BUFFER_MAX
81 #define JHI_INVALID_COMM_BUFFER 0x1002 ///< JVM_COMM_BUFFER passed to function is invalid
82
83 // Install errors
84 #define JHI_INVALID_INSTALL_FILE 0x1003 ///< the dalp file path is invalid
85 #define JHI_READ_FROM_FILE_FAILED 0x1004 ///< failed to read DALP file
86 #define JHI_INVALID_PACKAGE_FORMAT 0x1005 ///< dalp file format is not a valid
87 #define JHI_FILE_ERROR_COPY 0x103 ///< applet file could not be copied to repository
88 #define JHI_INVALID_INIT_BUFFER 0x1006 ///< passed an invalid init buffer to the function
89 #define JHI_FILE_NOT_FOUND JHI_FILE_MISSING_SRC ///< could not find the specified dalp file
90 #define JHI_INVALID_FILE_EXTENSION 0x1007 ///< applets package file must end with .dalp extension.
91 #define JHI_MAX_INSTALLED_APPLETS_REACHED JHI_JOM_OVERFLOW ///< exceeds max applets allowed, need to uninstall an applet.
92 #define JHI_INSTALL_FAILURE_SESSIONS_EXISTS 0x1008 ///< could not install because there are open sessions.
93 #define JHI_INSTALL_FAILED 0x1009 ///< no compatible applet was found in the DALP file
94 #define JHI_SVL_CHECK_FAIL 0x1040 ///< install failed due to an svl check
95
96 // Uninstall errors
97 #define JHI_DELETE_FROM_REPOSITORY_FAILURE JHI_FILE_ERROR_DELETE ///< unable to delete applet DALP file from repository
98 #define JHI_UNINSTALL_FAILURE_SESSIONS_EXISTS 0x100A ///< for app uninstallation errors
99
100 // Create Session errors
101 #define JHI_APPLET_NOT_INSTALLED JHI_APPID_NOT_EXIST ///< trying to create a session of uninstalled applet
102 #define JHI_MAX_SESSIONS_REACHED 0x100C ///< exceeds max sessions allowed, need to close a session.
103 #define JHI_SHARED_SESSION_NOT_SUPPORTED 0x100D ///< the applet does not support shared sessions.
104 #define JHI_MAX_SHARED_SESSION_REACHED 0x100E ///< failed to get session handle due to maximun handles limit.
105 #define JHI_FIRMWARE_OUT_OF_RESOURCES 0x1018 ///< request causes the VM to exceed its memory quota
106
107 // Close Session errors
108 #define JHI_INVALID_SESSION_HANDLE 0x100F ///< the session handle is not of an active session.
109
110 // Send And Recieve errors
111 #define JHI_INSUFFICIENT_BUFFER 0x200 ///< buffer overflow - response greater than supplied Rx buffer
112 #define JHI_APPLET_FATAL 0x400 ///< This may be a result of uncaught exception or unusual applet error that results in applet being terminated by TL VM.
113
114 // Register/Unregister session events
115 #define JHI_SESSION_NOT_REGISTERED 0x1010 ///< trying to unregister a session that is not registered for events.
116 #define JHI_SESSION_ALREADY_REGSITERED 0x1011 ///< Registration to an event is done only once.
117 #define JHI_EVENTS_NOT_SUPPORTED 0x1012 ///< events are not supported for this type of session
118
119 // Get Applet Property errors:
120 #define JHI_APPLET_PROPERTY_NOT_SUPPORTED 0x1013 ///< Rerturned when calling GetAppletProperty with invalid property
121
122 // Init errors
123 #define JHI_SPOOLER_NOT_FOUND 0x1014 ///< cannot find the spooler file
124 #define JHI_INVALID_SPOOLER 0x1015 ///< cannot download spooler / create an instance of the spooler
125 #define JHI_NO_CONNECTION_TO_FIRMWARE JHI_COMMS_ERROR ///< JHI has no connection to the VM
126
127 // DLL errors
128 #define JHI_VM_DLL_FILE_NOT_FOUND 0x1016 ///< VM DLL is missing from the exe path
129 #define JHI_VM_DLL_VERIFY_FAILED 0x1017 ///< DLL Signature or Publisher name are not valid.
130
131 // IAC errors
132 #define JHI_IAC_SERVER_SESSION_EXIST 0x1020 ///< May occur when trying to create two sessions on an IAC server applet
133 #define JHI_IAC_SERVER_INTERNAL_SESSIONS_EXIST 0x1021 ///< May occur when trying to close an IAC server applet session that has internal sessions
134
135 // Access control errors
136 #define JHI_MISSING_ACCESS_CONTROL 0x1030
137
138 // other errors
139 #define JHI_APPLET_AUTHENTICATION_FAILURE JHI_FILE_ERROR_AUTH ///< FW rejected the applet while trying to install it
140 #define JHI_BAD_APPLET_FORMAT 0x2001
141
142
143 // -----------------------------------------------------------
144 // Buffer size limitation is 2MB
145 // JHI will not accept any buffer with greater size.
146 //
147 // Note that this size limitiation does not mark the maximum buffer size an applet can recieve,
148 // applet max buffer size changes from one applet to another.
149 //
150 // This applies for all JHI API function that use buffers such as:
151 // SendAndRecieve, CreateSession, GetAppletProperty.
152 // -----------------------------------------------------------
153 #define JHI_BUFFER_MAX 2097152
154
155
156 //------------------------------------------------------------
157 // Applet version macros
158 //------------------------------------------------------------
159 // While applet version is represented in a Major.Minor format (i.e. 1.0)
160 // the VM repersntation of an applet version (that can be obtained using JHI_GetAppletProperty) is as an integer that combine both major and minor version.
161 // in order to perform the transition between to two representation we offer the following macros:
162
163 /*
164 Make VM Applet Version (32bit) from a Major.Minor format
165
166 Bits:
167 00-07 - Major
168 08-15 - Minor
169 15-31 - Reserved (All Zero)
170 */
171 #define MK_APPLET_VER(maj, min) ( (UINT32) \
172 (maj & 0x000000FFUL) | \
173 ((min << 8) & 0x0000FF00UL) & \
174 (0x0000FFFFUL) )
175
176 /* Extract Applet Major Version from a VM integer representation (num) */
177 #define MAJOR_APPLET_VER(num) ((UINT8) (num & 0x000000FFUL))
178
179 /* Extract Applet Minor Version from a VM integer representation (num) */
180 #define MINOR_APPLET_VER(num) ((UINT8) ((num & 0x0000FF00UL) >> 8))
181
182 #define APPID_BIN_LENGTH 16 ///< binary length of applet ID
183 #define APPID_STR_LENGTH 32 ///< string length of applet ID (without \0 and separators)
184
185 typedef VOID *VM_SESSION_HANDLE;
186 typedef CHAR8 APPID_STR [APPID_STR_LENGTH + 1]; // ANSI string, +1 for '\0'
187 typedef UINT8 APPID_BIN [APPID_BIN_LENGTH];
188 typedef UINT8 JHI_SESSION_ID [APPID_BIN_LENGTH];
189
190 //------------------------------------------------------------
191 // JHI Events
192 //------------------------------------------------------------
193
194 // this enum lists the types of data received by JHI event
195 typedef enum _JHI_EVENT_DATA_TYPE
196 {
197 JHI_DATA_FROM_APPLET = 0, // the event raised by an applet session
198 JHI_DATA_FROM_SERVICE = 1 // the event raised by JHI service
199 }JHI_EVENT_DATA_TYPE;
200
201 //this struct repersents the data received upon a JHI event
202 typedef struct {
203 UINT32 datalen; // byte length of the event data
204 UINT8* data; // the buffer that contains the event data
205 JHI_EVENT_DATA_TYPE dataType; // the event type
206 }JHI_EVENT_DATA;
207
208 // This is the format for a callback function that is used in order to
209 // receive session events.
210 typedef void (*JHI_EventFunc)(JHI_SESSION_HANDLE SessionHandle, JHI_EVENT_DATA EventData);
211
212
213 //------------------------------------------------------------
214 // JHI Version info.
215 //------------------------------------------------------------
216
217 // this enum lists the communication types that are used
218 // by JHI in order to communicate with the firmware
219 typedef enum _JHI_COMMUNICATION_TYPE
220 {
221 JHI_SOCKETS = 0, // communication by sockets
222 JHI_HECI = 1 // communication by HECI
223 } JHI_COMMUNICATION_TYPE;
224
225 #define VERSION_BUFFER_SIZE 50
226
227 // this enum lists the platfom types that are supported by JHI
228 typedef enum _JHI_PLATFROM_ID
229 {
230 ME = 0, // Intel(R) Management Engine (Intel(R) ME)
231 SEC = 1,
232 CSE = 2,
233 INVALID_PLATFORM_ID = -1
234 } JHI_PLATFROM_ID;
235
236 // This enum lists the VM types that are supported by JHI
237 typedef enum _JHI_VM_TYPE
238 {
239 JHI_VM_TYPE_INVALID = -1,
240 JHI_VM_TYPE_TL = 0,
241 JHI_VM_TYPE_BEIHAI = 1
242 } JHI_VM_TYPE;
243
244 // Different VM plugin types used by JHI
245 typedef enum _JHI_PLUGIN_TYPE
246 {
247 JHI_PLUGIN_TYPE_INVALID = -1,
248 JHI_PLUGIN_TYPE_TL = 0,
249 JHI_PLUGIN_TYPE_BEIHAI_V1 = 1,
250 JHI_PLUGIN_TYPE_BEIHAI_V2 = 2
251 } JHI_PLUGIN_TYPE;
252
253 // this struct contains information about the JHI service and the
254 // firmware versions, and additional info
255 typedef struct
256 {
257 CHAR8 JhiVersion[VERSION_BUFFER_SIZE]; // the version of the JHI service
258 CHAR8 FwVersion[VERSION_BUFFER_SIZE]; // the version of the firmware
259 JHI_COMMUNICATION_TYPE CommType; // the communication type between JHI and the firmware
260 JHI_PLATFROM_ID PlatformId; // the platform supported by the JHI service
261 JHI_VM_TYPE VmType; // the VM type supported by the JHI service
262 UINT8 JhiVerMajor; // Version information of JHI DXE driver
263 UINT8 JhiVerMinor;
264 UINT8 JhiVerHotfix;
265 UINT8 JhiVerBuild;
266 UINT8 FwMajor; // Firmware information of JHI DXE driver
267 UINT8 FwMinor;
268 UINT8 FwHotfix;
269 UINT8 FwBuild;
270 UINT32 Reserved[17]; // reserved bits
271 } JHI_VERSION_INFO;
272
273
274 //------------------------------------------------------------
275 // Session info
276 //------------------------------------------------------------
277
278 // this enum lists the states of a session
279 typedef enum _JHI_SESSION_STATE
280 {
281 JHI_SESSION_STATE_ACTIVE = 0, // the session is active
282 JHI_SESSION_STATE_NOT_EXISTS = 1 // the session does not exists
283 } JHI_SESSION_STATE;
284
285 // this struct contains information for a given session
286 typedef struct
287 {
288 JHI_SESSION_STATE state; // the session state
289 UINT32 flags; // the flags used when this session created
290 UINT32 reserved[20]; // reserved bits
291 } JHI_SESSION_INFO;
292
293 //------------------------------------------------------------
294 // Create Session flags
295 //------------------------------------------------------------
296 // this enum lists the flags that used when creating a session
297 //
298 #define JHI_NO_FLAGS 0 // no flags to be used
299 #define JHI_SHARED_SESSION 1 // create a shared session, or receive a handle for an existing shared session
300
301 //------------------------------------------------------------
302 // Data Buffer
303 //------------------------------------------------------------
304 typedef struct
305 {
306 VOID* buffer;
307 UINT32 length ;
308 } DATA_BUFFER ;
309
310
311 //------------------------------------------------------------
312 // For Tx and Rx downto the MEI routine
313 // DON'T ADD MEMBERS IN
314 //------------------------------------------------------------
315 typedef struct
316 {
317 DATA_BUFFER TxBuf [1] ;
318
319 //--------------------!!!!!!!!!!!--------------------//
320 // Dont add members in between TxBuf[1] & RxBuf[1] //
321 // The code that uses this depends on it //
322 //--------------------!!!!!!!!!!!--------------------//
323
324 DATA_BUFFER RxBuf [1] ;
325
326 // You may add anything here
327 } JVM_COMM_BUFFER ;
328
329
330 //
331 // Extern the GUID for protocol users.
332 //
333 extern EFI_GUID gJhiProtocolGuid;
334
335 //
336 // Forward reference for ANSI C compatibility
337 //
338 typedef struct _ME_JHI_PROTOCOL ME_JHI_PROTOCOL;
339
340 //
341 // Member functions
342 //
343 /**
344 Initializes the DAL client programming library by allocating resources, establishing
345 a session with the ME Firmware through the JHI Service installed in the PC client.
346 Typically, this is the first function called by the clients of the JHI interface.
347 Context must be NULL and flags set to 0.
348
349 @param[out] Handle The pointer to JHI handle.
350 Handle returned by the interface for use by the application
351 in future references to maintain application related info.
352 @param[in] Context The pointer to application related context information that
353 can be returned by interface if necessary.
354 @param[in] Flags Input parameter used to indicate future conditions.
355 @retval JHI_SUCCESS Initialize JHI core successfully.
356 @retval others Error code that return from JHI core.
357 **/
358 typedef
359 JHI_RET
360 (EFIAPI *JHI_INITIALIZE) (
361 OUT EFI_HANDLE *Handle,
362 IN VOID *Context,
363 IN UINT32 Flags
364 );
365
366 /**
367 Uninitializes the DAL client programming library by de-allocating resources and
368 closes the connection with host JHI service. Typically, this is the last function
369 called by the clients of the JHI interface and is used for cleanup at the end of
370 a session. This is a preboot version of JHI_Deinit API.
371
372 @param[in] Handle The JHI handle.
373
374 @retval JHI_SUCCESS Uninitialize JHI core successfully.
375 @retval others Error code that return from JHI core.
376 **/
377 typedef
378 JHI_RET
379 (EFIAPI *JHI_UNINIT) (
380 IN EFI_HANDLE Handle
381 );
382
383 /**
384 Install an applet file to JHI core. This is a preboot version of JHI_Install2 API.
385 This function gets the AppID and the path where the application package is stored
386 which are then sent to JOM through JHI service. On successful installation, the
387 application along with the manifest is then installed onto the ME through the JHI service.
388
389 @param[in] Handle The JHI handle.
390 @param[in] AppId The applet UUID string without separator characters ('-')
391 @param[in] SrcFile The file path of the applet.
392
393 @retval JHI_SUCCESS Install an applet to JHI core successfully.
394 @retval others Error code that return from JHI core.
395 **/
396 typedef
397 JHI_RET
398 (EFIAPI *JHI_INSTALL_FILE) (
399 IN EFI_HANDLE Handle,
400 IN CHAR8 *AppId,
401 IN CONST CHAR16 *SrcFile
402 );
403
404 /**
405 Install an applet from content to JHI core. This is a preboot version of JHI_Install3 API.
406 This API is similar with JHI_PROTOCOL.InstallFile. This function gets the AppID
407 and the contents (AppletBlob and AppletLength) of the application package then
408 sent to JOM through JHI service.
409
410 @param[in] Handle The JHI handle.
411 @param[in] AppId The applet UUID string without separator characters ('-')
412 @param[in] AppletBlob The raw data of the applet.
413 @param[in] AppletLength The data length of the applet.
414
415 @retval JHI_SUCCESS Install an applet to JHI core successfully.
416 @retval others Error code that return from JHI core.
417 **/
418 typedef
419 JHI_RET
420 (EFIAPI *JHI_INSTALL_CONTENT) (
421 IN EFI_HANDLE Handle,
422 IN CHAR8 *AppId,
423 IN CONST VOID *AppletBlob,
424 IN CONST UINT32 AppletLength
425 );
426
427 /**
428 Uninstall an applet from JHI core. This is the interface used to uninstall an
429 existing application from the JOM.
430
431 @param[in] Handle The JHI handle.
432 @param[in] AppId The applet UUID string without separator characters ('-')
433
434 @retval JHI_SUCCESS Uninstall an applet to JHI core successfully.
435 @retval others Error code that return from JHI core.
436 **/
437 typedef
438 JHI_RET
439 (EFIAPI *JHI_UNINSTALL) (
440 IN EFI_HANDLE Handle,
441 IN CHAR8 *AppId
442 );
443
444 /**
445 Get applet property from JHI core. This interface used to query one of the
446 following properties of an installed applet:
447 " applet.name
448 " applet.vendor
449 " applet.description
450 " applet.version
451 " security.version
452 " applet.flash.quota
453 " applet.debug.enable
454 " applet.shared.session.support
455 " applet.platform
456
457 @param[in] Handle The JHI handle.
458 @param[in] AppId The applet UUID string without separator characters ('-')
459 @param[in] CommBuffer The pointer to the buffer for information transfer.
460
461 @retval JHI_SUCCESS Get applet property from JHI core successfully.
462 @retval others Error code that return from JHI core.
463 **/
464 typedef
465 JHI_RET
466 (EFIAPI *JHI_GET_APPLET_PROPERTY) (
467 IN EFI_HANDLE Handle,
468 IN CHAR8 *AppId,
469 IN OUT JVM_COMM_BUFFER *CommBuffer
470 );
471
472 /**
473 Create a session for an applet. This API function creates a session to a given
474 applet (represented by appid) and return a session handle to which used to refer
475 to the applet instance that would like to communicate with.
476
477 @param[in] Handle The JHI handle.
478 @param[in] AppId The applet UUID string without separator characters ('-')
479 @param[in] Flags The flag to create session.
480 //
481 // Here lists the flags that used when creating a session:
482 //
483 #define JHI_NO_FLAGS 0 // no flags to be used
484 #define JHI_SHARED_SESSION 1 // create a shared session, or receive a handle for an existing shared session
485 // Note: for preboot JHI, we won't support multi-thread mechanism. So, there is no shared session, either.
486 // In the other words, JHI_NO_FLAGS(0) is the only value that we support for Flags field.
487
488 @param[in] InitBuffer The pointer to the buffer for creating session.
489 Some initialization data that will be passed to
490 the applet (the applet onInit() function). It can
491 be set to NULL if no init data is needed by the applet.
492 @param[in] SessionHandle The pointer to the session handle to be created
493 and returned.
494
495 @retval JHI_SUCCESS Create session successfully.
496 @retval others Error code that return from JHI core.
497 **/
498 typedef
499 JHI_RET
500 (EFIAPI *JHI_CREATE_SESSION) (
501 IN CONST EFI_HANDLE Handle,
502 IN CONST CHAR8 *AppId,
503 IN UINT32 Flags,
504 IN DATA_BUFFER *InitBuffer,
505 OUT EFI_HANDLE *SessionHandle
506 );
507
508 /**
509 Close a session for an applet. This API function close the session. After the
510 function return, SessionHandle value will be not valid to use.
511
512 @param[in] Handle The JHI handle.
513 @param[in] SessionHandle The pointer to the session handle to be closed.
514
515 @retval JHI_SUCCESS Close session successfully.
516 @retval others Error code that return from JHI core.
517 **/
518 typedef
519 JHI_RET
520 (EFIAPI *JHI_CLOSE_SESSION) (
521 IN EFI_HANDLE Handle,
522 IN EFI_HANDLE *SessionHandle
523 );
524
525 /**
526 This function gets number of active sessions of an installed applet.
527
528 @param[in] Handle The JHI handle.
529 @param[in] AppId The applet UUID string without separator characters ('-')
530 @param[in] SessionsCount The pointer to the buffer of session count.
531
532 @retval JHI_SUCCESS Get session count successfully.
533 @retval others Error code that return from JHI core.
534 **/
535 typedef
536 JHI_RET
537 (EFIAPI *JHI_GET_SESSIONS_COUNT) (
538 IN EFI_HANDLE Handle,
539 IN CHAR8 *AppId,
540 OUT UINT32 *SessionsCount
541 );
542
543 /**
544 Get session information for a session. This API function returns information of
545 a given session. Currently only the session state is available, but this API
546 an be extended later to return more info.
547
548 @param[in] Handle The JHI handle.
549 @param[in] SessionHandle The session handle to be queried.
550 @param[in] SessionInfo The pointer to the buffer of session information.
551
552 @retval JHI_SUCCESS Get session information successfully.
553 @retval others Error code that return from JHI core.
554 **/
555 typedef
556 JHI_RET
557 (EFIAPI *JHI_GET_SESSION_INFO) (
558 IN EFI_HANDLE Handle,
559 IN EFI_HANDLE SessionHandle,
560 OUT JHI_SESSION_INFO *SessionInfo
561 );
562
563 /**
564 Get version information of JHI core. This function is used in order to get the
565 versions of the FW, JHI and other general information such as Communication mode.
566
567 @param[in] Handle The JHI handle.
568 @param[in] VersionInfo The pointer to the buffer of version information.
569
570 @retval JHI_SUCCESS Get version information successfully.
571 @retval others Error code that return from JHI core.
572 **/
573 typedef
574 JHI_RET
575 (EFIAPI *JHI_GET_VERSION_INFO) (
576 IN CONST EFI_HANDLE Handle,
577 OUT JHI_VERSION_INFO *VersionInfo
578 );
579
580 /**
581 Send/Receive data to/from JHI core. This is a preboot version of JHI_SendAndRecv2 API.
582 The interface allows for sending and receiving raw data and in addition a UINT32
583 response code. This is an atomic operation from the perspective of the calling application.
584
585 @param[in] Handle The JHI handle.
586 @param[in] SessionHandle The session handle.
587 @param[in] CommandId The command id that is sent to the applet.
588 @param[in] CommBuffer I/O communication buffer for sending/receiving raw data.
589 In case the function returns JHI_INSUFFICIENT_BUFFER
590 the RxBuf->length will hold the buffer size required
591 by the applet for the response.
592
593 @param[in] ResponseCode The pointer to the buffer of response code.
594 The response code returned from the applet to
595 the application by using the SetResponseCode()
596 method. It can be NULL.
597
598 @retval JHI_SUCCESS Data transfer successfully.
599 @retval others Error code that return from JHI core.
600 **/
601 typedef
602 JHI_RET
603 (EFIAPI *JHI_SEND_ADN_RECEIVE) (
604 IN EFI_HANDLE Handle,
605 IN EFI_HANDLE SessionHandle,
606 IN INT32 CommandId,
607 IN OUT JVM_COMM_BUFFER *CommBuffer,
608 OUT INT32 *ResponseCode
609 );
610
611
612 ///
613 /// Revision
614 ///
615 #define JHI_PROTOCOL_REVISION 1
616
617 /**
618 JHI protocol provided for DXE phase
619 The interface functions are for JHI APIs to transfer data between host and Intel ME subsystem.
620 **/
621 struct _ME_JHI_PROTOCOL {
622 UINT8 Revision; ///< Structure revision number
623 JHI_INITIALIZE Initialize; ///< Initialize JHI DXE driver, allocate resource (JHI_Initialize)
624 JHI_UNINIT Uninit; ///< Uninitialized JHI DXE driver, free resource (JHI_Deinit)
625 JHI_INSTALL_FILE InstallFile; ///< Download an applet file into ME DAL VM (JHI_Install2)
626 JHI_INSTALL_CONTENT InstallContent; ///< Download an applet content into ME DAL VM (JHI_Install3)
627 JHI_UNINSTALL Uninstall; ///< Unload an applet from ME DAL VM (JHI_Uninstall)
628 JHI_GET_APPLET_PROPERTY GetAppletProperty; ///< Get information of downloaded applets (JHI_GetAppletProperty)
629 JHI_CREATE_SESSION CreateSession; ///< Create a session for a specific applet (JHI_CreateSession)
630 JHI_GET_SESSIONS_COUNT GetSessionsCount; ///< Get count of total sessions (JHI_GetSessionsCount)
631 JHI_CLOSE_SESSION CloseSession; ///< End a session for a specific applet (JHI_CloseSession)
632 JHI_GET_SESSION_INFO GetSessionInfo; ///< Get information of specific session (JHI_GetSessionInfo)
633 JHI_GET_VERSION_INFO GetVersionInfo; ///< Get information of JHI driver (JHI_GetVersionInfo)
634 JHI_SEND_ADN_RECEIVE SendAndReceive; ///< Send/receive data to/from a specific applet (JHI_SendAndRecv2)
635 };
636
637 #endif // __JHI_PROTOCOL_H__
638
_ME_JHI_PROTOCOL::CloseSession
JHI_CLOSE_SESSION CloseSession
End a session for a specific applet (JHI_CloseSession)
Definition: JhiProtocol.h:631
_ME_JHI_PROTOCOL::Uninit
JHI_UNINIT Uninit
Uninitialized JHI DXE driver, free resource (JHI_Deinit)
Definition: JhiProtocol.h:624
_ME_JHI_PROTOCOL::GetVersionInfo
JHI_GET_VERSION_INFO GetVersionInfo
Get information of JHI driver (JHI_GetVersionInfo)
Definition: JhiProtocol.h:633
JHI_GET_SESSION_INFO
JHI_RET(* JHI_GET_SESSION_INFO)(IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, OUT JHI_SESSION_INFO *SessionInfo)
Get session information for a session.
Definition: JhiProtocol.h:557
_ME_JHI_PROTOCOL::GetSessionsCount
JHI_GET_SESSIONS_COUNT GetSessionsCount
Get count of total sessions (JHI_GetSessionsCount)
Definition: JhiProtocol.h:630
JHI_GET_VERSION_INFO
JHI_RET(* JHI_GET_VERSION_INFO)(IN CONST EFI_HANDLE Handle, OUT JHI_VERSION_INFO *VersionInfo)
Get version information of JHI core.
Definition: JhiProtocol.h:575
JHI_GET_APPLET_PROPERTY
JHI_RET(* JHI_GET_APPLET_PROPERTY)(IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN OUT JVM_COMM_BUFFER *CommBuffer)
Get applet property from JHI core.
Definition: JhiProtocol.h:466
_ME_JHI_PROTOCOL::GetAppletProperty
JHI_GET_APPLET_PROPERTY GetAppletProperty
Get information of downloaded applets (JHI_GetAppletProperty)
Definition: JhiProtocol.h:628
_ME_JHI_PROTOCOL::Revision
UINT8 Revision
Structure revision number.
Definition: JhiProtocol.h:622
JHI_GET_SESSIONS_COUNT
JHI_RET(* JHI_GET_SESSIONS_COUNT)(IN EFI_HANDLE Handle, IN CHAR8 *AppId, OUT UINT32 *SessionsCount)
This function gets number of active sessions of an installed applet.
Definition: JhiProtocol.h:537
APPID_STR_LENGTH
#define APPID_STR_LENGTH
string length of applet ID (without \0 and separators)
Definition: JhiProtocol.h:183
_ME_JHI_PROTOCOL::InstallFile
JHI_INSTALL_FILE InstallFile
Download an applet file into ME DAL VM (JHI_Install2)
Definition: JhiProtocol.h:625
APPID_BIN_LENGTH
#define APPID_BIN_LENGTH
binary length of applet ID
Definition: JhiProtocol.h:182
_ME_JHI_PROTOCOL::Initialize
JHI_INITIALIZE Initialize
Initialize JHI DXE driver, allocate resource (JHI_Initialize)
Definition: JhiProtocol.h:623
JHI_INITIALIZE
JHI_RET(* JHI_INITIALIZE)(OUT EFI_HANDLE *Handle, IN VOID *Context, IN UINT32 Flags)
Initializes the DAL client programming library by allocating resources, establishing a session with t...
Definition: JhiProtocol.h:360
_ME_JHI_PROTOCOL::Uninstall
JHI_UNINSTALL Uninstall
Unload an applet from ME DAL VM (JHI_Uninstall)
Definition: JhiProtocol.h:627
JHI_UNINSTALL
JHI_RET(* JHI_UNINSTALL)(IN EFI_HANDLE Handle, IN CHAR8 *AppId)
Uninstall an applet from JHI core.
Definition: JhiProtocol.h:439
_ME_JHI_PROTOCOL::GetSessionInfo
JHI_GET_SESSION_INFO GetSessionInfo
Get information of specific session (JHI_GetSessionInfo)
Definition: JhiProtocol.h:632
JHI_CLOSE_SESSION
JHI_RET(* JHI_CLOSE_SESSION)(IN EFI_HANDLE Handle, IN EFI_HANDLE *SessionHandle)
Close a session for an applet.
Definition: JhiProtocol.h:520
JHI_SEND_ADN_RECEIVE
JHI_RET(* JHI_SEND_ADN_RECEIVE)(IN EFI_HANDLE Handle, IN EFI_HANDLE SessionHandle, IN INT32 CommandId, IN OUT JVM_COMM_BUFFER *CommBuffer, OUT INT32 *ResponseCode)
Send/Receive data to/from JHI core.
Definition: JhiProtocol.h:603
JHI_UNINIT
JHI_RET(* JHI_UNINIT)(IN EFI_HANDLE Handle)
Uninitializes the DAL client programming library by de-allocating resources and closes the connection...
Definition: JhiProtocol.h:379
_ME_JHI_PROTOCOL::CreateSession
JHI_CREATE_SESSION CreateSession
Create a session for a specific applet (JHI_CreateSession)
Definition: JhiProtocol.h:629
_ME_JHI_PROTOCOL::SendAndReceive
JHI_SEND_ADN_RECEIVE SendAndReceive
Send/receive data to/from a specific applet (JHI_SendAndRecv2)
Definition: JhiProtocol.h:634
JHI_INSTALL_CONTENT
JHI_RET(* JHI_INSTALL_CONTENT)(IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST VOID *AppletBlob, IN CONST UINT32 AppletLength)
Install an applet from content to JHI core.
Definition: JhiProtocol.h:420
_ME_JHI_PROTOCOL
JHI protocol provided for DXE phase The interface functions are for JHI APIs to transfer data between...
Definition: JhiProtocol.h:621
JHI_CREATE_SESSION
JHI_RET(* JHI_CREATE_SESSION)(IN CONST EFI_HANDLE Handle, IN CONST CHAR8 *AppId, IN UINT32 Flags, IN DATA_BUFFER *InitBuffer, OUT EFI_HANDLE *SessionHandle)
Create a session for an applet.
Definition: JhiProtocol.h:500
_ME_JHI_PROTOCOL::InstallContent
JHI_INSTALL_CONTENT InstallContent
Download an applet content into ME DAL VM (JHI_Install3)
Definition: JhiProtocol.h:626
JHI_INSTALL_FILE
JHI_RET(* JHI_INSTALL_FILE)(IN EFI_HANDLE Handle, IN CHAR8 *AppId, IN CONST CHAR16 *SrcFile)
Install an applet file to JHI core.
Definition: JhiProtocol.h:398
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): LockDownConfig.h File Reference

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Classes
LockDownConfig.h File Reference

Lock down policy. More...

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Classes

struct PCH_LOCK_DOWN_CONFIG
The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requirement. More...

Detailed Description

Lock down policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file LockDownConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): LockDownConfig.h Source File

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  • ConfigBlock
LockDownConfig.h
Go to the documentation of this file.
1 /** @file
2 Lock down policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _LOCK_DOWN_CONFIG_H_
36 #define _LOCK_DOWN_CONFIG_H_
37
38 #define PCH_LOCK_DOWN_CONFIG_REVISION 1
39 extern EFI_GUID gLockDownConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
45 for security requirement.
46 **/
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
49 /**
50 <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>.
51 **/
52 UINT32 GlobalSmi : 1;
53 /**
54 <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
55 Top Swap bit and the General Control and Status Registers Boot BIOS Straps.
56 Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
57 will mitigate malicious software attempts to replace the system BIOS with its own code.
58 0: Disable; <b>1: Enable</b>.
59 **/
60 UINT32 BiosInterface : 1;
61 /**
62 Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
63 for the BIOS region protection. When it is enabled, the BIOS Region can only be
64 modified from SMM.
65 If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
66 in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
67 then the InSMM.STS is a don't care.
68 The BIOS must set the EISS bit while BIOS Guard support is enabled.
69 In recovery path, platform can temporary disable EISS for SPI programming in
70 PEI phase or early DXE phase.
71 When PcdSmmVariableEnable is FALSE, to support BIOS regions update outside of SMM,
72 the BiosLock must be set to Disabled by platform.
73 0: Disable; <b>1: Enable.</b>
74 **/
75 UINT32 BiosLock : 1;
76 UINT32 SpiEiss : 1; ///< Separate EISS policy to be handled separately from BiosLock
77 /**
78 <b>(Test)</b> This test option when set will force all GPIO pads to be unlocked
79 before BIOS transitions to POSTBOOT_SAI. This option should not be enabled in production
80 configuration and used only for debug purpose when free runtime reconfiguration of
81 GPIO pads is needed.
82 <b>0: Disable</b>; 1: Enable.
83 **/
84 UINT32 UnlockGpioPads : 1;
85 UINT32 RsvdBits0 : 27; ///< Reserved bits
86 } PCH_LOCK_DOWN_CONFIG;
87
88 #pragma pack (pop)
89
90 #endif // _LOCK_DOWN_CONFIG_H_
PCH_LOCK_DOWN_CONFIG::SpiEiss
UINT32 SpiEiss
Separate EISS policy to be handled separately from BiosLock.
Definition: LockDownConfig.h:76
PCH_LOCK_DOWN_CONFIG::BiosLock
UINT32 BiosLock
Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region pro...
Definition: LockDownConfig.h:75
PCH_LOCK_DOWN_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: LockDownConfig.h:48
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_LOCK_DOWN_CONFIG
The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH for security requireme...
Definition: LockDownConfig.h:47
PCH_LOCK_DOWN_CONFIG::BiosInterface
UINT32 BiosInterface
(Test) Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register Top Swap ...
Definition: LockDownConfig.h:60
PCH_LOCK_DOWN_CONFIG::GlobalSmi
UINT32 GlobalSmi
(Test) Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
Definition: LockDownConfig.h:52
PCH_LOCK_DOWN_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: LockDownConfig.h:85
PCH_LOCK_DOWN_CONFIG::UnlockGpioPads
UINT32 UnlockGpioPads
(Test) This test option when set will force all GPIO pads to be unlocked before BIOS transitions to P...
Definition: LockDownConfig.h:84
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): LpcConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Classes
LpcConfig.h File Reference

Lpc policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_LPC_PREMEM_CONFIG
This structure contains the policies which are related to LPC. More...

Detailed Description

Lpc policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file LpcConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): LpcConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
LpcConfig.h
Go to the documentation of this file.
1 /** @file
2 Lpc policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _LPC_CONFIG_H_
36 #define _LPC_CONFIG_H_
37
38 #define PCH_LPC_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gLpcPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to LPC.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 Enhance the port 8xh decoding.
50 Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
51 @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
52 0: Disable, <b>1: Enable</b>
53 **/
54 UINT32 EnhancePort8xhDecoding : 1;
55 /**
56 Hardware Autonomous Enable.
57 When enabled, LPC will automatically engage power gating when it has reached its idle condition.
58 0: Disable, <b>1: Enable</b>
59 **/
60 UINT32 LpcPmHAE : 1;
61 UINT32 RsvdBits : 30; ///< Reserved bits
62 } PCH_LPC_PREMEM_CONFIG;
63
64 #pragma pack (pop)
65
66 #endif // _LPC_CONFIG_H_
PCH_LPC_PREMEM_CONFIG
This structure contains the policies which are related to LPC.
Definition: LpcConfig.h:46
PCH_LPC_PREMEM_CONFIG::LpcPmHAE
UINT32 LpcPmHAE
Hardware Autonomous Enable.
Definition: LpcConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_LPC_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved bits.
Definition: LpcConfig.h:61
PCH_LPC_PREMEM_CONFIG::EnhancePort8xhDecoding
UINT32 EnhancePort8xhDecoding
Enhance the port 8xh decoding.
Definition: LpcConfig.h:54
PCH_LPC_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: LpcConfig.h:47
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MbpSensitivePpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros | Variables
MbpSensitivePpi.h File Reference

MBP Sensitive PPI. More...

#include <MeBiosPayloadData.h>
Include dependency graph for MbpSensitivePpi.h:

Go to the source code of this file.

Classes

struct MBP_SENSITIVE_PPI
MBP SENSITIVE PPI Contains MBP sensitive data which should not be passed on to DXE as an HOB. More...

Macros

#define MBP_SENSITIVE_PPI_REVISION 1
Revision.

Variables

EFI_GUID gMbpSensitivePpiGuid
MBP Sensitive PPI GUID This PPI provides an interface to store MBP sensitive data in PEI phase.

Detailed Description

MBP Sensitive PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MbpSensitivePpi.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MbpSensitivePpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
MbpSensitivePpi.h
Go to the documentation of this file.
1 /** @file
2 MBP Sensitive PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MBP_SENSITIVE_PPI_H_
36 #define _MBP_SENSITIVE_PPI_H_
37
38 #include <MeBiosPayloadData.h>
39
40 ///
41 /// MBP Sensitive PPI GUID
42 /// This PPI provides an interface to store MBP sensitive data in PEI phase
43 ///
44 extern EFI_GUID gMbpSensitivePpiGuid;
45
46 ///
47 /// Revision
48 ///
49 #define MBP_SENSITIVE_PPI_REVISION 1
50
51 ///
52 /// MBP SENSITIVE PPI
53 /// Contains MBP sensitive data which should not be passed on to DXE as an HOB
54 ///
55 typedef struct {
56 UINT8 Revision; ///< Policy structure revision number
57 ME_BIOS_PAYLOAD_SENSITIVE MbpSensitiveData;
58 } MBP_SENSITIVE_PPI;
59
60 #endif // MBP_SENSITIVE_PPI
ME_BIOS_PAYLOAD_SENSITIVE
All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below str...
Definition: MeBiosPayloadData.h:310
gMbpSensitivePpiGuid
EFI_GUID gMbpSensitivePpiGuid
MBP Sensitive PPI GUID This PPI provides an interface to store MBP sensitive data in PEI phase.
MBP_SENSITIVE_PPI
MBP SENSITIVE PPI Contains MBP sensitive data which should not be passed on to DXE as an HOB.
Definition: MbpSensitivePpi.h:55
MBP_SENSITIVE_PPI::Revision
UINT8 Revision
Policy structure revision number.
Definition: MbpSensitivePpi.h:56
MeBiosPayloadData.h
Interface definition details for MBP.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeBiosPayloadData.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
MeBiosPayloadData.h File Reference

Interface definition details for MBP. More...

#include <CoreBiosMsg.h>
Include dependency graph for MeBiosPayloadData.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | MBP_HEADER
Common MBP types. More...
union | MBP_ITEM_HEADER
MBP items header. More...
struct | MBP_FW_VERSION_NAME
MBP items. More...
struct | MBP_IFWI_DNX_REQUEST
MBP IFWI DNX request structure containing IFWI Dnx request data. More...
union | HWA_DATA
HWA AppId. More...
struct | MBP_MPHY_DATA
ICC AppId. More...
struct | ME_BIOS_PAYLOAD
ME BIOS Payload structure containing insensitive data only. More...
struct | ME_BIOS_PAYLOAD_SENSITIVE
All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below structure only. More...

Macros

#define MBP_DATA_REVISION 2
ME-BIOS Payload Data. More...

Enumerations

enum MBP_ITEM_FLAGS

Detailed Description

Interface definition details for MBP.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeBiosPayloadData.h.

Macro Definition Documentation

◆ MBP_DATA_REVISION

#define MBP_DATA_REVISION 2

ME-BIOS Payload Data.

Revision 1:

  • Initial version. Revision 2:
  • Added Extended Performance data structure.
  • Deprecated MBP ICC profile structure.

Definition at line 48 of file MeBiosPayloadData.h.

Enumeration Type Documentation

◆ MBP_ITEM_FLAGS

enum MBP_ITEM_FLAGS
Enumerator
MbpItemFlagStoreToNvm | Item contains data to be stored in flash.
MbpItemFlagSensitive | Item contains sensitive data. Do not store in flash.
MbpItemFlagRuntime | Item is generated at runtime. Do not store in flash.

Definition at line 135 of file MeBiosPayloadData.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeBiosPayloadData.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeBiosPayloadData.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details for MBP.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_BIOS_PAYLOAD_DATA_H_
36 #define _ME_BIOS_PAYLOAD_DATA_H_
37 #include <CoreBiosMsg.h>
38
39 /**
40 ME-BIOS Payload Data
41
42 <b>Revision 1:</b>
43 - Initial version.
44 <b>Revision 2:</b>
45 - Added Extended Performance data structure.
46 - Deprecated MBP ICC profile structure.
47 **/
48 #define MBP_DATA_REVISION 2
49
50 #pragma pack (1)
51
52 ///
53 /// Common MBP types
54 ///
55 typedef struct {
56 UINT8 MbpSize; ///< Byte 0 - MBP Size in DW including Header
57 UINT8 NumEntries; ///< Byte 1 - Number of Entries (Data Items) in MBP
58 UINT16 Reserved; ///< Byte [3:2] - Reserved
59 } MBP_HEADER;
60
61 ///
62 /// MBP items header
63 ///
64 typedef union {
65 UINT32 Data;
66 struct {
67 UINT32 AppId : 8; ///< Byte 0 - Application ID
68 UINT32 ItemId : 8; ///< Byte 1 - Item ID
69 UINT32 Length : 8; ///< Byte 2 - Length in DW
70 UINT32 Flags : 8; ///< Byte 3 - Flags
71 } Fields;
72 } MBP_ITEM_HEADER;
73
74 //
75 // Macro to build abstract MBP Item Id
76 //
77 #define MBP_ITEM_ID(ApplicationId, ItemId) ((ApplicationId << 4) | ItemId)
78
79 #define MBP_ITEM_FW_VERSION_NAME MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdFwVerName)
80 #define MBP_ITEM_FW_CAPABILITIES MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdFwCapabilities)
81 #define MBP_ITEM_FW_BIOS_PLATFORM_KEY MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdBiosPlatformKey)
82 #define MBP_ITEM_CSE_PLATFORM_TYPE MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdCsePlatformType)
83 #define MBP_ITEM_UNCONFIG_ON_RTC MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdUnconfigOnRtc)
84 #define MBP_ITEM_SHIP_STATE MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdShipState)
85 #define MBP_ITEM_ID_FW_ARB_SVN MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdFwArbSvn)
86 #define MBP_ITEM_ID_MEASURED_BOOT MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdMeasuredBoot)
87 #define MBP_ITEM_PERF_DATA_EX MBP_ITEM_ID(MbpAppIdKernel, MbpItemIdPerfDataEx)
88 #define MBP_ITEM_ID_PSR MBP_ITEM_ID(MbpAppIdPsr, MbpItemIdPsr)
89 #define MBP_ITEM_HWA_MTU MBP_ITEM_ID(MbpAppIdHwa, MbpItemIdHwaMtu)
90 #define MBP_ITEM_CHIPSET_INIT_VER MBP_ITEM_ID(MbpAppIdIcc, MbpItemIdMphyData)
91 #define MBP_ITEM_OEM_PHY_DATA MBP_ITEM_ID(MbpAppIdIcc, MbpItemIdOemPhyData)
92
93 //
94 // Enum for AppId
95 //
96 typedef enum {
97 MbpAppIdKernel = 1,
98 MbpAppIdPsr = 2,
99 MbpAppIdHwa = 4,
100 MbpAppIdIcc = 5,
101 MbpAppIdDnx = 7
102 } MBP_APPLICATION_ID;
103
104 //
105 // Enums for ItemIds
106 //
107 typedef enum {
108 MbpItemIdFwVerName = 1,
109 MbpItemIdFwCapabilities = 2,
110 MbpItemIdBiosPlatformKey = 4,
111 MbpItemIdCsePlatformType = 5,
112 MbpItemIdUnconfigOnRtc = 8,
113 MbpItemIdShipState = 9,
114 MbpItemIdPerfDataEx = 13,
115 MbpItemIdFwArbSvn = 14,
116 MbpItemIdMeasuredBoot = 15
117 } MBP_KERNEL_ITEM_ID;
118
119 typedef enum {
120 MbpItemIdPsr = 1,
121 } MBP_PSR_ITEM_ID;
122
123 typedef enum {
124 MbpItemIdHwaMtu = 1
125 } MBP_HWA_ITEM_ID;
126
127 typedef enum {
128 MbpItemIdMphyData = 3,
129 MbpItemIdOemPhyData = 4
130 } MBP_ICC_ITEM_ID;
131
132 //
133 // Enum for Flags
134 //
135 typedef enum {
136 MbpItemFlagStoreToNvm = 0, ///< Item contains data to be stored in flash
137 MbpItemFlagSensitive = 1, ///< Item contains sensitive data. Do not store in flash.
138 MbpItemFlagRuntime = 2, ///< Item is generated at runtime. Do not store in flash.
139 } MBP_ITEM_FLAGS;
140
141 ///
142 /// MBP items
143 ///
144
145 ///
146 /// Kernel AppId
147 ///
148 typedef struct {
149 UINT32 MajorVersion : 16;
150 UINT32 MinorVersion : 16;
151 UINT32 HotfixVersion : 16;
152 UINT32 BuildVersion : 16;
153 } MBP_FW_VERSION_NAME;
154
155 typedef struct {
156 MEFWCAPS_SKU FwCapabilities;
157 BOOLEAN Available;
158 UINT8 Reserved[3];
159 } MBP_FW_CAPS_SKU;
160
161 typedef struct {
162 UINT32 Key[8];
163 } MBP_PLATFORM_KEY;
164
165 typedef struct {
166 PLATFORM_TYPE_RULE_DATA RuleData;
167 BOOLEAN Available;
168 UINT8 Reserved[3];
169 } MBP_PLAT_TYPE;
170
171 typedef struct {
172 UINT32 DisUnconfigOnRtcClearState : 1;
173 UINT32 Reserved : 31;
174 } MBP_ME_UNCONF_ON_RTC_DATA;
175
176 typedef struct {
177 MBP_ME_UNCONF_ON_RTC_DATA UnconfigOnRtcClearData;
178 BOOLEAN Available;
179 UINT8 Reserved[3];
180 } MBP_ME_UNCONF_ON_RTC_STATE;
181
182 typedef struct {
183 MEFWCAPS_SKU FwFeatures;
184 BOOLEAN Available;
185 UINT8 Reserved[3];
186 } MBP_FW_FEATURES_STATE;
187
188 typedef struct {
189 /*
190 ARB SVN flags:
191 BIT[0]: set if ARB SVN mismatch is found for any of ARB SVN components.
192 BIT[1..6]: Reserved, should be 0
193 BIT[7]: set if ARB_SVN exceeds 1 byte size
194 */
195 UINT8 Flags;
196 UINT8 MinCseArbSvn; ///< Minimal CSE ARB SVN.
197 UINT8 CurrCseArbSvn; ///< Current CSE ARB SVN.
198 UINT8 Reserved; ///< Reserved, should be 0.
199 } MBP_ARB_SVN_DATA;
200
201 typedef struct {
202 MBP_ARB_SVN_DATA ArbSvnData;
203 BOOLEAN Available;
204 UINT8 Reserved[3];
205 } MBP_ARB_SVN_STATE;
206
207 ///
208 /// MBP IFWI DNX request structure containing IFWI Dnx request data
209 ///
210 typedef struct {
211 UINT32 EnterRecovery;
212 BOOLEAN Available;
213 UINT8 Reserved[3];
214 } MBP_IFWI_DNX_REQUEST;
215
216 typedef struct {
217 UINT32 MeasuredBoot : 1;
218 UINT32 Reserved : 31;
219 } MBP_MEASURED_BOOT_DATA;
220
221 typedef struct {
222 MBP_MEASURED_BOOT_DATA MeasuredBootData;
223 BOOLEAN Available;
224 UINT8 Reserved[3];
225 } MBP_MEASURED_BOOT_SUPPORT;
226
227 typedef struct {
228 UINT32 TimeStamp0;
229 UINT16 TimeStamp1;
230 UINT16 TimeStamp2;
231 UINT16 TimeStamp3;
232 UINT16 TimeStamp4;
233 UINT16 TimeStamp5;
234 UINT16 TimeStamp6;
235 } MBP_PERF_DATA;
236
237 typedef struct {
238 MBP_PERF_DATA Data;
239 BOOLEAN Available;
240 UINT8 Reserved[3];
241 } MBP_PERF_DATA_EX;
242
243 ///
244 /// HWA AppId
245 ///
246 typedef union {
247 UINT32 Raw;
248 struct {
249 UINT32 MediaTablePush : 1;
250 UINT32 Reserved : 31;
251 } Fields;
252 } HWA_DATA;
253
254 typedef struct {
255 HWA_DATA Data;
256 BOOLEAN Available;
257 UINT8 Reserved[3];
258 } MBP_HWA_REQ;
259
260 ///
261 /// ICC AppId
262 ///
263 typedef struct {
264 UINT32 ChipsetInitVer[3];
265 BOOLEAN Available;
266 UINT8 Reserved[3];
267 } MBP_MPHY_DATA;
268
269 typedef struct {
270 UINT64 Data;
271 BOOLEAN Available;
272 UINT8 Reserved[3];
273 } MBP_OEM_PHY_DATA;
274
275 typedef struct {
276 UINT32 ChassisIntrusionEvent : 1; ///< Indicator to send the event from BIOS to CSME
277 UINT32 Reserved : 31; ///< Reserved for future usages. Should be 0.
278 } CHASSIS_PSR_DATA;
279
280 typedef struct {
281 CHASSIS_PSR_DATA PsrData;
282 BOOLEAN Available;
283 UINT8 Reserved[3];
284 } MBP_PSR;
285
286 ///
287 /// ME BIOS Payload structure containing insensitive data only
288 ///
289 typedef struct {
290 MBP_FW_VERSION_NAME FwVersionName;
291 MBP_FW_CAPS_SKU FwCapsSku;
292 MBP_FW_FEATURES_STATE FwFeaturesState;
293 MBP_PLAT_TYPE FwPlatType;
294 MBP_HWA_REQ HwaRequest;
295 MBP_ME_UNCONF_ON_RTC_STATE UnconfigOnRtcClearState;
296 MBP_ARB_SVN_STATE ArbSvnState;
297 MBP_MPHY_DATA MphyData;
298 MBP_IFWI_DNX_REQUEST IfwiDnxRequest;
299 UINT32 Reserved;
300 MBP_MEASURED_BOOT_SUPPORT MeasuredBootSupport;
301 MBP_PERF_DATA_EX PerfDataEx;
302 MBP_OEM_PHY_DATA OemPhyData;
303 MBP_PSR Psr;
304 } ME_BIOS_PAYLOAD;
305
306 ///
307 /// All items which can't be available when 3rd part OPROMs/drivers are loaded
308 /// must be added to below structure only
309 ///
310 typedef struct {
311 MBP_PLATFORM_KEY PlatformKey;
312 } ME_BIOS_PAYLOAD_SENSITIVE;
313
314 #pragma pack ()
315
316 #endif
MBP_ITEM_HEADER::Flags
UINT32 Flags
Byte 3 - Flags.
Definition: MeBiosPayloadData.h:70
MBP_HEADER::Reserved
UINT16 Reserved
Byte [3:2] - Reserved.
Definition: MeBiosPayloadData.h:58
MBP_ITEM_HEADER
MBP items header.
Definition: MeBiosPayloadData.h:64
ME_BIOS_PAYLOAD_SENSITIVE
All items which can't be available when 3rd part OPROMs/drivers are loaded must be added to below str...
Definition: MeBiosPayloadData.h:310
MBP_ITEM_HEADER::Length
UINT32 Length
Byte 2 - Length in DW.
Definition: MeBiosPayloadData.h:69
MbpItemFlagSensitive
@ MbpItemFlagSensitive
Item contains sensitive data. Do not store in flash.
Definition: MeBiosPayloadData.h:137
ME_BIOS_PAYLOAD
ME BIOS Payload structure containing insensitive data only.
Definition: MeBiosPayloadData.h:289
MBP_MPHY_DATA
ICC AppId.
Definition: MeBiosPayloadData.h:263
MbpItemFlagStoreToNvm
@ MbpItemFlagStoreToNvm
Item contains data to be stored in flash.
Definition: MeBiosPayloadData.h:136
CoreBiosMsg.h
Core BIOS Messages.
MBP_HEADER::MbpSize
UINT8 MbpSize
Byte 0 - MBP Size in DW including Header.
Definition: MeBiosPayloadData.h:56
HWA_DATA
HWA AppId.
Definition: MeBiosPayloadData.h:246
MbpItemFlagRuntime
@ MbpItemFlagRuntime
Item is generated at runtime. Do not store in flash.
Definition: MeBiosPayloadData.h:138
MBP_ITEM_HEADER::AppId
UINT32 AppId
Byte 0 - Application ID.
Definition: MeBiosPayloadData.h:67
MBP_IFWI_DNX_REQUEST
MBP IFWI DNX request structure containing IFWI Dnx request data.
Definition: MeBiosPayloadData.h:210
MBP_HEADER::NumEntries
UINT8 NumEntries
Byte 1 - Number of Entries (Data Items) in MBP.
Definition: MeBiosPayloadData.h:57
MBP_HEADER
Common MBP types.
Definition: MeBiosPayloadData.h:55
MBP_ITEM_HEADER::ItemId
UINT32 ItemId
Byte 1 - Item ID.
Definition: MeBiosPayloadData.h:68
MBP_FW_VERSION_NAME
MBP items.
Definition: MeBiosPayloadData.h:148
MEFWCAPS_SKU
Get Firmware Capability.
Definition: MkhiMsgs.h:404
MBP_ITEM_FLAGS
MBP_ITEM_FLAGS
Definition: MeBiosPayloadData.h:135
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeBiosPayloadHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeBiosPayloadHob.h File Reference

This file contains definitions of ME BIOS Payload HOB. More...

#include <MeBiosPayloadData.h>
#include <MeDataHob.h>
Include dependency graph for MeBiosPayloadHob.h:

Go to the source code of this file.

Detailed Description

This file contains definitions of ME BIOS Payload HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeBiosPayloadHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeBiosPayloadHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeBiosPayloadHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of ME BIOS Payload HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_BIOS_PAYLOAD_HOB_H_
36 #define _ME_BIOS_PAYLOAD_HOB_H_
37
38 #include <MeBiosPayloadData.h>
39 #include <MeDataHob.h>
40
41 typedef struct {
42 EFI_HOB_GUID_TYPE Header;
43 UINT8 Revision;
44 UINT8 Reserved[3];
45 ME_BIOS_PAYLOAD MeBiosPayload;
46 } ME_BIOS_PAYLOAD_HOB;
47
48 extern EFI_GUID gMeBiosPayloadHobGuid;
49
50 #endif // _ME_BIOS_PAYLOAD_HOB_H_
MeDataHob.h
The GUID definition for MeDataHob.
ME_BIOS_PAYLOAD
ME BIOS Payload structure containing insensitive data only.
Definition: MeBiosPayloadData.h:289
MeBiosPayloadData.h
Interface definition details for MBP.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxConfigProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
MebxConfigProtocol.h File Reference

MebxConfigProtocol definitions. More...

Go to the source code of this file.

Classes

struct _MEBX_CONFIG_PROTOCOL
AMT Mebx Config Protocol The interface function is to set/get MEBX settings. More...

Macros

#define MEBX_CONFIG_PROTOCOL_REVISION 1
Mebx Config Protocol The interface function is to set/get MEBX settings.

Typedefs

typedef EFI_STATUS(* | SET_MEBX_DATA) (IN UINTN DataSize, IN VOID *Data)
This function is used to set MEBx settings. More...
typedef EFI_STATUS(* | GET_MEBX_DATA) (IN OUT UINTN *DataSize, OUT VOID *Data)
This function is used to retrieve MEBx settings. More...

Detailed Description

MebxConfigProtocol definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MebxConfigProtocol.h.

Typedef Documentation

◆ GET_MEBX_DATA

typedef EFI_STATUS( * GET_MEBX_DATA) (IN OUT UINTN *DataSize, OUT VOID *Data)

This function is used to retrieve MEBx settings.

Parameters
[in,out] | DataSize | The size in bytes of the MEBx data buffer.
[out] | Data | The pointer to MEBx configuration data buffer.
Return values
EFI_SUCCESS | MEBx config was successfully retrieved.
EFI_INVALID_PARAMETER | Parameter Data or Datasize is NULL.
EFI_DEVICE_ERROR | MEBx config could not be retrieved due to a hardware error.

Definition at line 74 of file MebxConfigProtocol.h.

◆ SET_MEBX_DATA

typedef EFI_STATUS( * SET_MEBX_DATA) (IN UINTN DataSize, IN VOID *Data)

This function is used to set MEBx settings.

Parameters
[in] | DataSize | The size in bytes of the MEBx Data buffer.
[in] | Data | The contents for the MEBx Data.
Return values
EFI_SUCCESS | MEBx config saved.
EFI_OUT_OF_RESOURCES | Not enough storage is available to hold MEBx data.
EFI_DEVICE_ERROR | MEBx config could not be retrieved due to a hardware error.

Definition at line 57 of file MebxConfigProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxConfigProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MebxConfigProtocol.h
Go to the documentation of this file.
1 /** @file
2 MebxConfigProtocol definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEBX_CONFIG_PROTOCOL_H_
36 #define _MEBX_CONFIG_PROTOCOL_H_
37
38 ///
39 /// Mebx Config Protocol
40 /// The interface function is to set/get MEBX settings.
41 ///
42
43 #define MEBX_CONFIG_PROTOCOL_REVISION 1
44 typedef struct _MEBX_CONFIG_PROTOCOL MEBX_CONFIG_PROTOCOL;
45
46 /**
47 This function is used to set MEBx settings.
48
49 @param[in] DataSize The size in bytes of the MEBx Data buffer.
50 @param[in] Data The contents for the MEBx Data.
51
52 @retval EFI_SUCCESS MEBx config saved.
53 @retval EFI_OUT_OF_RESOURCES Not enough storage is available to hold MEBx data.
54 @retval EFI_DEVICE_ERROR MEBx config could not be retrieved due to a hardware error.
55 **/
56 typedef
57 EFI_STATUS
58 (EFIAPI *SET_MEBX_DATA) (
59 IN UINTN DataSize,
60 IN VOID *Data
61 );
62
63 /**
64 This function is used to retrieve MEBx settings.
65
66 @param[in,out] DataSize The size in bytes of the MEBx data buffer.
67 @param[out] Data The pointer to MEBx configuration data buffer.
68
69 @retval EFI_SUCCESS MEBx config was successfully retrieved.
70 @retval EFI_INVALID_PARAMETER Parameter Data or Datasize is NULL.
71 @retval EFI_DEVICE_ERROR MEBx config could not be retrieved due to a hardware error.
72 **/
73 typedef
74 EFI_STATUS
75 (EFIAPI *GET_MEBX_DATA) (
76 IN OUT UINTN *DataSize,
77 OUT VOID *Data
78 );
79
80 /**
81 AMT Mebx Config Protocol
82 The interface function is to set/get MEBX settings.
83 It is platform vendor's responsibility to implement the function instances.
84
85 <b>Revision 1:</b>
86 - Initial version.
87
88 **/
89 struct _MEBX_CONFIG_PROTOCOL {
90 UINT8 Revision;
91 SET_MEBX_DATA SetMebxConfig;
92 GET_MEBX_DATA GetMebxConfig;
93 };
94
95 extern EFI_GUID gMebxConfigProtocolGuid;
96
97 #endif // _MEBX_CONFIG_PROTOCOL_H_
SET_MEBX_DATA
EFI_STATUS(* SET_MEBX_DATA)(IN UINTN DataSize, IN VOID *Data)
This function is used to set MEBx settings.
Definition: MebxConfigProtocol.h:58
_MEBX_CONFIG_PROTOCOL
AMT Mebx Config Protocol The interface function is to set/get MEBX settings.
Definition: MebxConfigProtocol.h:89
GET_MEBX_DATA
EFI_STATUS(* GET_MEBX_DATA)(IN OUT UINTN *DataSize, OUT VOID *Data)
This function is used to retrieve MEBx settings.
Definition: MebxConfigProtocol.h:75
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxData.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MebxData.h File Reference

MEBx setup data definitions. More...

Go to the source code of this file.

Detailed Description

MEBx setup data definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MebxData.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxData.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MebxData.h
Go to the documentation of this file.
1 /** @file
2 MEBx setup data definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEBX_DATA_H_
36 #define _MEBX_DATA_H_
37
38 #pragma pack(1)
39
40 typedef struct {
41 UINT8 AmtSol; ///< Serial Over Lan State. 0: Disabled; 1: Enabled
42 UINT8 AmtSrou; ///< Storage Redirection Over USB-R State. 0: Disabled; 1: Enabled
43 UINT8 Reserved[2]; ///< Reserved for future use
44 } MEBX_DATA;
45
46 #pragma pack()
47
48 #endif // _MEBX_DATA_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxDisplayProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs | Enumerations
MebxDisplayProtocol.h File Reference

MEBx Display Protocol definitions. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _MEBX_DISPLAY_PROTOCOL
MEBx Display Protocol The interface functions are used for I/O operations related to screen. More...

Typedefs

typedef struct _MEBX_DISPLAY_PROTOCOL | MEBX_DISPLAY_PROTOCOL
MEBx Display Protocol. More...
typedef EFI_STATUS(* | MEBX_DISPLAY_TEXT) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId)
This function prints MEBx information string to screen. More...
typedef EFI_STATUS(* | MEBX_DISPLAY_ERROR) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId, IN UINT32 Delay)
This function prints MEBx error string to screen and to console. More...
typedef EFI_STATUS(* | MEBX_DISPLAY_IMAGE) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN UINT8 *Bitmap, IN UINT32 ImageWidth, IN UINT32 ImageHeight)
This function draws image on the graphics screen. More...
typedef EFI_STATUS(* | MEBX_CONFIGURE_SCREEN) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN SCREEN_MODE Mode)
This function sets specified graphics mode. More...
typedef EFI_STATUS(* | MEBX_GET_USER_INPUT) (IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT MEBX_USER_INPUT *UserInput)
This function reads user input. More...
typedef EFI_STATUS(* | MEBX_GET_SCREEN_RESOLUTION) (IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT UINT16 *Width, OUT UINT16 *Height)
This function gets information about current screen resolution. More...
typedef EFI_STATUS(* | MEBX_CLEAR_SCREEN) (IN OUT MEBX_DISPLAY_PROTOCOL *This)
This function clears a screen's content. More...

Enumerations

enum MEBX_MSG_ID
MEBx Message ID.

Detailed Description

MEBx Display Protocol definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MebxDisplayProtocol.h.

Typedef Documentation

◆ MEBX_CLEAR_SCREEN

typedef EFI_STATUS( * MEBX_CLEAR_SCREEN) (IN OUT MEBX_DISPLAY_PROTOCOL *This)

This function clears a screen's content.

Parameters
[in,out] This Pointer to MEBx Display Protocol
Return values
EFI_SUCCESS | The function succeeded
Others | Error has occurred

Definition at line 302 of file MebxDisplayProtocol.h.

◆ MEBX_CONFIGURE_SCREEN

typedef EFI_STATUS( * MEBX_CONFIGURE_SCREEN) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN SCREEN_MODE Mode)

This function sets specified graphics mode.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol
[in] | Mode | Graphics mode to set
Return values
EFI_SUCCESS | New graphics mode set successfully
Others | Error has occurred

Definition at line 252 of file MebxDisplayProtocol.h.

◆ MEBX_DISPLAY_ERROR

typedef EFI_STATUS( * MEBX_DISPLAY_ERROR) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId, IN UINT32 Delay)

This function prints MEBx error string to screen and to console.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol.
[in] | MsgId | The identifier of message.
[in] | Delay | The amount of time for which the text will be displayed in microseconds. If value is 0, the text is displayed in a fixed microseconds.
Return values
EFI_SUCCESS | Text was displayed successfully.
EFI_NOT_FOUND | The string specified by MsgId wasn't found.

Definition at line 215 of file MebxDisplayProtocol.h.

◆ MEBX_DISPLAY_IMAGE

typedef EFI_STATUS( * MEBX_DISPLAY_IMAGE) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN UINT8 *Bitmap, IN UINT32 ImageWidth, IN UINT32 ImageHeight)

This function draws image on the graphics screen.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol
[in] | Bitmap | The data to transfer to the graphics screen
[in] | ImageWidth | The width of image
[in] | ImageHeight | The height of image
Return values
EFI_SUCCESS | Image was displayed successfully
EFI_INVALID_PARAMETER | Invalid parameter

Definition at line 234 of file MebxDisplayProtocol.h.

◆ MEBX_DISPLAY_PROTOCOL

typedef struct _MEBX_DISPLAY_PROTOCOL MEBX_DISPLAY_PROTOCOL

MEBx Display Protocol.

MEBx Display Protocol The interface functions are used for I/O operations related to screen.

It is platform vendor's responsibility to implement the function instance.

Definition at line 1 of file MebxDisplayProtocol.h.

◆ MEBX_DISPLAY_TEXT

typedef EFI_STATUS( * MEBX_DISPLAY_TEXT) (IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId)

This function prints MEBx information string to screen.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol
[in] | MsgId | Message id
Return values
EFI_SUCCESS | Text was displayed successfully
Others | Error has occurred during displaying text

Definition at line 197 of file MebxDisplayProtocol.h.

◆ MEBX_GET_SCREEN_RESOLUTION

typedef EFI_STATUS( * MEBX_GET_SCREEN_RESOLUTION) (IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT UINT16 *Width, OUT UINT16 *Height)

This function gets information about current screen resolution.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol
[out] | Width | Current screen width
[out] | Height | Current screen height
Return values
EFI_SUCCESS | The function succeeded
Others | Error has occurred

Definition at line 286 of file MebxDisplayProtocol.h.

◆ MEBX_GET_USER_INPUT

typedef EFI_STATUS( * MEBX_GET_USER_INPUT) (IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT MEBX_USER_INPUT *UserInput)

This function reads user input.

Parameters
[in,out] | This | Pointer to MEBx Display Protocol
[out] | UserInput | User input
Return values
EFI_SUCCESS | Successfully read user input
EFI_NOT_READY | There was no input from an user.
Others | Error has occurred

Definition at line 269 of file MebxDisplayProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxDisplayProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MebxDisplayProtocol.h
Go to the documentation of this file.
1 /** @file
2 MEBx Display Protocol definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEBX_DISPLAY_PROTOCOL_H_
36 #define _MEBX_DISPLAY_PROTOCOL_H_
37
38
39 ///
40 /// MEBx Display Protocol
41 ///
42
43 typedef struct _MEBX_DISPLAY_PROTOCOL MEBX_DISPLAY_PROTOCOL;
44
45 typedef enum {
46 ScreenModeMebx,
47 ScreenModeBios
48 } SCREEN_MODE;
49
50 typedef enum {
51 MebxUserInputNoInput,
52 MebxUserInputEsc,
53 MebxUserInputEnter,
54 MebxUserInputOtherKey
55 } MEBX_USER_INPUT;
56
57 ///
58 /// MEBx Message ID
59 ///
60 typedef enum {
61 RecordInvalidError,
62 LoginFailedError,
63 ProvDataMissingError,
64 FailedEnabledFeaturesError,
65 FailedUpdateManageabilityModeError,
66 AppFailedLoadError,
67 FwUpdateError,
68 FwUpdateDeprecatedError,
69 FailedGetProvStatusError,
70 PkiDnsSuffixInvalidError,
71 PkiDnsSuffixError,
72 ConfigServerFqdnInvalidError,
73 RemoteConfigEnDisInvalidError,
74 RemoteConfigEnDisError,
75 DefaultHashEnInvalidError,
76 DefaultHashEnError,
77 DefaultHashDisError,
78 CustomHashConfigInvalidError,
79 CustomHashConfigError,
80 DeleteHashError,
81 CustomHashStateError,
82 InvalidCustomHashError,
83 SolStorageRedirConfigInvalidError,
84 SolStorageRedirDataError,
85 SolStorageRedirAuthProtError,
86 HostNameLargeError,
87 DomainNameLargeError,
88 DhcpInvalidError,
89 IdleTimeoutInvalidError,
90 IdleTimeoutError,
91 ProvServerInvalidError,
92 ProvServerPortInvalidError,
93 Ipv4ParamsInvalidError,
94 PwdPolicyInvalidError,
95 Ipv6DataInvalidError,
96 Ipv6SettingError,
97 SharedFqdnInvalidError,
98 DdnsInvalidError,
99 KvmStateInvalidError,
100 KvmStateError,
101 OptInDataInvalidError,
102 MeProvHaltDataInvalidError,
103 MeProvHaltError,
104 ManualSetupConfDataInvalidError,
105 ProvServAddressError,
106 HashHandlesError,
107 HashEntriesError,
108 AddCustomHashError,
109 MeProvActivateError,
110 Ipv4ParametersError,
111 FqdnSettingError,
112 OptinDataError,
113 CompleteConfigFailedError,
114 NewPasswordError,
115 PowerPackagesError,
116 ConinError,
117 AmthiGetAmthiInterfaceVersionApiError,
118 AmthiGetKvmStateApiError,
119 AmthiGetPolicyAmtRedirectionStateApiError,
120 AmthiGetOptinStateApiError,
121 AmthiGetConfigSvrDataApiError,
122 AmthiGetZtcConfigApiError,
123 AmthiGetPkiFqdnSuffixApiError,
124 AmthiGetIpv4ParamsApiError,
125 AmthiGetFqdnApiError,
126 AmthiGetIdleTimeoutApiError,
127 AmthiGetProvisionStateApiError,
128 AmthiGetAuditRecordApiError,
129 AmthiGetHashDataApiError,
130 AmthiGetConnectionStatusApiError,
131 AmthiGetIpv6LanIntfSettingsApiError,
132 AmthiGetPrivacyLevelApiError,
133 AmthiGetPowerPolicyApiError,
134 AmthiSetMebxEnterStateApiError,
135 AmthiSetMebxExitStateApiError,
136 KvmActiveSessionMsg,
137 AmthiSetIpv4ParamsApiError,
138 AmthiSetPkiFqdnSuffixApiError,
139 AmthiSetSolStorageRedirectionStateApiError,
140 AmthiSetKvmStateApiError,
141 AmthiSetPwdPolicyApiError,
142 AmthiSetFqdnApiError,
143 AmthiSetOptinStateApiError,
144 AmthiSetIdleTimeoutApiError,
145 AmthiSetConfigServerApiError,
146 AmthiPowerPolicyApiError,
147 AmthiSetHashStateApiError,
148 AmthiSetZtcApiError,
149 AmthiStopConfigUnprovisionApiError,
150 MeGetUserCapsApiError,
151 MeGetFwCapsApiError,
152 MeGetFwEnabledFeatureApiError,
153 MeMeWaitFwFeatureAvailableApiError,
154 MeGetMoffOvrdStateApiError,
155 MeGetSouthClinkStateApiError,
156 MeSetAmtStateApiError,
157 CoreUnconfigWoPassGetUnconfigStatusError,
158 CoreUsbProvError,
159 MeSetMoffOvrdStateApiError,
160 MeSetSouthClinkStateApiError,
161 AmthiCloseUserInitiatedConnApiError,
162 PressAnyKeyMsg,
163 FoundUsbKeyMsg,
164 ContinueAutoProvMsg,
165 LoadingAmtMsg,
166 DoneMsg,
167 AmtManageabilityUsbDataMissingMsg,
168 AmtManageabilityAlreadyProvMsg,
169 StringNotAppliedTooManyHashesMsg,
170 ConfigAppliedMsg,
171 ContinueBootMsg,
172 CoreCautionMsg,
173 CoreCpuReplacementMsg,
174 CoreFeaturesDisabledMsg,
175 CoreFeaturesEnabledMsg,
176 CoreConfirm1Msg,
177 CoreConfirm2Msg,
178 AmtManageabilityCilaMsg,
179 CoreUnconfigWoPassMsg,
180 AmtManualConfigUnsupportedMsg,
181
182 // Values from 0x80000 to 0x8FFFF are reserved for USB Provisioning record display
183 CorruptedDataEntryStart = 0x80000,
184 CorruptedDataEntryEnd = 0x8FFFF
185 } MEBX_MSG_ID;
186
187 /**
188 This function prints MEBx information string to screen.
189
190 @param[in,out] This Pointer to MEBx Display Protocol
191 @param[in] MsgId Message id
192
193 @retval EFI_SUCCESS Text was displayed successfully
194 @retval Others Error has occurred during displaying text
195 **/
196 typedef
197 EFI_STATUS
198 (EFIAPI *MEBX_DISPLAY_TEXT) (
199 IN OUT MEBX_DISPLAY_PROTOCOL *This,
200 IN MEBX_MSG_ID MsgId
201 );
202
203 /**
204 This function prints MEBx error string to screen and to console.
205
206 @param[in,out] This Pointer to MEBx Display Protocol.
207 @param[in] MsgId The identifier of message.
208 @param[in] Delay The amount of time for which the text will be displayed in microseconds.
209 If value is 0, the text is displayed in a fixed microseconds.
210
211 @retval EFI_SUCCESS Text was displayed successfully.
212 @retval EFI_NOT_FOUND The string specified by MsgId wasn't found.
213 **/
214 typedef
215 EFI_STATUS
216 (EFIAPI *MEBX_DISPLAY_ERROR) (
217 IN OUT MEBX_DISPLAY_PROTOCOL *This,
218 IN MEBX_MSG_ID MsgId,
219 IN UINT32 Delay
220 );
221
222 /**
223 This function draws image on the graphics screen.
224
225 @param[in,out] This Pointer to MEBx Display Protocol
226 @param[in] Bitmap The data to transfer to the graphics screen
227 @param[in] ImageWidth The width of image
228 @param[in] ImageHeight The height of image
229
230 @retval EFI_SUCCESS Image was displayed successfully
231 @retval EFI_INVALID_PARAMETER Invalid parameter
232 **/
233 typedef
234 EFI_STATUS
235 (EFIAPI *MEBX_DISPLAY_IMAGE) (
236 IN OUT MEBX_DISPLAY_PROTOCOL *This,
237 IN UINT8 *Bitmap,
238 IN UINT32 ImageWidth,
239 IN UINT32 ImageHeight
240 );
241
242 /**
243 This function sets specified graphics mode.
244
245 @param[in,out] This Pointer to MEBx Display Protocol
246 @param[in] Mode Graphics mode to set
247
248 @retval EFI_SUCCESS New graphics mode set successfully
249 @retval Others Error has occurred
250 **/
251 typedef
252 EFI_STATUS
253 (EFIAPI *MEBX_CONFIGURE_SCREEN) (
254 IN OUT MEBX_DISPLAY_PROTOCOL *This,
255 IN SCREEN_MODE Mode
256 );
257
258 /**
259 This function reads user input.
260
261 @param[in,out] This Pointer to MEBx Display Protocol
262 @param[out] UserInput User input
263
264 @retval EFI_SUCCESS Successfully read user input
265 @retval EFI_NOT_READY There was no input from an user.
266 @retval Others Error has occurred
267 **/
268 typedef
269 EFI_STATUS
270 (EFIAPI *MEBX_GET_USER_INPUT) (
271 IN OUT MEBX_DISPLAY_PROTOCOL *This,
272 OUT MEBX_USER_INPUT *UserInput
273 );
274
275 /**
276 This function gets information about current screen resolution.
277
278 @param[in,out] This Pointer to MEBx Display Protocol
279 @param[out] Width Current screen width
280 @param[out] Height Current screen height
281
282 @retval EFI_SUCCESS The function succeeded
283 @retval Others Error has occurred
284 **/
285 typedef
286 EFI_STATUS
287 (EFIAPI *MEBX_GET_SCREEN_RESOLUTION) (
288 IN OUT MEBX_DISPLAY_PROTOCOL *This,
289 OUT UINT16 *Width,
290 OUT UINT16 *Height
291 );
292
293 /**
294 This function clears a screen's content.
295
296 @param[in,out] This Pointer to MEBx Display Protocol
297
298 @retval EFI_SUCCESS The function succeeded
299 @retval Others Error has occurred
300 **/
301 typedef
302 EFI_STATUS
303 (EFIAPI *MEBX_CLEAR_SCREEN) (
304 IN OUT MEBX_DISPLAY_PROTOCOL *This
305 );
306
307 /**
308 MEBx Display Protocol
309 The interface functions are used for I/O operations related to screen.
310 It is platform vendor's responsibility to implement the function instance.
311 **/
312 typedef struct _MEBX_DISPLAY_PROTOCOL {
313 MEBX_CONFIGURE_SCREEN ConfigureScreen;
314 MEBX_DISPLAY_TEXT DisplayText;
315 MEBX_DISPLAY_ERROR DisplayError;
316 MEBX_DISPLAY_IMAGE DisplayImage;
317 MEBX_GET_USER_INPUT GetUserInput;
318 MEBX_GET_SCREEN_RESOLUTION GetScreenResolution;
319 MEBX_CLEAR_SCREEN ClearScreen;
320 } MEBX_DISPLAY_PROTOCOL;
321
322 extern EFI_GUID gMebxDisplayProtocolGuid;
323
324 #endif // _MEBX_DISPLAY_PROTOCOL_H_
MEBX_CLEAR_SCREEN
EFI_STATUS(* MEBX_CLEAR_SCREEN)(IN OUT MEBX_DISPLAY_PROTOCOL *This)
This function clears a screen's content.
Definition: MebxDisplayProtocol.h:303
MEBX_CONFIGURE_SCREEN
EFI_STATUS(* MEBX_CONFIGURE_SCREEN)(IN OUT MEBX_DISPLAY_PROTOCOL *This, IN SCREEN_MODE Mode)
This function sets specified graphics mode.
Definition: MebxDisplayProtocol.h:253
MEBX_GET_SCREEN_RESOLUTION
EFI_STATUS(* MEBX_GET_SCREEN_RESOLUTION)(IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT UINT16 *Width, OUT UINT16 *Height)
This function gets information about current screen resolution.
Definition: MebxDisplayProtocol.h:287
MEBX_DISPLAY_PROTOCOL
struct _MEBX_DISPLAY_PROTOCOL MEBX_DISPLAY_PROTOCOL
MEBx Display Protocol.
Definition: MebxDisplayProtocol.h:43
MEBX_DISPLAY_ERROR
EFI_STATUS(* MEBX_DISPLAY_ERROR)(IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId, IN UINT32 Delay)
This function prints MEBx error string to screen and to console.
Definition: MebxDisplayProtocol.h:216
MEBX_DISPLAY_IMAGE
EFI_STATUS(* MEBX_DISPLAY_IMAGE)(IN OUT MEBX_DISPLAY_PROTOCOL *This, IN UINT8 *Bitmap, IN UINT32 ImageWidth, IN UINT32 ImageHeight)
This function draws image on the graphics screen.
Definition: MebxDisplayProtocol.h:235
MEBX_DISPLAY_TEXT
EFI_STATUS(* MEBX_DISPLAY_TEXT)(IN OUT MEBX_DISPLAY_PROTOCOL *This, IN MEBX_MSG_ID MsgId)
This function prints MEBx information string to screen.
Definition: MebxDisplayProtocol.h:198
_MEBX_DISPLAY_PROTOCOL
MEBx Display Protocol The interface functions are used for I/O operations related to screen.
Definition: MebxDisplayProtocol.h:312
MEBX_MSG_ID
MEBX_MSG_ID
MEBx Message ID.
Definition: MebxDisplayProtocol.h:60
MEBX_GET_USER_INPUT
EFI_STATUS(* MEBX_GET_USER_INPUT)(IN OUT MEBX_DISPLAY_PROTOCOL *This, OUT MEBX_USER_INPUT *UserInput)
This function reads user input.
Definition: MebxDisplayProtocol.h:270
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
MebxProtocol.h File Reference

EFI MEBx Protocol. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct MEBX_PROTOCOL
MEBX protocol The interface for invoking MEBX binary. More...

Typedefs

typedef EFI_STATUS(* MEBX_API_ENTRY_POINT) (IN MEBX_BPF *BiosParams, OUT MEBX_EXIT_CODE *MebxReturnValue)
Function for invoking MEBX binary. More...

Detailed Description

EFI MEBx Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MebxProtocol.h.

Typedef Documentation

◆ MEBX_API_ENTRY_POINT

typedef EFI_STATUS( * MEBX_API_ENTRY_POINT) (IN MEBX_BPF *BiosParams, OUT MEBX_EXIT_CODE *MebxReturnValue)

Function for invoking MEBX binary.

Parameters
[in] | BiosParams | MebxBiosParams flat data
[out] | MebxReturnValue | MebxExitCode returned by Mebx
Return values
EFI_SUCCESS Command succeeded

Definition at line 79 of file MebxProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MebxProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MebxProtocol.h
Go to the documentation of this file.
1 /** @file
2 EFI MEBx Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEBX_PROTOCOL_H
36 #define _MEBX_PROTOCOL_H
37
38 typedef struct {
39 UINT16 MebxNonUiTextMode : 4;
40 UINT16 MebxUiTextMode : 4;
41 UINT16 MebxGraphicsMode : 4;
42 UINT16 Rsvd : 4;
43 } MEBX_OEM_RESOLUTION_SETTINGS;
44
45 typedef struct {
46 UINT16 BpfVersion; ///< Bios Parameter Frame Version
47 UINT8 CpuReplacementTimeout; ///< Cpu Replacement Timeout
48 UINT8 ActiveRemoteAssistanceProcess; ///< Activate CIRA
49 UINT8 CiraTimeout; ///< CIRA Timeout
50 UINT16 OemFlags; ///< OEM specified AMT support options
51 UINT32 UsbProvisionData; ///< 32 bit flat pointer to USB Config Strcuture
52 MEBX_OEM_RESOLUTION_SETTINGS OemResolutionSettings; ///< OEM resolution settings
53 UINT8 MebxDefaultSol; ///< Informs if this is first BIOS Boot
54 } MEBX_BPF;
55
56 //
57 // Header is a legacy leftover from older MEBx versions.
58 // Currently MEBx ignores this header.
59 //
60 typedef struct {
61 UINT32 Reserved[4];
62 } USB_PROVISION_HEADER;
63
64 typedef struct {
65 UINT32 BiosCmd : 8;
66 UINT32 BiosCmdData : 8;
67 UINT32 MebxStatusCode : 16;
68 } MEBX_EXIT_CODE;
69
70 /**
71 Function for invoking MEBX binary
72
73 @param[in] BiosParams MebxBiosParams flat data
74 @param[out] MebxReturnValue MebxExitCode returned by Mebx
75
76 @retval EFI_SUCCESS Command succeeded
77 **/
78 typedef
79 EFI_STATUS
80 (EFIAPI *MEBX_API_ENTRY_POINT) (
81 IN MEBX_BPF *BiosParams,
82 OUT MEBX_EXIT_CODE *MebxReturnValue
83 );
84
85 typedef struct {
86 UINT16 Major;
87 UINT16 Minor;
88 UINT16 Hotfix;
89 UINT16 Build;
90 } MEBX_VER;
91
92 typedef enum {
93 MEBX_GRAPHICS_AUTO = 0,
94 MEBX_GRAPHICS_640X480,
95 MEBX_GRAPHICS_800X600,
96 MEBX_GRAPHICS_1024X768
97 } MEBX_GRAPHICS_MODE;
98
99 typedef enum {
100 MEBX_TEXT_AUTO = 0,
101 MEBX_TEXT_80X25,
102 MEBX_TEXT_100X31
103 } MEBX_TEXT_MODE;
104
105 /**
106 MEBX protocol
107 The interface for invoking MEBX binary
108 **/
109 typedef struct {
110 MEBX_VER MebxVersion;
111 MEBX_API_ENTRY_POINT CoreMebxEntry;
112 } MEBX_PROTOCOL;
113
114 extern EFI_GUID gMebxProtocolGuid;
115
116 #endif
MEBX_API_ENTRY_POINT
EFI_STATUS(* MEBX_API_ENTRY_POINT)(IN MEBX_BPF *BiosParams, OUT MEBX_EXIT_CODE *MebxReturnValue)
Function for invoking MEBX binary.
Definition: MebxProtocol.h:80
MEBX_PROTOCOL
MEBX protocol The interface for invoking MEBX binary.
Definition: MebxProtocol.h:109
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeChipsetLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
MeChipsetLib.h File Reference

Header file for Me Chipset Lib. More...

#include <Uefi.h>
#include <IndustryStandard/Pci22.h>
Include dependency graph for MeChipsetLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Enumerations

enum ME_DEVICE
CSME PCI devices should be numbered according to their PCI function number HECI1 = 0, HECI2 = 1, IDER = 2, SOL = 3, HECI3 = 4, HECI4 = 5.

Functions

BOOLEAN | IsHeciDeviceFunction (IN ME_DEVICE Function)
Checks if the given PCIe ME Device Function is HECI Device Function. More...
VOID | ClearD0I3Bit (IN UINT32 Function)
Put ME device out of D0I3. More...
VOID | SetD0I3Bit (IN UINT32 Function)
Put ME device into D0I3. More...
VOID | MeDeviceControl (IN ME_DEVICE WhichDevice, IN ME_DEVICE_FUNC_CTRL DeviceFuncCtrl)
Enable/Disable Me devices. More...
VOID | MeDeviceInit (IN ME_DEVICE WhichDevice, IN UINT32 MmioAddrL32, IN UINT32 MmioAddrH32)
Initialize Me devices. More...
VOID | MeSaveBars (IN ME_DEVICE WhichDevice, IN OUT UINT32 BarList[PCI_MAX_BAR])
Save HECI BARs. More...
VOID | MeRestoreBars (IN ME_DEVICE WhichDevice, IN UINT32 BarList[PCI_MAX_BAR])
Restore HECI BARs. More...
EFI_STATUS | HeciGetHerDataSha384 (IN UINT32 *Her, IN UINT32 HerOffset, IN UINT8 HerMaxRegCount)
This function gets sha384 CSME Measured data from HECI1 MMIO space (HECI1_HER1 - HECI1_HER12) More...

Detailed Description

Header file for Me Chipset Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeChipsetLib.h.

Function Documentation

◆ ClearD0I3Bit()

VOID ClearD0I3Bit ( IN UINT32 Function )

Put ME device out of D0I3.

Parameters
[in] Function ME function where D0I3 is to be changed

◆ HeciGetHerDataSha384()

EFI_STATUS HeciGetHerDataSha384 | ( | IN UINT32 * | Her,
 |  | IN UINT32 | HerOffset,
 |  | IN UINT8 | HerMaxRegCount
 | ) |  |

This function gets sha384 CSME Measured data from HECI1 MMIO space (HECI1_HER1 - HECI1_HER12)

Parameters
[in] | Her | - Pointer to receive HER Data buffer of 12 DWORDS
[in] | HerOffset | - Offset of first HER register in MMIO Space
[in] | HerMaxRegCount | - Max Register count to read HER registers
Return values
EFI_SUCCESS | Event data read successfully
EFI_INVALID_PARAMETER | Input parameters are not valid
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_NOT_READY | Device is not ready

◆ IsHeciDeviceFunction()

BOOLEAN IsHeciDeviceFunction ( IN ME_DEVICE Function )

Checks if the given PCIe ME Device Function is HECI Device Function.

Parameters
[in] Function ME Device Function
Return values
TRUE | This is a HECI Device Function
FALSE | This is not a HECI Device Function

◆ MeDeviceControl()

VOID MeDeviceControl | ( | IN ME_DEVICE | WhichDevice,
 |  | IN ME_DEVICE_FUNC_CTRL | DeviceFuncCtrl
 | ) |  |

Enable/Disable Me devices.

Parameters
[in] | WhichDevice | Select of Me device
[in] | DeviceFuncCtrl | Function control

◆ MeDeviceInit()

VOID MeDeviceInit | ( | IN ME_DEVICE | WhichDevice,
 |  | IN UINT32 | MmioAddrL32,
 |  | IN UINT32 | MmioAddrH32
 | ) |  |

Initialize Me devices.

Parameters
[in] | WhichDevice | Select of Me device
[in] | MmioAddrL32 | MMIO address for 32-bit low dword
[in] | MmioAddrH32 | MMIO address for 32-bit high dword

◆ MeRestoreBars()

VOID MeRestoreBars | ( | IN ME_DEVICE | WhichDevice,
 |  | IN UINT32 | BarList[PCI_MAX_BAR]
 | ) |  |

Restore HECI BARs.

Parameters
[in] | WhichDevice | Select of Me device
[in] | BarList | Buffer for BAR addresses to be restored

◆ MeSaveBars()

VOID MeSaveBars | ( | IN ME_DEVICE | WhichDevice,
 |  | IN OUT UINT32 | BarList[PCI_MAX_BAR]
 | ) |  |

Save HECI BARs.

Parameters
[in] | WhichDevice | Select of Me device
[in] | BarList | Buffer to store BAR addresses

◆ SetD0I3Bit()

VOID SetD0I3Bit ( IN UINT32 Function )

Put ME device into D0I3.

Parameters
[in] Function Select of Me device
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeChipsetLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeChipsetLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Me Chipset Lib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_CHIPSET_LIB_H_
36 #define _ME_CHIPSET_LIB_H_
37
38 #include <Uefi.h>
39 #include <IndustryStandard/Pci22.h>
40
41 ///
42 /// CSME PCI devices should be numbered according to their PCI function number
43 /// HECI1 = 0, HECI2 = 1, IDER = 2, SOL = 3, HECI3 = 4, HECI4 = 5
44 ///
45 typedef enum {
46 HECI1 = 0,
47 HECI2,
48 IDER,
49 SOL,
50 HECI3,
51 HECI4,
52 } ME_DEVICE;
53
54 typedef enum {
55 Disabled = 0,
56 Enabled,
57 } ME_DEVICE_FUNC_CTRL;
58
59 /**
60 Checks if the given PCIe ME Device Function is HECI Device Function
61
62 @param[in] Function ME Device Function
63
64 @retval TRUE This is a HECI Device Function
65 @retval FALSE This is not a HECI Device Function
66 **/
67 BOOLEAN
68 IsHeciDeviceFunction (
69 IN ME_DEVICE Function
70 );
71
72 /**
73 Put ME device out of D0I3
74
75 @param[in] Function ME function where D0I3 is to be changed
76
77 **/
78 VOID
79 ClearD0I3Bit (
80 IN UINT32 Function
81 );
82
83 /**
84 Put ME device into D0I3
85
86 @param[in] Function Select of Me device
87
88 **/
89 VOID
90 SetD0I3Bit (
91 IN UINT32 Function
92 );
93
94 /**
95 Enable/Disable Me devices
96
97 @param[in] WhichDevice Select of Me device
98 @param[in] DeviceFuncCtrl Function control
99
100 **/
101 VOID
102 MeDeviceControl (
103 IN ME_DEVICE WhichDevice,
104 IN ME_DEVICE_FUNC_CTRL DeviceFuncCtrl
105 );
106
107 /**
108 Initialize Me devices
109
110 @param[in] WhichDevice Select of Me device
111 @param[in] MmioAddrL32 MMIO address for 32-bit low dword
112 @param[in] MmioAddrH32 MMIO address for 32-bit high dword
113
114 **/
115 VOID
116 MeDeviceInit (
117 IN ME_DEVICE WhichDevice,
118 IN UINT32 MmioAddrL32,
119 IN UINT32 MmioAddrH32
120 );
121
122 /**
123 Save HECI BARs
124
125 @param[in] WhichDevice Select of Me device
126 @param[in] BarList Buffer to store BAR addresses
127
128 **/
129 VOID
130 MeSaveBars (
131 IN ME_DEVICE WhichDevice,
132 IN OUT UINT32 BarList[PCI_MAX_BAR]
133 );
134
135 /**
136 Restore HECI BARs
137
138 @param[in] WhichDevice Select of Me device
139 @param[in] BarList Buffer for BAR addresses to be restored
140
141 **/
142 VOID
143 MeRestoreBars (
144 IN ME_DEVICE WhichDevice,
145 IN UINT32 BarList[PCI_MAX_BAR]
146 );
147
148 /**
149 This function gets sha384 CSME Measured data from HECI1 MMIO space (HECI1_HER1 - HECI1_HER12)
150
151 @param[in] Her - Pointer to receive HER Data buffer of 12 DWORDS
152 @param[in] HerOffset - Offset of first HER register in MMIO Space
153 @param[in] HerMaxRegCount - Max Register count to read HER registers
154
155 @retval EFI_SUCCESS Event data read successfully
156 @retval EFI_INVALID_PARAMETER Input parameters are not valid
157 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
158 @retval EFI_NOT_READY Device is not ready
159 **/
160 EFI_STATUS
161 HeciGetHerDataSha384 (
162 IN UINT32 *Her,
163 IN UINT32 HerOffset,
164 IN UINT8 HerMaxRegCount
165 );
166
167 #endif
168
IsHeciDeviceFunction
BOOLEAN IsHeciDeviceFunction(IN ME_DEVICE Function)
Checks if the given PCIe ME Device Function is HECI Device Function.
MeDeviceControl
VOID MeDeviceControl(IN ME_DEVICE WhichDevice, IN ME_DEVICE_FUNC_CTRL DeviceFuncCtrl)
Enable/Disable Me devices.
MeDeviceInit
VOID MeDeviceInit(IN ME_DEVICE WhichDevice, IN UINT32 MmioAddrL32, IN UINT32 MmioAddrH32)
Initialize Me devices.
MeSaveBars
VOID MeSaveBars(IN ME_DEVICE WhichDevice, IN OUT UINT32 BarList[PCI_MAX_BAR])
Save HECI BARs.
SetD0I3Bit
VOID SetD0I3Bit(IN UINT32 Function)
Put ME device into D0I3.
ME_DEVICE
ME_DEVICE
CSME PCI devices should be numbered according to their PCI function number HECI1 = 0,...
Definition: MeChipsetLib.h:45
HeciGetHerDataSha384
EFI_STATUS HeciGetHerDataSha384(IN UINT32 *Her, IN UINT32 HerOffset, IN UINT8 HerMaxRegCount)
This function gets sha384 CSME Measured data from HECI1 MMIO space (HECI1_HER1 - HECI1_HER12)
ClearD0I3Bit
VOID ClearD0I3Bit(IN UINT32 Function)
Put ME device out of D0I3.
MeRestoreBars
VOID MeRestoreBars(IN ME_DEVICE WhichDevice, IN UINT32 BarList[PCI_MAX_BAR])
Restore HECI BARs.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeDataHob.h File Reference

The GUID definition for MeDataHob. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

The GUID definition for MeDataHob.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeDataHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeDataHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for MeDataHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ME_DATA_HOB_H_
37 #define _ME_DATA_HOB_H_
38
39 extern EFI_GUID gMeDataHobGuid;
40
41 typedef struct {
42 EFI_HOB_GUID_TYPE EfiHobGuidType;
43 UINT32 LocalityState;
44 } ME_DATA_HOB;
45
46 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDisabledEventHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeDisabledEventHob.h File Reference

This file contains definition of ME Disabled Event HOB. More...

Go to the source code of this file.

Detailed Description

This file contains definition of ME Disabled Event HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeDisabledEventHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDisabledEventHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeDisabledEventHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definition of ME Disabled Event HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ME_DISABLED_EVENT_HOB_H_
37 #define _ME_DISABLED_EVENT_HOB_H_
38
39 #define MAX_EVENTLOG_SIZE 1024
40 #define HER_REG_COUNT_SHA384 12
41
42 extern EFI_GUID gMeDisabledEventHobGuid;
43
44 typedef struct {
45 EFI_HOB_GUID_TYPE EfiHobGuidType;
46 UINT32 Her [HER_REG_COUNT_SHA384];
47 UINT32 Hers;
48 UINT32 Enh_Hers;
49 UINT8 Events [MAX_EVENTLOG_SIZE];
50 UINT32 EventLogSize;
51 BOOLEAN LogUnavailable;
52 } ME_DISABLED_EVENT_HOB;
53
54 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDxeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Classes | Typedefs | Enumerations
MeDxeConfig.h File Reference

ME config block for DXE phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct ME_DXE_CONFIG
ME Dxe Configuration Structure. More...

Typedefs

typedef VOID(* ME_REPORT_ERROR) (IN ME_ERROR_MSG_ID MsgId)
Show ME Error message. More...

Enumerations

enum ME_ERROR_MSG_ID
ME Error Message ID.

Detailed Description

ME config block for DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeDxeConfig.h.

Typedef Documentation

◆ ME_REPORT_ERROR

typedef VOID(* ME_REPORT_ERROR) (IN ME_ERROR_MSG_ID MsgId)

Show ME Error message.

This is to display localized message in the console. This is used to display message strings in local language. To display the message, the routine will check the message ID and ConOut the message strings. For example, the End of Post error displayed in English will be: gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of Post message to ME\n"); It is recommended to clear the screen before displaying the error message and keep the message on the screen for several seconds. A sample is provided, see ShowMeReportError () to retrieve details.

Parameters
[in] MsgId ME error message ID for displaying on screen message

Definition at line 82 of file MeDxeConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeDxeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
MeDxeConfig.h
Go to the documentation of this file.
1 /** @file
2 ME config block for DXE phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_DXE_CONFIG_H_
36 #define _ME_DXE_CONFIG_H_
37
38 #define ME_DXE_CONFIG_REVISION 1
39 extern EFI_GUID gMeDxeConfigGuid;
40
41 #ifndef PLATFORM_POR
42 #define PLATFORM_POR 0
43 #endif
44 #ifndef FORCE_ENABLE
45 #define FORCE_ENABLE 1
46 #endif
47 #ifndef FORCE_DISABLE
48 #define FORCE_DISABLE 2
49 #endif
50
51 ///
52 /// ME Error Message ID
53 ///
54 typedef enum {
55 MSG_EOP_ERROR = 0,
56 MSG_ME_FW_UPDATE_FAILED,
57 MSG_HMRFPO_LOCK_FAILURE,
58 MSG_HMRFPO_UNLOCK_FAILURE,
59 MSG_ME_FW_UPDATE_WAIT,
60 MSG_ILLEGAL_CPU_PLUGGED_IN,
61 MSG_PLAT_DISABLE_WAIT,
62 MAX_ME_ERROR_ENUM
63 } ME_ERROR_MSG_ID;
64
65 /**
66 Show ME Error message. This is to display localized message in
67 the console. This is used to display message strings in local
68 language. To display the message, the routine will check the
69 message ID and ConOut the message strings. For example, the
70 End of Post error displayed in English will be:
71 gST->ConOut->OutputString (gST->ConOut, L"Error sending End Of
72 Post message to ME\n"); It is recommended to clear the screen
73 before displaying the error message and keep the message on
74 the screen for several seconds.
75 A sample is provided, see ShowMeReportError () to retrieve
76 details.
77
78 @param[in] MsgId ME error message ID for displaying on screen message
79
80 **/
81 typedef
82 VOID
83 (*ME_REPORT_ERROR) (
84 IN ME_ERROR_MSG_ID MsgId
85 );
86
87 #pragma pack (push,1)
88
89 /**
90 ME Dxe Configuration Structure.
91
92 <b>Revision 1</b>:
93 - Initial version.
94 **/
95 typedef struct {
96 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
97 UINT32 MeFwDownGrade : 1; ///< <b>0: Disabled</b>; 1: Enabled - Enable/Disable ME FW downgrade
98 UINT32 MeJhiSupport : 1; ///< <b>0: Disabled</b>; 1: Enabled - Enable/Disable Intel DAL Host Interface Service.
99 UINT32 CoreBiosDoneEnabled : 1; ///< 0: Disabled; <b>1: Enabled</b> - Enable/Disable Sending notification that BIOS is starting to run 3rd party code
100 UINT32 ExtendMeMeasuredBoot : 1; ///< 0: Disabled; <b>1: Enabled</b> - Enable/Disable ME/CSME Extended Measurement to TPM-PCR
101 UINT32 RsvdBits : 28; ///< Reserved for future use & Config block alignment
102
103 /**
104 Function pointer for displaying error message on screen
105 **/
106 ME_REPORT_ERROR MeReportError;
107 } ME_DXE_CONFIG;
108 #pragma pack (pop)
109
110 #endif // _ME_DXE_CONFIG_H_
ME_DXE_CONFIG::MeReportError
ME_REPORT_ERROR MeReportError
Function pointer for displaying error message on screen.
Definition: MeDxeConfig.h:106
ME_DXE_CONFIG::MeFwDownGrade
UINT32 MeFwDownGrade
0: Disabled; 1: Enabled - Enable/Disable ME FW downgrade
Definition: MeDxeConfig.h:97
ME_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MeDxeConfig.h:96
ME_ERROR_MSG_ID
ME_ERROR_MSG_ID
ME Error Message ID.
Definition: MeDxeConfig.h:54
ME_DXE_CONFIG
ME Dxe Configuration Structure.
Definition: MeDxeConfig.h:95
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ME_DXE_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MeDxeConfig.h:101
ME_DXE_CONFIG::CoreBiosDoneEnabled
UINT32 CoreBiosDoneEnabled
0: Disabled; 1: Enabled - Enable/Disable Sending notification that BIOS is starting to run 3rd party ...
Definition: MeDxeConfig.h:99
ME_REPORT_ERROR
VOID(* ME_REPORT_ERROR)(IN ME_ERROR_MSG_ID MsgId)
Show ME Error message.
Definition: MeDxeConfig.h:83
ME_DXE_CONFIG::MeJhiSupport
UINT32 MeJhiSupport
0: Disabled; 1: Enabled - Enable/Disable Intel DAL Host Interface Service.
Definition: MeDxeConfig.h:98
ME_DXE_CONFIG::ExtendMeMeasuredBoot
UINT32 ExtendMeMeasuredBoot
0: Disabled; 1: Enabled - Enable/Disable ME/CSME Extended Measurement to TPM-PCR
Definition: MeDxeConfig.h:100
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeEwlLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
MeEwlLib.h File Reference

Header file for ME Error Warning Log Lib. More...

#include <Library/ReportStatusCodeLib.h>
Include dependency graph for MeEwlLib.h:

Go to the source code of this file.

Enumerations

enum ME_EWL_SEVERITY
EWL severities.

Functions

VOID | MeEwlStateFailures (IN UINT32 Severity, IN UINT8 MajorCheckpoint, IN UINT8 MinorCheckpoint, IN UINT8 MajorWarningCode, IN UINT8 MinorWarningCode)
Add to Enhanced Warning Log entry for ME State Failures. More...
VOID | MeEwlCommunicationFailures (IN UINT32 Severity, IN UINT8 MajorCheckpoint, IN UINT8 MinorCheckpoint, IN UINT8 MajorWarningCode, IN UINT8 MinorWarningCode, IN UINT8 HeciDevice, IN UINT8 MeAddress, IN EFI_STATUS SendStatus, IN EFI_STATUS ReceiveStatus, IN UINT64 Request, IN UINT32 Response)
Add to Enhanced Warning Log entry for Me Communication Failures. More...

Detailed Description

Header file for ME Error Warning Log Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeEwlLib.h.

Function Documentation

◆ MeEwlCommunicationFailures()

VOID MeEwlCommunicationFailures | ( | IN UINT32 | Severity,
 |  | IN UINT8 | MajorCheckpoint,
 |  | IN UINT8 | MinorCheckpoint,
 |  | IN UINT8 | MajorWarningCode,
 |  | IN UINT8 | MinorWarningCode,
 |  | IN UINT8 | HeciDevice,
 |  | IN UINT8 | MeAddress,
 |  | IN EFI_STATUS | SendStatus,
 |  | IN EFI_STATUS | ReceiveStatus,
 |  | IN UINT64 | Request,
 |  | IN UINT32 | Response
 | ) |  |

Add to Enhanced Warning Log entry for Me Communication Failures.

Parameters
[in] | Severity | ME EWL severity
[in] | MajorCheckpoint | Major Warning code
[in] | MinorCheckpoint | Minor Warning code
[in] | MajorWarningCode | Major checkpoint progress indicators written to scratchpad CSR
[in] | MinorWarningCode | Minor checkpoint progress indicators written to scratchpad CSR
[in] | HeciDevice | HECI device (1, 2, or 3)
[in] | MeAddress | HECI address of ME entity
[in] | SendStatus | Status of send operation
[in] | ReceiveStatus | Status of receive operation
[in] | Request | First 8 bytes of request message
[in] | Response | First 4 bytes of response message
Return values
None

◆ MeEwlStateFailures()

VOID MeEwlStateFailures | ( | IN UINT32 | Severity,
 |  | IN UINT8 | MajorCheckpoint,
 |  | IN UINT8 | MinorCheckpoint,
 |  | IN UINT8 | MajorWarningCode,
 |  | IN UINT8 | MinorWarningCode
 | ) |  |

Add to Enhanced Warning Log entry for ME State Failures.

Parameters
[in] | Severity | ME EWL severity
[in] | MajorCheckpoint | Major Warning code
[in] | MinorCheckpoint | Minor Warning code
[in] | MajorWarningCode | Major checkpoint progress indicators written to scratchpad CSR
[in] | MinorWarningCode | Minor checkpoint progress indicators written to scratchpad CSR
Return values
None
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeEwlLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeEwlLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for ME Error Warning Log Lib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ME_EWL_LIB_H_
37 #define _ME_EWL_LIB_H_
38
39 #include <Library/ReportStatusCodeLib.h>
40
41 ///
42 /// EWL severities
43 ///
44 typedef enum {
45 MeEwlSeverityInfo,
46 MeEwlSeverityWarning,
47 MeEwlSeverityFatal,
48 MeEwlSeverityMax,
49 MeEwlSeverityDelim = MAX_UINT32
50 } ME_EWL_SEVERITY;
51
52 /**
53 Add to Enhanced Warning Log entry for ME State Failures
54
55 @param[in] Severity ME EWL severity
56 @param[in] MajorCheckpoint Major Warning code
57 @param[in] MinorCheckpoint Minor Warning code
58 @param[in] MajorWarningCode Major checkpoint progress indicators
59 written to scratchpad CSR
60 @param[in] MinorWarningCode Minor checkpoint progress indicators
61 written to scratchpad CSR
62 @retval None
63 **/
64 VOID
65 MeEwlStateFailures (
66 IN UINT32 Severity,
67 IN UINT8 MajorCheckpoint,
68 IN UINT8 MinorCheckpoint,
69 IN UINT8 MajorWarningCode,
70 IN UINT8 MinorWarningCode
71 );
72
73 /**
74 Add to Enhanced Warning Log entry for Me Communication Failures
75
76 @param[in] Severity ME EWL severity
77 @param[in] MajorCheckpoint Major Warning code
78 @param[in] MinorCheckpoint Minor Warning code
79 @param[in] MajorWarningCode Major checkpoint progress indicators
80 written to scratchpad CSR
81 @param[in] MinorWarningCode Minor checkpoint progress indicators
82 written to scratchpad CSR
83 @param[in] HeciDevice HECI device (1, 2, or 3)
84 @param[in] MeAddress HECI address of ME entity
85 @param[in] SendStatus Status of send operation
86 @param[in] ReceiveStatus Status of receive operation
87 @param[in] Request First 8 bytes of request message
88 @param[in] Response First 4 bytes of response message
89
90 @retval None
91 **/
92 VOID
93 MeEwlCommunicationFailures (
94 IN UINT32 Severity,
95 IN UINT8 MajorCheckpoint,
96 IN UINT8 MinorCheckpoint,
97 IN UINT8 MajorWarningCode,
98 IN UINT8 MinorWarningCode,
99 IN UINT8 HeciDevice,
100 IN UINT8 MeAddress,
101 IN EFI_STATUS SendStatus,
102 IN EFI_STATUS ReceiveStatus,
103 IN UINT64 Request,
104 IN UINT32 Response
105 );
106
107
108 //
109 // Checkpoint numbers used with type 30 & 31
110 //
111 #define ME_EWL_CHKP_MAJOR_NA 0 // Checkpoint unspecified
112 #define ME_EWL_CHKP_MINOR_NA 0 // Checkpoint unspecified
113
114 #define ME_EWL_CHKP_MAJOR_PREMEM 1 // Before DRAM_INIT_DONE message
115 #define ME_EWL_CHKP_PREMEM_HECI 0 // HECI initialization issue
116 #define ME_EWL_CHKP_PREMEM_MESTATE 1 // ME state analysis
117 #define ME_EWL_CHKP_PREMEM_MESEG 2 // MESEG (UMA) allocation
118
119 #define ME_EWL_CHKP_MAJOR_PREINIT 2 // Before MEFS1.InitComplete
120 #define ME_EWL_CHKP_PREINIT_MESTATE 0 // ME state analysis
121 #define ME_EWL_CHKP_PREINIT_MPHY 1 // MPHY update
122
123 #define ME_EWL_CHKP_MAJOR_POSTINIT 3 // Post MEFS1.InitComplete
124 #define ME_EWL_CHKP_POSTINIT_MESTATE 0 // ME in recovery mode
125 #define ME_EWL_CHKP_POSTINIT_MPHY 1 // MPHY update
126 #define ME_EWL_CHKP_POSTINIT_COMPATIB 2 // ME-BIOS compatibility
127 #define ME_EWL_CHKP_POSTINIT_ICC 3
128 #define ME_EWL_CHKP_POSTINIT_EOP 4
129
130 //
131 // Warning Codes used with type 30 & 31
132 //
133 #define ME_EWL_WARN_MAJOR_NA 0 // Warning Code unspecified
134 #define ME_EWL_WARN_MINOR_NA 0 // Warning Code unspecified
135
136 #define ME_EWL_WARN_MAJOR_HECI 1 // HECI access problem
137 #define ME_EWL_WARN_HECI_PCI 0 // HECI PCI device access problem
138 #define ME_EWL_WARN_HECI_API 1 // HECI API (protocol) access problem
139 #define ME_EWL_WARN_HECI_MESSAGE 2 // HECI protocol message failed
140
141 #define ME_EWL_WARN_MAJOR_MEFS1 2 // Issue in ME Firmware Status #1
142 #define ME_EWL_WARN_MEFS1_CURSTATE 0 // Unexpected MEFS1.CurrentState
143 #define ME_EWL_WARN_MEFS1_INCOMPLETE 1 // Unexpected MEFS1.InitComplete
144 #define ME_EWL_WARN_MEFS1_ERROR 0 // Unexpected MEFS1.ErrorCode
145 #define ME_EWL_WARN_MEFS1_OPMODE 0 // Unexpected MEFS1.OperatingMode
146
147
148 #endif // _ME_EWL_LIB_H_
MeEwlCommunicationFailures
VOID MeEwlCommunicationFailures(IN UINT32 Severity, IN UINT8 MajorCheckpoint, IN UINT8 MinorCheckpoint, IN UINT8 MajorWarningCode, IN UINT8 MinorWarningCode, IN UINT8 HeciDevice, IN UINT8 MeAddress, IN EFI_STATUS SendStatus, IN EFI_STATUS ReceiveStatus, IN UINT64 Request, IN UINT32 Response)
Add to Enhanced Warning Log entry for Me Communication Failures.
ME_EWL_SEVERITY
ME_EWL_SEVERITY
EWL severities.
Definition: MeEwlLib.h:44
MeEwlStateFailures
VOID MeEwlStateFailures(IN UINT32 Severity, IN UINT8 MajorCheckpoint, IN UINT8 MinorCheckpoint, IN UINT8 MajorWarningCode, IN UINT8 MinorWarningCode)
Add to Enhanced Warning Log entry for ME State Failures.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFirmwareVersionInfoHobGuid.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
MeFirmwareVersionInfoHobGuid.h File Reference

ME Version Info HUB definition. More...

#include <MkhiMsgs.h>
Include dependency graph for MeFirmwareVersionInfoHobGuid.h:

Go to the source code of this file.

Detailed Description

ME Version Info HUB definition.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeFirmwareVersionInfoHobGuid.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFirmwareVersionInfoHobGuid.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
MeFirmwareVersionInfoHobGuid.h
Go to the documentation of this file.
1 /** @file
2 ME Version Info HUB definition
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ME_FIRMWARE_VERSION_INFO_HOB_GUID_H_
37 #define _ME_FIRMWARE_VERSION_INFO_HOB_GUID_H_
38
39 #include <MkhiMsgs.h>
40
41 typedef struct {
42 MKHI_VERSION MkhiVersion;
43 } ME_FIRMWARE_VERSION_HOB;
44
45 extern EFI_GUID gMeFirmwareVersionHobGuid;
46
47 #endif // _ME_FIRMWARE_VERSION_INFO_HOB_GUID_H_
48
MkhiMsgs.h
MKHI Messages.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFwHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeFwHob.h File Reference

The GUID definition for MeFwHob. More...

#include <FwStsSmbiosTable.h>
Include dependency graph for MeFwHob.h:

Go to the source code of this file.

Detailed Description

The GUID definition for MeFwHob.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeFwHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFwHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeFwHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for MeFwHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ME_FW_HOB_H_
37 #define _ME_FW_HOB_H_
38
39 #include <FwStsSmbiosTable.h>
40
41 extern EFI_GUID gMeFwHobGuid;
42
43 #pragma pack(1)
44
45 typedef struct {
46 UINT32 FunNumber;
47 UINT32 Reg[MAX_FWSTS_REG];
48 } FWSTS_REG_MAP;
49
50 typedef struct {
51 EFI_HOB_GUID_TYPE EfiHobGuidType;
52 UINT8 Revision;
53 UINT8 Count;
54 UINT16 Reserved;
55 FWSTS_REG_MAP Group[HECI_MAX_FUNC];
56 } ME_FW_HOB;
57 #pragma pack()
58 #endif
FwStsSmbiosTable.h
Header file for Firmware Status Smbios Table Interface implementation.
MAX_FWSTS_REG
#define MAX_FWSTS_REG
BIOS FWSTS Structure SMBIOS Table DEF for OEM Type FWSTS structure is defined as SMBIOS OEM type stru...
Definition: FwStsSmbiosTable.h:129
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFwStsLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
MeFwStsLib.h File Reference

Definition for Me FWSTS Lib. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <FwStsSmbiosTable.h>
#include <Register/HeciRegs.h>
Include dependency graph for MeFwStsLib.h:

Go to the source code of this file.

Functions

UINT32 | FindMeFwStsIndex (IN UINT32 FwStsValue)
Find the index of ME FwStsValue in gFwStsOffsetTable. More...
UINT8 | GetMeFwStsDeviceCount (VOID)
Get ME device count that needs to report FWSTS SMBIOS. More...
UINT8 | GetMeFwStsOffsetCount (VOID)
Get ME register offset count that needs to report FWSTS SMBIOS. More...
BOOLEAN | IsCpuDebugDisabled (VOID)
Check if Debug CPU Disabled (DCD) bit is set from FIT CPU Debugging [Disabled]. More...
HECI_FWS_REGISTER | GetMeStatusFromFwstsHob (VOID)
Get ME Firmware Status from FWSTS Hob. More...
UINT32 | GetMeModeFromFwstsHob (VOID)
Get ME operation mode from FWSTS Hob. More...

Detailed Description

Definition for Me FWSTS Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeFwStsLib.h.

Function Documentation

◆ FindMeFwStsIndex()

UINT32 FindMeFwStsIndex ( IN UINT32 FwStsValue )

Find the index of ME FwStsValue in gFwStsOffsetTable.

Parameters
[in] FwStsValue FWSTS register value.
Return values
UINT32 | The index of FwStsValue in gFwStsOffsetTable
0xFF | The index of FwStsValue is not found

◆ GetMeFwStsDeviceCount()

UINT8 GetMeFwStsDeviceCount ( VOID )

Get ME device count that needs to report FWSTS SMBIOS.

Return values
UINT8 Count of device list.

◆ GetMeFwStsOffsetCount()

UINT8 GetMeFwStsOffsetCount ( VOID )

Get ME register offset count that needs to report FWSTS SMBIOS.

Return values
UINT8 Count of register offset.

◆ GetMeModeFromFwstsHob()

UINT32 GetMeModeFromFwstsHob ( VOID )

Get ME operation mode from FWSTS Hob.

Return values
UINT32 ME operation mode.

◆ GetMeStatusFromFwstsHob()

HECI_FWS_REGISTER GetMeStatusFromFwstsHob ( VOID )

Get ME Firmware Status from FWSTS Hob.

Return values
HECI_FWS_REGISTER ME firmware status value.

◆ IsCpuDebugDisabled()

BOOLEAN IsCpuDebugDisabled ( VOID )

Check if Debug CPU Disabled (DCD) bit is set from FIT CPU Debugging [Disabled].

If it is set, CPU probe is disabled.

Return values
TRUE | DCD is set
FALSE | DCD is clear
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeFwStsLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeFwStsLib.h
Go to the documentation of this file.
1 /** @file
2 Definition for Me FWSTS Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_FWSTS_LIB_H_
36 #define _ME_FWSTS_LIB_H_
37
38 #include <Uefi.h>
39 #include <Library/BaseLib.h>
40 #include <FwStsSmbiosTable.h>
41 #include <Register/HeciRegs.h>
42
43 extern CONST MEI_DEV_STRING gFwStsDeviceList[];
44 extern CONST UINT32 gFwStsOffsetTable[];
45
46 /**
47 Find the index of ME FwStsValue in gFwStsOffsetTable.
48
49 @param[in] FwStsValue FWSTS register value.
50
51 @retval UINT32 The index of FwStsValue in gFwStsOffsetTable
52 @retval 0xFF The index of FwStsValue is not found
53 **/
54 UINT32
55 EFIAPI
56 FindMeFwStsIndex (
57 IN UINT32 FwStsValue
58 );
59
60 /**
61 Get ME device count that needs to report FWSTS SMBIOS
62
63 @retval UINT8 Count of device list.
64 **/
65 UINT8
66 EFIAPI
67 GetMeFwStsDeviceCount (
68 VOID
69 );
70
71 /**
72 Get ME register offset count that needs to report FWSTS SMBIOS
73
74 @retval UINT8 Count of register offset.
75 **/
76 UINT8
77 EFIAPI
78 GetMeFwStsOffsetCount (
79 VOID
80 );
81
82 /**
83 Check if Debug CPU Disabled (DCD) bit is set from FIT CPU Debugging [Disabled].
84 If it is set, CPU probe is disabled.
85
86 @retval TRUE DCD is set
87 @retval FALSE DCD is clear
88 **/
89 BOOLEAN
90 IsCpuDebugDisabled (
91 VOID
92 );
93
94 /**
95 Get ME Firmware Status from FWSTS Hob.
96
97 @retval HECI_FWS_REGISTER ME firmware status value.
98 **/
99 HECI_FWS_REGISTER
100 GetMeStatusFromFwstsHob (
101 VOID
102 );
103
104 /**
105 Get ME operation mode from FWSTS Hob.
106
107 @retval UINT32 ME operation mode.
108 **/
109 UINT32
110 GetMeModeFromFwstsHob (
111 VOID
112 );
113
114 #endif
FindMeFwStsIndex
UINT32 FindMeFwStsIndex(IN UINT32 FwStsValue)
Find the index of ME FwStsValue in gFwStsOffsetTable.
GetMeFwStsOffsetCount
UINT8 GetMeFwStsOffsetCount(VOID)
Get ME register offset count that needs to report FWSTS SMBIOS.
GetMeModeFromFwstsHob
UINT32 GetMeModeFromFwstsHob(VOID)
Get ME operation mode from FWSTS Hob.
HeciRegs.h
Register Definitions for HECI.
HECI_FWS_REGISTER
HFSTS1, offset 40h.
Definition: HeciRegs.h:84
IsCpuDebugDisabled
BOOLEAN IsCpuDebugDisabled(VOID)
Check if Debug CPU Disabled (DCD) bit is set from FIT CPU Debugging [Disabled].
MEI_DEV_STRING
MEI Device Structure.
Definition: FwStsSmbiosTable.h:141
FwStsSmbiosTable.h
Header file for Firmware Status Smbios Table Interface implementation.
GetMeStatusFromFwstsHob
HECI_FWS_REGISTER GetMeStatusFromFwstsHob(VOID)
Get ME Firmware Status from FWSTS Hob.
GetMeFwStsDeviceCount
UINT8 GetMeFwStsDeviceCount(VOID)
Get ME device count that needs to report FWSTS SMBIOS.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeiBusMsg.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeiBusMsg.h File Reference

Definitions for MEI Bus message support. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Definitions for MEI Bus message support.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeiBusMsg.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeiBusMsg.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeiBusMsg.h
Go to the documentation of this file.
1 /** @file
2 Definitions for MEI Bus message support
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEI_BUS_MSG_H_
36 #define _MEI_BUS_MSG_H_
37
38 #define HBM_MINOR_VERSION_0 0
39 #define HBM_MINOR_VERSION_2 2
40 #define HBM_MAJOR_VERSION_1 1
41 #define HBM_MAJOR_VERSION_2 2
42
43 #define HOST_VERSION_REQUEST 0x01
44 #define HOST_STOP_REQUEST 0x02
45 #define HOST_ENUMERATE_REQUEST 0x04
46 #define HOST_CLIENT_PROPERTIES_REQUEST 0x05
47 #define CLIENT_CONNECT_REQUEST 0x06
48 #define CLIENT_DISCONNECT_REQUEST 0x07
49 #define FLOW_CONTROL 0x08
50 #define HECI_BUS_DISABLE_OPCODE 0x0C
51 #define CAPABILITIES_REQUEST 0x13
52 #define CLIENT_DMA_MAP_REQUEST 0x14
53 #define CLIENT_DMA_UNMAP_REQUEST 0x15
54
55 #pragma pack(1)
56
57 typedef union {
58 UINT8 Data;
59 struct {
60 UINT8 Command : 7;
61 UINT8 IsResponse : 1;
62 } Fields;
63 } HBM_COMMAND;
64
65 typedef struct {
66 UINT8 MinorVersion;
67 UINT8 MajorVersion;
68 } HBM_VERSION;
69
70 typedef struct {
71 HBM_COMMAND Command;
72 UINT8 Reserved;
73 HBM_VERSION HostVersion;
74 } HBM_HOST_VERSION_REQUEST;
75
76 typedef struct {
77 HBM_COMMAND Command;
78 UINT8 HostVersionSupported;
79 HBM_VERSION MeMaxVersion;
80 } HBM_HOST_VERSION_RESPONSE;
81
82 typedef union {
83 HBM_HOST_VERSION_REQUEST Request;
84 HBM_HOST_VERSION_RESPONSE Response;
85 } HBM_HOST_VERSION_BUFFER;
86
87 #define STOP_REASON_REQUEST_FROM_DRIVER 0x00
88
89 typedef struct {
90 HBM_COMMAND Command;
91 UINT8 Reason;
92 UINT8 Reserved[2];
93 } HBM_HOST_STOP_REQUEST;
94
95 typedef struct {
96 HBM_COMMAND Command;
97 UINT8 Reserved[3];
98 } HBM_HOST_STOP_RESPONSE;
99
100 typedef struct {
101 HBM_COMMAND Command;
102 UINT8 Reserved[3];
103 } HBM_HOST_ENUMERATION_REQUEST;
104
105 typedef struct {
106 HBM_COMMAND Command;
107 UINT8 Reserved[3];
108 UINT8 ValidAddresses[32];
109 } HBM_HOST_ENUMERATION_RESPONSE;
110
111 typedef union {
112 HBM_HOST_ENUMERATION_REQUEST Request;
113 HBM_HOST_ENUMERATION_RESPONSE Response;
114 } HBM_HOST_ENUMERATION_BUFFER;
115
116 #define NUMBER_OF_VALID_ADDRESS_BITS 32*8
117
118 typedef struct {
119 HBM_COMMAND Command;
120 UINT8 Address;
121 UINT8 Reserved[2];
122 } HBM_HOST_CLIENT_PROPERTIES_REQUEST;
123
124 typedef struct {
125 EFI_GUID ProtocolName;
126 UINT8 ProtocolVersion;
127 UINT8 MaxNumberOfConnections;
128 UINT8 FixedAddress;
129 UINT8 SingleReceiveBuffer;
130 UINT32 MaxMessageLength;
131 UINT32 Reserved;
132 } HECI_CLIENT_PROPERTIES;
133
134 typedef struct {
135 HBM_COMMAND Command;
136 UINT8 Address;
137 UINT8 Status;
138 UINT8 Reserved;
139 HECI_CLIENT_PROPERTIES ClientProperties;
140 } HBM_HOST_CLIENT_PROPERTIES_RESPONSE;
141
142 typedef union {
143 HBM_HOST_CLIENT_PROPERTIES_REQUEST Request;
144 HBM_HOST_CLIENT_PROPERTIES_RESPONSE Response;
145 } HBM_HOST_CLIENT_PROPERTIES_BUFFER;
146
147 typedef struct {
148 HBM_COMMAND Command;
149 UINT8 MeAddress;
150 UINT8 HostAddress;
151 UINT8 Reserved;
152 } HBM_CLIENT_CONNECT_REQUEST;
153
154 typedef struct {
155 HBM_COMMAND Command;
156 UINT8 MeAddress;
157 UINT8 HostAddress;
158 UINT8 Status;
159 } HBM_CLIENT_CONNECT_RESPONSE;
160
161 typedef union {
162 HBM_CLIENT_CONNECT_REQUEST Request;
163 HBM_CLIENT_CONNECT_RESPONSE Response;
164 } HBM_CLIENT_CONNECT_BUFFER;
165
166 typedef struct {
167 HBM_COMMAND Command;
168 UINT8 MeAddress;
169 UINT8 HostAddress;
170 UINT8 Reserved;
171 } HBM_CLIENT_DISCONNECT_REQUEST;
172
173 typedef struct {
174 HBM_COMMAND Command;
175 UINT8 MeAddress;
176 UINT8 HostAddress;
177 UINT8 Status;
178 } HBM_CLIENT_DISCONNECT_RESPONSE;
179
180 typedef union {
181 HBM_CLIENT_DISCONNECT_REQUEST Request;
182 HBM_CLIENT_DISCONNECT_RESPONSE Response;
183 } HBM_CLIENT_DISCONNECT_BUFFER;
184
185 typedef struct {
186 HBM_COMMAND Command;
187 UINT8 MeAddress;
188 UINT8 HostAddress;
189 UINT8 Reserved[5];
190 } HBM_FLOW_CONTROL;
191
192 typedef struct {
193 HBM_COMMAND Command;
194 UINT8 Reserved[3];
195 } HECI_BUS_DISABLE_CMD;
196
197 typedef struct {
198 HBM_COMMAND Command;
199 UINT8 Status;
200 UINT8 Reserved[2];
201 } HECI_BUS_DISABLE_CMD_ACK;
202
203 typedef union {
204 UINT8 Data;
205 struct {
206 UINT8 Vm : 1; ///< [0] VM tag
207 UINT8 GscSgl : 1; ///< [1] GSC SGL
208 UINT8 ClientDma : 1; ///< [2] Client DMA Mapping and DMA Map/Unmap HBM messages
209 UINT8 Reserved : 5; ///< [7:3] Reserved
210 } Capabilities;
211 } HBM_CAPS_DATA;
212
213 typedef struct {
214 HBM_COMMAND Command;
215 HBM_CAPS_DATA Capabilities; ///< Host driver HBM capabilities
216 UINT8 Reserved[2];
217 } HBM_CAPABILITIES_REQUEST;
218
219 typedef struct {
220 HBM_COMMAND Command;
221 HBM_CAPS_DATA Capabilities; ///< FW driver HBM capabilities
222 UINT8 Reserved[2];
223 } HBM_CAPABILITIES_RESPONSE;
224
225 typedef union {
226 HBM_CAPABILITIES_REQUEST Request;
227 HBM_CAPABILITIES_RESPONSE Response;
228 } HBM_CAPABILITIES_BUFFER;
229
230 typedef enum {
231 ClientDmaBufferIdError = 0,
232 ClientDmaBufferIdWlan
233 } HBM_CLIENT_DMA_BUFFER_ID;
234
235 typedef struct {
236 HBM_COMMAND Command;
237 UINT8 ClientBufferId;
238 UINT8 Reserved[2];
239 UINT32 AddressLow;
240 UINT32 AddressHigh;
241 UINT32 Size;
242 } HBM_CLIENT_DMA_MAP_REQUEST;
243
244 typedef struct {
245 HBM_COMMAND Command;
246 UINT8 Status;
247 UINT8 Reserved[2];
248 } HBM_CLIENT_DMA_MAP_RESPONSE;
249
250 typedef union {
251 HBM_CLIENT_DMA_MAP_REQUEST Request;
252 HBM_CLIENT_DMA_MAP_RESPONSE Response;
253 } HBM_CLIENT_DMA_MAP_BUFFER;
254
255 typedef struct {
256 HBM_COMMAND Command;
257 UINT8 Status;
258 UINT8 ClientBufferId;
259 UINT8 Reserved;
260 } HBM_CLIENT_DMA_UNMAP_REQUEST;
261
262 typedef struct {
263 HBM_COMMAND Command;
264 UINT8 Status;
265 UINT8 Reserved[2];
266 } HBM_CLIENT_DMA_UNMAP_RESPONSE;
267
268 typedef union {
269 HBM_CLIENT_DMA_UNMAP_REQUEST Request;
270 HBM_CLIENT_DMA_UNMAP_RESPONSE Response;
271 } HBM_CLIENT_DMA_UNMAP_BUFFER;
272
273 #pragma pack()
274
275 #endif // _MEI_BUS_MSG_H_
276
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemInfo.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
Classes
MemInfo.h File Reference

This protocol provides the memory information data, such as total physical memory size, memory frequency, memory size of each dimm and rank. More...

Go to the source code of this file.

Classes

struct | MEMORY_TIMING
Memory timing Structure. More...
struct | MEMORY_INFO_DATA
Memory information Data Structure. More...
struct | MEM_INFO_PROTOCOL
Memory information Protocol definition. More...

Detailed Description

This protocol provides the memory information data, such as total physical memory size, memory frequency, memory size of each dimm and rank.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemInfo.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemInfo.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
MemInfo.h
Go to the documentation of this file.
1 /** @file
2 This protocol provides the memory information data, such as
3 total physical memory size, memory frequency, memory size
4 of each dimm and rank.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2021 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
31 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
32 the terms of your license agreement with Intel or your vendor. This file may
33 be modified by the user, subject to additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37 #ifndef _MEM_INFO_PROTOCOL_H_
38 #define _MEM_INFO_PROTOCOL_H_
39
40
41 //
42 // Extern the GUID for protocol users.
43 //
44 extern EFI_GUID gMemInfoProtocolGuid;
45
46 //
47 // Protocol definitions
48 //
49 #define NODE_NUM 2
50 #define CH_NUM 4
51 #define DIMM_NUM 2
52 #define RANK_NUM 2
53 #define SLOT_NUM (NODE_NUM * CH_NUM * DIMM_NUM)
54 #define PROFILE_NUM 7 // number of memory profiles supported
55
56 //
57 // Matches MrcDdrType enum in MRC
58 //
59 #ifndef MRC_DDR_TYPE_DDR4
60 #define MRC_DDR_TYPE_DDR4 0
61 #endif
62 #ifndef MRC_DDR_TYPE_DDR5
63 #define MRC_DDR_TYPE_DDR5 1
64 #endif
65 #ifndef MRC_DDR_TYPE_LPDDR5
66 #define MRC_DDR_TYPE_LPDDR5 2
67 #endif
68 #ifndef MRC_DDR_TYPE_LPDDR4
69 #define MRC_DDR_TYPE_LPDDR4 3
70 #endif
71 #ifndef MRC_DDR_TYPE_UNKNOWN
72 #define MRC_DDR_TYPE_UNKNOWN 4
73 #endif
74
75 //
76 // Matches MrcChannelSts enum in MRC
77 //
78 #ifndef CHANNEL_NOT_PRESENT
79 #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
80 #endif
81 #ifndef CHANNEL_DISABLED
82 #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
83 #endif
84 #ifndef CHANNEL_PRESENT
85 #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
86 #endif
87
88 //
89 // Matches MrcDimmSts enum in MRC
90 //
91 #ifndef DIMM_ENABLED
92 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
93 #endif
94 #ifndef DIMM_DISABLED
95 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
96 #endif
97 #ifndef DIMM_PRESENT
98 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
99 #endif
100 #ifndef DIMM_NOT_PRESENT
101 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
102 #endif
103
104 #pragma pack(1)
105 ///
106 /// Memory timing Structure
107 ///
108 typedef struct {
109 UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds.
110 UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
111 UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
112 UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
113 UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
114 UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
115 UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
116 UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
117 UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
118 UINT16 tRFCpb; ///< Offset 20 Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
119 UINT16 tRFC2; ///< Offset 22 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
120 UINT16 tRFC4; ///< Offset 24 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
121 UINT16 tRPab; ///< Offset 26 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
122 UINT16 tRRD; ///< Offset 28 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
123 UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
124 UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
125 UINT16 tRTP; ///< Offset 34 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
126 UINT16 tWR; ///< Offset 36 Number of tCK cycles for the channel DIMM's minimum write recovery time.
127 UINT16 tWTR; ///< Offset 38 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
128 UINT16 tWTR_L; ///< Offset 40 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
129 UINT16 tWTR_S; ///< Offset 42 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
130 UINT16 tCCD_L; ///< Offset 44 Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
131 UINT8 Rsvd[2]; ///< Offset 46
132 } MEMORY_TIMING;
133
134 // @todo use the MemInfoHob data instead of duplicate structure.
135 ///
136 /// Memory information Data Structure
137 ///
138 typedef struct {
139 MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timming information for the DIMM
140 UINT32 memSize; ///< Offset 128 Total physical memory size
141 UINT16 ddrFreq; ///< Offset 132 DDR Current Frequency
142 UINT16 ddrFreqMax; ///< Offset 134 DDR Maximum Frequency
143 UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Size of each DIMM
144 UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144(ICL)/168(TGL) The voltage setting for the DIMM
145 UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152(ICL)/176(TGL) The enumeration value from MrcDimmSts
146 UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156(ICL)/192(TGL) No. of ranks in a dimm
147 UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160(ICL)/208(TGL) SPD data of each DIMM
148 UINT8 RefClk; ///< Offset 192(ICL)/336(TGL) Reference Clock
149 UINT8 Ratio; ///< Offset 193(ICL)/337(TGL) Clock Multiplier
150 BOOLEAN EccSupport; ///< Offset 194(ICL)/338(TGL) ECC supported or not
151 UINT8 Profile; ///< Offset 195(ICL)/339(TGL) Currently running memory profile
152 UINT8 XmpProfileEnable; ///< Offset 196(ICL)/340(TGL): Capability status. 0 is none supported. Bit 0: XMP 1, Bit 1: XMP 2, Bit 2: XMP 3, Bit 3: User 4, Bit 4: User 5.
153 UINT8 DdrType; ///< Offset 197(ICL)/341(TGL): Current DDR type, see DDR_TYPE_xxx defines above
154 UINT16 Ratio_UINT16; ///< Offset 198(ICL)/342(TGL) Clock Multiplier UINT16
155 UINT16 VddqVoltage[PROFILE_NUM]; ///< Offset 200(ICL)/344(TGL) The voltage setting for the DIMM
156 UINT16 VppVoltage[PROFILE_NUM]; ///< Offset 208(ICL)/352(TGL) The voltage setting for the DIMM
157 BOOLEAN XmpConfigWarning; ///< Offset 216(ICL)/360(TGL) XMP Dimm Config Warning - 1DPC capable but 2DPC is installed
158 UINT8 IsDMBRunning; ///< Offset 217(ICL)/361(TGL) Deprecated
159 BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
160 BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
161 } MEMORY_INFO_DATA;
162 #pragma pack()
163
164 ///
165 /// Memory information Protocol definition
166 ///
167 typedef struct {
168 MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure
169 } MEM_INFO_PROTOCOL;
170
171 #endif
MEMORY_INFO_DATA::ddrFreq
UINT16 ddrFreq
Offset 132 DDR Current Frequency.
Definition: MemInfo.h:141
MEMORY_TIMING::tWTR_L
UINT16 tWTR_L
Offset 40 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay ti...
Definition: MemInfo.h:128
MEMORY_TIMING::tREFI
UINT16 tREFI
Offset 16 Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
Definition: MemInfo.h:116
MEMORY_TIMING::tRAS
UINT16 tRAS
Offset 12 Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
Definition: MemInfo.h:114
MEMORY_TIMING::tFAW
UINT16 tFAW
Offset 10 Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
Definition: MemInfo.h:113
MEMORY_TIMING::tRTP
UINT16 tRTP
Offset 34 Number of tCK cycles for the channel DIMM's minimum internal read to precharge command dela...
Definition: MemInfo.h:125
MEM_INFO_PROTOCOL
Memory information Protocol definition.
Definition: MemInfo.h:167
MEMORY_TIMING::tRCDtRP
UINT16 tRCDtRP
Offset 14 Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Prechar...
Definition: MemInfo.h:115
MEMORY_TIMING::tRRD
UINT16 tRRD
Offset 28 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
Definition: MemInfo.h:122
MEMORY_TIMING::NMode
UINT16 NMode
Offset 4 Number of tCK cycles for the channel DIMM's command rate mode.
Definition: MemInfo.h:110
MEMORY_TIMING::tCL
UINT16 tCL
Offset 6 Number of tCK cycles for the channel DIMM's CAS latency.
Definition: MemInfo.h:111
MEMORY_INFO_DATA::XmpProfileEnable
UINT8 XmpProfileEnable
Offset 196(ICL)/340(TGL): Capability status. 0 is none supported. Bit 0: XMP 1, Bit 1: XMP 2,...
Definition: MemInfo.h:152
MEMORY_INFO_DATA::DdrType
UINT8 DdrType
Offset 197(ICL)/341(TGL): Current DDR type, see DDR_TYPE_xxx defines above.
Definition: MemInfo.h:153
MEMORY_INFO_DATA::Ratio_UINT16
UINT16 Ratio_UINT16
Offset 198(ICL)/342(TGL) Clock Multiplier UINT16.
Definition: MemInfo.h:154
MEMORY_INFO_DATA::XmpConfigWarning
BOOLEAN XmpConfigWarning
Offset 216(ICL)/360(TGL) XMP Dimm Config Warning - 1DPC capable but 2DPC is installed.
Definition: MemInfo.h:157
MEMORY_TIMING::tCWL
UINT16 tCWL
Offset 8 Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
Definition: MemInfo.h:112
MEMORY_TIMING::tRRD_S
UINT16 tRRD_S
Offset 32 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for...
Definition: MemInfo.h:124
MEMORY_TIMING::tRFCpb
UINT16 tRFCpb
Offset 20 Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
Definition: MemInfo.h:118
MEMORY_TIMING::tCCD_L
UINT16 tCCD_L
Offset 44 Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
Definition: MemInfo.h:130
MEMORY_INFO_DATA::Ratio
UINT8 Ratio
Offset 193(ICL)/337(TGL) Clock Multiplier.
Definition: MemInfo.h:149
MEMORY_INFO_DATA::DynamicMemoryBoostTrainingFailed
BOOLEAN DynamicMemoryBoostTrainingFailed
TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot....
Definition: MemInfo.h:160
MEMORY_TIMING::tRFC
UINT16 tRFC
Offset 18 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
Definition: MemInfo.h:117
MEMORY_TIMING::tRPab
UINT16 tRPab
Offset 26 Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
Definition: MemInfo.h:121
MEM_INFO_PROTOCOL::MemInfoData
MEMORY_INFO_DATA MemInfoData
Memory Information Data Structure.
Definition: MemInfo.h:168
MEMORY_TIMING
Memory timing Structure.
Definition: MemInfo.h:108
MEMORY_INFO_DATA::memSize
UINT32 memSize
Offset 128 Total physical memory size.
Definition: MemInfo.h:140
MEMORY_INFO_DATA::MemorySpeedReducedWrongDimmSlot
BOOLEAN MemorySpeedReducedWrongDimmSlot
Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DI...
Definition: MemInfo.h:159
MEMORY_TIMING::tCK
UINT32 tCK
Offset 0 Memory cycle time, in femtoseconds.
Definition: MemInfo.h:109
MEMORY_INFO_DATA::EccSupport
BOOLEAN EccSupport
Offset 194(ICL)/338(TGL) ECC supported or not.
Definition: MemInfo.h:150
MEMORY_TIMING::tRFC2
UINT16 tRFC2
Offset 22 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
Definition: MemInfo.h:119
MEMORY_TIMING::tWTR
UINT16 tWTR
Offset 38 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay ti...
Definition: MemInfo.h:127
MEMORY_INFO_DATA::IsDMBRunning
UINT8 IsDMBRunning
Offset 217(ICL)/361(TGL) Deprecated.
Definition: MemInfo.h:158
MEMORY_TIMING::tRFC4
UINT16 tRFC4
Offset 24 Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
Definition: MemInfo.h:120
MEMORY_INFO_DATA
Memory information Data Structure.
Definition: MemInfo.h:138
MEMORY_TIMING::tWTR_S
UINT16 tWTR_S
Offset 42 Number of tCK cycles for the channel DIMM's minimum internal write to read command delay ti...
Definition: MemInfo.h:129
MEMORY_TIMING::tRRD_L
UINT16 tRRD_L
Offset 30 Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for...
Definition: MemInfo.h:123
MEMORY_INFO_DATA::RefClk
UINT8 RefClk
Offset 192(ICL)/336(TGL) Reference Clock.
Definition: MemInfo.h:148
MEMORY_TIMING::tWR
UINT16 tWR
Offset 36 Number of tCK cycles for the channel DIMM's minimum write recovery time.
Definition: MemInfo.h:126
MEMORY_INFO_DATA::Profile
UINT8 Profile
Offset 195(ICL)/339(TGL) Currently running memory profile.
Definition: MemInfo.h:151
MEMORY_INFO_DATA::ddrFreqMax
UINT16 ddrFreqMax
Offset 134 DDR Maximum Frequency.
Definition: MemInfo.h:142
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Classes | Macros | Enumerations
MemInfoHob.h File Reference

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs. More...

Go to the source code of this file.

Classes

struct | DIMM_INFO
Memory SMBIOS & OC Memory Data Hob. More...
struct | HOB_SAGV_TIMING_OUT
This data structure contains per-SaGv timing values that are considered output by the MRC. More...
struct | HOB_SAGV_INFO
This data structure contains SAGV config values that are considered output by the MRC. More...
struct | MEMORY_PLATFORM_DATA
Memory Platform Data Hob. More...

Macros

#define | WARM_BOOT 2
Host reset states from MRC.
#define | MAX_SPD_SAVE 29
Defines taken from MRC so avoid having to include MrcInterface.h.

Enumerations

enum MRC_BOOT_MODE

Detailed Description

This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemInfoHob.h.

Enumeration Type Documentation

◆ MRC_BOOT_MODE

enum MRC_BOOT_MODE
Enumerator
bmCold | Cold boot.
bmWarm | Warm boot.
bmS3 | S3 resume.
bmFast | Fast boot.
MrcBootModeMax | MRC_BOOT_MODE enumeration maximum value.
MrcBootModeDelim | This value ensures the enum size is consistent on both sides of the PPI.

Definition at line 142 of file MemInfoHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
MemInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required for creation of
3 Memory S3 Save data, Memory Info data and Memory Platform
4 data hobs.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 1999 - 2021 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
31 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
32 the terms of your license agreement with Intel or your vendor. This file may
33 be modified by the user, subject to additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37 #ifndef _MEM_INFO_HOB_H_
38 #define _MEM_INFO_HOB_H_
39
40
41 #pragma pack (push, 1)
42
43 extern EFI_GUID gSiMemoryS3DataGuid;
44 extern EFI_GUID gSiMemoryInfoDataGuid;
45 extern EFI_GUID gSiMemoryPlatformDataGuid;
46
47 #define MAX_NODE 2
48 #define MAX_CH 4
49 #define MAX_DIMM 2
50 // Must match definitions in
51 // Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
52 #define HOB_MAX_SAGV_POINTS 4
53
54 ///
55 /// Host reset states from MRC.
56 ///
57 #define WARM_BOOT 2
58
59 #define R_MC_CHNL_RANK_PRESENT 0x7C
60 #define B_RANK0_PRS BIT0
61 #define B_RANK1_PRS BIT1
62 #define B_RANK2_PRS BIT4
63 #define B_RANK3_PRS BIT5
64
65 // @todo remove and use the MdePkg\Include\Pi\PiHob.h
66 #if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
67 #ifndef __HOB__H__
68 typedef struct _EFI_HOB_GENERIC_HEADER {
69 UINT16 HobType;
70 UINT16 HobLength;
71 UINT32 Reserved;
72 } EFI_HOB_GENERIC_HEADER;
73
74 typedef struct _EFI_HOB_GUID_TYPE {
75 EFI_HOB_GENERIC_HEADER Header;
76 EFI_GUID Name;
77 ///
78 /// Guid specific data goes here
79 ///
80 } EFI_HOB_GUID_TYPE;
81 #endif
82 #endif
83
84 ///
85 /// Defines taken from MRC so avoid having to include MrcInterface.h
86 ///
87
88 //
89 // Matches MAX_SPD_SAVE define in MRC
90 //
91 #ifndef MAX_SPD_SAVE
92 #define MAX_SPD_SAVE 29
93 #endif
94
95 //
96 // MRC version description.
97 //
98 typedef struct {
99 UINT8 Major; ///< Major version number
100 UINT8 Minor; ///< Minor version number
101 UINT8 Rev; ///< Revision number
102 UINT8 Build; ///< Build number
103 } SiMrcVersion;
104
105 //
106 // Matches MrcChannelSts enum in MRC
107 //
108 #ifndef CHANNEL_NOT_PRESENT
109 #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
110 #endif
111 #ifndef CHANNEL_DISABLED
112 #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
113 #endif
114 #ifndef CHANNEL_PRESENT
115 #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
116 #endif
117
118 //
119 // Matches MrcDimmSts enum in MRC
120 //
121 #ifndef DIMM_ENABLED
122 #define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
123 #endif
124 #ifndef DIMM_DISABLED
125 #define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
126 #endif
127 #ifndef DIMM_PRESENT
128 #define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
129 #endif
130 #ifndef DIMM_NOT_PRESENT
131 #define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
132 #endif
133
134 //
135 // Matches MrcBootMode enum in MRC
136 //
137 #ifndef __MRC_BOOT_MODE__
138 #define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h
139 #ifndef INT32_MAX
140 #define INT32_MAX (0x7FFFFFFF)
141 #endif //INT32_MAX
142 typedef enum {
143 bmCold, ///< Cold boot
144 bmWarm, ///< Warm boot
145 bmS3, ///< S3 resume
146 bmFast, ///< Fast boot
147 MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value.
148 MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI.
149 } MRC_BOOT_MODE;
150 #endif //__MRC_BOOT_MODE__
151
152 //
153 // Matches MrcDdrType enum in MRC
154 //
155 #ifndef MRC_DDR_TYPE_DDR5
156 #define MRC_DDR_TYPE_DDR5 1
157 #endif
158 #ifndef MRC_DDR_TYPE_LPDDR5
159 #define MRC_DDR_TYPE_LPDDR5 2
160 #endif
161 #ifndef MRC_DDR_TYPE_LPDDR4
162 #define MRC_DDR_TYPE_LPDDR4 3
163 #endif
164 #ifndef MRC_DDR_TYPE_UNKNOWN
165 #define MRC_DDR_TYPE_UNKNOWN 4
166 #endif
167
168 #define MAX_PROFILE_NUM 7 // number of memory profiles supported
169 #define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
170
171 #define MAX_TRACE_REGION 5
172 #define MAX_TRACE_CACHE_TYPE 2
173
174 //
175 // DIMM timings
176 //
177 typedef struct {
178 UINT32 tCK; ///< Memory cycle time, in femtoseconds.
179 UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
180 UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
181 UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
182 UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
183 UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
184 UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
185 UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
186 UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
187 UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
188 UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
189 UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
190 UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
191 UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
192 UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
193 UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
194 UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
195 UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
196 UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
197 UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
198 UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
199 UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
200 } MRC_CH_TIMING;
201
202 typedef struct {
203 UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
204 } MRC_IP_TIMING;
205
206 ///
207 /// Memory SMBIOS & OC Memory Data Hob
208 ///
209 typedef struct {
210 UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
211 UINT8 DimmId;
212 UINT32 DimmCapacity; ///< DIMM size in MBytes.
213 UINT16 MfgId;
214 UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
215 UINT8 RankInDimm; ///< The number of ranks in this DIMM.
216 UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
217 UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
218 UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
219 UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
220 UINT16 Speed; ///< The maximum capable speed of the device, in MHz
221 UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
222 } DIMM_INFO;
223
224 typedef struct {
225 UINT8 Status; ///< Indicates whether this channel should be used.
226 UINT8 ChannelId;
227 UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
228 MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
229 DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
230 } CHANNEL_INFO;
231
232 typedef struct {
233 UINT8 Status; ///< Indicates whether this controller should be used.
234 UINT16 DeviceId; ///< The PCI device id of this memory controller.
235 UINT8 RevisionId; ///< The PCI revision id of this memory controller.
236 UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
237 CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
238 } CONTROLLER_INFO;
239
240 typedef struct {
241 UINT64 BaseAddress; ///< Trace Base Address
242 UINT64 TotalSize; ///< Total Trace Region of Same Cache type
243 UINT8 CacheType; ///< Trace Cache Type
244 UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
245 UINT8 Rsvd[2];
246 } PSMI_MEM_INFO;
247
248 /// This data structure contains per-SaGv timing values that are considered output by the MRC.
249 typedef struct {
250 UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
251 MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
252 MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
253 } HOB_SAGV_TIMING_OUT;
254
255 /// This data structure contains SAGV config values that are considered output by the MRC.
256 typedef struct {
257 UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
258 UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
259 HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
260 } HOB_SAGV_INFO;
261
262 typedef struct {
263 UINT8 Revision;
264 UINT16 DataWidth; ///< Data width, in bits, of this memory device
265 /** As defined in SMBIOS 3.0 spec
266 Section 7.18.2 and Table 75
267 **/
268 UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
269 UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
270 UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
271 /** As defined in SMBIOS 3.0 spec
272 Section 7.17.3 and Table 72
273 **/
274 UINT8 ErrorCorrectionType;
275
276 SiMrcVersion Version;
277 BOOLEAN EccSupport;
278 UINT8 MemoryProfile;
279 UINT8 IsDMBRunning; ///< Deprecated.
280 UINT32 TotalPhysicalMemorySize;
281 UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
282 ///
283 /// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
284 /// Bit 0: XMP Profile 1 capability status
285 /// Bit 1: XMP Profile 2 capability status
286 /// Bit 2: XMP Profile 3 capability status
287 /// Bit 3: User Profile 4 capability status
288 /// Bit 4: User Profile 5 capability status
289 ///
290 UINT8 XmpProfileEnable;
291 UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
292 UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
293 UINT8 RefClk;
294 UINT32 VddVoltage[MAX_PROFILE_NUM];
295 UINT32 VddqVoltage[MAX_PROFILE_NUM];
296 UINT32 VppVoltage[MAX_PROFILE_NUM];
297 CONTROLLER_INFO Controller[MAX_NODE];
298 UINT16 Ratio_UINT16; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
299 UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
300 HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
301 UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
302 BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population
303 BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config
304 BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
305 } MEMORY_INFO_DATA_HOB;
306
307 /**
308 Memory Platform Data Hob
309
310 <b>Revision 1:</b>
311 - Initial version.
312 <b>Revision 2:</b>
313 - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
314 **/
315 typedef struct {
316 UINT8 Revision;
317 UINT8 Reserved[3];
318 UINT32 BootMode;
319 UINT32 TsegSize;
320 UINT32 TsegBase;
321 UINT32 PrmrrSize;
322 UINT64 PrmrrBase;
323 UINT32 GttBase;
324 UINT32 MmioSize;
325 UINT32 PciEBaseAddress;
326 PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
327 PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
328 BOOLEAN MrcBasicMemoryTestPass;
329 } MEMORY_PLATFORM_DATA;
330
331 typedef struct {
332 EFI_HOB_GUID_TYPE EfiHobGuidType;
333 MEMORY_PLATFORM_DATA Data;
334 UINT8 *Buffer;
335 } MEMORY_PLATFORM_DATA_HOB;
336
337 #pragma pack (pop)
338
339 #endif // _MEM_INFO_HOB_H_
HOB_SAGV_INFO::NumSaGvPointsEnabled
UINT32 NumSaGvPointsEnabled
Count of the total number of SAGV Points enabled.
Definition: MemInfoHob.h:257
MEMORY_PLATFORM_DATA
Memory Platform Data Hob.
Definition: MemInfoHob.h:315
DIMM_INFO::MdSocket
UINT8 MdSocket
MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
Definition: MemInfoHob.h:221
bmCold
@ bmCold
Cold boot.
Definition: MemInfoHob.h:143
DIMM_INFO
Memory SMBIOS & OC Memory Data Hob.
Definition: MemInfoHob.h:209
HOB_SAGV_TIMING_OUT::DataRate
UINT32 DataRate
The memory rate for the current SaGv Point in units of MT/s.
Definition: MemInfoHob.h:250
HOB_SAGV_TIMING_OUT::IpTiming
MRC_IP_TIMING IpTiming
Timings used for this entry's corresponding SaGv Point - IP specific.
Definition: MemInfoHob.h:252
MrcBootModeDelim
@ MrcBootModeDelim
This value ensures the enum size is consistent on both sides of the PPI.
Definition: MemInfoHob.h:148
bmS3
@ bmS3
S3 resume.
Definition: MemInfoHob.h:145
DIMM_INFO::Status
UINT8 Status
See MrcDimmStatus for the definition of this field.
Definition: MemInfoHob.h:210
DIMM_INFO::Speed
UINT16 Speed
The maximum capable speed of the device, in MHz.
Definition: MemInfoHob.h:220
HOB_SAGV_INFO
This data structure contains SAGV config values that are considered output by the MRC.
Definition: MemInfoHob.h:256
DIMM_INFO::RankInDimm
UINT8 RankInDimm
The number of ranks in this DIMM.
Definition: MemInfoHob.h:215
HOB_SAGV_TIMING_OUT::JedecTiming
MRC_CH_TIMING JedecTiming
Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec.
Definition: MemInfoHob.h:251
MrcBootModeMax
@ MrcBootModeMax
MRC_BOOT_MODE enumeration maximum value.
Definition: MemInfoHob.h:147
HOB_SAGV_INFO::SaGvPointMask
UINT32 SaGvPointMask
Bit mask where each bit indicates an enabled SAGV point.
Definition: MemInfoHob.h:258
DIMM_INFO::SpdModuleType
UINT8 SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:217
bmFast
@ bmFast
Fast boot.
Definition: MemInfoHob.h:146
DIMM_INFO::SpdModuleMemoryBusWidth
UINT8 SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:218
bmWarm
@ bmWarm
Warm boot.
Definition: MemInfoHob.h:144
MAX_SPD_SAVE
#define MAX_SPD_SAVE
Defines taken from MRC so avoid having to include MrcInterface.h.
Definition: MemInfoHob.h:92
MRC_BOOT_MODE
MRC_BOOT_MODE
Definition: MemInfoHob.h:142
DIMM_INFO::SpdDramDeviceType
UINT8 SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
Definition: MemInfoHob.h:216
DIMM_INFO::DimmCapacity
UINT32 DimmCapacity
DIMM size in MBytes.
Definition: MemInfoHob.h:212
HOB_SAGV_TIMING_OUT
This data structure contains per-SaGv timing values that are considered output by the MRC.
Definition: MemInfoHob.h:249
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
Classes | Macros | Typedefs | Enumerations
MemoryConfig.h File Reference

Policy definition of Memory Config Block. More...

Go to the source code of this file.

Classes

struct | SPD_DATA_BUFFER
SPD Data Buffer. More...
struct | SA_MEMORY_DQDQS_MAPPING
DqDqs Mapping. More...
struct | SA_MEMORY_RCOMP
Rcomp Policies. More...
struct | SPD_OFFSET_TABLE
SPD Offset Table. More...
struct | SA_ADDRESS_DECODE
SA memory address decode. More...
struct | SA_FUNCTION_CALLS
Function calls into the SA. More...
struct | SA_MEMORY_FUNCTIONS
Function calls into the MRC. More...
struct | MEMORY_CONFIGURATION
Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection. More...
struct | MEMORY_CONFIG_NO_CRC
Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detection. More...

Macros

#define | MRC_MAX_RCOMP_TARGETS 5
MEMORY_CONFIGURATION interface definitions.
#define | MEM_CFG_MAX_CONTROLLERS 2
Memory SubSystem Definitions.
#define | PEI_MR_SMRAM_ABSEG_MASK 0x01
SMRAM Memory Range.

Typedefs

typedef UINT8(* | SA_IO_READ_8) (UINTN IoAddress)
CPU I/O port 8-bit read.
typedef UINT16(* | SA_IO_READ_16) (UINTN IoAddress)
CPU I/O port 16-bit read.
typedef UINT32(* | SA_IO_READ_32) (UINTN IoAddress)
CPU I/O port 32-bit read.
typedef UINT8(* | SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value)
CPU I/O port 8-bit write.
typedef UINT16(* | SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value)
CPU I/O port 16-bit write.
typedef UINT32(* | SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value)
CPU I/O port 32-bit write.
typedef UINT8(* | SA_MMIO_READ_8) (UINTN Address)
Memory Mapped I/O port 8-bit read.
typedef UINT16(* | SA_MMIO_READ_16) (UINTN Address)
Memory Mapped I/O port 16-bit read.
typedef UINT32(* | SA_MMIO_READ_32) (UINTN Address)
Memory Mapped I/O port 32-bit read.
typedef UINT64(* | SA_MMIO_READ_64) (UINTN Address)
Memory Mapped I/O port 64-bit read.
typedef UINT8(* | SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value)
Memory Mapped I/O port 8-bit write.
typedef UINT16(* | SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value)
Memory Mapped I/O port 16-bit write.
typedef UINT32(* | SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value)
Memory Mapped I/O port 32-bit write.
typedef UINT64(* | SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value)
Memory Mapped I/O port 64-bit write.
typedef UINT8(* | SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status)
Smbus 8-bit read.
typedef UINT16(* | SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status)
Smbus 16-bit read.
typedef UINT8(* | SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status)
Smbus 8-bit write.
typedef UINT16(* | SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status)
Smbus 16-bit write.
typedef UINT32(* | SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI device address.
typedef UINT32(* | SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI express device address.
typedef VOID(* | SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year)
Get the current time value.
typedef UINT64(* | SA_GET_CPU_TIME) (VOID)
The current CPU time in milliseconds.
typedef VOID *(* | SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes)
Perform byte copy operation.
typedef VOID *(* | SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value)
Perform byte initialization operation.
typedef VOID *(* | SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value)
Perform word initialization operation.
typedef VOID *(* | SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value)
Perform dword initialization operation.
typedef UINT64(* | SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits)
Left shift the 64-bit data value by specified number of bits.
typedef UINT64(* | SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits)
Right shift the 64-bit data value by specified number of bits.
typedef UINT64(* | SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier)
Multiply a 64-bit data value by a 32-bit data value.
typedef UINT64(* | SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder)
Divide a 64-bit data value by a 64-bit data value.
typedef BOOLEAN(* | SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize)
Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
typedef BOOLEAN(* | SA_GET_RANDOM_NUMBER) (UINT32 *Rand)
Get the next random 32-bit number.
typedef EFI_STATUS(* | SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status)
Perform a CPU mailbox read.
typedef EFI_STATUS(* | SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status)
Perform a CPU mailbox write.
typedef UINT32(* | SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd)
Get the current memory voltage (VDD).
typedef UINT32(* | SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value)
Set the memory voltage (VDD) to the given value.
typedef UINT32(* | SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp)
Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
typedef UINT32(* | SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch)
Check point that is called at various points in the MRC.
typedef VOID(* | SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber)
Typically used to display to the I/O port 80h.
typedef UINT8(* | SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel)
Returns whether Channel is or is not present.
typedef INT32(* | SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format,...)
Print to output stream/device.
typedef VOID(* | SA_DEBUG_PRINT) (VOID *String)
Output a string to the debug stream/device.
typedef UINT32(* | SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam)
Change the margin.
typedef UINT8(* | SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb)
Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
typedef VOID(* | SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost)
Move CMD/CTL/CLK/CKE PIs during training.
typedef VOID(* | SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait)
Update the Vref value and wait until it is stable.
typedef UINT8(* | SA_GET_RTC_CMOS) (UINT8 Location)
Get the current value of the specified RTC CMOS location.
typedef UINT64(* | SA_MSR_READ_64) (UINT32 Location)
Get the current value of the specified MSR location.
typedef UINT64(* | SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data)
Set the current value of the specified MSR location.
typedef VOID(* | SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus)
Hook function after returning from MrcStartMemoryConfiguration()
typedef VOID(* | SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue)
Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
typedef VOID(* | SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs)
Delay (stall) for the given amount of nanoseconds.

Enumerations

enum | SA_SPD
SA SPD profile selections. More...
enum | SPD_BOOT_MODE
Define the boot modes used by the SPD read function. More...

Detailed Description

Policy definition of Memory Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemoryConfig.h.

Enumeration Type Documentation

◆ SA_SPD

enum SA_SPD

SA SPD profile selections.

Enumerator
DEFAULT_SPD | Standard DIMM profile select.
CUSTOM_PROFILE | XMP enthusiast settings: User specifies various override values.
XMP_PROFILE_1 | XMP enthusiast settings: XMP profile #1.
XMP_PROFILE_2 | XMP enthusiast settings: XMP profile #2.
XMP_PROFILE_3 | XMP enthusiast settings: XMP profile #3.
XMP_USER_PROFILE_4 | XMP enthusiast settings: XMP user profile #4.
XMP_USER_PROFILE_5 | XMP enthusiast settings: XMP user profile #5.
SPDProfileMax | Ensures SA_SPD is UINT8.

Definition at line 107 of file MemoryConfig.h.

◆ SPD_BOOT_MODE

enum SPD_BOOT_MODE

Define the boot modes used by the SPD read function.

Enumerator
SpdCold | Cold boot.
SpdWarm | Warm boot.
SpdS3 | S3 resume.
SpdFast | Fast boot.
SpdBootModeMax | Delimiter.

Definition at line 121 of file MemoryConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
MemoryConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition of Memory Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEMORY_CONFIG_H_
36 #define _MEMORY_CONFIG_H_
37
38
39 #pragma pack(push, 1)
40
41 // MEMORY_CONFIGURATION_REVISION:
42 // 3 - Adds DDR5 PDA Enumeration training
43 // 4 - Adds LPDDR4 Command Mirroring
44 // 5 - Adds PprEnableType
45 // 6 - Removed IbeccParity
46 // 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
47 // 8 - Adds LpddrRttCa, LpddrRttWr
48 // 9 - Adds VddqVoltage, VppVoltage
49 // 10 - Changes PprEnableType to PprEnable
50 // 11 - Changes DisableDimmChannel to DisableChannel
51 // 12 - Added DIMMDFE
52 // 13 - Added ExtendedBankHashing
53 // 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
54 // 15 - Added DynamicMemoryBoost
55 // 16 - Added ReuseAdlDdr5Board
56 // 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
57 // 18 - Added DebugValue
58 // 19 - Added McRefreshRate; Deprecated McRefresh2X
59 // 20 - Added RealtimeMemoryFrequency
60 // 21 - Added PeriodicDcc and LpMode
61 // 22 - Added Tx Dqs Dcc Training
62 // 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
63 // 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
64 // 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
65 // 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
66 // 27 - Added DRAMDCA
67 // 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
68 // 29 - Added LctCmdEyeWidth
69 // 30 - Added FirstDimmBitMaskEcc
70 // 31 - Added Lp5BankMode
71 // 32 - Added WRDS
72 #define MEMORY_CONFIGURATION_REVISION 32
73
74 // MEMORY_CONFIG_NO_CRC_REVISION:
75 // 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
76 #define MEMORY_CONFIG_NO_CRC_REVISION 3
77
78 ///
79 /// MEMORY_CONFIGURATION interface definitions
80 ///
81 #define MRC_MAX_RCOMP_TARGETS 5
82 ///
83 /// Memory SubSystem Definitions
84 ///
85 #define MEM_CFG_MAX_CONTROLLERS 2
86 #define MEM_CFG_MAX_CHANNELS 4
87 #define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2
88 #define MEM_CFG_MAX_DIMMS 2
89 #define MEM_CFG_MAX_RANKS_PER_DIMM 2
90 #define MEM_CFG_NUM_BYTES_MAPPED 2
91 #define MEM_CFG_MAX_SPD_SIZE 1024
92 #define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
93 #define MEM_CFG_MAX_ROWS (MEM_CFG_MAX_RANKS_PER_DIMM * MEM_CFG_MAX_SOCKETS)
94 #ifndef MEM_MAX_SAGV_POINTS
95 #define MEM_MAX_SAGV_POINTS 4
96 #endif
97 #define MEM_MAX_IBECC_REGIONS 8
98 ///
99 /// SMRAM Memory Range
100 ///
101 #define PEI_MR_SMRAM_ABSEG_MASK 0x01
102 #define PEI_MR_SMRAM_HSEG_MASK 0x02
103
104 ///
105 /// SA SPD profile selections.
106 ///
107 typedef enum {
108 DEFAULT_SPD, ///< Standard DIMM profile select.
109 CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
110 XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
111 XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
112 XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
113 XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
114 XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
115 SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
116 } SA_SPD;
117
118 ///
119 /// Define the boot modes used by the SPD read function.
120 ///
121 typedef enum {
122 SpdCold, ///< Cold boot
123 SpdWarm, ///< Warm boot
124 SpdS3, ///< S3 resume
125 SpdFast, ///< Fast boot
126 SpdBootModeMax ///< Delimiter
127 } SPD_BOOT_MODE;
128
129 /**
130 SPD Data Buffer
131 **/
132 typedef struct {
133 UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
134 //Next Field Offset 2048
135 } SPD_DATA_BUFFER;
136
137 /**
138 DqDqs Mapping
139 **/
140 typedef struct {
141 UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
142 UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
143 //Next Field Offset 16
144 } SA_MEMORY_DQDQS_MAPPING;
145
146 /**
147 Rcomp Policies
148 **/
149 typedef struct {
150 UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
151 UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
152 //Next Field Offset 16
153 } SA_MEMORY_RCOMP;
154
155 /**
156 SPD Offset Table
157 **/
158 typedef struct {
159 UINT16 Start; ///< Offset 0
160 UINT16 End; ///< Offset 2
161 UINT8 BootMode; ///< Offset 4
162 UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
163 } SPD_OFFSET_TABLE;
164
165 ///
166 /// SA memory address decode.
167 ///
168 typedef struct
169 {
170 UINT8 Controller; ///< Offset 0 Zero based Controller number
171 UINT8 Channel; ///< Offset 1 Zero based Channel number
172 UINT8 Dimm; ///< Offset 2 Zero based DIMM number
173 UINT8 Rank; ///< Offset 3 Zero based Rank number
174 UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
175 UINT8 Bank; ///< Offset 5 Zero based Bank number
176 UINT16 Cas; ///< Offset 6 Zero based CAS number
177 UINT32 Ras; ///< Offset 8 Zero based RAS number
178 } SA_ADDRESS_DECODE;
179
180 typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
181 typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
182 typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
183 typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
184 typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
185 typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
186 typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
187 typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
188 typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
189 typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
190 typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
191 typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
192 typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
193 typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
194 typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
195 typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
196 typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
197 typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
198 typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
199 typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
200 typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
201 typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
202 typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
203 typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
204 typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
205 typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
206 typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
207 typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
208 typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
209 typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
210 typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
211 typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
212 typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
213 typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
214 typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
215 typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
216 typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
217 typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
218 typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
219 typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
220 typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
221 typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
222 typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
223 typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
224 typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
225 typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
226 typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
227 typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
228 typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
229 typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
230 typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
231 typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
232 typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
233 typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
234 typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
235
236
237 ///
238 /// Function calls into the SA.
239 ///
240 typedef struct {
241 SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
242 SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
243 SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
244 SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
245 SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
246 SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
247 SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
248 SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
249 SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
250 SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
251 SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
252 SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
253 SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
254 SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
255 SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
256 SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
257 SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
258 SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
259 SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
260 SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
261 SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
262 SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
263 SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
264 SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
265 SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
266 SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
267 SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
268 SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
269 SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
270 SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
271 SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
272 SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
273 SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
274 SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
275 SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
276 SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
277 SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
278 SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
279 SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
280 SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
281 SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
282 SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
283 SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
284 SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
285 SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
286 SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
287 } SA_FUNCTION_CALLS;
288
289 ///
290 /// Function calls into the MRC.
291 ///
292 typedef struct {
293 SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
294 SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
295 SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
296 SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
297 SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
298 SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
299 } SA_MEMORY_FUNCTIONS;
300
301 /**
302 Memory Configuration
303 The contents of this structure are CRC'd by the MRC for option change detection.
304 This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
305 Revision history is at the top of this file
306 **/
307 typedef struct {
308 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
309 UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
310 UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
311
312 UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
313
314 // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
315 UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
316 UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
317 UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
318 UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
319 UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
320 UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
321 UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
322 UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
323 UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
324 UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
325 UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
326 UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
327 UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
328 UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
329 UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
330 UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
331
332 UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
333 UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
334 UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
335 UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
336 UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
337 UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
338 UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
339 UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
340 UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
341 UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
342 UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
343 UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
344 UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
345 UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
346 UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
347 UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
348 UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
349 UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
350 UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
351 UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
352 UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
353 UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
354 UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
355 UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
356 UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
357 UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
358 UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
359 /**
360 Channel Hash Enable.\n
361 NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
362 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
363 **/
364 UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
365 UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
366 UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
367
368 /// Training Algorithms 1 Offset 84
369 UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
370 UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
371 UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
372 UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
373 UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
374 UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
375 UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
376 UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
377 UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
378 UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
379 UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
380 UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
381 UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
382 UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
383 UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
384 UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
385 UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
386 UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
387 UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
388 UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
389 UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
390 UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
391 UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
392 UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
393 UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
394 UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
395 UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
396 UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
397 UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
398 UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
399 UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
400 UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
401 /// Training Algorithms 2 Offset 88
402 UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
403 UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
404 UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
405 UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
406 UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
407 UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
408 UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
409 UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
410 UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
411 UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
412 UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
413 UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
414 UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
415 UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
416 UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
417 UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
418 UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
419 UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
420 UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
421 UINT32 ReservedBits2 :13; ///< Bits 19:31 - Reserved
422
423 UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
424 UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
425 UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
426 UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
427 UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
428 UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
429 UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
430 UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
431 UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
432 UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
433 UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
434 UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
435 UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
436 UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
437 UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
438 UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
439 UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
440 UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
441 UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
442 UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
443 UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
444 UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
445 UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
446 UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
447 UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
448 UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
449 UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
450 UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
451 UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
452 UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
453 UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
454 UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
455 BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
456 UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
457 UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
458 UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
459 UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
460 UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
461 UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
462 UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
463 UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
464 UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
465 UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
466 UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
467 UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
468 UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
469 UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
470 UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
471 UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
472 UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
473 UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
474 UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
475 UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
476 UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
477 UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
478 UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
479 UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
480
481 UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
482 UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
483 UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
484 UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
485 UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
486 UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
487 UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
488 UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
489 UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
490 UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
491 UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
492 UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
493 UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
494 UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
495 UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
496 UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
497 UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
498 UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
499 UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
500 UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
501 UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
502 UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
503 UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
504 UINT32 DebugValue; ///< Offset 276 Debug Value for general use
505 UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
506 UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
507 UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
508 UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
509 UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
510 UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
511 UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
512 UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
513 UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
514 UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
515 UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
516
517
518 UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
519 UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
520 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
521 ///< For each MC, the first DIMM to be populated should be set to '1'.
522 ///< Note: this mask is only for non-ECC DIMM.
523 UINT8 UserBd; ///< Offset 319 MrcBoardType
524 ///< 1 - Desktop 1DPC
525 ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
526 ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
527 ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
528 ///< 5 - ULT Mobile
529 UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
530 UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
531 UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
532 UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
533 UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
534 UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
535 UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
536 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
537 UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
538 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
539 UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
540 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
541 UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
542 ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
543 UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
544 UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
545 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
546 ///< For each MC, the first DIMM to be populated should be set to '1'.
547 ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
548 ///< be populated firstly.
549 ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
550 UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
551 UINT8 Reserved336[6]; ///< Offset 338-343 Reserved for natural alignment
552 } MEMORY_CONFIGURATION;
553
554 /// Memory Configuration
555 /// The contents of this structure are not CRC'd by the MRC for option change detection.
556 /// <b>Revision 1</b>: - Initial version.
557 /// <b>Revision 2</b>: - Added MemTestOnWarmBoot
558 typedef struct {
559 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
560 SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
561 SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
562 SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
563 SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
564 SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
565 UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
566 UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
567 UINT32 ReservedBits5:31;
568 /**
569 Sets the serial debug message level\n
570 0x00 = Disabled\n
571 0x01 = Errors only\n
572 0x02 = Errors and Warnings\n
573 <b>0x03 = Errors, Warnings, and Info</b>\n
574 0x04 = Errors, Warnings, Info, and Events\n
575 0x05 = Displays Memory Init Execution Time Summary only\n
576 **/
577 UINT8 SerialDebugLevel; ///< Offset 260
578 UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
579 UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
580 } MEMORY_CONFIG_NO_CRC;
581 #pragma pack(pop)
582
583 #endif // _MEMORY_CONFIG_H_
MEMORY_CONFIGURATION::IbeccOperationMode
UINT32 IbeccOperationMode
Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address ran...
Definition: MemoryConfig.h:348
MEMORY_CONFIGURATION::Ddr4DdpSharedClock
UINT32 Ddr4DdpSharedClock
Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=Not shared,...
Definition: MemoryConfig.h:339
MEMORY_CONFIGURATION::WRTC1D
UINT32 WRTC1D
Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:377
SA_IO_WRITE_16
UINT16(* SA_IO_WRITE_16)(UINTN IoAddress, UINT16 Value)
CPU I/O port 16-bit write.
Definition: MemoryConfig.h:184
MEMORY_CONFIGURATION::DIMMRONT
UINT32 DIMMRONT
Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:381
MEMORY_CONFIGURATION::tRFC
UINT16 tRFC
Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:319
MEMORY_CONFIGURATION::DRAMDCA
UINT32 DRAMDCA
BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:419
MEMORY_CONFIGURATION::Vc1ReadMeter
UINT32 Vc1ReadMeter
Bit 4 - VC1 Read Metering Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:336
SA_FUNCTION_CALLS::MmioWrite64
SA_MMIO_WRITE_64 MmioWrite64
Offset 52: - Memory Mapped I/O port 64-bit write.
Definition: MemoryConfig.h:254
MEMORY_CONFIGURATION::SrefCfgEna
UINT32 SrefCfgEna
Bit 9 - Enable Self Refresh: 0=Disable, 1=Enable
Definition: MemoryConfig.h:432
MEMORY_CONFIGURATION::SagvSwitchFactorGT
UINT8 SagvSwitchFactorGT
Offset 321 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:530
MEMORY_CONFIGURATION::RmtPerTask
UINT32 RmtPerTask
Bit 10 - Rank Margin Tool Per Task. 0 = Disabled, 1 = Enabled.
Definition: MemoryConfig.h:342
MEMORY_CONFIGURATION::Lp5CccConfig
UINT32 Lp5CccConfig
Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel...
Definition: MemoryConfig.h:469
MEMORY_CONFIGURATION::IbeccErrInjMask
UINT64 IbeccErrInjMask
Offset 264 Mask to match against for ECC error injection.
Definition: MemoryConfig.h:500
MEMORY_CONFIGURATION::ForceSingleRank
UINT32 ForceSingleRank
Bit 16 - TRUE means use Rank0 only (in each DIMM): 0=Disable, 1=Enable.
Definition: MemoryConfig.h:439
SA_FUNCTION_CALLS::DebugPrint
SA_DEBUG_PRINT DebugPrint
Offset 152: - Output a string to the debug stream/device.
Definition: MemoryConfig.h:279
MEMORY_CONFIGURATION::tWTR_S
UINT16 tWTR_S
Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:512
MEMORY_CONFIGURATION::RDTC1D
UINT32 RDTC1D
Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:379
MEMORY_CONFIGURATION::EnablePwrDnLpddr
UINT32 EnablePwrDnLpddr
Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, 1=BIOS control
Definition: MemoryConfig.h:431
MEMORY_CONFIGURATION::RMTBIT
UINT32 RMTBIT
Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:415
SA_FUNCTION_CALLS::MmioWrite32
SA_MMIO_WRITE_32 MmioWrite32
Offset 48: - Memory Mapped I/O port 32-bit write.
Definition: MemoryConfig.h:253
MEMORY_CONFIGURATION::SaGv
UINT8 SaGv
Offset 110 SA GV: 0=Disabled, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled.
Definition: MemoryConfig.h:456
MEMORY_CONFIGURATION::ProbelessTrace
UINT8 ProbelessTrace
Offset 77 Probeless Trace: 0=Disabled, 1=Enabled
Definition: MemoryConfig.h:358
MEMORY_CONFIGURATION::WRDSUDT
UINT32 WRDSUDT
Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently.
Definition: MemoryConfig.h:400
MEMORY_CONFIGURATION::tRCDtRP
UINT16 tRCDtRP
Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTO...
Definition: MemoryConfig.h:316
MEMORY_CONFIG_NO_CRC::PlatformMemorySize
UINT64 PlatformMemorySize
Offset 248 The minimum platform memory size required to pass control into DXE.
Definition: MemoryConfig.h:565
MEMORY_CONFIGURATION::TXTCODQS
UINT32 TXTCODQS
Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:409
MEMORY_CONFIGURATION::VttTermination
UINT32 VttTermination
Bit 17 - Vtt Termination for Data ODT: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:440
MEMORY_CONFIGURATION::tRFC4
UINT16 tRFC4
Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0...
Definition: MemoryConfig.h:507
MEMORY_CONFIGURATION::PeriodicDcc
UINT32 PeriodicDcc
Bit 22 - Periodic DCC: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:353
MEMORY_CONFIGURATION::ERDMPRTC2D
UINT32 ERDMPRTC2D
Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this s...
Definition: MemoryConfig.h:371
SA_MEMORY_FUNCTIONS::MrcChannelExist
SA_CHANNEL_EXIST MrcChannelExist
Offset 0: - Returns whether Channel is or is not present.
Definition: MemoryConfig.h:293
MEMORY_CONFIGURATION::RefClk
UINT8 RefClk
Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, 0x00 = 133MHz
Definition: MemoryConfig.h:458
SA_FUNCTION_CALLS::SetMemDword
SA_MEMORY_SET_DWORD SetMemDword
Offset 100: - Perform dword initialization operation.
Definition: MemoryConfig.h:266
MEMORY_CONFIGURATION::DIMMDFE
UINT32 DIMMDFE
BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:417
SA_FUNCTION_CALLS::SmbusRead8
SA_SMBUS_READ_8 SmbusRead8
Offset 56: - Smbus 8-bit read.
Definition: MemoryConfig.h:255
MEMORY_CONFIGURATION::EnCmdRate
UINT8 EnCmdRate
Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, 7=3 CMDs, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs,...
Definition: MemoryConfig.h:459
SA_MEMORY_FUNCTIONS::ShiftPiCommandTrain
SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain
Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
Definition: MemoryConfig.h:297
MEMORY_CONFIGURATION::ExtendedBankHashing
UINT8 ExtendedBankHashing
Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; 1 = Enabled
Definition: MemoryConfig.h:494
MEMORY_CONFIGURATION::FreqLimitMixedConfig
UINT16 FreqLimitMixedConfig
Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config....
Definition: MemoryConfig.h:518
SPD_DATA_BUFFER
SPD Data Buffer.
Definition: MemoryConfig.h:132
MEMORY_CONFIGURATION::RCVENC1D
UINT32 RCVENC1D
Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to...
Definition: MemoryConfig.h:398
SA_MMIO_WRITE_8
UINT8(* SA_MMIO_WRITE_8)(UINTN Address, UINT8 Value)
Memory Mapped I/O port 8-bit write.
Definition: MemoryConfig.h:190
SA_FUNCTION_CALLS::MrcDramReset
SA_MRC_DRAM_RESET MrcDramReset
Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
Definition: MemoryConfig.h:284
SA_ADDRESS_DECODE::Dimm
UINT8 Dimm
Offset 2 Zero based DIMM number.
Definition: MemoryConfig.h:172
MEMORY_CONFIG_NO_CRC::MrcCall
SA_MEMORY_FUNCTIONS MrcCall
Offset 212 Function calls into the MRC.
Definition: MemoryConfig.h:561
MEMORY_CONFIG_NO_CRC::MemTestOnWarmBoot
UINT8 MemTestOnWarmBoot
Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, 1=Enabled
Definition: MemoryConfig.h:578
SA_FUNCTION_CALLS::RightShift64
SA_RIGHT_SHIFT_64 RightShift64
Offset 108: - Right shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:268
SA_CHANGE_MARGIN
UINT32(* SA_CHANGE_MARGIN)(VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam)
Change the margin.
Definition: MemoryConfig.h:224
MEMORY_CONFIGURATION::RDEQT
UINT32 RDEQT
Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting...
Definition: MemoryConfig.h:385
MEMORY_CONFIGURATION::RealtimeMemoryFrequency
UINT8 RealtimeMemoryFrequency
Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an X...
Definition: MemoryConfig.h:497
SPDProfileMax
@ SPDProfileMax
Ensures SA_SPD is UINT8.
Definition: MemoryConfig.h:115
MEMORY_CONFIGURATION::PerBankRefresh
BOOLEAN PerBankRefresh
Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that supp...
Definition: MemoryConfig.h:455
MEMORY_CONFIGURATION::WriteThreshold
UINT8 WriteThreshold
Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asse...
Definition: MemoryConfig.h:486
MEMORY_CONFIGURATION::Ibecc
UINT32 Ibecc
Bit 15 - In-band ECC: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:347
MEMORY_CONFIGURATION::DCC
UINT32 DCC
Training Algorithms 2 Offset 88.
Definition: MemoryConfig.h:402
MEMORY_CONFIGURATION::EnablePwrDn
UINT32 EnablePwrDn
Bit 7 - Enable Power Down control for DDR: 0=PCODE control, 1=BIOS control
Definition: MemoryConfig.h:430
MEMORY_CONFIGURATION::CMDVC
UINT32 CMDVC
Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this se...
Definition: MemoryConfig.h:391
XMP_USER_PROFILE_4
@ XMP_USER_PROFILE_4
XMP enthusiast settings: XMP user profile #4.
Definition: MemoryConfig.h:113
SPD_OFFSET_TABLE::End
UINT16 End
Offset 2.
Definition: MemoryConfig.h:160
MEMORY_CONFIGURATION::MrcTimeMeasure
UINT32 MrcTimeMeasure
Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: 0=Disable,...
Definition: MemoryConfig.h:423
SA_FUNCTION_CALLS::GetCpuTime
SA_GET_CPU_TIME GetCpuTime
Offset 84: - The current CPU time in milliseconds.
Definition: MemoryConfig.h:262
MEMORY_CONFIGURATION::RDTC2D
UINT32 RDTC2D
Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this ...
Definition: MemoryConfig.h:388
MEMORY_CONFIGURATION::DynamicMemoryBoost
UINT8 DynamicMemoryBoost
Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Pr...
Definition: MemoryConfig.h:495
MEMORY_CONFIGURATION::tFAW
UINT16 tFAW
Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:323
SA_FUNCTION_CALLS::DebugHook
SA_DEBUG_HOOK DebugHook
Offset 148: - Typically used to display to the I/O port 80h.
Definition: MemoryConfig.h:278
SA_FUNCTION_CALLS::IoRead16
SA_IO_READ_16 IoRead16
Offset 4: - CPU I/O port 16-bit read.
Definition: MemoryConfig.h:242
MEMORY_CONFIGURATION::RDVC2D
UINT32 RDVC2D
Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:390
MEMORY_CONFIGURATION::GearRatio
UINT8 GearRatio
Offset 130 Gear mode when SAGV is disabled: 0=Auto, 1 - Gear1, 2 - Gear2, 4 - Gear4.
Definition: MemoryConfig.h:472
MEMORY_CONFIGURATION::PDA
UINT32 PDA
BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting f...
Definition: MemoryConfig.h:416
SA_SET_MEMORY_VDD
UINT32(* SA_SET_MEMORY_VDD)(VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value)
Set the memory voltage (VDD) to the given value.
Definition: MemoryConfig.h:217
SA_SHIFT_PI_COMMAND_TRAIN
VOID(* SA_SHIFT_PI_COMMAND_TRAIN)(VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost)
Move CMD/CTL/CLK/CKE PIs during training.
Definition: MemoryConfig.h:226
MEMORY_CONFIGURATION::DqPinsInterleaved
UINT32 DqPinsInterleaved
Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: 0=Disable,...
Definition: MemoryConfig.h:425
SA_MEMORY_RCOMP::RcompResistor
UINT16 RcompResistor
Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms.
Definition: MemoryConfig.h:150
MEMORY_CONFIG_NO_CRC::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: MemoryConfig.h:559
SA_MEMORY_SET_DWORD
VOID *(* SA_MEMORY_SET_DWORD)(VOID *Buffer, UINTN NumDwords, UINT32 Value)
Perform dword initialization operation.
Definition: MemoryConfig.h:205
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_16GB
UINT16 FreqLimitMixedConfig_1R1R_16GB
Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one cha...
Definition: MemoryConfig.h:537
SA_IO_WRITE_32
UINT32(* SA_IO_WRITE_32)(UINTN IoAddress, UINT32 Value)
CPU I/O port 32-bit write.
Definition: MemoryConfig.h:185
SA_CHANNEL_EXIST
UINT8(* SA_CHANNEL_EXIST)(VOID *Outputs, UINT8 Channel)
Returns whether Channel is or is not present.
Definition: MemoryConfig.h:221
MEMORY_CONFIGURATION::Ratio
UINT8 Ratio
Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. 0 = Auto
Definition: MemoryConfig.h:357
SA_GET_RANDOM_NUMBER
BOOLEAN(* SA_GET_RANDOM_NUMBER)(UINT32 *Rand)
Get the next random 32-bit number.
Definition: MemoryConfig.h:213
MEMORY_CONFIGURATION::SagvHeuristicsUpControl
UINT8 SagvHeuristicsUpControl
Offset 324 Sagv duration in ms before heuristics up: 1 , 50=Maximum, default 1ms.
Definition: MemoryConfig.h:533
MEMORY_CONFIGURATION::PowerDownMode
UINT8 PowerDownMode
Offset 119 CKE Power Down Mode: 0xFF=AUTO, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode.
Definition: MemoryConfig.h:465
MEMORY_CONFIGURATION::ReservedBits2
UINT32 ReservedBits2
Bits 19:31 - Reserved.
Definition: MemoryConfig.h:421
MEMORY_CONFIGURATION::RhSelect
UINT32 RhSelect
Bit 22-23 - RH Select: 0=Disable, 1=RFM, 2=pTRR.
Definition: MemoryConfig.h:445
MEMORY_CONFIGURATION::tRRD
UINT16 tRRD
Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:320
SA_FUNCTION_CALLS::LeftShift64
SA_LEFT_SHIFT_64 LeftShift64
Offset 104: - Left shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:267
SA_FUNCTION_CALLS::IoWrite8
SA_IO_WRITE_8 IoWrite8
Offset 12: - CPU I/O port 8-bit write.
Definition: MemoryConfig.h:244
MEMORY_CONFIGURATION::ExitOnFailure
UINT32 ExitOnFailure
Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, 1=Enable
Definition: MemoryConfig.h:442
MEMORY_CONFIG_NO_CRC
Memory Configuration The contents of this structure are not CRC'd by the MRC for option change detect...
Definition: MemoryConfig.h:558
MEMORY_CONFIGURATION::ThrtCkeMinTmrLpddr
UINT8 ThrtCkeMinTmrLpddr
Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, 0x00=Default
Definition: MemoryConfig.h:454
MEMORY_CONFIGURATION::PwdwnIdleCounter
UINT8 PwdwnIdleCounter
Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, 0x80=0x80 DCLK
Definition: MemoryConfig.h:466
MEMORY_CONFIGURATION::MsHashInterleaveBit
UINT8 MsHashInterleaveBit
Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9.
Definition: MemoryConfig.h:471
MEMORY_CONFIGURATION::tCWL
UINT16 tCWL
Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:324
SA_DELAY_NS
VOID(* SA_DELAY_NS)(VOID *GlobalData, UINT32 DelayNs)
Delay (stall) for the given amount of nanoseconds.
Definition: MemoryConfig.h:233
MEMORY_CONFIGURATION::LCT
UINT32 LCT
Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from...
Definition: MemoryConfig.h:392
SA_FUNCTION_CALLS::IoWrite16
SA_IO_WRITE_16 IoWrite16
Offset 16: - CPU I/O port 16-bit write.
Definition: MemoryConfig.h:245
SA_FUNCTION_CALLS::IoWrite32
SA_IO_WRITE_32 IoWrite32
Offset 20: - CPU I/O port 32-bit write.
Definition: MemoryConfig.h:246
MEMORY_CONFIGURATION::ForceSingleSubchannel
UINT32 ForceSingleSubchannel
Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): 0=Disable, 1=Enable.
Definition: MemoryConfig.h:337
MEMORY_CONFIGURATION::LpDqsOscEn
UINT32 LpDqsOscEn
Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, 1=Enable
Definition: MemoryConfig.h:341
MEMORY_CONFIGURATION::MobilePlatform
UINT32 MobilePlatform
Bit 14 - Memory controller device id indicates: TRUE if mobile, FALSE if not. Note: This will be auto...
Definition: MemoryConfig.h:437
MEMORY_CONFIGURATION::RMC
UINT32 RMC
Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from ...
Definition: MemoryConfig.h:399
SA_FUNCTION_CALLS::IoRead32
SA_IO_READ_32 IoRead32
Offset 8: - CPU I/O port 32-bit read.
Definition: MemoryConfig.h:243
MEMORY_CONFIGURATION::MarginLimitL2
UINT16 MarginLimitL2
Offset 240 Margin limit check L2 threshold: 100=Default
Definition: MemoryConfig.h:489
MEMORY_CONFIGURATION::AutoSelfRefreshSupport
UINT32 AutoSelfRefreshSupport
Bit 12 - FALSE = No auto self refresh support, TRUE = auto self refresh support
Definition: MemoryConfig.h:435
MEMORY_CONFIGURATION::DdrFreqLimit
UINT16 DdrFreqLimit
Offset 104 Memory Frequency limit: 0 = Auto, or memory speed value in MT/s: 1067, 1333,...
Definition: MemoryConfig.h:451
MEMORY_CONFIGURATION::ReuseAdlSDdr5Board
UINT32 ReuseAdlSDdr5Board
Bit 21 - Indicate whether adl ddr5 board is reused.
Definition: MemoryConfig.h:352
SA_FUNCTION_CALLS::GetSpdData
SA_GET_SPD_DATA GetSpdData
Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to t...
Definition: MemoryConfig.h:271
SA_MMIO_READ_16
UINT16(* SA_MMIO_READ_16)(UINTN Address)
Memory Mapped I/O port 16-bit read.
Definition: MemoryConfig.h:187
MEMORY_CONFIGURATION::SmramMask
UINT8 SmramMask
Offset 79 Reserved memory ranges for SMRAM.
Definition: MemoryConfig.h:365
MEMORY_CONFIGURATION::tCCD_L
UINT16 tCCD_L
Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:511
SA_DEBUG_PRINT
VOID(* SA_DEBUG_PRINT)(VOID *String)
Output a string to the debug stream/device.
Definition: MemoryConfig.h:223
MEMORY_CONFIGURATION::PVTTDNLP
UINT32 PVTTDNLP
Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:412
SA_GET_SPD_DATA
BOOLEAN(* SA_GET_SPD_DATA)(SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize)
Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data struct...
Definition: MemoryConfig.h:210
SA_FUNCTION_CALLS::GetPciDeviceAddress
SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress
Offset 72: - Get PCI device address.
Definition: MemoryConfig.h:259
SA_SMBUS_READ_8
UINT8(* SA_SMBUS_READ_8)(UINTN Address, RETURN_STATUS *Status)
Smbus 8-bit read.
Definition: MemoryConfig.h:194
SPD_OFFSET_TABLE::Start
UINT16 Start
Offset 0.
Definition: MemoryConfig.h:159
SA_FUNCTION_CALLS::GetRtcCmos
SA_GET_RTC_CMOS GetRtcCmos
Offset 156: - Get the current value of the specified RTC CMOS location.
Definition: MemoryConfig.h:280
MEMORY_CONFIGURATION::LpddrRttCa
UINT8 LpddrRttCa
Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto.
Definition: MemoryConfig.h:491
MEMORY_CONFIGURATION::SafeMode
UINT32 SafeMode
Bit 12 - Define if safe mode is enabled for MC/IO.
Definition: MemoryConfig.h:344
MEMORY_CONFIGURATION::Lp5BankMode
UINT8 Lp5BankMode
Offset 337 LP5 Bank Mode.
Definition: MemoryConfig.h:550
SA_SET_MEMORY_PMIC_VOLTAGE
UINT32(* SA_SET_MEMORY_PMIC_VOLTAGE)(VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp)
Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
Definition: MemoryConfig.h:218
MEMORY_CONFIGURATION::RemapEnable
UINT32 RemapEnable
Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable,...
Definition: MemoryConfig.h:334
SA_MEMORY_FUNCTIONS::MrcUpdateVref
SA_UPDATE_VREF MrcUpdateVref
Offset 20: - Update the Vref value and wait until it is stable.
Definition: MemoryConfig.h:298
MEMORY_CONFIGURATION::EccErrInjCount
UINT32 EccErrInjCount
Offset 312 Number of transactions between ECC error injection.
Definition: MemoryConfig.h:515
SA_DEBUG_HOOK
VOID(* SA_DEBUG_HOOK)(VOID *GlobalData, UINT16 DisplayDebugNumber)
Typically used to display to the I/O port 80h.
Definition: MemoryConfig.h:220
SA_SMBUS_WRITE_16
UINT16(* SA_SMBUS_WRITE_16)(UINTN Address, UINT16 Value, RETURN_STATUS *Status)
Smbus 16-bit write.
Definition: MemoryConfig.h:197
MEMORY_CONFIGURATION::MrcFastBoot
UINT32 MrcFastBoot
Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, 1=Enable
Definition: MemoryConfig.h:424
SA_GET_PCI_DEVICE_ADDRESS
UINT32(* SA_GET_PCI_DEVICE_ADDRESS)(UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI device address.
Definition: MemoryConfig.h:198
MEMORY_CONFIGURATION::ChHashOverride
UINT32 ChHashOverride
Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically t...
Definition: MemoryConfig.h:349
SA_FUNCTION_CALLS::SetMemWord
SA_MEMORY_SET_WORD SetMemWord
Offset 96: - Perform word initialization operation.
Definition: MemoryConfig.h:265
MEMORY_CONFIGURATION::ChHashEnable
UINT32 ChHashEnable
Bit 6 - Channel Hash Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:429
SA_FUNCTION_CALLS::GetMemoryVdd
SA_GET_MEMORY_VDD GetMemoryVdd
Offset 136: - Get the current memory voltage (VDD).
Definition: MemoryConfig.h:275
MEMORY_CONFIGURATION::CmdMirror
UINT8 CmdMirror
Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel...
Definition: MemoryConfig.h:484
MEMORY_CONFIGURATION::Write0
UINT32 Write0
Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, 1=Enable
Definition: MemoryConfig.h:351
MEMORY_CONFIGURATION::tRTP
UINT16 tRTP
Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:322
SA_SMBUS_READ_16
UINT16(* SA_SMBUS_READ_16)(UINTN Address, RETURN_STATUS *Status)
Smbus 16-bit read.
Definition: MemoryConfig.h:195
MEMORY_CONFIGURATION::RetrainOnFastFail
UINT8 RetrainOnFastFail
Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled,...
Definition: MemoryConfig.h:464
SA_ADDRESS_DECODE
SA memory address decode.
Definition: MemoryConfig.h:169
SA_MRC_RETURN_FROM_SMC
VOID(* SA_MRC_RETURN_FROM_SMC)(VOID *GlobalData, UINT32 MrcStatus)
Hook function after returning from MrcStartMemoryConfiguration()
Definition: MemoryConfig.h:231
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MEMORY_CONFIGURATION::RDVC1D
UINT32 RDVC1D
Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:403
MEMORY_CONFIGURATION::Lfsr0Mask
UINT8 Lfsr0Mask
Offset 233 RH pTRR LFSR0 Mask.
Definition: MemoryConfig.h:482
MEMORY_CONFIGURATION::EpgEnable
UINT8 EpgEnable
Offset 115 Enable Energy Performance Gain.
Definition: MemoryConfig.h:461
MEMORY_CONFIGURATION::LpddrRttWr
UINT8 LpddrRttWr
Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto.
Definition: MemoryConfig.h:490
SA_FUNCTION_CALLS::MrcReturnFromSmc
SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc
Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
Definition: MemoryConfig.h:283
MEM_CFG_MAX_CONTROLLERS
#define MEM_CFG_MAX_CONTROLLERS
Memory SubSystem Definitions.
Definition: MemoryConfig.h:85
MEMORY_CONFIGURATION::RDMPRT
UINT32 RDMPRT
Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the ...
Definition: MemoryConfig.h:372
MEMORY_CONFIGURATION::CMDSR
UINT32 CMDSR
Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:406
MEMORY_CONFIGURATION::Idd3p
UINT16 Idd3p
Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
Definition: MemoryConfig.h:330
SA_MEMORY_FUNCTIONS::MrcPrintf
SA_PRINTF MrcPrintf
Offset 4: - Print to output stream/device.
Definition: MemoryConfig.h:294
SA_CHECKPOINT
UINT32(* SA_CHECKPOINT)(VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch)
Check point that is called at various points in the MRC.
Definition: MemoryConfig.h:219
MEMORY_CONFIGURATION::RefreshHpWm
UINT32 RefreshHpWm
Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
Definition: MemoryConfig.h:447
SpdBootModeMax
@ SpdBootModeMax
Delimiter.
Definition: MemoryConfig.h:126
MEMORY_CONFIGURATION::FirstDimmBitMask
UINT8 FirstDimmBitMask
Offset 318 Defines which DIMM should be populated first on a 2DPC board.
Definition: MemoryConfig.h:519
MEMORY_CONFIGURATION::MsHashEnable
UINT32 MsHashEnable
Bit 13 - Controller Hash Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:345
MEMORY_CONFIGURATION::tRAS
UINT16 tRAS
Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:317
MEMORY_CONFIGURATION::tRFC2
UINT16 tRFC2
Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0...
Definition: MemoryConfig.h:506
SA_MEMORY_SET_BYTE
VOID *(* SA_MEMORY_SET_BYTE)(VOID *Buffer, UINTN NumBytes, UINT8 Value)
Perform byte initialization operation.
Definition: MemoryConfig.h:203
MEMORY_CONFIGURATION::VppVoltage
UINT16 VppVoltage
Offset 246 DRAM voltage (Vpp) in millivolts: 0=Platform Default (no override), 1800=1....
Definition: MemoryConfig.h:493
MEMORY_CONFIGURATION::TAT
UINT32 TAT
Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting ...
Definition: MemoryConfig.h:394
MEMORY_CONFIGURATION::tWTR_L
UINT16 tWTR_L
Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:510
SA_MEMORY_FUNCTIONS::MrcSignExtend
SA_SIGN_EXTEND MrcSignExtend
Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
Definition: MemoryConfig.h:296
MEMORY_CONFIGURATION::SOT
UINT32 SOT
Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting f...
Definition: MemoryConfig.h:370
MEMORY_CONFIG_NO_CRC::RcompData
SA_MEMORY_RCOMP * RcompData
Offset 244 DDR RCOMP resistors and target values.
Definition: MemoryConfig.h:564
XMP_USER_PROFILE_5
@ XMP_USER_PROFILE_5
XMP enthusiast settings: XMP user profile #5.
Definition: MemoryConfig.h:114
CUSTOM_PROFILE
@ CUSTOM_PROFILE
XMP enthusiast settings: User specifies various override values.
Definition: MemoryConfig.h:109
MEMORY_CONFIGURATION::SimicsFlag
UINT32 SimicsFlag
Bit 6 - Option to Enable SIMICS: 0=Disable, 1=Enable
Definition: MemoryConfig.h:338
MEMORY_CONFIGURATION::VddVoltage
UINT16 VddVoltage
Offset 58 DRAM voltage (Vdd) in millivolts: 0=Platform Default (no override), 1200=1....
Definition: MemoryConfig.h:328
MEMORY_CONFIGURATION::PprEnable
UINT8 PprEnable
Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR.
Definition: MemoryConfig.h:487
MEMORY_CONFIG_NO_CRC::SaCall
SA_FUNCTION_CALLS SaCall
Offset 28 Function calls into the SA.
Definition: MemoryConfig.h:560
SA_FUNCTION_CALLS
Function calls into the SA.
Definition: MemoryConfig.h:240
SA_ADDRESS_DECODE::Controller
UINT8 Controller
Offset 0 Zero based Controller number.
Definition: MemoryConfig.h:170
MEMORY_CONFIGURATION::ChHashMask
UINT16 ChHashMask
Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum),...
Definition: MemoryConfig.h:450
MEMORY_CONFIGURATION::DebugValue
UINT32 DebugValue
Offset 276 Debug Value for general use.
Definition: MemoryConfig.h:504
SA_PRINTF
INT32(* SA_PRINTF)(VOID *Debug, UINT32 Level, char *Format,...)
Print to output stream/device.
Definition: MemoryConfig.h:222
MEMORY_CONFIGURATION::WRDS
UINT32 WRDS
BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:420
MEMORY_CONFIGURATION::TrainTrace
UINT32 TrainTrace
Bit 11 - Trained state tracing debug. 0 = Disabled, 1 = Enabled.
Definition: MemoryConfig.h:343
MEMORY_CONFIGURATION::RDODTT
UINT32 RDODTT
Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:384
MEMORY_CONFIGURATION::ALIASCHK
UINT32 ALIASCHK
Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, 1=Enable
Definition: MemoryConfig.h:397
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB
UINT16 FreqLimitMixedConfig_1R1R_8GB
Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channe...
Definition: MemoryConfig.h:535
MEMORY_CONFIGURATION::ThrtCkeMinTmr
UINT8 ThrtCkeMinTmr
Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, 0x00=Default
Definition: MemoryConfig.h:453
MEMORY_CONFIGURATION::Lfsr1Mask
UINT8 Lfsr1Mask
Offset 234 RH pTRR LFSR1 Mask.
Definition: MemoryConfig.h:483
MEMORY_CONFIGURATION
Memory Configuration The contents of this structure are CRC'd by the MRC for option change detection.
Definition: MemoryConfig.h:307
SA_MSR_READ_64
UINT64(* SA_MSR_READ_64)(UINT32 Location)
Get the current value of the specified MSR location.
Definition: MemoryConfig.h:229
SA_RIGHT_SHIFT_64
UINT64(* SA_RIGHT_SHIFT_64)(UINT64 Data, UINTN NumBits)
Right shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:207
MEMORY_CONFIGURATION::IbeccErrInjControl
UINT8 IbeccErrInjControl
Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Add...
Definition: MemoryConfig.h:496
MEMORY_CONFIGURATION::EnhancedInterleave
UINT32 EnhancedInterleave
Bit 4 - Enhanced Interleave Mode: 0=Disable, 1=Enable
Definition: MemoryConfig.h:427
SA_FUNCTION_CALLS::GetRandomNumber
SA_GET_RANDOM_NUMBER GetRandomNumber
Offset 124: - Get the next random 32-bit number.
Definition: MemoryConfig.h:272
MEMORY_CONFIGURATION::BClkFrequency
UINT32 BClkFrequency
Offset 80 Base reference clock value, in Hertz: 100000000 = 100Hz, 125000000=125Hz,...
Definition: MemoryConfig.h:366
MEMORY_CONFIGURATION::DIMMODTT
UINT32 DIMMODTT
Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the...
Definition: MemoryConfig.h:380
MEMORY_CONFIGURATION::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: MemoryConfig.h:308
MEMORY_CONFIGURATION::DIMMODTCA
UINT32 DIMMODTCA
Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:408
MEMORY_CONFIGURATION::FreqLimitMixedConfig_2R2R
UINT16 FreqLimitMixedConfig_2R2R
Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel...
Definition: MemoryConfig.h:541
MEMORY_CONFIG_NO_CRC::CleanMemory
UINT32 CleanMemory
Offset 256 Ask MRC to clear memory content: FALSE=Do not Clear Memory; TRUE=Clear Memory.
Definition: MemoryConfig.h:566
SA_IO_WRITE_8
UINT8(* SA_IO_WRITE_8)(UINTN IoAddress, UINT8 Value)
CPU I/O port 8-bit write.
Definition: MemoryConfig.h:183
SA_GET_MEMORY_VDD
UINT32(* SA_GET_MEMORY_VDD)(VOID *GlobalData, UINT32 DefaultVdd)
Get the current memory voltage (VDD).
Definition: MemoryConfig.h:216
MEMORY_CONFIG_NO_CRC::DqDqsMap
SA_MEMORY_DQDQS_MAPPING * DqDqsMap
Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
Definition: MemoryConfig.h:563
SPD_BOOT_MODE
SPD_BOOT_MODE
Define the boot modes used by the SPD read function.
Definition: MemoryConfig.h:121
MEMORY_CONFIGURATION::LctCmdEyeWidth
UINT16 LctCmdEyeWidth
Offset 334 LCT Command eyewidth.
Definition: MemoryConfig.h:543
MEMORY_CONFIGURATION::SpdProfileSelected
UINT8 SpdProfileSelected
Offset 31 SPD XMP profile selection - for XMP supported DIMM: 0=Default DIMM profile,...
Definition: MemoryConfig.h:312
SA_MMIO_READ_64
UINT64(* SA_MMIO_READ_64)(UINTN Address)
Memory Mapped I/O port 64-bit read.
Definition: MemoryConfig.h:189
MEMORY_CONFIGURATION::WRVC2D
UINT32 WRVC2D
Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change thi...
Definition: MemoryConfig.h:389
SA_FUNCTION_CALLS::GetRtcTime
SA_GET_RTC_TIME GetRtcTime
Offset 80: - Get the current time value.
Definition: MemoryConfig.h:261
MEMORY_CONFIGURATION::McRefreshRate
UINT8 McRefreshRate
Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4...
Definition: MemoryConfig.h:502
SA_FUNCTION_CALLS::GetPcieDeviceAddress
SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress
Offset 76: - Get PCI express device address.
Definition: MemoryConfig.h:260
SA_MMIO_READ_8
UINT8(* SA_MMIO_READ_8)(UINTN Address)
Memory Mapped I/O port 8-bit read.
Definition: MemoryConfig.h:186
SA_DIV_U64_U64
UINT64(* SA_DIV_U64_U64)(UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder)
Divide a 64-bit data value by a 64-bit data value.
Definition: MemoryConfig.h:209
SA_FUNCTION_CALLS::MultU64x32
SA_MULT_U64_U32 MultU64x32
Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
Definition: MemoryConfig.h:269
XMP_PROFILE_2
@ XMP_PROFILE_2
XMP enthusiast settings: XMP profile #2.
Definition: MemoryConfig.h:111
MEMORY_CONFIGURATION::JWRL
UINT32 JWRL
Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setti...
Definition: MemoryConfig.h:374
SA_FUNCTION_CALLS::SetMemoryPmicVoltage
SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage
Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
Definition: MemoryConfig.h:286
MEMORY_CONFIGURATION::ScramblerSupport
UINT32 ScramblerSupport
Bit 3 - Memory scrambler support: 0=Disable, 1=Enable
Definition: MemoryConfig.h:335
SA_FUNCTION_CALLS::CpuMailboxWrite
SA_CPU_MAILBOX_WRITE CpuMailboxWrite
Offset 132: - Perform a CPU mailbox write.
Definition: MemoryConfig.h:274
SA_MMIO_WRITE_64
UINT64(* SA_MMIO_WRITE_64)(UINTN Address, UINT64 Value)
Memory Mapped I/O port 64-bit write.
Definition: MemoryConfig.h:193
MEMORY_CONFIGURATION::EccSupport
UINT32 EccSupport
Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, 1=Enable
Definition: MemoryConfig.h:332
SA_IO_READ_32
UINT32(* SA_IO_READ_32)(UINTN IoAddress)
CPU I/O port 32-bit read.
Definition: MemoryConfig.h:182
MEMORY_CONFIGURATION::tREFI
UINT16 tREFI
Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=...
Definition: MemoryConfig.h:325
SA_ADDRESS_DECODE::BankGroup
UINT8 BankGroup
Offset 4 Zero based Bank Group number.
Definition: MemoryConfig.h:174
MEMORY_CONFIGURATION::Size
UINT16 Size
Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
Definition: MemoryConfig.h:309
MEMORY_CONFIGURATION::WRDSEQT
UINT32 WRDSEQT
Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended t...
Definition: MemoryConfig.h:382
SA_SPD
SA_SPD
SA SPD profile selections.
Definition: MemoryConfig.h:107
MEMORY_CONFIGURATION::MarginLimitCheck
UINT8 MarginLimitCheck
Offset 239 Margin limit check enable: 0=Disable, 1=L1 only, 2=L2 only, 3=Both L1 and L2.
Definition: MemoryConfig.h:488
SA_FUNCTION_CALLS::CpuMailboxRead
SA_CPU_MAILBOX_READ CpuMailboxRead
Offset 128: - Perform a CPU mailbox read.
Definition: MemoryConfig.h:273
MEMORY_CONFIGURATION::SrefCfgIdleTmr
UINT16 SrefCfgIdleTmr
Offset 100 Self Refresh idle timer: 512=Minimal, 65535=Maximum.
Definition: MemoryConfig.h:449
MEMORY_CONFIGURATION::UserBudgetEnable
UINT8 UserBudgetEnable
Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable,...
Definition: MemoryConfig.h:463
SA_SIGN_EXTEND
UINT8(* SA_SIGN_EXTEND)(UINT8 Value, UINT8 OldMsb, UINT8 NewMsb)
Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
Definition: MemoryConfig.h:225
MEMORY_CONFIGURATION::EccDftEn
UINT32 EccDftEn
Bit 19 - ECC DFT support option.
Definition: MemoryConfig.h:350
MEMORY_CONFIGURATION::WeaklockEn
UINT32 WeaklockEn
Bit 5 - Weak Lock Enable: 0=Disable, 1=Enable
Definition: MemoryConfig.h:428
MEMORY_CONFIGURATION::MaxRttWr
UINT8 MaxRttWr
Offset 106 Maximum DIMM RTT_WR to use in power training: 0=ODT Off, 1 = 120 ohms.
Definition: MemoryConfig.h:452
MEMORY_CONFIGURATION::NewFeatureEnable2
UINT32 NewFeatureEnable2
Bit 21 - Generic enable knob for new feature set 2 0: Disable ; 1: Enable.
Definition: MemoryConfig.h:444
MEMORY_CONFIGURATION::SagvSwitchFactorIA
UINT8 SagvSwitchFactorIA
Offset 320 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:529
SA_IO_READ_16
UINT16(* SA_IO_READ_16)(UINTN IoAddress)
CPU I/O port 16-bit read.
Definition: MemoryConfig.h:181
MEMORY_CONFIGURATION::PciData
UINT16 PciData
Offset 56 Pci data register address: 0xCFC=Default
Definition: MemoryConfig.h:327
MEMORY_CONFIGURATION::ExtTemperatureSupport
UINT32 ExtTemperatureSupport
Bit 13 - FALSE = No extended temperature support, TRUE = extended temperature support
Definition: MemoryConfig.h:436
MEMORY_CONFIG_NO_CRC::SpdData
SPD_DATA_BUFFER * SpdData
Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
Definition: MemoryConfig.h:562
SA_ADDRESS_DECODE::Cas
UINT16 Cas
Offset 6 Zero based CAS number.
Definition: MemoryConfig.h:176
XMP_PROFILE_1
@ XMP_PROFILE_1
XMP enthusiast settings: XMP profile #1.
Definition: MemoryConfig.h:110
SA_MSR_WRITE_64
UINT64(* SA_MSR_WRITE_64)(UINT32 Location, UINT64 Data)
Set the current value of the specified MSR location.
Definition: MemoryConfig.h:230
SA_FUNCTION_CALLS::MmioRead8
SA_MMIO_READ_8 MmioRead8
Offset 24: - Memory Mapped I/O port 8-bit read.
Definition: MemoryConfig.h:247
MEMORY_CONFIGURATION::RMT
UINT32 RMT
Bit 26 - Enable/Disable Rank Margin Tool function: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:395
MEMORY_CONFIGURATION::UserBd
UINT8 UserBd
Offset 319 MrcBoardType 1 - Desktop 1DPC 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated ...
Definition: MemoryConfig.h:523
SA_MEMORY_FUNCTIONS
Function calls into the MRC.
Definition: MemoryConfig.h:292
SA_FUNCTION_CALLS::MrcDelayNs
SA_DELAY_NS MrcDelayNs
Offset 176 - Delay (stall) for the given amount of nanoseconds.
Definition: MemoryConfig.h:285
SA_ADDRESS_DECODE::Ras
UINT32 Ras
Offset 8 Zero based RAS number.
Definition: MemoryConfig.h:177
MEMORY_CONFIGURATION::Idd3n
UINT16 Idd3n
Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
Definition: MemoryConfig.h:329
MEMORY_CONFIGURATION::McRefresh2X
UINT8 McRefresh2X
Offset 232 Deprecated from revision 19, use McRefreshRate instead.
Definition: MemoryConfig.h:481
SA_MEMORY_SET_WORD
VOID *(* SA_MEMORY_SET_WORD)(VOID *Buffer, UINTN NumWords, UINT16 Value)
Perform word initialization operation.
Definition: MemoryConfig.h:204
MEMORY_CONFIGURATION::ERDTC2D
UINT32 ERDTC2D
Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change th...
Definition: MemoryConfig.h:376
SA_CPU_MAILBOX_WRITE
EFI_STATUS(* SA_CPU_MAILBOX_WRITE)(UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status)
Perform a CPU mailbox write.
Definition: MemoryConfig.h:215
SA_MRC_DRAM_RESET
VOID(* SA_MRC_DRAM_RESET)(UINT32 PciEBaseAddress, UINT32 ResetValue)
Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
Definition: MemoryConfig.h:232
MEMORY_CONFIGURATION::tCL
UINT16 tCL
Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AU...
Definition: MemoryConfig.h:315
SA_MULT_U64_U32
UINT64(* SA_MULT_U64_U32)(UINT64 Multiplicand, UINT32 Multiplier)
Multiply a 64-bit data value by a 32-bit data value.
Definition: MemoryConfig.h:208
MEMORY_CONFIGURATION::FirstDimmBitMaskEcc
UINT8 FirstDimmBitMaskEcc
Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
Definition: MemoryConfig.h:544
SA_GET_RTC_CMOS
UINT8(* SA_GET_RTC_CMOS)(UINT8 Location)
Get the current value of the specified RTC CMOS location.
Definition: MemoryConfig.h:228
MEMORY_CONFIGURATION::ChHashInterleaveBit
UINT8 ChHashInterleaveBit
Channel Hash Enable.
Definition: MemoryConfig.h:364
MEMORY_CONFIGURATION::ThrtCkeMinDefeat
UINT32 ThrtCkeMinDefeat
Bit 11 - Throttler CKE min defeature: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:434
MEMORY_CONFIGURATION::CMDDSEQ
UINT32 CMDDSEQ
Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:407
MEMORY_CONFIGURATION::VddqVoltage
UINT16 VddqVoltage
Offset 244 DRAM voltage (Vddq) in millivolts: 0=Platform Default (no override), 1200=1....
Definition: MemoryConfig.h:492
MEMORY_CONFIGURATION::RDVREFDC
UINT32 RDVREFDC
Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:413
MEMORY_CONFIGURATION::PciIndex
UINT16 PciIndex
Offset 54 Pci index register address: 0xCF8=Default
Definition: MemoryConfig.h:326
MEMORY_CONFIG_NO_CRC::SerialDebugLevel
UINT8 SerialDebugLevel
Sets the serial debug message level 0x00 = Disabled 0x01 = Errors only 0x02 = Errors and Warnings ...
Definition: MemoryConfig.h:577
MEMORY_CONFIGURATION::EccErrInjAddress
UINT64 EccErrInjAddress
Offset 296 Address to match against for ECC error injection.
Definition: MemoryConfig.h:513
SpdS3
@ SpdS3
S3 resume.
Definition: MemoryConfig.h:124
MEMORY_CONFIGURATION::WRTC2D
UINT32 WRTC2D
Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:387
SPD_OFFSET_TABLE::BootMode
UINT8 BootMode
Offset 4.
Definition: MemoryConfig.h:161
MEMORY_CONFIGURATION::RefreshPanicWm
UINT32 RefreshPanicWm
Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
Definition: MemoryConfig.h:446
MEMORY_CONFIGURATION::tRRD_S
UINT16 tRRD_S
Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:509
SA_ADDRESS_DECODE::Rank
UINT8 Rank
Offset 3 Zero based Rank number.
Definition: MemoryConfig.h:173
MEMORY_CONFIGURATION::UserThresholdEnable
UINT8 UserThresholdEnable
Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable,...
Definition: MemoryConfig.h:462
MEMORY_CONFIGURATION::MrcSafeConfig
UINT32 MrcSafeConfig
Bit 1 - MRC Safe Mode: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:333
SA_GET_PCIE_DEVICE_ADDRESS
UINT32(* SA_GET_PCIE_DEVICE_ADDRESS)(UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset)
Get PCI express device address.
Definition: MemoryConfig.h:199
MEMORY_CONFIGURATION::Force1Dpc
UINT32 Force1Dpc
Bit 15 - TRUE means force one DIMM per channel, FALSE means no limit
Definition: MemoryConfig.h:438
MEMORY_CONFIGURATION::SagvHeuristicsDownControl
UINT8 SagvHeuristicsDownControl
Offset 325 Sagv duration in ms before heuristics down: 1 , 50=Maximum, default 1ms.
Definition: MemoryConfig.h:534
SA_FUNCTION_CALLS::MmioWrite16
SA_MMIO_WRITE_16 MmioWrite16
Offset 44: - Memory Mapped I/O port 16-bit write.
Definition: MemoryConfig.h:252
MEMORY_CONFIGURATION::MEMTST
UINT32 MEMTST
Bit 27 - Enable/Disable Memory Test function: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:396
MEMORY_CONFIGURATION::VddSettleWaitTime
UINT32 VddSettleWaitTime
Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC ...
Definition: MemoryConfig.h:448
SA_MEMORY_DQDQS_MAPPING
DqDqs Mapping.
Definition: MemoryConfig.h:140
SpdFast
@ SpdFast
Fast boot.
Definition: MemoryConfig.h:125
SpdWarm
@ SpdWarm
Warm boot.
Definition: MemoryConfig.h:123
MEMORY_CONFIGURATION::VttCompForVsshi
UINT32 VttCompForVsshi
Bit 18 - Enable/Disable Vtt Comparator For Vsshi: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:441
MEMORY_CONFIGURATION::IbeccErrInjCount
UINT32 IbeccErrInjCount
Offset 252 Number of transactions between ECC error injection.
Definition: MemoryConfig.h:498
MEMORY_CONFIGURATION::tRFCpb
UINT16 tRFCpb
Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:505
MEMORY_CONFIGURATION::NModeSupport
UINT8 NModeSupport
Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: 0=AUTO, 1=1N,...
Definition: MemoryConfig.h:457
SA_MEMORY_FUNCTIONS::MrcChangeMargin
SA_CHANGE_MARGIN MrcChangeMargin
Offset 8: - Change the margin.
Definition: MemoryConfig.h:295
SA_FUNCTION_CALLS::SmbusWrite16
SA_SMBUS_WRITE_16 SmbusWrite16
Offset 68: - Smbus 16-bit write.
Definition: MemoryConfig.h:258
SA_ADDRESS_DECODE::Channel
UINT8 Channel
Offset 1 Zero based Channel number.
Definition: MemoryConfig.h:171
SA_MEMORY_COPY
VOID *(* SA_MEMORY_COPY)(VOID *Destination, CONST VOID *Source, UINTN NumBytes)
Perform byte copy operation.
Definition: MemoryConfig.h:202
MEMORY_CONFIGURATION::RDAPT
UINT32 RDAPT
Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this sett...
Definition: MemoryConfig.h:386
SA_MMIO_WRITE_16
UINT16(* SA_MMIO_WRITE_16)(UINTN Address, UINT16 Value)
Memory Mapped I/O port 16-bit write.
Definition: MemoryConfig.h:191
SA_FUNCTION_CALLS::MmioRead32
SA_MMIO_READ_32 MmioRead32
Offset 32: - Memory Mapped I/O port 32-bit read.
Definition: MemoryConfig.h:249
SA_FUNCTION_CALLS::DivU64x64
SA_DIV_U64_U64 DivU64x64
Offset 116: - Divide a 64-bit data value by a 64-bit data value.
Definition: MemoryConfig.h:270
MEMORY_CONFIGURATION::ECT
UINT32 ECT
Training Algorithms 1 Offset 84.
Definition: MemoryConfig.h:369
MEMORY_CONFIGURATION::SharedZqPin
UINT32 SharedZqPin
Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=Not Shared,...
Definition: MemoryConfig.h:340
MEMORY_CONFIGURATION::LpMode
UINT32 LpMode
Bit 23:24 - LPMode: 0=Auto, 1=Enabled, 2=Disabled, 3=Reserved.
Definition: MemoryConfig.h:354
MEMORY_CONFIGURATION::AllowOppRefBelowWriteThrehold
UINT8 AllowOppRefBelowWriteThrehold
Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
Definition: MemoryConfig.h:485
MEMORY_CONFIGURATION::EccErrInjMask
UINT64 EccErrInjMask
Offset 304 Mask to match against for ECC error injection.
Definition: MemoryConfig.h:514
DEFAULT_SPD
@ DEFAULT_SPD
Standard DIMM profile select.
Definition: MemoryConfig.h:108
MEMORY_CONFIGURATION::SagvSwitchFactorIO
UINT8 SagvSwitchFactorIO
Offset 322 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:531
MEMORY_CONFIGURATION::Refresh2X
UINT8 Refresh2X
Offset 114 Refresh 2x: 0=Disable, 1=Enable for WARM or HOT, 2=Enable for HOT only.
Definition: MemoryConfig.h:460
MEMORY_CONFIGURATION::RsvdO64B25to31
UINT32 RsvdO64B25to31
Bits 25:31 reserved.
Definition: MemoryConfig.h:355
MEMORY_CONFIGURATION::TXTCO
UINT32 TXTCO
Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:404
SA_FUNCTION_CALLS::MmioWrite8
SA_MMIO_WRITE_8 MmioWrite8
Offset 40: - Memory Mapped I/O port 8-bit write.
Definition: MemoryConfig.h:251
MEMORY_CONFIGURATION::tWR
UINT16 tWR
Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=AU...
Definition: MemoryConfig.h:318
SA_FUNCTION_CALLS::CopyMem
SA_MEMORY_COPY CopyMem
Offset 88: - Perform byte copy operation.
Definition: MemoryConfig.h:263
MEMORY_CONFIGURATION::tRRD_L
UINT16 tRRD_L
Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: ...
Definition: MemoryConfig.h:508
MEMORY_CONFIGURATION::CMDDRUD
UINT32 CMDDRUD
Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:410
SA_MMIO_WRITE_32
UINT32(* SA_MMIO_WRITE_32)(UINTN Address, UINT32 Value)
Memory Mapped I/O port 32-bit write.
Definition: MemoryConfig.h:192
SA_FUNCTION_CALLS::WriteMsr64
SA_MSR_WRITE_64 WriteMsr64
Offset 164 - Set the current value of the specified MSR location.
Definition: MemoryConfig.h:282
SA_FUNCTION_CALLS::SmbusRead16
SA_SMBUS_READ_16 SmbusRead16
Offset 60: - Smbus 16-bit read.
Definition: MemoryConfig.h:256
MEMORY_CONFIGURATION::SagvSwitchFactorStall
UINT8 SagvSwitchFactorStall
Offset 323 Sagv Switch Factor: 1 , 50=Maximum, default 30.
Definition: MemoryConfig.h:532
SpdCold
@ SpdCold
Cold boot.
Definition: MemoryConfig.h:122
MEMORY_CONFIGURATION::RMTLoopCount
UINT8 RMTLoopCount
Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal,...
Definition: MemoryConfig.h:470
SA_FUNCTION_CALLS::IoRead8
SA_IO_READ_8 IoRead8
Offset 0: - CPU I/O port 8-bit read.
Definition: MemoryConfig.h:241
MEMORY_CONFIGURATION::DisPgCloseIdleTimeout
UINT32 DisPgCloseIdleTimeout
Bit 14 - Disable Page Close Idle Timeout: 0=Enable, 1=Disable
Definition: MemoryConfig.h:346
SA_IO_READ_8
UINT8(* SA_IO_READ_8)(UINTN IoAddress)
CPU I/O port 8-bit read.
Definition: MemoryConfig.h:180
MEMORY_CONFIGURATION::WRSRT
UINT32 WRSRT
Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting fr...
Definition: MemoryConfig.h:383
SA_GET_CPU_TIME
UINT64(* SA_GET_CPU_TIME)(VOID)
The current CPU time in milliseconds.
Definition: MemoryConfig.h:201
MEMORY_CONFIGURATION::EWRTC2D
UINT32 EWRTC2D
Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change t...
Definition: MemoryConfig.h:375
MEMORY_CONFIGURATION::RTL
UINT32 RTL
Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this settin...
Definition: MemoryConfig.h:393
SA_FUNCTION_CALLS::SmbusWrite8
SA_SMBUS_WRITE_8 SmbusWrite8
Offset 64: - Smbus 8-bit write.
Definition: MemoryConfig.h:257
MEMORY_CONFIGURATION::RCVET
UINT32 RCVET
Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting fro...
Definition: MemoryConfig.h:373
SPD_OFFSET_TABLE
SPD Offset Table.
Definition: MemoryConfig.h:158
MRC_MAX_RCOMP_TARGETS
#define MRC_MAX_RCOMP_TARGETS
MEMORY_CONFIGURATION interface definitions.
Definition: MemoryConfig.h:81
MEMORY_CONFIGURATION::IbeccErrInjAddress
UINT64 IbeccErrInjAddress
Offset 256 Address to match against for ECC error injection.
Definition: MemoryConfig.h:499
SA_FUNCTION_CALLS::CheckPoint
SA_CHECKPOINT CheckPoint
Offset 144: - Check point that is called at various points in the MRC.
Definition: MemoryConfig.h:277
SA_ADDRESS_DECODE::Bank
UINT8 Bank
Offset 5 Zero based Bank number.
Definition: MemoryConfig.h:175
XMP_PROFILE_3
@ XMP_PROFILE_3
XMP enthusiast settings: XMP profile #3.
Definition: MemoryConfig.h:112
SA_UPDATE_VREF
VOID(* SA_UPDATE_VREF)(VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait)
Update the Vref value and wait until it is stable.
Definition: MemoryConfig.h:227
SA_FUNCTION_CALLS::MmioRead16
SA_MMIO_READ_16 MmioRead16
Offset 28: - Memory Mapped I/O port 16-bit read.
Definition: MemoryConfig.h:248
SA_FUNCTION_CALLS::ReadMsr64
SA_MSR_READ_64 ReadMsr64
Offset 160: - Get the current value of the specified MSR location.
Definition: MemoryConfig.h:281
MEMORY_CONFIGURATION::ThrtCkeMinDefeatLpddr
UINT32 ThrtCkeMinDefeatLpddr
Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, 1=Enable
Definition: MemoryConfig.h:433
SA_LEFT_SHIFT_64
UINT64(* SA_LEFT_SHIFT_64)(UINT64 Data, UINTN NumBits)
Left shift the 64-bit data value by specified number of bits.
Definition: MemoryConfig.h:206
MEMORY_CONFIGURATION::tWTR
UINT16 tWTR
Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=A...
Definition: MemoryConfig.h:321
SA_MMIO_READ_32
UINT32(* SA_MMIO_READ_32)(UINTN Address)
Memory Mapped I/O port 32-bit read.
Definition: MemoryConfig.h:188
MEMORY_CONFIGURATION::RankInterleave
UINT32 RankInterleave
Bit 3 - Rank Interleave Mode: 0=Disable, 1=Enable
Definition: MemoryConfig.h:426
SA_SMBUS_WRITE_8
UINT8(* SA_SMBUS_WRITE_8)(UINTN Address, UINT8 Value, RETURN_STATUS *Status)
Smbus 8-bit write.
Definition: MemoryConfig.h:196
MEMORY_CONFIGURATION::TXDQSDCC
UINT32 TXDQSDCC
BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:418
MEMORY_CONFIGURATION::FreqLimitMixedConfig_1R1R_8GB_16GB
UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB
Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one ...
Definition: MemoryConfig.h:539
SA_GET_RTC_TIME
VOID(* SA_GET_RTC_TIME)(UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year)
Get the current time value.
Definition: MemoryConfig.h:200
MEMORY_CONFIGURATION::VDDQT
UINT32 VDDQT
Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:414
MEMORY_CONFIGURATION::MsHashMask
UINT16 MsHashMask
Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum),...
Definition: MemoryConfig.h:468
MEMORY_CONFIGURATION::RefreshWm
UINT8 RefreshWm
Offset 272 Refresh Watermarks, 0 = Low, 1 = High
Definition: MemoryConfig.h:501
MEMORY_CONFIGURATION::HobBufferSize
UINT8 HobBufferSize
Offset 30 Size of HOB buffer for MRC.
Definition: MemoryConfig.h:310
MEMORY_CONFIGURATION::WRVC1D
UINT32 WRVC1D
Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this...
Definition: MemoryConfig.h:378
SA_CPU_MAILBOX_READ
EFI_STATUS(* SA_CPU_MAILBOX_READ)(UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status)
Perform a CPU mailbox read.
Definition: MemoryConfig.h:214
SA_MEMORY_RCOMP
Rcomp Policies.
Definition: MemoryConfig.h:149
MEMORY_CONFIGURATION::CLKTCO
UINT32 CLKTCO
Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:405
MEMORY_CONFIGURATION::VCCDLLBP
UINT32 VCCDLLBP
Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
Definition: MemoryConfig.h:411
SA_FUNCTION_CALLS::MmioRead64
SA_MMIO_READ_64 MmioRead64
Offset 36: - Memory Mapped I/O port 64-bit read.
Definition: MemoryConfig.h:250
MEMORY_CONFIGURATION::CmdRanksTerminated
UINT8 CmdRanksTerminated
Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating an...
Definition: MemoryConfig.h:467
SA_FUNCTION_CALLS::SetMem
SA_MEMORY_SET_BYTE SetMem
Offset 92: - Perform byte initialization operation.
Definition: MemoryConfig.h:264
MEMORY_CONFIGURATION::Ddr4OneDpc
UINT8 Ddr4OneDpc
Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only,...
Definition: MemoryConfig.h:473
MEMORY_CONFIGURATION::NewFeatureEnable1
UINT32 NewFeatureEnable1
Bit 20 - Generic enable knob for new feature set 1 0: Disable ; 1: Enable.
Definition: MemoryConfig.h:443
SA_FUNCTION_CALLS::SetMemoryVdd
SA_SET_MEMORY_VDD SetMemoryVdd
Offset 140: - Set the memory voltage (VDD) to the given value.
Definition: MemoryConfig.h:276
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryDxeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes | Macros | Typedefs
MemoryDxeConfig.h File Reference

Memory DXE Policy definitions. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _MEMORY_DXE_CONFIG
The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map. More...

Macros

#define MEMORY_DXE_CONFIG_REVISION 2
Making any setup structure change after code frozen will need to maintain backward compatibility, bump up structure revision and update below history table
Revision 1: - Initial version.

Typedefs

typedef CHAR8 *(* | MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING) (IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)
Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field. More...
typedef CHAR8 *(* | MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING) (IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)
Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field. More...

Detailed Description

Memory DXE Policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MemoryDxeConfig.h.

Typedef Documentation

◆ MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING

typedef CHAR8*( * MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING) (IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)

Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.

Implementation of this function is optional, if this function pointer is NULL then the reference implementation of DeviceLocator will be used.

Parameters
[in] | This | A pointer to this instance of MEMORY_DXE_CONFIG.
[in] | Controller | Desired Controller to get a BankLocator string for.
[in] | Dimm | Desired DIMM to get a BankLocator string for.
[in] | MdSocket | 0 = Memory Down, 1 = Socketed.
Return values
The | BankLocator string
NULL | If the return value is NULL, the default value will be used.

Definition at line 86 of file MemoryDxeConfig.h.

◆ MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING

typedef CHAR8*( * MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING) (IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)

Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.

Implementation of this function is optional, if this function pointer is NULL then the reference implementation of DeviceLocator will be used.

Parameters
[in] | This | A pointer to this instance of MEMORY_DXE_CONFIG.
[in] | Controller | Desired Controller to get a DeviceLocator string for.
[in] | Dimm | Desired DIMM to get a DeviceLocator string for.
[in] | MdSocket | 0 = Memory Down, 1 = Socketed.
Return values
The | DeviceLocator string
NULL | If the return value is NULL, the default value will be used.

Definition at line 64 of file MemoryDxeConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryDxeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
MemoryDxeConfig.h
Go to the documentation of this file.
1 /** @file
2 Memory DXE Policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MEMORY_DXE_CONFIG_H_
36 #define _MEMORY_DXE_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 /**
41 Making any setup structure change after code frozen
42 will need to maintain backward compatibility, bump up
43 structure revision and update below history table\n
44 <b>Revision 1</b>: - Initial version.
45 **/
46 #define MEMORY_DXE_CONFIG_REVISION 2
47
48 typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;
49
50 /**
51 Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.
52 Implementation of this function is optional, if this function pointer is NULL then
53 the reference implementation of DeviceLocator will be used.
54
55 @param[in] This A pointer to this instance of MEMORY_DXE_CONFIG.
56 @param[in] Controller Desired Controller to get a DeviceLocator string for.
57 @param[in] Dimm Desired DIMM to get a DeviceLocator string for.
58 @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
59
60 @retval The DeviceLocator string
61 @retval NULL If the return value is NULL, the default value will be used.
62 **/
63 typedef
64 CHAR8*
65 (EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(
66 IN CONST MEMORY_DXE_CONFIG *This,
67 IN UINT8 Controller,
68 IN UINT8 Dimm,
69 IN UINT8 MdSocket
70 );
71
72 /**
73 Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.
74 Implementation of this function is optional, if this function pointer is NULL then
75 the reference implementation of DeviceLocator will be used.
76
77 @param[in] This A pointer to this instance of MEMORY_DXE_CONFIG.
78 @param[in] Controller Desired Controller to get a BankLocator string for.
79 @param[in] Dimm Desired DIMM to get a BankLocator string for.
80 @param[in] MdSocket 0 = Memory Down, 1 = Socketed.
81
82 @retval The BankLocator string
83 @retval NULL If the return value is NULL, the default value will be used.
84 **/
85 typedef
86 CHAR8*
87 (EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(
88 IN CONST MEMORY_DXE_CONFIG *This,
89 IN UINT8 Controller,
90 IN UINT8 Dimm,
91 IN UINT8 MdSocket
92 );
93
94 /**
95 The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map.
96 The data elements should be initialized by a Platform Module.\n
97 <b>Revision 1</b>:
98 - Initial version.
99 **/
100 struct _MEMORY_DXE_CONFIG {
101 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
102 /**
103 Offset 28:
104 Dimm SPD address
105 Only Server support 2 channels * 3 slots per channel = 6 sockets totally
106 The Desktop and mobile only support 2 channels * 2 slots per channel = 4 sockets totally
107 So there is mapping rule here for Desktop and mobile that there are no more 4 DIMMS totally in a system:
108 Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0]
109 Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1]
110 Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2]
111 Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3]
112 Refer to SmbiosMemory.c for use
113 If change the mapping rule, please update the Revision number.
114 **/
115 UINT8 *SpdAddressTable;
116 /**
117 Offset 36:
118 ChannelASlotMap and ChannelBSlotMap change to use SlotMap as the DIMM slot map solution.
119 Reserve 2-bytes in order to comply with 4-bytes alignment and keep the offset of other members.
120 **/
121 UINT8 ChannelASlotMap;
122 UINT8 ChannelBSlotMap;
123 /**
124 Offset 38:
125 MRC execution time measurement: <b>0=Disable</b>, 1=Enable
126 **/
127 UINT8 MrcTimeMeasure;
128 /**
129 Offset 39:
130 Fast boot: 0=Disable, <b>1=Enable</b>
131 **/
132 UINT8 MrcFastBoot;
133 /**
134 Offset 40:
135 Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.
136 **/
137 MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString;
138 /**
139 Offset 48:
140 Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.
141 **/
142 MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString;
143 /**
144 Offset 56:
145 Each DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1, ...
146 if the bit is 1, the related DIMM slot is present.
147 E.g. if memory controller 0 channel 3 has 2 DIMMs, SlotMap[0][3] = 0x03;
148 E.g. if memory controller 1 channel 2 has only 1 DIMMs, SlotMap[1][2] = 0x0;
149 **/
150 UINT8 **SlotMap;
151 };
152 #pragma pack(pop)
153
154 #endif // _MEMORY_DXE_CONFIG_H_
_MEMORY_DXE_CONFIG::MrcTimeMeasure
UINT8 MrcTimeMeasure
Offset 38: MRC execution time measurement: 0=Disable, 1=Enable.
Definition: MemoryDxeConfig.h:127
_MEMORY_DXE_CONFIG::SpdAddressTable
UINT8 * SpdAddressTable
Offset 28: Dimm SPD address Only Server support 2 channels * 3 slots per channel = 6 sockets totally ...
Definition: MemoryDxeConfig.h:115
_MEMORY_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27: Config Block Header.
Definition: MemoryDxeConfig.h:101
_MEMORY_DXE_CONFIG::ChannelASlotMap
UINT8 ChannelASlotMap
Offset 36: ChannelASlotMap and ChannelBSlotMap change to use SlotMap as the DIMM slot map solution.
Definition: MemoryDxeConfig.h:121
_MEMORY_DXE_CONFIG::MrcFastBoot
UINT8 MrcFastBoot
Offset 39: Fast boot: 0=Disable, 1=Enable
Definition: MemoryDxeConfig.h:132
_MEMORY_DXE_CONFIG::SlotMap
UINT8 ** SlotMap
Offset 56: Each DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -> DIMM1,...
Definition: MemoryDxeConfig.h:150
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING
CHAR8 *(* MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)
Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.
Definition: MemoryDxeConfig.h:65
_MEMORY_DXE_CONFIG
The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mechanical present bit map.
Definition: MemoryDxeConfig.h:100
_MEMORY_DXE_CONFIG::GetBankLocatorString
MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString
Offset 48: Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.
Definition: MemoryDxeConfig.h:142
_MEMORY_DXE_CONFIG::GetDeviceLocatorString
MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString
Offset 40: Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocator field.
Definition: MemoryDxeConfig.h:137
MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING
CHAR8 *(* MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(IN CONST MEMORY_DXE_CONFIG *This, IN UINT8 Controller, IN UINT8 Dimm, IN UINT8 MdSocket)
Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator field.
Definition: MemoryDxeConfig.h:87
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryTypeInformation.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
MemoryTypeInformation.h File Reference

This file defines: Memory Type Information GUID for HOB and Variable. More...

Go to the source code of this file.

Detailed Description

This file defines: Memory Type Information GUID for HOB and Variable.

Memory Type Information Variable Name. Memory Type Information GUID HOB data structure.

The memory type information HOB and variable can be used to store the information for each memory type in Variable or HOB.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file MemoryTypeInformation.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MemoryTypeInformation.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
MemoryTypeInformation.h
Go to the documentation of this file.
1 /** @file
2 This file defines:
3 * Memory Type Information GUID for HOB and Variable.
4 * Memory Type Information Variable Name.
5 * Memory Type Information GUID HOB data structure.
6
7 The memory type information HOB and variable can
8 be used to store the information for each memory type in Variable or HOB.
9
10 @copyright
11 INTEL CONFIDENTIAL
12 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
13 This program and the accompanying materials are licensed and made available under
14 the terms and conditions of the BSD License that accompanies this distribution.
15 The full text of the license may be found at
16 http://opensource.org/licenses/bsd-license.php.
17
18 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
19 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20
21 **/
22
23 #ifndef __MEMORY_TYPE_INFORMATION_GUID_H__
24 #define __MEMORY_TYPE_INFORMATION_GUID_H__
25
26 #define EFI_MEMORY_TYPE_INFORMATION_GUID \
27 { 0x4c19049f,0x4137,0x4dd3, { 0x9c,0x10,0x8b,0x97,0xa8,0x3f,0xfd,0xfa } }
28
29 #define EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME L"MemoryTypeInformation"
30
31 extern EFI_GUID gEfiMemoryTypeInformationGuid;
32
33 typedef struct {
34 UINT32 Type; ///< EFI memory type defined in UEFI specification.
35 UINT32 NumberOfPages; ///< The pages of this type memory.
36 } EFI_MEMORY_TYPE_INFORMATION;
37
38 #endif
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Classes
MePeiConfig.h File Reference

ME config block for PEI phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure. More...
struct | ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure. More...

Detailed Description

ME config block for PEI phase.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePeiConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
MePeiConfig.h
Go to the documentation of this file.
1 /** @file
2 ME config block for PEI phase
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_PEI_CONFIG_H_
36 #define _ME_PEI_CONFIG_H_
37
38 #define ME_PEI_PREMEM_CONFIG_REVISION 4
39 extern EFI_GUID gMePeiPreMemConfigGuid;
40
41 #ifndef PLATFORM_POR
42 #define PLATFORM_POR 0
43 #endif
44 #ifndef FORCE_ENABLE
45 #define FORCE_ENABLE 1
46 #endif
47 #ifndef FORCE_DISABLE
48 #define FORCE_DISABLE 2
49 #endif
50
51 #pragma pack (push,1)
52
53 /**
54 ME Pei Pre-Memory Configuration Structure.
55
56 <b>Revision 1:</b>
57 - Initial version.
58 <b>Revision 2:</b>
59 - Add SkipCpuReplacementCheck Option.
60 <b>Revision 3:</b>
61 - Deprecate SendDidMsg.
62 <b>Revision 4:</b>
63 - Add HeciFullTrace Option.
64 **/
65 typedef struct {
66 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
67 UINT32 HeciTimeouts : 1; ///< 0: Disable; <b>1: Enable</b> - HECI Send/Receive Timeouts.
68 /**
69 <b>(Test)</b>
70 <b>0: Disabled</b>
71 1: ME DID init stat 0 - Success
72 2: ME DID init stat 1 - No Memory in Channels
73 3: ME DID init stat 2 - Memory Init Error
74 **/
75 UINT32 DidInitStat : 2;
76 /**
77 <b>(Test)</b>
78 <b>0: Set to 0 to enable polling for CPU replacement</b>
79 1: Set to 1 will disable polling for CPU replacement
80 **/
81 UINT32 DisableCpuReplacedPolling : 1;
82 UINT32 SendDidMsg : 1; ///< <b>(Deprecated)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable to send DID message.
83 /**
84 <b>(Test)</b>
85 <b>0: ME BIOS will check each messages before sending</b>
86 1: ME BIOS always sends messages without checking
87 **/
88 UINT32 DisableMessageCheck : 1;
89 /**
90 <b>(Test)</b>
91 The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot
92 in a MBP message. If set to 1, BIOS will send the MBP message with SkipMbp flag
93 set causing CSME to respond with MKHI header only and no MBP data
94 <b>0: ME BIOS will keep MBP and create HOB for MBP data</b>
95 1: ME BIOS will skip MBP data
96 **/
97 UINT32 SkipMbpHob : 1;
98 UINT32 HeciCommunication2 : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable HECI2.
99 UINT32 KtDeviceEnable : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Kt Device.
100 UINT32 SkipCpuReplacementCheck : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable to skip CPU replacement check.
101 UINT32 HeciFullTrace : 1; ///< <b>(Test)</b> 0: Disable; <b>1: Enable</b> - Enable/Disable Full HECI communication information logged to serial
102 UINT32 RsvdBits : 21; ///< Reserved for future use & Config block alignment
103 UINT32 Heci1BarAddress; ///< HECI1 BAR address.
104 UINT32 Heci2BarAddress; ///< HECI2 BAR address.
105 UINT32 Heci3BarAddress; ///< HECI3 BAR address.
106 } ME_PEI_PREMEM_CONFIG;
107 #pragma pack (pop)
108
109
110 #define ME_PEI_CONFIG_REVISION 4
111 extern EFI_GUID gMePeiConfigGuid;
112
113 #pragma pack (push,1)
114
115 /**
116 ME Pei Post-Memory Configuration Structure.
117
118 <b>Revision 1:</b>
119 - Initial version.
120 <b>Revision 2</b>:
121 - Deprecated Heci3Enabled.
122 <b>Revision 3</b>
123 - Added EnforceEDebugMode.
124 <b>Revision 4</b>
125 - Added CseDataResilience.
126 **/
127
128 typedef struct {
129 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
130
131 UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send in PEI; <b>2: Send in DXE</b> - Send EOP at specific phase.
132 UINT32 Heci3Enabled : 1; ///< @deprecated
133 UINT32 DisableD0I3SettingForHeci : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Enable/Disable D0i3 for HECI.
134 /**
135 Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send MeUnconfigOnRtcClearDisable Msg with parameter 0.
136 It will cause ME to unconfig if RTC is cleared.
137 - 0: Disable
138 - <b>1: Enable</b>
139 - 2: Cmos is clear, status unkonwn
140 - 3: Reserved
141 **/
142 UINT32 MeUnconfigOnRtcClear : 2;
143 UINT32 MctpBroadcastCycle : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Enable - Program registers for MCTP Cycle.
144 UINT32 EnforceEDebugMode : 1; ///< <b>0: Disable</b>; 1: Enable - Enforces ME to enter Enhanced Debug Mode
145 UINT32 CseDataResilience : 1; ///< 0: Disable; <b>1: Enable</b> - CSE data resilience support
146 UINT32 RsvdBits : 23; ///< Reserved for future use & Config block alignment
147 } ME_PEI_CONFIG;
148
149 #pragma pack (pop)
150
151 #endif // _ME_PEI_CONFIG_H_
ME_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:66
ME_PEI_PREMEM_CONFIG::KtDeviceEnable
UINT32 KtDeviceEnable
(Test) 0: Disable; 1: Enable - Enable/Disable Kt Device.
Definition: MePeiConfig.h:99
ME_PEI_CONFIG
ME Pei Post-Memory Configuration Structure.
Definition: MePeiConfig.h:128
ME_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: MePeiConfig.h:129
ME_PEI_CONFIG::MctpBroadcastCycle
UINT32 MctpBroadcastCycle
(Test) 0: Disable; 1: Enable - Program registers for MCTP Cycle.
Definition: MePeiConfig.h:143
ME_PEI_PREMEM_CONFIG::Heci3BarAddress
UINT32 Heci3BarAddress
HECI3 BAR address.
Definition: MePeiConfig.h:105
ME_PEI_PREMEM_CONFIG::HeciCommunication2
UINT32 HeciCommunication2
(Test) 0: Disable; 1: Enable - Enable/Disable HECI2.
Definition: MePeiConfig.h:98
ME_PEI_CONFIG::MeUnconfigOnRtcClear
UINT32 MeUnconfigOnRtcClear
Enable/Disable Me Unconfig On Rtc Clear.
Definition: MePeiConfig.h:142
ME_PEI_PREMEM_CONFIG::SkipMbpHob
UINT32 SkipMbpHob
(Test) The SkipMbpHob policy determines whether ME BIOS Payload data will be requested during boot in...
Definition: MePeiConfig.h:97
ME_PEI_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:146
ME_PEI_PREMEM_CONFIG::DisableCpuReplacedPolling
UINT32 DisableCpuReplacedPolling
(Test) 0: Set to 0 to enable polling for CPU replacement 1: Set to 1 will disable polling for CPU rep...
Definition: MePeiConfig.h:81
ME_PEI_PREMEM_CONFIG
ME Pei Pre-Memory Configuration Structure.
Definition: MePeiConfig.h:65
ME_PEI_PREMEM_CONFIG::HeciTimeouts
UINT32 HeciTimeouts
0: Disable; 1: Enable - HECI Send/Receive Timeouts.
Definition: MePeiConfig.h:67
ME_PEI_CONFIG::Heci3Enabled
UINT32 Heci3Enabled
Definition: MePeiConfig.h:132
ME_PEI_CONFIG::CseDataResilience
UINT32 CseDataResilience
0: Disable; 1: Enable - CSE data resilience support
Definition: MePeiConfig.h:145
ME_PEI_PREMEM_CONFIG::SkipCpuReplacementCheck
UINT32 SkipCpuReplacementCheck
(Test) 0: Disable; 1: Enable - Enable/Disable to skip CPU replacement check.
Definition: MePeiConfig.h:100
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
ME_PEI_PREMEM_CONFIG::HeciFullTrace
UINT32 HeciFullTrace
(Test) 0: Disable; 1: Enable - Enable/Disable Full HECI communication information logged to serial
Definition: MePeiConfig.h:101
ME_PEI_CONFIG::EndOfPostMessage
UINT32 EndOfPostMessage
0: Disabled; 1: Send in PEI; 2: Send in DXE - Send EOP at specific phase.
Definition: MePeiConfig.h:131
ME_PEI_CONFIG::EnforceEDebugMode
UINT32 EnforceEDebugMode
0: Disable; 1: Enable - Enforces ME to enter Enhanced Debug Mode
Definition: MePeiConfig.h:144
ME_PEI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
Reserved for future use & Config block alignment.
Definition: MePeiConfig.h:102
ME_PEI_PREMEM_CONFIG::DisableMessageCheck
UINT32 DisableMessageCheck
(Test) 0: ME BIOS will check each messages before sending 1: ME BIOS always sends messages without ch...
Definition: MePeiConfig.h:88
ME_PEI_CONFIG::DisableD0I3SettingForHeci
UINT32 DisableD0I3SettingForHeci
(Test) 0: Disable; 1: Enable - Enable/Disable D0i3 for HECI.
Definition: MePeiConfig.h:133
ME_PEI_PREMEM_CONFIG::Heci2BarAddress
UINT32 Heci2BarAddress
HECI2 BAR address.
Definition: MePeiConfig.h:104
ME_PEI_PREMEM_CONFIG::SendDidMsg
UINT32 SendDidMsg
(Deprecated) 0: Disable; 1: Enable - Enable/Disable to send DID message.
Definition: MePeiConfig.h:82
ME_PEI_PREMEM_CONFIG::Heci1BarAddress
UINT32 Heci1BarAddress
HECI1 BAR address.
Definition: MePeiConfig.h:103
ME_PEI_PREMEM_CONFIG::DidInitStat
UINT32 DidInitStat
(Test) 0: Disabled 1: ME DID init stat 0 - Success 2: ME DID init stat 1 - No Memory in Channels 3: M...
Definition: MePeiConfig.h:75
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePlatformGetResetType.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs | Enumerations
MePlatformGetResetType.h File Reference

Interface definition Me Platform Get Reset Type. More...

Go to the source code of this file.

Classes

struct _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL
Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service is called. More...

Typedefs

typedef ME_SPECIAL_RESET_TYPES(* | ME_GET_RESET_TYPE) (IN EFI_RESET_TYPE Type)
Get Platform requested reset type. More...
typedef struct _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL | ME_PLATFORM_GET_RESET_TYPE_PROTOCOL
Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service is called.

Enumerations

enum ME_SPECIAL_RESET_TYPES
ME_SPECIAL_RESET_TYPES must be aligned with PCH_EXTENDED_RESET_TYPES.

Detailed Description

Interface definition Me Platform Get Reset Type.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePlatformGetResetType.h.

Typedef Documentation

◆ ME_GET_RESET_TYPE

typedef ME_SPECIAL_RESET_TYPES( * ME_GET_RESET_TYPE) (IN EFI_RESET_TYPE Type)

Get Platform requested reset type.

Parameters
[in] Type UEFI defined reset type
Return values
ME_SPEICAL_RESET_TYPES ME reset type aligned with PCH_EXTENDED_RESET_TYPES

Definition at line 60 of file MePlatformGetResetType.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePlatformGetResetType.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MePlatformGetResetType.h
Go to the documentation of this file.
1 /** @file
2 Interface definition Me Platform Get Reset Type.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_PLATFORM_GET_RESET_TYPE_H_
36 #define _ME_PLATFORM_GET_RESET_TYPE_H_
37
38
39 #define ME_PLATFORM_GET_RESET_TYPE_PROTOCOL_REVISION 1
40 extern EFI_GUID gMePlatformGetResetTypeGuid;
41
42 ///
43 /// ME_SPECIAL_RESET_TYPES must be aligned with PCH_EXTENDED_RESET_TYPES
44 ///
45 typedef enum {
46 PowerCycleResetReq = 3,
47 GlobalResetReq,
48 GlobalResetWithEcReq,
49 MaxRestReq
50 } ME_SPECIAL_RESET_TYPES;
51
52 /**
53 Get Platform requested reset type
54
55 @param[in] Type UEFI defined reset type
56
57 @retval ME_SPEICAL_RESET_TYPES ME reset type aligned with PCH_EXTENDED_RESET_TYPES
58 **/
59 typedef
60 ME_SPECIAL_RESET_TYPES
61 (EFIAPI *ME_GET_RESET_TYPE) (
62 IN EFI_RESET_TYPE Type
63 );
64 /**
65 Me Platform Get Reset Type Protocol
66 Provide reset services cooperated with ME FW and allow platform hook prior to architecture reset service
67 is called.
68 **/
69 typedef struct _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL {
70 UINT8 Revision;
71 ME_GET_RESET_TYPE MeGetResetType;
72 } ME_PLATFORM_GET_RESET_TYPE_PROTOCOL;
73
74 #endif
ME_GET_RESET_TYPE
ME_SPECIAL_RESET_TYPES(* ME_GET_RESET_TYPE)(IN EFI_RESET_TYPE Type)
Get Platform requested reset type.
Definition: MePlatformGetResetType.h:61
ME_PLATFORM_GET_RESET_TYPE_PROTOCOL
struct _ME_PLATFORM_GET_RESET_TYPE_PROTOCOL ME_PLATFORM_GET_RESET_TYPE_PROTOCOL
Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform h...
_ME_PLATFORM_GET_RESET_TYPE_PROTOCOL
Me Platform Get Reset Type Protocol Provide reset services cooperated with ME FW and allow platform h...
Definition: MePlatformGetResetType.h:69
ME_SPECIAL_RESET_TYPES
ME_SPECIAL_RESET_TYPES
ME_SPECIAL_RESET_TYPES must be aligned with PCH_EXTENDED_RESET_TYPES.
Definition: MePlatformGetResetType.h:45
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
MePolicy.h File Reference

Interface definition details between ME and platform drivers during DXE phase. More...

#include <ConfigBlock.h>
#include <MeDxeConfig.h>
Include dependency graph for MePolicy.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _ME_POLICY_PROTOCOL
ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information. More...

Macros

#define ME_POLICY_PROTOCOL_REVISION 1
ME Policy Protocol. More...

Typedefs

typedef struct _ME_POLICY_PROTOCOL ME_POLICY_PROTOCOL
ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information. More...

Detailed Description

Interface definition details between ME and platform drivers during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePolicy.h.

Macro Definition Documentation

◆ ME_POLICY_PROTOCOL_REVISION

#define ME_POLICY_PROTOCOL_REVISION 1

ME Policy Protocol.

All ME Policy Protocol change history listed here.

Definition at line 46 of file MePolicy.h.

Typedef Documentation

◆ ME_POLICY_PROTOCOL

typedef struct _ME_POLICY_PROTOCOL ME_POLICY_PROTOCOL

ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Configuration information.

Revision 1:

  • Initial version.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MePolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details between ME and platform drivers during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_POLICY_H_
36 #define _ME_POLICY_H_
37
38 #include <ConfigBlock.h>
39 #include <MeDxeConfig.h>
40
41 /**
42 ME Policy Protocol.
43 All ME Policy Protocol change history listed here.
44
45 **/
46 #define ME_POLICY_PROTOCOL_REVISION 1
47
48 extern EFI_GUID gDxeMePolicyGuid;
49
50 #pragma pack (push,1)
51
52 /**
53 ME policy provided by platform for DXE phase
54 This protocol provides an interface to get Intel ME Configuration information
55
56 <b>Revision 1</b>:
57 - Initial version.
58 **/
59 typedef struct _ME_POLICY_PROTOCOL {
60 CONFIG_BLOCK_TABLE_HEADER TableHeader;
61 /*
62 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
63 */
64 } ME_POLICY_PROTOCOL;
65
66 #pragma pack (pop)
67
68 #endif // _ME_POLICY_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
MeDxeConfig.h
ME config block for DXE phase.
_ME_POLICY_PROTOCOL
ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Conf...
Definition: MePolicy.h:59
ME_POLICY_PROTOCOL
struct _ME_POLICY_PROTOCOL ME_POLICY_PROTOCOL
ME policy provided by platform for DXE phase This protocol provides an interface to get Intel ME Conf...
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicyCommon.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MePolicyCommon.h File Reference

Definition for ME common policy. More...

#include <ConfigBlock.h>
#include <MePeiConfig.h>
Include dependency graph for MePolicyCommon.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Definition for ME common policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyCommon.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicyCommon.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MePolicyCommon.h
Go to the documentation of this file.
1 /** @file
2 Definition for ME common policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_POLICY_COMMON_H_
36 #define _ME_POLICY_COMMON_H_
37
38 #include <ConfigBlock.h>
39
40 #include <MePeiConfig.h>
41
42 #ifndef PLATFORM_POR
43 #define PLATFORM_POR 0
44 #endif
45 #ifndef FORCE_ENABLE
46 #define FORCE_ENABLE 1
47 #endif
48 #ifndef FORCE_DISABLE
49 #define FORCE_DISABLE 2
50 #endif
51
52 #endif // _ME_POLICY_COMMON_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
MePeiConfig.h
ME config block for PEI phase.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicyHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MePolicyHob.h File Reference

This file contains definitions of ME Policy HOB. More...

#include <MePolicyCommon.h>
Include dependency graph for MePolicyHob.h:

Go to the source code of this file.

Detailed Description

This file contains definitions of ME Policy HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MePolicyHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MePolicyHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MePolicyHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of ME Policy HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_POLICY_HOB_H_
36 #define _ME_POLICY_HOB_H_
37
38 #include <MePolicyCommon.h>
39
40 extern EFI_GUID gMePolicyHobGuid;
41 extern EFI_GUID gMePreMemPolicyHobGuid;
42
43 #endif // _ME_POLICY_HOB_H_
MePolicyCommon.h
Definition for ME common policy.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
MeRegs.h File Reference

Register definition for ME Devices. More...

#include <Library/MeChipsetLib.h>
Include dependency graph for MeRegs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | HECI_NAME_MAP(a) ((a < 2) ? (a + 1) : (a - 1))
Convert to HECI# defined in BWG from Fun#.
#define | V_INTEL_VENDOR_ID 0x8086
Default Vendor ID and Device ID.
#define | V_ME_VER1_PCH_N_HECI_DEVICE_ID 0x4DE0
Ver1 PCH-N ME Device IDs.
#define | V_ME_VER2_PCH_H_HECI_DEVICE_ID 0x43E0
Ver2 PCH-H/LP ME Device IDs.
#define | V_ME_VER3_PCH_HECI_DEVICE_ID 0x1BE0
Ver3 PCH ME Device IDs.
#define | V_ME_VER4_PCH_S_HECI_DEVICE_ID 0x7AE8
Ver4 PCH-S/P/M ME Device IDs.
#define | HeciEnable() MeDeviceControl (HECI1, Enabled);
ME-related Chipset Definition.
#define | IS_VER1_PCH_SOL_DEVICE_ID(DeviceId)
SoL Device Id Definitions.

Detailed Description

Register definition for ME Devices.

Conventions:

  • Prefixes:
    • Definitions beginning with "R_" are registers
    • Definitions beginning with "B_" are bits within registers
    • Definitions beginning with "V_" are meaningful values of bits within the registers
    • Definitions beginning with "S_" are register sizes
    • Definitions beginning with "N_" are the bit position
  • Registers / bits that are different between PCH generations are denoted by "_ME_[generation_name]_" in register/bit names.
  • Registers / bits that are specific to PCH-H denoted by "PCH_H_" in register/bit names. Registers / bits that are specific to PCH-LP denoted by "PCH_LP_" in register/bit names. e.g., "_ME_PCH_H_", "_ME_PCH_LP_" Registers / bits names without PCH_H or PCH_LP apply for both H and LP.
  • Registers / bits that are different between SKUs are denoted by "_[SKU_name]" at the end of the register/bit names
  • Registers / bits of new devices introduced in a PCH generation will be just named as "_ME_" without [generation_name] inserted.
Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeRegs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
MeRegs.h
Go to the documentation of this file.
1 /** @file
2 Register definition for ME Devices.
3
4 Conventions:
5
6 - Prefixes:
7 - Definitions beginning with "R_" are registers
8 - Definitions beginning with "B_" are bits within registers
9 - Definitions beginning with "V_" are meaningful values of bits within the registers
10 - Definitions beginning with "S_" are register sizes
11 - Definitions beginning with "N_" are the bit position
12 - Registers / bits that are different between PCH generations are denoted by
13 "_ME_[generation_name]_" in register/bit names.
14 - Registers / bits that are specific to PCH-H denoted by "PCH_H_" in register/bit names.
15 Registers / bits that are specific to PCH-LP denoted by "PCH_LP_" in register/bit names.
16 e.g., "_ME_PCH_H_", "_ME_PCH_LP_"
17 Registers / bits names without _PCH_H_ or _PCH_LP_ apply for both H and LP.
18 - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
19 at the end of the register/bit names
20 - Registers / bits of new devices introduced in a PCH generation will be just named
21 as "_ME_" without [generation_name] inserted.
22
23 @copyright
24 INTEL CONFIDENTIAL
25 Copyright 2011 - 2021 Intel Corporation.
26
27 The source code contained or described herein and all documents related to the
28 source code ("Material") are owned by Intel Corporation or its suppliers or
29 licensors. Title to the Material remains with Intel Corporation or its suppliers
30 and licensors. The Material may contain trade secrets and proprietary and
31 confidential information of Intel Corporation and its suppliers and licensors,
32 and is protected by worldwide copyright and trade secret laws and treaty
33 provisions. No part of the Material may be used, copied, reproduced, modified,
34 published, uploaded, posted, transmitted, distributed, or disclosed in any way
35 without Intel's prior express written permission.
36
37 No license under any patent, copyright, trade secret or other intellectual
38 property right is granted to or conferred upon you by disclosure or delivery
39 of the Materials, either expressly, by implication, inducement, estoppel or
40 otherwise. Any license under such intellectual property rights must be
41 express and approved by Intel in writing.
42
43 Unless otherwise agreed by Intel in writing, you may not remove or alter
44 this notice or any other notice embedded in Materials by Intel or
45 Intel's suppliers or licensors in any way.
46
47 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
48 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
49 the terms of your license agreement with Intel or your vendor. This file may
50 be modified by the user, subject to additional terms of the license agreement.
51
52 @par Specification Reference:
53 **/
54 #ifndef _ME_REGS_H_
55 #define _ME_REGS_H_
56
57 #include <Library/MeChipsetLib.h>
58
59 #define ME_SEGMENT 0
60 #define ME_BUS 0
61 #define ME_DEVICE_NUMBER 22
62 #define HECI_MIN_FUNC 0
63 #define HECI_MAX_FUNC 5
64
65 #define HECI_FUNCTION_NUMBER 0x00
66 #define HECI2_FUNCTION_NUMBER 0x01
67 #define IDER_FUNCTION_NUMBER 0x02
68 #define SOL_FUNCTION_NUMBER 0x03
69 #define HECI3_FUNCTION_NUMBER 0x04
70 #define HECI4_FUNCTION_NUMBER 0x05
71
72 typedef enum {
73 HECI1_DEVICE = 0,
74 HECI2_DEVICE = 1,
75 HECI3_DEVICE = 4,
76 HECI4_DEVICE = 5,
77 ISH_HECI = 8
78 } HECI_DEVICE;
79
80 ///
81 /// Convert to HECI# defined in BWG from Fun#
82 ///
83 #define HECI_NAME_MAP(a) ((a < 2) ? (a + 1) : (a - 1))
84
85 ///
86 /// Default Vendor ID and Device ID
87 ///
88 #define V_INTEL_VENDOR_ID 0x8086
89
90 #define V_ME_HECI_VENDOR_ID V_INTEL_VENDOR_ID
91 #define V_ME_SOL_VENDOR_ID V_INTEL_VENDOR_ID
92
93 ///
94 /// Ver1 PCH-N ME Device IDs
95 ///
96 #define V_ME_VER1_PCH_N_HECI_DEVICE_ID 0x4DE0
97 #define V_ME_VER1_PCH_N_HECI2_DEVICE_ID 0x4DE1
98 #define V_ME_VER1_PCH_N_SOL_DEVICE_ID 0x4DE3
99 #define V_ME_VER1_PCH_N_HECI3_DEVICE_ID 0x4DE4
100 #define V_ME_VER1_PCH_N_HECI4_DEVICE_ID 0x4DE5
101
102 ///
103 /// Ver2 PCH-H/LP ME Device IDs
104 ///
105 #define V_ME_VER2_PCH_H_HECI_DEVICE_ID 0x43E0
106 #define V_ME_VER2_PCH_H_HECI2_DEVICE_ID 0x43E1
107 #define V_ME_VER2_PCH_H_SOL_DEVICE_ID 0x43E3
108 #define V_ME_VER2_PCH_H_HECI3_DEVICE_ID 0x43E4
109 #define V_ME_VER2_PCH_H_HECI4_DEVICE_ID 0x43E5
110
111 #define V_ME_VER2_PCH_LP_HECI_DEVICE_ID 0xA0E0
112 #define V_ME_VER2_PCH_LP_HECI2_DEVICE_ID 0xA0E1
113 #define V_ME_VER2_PCH_LP_SOL_DEVICE_ID 0xA0E3
114 #define V_ME_VER2_PCH_LP_HECI3_DEVICE_ID 0xA0E4
115 #define V_ME_VER2_PCH_LP_HECI4_DEVICE_ID 0xA0E5
116
117 ///
118 /// Ver3 PCH ME Device IDs
119 ///
120 #define V_ME_VER3_PCH_HECI_DEVICE_ID 0x1BE0
121 #define V_ME_VER3_PCH_HECI2_DEVICE_ID 0x1BE1
122 #define V_ME_VER3_PCH_SOL_DEVICE_ID 0x1BE3
123 #define V_ME_VER3_PCH_HECI3_DEVICE_ID 0x1BE4
124 #define V_ME_VER3_PCH_HECI4_DEVICE_ID 0x1BE5
125
126 ///
127 /// Ver4 PCH-S/P/M ME Device IDs
128 ///
129 #define V_ME_VER4_PCH_S_HECI_DEVICE_ID 0x7AE8
130 #define V_ME_VER4_PCH_S_HECI2_DEVICE_ID 0x7AE9
131 #define V_ME_VER4_PCH_S_SOL_DEVICE_ID 0x7AEB
132 #define V_ME_VER4_PCH_S_HECI3_DEVICE_ID 0x7AEC
133 #define V_ME_VER4_PCH_S_HECI4_DEVICE_ID 0x7AED
134
135 #define V_ME_VER4_PCH_P_HECI_DEVICE_ID 0x51E0
136 #define V_ME_VER4_PCH_P_HECI2_DEVICE_ID 0x51E1
137 #define V_ME_VER4_PCH_P_SOL_DEVICE_ID 0x51E3
138 #define V_ME_VER4_PCH_P_HECI3_DEVICE_ID 0x51E4
139 #define V_ME_VER4_PCH_P_HECI4_DEVICE_ID 0x51E5
140
141 #define V_ME_VER4_PCH_M_HECI_DEVICE_ID 0x54E0
142 #define V_ME_VER4_PCH_M_HECI2_DEVICE_ID 0x54E1
143 #define V_ME_VER4_PCH_M_SOL_DEVICE_ID 0x54E3
144 #define V_ME_VER4_PCH_M_HECI3_DEVICE_ID 0x54E4
145 #define V_ME_VER4_PCH_M_HECI4_DEVICE_ID 0x54E5
146
147
148 #define R_ME_HFS 0x40
149 #define R_ME_HFS_2 0x48
150 #define R_ME_PMCSR 0x54
151 #define V_ME_PMCSR 0x03
152 #define R_ME_HFS_3 0x60
153 #define R_ME_HFS_4 0x64
154 #define R_ME_HFS_5 0x68
155 #define R_ME_HFS_6 0x6C
156
157 #define R_ME_H_GS 0x4C
158 #define R_ME_H_GS2 0x70
159 #define B_ME_H_GS2_PROXY_PRESENT BIT8
160 #define B_ME_H_GS2_STORAGE_OP_IN_PROGRESS BIT9
161 #define B_ME_H_GS2_IBB_DATA_READY BIT10
162 #define R_ME_HIDM 0xA0
163 #define V_ME_HIDM_MSI 0
164 #define V_ME_HIDM_SCI 1
165 #define V_ME_HIDM_SMI 2
166 #define B_ME_HIDM_MODE (BIT0 | BIT1)
167 #define B_ME_HIDM_L BIT2
168 #define R_ME_HERS 0xBC
169 #define B_ME_EXTEND_REG_ALGORITHM (BIT3 | BIT2 | BIT1 | BIT0) // Bits3:0 = 0x0 - SHA1; 0x2 - SHA256; 0x4 - SHA384
170 #define B_ME_EXTEND_COMPLETE BIT29
171 #define B_ME_EXTEND_FEAT_PRESENT BIT30
172 #define B_ME_EXTEND_REG_VALID BIT31
173 #define V_ME_SHA_1 0x00
174 #define V_ME_SHA_256 0x02
175 #define V_ME_SHA_384 0x04
176 #define R_ME_HER1 0xC0
177 #define R_ME_HER2 0xC4
178 #define R_ME_HER3 0xC8
179 #define R_ME_HER4 0xCC
180 #define R_ME_HER5 0xD0
181 #define R_ME_HER6 0xD4
182 #define R_ME_HER7 0xD8
183 #define R_ME_HER8 0xDC
184
185 ///
186 /// ME-related Chipset Definition
187 ///
188 #define HeciEnable() MeDeviceControl (HECI1, Enabled);
189 #define Heci2Enable() MeDeviceControl (HECI2, Enabled);
190 #define Heci3Enable() MeDeviceControl (HECI3, Enabled);
191 #define Heci4Enable() MeDeviceControl (HECI4, Enabled);
192 #define IderEnable() MeDeviceControl (IDER, Enabled);
193 #define SolEnable() MeDeviceControl (SOL, Enabled);
194
195 #define HeciDisable() MeDeviceControl (HECI1, Disabled);
196 #define Heci2Disable() MeDeviceControl (HECI2, Disabled);
197 #define Heci3Disable() MeDeviceControl (HECI3, Disabled);
198 #define IderDisable() MeDeviceControl (IDER, Disabled);
199 #define SolDisable() MeDeviceControl (SOL, Disabled);
200
201 #define DisableAllMeDevices() \
202 HeciDisable (); \
203 Heci2Disable (); \
204 Heci3Disable (); \
205 IderDisable (); \
206 SolDisable ();
207
208 ///
209 /// SoL Device Id Definitions
210 ///
211 #define IS_VER1_PCH_SOL_DEVICE_ID(DeviceId) \
212 ( \
213 (DeviceId == V_ME_VER1_PCH_N_SOL_DEVICE_ID) \
214 )
215
216 #define IS_VER2_PCH_SOL_DEVICE_ID(DeviceId) \
217 ( \
218 (DeviceId == V_ME_VER2_PCH_H_SOL_DEVICE_ID) || \
219 (DeviceId == V_ME_VER2_PCH_LP_SOL_DEVICE_ID) \
220 )
221
222 #define IS_VER3_PCH_SOL_DEVICE_ID(DeviceId) \
223 ( \
224 (DeviceId == V_ME_VER3_PCH_SOL_DEVICE_ID) \
225 )
226
227 #define IS_VER4_PCH_SOL_DEVICE_ID(DeviceId) \
228 ( \
229 (DeviceId == V_ME_VER4_PCH_S_SOL_DEVICE_ID) || \
230 (DeviceId == V_ME_VER4_PCH_P_SOL_DEVICE_ID) || \
231 (DeviceId == V_ME_VER4_PCH_M_SOL_DEVICE_ID) \
232 )
233
234 #define IS_PCH_SOL_DEVICE_ID(DeviceId) \
235 ( \
236 IS_VER1_PCH_SOL_DEVICE_ID(DeviceId) || \
237 IS_VER2_PCH_SOL_DEVICE_ID(DeviceId) || \
238 IS_VER3_PCH_SOL_DEVICE_ID(DeviceId) || \
239 IS_VER4_PCH_SOL_DEVICE_ID(DeviceId) \
240 )
241
242 #endif
MeChipsetLib.h
Header file for Me Chipset Lib.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeShowBufferLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
MeShowBufferLib.h File Reference

Definition for Me Debug Lib. More...

Go to the source code of this file.

Functions

VOID ShowBuffer (IN UINT8 *Message, IN UINT32 Length)
For serial debugger used, it will show the buffer message line by line to serial console. More...

Detailed Description

Definition for Me Debug Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeShowBufferLib.h.

Function Documentation

◆ ShowBuffer()

VOID ShowBuffer | ( | IN UINT8 * | Message,
 |  | IN UINT32 | Length
 | ) |  |

For serial debugger used, it will show the buffer message line by line to serial console.

Parameters
[in] | Message | the address point of buffer message
[in] | Length | message length
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeShowBufferLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeShowBufferLib.h
Go to the documentation of this file.
1 /** @file
2 Definition for Me Debug Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_SHOW_BUFFER_LIB_H_
36 #define _ME_SHOW_BUFFER_LIB_H_
37
38 /**
39 For serial debugger used, it will show the buffer message line by line to serial console.
40
41 @param[in] Message the address point of buffer message
42 @param[in] Length message length
43
44 **/
45 VOID
46 ShowBuffer (
47 IN UINT8 *Message,
48 IN UINT32 Length
49 );
50
51 #endif // End of _ME_SHOW_BUFFER_LIB_H
ShowBuffer
VOID ShowBuffer(IN UINT8 *Message, IN UINT32 Length)
For serial debugger used, it will show the buffer message line by line to serial console.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeSmbios.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
MeSmbios.h File Reference

Header file for the MeSmbios Driver. More...

#include <Library/BaseLib.h>
#include <IndustryStandard/SmBios.h>
#include <Guid/SmBios.h>
#include <Protocol/Smbios.h>
#include <Protocol/MebxProtocol.h>
#include <Library/DxeMeLib.h>
Include dependency graph for MeSmbios.h:

Go to the source code of this file.

Classes

struct | SMBIOS_TABLE_TYPE130
This is definition for SMBIOS Oem data type 130. More...
struct | ME_CAP
ME Platform Capabilities. More...
struct | SMBIOS_TABLE_TYPE131
This is definition for SMBIOS Oem data type 131. More...

Macros

#define | EXTENDED_DATA_RESERVED_BITMASK BIT0 | BIT2 | BIT5 | BIT7
ExtendedData.
#define | OEM_CAPS_1_RESERVED_BITMASK BIT0 | BIT1 | BIT5 | BIT6 | BIT7
OEMCapabilities1.
#define | OEM_CAPS_2_TERMINAL_EMULATION_VT100PLUS 0x02
OEMCapabilities2.
#define | OEM_CAPS_3_SECURE_ERASE_BIT_OFFSET 6
OEMCapabilities3.
#define | OEM_CAPS_4_VPRO_TBT_DOCK_BIT_OFFSET 0
OEMCapabilities4.

Detailed Description

Header file for the MeSmbios Driver.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file MeSmbios.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeSmbios.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeSmbios.h
Go to the documentation of this file.
1 /**@file
2 Header file for the MeSmbios Driver.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _ME_SMBIOS_H_
36 #define _ME_SMBIOS_H_
37
38 #include <Library/BaseLib.h>
39 #include <IndustryStandard/SmBios.h>
40 #include <Guid/SmBios.h>
41 #include <Protocol/Smbios.h>
42 #include <Protocol/MebxProtocol.h>
43 #include <Library/DxeMeLib.h>
44
45 #define MESMBIOS_TYPE_130 130
46 #define MESMBIOS_TYPE_131 131
47
48 ///
49 /// ExtendedData
50 ///
51 #define EXTENDED_DATA_RESERVED_BITMASK BIT0 | BIT2 | BIT5 | BIT7
52
53 ///
54 /// OEMCapabilities1
55 ///
56 #define OEM_CAPS_1_RESERVED_BITMASK BIT0 | BIT1 | BIT5 | BIT6 | BIT7
57
58 #define OEM_CAPS_1_BIOS_REFLASH_BIT_OFFSET 2
59 #define OEM_CAPS_1_BIOS_SETUP_BIT_OFFSET 3
60 #define OEM_CAPS_1_BIOS_PAUSE_BIT_OFFSET 4
61
62 ///
63 /// OEMCapabilities2
64 ///
65 #define OEM_CAPS_2_TERMINAL_EMULATION_VT100PLUS 0x02
66
67 ///
68 /// OEMCapabilities3
69 ///
70 #define OEM_CAPS_3_SECURE_ERASE_BIT_OFFSET 6
71 #define OEM_CAPS_3_BIOS_SECURE_BOOT_BIT_OFFSET 7
72
73 ///
74 /// OEMCapabilities4
75 ///
76 #define OEM_CAPS_4_VPRO_TBT_DOCK_BIT_OFFSET 0
77 #define OEM_CAPS_4_OCR_HTTPS_BOOT_BIT_OFFSET 1
78 #define OEM_CAPS_4_OCR_PBA_BOOT_BIT_OFFSET 2
79 #define OEM_CAPS_4_OCR_WINRE_BOOT_BIT_OFFSET 3
80 #define OEM_CAPS_4_OCR_AMT_DIS_SEC_BOOT_BIT_OFFSET 4
81 #define OEM_CAPS_4_OCR_WIFI_PROFILE_BIT_OFFSET 5
82
83 ///
84 /// This is definition for SMBIOS Oem data type 130
85 ///
86 typedef struct {
87 SMBIOS_STRUCTURE Header;
88 UINT8 AmtSignature[4]; ///< Table signature
89 UINT8 AmtSupported; ///< Any manageability supported, includes full or standard manageability
90 UINT8 AmtEnabled; ///< Any manageability enabled, includes full or standard manageability
91 UINT8 SrouEnabled; ///< Storage Redirection Over USB-R feature enablement
92 UINT8 SolEnabled; ///< Serial Over Lan feature enablement
93 UINT8 NetworkEnabled; ///< Network interface enablement
94 UINT8 ExtendedData; ///< Kept for backward compatibility
95 UINT8 OemCapabilities1; ///< 1st Byte of OEM Capabilities
96 UINT8 OemCapabilities2; ///< 2nd Byte of OEM Capabilities
97 UINT8 OemCapabilities3; ///< 3rd Byte of OEM Capabilities
98 UINT8 OemCapabilities4; ///< 4th Byte of OEM Capabilities
99 UINT8 KvmEnabled; ///< Kvm redirection enablement
100 UINT8 Reserved; ///< Reserved
101 UINT32 RpeCapabilities; ///< Remote Platform Erase Capbilities, keeps it at the end and 4 byte alignment
102 } SMBIOS_TABLE_TYPE130;
103
104 typedef struct {
105 UINT32 VMXState : 1; ///< [0] VMX enabled state (On/Off) (This bit is a duplicate of Bit 5 and maintained for backward compatibility)
106 UINT32 SMXState : 1; ///< [1] SMX enabled state (On/Off) (This bit is a duplicate of Bit 3 and maintained for backward compatibility)
107 UINT32 LtTxtCap : 1; ///< [2] LT/TXT capability
108 UINT32 LtTxtEnabled : 1; ///< [3] LT/TXT Enabled state (Optional for vPro verification)
109 UINT32 VTxCap : 1; ///< [4] VT-x capability
110 UINT32 VTxEnabled : 1; ///< [5] VT-x Enabled state (Optional for vPro verification)
111 UINT32 Reserved : 26; ///< [31:6] Reserved, set to 0
112 } CPU_CAP;
113
114 typedef struct {
115 UINT32 FunctionNumber : 3; ///< [2:0] PCI Device Function Number
116 UINT32 DeviceNumber : 5; ///< [7:3] PCI Device Device Number
117 UINT32 BusNumber : 8; ///< [15:8] PCI Device Bus Number
118 UINT32 DeviceID : 16; ///< [31:16] Device Identification Number (DID): This field is the identifier of PCH PCI device. DID will be set to 0xFF if not found.
119 UINT32 Reserved : 32; ///< [63:32] Reserved, must set to 0
120 } PCH_CAP;
121
122 ///
123 /// ME Platform Capabilities
124 ///
125 typedef struct {
126 UINT32 MeEnabled : 1; ///< [0] ME enabled/Disabled
127 UINT32 Reserved : 2; ///< [2:1] Reserved, must set to 0
128 UINT32 IntelAmtFw : 1; ///< [3] Intel AMT FW support
129 UINT32 IntelAmtFwStandard : 1; ///< [4] Intel AMT Standard FW support
130 UINT32 IntelAmtEnabled : 1; ///< [5] Intel AMT Enabled
131 UINT32 Reserved1 : 7; ///< [12:6] Reserved
132 UINT32 IntelKVMEnabled : 1; ///< [13] Intel KVM enabled
133 UINT32 IntelKVM : 1; ///< [14] Intel KVM supported
134 UINT32 LocalWakeupTimer : 1; ///< [15] Local Wakeup Timer support
135 UINT32 Reserved2 : 16; ///< [31:16] Reserved, must set to 0
136 UINT32 MeMinorVer : 16; ///< [47:32] ME FW Minor Version.
137 UINT32 MeMajorVer : 16; ///< [63:48] ME FW Major Version.
138 UINT32 MeBuildNo : 16; ///< [79:64] ME FW Build Number.
139 UINT32 MeHotFixNo : 16; ///< [95:80] ME FW Hotfix Number
140 } ME_CAP;
141
142 typedef struct {
143 UINT32 FunctionNumber : 3; ///< [2:0] PCI Device Function Number of Wired LAN
144 UINT32 DeviceNumber : 5; ///< [7:3] PCI Device Device Number of Wired LAN
145 UINT32 BusNumber : 8; ///< [15:8] PCI Device Bus Number of Wired LAN
146 UINT32 DeviceID : 16; ///< [31:16] PCI Device Identifier (DID) of wired NIC. DID will be set to 0xFF if not found.
147 UINT32 Reserved1 : 16; ///< [47:32] Reserved for Wired NIC.
148 UINT32 Reserved2 : 16; ///< [63:48] Reserved, must set to 0 (Wireless)
149 UINT32 Reserved3 : 32; ///< [95:64] Reserved, must set to 0 (Wireless)
150 } NETWORK_DEV;
151
152 typedef struct {
153 UINT32 Reserved1 : 1; ///< [0] Reserved, must be set to 0
154 UINT32 VTdSupport : 1; ///< [1] BIOS supports VT-d in BIOS setup screen (can be editable)
155 UINT32 TxtSupport : 1; ///< [2] BIOS supports TXT in BIOS setup screen (can be editable)
156 UINT32 Reserved2 : 1; ///< [3] Reserved, must be set to 0
157 UINT32 Reserved3 : 1; ///< [4] Reserved, must be set to 0
158 UINT32 VTxSupport : 1; ///< [5] BIOS supports VT-x in BIOS setup screen (can be editable)
159 UINT32 TdsMeasuredBoot : 1; ///< [6] BIOS supports Intel Trusted Device Setup Measured Boot
160 UINT32 TdsBiosLock : 1; ///< [7] BIOS supports Intel Trusted Device Setup Boot and Setup Lock
161 UINT32 TdsChassisIntrusion : 1; ///< [8] BIOS supports Intel Trusted Device Setup Chassis Intrusion
162 UINT32 Reserved4 : 23; ///< [31:9] Reserved, must be set to 0
163 } BIOS_CAP;
164
165 ///
166 /// This is definition for SMBIOS Oem data type 131
167 ///
168 typedef struct {
169 SMBIOS_STRUCTURE Header;
170 CPU_CAP CpuCapabilities;
171 MEBX_VER MebxVersion; ///< @deprecated
172 PCH_CAP PchCapabilities;
173 ME_CAP MeCapabilities;
174 MEFWCAPS_SKU MeFwConfigured;
175 NETWORK_DEV NetworkDevice;
176 BIOS_CAP BiosCapabilities;
177 UINT8 StructureIdentifier[4];
178 UINT32 Reserved;
179 } SMBIOS_TABLE_TYPE131;
180
181 #endif
ME_CAP::IntelKVMEnabled
UINT32 IntelKVMEnabled
[13] Intel KVM enabled
Definition: MeSmbios.h:132
ME_CAP::MeMinorVer
UINT32 MeMinorVer
[47:32] ME FW Minor Version.
Definition: MeSmbios.h:136
SMBIOS_TABLE_TYPE130::OemCapabilities3
UINT8 OemCapabilities3
3rd Byte of OEM Capabilities
Definition: MeSmbios.h:97
ME_CAP::LocalWakeupTimer
UINT32 LocalWakeupTimer
[15] Local Wakeup Timer support
Definition: MeSmbios.h:134
SMBIOS_TABLE_TYPE131::MebxVersion
MEBX_VER MebxVersion
Definition: MeSmbios.h:171
ME_CAP
ME Platform Capabilities.
Definition: MeSmbios.h:125
ME_CAP::MeHotFixNo
UINT32 MeHotFixNo
[95:80] ME FW Hotfix Number
Definition: MeSmbios.h:139
MebxProtocol.h
EFI MEBx Protocol.
SMBIOS_TABLE_TYPE130::ExtendedData
UINT8 ExtendedData
Kept for backward compatibility.
Definition: MeSmbios.h:94
SMBIOS_TABLE_TYPE130::SrouEnabled
UINT8 SrouEnabled
Storage Redirection Over USB-R feature enablement.
Definition: MeSmbios.h:91
SMBIOS_TABLE_TYPE130::SolEnabled
UINT8 SolEnabled
Serial Over Lan feature enablement.
Definition: MeSmbios.h:92
SMBIOS_TABLE_TYPE130
This is definition for SMBIOS Oem data type 130.
Definition: MeSmbios.h:86
SMBIOS_TABLE_TYPE130::NetworkEnabled
UINT8 NetworkEnabled
Network interface enablement.
Definition: MeSmbios.h:93
ME_CAP::Reserved2
UINT32 Reserved2
[31:16] Reserved, must set to 0
Definition: MeSmbios.h:135
SMBIOS_TABLE_TYPE130::AmtEnabled
UINT8 AmtEnabled
Any manageability enabled, includes full or standard manageability.
Definition: MeSmbios.h:90
ME_CAP::Reserved
UINT32 Reserved
[2:1] Reserved, must set to 0
Definition: MeSmbios.h:127
SMBIOS_TABLE_TYPE130::Reserved
UINT8 Reserved
Reserved.
Definition: MeSmbios.h:100
ME_CAP::IntelAmtFwStandard
UINT32 IntelAmtFwStandard
[4] Intel AMT Standard FW support
Definition: MeSmbios.h:129
SMBIOS_TABLE_TYPE130::OemCapabilities2
UINT8 OemCapabilities2
2nd Byte of OEM Capabilities
Definition: MeSmbios.h:96
ME_CAP::MeBuildNo
UINT32 MeBuildNo
[79:64] ME FW Build Number.
Definition: MeSmbios.h:138
ME_CAP::MeEnabled
UINT32 MeEnabled
[0] ME enabled/Disabled
Definition: MeSmbios.h:126
SMBIOS_TABLE_TYPE130::OemCapabilities1
UINT8 OemCapabilities1
1st Byte of OEM Capabilities
Definition: MeSmbios.h:95
SMBIOS_TABLE_TYPE130::KvmEnabled
UINT8 KvmEnabled
Kvm redirection enablement.
Definition: MeSmbios.h:99
SMBIOS_TABLE_TYPE130::OemCapabilities4
UINT8 OemCapabilities4
4th Byte of OEM Capabilities
Definition: MeSmbios.h:98
SMBIOS_TABLE_TYPE130::AmtSupported
UINT8 AmtSupported
Any manageability supported, includes full or standard manageability.
Definition: MeSmbios.h:89
SMBIOS_TABLE_TYPE131
This is definition for SMBIOS Oem data type 131.
Definition: MeSmbios.h:168
ME_CAP::IntelKVM
UINT32 IntelKVM
[14] Intel KVM supported
Definition: MeSmbios.h:133
ME_CAP::MeMajorVer
UINT32 MeMajorVer
[63:48] ME FW Major Version.
Definition: MeSmbios.h:137
ME_CAP::Reserved1
UINT32 Reserved1
[12:6] Reserved
Definition: MeSmbios.h:131
MEFWCAPS_SKU
Get Firmware Capability.
Definition: MkhiMsgs.h:404
DxeMeLib.h
Header file for functions to get Intel ME information.
ME_CAP::IntelAmtEnabled
UINT32 IntelAmtEnabled
[5] Intel AMT Enabled
Definition: MeSmbios.h:130
SMBIOS_TABLE_TYPE130::RpeCapabilities
UINT32 RpeCapabilities
Remote Platform Erase Capbilities, keeps it at the end and 4 byte alignment.
Definition: MeSmbios.h:101
ME_CAP::IntelAmtFw
UINT32 IntelAmtFw
[3] Intel AMT FW support
Definition: MeSmbios.h:128
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeSmbiosUpdateProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
MeSmbiosUpdateProtocol.h File Reference

MeSmbiosTablesUpdateProtocol definitions. More...

Go to the source code of this file.

Classes

struct ME_SMBIOS_TABLES_UPDATE_PROTOCOL
ME SMBIOS Tables update protocol The interface functions are to update SMBIOS type 130 (in case of AMT) and 131. More...

Typedefs

typedef EFI_STATUS(* ME_UPDATE_SMBIOS) (VOID)
ME SMBIOS Update Protocol. More...

Detailed Description

MeSmbiosTablesUpdateProtocol definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeSmbiosUpdateProtocol.h.

Typedef Documentation

◆ ME_UPDATE_SMBIOS

typedef EFI_STATUS( * ME_UPDATE_SMBIOS) (VOID)

ME SMBIOS Update Protocol.

This function is used to update ME SMBIOS table.

Returns
Standard EFI_STATUS is returned.

Definition at line 48 of file MeSmbiosUpdateProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeSmbiosUpdateProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
MeSmbiosUpdateProtocol.h
Go to the documentation of this file.
1 /** @file
2 MeSmbiosTablesUpdateProtocol definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_SMBIOS_UPDATE_PROTOCOL_H_
36 #define _ME_SMBIOS_UPDATE_PROTOCOL_H_
37
38 ///
39 /// ME SMBIOS Update Protocol
40 ///
41
42 /**
43 This function is used to update ME SMBIOS table.
44
45 @return Standard EFI_STATUS is returned.
46 **/
47 typedef
48 EFI_STATUS
49 (EFIAPI *ME_UPDATE_SMBIOS) (
50 VOID
51 );
52
53 /**
54 ME SMBIOS Tables update protocol
55 The interface functions are to update SMBIOS type 130 (in case of AMT) and 131.
56 It is platform vendor's responsibility to implement the function instance.
57 **/
58 typedef struct {
59 ME_UPDATE_SMBIOS UpdateSmbios130;
60 ME_UPDATE_SMBIOS UpdateSmbios131;
61 } ME_SMBIOS_TABLES_UPDATE_PROTOCOL;
62
63 extern EFI_GUID gMeSmbiosTablesUpdateProtocolGuid;
64
65 #endif // _ME_SMBIOS_UPDATE_PROTOCOL_H_
ME_SMBIOS_TABLES_UPDATE_PROTOCOL
ME SMBIOS Tables update protocol The interface functions are to update SMBIOS type 130 (in case of AM...
Definition: MeSmbiosUpdateProtocol.h:58
ME_UPDATE_SMBIOS
EFI_STATUS(* ME_UPDATE_SMBIOS)(VOID)
ME SMBIOS Update Protocol.
Definition: MeSmbiosUpdateProtocol.h:49
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeState.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros
MeState.h File Reference

Register Definitions for Me States. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | ME_STATUS_ME_STATE_ONLY(a) ((a) & (~(ME_FW_INIT_COMPLETE | ME_FW_BOOT_OPTIONS_PRESENT)))
Ignore ME_FW_INIT_COMPLETE status Macro.
#define | ME_STATUS_IS_ME_FW_INIT_COMPLETE(a) (((a) & ME_FW_INIT_COMPLETE) == ME_FW_INIT_COMPLETE)
Macro to check if ME FW INIT is completed.
#define | ME_STATUS_WITH_ME_INIT_COMPLETE(a) ((a) | ME_FW_INIT_COMPLETE)
Macro to combine the complete bit to status.
#define | ME_STATUS_IS_ME_FW_BOOT_OPTIONS_PRESENT(a) (((a) & ME_FW_BOOT_OPTIONS_PRESENT) == ME_FW_BOOT_OPTIONS_PRESENT)
Macro to check ME Boot Option Present.

Detailed Description

Register Definitions for Me States.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeState.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeState.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeState.h
Go to the documentation of this file.
1 /** @file
2 Register Definitions for Me States
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_STATE_H_
36 #define _ME_STATE_H_
37 ///
38 /// Ignore ME_FW_INIT_COMPLETE status Macro
39 ///
40 #define ME_STATUS_ME_STATE_ONLY(a) ((a) & (~(ME_FW_INIT_COMPLETE | ME_FW_BOOT_OPTIONS_PRESENT)))
41
42 ///
43 /// Macro to check if ME FW INIT is completed
44 ///
45 #define ME_STATUS_IS_ME_FW_INIT_COMPLETE(a) (((a) & ME_FW_INIT_COMPLETE) == ME_FW_INIT_COMPLETE)
46
47 ///
48 /// Macro to combine the complete bit to status
49 ///
50 #define ME_STATUS_WITH_ME_INIT_COMPLETE(a) ((a) | ME_FW_INIT_COMPLETE)
51
52 ///
53 /// Macro to check ME Boot Option Present
54 ///
55 #define ME_STATUS_IS_ME_FW_BOOT_OPTIONS_PRESENT(a) (((a) & ME_FW_BOOT_OPTIONS_PRESENT) == ME_FW_BOOT_OPTIONS_PRESENT)
56
57 //
58 // Abstract ME Mode Definitions
59 //
60 #define ME_MODE_NORMAL 0x00
61 #define ME_MODE_DEBUG 0x02
62 #define ME_MODE_TEMP_DISABLED 0x03
63 #define ME_MODE_SECOVER 0x04
64 #define ME_MODE_E_DEBUG 0x07
65 #define ME_MODE_DFX_FW 0x0F
66
67 #define ME_MODE_FAILED 0x06
68
69 //
70 // Abstract ME Status definitions
71 //
72 #define ME_READY 0x00
73 #define ME_INITIALIZING 0x01
74 #define ME_IN_RECOVERY_MODE 0x02
75 #define ME_DISABLE_WAIT 0x06
76 #define ME_TRANSITION 0x07
77 #define ME_NOT_READY 0x0F
78 #define ME_FW_INIT_COMPLETE 0x80
79 #define ME_FW_BOOT_OPTIONS_PRESENT 0x100
80 #define ME_FW_UPDATES_IN_PROGRESS 0x200
81
82 //
83 // HECI Software Progress Error Code definitions.
84 // Error Code Structure: (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000x00) | ERROR_STATUS) = 0x03008x00
85 //
86 #define EFI_STATUS_TO_STATUS_CODE_VALUE(EfiStatus) ((EFI_STATUS_CODE_VALUE) (EfiStatus & 0x1F))
87
88 #define SW_HECI_ACK_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000100))
89 #define SW_HECI_RECEIVE_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000200))
90 #define SW_HECI_SEND_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000300))
91 #define SW_HECI_INIT_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000400))
92 #define SW_HECI_GET_STATUS_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000500))
93 #define SW_HECI_GET_MODE_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000600))
94 #define SW_HECI_RESET_HECI_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000700))
95 #define SW_HECI_REINIT_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000800))
96 #define SW_HECI_RESETWAIT_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000900))
97 #define SW_HECI_EOP_ERROR (EFI_SOFTWARE_UNSPECIFIED | (EFI_OEM_SPECIFIC | 0x00000A00))
98 #endif // _ME_STATE_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeTypeDefs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
MeTypeDefs.h File Reference
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

Definition in file MeTypeDefs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeTypeDefs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MeTypeDefs.h
Go to the documentation of this file.
1 /** @file
2
3 @copyright
4 INTEL CONFIDENTIAL
5 Copyright 2014 - 2020 Intel Corporation.
6
7 The source code contained or described herein and all documents related to the
8 source code ("Material") are owned by Intel Corporation or its suppliers or
9 licensors. Title to the Material remains with Intel Corporation or its suppliers
10 and licensors. The Material may contain trade secrets and proprietary and
11 confidential information of Intel Corporation and its suppliers and licensors,
12 and is protected by worldwide copyright and trade secret laws and treaty
13 provisions. No part of the Material may be used, copied, reproduced, modified,
14 published, uploaded, posted, transmitted, distributed, or disclosed in any way
15 without Intel's prior express written permission.
16
17 No license under any patent, copyright, trade secret or other intellectual
18 property right is granted to or conferred upon you by disclosure or delivery
19 of the Materials, either expressly, by implication, inducement, estoppel or
20 otherwise. Any license under such intellectual property rights must be
21 express and approved by Intel in writing.
22
23 Unless otherwise agreed by Intel in writing, you may not remove or alter
24 this notice or any other notice embedded in Materials by Intel or
25 Intel's suppliers or licensors in any way.
26 **/
27
28 #ifndef _ME_TYPE_DEFS_H_
29 #define _ME_TYPE_DEFS_H_
30
31 // definitions for use in hfr files
32 #define METYPE_SPS 0x01
33 #define METYPE_SPS_EPO 0x02
34 #define METYPE_CLIENT 0x03
35 #define METYPE_IGNITION 0x07
36 #define METYPE_DFX 0x0F
37 #define METYPE_UNDEF 0xEE
38 #define METYPE_DISABLED 0xFF
39
40
41 // if METYPE == METYPE_SPS
42 #define MESUBTYPE_SPS_TYPE_E5 0x01
43 #define MESUBTYPE_SPS_TYPE_E3 0x02
44 #define MESUBTYPE_SPS_TYPE_DFX 0x03
45 #define MESUBTYPE_TYPE_IGNITION 0x07
46
47 // if METYPE == METYPE_SPS_EPO
48 #define MESUBTYPE_SPS_TYPE_EPO 0x01
49
50 // if METYPE == METYPE_CLIENT
51 #define MESUBTYPE_WS_TYPE_CLIENT 0x01
52 #define MESUBTYPE_WS_TYPE_HEDT 0x02
53 #define MESUBTYPE_WS_TYPE_WS 0x03
54
55
56 #endif // _ME_TYPE_DEFS_H_
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeTypeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
MeTypeLib.h File Reference

Header for ME type library. More...

#include <MeTypeDefs.h>
Include dependency graph for MeTypeLib.h:

Go to the source code of this file.

Enumerations

enum ME_TYPE
Define all the types of CSME firmware.

Functions

ME_TYPE | MeTypeGet (VOID)
Get detected Me FW type. More...
BOOLEAN | MeTypeIsDfx (VOID)
Checks if Me FW is DFX type. More...
BOOLEAN | MeTypeIsDisabled (VOID)
Checks if Me FW is DISABLED type. More...
BOOLEAN | MeTypeIsSps (VOID)
Checks if Me FW is SPS type. More...
BOOLEAN | MeTypeIsIgnition (VOID)
Checks if Me FW is Ignition type. More...
BOOLEAN | MeTypeIsClient (VOID)
Checks if Me FW is Client type. More...
VOID | PrintMeType (IN CHAR16 *DispString)
Print the the ME FW Type and Subtype.
VOID | MeTypeShowDebug (IN CHAR16 *dispString)
Displays debug information about detected Me FW type. More...
EFI_STATUS | GetMeFwTypeSubTypeFromHob (OUT UINT8 *FwType, OUT UINT8 *FwSubType)
Get ME FW type and subtype from HOB. More...

Detailed Description

Header for ME type library.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeTypeLib.h.

Function Documentation

◆ GetMeFwTypeSubTypeFromHob()

EFI_STATUS GetMeFwTypeSubTypeFromHob | ( | OUT UINT8 * | FwType,
 |  | OUT UINT8 * | FwSubType
 | ) |  |

Get ME FW type and subtype from HOB.

Parameters
[out] | FwType | ME FW type
[out] | FwSubType | ME FW subtype
Return values
EFI_SUCCESS | Success
EFI_UNSUPPORTED | Not supported
EFI_INVALID_PARAMETER | Both parameters are NULL
EFI_NOT_FOUND | Cannot get MeType HOB

◆ MeTypeGet()

ME_TYPE MeTypeGet ( VOID )

Get detected Me FW type.

Return values
MeType

◆ MeTypeIsClient()

BOOLEAN MeTypeIsClient ( VOID )

Checks if Me FW is Client type.

Return values
FALSE | No Client ME on board
TRUE | Client ME detected

◆ MeTypeIsDfx()

BOOLEAN MeTypeIsDfx ( VOID )

Checks if Me FW is DFX type.

Return values
FALSE | No Dfx ME on board
TRUE | Dfx ME detected

◆ MeTypeIsDisabled()

BOOLEAN MeTypeIsDisabled ( VOID )

Checks if Me FW is DISABLED type.

Return values
FALSE | ME is not disabled
TRUE | ME is disabled

◆ MeTypeIsIgnition()

BOOLEAN MeTypeIsIgnition ( VOID )

Checks if Me FW is Ignition type.

Return values
FALSE | No Ignition on board
TRUE | Ignition detected

◆ MeTypeIsSps()

BOOLEAN MeTypeIsSps ( VOID )

Checks if Me FW is SPS type.

Return values
FALSE | No SPS on board
TRUE | SPS detected

◆ MeTypeShowDebug()

VOID MeTypeShowDebug ( IN CHAR16 * dispString )

Displays debug information about detected Me FW type.

Parameters
[in] Leading debug string
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeTypeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeTypeLib.h
Go to the documentation of this file.
1 /** @file
2 Header for ME type library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _ME_TYPE_LIB_H_
36 #define _ME_TYPE_LIB_H_
37
38 #include <MeTypeDefs.h>
39
40 ///
41 /// Define all the types of CSME firmware
42 ///
43 typedef enum {
44 MeTypeSps = METYPE_SPS,
45 MeTypeSpsEpo = METYPE_SPS_EPO,
46 MeTypeClient = METYPE_CLIENT,
47 MeTypeIgnition = METYPE_IGNITION,
48 MeTypeDfx = METYPE_DFX,
49 MeTypeUndef = METYPE_UNDEF,
50 MeTypeDisabled = METYPE_DISABLED
51 } ME_TYPE;
52
53 /**
54 Get detected Me FW type
55
56 @retval MeType
57 **/
58 ME_TYPE
59 MeTypeGet (
60 VOID
61 );
62
63 /**
64 Checks if Me FW is DFX type
65
66 @retval FALSE No Dfx ME on board
67 @retval TRUE Dfx ME detected
68 **/
69 BOOLEAN
70 MeTypeIsDfx (
71 VOID
72 );
73
74 /**
75 Checks if Me FW is DISABLED type
76
77 @retval FALSE ME is not disabled
78 @retval TRUE ME is disabled
79 **/
80 BOOLEAN
81 MeTypeIsDisabled (
82 VOID
83 );
84
85 /**
86 Checks if Me FW is SPS type
87
88 @retval FALSE No SPS on board
89 @retval TRUE SPS detected
90 **/
91 BOOLEAN
92 MeTypeIsSps (
93 VOID
94 );
95
96 /**
97 Checks if Me FW is Ignition type
98
99 @retval FALSE No Ignition on board
100 @retval TRUE Ignition detected
101 **/
102 BOOLEAN
103 MeTypeIsIgnition (
104 VOID
105 );
106
107 /**
108 Checks if Me FW is Client type
109
110 @retval FALSE No Client ME on board
111 @retval TRUE Client ME detected
112 **/
113 BOOLEAN
114 MeTypeIsClient (
115 VOID
116 );
117
118 /**
119 Print the the ME FW Type and Subtype.
120 **/
121 VOID
122 EFIAPI
123 PrintMeType (
124 IN CHAR16 *DispString
125 );
126
127 /**
128 Displays debug information about detected Me FW type
129
130 @param[in] Leading debug string
131 **/
132 VOID
133 MeTypeShowDebug (
134 IN CHAR16 *dispString
135 );
136
137 /**
138 Get ME FW type and subtype from HOB.
139
140 @param[out] FwType ME FW type
141 @param[out] FwSubType ME FW subtype
142
143 @retval EFI_SUCCESS Success
144 @retval EFI_UNSUPPORTED Not supported
145 @retval EFI_INVALID_PARAMETER Both parameters are NULL
146 @retval EFI_NOT_FOUND Cannot get MeType HOB
147 **/
148 EFI_STATUS
149 GetMeFwTypeSubTypeFromHob (
150 OUT UINT8 *FwType,
151 OUT UINT8 *FwSubType
152 );
153 #endif // _ME_TYPE_LIB_H_
154
MeTypeIsIgnition
BOOLEAN MeTypeIsIgnition(VOID)
Checks if Me FW is Ignition type.
ME_TYPE
ME_TYPE
Define all the types of CSME firmware.
Definition: MeTypeLib.h:43
PrintMeType
VOID PrintMeType(IN CHAR16 *DispString)
Print the the ME FW Type and Subtype.
MeTypeIsClient
BOOLEAN MeTypeIsClient(VOID)
Checks if Me FW is Client type.
MeTypeIsDfx
BOOLEAN MeTypeIsDfx(VOID)
Checks if Me FW is DFX type.
MeTypeShowDebug
VOID MeTypeShowDebug(IN CHAR16 *dispString)
Displays debug information about detected Me FW type.
MeTypeIsSps
BOOLEAN MeTypeIsSps(VOID)
Checks if Me FW is SPS type.
MeTypeDefs.h
MeTypeGet
ME_TYPE MeTypeGet(VOID)
Get detected Me FW type.
GetMeFwTypeSubTypeFromHob
EFI_STATUS GetMeFwTypeSubTypeFromHob(OUT UINT8 *FwType, OUT UINT8 *FwSubType)
Get ME FW type and subtype from HOB.
MeTypeIsDisabled
BOOLEAN MeTypeIsDisabled(VOID)
Checks if Me FW is DISABLED type.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeUefiFwHealthStatusLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
MeUefiFwHealthStatusLib.h File Reference

Definitions for Me Uefi Health Status Library. More...

Go to the source code of this file.

Functions

EFI_STATUS | SetMeUefiFwHealthStatus (IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, IN ME_UEFI_FW_HEALTH_STATUS HealthStatus)
Function sets value of determined field in MeUefiFwHealthStatus HOB. More...
EFI_STATUS | GetMeUefiFwHealthStatus (IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, OUT ME_UEFI_FW_HEALTH_STATUS *HealthStatus)
Function gets value of determined field from MeUefiFwHealthStatus HOB. More...
EFI_STATUS | SetMeUefiFwHealthEfiStatus (ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, EFI_STATUS EfiStatus)
Function sets value (only StatusOk or StatusError) of the determined field in MeUefiFwHealthStatus HOB, depending on the received value of Efi Status. More...

Detailed Description

Definitions for Me Uefi Health Status Library.

Implements Health Status Library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MeUefiFwHealthStatusLib.h.

Function Documentation

◆ GetMeUefiFwHealthStatus()

EFI_STATUS GetMeUefiFwHealthStatus | ( | IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID | FieldId,
 |  | OUT ME_UEFI_FW_HEALTH_STATUS * | HealthStatus
 | ) |  |

Function gets value of determined field from MeUefiFwHealthStatus HOB.

Parameters
[in] | FieldId | MeUefiFwHealthStatus field id
[out] | HealthStatus | status of determined field
Return values
EFI_SUCCESS | The function completed successfully
EFI_INVALID_PARAMETER | Pointer to HealthStatus is NULL
EFI_OUT_OF_RESOURCES | MeUefiFwHealthStatus HOB doesn't exist
EFI_COMPROMISED_DATA | HOB data is not valid
EFI_UNSUPPORTED | MeUefiFwHealthStatus is not supported

◆ SetMeUefiFwHealthEfiStatus()

EFI_STATUS SetMeUefiFwHealthEfiStatus | ( | ME_UEFI_FW_HEALTH_STATUS_FIELD_ID | FieldId,
 |  | EFI_STATUS | EfiStatus
 | ) |  |

Function sets value (only StatusOk or StatusError) of the determined field in MeUefiFwHealthStatus HOB, depending on the received value of Efi Status.

Parameters
[in] | FieldId | MeUefiFwHealthStatus field id
[in] | Status | EFI status for determined field
Return values
EFI_SUCCESS | The function completed successfully.
EFI_OUT_OF_RESOURCES | HOB creation failed

◆ SetMeUefiFwHealthStatus()

EFI_STATUS SetMeUefiFwHealthStatus | ( | IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID | FieldId,
 |  | IN ME_UEFI_FW_HEALTH_STATUS | HealthStatus
 | ) |  |

Function sets value of determined field in MeUefiFwHealthStatus HOB.

When called in PEI with FieldId == HealthStatusFieldNumMax, HOB is created only.

Parameters
[in] | FieldId | MeUefiFwHealthStatus field id
[in] | HealthStatus | required status for determined field
Return values
EFI_SUCCESS | The function completed successfully.
EFI_OUT_OF_RESOURCES | HOB creation failed
EFI_COMPROMISED_DATA | HOB data is not valid
Returns
EFI_UNSUPPORTED HOB can't be created at DXE phase
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeUefiFwHealthStatusLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeUefiFwHealthStatusLib.h
Go to the documentation of this file.
1 /** @file
2 Definitions for Me Uefi Health Status Library.
3 Implements Health Status Library.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2018 - 2020 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _ME_UEFI_FW_HEALTH_STATUS_LIB_H_
38 #define _ME_UEFI_FW_HEALTH_STATUS_LIB_H_
39
40
41 typedef enum {
42 // Drivers' status
43 Heci1PpiInstalledStatus,
44 Heci2PpiInstalledStatus,
45 Heci3PpiInstalledStatus,
46 Heci4PpiInstalledStatus,
47 Heci1DxeInstalledStatus,
48 Heci2DxeInstalledStatus,
49 Heci3DxeInstalledStatus,
50 Heci4DxeInstalledStatus,
51 Heci1SmmInstalledStatus,
52 Heci2SmmInstalledStatus,
53 Heci3SmmInstalledStatus,
54 Heci4SmmInstalledStatus,
55 // Sending Status
56 DidSendingStatus,
57 CoreBiosDoneSendingStatus,
58 EndOfPostSendingStatus,
59 MeConfigDoneSendingStatus,
60 SscDisableSendingStatus,
61 // Receiving Status
62 MeUmaSizeInfoReceivingStatus,
63 BiosPayloadForWsReceivingStatus,
64 // State of ME devices
65 Heci1State,
66 Heci2State,
67 Heci3State,
68 Heci4State,
69 IdeRState,
70 KTState,
71 AcpiFilesLoadingStatus,
72 Heci1HideInMe,
73 Heci2HideInMe,
74 Heci3HideInMe,
75 Heci4HideInMe,
76
77 HealthStatusFieldNumMax,
78 } ME_UEFI_FW_HEALTH_STATUS_FIELD_ID;
79
80 typedef enum {
81 StatusNotTriggeredSupported = 0, // not triggerred/supported
82 StatusError = 1, // error status
83 StatusOk = 2, // OK status
84 StatusOther = 3, // status for other purpose
85 } ME_UEFI_FW_HEALTH_STATUS;
86
87 /**
88 Function sets value of determined field in MeUefiFwHealthStatus HOB.
89 When called in PEI with FieldId == HealthStatusFieldNumMax, HOB is created only.
90
91 @param[in] FieldId MeUefiFwHealthStatus field id
92 @param[in] HealthStatus required status for determined field
93
94 @retval EFI_SUCCESS The function completed successfully.
95 @retval EFI_OUT_OF_RESOURCES HOB creation failed
96 @retval EFI_COMPROMISED_DATA HOB data is not valid
97 @return EFI_UNSUPPORTED HOB can't be created at DXE phase
98 **/
99 EFI_STATUS
100 SetMeUefiFwHealthStatus (
101 IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId,
102 IN ME_UEFI_FW_HEALTH_STATUS HealthStatus
103 );
104
105 /**
106 Function gets value of determined field from MeUefiFwHealthStatus HOB.
107
108 @param[in] FieldId MeUefiFwHealthStatus field id
109 @param[out] HealthStatus status of determined field
110
111 @retval EFI_SUCCESS The function completed successfully
112 @retval EFI_INVALID_PARAMETER Pointer to HealthStatus is NULL
113 @retval EFI_OUT_OF_RESOURCES MeUefiFwHealthStatus HOB doesn't exist
114 @retval EFI_COMPROMISED_DATA HOB data is not valid
115 @retval EFI_UNSUPPORTED MeUefiFwHealthStatus is not supported
116 **/
117 EFI_STATUS
118 GetMeUefiFwHealthStatus (
119 IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId,
120 OUT ME_UEFI_FW_HEALTH_STATUS *HealthStatus
121 );
122
123 /**
124 Function sets value (only StatusOk or StatusError) of the determined field in MeUefiFwHealthStatus HOB,
125 depending on the received value of Efi Status.
126
127 @param[in] FieldId MeUefiFwHealthStatus field id
128 @param[in] Status EFI status for determined field
129
130 @retval EFI_SUCCESS The function completed successfully.
131 @retval EFI_OUT_OF_RESOURCES HOB creation failed
132 **/
133 EFI_STATUS
134 SetMeUefiFwHealthEfiStatus (
135 ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId,
136 EFI_STATUS EfiStatus
137 );
138 #endif // _ME_UEFI_FW_HEALTH_STATUS_LIB_H_
SetMeUefiFwHealthStatus
EFI_STATUS SetMeUefiFwHealthStatus(IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, IN ME_UEFI_FW_HEALTH_STATUS HealthStatus)
Function sets value of determined field in MeUefiFwHealthStatus HOB.
SetMeUefiFwHealthEfiStatus
EFI_STATUS SetMeUefiFwHealthEfiStatus(ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, EFI_STATUS EfiStatus)
Function sets value (only StatusOk or StatusError) of the determined field in MeUefiFwHealthStatus HO...
GetMeUefiFwHealthStatus
EFI_STATUS GetMeUefiFwHealthStatus(IN ME_UEFI_FW_HEALTH_STATUS_FIELD_ID FieldId, OUT ME_UEFI_FW_HEALTH_STATUS *HealthStatus)
Function gets value of determined field from MeUefiFwHealthStatus HOB.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeUtilsLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
MeUtilsLib.h File Reference

HECI utilities for use in PEI, DXE, and SMM. More...

#include <Library/SmmServicesTableLib.h>
Include dependency graph for MeUtilsLib.h:

Go to the source code of this file.

Enumerations

enum HECI_API_VERSION
HECI_API_VERSION defines what HECI API is returned by GetHeci ()

Functions

BOOLEAN | IsInSmm (IN OUT EFI_SMM_SYSTEM_TABLE2 **SmmSystemTable2)
Get Information is we are running in SMM or not. More...
EFI_STATUS | MeBiosGetMeMode (OUT UINT32 *MeMode)
Return ME Mode. More...
EFI_STATUS | MeBiosGetMeStatusRaw (OUT UINT32 *MeStatus)
Get an Intel ME Firmware Status from HECI-1 HFS register. More...
EFI_STATUS | MeBiosGetMeStatus (OUT UINT32 *MeStatus)
Get an abstract Intel ME Firmware Status from HECI-1 HFS register. More...
EFI_STATUS | ResetHeci1Interface (VOID)
Function forces a reinit of the heci interface by following the reset heci interface via host algorithm in HPS 0.90 doc 4-17-06. More...
UINTN | GetHeciPciSegment (VOID)
Get HECI PCI Segment. More...
UINTN | GetHeciPciBus (VOID)
Get HECI PCI Bus. More...
UINTN | GetHeciPciDevice (VOID)
Get HECI PCI Device Number. More...
BOOLEAN | MeClientIsReady (VOID)
Checks if Me FW is Client and it is ready. More...
BOOLEAN | MeClientIsCorporate (VOID)
Checks if Me FW is Client Corporate. More...
BOOLEAN | MeSpsIsReady (VOID)
Checks if Me FW is SPS ready. More...
BOOLEAN | MeSpsInRecovery (VOID)
Checks if Me FW is SPS in recovery. More...
BOOLEAN | MeClientInRecovery (VOID)
Checks if Me FW is Client in manufacturing. More...
BOOLEAN | MeIsInRecovery (VOID)
Checks if Me is in manufacturing. More...
BOOLEAN | MeSpsIsNm (VOID)
Checks if Me FW is SPS NM. More...
UINT32 | GetMeFwsts1FromHob (IN UINT32 Mefs1)
Reads ME Firmware Status 1 information from HOB. More...
VOID * | GetHeci (OUT HECI_API_VERSION *HeciVersion)
Gets Heci PPI/Protocol, returns pointer to HECI PPI/Protocol. More...
EFI_STATUS | HeciSendWithAck (IN VOID *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 Retries, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *ReqMsg, IN UINT32 ReqLen, OUT UINT32 *RspMsg, IN OUT UINT32 *RspLen, IN OUT EFI_STATUS *SendStatus, IN OUT EFI_STATUS *ReceiveStatus)
Wrapper for Heci HeciSendAndReceive HECI_CONTROL function. More...
BOOLEAN | GetInitComplete (OUT UINT32 *ReturnMeFs1)
Get InitComplete from Firmware Status. More...
BOOLEAN | GetSpsEndOfPostStatus (OUT UINT32 *ReturnMeFs2)
Get SPS End Of Post from Firmware Status. More...
VOID | GetMcaMsgParams (IN UINT32 Command, OUT UINT8 *GroupId, OUT UINT8 *MeClientAddress)
Returns the GroupId and Me Client Address for former MCA messages. More...
EFI_STATUS | WaitFirmwareInitComplete (IN UINT32 Timeout)
Wait until Firmware Init Complete is set in Firmware Status Register 1 [BIT9]. More...
VOID | GenerateUserNonce (IN UINT32 NonceSize, OUT UINT8 *NonceArray)
Generate User Nonce as an array of "NonceSize" bytes. More...

Detailed Description

HECI utilities for use in PEI, DXE, and SMM.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file MeUtilsLib.h.

Function Documentation

◆ GenerateUserNonce()

VOID GenerateUserNonce | ( | IN UINT32 | NonceSize,
 |  | OUT UINT8 * | NonceArray
 | ) |  |

Generate User Nonce as an array of "NonceSize" bytes.

Parameters
[in] | NonceSize | Size of nonce array to be generated
[out] | NonceArray | User Nonce array

◆ GetHeci()

VOID* GetHeci ( OUT HECI_API_VERSION * HeciVersion )

Gets Heci PPI/Protocol, returns pointer to HECI PPI/Protocol.

Parameters
[out] HeciVersion HECI interface API Version
Return values
Valid | pointer Pointer to HECI PPI/Protocol
NULL | Error, PPI/Protocol not found

◆ GetHeciPciBus()

UINTN GetHeciPciBus ( VOID )

Get HECI PCI Bus.

Return values
HECI PCI Bus

◆ GetHeciPciDevice()

UINTN GetHeciPciDevice ( VOID )

Get HECI PCI Device Number.

Return values
HECI PCI Device Number

◆ GetHeciPciSegment()

UINTN GetHeciPciSegment ( VOID )

Get HECI PCI Segment.

Return values
HECI PCI Segment

◆ GetInitComplete()

BOOLEAN GetInitComplete ( OUT UINT32 * ReturnMeFs1 )

Get InitComplete from Firmware Status.

Parameters
[out] ReturnMeFs1 Pointer to return ME Firmware Status 1
Return values
FALSE | InitComplete bit is not set
TRUE | InitComplete bit is set

◆ GetMcaMsgParams()

VOID GetMcaMsgParams | ( | IN UINT32 | Command,
 |  | OUT UINT8 * | GroupId,
 |  | OUT UINT8 * | MeClientAddress
 | ) |  |

Returns the GroupId and Me Client Address for former MCA messages.

If no MhkiVersion HOB exists use HECI_MCHI_MESSAGE_ADDR and MKHI_MCA_GROUP_ID as a default.

Parameters
[in] | Command | Former MCA Command
[out] | GroupId | GroupId for the given command
[out] | MeClientAddress | Me Client for the given command

◆ GetMeFwsts1FromHob()

UINT32 GetMeFwsts1FromHob ( IN UINT32 Mefs1 )

Reads ME Firmware Status 1 information from HOB.

Parameters
[in] Mefs1 Current Mefs1 that will be return in error case
Return values
On | Error: Passed in Mefs1
On | Success: MEFS1

◆ GetSpsEndOfPostStatus()

BOOLEAN GetSpsEndOfPostStatus ( OUT UINT32 * ReturnMeFs2 )

Get SPS End Of Post from Firmware Status.

Parameters
[out] ReturnMeFs2 Pointer to return ME Firmware Status 2
Return values
FALSE | EndOfPost bit is not set
TRUE | EndOfPost bit is set

◆ HeciSendWithAck()

EFI_STATUS HeciSendWithAck | ( | IN VOID * | This,
 |  | IN UINT32 | HeciPchId,
 |  | IN OUT UINT32 * | Timeout,
 |  | IN UINT8 | Retries,
 |  | IN UINT8 | HostAddress,
 |  | IN UINT8 | EngineAddress,
 |  | IN UINT32 * | ReqMsg,
 |  | IN UINT32 | ReqLen,
 |  | OUT UINT32 * | RspMsg,
 |  | IN OUT UINT32 * | RspLen,
 |  | IN OUT EFI_STATUS * | SendStatus,
 |  | IN OUT EFI_STATUS * | ReceiveStatus
 | ) |  |

Wrapper for Heci HeciSendAndReceive HECI_CONTROL function.

Parameters
[in] | This | Heci instance
[in] | HeciPchId | PchId we want to communicate with 0..N HECI_DEFAULT_PCH_ID Id is default and HeciControl decides where to route communication
[in,out] | Timeout | On input timeout in us, on exit time left
[in] | Retries | The number of retries requested (0 => no retry)
[in] | HostAddress | Host address
[in] | EngineAddress | Engine (ME/IE) address
[in] | ReqMsg | Request message
[in] | ReqLen | Request message length in bytes
[out] | RspMsg | Buffer for the response message
[in,out] | RspLen | On input buffer size, on exit message, in bytes
[in,out] | SendStatus | Send operation status
[in,out] | ReceiveStatus | Receive operation status
Return values
EFI_INVALID_PARAMETER | Input parameters are invalid
EFI_WRITE_PROTECTED | Can't find suitable HECI Transport Possible reason: HECI filter active
EFI_DEVICE_ERROR | HECI MBar can't be initialized
EFI_TIMEOUT | Timeout occurs during operation
EFI_BAD_BUFFER_SIZE | Message is too big
EFI_SUCCESS | Message request has been completed successfully

◆ IsInSmm()

BOOLEAN IsInSmm ( IN OUT EFI_SMM_SYSTEM_TABLE2 ** SmmSystemTable2 )

Get Information is we are running in SMM or not.

Parameters
[in,out] Pointer to EFI_SMM_SYSTEM_TABLE2 pointer
Return values
TRUE | We are in SMM
FALSE | We are not in SMM

◆ MeBiosGetMeMode()

EFI_STATUS MeBiosGetMeMode ( OUT UINT32 * MeMode )

Return ME Mode.

Parameters
[out] MeMode Pointer for ME Mode report
Return values
EFI_SUCCESS | MeMode copied
EFI_INVALID_PARAMETER | Pointer of MeMode is invalid

◆ MeBiosGetMeStatus()

EFI_STATUS MeBiosGetMeStatus ( OUT UINT32 * MeStatus )

Get an abstract Intel ME Firmware Status from HECI-1 HFS register.

This is used to control BIOS flow for various Intel ME functions.

Parameters
[out] MeStatus Pointer for status report see MeState.h - Abstract ME status definitions.
Return values
EFI_SUCCESS | MeStatus copied
EFI_INVALID_PARAMETER | Pointer of MeStatus is invalid

◆ MeBiosGetMeStatusRaw()

EFI_STATUS MeBiosGetMeStatusRaw ( OUT UINT32 * MeStatus )

Get an Intel ME Firmware Status from HECI-1 HFS register.

Parameters
[out] MeStatus Pointer for status report
Return values
EFI_SUCCESS | MeStatus copied
EFI_INVALID_PARAMETER | Pointer of MeStatus is invalid
EFI_DEVICE_ERROR | Read device is not HECI

◆ MeClientInRecovery()

BOOLEAN MeClientInRecovery ( VOID )

Checks if Me FW is Client in manufacturing.

Return values
FALSE Client is not in recovery
TRUE CLient is in recovery

◆ MeClientIsCorporate()

BOOLEAN MeClientIsCorporate ( VOID )

Checks if Me FW is Client Corporate.

Return values
FALSE | Not ME Client corporate
TRUE | Corporate Client ME detected

◆ MeClientIsReady()

BOOLEAN MeClientIsReady ( VOID )

Checks if Me FW is Client and it is ready.

Return values
FALSE | Not ME Client and ready
TRUE | Ready Client ME detected

◆ MeIsInRecovery()

BOOLEAN MeIsInRecovery ( VOID )

Checks if Me is in manufacturing.

Return values
FALSE | ME is not in recovery
TRUE | ME is in recovery

◆ MeSpsInRecovery()

BOOLEAN MeSpsInRecovery ( VOID )

Checks if Me FW is SPS in recovery.

Return values
FALSE | SPS is not in recovery
TRUE | SPS is in recovery

◆ MeSpsIsNm()

BOOLEAN MeSpsIsNm ( VOID )

Checks if Me FW is SPS NM.

Return values
FALSE | SPS NM not detected
TRUE | SPS NM detected

◆ MeSpsIsReady()

BOOLEAN MeSpsIsReady ( VOID )

Checks if Me FW is SPS ready.

Return values
FALSE | SPS is not ready
TRUE | Ready SPS detected

◆ ResetHeci1Interface()

EFI_STATUS ResetHeci1Interface ( VOID )

Function forces a reinit of the heci interface by following the reset heci interface via host algorithm in HPS 0.90 doc 4-17-06.

Return values
EFI_TIMEOUT | ME is not ready
EFI_SUCCESS | Interface reset
EFI_UNSUPPORTED | Not supported

◆ WaitFirmwareInitComplete()

EFI_STATUS WaitFirmwareInitComplete ( IN UINT32 Timeout )

Wait until Firmware Init Complete is set in Firmware Status Register 1 [BIT9].

Parameters
[in] Timeout Time in microseconds
Return values
EFI_SUCCESS | Firmware Init Complete bit is set
EFI_TIMEOUT | Firmware Init Complete bit is not set within specified time
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MeUtilsLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MeUtilsLib.h
Go to the documentation of this file.
1 /** @file
2 HECI utilities for use in PEI, DXE, and SMM.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 **/
34
35 #ifndef _ME_UTILS_LIB_H_
36 #define _ME_UTILS_LIB_H_
37
38 #include <Library/SmmServicesTableLib.h>
39
40 /**
41 Get Information is we are running in SMM or not
42
43 @param[in, out] Pointer to EFI_SMM_SYSTEM_TABLE2 pointer
44
45 @retval TRUE We are in SMM
46 @retval FALSE We are not in SMM
47 **/
48 BOOLEAN
49 IsInSmm (
50 IN OUT EFI_SMM_SYSTEM_TABLE2 **SmmSystemTable2
51 );
52
53 /**
54 Return ME Mode
55
56 @param [out] MeMode Pointer for ME Mode report
57
58 @retval EFI_SUCCESS MeMode copied
59 @retval EFI_INVALID_PARAMETER Pointer of MeMode is invalid
60 **/
61 EFI_STATUS
62 MeBiosGetMeMode (
63 OUT UINT32 *MeMode
64 );
65
66 /**
67 Get an Intel ME Firmware Status from HECI-1 HFS register.
68
69 @param [out] MeStatus Pointer for status report
70
71
72 @retval EFI_SUCCESS MeStatus copied
73 @retval EFI_INVALID_PARAMETER Pointer of MeStatus is invalid
74 @retval EFI_DEVICE_ERROR Read device is not HECI
75 **/
76 EFI_STATUS
77 MeBiosGetMeStatusRaw (
78 OUT UINT32 *MeStatus
79 );
80
81 /**
82 Get an abstract Intel ME Firmware Status from HECI-1 HFS register.
83 This is used to control BIOS flow for various Intel ME functions.
84
85 @param [out] MeStatus Pointer for status report
86 see MeState.h - Abstract ME status definitions.
87
88 @retval EFI_SUCCESS MeStatus copied
89 @retval EFI_INVALID_PARAMETER Pointer of MeStatus is invalid
90 **/
91 EFI_STATUS
92 MeBiosGetMeStatus (
93 OUT UINT32 *MeStatus
94 );
95
96 /**
97 Function forces a reinit of the heci interface by following the reset heci interface via host algorithm
98 in HPS 0.90 doc 4-17-06
99
100 @retval EFI_TIMEOUT ME is not ready
101 @retval EFI_SUCCESS Interface reset
102 @retval EFI_UNSUPPORTED Not supported
103 **/
104 EFI_STATUS
105 ResetHeci1Interface (
106 VOID
107 );
108
109 /**
110 Get HECI PCI Segment
111
112 @retval HECI PCI Segment
113 **/
114 UINTN
115 GetHeciPciSegment (
116 VOID
117 );
118
119 /**
120 Get HECI PCI Bus
121
122 @retval HECI PCI Bus
123 **/
124 UINTN
125 GetHeciPciBus (
126 VOID
127 );
128
129 /**
130 Get HECI PCI Device Number
131
132 @retval HECI PCI Device Number
133 **/
134 UINTN
135 GetHeciPciDevice (
136 VOID
137 );
138
139 /**
140 Checks if Me FW is Client and it is ready
141
142 @retval FALSE Not ME Client and ready
143 @retval TRUE Ready Client ME detected
144 **/
145 BOOLEAN
146 MeClientIsReady (
147 VOID
148 );
149
150 /**
151 Checks if Me FW is Client Corporate
152
153 @retval FALSE Not ME Client corporate
154 @retval TRUE Corporate Client ME detected
155 **/
156 BOOLEAN
157 MeClientIsCorporate (
158 VOID
159 );
160
161 /**
162 Checks if Me FW is SPS ready
163
164 @retval FALSE SPS is not ready
165 @retval TRUE Ready SPS detected
166 **/
167 BOOLEAN
168 MeSpsIsReady (
169 VOID
170 );
171
172 /**
173 Checks if Me FW is SPS in recovery
174
175 @retval FALSE SPS is not in recovery
176 @retval TRUE SPS is in recovery
177 **/
178 BOOLEAN
179 MeSpsInRecovery (
180 VOID
181 );
182
183 /**
184 Checks if Me FW is Client in manufacturing
185
186 @retval FALSE Client is not in recovery
187 @retval TRUE CLient is in recovery
188 -**/
189 BOOLEAN
190 MeClientInRecovery (
191 VOID
192 );
193
194 /**
195 Checks if Me is in manufacturing
196
197 @retval FALSE ME is not in recovery
198 @retval TRUE ME is in recovery
199 **/
200 BOOLEAN
201 MeIsInRecovery (
202 VOID
203 );
204
205 /**
206 Checks if Me FW is SPS NM
207
208 @retval FALSE SPS NM not detected
209 @retval TRUE SPS NM detected
210 **/
211 BOOLEAN
212 MeSpsIsNm (
213 VOID
214 );
215
216 /**
217 Reads ME Firmware Status 1 information from HOB
218
219 @param [in] Mefs1 Current Mefs1 that will be return in error case
220
221 @retval On Error: Passed in Mefs1
222 @retval On Success: MEFS1
223
224 **/
225 UINT32
226 GetMeFwsts1FromHob (
227 IN UINT32 Mefs1
228 );
229
230 ///
231 /// HECI_API_VERSION defines
232 /// what HECI API is returned by GetHeci ()
233 ///
234 typedef enum {
235 HeciApiHeciProtocol, // Legacy HECI
236 HeciApiHeciControl, // HECI_CONTROL
237 HeciApiUnknown = MAX_UINT32
238 } HECI_API_VERSION;
239
240 /**
241 Gets Heci PPI/Protocol, returns pointer to HECI PPI/Protocol
242
243 @param[out] HeciVersion HECI interface API Version
244
245 @retval Valid pointer Pointer to HECI PPI/Protocol
246 @retval NULL Error, PPI/Protocol not found
247 **/
248 VOID*
249 GetHeci (
250 OUT HECI_API_VERSION *HeciVersion
251 );
252
253 /**
254 Wrapper for Heci HeciSendAndReceive HECI_CONTROL function
255
256 @param[in] This Heci instance
257 @param[in] HeciPchId PchId we want to communicate with 0..N
258 HECI_DEFAULT_PCH_ID Id is default and
259 HeciControl decides where to route communication
260 @param[in,out] Timeout On input timeout in us, on exit time left
261 @param[in] Retries The number of retries requested (0 => no retry)
262 @param[in] HostAddress Host address
263 @param[in] EngineAddress Engine (ME/IE) address
264 @param[in] ReqMsg Request message
265 @param[in] ReqLen Request message length in bytes
266 @param[out] RspMsg Buffer for the response message
267 @param[in,out] RspLen On input buffer size, on exit message, in bytes
268 @param[in,out] SendStatus Send operation status
269 @param[in,out] ReceiveStatus Receive operation status
270
271 @retval EFI_INVALID_PARAMETER Input parameters are invalid
272 @retval EFI_WRITE_PROTECTED Can't find suitable HECI Transport
273 Possible reason: HECI filter active
274 @retval EFI_DEVICE_ERROR HECI MBar can't be initialized
275 @retval EFI_TIMEOUT Timeout occurs during operation
276 @retval EFI_BAD_BUFFER_SIZE Message is too big
277 @retval EFI_SUCCESS Message request has been completed successfully
278 **/
279 EFI_STATUS
280 HeciSendWithAck (
281 IN VOID *This,
282 IN UINT32 HeciPchId,
283 IN OUT UINT32 *Timeout,
284 IN UINT8 Retries,
285 IN UINT8 HostAddress,
286 IN UINT8 EngineAddress,
287 IN UINT32 *ReqMsg,
288 IN UINT32 ReqLen,
289 OUT UINT32 *RspMsg,
290 IN OUT UINT32 *RspLen,
291 IN OUT EFI_STATUS *SendStatus,
292 IN OUT EFI_STATUS *ReceiveStatus
293 );
294
295 /**
296 Get InitComplete from Firmware Status
297
298 @param[out] ReturnMeFs1 Pointer to return ME Firmware Status 1
299
300 @retval FALSE InitComplete bit is not set
301 @retval TRUE InitComplete bit is set
302 **/
303 BOOLEAN
304 GetInitComplete (
305 OUT UINT32 *ReturnMeFs1
306 );
307
308 /**
309 Get SPS End Of Post from Firmware Status
310
311 @param[out] ReturnMeFs2 Pointer to return ME Firmware Status 2
312
313 @retval FALSE EndOfPost bit is not set
314 @retval TRUE EndOfPost bit is set
315 **/
316 BOOLEAN
317 GetSpsEndOfPostStatus (
318 OUT UINT32 *ReturnMeFs2
319 );
320
321 /**
322 Returns the GroupId and Me Client Address for former MCA
323 messages
324
325 If no MhkiVersion HOB exists use HECI_MCHI_MESSAGE_ADDR
326 and MKHI_MCA_GROUP_ID as a default.
327
328 @param[in] Command Former MCA Command
329 @param[out] GroupId GroupId for the given command
330 @param[out] MeClientAddress Me Client for the given command
331 **/
332 VOID
333 GetMcaMsgParams (
334 IN UINT32 Command,
335 OUT UINT8 *GroupId,
336 OUT UINT8 *MeClientAddress
337 );
338
339 /**
340 Wait until Firmware Init Complete is set in Firmware Status Register 1 [BIT9].
341
342 @param[in] Timeout Time in microseconds
343
344 @retval EFI_SUCCESS Firmware Init Complete bit is set
345 @retval EFI_TIMEOUT Firmware Init Complete bit is not set within specified time
346 **/
347 EFI_STATUS
348 WaitFirmwareInitComplete (
349 IN UINT32 Timeout
350 );
351
352 /**
353 Generate User Nonce as an array of "NonceSize" bytes
354
355 @param[in] NonceSize Size of nonce array to be generated
356 @param[out] NonceArray User Nonce array
357
358 **/
359 VOID
360 GenerateUserNonce (
361 IN UINT32 NonceSize,
362 OUT UINT8 *NonceArray
363 );
364
365 #endif // _ME_UTILS_LIB_H_
GetSpsEndOfPostStatus
BOOLEAN GetSpsEndOfPostStatus(OUT UINT32 *ReturnMeFs2)
Get SPS End Of Post from Firmware Status.
GetInitComplete
BOOLEAN GetInitComplete(OUT UINT32 *ReturnMeFs1)
Get InitComplete from Firmware Status.
MeClientIsReady
BOOLEAN MeClientIsReady(VOID)
Checks if Me FW is Client and it is ready.
GetHeciPciBus
UINTN GetHeciPciBus(VOID)
Get HECI PCI Bus.
GenerateUserNonce
VOID GenerateUserNonce(IN UINT32 NonceSize, OUT UINT8 *NonceArray)
Generate User Nonce as an array of "NonceSize" bytes.
HeciSendWithAck
EFI_STATUS HeciSendWithAck(IN VOID *This, IN UINT32 HeciPchId, IN OUT UINT32 *Timeout, IN UINT8 Retries, IN UINT8 HostAddress, IN UINT8 EngineAddress, IN UINT32 *ReqMsg, IN UINT32 ReqLen, OUT UINT32 *RspMsg, IN OUT UINT32 *RspLen, IN OUT EFI_STATUS *SendStatus, IN OUT EFI_STATUS *ReceiveStatus)
Wrapper for Heci HeciSendAndReceive HECI_CONTROL function.
GetMeFwsts1FromHob
UINT32 GetMeFwsts1FromHob(IN UINT32 Mefs1)
Reads ME Firmware Status 1 information from HOB.
GetHeciPciDevice
UINTN GetHeciPciDevice(VOID)
Get HECI PCI Device Number.
GetMcaMsgParams
VOID GetMcaMsgParams(IN UINT32 Command, OUT UINT8 *GroupId, OUT UINT8 *MeClientAddress)
Returns the GroupId and Me Client Address for former MCA messages.
MeBiosGetMeMode
EFI_STATUS MeBiosGetMeMode(OUT UINT32 *MeMode)
Return ME Mode.
MeBiosGetMeStatusRaw
EFI_STATUS MeBiosGetMeStatusRaw(OUT UINT32 *MeStatus)
Get an Intel ME Firmware Status from HECI-1 HFS register.
MeClientInRecovery
BOOLEAN MeClientInRecovery(VOID)
Checks if Me FW is Client in manufacturing.
MeIsInRecovery
BOOLEAN MeIsInRecovery(VOID)
Checks if Me is in manufacturing.
MeSpsIsReady
BOOLEAN MeSpsIsReady(VOID)
Checks if Me FW is SPS ready.
HECI_API_VERSION
HECI_API_VERSION
HECI_API_VERSION defines what HECI API is returned by GetHeci ()
Definition: MeUtilsLib.h:234
GetHeciPciSegment
UINTN GetHeciPciSegment(VOID)
Get HECI PCI Segment.
MeClientIsCorporate
BOOLEAN MeClientIsCorporate(VOID)
Checks if Me FW is Client Corporate.
WaitFirmwareInitComplete
EFI_STATUS WaitFirmwareInitComplete(IN UINT32 Timeout)
Wait until Firmware Init Complete is set in Firmware Status Register 1 [BIT9].
MeBiosGetMeStatus
EFI_STATUS MeBiosGetMeStatus(OUT UINT32 *MeStatus)
Get an abstract Intel ME Firmware Status from HECI-1 HFS register.
MeSpsInRecovery
BOOLEAN MeSpsInRecovery(VOID)
Checks if Me FW is SPS in recovery.
MeSpsIsNm
BOOLEAN MeSpsIsNm(VOID)
Checks if Me FW is SPS NM.
ResetHeci1Interface
EFI_STATUS ResetHeci1Interface(VOID)
Function forces a reinit of the heci interface by following the reset heci interface via host algorit...
GetHeci
VOID * GetHeci(OUT HECI_API_VERSION *HeciVersion)
Gets Heci PPI/Protocol, returns pointer to HECI PPI/Protocol.
IsInSmm
BOOLEAN IsInSmm(IN OUT EFI_SMM_SYSTEM_TABLE2 **SmmSystemTable2)
Get Information is we are running in SMM or not.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MkhiMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros | Enumerations
MkhiMsgs.h File Reference

MKHI Messages. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | MKHI_MESSAGE_HEADER
MKHI host message header. More...
union | INVOCATION_CODE_BITS
MKHI_CBM_GROUP Definitions. More...
union | MEFWCAPS_SKU
Get Firmware Capability. More...
union | TPM_STATE
Set ACM TPM. More...
struct | HMRFPO_ENABLE
HMRFPO ENABLE. More...
struct | HMRFPO_LOCK
HMRFPO LOCK. More...
struct | HMRFPO_GET_STATUS
HMRFPO GET STATUS. More...
struct | READ_FILE
Read File, Ver3 API only. More...
struct | SET_FILE
Set File, Ver3 API only. More...
struct | COMMIT_FILES
Commit Files. More...
struct | CORE_BIOS_DONE
Core Bios Done - both GEN and MCA group definition. More...
struct | GET_RPMC_STATUS
Get RPMC Status. More...
struct | READ_FILE_EX
Read File Ex. More...
struct | SET_FILE_EX
Set File Ex. More...
struct | REQUEST_OWNERSHIP
Request Device Ownership. More...
struct | ARB_SVN_COMMIT
HW Anti-Rollback (ARB) Security Version Number Commit. More...
struct | ARB_SVN_GET_INFO
HW Anti-Rollback (ARB) Security Version Number Get Info. More...
struct | DNX_REQ_SET
DNX Request Set. More...
struct | DNX_REQ_CLEAR
DNX Request Clear. More...
struct | GET_FW_VER
Get FW Version. More...
struct | GEN_SEND_CPU_BRAND
Send CPU brand class fuse. More...
struct | SET_ME_RESET_HALT
Set Manufacturing ME Reset and Halt messages. More...
struct | FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA
FW Feature Shipment Time State Override. More...
struct | FIPS_VERSION
Get FIPS Mode. More...
struct | SET_MEASURED_BOOT
Set CSME Measured Boot. More...
struct | GET_MEASURED_BOOT
Get CSME Measured Boot. More...

Macros

#define | MKHI_CBM_GROUP_ID 0x00
Defines for GroupID.
#define | CBM_RESET_CMD 0x0B
Defines for Command. More...
#define | PWD_CHANGE_CMD 0x01
Defines for PWD_GROUP Command.
#define | FWCAPS_GET_RULE_CMD 0x02
Defines for FWCAPS_GROUP Command.
#define | HMRFPO_ENABLE_CMD_ID 0x01
Defines for HMRFPO_GROUP Command.
#define | MCA_READ_FILE_CMD 0x02
Defines for MCA_GROUP Command.
#define | DNX_REQ_SET_CMD 0x01
Defines for DNX_GROUP Command.
#define | GEN_GET_MKHI_VERSION_CMD 0x01
Defines for GEN_GROUP Command.
#define | MEPWDID_ME_BIOS_EXT 0
MEBx password Identifier.
#define | MEPWDMGMT_PWD_MAX_SIZE 32
Maximum Password Length.
#define | MEPWDMGMT_PWD_MIN_SIZE 8
Minimum Password Length.
#define | ME_DISABLE 0
Set ME Disable.
#define | HMRFPO_ENABLE_SUCCESS 0x00
HMRFPO_ENABLE returned Status.
#define | HMRFPO_LOCK_SUCCESS 0x00
HMRFPO_LOCK_RESPONSE returned Status.
#define | HMRFPO_DISABLED 0x00
HMRFPO_GET_STATUS returned Status.
#define | MCA_DAM_FILE_SIZE 1
MKHI_MCA_GROUP_ID Definitions.
#define | ARB_SVN_COMMIT_ALL 0xFF
Value 0xFF refers to committing all pending ARBSVN values.
#define | MKHI_MSG_VERSION_MAJOR 0x1
Get MKHI Version.
#define | MAX_SKU_BITMAP 8
CPU type change response feature masks size in DWORDS.
#define | USER_FEEDBACK_REQUESTED 1
User feedback is requested.
#define | CPU_TYPE_CHANGE_ACCEPTED 1
CPU type change accepted.
#define | EOP_DISABLED 0
End of Post.
#define | ME_UNCONFIG_TIMEOUT 200
Get ME Unconfiguration State. More...
#define | ME_UNCONFIG_IN_PROGRESS 0x01
Unconfig without password is in progress.
#define | ME_UNCONFIG_NOT_IN_PROGRESS 0x02
Normal case, there is no unconfigure w/o password to be processed.
#define | ME_UNCONFIG_FINISHED 0x03
CSME finished processing unconfigure w/o password. Bios will perform a global reset.
#define | ME_UNCONFIG_ERROR 0x80
CSME encountered error while processing revert back to default. Specific error status defined starting at 0x81.
#define | FTP_PARTITION_NAME_PMCP 0x50434D50
Get Image FW Version.
#define | FIPS_MODE_DISABLED 0
Set FIPS Mode.

Enumerations

enum | ME_PWD_STATUS
enum | LOCAL_FW_UPDATE
Get/Set Local FW Update.
enum | PLATFORM_TARGET_USAGE_TYPE
Get Platform Type. More...
enum | SKU_TYPE
[6]
enum | ME_IMAGE_TYPE
[11:8]
enum | PLATFORM_BRAND
[15:12]
enum | ME_UNCONFIG_ON_RTC_CLEAR_STATUS
Unconfig On Rtc Clear Status. More...
enum | MFT_KEY_USAGE
HW Anti-Rollback. More...

Detailed Description

MKHI Messages.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MkhiMsgs.h.

Macro Definition Documentation

◆ CBM_RESET_CMD

#define CBM_RESET_CMD 0x0B

Defines for Command.

Defines for CBM_GROUP Command

Definition at line 76 of file MkhiMsgs.h.

◆ ME_UNCONFIG_TIMEOUT

#define ME_UNCONFIG_TIMEOUT 200

Get ME Unconfiguration State.

Unconfig timeout in seconds

Definition at line 1037 of file MkhiMsgs.h.

Enumeration Type Documentation

◆ ME_PWD_STATUS

enum ME_PWD_STATUS
Enumerator
ME_PWDSTS_PWD_SUCCESS | Password change/verification was successful.
ME_PWDSTS_INVALID_PWD | Current password in use is invalid.
ME_PWDSTS_INVALID_NEW_PWD | New password provided does not meet the required syntax.
ME_PWDSTS_OUT_OF_RESOURCES | Not sufficient flash space.
ME_PWDSTS_OPERATION_NOT_ALLOWED | Password change/verification cannot be performed at this point in time.
ME_PWDSTS_FAILURE | Unknown failure has occured.

Definition at line 252 of file MkhiMsgs.h.

◆ ME_UNCONFIG_ON_RTC_CLEAR_STATUS

enum ME_UNCONFIG_ON_RTC_CLEAR_STATUS

Unconfig On Rtc Clear Status.

Enumerator
EnableState | [Unconfigure on RTC Clear] is enabled.
DisableState | [Unconfigure on RTC Clear] is disabled.

Definition at line 512 of file MkhiMsgs.h.

◆ MFT_KEY_USAGE

enum MFT_KEY_USAGE

HW Anti-Rollback.

Enumerator
MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST | RBE manifest.
MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST | Undefined and maximum usage.

Definition at line 778 of file MkhiMsgs.h.

◆ PLATFORM_TARGET_USAGE_TYPE

enum PLATFORM_TARGET_USAGE_TYPE

Get Platform Type.

[3:0]

Definition at line 447 of file MkhiMsgs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MkhiMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
MkhiMsgs.h
Go to the documentation of this file.
1 /** @file
2 MKHI Messages
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MKHI_MSGS_H
36 #define _MKHI_MSGS_H
37
38 #pragma pack(1)
39
40 ///
41 /// MKHI host message header. This header is part of HECI message sent from MEBx via
42 /// Host Configuration Interface (HCI). ME Configuration Manager or Power Configuration
43 /// Manager also include this header with appropriate fields set as part of the
44 /// response message to the HCI.
45 ///
46 typedef union {
47 UINT32 Data;
48 struct {
49 UINT32 GroupId : 8;
50 UINT32 Command : 7;
51 UINT32 IsResponse : 1;
52 UINT32 Reserved : 8;
53 UINT32 Result : 8;
54 } Fields;
55 } MKHI_MESSAGE_HEADER;
56
57
58 ///
59 /// Defines for GroupID
60 ///
61 #define MKHI_CBM_GROUP_ID 0x00
62 #define MKHI_PWD_GROUP_ID 0x02
63 #define MKHI_FWCAPS_GROUP_ID 0x03
64 #define MKHI_HMRFPO_GROUP_ID 0x05
65 #define MKHI_MCA_GROUP_ID 0x0A
66 #define MKHI_DNX_GROUP_ID 0x0D
67 #define MKHI_GEN_GROUP_ID 0xFF
68
69
70 ///
71 /// Defines for Command
72 ///
73 ///
74 /// Defines for CBM_GROUP Command
75 ///
76 #define CBM_RESET_CMD 0x0B
77 #define CBM_GET_INVOCATION_CODE 0x0D
78 #define CBM_SET_INVOCATION_CODE 0x0E
79 #define CBM_CLR_INVOCATION_CODE 0x0F
80 ///
81 /// Defines for PWD_GROUP Command
82 ///
83 #define PWD_CHANGE_CMD 0x01
84 #define PWD_VALIDATE_CMD 0x02
85 #define PWD_IS_MODIFIED_CMD 0x03
86 ///
87 /// Defines for FWCAPS_GROUP Command
88 ///
89 #define FWCAPS_GET_RULE_CMD 0x02
90 #define FWCAPS_SET_RULE_CMD 0x03
91 #define FWCAPS_GET_RULE_STATE_CMD 0x05
92 ///
93 /// Defines for HMRFPO_GROUP Command
94 ///
95 #define HMRFPO_ENABLE_CMD_ID 0x01
96 #define HMRFPO_LOCK_CMD_ID 0x02
97 #define HMRFPO_GET_STATUS_CMD_ID 0x03
98 ///
99 /// Defines for MCA_GROUP Command
100 ///
101 #define MCA_READ_FILE_CMD 0x02 // Ver3 API only
102 #define MCA_SET_FILE_CMD 0x03 // Ver3 API only
103 #define MCA_COMMIT_FILES_CMD 0x04
104 #define MCA_CORE_BIOS_DONE_CMD 0x05
105 #define MCA_GET_RPMC_STATUS_CMD 0x08
106 #define MCA_READ_FILE_EX_CMD 0x0A
107 #define MCA_SET_FILE_EX_CMD 0x0B
108 #define MCA_REQUEST_DEVICE_OWNERSHIP 0x0F
109 #define MCA_ARB_SVN_COMMIT_CMD 0x1B
110 #define MCA_ARB_SVN_GET_INFO_CMD 0x1C
111 ///
112 /// Defines for DNX_GROUP Command
113 ///
114 #define DNX_REQ_SET_CMD 0x01
115 #define DNX_REQ_CLEAR_CMD 0x02
116 ///
117 /// Defines for GEN_GROUP Command
118 ///
119 #define GEN_GET_MKHI_VERSION_CMD 0x01
120 #define GEN_GET_FW_VERSION_CMD 0x02
121 #define GEN_CORE_BIOS_DONE_CMD 0x05
122 #define GEN_SEND_CPU_BRAND_CLASS_FUSE_CMD 0x07
123 #define GEN_GET_CPU_TYPE_CHANGE_USER_MESSAGE_CMD 0x08
124 #define GEN_SET_CPU_TYPE_CHANGE_USER_RESPONSE_CMD 0x09
125 #define GEN_END_OF_POST_CMD 0x0C
126 #define GEN_UNCFG_WO_PWD_CMD 0x0D
127 #define GEN_GET_ME_UNCFG_STATE_CMD 0x0E
128 #define GEN_SET_ME_RESET_HALT_CMD 0x10
129 #define GEN_FW_FEATURE_STATE_OVERRIDE_CMD 0x14
130 #define GEN_GET_IMAGE_FW_VERSION 0x1C
131 #define GEN_SET_FIPS_MODE_CMD 0x20
132 #define GEN_GET_FIPS_MODE_CMD 0x21
133 #define GEN_SET_MEASURED_BOOT_STATE_CMD 0x22
134 #define GEN_GET_MEASURED_BOOT_STATE_CMD 0x23
135
136 //
137 // Typedef for Result field of MHKI Header
138 //
139 typedef enum {
140 MkhiStatusSuccess,
141 MkhiStatusInvalidState,
142 MkhiStatusMessageSkipped,
143 MkhiStatusSizeError = 0x5,
144 MkhiStatusInvalidAccess = 0x84,
145 MkhiStatusInvalidParams = 0x85,
146 MkhiStatusNotReady = 0x88,
147 MkhiStatusNotSupported = 0x89,
148 MkhiStatusInvalidAddress = 0x8C,
149 MkhiStatusInvalidCommand = 0x8D,
150 MkhiStatusFailure = 0x9E,
151 MkhiStatusInvalidResource = 0xE4,
152 MkhiStatusResourceInUse = 0xE5,
153 MkhiStatusNoResource = 0xE6,
154 MkhiStatusGeneralError = 0xFF
155 } MKHI_RESULT;
156
157 ///
158 /// MKHI_CBM_GROUP Definitions
159 ///
160 typedef union {
161 UINT32 Data;
162 struct {
163 UINT32 TableSyncError : 1; ///< BIT_0 No longer used
164 UINT32 CpuReplacement : 1; ///< BIT_1
165 UINT32 SyncMngState : 1; ///< BIT_2
166 UINT32 SolStateChange : 1; ///< BIT_3 No longer used
167 UINT32 IderStateChange : 1; ///< BIT_4 No longer used
168 UINT32 KvmStateChange : 1; ///< BIT_5 No longer used
169 UINT32 SyncRaAvailability : 1; ///< BIT_6
170 UINT32 FwUnconfiguration : 1; ///< BIT_7
171 UINT32 UserConsentFlow : 1; ///< BIT_8
172 UINT32 WlanPowerConfigChange : 1; ///< BIT_9
173 UINT32 FwUpdate : 1; ///< BIT_10 No longer used
174 UINT32 FirstMebxBoot : 1; ///< BIT_11
175 UINT32 DataSyncConfirmation : 1; ///< BIT_12
176 UINT32 ClsUserInfo : 1; ///< BIT_13 No longer used
177 UINT32 Reserved2 : 18; ///< BIT_14-31
178 } Fields;
179 } INVOCATION_CODE_BITS;
180
181 #define DATA_SYNC_CONFIRMATION BIT12
182
183 //
184 // Get Invocation Code
185 //
186 typedef struct {
187 MKHI_MESSAGE_HEADER MkhiHeader;
188 } GET_INVOCATION_CODE;
189
190 typedef struct {
191 MKHI_MESSAGE_HEADER MkhiHeader;
192 UINT32 InvocationCode;
193 } GET_INVOCATION_CODE_ACK;
194
195 typedef union {
196 GET_INVOCATION_CODE Request;
197 GET_INVOCATION_CODE_ACK Response;
198 } GET_INVOCATION_CODE_BUFFER;
199
200 //
201 // Set Invocation Code
202 //
203 typedef struct {
204 MKHI_MESSAGE_HEADER MkhiHeader;
205 UINT32 InvocationCode;
206 } SET_INVOCATION_CODE;
207
208 typedef struct {
209 MKHI_MESSAGE_HEADER MkhiHeader;
210 } SET_INVOCATION_CODE_ACK;
211
212 typedef union {
213 SET_INVOCATION_CODE Request;
214 SET_INVOCATION_CODE_ACK Response;
215 } SET_INVOCATION_CODE_BUFFER;
216
217 //
218 // Clear Invocation Code
219 //
220 typedef struct {
221 MKHI_MESSAGE_HEADER MkhiHeader;
222 UINT32 InvocationCode;
223 } CLEAR_INVOCATION_CODE;
224
225 typedef struct {
226 MKHI_MESSAGE_HEADER MkhiHeader;
227 } CLEAR_INVOCATION_CODE_ACK;
228
229 typedef union {
230 CLEAR_INVOCATION_CODE Request;
231 CLEAR_INVOCATION_CODE_ACK Response;
232 } CLEAR_INVOCATION_CODE_BUFFER;
233
234 //
235 // MKHI_PWD_GROUP_ID Definitions
236 //
237 //
238 // Password Information
239 // The following is the information required for authenticating and storing a password.
240 //
241 // Password Identifier
242 // Identifier to track passwords used by various entities interacting with ME Kernel
243 //
244 #define MEPWDID_ME_BIOS_EXT 0 ///< MEBx password Identifier
245
246 #define MEPWDMGMT_PWD_MAX_SIZE 32 ///< Maximum Password Length
247 #define MEPWDMGMT_PWD_MIN_SIZE 8 ///< Minimum Password Length
248
249 //
250 // Password Management Status Codes.
251 //
252 typedef enum {
253 ME_PWDSTS_PWD_SUCCESS = 0, ///< Password change/verification was successful.
254 ME_PWDSTS_INVALID_PWD, ///< Current password in use is invalid.
255 ME_PWDSTS_INVALID_NEW_PWD, ///< New password provided does not meet the required syntax.
256 ME_PWDSTS_OUT_OF_RESOURCES, ///< Not sufficient flash space.
257 ME_PWDSTS_OPERATION_NOT_ALLOWED, ///< Password change/verification cannot be performed at this point in time.
258 ME_PWDSTS_FAILURE ///< Unknown failure has occured
259 } ME_PWD_STATUS;
260
261 //
262 // Change Password
263 //
264 typedef struct {
265 MKHI_MESSAGE_HEADER MkhiHeader;
266 UINT32 PwdId;
267 UINT8 Reserved[2];
268 UINT8 OldPwdSize;
269 UINT8 OldPwd[MEPWDMGMT_PWD_MAX_SIZE];
270 UINT8 NewPwdSize;
271 UINT8 NewPwd[MEPWDMGMT_PWD_MAX_SIZE];
272 } PWD_CHANGE;
273
274 typedef struct {
275 MKHI_MESSAGE_HEADER MkhiHeader;
276 UINT32 PwdId;
277 } PWD_CHANGE_ACK;
278
279 typedef union {
280 PWD_CHANGE Request;
281 PWD_CHANGE_ACK Response;
282 } PWD_CHANGE_BUFFER;
283
284 //
285 // Validate Password
286 //
287 typedef struct {
288 MKHI_MESSAGE_HEADER MkhiHeader;
289 UINT32 PwdId;
290 UINT8 Reserved[3];
291 UINT8 PwdSize;
292 UINT8 Pwd[MEPWDMGMT_PWD_MAX_SIZE];
293 } PWD_VALIDATE;
294
295 typedef struct {
296 MKHI_MESSAGE_HEADER MkhiHeader;
297 UINT32 PwdId;
298 UINT32 MaxCountExpired;
299 } PWD_VALIDATE_ACK;
300
301 typedef union {
302 PWD_VALIDATE Request;
303 PWD_VALIDATE_ACK Response;
304 } PWD_VALIDATE_BUFFER;
305
306 //
307 // Is Password Modified
308 //
309 typedef struct {
310 MKHI_MESSAGE_HEADER MkhiHeader;
311 } PWD_IS_MODIFIED;
312
313 typedef struct {
314 MKHI_MESSAGE_HEADER MkhiHeader;
315 UINT32 IsModified;
316 } PWD_IS_MODIFIED_ACK;
317
318 typedef union {
319 PWD_IS_MODIFIED Request;
320 PWD_IS_MODIFIED_ACK Response;
321 } PWD_IS_MODIFIED_BUFFER;
322
323 //
324 // MKHI_FWCAPS_GROUP_ID Definitions
325 //
326
327 #define RULE_DATA_LENGTH 0x04
328
329 //Macro to build a rule identifier. For Me rules all other fields are zeros
330 #define FWCAPS_RULE_ID(FeatureId, RuleTypeId) ((FeatureId << 16) | RuleTypeId)
331
332 typedef enum {
333 KernelFeatureId = 0,
334 AmtFeatureId = 3
335 } FWCAPS_FEATURE_ID;
336
337 typedef enum {
338 FwCapsRuleTypeId = 0,
339 MePlatformStateRuleTypeId = 6,
340 MeFwUpdateRuleTypeId = 7,
341 UserCapsRuleTypeId = 9,
342 PlatTypeRuleTypeId = 29,
343 FeatureStateRuleTypeId = 32,
344 StateForAllFeaturesRuleTypeId = 33,
345 EnableClinkRuleTypeId = 38,
346 AvailableBitmapRuleTypeId = 39,
347 EnableMoffOverrideRuleTypeId = 41,
348 OemTagRuleTypeId = 43,
349 AcmTpmRuleTypeId = 47,
350 UnconfigOnRtcClarRuleTypeId = 48
351 } KERNEL_FEATURE_RULE_TYPE_ID;
352
353 typedef enum {
354 AmtBiosSyncInfoRuleTypeId = 5,
355 DisplayUserConsentRuleTypeId = 10
356 } AMT_FEATURE_RULE_TYPE_ID;
357
358 typedef union {
359 UINT32 Data;
360 struct {
361 UINT32 RuleTypeId : 16;
362 UINT32 FeatureId : 8;
363 UINT32 Reserved : 8;
364 } Fields;
365 } RULE_ID;
366
367 typedef struct {
368 MKHI_MESSAGE_HEADER MkhiHeader;
369 UINT32 RuleId;
370 } GET_RULE;
371
372 typedef struct {
373 MKHI_MESSAGE_HEADER MkhiHeader;
374 UINT32 RuleId;
375 UINT8 RuleDataLen;
376 UINT32 RuleData;
377 } GET_RULE_ACK;
378
379 typedef union {
380 GET_RULE Request;
381 GET_RULE_ACK Response;
382 } GET_RULE_BUFFER;
383
384 typedef struct {
385 MKHI_MESSAGE_HEADER MkhiHeader;
386 UINT32 RuleId;
387 UINT8 RuleDataLen;
388 UINT32 RuleData;
389 } SET_RULE;
390
391 typedef struct {
392 MKHI_MESSAGE_HEADER MkhiHeader;
393 UINT32 RuleId;
394 } SET_RULE_ACK;
395
396 typedef union {
397 SET_RULE Request;
398 SET_RULE_ACK Response;
399 } SET_RULE_BUFFER;
400
401 ///
402 /// Get Firmware Capability
403 ///
404 typedef union {
405 UINT32 Data;
406 struct {
407 UINT32 FullMng : 1; ///< [0] Full manageability
408 UINT32 StdMng : 1; ///< [1] Standard manageability
409 UINT32 Amt : 1; ///< [2] Any manageability
410 UINT32 Reserved : 1; ///< [3] Reserved
411 UINT32 IntegratedTouch : 1; ///< [4] Intel Integrated Touch [Deprecated]
412 UINT32 Reserved1 : 1; ///< [5] Reserved
413 UINT32 IntelCLS : 1; ///< [6] IntelR Capability Licensing Service (CLS)
414 UINT32 Reserved2 : 3; ///< [9:7] Reserved
415 UINT32 ISH : 1; ///< [10] IntelR Sensor Hub
416 UINT32 Reserved3 : 1; ///< [11] Reserved
417 UINT32 PAVP : 1; ///< [12] Protected Audio Video Path (PAVP)
418 UINT32 Reserved4 : 4; ///< [16:13] Reserved
419 UINT32 IPV6 : 1; ///< [17] IPV6
420 UINT32 KVM : 1; ///< [18] KVM Remote Control (KVM)
421 UINT32 Reserved5 : 1; ///< [19] Reserved
422 UINT32 DAL : 1; ///< [20] Dynamic Application Loader (DAL)
423 UINT32 TLS : 1; ///< [21] Cipher Transport Layer (TLS)
424 UINT32 Reserved6 : 1; ///< [22] Reserved
425 UINT32 WLAN : 1; ///< [23] Wireless LAN (WLAN)
426 UINT32 Reserved7 : 1; ///< [24] Reserved
427 UINT32 TrustedDevice : 1; ///< [25] Trusted Device
428 UINT32 Reserved8 : 3; ///< [28:26] Reserved
429 UINT32 PTT : 1; ///< [29] Platform Trust Technology (PTT)
430 UINT32 Reserved9 : 2; ///< [31:30] Reserved
431 } Fields;
432 } MEFWCAPS_SKU;
433
434 ///
435 /// Get/Set Local FW Update
436 ///
437 typedef enum {
438 UpdateDisabled,
439 UpdateEnabled
440 } LOCAL_FW_UPDATE;
441
442 ///
443 /// Get Platform Type
444 ///
445
446 /// [3:0]
447 typedef enum {
448 PlatformMobile = 1,
449 PlatformDesktop = 2,
450 PlatformServer = 4,
451 PlatformWorkstation = 8
452 } PLATFORM_TARGET_USAGE_TYPE;
453
454 /// [6]
455 typedef enum {
456 RegularSku,
457 SuperSku
458 } SKU_TYPE;
459
460 /// [11:8]
461 typedef enum {
462 IntelMeConsumerFw = 3,
463 IntelMeCorporateFw = 4,
464 IntelMeLiteFw = 5
465 } ME_IMAGE_TYPE;
466
467 /// [15:12]
468 typedef enum {
469 NoBrand,
470 IntelAmtBrand,
471 IntelStandardManageabilityBrand,
472 IntelReservedBrand1,
473 IntelReservedBrand2,
474 IntelReservedBrand3
475 } PLATFORM_BRAND;
476
477 typedef union {
478 UINT32 Data;
479 struct {
480 UINT32 PlatformTargetUsageType : 4;
481 UINT32 Reserved : 2;
482 UINT32 SuperSku : 1;
483 UINT32 Reserved1 : 1;
484 UINT32 IntelMeFwImageType : 4;
485 UINT32 PlatformBrand : 4;
486 UINT32 Reserved2 : 16;
487 } Fields;
488 } PLATFORM_TYPE_RULE_DATA;
489
490 ///
491 /// Set ME Disable
492 ///
493
494 #define ME_DISABLE 0
495
496 ///
497 /// Set ACM TPM
498 ///
499
500 typedef union {
501 UINT32 Data;
502 struct {
503 UINT32 Reserved : 8;
504 UINT32 TpmDeactivate : 1;
505 UINT32 Reserved1 : 23;
506 } Fields;
507 } TPM_STATE;
508
509 ///
510 /// Unconfig On Rtc Clear Status
511 ///
512 typedef enum {
513 EnableState = 0, ///< [Unconfigure on RTC Clear] is enabled.
514 DisableState = 1 ///< [Unconfigure on RTC Clear] is disabled.
515 } ME_UNCONFIG_ON_RTC_CLEAR_STATUS;
516
517 typedef enum {
518 AmtProvisioningStatePre = 0,
519 AmtProvisioningStateIn = 1,
520 AmtProvisioningStatePost = 2
521 } AMT_PROVISIONING_STATE;
522
523 typedef struct {
524 UINT32 Reserved : 1;
525 UINT32 CiraAvailable : 1; ///< CIRA Available
526 UINT32 ProvisioningAvailable : 1; ///< Corporate Provisioning Available
527 UINT32 ProvisioningState : 2; ///< Provisioning state. @see AMT_PROVISIONING_STATE
528 UINT32 Reserved1 : 27;
529 } AMT_BIOS_SYNC_INFO;
530
531 //
532 // MKHI_HMRFPO_GROUP_ID Definitions
533 //
534
535 ///
536 /// HMRFPO ENABLE
537 ///
538 typedef struct {
539 MKHI_MESSAGE_HEADER MkhiHeader;
540 UINT32 Reserved[2];
541 } HMRFPO_ENABLE;
542
543 ///
544 /// HMRFPO_ENABLE returned Status
545 ///
546 #define HMRFPO_ENABLE_SUCCESS 0x00
547 #define HMRFPO_ENABLE_LOCKED 0x01
548 #define HMRFPO_NVAR_FAILURE 0x02
549 #define HMRFPO_ENABLE_UNKNOWN_FAILURE 0x05
550
551 typedef struct {
552 MKHI_MESSAGE_HEADER MkhiHeader;
553 UINT32 Reserved[2];
554 UINT8 Status;
555 UINT8 Reserved1[3];
556 } HMRFPO_ENABLE_ACK;
557
558 typedef union {
559 HMRFPO_ENABLE Request;
560 HMRFPO_ENABLE_ACK Response;
561 } HMRFPO_ENABLE_BUFFER;
562
563 ///
564 /// HMRFPO LOCK
565 ///
566 typedef struct {
567 MKHI_MESSAGE_HEADER MkhiHeader;
568 } HMRFPO_LOCK;
569
570 ///
571 /// HMRFPO_LOCK_RESPONSE returned Status
572 ///
573 #define HMRFPO_LOCK_SUCCESS 0x00
574 #define HMRFPO_LOCK_FAILURE 0x01
575
576 typedef struct {
577 MKHI_MESSAGE_HEADER MkhiHeader;
578 UINT32 Reserved[4];
579 UINT8 Status;
580 UINT8 Reserved1[3];
581 } HMRFPO_LOCK_ACK;
582
583 typedef union {
584 HMRFPO_LOCK Request;
585 HMRFPO_LOCK_ACK Response;
586 } HMRFPO_LOCK_BUFFER;
587
588 ///
589 /// HMRFPO GET STATUS
590 ///
591 typedef struct {
592 MKHI_MESSAGE_HEADER MkhiHeader;
593 } HMRFPO_GET_STATUS;
594
595 ///
596 /// HMRFPO_GET_STATUS returned Status
597 ///
598 #define HMRFPO_DISABLED 0x00
599 #define HMRFPO_LOCKED 0x01
600 #define HMRFPO_ENABLED 0x02
601
602 typedef struct {
603 MKHI_MESSAGE_HEADER MkhiHeader;
604 UINT8 Status;
605 UINT8 Reserved[3];
606 } HMRFPO_GET_STATUS_ACK;
607
608 typedef union {
609 HMRFPO_GET_STATUS Request;
610 HMRFPO_GET_STATUS_ACK Response;
611 } HMRFPO_GET_STATUS_BUFFER;
612
613 ///
614 /// MKHI_MCA_GROUP_ID Definitions
615 ///
616 #define MCA_DAM_FILE_SIZE 1
617 #define MCA_PLAT_ID_SUPPORT_FILE_SIZE 1
618 #define MCA_MAX_FILE_SIZE 4096
619
620 #define MCA_DAM_FILE_ID 0x10050000
621 #define MCA_AMT_PROV_STATE_FILE_ID 0x10080200
622 #define MCA_AMT_PROV_ADT_REC_FILE_ID 0x1001A600
623 #define MCA_AMT_SEC_PKI_FILE_ID 0x1001A000
624 #define MCA_PLAT_ID_SUPPORT_FILE_ID 0x1001B900
625 #define MCA_AMT_BIOS_REDIR_FILE_ID 0x10080300
626 #define MCAPHY_OEM_CFG_ID 0x1001F200
627
628 ///
629 /// Read File, Ver3 API only
630 ///
631 typedef struct {
632 MKHI_MESSAGE_HEADER MkhiHeader;
633 UINT8 FilePath[64];
634 UINT32 Offset;
635 UINT32 DataSize;
636 UINT8 Flags;
637 } READ_FILE;
638
639 typedef struct {
640 MKHI_MESSAGE_HEADER MkhiHeader;
641 UINT32 DataSize;
642 UINT8 Data[]; ///< Data Buffer
643 } READ_FILE_ACK;
644
645 typedef union {
646 READ_FILE Request;
647 READ_FILE_ACK Response;
648 } READ_FILE_BUFFER;
649
650 ///
651 /// Set File, Ver3 API only
652 ///
653 typedef struct {
654 MKHI_MESSAGE_HEADER MkhiHeader;
655 UINT8 FilePath[64];
656 UINT32 Offset;
657 UINT32 DataSize;
658 UINT8 Flags;
659 UINT8 Data[]; ///< Data Buffer
660 } SET_FILE;
661
662 typedef struct {
663 MKHI_MESSAGE_HEADER MkhiHeader;
664 } SET_FILE_ACK;
665
666 typedef union {
667 SET_FILE Request;
668 SET_FILE_ACK Response;
669 } SET_FILE_BUFFER;
670
671 ///
672 /// Commit Files
673 ///
674 typedef struct {
675 MKHI_MESSAGE_HEADER MkhiHeader;
676 } COMMIT_FILES;
677
678 ///
679 /// Core Bios Done - both GEN and MCA group definition
680 ///
681 typedef struct {
682 MKHI_MESSAGE_HEADER MkhiHeader;
683 } CORE_BIOS_DONE;
684
685 typedef struct {
686 MKHI_MESSAGE_HEADER MkhiHeader;
687 } CORE_BIOS_DONE_ACK;
688
689 ///
690 /// Get RPMC Status
691 ///
692 typedef struct {
693 MKHI_MESSAGE_HEADER MkhiHeader;
694 } GET_RPMC_STATUS;
695
696 typedef struct {
697 UINT32 DeviceType : 2; ///< Device Type. 00: EMMC; 01: UFS; 10: SPI; 11: No device
698 UINT32 RpSupport : 1; ///< Relay Protection. 0: Not supported; 1: Support NVM and FW configuraion
699 UINT32 BindStatus : 1; ///< 0: Pre-bind; 1: Post-bind
700 UINT32 RpRebindingAllowed : 1; ///< Rebind. 0: Not allowed 1: Allowed
701 UINT32 BindingCounter : 5; ///< Current binding counter
702 UINT32 MaxRebinds : 4; ///< Number of max rebinds allowed
703 UINT32 SpiRpmcCounters : 3; ///< Number of RPMC counters avaiable (0 if EMMC/UFS)
704 UINT32 SpiRpmcChipselect : 1; ///< 0 if EMMC/UFS
705 UINT32 SpiRpmcFatalError : 8; ///< 0 if EMMC/UFS
706 UINT32 Reserved : 6;
707 } RP_STATUS_2;
708
709 typedef struct {
710 MKHI_MESSAGE_HEADER MkhiHeader;
711 RP_STATUS_2 Status;
712 } GET_RPMC_STATUS_ACK;
713
714 typedef union {
715 GET_RPMC_STATUS Request;
716 GET_RPMC_STATUS_ACK Response;
717 } GET_RPMC_STATUS_BUFFER;
718
719 ///
720 /// Read File Ex
721 ///
722 typedef struct {
723 MKHI_MESSAGE_HEADER MkhiHeader;
724 UINT32 FileId;
725 UINT32 Offset;
726 UINT32 DataSize;
727 UINT8 Flags;
728 } READ_FILE_EX;
729
730 typedef struct {
731 MKHI_MESSAGE_HEADER MkhiHeader;
732 UINT32 DataSize;
733 UINT8 Data[]; ///< Data Buffer
734 } READ_FILE_EX_ACK;
735
736 typedef union {
737 READ_FILE_EX Request;
738 READ_FILE_EX_ACK Response;
739 } READ_FILE_EX_BUFFER;
740
741 ///
742 /// Set File Ex
743 ///
744 typedef struct {
745 MKHI_MESSAGE_HEADER MkhiHeader;
746 UINT32 FileId;
747 UINT32 Offset;
748 UINT32 DataSize;
749 UINT8 Flags;
750 UINT8 Data[]; ///< Data Buffer
751 } SET_FILE_EX;
752
753 typedef struct {
754 MKHI_MESSAGE_HEADER MkhiHeader;
755 } SET_FILE_EX_ACK;
756
757 typedef union {
758 SET_FILE_EX Request;
759 SET_FILE_EX_ACK Response;
760 } SET_FILE_EX_BUFFER;
761
762 ///
763 /// Request Device Ownership
764 ///
765 typedef struct {
766 MKHI_MESSAGE_HEADER MkhiHeader;
767 } REQUEST_OWNERSHIP;
768
769 typedef union {
770 REQUEST_OWNERSHIP Request;
771 REQUEST_OWNERSHIP Response;
772 } REQUEST_OWNERSHIP_BUFFER;
773
774 ///
775 /// HW Anti-Rollback
776 ///
777
778 typedef enum {
779 MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST = 3, ///< RBE manifest
780 MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST = 255 ///< Undefined and maximum usage
781 } MFT_KEY_USAGE;
782
783 #define ARB_SVN_COMMIT_ALL 0xFF ///< Value 0xFF refers to committing all pending ARBSVN values.
784 ///
785 /// HW Anti-Rollback (ARB) Security Version Number Commit
786 ///
787 typedef struct {
788 MKHI_MESSAGE_HEADER MkhiHeader;
789 UINT8 UsageId;
790 UINT8 Reserved[3]; ///< Reserved for future use, to allow specifying explicit usage to be committed.
791 } ARB_SVN_COMMIT;
792
793 typedef struct {
794 MKHI_MESSAGE_HEADER MkhiHeader;
795 } ARB_SVN_COMMIT_ACK;
796
797 typedef union {
798 ARB_SVN_COMMIT Request;
799 ARB_SVN_COMMIT_ACK Response;
800 } ARB_SVN_COMMIT_BUFFER;
801
802 ///
803 /// HW Anti-Rollback (ARB) Security Version Number Get Info
804 ///
805 typedef struct {
806 MKHI_MESSAGE_HEADER MkhiHeader;
807 } ARB_SVN_GET_INFO;
808
809 typedef struct {
810 UINT8 UsageId; ///< Key usage number according to FAS manifest.
811 /* Used in SPS to indicate partition.
812 In client the SVN is same for all partitions
813 0 - Boot partition 1 (RCV in SPS)
814 1 - Boot partition 2 (OPR1 in SPS)
815 2 - Boot partition 3 (OPR2 in SPS)
816 */
817 UINT8 BootPartitionId;
818 UINT8 ExecutingSvn; ///< The SVN value of the FW currently running.
819 UINT8 MinAllowedSvn; ///< The minimal SVN allowed on platform for given usage.
820 } ARB_SVN_INFO_ENTRY;
821
822 typedef struct {
823 MKHI_MESSAGE_HEADER MkhiHeader;
824 UINT32 NumEntries; ///< Number of ARB SVN Entry
825 ARB_SVN_INFO_ENTRY ArbSvnEntry[0];
826 } ARB_SVN_GET_INFO_ACK;
827
828 typedef union {
829 ARB_SVN_GET_INFO Request;
830 ARB_SVN_GET_INFO_ACK Response;
831 } ARB_SVN_GET_INFO_BUFFER;
832
833 //
834 // MKHI_DNX_GROUP_ID Definitions
835 //
836
837 ///
838 /// DNX Request Set
839 ///
840 typedef struct {
841 MKHI_MESSAGE_HEADER MkhiHeader;
842 } DNX_REQ_SET;
843
844 typedef struct {
845 MKHI_MESSAGE_HEADER MkhiHeader;
846 UINT32 BiosAction;
847 } DNX_REQ_SET_ACK;
848
849 typedef union {
850 DNX_REQ_SET Request;
851 DNX_REQ_SET_ACK Response;
852 } DNX_REQ_SET_BUFFER;
853
854 ///
855 /// DNX Request Clear
856 ///
857 typedef struct {
858 MKHI_MESSAGE_HEADER MkhiHeader;
859 UINT32 Flag;
860 } DNX_REQ_CLEAR;
861
862 typedef struct {
863 MKHI_MESSAGE_HEADER MkhiHeader;
864 } DNX_REQ_CLEAR_ACK;
865
866 typedef union {
867 DNX_REQ_CLEAR Request;
868 DNX_REQ_CLEAR_ACK Response;
869 } DNX_REQ_CLEAR_BUFFER;
870
871 //
872 // MKHI_GEN_GROUP_ID Definitions
873 //
874
875 ///
876 /// Get MKHI Version
877 ///
878 #define MKHI_MSG_VERSION_MAJOR 0x1
879 #define MKHI_MSG_VERSION_MINOR 0x1
880
881 typedef union {
882 UINT32 Data;
883 struct {
884 UINT32 Minor : 16;
885 UINT32 Major : 16;
886 } Fields;
887 } MKHI_VERSION;
888
889 typedef struct {
890 MKHI_MESSAGE_HEADER MkhiHeader;
891 } GET_MKHI_VERSION;
892
893 typedef struct {
894 MKHI_MESSAGE_HEADER MkhiHeader;
895 MKHI_VERSION MkhiVersion;
896 } GET_MKHI_VERSION_ACK;
897
898 typedef union {
899 GET_MKHI_VERSION Request;
900 GET_MKHI_VERSION_ACK Response;
901 } GET_MKHI_VERSION_BUFFER;
902
903 ///
904 /// Get FW Version
905 ///
906 typedef struct {
907 MKHI_MESSAGE_HEADER MkhiHeader;
908 } GET_FW_VER;
909
910 typedef struct {
911 UINT32 CodeMinor : 16;
912 UINT32 CodeMajor : 16;
913 UINT32 CodeBuildNo : 16;
914 UINT32 CodeHotFix : 16;
915 UINT32 RcvyMinor : 16;
916 UINT32 RcvyMajor : 16;
917 UINT32 RcvyBuildNo : 16;
918 UINT32 RcvyHotFix : 16;
919 UINT32 FitcMinor : 16;
920 UINT32 FitcMajor : 16;
921 UINT32 FitcBuildNo : 16;
922 UINT32 FitcHotFix : 16;
923 } GET_FW_VER_ACK_DATA;
924
925 typedef struct {
926 MKHI_MESSAGE_HEADER MkhiHeader;
927 GET_FW_VER_ACK_DATA Data;
928 } GET_FW_VER_ACK;
929
930 ///
931 /// Send CPU brand class fuse
932 ///
933
934 typedef struct {
935 MKHI_MESSAGE_HEADER MkhiHeader;
936 UINT8 CpuBrandClass;
937 } GEN_SEND_CPU_BRAND;
938
939 typedef struct {
940 MKHI_MESSAGE_HEADER MkhiHeader;
941 } GEN_SEND_CPU_BRAND_ACK;
942
943 typedef union {
944 GEN_SEND_CPU_BRAND Request;
945 GEN_SEND_CPU_BRAND_ACK Response;
946 } GEN_SEND_CPU_BRAND_BUFFER;
947
948 //
949 // Get CPU Type Change message
950 //
951 #define MAX_SKU_BITMAP 8 ///< CPU type change response feature masks size in DWORDS
952 #define USER_FEEDBACK_REQUESTED 1 ///< User feedback is requested
953
954 typedef struct {
955 UINT8 UserFeedback;
956 UINT32 FeaturesDisabled[MAX_SKU_BITMAP];
957 UINT32 FeaturesEnabled[MAX_SKU_BITMAP];
958 UINT8 GlobalResetRequired;
959 } GEN_GET_CPU_TYPE_CHANGE_DATA;
960
961 typedef struct {
962 MKHI_MESSAGE_HEADER MkhiHeader;
963 } GEN_GET_CPU_TYPE_CHANGE;
964
965 typedef struct {
966 MKHI_MESSAGE_HEADER MkhiHeader;
967 GEN_GET_CPU_TYPE_CHANGE_DATA Data;
968 } GEN_GET_CPU_TYPE_CHANGE_ACK;
969
970 typedef union {
971 GEN_GET_CPU_TYPE_CHANGE Request;
972 GEN_GET_CPU_TYPE_CHANGE_ACK Response;
973 } GEN_GET_CPU_TYPE_CHANGE_BUFFER;
974
975 //
976 // Set CPU Type Change message
977 //
978 #define CPU_TYPE_CHANGE_ACCEPTED 1 ///< CPU type change accepted
979
980 typedef struct {
981 MKHI_MESSAGE_HEADER MkhiHeader;
982 UINT8 UserResponse;
983 } GEN_SET_CPU_TYPE_CHANGE;
984
985 typedef struct {
986 MKHI_MESSAGE_HEADER MkhiHeader;
987 } GEN_SET_CPU_TYPE_CHANGE_ACK;
988
989 typedef union {
990 GEN_SET_CPU_TYPE_CHANGE Request;
991 GEN_SET_CPU_TYPE_CHANGE_ACK Response;
992 } GEN_SET_CPU_TYPE_CHANGE_BUFFER;
993
994
995 ///
996 /// End of Post
997 ///
998 #define EOP_DISABLED 0
999 #define EOP_SEND_IN_PEI 1
1000 #define EOP_SEND_IN_DXE 2
1001
1002 #define MAX_EOP_SEND_RETRIES 3
1003
1004 typedef struct {
1005 MKHI_MESSAGE_HEADER MkhiHeader;
1006 } END_OF_POST;
1007
1008 typedef enum {
1009 HeciEopStatusSuccess,
1010 HeciEopPerformGlobalReset
1011 } EOP_REQUESTED_ACTIONS;
1012
1013 typedef struct {
1014 UINT32 RequestedActions;
1015 } EOP_ACK_DATA;
1016
1017 typedef struct {
1018 MKHI_MESSAGE_HEADER MkhiHeader;
1019 EOP_ACK_DATA Data;
1020 } END_OF_POST_ACK;
1021
1022 typedef union {
1023 END_OF_POST Request;
1024 END_OF_POST_ACK Response;
1025 } END_OF_POST_BUFFER;
1026
1027 //
1028 // Unconfig without password messages
1029 //
1030 typedef struct {
1031 MKHI_MESSAGE_HEADER MkhiHeader;
1032 } UNCONFIG_WO_PASSWORD;
1033
1034 ///
1035 /// Get ME Unconfiguration State
1036 ///
1037 #define ME_UNCONFIG_TIMEOUT 200 ///< Unconfig timeout in seconds
1038
1039 #define ME_UNCONFIG_IN_PROGRESS 0x01 ///< Unconfig without password is in progress
1040 #define ME_UNCONFIG_NOT_IN_PROGRESS 0x02 ///< Normal case, there is no unconfigure w/o password to be processed
1041 #define ME_UNCONFIG_FINISHED 0x03 ///< CSME finished processing unconfigure w/o password. Bios will perform a global reset
1042 #define ME_UNCONFIG_ERROR 0x80 ///< CSME encountered error while processing revert back to default. Specific error status defined starting at 0x81
1043
1044 typedef struct {
1045 MKHI_MESSAGE_HEADER MkhiHeader;
1046 } GEN_GET_ME_UNCFG_STATE;
1047
1048 ///
1049 /// Set Manufacturing ME Reset and Halt messages
1050 ///
1051 typedef struct {
1052 MKHI_MESSAGE_HEADER MkhiHeader;
1053 } SET_ME_RESET_HALT;
1054
1055 typedef struct {
1056 MKHI_MESSAGE_HEADER MkhiHeader;
1057 } SET_ME_RESET_HALT_ACK;
1058
1059 ///
1060 /// FW Feature Shipment Time State Override
1061 ///
1062 typedef struct {
1063 UINT32 EnableFeature;
1064 UINT32 DisableFeature;
1065 } FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA;
1066
1067 typedef struct {
1068 MKHI_MESSAGE_HEADER MkhiHeader;
1069 FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA FeatureState;
1070 } FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE;
1071
1072 //
1073 // FW Feature Shipment Time State Override returned Status
1074 //
1075 typedef enum {
1076 SetFeatureStateAccepted,
1077 SetFeatureStateRejected
1078 } FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_RESPONSE;
1079
1080 typedef struct {
1081 MKHI_MESSAGE_HEADER MkhiHeader;
1082 UINT32 Status;
1083 } FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_ACK;
1084
1085 typedef union {
1086 FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE Request;
1087 FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_ACK Response;
1088 } FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_BUFFER;
1089
1090 ///
1091 /// Get Image FW Version
1092 ///
1093 #define FTP_PARTITION_NAME_PMCP 0x50434D50
1094
1095 typedef struct {
1096 MKHI_MESSAGE_HEADER MkhiHeader;
1097 UINT32 PartitionId;
1098 } GET_IMAGE_FW_VER;
1099
1100 typedef struct {
1101 UINT16 Major;
1102 UINT16 Minor;
1103 UINT16 Hotfix;
1104 UINT16 Build;
1105 } FW_VERSION;
1106
1107 typedef struct {
1108 UINT32 PartitionId; ///< Partition ID
1109 UINT8 Reserved[8]; ///< Should be 0
1110 FW_VERSION Version; ///< Module version
1111 UINT32 VendorId; ///< Module vendor ID(0x8086 for Intel)
1112 UINT32 TcbSvn; ///< TCB SVN
1113 UINT32 Reserved1[15]; ///< Reserved bytes for future extension. Should be 0 while reserved
1114 } FLASH_PARTITION_DATA;
1115
1116 typedef struct {
1117 MKHI_MESSAGE_HEADER MkhiHeader;
1118 UINT32 NumOfModules;
1119 FLASH_PARTITION_DATA ManifestData;
1120 } GET_IMAGE_FW_VER_ACK;
1121
1122 typedef union {
1123 GET_IMAGE_FW_VER Request;
1124 GET_IMAGE_FW_VER_ACK Response;
1125 } GET_IMAGE_FW_VERSION_BUFFER;
1126
1127 ///
1128 /// Set FIPS Mode
1129 ///
1130 #define FIPS_MODE_DISABLED 0
1131 #define FIPS_MODE_ENABLED 1
1132
1133 typedef struct {
1134 UINT32 FipsMode;
1135 } SET_FIPS_MODE_DATA;
1136
1137 typedef struct {
1138 MKHI_MESSAGE_HEADER MkhiHeader;
1139 SET_FIPS_MODE_DATA Data;
1140 } SET_FIPS_MODE;
1141
1142 typedef struct {
1143 MKHI_MESSAGE_HEADER MkhiHeader;
1144 } SET_FIPS_MODE_ACK;
1145
1146 typedef union {
1147 SET_FIPS_MODE Request;
1148 SET_FIPS_MODE_ACK Response;
1149 } SET_FIPS_MODE_BUFFER;
1150
1151 ///
1152 /// Get FIPS Mode
1153 ///
1154 typedef struct {
1155 UINT16 Major;
1156 UINT16 Minor;
1157 UINT16 Hotfix;
1158 UINT16 Build;
1159 } FIPS_VERSION;
1160
1161 typedef struct {
1162 UINT32 FipsMode;
1163 FIPS_VERSION CryptoVersion;
1164 UINT8 Reserved[8];
1165 } GET_FIPS_MODE_DATA;
1166
1167 typedef struct {
1168 MKHI_MESSAGE_HEADER MkhiHeader;
1169 } GET_FIPS_MODE;
1170
1171 typedef struct {
1172 MKHI_MESSAGE_HEADER MkhiHeader;
1173 GET_FIPS_MODE_DATA Data;
1174 } GET_FIPS_MODE_ACK;
1175
1176 typedef union {
1177 GET_FIPS_MODE Request;
1178 GET_FIPS_MODE_ACK Response;
1179 } GET_FIPS_MODE_BUFFER;
1180
1181 ///
1182 /// Set CSME Measured Boot
1183 ///
1184 typedef struct {
1185 MKHI_MESSAGE_HEADER MkhiHeader;
1186 UINT8 Data;
1187 } SET_MEASURED_BOOT;
1188
1189 typedef struct {
1190 MKHI_MESSAGE_HEADER MkhiHeader;
1191 } SET_MEASURED_BOOT_ACK;
1192
1193 typedef union {
1194 SET_MEASURED_BOOT Request;
1195 SET_MEASURED_BOOT_ACK Response;
1196 } SET_MEASURED_BOOT_BUFFER;
1197
1198 ///
1199 /// Get CSME Measured Boot
1200 ///
1201 typedef struct {
1202 MKHI_MESSAGE_HEADER MkhiHeader;
1203 } GET_MEASURED_BOOT;
1204
1205 typedef struct {
1206 MKHI_MESSAGE_HEADER MkhiHeader;
1207 UINT8 Data;
1208 } GET_MEASURED_BOOT_ACK;
1209
1210 typedef union {
1211 GET_MEASURED_BOOT Request;
1212 GET_MEASURED_BOOT_ACK Response;
1213 } GET_MEASURED_BOOT_BUFFER;
1214
1215 #pragma pack()
1216
1217 #endif // _MKHI_MSGS_H
MAX_SKU_BITMAP
#define MAX_SKU_BITMAP
CPU type change response feature masks size in DWORDS.
Definition: MkhiMsgs.h:951
MEFWCAPS_SKU::KVM
UINT32 KVM
[18] KVM Remote Control (KVM)
Definition: MkhiMsgs.h:420
MEFWCAPS_SKU::PAVP
UINT32 PAVP
[12] Protected Audio Video Path (PAVP)
Definition: MkhiMsgs.h:417
READ_FILE
Read File, Ver3 API only.
Definition: MkhiMsgs.h:631
MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST
@ MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST
RBE manifest.
Definition: MkhiMsgs.h:779
MEFWCAPS_SKU::Reserved8
UINT32 Reserved8
[28:26] Reserved
Definition: MkhiMsgs.h:428
ME_PWDSTS_INVALID_NEW_PWD
@ ME_PWDSTS_INVALID_NEW_PWD
New password provided does not meet the required syntax.
Definition: MkhiMsgs.h:255
MEFWCAPS_SKU::Reserved7
UINT32 Reserved7
[24] Reserved
Definition: MkhiMsgs.h:426
DNX_REQ_CLEAR
DNX Request Clear.
Definition: MkhiMsgs.h:857
HMRFPO_ENABLE
HMRFPO ENABLE.
Definition: MkhiMsgs.h:538
INVOCATION_CODE_BITS::FirstMebxBoot
UINT32 FirstMebxBoot
BIT_11.
Definition: MkhiMsgs.h:174
ARB_SVN_GET_INFO
HW Anti-Rollback (ARB) Security Version Number Get Info.
Definition: MkhiMsgs.h:805
LOCAL_FW_UPDATE
LOCAL_FW_UPDATE
Get/Set Local FW Update.
Definition: MkhiMsgs.h:437
TPM_STATE
Set ACM TPM.
Definition: MkhiMsgs.h:500
HMRFPO_LOCK
HMRFPO LOCK.
Definition: MkhiMsgs.h:566
INVOCATION_CODE_BITS::SolStateChange
UINT32 SolStateChange
BIT_3 No longer used.
Definition: MkhiMsgs.h:166
MEFWCAPS_SKU::TrustedDevice
UINT32 TrustedDevice
[25] Trusted Device
Definition: MkhiMsgs.h:427
GET_FW_VER
Get FW Version.
Definition: MkhiMsgs.h:906
MEFWCAPS_SKU::Reserved2
UINT32 Reserved2
[9:7] Reserved
Definition: MkhiMsgs.h:414
MEFWCAPS_SKU::IPV6
UINT32 IPV6
[17] IPV6
Definition: MkhiMsgs.h:419
MEFWCAPS_SKU::IntegratedTouch
UINT32 IntegratedTouch
[4] Intel Integrated Touch [Deprecated]
Definition: MkhiMsgs.h:411
MEFWCAPS_SKU::Reserved3
UINT32 Reserved3
[11] Reserved
Definition: MkhiMsgs.h:416
SET_ME_RESET_HALT
Set Manufacturing ME Reset and Halt messages.
Definition: MkhiMsgs.h:1051
INVOCATION_CODE_BITS::TableSyncError
UINT32 TableSyncError
BIT_0 No longer used.
Definition: MkhiMsgs.h:163
MEPWDMGMT_PWD_MAX_SIZE
#define MEPWDMGMT_PWD_MAX_SIZE
Maximum Password Length.
Definition: MkhiMsgs.h:246
INVOCATION_CODE_BITS::ClsUserInfo
UINT32 ClsUserInfo
BIT_13 No longer used.
Definition: MkhiMsgs.h:176
MEFWCAPS_SKU::Reserved1
UINT32 Reserved1
[5] Reserved
Definition: MkhiMsgs.h:412
FIPS_VERSION
Get FIPS Mode.
Definition: MkhiMsgs.h:1154
PLATFORM_TARGET_USAGE_TYPE
PLATFORM_TARGET_USAGE_TYPE
Get Platform Type.
Definition: MkhiMsgs.h:447
MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST
@ MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST
Undefined and maximum usage.
Definition: MkhiMsgs.h:780
SET_MEASURED_BOOT
Set CSME Measured Boot.
Definition: MkhiMsgs.h:1184
MEFWCAPS_SKU::DAL
UINT32 DAL
[20] Dynamic Application Loader (DAL)
Definition: MkhiMsgs.h:422
MEFWCAPS_SKU::Reserved5
UINT32 Reserved5
[19] Reserved
Definition: MkhiMsgs.h:421
INVOCATION_CODE_BITS::WlanPowerConfigChange
UINT32 WlanPowerConfigChange
BIT_9.
Definition: MkhiMsgs.h:172
INVOCATION_CODE_BITS::SyncRaAvailability
UINT32 SyncRaAvailability
BIT_6.
Definition: MkhiMsgs.h:169
MEFWCAPS_SKU::Reserved4
UINT32 Reserved4
[16:13] Reserved
Definition: MkhiMsgs.h:418
ME_IMAGE_TYPE
ME_IMAGE_TYPE
[11:8]
Definition: MkhiMsgs.h:461
EnableState
@ EnableState
[Unconfigure on RTC Clear] is enabled.
Definition: MkhiMsgs.h:513
MEFWCAPS_SKU::IntelCLS
UINT32 IntelCLS
[6] IntelR Capability Licensing Service (CLS)
Definition: MkhiMsgs.h:413
GET_MEASURED_BOOT
Get CSME Measured Boot.
Definition: MkhiMsgs.h:1201
HMRFPO_GET_STATUS
HMRFPO GET STATUS.
Definition: MkhiMsgs.h:591
GEN_SEND_CPU_BRAND
Send CPU brand class fuse.
Definition: MkhiMsgs.h:934
MEFWCAPS_SKU::Reserved6
UINT32 Reserved6
[22] Reserved
Definition: MkhiMsgs.h:424
MEFWCAPS_SKU::Reserved
UINT32 Reserved
[3] Reserved
Definition: MkhiMsgs.h:410
GET_RPMC_STATUS
Get RPMC Status.
Definition: MkhiMsgs.h:692
INVOCATION_CODE_BITS::CpuReplacement
UINT32 CpuReplacement
BIT_1.
Definition: MkhiMsgs.h:164
FW_FEATURE_SHIPMENT_TIME_STATE_OVERRIDE_DATA
FW Feature Shipment Time State Override.
Definition: MkhiMsgs.h:1062
INVOCATION_CODE_BITS::FwUpdate
UINT32 FwUpdate
BIT_10 No longer used.
Definition: MkhiMsgs.h:173
INVOCATION_CODE_BITS::SyncMngState
UINT32 SyncMngState
BIT_2.
Definition: MkhiMsgs.h:165
INVOCATION_CODE_BITS::IderStateChange
UINT32 IderStateChange
BIT_4 No longer used.
Definition: MkhiMsgs.h:167
MKHI_MESSAGE_HEADER
MKHI host message header.
Definition: MkhiMsgs.h:46
ME_PWDSTS_INVALID_PWD
@ ME_PWDSTS_INVALID_PWD
Current password in use is invalid.
Definition: MkhiMsgs.h:254
DisableState
@ DisableState
[Unconfigure on RTC Clear] is disabled.
Definition: MkhiMsgs.h:514
MEFWCAPS_SKU::StdMng
UINT32 StdMng
[1] Standard manageability
Definition: MkhiMsgs.h:408
SET_FILE_EX
Set File Ex.
Definition: MkhiMsgs.h:744
INVOCATION_CODE_BITS
MKHI_CBM_GROUP Definitions.
Definition: MkhiMsgs.h:160
ME_PWDSTS_PWD_SUCCESS
@ ME_PWDSTS_PWD_SUCCESS
Password change/verification was successful.
Definition: MkhiMsgs.h:253
MEFWCAPS_SKU::WLAN
UINT32 WLAN
[23] Wireless LAN (WLAN)
Definition: MkhiMsgs.h:425
MEFWCAPS_SKU::ISH
UINT32 ISH
[10] IntelR Sensor Hub
Definition: MkhiMsgs.h:415
COMMIT_FILES
Commit Files.
Definition: MkhiMsgs.h:674
SKU_TYPE
SKU_TYPE
[6]
Definition: MkhiMsgs.h:455
MEFWCAPS_SKU::PTT
UINT32 PTT
[29] Platform Trust Technology (PTT)
Definition: MkhiMsgs.h:429
ME_UNCONFIG_ON_RTC_CLEAR_STATUS
ME_UNCONFIG_ON_RTC_CLEAR_STATUS
Unconfig On Rtc Clear Status.
Definition: MkhiMsgs.h:512
ME_PWDSTS_OUT_OF_RESOURCES
@ ME_PWDSTS_OUT_OF_RESOURCES
Not sufficient flash space.
Definition: MkhiMsgs.h:256
MFT_KEY_USAGE
MFT_KEY_USAGE
HW Anti-Rollback.
Definition: MkhiMsgs.h:778
INVOCATION_CODE_BITS::UserConsentFlow
UINT32 UserConsentFlow
BIT_8.
Definition: MkhiMsgs.h:171
READ_FILE_EX
Read File Ex.
Definition: MkhiMsgs.h:722
DNX_REQ_SET
DNX Request Set.
Definition: MkhiMsgs.h:840
MEFWCAPS_SKU::Amt
UINT32 Amt
[2] Any manageability
Definition: MkhiMsgs.h:409
MEFWCAPS_SKU::FullMng
UINT32 FullMng
[0] Full manageability
Definition: MkhiMsgs.h:407
MEFWCAPS_SKU
Get Firmware Capability.
Definition: MkhiMsgs.h:404
MEFWCAPS_SKU::Reserved9
UINT32 Reserved9
[31:30] Reserved
Definition: MkhiMsgs.h:430
ME_PWD_STATUS
ME_PWD_STATUS
Definition: MkhiMsgs.h:252
INVOCATION_CODE_BITS::KvmStateChange
UINT32 KvmStateChange
BIT_5 No longer used.
Definition: MkhiMsgs.h:168
INVOCATION_CODE_BITS::FwUnconfiguration
UINT32 FwUnconfiguration
BIT_7.
Definition: MkhiMsgs.h:170
INVOCATION_CODE_BITS::Reserved2
UINT32 Reserved2
BIT_14-31.
Definition: MkhiMsgs.h:177
ME_PWDSTS_FAILURE
@ ME_PWDSTS_FAILURE
Unknown failure has occured.
Definition: MkhiMsgs.h:258
REQUEST_OWNERSHIP
Request Device Ownership.
Definition: MkhiMsgs.h:765
PLATFORM_BRAND
PLATFORM_BRAND
[15:12]
Definition: MkhiMsgs.h:468
MEFWCAPS_SKU::TLS
UINT32 TLS
[21] Cipher Transport Layer (TLS)
Definition: MkhiMsgs.h:423
ARB_SVN_COMMIT
HW Anti-Rollback (ARB) Security Version Number Commit.
Definition: MkhiMsgs.h:787
CORE_BIOS_DONE
Core Bios Done - both GEN and MCA group definition.
Definition: MkhiMsgs.h:681
SET_FILE
Set File, Ver3 API only.
Definition: MkhiMsgs.h:653
ME_PWDSTS_OPERATION_NOT_ALLOWED
@ ME_PWDSTS_OPERATION_NOT_ALLOWED
Password change/verification cannot be performed at this point in time.
Definition: MkhiMsgs.h:257
INVOCATION_CODE_BITS::DataSyncConfirmation
UINT32 DataSyncConfirmation
BIT_12.
Definition: MkhiMsgs.h:175
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MmPciLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
MmPciLib.h File Reference

Get Pci Express address library implementation. More...

Go to the source code of this file.

Functions

UINTN MmPciBase (IN UINT32 Bus, IN UINT32 Device, IN UINT32 Function)
This procedure will get PCIE address. More...

Detailed Description

Get Pci Express address library implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file MmPciLib.h.

Function Documentation

◆ MmPciBase()

UINTN MmPciBase | ( | IN UINT32 | Bus,
 |  | IN UINT32 | Device,
 |  | IN UINT32 | Function
 | ) |  |

This procedure will get PCIE address.

Parameters
[in] | Bus | Pci Bus Number
[in] | Device | Pci Device Number
[in] | Function | Pci Function Number
Return values
PCIE address
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): MmPciLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
MmPciLib.h
Go to the documentation of this file.
1 /** @file
2 Get Pci Express address library implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _MM_PCI_LIB_H_
36 #define _MM_PCI_LIB_H_
37
38 /**
39 This procedure will get PCIE address
40
41 @param[in] Bus Pci Bus Number
42 @param[in] Device Pci Device Number
43 @param[in] Function Pci Function Number
44
45 @retval PCIE address
46 **/
47 UINTN
48 EFIAPI
49 MmPciBase (
50 IN UINT32 Bus,
51 IN UINT32 Device,
52 IN UINT32 Function
53 );
54
55 #endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
MmPciBase
UINTN MmPciBase(IN UINT32 Bus, IN UINT32 Device, IN UINT32 Function)
This procedure will get PCIE address.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OcWdtLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
OcWdtLib.h File Reference

Header file for OC WDT Library. More...

Go to the source code of this file.

Functions

VOID | OcWdtResetCheck (VOID)
Check for unexpected reset. More...
EFI_STATUS | OcWdtInit (VOID)
This function install WDT PPI. More...

Detailed Description

Header file for OC WDT Library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file OcWdtLib.h.

Function Documentation

◆ OcWdtInit()

EFI_STATUS OcWdtInit ( VOID )

This function install WDT PPI.

Return values
EFI_STATUS Results of the installation of the WDT PPI

◆ OcWdtResetCheck()

VOID OcWdtResetCheck ( VOID )

Check for unexpected reset.

If there was an unexpected reset, enforces WDT expiration. Stops watchdog.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OcWdtLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
OcWdtLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for OC WDT Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _OC_WDT_LIB_H_
36 #define _OC_WDT_LIB_H_
37
38 /**
39 Check for unexpected reset.
40 If there was an unexpected reset, enforces WDT expiration.
41 Stops watchdog.
42 **/
43 VOID
44 OcWdtResetCheck(
45 VOID
46 );
47
48 /**
49 This function install WDT PPI
50
51 @retval EFI_STATUS Results of the installation of the WDT PPI
52 **/
53 EFI_STATUS
54 EFIAPI
55 OcWdtInit (
56 VOID
57 );
58
59 #endif
OcWdtResetCheck
VOID OcWdtResetCheck(VOID)
Check for unexpected reset.
OcWdtInit
EFI_STATUS OcWdtInit(VOID)
This function install WDT PPI.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OneClickRecoveryProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Macros | Typedefs
OneClickRecoveryProtocol.h File Reference

APIs for Intel One Click Recovery Main Protocol. More...

#include <AsfMsgs.h>
Include dependency graph for OneClickRecoveryProtocol.h:

Go to the source code of this file.

Macros

#define ONE_CLICK_RECOVERY_PROTOCOL_REVISION 1
Intel One Click Recovery Setup Protocol revision number. More...

Typedefs

typedef EFI_STATUS(* | ONE_CLICK_RECOVERY_ENTRY) (VOID)
The Intel One Click Recovery Setup main function. More...
typedef ONE_CLICK_RECOVERY_CAP(* | ONE_CLICK_RECOVERY_CAPABILITIES) (VOID)
Gives Intel One click Recovery BIOS Capabilities supported. More...
typedef EFI_STATUS(* | ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION) (IN ASF_BOOT_OPTIONS AsfBootOptions)
Saves OCR Uefi Boot Option from AMT. More...

Detailed Description

APIs for Intel One Click Recovery Main Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file OneClickRecoveryProtocol.h.

Macro Definition Documentation

◆ ONE_CLICK_RECOVERY_PROTOCOL_REVISION

#define ONE_CLICK_RECOVERY_PROTOCOL_REVISION 1

Intel One Click Recovery Setup Protocol revision number.

Revision 1: Initial version

Definition at line 118 of file OneClickRecoveryProtocol.h.

Typedef Documentation

◆ ONE_CLICK_RECOVERY_CAPABILITIES

typedef ONE_CLICK_RECOVERY_CAP( * ONE_CLICK_RECOVERY_CAPABILITIES) (VOID)

Gives Intel One click Recovery BIOS Capabilities supported.

Return values
ONE_CLICK_RECOVERY_CAPS One Click Recovery BIOS Capabilites

Definition at line 84 of file OneClickRecoveryProtocol.h.

◆ ONE_CLICK_RECOVERY_ENTRY

typedef EFI_STATUS( * ONE_CLICK_RECOVERY_ENTRY) (VOID)

The Intel One Click Recovery Setup main function.

The function does the necessary work to Setup the One Click Recovery feature.

Return values
EFI_SUCCESS | One Click Recovery tasks have been ran
EFI_UNSUPPORTED | One Click Recovery is not supported

Definition at line 73 of file OneClickRecoveryProtocol.h.

◆ ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION

typedef EFI_STATUS( * ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION) (IN ASF_BOOT_OPTIONS AsfBootOptions)

Saves OCR Uefi Boot Option from AMT.

Needs to Be called before Clear Boot Options.

Return values
EFI_SUCCESS Saved Boot Option

Definition at line 97 of file OneClickRecoveryProtocol.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OneClickRecoveryProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
OneClickRecoveryProtocol.h
Go to the documentation of this file.
1 /** @file
2 APIs for Intel One Click Recovery Main Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _ONE_CLICK_RECOVERY_PROTOCOL_H_
35 #define _ONE_CLICK_RECOVERY_PROTOCOL_H_
36
37 #include <AsfMsgs.h>
38
39 //
40 // Intel One Click Recovery Capabilites
41 //
42 typedef union {
43 struct{
44 UINT8 OcrBootHttps : 1; ///< [0] BIOS supports Intel One Click Recovery Https with AMT specified device path
45 UINT8 OcrBootPba : 1; ///< [1] BIOS supports Intel One Click Recovery PBA Boot with AMT specified device path
46 UINT8 OcrBootWinRe : 1; ///< [2] BIOS supports Intel One Click Recovery WinRe Boot
47 UINT8 OcrAmtDisSecBoot : 1; ///< [3] BIOS suporrts Intel One Click Recovery disable Secure Boot for AMT provided UEFI Load option
48 UINT8 OcrWifiProfile : 1; ///< [4] BIOS suporrts Intel One Click Recovery WiFi Profile sync
49 UINT8 Reserved2 : 3; ///< [7:5] Reserved
50 } Bits;
51 UINT8 Data;
52 } ONE_CLICK_RECOVERY_CAP;
53
54 //
55 // Extern the GUID for protocol users.
56 //
57 extern EFI_GUID gOneClickRecoveryProtocolGuid;
58
59 //
60 // Forward reference for ANSI C compatibility
61 //
62 typedef struct _ONE_CLICK_RECOVERY_PROTOCOL ONE_CLICK_RECOVERY_PROTOCOL;
63
64 /**
65 The Intel One Click Recovery Setup main function.
66
67 The function does the necessary work to Setup the One Click Recovery feature.
68
69 @retval EFI_SUCCESS One Click Recovery tasks have been ran
70 @retval EFI_UNSUPPORTED One Click Recovery is not supported
71 **/
72 typedef
73 EFI_STATUS
74 (EFIAPI *ONE_CLICK_RECOVERY_ENTRY) (
75 VOID
76 );
77
78 /**
79 Gives Intel One click Recovery BIOS Capabilities supported
80
81 @retval ONE_CLICK_RECOVERY_CAPS One Click Recovery BIOS Capabilites
82 **/
83 typedef
84 ONE_CLICK_RECOVERY_CAP
85 (EFIAPI *ONE_CLICK_RECOVERY_CAPABILITIES) (
86 VOID
87 );
88
89 /**
90 Saves OCR Uefi Boot Option from AMT.
91
92 Needs to Be called before Clear Boot Options.
93
94 @retval EFI_SUCCESS Saved Boot Option
95 **/
96 typedef
97 EFI_STATUS
98 (EFIAPI *ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION) (
99 IN ASF_BOOT_OPTIONS AsfBootOptions
100 );
101
102 struct _ONE_CLICK_RECOVERY_PROTOCOL {
103 /**
104 This member specifies the revision of this structure. This field is used to
105 indicate backwards compatible changes to the protocol.
106 **/
107 UINT32 Revision;
108 ONE_CLICK_RECOVERY_ENTRY OcrEntry;
109 ONE_CLICK_RECOVERY_CAPABILITIES OcrCap;
110 ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION OcrSaveUefiBootOption;
111 };
112
113 /**
114 Intel One Click Recovery Setup Protocol revision number
115
116 Revision 1: Initial version
117 **/
118 #define ONE_CLICK_RECOVERY_PROTOCOL_REVISION 1
119
120 #endif
ONE_CLICK_RECOVERY_CAPABILITIES
ONE_CLICK_RECOVERY_CAP(* ONE_CLICK_RECOVERY_CAPABILITIES)(VOID)
Gives Intel One click Recovery BIOS Capabilities supported.
Definition: OneClickRecoveryProtocol.h:85
AsfMsgs.h
AMT/ASF Messages.
ASF_BOOT_OPTIONS
Return Boot Options Elements' description is based on Get Boot Options and No Boot Options Message.
Definition: AsfMsgs.h:136
ONE_CLICK_RECOVERY_ENTRY
EFI_STATUS(* ONE_CLICK_RECOVERY_ENTRY)(VOID)
The Intel One Click Recovery Setup main function.
Definition: OneClickRecoveryProtocol.h:74
ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION
EFI_STATUS(* ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION)(IN ASF_BOOT_OPTIONS AsfBootOptions)
Saves OCR Uefi Boot Option from AMT.
Definition: OneClickRecoveryProtocol.h:98
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OverclockingConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
Classes
OverclockingConfig.h File Reference

Overclocking Config Block. More...

#include <CpuLimits.h>
Include dependency graph for OverclockingConfig.h:

Go to the source code of this file.

Classes

struct OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure. More...

Detailed Description

Overclocking Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file OverclockingConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): OverclockingConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
OverclockingConfig.h
Go to the documentation of this file.
1 /** @file
2 Overclocking Config Block.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _OVERCLOCKING_PREMEM_CONFIG_H_
36 #define _OVERCLOCKING_PREMEM_CONFIG_H_
37
38 #include <CpuLimits.h>
39
40 #define OVERCLOCKING_PREMEM_CONFIG_REVISION 37
41
42 extern EFI_GUID gOverclockingPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 //
47 // Max number of VF point offset
48 //
49 #ifndef CPU_OC_MAX_VF_POINTS
50 #define CPU_OC_MAX_VF_POINTS 0xF
51 #endif
52
53 /**
54 Overclocking Configuration Structure.
55
56 <b>Revision 1</b>:
57 - Initial version.
58 <b>Revision 2</b>
59 - Add PerCoreHtDisable
60 <b>Revision 3</b>
61 - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor
62 <b>Revision 4</b>
63 - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & CoreVfPointCount
64 <b>Revision 5</b>
65 - Change OcLock default to 'Enabled'
66 <b>Revision 6</b>
67 - Add CoreVfScope & PerCoreVoltageOffset
68 <b>Revision 7</b>
69 - Add AtomMaxOcRatio
70 <b>Revision 8</b>
71 - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overclocking.
72 <b>Revision 9</b>
73 Add UnlimitedIccMax
74 <b>Revision 10</b>
75 Add Atom Voltage configurations
76 <b>Revision 11</b>
77 Add SA Voltage adaptive and override configurations
78 <b>Revision 12</b>
79 Add RingVfPointOffsetMode & RingVfPointOffset & RingVfPointRatio & RingVfPointCount
80 <b>Revision 13</b>
81 Add CpuBclkOcFrequency
82 <b>Revision 14</b>:
83 - Add DisablePerCoreMask & DisablePerAtomMask.
84 <b>Revision 15</b>
85 Add CoreRatioExtensionMode
86 <b>Revision 16</b>
87 Add PvdRatioThreshold
88 <b>Revision 17</b>
89 Add IaCepEnable & GtCepEnable & SaCepEnable & IaSirpEnable
90 <b>Revision 18</b>
91 Add Per Atom Cluster VF support
92 Corrected the policy name of AtomMaxOcRatio to be AtomL2MaxOcRatio
93 <b>Revision 19</b>
94 Modify PllVoltageOffset of each Domain Range in 0 - 15 instead of 0 - 63
95 <b>Revision 20</b>
96 Add ItdThrottleEnable
97 <b>Revision 21</b>
98 Add AtomClusterRatio & Correct max big core number to be 8
99 <b>Revision 22</b>
100 Add SocBclkOcFrequency
101 <b>Revision 23</b>
102 Add AtomPllVoltageOffset
103 <b>Revision 24</b>
104 Deprecated FivrFaults, FivrEfficiency.
105 <b>Revision 25</b>
106 Add DlvrBypassModeEnable.
107 <b>Revision 26</b>
108 Add PvdMode and FllOverclockMode
109 <b>Revision 27</b>
110 Deprecated AtomL2MaxOcRatio
111 <b>Revision 28</b>
112 Deprecated Avx512VoltageScaleFactor and Avx3RatioOffset
113 <b>Revision 29</b>
114 Add SaPllFreqOverride
115 <b>Revision 30</b>
116 Add PllMaxBandingRatio
117 <b>Revision 31</b>
118 Add TscDisableHwFixup
119 <b>Revision 32</b>
120 Add IaIccUnlimitedMode & IaIccMax & GtIccUnlimitedMode & GtIccMax and deprecated UnlimitedIccMax
121 <b>Revision 33</b>
122 Add TvbDownBinsTempThreshold0, TvbDownBinsTempThreshold1, TvbTempThreshold0, TvbTempThreshold1
123 <b>Revision 34</b>
124 Deprecated PllMaxBandingRatio
125 <b>Revision 35</b>
126 Add FllOcModeEn
127 <b>Revision 36</b>
128 Deprecated DisablePerAtomMask (DisablePerCoreMask is used for both the cores)
129 <b>Revision 37</b>
130 Add Etvb
131 **/
132 typedef struct {
133 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
134 /**
135 Overclocking support. This controls whether OC mailbox transactions are sent.
136 If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
137 <b>0: Disable</b>;
138 1: Enable.
139 @note If PcdOverclockEnable is disabled, this should also be disabled.
140 **/
141 UINT32 OcSupport : 1;
142 UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; 0: Disable; <b>1: Enable (Lock)</b>.
143 /**
144 Core voltage mode, specifies which voltage mode the processor will be operating.
145 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
146 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
147 **/
148 UINT32 CoreVoltageMode : 1;
149 UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
150 UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
151 UINT32 Avx3RatioOffset : 5; ///< deprecated from version 28
152 UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
153 /**
154 Ring Downbin enable/disable.
155 When enabled, the CPU will force the ring ratio to be lower than the core ratio.
156 Disabling will allow the ring and core ratios to run at the same frequency.
157 Uses OC Mailbox command 0x19.
158 0: Disables Ring Downbin feature. <b>1: Enables Ring downbin feature.</b>
159 **/
160 UINT32 RingDownBin : 1;
161 /**
162 Ring voltage mode, specifies which voltage mode the processor will be operating.
163 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
164 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
165 **/
166 UINT32 RingVoltageMode : 1;
167 UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage is operating in Adaptive or Override mode: <b>0=Adaptive</b>, 1=Override
168 UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE. <b>0=Disable</b>, 1=Enable
169 UINT32 FivrFaults : 1; /// Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, <b>1: Enabled.</b>
170 UINT32 FivrEfficiency : 1; /// Deprecated < Fivr Efficiency Management. 0: Disabled, <b>1: Enabled.</b>
171 /**
172 Selects Core Voltage & Frequency Offset between Legacy and Selection modes.
173 Need Reset System after enabling OverClocking Feature to Initialize the default value.
174 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
175 1: In Selection Mode, setting a selected VF point.
176 **/
177 UINT32 CoreVfPointOffsetMode : 1;
178 /**
179 Core VF Configuration Scope.
180 Alows both all-core VF curve or per-core VF curve configuration.
181 <b>0: All-core Scope, setting the VF curve for all cores.</b>
182 1: Per-core Scope, setting the VF curve per-core.
183 **/
184 UINT32 CoreVfConfigScope : 1;
185 UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio to each Core. <b>0: Disable</b>, 1: enable
186 UINT32 UnlimitedIccMax : 1; ///< deprecated from version 32
187 /**
188 SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
189 <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
190 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
191 **/
192 UINT32 SaVoltageMode : 1;
193 UINT32 CoreRatioExtensionMode : 1; ///< Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MULTIPLIER_UNLOCK_EN. <b>0: Disable</b>, 1: enable
194
195 /**
196 Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
197 <b>0. no override/HW defaults.</b>. Range non-turbo max - 120 (Previously max turbo is 83).
198 **/
199 UINT8 CoreMaxOcRatio;
200 UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, <b>0=AUTO</b>
201 /**
202 Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio limit.
203 <b>0. no override/HW defaults.</b>. Range non-turbo max - 85.
204 **/
205 UINT8 RingMaxOcRatio;
206 /**
207 Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
208 <b>0. no override/HW defaults.</b>. non-turbo max - 120.
209 **/
210 UINT8 AtomL2MaxOcRatio; ///<deprecated from version 27
211 /**
212 The core voltage override which is applied to the entire range of cpu core frequencies.
213 Used when CoreVoltageMode = Override.
214 <b>0. no override</b>. Range 0-2000 mV.
215 **/
216 UINT16 CoreVoltageOverride;
217 /**
218 Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
219 Used when CoreVoltageMode = Adaptive.
220 <b>0. no override</b>. Range 0-2000mV.
221 **/
222 UINT16 CoreVoltageAdaptive;
223 /**
224 The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
225 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
226 **/
227 INT16 CoreVoltageOffset;
228 /**
229 The ring voltage override which is applied to the entire range of cpu ring frequencies.
230 Used when RingVoltageMode = Override.
231 <b>0. no override</b>. Range 0-2000 mV.
232 **/
233 UINT16 RingVoltageOverride;
234 /**
235 Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operating in turbo mode range.
236 Used when RingVoltageMode = Adaptive.
237 <b>0. no override</b>. Range 0-2000mV.
238 **/
239 UINT16 RingVoltageAdaptive;
240 /**
241 The ring voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
242 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
243 **/
244 INT16 RingVoltageOffset;
245
246 INT16 GtVoltageOffset; ///< The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: <b>0=Minimal</b>, 1000=Maximum
247 UINT16 GtVoltageOverride; ///< The GT voltage override which is applied to the entire range of GT frequencies <b>0=Default</b>
248 UINT16 GtExtraTurboVoltage; ///< The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: <b>0=Minimal</b>, 2000=Maximum
249 INT16 SaVoltageOffset; ///< The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: <b>0=Default</b>
250 UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
251 UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
252 UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
253 UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
254 UINT32 IaCepEnable : 1; ///< Enable IA Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
255 UINT32 GtCepEnable : 1; ///< Enable GT Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
256 UINT32 SaCepEnable : 1; ///< Enable SA Current Excursion Protection. <b>1: Enable</b>. 0: Disable.
257 UINT32 IaSirpEnable : 1; ///< Enable IA SoC Iccmax Reactive Protector. <b>1: Enable</b>. 0: Disable.
258 UINT32 ItdThrottleEnable : 1; ///< Enable Inverse Temperature Dependency Throttle Support. <b>1: Enable</b>. 0: Disable.
259 UINT32 DlvrBypassModeEnable : 1; ///< Enable CPU DLVR bypass mode support, <b>0: Disable</b>. 0: Enable.
260 UINT32 SaPllFreqOverride : 1; ///< Sa PLL Frequecy Override. <b>0: 3200MHz</b>. 1: 1600MHz.
261 UINT32 TscDisableHwFixup : 1; ///< Core HW Fixup disable during TSC copy from PMA to APIC, <b>0: Enable</b>. 1: Disable.
262
263 /**
264 TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support TjMax in the range of 62 to 115 deg Celsius.
265 <b> Default: 0 Hardware Defaults </b> Range 10 to 63. 0 = No offset / Keep HW default.
266 **/
267 UINT8 TjMaxOffset;
268 UINT8 RsvdByte2[3]; ///< Reserved for dword alignment
269 /**
270 This service controls Core frequency reduction caused by high package temperatures for processors that
271 implement the Intel Thermal Velocity Boost (TVB) feature. It is required to be disabled for supporting
272 overclocking at frequencies higher than the default max turbo frequency.
273 <b>0: Disables TVB ratio clipping. </b>1: Enables TVB ratio clipping.
274 **/
275 UINT32 TvbRatioClipping : 1;
276 /**
277 This service controls thermal based voltage optimizations for processors that implement the Intel
278 Thermal Velocity Boost (TVB) feature.
279 0: Disables TVB voltage optimization. <b>1: Enables TVB voltage optimization.</b>
280 **/
281 UINT32 TvbVoltageOptimization : 1;
282 UINT32 IaIccUnlimitedMode : 1; ///< Support IA Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
283 UINT32 GtIccUnlimitedMode : 1; ///< Support GT Unlimited ICCMAX up to maximum value 512A., <b>0: Disable</b>. 1: Enable.
284 UINT32 FllOcModeEn : 1; ///< Enable FLL Mode override with the value in FllOcMode. <b>0: Disable</b>. 1: Enable.
285 UINT32 Etvb : 1; ///< Enhanced Thermal Turbo Mode (eTVB). <b>0:eTVB is disabled on supporting products</b> 1:eTVB is enabled on supporting products.
286 UINT32 RsvdBits2 : 26;
287 /**
288 Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
289 Input is in HEX and each bit maps to a logical core. Ex. A value of '1F' would disable HT for cores 4,3,2,1 and 0.
290 <b>Default is 0</b>, all cores have HT enabled. Range is 0 - 0x1FF. You can only disable up to MAX_CORE_COUNT - 1.
291 **/
292 UINT16 PerCoreHtDisable;
293 /**
294 Avx2 Voltage Guardband Scale Factor
295 This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 workloads.
296 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
297 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
298 A value of 100 applies the default voltage guardband values (1.0 factor).
299 A value > 100 will increase the voltage guardband on AVX2 workloads.
300 A value < 100 will decrease the voltage guardband on AVX2 workloads.
301
302 <b>0. No scale factor applied</b>
303 **/
304 UINT8 Avx2VoltageScaleFactor;
305 /**
306 Avx512 Voltage Guardband Scale Factor
307 This controls the AVX512 Voltage Guardband Scale factor applied to AVX512 workloads.
308 Valid range is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
309 A value of 0 means no scale factor applied (no change to voltage on AVX commands)
310 A value of 100 applies the default voltage guardband values (1.0 factor).
311 A value > 100 will increase the voltage guardband on AVX512 workloads.
312 A value < 100 will decrease the voltage guardband on AVX512 workloads.
313
314 <b>0. No scale factor applied</b>
315 **/
316 UINT8 Avx512VoltageScaleFactor; ///<deprecated from version 28
317 /**
318 Array used to specifies the Core Voltage Offset applied to the each selected VF Point.
319 This voltage is specified in millivolts.
320 **/
321 INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];
322 UINT8 RsvdByte3[2]; ///< Reserved for dword alignment
323 /**
324 Array for the each selected VF Point to display the Core Ration.
325 **/
326 UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS];
327 /**
328 Number of supported Core Voltage & Frequency Point.
329 **/
330 UINT8 CoreVfPointCount;
331 /**
332 Array used to specifies the selected Core Offset Voltage.
333 This voltage is specified in millivolts.
334 **/
335 INT16 PerCoreVoltageOffset[CPU_MAX_BIG_CORES];
336 INT16 PerCoreVoltageOffset1[CPU_MAX_BIG_CORES];
337 UINT8 PerCoreRatio[CPU_MAX_BIG_CORES];
338 /**
339 The Atom cluster max ratio overrides.
340 <b>Default: 0</b> Range: 0 to 120.
341 **/
342 UINT8 AtomClusterRatio[CPU_MAX_ATOM_CLUSTERS];
343 /**
344 Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.
345 <b>0: Adaptive Mode</b> allows the atom processor to interpolate a voltage curve when beyond fused P0 range;
346 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
347 **/
348 UINT8 AtomL2VoltageMode;
349 UINT8 RsvdByte4; ///< Reserved for dword alignment
350 /**
351 The atom L2 voltage override which is applied to the entire range of atom core frequencies.
352 Used when AtomL2VoltageMode = Override.
353 <b>0. no override</b>. Range 0-2000 mV.
354 **/
355 UINT16 AtomL2VoltageOverride;
356 /**
357 Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operating in turbo mode range.
358 Used when AtomL2VoltageMode = Adaptive.
359 <b>0. no override</b>. Range 0-2000mV.
360 **/
361 UINT16 AtomL2VoltageAdaptive;
362 /**
363 The atom L2 voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
364 This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
365 **/
366 INT16 AtomL2VoltageOffset;
367 /**
368 The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
369 Used when SaVoltageMode = Override.
370 <b>0. no override</b>. Range 0-2000 mV.
371 **/
372 UINT16 SaVoltageOverride;
373 /**
374 Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is operating in turbo mode range.
375 Used when SaVoltageMode = Adaptive.
376 <b>0. no override</b>. Range 0-2000mV.
377 **/
378 UINT16 SaExtraTurboVoltage;
379 /**
380 Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
381 Need Reset System after enabling OverClocking Feature to Initialize the default value.
382 <b>0: In Legacy Mode, setting a global offset for the entire VF curve.</b>
383 1: In Selection modes, setting a selected VF point.
384 **/
385 UINT8 RingVfPointOffsetMode;
386 /**
387 Number of supported Ring Voltage & Frequency Point.
388 **/
389 UINT8 RingVfPointCount;
390 UINT8 RsvdByte5[2]; ///< Reserved for dword alignment
391 /**
392 Array used to specifies the Ring Voltage Offset applied to the each selected VF Point.
393 This voltage is specified in millivolts.
394 **/
395 INT16 RingVfPointOffset[CPU_OC_MAX_VF_POINTS];
396 UINT8 RsvdByte6[2]; ///< Reserved for dword alignment
397 /**
398 Array for the each selected VF Point to display the Ring Ration.
399 **/
400 UINT8 RingVfPointRatio[CPU_OC_MAX_VF_POINTS];
401 UINT8 AtomPllVoltageOffset; ///< Atom PLL voltage offset. <b>0: No offset</b>. Range 0-15 in 17.5mv units.
402 UINT32 CpuBclkOcFrequency; ///< CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 8000-50000 (10KHz)
403 /**
404 Core disable mask is a bitwise indication of which core should be disabled.
405 Each bit represents physical core id for both P-core and E-core:
406 1 - Disable
407 0 - Ignored
408 Default is 0, means no Core disable mask setting.
409 **/
410 UINT32 DisablePerCoreMask;
411 /**
412 Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCoreCount is to set the number of active atoms.
413 Each bit represents logical core id:
414 1 - Disable
415 0 - Ignored
416 Defalut is 0, means no Small Core disable mask setting.
417 **/
418 UINT32 DisablePerAtomMask; //Deprecated from version 36
419 /**
420 The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier
421 so that the output is within the DCO frequency range. This threshold is applied to all the domains
422 (Cores, Ring, SA, Memory and GT).
423 <b>0. Default/No Override</b>. Range 1-63.
424 **/
425 UINT8 PvdRatioThreshold;
426 /**
427 PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).
428 0x0 = div-1 (VCO = Output clock), 0x1 = div-2 (VCO = 2x Output clock)
429 0x2 = div-4 (VCO = 4x Output clock), 0x3 = div-8 (VCO = 8x Output clock)
430 **/
431 UINT8 PvdMode;
432 /**
433 FLL_OVERCLOCK_MODE: 0x0 = no overclocking,
434 0x1 = ratio overclocking with nominal (0.5-1x) reference clock frequency,
435 0x2 = BCLK overclocking with elevated (1-3x) reference clock frequency,
436 0x3 = BCLK overclocking with extreme elevated (3-5x) reference clock frequency and ratio limited to 63.
437 **/
438 UINT8 FllOverclockMode;
439 /**
440 The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.
441 <b>0. Hardware Default/No Override</b>. Minimum must be greater than P0 and maximum is 120.
442 **/
443 UINT8 PllMaxBandingRatio; /// Deprecated from revision 34
444 INT16 PerAtomClusterVoltageOffset[CPU_MAX_ATOM_CLUSTERS];
445 UINT32 SocBclkOcFrequency; ///< SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 - Auto</b>. Range is 4000-100000 (10KHz)
446 /**
447 Voltage Regulator Current Limit (Icc Max) for IA and GT. This value represents the Maximum instantaneous current allowed at any given time.
448 The value is represented in 1/4 A increments. A value of 400 = 100A. <b>4</b>. Range is 4-2047.
449 **/
450 UINT16 IaIccMax;
451 UINT16 GtIccMax;
452 /**
453 Down Bins (delta) for Temperature Threshold 0. When running above Temperature Threshold 0,
454 the ratio will be clipped by MAX_RATIO[n]-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
455 <b>1 </b>. Range 0-10.
456 **/
457 UINT8 TvbDownBinsTempThreshold0;
458 /**
459 TVB Temp (degrees C) - Temperature Threshold 0. Running ABOVE this temperature will clip delta
460 Down Bins for Threshold 0 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
461 <b>70 </b>. Range 0-100.
462 **/
463 UINT8 TvbTempThreshold0;
464 /**
465 TVB Temp (degrees C) - Temperature Threshold 1. Running ABOVE this temperature, clip delta
466 Down Bins for Threshold 1 from the resolved OC Ratio, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
467 <b>100 </b>. Range 0-100.
468 **/
469 UINT8 TvbTempThreshold1;
470 /**
471 Down Bins (delta) for Temperature Threshold 1. When running above Temperature Threshold 1,
472 the ratio will be clipped by MAX_RATIO[n]-Down Bin Threshold 0-This value, when Thermal turbo is enabled from OCMB 0x18 Bit 2 = 0 (Enabled).
473 <b>2 </b>. Range 0-10.
474 **/
475 UINT8 TvbDownBinsTempThreshold1;
476 } OVERCLOCKING_PREMEM_CONFIG;
477
478 #pragma pack (pop)
479
480 #endif // _CPU_OVERCLOCKING_CONFIG_H_
OVERCLOCKING_PREMEM_CONFIG::RingVoltageAdaptive
UINT16 RingVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the ring is operati...
Definition: OverclockingConfig.h:239
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOffset
INT16 RingVoltageOffset
The ring voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:244
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOverride
UINT16 GtVoltageOverride
The GT voltage override which is applied to the entire range of GT frequencies 0=Default
Definition: OverclockingConfig.h:247
OVERCLOCKING_PREMEM_CONFIG::Avx512VoltageScaleFactor
UINT8 Avx512VoltageScaleFactor
Avx512 Voltage Guardband Scale Factor This controls the AVX512 Voltage Guardband Scale factor applied...
Definition: OverclockingConfig.h:316
OVERCLOCKING_PREMEM_CONFIG::GtVoltageOffset
INT16 GtVoltageOffset
The voltage offset applied to GT slice. Valid range from -1000mv to 1000mv: 0=Minimal,...
Definition: OverclockingConfig.h:246
OVERCLOCKING_PREMEM_CONFIG::SaCepEnable
UINT32 SaCepEnable
Enable SA Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:256
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageAdaptive
UINT16 CoreVoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operatin...
Definition: OverclockingConfig.h:222
OVERCLOCKING_PREMEM_CONFIG::FllOverclockMode
UINT8 FllOverclockMode
FLL_OVERCLOCK_MODE: 0x0 = no overclocking, 0x1 = ratio overclocking with nominal (0....
Definition: OverclockingConfig.h:438
OVERCLOCKING_PREMEM_CONFIG::IaIccMax
UINT16 IaIccMax
Voltage Regulator Current Limit (Icc Max) for IA and GT.
Definition: OverclockingConfig.h:450
OVERCLOCKING_PREMEM_CONFIG::ItdThrottleEnable
UINT32 ItdThrottleEnable
Enable Inverse Temperature Dependency Throttle Support. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:258
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointOffsetMode
UINT32 CoreVfPointOffsetMode
Deprecated < Fivr Efficiency Management. 0: Disabled, 1: Enabled.
Definition: OverclockingConfig.h:177
OVERCLOCKING_PREMEM_CONFIG::RealtimeMemoryTiming
UINT32 RealtimeMemoryTiming
Enable/Disable the message sent to the CPU to allow realtime memory timing changes after MRC_DONE....
Definition: OverclockingConfig.h:168
OVERCLOCKING_PREMEM_CONFIG::SocBclkOcFrequency
UINT32 SocBclkOcFrequency
SOC BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:445
OVERCLOCKING_PREMEM_CONFIG::Avx2VoltageScaleFactor
UINT8 Avx2VoltageScaleFactor
Avx2 Voltage Guardband Scale Factor This controls the AVX2 Voltage Guardband Scale factor applied to ...
Definition: OverclockingConfig.h:304
OVERCLOCKING_PREMEM_CONFIG::DisablePerAtomMask
UINT32 DisablePerAtomMask
Small Core disable mask is a bitwise indication of which atom should be disabled, while ActiveSmallCo...
Definition: OverclockingConfig.h:418
OVERCLOCKING_PREMEM_CONFIG::RingDownBin
UINT32 RingDownBin
Ring Downbin enable/disable.
Definition: OverclockingConfig.h:160
OVERCLOCKING_PREMEM_CONFIG::UnlimitedIccMax
UINT32 UnlimitedIccMax
deprecated from version 32
Definition: OverclockingConfig.h:186
OVERCLOCKING_PREMEM_CONFIG::Avx2RatioOffset
UINT32 Avx2RatioOffset
AVX2 Ratio Offset. 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize possible rati...
Definition: OverclockingConfig.h:150
OVERCLOCKING_PREMEM_CONFIG::FllOcModeEn
UINT32 FllOcModeEn
Enable FLL Mode override with the value in FllOcMode. 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:284
OVERCLOCKING_PREMEM_CONFIG::CoreVfPointCount
UINT8 CoreVfPointCount
Number of supported Core Voltage & Frequency Point.
Definition: OverclockingConfig.h:330
OVERCLOCKING_PREMEM_CONFIG::PerCoreHtDisable
UINT16 PerCoreHtDisable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, 0 - is ignored.
Definition: OverclockingConfig.h:292
OVERCLOCKING_PREMEM_CONFIG::SaPllFreqOverride
UINT32 SaPllFreqOverride
Sa PLL Frequecy Override. 0: 3200MHz. 1: 1600MHz.
Definition: OverclockingConfig.h:260
OVERCLOCKING_PREMEM_CONFIG::RingVfPointCount
UINT8 RingVfPointCount
Number of supported Ring Voltage & Frequency Point.
Definition: OverclockingConfig.h:389
OVERCLOCKING_PREMEM_CONFIG::GtCepEnable
UINT32 GtCepEnable
Enable GT Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:255
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOverride
UINT16 AtomL2VoltageOverride
The atom L2 voltage override which is applied to the entire range of atom core frequencies.
Definition: OverclockingConfig.h:355
OVERCLOCKING_PREMEM_CONFIG
Overclocking Configuration Structure.
Definition: OverclockingConfig.h:132
OVERCLOCKING_PREMEM_CONFIG::IaSirpEnable
UINT32 IaSirpEnable
Enable IA SoC Iccmax Reactive Protector. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:257
OVERCLOCKING_PREMEM_CONFIG::GtMaxOcRatio
UINT8 GtMaxOcRatio
Maximum GT turbo ratio override: 0=Minimal, 60=Maximum, 0=AUTO
Definition: OverclockingConfig.h:200
OVERCLOCKING_PREMEM_CONFIG::RingVoltageOverride
UINT16 RingVoltageOverride
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Definition: OverclockingConfig.h:233
OVERCLOCKING_PREMEM_CONFIG::OcSupport
UINT32 OcSupport
Overclocking support.
Definition: OverclockingConfig.h:141
OVERCLOCKING_PREMEM_CONFIG::Etvb
UINT32 Etvb
Enhanced Thermal Turbo Mode (eTVB). 0:eTVB is disabled on supporting products 1:eTVB is enabled on su...
Definition: OverclockingConfig.h:285
OVERCLOCKING_PREMEM_CONFIG::RsvdByte4
UINT8 RsvdByte4
Reserved for dword alignment.
Definition: OverclockingConfig.h:349
OVERCLOCKING_PREMEM_CONFIG::IaIccUnlimitedMode
UINT32 IaIccUnlimitedMode
Support IA Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:282
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
OVERCLOCKING_PREMEM_CONFIG::FivrEfficiency
UINT32 FivrEfficiency
Deprecated < Fivr Faults. Enable or Disable FIVR Faults. 0: Disabled, 1: Enabled.
Definition: OverclockingConfig.h:170
OVERCLOCKING_PREMEM_CONFIG::CoreRatioExtensionMode
UINT32 CoreRatioExtensionMode
Enable or disable Core Ratio above 85 Extension Mode by writing BIOS MB 0x37 to enable FULL_RANGE_MUL...
Definition: OverclockingConfig.h:193
OVERCLOCKING_PREMEM_CONFIG::AtomL2MaxOcRatio
UINT8 AtomL2MaxOcRatio
Maximum ATOM L2 turbo ratio override allows to increase CPU core frequency beyond the fused max turbo...
Definition: OverclockingConfig.h:210
CpuLimits.h
This file declares CPU limitated definition.
OVERCLOCKING_PREMEM_CONFIG::IaCepEnable
UINT32 IaCepEnable
Enable IA Current Excursion Protection. 1: Enable. 0: Disable.
Definition: OverclockingConfig.h:254
OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold1
UINT8 TvbTempThreshold1
TVB Temp (degrees C) - Temperature Threshold 1.
Definition: OverclockingConfig.h:469
OVERCLOCKING_PREMEM_CONFIG::SaVoltageMode
UINT32 SaVoltageMode
SA/Uncore voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:192
OVERCLOCKING_PREMEM_CONFIG::DisablePerCoreMask
UINT32 DisablePerCoreMask
Core disable mask is a bitwise indication of which core should be disabled.
Definition: OverclockingConfig.h:410
OVERCLOCKING_PREMEM_CONFIG::GtPllVoltageOffset
UINT32 GtPllVoltageOffset
GT PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:250
OVERCLOCKING_PREMEM_CONFIG::DlvrBypassModeEnable
UINT32 DlvrBypassModeEnable
Enable CPU DLVR bypass mode support, 0: Disable. 0: Enable.
Definition: OverclockingConfig.h:259
OVERCLOCKING_PREMEM_CONFIG::CpuBclkOcFrequency
UINT32 CpuBclkOcFrequency
CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz 0 - Auto....
Definition: OverclockingConfig.h:402
OVERCLOCKING_PREMEM_CONFIG::RingMaxOcRatio
UINT8 RingMaxOcRatio
Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max ring ratio lim...
Definition: OverclockingConfig.h:205
OVERCLOCKING_PREMEM_CONFIG::Avx3RatioOffset
UINT32 Avx3RatioOffset
deprecated from version 28
Definition: OverclockingConfig.h:151
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageOffset
INT16 AtomL2VoltageOffset
The atom L2 voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:366
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOverride
UINT16 SaVoltageOverride
The SA/Uncore voltage override which is applied to the entire range of uncore frequencies.
Definition: OverclockingConfig.h:372
OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold1
UINT8 TvbDownBinsTempThreshold1
Down Bins (delta) for Temperature Threshold 1.
Definition: OverclockingConfig.h:475
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOverride
UINT16 CoreVoltageOverride
The core voltage override which is applied to the entire range of cpu core frequencies.
Definition: OverclockingConfig.h:216
OVERCLOCKING_PREMEM_CONFIG::TvbTempThreshold0
UINT8 TvbTempThreshold0
TVB Temp (degrees C) - Temperature Threshold 0.
Definition: OverclockingConfig.h:463
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageMode
UINT32 CoreVoltageMode
Core voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:148
OVERCLOCKING_PREMEM_CONFIG::CoreVfConfigScope
UINT32 CoreVfConfigScope
Core VF Configuration Scope.
Definition: OverclockingConfig.h:184
OVERCLOCKING_PREMEM_CONFIG::PvdMode
UINT8 PvdMode
PVD Mode selects Static PVD ratio (when PVD THRESHOLD is 0).
Definition: OverclockingConfig.h:431
OVERCLOCKING_PREMEM_CONFIG::BclkAdaptiveVoltage
UINT32 BclkAdaptiveVoltage
Bclk Adaptive Voltage enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/F curves are a...
Definition: OverclockingConfig.h:152
OVERCLOCKING_PREMEM_CONFIG::McPllVoltageOffset
UINT32 McPllVoltageOffset
Memory Controller PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:253
OVERCLOCKING_PREMEM_CONFIG::PvdRatioThreshold
UINT8 PvdRatioThreshold
The Pvd Ratio Threshold is the threshold value for input ratio (P0 to Pn) to select the multiplier so...
Definition: OverclockingConfig.h:425
OVERCLOCKING_PREMEM_CONFIG::PllMaxBandingRatio
UINT8 PllMaxBandingRatio
The PLL Max Banding Ratio is to allow setting a new PLL Max Banding Ratio for IA domains.
Definition: OverclockingConfig.h:443
OVERCLOCKING_PREMEM_CONFIG::TvbVoltageOptimization
UINT32 TvbVoltageOptimization
This service controls thermal based voltage optimizations for processors that implement the Intel The...
Definition: OverclockingConfig.h:281
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageAdaptive
UINT16 AtomL2VoltageAdaptive
Adaptive Turbo voltage target used to define the interpolation voltage point when the atom is operati...
Definition: OverclockingConfig.h:361
OVERCLOCKING_PREMEM_CONFIG::SaExtraTurboVoltage
UINT16 SaExtraTurboVoltage
Adaptive Turbo voltage target used to define the interpolation voltage point when the SA/Uncore is op...
Definition: OverclockingConfig.h:378
OVERCLOCKING_PREMEM_CONFIG::SaVoltageOffset
INT16 SaVoltageOffset
The voltage offset applied to the SA. Valid range from -1000mv to 1000mv: 0=Default
Definition: OverclockingConfig.h:249
OVERCLOCKING_PREMEM_CONFIG::GtVoltageMode
UINT32 GtVoltageMode
Specifies whether GT voltage is operating in Adaptive or Override mode: 0=Adaptive,...
Definition: OverclockingConfig.h:167
OVERCLOCKING_PREMEM_CONFIG::OcLock
UINT32 OcLock
If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration sett...
Definition: OverclockingConfig.h:142
OVERCLOCKING_PREMEM_CONFIG::AtomPllVoltageOffset
UINT8 AtomPllVoltageOffset
Atom PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:401
OVERCLOCKING_PREMEM_CONFIG::CorePllVoltageOffset
UINT32 CorePllVoltageOffset
Core PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:149
OVERCLOCKING_PREMEM_CONFIG::TscDisableHwFixup
UINT32 TscDisableHwFixup
Core HW Fixup disable during TSC copy from PMA to APIC, 0: Enable. 1: Disable.
Definition: OverclockingConfig.h:261
OVERCLOCKING_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: OverclockingConfig.h:133
OVERCLOCKING_PREMEM_CONFIG::RingVfPointOffsetMode
UINT8 RingVfPointOffsetMode
Selects Ring Voltage & Frequency Point Offset between Legacy and Selection modes.
Definition: OverclockingConfig.h:385
OVERCLOCKING_PREMEM_CONFIG::SaPllVoltageOffset
UINT32 SaPllVoltageOffset
System Agent PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:252
OVERCLOCKING_PREMEM_CONFIG::CoreVoltageOffset
INT16 CoreVoltageOffset
The core voltage offset applied on top of all other voltage modes.
Definition: OverclockingConfig.h:227
OVERCLOCKING_PREMEM_CONFIG::PerCoreRatioOverride
UINT32 PerCoreRatioOverride
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new favored core ratio...
Definition: OverclockingConfig.h:185
OVERCLOCKING_PREMEM_CONFIG::RingVoltageMode
UINT32 RingVoltageMode
Ring voltage mode, specifies which voltage mode the processor will be operating.
Definition: OverclockingConfig.h:166
OVERCLOCKING_PREMEM_CONFIG::RingPllVoltageOffset
UINT32 RingPllVoltageOffset
Ring PLL voltage offset. 0: No offset. Range 0-15 in 17.5mv units.
Definition: OverclockingConfig.h:251
OVERCLOCKING_PREMEM_CONFIG::TvbDownBinsTempThreshold0
UINT8 TvbDownBinsTempThreshold0
Down Bins (delta) for Temperature Threshold 0.
Definition: OverclockingConfig.h:457
OVERCLOCKING_PREMEM_CONFIG::GtExtraTurboVoltage
UINT16 GtExtraTurboVoltage
The adaptive voltage applied during turbo frequencies. Valid range from 0 to 2000mV: 0=Minimal,...
Definition: OverclockingConfig.h:248
OVERCLOCKING_PREMEM_CONFIG::GtIccUnlimitedMode
UINT32 GtIccUnlimitedMode
Support GT Unlimited ICCMAX up to maximum value 512A., 0: Disable. 1: Enable.
Definition: OverclockingConfig.h:283
OVERCLOCKING_PREMEM_CONFIG::CoreMaxOcRatio
UINT8 CoreMaxOcRatio
Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ra...
Definition: OverclockingConfig.h:199
OVERCLOCKING_PREMEM_CONFIG::TvbRatioClipping
UINT32 TvbRatioClipping
This service controls Core frequency reduction caused by high package temperatures for processors tha...
Definition: OverclockingConfig.h:275
OVERCLOCKING_PREMEM_CONFIG::TjMaxOffset
UINT8 TjMaxOffset
TjMax Offset.
Definition: OverclockingConfig.h:267
OVERCLOCKING_PREMEM_CONFIG::AtomL2VoltageMode
UINT8 AtomL2VoltageMode
Atom L2 voltage mode, specifies which voltage mode the atom processor will be operating.
Definition: OverclockingConfig.h:348
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): P2sbConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
Classes
P2sbConfig.h File Reference

P2sb policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device. More...

Detailed Description

P2sb policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file P2sbConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): P2sbConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sbConfig.h
Go to the documentation of this file.
1 /** @file
2 P2sb policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _P2SB_CONFIG_H_
36 #define _P2SB_CONFIG_H_
37
38 #define PCH_P2SB_CONFIG_REVISION 1
39 extern EFI_GUID gP2sbConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure contains the policies which are related to P2SB device.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 <b>(Test)</b>
50 The sideband MMIO register access to specific ports will be locked
51 before 3rd party code execution. Currently it disables PSFx access.
52 This policy unlocks the sideband MMIO space for those IPs.
53 <b>0: Lock sideband access </b>; 1: Unlock sideband access.
54 NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.
55 **/
56 UINT32 SbAccessUnlock : 1;
57 UINT32 Rsvdbits : 31; ///< Reserved bits
58 } PCH_P2SB_CONFIG;
59
60 #pragma pack (pop)
61
62 #endif // _P2SB_CONFIG_H_
PCH_P2SB_CONFIG
This structure contains the policies which are related to P2SB device.
Definition: P2sbConfig.h:46
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_P2SB_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: P2sbConfig.h:57
PCH_P2SB_CONFIG::SbAccessUnlock
UINT32 SbAccessUnlock
(Test) The sideband MMIO register access to specific ports will be locked before 3rd party code execu...
Definition: P2sbConfig.h:56
PCH_P2SB_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: P2sbConfig.h:47
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): P2sbLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
P2sbLib.h File Reference

This file provides P2SB public library. More...

Go to the source code of this file.

Functions

UINT32 | P2sbGetEpmask (IN UINT32 EpMaskNum)
Get P2SB EPMASK setting Note: after end of pei this function can be used only in SMM. More...
BOOLEAN | P2sbIsEpmaskLock (VOID)
Check P2SB EPMASK is locked Note: after end of pei this function can be used only in SMM. More...

Detailed Description

This file provides P2SB public library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file P2sbLib.h.

Function Documentation

◆ P2sbGetEpmask()

UINT32 P2sbGetEpmask ( IN UINT32 EpMaskNum )

Get P2SB EPMASK setting Note: after end of pei this function can be used only in SMM.

Parameters
[in] EpMaskNum EPMASK number
Return values
EPMASKx setting

◆ P2sbIsEpmaskLock()

BOOLEAN P2sbIsEpmaskLock ( VOID )

Check P2SB EPMASK is locked Note: after end of pei this function can be used only in SMM.

Return values
TRUE P2SB EPMASK is locked FALSE P2SB EPMASK is not locked
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): P2sbLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
P2sbLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides P2SB public library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _P2SB_LIB_H_
36 #define _P2SB_LIB_H_
37
38 /**
39 Get P2SB EPMASK setting
40 Note: after end of pei this function can be used only in SMM
41
42 @param[in] EpMaskNum EPMASK number
43
44 @retval EPMASKx setting
45 **/
46 UINT32
47 P2sbGetEpmask (
48 IN UINT32 EpMaskNum
49 );
50
51 /**
52 Check P2SB EPMASK is locked
53 Note: after end of pei this function can be used only in SMM
54
55 @retval TRUE P2SB EPMASK is locked
56 FALSE P2SB EPMASK is not locked
57 **/
58 BOOLEAN
59 P2sbIsEpmaskLock (
60 VOID
61 );
62
63 #endif // _P2SB_LIB_H_
P2sbGetEpmask
UINT32 P2sbGetEpmask(IN UINT32 EpMaskNum)
Get P2SB EPMASK setting Note: after end of pei this function can be used only in SMM.
P2sbIsEpmaskLock
BOOLEAN P2sbIsEpmaskLock(VOID)
Check P2SB EPMASK is locked Note: after end of pei this function can be used only in SMM.
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchAcpiSmiDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Macros | Typedefs
PchAcpiSmiDispatch.h File Reference

APIs of PCH ACPI SMI Dispatch Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL
Interface structure for PCH ACPI SMIs Dispatch Protocol The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs. More...

Macros

#define PCH_ACPI_SMI_DISPATCH_REVISION 1
PCH ACPI SMI dispatch revision number. More...

Typedefs

typedef VOID(* | PCH_ACPI_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)
Callback function for an PCH ACPI SMI handler dispatch. More...
typedef EFI_STATUS(* | PCH_ACPI_SMI_DISPATCH_REGISTER) (IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH ACPI SMI events. More...
typedef EFI_STATUS(* | PCH_ACPI_SMI_DISPATCH_UNREGISTER) (IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent ACPI SMM driver. More...

Detailed Description

APIs of PCH ACPI SMI Dispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchAcpiSmiDispatch.h.

Macro Definition Documentation

◆ PCH_ACPI_SMI_DISPATCH_REVISION

#define PCH_ACPI_SMI_DISPATCH_REVISION 1

PCH ACPI SMI dispatch revision number.

Revision 1: Initial version

Definition at line 160 of file PchAcpiSmiDispatch.h.

Typedef Documentation

◆ PCH_ACPI_SMI_DISPATCH_CALLBACK

typedef VOID( * PCH_ACPI_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)

Callback function for an PCH ACPI SMI handler dispatch.

Parameters
[in] DispatchHandle The unique handle assigned to this handler by register function.

Definition at line 59 of file PchAcpiSmiDispatch.h.

◆ PCH_ACPI_SMI_DISPATCH_REGISTER

typedef EFI_STATUS( * PCH_ACPI_SMI_DISPATCH_REGISTER) (IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)

Register a child SMI source dispatch function for PCH ACPI SMI events.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchFunction | Pointer to dispatch function to be invoked for this SMI source
[out] | DispatchHandle | Handle of dispatch function, for when interfacing with the parent SMM driver.
Return values
EFI_SUCCESS | The dispatch function has been successfully registered and the SMI source has been enabled.
EFI_DEVICE_ERROR | The driver was unable to enable the SMI source.
EFI_OUT_OF_RESOURCES | Not enough memory (system or SMM) to manage this child.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 80 of file PchAcpiSmiDispatch.h.

◆ PCH_ACPI_SMI_DISPATCH_UNREGISTER

typedef EFI_STATUS( * PCH_ACPI_SMI_DISPATCH_UNREGISTER) (IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

Unregister a child SMI source dispatch function with a parent ACPI SMM driver.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchHandle | Handle of dispatch function to deregister.
Return values
EFI_SUCCESS | The dispatch function has been successfully unregistered and the SMI source has been disabled if there are no other registered child dispatch functions for this SMI source.
EFI_INVALID_PARAMETER | Handle is invalid.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 101 of file PchAcpiSmiDispatch.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchAcpiSmiDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchAcpiSmiDispatch.h
Go to the documentation of this file.
1 /** @file
2 APIs of PCH ACPI SMI Dispatch Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_
36 #define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid;
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PROTOCOL;
47
48 //
49 // Member functions
50 //
51
52 /**
53 Callback function for an PCH ACPI SMI handler dispatch.
54
55 @param[in] DispatchHandle The unique handle assigned to this handler by register function.
56
57 **/
58 typedef
59 VOID
60 (EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) (
61 IN EFI_HANDLE DispatchHandle
62 );
63
64 /**
65 Register a child SMI source dispatch function for PCH ACPI SMI events.
66
67 @param[in] This Protocol instance pointer.
68 @param[in] DispatchFunction Pointer to dispatch function to be invoked for
69 this SMI source
70 @param[out] DispatchHandle Handle of dispatch function, for when interfacing
71 with the parent SMM driver.
72
73 @retval EFI_SUCCESS The dispatch function has been successfully
74 registered and the SMI source has been enabled.
75 @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
76 @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
77 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
78 **/
79 typedef
80 EFI_STATUS
81 (EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) (
82 IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,
83 IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction,
84 OUT EFI_HANDLE *DispatchHandle
85 );
86
87 /**
88 Unregister a child SMI source dispatch function with a parent ACPI SMM driver
89
90 @param[in] This Protocol instance pointer.
91 @param[in] DispatchHandle Handle of dispatch function to deregister.
92
93 @retval EFI_SUCCESS The dispatch function has been successfully
94 unregistered and the SMI source has been disabled
95 if there are no other registered child dispatch
96 functions for this SMI source.
97 @retval EFI_INVALID_PARAMETER Handle is invalid.
98 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
99 **/
100 typedef
101 EFI_STATUS
102 (EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) (
103 IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,
104 IN EFI_HANDLE DispatchHandle
105 );
106
107 /**
108 Interface structure for PCH ACPI SMIs Dispatch Protocol
109 The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs.
110 It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow.
111 **/
112 struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL {
113 /**
114 This member specifies the revision of this structure. This field is used to
115 indicate backwards compatible changes to the protocol.
116 **/
117 UINT8 Revision;
118 /**
119 Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL.
120 **/
121 PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister;
122 /**
123 Pme
124 The event is triggered by hardware when the PME# signal goes active.
125 Additionally, the event is only triggered when SCI_EN is not set.
126 **/
127 PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister;
128 /**
129 PmeB0
130 The event is triggered PCH when any internal device with PCI Power Management
131 capabilities on bus 0 asserts the equivalent of the PME# signal.
132 Additionally, the event is only triggered when SCI_EN is not set.
133 The following are internal devices which can set this bit:
134 Intel HD Audio, Intel Management Engine "maskable" wake events, Integrated LAN,
135 SATA, xHCI, Intel SST
136 **/
137 PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register;
138 /**
139 RtcAlarm
140 The event is triggered by hardware when the RTC generates an alarm
141 (assertion of the IRQ8# signal).
142 **/
143 PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister;
144 /**
145 TmrOverflow
146 The event is triggered any time bit 22 of the 24-bit timer goes high
147 (bits are numbered from 0 to 23).
148 This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 02h, bit 0) is set,
149 then the setting of the TMROF_STS bit will additionally generate an SMI#
150 Additionally, the event is only triggered when SCI_EN is not set.
151 **/
152 PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister;
153 };
154
155 /**
156 PCH ACPI SMI dispatch revision number
157
158 Revision 1: Initial version
159 **/
160 #define PCH_ACPI_SMI_DISPATCH_REVISION 1
161
162 #endif
PCH_ACPI_SMI_DISPATCH_CALLBACK
VOID(* PCH_ACPI_SMI_DISPATCH_CALLBACK)(IN EFI_HANDLE DispatchHandle)
Callback function for an PCH ACPI SMI handler dispatch.
Definition: PchAcpiSmiDispatch.h:60
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: PchAcpiSmiDispatch.h:117
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::PmeRegister
PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister
Pme The event is triggered by hardware when the PME# signal goes active.
Definition: PchAcpiSmiDispatch.h:127
PCH_ACPI_SMI_DISPATCH_UNREGISTER
EFI_STATUS(* PCH_ACPI_SMI_DISPATCH_UNREGISTER)(IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent ACPI SMM driver.
Definition: PchAcpiSmiDispatch.h:102
PCH_ACPI_SMI_DISPATCH_REGISTER
EFI_STATUS(* PCH_ACPI_SMI_DISPATCH_REGISTER)(IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH ACPI SMI events.
Definition: PchAcpiSmiDispatch.h:81
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::PmeB0Register
PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register
PmeB0 The event is triggered PCH when any internal device with PCI Power Management capabilities on b...
Definition: PchAcpiSmiDispatch.h:137
_PCH_ACPI_SMI_DISPATCH_PROTOCOL
Interface structure for PCH ACPI SMIs Dispatch Protocol The PCH ACPI SMI DISPATCH PROTOCOL provides t...
Definition: PchAcpiSmiDispatch.h:112
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::UnRegister
PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL.
Definition: PchAcpiSmiDispatch.h:121
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::RtcAlarmRegister
PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister
RtcAlarm The event is triggered by hardware when the RTC generates an alarm (assertion of the IRQ8# s...
Definition: PchAcpiSmiDispatch.h:143
_PCH_ACPI_SMI_DISPATCH_PROTOCOL::TmrOverflowRegister
PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister
TmrOverflow The event is triggered any time bit 22 of the 24-bit timer goes high (bits are numbered f...
Definition: PchAcpiSmiDispatch.h:152
Generated on Wed Jan 5 2022 01:24:00 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchCycleDecodingLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Classes | Functions
PchCycleDecodingLib.h File Reference

Header file for PchCycleDecodingLib. More...

Go to the source code of this file.

Classes

struct | PCH_LPC_GEN_IO_RANGE
structure of LPC general IO range register It contains base address, address mask, and enable status. More...
struct | PCH_LPC_GEN_IO_RANGE_LIST
structure of LPC general IO range register list It lists all LPC general IO ran registers supported by PCH. More...

Functions

EFI_STATUS | PchTcoBaseSet (IN UINT16 Address)
Set PCH TCO base address. More...
EFI_STATUS | PchTcoBaseGet (OUT UINT16 *Address)
Get PCH TCO base address. More...
EFI_STATUS | PchLpcGenIoRangeSet (IN UINT16 Address, IN UINTN Length)
Set PCH LPC/eSPI generic IO range. More...
EFI_STATUS | PchLpcGenIoRangeClear (IN UINT16 Address, IN UINTN Length)
Clear IBL eSPI generic IO range. More...
EFI_STATUS | PchEspiCs1GenIoRangeSet (IN UINT16 Address, IN UINTN Length)
Set PCH eSPI CS1# generic IO range decoding. More...
EFI_STATUS | PchLpcGenIoRangeGet (OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList)
Get PCH LPC/eSPI generic IO range list. More...
EFI_STATUS | PchEspiCs1GenIoRangeGet (OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList)
Get PCH eSPI CS1# generic IO range list. More...
EFI_STATUS | PchLpcMemRangeSet (IN UINT32 Address)
Set PCH LPC/eSPI memory range decoding. More...
EFI_STATUS | PchEspiCs1MemRangeSet (IN UINT32 Address)
Set PCH eSPI CS1# memory range decoding. More...
EFI_STATUS | PchLpcMemRangeGet (OUT UINT32 *Address)
Get PCH LPC/eSPI memory range decoding address. More...
EFI_STATUS | PchEspiCs1MemRangeGet (OUT UINT32 *Address)
Get PCH eSPI CS1# memory range decoding address. More...
EFI_STATUS | PchBiosDecodeEnableSet (IN UINT16 BiosDecodeEnable)
Set PCH BIOS range deocding. More...
EFI_STATUS | PchLpcIoDecodeRangesSet (IN UINT16 LpcIoDecodeRanges)
Set PCH LPC IO decode ranges. More...
EFI_STATUS | PchLpcIoEnableDecodingSet (IN UINT16 LpcIoEnableDecoding)
Set PCH LPC and eSPI CS0# IO enable decoding. More...
EFI_STATUS | PchEspiCs1IoEnableDecodingSet (IN UINT16 IoEnableDecoding)
Set PCH eSPI CS1# IO enable decoding. More...
EFI_STATUS | PchLpcIoEnableDecodingAndThenOr (IN UINT16 AndValue, IN UINT16 OrValue)
AND then OR PCH LPC and eSPI CS0# IO enable decoding. More...
EFI_STATUS | PchIoPort80DecodeSet (IN UINTN RpPhyNumber)
Set PCH IO port 80h cycle decoding to PCIE root port. More...
EFI_STATUS | PchIoApicBaseGet (OUT UINT32 *IoApicBase)
Get IO APIC regsiters base address. More...
EFI_STATUS | PchHpetBaseGet (OUT UINT32 *HpetBase)
Get HPET base address. More...

Detailed Description

Header file for PchCycleDecodingLib.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchCycleDecodingLib.h.

Function Documentation

◆ PchBiosDecodeEnableSet()

EFI_STATUS PchBiosDecodeEnableSet ( IN UINT16 BiosDecodeEnable )

Set PCH BIOS range deocding.

This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly. Please check EDS for detail of BiosDecodeEnable bit definition. bit 15: F8-FF Enable bit 14: F0-F8 Enable bit 13: E8-EF Enable bit 12: E0-E8 Enable bit 11: D8-DF Enable bit 10: D0-D7 Enable bit 9: C8-CF Enable bit 8: C0-C7 Enable bit 7: Legacy F Segment Enable bit 6: Legacy E Segment Enable bit 5: Reserved bit 4: Reserved bit 3: 70-7F Enable bit 2: 60-6F Enable bit 1: 50-5F Enable bit 0: 40-4F Enable This cycle decoding is allowed to set when DMIC.SRL is 0. Programming steps:

  1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
  2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
Parameters
[in] BiosDecodeEnable Bios decode enable setting.
Return values
EFI_SUCCESS Successfully completed.

◆ PchEspiCs1GenIoRangeGet()

EFI_STATUS PchEspiCs1GenIoRangeGet ( OUT PCH_LPC_GEN_IO_RANGE_LIST * GenIoRangeList )

Get PCH eSPI CS1# generic IO range list.

This function returns a list of base address, length, and enable for all eSPI CS1# generic IO range registers.

Parameters
[out] GenIoRangeList eSPI generic IO range registers.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address passed.
EFI_UNSUPPORTED | eSPI secondary target not supported

◆ PchEspiCs1GenIoRangeSet()

EFI_STATUS PchEspiCs1GenIoRangeSet | ( | IN UINT16 | Address,
 |  | IN UINTN | Length
 | ) |  |

Set PCH eSPI CS1# generic IO range decoding.

For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 and less than or equal to 256. Moreover, the address must be length aligned. This function basically checks the address and length, which should not overlap with all other generic ranges. If no more generic range register available, it returns out of resource error. This cycle decoding is also required on DMI side Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges: 0x00-0x1F, 0x44-0x4B, 0x54-0x5F, 0x68-0x6F, 0x80-0x8F, 0xC0-0xFF Steps of programming generic IO range:

  1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable.
  2. Program eSPI Generic IO Range in DMI
Parameters
[in] | Address | Address for generic IO range decoding.
[in] | Length | Length of generic IO range.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address or length passed.
EFI_OUT_OF_RESOURCES | No more generic range available.
EFI_UNSUPPORTED | eSPI secondary target not supported

◆ PchEspiCs1IoEnableDecodingSet()

EFI_STATUS PchEspiCs1IoEnableDecodingSet ( IN UINT16 IoEnableDecoding )

Set PCH eSPI CS1# IO enable decoding.

Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h (eSPI CS1#). Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive agent for handling. Please check EDS for detail of eSPI IO decode ranges bit definition.

Parameters
[in] IoEnableDecoding eSPI IO enable decoding bit settings.
Return values
EFI_SUCCESS | Successfully completed.
EFI_UNSUPPORTED | DMI configuration is locked

◆ PchEspiCs1MemRangeGet()

EFI_STATUS PchEspiCs1MemRangeGet ( OUT UINT32 * Address )

Get PCH eSPI CS1# memory range decoding address.

Parameters
[out] Address Address of eSPI CS1# memory decoding base address.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address passed.
EFI_UNSUPPORTED | eSPI secondary target not supported

◆ PchEspiCs1MemRangeSet()

EFI_STATUS PchEspiCs1MemRangeSet ( IN UINT32 Address )

Set PCH eSPI CS1# memory range decoding.

This cycle decoding is required to be set on DMI side Programming steps:

  1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory decoding first before changing base address.
  2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
  3. Program eSPI Memory Range in DMI
Parameters
[in] Address Address for memory for decoding.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address or length passed.
EFI_UNSUPPORTED | eSPI secondary target not supported

◆ PchHpetBaseGet()

EFI_STATUS PchHpetBaseGet ( OUT UINT32 * HpetBase )

Get HPET base address.

This function will be unavailable after P2SB is hidden by PSF.

Parameters
[out] HpetBase Buffer of HPET base address
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid offset passed.

◆ PchIoApicBaseGet()

EFI_STATUS PchIoApicBaseGet ( OUT UINT32 * IoApicBase )

Get IO APIC regsiters base address.

Parameters
[out] IoApicBase Buffer of IO APIC regsiter address
Return values
EFI_SUCCESS Successfully completed.

◆ PchIoPort80DecodeSet()

EFI_STATUS PchIoPort80DecodeSet ( IN UINTN RpPhyNumber )

Set PCH IO port 80h cycle decoding to PCIE root port.

System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12]) before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default IO range values. This cycle decoding is allowed to set when DMIC.SRL is 0. Programming steps:

  1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
  2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO.
  3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding.
Parameters
[in] RpPhyNumber PCIE root port physical number.
Return values
EFI_SUCCESS Successfully completed.

◆ PchLpcGenIoRangeClear()

EFI_STATUS PchLpcGenIoRangeClear | ( | IN UINT16 | Address,
 |  | IN UINTN | Length
 | ) |  |

Clear IBL eSPI generic IO range.

Clear Generic IO range if already programmed. If Address/Length not match any already programmed values return EFI_NOT_FOUND status.

Steps of programming generic IO range:

  1. Clear eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
Parameters
[in] | Address | Address for generic IO range base address.
[in] | Length | Length of generic IO range.
Return values
EFI_SUCCESS | Successfully completed.
EFI_NOT_FOUND | Address/Length not found in alredy programmed Gen IO.

◆ PchLpcGenIoRangeGet()

EFI_STATUS PchLpcGenIoRangeGet ( OUT PCH_LPC_GEN_IO_RANGE_LIST * LpcGenIoRangeList )

Get PCH LPC/eSPI generic IO range list.

This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range registers.

Parameters
[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address passed.

◆ PchLpcGenIoRangeSet()

EFI_STATUS PchLpcGenIoRangeSet | ( | IN UINT16 | Address,
 |  | IN UINTN | Length
 | ) |  |

Set PCH LPC/eSPI generic IO range.

For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2 and less than or equal to 256. Moreover, the address must be length aligned. This function basically checks the address and length, which should not overlap with all other generic ranges. If no more generic range register available, it returns out of resource error. This cycle decoding is also required on DMI side. Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges: 0x00-0x1F, 0x44-0x4B, 0x54-0x5F, 0x68-0x6F, 0x80-0x8F, 0xC0-0xFF Steps of programming generic IO range:

  1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
  2. Program LPC/eSPI Generic IO Range in DMI
Parameters
[in] | Address | Address for generic IO range base address.
[in] | Length | Length of generic IO range.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address or length passed.
EFI_OUT_OF_RESOURCES | No more generic range available.
EFI_UNSUPPORTED | DMIC.SRL is set.

◆ PchLpcIoDecodeRangesSet()

EFI_STATUS PchLpcIoDecodeRangesSet ( IN UINT16 LpcIoDecodeRanges )

Set PCH LPC IO decode ranges.

Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h. Please check EDS for detail of Lpc IO decode ranges bit definition. Bit 12: FDD range Bit 9:8: LPT range Bit 6:4: ComB range Bit 2:0: ComA range

Parameters
[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
Return values
EFI_SUCCESS | Successfully completed.
EFI_UNSUPPORTED | DMIC.SRL is set.

◆ PchLpcIoEnableDecodingAndThenOr()

EFI_STATUS PchLpcIoEnableDecodingAndThenOr | ( | IN UINT16 | AndValue,
 |  | IN UINT16 | OrValue
 | ) |  |

AND then OR PCH LPC and eSPI CS0# IO enable decoding.

Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h. Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.

Parameters
[in] | AndValue | LPC IO enable decoding "AND" value.
[in] | OrValue | LPC IO enable decoding "OR" value.
Return values
EFI_SUCCESS | Successfully completed.
EFI_UNSUPPORTED | DMIC.SRL is set.

◆ PchLpcIoEnableDecodingSet()

EFI_STATUS PchLpcIoEnableDecodingSet ( IN UINT16 LpcIoEnableDecoding )

Set PCH LPC and eSPI CS0# IO enable decoding.

Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h. Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling. Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.

Parameters
[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
Return values
EFI_SUCCESS | Successfully completed.
EFI_UNSUPPORTED | DMIC.SRL is set.

◆ PchLpcMemRangeGet()

EFI_STATUS PchLpcMemRangeGet ( OUT UINT32 * Address )

Get PCH LPC/eSPI memory range decoding address.

Parameters
[out] Address Address of LPC/eSPI memory decoding base address.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address passed.

◆ PchLpcMemRangeSet()

EFI_STATUS PchLpcMemRangeSet ( IN UINT32 Address )

Set PCH LPC/eSPI memory range decoding.

This cycle decoding is required to be set on DMI side Programming steps:

  1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
  2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
  3. Program LPC Memory Range in DMI
Parameters
[in] Address Address for memory base address.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address or length passed.
EFI_OUT_OF_RESOURCES | No more generic range available.
EFI_UNSUPPORTED | DMIC.SRL is set.

◆ PchTcoBaseGet()

EFI_STATUS PchTcoBaseGet ( OUT UINT16 * Address )

Get PCH TCO base address.

Parameters
[out] Address Address of TCO base address.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid pointer passed.

◆ PchTcoBaseSet()

EFI_STATUS PchTcoBaseSet ( IN UINT16 Address )

Set PCH TCO base address.

This cycle decoding is allowed to set when DMIC.SRL is 0. Programming steps:

  1. set Smbus PCI offset 54h [8] to enable TCO base address.
  2. program Smbus PCI offset 50h [15:5] to TCO base address.
  3. set Smbus PCI offset 54h [8] to enable TCO base address.
  4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1].
Parameters
[in] Address Address for TCO base address.
Return values
EFI_SUCCESS | Successfully completed.
EFI_INVALID_PARAMETER | Invalid base address passed.
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchCycleDecodingLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchCycleDecodingLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchCycleDecodingLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_CYCLE_DECODING_LIB_H_
36 #define _PCH_CYCLE_DECODING_LIB_H_
37
38 /**
39 Set PCH TCO base address.
40 This cycle decoding is allowed to set when DMIC.SRL is 0.
41 Programming steps:
42 1. set Smbus PCI offset 54h [8] to enable TCO base address.
43 2. program Smbus PCI offset 50h [15:5] to TCO base address.
44 3. set Smbus PCI offset 54h [8] to enable TCO base address.
45 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI offset 50h[15:5], 1].
46
47 @param[in] Address Address for TCO base address.
48
49 @retval EFI_SUCCESS Successfully completed.
50 @retval EFI_INVALID_PARAMETER Invalid base address passed.
51 **/
52 EFI_STATUS
53 PchTcoBaseSet (
54 IN UINT16 Address
55 );
56
57 /**
58 Get PCH TCO base address.
59
60 @param[out] Address Address of TCO base address.
61
62 @retval EFI_SUCCESS Successfully completed.
63 @retval EFI_INVALID_PARAMETER Invalid pointer passed.
64 **/
65 EFI_STATUS
66 PchTcoBaseGet (
67 OUT UINT16 *Address
68 );
69
70 ///
71 /// structure of LPC general IO range register
72 /// It contains base address, address mask, and enable status.
73 ///
74 typedef struct {
75 UINT32 BaseAddr :16;
76 UINT32 Length :15;
77 UINT32 Enable : 1;
78 } PCH_LPC_GEN_IO_RANGE;
79
80 #define PCH_LPC_GEN_IO_RANGE_MAX 4
81 #define ESPI_CS1_GEN_IO_RANGE_MAX 1
82
83 ///
84 /// structure of LPC general IO range register list
85 /// It lists all LPC general IO ran registers supported by PCH.
86 ///
87 typedef struct {
88 PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
89 } PCH_LPC_GEN_IO_RANGE_LIST;
90
91 /**
92 Set PCH LPC/eSPI generic IO range.
93 For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
94 and less than or equal to 256. Moreover, the address must be length aligned.
95 This function basically checks the address and length, which should not overlap with all other generic ranges.
96 If no more generic range register available, it returns out of resource error.
97 This cycle decoding is also required on DMI side.
98 Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
99 but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
100 0x00-0x1F,
101 0x44-0x4B,
102 0x54-0x5F,
103 0x68-0x6F,
104 0x80-0x8F,
105 0xC0-0xFF
106 Steps of programming generic IO range:
107 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
108 2. Program LPC/eSPI Generic IO Range in DMI
109
110 @param[in] Address Address for generic IO range base address.
111 @param[in] Length Length of generic IO range.
112
113 @retval EFI_SUCCESS Successfully completed.
114 @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
115 @retval EFI_OUT_OF_RESOURCES No more generic range available.
116 @retval EFI_UNSUPPORTED DMIC.SRL is set.
117 **/
118 EFI_STATUS
119 PchLpcGenIoRangeSet (
120 IN UINT16 Address,
121 IN UINTN Length
122 );
123
124 /**
125 Clear IBL eSPI generic IO range.
126 Clear Generic IO range if already programmed.
127 If Address/Length not match any already programmed values return EFI_NOT_FOUND status.
128
129 Steps of programming generic IO range:
130 1. Clear eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
131
132 @param[in] Address Address for generic IO range base address.
133 @param[in] Length Length of generic IO range.
134
135 @retval EFI_SUCCESS Successfully completed.
136 @retval EFI_NOT_FOUND Address/Length not found in alredy programmed Gen IO.
137 **/
138 EFI_STATUS
139 PchLpcGenIoRangeClear (
140 IN UINT16 Address,
141 IN UINTN Length
142 );
143
144 /**
145 Set PCH eSPI CS1# generic IO range decoding.
146 For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
147 and less than or equal to 256. Moreover, the address must be length aligned.
148 This function basically checks the address and length, which should not overlap with all other generic ranges.
149 If no more generic range register available, it returns out of resource error.
150 This cycle decoding is also required on DMI side
151 Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
152 but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
153 0x00-0x1F,
154 0x44-0x4B,
155 0x54-0x5F,
156 0x68-0x6F,
157 0x80-0x8F,
158 0xC0-0xFF
159 Steps of programming generic IO range:
160 1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable.
161 2. Program eSPI Generic IO Range in DMI
162
163 @param[in] Address Address for generic IO range decoding.
164 @param[in] Length Length of generic IO range.
165
166 @retval EFI_SUCCESS Successfully completed.
167 @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
168 @retval EFI_OUT_OF_RESOURCES No more generic range available.
169 @retval EFI_UNSUPPORTED eSPI secondary target not supported
170 **/
171 EFI_STATUS
172 PchEspiCs1GenIoRangeSet (
173 IN UINT16 Address,
174 IN UINTN Length
175 );
176
177 /**
178 Get PCH LPC/eSPI generic IO range list.
179 This function returns a list of base address, length, and enable for all LPC/eSPI generic IO range registers.
180
181 @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO range register status.
182
183 @retval EFI_SUCCESS Successfully completed.
184 @retval EFI_INVALID_PARAMETER Invalid base address passed.
185 **/
186 EFI_STATUS
187 PchLpcGenIoRangeGet (
188 OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList
189 );
190
191 /**
192 Get PCH eSPI CS1# generic IO range list.
193 This function returns a list of base address, length, and enable for all eSPI CS1# generic IO range registers.
194
195 @param[out] GenIoRangeList eSPI generic IO range registers.
196
197 @retval EFI_SUCCESS Successfully completed.
198 @retval EFI_INVALID_PARAMETER Invalid base address passed.
199 @retval EFI_UNSUPPORTED eSPI secondary target not supported
200 **/
201 EFI_STATUS
202 PchEspiCs1GenIoRangeGet (
203 OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList
204 );
205
206 /**
207 Set PCH LPC/eSPI memory range decoding.
208 This cycle decoding is required to be set on DMI side
209 Programming steps:
210 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
211 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
212 3. Program LPC Memory Range in DMI
213
214 @param[in] Address Address for memory base address.
215
216 @retval EFI_SUCCESS Successfully completed.
217 @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
218 @retval EFI_OUT_OF_RESOURCES No more generic range available.
219 @retval EFI_UNSUPPORTED DMIC.SRL is set.
220 **/
221 EFI_STATUS
222 PchLpcMemRangeSet (
223 IN UINT32 Address
224 );
225
226 /**
227 Set PCH eSPI CS1# memory range decoding.
228 This cycle decoding is required to be set on DMI side
229 Programming steps:
230 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory decoding first before changing base address.
231 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
232 3. Program eSPI Memory Range in DMI
233
234 @param[in] Address Address for memory for decoding.
235
236 @retval EFI_SUCCESS Successfully completed.
237 @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
238 @retval EFI_UNSUPPORTED eSPI secondary target not supported
239 **/
240 EFI_STATUS
241 PchEspiCs1MemRangeSet (
242 IN UINT32 Address
243 );
244
245 /**
246 Get PCH LPC/eSPI memory range decoding address.
247
248 @param[out] Address Address of LPC/eSPI memory decoding base address.
249
250 @retval EFI_SUCCESS Successfully completed.
251 @retval EFI_INVALID_PARAMETER Invalid base address passed.
252 **/
253 EFI_STATUS
254 PchLpcMemRangeGet (
255 OUT UINT32 *Address
256 );
257
258 /**
259 Get PCH eSPI CS1# memory range decoding address.
260
261 @param[out] Address Address of eSPI CS1# memory decoding base address.
262
263 @retval EFI_SUCCESS Successfully completed.
264 @retval EFI_INVALID_PARAMETER Invalid base address passed.
265 @retval EFI_UNSUPPORTED eSPI secondary target not supported
266 **/
267 EFI_STATUS
268 PchEspiCs1MemRangeGet (
269 OUT UINT32 *Address
270 );
271
272 /**
273 Set PCH BIOS range deocding.
274 This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
275 Please check EDS for detail of BiosDecodeEnable bit definition.
276 bit 15: F8-FF Enable
277 bit 14: F0-F8 Enable
278 bit 13: E8-EF Enable
279 bit 12: E0-E8 Enable
280 bit 11: D8-DF Enable
281 bit 10: D0-D7 Enable
282 bit 9: C8-CF Enable
283 bit 8: C0-C7 Enable
284 bit 7: Legacy F Segment Enable
285 bit 6: Legacy E Segment Enable
286 bit 5: Reserved
287 bit 4: Reserved
288 bit 3: 70-7F Enable
289 bit 2: 60-6F Enable
290 bit 1: 50-5F Enable
291 bit 0: 40-4F Enable
292 This cycle decoding is allowed to set when DMIC.SRL is 0.
293 Programming steps:
294 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
295 if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
296 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
297
298 @param[in] BiosDecodeEnable Bios decode enable setting.
299
300 @retval EFI_SUCCESS Successfully completed.
301 **/
302 EFI_STATUS
303 PchBiosDecodeEnableSet (
304 IN UINT16 BiosDecodeEnable
305 );
306
307 /**
308 Set PCH LPC IO decode ranges.
309 Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
310 Please check EDS for detail of Lpc IO decode ranges bit definition.
311 Bit 12: FDD range
312 Bit 9:8: LPT range
313 Bit 6:4: ComB range
314 Bit 2:0: ComA range
315
316 @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
317
318 @retval EFI_SUCCESS Successfully completed.
319 @retval EFI_UNSUPPORTED DMIC.SRL is set.
320 **/
321 EFI_STATUS
322 PchLpcIoDecodeRangesSet (
323 IN UINT16 LpcIoDecodeRanges
324 );
325
326 /**
327 Set PCH LPC and eSPI CS0# IO enable decoding.
328 Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h.
329 Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
330 in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
331 Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
332
333 @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
334
335 @retval EFI_SUCCESS Successfully completed.
336 @retval EFI_UNSUPPORTED DMIC.SRL is set.
337 **/
338 EFI_STATUS
339 PchLpcIoEnableDecodingSet (
340 IN UINT16 LpcIoEnableDecoding
341 );
342
343 /**
344 Set PCH eSPI CS1# IO enable decoding.
345 Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h (eSPI CS1#).
346 Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
347 in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive agent for handling.
348 Please check EDS for detail of eSPI IO decode ranges bit definition.
349
350 @param[in] IoEnableDecoding eSPI IO enable decoding bit settings.
351
352 @retval EFI_SUCCESS Successfully completed.
353 @retval EFI_UNSUPPORTED DMI configuration is locked
354 **/
355 EFI_STATUS
356 PchEspiCs1IoEnableDecodingSet (
357 IN UINT16 IoEnableDecoding
358 );
359
360 /**
361 AND then OR PCH LPC and eSPI CS0# IO enable decoding.
362 Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h.
363 Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
364 in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
365
366 @param[in] AndValue LPC IO enable decoding "AND" value.
367 @param[in] OrValue LPC IO enable decoding "OR" value.
368
369 @retval EFI_SUCCESS Successfully completed.
370 @retval EFI_UNSUPPORTED DMIC.SRL is set.
371 **/
372 EFI_STATUS
373 PchLpcIoEnableDecodingAndThenOr (
374 IN UINT16 AndValue,
375 IN UINT16 OrValue
376 );
377
378 /**
379 Set PCH IO port 80h cycle decoding to PCIE root port.
380 System BIOS is likely to do this very soon after reset before PCI bus enumeration, it must ensure that
381 the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than the IO Limit field (PCIe:1Ch[15:12])
382 before setting the IOSE bit. Otherwise the bridge will positively decode IO range 000h - FFFh by its default
383 IO range values.
384 This cycle decoding is allowed to set when DMIC.SRL is 0.
385 Programming steps:
386 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID of RP.
387 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte write on GCS+1 and leave the BILD bit which is RWO.
388 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cycles to PCIe bus for subtractive decoding.
389
390 @param[in] RpPhyNumber PCIE root port physical number.
391
392 @retval EFI_SUCCESS Successfully completed.
393 **/
394 EFI_STATUS
395 PchIoPort80DecodeSet (
396 IN UINTN RpPhyNumber
397 );
398
399 /**
400 Get IO APIC regsiters base address.
401
402 @param[out] IoApicBase Buffer of IO APIC regsiter address
403
404 @retval EFI_SUCCESS Successfully completed.
405 **/
406 EFI_STATUS
407 PchIoApicBaseGet (
408 OUT UINT32 *IoApicBase
409 );
410
411 /**
412 Get HPET base address.
413 This function will be unavailable after P2SB is hidden by PSF.
414
415 @param[out] HpetBase Buffer of HPET base address
416
417 @retval EFI_SUCCESS Successfully completed.
418 @retval EFI_INVALID_PARAMETER Invalid offset passed.
419 **/
420 EFI_STATUS
421 PchHpetBaseGet (
422 OUT UINT32 *HpetBase
423 );
424
425 #endif // _PCH_CYCLE_DECODING_LIB_H_
PchLpcGenIoRangeSet
EFI_STATUS PchLpcGenIoRangeSet(IN UINT16 Address, IN UINTN Length)
Set PCH LPC/eSPI generic IO range.
PchEspiCs1MemRangeSet
EFI_STATUS PchEspiCs1MemRangeSet(IN UINT32 Address)
Set PCH eSPI CS1# memory range decoding.
PchEspiCs1IoEnableDecodingSet
EFI_STATUS PchEspiCs1IoEnableDecodingSet(IN UINT16 IoEnableDecoding)
Set PCH eSPI CS1# IO enable decoding.
PchLpcGenIoRangeGet
EFI_STATUS PchLpcGenIoRangeGet(OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList)
Get PCH LPC/eSPI generic IO range list.
PchEspiCs1GenIoRangeSet
EFI_STATUS PchEspiCs1GenIoRangeSet(IN UINT16 Address, IN UINTN Length)
Set PCH eSPI CS1# generic IO range decoding.
PchLpcIoEnableDecodingAndThenOr
EFI_STATUS PchLpcIoEnableDecodingAndThenOr(IN UINT16 AndValue, IN UINT16 OrValue)
AND then OR PCH LPC and eSPI CS0# IO enable decoding.
PCH_LPC_GEN_IO_RANGE
structure of LPC general IO range register It contains base address, address mask,...
Definition: PchCycleDecodingLib.h:74
PCH_LPC_GEN_IO_RANGE_LIST
structure of LPC general IO range register list It lists all LPC general IO ran registers supported b...
Definition: PchCycleDecodingLib.h:87
PchEspiCs1GenIoRangeGet
EFI_STATUS PchEspiCs1GenIoRangeGet(OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList)
Get PCH eSPI CS1# generic IO range list.
PchIoPort80DecodeSet
EFI_STATUS PchIoPort80DecodeSet(IN UINTN RpPhyNumber)
Set PCH IO port 80h cycle decoding to PCIE root port.
PchHpetBaseGet
EFI_STATUS PchHpetBaseGet(OUT UINT32 *HpetBase)
Get HPET base address.
PchLpcIoDecodeRangesSet
EFI_STATUS PchLpcIoDecodeRangesSet(IN UINT16 LpcIoDecodeRanges)
Set PCH LPC IO decode ranges.
PchTcoBaseSet
EFI_STATUS PchTcoBaseSet(IN UINT16 Address)
Set PCH TCO base address.
PchLpcIoEnableDecodingSet
EFI_STATUS PchLpcIoEnableDecodingSet(IN UINT16 LpcIoEnableDecoding)
Set PCH LPC and eSPI CS0# IO enable decoding.
PchTcoBaseGet
EFI_STATUS PchTcoBaseGet(OUT UINT16 *Address)
Get PCH TCO base address.
PchLpcGenIoRangeClear
EFI_STATUS PchLpcGenIoRangeClear(IN UINT16 Address, IN UINTN Length)
Clear IBL eSPI generic IO range.
PchEspiCs1MemRangeGet
EFI_STATUS PchEspiCs1MemRangeGet(OUT UINT32 *Address)
Get PCH eSPI CS1# memory range decoding address.
PchIoApicBaseGet
EFI_STATUS PchIoApicBaseGet(OUT UINT32 *IoApicBase)
Get IO APIC regsiters base address.
PchLpcMemRangeSet
EFI_STATUS PchLpcMemRangeSet(IN UINT32 Address)
Set PCH LPC/eSPI memory range decoding.
PchLpcMemRangeGet
EFI_STATUS PchLpcMemRangeGet(OUT UINT32 *Address)
Get PCH LPC/eSPI memory range decoding address.
PchBiosDecodeEnableSet
EFI_STATUS PchBiosDecodeEnableSet(IN UINT16 BiosDecodeEnable)
Set PCH BIOS range deocding.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi14Regs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchDmi14Regs.h File Reference

Register names for PCH DMI SIP14. More...

Go to the source code of this file.

Macros

#define | R_PCH_DMI14_PCR_V0CTL 0x2014
Virtual channel 0 resource control.
#define | R_PCH_DMI14_PCR_V0STS 0x201A
Virtual channel 0 status.
#define | R_PCH_DMI14_PCR_V1CTL 0x2020
Virtual channel 1 resource control.
#define | R_PCH_DMI14_PCR_V1STS 0x2026
Virtual channel 1 status.
#define | R_PCH_DMI14_PCR_VMCTL 0x2040
ME Virtual Channel (VCm) resource control.
#define | R_PCH_DMI14_PCR_VMSTS 0x2046
ME Virtual Channel Resource Status.
#define | R_PCH_DMI14_PCR_UEM 0x2088
Uncorrectable Error Mask.
#define | R_PCH_DMI14_PCR_REC 0x20AC
Root Error Command.
#define | R_PCH_DMI14_PCR_LCTL 0x21A8
Link Control.
#define | R_PCH_DMI14_PCR_DMIC 0x2234
DMI Control.
#define | B_PCH_DMI14_PCR_DMIC_SRL BIT31
Secured register lock.
#define | B_PCH_DMI14_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
DMI Clock Gate Enable.
#define | R_PCH_DMI14_PCR_DMIHWAWC 0x2238
DMI HW Autonomus Width Control.
#define | R_PCH_DMI14_PCR_IPCS 0x223C
IOSF Primary Control And Status.
#define | B_PCH_DMI14_PCR_IPCS_PSS BIT15
IOSF Primary SAI Select.
#define | R_PCH_DMI14_PCR_IOSFSBCS 0x223E
IOSF Sideband Control and Status.
#define | R_PCH_DMI14_PCR_G3L0SCTL 0x2478
GEN3 L0s Control.
#define | R_PCH_OPDMI14_PCR_LCTL 0x2600
Link Control.
#define | R_PCH_OPDMI14_PCR_STC 0x260C
Sideband Timing Control.
#define | R_PCH_OPDMI14_PCR_LPMC 0x2614
Link Power Management Control.
#define | R_PCH_OPDMI14_PCR_LCFG 0x2618
Link Configuration.

Detailed Description

Register names for PCH DMI SIP14.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmi14Regs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi14Regs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
PchDmi14Regs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH DMI SIP14
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2018 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_DMI14_REGS_H_
65 #define _PCH_DMI14_REGS_H_
66
67 //
68 // DMI Chipset Configuration Registers (PID:DMI)
69 //
70
71 //
72 // VC Configuration (Common)
73 //
74 #define R_PCH_DMI14_PCR_V0CTL 0x2014 ///< Virtual channel 0 resource control
75 #define R_PCH_DMI14_PCR_V0STS 0x201A ///< Virtual channel 0 status
76 #define R_PCH_DMI14_PCR_V1CTL 0x2020 ///< Virtual channel 1 resource control
77 #define R_PCH_DMI14_PCR_V1STS 0x2026 ///< Virtual channel 1 status
78 #define R_PCH_DMI14_PCR_VMCTL 0x2040 ///< ME Virtual Channel (VCm) resource control
79 #define R_PCH_DMI14_PCR_VMSTS 0x2046 ///< ME Virtual Channel Resource Status
80 #define R_PCH_DMI14_PCR_UEM 0x2088 ///< Uncorrectable Error Mask
81 #define R_PCH_DMI14_PCR_REC 0x20AC ///< Root Error Command
82
83 //
84 // Internal Link Configuration (DMI Only)
85 //
86 #define R_PCH_DMI14_PCR_LCTL 0x21A8 ///< Link Control
87 #define B_PCH_DMI14_PCR_LCTL_ES BIT7
88
89 //
90 // DMI Control
91 //
92 #define R_PCH_DMI14_PCR_DMIC 0x2234 ///< DMI Control
93 #define B_PCH_DMI14_PCR_DMIC_SRL BIT31 ///< Secured register lock
94 #define B_PCH_DMI14_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< DMI Clock Gate Enable
95 #define R_PCH_DMI14_PCR_DMIHWAWC 0x2238 ///< DMI HW Autonomus Width Control
96 #define R_PCH_DMI14_PCR_IPCS 0x223C ///< IOSF Primary Control And Status
97 #define B_PCH_DMI14_PCR_IPCS_PSS BIT15 ///< IOSF Primary SAI Select
98 #define R_PCH_DMI14_PCR_IOSFSBCS 0x223E ///< IOSF Sideband Control and Status
99
100 #define R_PCH_DMI14_PCR_2300 0x2300
101 #define R_PCH_DMI14_PCR_2304 0x2304
102 #define R_PCH_DMI14_PCR_2310 0x2310
103 #define R_PCH_DMI14_PCR_2314 0x2314
104 #define R_PCH_DMI14_PCR_2320 0x2320
105 #define R_PCH_DMI14_PCR_232C 0x232C
106 #define R_PCH_DMI14_PCR_2334 0x2334
107 #define R_PCH_DMI14_PCR_2340 0x2340
108 #define R_PCH_DMI14_PCR_2344 0x2344
109 #define R_PCH_DMI14_PCR_2348 0x2348
110 #define R_PCH_DMI14_PCR_234C 0x234C
111
112 #define R_PCH_DMI14_PCR_2400 0x2400
113 //
114 // Port Configuration Extension(DMI Only)
115 //
116 #define R_PCH_DMI14_PCR_G3L0SCTL 0x2478 ///< GEN3 L0s Control
117
118 //
119 // OP-DMI Specific Registers (OP-DMI Only)
120 //
121 #define R_PCH_OPDMI14_PCR_LCTL 0x2600 ///< Link Control
122 #define R_PCH_OPDMI14_PCR_STC 0x260C ///< Sideband Timing Control
123 #define R_PCH_OPDMI14_PCR_LPMC 0x2614 ///< Link Power Management Control
124 #define R_PCH_OPDMI14_PCR_LCFG 0x2618 ///< Link Configuration
125
126 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi15Regs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchDmi15Regs.h File Reference

Register names for PCH DMI and OP-DMI. More...

Go to the source code of this file.

Macros

#define | R_PCH_DMI15_PCR_LCAP 0x204C
Link Capabilities.
#define | R_PCH_DMI15_PCR_LCTL 0x2050
Link Control.
#define | B_PCH_DMI15_PCR_LCTL_ES BIT7
Extended Synch.
#define | B_PCH_DMI15_PCR_LCTL_ASPM (BIT1 | BIT0)
Active State Link PM Control.
#define | V_PCH_DMI15_PCR_LCTL_ASPM_DIS 0x0
ASPM Disabled.
#define | V_PCH_DMI15_PCR_LCTL_ASPM_L0S 0x1
L0s Entry Enabled.
#define | V_PCH_DMI15_PCR_LCTL_ASPM_L1 0x2
L1 Entry Enabled.
#define | V_PCH_DMI15_PCR_LCTL_ASPM_L0SL1 0x3
L0s and L1 Entry Enabled.
#define | B_PCH_DMI15_PCR_LCTL_RL BIT5
Link Retrain.
#define | R_PCH_DMI15_PCR_LSTS 0x2052
Link Status.
#define | R_PCH_DMI15_PCR_LCTL2 0x2070
Link Control 2.
#define | B_PCH_DMI15_PCR_LCTL2_TLS 0xF
Target Link Speed.
#define | R_PCH_DMI15_PCR_CCFG 0x20D0
Channel Configuration.
#define | B_PCH_DMI15_PCR_CCFG_DCGEISMA BIT15
Dynamic Clock Gating Enable on ISM Active.
#define | R_PCH_DMI15_PCR_MPC2 0x20D4
Miscellaneous Port Configuration 2.
#define | B_PCH_DMI15_PCR_MPC2_PLLWAIT (BIT26 | BIT25 | BIT24)
PLL Wait.
#define | N_PCH_DMI15_PCR_MPC2_PLLWAIT 24
PLL Wait.
#define | V_PCH_DMI15_PCR_MPC2_PLLWAIT_0US 0x0
PLL Wait = 0us.
#define | V_PCH_DMI15_PCR_MPC2_PLLWAIT_5US 0x1
PLL Wait = 5us.
#define | B_PCH_DMI15_PCR_MPC2_RUD BIT23
Recovery Upconfiguration Disable.
#define | B_PCH_DMI15_PCR_MPC2_GEN2PLLC BIT21
GEN2 PLL Coupling.
#define | B_PCH_DMI15_PCR_MPC2_GEN3PLLC BIT20
GEN3 PLL Coupling.
#define | B_PCH_DMI15_PCR_MPC2_ORCE (BIT15 | BIT14)
Offset Re-Calibration Enable.
#define | N_PCH_DMI15_PCR_MPC2_ORCE 14
Offset Re-Calibration Enable.
#define | V_PCH_DMI15_PCR_MPC2_ORCE_EN_GEN2_GEN3 1
Enable offset re-calibration for Gen 2 and Gen 3 data rate only.
#define | B_PCH_DMI15_PCR_MPC2_TLPF BIT9
Transaction Layer Packet Fast Transmit Mode.
#define | B_PCH_DMI15_PCR_MPC2_CAM BIT8
DMI Credit Allocated Update Mode.
#define | R_PCH_DMI15_PCR_MPC 0x20D8
Miscellaneous Port Configuration.
#define | B_PCH_DMI15_PCR_MPC_SRL BIT23
Secured register lock.
#define | B_PCH_DMI15_PCR_MPC_FCP (BIT6 | BIT5 | BIT4)
Flow Control Update Policy.
#define | R_PCH_DMI15_PCR_RPDCGEN 0x20E1
Root Port Dynamic Clock Gate Enable.
#define | B_PCH_DMI15_PCR_PTOCGE BIT6
Partition/Trunk Oscillator Clock Gate Enable.
#define | B_PCH_DMI15_PCR_LCLKREQEN BIT5
Link CLKREQ Enable.
#define | B_PCH_DMI15_PCR_BBCLKREQEN BIT4
Backbone CLKREQ Enable.
#define | B_PCH_DMI15_PCR_SRDBCGEN BIT2
Shared Resource Dynamic Backbone Clock Gate Enable.
#define | B_PCH_DMI15_PCR_RPDLCGEN BIT1
Root Port Dynamic Link Clock Gate Enable.
#define | B_PCH_DMI15_PCR_RPDBCGEN BIT0
Root Port Dynamic Backbone Clock Gate Enable.
#define | R_PCH_DMI15_PCR_RPPGEN 0x20E2
Root Port Power Gating Enable.
#define | B_PCH_DMI15_PCR_RPPGEN_SEOSCGE BIT4
Sideband Endpoint Oscillator/Side Clock Gating Enable.
#define | R_PCH_DMI15_PCR_PWRCTL 0x20E8
Power Control.
#define | B_PCH_DMI15_PCR_PWRCTL_DBUPI BIT15
De-skew Buffer Unload Pointer Increment.
#define | B_PCH_DMI15_PCR_PWRCTL_RPSEWL (BIT3 | BIT2)
Root Port Squelch Exit Wait Latency.
#define | N_PCH_DMI15_PCR_PWRCTL_RPSEWL 2
Root Port Squelch Exit Wait Latency.
#define | V_PCH_DMI15_PCR_PWRCTL_RPSEWL_120NS 0x1
Root Port Squelch Exit Wait Latency = 120 ns.
#define | R_PCH_DMI15_PCR_PHYCTL2 0x20F5
Physical Layer And AFE Control 2.
#define | B_PCH_DMI15_PCR_PHYCTL2_TDFT (BIT7 | BIT6)
Transmit Datapath Flush Timer.
#define | B_PCH_DMI15_PCR_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
Transmit Configuration Change Wait Time.
#define | B_PCH_DMI15_PCR_PHYCTL2_PXPG3PLLOFFEN BIT1
PCI Express GEN3 PLL Off Enable.
#define | B_PCH_DMI15_PCR_PHYCTL2_PXPG2PLLOFFEN BIT0
PCI Express GEN2 PLL Off Enable.
#define | R_PCH_DMI15_PCR_PHYCTL3 0x20F6
Physical Layer And AFE Control 3.
#define | B_PCH_DMI15_PCR_PHYCTL3_SQDIROVREN BIT2
Squelch Direction Override Enable.
#define | B_PCH_DMI15_PCR_PHYCTL3_SQDIRCTRL BIT1
Squelch Direction.
#define | R_PCH_DMI15_PCR_IOSFSBCS 0x20F7
IOSF Sideband Control And Status.
#define | B_PCH_DMI15_PCR_IOSFSBCS_SCPTCGE BIT6
Side Clock Partition/Trunk Clock Gating Enable.
#define | B_PCH_DMI15_PCR_IOSFSBCS_SIID (BIT3 | BIT2)
IOSF Sideband Interface Idle Counter.
#define | R_PCH_DMI15_PCR_UEM 0x2108
Uncorrectable Error Mask.
#define | B_PCH_DMI15_PCR_UEM_URE BIT20
Unsupported Request Error Mask.
#define | B_PCH_DMI15_PCR_UEM_CM BIT15
Completer Abort Mask.
#define | B_PCH_DMI15_PCR_UEM_PT BIT12
Poisoned TLP Mask.
#define | R_PCH_DMI15_PCR_CEM 0x2114
Correctable Error Mask.
#define | R_PCH_DMI15_PCR_V0CTL 0x2284
Virtual channel 0 resource control.
#define | R_PCH_DMI15_PCR_V0STS 0x228A
Virtual channel 0 status.
#define | R_PCH_DMI15_PCR_V1CTL 0x2290
Virtual channel 1 resource control.
#define | R_PCH_DMI15_PCR_V1STS 0x2296
Virtual channel 1 status.
#define | R_PCH_DMI15_PCR_VMCTL 0x22B0
ME Virtual Channel (VCm) resource control.
#define | R_PCH_DMI15_PCR_VMSTS 0x22B6
ME Virtual Channel Resource Status.
#define | R_PCH_DMI15_PCR_PCIENFTS 0x2314
PCI Express NFTS.
#define | B_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS 0xFF0000
Gen2 Common Clock N_FTS.
#define | N_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS 16
Gen2 Common Clock N_FTS.
#define | B_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS 0xFF
Gen1 Common Clock N_FTS.
#define | N_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS 0
Gen1 Common Clock N_FTS.
#define | R_PCH_DMI15_PCR_PCIEL0SC 0x2318
PCI Express L0s Control.
#define | B_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL 0xFF000000
Gen2 Active State L0s Preparation Latency.
#define | N_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL 24
Gen2 Active State L0s Preparation Latency.
#define | B_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL 0x00FF0000
Gen1 Active State L0s Preparation Latency.
#define | N_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL 16
Gen1 Active State L0s Preparation Latency.
#define | R_PCH_DMI15_PCR_PCIECFG2 0x2320
PCI Express Configuration 2.
#define | B_PCH_DMI15_PCR_PCIECFG2_LBWSSTE BIT30
Low Bandwidth Squelch Settling Timer Enable.
#define | B_PCH_DMI15_PCR_PCIECFG2_CROAOV BIT24
Completion Relaxed Ordering Attribute Override Value.
#define | B_PCH_DMI15_PCR_PCIECFG2_CROAOE BIT23
Completion Relaxed Ordering Attribute Override Enable.
#define | R_PCH_DMI15_PCR_PCIEDBG 0x2324
PCI Express Debug And Configuration.
#define | B_PCH_DMI15_PCR_PCIEDBG_SPCE BIT5
Squelch Propagation Control Enable.
#define | R_PCH_DMI15_PCR_PHYCTL4 0x2408
Physical Layer And AFE Control 4.
#define | B_PCH_DMI15_PCR_PHYCTL4_SQDIS BIT27
Squelch Disable.
#define | R_PCH_DMI15_PCR_PCIEPMECTL 0x2420
PCIe PM Extension Control.
#define | B_PCH_DMI15_PCR_PCIEPMECTL_DLSULPPGE BIT30
Disabled, Detect and L23_Rdy State PHY Lane Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL_DLSULDLSD BIT29
Disabled, Detect, L23_Rdy State,Un-Configured Lane and Down-Configured Lane Squelch Disable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL_IPIEP BIT21
IP-Inaccessible Entry Policy.
#define | B_PCH_DMI15_PCR_PCIEPMECTL_IPACPE BIT20
IP-Accessible Context Propagation Enable.
#define | R_PCH_DMI15_PCR_PCIEPMECTL2 0x2424
PCIe PM Extension Control 2.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_PHYCLPGE BIT11
PHY Common Lane Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_L1SPHYDLPGE BIT9
L1 State PHY Data Lane Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_FDCPGE BIT8
Function Disable Controller Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_DETSCPGE BIT7
Detect State Controller Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_L23RDYSCPGE BIT6
L23_Rdy State Controller Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_DISSCPGE BIT5
L1 Disabled State Controller Power Gating Enable.
#define | B_PCH_DMI15_PCR_PCIEPMECTL2_L1SCPGE BIT4
L1 State Controller Power Gating Enable.
#define | R_PCH_DMI15_PCR_PCE 0x2428
Power Control Enable.
#define | B_PCH_DMI15_PCR_PCE_HAE BIT5
Hardware Autonomous Enable.
#define | B_PCH_DMI15_PCR_PCE_SE BIT3
Sleep Enable.
#define | B_PCH_DMI15_PCR_PCE_PMCRE BIT0
PMC Request Enable.
#define | R_PCH_DMI15_PCR_EQCFG1 0x2450
Equalization Configuration 1.
#define | B_PCH_DMI15_PCR_EQCFG1_RTLEPCEB BIT16
Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass.
#define | B_PCH_DMI15_PCR_EQCFG1_RTPCOE BIT15
Remote Transmitter Preset Coefficient Override Enable.
#define | R_PCH_DMI15_PCR_RTPCL1 0x2454
Remote Transmitter Preset Coefficient List 1.
#define | R_PCH_DMI15_PCR_RTPCL2 0x2458
Remote Transmitter Preset Coefficient List 2.
#define | R_PCH_DMI15_PCR_LTCO1 0x2470
Local Transmitter Coefficient Override 1.
#define | R_PCH_DMI15_PCR_LTCO2 0x2474
Local Transmitter Coefficient Override 2.
#define | B_PCH_DMI15_PCR_L1357TCOE BIT25
Lane 1/3 Transmitter Coefficient Override Enable.
#define | B_PCH_DMI15_PCR_L0246TCOE BIT24
Lane 0/2 Transmitter Coefficient Override Enable.
#define | B_PCH_DMI15_PCR_L1357TPOSTCO 0x00FC0000
Lane 1/3 Transmitter Post-Cursor Coefficient Override mask.
#define | N_PCH_DMI15_PCR_L1357TPOSTCO 18
Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset.
#define | B_PCH_DMI15_PCR_L1357TPRECO 0x0003F000
Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask.
#define | N_PCH_DMI15_PCR_L1357TPRECO 12
Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset.
#define | B_PCH_DMI15_PCR_L0246TPOSTCO 0x00000FC0
Lane 0/2 Transmitter Post-Cursor Coefficient Override mask.
#define | N_PCH_DMI15_PCR_L0246TPOSTCO 6
Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset.
#define | B_PCH_DMI15_PCR_L0246TPRECO 0x0000003F
Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask.
#define | N_PCH_DMI15_PCR_L0246TPRECO 0
Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset.
#define | R_PCH_DMI15_PCR_G3L0SCTL 0x2478
GEN3 L0s Control.
#define | B_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL 0xFF000000
Gen3 Active State L0s Preparation Latency.
#define | N_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL 24
Gen3 Active State L0s Preparation Latency.
#define | B_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS 0xFF
Gen3 Common Clock N_FTS.
#define | N_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS 0
Gen3 Common Clock N_FTS.
#define | R_PCH_DMI15_PCR_UPHWAWC 0x249C
Upstream Port HW Autonomous Width Control.
#define | B_PCH_DMI15_PCR_UPHWAWC_TS3TW (BIT15 | BIT14 | BIT13)
Thermal Sensor 3 Target Width.
#define | N_PCH_DMI15_PCR_UPHWAWC_TS3TW 13
Thermal Sensor 3 Target Width.
#define | B_PCH_DMI15_PCR_UPHWAWC_TS2TW (BIT12 | BIT11 | BIT10)
Thermal Sensor 2 Target Width.
#define | N_PCH_DMI15_PCR_UPHWAWC_TS2TW 10
Thermal Sensor 2 Target Width.
#define | B_PCH_DMI15_PCR_UPHWAWC_TS1TW (BIT9 | BIT8 | BIT7)
Thermal Sensor 1 Target Width.
#define | N_PCH_DMI15_PCR_UPHWAWC_TS1TW 7
Thermal Sensor 1 Target Width.
#define | B_PCH_DMI15_PCR_UPHWAWC_TS0TW (BIT6 | BIT5 | BIT4)
Thermal Sensor 0 Target Width.
#define | N_PCH_DMI15_PCR_UPHWAWC_TS0TW 4
Thermal Sensor 0 Target Width.
#define | B_PCH_DMI15_PCR_UPHWAWC_TSAWEN BIT0
Thermal Sensor Autonomous Width Enable.
#define | R_PCH_DMI15_PCR_CTRL1 0x24A0
Control 1.
#define | B_PCH_DMI15_PCR_CTRL1_MRSCDIS BIT21
MEUMA Root Space Check Disable.
#define | B_PCH_DMI15_PCR_CTRL1_L0SPFCUF (BIT16 | BIT15)
L0s Periodic Flow Control Update Frequency.
#define | B_PCH_DMI15_PCR_CTRL1_L1RC BIT12
DMI L1 Root Port Control.
#define | B_PCH_DMI15_PCR_CTRL1_L1PL (BIT11 | BIT10 | BIT9)
DMI L1 Preparation Latency.
#define | N_PCH_DMI15_PCR_CTRL1_L1PL 9
DMI L1 Preparation Latency.
#define | V_PCH_DMI15_PCR_CTRL1_L1PL_8US 0x4
DMI L1 Preparation Latency.
#define | B_PCH_DMI15_PCR_CTRL1_TCUAPF BIT6
Transaction Credit Update Arbitration Performance Fix.
#define | B_PCH_DMI15_PCR_CTRL1_DLDHB BIT4
DMI Link Down Hang Bypass.
#define | B_PCH_DMI15_PCR_CTRL1_PSS BIT3
IOSF Primary SAI Select.
#define | B_PCH_DMI15_PCR_CTRL1_UTPB BIT0
Unsupported Transaction Policy Bit.
#define | R_PCH_DMI15_PCR_CTRL2 0x24A4
Control 2.
#define | B_PCH_DMI15_PCR_CTRL2_DLDRSP BIT13
DMI Link Data Rate Sustain Policy.
#define | B_PCH_DMI15_PCR_CTRL2_CPGEXLCWDIS BIT5
CPG Exit Link Clock Wake Disable.
#define | R_PCH_DMI15_PCR_L0P0P1PCM 0x2500
Lane 0 P0 And P1 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P1P2P3PCM 0x2504
Lane 0 P1, P2 And P3 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P3P4PCM 0x2508
Lane 0 P3 And P4 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P5P6PCM 0x250C
Lane 0 P5 And P6 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P6P7P8PCM 0x2510
Lane 0 P6, P7 And P8 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P8P9PCM 0x2514
Lane 0 P8 And P9 Preset-Coefficient Mapping.
#define | R_PCH_DMI15_PCR_L0P10PCM 0x2518
Lane 0 P10 Preset-Coefficient Mapping ()
#define | R_PCH_DMI15_PCR_L0LFFS 0x251C
Lane 0 LF And FS.
#define | R_PCH_DMI15_PCR_LTCO3 0x2598
Local Transmitter Coefficient Override 3.
#define | R_PCH_DMI15_PCR_LTCO4 0x259C
Local Transmitter Coefficient Override 4.
#define | R_PCH_DMI15_PCR_CWBCTL 0x2820
Central Write Buffer Control.
#define | B_PCH_DMI15_PCR_CWBCTL_CWBE BIT0
Central Write Buffer Enable.
#define | R_PCH_DMI15_PCR_EEPPES 0x2900
DMI End-to-End Parity Protection Error Status.
#define | B_PCH_DMI15_PCR_PSSSGE BIT31
End-to-End Parity Error Stop and Scream SERR generation Enable.
#define | R_PCH_DMI15_PCR_L01EC 0x2A3C
Lane 0 and Lane 1 Equalization Control.
#define | R_PCH_DMI15_PCR_L23EC 0x2A40
Lane 2 and Lane 3 Equalization Control.
#define | R_PCH_DMI15_PCR_L45EC 0x2A44
Lane 4 and Lane 5 Equalization Control.
#define | R_PCH_DMI15_PCR_L67EC 0x2A48
Lane 6 and Lane 7 Equalization Control.
#define | B_PCH_DMI15_PCR_UPL1357TP 0x0F000000
Upstream Port Lane 1/3/5/7 Transmitter Preset mask.
#define | N_PCH_DMI15_PCR_UPL1357TP 24
Upstream Port Lane 1/3/5/7 Transmitter Preset value offset.
#define | B_PCH_DMI15_PCR_UPL0246TP 0x00000F00
Upstream Port Lane 0/2/4/6 Transmitter Preset mask.
#define | N_PCH_DMI15_PCR_UPL0246TP 8
Upstream Port Lane 0/2/4/6 Transmitter Preset value offset.
#define | V_PCH_DMI15_PCR_UPL0TP 7
Upstream Port Lane 0 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL1TP 7
Upstream Port Lane 1 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL2TP 7
Upstream Port Lane 2 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL3TP 7
Upstream Port Lane 3 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL4TP 7
Upstream Port Lane 4 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL5TP 7
Upstream Port Lane 5 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL6TP 7
Upstream Port Lane 6 Transmitter Preset value.
#define | V_PCH_DMI15_PCR_UPL7TP 7
Upstream Port Lane 7 Transmitter Preset value.

Detailed Description

Register names for PCH DMI and OP-DMI.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmi15Regs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi15Regs.h Source File

  • Intel
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  • Register
PchDmi15Regs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH DMI and OP-DMI
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2016 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_DMI15_REGS_H_
65 #define _PCH_DMI15_REGS_H_
66
67 //
68 // DMI Chipset Configuration Registers (PID:DMI)
69 //
70 #define R_PCH_DMI15_PCR_LCAP 0x204C ///< Link Capabilities
71
72 #define R_PCH_DMI15_PCR_LCTL 0x2050 ///< Link Control
73 #define B_PCH_DMI15_PCR_LCTL_ES BIT7 ///< Extended Synch
74 #define B_PCH_DMI15_PCR_LCTL_ASPM (BIT1 | BIT0) ///< Active State Link PM Control
75 #define V_PCH_DMI15_PCR_LCTL_ASPM_DIS 0x0 ///< ASPM Disabled
76 #define V_PCH_DMI15_PCR_LCTL_ASPM_L0S 0x1 ///< L0s Entry Enabled
77 #define V_PCH_DMI15_PCR_LCTL_ASPM_L1 0x2 ///< L1 Entry Enabled
78 #define V_PCH_DMI15_PCR_LCTL_ASPM_L0SL1 0x3 ///< L0s and L1 Entry Enabled
79 #define B_PCH_DMI15_PCR_LCTL_RL BIT5 ///< Link Retrain
80
81 #define R_PCH_DMI15_PCR_LSTS 0x2052 ///< Link Status
82 #define B_PCH_DMI15_PCR_LSTS_LT BIT11
83
84 #define R_PCH_DMI15_PCR_LCTL2 0x2070 ///< Link Control 2
85 #define B_PCH_DMI15_PCR_LCTL2_TLS 0xF ///< Target Link Speed
86
87 #define R_PCH_DMI15_PCR_CCFG 0x20D0 ///< Channel Configuration
88 #define B_PCH_DMI15_PCR_CCFG_DCGEISMA BIT15 ///< Dynamic Clock Gating Enable on ISM Active
89
90 #define R_PCH_DMI15_PCR_MPC2 0x20D4 ///< Miscellaneous Port Configuration 2
91 #define B_PCH_DMI15_PCR_MPC2_PLLWAIT (BIT26 | BIT25 | BIT24) ///< PLL Wait
92 #define N_PCH_DMI15_PCR_MPC2_PLLWAIT 24 ///< PLL Wait
93 #define V_PCH_DMI15_PCR_MPC2_PLLWAIT_0US 0x0 ///< PLL Wait = 0us
94 #define V_PCH_DMI15_PCR_MPC2_PLLWAIT_5US 0x1 ///< PLL Wait = 5us
95 #define B_PCH_DMI15_PCR_MPC2_RUD BIT23 ///< Recovery Upconfiguration Disable
96 #define B_PCH_DMI15_PCR_MPC2_GEN2PLLC BIT21 ///< GEN2 PLL Coupling
97 #define B_PCH_DMI15_PCR_MPC2_GEN3PLLC BIT20 ///< GEN3 PLL Coupling
98 #define B_PCH_DMI15_PCR_MPC2_ORCE (BIT15 | BIT14) ///< Offset Re-Calibration Enable
99 #define N_PCH_DMI15_PCR_MPC2_ORCE 14 ///< Offset Re-Calibration Enable
100 #define V_PCH_DMI15_PCR_MPC2_ORCE_EN_GEN2_GEN3 1 ///< Enable offset re-calibration for Gen 2 and Gen 3 data rate only.
101 #define B_PCH_DMI15_PCR_MPC2_TLPF BIT9 ///< Transaction Layer Packet Fast Transmit Mode
102 #define B_PCH_DMI15_PCR_MPC2_CAM BIT8 ///< DMI Credit Allocated Update Mode
103
104
105 #define R_PCH_DMI15_PCR_MPC 0x20D8 ///< Miscellaneous Port Configuration
106 #define B_PCH_DMI15_PCR_MPC_SRL BIT23 ///< Secured register lock
107 #define B_PCH_DMI15_PCR_MPC_FCP (BIT6 | BIT5 | BIT4) ///< Flow Control Update Policy
108 #define N_PCH_DMI15_PCR_MPC_FCP 4
109 #define V_PCH_DMI15_PCR_MPC_FCP 0x4
110
111
112 #define R_PCH_DMI15_PCR_RPDCGEN 0x20E1 ///< Root Port Dynamic Clock Gate Enable
113 #define B_PCH_DMI15_PCR_PTOCGE BIT6 ///< Partition/Trunk Oscillator Clock Gate Enable
114 #define B_PCH_DMI15_PCR_LCLKREQEN BIT5 ///< Link CLKREQ Enable
115 #define B_PCH_DMI15_PCR_BBCLKREQEN BIT4 ///< Backbone CLKREQ Enable
116 #define B_PCH_DMI15_PCR_SRDBCGEN BIT2 ///< Shared Resource Dynamic Backbone Clock Gate Enable
117 #define B_PCH_DMI15_PCR_RPDLCGEN BIT1 ///< Root Port Dynamic Link Clock Gate Enable
118 #define B_PCH_DMI15_PCR_RPDBCGEN BIT0 ///< Root Port Dynamic Backbone Clock Gate Enable
119
120 #define R_PCH_DMI15_PCR_RPPGEN 0x20E2 ///< Root Port Power Gating Enable
121 #define B_PCH_DMI15_PCR_RPPGEN_PTOTOP BIT6
122 #define B_PCH_DMI15_PCR_RPPGEN_SEOSCGE BIT4 ///< Sideband Endpoint Oscillator/Side Clock Gating Enable
123
124 #define R_PCH_DMI15_PCR_PWRCTL 0x20E8 ///< Power Control
125 #define B_PCH_DMI15_PCR_PWRCTL_DBUPI BIT15 ///< De-skew Buffer Unload Pointer Increment
126 #define B_PCH_DMI15_PCR_PWRCTL_RPSEWL (BIT3 | BIT2) ///< Root Port Squelch Exit Wait Latency
127 #define N_PCH_DMI15_PCR_PWRCTL_RPSEWL 2 ///< Root Port Squelch Exit Wait Latency
128 #define V_PCH_DMI15_PCR_PWRCTL_RPSEWL_120NS 0x1 ///< Root Port Squelch Exit Wait Latency = 120 ns
129
130 #define R_PCH_DMI15_PCR_PHYCTL2 0x20F5 ///< Physical Layer And AFE Control 2
131 #define B_PCH_DMI15_PCR_PHYCTL2_TDFT (BIT7 | BIT6) ///< Transmit Datapath Flush Timer
132 #define B_PCH_DMI15_PCR_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) ///< Transmit Configuration Change Wait Time
133 #define B_PCH_DMI15_PCR_PHYCTL2_PXPG3PLLOFFEN BIT1 ///< PCI Express GEN3 PLL Off Enable
134 #define B_PCH_DMI15_PCR_PHYCTL2_PXPG2PLLOFFEN BIT0 ///< PCI Express GEN2 PLL Off Enable
135
136 #define R_PCH_DMI15_PCR_PHYCTL3 0x20F6 ///< Physical Layer And AFE Control 3
137 #define B_PCH_DMI15_PCR_PHYCTL3_SQDIROVREN BIT2 ///< Squelch Direction Override Enable
138 #define B_PCH_DMI15_PCR_PHYCTL3_SQDIRCTRL BIT1 ///< Squelch Direction
139
140 #define R_PCH_DMI15_PCR_IOSFSBCS 0x20F7 ///< IOSF Sideband Control And Status
141 #define B_PCH_DMI15_PCR_IOSFSBCS_SCPTCGE BIT6 ///< Side Clock Partition/Trunk Clock Gating Enable
142 #define B_PCH_DMI15_PCR_IOSFSBCS_SIID (BIT3 | BIT2) ///< IOSF Sideband Interface Idle Counter
143
144 #define R_PCH_DMI15_PCR_UEM 0x2108 ///< Uncorrectable Error Mask
145 #define B_PCH_DMI15_PCR_UEM_URE BIT20 ///< Unsupported Request Error Mask
146 #define B_PCH_DMI15_PCR_UEM_CM BIT15 ///< Completer Abort Mask
147 #define B_PCH_DMI15_PCR_UEM_PT BIT12 ///< Poisoned TLP Mask
148
149 #define R_PCH_DMI15_PCR_CEM 0x2114 ///< Correctable Error Mask
150
151 #define R_PCH_DMI15_PCR_V0CTL 0x2284 ///< Virtual channel 0 resource control
152 #define R_PCH_DMI15_PCR_V0STS 0x228A ///< Virtual channel 0 status
153
154 #define R_PCH_DMI15_PCR_V1CTL 0x2290 ///< Virtual channel 1 resource control
155 #define R_PCH_DMI15_PCR_V1STS 0x2296 ///< Virtual channel 1 status
156
157 #define R_PCH_DMI15_PCR_VMCTL 0x22B0 ///< ME Virtual Channel (VCm) resource control
158 #define R_PCH_DMI15_PCR_VMSTS 0x22B6 ///< ME Virtual Channel Resource Status
159
160 #define R_PCH_DMI15_PCR_PCIENFTS 0x2314 ///< PCI Express NFTS
161 #define B_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS 0xFF0000 ///< Gen2 Common Clock N_FTS
162 #define N_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS 16 ///< Gen2 Common Clock N_FTS
163 #define B_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS 0xFF ///< Gen1 Common Clock N_FTS
164 #define N_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS 0 ///< Gen1 Common Clock N_FTS
165
166 #define R_PCH_DMI15_PCR_PCIEL0SC 0x2318 ///< PCI Express L0s Control
167 #define B_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL 0xFF000000 ///< Gen2 Active State L0s Preparation Latency
168 #define N_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL 24 ///< Gen2 Active State L0s Preparation Latency
169 #define B_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL 0x00FF0000 ///< Gen1 Active State L0s Preparation Latency
170 #define N_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL 16 ///< Gen1 Active State L0s Preparation Latency
171
172 #define R_PCH_DMI15_PCR_PCIECFG2 0x2320 ///< PCI Express Configuration 2
173 #define B_PCH_DMI15_PCR_PCIECFG2_LBWSSTE BIT30 ///< Low Bandwidth Squelch Settling Timer Enable
174 #define B_PCH_DMI15_PCR_PCIECFG2_CROAOV BIT24 ///< Completion Relaxed Ordering Attribute Override Value
175 #define B_PCH_DMI15_PCR_PCIECFG2_CROAOE BIT23 ///< Completion Relaxed Ordering Attribute Override Enable
176
177 #define R_PCH_DMI15_PCR_PCIEDBG 0x2324 ///< PCI Express Debug And Configuration
178 #define B_PCH_DMI15_PCR_PCIEDBG_SPCE BIT5 ///< Squelch Propagation Control Enable
179
180 #define R_PCH_DMI15_PCR_PHYCTL4 0x2408 ///< Physical Layer And AFE Control 4
181 #define B_PCH_DMI15_PCR_PHYCTL4_SQDIS BIT27 ///< Squelch Disable
182
183 #define R_PCH_DMI15_PCR_PCIEPMECTL 0x2420 ///< PCIe PM Extension Control
184 #define B_PCH_DMI15_PCR_PCIEPMECTL_FDPPGE BIT31
185 #define B_PCH_DMI15_PCR_PCIEPMECTL_DLSULPPGE BIT30 ///< Disabled, Detect and L23_Rdy State PHY Lane Power Gating Enable
186 #define B_PCH_DMI15_PCR_PCIEPMECTL_DLSULDLSD BIT29 ///< Disabled, Detect, L23_Rdy State,Un-Configured Lane and Down-Configured Lane Squelch Disable
187 #define B_PCH_DMI15_PCR_PCIEPMECTL_IPIEP BIT21 ///< IP-Inaccessible Entry Policy
188 #define B_PCH_DMI15_PCR_PCIEPMECTL_IPACPE BIT20 ///< IP-Accessible Context Propagation Enable
189
190 #define R_PCH_DMI15_PCR_PCIEPMECTL2 0x2424 ///< PCIe PM Extension Control 2
191 #define B_PCH_DMI15_PCR_PCIEPMECTL2_PHYCLPGE BIT11 ///< PHY Common Lane Power Gating Enable
192 #define B_PCH_DMI15_PCR_PCIEPMECTL2_L1SPHYDLPGE BIT9 ///< L1 State PHY Data Lane Power Gating Enable
193 #define B_PCH_DMI15_PCR_PCIEPMECTL2_FDCPGE BIT8 ///< Function Disable Controller Power Gating Enable
194 #define B_PCH_DMI15_PCR_PCIEPMECTL2_DETSCPGE BIT7 ///< Detect State Controller Power Gating Enable
195 #define B_PCH_DMI15_PCR_PCIEPMECTL2_L23RDYSCPGE BIT6 ///< L23_Rdy State Controller Power Gating Enable
196 #define B_PCH_DMI15_PCR_PCIEPMECTL2_DISSCPGE BIT5 ///< L1 Disabled State Controller Power Gating Enable
197 #define B_PCH_DMI15_PCR_PCIEPMECTL2_L1SCPGE BIT4 ///< L1 State Controller Power Gating Enable
198
199 #define R_PCH_DMI15_PCR_PCE 0x2428 ///< Power Control Enable
200 #define B_PCH_DMI15_PCR_PCE_HAE BIT5 ///< Hardware Autonomous Enable
201 #define B_PCH_DMI15_PCR_PCE_SE BIT3 ///< Sleep Enable
202 #define B_PCH_DMI15_PCR_PCE_PMCRE BIT0 ///< PMC Request Enable
203
204 #define R_PCH_DMI15_PCR_EQCFG1 0x2450 ///< Equalization Configuration 1
205 #define B_PCH_DMI15_PCR_EQCFG1_RTLEPCEB BIT16 ///< Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass
206 #define B_PCH_DMI15_PCR_EQCFG1_RTPCOE BIT15 ///< Remote Transmitter Preset Coefficient Override Enable
207
208 #define R_PCH_DMI15_PCR_RTPCL1 0x2454 ///< Remote Transmitter Preset Coefficient List 1
209 #define N_PCH_DMI15_PCR_RTPCL1_RTPRECL2PL4 24
210 #define N_PCH_DMI15_PCR_RTPCL1_RTPOSTCL1PL3 18
211 #define N_PCH_DMI15_PCR_RTPCL1_RTPRECL1PL2 12
212 #define N_PCH_DMI15_PCR_RTPCL1_RTPOSTCL0PL1 6
213 #define N_PCH_DMI15_PCR_RTPCL1_RTPRECL0PL0 0
214 #define B_PCH_DMI15_PCR_RTPCL1_PCM BIT31
215 #define B_PCH_DMI15_PCR_RTPCL1_RTPRECL2PL4 (0x3F << N_PCH_DMI15_PCR_RTPCL1_RTPRECL2PL4)
216 #define B_PCH_DMI15_PCR_RTPCL1_RTPOSTCL1PL3 (0x3F << N_PCH_DMI15_PCR_RTPCL1_RTPOSTCL1PL3)
217 #define B_PCH_DMI15_PCR_RTPCL1_RTPRECL1PL2 (0x3F << N_PCH_DMI15_PCR_RTPCL1_RTPRECL1PL2)
218 #define B_PCH_DMI15_PCR_RTPCL1_RTPOSTCL0PL1 (0x3F << N_PCH_DMI15_PCR_RTPCL1_RTPOSTCL0PL1)
219 #define B_PCH_DMI15_PCR_RTPCL1_RTPRECL0PL0 (0x3F << N_PCH_DMI15_PCR_RTPCL1_RTPRECL0PL0)
220
221 #define R_PCH_DMI15_PCR_RTPCL2 0x2458 ///< Remote Transmitter Preset Coefficient List 2
222 #define N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL4PL9 24
223 #define N_PCH_DMI15_PCR_RTPCL2_RTPRECL4PL8 18
224 #define N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL3PL7 12
225 #define N_PCH_DMI15_PCR_RTPCL2_RTPRECL3PL6 6
226 #define N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL2PL5 0
227 #define B_PCH_DMI15_PCR_RTPCL2_RTPOSTCL4PL9 (0x3F << N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL4PL9)
228 #define B_PCH_DMI15_PCR_RTPCL2_RTPRECL4PL8 (0x3F << N_PCH_DMI15_PCR_RTPCL2_RTPRECL4PL8)
229 #define B_PCH_DMI15_PCR_RTPCL2_RTPOSTCL3PL7 (0x3F << N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL3PL7)
230 #define B_PCH_DMI15_PCR_RTPCL2_RTPRECL3PL6 (0x3F << N_PCH_DMI15_PCR_RTPCL2_RTPRECL3PL6)
231 #define B_PCH_DMI15_PCR_RTPCL2_RTPOSTCL2PL5 (0x3F << N_PCH_DMI15_PCR_RTPCL2_RTPOSTCL2PL5)
232
233 #define R_PCH_DMI15_PCR_LTCO1 0x2470 ///< Local Transmitter Coefficient Override 1
234 #define R_PCH_DMI15_PCR_LTCO2 0x2474 ///< Local Transmitter Coefficient Override 2
235 #define B_PCH_DMI15_PCR_L1357TCOE BIT25 ///< Lane 1/3 Transmitter Coefficient Override Enable
236 #define B_PCH_DMI15_PCR_L0246TCOE BIT24 ///< Lane 0/2 Transmitter Coefficient Override Enable
237 #define B_PCH_DMI15_PCR_L1357TPOSTCO 0x00FC0000 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override mask
238 #define N_PCH_DMI15_PCR_L1357TPOSTCO 18 ///< Lane 1/3 Transmitter Post-Cursor Coefficient Override value offset
239 #define B_PCH_DMI15_PCR_L1357TPRECO 0x0003F000 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override mask
240 #define N_PCH_DMI15_PCR_L1357TPRECO 12 ///< Lane 1/3 Transmitter Pre-Cursor Coefficient Override value offset
241 #define B_PCH_DMI15_PCR_L0246TPOSTCO 0x00000FC0 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override mask
242 #define N_PCH_DMI15_PCR_L0246TPOSTCO 6 ///< Lane 0/2 Transmitter Post-Cursor Coefficient Override value offset
243 #define B_PCH_DMI15_PCR_L0246TPRECO 0x0000003F ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override mask
244 #define N_PCH_DMI15_PCR_L0246TPRECO 0 ///< Lane 0/2 Transmitter Pre-Cursor Coefficient Override value offset
245
246 #define R_PCH_DMI15_PCR_G3L0SCTL 0x2478 ///< GEN3 L0s Control
247 #define B_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL 0xFF000000 ///< Gen3 Active State L0s Preparation Latency
248 #define N_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL 24 ///< Gen3 Active State L0s Preparation Latency
249 #define B_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS 0xFF ///< Gen3 Common Clock N_FTS
250 #define N_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS 0 ///< Gen3 Common Clock N_FTS
251
252 #define R_PCH_DMI15_PCR_UPHWAWC 0x249C ///< Upstream Port HW Autonomous Width Control
253 #define B_PCH_DMI15_PCR_UPHWAWC_TS3TW (BIT15 | BIT14 | BIT13) ///< Thermal Sensor 3 Target Width
254 #define N_PCH_DMI15_PCR_UPHWAWC_TS3TW 13 ///< Thermal Sensor 3 Target Width
255 #define B_PCH_DMI15_PCR_UPHWAWC_TS2TW (BIT12 | BIT11 | BIT10) ///< Thermal Sensor 2 Target Width
256 #define N_PCH_DMI15_PCR_UPHWAWC_TS2TW 10 ///< Thermal Sensor 2 Target Width
257 #define B_PCH_DMI15_PCR_UPHWAWC_TS1TW (BIT9 | BIT8 | BIT7) ///< Thermal Sensor 1 Target Width
258 #define N_PCH_DMI15_PCR_UPHWAWC_TS1TW 7 ///< Thermal Sensor 1 Target Width
259 #define B_PCH_DMI15_PCR_UPHWAWC_TS0TW (BIT6 | BIT5 | BIT4) ///< Thermal Sensor 0 Target Width
260 #define N_PCH_DMI15_PCR_UPHWAWC_TS0TW 4 ///< Thermal Sensor 0 Target Width
261 #define B_PCH_DMI15_PCR_UPHWAWC_TSAWEN BIT0 ///< Thermal Sensor Autonomous Width Enable
262
263 #define R_PCH_DMI15_PCR_CTRL1 0x24A0 ///< Control 1
264 #define B_PCH_DMI15_PCR_CTRL1_MRSCDIS BIT21 ///< MEUMA Root Space Check Disable
265 #define B_PCH_DMI15_PCR_CTRL1_L0SPFCUF (BIT16 | BIT15) ///< L0s Periodic Flow Control Update Frequency
266 #define B_PCH_DMI15_PCR_CTRL1_L1RC BIT12 ///< DMI L1 Root Port Control
267 #define B_PCH_DMI15_PCR_CTRL1_L1PL (BIT11 | BIT10 | BIT9) ///< DMI L1 Preparation Latency
268 #define N_PCH_DMI15_PCR_CTRL1_L1PL 9 ///< DMI L1 Preparation Latency
269 #define V_PCH_DMI15_PCR_CTRL1_L1PL_8US 0x4 ///< DMI L1 Preparation Latency
270 #define V_PCH_DMI15_PCR_CTRL1_L1PL_4US 0x3
271 #define V_PCH_DMI15_PCR_CTRL1_L1PL_2US 0x2
272 #define B_PCH_DMI15_PCR_CTRL1_L1RCEP BIT8
273 #define B_PCH_DMI15_PCR_CTRL1_TCUAPF BIT6 ///< Transaction Credit Update Arbitration Performance Fix
274 #define B_PCH_DMI15_PCR_CTRL1_DLDHB BIT4 ///< DMI Link Down Hang Bypass
275 #define B_PCH_DMI15_PCR_CTRL1_PSS BIT3 ///< IOSF Primary SAI Select
276 #define B_PCH_DMI15_PCR_CTRL1_UTPB BIT0 ///< Unsupported Transaction Policy Bit
277
278 #define R_PCH_DMI15_PCR_CTRL2 0x24A4 ///< Control 2
279 #define B_PCH_DMI15_PCR_CTRL2_DLDRSP BIT13 ///< DMI Link Data Rate Sustain Policy
280 #define B_PCH_DMI15_PCR_CTRL2_PMETOFD BIT6
281 #define B_PCH_DMI15_PCR_CTRL2_CPGEXLCWDIS BIT5 ///< CPG Exit Link Clock Wake Disable
282
283 #define R_PCH_DMI15_PCR_L0P0P1PCM 0x2500 ///< Lane 0 P0 And P1 Preset-Coefficient Mapping
284 #define R_PCH_DMI15_PCR_L0P1P2P3PCM 0x2504 ///< Lane 0 P1, P2 And P3 Preset-Coefficient Mapping
285 #define R_PCH_DMI15_PCR_L0P3P4PCM 0x2508 ///< Lane 0 P3 And P4 Preset-Coefficient Mapping
286 #define R_PCH_DMI15_PCR_L0P5P6PCM 0x250C ///< Lane 0 P5 And P6 Preset-Coefficient Mapping
287 #define R_PCH_DMI15_PCR_L0P6P7P8PCM 0x2510 ///< Lane 0 P6, P7 And P8 Preset-Coefficient Mapping
288 #define R_PCH_DMI15_PCR_L0P8P9PCM 0x2514 ///< Lane 0 P8 And P9 Preset-Coefficient Mapping
289 #define R_PCH_DMI15_PCR_L0P10PCM 0x2518 ///< Lane 0 P10 Preset-Coefficient Mapping ()
290 #define R_PCH_DMI15_PCR_L0LFFS 0x251C ///< Lane 0 LF And FS
291
292 #define R_PCH_DMI15_PCR_LTCO3 0x2598 ///< Local Transmitter Coefficient Override 3
293 #define R_PCH_DMI15_PCR_LTCO4 0x259C ///< Local Transmitter Coefficient Override 4
294
295 #define R_PCH_DMI15_PCR_CWBCTL 0x2820 ///< Central Write Buffer Control
296 #define B_PCH_DMI15_PCR_CWBCTL_CWBE BIT0 ///< Central Write Buffer Enable
297
298 #define R_PCH_DMI15_PCR_EEPPES 0x2900 ///< DMI End-to-End Parity Protection Error Status
299 #define B_PCH_DMI15_PCR_PSSSGE BIT31 ///< End-to-End Parity Error Stop and Scream SERR generation Enable
300
301 #define R_PCH_DMI15_PCR_L01EC 0x2A3C ///< Lane 0 and Lane 1 Equalization Control
302 #define R_PCH_DMI15_PCR_L23EC 0x2A40 ///< Lane 2 and Lane 3 Equalization Control
303 #define R_PCH_DMI15_PCR_L45EC 0x2A44 ///< Lane 4 and Lane 5 Equalization Control
304 #define R_PCH_DMI15_PCR_L67EC 0x2A48 ///< Lane 6 and Lane 7 Equalization Control
305 #define B_PCH_DMI15_PCR_UPL1357TP 0x0F000000 ///< Upstream Port Lane 1/3/5/7 Transmitter Preset mask
306 #define N_PCH_DMI15_PCR_UPL1357TP 24 ///< Upstream Port Lane 1/3/5/7 Transmitter Preset value offset
307 #define B_PCH_DMI15_PCR_UPL0246TP 0x00000F00 ///< Upstream Port Lane 0/2/4/6 Transmitter Preset mask
308 #define N_PCH_DMI15_PCR_UPL0246TP 8 ///< Upstream Port Lane 0/2/4/6 Transmitter Preset value offset
309 #define V_PCH_DMI15_PCR_UPL0TP 7 ///< Upstream Port Lane 0 Transmitter Preset value
310 #define V_PCH_DMI15_PCR_UPL1TP 7 ///< Upstream Port Lane 1 Transmitter Preset value
311 #define V_PCH_DMI15_PCR_UPL2TP 7 ///< Upstream Port Lane 2 Transmitter Preset value
312 #define V_PCH_DMI15_PCR_UPL3TP 7 ///< Upstream Port Lane 3 Transmitter Preset value
313 #define V_PCH_DMI15_PCR_UPL4TP 7 ///< Upstream Port Lane 4 Transmitter Preset value
314 #define V_PCH_DMI15_PCR_UPL5TP 7 ///< Upstream Port Lane 5 Transmitter Preset value
315 #define V_PCH_DMI15_PCR_UPL6TP 7 ///< Upstream Port Lane 6 Transmitter Preset value
316 #define V_PCH_DMI15_PCR_UPL7TP 7 ///< Upstream Port Lane 7 Transmitter Preset value
317
318
319 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi17Regs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchDmi17Regs.h File Reference

Register names for PCH DMI starting from SIP 17. More...

Go to the source code of this file.

Macros

#define | R_PCH_DMI17_PCR_LCAP2 0x206C
Link Capabilities 2.
#define | R_PCH_DMI17_PCR_LCTL2 0x2070
Link Control 2.

Detailed Description

Register names for PCH DMI starting from SIP 17.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmi17Regs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi17Regs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
PchDmi17Regs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH DMI starting from SIP 17
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2020 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_DMI17_REGS_H_
65 #define _PCH_DMI17_REGS_H_
66
67 #define R_PCH_DMI17_PCR_FCTL 0x1300
68 #define B_PCH_DMI17_PCR_FCTL_CRSPSEL BIT12
69
70 #define R_PCH_DMI17_PCR_FCUCTL 0x1304
71 #define B_PCH_DMI17_PCR_FCUCTL_FC_CP_FCM_VCM BIT28
72 #define B_PCH_DMI17_PCR_FCUCTL_FC_CP_FCM_VC1 BIT27
73 #define B_PCH_DMI17_PCR_FCUCTL_FC_CP_FCM BIT20
74
75 #define R_PCH_DMI17_PCR_FCTL2 0x1330
76 #define B_PCH_DMI17_PCR_FCTL2_HRTCTL_MASK (BIT9 | BIT8 | BIT7)
77 #define B_PCH_DMI17_PCR_FCTL2_HRTCTL_OFFSET 7
78 #define V_PCH_DMI17_PCR_FCTL2_HRTCTL 0x1
79 #define B_PCH_DMI17_PCR_FCTL2_RPTOT_MASK (BIT6 | BIT5 | BIT4)
80 #define B_PCH_DMI17_PCR_FCTL2_RPTOT_OFFSET 4
81 #define V_PCH_DMI17_PCR_FCTL2_RPTOT 0x5
82
83 #define R_PCH_DMI17_PCR_RPR 0x1334
84 #define B_PCH_DMI17_PCR_RPR_S5SMTO_MASK (BIT23 | BIT22)
85 #define B_PCH_DMI17_PCR_RPR_S5SMTO_OFFSET 22
86 #define V_PCH_DMI17_PCR_RPR_S5SMTO 0x1
87 #define B_PCH_DMI17_PCR_RPR_S4SMTO_MASK (BIT21 | BIT20)
88 #define B_PCH_DMI17_PCR_RPR_S4SMTO_OFFSET 20
89 #define V_PCH_DMI17_PCR_RPR_S4SMTO 0x1
90 #define B_PCH_DMI17_PCR_RPR_S3SMTO_MASK (BIT19 | BIT18)
91 #define B_PCH_DMI17_PCR_RPR_S3SMTO_OFFSET 18
92 #define V_PCH_DMI17_PCR_RPR_S3SMTO 0x1
93 #define B_PCH_DMI17_PCR_RPR_CRMTO_MASK (BIT17 | BIT16)
94 #define B_PCH_DMI17_PCR_RPR_CRMTO_OFFSET 16
95 #define V_PCH_DMI17_PCR_RPR_CRMTO 0x1
96 #define B_PCH_DMI17_PCR_RPR_WRMTO_MASK (BIT15 | BIT14)
97 #define B_PCH_DMI17_PCR_RPR_WRMTO_OFFSET 14
98 #define V_PCH_DMI17_PCR_RPR_WRMTO 0x1
99 #define B_PCH_DMI17_PCR_RPR_DMTO_MASK (BIT13 | BIT12)
100 #define B_PCH_DMI17_PCR_RPR_DMTO_OFFSET 12
101 #define V_PCH_DMI17_PCR_RPR_DMTO 0x1
102 #define B_PCH_DMI17_PCR_RPR_S5SM_MASK (BIT11 | BIT10)
103 #define B_PCH_DMI17_PCR_RPR_S5SM_OFFSET 10
104 #define V_PCH_DMI17_PCR_RPR_S5SM 0x1
105 #define B_PCH_DMI17_PCR_RPR_S4SM_MASK (BIT9 | BIT8)
106 #define B_PCH_DMI17_PCR_RPR_S4SM_OFFSET 8
107 #define V_PCH_DMI17_PCR_RPR_S4SM 0x1
108 #define B_PCH_DMI17_PCR_RPR_S3SM_MASK (BIT7 | BIT6)
109 #define B_PCH_DMI17_PCR_RPR_S3SM_OFFSET 6
110 #define V_PCH_DMI17_PCR_RPR_S3SM 0x1
111 #define B_PCH_DMI17_PCR_RPR_CRM_MASK (BIT5 | BIT4)
112 #define B_PCH_DMI17_PCR_RPR_CRM_OFFSET 4
113 #define V_PCH_DMI17_PCR_RPR_CRM 0x1
114 #define B_PCH_DMI17_PCR_RPR_WRM_MASK (BIT3 | BIT2)
115 #define B_PCH_DMI17_PCR_RPR_WRM_OFFSET 2
116 #define V_PCH_DMI17_PCR_RPR_WRM 0x1
117
118 #define R_PCH_DMI17_PCR_DCGEN1 0x1350
119 #define B_PCH_DMI17_PCR_DCGEN1_PXTTSULDCGEN BIT25
120 #define B_PCH_DMI17_PCR_DCGEN1_PXTTSULDCGEN_OFFSET 25
121 #define B_PCH_DMI17_PCR_DCGEN1_PXTTULDCGEN BIT24
122 #define B_PCH_DMI17_PCR_DCGEN1_PXTTULDCGEN_OFFSET 24
123 #define B_PCH_DMI17_PCR_DCGEN1_PXTRSULDCGEN BIT17
124 #define B_PCH_DMI17_PCR_DCGEN1_PXTRSULDCGEN_OFFSET 17
125 #define B_PCH_DMI17_PCR_DCGEN1_PXTRULDCGEN BIT16
126 #define B_PCH_DMI17_PCR_DCGEN1_PXTRULDCGEN_OFFSET 16
127 #define B_PCH_DMI17_PCR_DCGEN1_PXLSULDCGEN BIT11
128 #define B_PCH_DMI17_PCR_DCGEN1_PXLSULDCGEN_OFFSET 11
129 #define B_PCH_DMI17_PCR_DCGEN1_PXLIULDCGEN BIT10
130 #define B_PCH_DMI17_PCR_DCGEN1_PXLIULDCGEN_OFFSET 10
131 #define B_PCH_DMI17_PCR_DCGEN1_PXLRULDCGEN BIT8
132 #define B_PCH_DMI17_PCR_DCGEN1_PXLRULDCGEN_OFFSET 8
133 #define B_PCH_DMI17_PCR_DCGEN1_PXCULDCGEN BIT1
134 #define B_PCH_DMI17_PCR_DCGEN1_PXCULDCGEN_OFFSET 1
135 #define B_PCH_DMI17_PCR_DCGEN1_PXKGULDCGEN BIT0
136 #define B_PCH_DMI17_PCR_DCGEN1_PXKGULDCGEN_OFFSET 0
137
138 #define R_PCH_DMI17_PCR_DCGEN2 0x1354
139 #define B_PCH_DMI17_PCR_DCGEN2_PXSDRULDCGEN BIT17
140 #define B_PCH_DMI17_PCR_DCGEN2_PXSDRULDCGEN_OFFSET 17
141 #define B_PCH_DMI17_PCR_DCGEN2_PXSDTULDCGEN BIT16
142 #define B_PCH_DMI17_PCR_DCGEN2_PXSDTULDCGEN_OFFSET 16
143 #define B_PCH_DMI17_PCR_DCGEN2_PXSDIULDCGEN BIT15
144 #define B_PCH_DMI17_PCR_DCGEN2_PXSDIULDCGEN_OFFSET 15
145 #define B_PCH_DMI17_PCR_DCGEN2_PXFRULDCGEN BIT5
146 #define B_PCH_DMI17_PCR_DCGEN2_PXFRULDCGEN_OFFSET 5
147 #define B_PCH_DMI17_PCR_DCGEN2_PXFTULDCGEN BIT4
148 #define B_PCH_DMI17_PCR_DCGEN2_PXFTULDCGEN_OFFSET 4
149 #define B_PCH_DMI17_PCR_DCGEN2_PXPBULDCGEN BIT2
150 #define B_PCH_DMI17_PCR_DCGEN2_PXPBULDCGEN_OFFSET 2
151 #define B_PCH_DMI17_PCR_DCGEN2_PXPSULDCGEN BIT1
152 #define B_PCH_DMI17_PCR_DCGEN2_PXPSULDCGEN_OFFSET 1
153 #define B_PCH_DMI17_PCR_DCGEN2_PXPIULDCGEN BIT0
154 #define B_PCH_DMI17_PCR_DCGEN2_PXPIULDCGEN_OFFSET 0
155
156 #define R_PCH_DMI17_PCR_DCGM1 0x1358
157 #define B_PCH_DMI17_PCR_DCGM1_PXTTSULDCGM BIT25
158 #define B_PCH_DMI17_PCR_DCGM1_PXTTSULDCGM_OFFSET 25
159 #define B_PCH_DMI17_PCR_DCGM1_PXTTULDCGM BIT24
160 #define B_PCH_DMI17_PCR_DCGM1_PXTTULDCGM_OFFSET 24
161 #define B_PCH_DMI17_PCR_DCGM1_PXTRSULDCGM BIT17
162 #define B_PCH_DMI17_PCR_DCGM1_PXTRSULDCGM_OFFSET 17
163 #define B_PCH_DMI17_PCR_DCGM1_PXTRULDCGM BIT16
164 #define B_PCH_DMI17_PCR_DCGM1_PXTRULDCGM_OFFSET 16
165 #define B_PCH_DMI17_PCR_DCGM1_PXLSULDCGM BIT11
166 #define B_PCH_DMI17_PCR_DCGM1_PXLSULDCGM_OFFSET 11
167 #define B_PCH_DMI17_PCR_DCGM1_PXLIULDCGM BIT10
168 #define B_PCH_DMI17_PCR_DCGM1_PXLIULDCGM_OFFSET 10
169 #define B_PCH_DMI17_PCR_DCGM1_PXLTULDCGM BIT9
170 #define B_PCH_DMI17_PCR_DCGM1_PXLTULDCGM_OFFSET 9
171 #define B_PCH_DMI17_PCR_DCGM1_PXLRULDCGM BIT8
172 #define B_PCH_DMI17_PCR_DCGM1_PXLRULDCGM_OFFSET 8
173 #define B_PCH_DMI17_PCR_DCGM1_PXCULDCGM BIT1
174 #define B_PCH_DMI17_PCR_DCGM1_PXCULDCGM_OFFSET 1
175 #define B_PCH_DMI17_PCR_DCGM1_PXKGULDCGM BIT0
176 #define B_PCH_DMI17_PCR_DCGM1_PXKGULDCGM_OFFSET 0
177
178 #define R_PCH_DMI17_PCR_DCGM2 0x135C
179 #define B_PCH_DMI17_PCR_DCGM2_PXSDRULDCGM BIT17
180 #define B_PCH_DMI17_PCR_DCGM2_PXSDRULDCGM_OFFSET 17
181 #define B_PCH_DMI17_PCR_DCGM2_PXSDTULDCGM BIT16
182 #define B_PCH_DMI17_PCR_DCGM2_PXSDTULDCGM_OFFSET 16
183 #define B_PCH_DMI17_PCR_DCGM2_PXSDIULDCGM BIT15
184 #define B_PCH_DMI17_PCR_DCGM2_PXSDIULDCGM_OFFSET 15
185 #define B_PCH_DMI17_PCR_DCGM2_PXFRULDCGM BIT5
186 #define B_PCH_DMI17_PCR_DCGM2_PXFRULDCGM_OFFSET 5
187 #define B_PCH_DMI17_PCR_DCGM2_PXFTULDCGM BIT4
188 #define B_PCH_DMI17_PCR_DCGM2_PXFTULDCGM_OFFSET 4
189 #define B_PCH_DMI17_PCR_DCGM2_PXPBULDCGM BIT2
190 #define B_PCH_DMI17_PCR_DCGM2_PXPBULDCGM_OFFSET 2
191 #define B_PCH_DMI17_PCR_DCGM2_PXPSULDCGM BIT1
192 #define B_PCH_DMI17_PCR_DCGM2_PXPSULDCGM_OFFSET 1
193 #define B_PCH_DMI17_PCR_DCGM2_PXPIULDCGM BIT0
194 #define B_PCH_DMI17_PCR_DCGM2_PXPIULDCGM_OFFSET 0
195
196 #define R_PCH_DMI17_PCR_DCGEN3 0x1360
197 #define B_PCH_DMI17_PCR_DCGEN3_PXTTSUPDCGEN BIT25
198 #define B_PCH_DMI17_PCR_DCGEN3_PXTTSUPDCGEN_OFFSET 25
199 #define B_PCH_DMI17_PCR_DCGEN3_PXTTUPDCGEN BIT24
200 #define B_PCH_DMI17_PCR_DCGEN3_PXTTUPDCGEN_OFFSET 24
201 #define B_PCH_DMI17_PCR_DCGEN3_PXTOUPDCGEN BIT19
202 #define B_PCH_DMI17_PCR_DCGEN3_PXTOUPDCGEN_OFFSET 19
203 #define B_PCH_DMI17_PCR_DCGEN3_PXTRSUPDCGEN BIT17
204 #define B_PCH_DMI17_PCR_DCGEN3_PXTRSUPDCGEN_OFFSET 17
205 #define B_PCH_DMI17_PCR_DCGEN3_PXTRUPDCGEN BIT16
206 #define B_PCH_DMI17_PCR_DCGEN3_PXTRUPDCGEN_OFFSET 16
207 #define B_PCH_DMI17_PCR_DCGEN3_PXLIUPDCGEN BIT10
208 #define B_PCH_DMI17_PCR_DCGEN3_PXLIUPDCGEN_OFFSET 10
209 #define B_PCH_DMI17_PCR_DCGEN3_PXLTUPDCGEN BIT9
210 #define B_PCH_DMI17_PCR_DCGEN3_PXLTUPDCGEN_OFFSET 9
211 #define B_PCH_DMI17_PCR_DCGEN3_PXLRUPDCGEN BIT8
212 #define B_PCH_DMI17_PCR_DCGEN3_PXLRUPDCGEN_OFFSET 8
213 #define B_PCH_DMI17_PCR_DCGEN3_PXSRUSSNRDCGEN BIT6
214 #define B_PCH_DMI17_PCR_DCGEN3_PXSRUSSNRDCGEN_OFFSET 6
215 #define B_PCH_DMI17_PCR_DCGEN3_PXCUPSNRDCGEN BIT5
216 #define B_PCH_DMI17_PCR_DCGEN3_PXCUPSNRDCGEN_OFFSET 5
217 #define B_PCH_DMI17_PCR_DCGEN3_PXCUPSRCDCGEN BIT4
218 #define B_PCH_DMI17_PCR_DCGEN3_PXCUPSRCDCGEN_OFFSET 4
219 #define B_PCH_DMI17_PCR_DCGEN3_PXBUPDCGEN BIT1
220 #define B_PCH_DMI17_PCR_DCGEN3_PXBUPDCGEN_OFFSET 1
221 #define B_PCH_DMI17_PCR_DCGEN3_PXEUPDCGEN BIT0
222 #define B_PCH_DMI17_PCR_DCGEN3_PXEUPDCGEN_OFFSET 0
223
224 #define R_PCH_DMI17_PCR_DCGM3 0x1368
225 #define B_PCH_DMI17_PCR_DCGM3_PXTTSUPDCGM BIT25
226 #define B_PCH_DMI17_PCR_DCGM3_PXTTSUPDCGM_OFFSET 25
227 #define B_PCH_DMI17_PCR_DCGM3_PXTTUPDCGM BIT24
228 #define B_PCH_DMI17_PCR_DCGM3_PXTTUPDCGM_OFFSET 24
229 #define B_PCH_DMI17_PCR_DCGM3_PXTOUPDCGM BIT19
230 #define B_PCH_DMI17_PCR_DCGM3_PXTOUPDCGM_OFFSET 19
231 #define B_PCH_DMI17_PCR_DCGM3_PXTRSUPDCGM BIT17
232 #define B_PCH_DMI17_PCR_DCGM3_PXTRSUPDCGM_OFFSET 17
233 #define B_PCH_DMI17_PCR_DCGM3_PXTRUPDCGM BIT16
234 #define B_PCH_DMI17_PCR_DCGM3_PXTRUPDCGM_OFFSET 16
235 #define B_PCH_DMI17_PCR_DCGM3_PXLIUPDCGM BIT10
236 #define B_PCH_DMI17_PCR_DCGM3_PXLIUPDCGM_OFFSET 10
237 #define B_PCH_DMI17_PCR_DCGM3_PXLTUPDCGM BIT9
238 #define B_PCH_DMI17_PCR_DCGM3_PXLTUPDCGM_OFFSET 9
239 #define B_PCH_DMI17_PCR_DCGM3_PXLRUPDCGM BIT8
240 #define B_PCH_DMI17_PCR_DCGM3_PXLRUPDCGM_OFFSET 8
241 #define B_PCH_DMI17_PCR_DCGM3_PXSRUSSNRDCGM BIT6
242 #define B_PCH_DMI17_PCR_DCGM3_PXSRUSSNRDCGM_OFFSET 6
243 #define B_PCH_DMI17_PCR_DCGM3_PXCUPSNRDCGM BIT5
244 #define B_PCH_DMI17_PCR_DCGM3_PXCUPSNRDCGM_OFFSET 5
245 #define B_PCH_DMI17_PCR_DCGM3_PXCUPSRCDCGM BIT4
246 #define B_PCH_DMI17_PCR_DCGM3_PXCUPSRCDCGM_OFFSET 4
247 #define B_PCH_DMI17_PCR_DCGM3_PXBUPDCGM BIT1
248 #define B_PCH_DMI17_PCR_DCGM3_PXBUPDCGM_OFFSET 1
249 #define B_PCH_DMI17_PCR_DCGM3_PXEUPDCGM BIT0
250 #define B_PCH_DMI17_PCR_DCGM3_PXEUPDCGM_OFFSET 0
251
252 #define R_PCH_DMI17_PCR_IPCLKCTR 0x1370
253 #define B_PCH_DMI17_PCR_IPCLKCTR_MDPCCEN BIT3
254 #define B_PCH_DMI17_PCR_IPCLKCTR_PXDCGE BIT2
255 #define B_PCH_DMI17_PCR_IPCLKCTR_PXDCGE_OFFSET 2
256
257 #define R_PCH_DMI17_PCR_LPHYCP1 0x1410
258 #define B_PCH_DMI17_PCR_LPHYCP1_RXEQFNEVC BIT4
259 #define B_PCH_DMI17_PCR_LPHYCP1_RXEQFNEVC_OFFSET 4
260 #define B_PCH_DMI17_PCR_LPHYCP1_RXADPHM BIT3
261 #define B_PCH_DMI17_PCR_LPHYCP1_RXADPHM_OFFSET 3
262
263 #define R_PCH_DMI17_PCR_UPDLPHYCP 0x1414
264 #define B_PCH_DMI17_PCR_UPDLPHYCP_UPDLTCDC BIT1
265 #define B_PCH_DMI17_PCR_UPDLPHYCP_UPDLTCDC_OFFSET 1
266 #define B_PCH_DMI17_PCR_UPDLPHYCP_UPDLLSMFLD BIT0
267 #define B_PCH_DMI17_PCR_UPDLPHYCP_UPDLLSMFLD_OFFSET 0
268
269 #define R_PCH_DMI17_PCR_RXL0SESQCP1 0x1420
270 #define B_PCH_DMI17_PCR_RXL0SESQCP1_SSMFRXL0S_MASK (BIT1 | BIT0)
271 #define B_PCH_DMI17_PCR_RXL0SESQCP1_SSMFRXL0S_OFFSET 0
272 #define V_PCH_DMI17_PCR_RXL0SESQCP1_SSMFRXL0S 0x2
273
274 #define R_PCH_DMI17_PCR_RXL0SESQCP2 0x1424
275 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4SQPDC_MASK 0xF0000000
276 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4SQPDC_OFFSET 28
277 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G4SQPDC 0x0
278 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4SSDFRXL0S_MASK (BIT26 | BIT25 | BIT24)
279 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4SSDFRXL0S_OFFSET 24
280 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G4SSDFRXL0S 0x2
281 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3SQPDC_MASK 0xF00000
282 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3SQPDC_OFFSET 20
283 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G3SQPDC 0x0
284 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3SSDFRXL0S_MASK (BIT18 | BIT17 | BIT16)
285 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3SSDFRXL0S_OFFSET 16
286 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G3SSDFRXL0S 0x2
287 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2SQPDC_MASK 0xF000
288 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2SQPDC_OFFSET 12
289 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G2SQPDC 0x0
290 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2SSDFRXL0S_MASK (BIT10 | BIT9 | BIT8)
291 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2SSDFRXL0S_OFFSET 8
292 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G2SSDFRXL0S 0x2
293 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G1SQPDC_MASK 0xF0
294 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G1SQPDC_OFFSET 4
295 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G1SQPDC 0x0
296 #define B_PCH_DMI17_PCR_RXL0SESQCP2_G1SSDFRXL0S_MASK (BIT1 | BIT0)
297 #define B_PCH_DMI17_PCR_RXL0SESQCP2_G1SSDFRXL0S_OFFSET 0
298 #define V_PCH_DMI17_PCR_RXL0SESQCP2_G1SSDFRXL0S 0x2
299
300 #define R_PCH_DMI17_PCR_RXL0SESQCP4 0x142C
301 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4LBWSST_MASK 0xFF000000
302 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G4LBWSST_OFFSET 24
303 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G4LBWSST 0x4
304 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3LBWSST_MASK 0xFF0000
305 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G3LBWSST_OFFSET 16
306 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G3LBWSST 0x4
307 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2LBWSST_MASK 0xFF00
308 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G2LBWSST_OFFSET 8
309 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G2LBWSST 0x4
310 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G1LBWSST_MASK 0xFF
311 #define B_PCH_DMI17_PCR_RXL0SESQCP4_G1LBWSST_OFFSET 0
312 #define V_PCH_DMI17_PCR_RXL0SESQCP4_G1LBWSST 0x4
313
314 #define R_PCH_DMI17_PCR_LPHYCP4 0x1434
315 #define B_PCH_DMI17_PCR_LPHYCP4_DPMDNDBFE BIT12
316 #define B_PCH_DMI17_PCR_LPHYCP4_DPMDNDBFE_OFFSET 12
317 #define B_PCH_DMI17_PCR_LPHYCP4_PLLBUSDRC BIT10
318 #define B_PCH_DMI17_PCR_LPHYCP4_PLLBUSDRC_OFFSET 10
319 #define B_PCH_DMI17_PCR_LPHYCP4_LGUSSP_MASK (BIT7 | BIT6)
320 #define B_PCH_DMI17_PCR_LPHYCP4_LGUSSP_OFFSET 6
321 #define V_PCH_DMI17_PCR_LPHYCP4_LGUSSP 0x1
322 #define B_PCH_DMI17_PCR_LPHYCP4_OSCCLKSQEXITDBTIMERS_MASK (BIT5 | BIT4 | BIT3)
323 #define B_PCH_DMI17_PCR_LPHYCP4_OSCCLKSQEXITDBTIMERS_OFFSET 3
324 #define V_PCH_DMI17_PCR_LPHYCP4_OSCCLKSQEXITDBTIMERS 0x2
325 #define B_PCH_DMI17_PCR_LPHYCP4_LGCLKSQEXITDBTIMERS_MASK (BIT2 | BIT1 | BIT0)
326 #define B_PCH_DMI17_PCR_LPHYCP4_LGCLKSQEXITDBTIMERS_OFFSET 0
327 #define V_PCH_DMI17_PCR_LPHYCP4_LGCLKSQEXITDBTIMERS 0x2
328
329 #define R_PCH_DMI17_PCR_IORCCP1 0x144C
330 #define B_PCH_DMI17_PCR_IORCCP1_G5ORRRXECC_MASK (BIT30 | BIT29 | BIT28)
331 #define B_PCH_DMI17_PCR_IORCCP1_G5ORRRXECC_OFFSET 28
332 #define V_PCH_DMI17_PCR_IORCCP1_G5ORRRXECC 0x1
333 #define B_PCH_DMI17_PCR_IORCCP1_G4ORRRXECC_MASK (BIT27 | BIT26 | BIT25)
334 #define B_PCH_DMI17_PCR_IORCCP1_G4ORRRXECC_OFFSET 25
335 #define V_PCH_DMI17_PCR_IORCCP1_G4ORRRXECC 0x1
336 #define B_PCH_DMI17_PCR_IORCCP1_G3ORRRXECC_MASK (BIT24 | BIT23 | BIT22)
337 #define B_PCH_DMI17_PCR_IORCCP1_G3ORRRXECC_OFFSET 22
338 #define V_PCH_DMI17_PCR_IORCCP1_G3ORRRXECC 0x1
339 #define B_PCH_DMI17_PCR_IORCCP1_G2ORRRXECC_MASK (BIT21 | BIT20 | BIT19)
340 #define B_PCH_DMI17_PCR_IORCCP1_G2ORRRXECC_OFFSET 19
341 #define V_PCH_DMI17_PCR_IORCCP1_G2ORRRXECC 0x1
342 #define B_PCH_DMI17_PCR_IORCCP1_G1ORRRXECC_MASK (BIT18 | BIT17 | BIT16)
343 #define B_PCH_DMI17_PCR_IORCCP1_G1ORRRXECC_OFFSET 16
344 #define V_PCH_DMI17_PCR_IORCCP1_G1ORRRXECC 0x1
345 #define B_PCH_DMI17_PCR_IORCCP1_DISORCRODI BIT2
346 #define B_PCH_DMI17_PCR_IORCCP1_DISORCRODI_OFFSET 2
347 #define B_PCH_DMI17_PCR_IORCCP1_DRCORRP BIT1
348 #define B_PCH_DMI17_PCR_IORCCP1_DRCORRP_OFFSET 1
349 #define B_PCH_DMI17_PCR_IORCCP1_DISORCL12REC BIT0
350 #define B_PCH_DMI17_PCR_IORCCP1_DISORCL12REC_OFFSET 0
351
352 #define R_PCH_DMI17_PCR_DETPHYPGE 0x1590
353 #define B_PCH_DMI17_PCR_DETPHYPGE_DLPPGP BIT4
354 #define B_PCH_DMI17_PCR_DETPHYPGE_DUCFGPHYPGE BIT3
355 #define B_PCH_DMI17_PCR_DETPHYPGE_L23PHYPGE BIT2
356 #define B_PCH_DMI17_PCR_DETPHYPGE_DISPHYPGE BIT1
357 #define B_PCH_DMI17_PCR_DETPHYPGE_DETPHYPGE BIT0
358
359 #define R_PCH_DMI17_PCR_PIPEPDCTL 0x1594
360 #define B_PCH_DMI17_PCR_PIPEPDCTL_L1PGUPGPDCTL_MASK (BIT31 | BIT30 | BIT29 | BIT28)
361 #define B_PCH_DMI17_PCR_PIPEPDCTL_L1PGUPGPDCTL_OFFSET 28
362 #define V_PCH_DMI17_PCR_PIPEPDCTL_L1PGUPGPDCTL 0x4
363 #define B_PCH_DMI17_PCR_PIPEPDCTL_L1PGNOPGPDCTL_MASK (BIT27 | BIT26 | BIT25 | BIT24)
364 #define B_PCH_DMI17_PCR_PIPEPDCTL_L1PGNOPGPDCTL_OFFSET 24
365 #define V_PCH_DMI17_PCR_PIPEPDCTL_L1PGNOPGPDCTL 0x4
366 #define B_PCH_DMI17_PCR_PIPEPDCTL_DISPGPDCTL_MASK (BIT23 | BIT22 | BIT21 | BIT20)
367 #define B_PCH_DMI17_PCR_PIPEPDCTL_DISPGPDCTL_OFFSET 20
368 #define V_PCH_DMI17_PCR_PIPEPDCTL_DISPGPDCTL 0x3
369 #define B_PCH_DMI17_PCR_PIPEPDCTL_DISNOPGPDCTL_MASK (BIT19 | BIT18 | BIT17 | BIT16)
370 #define B_PCH_DMI17_PCR_PIPEPDCTL_DISNOPGPDCTL_OFFSET 16
371 #define V_PCH_DMI17_PCR_PIPEPDCTL_DISNOPGPDCTL 0x3
372 #define B_PCH_DMI17_PCR_PIPEPDCTL_L23PGPDCTL_MASK (BIT15 | BIT14 | BIT13 | BIT12)
373 #define B_PCH_DMI17_PCR_PIPEPDCTL_L23PGPDCTL_OFFSET 12
374 #define V_PCH_DMI17_PCR_PIPEPDCTL_L23PGPDCTL 0x3
375 #define B_PCH_DMI17_PCR_PIPEPDCTL_L23NOPGPDCTL_MASK (BIT11 | BIT10 | BIT9 | BIT8)
376 #define B_PCH_DMI17_PCR_PIPEPDCTL_L23NOPGPDCTL_OFFSET 8
377 #define V_PCH_DMI17_PCR_PIPEPDCTL_L23NOPGPDCTL 0x3
378 #define B_PCH_DMI17_PCR_PIPEPDCTL_DETPGPDCTL_MASK (BIT7 | BIT6 | BIT5 | BIT4)
379 #define B_PCH_DMI17_PCR_PIPEPDCTL_DETPGPDCTL_OFFSET 4
380 #define V_PCH_DMI17_PCR_PIPEPDCTL_DETPGPDCTL 0x3
381 #define B_PCH_DMI17_PCR_PIPEPDCTL_DETNOPGPDCTL_MASK (BIT3 | BIT2 | BIT1 | BIT0)
382 #define B_PCH_DMI17_PCR_PIPEPDCTL_DETNOPGPDCTL_OFFSET 0
383 #define V_PCH_DMI17_PCR_PIPEPDCTL_DETNOPGPDCTL 0x3
384
385 #define R_PCH_DMI17_PCR_PIPEPDCTL2 0x1598
386 #define B_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGPGPDCTL_MASK (BIT31 | BIT30 | BIT29 | BIT28)
387 #define B_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGPGPDCTL_OFFSET 28
388 #define V_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGPGPDCTL 0x3
389 #define B_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGNOPGPDCTL_MASK (BIT27 | BIT26 | BIT25 | BIT24)
390 #define B_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGNOPGPDCTL_OFFSET 24
391 #define V_PCH_DMI17_PCR_PIPEPDCTL2_DUCFGNOPGPDCTL 0x3
392 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D2PGPDCTL_MASK (BIT23 | BIT22 | BIT21 | BIT20)
393 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D2PGPDCTL_OFFSET 20
394 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1D2PGPDCTL 0x4
395 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D2NOPGPDCTL_MASK (BIT19 | BIT18 | BIT17 | BIT16)
396 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D2NOPGPDCTL_OFFSET 16
397 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1D2NOPGPDCTL 0x4
398 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGPGPDCTL_MASK (BIT15 | BIT14 | BIT13 | BIT12)
399 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGPGPDCTL_OFFSET 12
400 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGPGPDCTL 0x4
401 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGNOPGPDCTL_MASK (BIT11 | BIT10 | BIT9 | BIT8)
402 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGNOPGPDCTL_OFFSET 8
403 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1D1PGNOPGPDCTL 0x4
404 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1UPUPGPDCTL_MASK (BIT7 | BIT6 | BIT5 | BIT4)
405 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1D1UPUPGPDCTL_OFFSET 4
406 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1D1UPUPGPDCTL 0x6
407 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1UPNOPGPDCTL_MASK (BIT3 | BIT2 | BIT1 | BIT0)
408 #define B_PCH_DMI17_PCR_PIPEPDCTL2_L1UPNOPGPDCTL_OFFSET 0
409 #define V_PCH_DMI17_PCR_PIPEPDCTL2_L1UPNOPGPDCTL 0x6
410
411 #define R_PCH_DMI17_PCR_PIPEPDCTL3 0x159C
412 #define B_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWPGPDCTL_MASK (BIT7 | BIT6 | BIT5 | BIT4)
413 #define B_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWPGPDCTL_OFFSET 4
414 #define V_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWPGPDCTL 0x4
415 #define B_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWNOPGPDCTL_MASK (BIT3 | BIT2 | BIT1 | BIT0)
416 #define B_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWNOPGPDCTL_OFFSET 0
417 #define V_PCH_DMI17_PCR_PIPEPDCTL3_L1DLOWNOPGPDCTL 0x4
418
419 #define R_PCH_DMI17_PCR_PIPEPDCTLEXT 0x15A0
420 #define B_PCH_DMI17_PCR_PIPEPDCTLEXT_P2TP2T BIT2
421 #define B_PCH_DMI17_PCR_PIPEPDCTLEXT_P2TP2T_OFFSET 2
422 #define B_PCH_DMI17_PCR_PIPEPDCTLEXT_P2TP2TCD BIT1
423 #define B_PCH_DMI17_PCR_PIPEPDCTLEXT_P2TP2TCD_OFFSET 1
424
425 #define R_PCH_DMI17_PCR_RPDEC1 0x1780
426 #define B_PCH_DMI17_PCR_RPDEC1_RPCREPT_MASK 0xFF000000
427 #define B_PCH_DMI17_PCR_RPDEC1_RPCREPT_OFFSET 24
428 #define V_PCH_DMI17_PCR_RPDEC1_RPCREPT 0x3
429 #define B_PCH_DMI17_PCR_RPDEC1_RPCRERT_MASK 0xFF0000
430 #define B_PCH_DMI17_PCR_RPDEC1_RPCRERT_OFFSET 16
431 #define V_PCH_DMI17_PCR_RPDEC1_RPCRERT 0x11
432 #define B_PCH_DMI17_PCR_RPDEC1_RPWREPT_MASK 0xFF00
433 #define B_PCH_DMI17_PCR_RPDEC1_RPWREPT_OFFSET 8
434 #define V_PCH_DMI17_PCR_RPDEC1_RPWREPT 0x3
435 #define B_PCH_DMI17_PCR_RPDEC1_RPWRERT_MASK 0xFF
436 #define B_PCH_DMI17_PCR_RPDEC1_RPWRERT_OFFSET 0
437 #define V_PCH_DMI17_PCR_RPDEC1_RPWRERT 0x10
438
439 #define R_PCH_DMI17_PCR_RPDEC2 0x1784
440 #define B_PCH_DMI17_PCR_RPDEC2_RPS4EPT_MASK 0xFF000000
441 #define B_PCH_DMI17_PCR_RPDEC2_RPS4EPT_OFFSET 24
442 #define V_PCH_DMI17_PCR_RPDEC2_RPS4EPT 0x3
443 #define B_PCH_DMI17_PCR_RPDEC2_RPS4ERT_MASK 0xFF0000
444 #define B_PCH_DMI17_PCR_RPDEC2_RPS4ERT_OFFSET 16
445 #define V_PCH_DMI17_PCR_RPDEC2_RPS4ERT 0x4
446 #define B_PCH_DMI17_PCR_RPDEC2_RPS3EPT_MASK 0xFF00
447 #define B_PCH_DMI17_PCR_RPDEC2_RPS3EPT_OFFSET 8
448 #define V_PCH_DMI17_PCR_RPDEC2_RPS3EPT 0x3
449 #define B_PCH_DMI17_PCR_RPDEC2_RPS3ERT_MASK 0xFF
450 #define B_PCH_DMI17_PCR_RPDEC2_RPS3ERT_OFFSET 0
451 #define V_PCH_DMI17_PCR_RPDEC2_RPS3ERT 0x3
452
453 #define R_PCH_DMI17_PCR_RPDEC3 0x1788
454 #define B_PCH_DMI17_PCR_RPDEC3_RPDH_MASK (BIT18 | BIT17 | BIT16)
455 #define B_PCH_DMI17_PCR_RPDEC3_RPDH_OFFSET 16
456 #define V_PCH_DMI17_PCR_RPDEC3_RPDH 0x5
457 #define B_PCH_DMI17_PCR_RPDEC3_RPS5EPT_MASK 0xFF00
458 #define B_PCH_DMI17_PCR_RPDEC3_RPS5EPT_OFFSET 8
459 #define V_PCH_DMI17_PCR_RPDEC3_RPS5EPT 0x3
460 #define B_PCH_DMI17_PCR_RPDEC3_RPS5ERT_MASK 0xFF
461 #define B_PCH_DMI17_PCR_RPDEC3_RPS5ERT_OFFSET 0
462 #define V_PCH_DMI17_PCR_RPDEC3_RPS5ERT 0x5
463
464 #define R_PCH_DMI17_PCR_DECCTL 0x1904
465 #define B_PCH_DMI17_PCR_DECCTL_RXIMDECEN BIT31
466 #define B_PCH_DMI17_PCR_DECCTL_URRXMCTPNTCO BIT30
467 #define B_PCH_DMI17_PCR_DECCTL_RXMCTPBRCDECEN BIT29
468 #define B_PCH_DMI17_PCR_DECCTL_URRXUVDMRGRTRC BIT28
469 #define B_PCH_DMI17_PCR_DECCTL_URRXUVDMRBFRC BIT27
470 #define B_PCH_DMI17_PCR_DECCTL_LCRXPTMREQ BIT26
471 #define B_PCH_DMI17_PCR_DECCTL_RSVD_RW BIT25
472 #define B_PCH_DMI17_PCR_DECCTL_LCRXERRMSG BIT24
473 #define B_PCH_DMI17_PCR_DECCTL_RXLTRMDECH BIT23
474 #define B_PCH_DMI17_PCR_DECCTL_RXADLEDDECEN BIT22
475 #define B_PCH_DMI17_PCR_DECCTL_RXSBEMCAPDECEN BIT21
476 #define B_PCH_DMI17_PCR_DECCTL_RXGPEDECEN BIT20
477 #define B_PCH_DMI17_PCR_DECCTL_RXVDMDECE BIT19
478 #define B_PCH_DMI17_PCR_DECCTL_RXMCTPDECEN BIT18
479 #define B_PCH_DMI17_PCR_DECCTL_ICHKINVREQRMSGRBID BIT17
480 #define B_PCH_DMI17_PCR_DECCTL_URRXVMCTPBFRC BIT16
481 #define B_PCH_DMI17_PCR_DECCTL_URRXUORVDM BIT15
482 #define B_PCH_DMI17_PCR_DECCTL_URRXURIDVDM BIT14
483 #define B_PCH_DMI17_PCR_DECCTL_URRXURAVDM BIT13
484 #define B_PCH_DMI17_PCR_DECCTL_URRXULTVDM BIT12
485 #define B_PCH_DMI17_PCR_DECCTL_URRXURTRCVDM BIT11
486 #define B_PCH_DMI17_PCR_DECCTL_URRXUVDMUVID BIT10
487 #define B_PCH_DMI17_PCR_DECCTL_URRXUVDMINTELVID BIT9
488 #define B_PCH_DMI17_PCR_DECCTL_URVDME16DW BIT8
489 #define B_PCH_DMI17_PCR_DECCTL_VDMATAC BIT7
490 #define B_PCH_DMI17_PCR_DECCTL_LCRXINT BIT6
491 #define B_PCH_DMI17_PCR_DECCTL_DROPCPLATNZCE BIT4
492 #define B_PCH_DMI17_PCR_DECCTL_OUTBEXPCPLCHKEN BIT3
493 #define B_PCH_DMI17_PCR_DECCTL_MTRXLTC BIT2
494 #define B_PCH_DMI17_PCR_DECCTL_BUSNUMZCHK BIT1
495 #define B_PCH_DMI17_PCR_DECCTL_ATSCE BIT0
496
497 #define R_PCH_DMI17_PCR_PIDECCTL 0x190C
498 #define B_PCH_DMI17_PCR_PIDECCTL_CPLBNCHK BIT0
499 #define B_PCH_DMI17_PCR_PIDECCTL_CPLBNCHK_OFFSET 0
500
501 #define R_PCH_DMI17_PCR_G5L0SCTL 0x1E00
502 #define B_PCH_DMI17_PCR_G5L0SCTL_G5UCNFTS_MASK 0xFF00
503 #define B_PCH_DMI17_PCR_G5L0SCTL_G5UCNFTS_OFFSET 8
504 #define V_PCH_DMI17_PCR_G5L0SCTL_G5UCNFTS 0xFF
505 #define B_PCH_DMI17_PCR_G5L0SCTL_G5CCNFTS_MASK 0xFF
506 #define B_PCH_DMI17_PCR_G5L0SCTL_G5CCNFTS_OFFSET 0
507 #define V_PCH_DMI17_PCR_G5L0SCTL_G5CCNFTS 0xE6
508
509 #define R_PCH_DMI17_PCR_DCAP 0x2044
510 #define B_PCH_DMI17_PCR_DCAP_MPS_MASK (BIT2 | BIT1 | BIT0)
511 #define B_PCH_DMI17_PCR_DCAP_MPS_OFFSET 0
512 #define V_PCH_DMI17_PCR_DCAP_MPS_256 0x1
513
514 #define R_PCH_DMI17_PCR_CMD 0x2004
515 #define B_PCH_DMI17_PCR_CMD_SEE BIT8
516
517 #define R_PCH_DMI17_PCR_BCTRL 0x203E
518 #define B_PCH_DMI17_PCR_BCTRL_SE BIT1
519
520 #define R_PCH_DMI17_PCR_DCTL 0x2048
521 #define B_PCH_DMI17_PCR_DCTL_MPS_MASK (BIT7 | BIT6 | BIT5)
522 #define B_PCH_DMI17_PCR_DCTL_MPS_OFFSET 5
523 #define V_PCH_DMI17_PCR_DCTL_MPS_256 0x1
524 #define B_PCH_DMI17_PCR_DCTL_URE BIT3
525 #define B_PCH_DMI17_PCR_DCTL_URE_OFFSET 3
526 #define B_PCH_DMI17_PCR_DCTL_FEE BIT2
527 #define B_PCH_DMI17_PCR_DCTL_FEE_OFFSET 2
528 #define B_PCH_DMI17_PCR_DCTL_NFE BIT1
529 #define B_PCH_DMI17_PCR_DCTL_NFE_OFFSET 1
530 #define B_PCH_DMI17_PCR_DCTL_CEE BIT0
531 #define B_PCH_DMI17_PCR_DCTL_CEE_OFFSET 0
532
533 #define R_PCH_DMI17_PCR_DCAP2 0x2064
534 #define B_PCH_DMI17_PCR_DCAP2_PX10BTRS BIT17
535 #define B_PCH_DMI17_PCR_DCAP2_PX10BTRS_OFFSET 17
536 #define B_PCH_DMI17_PCR_DCAP2_PX10BTCS BIT16
537 #define B_PCH_DMI17_PCR_DCAP2_PX10BTCS_OFFSET 16
538 #define B_PCH_DMI17_PCR_DCAP2_AC64BS BIT8
539 #define B_PCH_DMI17_PCR_DACP2_AC64BS_OFFSET 8
540 #define B_PCH_DMI17_PCR_DCAP2_AC32BS BIT7
541 #define B_PCH_DMI17_PCR_DCAP2_AC32BS_OFFSET 7
542 #define B_PCH_DMI17_PCR_DCAP2_ARS BIT6
543 #define B_PCH_DMI17_PCR_DCAP2_ARS_OFFSET 6
544
545 #define R_PCH_DMI17_PCR_DCTL2 0x2068
546 #define B_PCH_DMI17_PCR_DCTL2_PX10BTRE BIT11
547 #define B_PCH_DMI17_PCR_DCTL2_PX10BTRE_OFFSET 11
548 #define B_PCH_DMI17_PCR_DCTL2_AEB BIT7
549 #define B_PCH_DMI17_PCR_DCTL2_AEB_OFFSET 7
550 #define B_PCH_DMI17_PCR_DCTL2_ARE BIT6
551 #define B_PCH_DMI17_PCR_DCTL2_ARE_OFFSET 6
552
553 #define R_PCH_DMI17_PCR_LCAP 0x204C
554 #define B_PCH_DMI17_PCR_LCAP_ASPMOC BIT22
555 #define B_PCH_DMI17_PCR_LCAP_ASPMOC_OFFSET 22
556 #define B_PCH_DMI17_PCR_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15)
557 #define B_PCH_DMI17_PCR_LCAP_EL1_OFFSET 15
558 #define V_PCH_DMI17_PCR_LCAP_EL1 0x6
559 #define B_PCH_DMI17_PCR_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12)
560 #define B_PCH_DMI17_PCR_LCAP_EL0_OFFSET 12
561 #define V_PCH_DMI17_PCR_LCAP_EL0 0x4
562 #define B_PCH_DMI17_PCR_LCAP_APMS_MASK (BIT11 | BIT10)
563 #define B_PCH_DMI17_PCR_LCAP_APMS_OFFSET 10
564 #define V_PCH_DMI17_PCR_LCAP_APMS_DIS 0x0
565 #define V_PCH_DMI17_PCR_LCAP_APMS_L0S 0x1
566 #define V_PCH_DMI17_PCR_LCAP_APMS_L1 0x2
567 #define V_PCH_DMI17_PCR_LCAP_APMS_L0SL1 0x3
568
569 #define R_PCH_DMI17_PCR_LCAP2 0x206C ///< Link Capabilities 2
570 #define R_PCH_DMI17_PCR_LCTL2 0x2070 ///< Link Control 2
571
572 #define R_PCH_DMI17_PCR_CCFG 0x20D0
573 #define B_PCH_DMI17_PCR_CCFG_UPMWPD BIT25
574 #define B_PCH_DMI17_PCR_CCFG_UPMWPD_OFFSET 25
575 #define B_PCH_DMI17_PCR_CCFG_UPSD BIT24
576 #define B_PCH_DMI17_PCR_CCFG_UPSD_OFFSET 24
577 #define B_PCH_DMI17_PCR_CCFG_UNRD BIT12
578 #define B_PCH_DMI17_PCR_CCFG_UNRD_OFFSET 12
579 #define B_PCH_DMI17_PCR_CCFG_UNRD_MASK 0x3000
580
581 #define R_PCH_DMI17_PCR_MPC2 0x20D4
582 #define B_PCH_DMI17_PCR_MPC2_L1SSESE BIT30
583 #define B_PCH_DMI17_PCR_MPC2_ORCE_MASK (BIT15 | BIT14)
584 #define B_PCH_DMI17_PCR_MPC2_ORCE_OFFSET 14
585 #define V_PCH_DMI17_PCR_MPC2_ORCE 0x0
586 #define B_PCH_DMI17_PCR_MPC2_PTNFAE BIT12
587 #define B_PCH_DMI17_PCR_MPC2_LSTP BIT6
588 #define B_PCH_DMI17_PCR_MPC2_EOIFD BIT1
589
590 #define R_PCH_DMI17_PCR_MPC 0x20D8
591 #define B_PCH_DMI17_PCR_MPC_IRRCE BIT25
592 #define B_PCH_DMI17_PCR_MPC_IRRCE_OFFSET 25
593 #define B_PCH_DMI17_PCR_MPC_FCDL1E BIT21
594 #define B_PCH_DMI17_PCR_MPC_CCEL_MASK (BIT17 | BIT16 | BIT15)
595 #define B_PCH_DMI17_PCR_MPC_CCEL_OFFSET 15
596 #define V_PCH_DMI17_PCR_MPC_CCEL 0x4
597 #define B_PCH_DMI17_PCR_MPC_BT BIT2
598 #define B_PCH_DMI17_PCR_MPC_BT_OFFSET 2
599
600 #define R_PCH_DMI17_PCR_PWRCTL 0x20E8
601 #define B_PCH_DMI17_PCR_PWRCTL_DARECE BIT28
602 #define B_PCH_DMI17_PCR_PWRCTL_LIFECF BIT23
603 #define B_PCH_DMI17_PCR_PWRCTL_WPDMPGEP BIT17
604 #define B_PCH_DMI17_PCR_PWRCTL_TXSWING BIT13
605
606 #define R_PCH_DMI17_PCR_DC 0x20EC
607 #define B_PCH_DMI17_PCR_DC_DCT1C BIT15
608 #define B_PCH_DMI17_PCR_DC_DCT1C_OFFSET 15
609 #define B_PCH_DMI17_PCR_DC_DCT0C BIT14
610 #define B_PCH_DMI17_PCR_DC_DCT0C_OFFSET 14
611 #define B_PCH_DMI17_PCR_DC_COM BIT13
612 #define B_PCH_DMI17_PCR_DC_COM_OFFSET 13
613
614 #define R_PCH_DMI17_PCR_IPCS 0x20F0
615 #define B_PCH_DMI17_PCR_IPCS_IMPS BIT8
616 #define B_PCH_DMI17_PCR_IPCS_IMPS_OFFSET 8
617 #define B_PCH_DMI17_PCR_IPCS_IMPS_MASK 0x700
618 #define V_PCH_DMI17_PCR_IPCS_IMPS 0x1
619
620 #define R_PCH_DMI17_PCR_STRPFUSECFG 0x20FC
621 #define B_PCH_DMI17_PCR_STRPFUSECFG_SERM BIT29
622 #define B_PCH_DMI17_PCR_STRPFUSECFG_SERM_OFFSET 29
623 #define B_PCH_DMI17_PCR_STRPFUSECFG_PXIP_MASK (BIT27 | BIT26 | BIT25 | BIT24)
624 #define B_PCH_DMI17_PCR_STRPFUSECFG_PXIP_OFFSET 24
625 #define V_PCH_DMI17_PCR_STRPFUSECFG_PXIP 0x0
626
627 #define R_PCH_DMI17_PCR_AECH 0x2100
628 #define B_PCH_DMI17_PCR_AECH_CID_MASK 0xFFFF
629 #define B_PCH_DMI17_PCR_AECH_CID_OFFSET 0
630 #define V_PCH_DMI17_PCR_AECH_CID 0x1
631 #define B_PCH_DMI17_PCR_AECH_CV_MASK (BIT19 | BIT18 | BIT17 | BIT16)
632 #define B_PCH_DMI17_PCR_AECH_CV_OFFSET 16
633 #define V_PCH_DMI17_PCR_AECH_CV 0x1
634 #define B_PCH_DMI17_PCR_AECH_NCO_MASK 0xFFF00000
635 #define B_PCH_DMI17_PCR_AECH_NCO_OFFSET 20
636 #define V_PCH_DMI17_PCR_AECH_NCO 0x280
637
638 #define R_PCH_DMI17_PCR_VCCH 0x2280
639 #define B_PCH_DMI17_PCR_VCCH_CID_MASK 0xFFFF
640 #define B_PCH_DMI17_PCR_VCCH_CID_OFFSET 0
641 #define V_PCH_DMI17_PCR_VCCH_CID_3_VC 0x2
642 #define B_PCH_DMI17_PCR_VCCH_CV_MASK (BIT19 | BIT18 | BIT17 | BIT16)
643 #define B_PCH_DMI17_PCR_VCCH_CV_OFFSET 16
644 #define V_PCH_DMI17_PCR_VCCH_CV_3_VC 0x1
645 #define B_PCH_DMI17_PCR_VCCH_NCO_MASK 0xFFF00000
646 #define B_PCH_DMI17_PCR_VCCH_NCO_OFFSET 20
647 #define V_PCH_DMI17_PCR_VCCH_NCO 0xA30
648
649 #define R_PCH_DMI17_PCR_L1SCAP 0x2204
650 #define B_PCH_DMI17_PCR_L1SCAP_L1PSS BIT4
651 #define B_PCH_DMI17_PCR_L1SCAP_AL11S BIT3
652 #define B_PCH_DMI17_PCR_L1SCAP_AL12S BIT2
653 #define B_PCH_DMI17_PCR_L1SCAP_PPL11S BIT1
654 #define B_PCH_DMI17_PCR_L1SCAP_PPL12S BIT0
655
656 #define R_PCH_DMI17_PCR_PVCCR1 0x2284
657 #define B_PCH_DMI17_PCR_PVCCR1_EVCC_MASK (BIT2 | BIT1 | BIT0)
658 #define B_PCH_DMI17_PCR_PVCCR1_EVCC_OFFSET 0
659 #define V_PCH_DMI17_PCR_PVCCR1_EVCC_2_VC 0x1
660 #define V_PCH_DMI17_PCR_PVCCR1_EVCC_3_VC 0x2
661
662 #define R_PCH_DMI17_PCR_V0VCRC 0x2290
663 #define B_PCH_DMI17_PCR_V0VCRC_MTS_MASK 0x7F0000
664
665 #define R_PCH_DMI17_PCR_V0CTL 0x2294
666 #define B_PCH_DMI17_PCR_V0CTL_TVM_MASK 0xFE
667 #define V_PCH_DMI17_PCR_V0CTL_ETVM_MASK 0xFC00
668 #define B_PCH_DMI17_PCR_V0CTL_TVM_OFFSET 1
669 #define V_PCH_DMI17_PCR_V0CTL_TVM_NO_VC 0x7F
670 #define V_PCH_DMI17_PCR_V0CTL_TVM_EN_VC 0x3E
671
672 #define R_PCH_DMI17_PCR_V0STS 0x229A
673
674 #define R_PCH_DMI17_PCR_V1VCRC 0x229C
675 #define B_PCH_DMI17_PCR_V1VCRC_MTS_MASK 0x7F0000
676
677 #define R_PCH_DMI17_PCR_V1CTL 0x22A0
678 #define B_PCH_DMI17_PCR_V1CTL_TVM_MASK 0xFE
679 #define B_PCH_DMI17_PCR_V1CTL_TVM BIT1
680 #define B_PCH_DMI17_PCR_V1CTL_TVM_OFFSET 1
681 #define V_PCH_DMI17_PCR_V1CTL_TVM_EN_VC 0x60
682 #define B_PCH_DMI17_PCR_V1CTL_ID_MASK 0xF000000
683 #define B_PCH_DMI17_PCR_V1CTL_ID_OFFSET 24
684 #define V_PCH_DMI17_PCR_V1CTL_ID_ONE 1
685 #define B_PCH_DMI17_PCR_V1CTL_EN_MASK 0x80000000
686 #define B_PCH_DMI17_PCR_V1CTL_EN BIT31
687
688 #define R_PCH_DMI17_PCR_V1STS 0x22A6
689
690 #define R_PCH_DMI17_PCR_VMCTL 0x22B0
691 #define B_PCH_DMI17_PCR_VMCTL_TVM_MASK 0xFE
692 #define B_PCH_DMI17_PCR_VMCTL_TVM BIT7
693 #define B_PCH_DMI17_PCR_VMCTL_ID_MASK 0xF000000
694 #define B_PCH_DMI17_PCR_VMCTL_ID_OFFSET 24
695 #define V_PCH_DMI17_PCR_VMCTL_ID_TWO 7
696 #define B_PCH_DMI17_PCR_VMCTL_EN_MASK 0x80000000
697 #define B_PCH_DMI17_PCR_VMCTL_EN BIT31
698
699 #define R_PCH_DMI17_PCR_VMSTS 0x22B6
700
701 #define R_PCH_DMI17_PCR_PCIERTP1 0x2300
702 #define B_PCH_DMI17_PCR_PCIERTP1_G2X1_MASK (BIT23 | BIT22 | BIT21 | BIT20)
703 #define B_PCH_DMI17_PCR_PCIERTP1_G2X1_OFFSET 20
704 #define V_PCH_DMI17_PCR_PCIERTP1_G2X1 0xB
705 #define B_PCH_DMI17_PCR_PCIERTP1_G2X2_MASK (BIT19 | BIT18 | BIT17 | BIT16)
706 #define B_PCH_DMI17_PCR_PCIERTP1_G2X2_OFFSET 16
707 #define V_PCH_DMI17_PCR_PCIERTP1_G2X2 0x7
708 #define B_PCH_DMI17_PCR_PCIERTP1_G2X4_MASK (BIT15 | BIT14 | BIT13 | BIT12)
709 #define B_PCH_DMI17_PCR_PCIERTP1_G2X4_OFFSET 12
710 #define V_PCH_DMI17_PCR_PCIERTP1_G2X4 0xE
711 #define B_PCH_DMI17_PCR_PCIERTP1_G1X1_MASK (BIT11 | BIT10 | BIT9 | BIT8)
712 #define B_PCH_DMI17_PCR_PCIERTP1_G1X1_OFFSET 8
713 #define V_PCH_DMI17_PCR_PCIERTP1_G1X1 0x5
714 #define B_PCH_DMI17_PCR_PCIERTP1_G1X2_MASK (BIT7 | BIT6 | BIT5 | BIT4)
715 #define B_PCH_DMI17_PCR_PCIERTP1_G1X2_OFFSET 4
716 #define V_PCH_DMI17_PCR_PCIERTP1_G1X2 0xB
717 #define B_PCH_DMI17_PCR_PCIERTP1_G1X4_MASK (BIT3 | BIT2 | BIT1 | BIT0)
718 #define B_PCH_DMI17_PCR_PCIERTP1_G1X4_OFFSET 0
719 #define V_PCH_DMI17_PCR_PCIERTP1_G1X4 0x0
720
721 #define R_PCH_DMI17_PCR_G4L0SCTL 0x2310
722 #define B_PCH_DMI17_PCR_G4L0SCTL_G4ASL0SPL_MASK 0xFF000000
723 #define B_PCH_DMI17_PCR_G4L0SCTL_G4ASL0SPL_OFFSET 24
724 #define V_PCH_DMI17_PCR_G4L0SCTL_G4ASL0SPL 0x28
725 #define B_PCH_DMI17_PCR_G4L0SCTL_G4L0SIC_MASK (BIT23 | BIT22)
726 #define B_PCH_DMI17_PCR_G4L0SCTL_G4L0SIC_OFFSET 22
727 #define V_PCH_DMI17_PCR_G4L0SCTL_G4L0SIC 0x3
728 #define B_PCH_DMI17_PCR_G4L0SCTL_G4UCNFTS_MASK 0xFF00
729 #define B_PCH_DMI17_PCR_G4L0SCTL_G4UCNFTS_OFFSET 8
730 #define V_PCH_DMI17_PCR_G4L0SCTL_G4UCNFTS 0x80
731 #define B_PCH_DMI17_PCR_G4L0SCTL_G4CCNFTS_MASK 0xFF
732 #define B_PCH_DMI17_PCR_G4L0SCTL_G4CCNFTS_OFFSET 0
733 #define V_PCH_DMI17_PCR_G4L0SCTL_G4CCNFTS 0x5B
734
735 #define R_PCH_DMI17_PCR_PCIENFTS 0x2314
736 #define B_PCH_DMI17_PCR_PCIENFTS_G2UCNFTS_MASK 0xFF000000
737 #define B_PCH_DMI17_PCR_PCIENFTS_G2UCNFTS_OFFSET 24
738 #define V_PCH_DMI17_PCR_PCIENFTS_G2UCNFTS 0x7E
739 #define B_PCH_DMI17_PCR_PCIENFTS_G2CCNFTS_MASK 0xFF0000
740 #define B_PCH_DMI17_PCR_PCIENFTS_G2CCNFTS_OFFSET 16
741 #define V_PCH_DMI17_PCR_PCIENFTS_G2CCNFTS 0x5B
742 #define B_PCH_DMI17_PCR_PCIENFTS_G1UCNFTS_MASK 0xFF00
743 #define B_PCH_DMI17_PCR_PCIENFTS_G1UCNFTS_OFFSET 8
744 #define V_PCH_DMI17_PCR_PCIENFTS_G1UCNFTS 0x3F
745 #define B_PCH_DMI17_PCR_PCIENFTS_G1CCNFTS_MASK 0xFF
746 #define B_PCH_DMI17_PCR_PCIENFTS_G1CCNFTS_OFFSET 0
747 #define V_PCH_DMI17_PCR_PCIENFTS_G1CCNFTS 0x2C
748
749 #define R_PCH_DMI17_PCR_PCIECFG2 0x2320
750 #define B_PCH_DMI17_PCR_PCIECFG2_RLLG3R BIT27
751 #define B_PCH_DMI17_PCR_PCIECFG2_RLLG3R_OFFSET 27
752 #define B_PCH_DMI17_PCR_PCIECFG2_CROAOV BIT24
753 #define B_PCH_DMI17_PCR_PCIECFG2_CROAOE BIT23
754 #define B_PCH_DMI17_PCR_PCIECFG2_CRSREN BIT22
755 #define B_PCH_DMI17_PCR_PCIECFG2_CRSREN_OFFSET 22
756 #define B_PCH_DMI17_PCR_PCIECFG2_PMET_MASK (BIT21 | BIT20)
757 #define B_PCH_DMI17_PCR_PCIECFG2_PMET_OFFSET 20
758 #define V_PCH_DMI17_PCR_PCIECFG2_PMET 0x1
759 #define B_PCH_DMI17_PCR_PCIECFG2_DTCA BIT4
760 #define B_PCH_DMI17_PCR_PCIECFG2_DTCA_OFFSET 4
761
762 #define R_PCH_DMI17_PCR_PCIEDBG 0x2324
763 #define B_PCH_DMI17_PCR_PCIEDBG_USSP_MASK (BIT27 | BIT26)
764 #define B_PCH_DMI17_PCR_PCIEDBG_USSP_OFFSET 26
765 #define V_PCH_DMI17_PCR_PCIEDBG_USSP 0x01
766 #define B_PCH_DMI17_PCR_PCIEDBG_LGCLKSQEXITDBTIMERS_MASK (BIT25 | BIT24)
767 #define B_PCH_DMI17_PCR_PCIEDBG_LGCLKSQEXITDBTIMERS_OFFSET 24
768 #define V_PCH_DMI17_PCR_PCIEDBG_LGCLKSQEXITDBTIMERS 0x00
769 #define B_PCH_DMI17_PCR_PCIEDBG_CTONFAE BIT14
770 #define B_PCH_DMI17_PCR_PCIEDBG_CTONFAE_OFFSET 14
771 #define B_PCH_DMI17_PCR_PCIEDBG_LDSWQRP BIT13
772 #define B_PCH_DMI17_PCR_PCIEDBG_LDSWQRP_OFFSET 13
773 #define B_PCH_DMI17_PCR_PCIEDBG_SPCE BIT5
774 #define B_PCH_DMI17_PCR_PCIEDBG_SPCE_OFFSET 5
775 #define B_PCH_DMI17_PCR_PCIEDBG_DTCA BIT4
776 #define B_PCH_DMI17_PCR_PCIEDBG_DTCA_OFFSET 4
777
778 #define R_PCH_DMI17_PCR_PCIEALC 0x2338
779 #define B_PCH_DMI17_PCR_PCIEALC_ITLRCLD BIT29
780 #define B_PCH_DMI17_PCR_PCIEALC_ITLRCLD_OFFSET 29
781 #define B_PCH_DMI17_PCR_PCIEALC_ILLRCLD BIT28
782 #define B_PCH_DMI17_PCR_PCIEALC_ILLRCLD_OFFSET 28
783 #define B_PCH_DMI17_PCR_PCIEALC_SSRLD BIT24
784 #define B_PCH_DMI17_PCR_PCIEALC_SSRLD_OFFSET 24
785 #define B_PCH_DMI17_PCR_PCIEALC_SSRRS BIT23
786 #define B_PCH_DMI17_PCR_PCIEALC_SSRRS_OFFSET 23
787 #define B_PCH_DMI17_PCR_PCIEALC_RTD3PDSP BIT21
788 #define B_PCH_DMI17_PCR_PCIEALC_RTD3PDSP_OFFSET 21
789 #define B_PCH_DMI17_PCR_PCIEALC_PDSP BIT20
790 #define B_PCH_DMI17_PCR_PCIEALC_PDSP_OFFSET 20
791
792 #define R_PCH_DMI17_PCR_LTROVR2 0x2404
793 #define B_PCH_DMI17_PCR_LTROVR2_LTRNSOVREN BIT1
794 #define B_PCH_DMI17_PCR_LTROVR2_LTRSOVREN BIT0
795
796 #define R_PCH_DMI17_PCR_PCIEPMECTL 0x2420
797 #define B_PCH_DMI17_PCR_PCIEPMECTL_DLSULPPGE BIT30
798 #define B_PCH_DMI17_PCR_PCIEPMECTL_DLSULPPGE_OFFSET 30
799 #define B_PCH_DMI17_PCR_PCIEPMECTL_DLSULDLSD BIT29
800 #define B_PCH_DMI17_PCR_PCIEPMECTL_DLSULDLSD_OFFSET 29
801 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLSV (BIT16 | BIT15 | BIT14)
802 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLSV_OFFSET 14
803 #define V_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLSV 0x2
804 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLV 0x3FF0
805 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLV_OFFSET 4
806 #define V_PCH_DMI17_PCR_PCIEPMECTL_L1LTRTLV 0x32
807 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1FSOE BIT0
808 #define B_PCH_DMI17_PCR_PCIEPMECTL_L1FSOE_OFFSET 0
809
810 #define R_PCH_DMI17_PCR_STRPFUSECFG2 0x2414
811 #define B_PCH_DMI17_PCR_STRPFUSECFG2 (BIT9 | BIT8 | BIT7)
812 #define N_PCH_DMI17_PCR_STRPFUSECFG2 7
813
814 #define R_PCH_DMI17_PCR_PCIEPMECTL2 0x2424
815 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPMCSRE BIT27
816 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPMCSRE_OFFSET 27
817 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPGEXH_MASK (BIT15 | BIT14)
818 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPGEXH_OFFSET 14
819 #define V_PCH_DMI17_PCR_PCIEPMECTL2_CPGEXH 0x0
820 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPGENH_MASK (BIT13 | BIT12)
821 #define B_PCH_DMI17_PCR_PCIEPMECTL2_CPGENH_OFFSET 12
822 #define V_PCH_DMI17_PCR_PCIEPMECTL2_CPGENH 0x0
823
824 #define R_PCH_DMI17_PCR_PGCBCTL1 0x242C
825 #define B_PCH_DMI17_PCR_PGCBCTL1_TACCRSTUP_MASK (BIT11 | BIT10)
826 #define B_PCH_DMI17_PCR_PGCBCTL1_TACCRSTUP_OFFSET 10
827 #define V_PCH_DMI17_PCR_PGCBCTL1_TACCRSTUP 0x3
828
829 #define R_PCH_DMI17_PCR_PME_CTL3 0x2434
830 #define B_PCH_DMI17_PCR_PME_CTL3_L1PGAUTOPGEN BIT4
831 #define B_PCH_DMI17_PCR_PME_CTL3_L1PGAUTOPGEN_OFFSET 4
832 #define B_PCH_DMI17_PCR_PME_CTL3_OSCCGH (BIT3 | BIT2)
833 #define N_PCH_DMI17_PCR_PME_CTL3_OSCCGH 2
834 #define B_PCH_DMI17_PCR_PME_CTL3_OSCCGH_OFFSET 2
835 #define V_PCH_DMI17_PCR_PME_CTL3_OSCCGH_0US 0x0
836 #define V_PCH_DMI17_PCR_PME_CTL3_OSCCGH_1US 0x1
837 #define B_PCH_DMI17_PCR_PME_CTL3_PMREQCPGEXH_MASK (BIT1 | BIT0)
838 #define B_PCH_DMI17_PCR_PME_CTL3_PMREQCPGEXH_OFFSET 0
839 #define V_PCH_DMI17_PCR_PME_CTL3_PMREQCPGEXH 0x0
840
841 #define R_PCH_DMI17_PCR_EQCFG1 0x2450
842 #define B_PCH_DMI17_PCR_EQCFG1_LERSMIE BIT21
843 #define B_PCH_DMI17_PCR_EQCFG1_RTLEPCEB BIT16
844 #define B_PCH_DMI17_PCR_EQCFG1_RTPCOE BIT15
845 #define B_PCH_DMI17_PCR_EQCFG1_RWTNEVE_MASK (BIT11 | BIT10 | BIT9 | BIT8)
846 #define B_PCH_DMI17_PCR_EQCFG1_RWTNEVE_OFFSET 8
847 #define V_PCH_DMI17_PCR_EQCFG1_RWTNEVE 0x1
848 #define B_PCH_DMI17_PCR_EQCFG1_HAPCCPIE BIT5
849 #define B_PCH_DMI17_PCR_EQCFG1_TUPP BIT1
850
851 #define R_PCH_DMI17_PCR_RTPCL1 0x2454
852 #define N_PCH_DMI17_PCR_RTPCL1_RTPRECL2PL4 24
853 #define N_PCH_DMI17_PCR_RTPCL1_RTPOSTCL1PL3 18
854 #define N_PCH_DMI17_PCR_RTPCL1_RTPRECL1PL2 12
855 #define N_PCH_DMI17_PCR_RTPCL1_RTPOSTCL0PL1 6
856 #define N_PCH_DMI17_PCR_RTPCL1_RTPRECL0PL0 0
857 #define B_PCH_DMI17_PCR_RTPCL1_PCM BIT31
858 #define B_PCH_DMI17_PCR_RTPCL1_RTPRECL2PL4 (0x3F << N_PCH_DMI17_PCR_RTPCL1_RTPRECL2PL4)
859 #define B_PCH_DMI17_PCR_RTPCL1_RTPOSTCL1PL3 (0x3F << N_PCH_DMI17_PCR_RTPCL1_RTPOSTCL1PL3)
860 #define B_PCH_DMI17_PCR_RTPCL1_RTPRECL1PL2 (0x3F << N_PCH_DMI17_PCR_RTPCL1_RTPRECL1PL2)
861 #define B_PCH_DMI17_PCR_RTPCL1_RTPOSTCL0PL1 (0x3F << N_PCH_DMI17_PCR_RTPCL1_RTPOSTCL0PL1)
862 #define B_PCH_DMI17_PCR_RTPCL1_RTPRECL0PL0 (0x3F << N_PCH_DMI17_PCR_RTPCL1_RTPRECL0PL0)
863
864 #define R_PCH_DMI17_PCR_RTPCL2 0x2458
865 #define N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL4PL9 24
866 #define N_PCH_DMI17_PCR_RTPCL2_RTPRECL4PL8 18
867 #define N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL3PL7 12
868 #define N_PCH_DMI17_PCR_RTPCL2_RTPRECL3PL6 6
869 #define N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL2PL5 0
870 #define B_PCH_DMI17_PCR_RTPCL2_RTPOSTCL4PL9 (0x3F << N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL4PL9)
871 #define B_PCH_DMI17_PCR_RTPCL2_RTPRECL4PL8 (0x3F << N_PCH_DMI17_PCR_RTPCL2_RTPRECL4PL8)
872 #define B_PCH_DMI17_PCR_RTPCL2_RTPOSTCL3PL7 (0x3F << N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL3PL7)
873 #define B_PCH_DMI17_PCR_RTPCL2_RTPRECL3PL6 (0x3F << N_PCH_DMI17_PCR_RTPCL2_RTPRECL3PL6)
874 #define B_PCH_DMI17_PCR_RTPCL2_RTPOSTCL2PL5 (0x3F << N_PCH_DMI17_PCR_RTPCL2_RTPOSTCL2PL5)
875
876 #define R_PCH_DMI17_PCR_FOMS 0x2464
877 #define B_PCH_DMI17_PCR_FOMS_I (BIT31 | BIT30 | BIT29)
878 #define B_PCH_DMI17_PCR_FOMS_I_OFFSET 29
879 #define B_PCH_DMI17_PCR_FOMS_LN 0x1F000000
880 #define B_PCH_DMI17_PCR_FOMS_LN_OFFSET 24
881 #define B_PCH_DMI17_PCR_FOMS_FOMSV 0x00FFFFFF
882 #define B_PCH_DMI17_PCR_FOMS_FOMSV0 0x000000FF
883 #define B_PCH_DMI17_PCR_FOMS_FOMSV0_OFFSET 0
884 #define B_PCH_DMI17_PCR_FOMS_FOMSV1 0x0000FF00
885 #define B_PCH_DMI17_PCR_FOMS_FOMSV1_OFFSET 8
886 #define B_PCH_DMI17_PCR_FOMS_FOMSV2 0x00FF0000
887 #define B_PCH_DMI17_PCR_FOMS_FOMSV2_OFFSET 16
888
889 #define R_PCH_DMI17_PCR_HAEQ 0x2468
890 #define B_PCH_DMI17_PCR_HAEQ_HAPCCPI_MASK 0xF0000000
891 #define B_PCH_DMI17_PCR_HAEQ_HAPCCPI_OFFSET 28
892 #define V_PCH_DMI17_PCR_HAEQ_HAPCCPI 0x0
893 #define B_PCH_DMI17_PCR_HAEQ_MACFOMC BIT19
894 #define B_PCH_DMI17_PCR_HAEQ_DL_MASK 0xFF00
895 #define B_PCH_DMI17_PCR_HAEQ_DL_OFFSET 8
896 #define V_PCH_DMI17_PCR_HAEQ_DL 0xE
897
898 #define R_PCH_DMI17_PCR_G3L0SCTL 0x2478
899 #define B_PCH_DMI17_PCR_G3L0SCTL_G3ASL0SPL_MASK 0xFF000000
900 #define B_PCH_DMI17_PCR_G3L0SCTL_G3ASL0SPL_OFFSET 24
901 #define V_PCH_DMI17_PCR_G3L0SCTL_G3ASL0SPL 0x28
902 #define B_PCH_DMI17_PCR_G3L0SCTL_G3UCNFTS_MASK 0xFF00
903 #define B_PCH_DMI17_PCR_G3L0SCTL_G3UCNFTS_OFFSET 8
904 #define V_PCH_DMI17_PCR_G3L0SCTL_G3UCNFTS 0x40
905 #define B_PCH_DMI17_PCR_G3L0SCTL_G3CCNFTS_MASK 0xFF
906 #define B_PCH_DMI17_PCR_G3L0SCTL_G3CCNFTS_OFFSET 0
907 #define V_PCH_DMI17_PCR_G3L0SCTL_G3CCNFTS 0x2C
908
909 #define R_PCH_DMI17_PCR_EQCFG2 0x247C
910 #define B_PCH_DMI17_PCR_EQCFG2_PCET_MASK 0xF0000
911 #define B_PCH_DMI17_PCR_EQCFG2_PCET_OFFSET 16
912 #define V_PCH_DMI17_PCR_EQCFG2_PCET 0x2
913 #define B_PCH_DMI17_PCR_EQCFG2_HAPCSB_MASK 0xF000
914 #define B_PCH_DMI17_PCR_EQCFG2_HAPCSB_OFFSET 12
915 #define V_PCH_DMI17_PCR_EQCFG2_HAPCSB 0x2
916 #define B_PCH_DMI17_PCR_EQCFG2_REWMET_MASK 0xFF
917 #define B_PCH_DMI17_PCR_EQCFG2_REWMET_OFFSET 0
918 #define V_PCH_DMI17_PCR_EQCFG2_REWMET 0x10
919
920 #define R_PCH_DMI17_PCR_EQCFG4 0x248C
921 #define B_PCH_DMI17_PCR_EQCFG4_FOMSCP_MASK (BIT23 | BIT22 | BIT21)
922 #define B_PCH_DMI17_PCR_EQCFG4_FOMSCP_OFFSET 21
923 #define B_PCH_DMI17_PCR_EQCFG4_PX16GRTLEPCEB BIT16
924 #define B_PCH_DMI17_PCR_EQCFG4_PX16GRTPCOE BIT15
925 #define B_PCH_DMI17_PCR_EQCFG4_PX16GRWTNEVE_MASK 0xF00
926 #define B_PCH_DMI17_PCR_EQCFG4_PX16GRWTNEVE_OFFSET 8
927 #define V_PCH_DMI17_PCR_EQCFG4_PX16GRWTNEVE 0x3
928 #define B_PCH_DMI17_PCR_EQCFG4_PX16GHAPCCPI_MASK 0xF0
929 #define B_PCH_DMI17_PCR_EQCFG4_PX16GHAPCCPI_OFFSET 3
930 #define V_PCH_DMI17_PCR_EQCFG4_PX16GHAPCCPI 0x2
931
932 #define R_PCH_DMI17_PCR_CTRL2 0x24A4
933 #define B_PCH_DMI17_PCR_CTRL2_RXHALEP BIT19
934 #define B_PCH_DMI17_PCR_CTRL2_HALEP BIT18
935 #define B_PCH_DMI17_PCR_CTRL2_HALEP_OFFSET 18
936 #define B_PCH_DMI17_PCR_CTRL2_PMETOFD BIT6
937 #define B_PCH_DMI17_PCR_CTRL2_PMETOFD_OFFSET 6
938
939 #define R_PCH_DMI17_PCR_IOSFC3TC 0x24C8
940 #define B_PCH_DMI17_PCR_IOSFC3TC_C0CPDC_MASK 0xFF00
941 #define B_PCH_DMI17_PCR_IOSFC3TC_C0CPDC_OFFSET 8
942 #define V_PCH_DMI17_PCR_IOSFC3TC_C0CPDC 0x4
943
944 #define R_PCH_DMI17_PCR_PX16GRTPCL1 0x24DC
945 #define N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL2PL4 24
946 #define N_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL1PL3 18
947 #define N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL1PL2 12
948 #define N_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL0PL1 6
949 #define N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL0PL0 0
950 #define B_PCH_DMI17_PCR_PX16GRTPCL1_PCM BIT31
951 #define B_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL2PL4 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL2PL4)
952 #define B_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL1PL3 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL1PL3)
953 #define B_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL1PL2 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL1PL2)
954 #define B_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL0PL1 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL1_RTPOSTCL0PL1)
955 #define B_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL0PL0 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL1_RTPRECL0PL0)
956
957 #define R_PCH_DMI17_PCR_PX16GRTPCL2 0x24E0
958 #define N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL4PL9 24
959 #define N_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL4PL8 18
960 #define N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL3PL7 12
961 #define N_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL3PL6 6
962 #define N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL2PL5 0
963 #define B_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL4PL9 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL4PL9)
964 #define B_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL4PL8 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL4PL8)
965 #define B_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL3PL7 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL3PL7)
966 #define B_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL3PL6 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL2_RTPRECL3PL6)
967 #define B_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL2PL5 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL2_RTPOSTCL2PL5)
968
969 #define R_PCH_DMI17_PCR_PX16GRTPCL3 0x24E4
970 #define N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL7 24
971 #define N_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL6 18
972 #define N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL6 12
973 #define N_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL5 6
974 #define N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL5PL10 0
975 #define B_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL7 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL7)
976 #define B_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL6 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL6)
977 #define B_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL6 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL6)
978 #define B_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL5 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL3_RTPOSTCL5)
979 #define B_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL5PL10 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL3_RTPRECL5PL10)
980
981 #define R_PCH_DMI17_PCR_PX16GRTPCL4 0x24E8
982 #define N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL9 24
983 #define N_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL9 18
984 #define N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL8 12
985 #define N_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL8 6
986 #define N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL7 0
987 #define B_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL9 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL9)
988 #define B_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL9 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL9)
989 #define B_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL8 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL8)
990 #define B_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL8 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL4_RTPRECL8)
991 #define B_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL7 (0x3F << N_PCH_DMI17_PCR_PX16GRTPCL4_RTPOSTCL7)
992
993 #define R_PCH_DMI17_PCR_EQCFG5 0x24F8
994 #define B_PCH_DMI17_PCR_EQCFG5_PCET_MASK 0xF0000
995 #define B_PCH_DMI17_PCR_EQCFG5_PCET_OFFSET 16
996 #define V_PCH_DMI17_PCR_EQCFG5_PCET 0x2
997 #define B_PCH_DMI17_PCR_EQCFG5_HAPCSB_MASK 0xF000
998 #define B_PCH_DMI17_PCR_EQCFG5_HAPCSB_OFFSET 12
999 #define V_PCH_DMI17_PCR_EQCFG5_HAPCSB 0x0
1000
1001 #define R_PCH_DMI17_PCR_L0P0P1PCM 0x2500
1002 #define R_PCH_DMI17_PCR_L0P1P2P3PCM 0x2504
1003 #define R_PCH_DMI17_PCR_L0P3P4PCM 0x2508
1004 #define R_PCH_DMI17_PCR_L0P5P6PCM 0x250C
1005 #define R_PCH_DMI17_PCR_L0P6P7P8PCM 0x2510
1006 #define R_PCH_DMI17_PCR_L0P8P9PCM 0x2514
1007 #define R_PCH_DMI17_PCR_L0P10PCM 0x2518
1008 #define R_PCH_DMI17_PCR_L0LFFS 0x251C
1009
1010 #define R_PCH_DMI17_PCR_PX16GP0P1PCM 0x2520
1011 #define R_PCH_DMI17_PCR_PX16GP1P2P3PCM 0x2524
1012 #define R_PCH_DMI17_PCR_PX16GP3P4PCM 0x2528
1013 #define R_PCH_DMI17_PCR_PX16GP5P6PCM 0x252C
1014 #define R_PCH_DMI17_PCR_PX16GP6P7P8PCM 0x2530
1015 #define R_PCH_DMI17_PCR_PX16GP8P9PCM 0x2534
1016 #define R_PCH_DMI17_PCR_PX16GP10PCM 0x2538
1017 #define R_PCH_DMI17_PCR_PX16GLFFS 0x253C
1018
1019 #define R_PCH_DMI17_PCR_COCTL 0x2594
1020 #define B_PCH_DMI17_PCR_COCTL_NPCLM_MASK (BIT16 | BIT15)
1021 #define B_PCH_DMI17_PCR_COCTL_NPCLM_OFFSET 13
1022 #define V_PCH_DMI17_PCR_COCTL_NPCLM 0x2
1023 #define B_PCH_DMI17_PCR_COCTL_PCLM_MASK (BIT14 | BIT13)
1024 #define B_PCH_DMI17_PCR_COCTL_PCLM_OFFSET 13
1025 #define V_PCH_DMI17_PCR_COCTL_PCLM 0x2
1026 #define B_PCH_DMI17_PCR_COCTL_ROAOP BIT11
1027 #define B_PCH_DMI17_PCR_COCTL_ROAOP_OFFSET 11
1028
1029 #define R_PCH_DMI17_PCR_ADVMCTRL 0x25BC
1030 #define B_PCH_DMI17_PCR_ADVMCTRL_F10BTSE BIT24
1031 #define B_PCH_DMI17_PCR_ADVMCTRL_F10BTSE_OFFSET 24
1032 #define B_PCH_DMI17_PCR_ADVMCTRL_CCBE BIT23
1033 #define B_PCH_DMI17_PCR_ADVMCTRL_CCBE_OFFSET 23
1034 #define B_PCH_DMI17_PCR_ADVMCTRL_INRXL0CTRL BIT22
1035 #define B_PCH_DMI17_PCR_ADVMCTRL_INRXL0CTRL_OFFSET 22
1036 #define B_PCH_DMI17_PCR_ADVMCTRL_ACCRM BIT21
1037 #define B_PCH_DMI17_PCR_ADVMCTRL_ACCRM_OFFSET 21
1038 #define B_PCH_DMI17_PCR_ADVMCTRL_EIOSDISDS BIT20
1039 #define B_PCH_DMI17_PCR_ADVMCTRL_EIOSDISDS_OFFSET 20
1040 #define B_PCH_DMI17_PCR_ADVMCTRL_EIOSMASKRX BIT19
1041 #define B_PCH_DMI17_PCR_ADVMCTRL_EIOSMASKRX_OFFSET 19
1042 #define B_PCH_DMI17_PCR_ADVMCTRL_PMREQCWC (BIT18 | BIT17 | BIT16)
1043 #define B_PCH_DMI17_PCR_ADVMCTRL_PMREQCWC_OFFSET 16
1044 #define V_PCH_DMI17_PCR_ADVMCTRL_PMREQCWC 0x6
1045 #define B_PCH_DMI17_PCR_ADVMCTRL_RXL0DC BIT15
1046 #define B_PCH_DMI17_PCR_ADVMCTRL_RXL0DC_OFFSET 15
1047 #define B_PCH_DMI17_PCR_ADVMCTRL_G3STFER BIT13
1048 #define B_PCH_DMI17_PCR_ADVMCTRL_G3STFER_OFFSET 13
1049 #define B_PCH_DMI17_PCR_ADVMCTRL_RRLLCL BIT11
1050 #define B_PCH_DMI17_PCR_ADVMCTRL_RRLLCL_OFFSET 11
1051 #define B_PCH_DMI17_PCR_ADVMCTRL_RLLG12R BIT10
1052 #define B_PCH_DMI17_PCR_ADVMCTRL_RLLG12R_OFFSET 10
1053 #define B_PCH_DMI17_PCR_ADVMCTRL_PMREQBLKPGRSPT (BIT7 | BIT6 | BIT5)
1054 #define B_PCH_DMI17_PCR_ADVMCTRL_PMREQBLKPGRSPT_OFFSET 5
1055 #define V_PCH_DMI17_PCR_ADVMCTRL_PMREQBLKPGRSPT 0x2
1056
1057 #define R_PCH_DMI17_PCR_PGTHRES 0x25C0
1058 #define B_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLSV (BIT31 | BIT30 | BIT29)
1059 #define B_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLSV_OFFSET 29
1060 #define V_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLSV 0x2
1061 #define B_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLV 0x3FF0000
1062 #define B_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLV_OFFSET 16
1063 #define V_PCH_DMI17_PCR_PGTHRES_L1PGLTRTLV 0x32
1064
1065 #define R_PCH_DMI17_PCR_HWSNR 0x25F0
1066 #define B_PCH_DMI17_PCR_HWSNR_EEH_MASK (BIT9 | BIT8)
1067 #define B_PCH_DMI17_PCR_HWSNR_EEH_OFFSET 8
1068 #define V_PCH_DMI17_PCR_HWSNR_EEH 0x2
1069 #define B_PCH_DMI17_PCR_HWSNR_REPW_MASK (BIT7 | BIT6 | BIT5 | BIT4)
1070 #define B_PCH_DMI17_PCR_HWSNR_REPW_OFFSET 4
1071 #define V_PCH_DMI17_PCR_HWSNR_REPW 0x1
1072 #define B_PCH_DMI17_PCR_HWSNR_BEPW_MASK (BIT3 | BIT2 | BIT1 | BIT0)
1073 #define B_PCH_DMI17_PCR_HWSNR_BEPW_OFFSET 0
1074 #define V_PCH_DMI17_PCR_HWSNR_BEPW 0x5
1075
1076 #define R_PCH_DMI17_PCR_PGCTRL 0x25F4
1077 #define B_PCH_DMI17_PCR_PGCTRL_PMREQBLKRSPT_MASK (BIT2 | BIT1 | BIT0)
1078 #define B_PCH_DMI17_PCR_PGCTRL_PMREQBLKRSPT_OFFSET 0
1079 #define V_PCH_DMI17_PCR_PGCTRL_PMREQBLKRSPT 0x2
1080
1081 #define R_PCH_DMI17_PCR_ACRG3 0x26CC
1082 #define B_PCH_DMI17_PCR_ACRG3_RRXDME BIT27
1083 #define B_PCH_DMI17_PCR_ACRG3_RRXDME_OFFSET 27
1084 #define B_PCH_DMI17_PCR_ACRG3_CBGM BIT21
1085 #define B_PCH_DMI17_PCR_ACRG3_CBGM_OFFSET 21
1086 #define B_PCH_DMI17_PCR_ACRG3_ADESKEW_DIS BIT10
1087 #define B_PCH_DMI17_PCR_ACRG3_ADESKEW_DIS_OFFSET 10
1088
1089 #define R_PCH_DMI17_PCR_PCIERTP3 0x26A0
1090 #define B_PCH_DMI17_PCR_PCIERTP3_G1X8_MASK (BIT7 | BIT6 | BIT5 | BIT4)
1091 #define B_PCH_DMI17_PCR_PCIERTP3_G1X8_OFFSET 4
1092 #define V_PCH_DMI17_PCR_PCIERTP3_G1X8 0x5
1093 #define B_PCH_DMI17_PCR_PCIERTP3_G1X16_MASK (BIT3 | BIT2 | BIT1 | BIT0)
1094 #define B_PCH_DMI17_PCR_PCIERTP3_G1X16_OFFSET 0
1095 #define V_PCH_DMI17_PCR_PCIERTP3_G1X16 0x0
1096
1097 #define R_PCH_DMI17_PCR_DPCCAPR 0x2A04
1098 #define B_PCH_DMI17_PCR_DPCCAPR_RPEFDPC BIT5
1099
1100 #define R_PCH_DMI17_PCR_SPEECH 0x2A30
1101 #define B_PCH_DMI17_PCR_SPEECH_NCO_MASK 0xFFF00000
1102 #define B_PCH_DMI17_PCR_SPEECH_NCO_OFFSET 20
1103 #define V_PCH_DMI17_PCR_SPEECH_NCO 0xA90
1104 #define B_PCH_DMI17_PCR_SPEECH_CV_MASK 0xF0000
1105 #define B_PCH_DMI17_PCR_SPEECH_CV_OFFSET 16
1106 #define V_PCH_DMI17_PCR_SPEECH_CV 0x1
1107 #define B_PCH_DMI17_PCR_SPEECH_PCIEECID_MASK 0xFFFF
1108 #define B_PCH_DMI17_PCR_SPEECH_PCIEECID_OFFSET 0
1109 #define V_PCH_DMI17_PCR_SPEECH_PCIEECID 0x19
1110
1111 #define R_PCH_DMI17_PCR_DLFECH 0x2A90
1112 #define B_PCH_DMI17_PCR_DLFECH_NCO_MASK 0xFFF00000
1113 #define B_PCH_DMI17_PCR_DLFECH_NCO_OFFSET 20
1114 #define V_PCH_DMI17_PCR_DLFECH_NCO 0xA9C
1115 #define B_PCH_DMI17_PCR_DLFECH_CV_MASK 0xF0000
1116 #define B_PCH_DMI17_PCR_DLFECH_CV_OFFSET 16
1117 #define V_PCH_DMI17_PCR_DLFECH_CV 0x1
1118 #define B_PCH_DMI17_PCR_DLFECH_PCIECID_MASK 0xFFFF
1119 #define B_PCH_DMI17_PCR_DLFECH_PCIECID_OFFSET 0
1120 #define V_PCH_DMI17_PCR_DLFECH_PCIECID 0x25
1121
1122 #define R_PCH_DMI17_PCR_DLFCAP 0x2A94
1123 #define B_PCH_DMI17_PCR_DLFCAP_LSFCS BIT0
1124 #define B_PCH_DMI17_PCR_DLFCAP_LSFCS_OFFSET 0
1125
1126 #define R_PCH_DMI17_PCR_PL16GECH 0x2A9C
1127 #define B_PCH_DMI17_PCR_PL16GECH_NCO_MASK 0xFFF00000
1128 #define B_PCH_DMI17_PCR_PL16GECH_NCO_OFFSET 20
1129 #define V_PCH_DMI17_PCR_PL16GECH_NCO 0xEDC
1130 #define B_PCH_DMI17_PCR_PL16GECH_CV_MASK 0xF0000
1131 #define B_PCH_DMI17_PCR_PL16GECH_CV_OFFSET 16
1132 #define V_PCH_DMI17_PCR_PL16GECH_CV 0x1
1133 #define B_PCH_DMI17_PCR_PL16GECH_PCIECID_MASK 0xFFFF
1134 #define B_PCH_DMI17_PCR_PL16GECH_PCIECID_OFFSET 0
1135 #define V_PCH_DMI17_PCR_PL16GECH_PCIECID 0x26
1136
1137 #define R_PCH_DMI17_PCR_PL16L01EC 0x2ABC
1138 #define R_PCH_DMI17_PCR_PL16L23EC 0x2ABE
1139 #define R_PCH_DMI17_PCR_PL16L45EC 0x2AC0
1140 #define R_PCH_DMI17_PCR_PL16L67EC 0x2AC2
1141 #define B_PCH_DMI17_PCR_GEN4_UPL1357TP 0xF000
1142 #define N_PCH_DMI17_PCR_GEN4_UPL1357TP 12
1143 #define B_PCH_DMI17_PCR_GEN4_UPL0246TP 0x00F0
1144 #define N_PCH_DMI17_PCR_GEN4_UPL0246TP 4
1145 #define V_PCH_DMI17_PCR_GEN4_UPL0TP 7
1146 #define V_PCH_DMI17_PCR_GEN4_UPL1TP 7
1147 #define V_PCH_DMI17_PCR_GEN4_UPL2TP 7
1148 #define V_PCH_DMI17_PCR_GEN4_UPL3TP 7
1149 #define V_PCH_DMI17_PCR_GEN4_UPL4TP 7
1150 #define V_PCH_DMI17_PCR_GEN4_UPL5TP 7
1151 #define V_PCH_DMI17_PCR_GEN4_UPL6TP 7
1152 #define V_PCH_DMI17_PCR_GEN4_UPL7TP 7
1153
1154 #define R_PCH_DMI17_PCR_ACGR3S2 0x2C50
1155 #define B_PCH_DMI17_PCR_ACGR3S2_UPL1EPC BIT19
1156 #define B_PCH_DMI17_PCR_ACGR3S2_UPL1EPC_OFFSET 19
1157 #define B_PCH_DMI17_PCR_ACGR3S2_G4EBM BIT9
1158 #define B_PCH_DMI17_PCR_ACGR3S2_G4EBM_OFFSET 9
1159 #define B_PCH_DMI17_PCR_ACGR3S2_G3EBM BIT8
1160 #define B_PCH_DMI17_PCR_ACGR3S2_G3EBM_OFFSET 8
1161 #define B_PCH_DMI17_PCR_ACGR3S2_G2EBM BIT7
1162 #define B_PCH_DMI17_PCR_ACGR3S2_G2EBM_OFFSET 7
1163 #define B_PCH_DMI17_PCR_ACGR3S2_G1EBM BIT6
1164 #define B_PCH_DMI17_PCR_ACGR3S2_G1EBM_OFFSET 6
1165 #define B_PCH_DMI17_PCR_ACGR3S2_SRT BIT5
1166 #define B_PCH_DMI17_PCR_ACGR3S2_SRT_OFFSET 5
1167 #define B_PCH_DMI17_PCR_ACGR3S2_LSTPTLS_MASK 0xF
1168 #define B_PCH_DMI17_PCR_ACGR3S2_LSTPTLS_OFFSET 0
1169 #define V_PCH_DMI17_PCR_ACGR3S2_LSTPTLS 0x1
1170
1171 #define R_PCH_DMI17_PCR_VNNREMCTL 0x2C70
1172 #define B_PCH_DMI17_PCR_VNNREMCTL_FDVNNRE BIT8
1173 #define B_PCH_DMI17_PCR_VNNREMCTL_FDVNNRE_OFFSET 8
1174 #define B_PCH_DMI17_PCR_VNNREMCTL_HPVNNRE BIT7
1175 #define B_PCH_DMI17_PCR_VNNREMCTL_HPVNNRE_OFFSET 7
1176 #define B_PCH_DMI17_PCR_VNNREMCTL_DNPVNNRE BIT6
1177 #define B_PCH_DMI17_PCR_VNNREMCTL_DNPVNNRE_OFFSET 6
1178 #define B_PCH_DMI17_PCR_VNNREMCTL_RTD3VNNRE BIT5
1179 #define B_PCH_DMI17_PCR_VNNREMCTL_RTD3VNNRE_OFFSET 5
1180 #define B_PCH_DMI17_PCR_VNNREMCTL_LDVNNRE BIT4
1181 #define B_PCH_DMI17_PCR_VNNREMCTL_LDVNNRE_OFFSET 4
1182 #define B_PCH_DMI17_PCR_VNNREMCTL_ISPLFVNNRE_MASK (BIT3 | BIT2)
1183 #define B_PCH_DMI17_PCR_VNNREMCTL_ISPLFVNNRE_OFFSET 2
1184 #define V_PCH_DMI17_PCR_VNNREMCTL_ISPLFVNNRE_16CLKS 0x1
1185 #define V_PCH_DMI17_PCR_VNNREMCTL_ISPLFVNNRE_8CLKS 0x0
1186 #define B_PCH_DMI17_PCR_VNNREMCTL_LRSLFVNNRE_MASK (BIT1 | BIT0)
1187 #define B_PCH_DMI17_PCR_VNNREMCTL_LRSLFVNNRE_OFFSET 0
1188 #define V_PCH_DMI17_PCR_VNNREMCTL_LRSLFVNNRE_4CLKS 0x0
1189
1190 #define R_PCH_DMI17_PCR_RXQC 0x2C7C
1191 #define B_PCH_DMI17_PCR_RXQC_VMRQNPCOC_MASK (BIT15 | BIT14)
1192 #define B_PCH_DMI17_PCR_RXQC_VMRQNPCOC_OFFSET 14
1193 #define V_PCH_DMI17_PCR_RXQC_VMRQNPCOC 0x1
1194 #define B_PCH_DMI17_PCR_RXQC_VMRQPCOC_MASK (BIT13 | BIT12)
1195 #define B_PCH_DMI17_PCR_RXQC_VMRQPCOC_OFFSET 12
1196 #define V_PCH_DMI17_PCR_RXQC_VMRQPCOC 0x1
1197 #define B_PCH_DMI17_PCR_RXQC_V1RQNPCOC_MASK (BIT9 | BIT8)
1198 #define B_PCH_DMI17_PCR_RXQC_V1RQNPCOC_OFFSET 8
1199 #define V_PCH_DMI17_PCR_RXQC_V1RQNPCOC 0x1
1200 #define B_PCH_DMI17_PCR_RXQC_V1RQPCOC_MASK (BIT7 | BIT6)
1201 #define B_PCH_DMI17_PCR_RXQC_V1RQPCOC_OFFSET 6
1202 #define V_PCH_DMI17_PCR_RXQC_V1RQPCOC 0x1
1203 #define B_PCH_DMI17_PCR_RXQC_V0RQNPCOC_MASK (BIT3 | BIT2)
1204 #define B_PCH_DMI17_PCR_RXQC_V0RQNPCOC_OFFSET 2
1205 #define V_PCH_DMI17_PCR_RXQC_V0RQNPCOC 0x1
1206 #define B_PCH_DMI17_PCR_RXQC_V0RQPCOC_MASK (BIT1 | BIT0)
1207 #define B_PCH_DMI17_PCR_RXQC_V0RQPCOC_OFFSET 0
1208 #define V_PCH_DMI17_PCR_RXQC_V0RQPCOC 0x1
1209
1210 #define R_PCH_DMI17_PCR_AECR1G3 0x2C80
1211 #define B_PCH_DMI17_PCR_AECR1G3_DTCGCM BIT14
1212 #define B_PCH_DMI17_PCR_AECR1G3_DTCGCM_OFFSET 14
1213 #define B_PCH_DMI17_PCR_AECR1G3_TPSE BIT10
1214 #define B_PCH_DMI17_PCR_AECR1G3_TPSE_OFFSET 10
1215
1216 #define R_PCH_DMI17_PCR_AECR2G3 0x2C84
1217
1218 #define R_PCH_DMI17_PCR_LPCR 0x2C8C
1219 #define B_PCH_DMI17_PCR_LPCR_DIDOVRLOCK BIT24
1220 #define B_PCH_DMI17_PCR_LPCR_LTRCFGLOCK BIT16
1221 #define B_PCH_DMI17_PCR_LPCR_SERL BIT8
1222 #define B_PCH_DMI17_PCR_LPCR_SRL BIT0
1223
1224 #define R_PCH_DMI17_PCR_RXMC1 0x2C90
1225 #define B_PCH_DMI17_PCR_RXMC1_MSRVS_MASK 0xFC000000
1226 #define B_PCH_DMI17_PCR_RXMC1_MSRVS_OFFSET 26
1227 #define V_PCH_DMI17_PCR_RXMC1_MSRVS 0x1F
1228 #define B_PCH_DMI17_PCR_RXMC1_MSRTS_MASK 0x3F00000
1229 #define B_PCH_DMI17_PCR_RXMC1_MSRTS_OFFSET 20
1230 #define V_PCH_DMI17_PCR_RXMC1_MSRTS 0x3F
1231 #define B_PCH_DMI17_PCR_RXMC1_TMSLOP_MASK (BIT14 | BIT13)
1232 #define B_PCH_DMI17_PCR_RXMC1_TMSLOP_OFFSET 13
1233 #define V_PCH_DMI17_PCR_RXMC1_TMSLOP 0x1
1234 #define B_PCH_DMI17_PCR_RXMC1_VMSLOP_MASK (BIT12 | BIT11)
1235 #define B_PCH_DMI17_PCR_RXMC1_VMSLOP_OFFSET 11
1236 #define V_PCH_DMI17_PCR_RXMC1_VMSLOP 0x1
1237 #define B_PCH_DMI17_PCR_RXMC1_MMNOLS_MASK 0x1F0
1238 #define B_PCH_DMI17_PCR_RXMC1_MMNOLS_OFFSET 4
1239 #define V_PCH_DMI17_PCR_RXMC1_MMNOLS 0x1
1240
1241 #define R_PCH_DMI17_PCR_RXMC2 0x2C94
1242 #define B_PCH_DMI17_PCR_RXMC2_MNOTSS_MASK 0x1F80000
1243 #define B_PCH_DMI17_PCR_RXMC2_MNOTSS_OFFSET 19
1244 #define V_PCH_DMI17_PCR_RXMC2_MNOTSS 0x20
1245 #define B_PCH_DMI17_PCR_RXMC2_MMTOS_MASK 0x7E000
1246 #define B_PCH_DMI17_PCR_RXMC2_MMTOS_OFFSET 13
1247 #define V_PCH_DMI17_PCR_RXMC2_MMTOS 0x28
1248 #define B_PCH_DMI17_PCR_RXMC2_MNOVSS_MASK 0x1FC0
1249 #define B_PCH_DMI17_PCR_RXMC2_MNOVSS_OFFSET 6
1250 #define V_PCH_DMI17_PCR_RXMC2_MNOVSS 0x28
1251
1252 #define R_PCH_DMI17_PCR_EINJCTL 0x2CA8
1253 #define B_PCH_DMI17_PCR_EINJCTL_EINJDIS BIT0
1254 #define B_PCH_DMI17_PCR_EINJCTL_EINJDIS_OFFSET 0
1255
1256 #define R_PCH_DMI17_PCR_PL16MECH 0x2EDC
1257 #define B_PCH_DMI17_PCR_PL16MECH_NCO_MASK 0xFFF00000
1258 #define B_PCH_DMI17_PCR_PL16MECH_NCO_OFFSET 20
1259 #define V_PCH_DMI17_PCR_PL16MECH_NCO 0x0
1260 #define B_PCH_DMI17_PCR_PL16MECH_CV_MASK 0xF0000
1261 #define B_PCH_DMI17_PCR_PL16MECH_CV_OFFSET 16
1262 #define V_PCH_DMI17_PCR_PL16MECH_CV 0x1
1263 #define B_PCH_DMI17_PCR_PL16MECH_PCIECID_MASK 0xFFFF
1264 #define B_PCH_DMI17_PCR_PL16MECH_PCIECID_OFFSET 0
1265 #define V_PCH_DMI17_PCR_PL16MECH_PCIECID 0x27
1266
1267 #define R_PCH_DMI17_PCR_SRL 0x3E24
1268 #define B_PCH_DMI17_PCR_SRL_SRL BIT0
1269 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PchDmiAccessLib.h File Reference

DMI library header for abstraction of DMI PCR registers access. More...

Go to the source code of this file.

Functions

BOOLEAN | PchDmiIsBiosInterfaceLock (VOID)
Check DMI BIOS interface is locked. More...
VOID | PchDmiGetExtendedBiosRegionRange (OUT UINT64 *RangeBase, OUT UINT64 *RangeLimit)
Gets the extended BIOS region base and limit addresses. More...
BOOLEAN | PchDmiIsExtendedBiosRegionLimitLocked (VOID)
Checks lock of extended BIOS Region Limit address. More...

Detailed Description

DMI library header for abstraction of DMI PCR registers access.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiAccessLib.h.

Function Documentation

◆ PchDmiGetExtendedBiosRegionRange()

VOID PchDmiGetExtendedBiosRegionRange | ( | OUT UINT64 * | RangeBase,
 |  | OUT UINT64 * | RangeLimit
 | ) |  |

Gets the extended BIOS region base and limit addresses.

Parameters
[out] | UINT64 | Extended BIOS Region Range Base address
[out] | UINT64 | Extended BIOS Region Range Limit address

◆ PchDmiIsBiosInterfaceLock()

BOOLEAN PchDmiIsBiosInterfaceLock ( VOID )

Check DMI BIOS interface is locked.

Return values
TRUE DMI BIOS interface is locked FALSE DMI BIOS interface is not locked

◆ PchDmiIsExtendedBiosRegionLimitLocked()

BOOLEAN PchDmiIsExtendedBiosRegionLimitLocked ( VOID )

Checks lock of extended BIOS Region Limit address.

Return values
TRUE | Extended BIOS Region limit address is locked
FALSE | Extended BIOS Region limit address is unlocked
Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PchDmiAccessLib.h
Go to the documentation of this file.
1 /** @file
2 DMI library header for abstraction of DMI PCR registers access
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_DMI_ACCESS_LIB_H_
36 #define _PCH_DMI_ACCESS_LIB_H_
37
38 /**
39 Check DMI BIOS interface is locked
40
41 @retval TRUE DMI BIOS interface is locked
42 FALSE DMI BIOS interface is not locked
43 **/
44 BOOLEAN
45 PchDmiIsBiosInterfaceLock (
46 VOID
47 );
48
49 /**
50 Gets the extended BIOS region base and limit addresses
51
52 @param[out] UINT64 Extended BIOS Region Range Base address
53 @param[out] UINT64 Extended BIOS Region Range Limit address
54 **/
55 VOID
56 PchDmiGetExtendedBiosRegionRange (
57 OUT UINT64 *RangeBase,
58 OUT UINT64 *RangeLimit
59 );
60
61 /**
62 Checks lock of extended BIOS Region Limit address
63
64 @retval TRUE Extended BIOS Region limit address is locked
65 @retval FALSE Extended BIOS Region limit address is unlocked
66 **/
67 BOOLEAN
68 PchDmiIsExtendedBiosRegionLimitLocked (
69 VOID
70 );
71
72 #endif // _PCH_DMI_ACCESS_LIB_H_
73
PchDmiIsBiosInterfaceLock
BOOLEAN PchDmiIsBiosInterfaceLock(VOID)
Check DMI BIOS interface is locked.
PchDmiIsExtendedBiosRegionLimitLocked
BOOLEAN PchDmiIsExtendedBiosRegionLimitLocked(VOID)
Checks lock of extended BIOS Region Limit address.
PchDmiGetExtendedBiosRegionRange
VOID PchDmiGetExtendedBiosRegionRange(OUT UINT64 *RangeBase, OUT UINT64 *RangeLimit)
Gets the extended BIOS region base and limit addresses.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
Classes
PchDmiConfig.h File Reference

DMI policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_DMI_EQ_PARAM
Lane specific Dmi Gen3, Gen4 equalization parameters. More...
struct | PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI. More...

Detailed Description

DMI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmiConfig.h
Go to the documentation of this file.
1 /** @file
2 DMI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_DMI_CONFIG_H_
36 #define _PCH_DMI_CONFIG_H_
37
38 #define PCH_DMI_CONFIG_REVISION 1
39 extern EFI_GUID gPchDmiConfigGuid;
40
41 /*
42 <b>Revision 1</b>: - Initial version.
43 <b>Revision 2</b>: - Added Policies to support FOM
44 */
45 #define PCH_DMI_PREMEM_CONFIG_REVISION 2
46 extern EFI_GUID gPchDmiPreMemConfigGuid;
47
48 #pragma pack (push,1)
49
50 #define PCH_DMI_HWEQ_COEFFS_MAX 8
51 /**
52 Lane specific Dmi Gen3, Gen4 equalization parameters.
53 **/
54 typedef struct {
55 UINT8 Cm; ///< Coefficient C-1
56 UINT8 Cp; ///< Coefficient C+1
57 UINT8 Rsvd0[2]; ///< Reserved bytes
58 } PCH_DMI_EQ_PARAM;
59
60 typedef struct {
61 CONFIG_BLOCK_HEADER Header; ///< Config Block
62 PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
63 UINT8 DmiHweq;
64 UINT8 Reserved[3];
65 } PCH_DMI_PREMEM_CONFIG;
66
67
68 /**
69 The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
70 <b>Revision 1</b>:
71 - Initial version.
72 **/
73 typedef struct {
74 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
75
76 UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
77 UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
78 UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
79 UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
80 /**
81 When set to TRUE turns on:
82 - L1 State Controller Power Gating
83 - L1 State PHY Data Lane Power Gating
84 - PHY Common Lane Power Gating
85 - Hardware Autonomous Enable
86 - PMC Request Enable and Sleep Enable
87 **/
88 UINT32 DmiPowerReduction : 1;
89 UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
90 UINT32 Rsvdbits : 19; ///< Reserved bits
91 } PCH_DMI_CONFIG;
92
93 #pragma pack (pop)
94
95 #endif // _PCH_DMI_CONFIG_H_
PCH_DMI_CONFIG::PwrOptEnable
UINT32 PwrOptEnable
0: Disable; 1: Enable DMI Power Optimizer on PCH side.
Definition: PchDmiConfig.h:76
PCH_DMI_CONFIG::DmiAspmCtrl
UINT32 DmiAspmCtrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig
Definition: PchDmiConfig.h:77
PCH_DMI_CONFIG
The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
Definition: PchDmiConfig.h:73
PCH_DMI_CONFIG::Rsvdbits
UINT32 Rsvdbits
Reserved bits.
Definition: PchDmiConfig.h:90
PCH_DMI_CONFIG::DmiPowerReduction
UINT32 DmiPowerReduction
When set to TRUE turns on:
Definition: PchDmiConfig.h:88
PCH_DMI_CONFIG::CwbEnable
UINT32 CwbEnable
0: Disable; 1: Enable Central Write Buffer feature configurable and enabled by default
Definition: PchDmiConfig.h:78
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_DMI_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: PchDmiConfig.h:56
PCH_DMI_CONFIG::ClockGating
UINT32 ClockGating
0: Disable; 1: Enable clock gating.
Definition: PchDmiConfig.h:89
PCH_DMI_CONFIG::L1RpCtl
UINT32 L1RpCtl
0: Disable; 1: Enable Allow DMI enter L1 when all root ports are in L1, L0s or link down....
Definition: PchDmiConfig.h:79
PCH_DMI_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: PchDmiConfig.h:55
PCH_DMI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchDmiConfig.h:74
PCH_DMI_EQ_PARAM
Lane specific Dmi Gen3, Gen4 equalization parameters.
Definition: PchDmiConfig.h:54
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
PchDmiHob.h File Reference

The GUID definition for CpuDmiHob. More...

#include <Base.h>
Include dependency graph for PchDmiHob.h:

Go to the source code of this file.

Classes

struct PCH_DMI_HOB
The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization. More...

Detailed Description

The GUID definition for CpuDmiHob.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PchDmiHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for CpuDmiHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_DMI_HOB_H_
36 #define _PCH_DMI_HOB_H_
37
38 #include <Base.h>
39
40 #define PCH_DMI_HWEQ_COEFFS_MAX 8
41
42 extern EFI_GUID gPchDmiHobGuid;
43 #pragma pack (push,1)
44
45 /**
46 The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization
47 **/
48 typedef struct {
49 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gPchPcieHobGuid
50 ///
51 /// These members describe the configuration of each PCH Dmi root port.
52 ///
53 UINT8 CmGen3[PCH_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C-1 for Gen3
54 UINT8 CpGen3[PCH_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C+1 for Gen3
55 UINT8 CmGen4[PCH_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C-1 for Gen4
56 UINT8 CpGen4[PCH_DMI_HWEQ_COEFFS_MAX]; ///< Coefficient C+1 for Gen4
57 } PCH_DMI_HOB;
58 #pragma pack (pop)
59 #endif
PCH_DMI_HOB
The PCH_DMI_HOB block describes the expected configuration of Pch Dmi Equalization.
Definition: PchDmiHob.h:48
PCH_DMI_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gPchPcieHobGuid.
Definition: PchDmiHob.h:49
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchDmiRegs.h File Reference

Register names for PCH DMI and OP-DMI. More...

Go to the source code of this file.

Macros

#define | B_PCH_DMI_PCR_V0CTL_ID (7 << 24)
Bit[26:24].
#define | B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24)
Bit[27:24].
#define | R_PCH_DMI_PCR_LCAP 0x204C
Link Capabilities.
#define | B_PCH_DMI_PCR_LCAP_EL1 (BIT17 | BIT16 | BIT15)
L1 Exit Latency.
#define | N_PCH_DMI_PCR_LCAP_EL1 15
L1 Exit Latency.
#define | V_PCH_DMI_PCR_LCAP_EL1_8US_16US 0x4
L1 Exit Latency = 8us to less than 16us.
#define | B_PCH_DMI_PCR_LCAP_EL0 (BIT14 | BIT13 | BIT12)
L0 Exit Latency.
#define | N_PCH_DMI_PCR_LCAP_EL0 12
L0 Exit Latency.
#define | V_PCH_DMI_PCR_LCAP_EL0_256NS_512NS 0x3
L0 Exit Latency = 256ns to less than 512ns.
#define | B_PCH_DMI_PCR_LCAP_APMS (BIT11 | BIT10)
L0 is supported on DMI.
#define | R_PCH_DMI_PCR_PCIEPAR1E 0x2700
PCIE Port IOxAPIC Range 1 Enable.
#define | R_PCH_DMI_PCR_PCIEPAR2E 0x2704
PCIE Port IOxAPIC Range 2 Enable.
#define | R_PCH_DMI_PCR_PCIEPAR3E 0x2708
PCIE Port IOxAPIC Range 3 Enable.
#define | R_PCH_DMI_PCR_PCIEPAR4E 0x270C
PCIE Port IOxAPIC Range 4 Enable.
#define | R_PCH_DMI_PCR_PCIEPAR1DID 0x2710
PCIE Port IOxAPIC Range 1 Destination ID.
#define | R_PCH_DMI_PCR_PCIEPAR2DID 0x2714
PCIE Port IOxAPIC Range 2 Destination ID.
#define | R_PCH_DMI_PCR_PCIEPAR3DID 0x2718
PCIE Port IOxAPIC Range 3 Destination ID.
#define | R_PCH_DMI_PCR_PCIEPAR4DID 0x271C
PCIE Port IOxAPIC Range 4 Destination ID.
#define | R_PCH_DMI_PCR_P2SBIOR 0x2720
P2SB IO Range.
#define | R_PCH_DMI_PCR_TTTBARB 0x2724
Thermal Throttling BIOS Assigned Thermal Base Address.
#define | R_PCH_DMI_PCR_TTTBARBH 0x2728
Thermal Throttling BIOS Assigned Thermal Base High Address.
#define | R_PCH_DMI_PCR_LPCLGIR1 0x2730
LPC Generic I/O Range 1.
#define | R_PCH_DMI_PCR_LPCLGIR2 0x2734
LPC Generic I/O Range 2.
#define | R_PCH_DMI_PCR_LPCLGIR3 0x2738
LPC Generic I/O Range 3.
#define | R_PCH_DMI_PCR_LPCLGIR4 0x273C
LPC Generic I/O Range 4.
#define | R_PCH_DMI_PCR_LPCGMR 0x2740
LPC Generic Memory Range.
#define | R_PCH_DMI_PCR_SEGIR 0x27BC
Second ESPI Generic I/O Range.
#define | R_PCH_DMI_PCR_SEGMR 0x27C0
Second ESPI Generic Memory Range.
#define | R_PCH_DMI_PCR_LPCBDE 0x2744
LPC BIOS Decode Enable.
#define | R_PCH_DMI_PCR_UCPR 0x2748
uCode Patch Region
#define | B_PCH_DMI_PCR_UCPR_UPRE BIT0
uCode Patch Region Enable
#define | R_PCH_DMI_PCR_GCS 0x274C
Generic Control and Status.
#define | B_PCH_DMI_PCR_RPRDID 0xFFFF0000
RPR Destination ID.
#define | B_PCH_DMI_PCR_BBS BIT10
Boot BIOS Strap.
#define | B_PCH_DMI_PCR_RPR BIT11
Reserved Page Route.
#define | B_PCH_DMI_PCR_BILD BIT0
BIOS Interface Lock-Down.
#define | R_PCH_DMI_PCR_IOT1 0x2750
I/O Trap Register 1.
#define | R_PCH_DMI_PCR_IOT2 0x2758
I/O Trap Register 2.
#define | R_PCH_DMI_PCR_IOT3 0x2760
I/O Trap Register 3.
#define | R_PCH_DMI_PCR_IOT4 0x2768
I/O Trap Register 4.
#define | R_PCH_DMI_PCR_LPCIOD 0x2770
LPC I/O Decode Ranges.
#define | R_PCH_DMI_PCR_LPCIOE 0x2774
LPC I/O Enables.
#define | R_PCH_DMI_PCR_TCOBASE 0x2778
TCO Base Address.
#define | B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0
TCO Base Address Mask.
#define | R_PCH_DMI_PCR_GPMR1 0x277C
General Purpose Memory Range 1.
#define | N_PCH_DMI_PCR_GPMRX_GPMRL1 16
General Purpose Memory Range Limit 1 bits position.
#define | R_PCH_DMI_PCR_GPMR1DID 0x2780
General Purpose Memory Range 1 Destination ID.
#define | B_PCH_DMI_PCR_GPMRXDID_GPMR1DE BIT31
General Purpose Memory Range 1 Decode Enable bit.
#define | R_PCH_DMI_PCR_GPMR2 0x2784
General Purpose Memory Range 2.
#define | R_PCH_DMI_PCR_GPMR2DID 0x2788
General Purpose Memory Range 2 Destination ID.
#define | R_PCH_DMI_PCR_GPMR3 0x278C
General Purpose Memory Range 3.
#define | R_PCH_DMI_PCR_GPMR3DID 0x2790
General Purpose Memory Range 3 Destination ID.
#define | R_PCH_DMI_PCR_GPIOR1 0x2794
General Purpose I/O Range 1.
#define | R_PCH_DMI_PCR_GPIOR1DID 0x2798
General Purpose I/O Range 1 Destination ID.
#define | R_PCH_DMI_PCR_GPIOR2 0x279C
General Purpose I/O Range 2.
#define | R_PCH_DMI_PCR_GPIOR2DID 0x27A0
General Purpose I/O Range 2 Destination ID.
#define | R_PCH_DMI_PCR_GPIOR3 0x27A4
General Purpose I/O Range 3.
#define | R_PCH_DMI_PCR_GPIOR3DID 0x27A8
General Purpose I/O Range 3 Destination ID.

Detailed Description

Register names for PCH DMI and OP-DMI.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchDmiRegs.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmiRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
PchDmiRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH DMI and OP-DMI
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2014 - 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_DMI_REGS_H_
65 #define _PCH_DMI_REGS_H_
66
67 //
68 // PCH DMI Chipset Configuration Registers (PID:DMI)
69 //
70
71 //
72 // VC Configuration (Common)
73 //
74 #define B_PCH_DMI_PCR_V0CTL_EN BIT31
75 #define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) ///< Bit[26:24]
76 #define N_PCH_DMI_PCR_V0CTL_ID 24
77 #define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00
78 #define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E
79 #define B_PCH_DMI_PCR_V0STS_NP BIT1
80 #define B_PCH_DMI_PCR_V1CTL_EN BIT31
81 #define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) ///< Bit[27:24]
82 #define N_PCH_DMI_PCR_V1CTL_ID 24
83 #define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00
84 #define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE
85 #define B_PCH_DMI_PCR_V1STS_NP BIT1
86
87 //
88 // Internal Link Configuration (PCH DMI Only)
89 //
90 #define R_PCH_DMI_PCR_LCAP 0x204C ///< Link Capabilities
91 #define B_PCH_DMI_PCR_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency
92 #define N_PCH_DMI_PCR_LCAP_EL1 15 ///< L1 Exit Latency
93 #define V_PCH_DMI_PCR_LCAP_EL1_8US_16US 0x4 ///< L1 Exit Latency = 8us to less than 16us
94 #define B_PCH_DMI_PCR_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0 Exit Latency
95 #define N_PCH_DMI_PCR_LCAP_EL0 12 ///< L0 Exit Latency
96 #define V_PCH_DMI_PCR_LCAP_EL0_256NS_512NS 0x3 ///< L0 Exit Latency = 256ns to less than 512ns
97 #define B_PCH_DMI_PCR_LCAP_APMS (BIT11 | BIT10) ///< L0 is supported on DMI
98 #define B_PCH_DMI_PCR_LCAP_MLW 0x000003F0
99 #define B_PCH_DMI_PCR_LCAP_MLS 0x0000000F
100
101 //
102 // PCH DMI Source Decode PCRs (Common)
103 //
104 #define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Port IOxAPIC Range 1 Enable
105 #define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Port IOxAPIC Range 2 Enable
106 #define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Port IOxAPIC Range 3 Enable
107 #define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Port IOxAPIC Range 4 Enable
108 #define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE Port IOxAPIC Range 1 Destination ID
109 #define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE Port IOxAPIC Range 2 Destination ID
110 #define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE Port IOxAPIC Range 3 Destination ID
111 #define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE Port IOxAPIC Range 4 Destination ID
112 #define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO Range
113 #define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal Throttling BIOS Assigned Thermal Base Address
114 #define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal Throttling BIOS Assigned Thermal Base High Address
115 #define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC Generic I/O Range 1
116 #define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC Generic I/O Range 2
117 #define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC Generic I/O Range 3
118 #define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC Generic I/O Range 4
119 #define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC Generic Memory Range
120 #define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second ESPI Generic I/O Range
121 #define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second ESPI Generic Memory Range
122 #define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIOS Decode Enable
123 #define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode Patch Region
124 #define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode Patch Region Enable
125 #define R_PCH_DMI_PCR_GCS 0x274C ///< Generic Control and Status
126 #define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR Destination ID
127 #define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BIOS Strap
128 #define B_PCH_DMI_PCR_RPR BIT11 ///< Reserved Page Route
129 #define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS Interface Lock-Down
130 #define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Trap Register 1
131 #define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Trap Register 2
132 #define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Trap Register 3
133 #define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Trap Register 4
134 #define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
135 #define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
136 #define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
137 #define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
138 #define R_PCH_DMI_PCR_GPMR1 0x277C ///< General Purpose Memory Range 1
139 #define N_PCH_DMI_PCR_GPMRX_GPMRL1 16 ///< General Purpose Memory Range Limit 1 bits position
140 #define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General Purpose Memory Range 1 Destination ID
141 #define B_PCH_DMI_PCR_GPMRXDID_GPMR1DE BIT31 ///< General Purpose Memory Range 1 Decode Enable bit
142 #define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General Purpose Memory Range 2
143 #define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General Purpose Memory Range 2 Destination ID
144 #define R_PCH_DMI_PCR_GPMR3 0x278C ///< General Purpose Memory Range 3
145 #define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General Purpose Memory Range 3 Destination ID
146 #define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General Purpose I/O Range 1
147 #define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General Purpose I/O Range 1 Destination ID
148 #define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General Purpose I/O Range 2
149 #define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General Purpose I/O Range 2 Destination ID
150 #define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General Purpose I/O Range 3
151 #define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General Purpose I/O Range 3 Destination ID
152
153 //
154 // Opi PHY registers
155 //
156 #define R_OPIPHY_PCR_0000 0x0000
157 #define R_OPIPHY_PCR_0110 0x0110
158 #define R_OPIPHY_PCR_0118 0x0118
159 #define R_OPIPHY_PCR_011C 0x011C
160 #define R_OPIPHY_PCR_0354 0x0354
161 #define R_OPIPHY_PCR_B104 0xB104
162 #define R_OPIPHY_PCR_B10C 0xB10C
163
164 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchEspiSmiDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Macros | Typedefs
PchEspiSmiDispatch.h File Reference

SmmEspiDispatch Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL
Interface structure for PCH eSPI SMIs Dispatch Protocol The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs. More...

Macros

#define PCH_ESPI_SMI_DISPATCH_REVISION 1
PCH ESPI SMI dispatch revision number. More...

Typedefs

typedef VOID(* | PCH_ESPI_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)
Callback function for an PCH eSPI SMI handler dispatch. More...
typedef EFI_STATUS(* | PCH_ESPI_SMI_REGISTER) (IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Generic function to register different types of eSPI SMI types. More...
typedef EFI_STATUS(* | PCH_ESPI_SMI_UNREGISTER) (IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
eSPI SMI Dispatch Protocol instance to unregister a callback based on handle More...

Detailed Description

SmmEspiDispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchEspiSmiDispatch.h.

Macro Definition Documentation

◆ PCH_ESPI_SMI_DISPATCH_REVISION

#define PCH_ESPI_SMI_DISPATCH_REVISION 1

PCH ESPI SMI dispatch revision number.

Revision 1: Initial version

Definition at line 170 of file PchEspiSmiDispatch.h.

Typedef Documentation

◆ PCH_ESPI_SMI_DISPATCH_CALLBACK

typedef VOID( * PCH_ESPI_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)

Callback function for an PCH eSPI SMI handler dispatch.

Parameters
[in] DispatchHandle The unique handle assigned to this handler by register function.

Definition at line 58 of file PchEspiSmiDispatch.h.

◆ PCH_ESPI_SMI_REGISTER

typedef EFI_STATUS( * PCH_ESPI_SMI_REGISTER) (IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)

Generic function to register different types of eSPI SMI types.

Parameters
[in] | This | Not used
[in] | DispatchFunction | The callback to execute
[out] | DispatchHandle | The handle for this callback registration
Return values
EFI_SUCCESS | Registration successful
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered
others | Registration failed

Definition at line 75 of file PchEspiSmiDispatch.h.

◆ PCH_ESPI_SMI_UNREGISTER

typedef EFI_STATUS( * PCH_ESPI_SMI_UNREGISTER) (IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

eSPI SMI Dispatch Protocol instance to unregister a callback based on handle

Parameters
[in] | This | Not used
[in] | DispatchHandle | Handle acquired during registration
Return values
EFI_SUCCESS | Unregister successful
EFI_INVALID_PARAMETER | DispatchHandle is null
EFI_INVALID_PARAMETER | DispatchHandle's forward link has bad pointer
EFI_INVALID_PARAMETER | DispatchHandle does not exist in database
EFI_ACCESS_DENIED | Unregistration is done after end of DXE

Definition at line 96 of file PchEspiSmiDispatch.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchEspiSmiDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchEspiSmiDispatch.h
Go to the documentation of this file.
1 /** @file
2 SmmEspiDispatch Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_
36 #define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gPchEspiSmiDispatchProtocolGuid;
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL;
47
48 //
49 // Member functions
50 //
51
52 /**
53 Callback function for an PCH eSPI SMI handler dispatch.
54
55 @param[in] DispatchHandle The unique handle assigned to this handler by register function.
56 **/
57 typedef
58 VOID
59 (EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) (
60 IN EFI_HANDLE DispatchHandle
61 );
62
63 /**
64 Generic function to register different types of eSPI SMI types
65
66 @param[in] This Not used
67 @param[in] DispatchFunction The callback to execute
68 @param[out] DispatchHandle The handle for this callback registration
69
70 @retval EFI_SUCCESS Registration successful
71 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
72 @retval others Registration failed
73 **/
74 typedef
75 EFI_STATUS
76 (EFIAPI *PCH_ESPI_SMI_REGISTER) (
77 IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,
78 IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction,
79 OUT EFI_HANDLE *DispatchHandle
80 );
81
82 /**
83 eSPI SMI Dispatch Protocol instance to unregister a callback based on handle
84
85 @param[in] This Not used
86 @param[in] DispatchHandle Handle acquired during registration
87
88 @retval EFI_SUCCESS Unregister successful
89 @retval EFI_INVALID_PARAMETER DispatchHandle is null
90 @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has bad pointer
91 @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in database
92 @retval EFI_ACCESS_DENIED Unregistration is done after end of DXE
93 **/
94
95 typedef
96 EFI_STATUS
97 (EFIAPI *PCH_ESPI_SMI_UNREGISTER) (
98 IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,
99 IN EFI_HANDLE DispatchHandle
100 );
101
102 /**
103 Interface structure for PCH eSPI SMIs Dispatch Protocol
104 The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs.
105 It contains SMI types of BiosWr, EcAssertedVw, and eSPI Initiator asserted SMIs
106 **/
107 struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL {
108 /**
109 This member specifies the revision of this structure. This field is used to
110 indicate backwards compatible changes to the protocol.
111 **/
112 UINT8 Revision;
113 /**
114 Unregister eSPI SMI events
115 **/
116 PCH_ESPI_SMI_UNREGISTER UnRegister;
117 /**
118 Register a BIOS Write Protect event
119 **/
120 PCH_ESPI_SMI_REGISTER BiosWrProtectRegister;
121 /**
122 Register a BIOS Write Report event
123 **/
124 PCH_ESPI_SMI_REGISTER BiosWrReportRegister;
125 /**
126 Register a Peripheral Channel Non Fatal Error event
127 **/
128 PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister;
129 /**
130 Register a Peripheral Channel Fatal Error event
131 **/
132 PCH_ESPI_SMI_REGISTER PcErrFatalRegister;
133 /**
134 Register a Virtual Wire Non Fatal Error event
135 **/
136 PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister;
137 /**
138 Register a Virtual Wire Fatal Error event
139 **/
140 PCH_ESPI_SMI_REGISTER VwErrFatalRegister;
141 /**
142 Register a Flash Channel Non Fatal Error event
143 **/
144 PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister;
145 /**
146 Register a Flash Channel Fatal Error event
147 **/
148 PCH_ESPI_SMI_REGISTER FlashErrFatalRegister;
149 /**
150 Register a Link Error event
151 **/
152 PCH_ESPI_SMI_REGISTER LnkErrType1Register;
153 /**
154 Register a SMI handler for Espi slaver
155 This routine will also lock down ESPI_SMI_LOCK bit after registration and prevent
156 this handler from unregistration.
157 On platform that supports more than 1 device through another chip select (SPT-H),
158 the SMI handler itself needs to inspect both the eSPI devices' interrupt status registers
159 (implementation specific for each Slave) in order to identify and service the cause.
160 After servicing it, it has to clear the Slaves' internal SMI# status registers
161 **/
162 PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister;
163 };
164
165 /**
166 PCH ESPI SMI dispatch revision number
167
168 Revision 1: Initial version
169 **/
170 #define PCH_ESPI_SMI_DISPATCH_REVISION 1
171
172 #endif
PCH_ESPI_SMI_REGISTER
EFI_STATUS(* PCH_ESPI_SMI_REGISTER)(IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Generic function to register different types of eSPI SMI types.
Definition: PchEspiSmiDispatch.h:76
PCH_ESPI_SMI_DISPATCH_CALLBACK
VOID(* PCH_ESPI_SMI_DISPATCH_CALLBACK)(IN EFI_HANDLE DispatchHandle)
Callback function for an PCH eSPI SMI handler dispatch.
Definition: PchEspiSmiDispatch.h:59
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::PcErrNonFatalRegister
PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister
Register a Peripheral Channel Non Fatal Error event.
Definition: PchEspiSmiDispatch.h:128
PCH_ESPI_SMI_UNREGISTER
EFI_STATUS(* PCH_ESPI_SMI_UNREGISTER)(IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
eSPI SMI Dispatch Protocol instance to unregister a callback based on handle
Definition: PchEspiSmiDispatch.h:97
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::UnRegister
PCH_ESPI_SMI_UNREGISTER UnRegister
Unregister eSPI SMI events.
Definition: PchEspiSmiDispatch.h:116
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::LnkErrType1Register
PCH_ESPI_SMI_REGISTER LnkErrType1Register
Register a Link Error event.
Definition: PchEspiSmiDispatch.h:152
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::EspiSlaveSmiRegister
PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister
Register a SMI handler for Espi slaver This routine will also lock down ESPI_SMI_LOCK bit after regis...
Definition: PchEspiSmiDispatch.h:162
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::FlashErrFatalRegister
PCH_ESPI_SMI_REGISTER FlashErrFatalRegister
Register a Flash Channel Fatal Error event.
Definition: PchEspiSmiDispatch.h:148
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::PcErrFatalRegister
PCH_ESPI_SMI_REGISTER PcErrFatalRegister
Register a Peripheral Channel Fatal Error event.
Definition: PchEspiSmiDispatch.h:132
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::BiosWrProtectRegister
PCH_ESPI_SMI_REGISTER BiosWrProtectRegister
Register a BIOS Write Protect event.
Definition: PchEspiSmiDispatch.h:120
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::VwErrNonFatalRegister
PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister
Register a Virtual Wire Non Fatal Error event.
Definition: PchEspiSmiDispatch.h:136
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::VwErrFatalRegister
PCH_ESPI_SMI_REGISTER VwErrFatalRegister
Register a Virtual Wire Fatal Error event.
Definition: PchEspiSmiDispatch.h:140
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::BiosWrReportRegister
PCH_ESPI_SMI_REGISTER BiosWrReportRegister
Register a BIOS Write Report event.
Definition: PchEspiSmiDispatch.h:124
_PCH_ESPI_SMI_DISPATCH_PROTOCOL
Interface structure for PCH eSPI SMIs Dispatch Protocol The PCH ESPI SMI DISPATCH PROTOCOL provides t...
Definition: PchEspiSmiDispatch.h:107
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: PchEspiSmiDispatch.h:112
_PCH_ESPI_SMI_DISPATCH_PROTOCOL::FlashErrNonFatalRegister
PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister
Register a Flash Channel Non Fatal Error event.
Definition: PchEspiSmiDispatch.h:144
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchGeneralConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
Classes | Enumerations
PchGeneralConfig.h File Reference

PCH General policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_GENERAL_CONFIG
PCH General Configuration Revision 1: - Initial version. More...
struct | PCH_GENERAL_PREMEM_CONFIG
PCH General Pre-Memory Configuration Revision 1: - Initial version. More...

Enumerations

enum PCH_RESERVED_PAGE_ROUTE

Detailed Description

PCH General policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchGeneralConfig.h.

Enumeration Type Documentation

◆ PCH_RESERVED_PAGE_ROUTE

enum PCH_RESERVED_PAGE_ROUTE
Enumerator
PchReservedPageToLpc | Port 80h cycles are sent to LPC.
PchReservedPageToPcie | Port 80h cycles are sent to PCIe.

Definition at line 46 of file PchGeneralConfig.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchGeneralConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
PchGeneralConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH General policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_GENERAL_CONFIG_H_
36 #define _PCH_GENERAL_CONFIG_H_
37
38 #define PCH_GENERAL_CONFIG_REVISION 2
39 #define PCH_GENERAL_PREMEM_CONFIG_REVISION 3
40
41 extern EFI_GUID gPchGeneralConfigGuid;
42 extern EFI_GUID gPchGeneralPreMemConfigGuid;
43
44 #pragma pack (push,1)
45
46 enum PCH_RESERVED_PAGE_ROUTE {
47 PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
48 PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
49 };
50
51 /**
52 PCH General Configuration
53 <b>Revision 1</b>: - Initial version.
54 <b>Revision 2</b>: - Added AcpiL6dPmeHandling
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
58 /**
59 This member describes whether or not the Compatibility Revision ID (CRID) feature
60 of PCH should be enabled. <b>0: Disable</b>; 1: Enable
61 **/
62 UINT32 Crid : 1;
63 /**
64 Set to enable low latency of legacy IO.
65 Some systems require lower IO latency irrespective of power.
66 This is a tradeoff between power and IO latency.
67 @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
68 and ITSS Clock Gating are forced to disabled.
69 <b>0: Disable</b>, 1: Enable
70 **/
71 UINT32 LegacyIoLowLatency : 1;
72 /**
73 Enables _L6D ACPI handler.
74 PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit
75 <b>0: Disable</b>, 1: Enable
76 **/
77 UINT32 AcpiL6dPmeHandling : 1;
78 UINT32 RsvdBits0 : 29; ///< Reserved bits
79 } PCH_GENERAL_CONFIG;
80
81 /**
82 PCH General Pre-Memory Configuration
83 <b>Revision 1</b>: - Initial version.
84 <b>Revision 2</b>: - Added GpioOverride.
85 <b>Revision 3</b>: - Added IoeDebugEn, PmodeClkEn
86 **/
87 typedef struct {
88 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
89 /**
90 Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
91 **/
92 UINT32 Port80Route : 1;
93 UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO
94 /**
95 Gpio override Level
96 -- <b>0: Disable</b>;
97 - 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase
98 - 2: Override Level 2 - Reserved for future use
99 **/
100 UINT32 GpioOverride : 3;
101 /**
102 Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link and clock will keep up for debug
103 <b>0: Disable</b>; 1: Enable
104 **/
105 UINT32 IoeDebugEn : 1;
106 /**
107 Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use
108 <b>0: Disable</b>; 1: Enable
109 **/
110 UINT32 PmodeClkEn : 1;
111 UINT32 RsvdBits0 : 25; ///< Reserved bits
112 } PCH_GENERAL_PREMEM_CONFIG;
113
114 #pragma pack (pop)
115
116 #endif // _PCH_GENERAL_CONFIG_H_
PCH_GENERAL_PREMEM_CONFIG::IotgPllSscEn
UINT32 IotgPllSscEn
Need to disable CPU Side SSC for A0 PO.
Definition: PchGeneralConfig.h:93
PCH_RESERVED_PAGE_ROUTE
PCH_RESERVED_PAGE_ROUTE
Definition: PchGeneralConfig.h:46
PCH_GENERAL_PREMEM_CONFIG::Port80Route
UINT32 Port80Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
Definition: PchGeneralConfig.h:92
PCH_GENERAL_CONFIG::LegacyIoLowLatency
UINT32 LegacyIoLowLatency
Set to enable low latency of legacy IO.
Definition: PchGeneralConfig.h:71
PCH_GENERAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchGeneralConfig.h:57
PCH_GENERAL_PREMEM_CONFIG::GpioOverride
UINT32 GpioOverride
Gpio override Level – 0: Disable;.
Definition: PchGeneralConfig.h:100
PCH_GENERAL_CONFIG::Crid
UINT32 Crid
This member describes whether or not the Compatibility Revision ID (CRID) feature of PCH should be en...
Definition: PchGeneralConfig.h:62
PCH_GENERAL_CONFIG::AcpiL6dPmeHandling
UINT32 AcpiL6dPmeHandling
Enables _L6D ACPI handler.
Definition: PchGeneralConfig.h:77
PCH_GENERAL_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchGeneralConfig.h:88
PCH_GENERAL_PREMEM_CONFIG::IoeDebugEn
UINT32 IoeDebugEn
Enable/Disable IOE Debug.
Definition: PchGeneralConfig.h:105
PchReservedPageToPcie
@ PchReservedPageToPcie
Port 80h cycles are sent to PCIe.
Definition: PchGeneralConfig.h:48
PCH_GENERAL_PREMEM_CONFIG::PmodeClkEn
UINT32 PmodeClkEn
Enable/Disable PMODE clock.
Definition: PchGeneralConfig.h:110
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PchReservedPageToLpc
@ PchReservedPageToLpc
Port 80h cycles are sent to LPC.
Definition: PchGeneralConfig.h:47
PCH_GENERAL_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PchGeneralConfig.h:111
PCH_GENERAL_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PchGeneralConfig.h:78
PCH_GENERAL_PREMEM_CONFIG
PCH General Pre-Memory Configuration Revision 1: - Initial version.
Definition: PchGeneralConfig.h:87
PCH_GENERAL_CONFIG
PCH General Configuration Revision 1: - Initial version.
Definition: PchGeneralConfig.h:56
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchHybridStorageHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
PchHybridStorageHob.h File Reference

Definitions required to create HybridStorageHob. More...

Go to the source code of this file.

Detailed Description

Definitions required to create HybridStorageHob.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchHybridStorageHob.h.

Generated on Wed Jan 5 2022 01:24:02 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchHybridStorageHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PchHybridStorageHob.h
Go to the documentation of this file.
1 /** @file
2
3 Definitions required to create HybridStorageHob
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2020 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PCH_HYBRIDSTORAGE_HOB_
38 #define _PCH_HYBRIDSTORAGE_HOB_
39
40 extern EFI_GUID gHybridStorageHobGuid;
41
42 //
43 // Passes to DXE Hybrid Storage location
44 //
45 typedef struct {
46 UINT32 HybridStorageLocation;
47 UINT32 HybridStorageCpuRpLocation;
48 UINT32 HybridStorageCpuAttachPchRpLocation;
49 BOOLEAN CpuHybridStorageConnected;
50 UINT8 Reserved[3];
51 } PCH_HYBRIDSTORAGE_HOB;
52
53 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoDefs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchInfoDefs.h File Reference

Header file for PchInfoDefs. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Header file for PchInfoDefs.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchInfoDefs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoDefs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchInfoDefs.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchInfoDefs.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_INFO_DEFS_H_
36 #define _PCH_INFO_DEFS_H_
37
38
39 #define PCH_A0 0x00
40 #define PCH_A1 0x01
41 #define PCH_B0 0x10
42 #define PCH_B1 0x11
43 #define PCH_C0 0x20
44 #define PCH_C1 0x21
45 #define PCH_D0 0x30
46 #define PCH_D1 0x31
47 #define PCH_Z0 0xF0
48 #define PCH_Z1 0xF1
49 #define PCH_STEPPING_MAX 0xFF
50
51 #define PCH_H 1
52 #define PCH_LP 2
53 #define PCH_N 3
54 #define PCH_S 4
55 #define PCH_P 5
56 #define PCH_M 6
57 #define PCH_SERVER 0x80
58 #define PCH_UNKNOWN_SERIES 0xFF
59
60 #define CNL_PCH 3
61 #define ICL_PCH 4
62 #define TGL_PCH 5
63 #define JSL_PCH 6
64 #define ADL_PCH 7
65 #define CDF_PCH 0x80
66 #define EBG_PCH 0x81
67 #define S3M2_IBL 0x90
68 #define PCH_UNKNOWN_GENERATION 0xFF
69
70 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Classes
PchInfoHob.h File Reference

This file contains definitions of PCH Info HOB. More...

#include <PchLimits.h>
Include dependency graph for PchInfoHob.h:

Go to the source code of this file.

Classes

struct PCH_INFO_HOB
This structure is used to provide the information of PCH controller. More...

Detailed Description

This file contains definitions of PCH Info HOB.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchInfoHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of PCH Info HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_INFO_HOB_H_
36 #define _PCH_INFO_HOB_H_
37
38 extern EFI_GUID gPchInfoHobGuid;
39
40 #include <PchLimits.h>
41
42 #define PCH_INFO_HOB_REVISION 5
43
44 #pragma pack (push,1)
45 /**
46 This structure is used to provide the information of PCH controller.
47
48 <b>Revision 1</b>:
49 - Initial version.
50 <b>Revision 2</b>:
51 - Add CridSupport, CridOrgRid, and CridNewRid.
52 <b>Revision 3</b>:
53 - Add Thc0Strap.
54 <b>Revision 4</b>
55 - Removed GbePciePortNumber
56 <b>Revision 5</b>
57 - Add AudioDspFusedOut
58 **/
59 typedef struct {
60 /**
61 This member specifies the revision of the PCH Info HOB. This field is used
62 to indicate backwards compatible changes to the protocol. Platform code that
63 consumes this protocol must read the correct revision value to correctly interpret
64 the content of the protocol fields.
65 **/
66 UINT8 Revision;
67 UINT8 PcieControllerCfg[PCH_MAX_PCIE_CONTROLLERS];
68 /**
69 THC strap disable/enable status
70 **/
71 UINT8 Thc0Strap;
72 UINT32 PciePortFuses;
73 /**
74 Bit map for PCIe Root Port Lane setting. If bit is set it means that
75 corresponding Root Port has its lane enabled.
76 BIT0 - RP0, BIT1 - RP1, ...
77 This information needs to be passed through HOB as FIA registers
78 are not accessible with POSTBOOT_SAI
79 **/
80 UINT32 PciePortLaneEnabled;
81 /**
82 Publish Hpet BDF and IoApic BDF information for VTD.
83 **/
84 UINT32 HpetBusNum : 8;
85 UINT32 HpetDevNum : 5;
86 UINT32 HpetFuncNum : 3;
87 UINT32 IoApicBusNum : 8;
88 UINT32 IoApicDevNum : 5;
89 UINT32 IoApicFuncNum : 3;
90 /**
91 Publish the CRID information.
92 **/
93 UINT32 CridOrgRid : 8;
94 UINT32 CridNewRid : 8;
95 UINT32 CridSupport : 1;
96 /**
97 Publish the HDA information.
98 **/
99 UINT32 AudioDspFusedOut : 1;
100 UINT32 Rsvdbits : 14;
101 } PCH_INFO_HOB;
102
103 #pragma pack (pop)
104
105 #endif // _PCH_INFO_HOB_H_
106
PCH_INFO_HOB::Thc0Strap
UINT8 Thc0Strap
THC strap disable/enable status.
Definition: PchInfoHob.h:71
PCH_INFO_HOB::PciePortLaneEnabled
UINT32 PciePortLaneEnabled
Bit map for PCIe Root Port Lane setting.
Definition: PchInfoHob.h:80
PCH_INFO_HOB::Revision
UINT8 Revision
This member specifies the revision of the PCH Info HOB.
Definition: PchInfoHob.h:66
PCH_INFO_HOB::HpetBusNum
UINT32 HpetBusNum
Publish Hpet BDF and IoApic BDF information for VTD.
Definition: PchInfoHob.h:84
PCH_INFO_HOB::CridOrgRid
UINT32 CridOrgRid
Publish the CRID information.
Definition: PchInfoHob.h:93
PCH_INFO_HOB::AudioDspFusedOut
UINT32 AudioDspFusedOut
Publish the HDA information.
Definition: PchInfoHob.h:99
PCH_INFO_HOB
This structure is used to provide the information of PCH controller.
Definition: PchInfoHob.h:59
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Functions
PchInfoLib.h File Reference

Header file for PchInfoLib. More...

#include <Hda.h>
#include <Uefi/UefiBaseType.h>
#include "PchInfoDefs.h"
Include dependency graph for PchInfoLib.h:

Go to the source code of this file.

Functions

UINT16 | PchGetLpcDid (VOID)
Return LPC Device Id. More...
PCH_STEPPING | PchStepping (VOID)
Return Pch stepping type. More...
BOOLEAN | IsPchSupported (VOID)
Determine if PCH is supported. More...
PCH_SERIES | PchSeries (VOID)
Return Pch Series. More...
BOOLEAN | IsPchLp (VOID)
Check if this is PCH LP series. More...
BOOLEAN | IsPchH (VOID)
Check if this is PCH H series. More...
BOOLEAN | IsPchN (VOID)
Check if this is PCH N series. More...
BOOLEAN | IsPchP (VOID)
Check if this is PCH P series. More...
BOOLEAN | IsPchM (VOID)
Check if this is PCH M series. More...
BOOLEAN | IsPchS (VOID)
Check if this is PCH S series. More...
BOOLEAN | IsPchServer (VOID)
Check if this is Server PCH. More...
PCH_GENERATION | PchGeneration (VOID)
Return Pch Generation. More...
BOOLEAN | IsEbgPch (VOID)
Check if this is EBG PCH generation. More...
BOOLEAN | IsAdlPch (VOID)
Check if this is ADL PCH generation. More...
BOOLEAN | IsS3m2Ibl (VOID)
Check if this is S3m2.0 IBL generation. More...
UINT8 | GetPchMaxPciePortNum (VOID)
Get Pch Maximum Pcie Root Port Number. More...
UINT8 | GetPchMaxPcieControllerNum (VOID)
Get Pch Maximum Pcie Controller Number. More...
UINT8 | GetPchMaxPcieClockNum (VOID)
Get Pch Maximum Pcie Clock Number. More...
UINT8 | GetPchMaxPcieClockReqNum (VOID)
Get Pch Maximum Pcie ClockReq Number. More...
UINT8 | GetPchUsb2MaxPhysicalPortNum (VOID)
Get Pch Usb2 Maximum Physical Port Number. More...
UINT8 | GetPchXhciMaxUsb2PortNum (VOID)
Get Pch Maximum Usb2 Port Number of XHCI Controller. More...
UINT8 | GetPchUsb3MaxPhysicalPortNum (VOID)
Get Pch Usb3 Maximum Physical Port Number. More...
UINT8 | GetPchXhciMaxUsb3PortNum (VOID)
Get Pch Maximum Usb3 Port Number of XHCI Controller. More...
UINT8 | GetPchUsbrKvmPortNum (VOID)
Get Pch USB-R Port Number for KVM session. More...
UINT8 | GetPchUsbrStoragePortNum (VOID)
Get Pch USB-R Port Number for Storage session. More...
UINT8 | GetPchMaxSerialIoI2cControllersNum (VOID)
Get Pch Maximum Serial IO I2C controllers number. More...
UINT8 | GetPchMaxSerialIoI3cControllersNum (VOID)
Get Pch Maximum Serial IO I3C controllers number. More...
UINT8 | GetPchMaxSerialIoSpiControllersNum (VOID)
Get Pch Maximum Serial IO SPI controllers number. More...
UINT8 | GetPchMaxSerialIoUartControllersNum (VOID)
Get Pch Maximum Serial IO UART controllers number. More...
UINT8 | GetPchMaxSerialIoSpiChipSelectsNum (VOID)
Get Pch Maximum Serial IO SPI Chip Selects count. More...
UINT8 | GetPchMaxIshUartControllersNum (VOID)
Get Pch Maximum ISH UART Controller number. More...
UINT8 | GetPchMaxIshI2cControllersNum (VOID)
Get Pch Maximum ISH I2C Controller number. More...
UINT8 | GetPchMaxIshSpiControllersNum (VOID)
Get Pch Maximum ISH SPI Controller number. More...
UINT8 | GetPchMaxIshSpiControllerCsPinsNum (VOID)
Get Pch Maximum ISH SPI Controller Cs pins number. More...
UINT8 | GetPchMaxIshGpNum (VOID)
Get Pch Maximum ISH GP number. More...
UINT8 | GetPchMaxMeAppletCount (VOID)
Get Pch Maximum ME Applet count. More...
UINT8 | GetPchMaxMeSessionCount (VOID)
Get Pch Maximum ME Session count. More...
UINT8 | GetPchMaxTypeCPortNum (VOID)
Get Pch Maximum Type C Port Number. More...
EFI_STATUS | PchGetSteppingStr (OUT CHAR8 *Buffer, IN UINT32 BufferSize)
Get PCH stepping ASCII string. More...
CHAR8 * | PchGetSeriesStr ()
Get PCH series ASCII string. More...
CHAR8 * | PchGetSkuStr (VOID)
Get PCH Sku ASCII string The return string is zero terminated. More...
BOOLEAN | IsPchEmmcSupported (VOID)
Check if this chipset supports eMMC controller. More...
BOOLEAN | IsPchSdCardSupported (VOID)
Check if this chipset supports SD controller. More...
BOOLEAN | IsPchThcSupported (VOID)
Check if this chipset supports THC controller. More...
BOOLEAN | IsPchChipsetInitSyncSupported (VOID)
Check if this chipset supports HSIO BIOS Sync. More...
UINT8 | PchGetMaxUfsNum (VOID)
Gets the maximum number of UFS controller supported by this chipset. More...
RST_MODE | PchGetSupportedRstMode (VOID)
Get RST mode supported by the silicon. More...
BOOLEAN | PchIsGbeSupported (VOID)
Check whether integrated LAN controller is supported. More...
BOOLEAN | PchIsTsnSupported (VOID)
Check whether integrated TSN is supported. More...
BOOLEAN | PchIsIshSupported (VOID)
Check whether ISH is supported. More...
BOOLEAN | IsPchPSOnSupported (VOID)
Check whether ATX Shutdown (PS_ON) is supported. More...
UINT8 | GetPchHdaMaxSndwLinkNum (VOID)
Get Pch Maximum Hda Sndw Link. More...
UINT8 | GetPchHdaMaxSspLinkNum (VOID)
Get Pch Maximum Hda Ssp Link. More...
UINT8 | GetPchHdaMaxDmicLinkNum (VOID)
Get Pch Maximum Hda Dmic Link. More...
BOOLEAN | IsAudioInterfaceSupported (IN HDAUDIO_LINK_TYPE AudioLinkType, IN UINT32 AudioLinkIndex)
Check if given Audio Interface is supported. More...
BOOLEAN | IsPchWithPdmi (VOID)
Check if link between PCH and CPU is an P-DMI. More...
BOOLEAN | IsPchWithOpdmi (VOID)
Check if link between PCH and CPU is an OP-DMI. More...
BOOLEAN | IsPchWithFdmi (VOID)
Check if link between PCH and CPU is an F-DMI. More...
UINT8 | GetPchMaxThcCount (VOID)
Get Pch Maximum THC count. More...
BOOLEAN | IsPchThcHidModeSupported (VOID)
Check if this generation supports THC controller in HID over SPI mode. More...
BOOLEAN | IsP2sb20bPcrSupported (VOID)
return support status for P2SB PCR 20-bit addressing More...
BOOLEAN | IsExtendedBiosRangeDecodeSupported (VOID)
Check if SPI in a given PCH generation supports an Extended BIOS Range Decode. More...
UINT16 | GetPchSpiDmiTarget (VOID)
Returns DMI target for current PCH SPI. More...

Detailed Description

Header file for PchInfoLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchInfoLib.h.

Function Documentation

◆ GetPchHdaMaxDmicLinkNum()

UINT8 GetPchHdaMaxDmicLinkNum ( VOID )

Get Pch Maximum Hda Dmic Link.

Return values
Pch Maximum Hda Dmic Link

◆ GetPchHdaMaxSndwLinkNum()

UINT8 GetPchHdaMaxSndwLinkNum ( VOID )

Get Pch Maximum Hda Sndw Link.

Return values
Pch Maximum Hda Sndw Link

◆ GetPchHdaMaxSspLinkNum()

UINT8 GetPchHdaMaxSspLinkNum ( VOID )

Get Pch Maximum Hda Ssp Link.

Return values
Pch Maximum Hda Ssp Link

◆ GetPchMaxIshGpNum()

UINT8 GetPchMaxIshGpNum ( VOID )

Get Pch Maximum ISH GP number.

Return values
Pch Maximum ISH GP number

◆ GetPchMaxIshI2cControllersNum()

UINT8 GetPchMaxIshI2cControllersNum ( VOID )

Get Pch Maximum ISH I2C Controller number.

Return values
Pch Maximum ISH I2C controllers number

◆ GetPchMaxIshSpiControllerCsPinsNum()

UINT8 GetPchMaxIshSpiControllerCsPinsNum ( VOID )

Get Pch Maximum ISH SPI Controller Cs pins number.

Return values
Pch Maximum ISH SPI controller Cs pins number

◆ GetPchMaxIshSpiControllersNum()

UINT8 GetPchMaxIshSpiControllersNum ( VOID )

Get Pch Maximum ISH SPI Controller number.

Return values
Pch Maximum ISH SPI controllers number

◆ GetPchMaxIshUartControllersNum()

UINT8 GetPchMaxIshUartControllersNum ( VOID )

Get Pch Maximum ISH UART Controller number.

Return values
Pch Maximum ISH UART controllers number

◆ GetPchMaxMeAppletCount()

UINT8 GetPchMaxMeAppletCount ( VOID )

Get Pch Maximum ME Applet count.

Return values
Pch Maximum ME Applet number

◆ GetPchMaxMeSessionCount()

UINT8 GetPchMaxMeSessionCount ( VOID )

Get Pch Maximum ME Session count.

Return values
Pch Maximum ME Sesion number

◆ GetPchMaxPcieClockNum()

UINT8 GetPchMaxPcieClockNum ( VOID )

Get Pch Maximum Pcie Clock Number.

Return values
Pch Maximum Pcie Clock Number

◆ GetPchMaxPcieClockReqNum()

UINT8 GetPchMaxPcieClockReqNum ( VOID )

Get Pch Maximum Pcie ClockReq Number.

Return values
Pch Maximum Pcie ClockReq Number

◆ GetPchMaxPcieControllerNum()

UINT8 GetPchMaxPcieControllerNum ( VOID )

Get Pch Maximum Pcie Controller Number.

Return values
Pch Maximum Pcie Controller Number

◆ GetPchMaxPciePortNum()

UINT8 GetPchMaxPciePortNum ( VOID )

Get Pch Maximum Pcie Root Port Number.

Return values
PcieMaxRootPort Pch Maximum Pcie Root Port Number

◆ GetPchMaxSerialIoI2cControllersNum()

UINT8 GetPchMaxSerialIoI2cControllersNum ( VOID )

Get Pch Maximum Serial IO I2C controllers number.

Return values
Pch Maximum Serial IO I2C controllers number

◆ GetPchMaxSerialIoI3cControllersNum()

UINT8 GetPchMaxSerialIoI3cControllersNum ( VOID )

Get Pch Maximum Serial IO I3C controllers number.

Return values
Pch Maximum Serial IO I3C controllers number

◆ GetPchMaxSerialIoSpiChipSelectsNum()

UINT8 GetPchMaxSerialIoSpiChipSelectsNum ( VOID )

Get Pch Maximum Serial IO SPI Chip Selects count.

Return values
Pch Maximum Serial IO SPI Chip Selects nu,ber

◆ GetPchMaxSerialIoSpiControllersNum()

UINT8 GetPchMaxSerialIoSpiControllersNum ( VOID )

Get Pch Maximum Serial IO SPI controllers number.

Return values
Pch Maximum Serial IO SPI controllers number

◆ GetPchMaxSerialIoUartControllersNum()

UINT8 GetPchMaxSerialIoUartControllersNum ( VOID )

Get Pch Maximum Serial IO UART controllers number.

Return values
Pch Maximum Serial IO UART controllers number

◆ GetPchMaxThcCount()

UINT8 GetPchMaxThcCount ( VOID )

Get Pch Maximum THC count.

Return values
Pch Maximum THC count number

◆ GetPchMaxTypeCPortNum()

UINT8 GetPchMaxTypeCPortNum ( VOID )

Get Pch Maximum Type C Port Number.

Return values
Pch Maximum Type C Port Number

◆ GetPchSpiDmiTarget()

UINT16 GetPchSpiDmiTarget ( VOID )

Returns DMI target for current PCH SPI.

Return values
PCH SPI DMI target

◆ GetPchUsb2MaxPhysicalPortNum()

UINT8 GetPchUsb2MaxPhysicalPortNum ( VOID )

Get Pch Usb2 Maximum Physical Port Number.

Return values
Pch Usb2 Maximum Physical Port Number

◆ GetPchUsb3MaxPhysicalPortNum()

UINT8 GetPchUsb3MaxPhysicalPortNum ( VOID )

Get Pch Usb3 Maximum Physical Port Number.

Return values
Pch Usb3 Maximum Physical Port Number

◆ GetPchUsbrKvmPortNum()

UINT8 GetPchUsbrKvmPortNum ( VOID )

Get Pch USB-R Port Number for KVM session.

Return values
Pch USB-R Port Number for KVM session

◆ GetPchUsbrStoragePortNum()

UINT8 GetPchUsbrStoragePortNum ( VOID )

Get Pch USB-R Port Number for Storage session.

Return values
Pch USB-R Port Number for Storage session

◆ GetPchXhciMaxUsb2PortNum()

UINT8 GetPchXhciMaxUsb2PortNum ( VOID )

Get Pch Maximum Usb2 Port Number of XHCI Controller.

Return values
Pch Maximum Usb2 Port Number of XHCI Controller

◆ GetPchXhciMaxUsb3PortNum()

UINT8 GetPchXhciMaxUsb3PortNum ( VOID )

Get Pch Maximum Usb3 Port Number of XHCI Controller.

Return values
Pch Maximum Usb3 Port Number of XHCI Controller

◆ IsAdlPch()

BOOLEAN IsAdlPch ( VOID )

Check if this is ADL PCH generation.

Return values
TRUE | It's ADL PCH
FALSE | It's not ADL PCH

◆ IsAudioInterfaceSupported()

BOOLEAN IsAudioInterfaceSupported | ( | IN HDAUDIO_LINK_TYPE | AudioLinkType,
 |  | IN UINT32 | AudioLinkIndex
 | ) |  |

Check if given Audio Interface is supported.

Parameters
[in] | AudioLinkType | Link type support to be checked
[in] | AudioLinkIndex | Link number
Return values
TRUE | Link supported
FALSE | Link not supported

◆ IsEbgPch()

BOOLEAN IsEbgPch ( VOID )

Check if this is EBG PCH generation.

Return values
TRUE | It's EBG PCH
FALSE | It's not EBG PCH

◆ IsExtendedBiosRangeDecodeSupported()

BOOLEAN IsExtendedBiosRangeDecodeSupported ( VOID )

Check if SPI in a given PCH generation supports an Extended BIOS Range Decode.

Return values
TRUE or FALSE if PCH supports Extended BIOS Range Decode

◆ IsP2sb20bPcrSupported()

BOOLEAN IsP2sb20bPcrSupported ( VOID )

return support status for P2SB PCR 20-bit addressing

Return values
TRUE
FALSE

◆ IsPchChipsetInitSyncSupported()

BOOLEAN IsPchChipsetInitSyncSupported ( VOID )

Check if this chipset supports HSIO BIOS Sync.

Return values
BOOLEAN TRUE if supported, FALSE otherwise

◆ IsPchEmmcSupported()

BOOLEAN IsPchEmmcSupported ( VOID )

Check if this chipset supports eMMC controller.

Return values
BOOLEAN TRUE if supported, FALSE otherwise

◆ IsPchH()

BOOLEAN IsPchH ( VOID )

Check if this is PCH H series.

Return values
TRUE | It's PCH H series
FALSE | It's not PCH H series

◆ IsPchLp()

BOOLEAN IsPchLp ( VOID )

Check if this is PCH LP series.

Return values
TRUE | It's PCH LP series
FALSE | It's not PCH LP series

◆ IsPchM()

BOOLEAN IsPchM ( VOID )

Check if this is PCH M series.

Return values
TRUE | It's PCH M series
FALSE | It's not PCH M series

◆ IsPchN()

BOOLEAN IsPchN ( VOID )

Check if this is PCH N series.

Return values
TRUE | It's PCH N series
FALSE | It's not PCH N series

◆ IsPchP()

BOOLEAN IsPchP ( VOID )

Check if this is PCH P series.

Return values
TRUE | It's PCH P series
FALSE | It's not PCH P series

◆ IsPchPSOnSupported()

BOOLEAN IsPchPSOnSupported ( VOID )

Check whether ATX Shutdown (PS_ON) is supported.

Return values
TRUE | ATX Shutdown (PS_ON) is supported in PCH
FALSE | ATX Shutdown (PS_ON) is not supported by PCH

◆ IsPchS()

BOOLEAN IsPchS ( VOID )

Check if this is PCH S series.

Return values
TRUE | It's PCH S series
FALSE | It's not PCH S series

◆ IsPchSdCardSupported()

BOOLEAN IsPchSdCardSupported ( VOID )

Check if this chipset supports SD controller.

Return values
BOOLEAN TRUE if supported, FALSE otherwise

◆ IsPchServer()

BOOLEAN IsPchServer ( VOID )

Check if this is Server PCH.

Return values
TRUE | It's a Server PCH
FALSE | It's not a Server PCH

◆ IsPchSupported()

BOOLEAN IsPchSupported ( VOID )

Determine if PCH is supported.

Return values
TRUE | PCH is supported
FALSE | PCH is not supported

◆ IsPchThcHidModeSupported()

BOOLEAN IsPchThcHidModeSupported ( VOID )

Check if this generation supports THC controller in HID over SPI mode.

Return values
THC HID Mode support

◆ IsPchThcSupported()

BOOLEAN IsPchThcSupported ( VOID )

Check if this chipset supports THC controller.

Return values
BOOLEAN TRUE if supported, FALSE otherwise

◆ IsPchWithFdmi()

BOOLEAN IsPchWithFdmi ( VOID )

Check if link between PCH and CPU is an F-DMI.

Return values
TRUE | F-DMI link
FALSE | Not an F-DMI link

◆ IsPchWithOpdmi()

BOOLEAN IsPchWithOpdmi ( VOID )

Check if link between PCH and CPU is an OP-DMI.

Return values
TRUE | OP-DMI link
FALSE | Not an OP-DMI link

◆ IsPchWithPdmi()

BOOLEAN IsPchWithPdmi ( VOID )

Check if link between PCH and CPU is an P-DMI.

Return values
TRUE | P-DMI link
FALSE | Not an P-DMI link

◆ IsS3m2Ibl()

BOOLEAN IsS3m2Ibl ( VOID )

Check if this is S3m2.0 IBL generation.

Return values
TRUE | It's S3m 2.0 IBL
FALSE | It's not S3m 2.0 IBL

◆ PchGeneration()

PCH_GENERATION PchGeneration ( VOID )

Return Pch Generation.

Return values
PCH_GENERATION Pch Generation

◆ PchGetLpcDid()

UINT16 PchGetLpcDid ( VOID )

Return LPC Device Id.

Return values
PCH_LPC_DEVICE_ID PCH Lpc Device ID

◆ PchGetMaxUfsNum()

UINT8 PchGetMaxUfsNum ( VOID )

Gets the maximum number of UFS controller supported by this chipset.

Returns
Number of supported UFS controllers

◆ PchGetSeriesStr()

CHAR8* PchGetSeriesStr ( )

Get PCH series ASCII string.

The return string is zero terminated.

Return values
Static ASCII string of PCH Series

◆ PchGetSkuStr()

CHAR8* PchGetSkuStr ( VOID )

Get PCH Sku ASCII string The return string is zero terminated.

Return values
Static ASCII string of PCH Sku

◆ PchGetSteppingStr()

EFI_STATUS PchGetSteppingStr | ( | OUT CHAR8 * | Buffer,
 |  | IN UINT32 | BufferSize
 | ) |  |

Get PCH stepping ASCII string.

Function determines major and minor stepping versions and writes them into a buffer. The return string is zero terminated

Parameters
[out] | Buffer | Output buffer of string
[in] | BufferSize | Buffer size. Must not be less then PCH_STEPPING_STR_LENGTH_MAX
Return values
EFI_SUCCESS | String copied successfully
EFI_INVALID_PARAMETER | The stepping is not supported, or parameters are NULL
EFI_BUFFER_TOO_SMALL | Input buffer size is too small

◆ PchGetSupportedRstMode()

RST_MODE PchGetSupportedRstMode ( VOID )

Get RST mode supported by the silicon.

Return values
RST_MODE RST mode supported by silicon

◆ PchIsGbeSupported()

BOOLEAN PchIsGbeSupported ( VOID )

Check whether integrated LAN controller is supported.

Return values
TRUE | GbE is supported in PCH
FALSE | GbE is not supported by PCH

◆ PchIsIshSupported()

BOOLEAN PchIsIshSupported ( VOID )

Check whether ISH is supported.

Return values
TRUE | ISH is supported in PCH
FALSE | ISH is not supported by PCH

◆ PchIsTsnSupported()

BOOLEAN PchIsTsnSupported ( VOID )

Check whether integrated TSN is supported.

Return values
TRUE | TSN is supported in current PCH
FALSE | TSN is not supported on current PCH

◆ PchSeries()

PCH_SERIES PchSeries ( VOID )

Return Pch Series.

Return values
PCH_SERIES Pch Series

◆ PchStepping()

PCH_STEPPING PchStepping ( VOID )

Return Pch stepping type.

Return values
PCH_STEPPING Pch stepping type
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchInfoLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_INFO_LIB_H_
36 #define _PCH_INFO_LIB_H_
37
38 #include <Hda.h>
39 #include <Uefi/UefiBaseType.h>
40 #include "PchInfoDefs.h"
41
42 typedef UINT8 PCH_STEPPING;
43 typedef UINT8 PCH_SERIES;
44 typedef UINT8 PCH_GENERATION;
45
46 typedef enum {
47 RstUnsupported = 0,
48 RstPremium,
49 RstOptane,
50 RstMaxMode
51 } RST_MODE;
52
53 /**
54 Return LPC Device Id
55
56 @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
57 **/
58 UINT16
59 PchGetLpcDid (
60 VOID
61 );
62
63 /**
64 Return Pch stepping type
65
66 @retval PCH_STEPPING Pch stepping type
67 **/
68 PCH_STEPPING
69 PchStepping (
70 VOID
71 );
72
73 /**
74 Determine if PCH is supported
75
76 @retval TRUE PCH is supported
77 @retval FALSE PCH is not supported
78 **/
79 BOOLEAN
80 IsPchSupported (
81 VOID
82 );
83
84 /**
85 Return Pch Series
86
87 @retval PCH_SERIES Pch Series
88 **/
89 PCH_SERIES
90 PchSeries (
91 VOID
92 );
93
94 /**
95 Check if this is PCH LP series
96
97 @retval TRUE It's PCH LP series
98 @retval FALSE It's not PCH LP series
99 **/
100 BOOLEAN
101 IsPchLp (
102 VOID
103 );
104
105 /**
106 Check if this is PCH H series
107
108 @retval TRUE It's PCH H series
109 @retval FALSE It's not PCH H series
110 **/
111 BOOLEAN
112 IsPchH (
113 VOID
114 );
115
116 /**
117 Check if this is PCH N series
118
119 @retval TRUE It's PCH N series
120 @retval FALSE It's not PCH N series
121 **/
122 BOOLEAN
123 IsPchN (
124 VOID
125 );
126
127 /**
128 Check if this is PCH P series
129
130 @retval TRUE It's PCH P series
131 @retval FALSE It's not PCH P series
132 **/
133 BOOLEAN
134 IsPchP (
135 VOID
136 );
137
138 /**
139 Check if this is PCH M series
140
141 @retval TRUE It's PCH M series
142 @retval FALSE It's not PCH M series
143 **/
144 BOOLEAN
145 IsPchM (
146 VOID
147 );
148
149 /**
150 Check if this is PCH S series
151
152 @retval TRUE It's PCH S series
153 @retval FALSE It's not PCH S series
154 **/
155 BOOLEAN
156 IsPchS (
157 VOID
158 );
159
160 /**
161 Check if this is Server PCH
162
163 @retval TRUE It's a Server PCH
164 @retval FALSE It's not a Server PCH
165 **/
166 BOOLEAN
167 IsPchServer (
168 VOID
169 );
170
171 /**
172 Return Pch Generation
173
174 @retval PCH_GENERATION Pch Generation
175 **/
176 PCH_GENERATION
177 PchGeneration (
178 VOID
179 );
180
181
182 /**
183 Check if this is EBG PCH generation
184
185 @retval TRUE It's EBG PCH
186 @retval FALSE It's not EBG PCH
187 **/
188 BOOLEAN
189 IsEbgPch (
190 VOID
191 );
192
193 /**
194 Check if this is ADL PCH generation
195
196 @retval TRUE It's ADL PCH
197 @retval FALSE It's not ADL PCH
198 **/
199 BOOLEAN
200 IsAdlPch (
201 VOID
202 );
203
204
205
206 /**
207 Check if this is S3m2.0 IBL generation
208
209 @retval TRUE It's S3m 2.0 IBL
210 @retval FALSE It's not S3m 2.0 IBL
211 **/
212 BOOLEAN
213 IsS3m2Ibl (
214 VOID
215 );
216
217 /**
218 Get Pch Maximum Pcie Root Port Number
219
220 @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
221 **/
222 UINT8
223 GetPchMaxPciePortNum (
224 VOID
225 );
226
227 /**
228 Get Pch Maximum Pcie Controller Number
229
230 @retval Pch Maximum Pcie Controller Number
231 **/
232 UINT8
233 GetPchMaxPcieControllerNum (
234 VOID
235 );
236
237 /**
238 Get Pch Maximum Pcie Clock Number
239
240 @retval Pch Maximum Pcie Clock Number
241 **/
242 UINT8
243 GetPchMaxPcieClockNum (
244 VOID
245 );
246
247 /**
248 Get Pch Maximum Pcie ClockReq Number
249
250 @retval Pch Maximum Pcie ClockReq Number
251 **/
252 UINT8
253 GetPchMaxPcieClockReqNum (
254 VOID
255 );
256
257 /**
258 Get Pch Usb2 Maximum Physical Port Number
259
260 @retval Pch Usb2 Maximum Physical Port Number
261 **/
262 UINT8
263 GetPchUsb2MaxPhysicalPortNum (
264 VOID
265 );
266
267 /**
268 Get Pch Maximum Usb2 Port Number of XHCI Controller
269
270 @retval Pch Maximum Usb2 Port Number of XHCI Controller
271 **/
272 UINT8
273 GetPchXhciMaxUsb2PortNum (
274 VOID
275 );
276
277 /**
278 Get Pch Usb3 Maximum Physical Port Number
279
280 @retval Pch Usb3 Maximum Physical Port Number
281 **/
282 UINT8
283 GetPchUsb3MaxPhysicalPortNum (
284 VOID
285 );
286
287 /**
288 Get Pch Maximum Usb3 Port Number of XHCI Controller
289
290 @retval Pch Maximum Usb3 Port Number of XHCI Controller
291 **/
292 UINT8
293 GetPchXhciMaxUsb3PortNum (
294 VOID
295 );
296
297 /**
298 Get Pch USB-R Port Number for KVM session
299
300 @retval Pch USB-R Port Number for KVM session
301 **/
302 UINT8
303 GetPchUsbrKvmPortNum (
304 VOID
305 );
306
307 /**
308 Get Pch USB-R Port Number for Storage session
309
310 @retval Pch USB-R Port Number for Storage session
311 **/
312 UINT8
313 GetPchUsbrStoragePortNum (
314 VOID
315 );
316
317 /**
318 Get Pch Maximum Serial IO I2C controllers number
319
320 @retval Pch Maximum Serial IO I2C controllers number
321 **/
322 UINT8
323 GetPchMaxSerialIoI2cControllersNum (
324 VOID
325 );
326
327 /**
328 Get Pch Maximum Serial IO I3C controllers number
329
330 @retval Pch Maximum Serial IO I3C controllers number
331 **/
332 UINT8
333 GetPchMaxSerialIoI3cControllersNum (
334 VOID
335 );
336
337 /**
338 Get Pch Maximum Serial IO SPI controllers number
339
340 @retval Pch Maximum Serial IO SPI controllers number
341 **/
342 UINT8
343 GetPchMaxSerialIoSpiControllersNum (
344 VOID
345 );
346
347 /**
348 Get Pch Maximum Serial IO UART controllers number
349
350 @retval Pch Maximum Serial IO UART controllers number
351 **/
352 UINT8
353 GetPchMaxSerialIoUartControllersNum (
354 VOID
355 );
356
357 /**
358 Get Pch Maximum Serial IO SPI Chip Selects count
359
360 @retval Pch Maximum Serial IO SPI Chip Selects nu,ber
361 **/
362 UINT8
363 GetPchMaxSerialIoSpiChipSelectsNum (
364 VOID
365 );
366
367 /**
368 Get Pch Maximum ISH UART Controller number
369
370 @retval Pch Maximum ISH UART controllers number
371 **/
372 UINT8
373 GetPchMaxIshUartControllersNum (
374 VOID
375 );
376
377 /**
378 Get Pch Maximum ISH I2C Controller number
379
380 @retval Pch Maximum ISH I2C controllers number
381 **/
382 UINT8
383 GetPchMaxIshI2cControllersNum (
384 VOID
385 );
386
387 /**
388 Get Pch Maximum ISH SPI Controller number
389
390 @retval Pch Maximum ISH SPI controllers number
391 **/
392 UINT8
393 GetPchMaxIshSpiControllersNum (
394 VOID
395 );
396
397 /**
398 Get Pch Maximum ISH SPI Controller Cs pins number
399
400 @retval Pch Maximum ISH SPI controller Cs pins number
401 **/
402 UINT8
403 GetPchMaxIshSpiControllerCsPinsNum (
404 VOID
405 );
406
407 /**
408 Get Pch Maximum ISH GP number
409
410 @retval Pch Maximum ISH GP number
411 **/
412 UINT8
413 GetPchMaxIshGpNum (
414 VOID
415 );
416
417 /**
418 Get Pch Maximum ME Applet count
419
420 @retval Pch Maximum ME Applet number
421 **/
422 UINT8
423 GetPchMaxMeAppletCount (
424 VOID
425 );
426
427 /**
428 Get Pch Maximum ME Session count
429
430 @retval Pch Maximum ME Sesion number
431 **/
432 UINT8
433 GetPchMaxMeSessionCount(
434 VOID
435 );
436
437 /**
438 Get Pch Maximum Type C Port Number
439
440 @retval Pch Maximum Type C Port Number
441 **/
442 UINT8
443 GetPchMaxTypeCPortNum (
444 VOID
445 );
446
447 #define PCH_STEPPING_STR_LENGTH_MAX 3
448
449 /**
450 Get PCH stepping ASCII string.
451 Function determines major and minor stepping versions and writes them into a buffer.
452 The return string is zero terminated
453
454 @param [out] Buffer Output buffer of string
455 @param [in] BufferSize Buffer size.
456 Must not be less then PCH_STEPPING_STR_LENGTH_MAX
457
458 @retval EFI_SUCCESS String copied successfully
459 @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL
460 @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
461 **/
462 EFI_STATUS
463 PchGetSteppingStr (
464 OUT CHAR8 *Buffer,
465 IN UINT32 BufferSize
466 );
467
468 /**
469 Get PCH series ASCII string.
470 The return string is zero terminated.
471
472 @retval Static ASCII string of PCH Series
473 **/
474 CHAR8*
475 PchGetSeriesStr (
476 );
477
478 /**
479 Get PCH Sku ASCII string
480 The return string is zero terminated.
481
482 @retval Static ASCII string of PCH Sku
483 **/
484 CHAR8*
485 PchGetSkuStr (
486 VOID
487 );
488
489 /**
490 Check if this chipset supports eMMC controller
491
492 @retval BOOLEAN TRUE if supported, FALSE otherwise
493 **/
494 BOOLEAN
495 IsPchEmmcSupported (
496 VOID
497 );
498
499 /**
500 Check if this chipset supports SD controller
501
502 @retval BOOLEAN TRUE if supported, FALSE otherwise
503 **/
504 BOOLEAN
505 IsPchSdCardSupported (
506 VOID
507 );
508
509 /**
510 Check if this chipset supports THC controller
511
512 @retval BOOLEAN TRUE if supported, FALSE otherwise
513 **/
514 BOOLEAN
515 IsPchThcSupported (
516 VOID
517 );
518
519 /**
520 Check if this chipset supports HSIO BIOS Sync
521
522 @retval BOOLEAN TRUE if supported, FALSE otherwise
523 **/
524 BOOLEAN
525 IsPchChipsetInitSyncSupported (
526 VOID
527 );
528
529 /**
530 Gets the maximum number of UFS controller supported by this chipset.
531
532 @return Number of supported UFS controllers
533 **/
534 UINT8
535 PchGetMaxUfsNum (
536 VOID
537 );
538
539 /**
540 Get RST mode supported by the silicon
541
542 @retval RST_MODE RST mode supported by silicon
543 **/
544 RST_MODE
545 PchGetSupportedRstMode (
546 VOID
547 );
548
549 /**
550 Check whether integrated LAN controller is supported.
551
552 @retval TRUE GbE is supported in PCH
553 @retval FALSE GbE is not supported by PCH
554 **/
555 BOOLEAN
556 PchIsGbeSupported (
557 VOID
558 );
559
560 /**
561 Check whether integrated TSN is supported.
562
563 @retval TRUE TSN is supported in current PCH
564 @retval FALSE TSN is not supported on current PCH
565 **/
566 BOOLEAN
567 PchIsTsnSupported (
568 VOID
569 );
570
571 /**
572 Check whether ISH is supported.
573
574 @retval TRUE ISH is supported in PCH
575 @retval FALSE ISH is not supported by PCH
576 **/
577 BOOLEAN
578 PchIsIshSupported (
579 VOID
580 );
581
582 /**
583 Check whether ATX Shutdown (PS_ON) is supported.
584
585 @retval TRUE ATX Shutdown (PS_ON) is supported in PCH
586 @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH
587 **/
588 BOOLEAN
589 IsPchPSOnSupported (
590 VOID
591 );
592
593 /**
594 Get Pch Maximum Hda Sndw Link
595
596 @retval Pch Maximum Hda Sndw Link
597 **/
598 UINT8
599 GetPchHdaMaxSndwLinkNum (
600 VOID
601 );
602
603 /**
604 Get Pch Maximum Hda Ssp Link
605
606 @retval Pch Maximum Hda Ssp Link
607 **/
608 UINT8
609 GetPchHdaMaxSspLinkNum (
610 VOID
611 );
612
613 /**
614 Get Pch Maximum Hda Dmic Link
615
616 @retval Pch Maximum Hda Dmic Link
617 **/
618 UINT8
619 GetPchHdaMaxDmicLinkNum (
620 VOID
621 );
622
623 /**
624 Check if given Audio Interface is supported
625
626 @param[in] AudioLinkType Link type support to be checked
627 @param[in] AudioLinkIndex Link number
628
629 @retval TRUE Link supported
630 @retval FALSE Link not supported
631 **/
632 BOOLEAN
633 IsAudioInterfaceSupported (
634 IN HDAUDIO_LINK_TYPE AudioLinkType,
635 IN UINT32 AudioLinkIndex
636 );
637
638 /**
639 Check if link between PCH and CPU is an P-DMI
640
641 @retval TRUE P-DMI link
642 @retval FALSE Not an P-DMI link
643 **/
644 BOOLEAN
645 IsPchWithPdmi (
646 VOID
647 );
648
649 /**
650 Check if link between PCH and CPU is an OP-DMI
651
652 @retval TRUE OP-DMI link
653 @retval FALSE Not an OP-DMI link
654 **/
655 BOOLEAN
656 IsPchWithOpdmi (
657 VOID
658 );
659
660 /**
661 Check if link between PCH and CPU is an F-DMI
662
663 @retval TRUE F-DMI link
664 @retval FALSE Not an F-DMI link
665 **/
666 BOOLEAN
667 IsPchWithFdmi (
668 VOID
669 );
670
671 /**
672 Get Pch Maximum THC count
673
674 @retval Pch Maximum THC count number
675 **/
676 UINT8
677 GetPchMaxThcCount (
678 VOID
679 );
680
681 /**
682 Check if this generation supports THC controller in HID over SPI mode
683
684 @retval THC HID Mode support
685 **/
686 BOOLEAN
687 IsPchThcHidModeSupported (
688 VOID
689 );
690
691 /**
692 return support status for P2SB PCR 20-bit addressing
693
694 @retval TRUE
695 @retval FALSE
696 **/
697 BOOLEAN
698 IsP2sb20bPcrSupported (
699 VOID
700 );
701
702 /**
703 Check if SPI in a given PCH generation supports an Extended BIOS Range Decode
704
705 @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode
706 **/
707 BOOLEAN
708 IsExtendedBiosRangeDecodeSupported (
709 VOID
710 );
711
712 /**
713 Returns DMI target for current PCH SPI
714
715 @retval PCH SPI DMI target
716 **/
717 UINT16
718 GetPchSpiDmiTarget (
719 VOID
720 );
721 #endif // _PCH_INFO_LIB_H_
PchGetSeriesStr
CHAR8 * PchGetSeriesStr()
Get PCH series ASCII string.
GetPchMaxThcCount
UINT8 GetPchMaxThcCount(VOID)
Get Pch Maximum THC count.
PchGetMaxUfsNum
UINT8 PchGetMaxUfsNum(VOID)
Gets the maximum number of UFS controller supported by this chipset.
GetPchMaxTypeCPortNum
UINT8 GetPchMaxTypeCPortNum(VOID)
Get Pch Maximum Type C Port Number.
GetPchMaxIshSpiControllerCsPinsNum
UINT8 GetPchMaxIshSpiControllerCsPinsNum(VOID)
Get Pch Maximum ISH SPI Controller Cs pins number.
GetPchMaxSerialIoSpiChipSelectsNum
UINT8 GetPchMaxSerialIoSpiChipSelectsNum(VOID)
Get Pch Maximum Serial IO SPI Chip Selects count.
GetPchXhciMaxUsb3PortNum
UINT8 GetPchXhciMaxUsb3PortNum(VOID)
Get Pch Maximum Usb3 Port Number of XHCI Controller.
GetPchUsb2MaxPhysicalPortNum
UINT8 GetPchUsb2MaxPhysicalPortNum(VOID)
Get Pch Usb2 Maximum Physical Port Number.
GetPchMaxIshUartControllersNum
UINT8 GetPchMaxIshUartControllersNum(VOID)
Get Pch Maximum ISH UART Controller number.
PchIsIshSupported
BOOLEAN PchIsIshSupported(VOID)
Check whether ISH is supported.
IsAdlPch
BOOLEAN IsAdlPch(VOID)
Check if this is ADL PCH generation.
GetPchMaxPcieClockReqNum
UINT8 GetPchMaxPcieClockReqNum(VOID)
Get Pch Maximum Pcie ClockReq Number.
GetPchMaxIshGpNum
UINT8 GetPchMaxIshGpNum(VOID)
Get Pch Maximum ISH GP number.
PchGetLpcDid
UINT16 PchGetLpcDid(VOID)
Return LPC Device Id.
PchGetSteppingStr
EFI_STATUS PchGetSteppingStr(OUT CHAR8 *Buffer, IN UINT32 BufferSize)
Get PCH stepping ASCII string.
IsExtendedBiosRangeDecodeSupported
BOOLEAN IsExtendedBiosRangeDecodeSupported(VOID)
Check if SPI in a given PCH generation supports an Extended BIOS Range Decode.
GetPchUsbrStoragePortNum
UINT8 GetPchUsbrStoragePortNum(VOID)
Get Pch USB-R Port Number for Storage session.
PchGeneration
PCH_GENERATION PchGeneration(VOID)
Return Pch Generation.
IsPchH
BOOLEAN IsPchH(VOID)
Check if this is PCH H series.
GetPchMaxSerialIoUartControllersNum
UINT8 GetPchMaxSerialIoUartControllersNum(VOID)
Get Pch Maximum Serial IO UART controllers number.
GetPchSpiDmiTarget
UINT16 GetPchSpiDmiTarget(VOID)
Returns DMI target for current PCH SPI.
IsPchPSOnSupported
BOOLEAN IsPchPSOnSupported(VOID)
Check whether ATX Shutdown (PS_ON) is supported.
GetPchXhciMaxUsb2PortNum
UINT8 GetPchXhciMaxUsb2PortNum(VOID)
Get Pch Maximum Usb2 Port Number of XHCI Controller.
IsPchSdCardSupported
BOOLEAN IsPchSdCardSupported(VOID)
Check if this chipset supports SD controller.
GetPchMaxPciePortNum
UINT8 GetPchMaxPciePortNum(VOID)
Get Pch Maximum Pcie Root Port Number.
GetPchMaxSerialIoI3cControllersNum
UINT8 GetPchMaxSerialIoI3cControllersNum(VOID)
Get Pch Maximum Serial IO I3C controllers number.
PchIsTsnSupported
BOOLEAN PchIsTsnSupported(VOID)
Check whether integrated TSN is supported.
Hda.h
Header file for HD Audio configuration.
GetPchHdaMaxSspLinkNum
UINT8 GetPchHdaMaxSspLinkNum(VOID)
Get Pch Maximum Hda Ssp Link.
GetPchHdaMaxDmicLinkNum
UINT8 GetPchHdaMaxDmicLinkNum(VOID)
Get Pch Maximum Hda Dmic Link.
PchSeries
PCH_SERIES PchSeries(VOID)
Return Pch Series.
IsPchThcHidModeSupported
BOOLEAN IsPchThcHidModeSupported(VOID)
Check if this generation supports THC controller in HID over SPI mode.
IsPchS
BOOLEAN IsPchS(VOID)
Check if this is PCH S series.
IsPchN
BOOLEAN IsPchN(VOID)
Check if this is PCH N series.
IsPchWithOpdmi
BOOLEAN IsPchWithOpdmi(VOID)
Check if link between PCH and CPU is an OP-DMI.
GetPchMaxSerialIoI2cControllersNum
UINT8 GetPchMaxSerialIoI2cControllersNum(VOID)
Get Pch Maximum Serial IO I2C controllers number.
PchStepping
PCH_STEPPING PchStepping(VOID)
Return Pch stepping type.
IsAudioInterfaceSupported
BOOLEAN IsAudioInterfaceSupported(IN HDAUDIO_LINK_TYPE AudioLinkType, IN UINT32 AudioLinkIndex)
Check if given Audio Interface is supported.
GetPchMaxMeSessionCount
UINT8 GetPchMaxMeSessionCount(VOID)
Get Pch Maximum ME Session count.
GetPchMaxMeAppletCount
UINT8 GetPchMaxMeAppletCount(VOID)
Get Pch Maximum ME Applet count.
IsS3m2Ibl
BOOLEAN IsS3m2Ibl(VOID)
Check if this is S3m2.0 IBL generation.
PchIsGbeSupported
BOOLEAN PchIsGbeSupported(VOID)
Check whether integrated LAN controller is supported.
IsPchM
BOOLEAN IsPchM(VOID)
Check if this is PCH M series.
GetPchMaxSerialIoSpiControllersNum
UINT8 GetPchMaxSerialIoSpiControllersNum(VOID)
Get Pch Maximum Serial IO SPI controllers number.
IsPchEmmcSupported
BOOLEAN IsPchEmmcSupported(VOID)
Check if this chipset supports eMMC controller.
GetPchMaxIshI2cControllersNum
UINT8 GetPchMaxIshI2cControllersNum(VOID)
Get Pch Maximum ISH I2C Controller number.
GetPchMaxPcieControllerNum
UINT8 GetPchMaxPcieControllerNum(VOID)
Get Pch Maximum Pcie Controller Number.
IsP2sb20bPcrSupported
BOOLEAN IsP2sb20bPcrSupported(VOID)
return support status for P2SB PCR 20-bit addressing
IsPchP
BOOLEAN IsPchP(VOID)
Check if this is PCH P series.
GetPchMaxPcieClockNum
UINT8 GetPchMaxPcieClockNum(VOID)
Get Pch Maximum Pcie Clock Number.
IsPchWithFdmi
BOOLEAN IsPchWithFdmi(VOID)
Check if link between PCH and CPU is an F-DMI.
IsPchServer
BOOLEAN IsPchServer(VOID)
Check if this is Server PCH.
IsPchSupported
BOOLEAN IsPchSupported(VOID)
Determine if PCH is supported.
IsEbgPch
BOOLEAN IsEbgPch(VOID)
Check if this is EBG PCH generation.
IsPchLp
BOOLEAN IsPchLp(VOID)
Check if this is PCH LP series.
PchGetSupportedRstMode
RST_MODE PchGetSupportedRstMode(VOID)
Get RST mode supported by the silicon.
GetPchUsb3MaxPhysicalPortNum
UINT8 GetPchUsb3MaxPhysicalPortNum(VOID)
Get Pch Usb3 Maximum Physical Port Number.
GetPchMaxIshSpiControllersNum
UINT8 GetPchMaxIshSpiControllersNum(VOID)
Get Pch Maximum ISH SPI Controller number.
IsPchThcSupported
BOOLEAN IsPchThcSupported(VOID)
Check if this chipset supports THC controller.
GetPchHdaMaxSndwLinkNum
UINT8 GetPchHdaMaxSndwLinkNum(VOID)
Get Pch Maximum Hda Sndw Link.
PchInfoDefs.h
Header file for PchInfoDefs.
IsPchChipsetInitSyncSupported
BOOLEAN IsPchChipsetInitSyncSupported(VOID)
Check if this chipset supports HSIO BIOS Sync.
PchGetSkuStr
CHAR8 * PchGetSkuStr(VOID)
Get PCH Sku ASCII string The return string is zero terminated.
IsPchWithPdmi
BOOLEAN IsPchWithPdmi(VOID)
Check if link between PCH and CPU is an P-DMI.
GetPchUsbrKvmPortNum
UINT8 GetPchUsbrKvmPortNum(VOID)
Get Pch USB-R Port Number for KVM session.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPciBdfLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Functions
PchPciBdfLib.h File Reference

Header file for PchPciBdfLib. More...

Go to the source code of this file.

Functions

UINT64 | CnviPciCfgBase (VOID)
Get CNVI controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | CnviDevNumber (VOID)
Get CNVI controller PCIe Device Number. More...
UINT8 | CnviFuncNumber (VOID)
Get CNVI controller PCIe Function Number. More...
UINT64 | EspiPciCfgBase (VOID)
Get eSPI controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | EspiDevNumber (VOID)
Get eSPI controller PCIe Device Number. More...
UINT8 | EspiFuncNumber (VOID)
Get eSPI controller PCIe Function Number. More...
UINT64 | GbePciCfgBase (VOID)
Get GbE controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | GbeDevNumber (VOID)
Returns Gigabit Ethernet PCI Device Number. More...
UINT8 | GbeFuncNumber (VOID)
Returns Gigabit Ethernet PCI Function Number. More...
UINT64 | HdaPciCfgBase (VOID)
Get HDA controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | HdaDevNumber (VOID)
Get HDA PCI device number. More...
UINT8 | HdaFuncNumber (VOID)
Get HDA PCI function number. More...
UINT64 | IehPciCfgBase (VOID)
Get IEH controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | IehDevNumber (VOID)
Get IEH PCI device number. More...
UINT8 | IehFuncNumber (VOID)
Get IEH PCI function number. More...
UINT64 | P2sbPciCfgBase (VOID)
Get P2SB controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | P2sbDevNumber (VOID)
Get P2SB PCI device number. More...
UINT8 | P2sbFuncNumber (VOID)
Get P2SB PCI function number. More...
UINT64 | IshPciCfgBase (VOID)
Get ISH controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | IshDevNumber (VOID)
Get ISH Device Number. More...
UINT8 | IshFuncNumber (VOID)
Get ISH Function Number. More...
UINT64 | PchTraceHubPciCfgBase (VOID)
Get PCH Trace Hub PCI config space base address. More...
UINT8 | PchTraceHubDevNumber (VOID)
Get PCH Trace Hub PCI device number. More...
UINT8 | PchTraceHubFuncNumber (VOID)
Get PCH Trace Hub PCI function number. More...
UINT64 | PmcPciCfgBase (VOID)
Get PMC controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PmcDevNumber (VOID)
Get PMC PCI device number. More...
UINT8 | PmcFuncNumber (VOID)
Get PMC PCI function number. More...
UINT64 | PmcSsramPciCfgBase (VOID)
Get PMC SSRAM controller address that can be passed to the PCI Segment Library functions. More...
UINT64 | TsnPciCfgBase (VOID)
Get TSN controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | TsnDevNumber (VOID)
Get Tsn PCI device number. More...
UINT8 | TsnFuncNumber (VOID)
Get Tsn PCI function number. More...
UINT64 | SpiPciCfgBase (VOID)
Returns SPI PCI Config Space base address. More...
UINT8 | SpiDevNumber (VOID)
Returns SPI Device number. More...
UINT8 | SpiFuncNumber (VOID)
Returns SPI Function number. More...
UINT64 | PchXhciPciCfgBase (VOID)
Get XHCI controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PchXhciDevNumber (VOID)
Get XHCI controller PCIe Device Number. More...
UINT8 | PchXhciFuncNumber (VOID)
Get XHCI controller PCIe Function Number. More...
UINT64 | PchXdciPciCfgBase (VOID)
Get XDCI controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PchXdciDevNumber (VOID)
Get XDCI controller PCIe Device Number. More...
UINT8 | PchXdciFuncNumber (VOID)
Get XDCI controller PCIe Function Number. More...
UINT64 | SmbusPciCfgBase (VOID)
Get SMBUS controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | SmbusDmaDevNumber (VOID)
Return DMA Smbus Device Number. More...
UINT8 | SmbusDmaFuncNumber (VOID)
Return DMA Smbus Function Number. More...
UINT64 | SmbusDmaPciCfgBase (VOID)
Get DMA SMBUS controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | SmbusDevNumber (VOID)
Return Smbus Device Number. More...
UINT8 | SmbusFuncNumber (VOID)
Return Smbus Function Number. More...
UINT64 | ScsSdCardPciCfgBase (VOID)
Get SCS SD Card controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | ScsSdCardDevNumber (VOID)
Get SD Card controller PCIe Device Number. More...
UINT8 | ScsSdCardFuncNumber (VOID)
Get SD Card controller PCIe Function Number. More...
UINT64 | ScsEmmcPciCfgBase (VOID)
Get SCS EMMC controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | ScsEmmcDevNumber (VOID)
Get EMMC controller PCIe Device Number. More...
UINT8 | ScsEmmcFuncNumber (VOID)
Get EMMC controller PCIe Function Number. More...
UINT8 | ScsUfsDevNumber (IN UINT8 UfsIndex)
Get UFS controller PCIe Device Number. More...
UINT8 | ScsUfsFuncNumber (IN UINT8 UfsIndex)
Get UFS controller PCIe Function Number. More...
UINT64 | ScsUfsPciCfgBase (IN UINT8 UfsIndex)
Get SCS EMMC controller address that can be passed to the PCI Segment Library functions. More...
UINT64 | SataPciCfgBase (IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe config space base address. More...
UINT8 | SataDevNumber (IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe Device Number. More...
UINT8 | SataFuncNumber (IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe Function Number. More...
UINT64 | LpcPciCfgBase (VOID)
Returns PCH LPC device PCI base address. More...
UINT8 | LpcDevNumber (VOID)
Get LPC controller PCIe Device Number. More...
UINT8 | ThermalDevNumber (VOID)
Get Thermal Device PCIe Device Number. More...
UINT8 | ThermalFuncNumber (VOID)
Get Thermal Device PCIe Function Number. More...
UINT64 | ThermalPciCfgBase (VOID)
Returns Thermal Device PCI base address. More...
UINT8 | LpcFuncNumber (VOID)
Get LPC controller PCIe Function Number. More...
UINT8 | SerialIoI2cDevNumber (IN UINT8 I2cNumber)
Get Serial IO I2C controller PCIe Device Number. More...
UINT8 | SerialIoI2cFuncNumber (IN UINT8 I2cNumber)
Get Serial IO I2C controller PCIe Function Number. More...
UINT64 | SerialIoI2cPciCfgBase (IN UINT8 I2cNumber)
Get Serial IO I2C controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | SerialIoI3cDevNumber (IN UINT8 I3cNumber)
Get Serial IO I3C controller PCIe Device Number. More...
UINT8 | SerialIoI3cFuncNumber (IN UINT8 I3cNumber)
Get Serial IO I3C controller PCIe Function Number. More...
UINT64 | SerialIoI3cPciCfgBase (IN UINT8 I3cNumber)
Get Serial IO I3C controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | SerialIoSpiDevNumber (IN UINT8 SpiNumber)
Get Serial IO SPI controller PCIe Device Number. More...
UINT8 | SerialIoSpiFuncNumber (IN UINT8 SpiNumber)
Get Serial IO SPI controller PCIe Function Number. More...
UINT64 | SerialIoSpiPciCfgBase (IN UINT8 SpiNumber)
Get Serial IO SPI controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | SerialIoUartDevNumber (IN UINT8 UartNumber)
Get Serial IO UART controller PCIe Device Number. More...
UINT8 | SerialIoUartFuncNumber (IN UINT8 UartNumber)
Get Serial IO UART controller PCIe Function Number. More...
UINT64 | SerialIoUartPciCfgBase (IN UINT8 UartNumber)
Get Serial IO UART controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PchPcieRpDevNumber (IN UINTN RpIndex)
Get PCH PCIe controller PCIe Device Number. More...
UINT8 | PchPcieRpFuncNumber (IN UINTN RpIndex)
Get PCH PCIe controller PCIe Function Number. More...
UINT64 | PchPcieRpPciCfgBase (IN UINT32 RpIndex)
Get PCH PCIe controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PchHeci1DevNumber (VOID)
Get HECI1 PCI device number. More...
UINT8 | PchHeci1FuncNumber (VOID)
Get HECI1 PCI function number. More...
UINT64 | PchHeci1PciCfgBase (VOID)
Get HECI1 controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | PchHeci3DevNumber (VOID)
Get HECI3 PCI device number. More...
UINT8 | PchHeci3FuncNumber (VOID)
Get HECI3 PCI function number. More...
UINT64 | PchHeci3PciCfgBase (VOID)
Get HECI3 controller address that can be passed to the PCI Segment Library functions. More...
UINT8 | ThcDevNumber (IN UINT8 ThcNumber)
Get Touch Host Controller PCIe Device Number. More...
UINT8 | ThcFuncNumber (IN UINT8 ThcNumber)
Get Touch Host Controller PCIe Function Number. More...
UINT64 | ThcPciCfgBase (IN UINT8 ThcNumber)
Get Touch Host Controller address that can be passed to the PCI Segment Library functions. More...

Detailed Description

Header file for PchPciBdfLib.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPciBdfLib.h.

Function Documentation

◆ CnviDevNumber()

UINT8 CnviDevNumber ( VOID )

Get CNVI controller PCIe Device Number.

Return values
CNVI controller PCIe Device Number

◆ CnviFuncNumber()

UINT8 CnviFuncNumber ( VOID )

Get CNVI controller PCIe Function Number.

Return values
CNVI controller PCIe Function Number

◆ CnviPciCfgBase()

UINT64 CnviPciCfgBase ( VOID )

Get CNVI controller address that can be passed to the PCI Segment Library functions.

Return values
CNVI controller address in PCI Segment Library representation

◆ EspiDevNumber()

UINT8 EspiDevNumber ( VOID )

Get eSPI controller PCIe Device Number.

Return values
eSPI controller PCIe Device Number

◆ EspiFuncNumber()

UINT8 EspiFuncNumber ( VOID )

Get eSPI controller PCIe Function Number.

Return values
eSPI controller PCIe Function Number

◆ EspiPciCfgBase()

UINT64 EspiPciCfgBase ( VOID )

Get eSPI controller address that can be passed to the PCI Segment Library functions.

Return values
eSPI controller address in PCI Segment Library representation

◆ GbeDevNumber()

UINT8 GbeDevNumber ( VOID )

Returns Gigabit Ethernet PCI Device Number.

Return values
GbE device number

◆ GbeFuncNumber()

UINT8 GbeFuncNumber ( VOID )

Returns Gigabit Ethernet PCI Function Number.

Return values
GbE function number

◆ GbePciCfgBase()

UINT64 GbePciCfgBase ( VOID )

Get GbE controller address that can be passed to the PCI Segment Library functions.

Return values
GbE controller address in PCI Segment Library representation

◆ HdaDevNumber()

UINT8 HdaDevNumber ( VOID )

Get HDA PCI device number.

Return values
PCI dev number

◆ HdaFuncNumber()

UINT8 HdaFuncNumber ( VOID )

Get HDA PCI function number.

Return values
PCI fun number

◆ HdaPciCfgBase()

UINT64 HdaPciCfgBase ( VOID )

Get HDA controller address that can be passed to the PCI Segment Library functions.

Return values
HDA controller address in PCI Segment Library representation

◆ IehDevNumber()

UINT8 IehDevNumber ( VOID )

Get IEH PCI device number.

Return values
PCI dev number

◆ IehFuncNumber()

UINT8 IehFuncNumber ( VOID )

Get IEH PCI function number.

Return values
PCI fun number

◆ IehPciCfgBase()

UINT64 IehPciCfgBase ( VOID )

Get IEH controller address that can be passed to the PCI Segment Library functions.

Return values
IEH controller address in PCI Segment Library representation

◆ IshDevNumber()

UINT8 IshDevNumber ( VOID )

Get ISH Device Number.

Return values
ISH Device Number

◆ IshFuncNumber()

UINT8 IshFuncNumber ( VOID )

Get ISH Function Number.

Return values
ISH Function Number

◆ IshPciCfgBase()

UINT64 IshPciCfgBase ( VOID )

Get ISH controller address that can be passed to the PCI Segment Library functions.

Return values
ISH controller address in PCI Segment Library representation

◆ LpcDevNumber()

UINT8 LpcDevNumber ( VOID )

Get LPC controller PCIe Device Number.

Return values
LPC controller PCIe Device Number

◆ LpcFuncNumber()

UINT8 LpcFuncNumber ( VOID )

Get LPC controller PCIe Function Number.

Return values
LPC controller PCIe Function Number

◆ LpcPciCfgBase()

UINT64 LpcPciCfgBase ( VOID )

Returns PCH LPC device PCI base address.

Return values
PCH LPC PCI base address.

◆ P2sbDevNumber()

UINT8 P2sbDevNumber ( VOID )

Get P2SB PCI device number.

Return values
PCI dev number

◆ P2sbFuncNumber()

UINT8 P2sbFuncNumber ( VOID )

Get P2SB PCI function number.

Return values
PCI fun number

◆ P2sbPciCfgBase()

UINT64 P2sbPciCfgBase ( VOID )

Get P2SB controller address that can be passed to the PCI Segment Library functions.

Return values
P2SB controller address in PCI Segment Library representation

◆ PchHeci1DevNumber()

UINT8 PchHeci1DevNumber ( VOID )

Get HECI1 PCI device number.

Return values
PCI dev number

◆ PchHeci1FuncNumber()

UINT8 PchHeci1FuncNumber ( VOID )

Get HECI1 PCI function number.

Return values
PCI fun number

◆ PchHeci1PciCfgBase()

UINT64 PchHeci1PciCfgBase ( VOID )

Get HECI1 controller address that can be passed to the PCI Segment Library functions.

Return values
HECI1 controller address in PCI Segment Library representation

◆ PchHeci3DevNumber()

UINT8 PchHeci3DevNumber ( VOID )

Get HECI3 PCI device number.

Return values
PCI dev number

◆ PchHeci3FuncNumber()

UINT8 PchHeci3FuncNumber ( VOID )

Get HECI3 PCI function number.

Return values
PCI fun number

◆ PchHeci3PciCfgBase()

UINT64 PchHeci3PciCfgBase ( VOID )

Get HECI3 controller address that can be passed to the PCI Segment Library functions.

Return values
HECI3 controller address in PCI Segment Library representation

◆ PchPcieRpDevNumber()

UINT8 PchPcieRpDevNumber ( IN UINTN RpIndex )

Get PCH PCIe controller PCIe Device Number.

Parameters
[in] RpIndex Root port physical number. (0-based)
Return values
PCH PCIe controller PCIe Device Number

◆ PchPcieRpFuncNumber()

UINT8 PchPcieRpFuncNumber ( IN UINTN RpIndex )

Get PCH PCIe controller PCIe Function Number.

Parameters
[in] RpIndex Root port physical number. (0-based)
Return values
PCH PCIe controller PCIe Function Number

◆ PchPcieRpPciCfgBase()

UINT64 PchPcieRpPciCfgBase ( IN UINT32 RpIndex )

Get PCH PCIe controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] RpIndex PCH PCIe Root Port physical number. (0-based)
Return values
PCH PCIe controller address in PCI Segment Library representation

◆ PchTraceHubDevNumber()

UINT8 PchTraceHubDevNumber ( VOID )

Get PCH Trace Hub PCI device number.

Return values
PCI dev number

◆ PchTraceHubFuncNumber()

UINT8 PchTraceHubFuncNumber ( VOID )

Get PCH Trace Hub PCI function number.

Return values
PCI fun number

◆ PchTraceHubPciCfgBase()

UINT64 PchTraceHubPciCfgBase ( VOID )

Get PCH Trace Hub PCI config space base address.

Return values
PCI config space base address

◆ PchXdciDevNumber()

UINT8 PchXdciDevNumber ( VOID )

Get XDCI controller PCIe Device Number.

Return values
XDCI controller PCIe Device Number

◆ PchXdciFuncNumber()

UINT8 PchXdciFuncNumber ( VOID )

Get XDCI controller PCIe Function Number.

Return values
XDCI controller PCIe Function Number

◆ PchXdciPciCfgBase()

UINT64 PchXdciPciCfgBase ( VOID )

Get XDCI controller address that can be passed to the PCI Segment Library functions.

Return values
XDCI controller address in PCI Segment Library representation

◆ PchXhciDevNumber()

UINT8 PchXhciDevNumber ( VOID )

Get XHCI controller PCIe Device Number.

Return values
XHCI controller PCIe Device Number

◆ PchXhciFuncNumber()

UINT8 PchXhciFuncNumber ( VOID )

Get XHCI controller PCIe Function Number.

Return values
XHCI controller PCIe Function Number

◆ PchXhciPciCfgBase()

UINT64 PchXhciPciCfgBase ( VOID )

Get XHCI controller address that can be passed to the PCI Segment Library functions.

Return values
XHCI controller address in PCI Segment Library representation

◆ PmcDevNumber()

UINT8 PmcDevNumber ( VOID )

Get PMC PCI device number.

Return values
PCI dev number

◆ PmcFuncNumber()

UINT8 PmcFuncNumber ( VOID )

Get PMC PCI function number.

Return values
PCI fun number

◆ PmcPciCfgBase()

UINT64 PmcPciCfgBase ( VOID )

Get PMC controller address that can be passed to the PCI Segment Library functions.

Return values
PMC controller address in PCI Segment Library representation

◆ PmcSsramPciCfgBase()

UINT64 PmcSsramPciCfgBase ( VOID )

Get PMC SSRAM controller address that can be passed to the PCI Segment Library functions.

Return values
PMC SSRAM controller address in PCI Segment Library representation

◆ SataDevNumber()

UINT8 SataDevNumber ( IN UINT32 SataCtrlIndex )

Gets SATA controller PCIe Device Number.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
SATA controller PCIe Device Number

◆ SataFuncNumber()

UINT8 SataFuncNumber ( IN UINT32 SataCtrlIndex )

Gets SATA controller PCIe Function Number.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
SATA controller PCIe Function Number

◆ SataPciCfgBase()

UINT64 SataPciCfgBase ( IN UINT32 SataCtrlIndex )

Gets SATA controller PCIe config space base address.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
SATA controller PCIe config space base address

◆ ScsEmmcDevNumber()

UINT8 ScsEmmcDevNumber ( VOID )

Get EMMC controller PCIe Device Number.

Return values
EMMC controller PCIe Device Number

◆ ScsEmmcFuncNumber()

UINT8 ScsEmmcFuncNumber ( VOID )

Get EMMC controller PCIe Function Number.

Return values
EMMC controller PCIe Function Number

◆ ScsEmmcPciCfgBase()

UINT64 ScsEmmcPciCfgBase ( VOID )

Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.

Return values
SCS EMMC controller address in PCI Segment Library representation

◆ ScsSdCardDevNumber()

UINT8 ScsSdCardDevNumber ( VOID )

Get SD Card controller PCIe Device Number.

Return values
SD Card controller PCIe Device Number

◆ ScsSdCardFuncNumber()

UINT8 ScsSdCardFuncNumber ( VOID )

Get SD Card controller PCIe Function Number.

Return values
SD Card controller PCIe Function Number

◆ ScsSdCardPciCfgBase()

UINT64 ScsSdCardPciCfgBase ( VOID )

Get SCS SD Card controller address that can be passed to the PCI Segment Library functions.

Return values
SCS SD Card controller address in PCI Segment Library representation

◆ ScsUfsDevNumber()

UINT8 ScsUfsDevNumber ( IN UINT8 UfsIndex )

Get UFS controller PCIe Device Number.

Parameters
[in] UfsIndex Index of the UFS controller
Return values
UFS controller PCIe Device Number

◆ ScsUfsFuncNumber()

UINT8 ScsUfsFuncNumber ( IN UINT8 UfsIndex )

Get UFS controller PCIe Function Number.

Parameters
[in] UfsIndex Index of the UFS controller
Return values
UFS controller PCIe Function Number

◆ ScsUfsPciCfgBase()

UINT64 ScsUfsPciCfgBase ( IN UINT8 UfsIndex )

Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] UfsIndex Index of the UFS controller
Return values
SCS EMMC controller address in PCI Segment Library representation

◆ SerialIoI2cDevNumber()

UINT8 SerialIoI2cDevNumber ( IN UINT8 I2cNumber )

Get Serial IO I2C controller PCIe Device Number.

Parameters
[in] I2cNumber Serial IO I2C controller index
Return values
Serial IO I2C controller PCIe Device Number

◆ SerialIoI2cFuncNumber()

UINT8 SerialIoI2cFuncNumber ( IN UINT8 I2cNumber )

Get Serial IO I2C controller PCIe Function Number.

Parameters
[in] I2cNumber Serial IO I2C controller index
Return values
Serial IO I2C controller PCIe Function Number

◆ SerialIoI2cPciCfgBase()

UINT64 SerialIoI2cPciCfgBase ( IN UINT8 I2cNumber )

Get Serial IO I2C controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] I2cNumber Serial IO I2C controller index
Return values
Serial IO I2C controller address in PCI Segment Library representation

◆ SerialIoI3cDevNumber()

UINT8 SerialIoI3cDevNumber ( IN UINT8 I3cNumber )

Get Serial IO I3C controller PCIe Device Number.

Parameters
[in] I3CNumber Serial IO I3C controller index
Return values
Serial IO I3C controller PCIe Device Number

◆ SerialIoI3cFuncNumber()

UINT8 SerialIoI3cFuncNumber ( IN UINT8 I3cNumber )

Get Serial IO I3C controller PCIe Function Number.

Parameters
[in] I3cNumber Serial IO I3C controller index
Return values
Serial IO I3C controller PCIe Function Number

◆ SerialIoI3cPciCfgBase()

UINT64 SerialIoI3cPciCfgBase ( IN UINT8 I3cNumber )

Get Serial IO I3C controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] I3cNumber Serial IO I3C controller index
Return values
Serial IO I3C controller address in PCI Segment Library representation

◆ SerialIoSpiDevNumber()

UINT8 SerialIoSpiDevNumber ( IN UINT8 SpiNumber )

Get Serial IO SPI controller PCIe Device Number.

Parameters
[in] I2cNumber Serial IO SPI controller index
Return values
Serial IO SPI controller PCIe Device Number

◆ SerialIoSpiFuncNumber()

UINT8 SerialIoSpiFuncNumber ( IN UINT8 SpiNumber )

Get Serial IO SPI controller PCIe Function Number.

Parameters
[in] SpiNumber Serial IO SPI controller index
Return values
Serial IO SPI controller PCIe Function Number

◆ SerialIoSpiPciCfgBase()

UINT64 SerialIoSpiPciCfgBase ( IN UINT8 SpiNumber )

Get Serial IO SPI controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] SpiNumber Serial IO SPI controller index
Return values
Serial IO SPI controller address in PCI Segment Library representation

◆ SerialIoUartDevNumber()

UINT8 SerialIoUartDevNumber ( IN UINT8 UartNumber )

Get Serial IO UART controller PCIe Device Number.

Parameters
[in] UartNumber Serial IO UART controller index
Return values
Serial IO UART controller PCIe Device Number

◆ SerialIoUartFuncNumber()

UINT8 SerialIoUartFuncNumber ( IN UINT8 UartNumber )

Get Serial IO UART controller PCIe Function Number.

Parameters
[in] UartNumber Serial IO UART controller index
Return values
Serial IO UART controller PCIe Function Number

◆ SerialIoUartPciCfgBase()

UINT64 SerialIoUartPciCfgBase ( IN UINT8 UartNumber )

Get Serial IO UART controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] UartNumber Serial IO UART controller index
Return values
Serial IO UART controller address in PCI Segment Library representation

◆ SmbusDevNumber()

UINT8 SmbusDevNumber ( VOID )

Return Smbus Device Number.

Return values
Smbus Device Number

◆ SmbusDmaDevNumber()

UINT8 SmbusDmaDevNumber ( VOID )

Return DMA Smbus Device Number.

Return values
DMA Smbus Device Number

◆ SmbusDmaFuncNumber()

UINT8 SmbusDmaFuncNumber ( VOID )

Return DMA Smbus Function Number.

Return values
DMA Smbus Function Number

◆ SmbusDmaPciCfgBase()

UINT64 SmbusDmaPciCfgBase ( VOID )

Get DMA SMBUS controller address that can be passed to the PCI Segment Library functions.

Return values
DMA SMBUS controller address in PCI Segment Library representation

◆ SmbusFuncNumber()

UINT8 SmbusFuncNumber ( VOID )

Return Smbus Function Number.

Return values
Smbus Function Number

◆ SmbusPciCfgBase()

UINT64 SmbusPciCfgBase ( VOID )

Get SMBUS controller address that can be passed to the PCI Segment Library functions.

Return values
SMBUS controller address in PCI Segment Library representation

◆ SpiDevNumber()

UINT8 SpiDevNumber ( VOID )

Returns SPI Device number.

Return values
UINT8 PCH SPI Device number

◆ SpiFuncNumber()

UINT8 SpiFuncNumber ( VOID )

Returns SPI Function number.

Return values
UINT8 PCH SPI Function number

◆ SpiPciCfgBase()

UINT64 SpiPciCfgBase ( VOID )

Returns SPI PCI Config Space base address.

Return values
UINT64 SPI Config Space base address

◆ ThcDevNumber()

UINT8 ThcDevNumber ( IN UINT8 ThcNumber )

Get Touch Host Controller PCIe Device Number.

Parameters
[in] ThcNumber THC controller index
Return values
THC controller PCIe Device Number

◆ ThcFuncNumber()

UINT8 ThcFuncNumber ( IN UINT8 ThcNumber )

Get Touch Host Controller PCIe Function Number.

Parameters
[in] ThcNumber THC controller index
Return values
THC controller PCIe Function Number

◆ ThcPciCfgBase()

UINT64 ThcPciCfgBase ( IN UINT8 ThcNumber )

Get Touch Host Controller address that can be passed to the PCI Segment Library functions.

Parameters
[in] ThcNumber THC controller index
Return values
THC controller address in PCI Segment Library representation

◆ ThermalDevNumber()

UINT8 ThermalDevNumber ( VOID )

Get Thermal Device PCIe Device Number.

Return values
Thermal Device PCIe Device Number

◆ ThermalFuncNumber()

UINT8 ThermalFuncNumber ( VOID )

Get Thermal Device PCIe Function Number.

Return values
Thermal Device PCIe Function Number

◆ ThermalPciCfgBase()

UINT64 ThermalPciCfgBase ( VOID )

Returns Thermal Device PCI base address.

Return values
Thermal Device PCI base address.

◆ TsnDevNumber()

UINT8 TsnDevNumber ( VOID )

Get Tsn PCI device number.

Return values
PCI dev number

◆ TsnFuncNumber()

UINT8 TsnFuncNumber ( VOID )

Get Tsn PCI function number.

Return values
PCI fun number

◆ TsnPciCfgBase()

UINT64 TsnPciCfgBase ( VOID )

Get TSN controller address that can be passed to the PCI Segment Library functions.

Return values
TSN controller address in PCI Segment Library representation
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPciBdfLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
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  • Library
PchPciBdfLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchPciBdfLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCI_BDF_LIB_H_
36 #define _PCH_PCI_BDF_LIB_H_
37
38 /**
39 Get CNVI controller address that can be passed to the PCI Segment Library functions.
40
41 @retval CNVI controller address in PCI Segment Library representation
42 **/
43 UINT64
44 CnviPciCfgBase (
45 VOID
46 );
47
48 /**
49 Get CNVI controller PCIe Device Number
50
51 @retval CNVI controller PCIe Device Number
52 **/
53 UINT8
54 CnviDevNumber (
55 VOID
56 );
57
58 /**
59 Get CNVI controller PCIe Function Number
60
61 @retval CNVI controller PCIe Function Number
62 **/
63 UINT8
64 CnviFuncNumber (
65 VOID
66 );
67
68 /**
69 Get eSPI controller address that can be passed to the PCI Segment Library functions.
70
71 @retval eSPI controller address in PCI Segment Library representation
72 **/
73 UINT64
74 EspiPciCfgBase (
75 VOID
76 );
77
78 /**
79 Get eSPI controller PCIe Device Number
80
81 @retval eSPI controller PCIe Device Number
82 **/
83 UINT8
84 EspiDevNumber (
85 VOID
86 );
87
88 /**
89 Get eSPI controller PCIe Function Number
90
91 @retval eSPI controller PCIe Function Number
92 **/
93 UINT8
94 EspiFuncNumber (
95 VOID
96 );
97
98 /**
99 Get GbE controller address that can be passed to the PCI Segment Library functions.
100
101 @retval GbE controller address in PCI Segment Library representation
102 **/
103 UINT64
104 GbePciCfgBase (
105 VOID
106 );
107
108 /**
109 Returns Gigabit Ethernet PCI Device Number
110
111 @retval GbE device number
112 **/
113 UINT8
114 GbeDevNumber (
115 VOID
116 );
117
118 /**
119 Returns Gigabit Ethernet PCI Function Number
120
121 @retval GbE function number
122 **/
123 UINT8
124 GbeFuncNumber (
125 VOID
126 );
127
128 /**
129 Get HDA controller address that can be passed to the PCI Segment Library functions.
130
131 @retval HDA controller address in PCI Segment Library representation
132 **/
133 UINT64
134 HdaPciCfgBase (
135 VOID
136 );
137
138 /**
139 Get HDA PCI device number
140
141 @retval PCI dev number
142 **/
143 UINT8
144 HdaDevNumber (
145 VOID
146 );
147
148 /**
149 Get HDA PCI function number
150
151 @retval PCI fun number
152 **/
153 UINT8
154 HdaFuncNumber (
155 VOID
156 );
157
158 /**
159 Get IEH controller address that can be passed to the PCI Segment Library functions.
160
161 @retval IEH controller address in PCI Segment Library representation
162 **/
163 UINT64
164 IehPciCfgBase (
165 VOID
166 );
167
168 /**
169 Get IEH PCI device number
170
171 @retval PCI dev number
172 **/
173 UINT8
174 IehDevNumber (
175 VOID
176 );
177
178 /**
179 Get IEH PCI function number
180
181 @retval PCI fun number
182 **/
183 UINT8
184 IehFuncNumber (
185 VOID
186 );
187
188 /**
189 Get P2SB controller address that can be passed to the PCI Segment Library functions.
190
191 @retval P2SB controller address in PCI Segment Library representation
192 **/
193 UINT64
194 P2sbPciCfgBase (
195 VOID
196 );
197
198 /**
199 Get P2SB PCI device number
200
201 @retval PCI dev number
202 **/
203 UINT8
204 P2sbDevNumber (
205 VOID
206 );
207
208 /**
209 Get P2SB PCI function number
210
211 @retval PCI fun number
212 **/
213 UINT8
214 P2sbFuncNumber (
215 VOID
216 );
217
218 /**
219 Get ISH controller address that can be passed to the PCI Segment Library functions.
220
221 @retval ISH controller address in PCI Segment Library representation
222 **/
223 UINT64
224 IshPciCfgBase (
225 VOID
226 );
227
228 /**
229 Get ISH Device Number
230
231 @retval ISH Device Number
232 **/
233 UINT8
234 IshDevNumber (
235 VOID
236 );
237
238 /**
239 Get ISH Function Number
240
241 @retval ISH Function Number
242 **/
243 UINT8
244 IshFuncNumber (
245 VOID
246 );
247
248 /**
249 Get PCH Trace Hub PCI config space base address
250
251 @retval PCI config space base address
252 **/
253 UINT64
254 PchTraceHubPciCfgBase (
255 VOID
256 );
257
258 /**
259 Get PCH Trace Hub PCI device number
260
261 @retval PCI dev number
262 **/
263 UINT8
264 PchTraceHubDevNumber (
265 VOID
266 );
267
268 /**
269 Get PCH Trace Hub PCI function number
270
271 @retval PCI fun number
272 **/
273 UINT8
274 PchTraceHubFuncNumber (
275 VOID
276 );
277
278 /**
279 Get PMC controller address that can be passed to the PCI Segment Library functions.
280
281 @retval PMC controller address in PCI Segment Library representation
282 **/
283 UINT64
284 PmcPciCfgBase (
285 VOID
286 );
287
288 /**
289 Get PMC PCI device number
290
291 @retval PCI dev number
292 **/
293 UINT8
294 PmcDevNumber (
295 VOID
296 );
297
298 /**
299 Get PMC PCI function number
300
301 @retval PCI fun number
302 **/
303 UINT8
304 PmcFuncNumber (
305 VOID
306 );
307
308 /**
309 Get PMC SSRAM controller address that can be passed to the PCI Segment Library functions.
310
311 @retval PMC SSRAM controller address in PCI Segment Library representation
312 **/
313 UINT64
314 PmcSsramPciCfgBase (
315 VOID
316 );
317
318 /**
319 Get TSN controller address that can be passed to the PCI Segment Library functions.
320
321 @retval TSN controller address in PCI Segment Library representation
322 **/
323 UINT64
324 TsnPciCfgBase (
325 VOID
326 );
327
328 /**
329 Get Tsn PCI device number
330
331 @retval PCI dev number
332 **/
333 UINT8
334 TsnDevNumber (
335 VOID
336 );
337
338 /**
339 Get Tsn PCI function number
340
341 @retval PCI fun number
342 **/
343 UINT8
344 TsnFuncNumber (
345 VOID
346 );
347
348 /**
349 Returns SPI PCI Config Space base address
350
351 @retval UINT64 SPI Config Space base address
352 **/
353 UINT64
354 SpiPciCfgBase (
355 VOID
356 );
357
358 /**
359 Returns SPI Device number
360
361 @retval UINT8 PCH SPI Device number
362 **/
363 UINT8
364 SpiDevNumber (
365 VOID
366 );
367
368 /**
369 Returns SPI Function number
370
371 @retval UINT8 PCH SPI Function number
372 **/
373 UINT8
374 SpiFuncNumber (
375 VOID
376 );
377
378 /**
379 Get XHCI controller address that can be passed to the PCI Segment Library functions.
380
381 @retval XHCI controller address in PCI Segment Library representation
382 **/
383 UINT64
384 PchXhciPciCfgBase (
385 VOID
386 );
387
388 /**
389 Get XHCI controller PCIe Device Number
390
391 @retval XHCI controller PCIe Device Number
392 **/
393 UINT8
394 PchXhciDevNumber (
395 VOID
396 );
397
398 /**
399 Get XHCI controller PCIe Function Number
400
401 @retval XHCI controller PCIe Function Number
402 **/
403 UINT8
404 PchXhciFuncNumber (
405 VOID
406 );
407
408 /**
409 Get XDCI controller address that can be passed to the PCI Segment Library functions.
410
411 @retval XDCI controller address in PCI Segment Library representation
412 **/
413 UINT64
414 PchXdciPciCfgBase (
415 VOID
416 );
417
418 /**
419 Get XDCI controller PCIe Device Number
420
421 @retval XDCI controller PCIe Device Number
422 **/
423 UINT8
424 PchXdciDevNumber (
425 VOID
426 );
427
428 /**
429 Get XDCI controller PCIe Function Number
430
431 @retval XDCI controller PCIe Function Number
432 **/
433 UINT8
434 PchXdciFuncNumber (
435 VOID
436 );
437
438 /**
439 Get SMBUS controller address that can be passed to the PCI Segment Library functions.
440
441 @retval SMBUS controller address in PCI Segment Library representation
442 **/
443 UINT64
444 SmbusPciCfgBase (
445 VOID
446 );
447
448 /**
449 Return DMA Smbus Device Number
450
451 @retval DMA Smbus Device Number
452 **/
453 UINT8
454 SmbusDmaDevNumber (
455 VOID
456 );
457
458 /**
459 Return DMA Smbus Function Number
460
461 @retval DMA Smbus Function Number
462 **/
463 UINT8
464 SmbusDmaFuncNumber (
465 VOID
466 );
467
468 /**
469 Get DMA SMBUS controller address that can be passed to the PCI Segment Library functions.
470
471 @retval DMA SMBUS controller address in PCI Segment Library representation
472 **/
473 UINT64
474 SmbusDmaPciCfgBase (
475 VOID
476 );
477
478 /**
479 Return Smbus Device Number
480
481 @retval Smbus Device Number
482 **/
483 UINT8
484 SmbusDevNumber (
485 VOID
486 );
487
488 /**
489 Return Smbus Function Number
490
491 @retval Smbus Function Number
492 **/
493 UINT8
494 SmbusFuncNumber (
495 VOID
496 );
497
498 /**
499 Get SCS SD Card controller address that can be passed to the PCI Segment Library functions.
500
501 @retval SCS SD Card controller address in PCI Segment Library representation
502 **/
503 UINT64
504 ScsSdCardPciCfgBase (
505 VOID
506 );
507
508 /**
509 Get SD Card controller PCIe Device Number
510
511 @retval SD Card controller PCIe Device Number
512 **/
513 UINT8
514 ScsSdCardDevNumber (
515 VOID
516 );
517
518 /**
519 Get SD Card controller PCIe Function Number
520
521 @retval SD Card controller PCIe Function Number
522 **/
523 UINT8
524 ScsSdCardFuncNumber (
525 VOID
526 );
527
528 /**
529 Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.
530
531 @retval SCS EMMC controller address in PCI Segment Library representation
532 **/
533 UINT64
534 ScsEmmcPciCfgBase (
535 VOID
536 );
537
538 /**
539 Get EMMC controller PCIe Device Number
540
541 @retval EMMC controller PCIe Device Number
542 **/
543 UINT8
544 ScsEmmcDevNumber (
545 VOID
546 );
547
548 /**
549 Get EMMC controller PCIe Function Number
550
551 @retval EMMC controller PCIe Function Number
552 **/
553 UINT8
554 ScsEmmcFuncNumber (
555 VOID
556 );
557
558 /**
559 Get UFS controller PCIe Device Number
560
561 @param[in] UfsIndex Index of the UFS controller
562
563 @retval UFS controller PCIe Device Number
564 **/
565 UINT8
566 ScsUfsDevNumber (
567 IN UINT8 UfsIndex
568 );
569
570 /**
571 Get UFS controller PCIe Function Number
572
573 @param[in] UfsIndex Index of the UFS controller
574
575 @retval UFS controller PCIe Function Number
576 **/
577 UINT8
578 ScsUfsFuncNumber (
579 IN UINT8 UfsIndex
580 );
581
582 /**
583 Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.
584
585 @param[in] UfsIndex Index of the UFS controller
586
587 @retval SCS EMMC controller address in PCI Segment Library representation
588 **/
589 UINT64
590 ScsUfsPciCfgBase (
591 IN UINT8 UfsIndex
592 );
593
594 /**
595 Gets SATA controller PCIe config space base address
596
597 @param[in] SataCtrlIndex SATA controller index
598
599 @retval SATA controller PCIe config space base address
600 **/
601 UINT64
602 SataPciCfgBase (
603 IN UINT32 SataCtrlIndex
604 );
605
606 /**
607 Gets SATA controller PCIe Device Number
608
609 @param[in] SataCtrlIndex SATA controller index
610
611 @retval SATA controller PCIe Device Number
612 **/
613 UINT8
614 SataDevNumber (
615 IN UINT32 SataCtrlIndex
616 );
617
618 /**
619 Gets SATA controller PCIe Function Number
620
621 @param[in] SataCtrlIndex SATA controller index
622
623 @retval SATA controller PCIe Function Number
624 **/
625 UINT8
626 SataFuncNumber (
627 IN UINT32 SataCtrlIndex
628 );
629
630 /**
631 Returns PCH LPC device PCI base address.
632
633 @retval PCH LPC PCI base address.
634 **/
635 UINT64
636 LpcPciCfgBase (
637 VOID
638 );
639
640 /**
641 Get LPC controller PCIe Device Number
642
643 @retval LPC controller PCIe Device Number
644 **/
645 UINT8
646 LpcDevNumber (
647 VOID
648 );
649
650 /**
651 Get Thermal Device PCIe Device Number
652
653 @retval Thermal Device PCIe Device Number
654 **/
655 UINT8
656 ThermalDevNumber (
657 VOID
658 );
659
660 /**
661 Get Thermal Device PCIe Function Number
662
663 @retval Thermal Device PCIe Function Number
664 **/
665 UINT8
666 ThermalFuncNumber (
667 VOID
668 );
669
670 /**
671 Returns Thermal Device PCI base address.
672
673 @retval Thermal Device PCI base address.
674 **/
675 UINT64
676 ThermalPciCfgBase (
677 VOID
678 );
679
680 /**
681 Get LPC controller PCIe Function Number
682
683 @retval LPC controller PCIe Function Number
684 **/
685 UINT8
686 LpcFuncNumber (
687 VOID
688 );
689
690 /**
691 Get Serial IO I2C controller PCIe Device Number
692
693 @param[in] I2cNumber Serial IO I2C controller index
694
695 @retval Serial IO I2C controller PCIe Device Number
696 **/
697 UINT8
698 SerialIoI2cDevNumber (
699 IN UINT8 I2cNumber
700 );
701
702 /**
703 Get Serial IO I2C controller PCIe Function Number
704
705 @param[in] I2cNumber Serial IO I2C controller index
706
707 @retval Serial IO I2C controller PCIe Function Number
708 **/
709 UINT8
710 SerialIoI2cFuncNumber (
711 IN UINT8 I2cNumber
712 );
713
714 /**
715 Get Serial IO I2C controller address that can be passed to the PCI Segment Library functions.
716
717 @param[in] I2cNumber Serial IO I2C controller index
718
719 @retval Serial IO I2C controller address in PCI Segment Library representation
720 **/
721 UINT64
722 SerialIoI2cPciCfgBase (
723 IN UINT8 I2cNumber
724 );
725
726 /**
727 Get Serial IO I3C controller PCIe Device Number
728
729 @param[in] I3CNumber Serial IO I3C controller index
730
731 @retval Serial IO I3C controller PCIe Device Number
732 **/
733 UINT8
734 SerialIoI3cDevNumber (
735 IN UINT8 I3cNumber
736 );
737
738 /**
739 Get Serial IO I3C controller PCIe Function Number
740
741 @param[in] I3cNumber Serial IO I3C controller index
742
743 @retval Serial IO I3C controller PCIe Function Number
744 **/
745 UINT8
746 SerialIoI3cFuncNumber (
747 IN UINT8 I3cNumber
748 );
749
750 /**
751 Get Serial IO I3C controller address that can be passed to the PCI Segment Library functions.
752
753 @param[in] I3cNumber Serial IO I3C controller index
754
755 @retval Serial IO I3C controller address in PCI Segment Library representation
756 **/
757 UINT64
758 SerialIoI3cPciCfgBase (
759 IN UINT8 I3cNumber
760 );
761
762 /**
763 Get Serial IO SPI controller PCIe Device Number
764
765 @param[in] I2cNumber Serial IO SPI controller index
766
767 @retval Serial IO SPI controller PCIe Device Number
768 **/
769 UINT8
770 SerialIoSpiDevNumber (
771 IN UINT8 SpiNumber
772 );
773
774 /**
775 Get Serial IO SPI controller PCIe Function Number
776
777 @param[in] SpiNumber Serial IO SPI controller index
778
779 @retval Serial IO SPI controller PCIe Function Number
780 **/
781 UINT8
782 SerialIoSpiFuncNumber (
783 IN UINT8 SpiNumber
784 );
785
786 /**
787 Get Serial IO SPI controller address that can be passed to the PCI Segment Library functions.
788
789 @param[in] SpiNumber Serial IO SPI controller index
790
791 @retval Serial IO SPI controller address in PCI Segment Library representation
792 **/
793 UINT64
794 SerialIoSpiPciCfgBase (
795 IN UINT8 SpiNumber
796 );
797
798 /**
799 Get Serial IO UART controller PCIe Device Number
800
801 @param[in] UartNumber Serial IO UART controller index
802
803 @retval Serial IO UART controller PCIe Device Number
804 **/
805 UINT8
806 SerialIoUartDevNumber (
807 IN UINT8 UartNumber
808 );
809
810 /**
811 Get Serial IO UART controller PCIe Function Number
812
813 @param[in] UartNumber Serial IO UART controller index
814
815 @retval Serial IO UART controller PCIe Function Number
816 **/
817 UINT8
818 SerialIoUartFuncNumber (
819 IN UINT8 UartNumber
820 );
821
822 /**
823 Get Serial IO UART controller address that can be passed to the PCI Segment Library functions.
824
825 @param[in] UartNumber Serial IO UART controller index
826
827 @retval Serial IO UART controller address in PCI Segment Library representation
828 **/
829 UINT64
830 SerialIoUartPciCfgBase (
831 IN UINT8 UartNumber
832 );
833
834 /**
835 Get PCH PCIe controller PCIe Device Number
836
837 @param[in] RpIndex Root port physical number. (0-based)
838
839 @retval PCH PCIe controller PCIe Device Number
840 **/
841 UINT8
842 PchPcieRpDevNumber (
843 IN UINTN RpIndex
844 );
845
846 /**
847 Get PCH PCIe controller PCIe Function Number
848
849 @param[in] RpIndex Root port physical number. (0-based)
850
851 @retval PCH PCIe controller PCIe Function Number
852 **/
853 UINT8
854 PchPcieRpFuncNumber (
855 IN UINTN RpIndex
856 );
857
858 /**
859 Get PCH PCIe controller address that can be passed to the PCI Segment Library functions.
860
861 @param[in] RpIndex PCH PCIe Root Port physical number. (0-based)
862
863 @retval PCH PCIe controller address in PCI Segment Library representation
864 **/
865 UINT64
866 PchPcieRpPciCfgBase (
867 IN UINT32 RpIndex
868 );
869
870 /**
871 Get HECI1 PCI device number
872
873 @retval PCI dev number
874 **/
875 UINT8
876 PchHeci1DevNumber (
877 VOID
878 );
879
880 /**
881 Get HECI1 PCI function number
882
883 @retval PCI fun number
884 **/
885 UINT8
886 PchHeci1FuncNumber (
887 VOID
888 );
889
890 /**
891 Get HECI1 controller address that can be passed to the PCI Segment Library functions.
892
893 @retval HECI1 controller address in PCI Segment Library representation
894 **/
895 UINT64
896 PchHeci1PciCfgBase (
897 VOID
898 );
899
900 /**
901 Get HECI3 PCI device number
902
903 @retval PCI dev number
904 **/
905 UINT8
906 PchHeci3DevNumber (
907 VOID
908 );
909
910 /**
911 Get HECI3 PCI function number
912
913 @retval PCI fun number
914 **/
915 UINT8
916 PchHeci3FuncNumber (
917 VOID
918 );
919
920 /**
921 Get HECI3 controller address that can be passed to the PCI Segment Library functions.
922
923 @retval HECI3 controller address in PCI Segment Library representation
924 **/
925 UINT64
926 PchHeci3PciCfgBase (
927 VOID
928 );
929
930 /**
931 Get Touch Host Controller PCIe Device Number
932
933 @param[in] ThcNumber THC controller index
934
935 @retval THC controller PCIe Device Number
936 **/
937 UINT8
938 ThcDevNumber (
939 IN UINT8 ThcNumber
940 );
941
942 /**
943 Get Touch Host Controller PCIe Function Number
944
945 @param[in] ThcNumber THC controller index
946
947 @retval THC controller PCIe Function Number
948 **/
949 UINT8
950 ThcFuncNumber (
951 IN UINT8 ThcNumber
952 );
953
954 /**
955 Get Touch Host Controller address that can be passed to the PCI Segment Library functions.
956
957 @param[in] ThcNumber THC controller index
958
959 @retval THC controller address in PCI Segment Library representation
960 **/
961 UINT64
962 ThcPciCfgBase (
963 IN UINT8 ThcNumber
964 );
965
966 #endif //_PCH_PCI_BDF_LIB_H_
ScsUfsDevNumber
UINT8 ScsUfsDevNumber(IN UINT8 UfsIndex)
Get UFS controller PCIe Device Number.
GbeFuncNumber
UINT8 GbeFuncNumber(VOID)
Returns Gigabit Ethernet PCI Function Number.
PchTraceHubDevNumber
UINT8 PchTraceHubDevNumber(VOID)
Get PCH Trace Hub PCI device number.
PchHeci3DevNumber
UINT8 PchHeci3DevNumber(VOID)
Get HECI3 PCI device number.
ScsSdCardDevNumber
UINT8 ScsSdCardDevNumber(VOID)
Get SD Card controller PCIe Device Number.
SmbusDmaPciCfgBase
UINT64 SmbusDmaPciCfgBase(VOID)
Get DMA SMBUS controller address that can be passed to the PCI Segment Library functions.
PmcFuncNumber
UINT8 PmcFuncNumber(VOID)
Get PMC PCI function number.
SataPciCfgBase
UINT64 SataPciCfgBase(IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe config space base address.
ScsUfsPciCfgBase
UINT64 ScsUfsPciCfgBase(IN UINT8 UfsIndex)
Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.
ThcDevNumber
UINT8 ThcDevNumber(IN UINT8 ThcNumber)
Get Touch Host Controller PCIe Device Number.
ScsUfsFuncNumber
UINT8 ScsUfsFuncNumber(IN UINT8 UfsIndex)
Get UFS controller PCIe Function Number.
SmbusPciCfgBase
UINT64 SmbusPciCfgBase(VOID)
Get SMBUS controller address that can be passed to the PCI Segment Library functions.
SerialIoSpiPciCfgBase
UINT64 SerialIoSpiPciCfgBase(IN UINT8 SpiNumber)
Get Serial IO SPI controller address that can be passed to the PCI Segment Library functions.
PchPcieRpDevNumber
UINT8 PchPcieRpDevNumber(IN UINTN RpIndex)
Get PCH PCIe controller PCIe Device Number.
IehFuncNumber
UINT8 IehFuncNumber(VOID)
Get IEH PCI function number.
PchHeci1PciCfgBase
UINT64 PchHeci1PciCfgBase(VOID)
Get HECI1 controller address that can be passed to the PCI Segment Library functions.
SerialIoI3cDevNumber
UINT8 SerialIoI3cDevNumber(IN UINT8 I3cNumber)
Get Serial IO I3C controller PCIe Device Number.
SerialIoSpiFuncNumber
UINT8 SerialIoSpiFuncNumber(IN UINT8 SpiNumber)
Get Serial IO SPI controller PCIe Function Number.
HdaFuncNumber
UINT8 HdaFuncNumber(VOID)
Get HDA PCI function number.
PchTraceHubFuncNumber
UINT8 PchTraceHubFuncNumber(VOID)
Get PCH Trace Hub PCI function number.
SerialIoI2cPciCfgBase
UINT64 SerialIoI2cPciCfgBase(IN UINT8 I2cNumber)
Get Serial IO I2C controller address that can be passed to the PCI Segment Library functions.
EspiPciCfgBase
UINT64 EspiPciCfgBase(VOID)
Get eSPI controller address that can be passed to the PCI Segment Library functions.
PchXdciPciCfgBase
UINT64 PchXdciPciCfgBase(VOID)
Get XDCI controller address that can be passed to the PCI Segment Library functions.
IehDevNumber
UINT8 IehDevNumber(VOID)
Get IEH PCI device number.
PchHeci3FuncNumber
UINT8 PchHeci3FuncNumber(VOID)
Get HECI3 PCI function number.
HdaDevNumber
UINT8 HdaDevNumber(VOID)
Get HDA PCI device number.
IshPciCfgBase
UINT64 IshPciCfgBase(VOID)
Get ISH controller address that can be passed to the PCI Segment Library functions.
PchXhciFuncNumber
UINT8 PchXhciFuncNumber(VOID)
Get XHCI controller PCIe Function Number.
IehPciCfgBase
UINT64 IehPciCfgBase(VOID)
Get IEH controller address that can be passed to the PCI Segment Library functions.
ScsEmmcPciCfgBase
UINT64 ScsEmmcPciCfgBase(VOID)
Get SCS EMMC controller address that can be passed to the PCI Segment Library functions.
SerialIoI2cDevNumber
UINT8 SerialIoI2cDevNumber(IN UINT8 I2cNumber)
Get Serial IO I2C controller PCIe Device Number.
SmbusDmaDevNumber
UINT8 SmbusDmaDevNumber(VOID)
Return DMA Smbus Device Number.
CnviDevNumber
UINT8 CnviDevNumber(VOID)
Get CNVI controller PCIe Device Number.
GbeDevNumber
UINT8 GbeDevNumber(VOID)
Returns Gigabit Ethernet PCI Device Number.
SerialIoSpiDevNumber
UINT8 SerialIoSpiDevNumber(IN UINT8 SpiNumber)
Get Serial IO SPI controller PCIe Device Number.
CnviPciCfgBase
UINT64 CnviPciCfgBase(VOID)
Get CNVI controller address that can be passed to the PCI Segment Library functions.
IshDevNumber
UINT8 IshDevNumber(VOID)
Get ISH Device Number.
PchPcieRpFuncNumber
UINT8 PchPcieRpFuncNumber(IN UINTN RpIndex)
Get PCH PCIe controller PCIe Function Number.
ThermalDevNumber
UINT8 ThermalDevNumber(VOID)
Get Thermal Device PCIe Device Number.
SpiDevNumber
UINT8 SpiDevNumber(VOID)
Returns SPI Device number.
PchHeci3PciCfgBase
UINT64 PchHeci3PciCfgBase(VOID)
Get HECI3 controller address that can be passed to the PCI Segment Library functions.
PmcPciCfgBase
UINT64 PmcPciCfgBase(VOID)
Get PMC controller address that can be passed to the PCI Segment Library functions.
SmbusDevNumber
UINT8 SmbusDevNumber(VOID)
Return Smbus Device Number.
PchXhciPciCfgBase
UINT64 PchXhciPciCfgBase(VOID)
Get XHCI controller address that can be passed to the PCI Segment Library functions.
TsnFuncNumber
UINT8 TsnFuncNumber(VOID)
Get Tsn PCI function number.
ScsEmmcDevNumber
UINT8 ScsEmmcDevNumber(VOID)
Get EMMC controller PCIe Device Number.
P2sbDevNumber
UINT8 P2sbDevNumber(VOID)
Get P2SB PCI device number.
ThermalFuncNumber
UINT8 ThermalFuncNumber(VOID)
Get Thermal Device PCIe Function Number.
SataDevNumber
UINT8 SataDevNumber(IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe Device Number.
CnviFuncNumber
UINT8 CnviFuncNumber(VOID)
Get CNVI controller PCIe Function Number.
EspiFuncNumber
UINT8 EspiFuncNumber(VOID)
Get eSPI controller PCIe Function Number.
ThcPciCfgBase
UINT64 ThcPciCfgBase(IN UINT8 ThcNumber)
Get Touch Host Controller address that can be passed to the PCI Segment Library functions.
LpcPciCfgBase
UINT64 LpcPciCfgBase(VOID)
Returns PCH LPC device PCI base address.
LpcDevNumber
UINT8 LpcDevNumber(VOID)
Get LPC controller PCIe Device Number.
PchXhciDevNumber
UINT8 PchXhciDevNumber(VOID)
Get XHCI controller PCIe Device Number.
PchPcieRpPciCfgBase
UINT64 PchPcieRpPciCfgBase(IN UINT32 RpIndex)
Get PCH PCIe controller address that can be passed to the PCI Segment Library functions.
HdaPciCfgBase
UINT64 HdaPciCfgBase(VOID)
Get HDA controller address that can be passed to the PCI Segment Library functions.
PchXdciDevNumber
UINT8 PchXdciDevNumber(VOID)
Get XDCI controller PCIe Device Number.
ThcFuncNumber
UINT8 ThcFuncNumber(IN UINT8 ThcNumber)
Get Touch Host Controller PCIe Function Number.
PchTraceHubPciCfgBase
UINT64 PchTraceHubPciCfgBase(VOID)
Get PCH Trace Hub PCI config space base address.
SmbusFuncNumber
UINT8 SmbusFuncNumber(VOID)
Return Smbus Function Number.
SmbusDmaFuncNumber
UINT8 SmbusDmaFuncNumber(VOID)
Return DMA Smbus Function Number.
SerialIoI2cFuncNumber
UINT8 SerialIoI2cFuncNumber(IN UINT8 I2cNumber)
Get Serial IO I2C controller PCIe Function Number.
PmcDevNumber
UINT8 PmcDevNumber(VOID)
Get PMC PCI device number.
SerialIoUartDevNumber
UINT8 SerialIoUartDevNumber(IN UINT8 UartNumber)
Get Serial IO UART controller PCIe Device Number.
IshFuncNumber
UINT8 IshFuncNumber(VOID)
Get ISH Function Number.
ScsEmmcFuncNumber
UINT8 ScsEmmcFuncNumber(VOID)
Get EMMC controller PCIe Function Number.
ScsSdCardFuncNumber
UINT8 ScsSdCardFuncNumber(VOID)
Get SD Card controller PCIe Function Number.
SerialIoI3cPciCfgBase
UINT64 SerialIoI3cPciCfgBase(IN UINT8 I3cNumber)
Get Serial IO I3C controller address that can be passed to the PCI Segment Library functions.
SerialIoI3cFuncNumber
UINT8 SerialIoI3cFuncNumber(IN UINT8 I3cNumber)
Get Serial IO I3C controller PCIe Function Number.
SerialIoUartFuncNumber
UINT8 SerialIoUartFuncNumber(IN UINT8 UartNumber)
Get Serial IO UART controller PCIe Function Number.
ThermalPciCfgBase
UINT64 ThermalPciCfgBase(VOID)
Returns Thermal Device PCI base address.
GbePciCfgBase
UINT64 GbePciCfgBase(VOID)
Get GbE controller address that can be passed to the PCI Segment Library functions.
SpiPciCfgBase
UINT64 SpiPciCfgBase(VOID)
Returns SPI PCI Config Space base address.
PchHeci1DevNumber
UINT8 PchHeci1DevNumber(VOID)
Get HECI1 PCI device number.
PchHeci1FuncNumber
UINT8 PchHeci1FuncNumber(VOID)
Get HECI1 PCI function number.
P2sbPciCfgBase
UINT64 P2sbPciCfgBase(VOID)
Get P2SB controller address that can be passed to the PCI Segment Library functions.
P2sbFuncNumber
UINT8 P2sbFuncNumber(VOID)
Get P2SB PCI function number.
SerialIoUartPciCfgBase
UINT64 SerialIoUartPciCfgBase(IN UINT8 UartNumber)
Get Serial IO UART controller address that can be passed to the PCI Segment Library functions.
EspiDevNumber
UINT8 EspiDevNumber(VOID)
Get eSPI controller PCIe Device Number.
SataFuncNumber
UINT8 SataFuncNumber(IN UINT32 SataCtrlIndex)
Gets SATA controller PCIe Function Number.
LpcFuncNumber
UINT8 LpcFuncNumber(VOID)
Get LPC controller PCIe Function Number.
TsnPciCfgBase
UINT64 TsnPciCfgBase(VOID)
Get TSN controller address that can be passed to the PCI Segment Library functions.
SpiFuncNumber
UINT8 SpiFuncNumber(VOID)
Returns SPI Function number.
ScsSdCardPciCfgBase
UINT64 ScsSdCardPciCfgBase(VOID)
Get SCS SD Card controller address that can be passed to the PCI Segment Library functions.
PchXdciFuncNumber
UINT8 PchXdciFuncNumber(VOID)
Get XDCI controller PCIe Function Number.
TsnDevNumber
UINT8 TsnDevNumber(VOID)
Get Tsn PCI device number.
PmcSsramPciCfgBase
UINT64 PmcSsramPciCfgBase(VOID)
Get PMC SSRAM controller address that can be passed to the PCI Segment Library functions.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
Classes | Enumerations
PchPcieRpConfig.h File Reference

PCH Pcie root port policy. More...

#include <PchLimits.h>
#include <PcieConfig.h>
#include <ConfigBlock.h>
Include dependency graph for PchPcieRpConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. More...
struct | PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port. More...
struct | PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers Revision 1: More...
struct | PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase. More...

Enumerations

enum | PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature.
enum | PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
enum | PCH_PCIE_CLOCK_USAGE

Detailed Description

PCH Pcie root port policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieRpConfig.h.

Enumeration Type Documentation

◆ PCH_PCIE_CLOCK_USAGE

enum PCH_PCIE_CLOCK_USAGE
Enumerator
PchClockUsageCpuPcie0

Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silicon generations and series.

Do not assume that PCH port 0 will be always encoded by 0. Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible

PchClockUsageUnspecified

In use for a purpose not listed above.

Definition at line 134 of file PchPcieRpConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRpConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH Pcie root port policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCIERP_CONFIG_H_
36 #define _PCH_PCIERP_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <PcieConfig.h>
40 #include <ConfigBlock.h>
41
42 /*
43 Making any setup structure change after code frozen
44 will need to maintain backward compatibility, bump up
45 structure revision and update below history table\n
46
47 <b>Revision 1</b>: - Initial version.
48 <b>Revision 2</b>:
49 FomsCp - Deprecated
50 <b>Revision 3</b>:
51 Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
52 Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
53 Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
54 <b>Revision 4</b>:
55 AllowL0sWithGen3 - Deprecated
56 Moved EnablePeerMemoryWrite policy from PCIE_COMMON_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
57 Moved ClockGating policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
58 Moved PowerGating policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
59 Moved EnablePort8xhDecode policy form PCH_PCIE_CONFIG to PCIE_COMMON_CONFIG
60 Added LinkDownGpios policy to PCIE_ROOT_PORT_COMMON_CONFIG
61 <b>Revision 5</b>:
62 Deprecated PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS
63 <b>Revision 6</b>:
64 Move PcieGen3LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
65 Move PcieGen4LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
66 Move PcieGen5LinkEqPlatformSettings policies from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
67 Move OverrideEqualizationDefaults policy from CPU_PCIE_CONFIG to PCIE_ROOT_PORT_COMMON_CONFIG
68 */
69 #define PCH_PCIE_CONFIG_REVISION 6
70
71 /*
72 Making any setup structure change after code frozen
73 will need to maintain backward compatibility, bump up
74 structure revision and update below history table\n
75
76 <b>Revision 1</b>: - Initial version.
77 */
78 #define PCH_PCIE_RP_PREMEM_CONFIG_REVISION 2
79
80 /*
81 Making any setup structure change after code frozen
82 will need to maintain backward compatibility, bump up
83 structure revision and update below history table\n
84
85 <b>Revision 1</b>: - Initial version.
86 */
87 #define PCIE_RP_DXE_CONFIG_REVISION 1
88
89 extern EFI_GUID gPchPcieConfigGuid;
90 extern EFI_GUID gPcieRpPreMemConfigGuid;
91
92 #pragma pack (push,1)
93
94 typedef enum {
95 PchPcieOverrideDisabled = 0,
96 PchPcieL1L2Override = 0x01,
97 PchPcieL1SubstatesOverride = 0x02,
98 PchPcieL1L2AndL1SubstatesOverride = 0x03,
99 PchPcieLtrOverride = 0x04
100 } PCH_PCIE_OVERRIDE_CONFIG;
101
102 ///
103 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
104 ///
105 typedef enum {
106 PchPcieAspmDisabled,
107 PchPcieAspmL0s,
108 PchPcieAspmL1,
109 PchPcieAspmL0sL1,
110 PchPcieAspmAutoConfig,
111 PchPcieAspmMax
112 } PCH_PCIE_ASPM_CONTROL;
113
114 /**
115 Refer to PCH EDS for the PCH implementation values corresponding
116 to below PCI-E spec defined ranges
117 **/
118 typedef enum {
119 PchPcieL1SubstatesDisabled,
120 PchPcieL1SubstatesL1_1,
121 PchPcieL1SubstatesL1_1_2,
122 PchPcieL1SubstatesMax
123 } PCH_PCIE_L1SUBSTATES_CONTROL;
124
125 enum PCH_PCIE_MAX_PAYLOAD {
126 PchPcieMaxPayload128 = 0,
127 PchPcieMaxPayload256,
128 PchPcieMaxPayloadMax
129 };
130
131 #define PCH_PCIE_NO_SUCH_CLOCK 0xFF
132 #define PCH_PCIE_NO_GPIO_MUXING 0x00
133
134 typedef enum {
135 PchClockUsagePchPcie0 = 0,
136 PchClockUsagePchPcie1 = 1,
137 PchClockUsagePchPcie2 = 2,
138 PchClockUsagePchPcie3 = 3,
139 PchClockUsagePchPcie4 = 4,
140 PchClockUsagePchPcie5 = 5,
141 PchClockUsagePchPcie6 = 6,
142 PchClockUsagePchPcie7 = 7,
143 PchClockUsagePchPcie8 = 8,
144 PchClockUsagePchPcie9 = 9,
145 PchClockUsagePchPcie10 = 10,
146 PchClockUsagePchPcie11 = 11,
147 PchClockUsagePchPcie12 = 12,
148 PchClockUsagePchPcie13 = 13,
149 PchClockUsagePchPcie14 = 14,
150 PchClockUsagePchPcie15 = 15,
151 PchClockUsagePchPcie16 = 16,
152 PchClockUsagePchPcie17 = 17,
153 PchClockUsagePchPcie18 = 18,
154 PchClockUsagePchPcie19 = 19,
155 PchClockUsagePchPcie20 = 20,
156 PchClockUsagePchPcie21 = 21,
157 PchClockUsagePchPcie22 = 22,
158 PchClockUsagePchPcie23 = 23,
159 /**
160 Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
161 silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
162 Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortIndex) style to be forward-compatible
163 **/
164 PchClockUsageCpuPcie0 = 0x40,
165 PchClockUsageCpuPcie1 = 0x41,
166 PchClockUsageCpuPcie2 = 0x42,
167 PchClockUsageCpuPcie3 = 0x43,
168
169 PchClockUsageLan = 0x70,
170 PchClockUsageUnspecified = 0x80, ///< In use for a purpose not listed above
171 PchClockUsageNotUsed = 0xFF
172 } PCH_PCIE_CLOCK_USAGE;
173
174 /**
175 PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
176 **/
177 typedef struct {
178 UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
179 UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
180 UINT8 RsvdBytes[2]; ///< Reserved byte
181 UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
182 } PCH_PCIE_CLOCK;
183
184
185 /**
186 The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
187 **/
188 typedef struct {
189 PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
190 UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
191 //
192 // Error handlings
193 //
194 UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
195 /**
196 The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
197 Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
198 DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
199 RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
200 disabled.
201 <b>0: Disable</b>; 1: Enable
202 **/
203 UINT8 MvcEnabled;
204 /**
205 Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
206 when GPIO pins expansion is needed. It is server specific feature.
207 <b>0x00: Default</b>; 0xFF: Disabled
208 **/
209 UINT8 VppPort;
210 UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
211 UINT8 RsvdBytes0[3]; ///< Reserved bytes
212 } PCH_PCIE_ROOT_PORT_CONFIG;
213
214 /**
215 The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
216 <b>Revision 1</b>:
217 - Initial version.
218 <b>Revision 2</b>:
219 - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
220 **/
221 typedef struct {
222 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
223 ///
224 /// These members describe the configuration of each PCH PCIe root port.
225 ///
226 PCIE_COMMON_CONFIG PcieCommonConfig;
227 PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
228 PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
229
230 ///
231 /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
232 ///
233 UINT8 PchPciePort8xhDecodePortIndex;
234 UINT8 DmiPowerReduction;
235 UINT8 RsvdBytes0[2];
236 } PCH_PCIE_CONFIG;
237
238 /**
239 The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
240 <b>Revision 1</b>:
241 - Initial version.
242 **/
243 typedef struct {
244 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
245 /**
246 Root Port enabling mask.
247 Bit0 presents RP1, Bit1 presents RP2, and so on.
248 0: Disable; <b>1: Enable</b>.
249 **/
250 UINT32 RpEnabledMask;
251 /// Configuration of PCIe source clocks
252 ///
253 PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
254
255 /**
256 Per Controller Bifurcation Configuration
257 <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
258 **/
259 UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
260 UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
261 } PCH_PCIE_RP_PREMEM_CONFIG;
262
263 /**
264 The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
265
266 <b>Revision 1</b>:
267 - Init version
268 **/
269 typedef struct {
270 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
271
272 /**
273 PCIe device override table
274 The PCIe device table is being used to override PCIe device ASPM settings.
275 And it's only used in DXE phase.
276 Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
277 Last entry VendorId must be 0.
278 **/
279 PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
280 } PCIE_RP_DXE_CONFIG;
281
282 #pragma pack (pop)
283
284 #endif // _PCH_PCIERP_CONFIG_H_
PCH_PCIE_CLOCK::ClkReq
UINT8 ClkReq
ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers.
Definition: PchPcieRpConfig.h:179
PCH_PCIE_CLOCK::Usage
UINT8 Usage
Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF.
Definition: PchPcieRpConfig.h:178
PCIE_RP_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:270
PCH_PCIE_CONFIG::PchPciePort8xhDecodePortIndex
UINT8 PchPciePort8xhDecodePortIndex
(Test) The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
Definition: PchPcieRpConfig.h:233
ConfigBlock.h
Header file for Config Block Lib implementation.
PCH_PCIE_CONFIG::PcieCommonConfig
PCIE_COMMON_CONFIG PcieCommonConfig
These members describe the configuration of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:226
PCH_PCIE_ROOT_PORT_CONFIG::ExtSync
UINT8 ExtSync
an instance of Pcie Common Config
Definition: PchPcieRpConfig.h:190
PCH_PCIE_CLOCK
PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
Definition: PchPcieRpConfig.h:177
PCH_PCIE_L1SUBSTATES_CONTROL
PCH_PCIE_L1SUBSTATES_CONTROL
Refer to PCH EDS for the PCH implementation values corresponding to below PCI-E spec defined ranges.
Definition: PchPcieRpConfig.h:118
PCH_PCIE_ASPM_CONTROL
PCH_PCIE_ASPM_CONTROL
The values before AutoConfig match the setting of PCI Express Base Specification 1....
Definition: PchPcieRpConfig.h:105
PchClockUsageUnspecified
@ PchClockUsageUnspecified
In use for a purpose not listed above.
Definition: PchPcieRpConfig.h:170
PCH_PCIE_ROOT_PORT_CONFIG::VppAddress
UINT8 VppAddress
PCIe Hot Plug VPP SMBus Address. Default is zero.
Definition: PchPcieRpConfig.h:210
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PchClockUsageCpuPcie0
@ PchClockUsageCpuPcie0
Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silico...
Definition: PchPcieRpConfig.h:164
PCH_PCIE_ROOT_PORT_CONFIG::SystemErrorEnable
UINT8 SystemErrorEnable
Indicate whether the System Error is enabled. 0: Disable; 1: Enable.
Definition: PchPcieRpConfig.h:194
PCH_PCIE_CONFIG
The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers Rev...
Definition: PchPcieRpConfig.h:221
PCIE_RP_DXE_CONFIG
The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:269
PCH_PCIE_ROOT_PORT_CONFIG
The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
Definition: PchPcieRpConfig.h:188
PCH_PCIE_RP_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:244
PCH_PCIE_ROOT_PORT_CONFIG::VppPort
UINT8 VppPort
Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems when GPIO pins e...
Definition: PchPcieRpConfig.h:209
PCH_PCIE_ROOT_PORT_CONFIG::MvcEnabled
UINT8 MvcEnabled
The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
Definition: PchPcieRpConfig.h:203
PCH_PCIE_CLOCK_USAGE
PCH_PCIE_CLOCK_USAGE
Definition: PchPcieRpConfig.h:134
PCH_PCIE_RP_PREMEM_CONFIG
The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers ...
Definition: PchPcieRpConfig.h:243
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PcieConfig.h
PCIe Config Block.
PCH_PCIE_RP_PREMEM_CONFIG::RpEnabledMask
UINT32 RpEnabledMask
Root Port enabling mask.
Definition: PchPcieRpConfig.h:250
PCIE_RP_DXE_CONFIG::PcieDeviceOverrideTablePtr
PCIE_DEVICE_OVERRIDE * PcieDeviceOverrideTablePtr
PCIe device override table The PCIe device table is being used to override PCIe device ASPM settings.
Definition: PchPcieRpConfig.h:279
PCH_PCIE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PchPcieRpConfig.h:222
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:337
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
PchPcieRpLib.h File Reference

Header file for PchPcieRpLib. More...

#include <Uefi.h>
#include <Library/PchPcrLib.h>
Include dependency graph for PchPcieRpLib.h:

Go to the source code of this file.

Enumerations

enum PCIE_BIFURCATION_CONFIG
PCIe controller bifurcation configuration.

Functions

PCH_SBI_PID | PchGetPcieControllerSbiPid (IN UINT32 ControllerIndex)
This function returns PID according to PCIe controller index. More...
PCH_SBI_PID | GetRpSbiPid (IN UINTN RpIndex)
This function returns PID according to Root Port Number. More...
EFI_STATUS | GetPchPcieRpDevFun (IN UINTN RpNumber, OUT UINTN *RpDev, OUT UINTN *RpFun)
Get Pch Pcie Root Port Device and Function Number by Root Port physical Number. More...
EFI_STATUS | GetPchPcieRpNumber (IN UINTN RpDev, IN UINTN RpFun, OUT UINTN *RpNumber)
Get Root Port physical Number by Pch Pcie Root Port Device and Function Number. More...
UINT64 | PchPcieBase (IN UINT32 RpIndex)
Gets pci segment base address of PCIe root port. More...
UINT8 | GetClkReqForClkSrc (IN UINT8 ClkSrc)
Checks which CLK_REQ signal is assigned to given CLK_SRC. More...
BOOLEAN | PchIsPcieL0sSupported (VOID)
Determines whether L0s is supported on current stepping. More...
BOOLEAN | PchIsPcieNativeAspmSupported (VOID)
Some early PCH steppings require Native ASPM to be disabled due to hardware issues: More...

Detailed Description

Header file for PchPcieRpLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieRpLib.h.

Function Documentation

◆ GetClkReqForClkSrc()

UINT8 GetClkReqForClkSrc ( IN UINT8 ClkSrc )

Checks which CLK_REQ signal is assigned to given CLK_SRC.

Parameters
ClkSrc number of CLK_SRC, 0-based
Return values
number of CLK_REQ, 0-based

◆ GetPchPcieRpDevFun()

EFI_STATUS GetPchPcieRpDevFun | ( | IN UINTN | RpNumber,
 |  | OUT UINTN * | RpDev,
 |  | OUT UINTN * | RpFun
 | ) |  |

Get Pch Pcie Root Port Device and Function Number by Root Port physical Number.

Parameters
[in] | RpNumber | Root port physical number. (0-based)
[out] | RpDev | Return corresponding root port device number.
[out] | RpFun | Return corresponding root port function number.
Return values
EFI_SUCCESS

◆ GetPchPcieRpNumber()

EFI_STATUS GetPchPcieRpNumber | ( | IN UINTN | RpDev,
 |  | IN UINTN | RpFun,
 |  | OUT UINTN * | RpNumber
 | ) |  |

Get Root Port physical Number by Pch Pcie Root Port Device and Function Number.

Parameters
[in] | RpDev | Root port device number.
[in] | RpFun | Root port function number.
[out] | RpNumber | Return corresponding physical Root Port index (0-based)
Return values
EFI_SUCCESS | Physical root port is retrieved
EFI_INVALID_PARAMETER | RpDev and/or RpFun are invalid
EFI_UNSUPPORTED | Root port device and function is not assigned to any physical root port

◆ GetRpSbiPid()

PCH_SBI_PID GetRpSbiPid ( IN UINTN RpIndex )

This function returns PID according to Root Port Number.

Parameters
[in] RpIndex Root Port Index (0-based)
Return values
PCH_SBI_PID Returns PID for SBI Access

◆ PchGetPcieControllerSbiPid()

PCH_SBI_PID PchGetPcieControllerSbiPid ( IN UINT32 ControllerIndex )

This function returns PID according to PCIe controller index.

Parameters
[in] ControllerIndex PCIe controller index
Return values
PCH_SBI_PID Returns PID for SBI Access

◆ PchIsPcieL0sSupported()

BOOLEAN PchIsPcieL0sSupported ( VOID )

Determines whether L0s is supported on current stepping.

Returns
TRUE if L0s is supported, FALSE otherwise

◆ PchIsPcieNativeAspmSupported()

BOOLEAN PchIsPcieNativeAspmSupported ( VOID )

Some early PCH steppings require Native ASPM to be disabled due to hardware issues:

  • RxL0s exit causes recovery
  • Disabling PCIe L0s capability disables L1 Use this function to determine affected steppings.
Returns
TRUE if Native ASPM is supported, FALSE otherwise

◆ PchPcieBase()

UINT64 PchPcieBase ( IN UINT32 RpIndex )

Gets pci segment base address of PCIe root port.

Parameters
RpIndex Root Port Index (0 based)
Returns
PCIe port base address.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PchPcieRpLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchPcieRpLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCIERP_LIB_H_
36 #define _PCH_PCIERP_LIB_H_
37
38 #include <Uefi.h>
39 #include <Library/PchPcrLib.h>
40
41 /**
42 PCIe controller bifurcation configuration.
43 **/
44 typedef enum {
45 PcieBifurcationDefault = 0,
46 PcieBifurcation4x1,
47 PcieBifurcation1x2_2x1,
48 PcieBifurcation2x2,
49 PcieBifurcation1x4,
50 PcieBifurcation4x2,
51 PcieBifurcation1x4_2x2,
52 PcieBifurcation2x2_1x4,
53 PcieBifurcation2x4,
54 PcieBifurcation1x8,
55 PcieBifurcationUnknown,
56 PcieBifurcationMax
57 } PCIE_BIFURCATION_CONFIG;
58
59 /**
60 This function returns PID according to PCIe controller index
61
62 @param[in] ControllerIndex PCIe controller index
63
64 @retval PCH_SBI_PID Returns PID for SBI Access
65 **/
66 PCH_SBI_PID
67 PchGetPcieControllerSbiPid (
68 IN UINT32 ControllerIndex
69 );
70
71 /**
72 This function returns PID according to Root Port Number
73
74 @param[in] RpIndex Root Port Index (0-based)
75
76 @retval PCH_SBI_PID Returns PID for SBI Access
77 **/
78 PCH_SBI_PID
79 GetRpSbiPid (
80 IN UINTN RpIndex
81 );
82
83 /**
84 Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
85
86 @param[in] RpNumber Root port physical number. (0-based)
87 @param[out] RpDev Return corresponding root port device number.
88 @param[out] RpFun Return corresponding root port function number.
89
90 @retval EFI_SUCCESS
91 **/
92 EFI_STATUS
93 EFIAPI
94 GetPchPcieRpDevFun (
95 IN UINTN RpNumber,
96 OUT UINTN *RpDev,
97 OUT UINTN *RpFun
98 );
99
100 /**
101 Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
102
103 @param[in] RpDev Root port device number.
104 @param[in] RpFun Root port function number.
105 @param[out] RpNumber Return corresponding physical Root Port index (0-based)
106
107 @retval EFI_SUCCESS Physical root port is retrieved
108 @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
109 @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
110 **/
111 EFI_STATUS
112 EFIAPI
113 GetPchPcieRpNumber (
114 IN UINTN RpDev,
115 IN UINTN RpFun,
116 OUT UINTN *RpNumber
117 );
118
119 /**
120 Gets pci segment base address of PCIe root port.
121
122 @param RpIndex Root Port Index (0 based)
123 @return PCIe port base address.
124 **/
125 UINT64
126 PchPcieBase (
127 IN UINT32 RpIndex
128 );
129
130 /**
131 Checks which CLK_REQ signal is assigned to given CLK_SRC
132
133 @param ClkSrc number of CLK_SRC, 0-based
134 @retval number of CLK_REQ, 0-based
135 **/
136 UINT8
137 GetClkReqForClkSrc (
138 IN UINT8 ClkSrc
139 );
140
141 /**
142 Determines whether L0s is supported on current stepping.
143
144 @return TRUE if L0s is supported, FALSE otherwise
145 **/
146 BOOLEAN
147 PchIsPcieL0sSupported (
148 VOID
149 );
150
151 /**
152 Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
153 - RxL0s exit causes recovery
154 - Disabling PCIe L0s capability disables L1
155 Use this function to determine affected steppings.
156
157 @return TRUE if Native ASPM is supported, FALSE otherwise
158 **/
159 BOOLEAN
160 PchIsPcieNativeAspmSupported (
161 VOID
162 );
163 #endif // _PCH_PCIERP_LIB_H_
PCIE_BIFURCATION_CONFIG
PCIE_BIFURCATION_CONFIG
PCIe controller bifurcation configuration.
Definition: PchPcieRpLib.h:44
GetPchPcieRpNumber
EFI_STATUS GetPchPcieRpNumber(IN UINTN RpDev, IN UINTN RpFun, OUT UINTN *RpNumber)
Get Root Port physical Number by Pch Pcie Root Port Device and Function Number.
PchGetPcieControllerSbiPid
PCH_SBI_PID PchGetPcieControllerSbiPid(IN UINT32 ControllerIndex)
This function returns PID according to PCIe controller index.
PchIsPcieNativeAspmSupported
BOOLEAN PchIsPcieNativeAspmSupported(VOID)
Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
GetRpSbiPid
PCH_SBI_PID GetRpSbiPid(IN UINTN RpIndex)
This function returns PID according to Root Port Number.
PchIsPcieL0sSupported
BOOLEAN PchIsPcieL0sSupported(VOID)
Determines whether L0s is supported on current stepping.
PchPcieBase
UINT64 PchPcieBase(IN UINT32 RpIndex)
Gets pci segment base address of PCIe root port.
GetPchPcieRpDevFun
EFI_STATUS GetPchPcieRpDevFun(IN UINTN RpNumber, OUT UINTN *RpDev, OUT UINTN *RpFun)
Get Pch Pcie Root Port Device and Function Number by Root Port physical Number.
PchPcrLib.h
Header file for PchPcrLib.
GetClkReqForClkSrc
UINT8 GetClkReqForClkSrc(IN UINT8 ClkSrc)
Checks which CLK_REQ signal is assigned to given CLK_SRC.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchPcieRpRegs.h File Reference

Register names for PCH PCI-E root port devices. More...

Go to the source code of this file.

Macros

#define | R_PCH_PCIE_CFG_EX_AECH 0x100
Advanced Error Reporting Capability Header.
#define | R_PCH_PCIE_CFG_EX_CES 0x110
Correctable Error Status.
#define | B_PCH_PCIE_CFG_EX_CES_BD BIT7
Bad DLLP Status.
#define | B_PCH_PCIE_CFG_EX_CES_BT BIT6
Bad TLP Status.
#define | B_PCH_PCIE_CFG_EX_CES_RE BIT0
Receiver Error Status.
#define | R_PCH_PCIE_CFG_L1SCTL2 0x20C
L1 Sub-States Control 2.
#define | R_PCH_PCIE_CFG_EX_ACSECH 0x220
ACS Extended Capability Header.
#define | R_PCH_PCIE_CFG_EX_PTMECH 0x150
PTM Extended Capability Header.
#define | R_PCH_PCIE_CFG_VC0CTL 0x294
Virtual Channel 0 Resource Control.
#define | R_PCH_PCIE_CFG_EX_L1SECH 0x200
L1 Sub-States Extended Capability Header.
#define | R_PCH_PCIE_CFG_EX_DPCECH 0xA00
Downstream Port Containment.
#define | R_PCH_PCIE_CFG_PTMPD 0x390
PTM Propagation Delay.
#define | R_PCH_PCIE_CFG_PTMLLMT 0x394
PTM Lower Local Master Time.
#define | R_PCH_PCIE_CFG_PTMULMT 0x398
PTM Upper Local Master Time.
#define | R_PCH_PCIE_CFG_PTMPSDC1 0x39C
PTM Pipe Stage Delay Configuration 1.
#define | R_PCH_PCIE_CFG_PTMPSDC2 0x3A0
PTM Pipe Stage Delay Configuration 2.
#define | R_PCH_PCIE_CFG_PTMPSDC3 0x3A4
PTM Pipe Stage Delay Configuration 3.
#define | R_PCH_PCIE_CFG_PTMPSDC4 0x3A8
PTM Pipe Stage Delay Configuration 4.
#define | R_PCH_PCIE_CFG_PTMPSDC5 0x3AC
PTM Pipe Stage Delay Configuration 5.
#define | R_PCH_PCIE_CFG_PTMECFG 0x3B0
PTM Extended Configuration.
#define | B_PCH_PCIE_CFG_PTMECFG_IOSFMADP 0xF
IOSF Max Allowed Delay programming. bit0~bit3.
#define | B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31
LTR Non-Snoop Requirement Bit Override.
#define | B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15
LTR Snoop Requirement Bit Override.
#define | B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3
LTR Force Override Enable.
#define | B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2
LTR Override Lock.
#define | B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1
LTR Non-Snoop Override Enable.
#define | B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0
LTR Snoop Override Enable.
#define | R_PCH_PCIE_CFG_TNPT 0x418
Thermal and Power Throttling.
#define | R_SPX_PCR_PCD 0
Port configuration and disable.
#define | B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0)
Port 1 Function Number.
#define | B_SPX_PCR_PCD_RP1CH BIT3
Port 1 config hide.
#define | B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4)
Port 2 Function Number.
#define | B_SPX_PCR_PCD_RP2CH BIT7
Port 2 config hide.
#define | B_SPX_PCR_PCD_RP3FN (BIT10 | BIT9 | BIT8)
Port 3 Function Number.
#define | B_SPX_PCR_PCD_RP3CH BIT11
Port 3 config hide.
#define | B_SPX_PCR_PCD_RP4FN (BIT14 | BIT13 | BIT12)
Port 4 Function Number.
#define | B_SPX_PCR_PCD_RP4CH BIT15
Port 4 config hide.
#define | S_SPX_PCR_PCD_RP_FIELD 4
4 bits for each RP FN
#define | B_SPX_PCR_PCD_P1D BIT16
Port 1 disable.
#define | B_SPX_PCR_PCD_P2D BIT17
Port 2 disable.
#define | B_SPX_PCR_PCD_P3D BIT18
Port 3 disable.
#define | B_SPX_PCR_PCD_P4D BIT19
Port 4 disable.
#define | B_SPX_PCR_PCD_SRL BIT31
Secured Register Lock.
#define | R_SPX_PCR_PCIEHBP 0x0004
PCI Express high-speed bypass.
#define | B_SPX_PCR_PCIEHBP_PCIEHBPME BIT0
PCIe HBP mode enable.
#define | B_SPX_PCR_PCIEHBP_PCIEGMO (BIT2 | BIT1)
PCIe gen mode override.
#define | B_SPX_PCR_PCIEHBP_PCIETIL0O BIT3
PCIe transmitter-in-L0 override.
#define | B_SPX_PCR_PCIEHBP_PCIERIL0O BIT4
PCIe receiver-in-L0 override.
#define | B_SPX_PCR_PCIEHBP_PCIELRO BIT5
PCIe link recovery override.
#define | B_SPX_PCR_PCIEHBP_PCIELDO BIT6
PCIe link down override.
#define | B_SPX_PCR_PCIEHBP_PCIESSM BIT7
PCIe SKP suppression mode.
#define | B_SPX_PCR_PCIEHBP_PCIESST BIT8
PCIe suppress SKP transmission.
#define | B_SPX_PCR_PCIEHBP_PCIEHBPPS (BIT13 | BIT12)
PCIe HBP port select.
#define | B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14)
CRC select.
#define | B_SPX_PCR_PCIEHBP_PCIEHBPCRC 0xFFFF0000
PCIe HBP CRC.
#define | R_SPX_PCR_IMRAMBL 0x10
IMR access memory base and limit.
#define | B_SPX_PCR_IMRAMBL_RS3BN 0x000000FF
Bus Number for RS3.
#define | B_SPX_PCR_IMRAMBL_IAMB 0x000FFF00
IMR access memory base, lower bits.
#define | B_SPX_PCR_IMRAMBL_IAML 0xFFF00000
IMR access memory limit, lower bits.
#define | R_SPX_PCR_IMRAMBU32 0x14
IMR access memory base, upper bits.
#define | R_SPX_PCR_IMRAMLU32 0x18
IMR access memory limit, upper bits.
#define | R_SPX_PCR_IMRAMLE 0x1C
IMR access memory lock & enable.
#define | B_SPX_PCR_IMRAMLE_IAE1 BIT0
IMR access enable for port 1 of given controller.
#define | B_SPX_PCR_IMRAMLE_IAE2 BIT1
IMR access enable for port 1 of given controller.
#define | B_SPX_PCR_IMRAMLE_IAE3 BIT2
IMR access enable for port 1 of given controller.
#define | B_SPX_PCR_IMRAMLE_IAE4 BIT3
IMR access enable for port 1 of given controller.
#define | B_SPX_PCR_IMRAMLE_SRL BIT31
IMR register lock.
#define | R_SPX_SIP16_PCR_PCD 0x3E00
Port configuration and disable.
#define | R_ICC_PCR_TMCSRCCLK 0x1000
Timing Control SRC Clock Register.
#define | R_ICC_PCR_TMCSRCCLK2 0x1004
Timing Control SRC Clock Register 2.
#define | R_ICC_PCR_MSKCKRQ 0x100C
Mask Control CLKREQ.

Detailed Description

Register names for PCH PCI-E root port devices.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieRpRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRpRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
PchPcieRpRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH PCI-E root port devices
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_REGS_PCIE_H_
65 #define _PCH_REGS_PCIE_H_
66
67 #define V_PCH_PCIE_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID
68
69 #define R_PCH_PCIE_CFG_MID 0x80
70 #define S_PCH_PCIE_CFG_MID 2
71 #define R_PCH_PCIE_CFG_MC 0x82
72 #define S_PCH_PCIE_CFG_MC 2
73 #define R_PCH_PCIE_CFG_MA 0x84
74 #define S_PCH_PCIE_CFG_MA 4
75 #define R_PCH_PCIE_CFG_MD 0x88
76 #define S_PCH_PCIE_CFG_MD 2
77
78 #define R_PCH_PCIE_CFG_SVCAP 0x90
79 #define R_PCH_PCIE_CFG_SIP17_SVCAP 0x98
80 #define S_PCH_PCIE_CFG_SVCAP 2
81 #define R_PCH_PCIE_CFG_SVID 0x94
82 #define S_PCH_PCIE_CFG_SVID 4
83
84 #define R_PCH_PCIE_CFG_PMCAP 0xA0
85 #define R_PCH_PCIE_CFG_PMCS (R_PCH_PCIE_CFG_PMCAP + R_PCIE_PMCS_OFFST)
86
87 #define R_PCH_PCIE_CFG_MPC2 0xD4
88 #define B_PCH_PCIE_CFG_MPC2_L1SSESE BIT30
89 #define B_PCH_PCIE_CFG_MPC2_PLLWAIT (BIT26 | BIT25 | BIT24)
90 #define B_PCH_PCIE_CFG_MPC2_DISPLLEWL1SE BIT16
91 #define S_PCH_PCIE_CFG_MPC2 4
92 #define B_PCH_PCIE_CFG_MPC2_PTNFAE BIT12
93 #define B_PCH_PCIE_CFG_MPC2_LSTP BIT6
94 #define B_PCH_PCIE_CFG_MPC2_IEIME BIT5
95 #define B_PCH_PCIE_CFG_MPC2_ASPMCOEN BIT4
96 #define B_PCH_PCIE_CFG_MPC2_ASPMCO (BIT3 | BIT2)
97 #define V_PCH_PCIE_CFG_MPC2_ASPMCO_DISABLED 0
98 #define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S (1 << 2)
99 #define V_PCH_PCIE_CFG_MPC2_ASPMCO_L1 (2 << 2)
100 #define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S_L1 (3 << 2)
101 #define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1
102
103 #define R_PCH_PCIE_CFG_MPC 0xD8
104 #define S_PCH_PCIE_CFG_MPC 4
105 #define B_PCH_PCIE_CFG_MPC_PMCE BIT31
106 #define B_PCH_PCIE_CFG_MPC_HPCE BIT30
107 #define B_PCH_PCIE_CFG_MPC_MMBNCE BIT27
108 #define B_PCH_PCIE_CFG_MPC_P8XDE BIT26
109 #define B_PCH_PCIE_CFG_MPC_IRRCE BIT25
110 #define B_PCH_PCIE_CFG_MPC_SRL BIT23
111 #define B_PCH_PCIE_CFG_MPC_UCEL (BIT20 | BIT19 | BIT18)
112 #define N_PCH_PCIE_CFG_MPC_UCEL 18
113 #define B_PCH_PCIE_CFG_MPC_CCEL (BIT17 | BIT16 | BIT15)
114 #define N_PCH_PCIE_CFG_MPC_CCEL 15
115 #define B_PCH_PCIE_CFG_MPC_PCIESD (BIT14 | BIT13)
116 #define N_PCH_PCIE_CFG_MPC_PCIESD 13
117 #define V_PCH_PCIE_CFG_MPC_PCIESD_GEN1 1
118 #define V_PCH_PCIE_CFG_MPC_PCIESD_GEN2 2
119 #define V_PCH_PCIE_CFG_MPC_PCIESD_GEN3 3
120 #define V_PCH_PCIE_CFG_MPC_PCIESD_GEN4 4
121 #define B_PCH_PCIE_CFG_MPC_MCTPSE BIT3
122 #define B_PCH_PCIE_CFG_MPC_HPME BIT1
123 #define N_PCH_PCIE_CFG_MPC_HPME 1
124 #define B_PCH_PCIE_CFG_MPC_PMME BIT0
125
126 #define R_PCH_PCIE_CFG_SMSCS 0xDC
127 #define S_PCH_PCIE_CFG_SMSCS 4
128 #define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31
129 #define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5
130 #define N_PCH_PCIE_CFG_SMSCS_HPLAS 4
131 #define N_PCH_PCIE_CFG_SMSCS_HPPDM 1
132
133 #define R_PCH_PCIE_CFG_SPR 0xE0
134
135 #define R_PCH_PCIE_CFG_RPDCGEN 0xE1
136 #define S_PCH_PCIE_CFG_RPDCGEN 1
137 #define B_PCH_PCIE_CFG_RPDCGEN_RPSCGEN BIT7
138 #define B_PCH_PCIE_CFG_RPDCGEN_PTOCGE BIT6
139 #define B_PCH_PCIE_CFG_RPDCGEN_LCLKREQEN BIT5
140 #define B_PCH_PCIE_CFG_RPDCGEN_BBCLKREQEN BIT4
141 #define B_PCH_PCIE_CFG_RPDCGEN_SRDBCGEN BIT2
142 #define B_PCH_PCIE_CFG_RPDCGEN_RPDLCGEN BIT1
143 #define B_PCH_PCIE_CFG_RPDCGEN_RPDBCGEN BIT0
144
145 #define R_PCH_PCIE_CFG_RPPGEN 0xE2
146 #define B_PCH_PCIE_CFG_RPPGEN_PTOTOP BIT6
147 #define B_PCH_PCIE_CFG_RPPGEN_SEOSCGE BIT4
148
149 #define R_PCH_PCIE_CFG_PWRCTL 0xE8
150 #define B_PCH_PCIE_CFG_PWRCTL_LTSSMRTC BIT20
151 #define B_PCH_PCIE_CFG_PWRCTL_WPDMPGEP BIT17
152 #define B_PCH_PCIE_CFG_PWRCTL_DBUPI BIT15
153 #define B_PCH_PCIE_CFG_PWRCTL_TXSWING BIT13
154 #define B_PCH_PCIE_CFG_PWRCTL_RPL1SQPOL BIT1
155 #define B_PCH_PCIE_CFG_PWRCTL_RPDTSQPOL BIT0
156
157 #define R_PCH_PCIE_CFG_DC 0xEC
158 #define B_PCH_PCIE_CFG_DC_PCIBEM BIT2
159 #define B_PCH_PCIE_CFG_DC_COM BIT13
160
161 #define R_PCH_PCIE_CFG_IPCS 0xF0
162 #define B_PCH_PCIE_CFG_IPCS_IMPS (BIT10 | BIT9 | BIT8)
163 #define N_PCH_PCIE_CFG_IPCS_IMPS 8
164 #define V_PCH_PCIE_CFG_IPCS_IMPS_64B 7
165 #define V_PCH_PCIE_CFG_IPCS_IMPS_256B 1
166
167 #define R_PCH_PCIE_CFG_PHYCTL2 0xF5
168 #define B_PCH_PCIE_CFG_PHYCTL2_TDFT (BIT7 | BIT6)
169 #define B_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4)
170 #define N_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT 4
171 #define B_PCH_PCIE_CFG_PHYCTL2_PXPG3PLLOFFEN BIT1
172 #define B_PCH_PCIE_CFG_PHYCTL2_PXPG2PLLOFFEN BIT0
173
174 #define R_PCH_PCIE_CFG_IOSFSBCS 0xF7
175 #define B_PCH_PCIE_CFG_IOSFSBCS_SCPTCGE BIT6
176 #define B_PCH_PCIE_CFG_IOSFSBCS_SIID (BIT3 | BIT2)
177
178 #define R_PCH_PCIE_CFG_STRPFUSECFG 0xFC
179 #define B_PCH_PCIE_CFG_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT25 | BIT24)
180 #define N_PCH_PCIE_CFG_STRPFUSECFG_PXIP 24
181 #define B_PCH_PCIE_CFG_STRPFUSECFG_RPC_SIP17 (BIT16 | BIT15 | BIT14)
182 #define B_PCH_PCIE_CFG_STRPFUSECFG_RPC (BIT15 | BIT14)
183 #define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_1_1_1_1 0
184 #define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_1_1 1
185 #define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_2 2
186 #define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_4 3
187 #define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_4_SIP17 4
188 #define N_PCH_PCIE_CFG_STRPFUSECFG_RPC 14
189 #define B_PCH_PCIE_CFG_STRPFUSECFG_MODPHYIOPMDIS BIT9
190 #define B_PCH_PCIE_CFG_STRPFUSECFG_PLLSHTDWNDIS BIT8
191 #define B_PCH_PCIE_CFG_STRPFUSECFG_STPGATEDIS BIT7
192 #define B_PCH_PCIE_CFG_STRPFUSECFG_ASPMDIS BIT6
193 #define B_PCH_PCIE_CFG_STRPFUSECFG_LDCGDIS BIT5
194 #define B_PCH_PCIE_CFG_STRPFUSECFG_LTCGDIS BIT4
195 #define B_PCH_PCIE_CFG_STRPFUSECFG_CDCGDIS BIT3
196 #define B_PCH_PCIE_CFG_STRPFUSECFG_DESKTOPMOB BIT2
197
198 //
199 //PCI Express Extended Capability Registers
200 //
201
202 #define R_PCH_PCIE_CFG_EXCAP_OFFSET 0x100
203
204 #define R_PCH_PCIE_CFG_EX_AECH 0x100 ///< Advanced Error Reporting Capability Header
205 #define V_PCH_PCIE_CFG_EX_AEC_CV 0x1
206 #define R_PCH_PCIE_CFG_EX_UEM (R_PCH_PCIE_CFG_EX_AECH + R_PCIE_EX_UEM_OFFSET) // Uncorrectable Error Mask
207
208 #define R_PCH_PCIE_CFG_EX_CES 0x110 ///< Correctable Error Status
209 #define B_PCH_PCIE_CFG_EX_CES_BD BIT7 ///< Bad DLLP Status
210 #define B_PCH_PCIE_CFG_EX_CES_BT BIT6 ///< Bad TLP Status
211 #define B_PCH_PCIE_CFG_EX_CES_RE BIT0 ///< Receiver Error Status
212
213 #define R_PCH_PCIE_CFG_L1SCTL2 0x20C ///< L1 Sub-States Control 2
214 #define B_PCH_PCIE_CFG_L1SCTL2_POWT BIT3
215 #define B_PCH_PCIE_CFG_L1SCTL2_POWT_OFFSET 3
216 #define B_PCH_PCIE_CFG_L1SCTL2_POWT_MASK 0x000000F8
217 #define V_PCH_PCIE_CFG_L1SCTL2_POWT 0x5
218 #define B_PCH_PCIE_CFG_L1SCTL2_TPOS BIT0
219 #define B_PCH_PCIE_CFG_L1SCTL2_TPOS_OFFSET 0
220 #define B_PCH_PCIE_CFG_L1SCTL2_TPOS_MASK 0x00000003
221 #define V_PCH_PCIE_CFG_L1SCTL2_TPOS 0x2
222
223 //CES.RE, CES.BT, CES.BD
224
225 #define R_PCH_PCIE_CFG_EX_ACSECH 0x220 ///< ACS Extended Capability Header
226 #define V_PCH_PCIE_CFG_EX_ACS_CV 0x1
227 #define R_PCH_PCIE_CFG_EX_ACSCAPR (R_PCH_PCIE_CFG_EX_ACSECH + R_PCIE_EX_ACSCAPR_OFFSET)
228
229 #define R_PCH_PCIE_CFG_EX_PTMECH 0x150 ///< PTM Extended Capability Header
230 #define V_PCH_PCIE_CFG_EX_PTM_CV 0x1
231 #define R_PCH_PCIE_CFG_EX_PTMCAPR (R_PCH_PCIE_CFG_EX_PTMECH + R_PCIE_EX_PTMCAP_OFFSET)
232
233 #define R_PCH_PCIE_CFG_PVCCR1 0x284
234 #define B_PCH_PCIE_CFG_PVCCR1_EVCC_MASK 0x7
235 #define V_PCH_PCIE_CFG_PVCCR1_EVCC_2_VC 0x1
236
237 #define R_PCH_PCIE_CFG_V0VCRC 0x290
238 #define B_PCH_PCIE_CFG_V0VCRC_MTS_MASK 0x7F0000
239
240 #define R_PCH_PCIE_CFG_VC0CTL 0x294 ///< Virtual Channel 0 Resource Control
241 #define B_PCH_PCIE_CFG_VC0CTL_TVM_MASK 0xFE
242 #define B_PCH_PCIE_CFG_VC0CTL_TVM_OFFSET 1
243 #define B_PCH_PCIE_CFG_VC0CTL_TVM_NO_VC 0x7F
244 #define B_PCH_PCIE_CFG_VC0CTL_TVM_EN_VC 0x1F
245 #define B_PCH_PCIE_CFG_VC0CTL_ETVM_MASK 0x3F
246 #define B_PCH_PCIE_CFG_VC0CTL_ETVM_OFFSET 10
247
248 #define R_PCH_PCIE_CFG_V1VCRC 0x29C
249 #define B_PCH_PCIE_CFG_V1VCRC_MTS_MASK 0x7F0000
250
251 #define R_PCH_PCIE_CFG_VC1CTL 0x2A0
252 #define B_PCH_PCIE_CFG_VC1CTL_TVM_MASK 0xFE
253 #define B_PCH_PCIE_CFG_VC1CTL_TVM BIT1
254 #define B_PCH_PCIE_CFG_VC1CTL_TVM_OFFSET 1
255 #define V_PCH_PCIE_CFG_VC1CTL_TVM 0x7F
256 #define B_PCH_PCIE_CFG_VC1CTL_ETVM_MASK 0x1F
257 #define B_PCH_PCIE_CFG_VC1CTL_ETVM_OFFSET 10
258 #define B_PCH_PCIE_CFG_VC1CTL_ID_MASK 0xF000000
259 #define B_PCH_PCIE_CFG_VC1CTL_ID_OFFSET 24
260 #define V_PCH_PCIE_CFG_VC1CTL_ID_ONE 1
261 #define B_PCH_PCIE_CFG_VC1CTL_EN_OFFSET 0x80000000
262 #define B_PCH_PCIE_CFG_VC1CTL_EN BIT31
263
264 #define R_PCH_PCIE_CFG_VC1STS 0x2A6
265 #define B_PCH_PCIE_CFG_VC1STS_NP BIT1
266
267 #define R_PCH_PCIE_CFG_VC0STS 0x2A9
268 #define B_PCH_PCIE_CFG_VC0STS_NP BIT1
269
270 #define R_PCH_PCIE_CFG_V1VCRC 0x29C
271 #define R_PCH_PCIE_CFG_V1VCRC_MTS_MASK 0x7F
272 #define R_PCH_PCIE_CFG_V1VCRC_MTS_OFFSET 16
273
274 #define R_PCH_PCIE_CFG_EX_L1SECH 0x200 ///< L1 Sub-States Extended Capability Header
275 #define V_PCH_PCIE_CFG_EX_L1S_CV 0x1
276 #define R_PCH_PCIE_CFG_EX_L1SCAP (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCAP_OFFSET)
277 #define R_PCH_PCIE_CFG_EX_L1SCTL1 (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCTL1_OFFSET)
278 #define R_PCH_PCIE_CFG_EX_L1SCTL2 (R_PCH_PCIE_CFG_EX_L1SECH + R_PCIE_EX_L1SCTL2_OFFSET)
279
280 #define R_PCH_PCIE_CFG_EX_DPCECH 0xA00 ///< Downstream Port Containment
281 #define V_PCH_PCIE_CFG_EX_DPCECH_CV 0x1
282
283 #define R_PCH_PCIE_CFG_PCIERTP1 0x300
284 #define R_PCH_PCIE_CFG_PCIERTP2 0x304
285 #define R_PCH_PCIE_CFG_G4L0SCTL 0x310
286 #define R_PCH_PCIE_CFG_PCIENFTS 0x314
287 #define R_PCH_PCIE_CFG_PCIEL0SC 0x318
288 #define R_PCH_PCIE_CFG_G4L0SCTL 0x310
289 #define R_PCH_PCIE_CFG_G5L0SCTL 0x1E00
290
291 #define R_PCH_PCIE_CFG_PCIECFG2 0x320
292 #define B_PCH_PCIE_CFG_PCIECFG2_LBWSSTE BIT30
293 #define B_PCH_PCIE_CFG_PCIECFG2_RLLG3R BIT27
294 #define B_PCH_PCIE_CFG_PCIECFG2_CROAOV BIT24
295 #define B_PCH_PCIE_CFG_PCIECFG2_CROAOE BIT23
296 #define B_PCH_PCIE_CFG_PCIECFG2_CRSREN BIT22
297 #define B_PCH_PCIE_CFG_PCIECFG2_PMET (BIT21 | BIT20)
298 #define V_PCH_PCIE_CFG_PCIECFG2_PMET 1
299 #define N_PCH_PCIE_CFG_PCIECFG2_PMET 20
300
301 #define R_PCH_PCIE_CFG_PCIEDBG 0x324
302 #define B_PCH_PCIE_CFG_PCIEDBG_LBWSSTE BIT30
303 #define B_PCH_PCIE_CFG_PCIEDBG_USSP (BIT27 | BIT26)
304 #define B_PCH_PCIE_CFG_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24)
305 #define B_PCH_PCIE_CFG_PCIEDBG_CTONFAE BIT14
306 #define B_PCH_PCIE_CFG_PCIEDBG_LDSWQRP BIT13
307 #define B_PCH_PCIE_CFG_PCIEDBG_SQOL0 BIT7
308 #define B_PCH_PCIE_CFG_PCIEDBG_SPCE BIT5
309 #define B_PCH_PCIE_CFG_PCIEDBG_LR BIT4
310
311 #define R_PCH_PCIE_CFG_PCIESTS1 0x328
312 #define B_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 0xFF000000
313 #define N_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 24
314 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDY 0x01
315 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E
316 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_L0 0x33
317 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAIT 0x5E
318 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAITPG 0x60
319 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C
320 #define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F
321
322
323 #define B_PCH_PCIE_CFG_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT20 | BIT19)
324 #define N_PCH_PCIE_CFG_PCIESTS1_LNKSTAT 19
325 #define V_PCH_PCIE_CFG_PCIESTS1_LNKSTAT_L0 0x7
326
327 #define R_PCH_PCIE_CFG_PCIESTS2 0x32C
328 #define B_PCH_PCIE_CFG_PCIESTS2_P4PNCCWSSCMES BIT31
329 #define B_PCH_PCIE_CFG_PCIESTS2_P3PNCCWSSCMES BIT30
330 #define B_PCH_PCIE_CFG_PCIESTS2_P2PNCCWSSCMES BIT29
331 #define B_PCH_PCIE_CFG_PCIESTS2_P1PNCCWSSCMES BIT28
332 #define B_PCH_PCIE_CFG_PCIESTS2_CLRE 0x0000F000
333 #define N_PCH_PCIE_CFG_PCIESTS2_CLRE 12
334
335 #define R_PCH_PCIE_CFG_PCIEALC 0x338
336 #define B_PCH_PCIE_CFG_PCIEALC_ITLRCLD BIT29
337 #define B_PCH_PCIE_CFG_PCIEALC_ILLRCLD BIT28
338 #define B_PCH_PCIE_CFG_PCIEALC_BLKDQDA BIT26
339 #define B_PCH_PCIE_CFG_PCIEALC_BLKDQDASD BIT25
340 #define B_PCH_PCIE_CFG_PCIEALC_RTD3PDSP_SIP17 BIT21
341 #define B_PCH_PCIE_CFG_PCIEALC_RTD3PDSP BIT20
342 #define B_PCH_PCIE_CFG_SIP17_PCIEALC_RTD3PDSP BIT21 /// From SIP17 register layout is changed
343 #define B_PCH_PCIE_CFG_SIP17_PCIEALC_PDSP BIT20 /// From SIP17 register layout is changed
344
345 #define R_PCH_PCIE_CFG_PTMPD 0x390 ///< PTM Propagation Delay
346 #define R_PCH_PCIE_CFG_PTMLLMT 0x394 ///< PTM Lower Local Master Time
347 #define R_PCH_PCIE_CFG_PTMULMT 0x398 ///< PTM Upper Local Master Time
348 #define R_PCH_PCIE_CFG_PTMPSDC1 0x39C ///< PTM Pipe Stage Delay Configuration 1
349 #define R_PCH_PCIE_CFG_PTMPSDC2 0x3A0 ///< PTM Pipe Stage Delay Configuration 2
350 #define R_PCH_PCIE_CFG_PTMPSDC3 0x3A4 ///< PTM Pipe Stage Delay Configuration 3
351 #define R_PCH_PCIE_CFG_PTMPSDC4 0x3A8 ///< PTM Pipe Stage Delay Configuration 4
352 #define R_PCH_PCIE_CFG_PTMPSDC5 0x3AC ///< PTM Pipe Stage Delay Configuration 5
353 #define R_PCH_PCIE_CFG_PTMECFG 0x3B0 ///< PTM Extended Configuration
354 #define B_PCH_PCIE_CFG_PTMECFG_IOSFMADP 0xF ///< IOSF Max Allowed Delay programming. bit0~bit3
355
356 #define R_PCH_PCIE_CFG_LTROVR 0x400
357 #define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non-Snoop Requirement Bit Override
358 #define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop Requirement Bit Override
359
360 #define R_PCH_PCIE_CFG_LTROVR2 0x404
361 #define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR Force Override Enable
362 #define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Override Lock
363 #define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR Non-Snoop Override Enable
364 #define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR Snoop Override Enable
365
366 #define R_PCH_PCIE_CFG_PHYCTL4 0x408
367 #define B_PCH_PCIE_CFG_PHYCTL4_SQDIS BIT27
368
369 #define R_PCH_PCIE_CFG_TNPT 0x418 ///< Thermal and Power Throttling
370 #define B_PCH_PCIE_CFG_TNPT_DRXLTE BIT1
371 #define B_PCH_PCIE_CFG_TNPT_DTXLTE BIT0
372 #define N_PCH_PCIE_CFG_TNPT_TP 24
373 #define V_PCH_PCIE_CFG_TNPT_TP_3_MS 0x2
374 #define R_PCH_PCIE_CFG_PCIEPMECTL 0x420
375 #define B_PCH_PCIE_CFG_PCIEPMECTL_FDPPGE BIT31
376 #define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30
377 #define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULDLSD BIT29
378 #define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17
379 #define B_PCH_PCIE_CFG_PCIEPMECTL_L1LTRTLV (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4)
380 #define N_PCH_PCIE_CFG_PCIEPMECTL_L1LTRTLV 4
381 #define V_PCH_PCIE_CFG_PCIEPMECTL_L1LTRTLV 0x32
382 #define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0
383
384 #define R_PCH_PCIE_CFG_PCIEPMECTL2 0x424
385 #define B_PCH_PCIE_CFG_PCIEPMECTL2_CPMCSRE BIT27
386 #define B_PCH_PCIE_CFG_PCIEPMECTL2_CPGEXH BIT14
387 #define N_PCH_PCIE_CFG_PCIEPMECTL2_CPGEXH_OFFSET 14
388 #define B_PCH_PCIE_CFG_PCIEPMECTL2_CPGEXH_MASK (BIT14 | BIT15)
389 #define V_PCH_PCIE_CFG_PCIEPMECTL2_CPGEXH_5US 0x1
390 #define B_PCH_PCIE_CFG_PCIEPMECTL2_CPGENH BIT12
391 #define N_PCH_PCIE_CFG_PCIEPMECTL2_CPGENH_OFFSET 12
392 #define B_PCH_PCIE_CFG_PCIEPMECTL2_CPGENH_MASK (BIT12 | BIT13)
393 #define B_PCH_PCIE_CFG_PCIEPMECTL2_PHYCLPGE BIT11
394 #define B_PCH_PCIE_CFG_PCIEPMECTL2_FDCPGE BIT8
395 #define B_PCH_PCIE_CFG_PCIEPMECTL2_DETSCPGE BIT7
396 #define B_PCH_PCIE_CFG_PCIEPMECTL2_L23RDYSCPGE BIT6
397 #define B_PCH_PCIE_CFG_PCIEPMECTL2_DISSCPGE BIT5
398 #define B_PCH_PCIE_CFG_PCIEPMECTL2_L1SCPGE BIT4
399
400 #define R_PCH_PCIE_CFG_PCE 0x428
401 #define B_PCH_PCIE_CFG_PCE_HAE BIT5
402 #define B_PCH_PCIE_CFG_PCE_SE BIT3
403 #define B_PCH_PCIE_CFG_PCE_PMCRE BIT0
404
405 #define R_PCH_PCIE_CFG_PGCBCTL1 0x42C
406
407 #define R_PCH_PCIE_CFG_PCIEPMECTL3 0x434
408 #define B_PCH_PCIE_CFG_PCIEPMECTL3_L1PGAUTOPGEN BIT4
409 #define B_PCH_PCIE_CFG_PCIEPMECTL3_OSCCGH BIT2
410 #define B_PCH_PCIE_CFG_PCIEPMECTL3_OSCCGH_OFFSET 2
411 #define B_PCH_PCIE_CFG_PCIEPMECTL3_OSCCGH_MASK (BIT3 | BIT2)
412 #define V_PCH_PCIE_CFG_PCIEPMECTL3_OSCCGH_1US 1
413 #define B_PCH_PCIE_CFG_PCIEPMECTL3_PMREQCPGEXH BIT0
414 #define B_PCH_PCIE_CFG_PCIEPMECTL3_PMREQCPGEXH_MASK 0x3
415 #define B_PCH_PCIE_CFG_PCIEPMECTL3_PMREQCPGEXH_OFFSET 0
416 #define V_PCH_PCIE_CFG_PCIEPMECTL3_PMREQCPGEXH 0x1
417
418 #define R_PCH_PCIE_CFG_RTPCL2 0x458
419 #define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL3PL 0x3F000
420 #define B_PCH_PCIE_CFG_RTPCL2_RTPRECL3PL6 0xFC0
421 #define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL2PL5 0x3F
422
423 #define R_PCH_PCIE_CFG_RTPCL3 0x45C
424 #define B_PCH_PCIE_CFG_RTPCL3_RTPRECL7 0x3F000000
425 #define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL6 0xFC0000
426 #define B_PCH_PCIE_CFG_RTPCL3_RTPRECL6 0x3F000
427 #define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL5 0xFC0
428 #define B_PCH_PCIE_CFG_RTPCL3_RTPRECL5PL10 0x3F
429
430 #define R_PCH_PCIE_CFG_RTPCL4 0x460
431 #define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL9 0x3F000000
432 #define B_PCH_PCIE_CFG_RTPCL4_RTPRECL9 0xFC0000
433 #define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL8 0x3F000
434 #define B_PCH_PCIE_CFG_RTPCL4_RTPRECL8 0xFC0
435 #define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL7 0x3F
436
437 #define R_PCH_PCIE_CFG_LTCO2 0x474
438 #define B_PCH_PCIE_CFG_LTCO2_L3TCOE BIT25
439 #define B_PCH_PCIE_CFG_LTCO2_L2TCOE BIT24
440 #define B_PCH_PCIE_CFG_LTCO2_L3TPOSTCO 0xFC0000
441 #define B_PCH_PCIE_CFG_LTCO2_L3TPRECO 0x3F000
442 #define B_PCH_PCIE_CFG_LTCO2_L2TPOSTCO 0xFC0
443 #define B_PCH_PCIE_CFG_LTCO2_L2TPRECO 0x3F
444
445 #define R_PCH_PCIE_CFG_G3L0SCTL 0x478
446 #define B_PCH_PCIE_CFG_G3L0SCTL_G3UCNFTS 0x0000FF00
447 #define B_PCH_PCIE_CFG_G3L0SCTL_G3CCNFTS 0x000000FF
448
449 #define R_PCH_PCIE_CFG_GDR 0x690
450 #define B_PCH_PCIE_CFG_GDR_GPIOALD BIT10
451
452 #define R_PCH_PCIE_ACGR3S2 0xC50
453 #define B_PCH_PCIE_ACGR3S2_G5EBM BIT20
454 #define B_PCH_PCIE_ACGR3S2_G4EBM BIT9
455 #define B_PCH_PCIE_ACGR3S2_G3EBM BIT8
456 #define B_PCH_PCIE_ACGR3S2_G2EBM BIT7
457 #define B_PCH_PCIE_ACGR3S2_G1EBM BIT6
458 #define B_PCH_PCIE_ACGR3S2_SRT BIT5
459
460 #define R_PCH_PCIE_CFG_VNNREMCTL 0xC70
461 #define B_PCH_PCIE_CFG_VNNREMCTL_LRSLFVNNRE (BIT1 | BIT0)
462 #define V_PCH_PCIE_CFG_VNNREMCTL_LRSLFVNNRE_4_OSC_CLK 0x0
463 #define V_PCH_PCIE_CFG_VNNREMCTL_LRSLFVNNRE_8_OSC_CLK 0x1
464 #define V_PCH_PCIE_CFG_VNNREMCTL_LRSLFVNNRE_16_OSC_CLK 0x2
465 #define V_PCH_PCIE_CFG_VNNREMCTL_LRSLFVNNRE_32_OSC_CLK 0x3
466 #define B_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE (BIT3 | BIT2)
467 #define N_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE 2
468 #define V_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE_8_OSC_CLK 0x0
469 #define V_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE_16_OSC_CLK 0x1
470 #define V_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE_32_OSC_CLK 0x2
471 #define V_PCH_PCIE_CFG_VNNREMCTL_ISPLFVNNRE_64_OSC_CLK 0x3
472 #define B_PCH_PCIE_CFG_VNNREMCTL_LDVNNRE BIT4
473 #define B_PCH_PCIE_CFG_VNNREMCTL_RTD3VNNRE BIT5
474 #define B_PCH_PCIE_CFG_VNNREMCTL_DNPVNNRE BIT6
475 #define B_PCH_PCIE_CFG_VNNREMCTL_HPVNNRE BIT7
476 #define B_PCH_PCIE_CFG_VNNREMCTL_FDVNNRE BIT8
477
478 #define R_PCH_PCIE_CFG_VNNRSNRC1 0xC74
479
480 #define R_PCH_PCIE_AECR1G3 0xC80
481 #define B_PCH_PCIE_AECR1G3_DTCGCM BIT14
482 #define B_PCH_PCIE_AECR1G3_TPSE BIT10
483 #define B_PCH_PCIE_AECR1G3_L1OFFRDYHEWT BIT7
484 #define B_PCH_PCIE_AECR1G3_L1OFFRDYHEWTEN BIT6
485
486 #define R_PCH_PCIE_CFG_EINJCTL 0xCA8
487 #define B_PCH_PCIE_CFG_EINJCTL_EINJDIS BIT0
488
489 #define R_PCH_PCIE_RXMC1 0xC90
490 #define B_PCH_PCIE_RXMC1_MSRVS BIT26
491 #define B_PCH_PCIE_RXMC1_MSRVS_OFFSET 26
492 #define B_PCH_PCIE_RXMC1_MSRVS_MASK 0xFC000000
493 #define V_PCH_PCIE_RXMC1_MSRVS 0x13
494 #define B_PCH_PCIE_RXMC1_MSRTS BIT20
495 #define B_PCH_PCIE_RXMC1_MSRTS_OFFSET 20
496 #define B_PCH_PCIE_RXMC1_MSRTS_MASK 0x3F00000
497 #define V_PCH_PCIE_RXMC1_MSRTS 0x3F
498 #define B_PCH_PCIE_RXMC1_TMSLOP BIT13
499 #define B_PCH_PCIE_RXMC1_TMSLOP_OFFSET 13
500 #define B_PCH_PCIE_RXMC1_TMSLOP_MASK 0x6000
501 #define V_PCH_PCIE_RXMC1_TMSLOP 0x1
502 #define B_PCH_PCIE_RXMC1_VMSLOP BIT11
503 #define B_PCH_PCIE_RXMC1_VMSLOP_OFFSET 11
504 #define B_PCH_PCIE_RXMC1_VMSLOP_MASK 0x1800
505 #define V_PCH_PCIE_RXMC1_VMSLOP 0x1
506 #define B_PCH_PCIE_RXMC1_MSRM BIT9
507 #define B_PCH_PCIE_RXMC1_MMNOLS BIT4
508 #define B_PCH_PCIE_RXMC1_MMNOLS_OFFSET 4
509 #define B_PCH_PCIE_RXMC1_MMNOLS_MASK 0x1F0
510 #define V_PCH_PCIE_RXMC1_MMNOLS 0x1
511 #define B_PCH_PCIE_RXMC1_MVS BIT3
512 #define B_PCH_PCIE_RXMC1_MILRTS BIT2
513 #define B_PCH_PCIE_RXMC1_MIUDVMS BIT1
514 #define B_PCH_PCIE_RXMC1_MIESS BIT0
515
516 #define R_PCH_PCIE_RXMC2 0xC94
517 #define B_PCH_PCIE_RXMC2_MNOTSS BIT19
518 #define B_PCH_PCIE_RXMC2_MNOTSS_OFFSET 19
519 #define B_PCH_PCIE_RXMC2_MNOTSS_MASK 0x1F80000
520 #define V_PCH_PCIE_RXMC2_MNOTSS 0x20
521 #define B_PCH_PCIE_RXMC2_MMTOS BIT13
522 #define B_PCH_PCIE_RXMC2_MMTOS_OFFSET 13
523 #define B_PCH_PCIE_RXMC2_MMTOS_MASK 0x7E000
524 #define V_PCH_PCIE_RXMC2_MMTOS 0x1C
525 #define B_PCH_PCIE_RXMC2_MNOVSS BIT6
526 #define B_PCH_PCIE_RXMC2_MNOVSS_OFFSET 6
527 #define B_PCH_PCIE_RXMC2_MNOVSS_MASK 0x1FC0
528 #define V_PCH_PCIE_RXMC2_MNOVSS 0x1C
529 #define B_PCH_PCIE_RXMC2_MMVOS BIT0
530 #define B_PCH_PCIE_RXMC2_MMVOS_OFFSET 0
531 #define B_PCH_PCIE_RXMC2_MMVOS_MASK 0x3F
532 #define V_PCH_PCIE_RXMC2_MMVOS 0x0
533
534 #define R_PCH_PCIE_PL16MPCPS 0xEE0
535 #define B_PCH_PCIE_PL16MPCPS_MARGINDRISW BIT0
536 //
537 // PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
538 //
539 #define R_SPX_PCR_PCD 0 ///< Port configuration and disable
540 #define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
541 #define B_SPX_PCR_PCD_RP1CH BIT3 ///< Port 1 config hide
542 #define B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///< Port 2 Function Number
543 #define B_SPX_PCR_PCD_RP2CH BIT7 ///< Port 2 config hide
544 #define B_SPX_PCR_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///< Port 3 Function Number
545 #define B_SPX_PCR_PCD_RP3CH BIT11 ///< Port 3 config hide
546 #define B_SPX_PCR_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///< Port 4 Function Number
547 #define B_SPX_PCR_PCD_RP4CH BIT15 ///< Port 4 config hide
548 #define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
549 #define B_SPX_PCR_PCD_P1D BIT16 ///< Port 1 disable
550 #define B_SPX_PCR_PCD_P2D BIT17 ///< Port 2 disable
551 #define B_SPX_PCR_PCD_P3D BIT18 ///< Port 3 disable
552 #define B_SPX_PCR_PCD_P4D BIT19 ///< Port 4 disable
553 #define B_SPX_PCR_PCD_SRL BIT31 ///< Secured Register Lock
554
555 #define R_SPX_PCR_PCIEHBP 0x0004 ///< PCI Express high-speed bypass
556 #define B_SPX_PCR_PCIEHBP_PCIEHBPME BIT0 ///< PCIe HBP mode enable
557 #define B_SPX_PCR_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///< PCIe gen mode override
558 #define B_SPX_PCR_PCIEHBP_PCIETIL0O BIT3 ///< PCIe transmitter-in-L0 override
559 #define B_SPX_PCR_PCIEHBP_PCIERIL0O BIT4 ///< PCIe receiver-in-L0 override
560 #define B_SPX_PCR_PCIEHBP_PCIELRO BIT5 ///< PCIe link recovery override
561 #define B_SPX_PCR_PCIEHBP_PCIELDO BIT6 ///< PCIe link down override
562 #define B_SPX_PCR_PCIEHBP_PCIESSM BIT7 ///< PCIe SKP suppression mode
563 #define B_SPX_PCR_PCIEHBP_PCIESST BIT8 ///< PCIe suppress SKP transmission
564 #define B_SPX_PCR_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///< PCIe HBP port select
565 #define B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14) ///< CRC select
566 #define B_SPX_PCR_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///< PCIe HBP CRC
567
568 #define R_SPX_PCR_IMRAMBL 0x10 ///< IMR access memory base and limit
569 #define B_SPX_PCR_IMRAMBL_RS3BN 0x000000FF ///< Bus Number for RS3
570 #define N_SPX_PCR_IMRAMBL_RS3BN 0
571 #define B_SPX_PCR_IMRAMBL_IAMB 0x000FFF00 ///< IMR access memory base, lower bits
572 #define N_SPX_PCR_IMRAMBL_IAMB 8
573 #define B_SPX_PCR_IMRAMBL_IAML 0xFFF00000 ///< IMR access memory limit, lower bits
574 #define N_SPX_PCR_IMRAMBL_IAML 20
575
576 #define R_SPX_PCR_IMRAMBU32 0x14 ///< IMR access memory base, upper bits
577
578 #define R_SPX_PCR_IMRAMLU32 0x18 ///< IMR access memory limit, upper bits
579
580 #define R_SPX_PCR_IMRAMLE 0x1C ///< IMR access memory lock & enable
581 #define B_SPX_PCR_IMRAMLE_IAE1 BIT0 ///< IMR access enable for port 1 of given controller
582 #define B_SPX_PCR_IMRAMLE_IAE2 BIT1 ///< IMR access enable for port 1 of given controller
583 #define B_SPX_PCR_IMRAMLE_IAE3 BIT2 ///< IMR access enable for port 1 of given controller
584 #define B_SPX_PCR_IMRAMLE_IAE4 BIT3 ///< IMR access enable for port 1 of given controller
585 #define B_SPX_PCR_IMRAMLE_SRL BIT31 ///< IMR register lock
586
587 #define R_SPX_SIP16_PCR_PCD 0x3E00 ///< Port configuration and disable
588
589 //
590 // ICC PCR (PID: ICC)
591 //
592 #define R_ICC_PCR_TMCSRCCLK 0x1000 ///< Timing Control SRC Clock Register
593 #define R_ICC_PCR_TMCSRCCLK2 0x1004 ///< Timing Control SRC Clock Register 2
594 #define R_ICC_PCR_MSKCKRQ 0x100C ///< Mask Control CLKREQ
595 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieSmiDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Macros | Typedefs | Enumerations
PchPcieSmiDispatch.h File Reference

APIs of PCH PCIE SMI Dispatch Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL
Interface structure for PCH PCIE SMIs Dispatch Protocol The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs. More...

Macros

#define PCH_PCIE_SMI_DISPATCH_REVISION 1
PCH PCIE SMI dispatch revision number. More...

Typedefs

typedef VOID(* | PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle, IN PCH_PCIE_SMI_RP_CONTEXT *RpContext)
Callback function for an PCH PCIE RP SMI handler dispatch. More...
typedef EFI_STATUS(* | PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, IN UINTN RpIndex, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH PCIERP SMI events. More...
typedef EFI_STATUS(* | PCH_PCIE_SMI_DISPATCH_UNREGISTER) (IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent PCIE SMM driver. More...

Enumerations

enum PCIE_COMBINED_RPINDEX

Detailed Description

APIs of PCH PCIE SMI Dispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieSmiDispatch.h.

Macro Definition Documentation

◆ PCH_PCIE_SMI_DISPATCH_REVISION

#define PCH_PCIE_SMI_DISPATCH_REVISION 1

PCH PCIE SMI dispatch revision number.

Revision 1: Initial version

Definition at line 192 of file PchPcieSmiDispatch.h.

Typedef Documentation

◆ PCH_PCIE_SMI_DISPATCH_UNREGISTER

typedef EFI_STATUS( * PCH_PCIE_SMI_DISPATCH_UNREGISTER) (IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

Unregister a child SMI source dispatch function with a parent PCIE SMM driver.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchHandle | Handle of dispatch function to deregister.
Return values
EFI_SUCCESS | The dispatch function has been successfully unregistered and the SMI source has been disabled if there are no other registered child dispatch functions for this SMI source.
EFI_INVALID_PARAMETER | Handle is invalid.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 149 of file PchPcieSmiDispatch.h.

◆ PCH_PCIE_SMI_RP_DISPATCH_CALLBACK

typedef VOID( * PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle, IN PCH_PCIE_SMI_RP_CONTEXT *RpContext)

Callback function for an PCH PCIE RP SMI handler dispatch.

Parameters
[in] | DispatchHandle | The unique handle assigned to this handler by register function.
[in] | RpContext | Pointer of PCH PCIE Root Port context.

Definition at line 103 of file PchPcieSmiDispatch.h.

◆ PCH_PCIE_SMI_RP_DISPATCH_REGISTER

typedef EFI_STATUS( * PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, IN UINTN RpIndex, OUT EFI_HANDLE *DispatchHandle)

Register a child SMI source dispatch function for PCH PCIERP SMI events.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchFunction | Pointer to dispatch function to be invoked for this SMI source
[in] | RpIndex | Refer PCIE_COMBINED_RPINDEX for PCH RP index and CPU RP index. 0: RP1, 1: RP2, n: RP(N+1)
[out] | DispatchHandle | Handle of dispatch function, for when interfacing with the parent SMM driver.
Return values
EFI_SUCCESS | The dispatch function has been successfully registered and the SMI source has been enabled.
EFI_DEVICE_ERROR | The driver was unable to enable the SMI source.
EFI_OUT_OF_RESOURCES | Not enough memory (system or SMM) to manage this child.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 127 of file PchPcieSmiDispatch.h.

Enumeration Type Documentation

◆ PCIE_COMBINED_RPINDEX

enum PCIE_COMBINED_RPINDEX
Enumerator
CpuRpIndex0

Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silicon generations and series.

Do not assume that PCH port 0 will be always encoded by 0. Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style to be forward-compatible

Definition at line 48 of file PchPcieSmiDispatch.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieSmiDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchPcieSmiDispatch.h
Go to the documentation of this file.
1 /** @file
2 APIs of PCH PCIE SMI Dispatch Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
36 #define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gPchPcieSmiDispatchProtocolGuid;
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL;
47
48 typedef enum {
49 PchRpIndex0 = 0,
50 PchRpIndex1 = 1,
51 PchRpIndex2 = 2,
52 PchRpIndex3 = 3,
53 PchRpIndex4 = 4,
54 PchRpIndex5 = 5,
55 PchRpIndex6 = 6,
56 PchRpIndex7 = 7,
57 PchRpIndex8 = 8,
58 PchRpIndex9 = 9,
59 PchRpIndex10 = 10,
60 PchRpIndex11 = 11,
61 PchRpIndex12 = 12,
62 PchRpIndex13 = 13,
63 PchRpIndex14 = 14,
64 PchRpIndex15 = 15,
65 PchRpIndex16 = 16,
66 PchRpIndex17 = 17,
67 PchRpIndex18 = 18,
68 PchRpIndex19 = 19,
69 PchRpIndex20 = 20,
70 PchRpIndex21 = 21,
71 PchRpIndex22 = 22,
72 PchRpIndex23 = 23,
73 /**
74 Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
75 silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
76 Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style to be forward-compatible
77 **/
78 CpuRpIndex0 = 0x40,
79 CpuRpIndex1 = 0x41,
80 CpuRpIndex2 = 0x42,
81 CpuRpIndex3 = 0x43
82 } PCIE_COMBINED_RPINDEX;
83
84 //
85 // Member functions
86 //
87
88 typedef struct {
89 UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1)
90 UINT8 BusNum; ///< Root port pci bus number
91 UINT8 DevNum; ///< Root port pci device number
92 UINT8 FuncNum; ///< Root port pci function number
93 } PCH_PCIE_SMI_RP_CONTEXT;
94
95 /**
96 Callback function for an PCH PCIE RP SMI handler dispatch.
97
98 @param[in] DispatchHandle The unique handle assigned to this handler by register function.
99 @param[in] RpContext Pointer of PCH PCIE Root Port context.
100
101 **/
102 typedef
103 VOID
104 (EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (
105 IN EFI_HANDLE DispatchHandle,
106 IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
107 );
108
109 /**
110 Register a child SMI source dispatch function for PCH PCIERP SMI events.
111
112 @param[in] This Protocol instance pointer.
113 @param[in] DispatchFunction Pointer to dispatch function to be invoked for
114 this SMI source
115 @param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for PCH RP index and CPU RP index.
116 0: RP1, 1: RP2, n: RP(N+1)
117 @param[out] DispatchHandle Handle of dispatch function, for when interfacing
118 with the parent SMM driver.
119
120 @retval EFI_SUCCESS The dispatch function has been successfully
121 registered and the SMI source has been enabled.
122 @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
123 @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
124 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
125 **/
126 typedef
127 EFI_STATUS
128 (EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (
129 IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
130 IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction,
131 IN UINTN RpIndex,
132 OUT EFI_HANDLE *DispatchHandle
133 );
134
135 /**
136 Unregister a child SMI source dispatch function with a parent PCIE SMM driver
137
138 @param[in] This Protocol instance pointer.
139 @param[in] DispatchHandle Handle of dispatch function to deregister.
140
141 @retval EFI_SUCCESS The dispatch function has been successfully
142 unregistered and the SMI source has been disabled
143 if there are no other registered child dispatch
144 functions for this SMI source.
145 @retval EFI_INVALID_PARAMETER Handle is invalid.
146 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
147 **/
148 typedef
149 EFI_STATUS
150 (EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) (
151 IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
152 IN EFI_HANDLE DispatchHandle
153 );
154
155 /**
156 Interface structure for PCH PCIE SMIs Dispatch Protocol
157 The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs.
158 It contains SMI types of HotPlug, LinkActive, and Link EQ.
159 **/
160 struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL {
161 /**
162 This member specifies the revision of this structure. This field is used to
163 indicate backwards compatible changes to the protocol.
164 **/
165 UINT8 Revision;
166 /**
167 Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.
168 **/
169 PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister;
170 /**
171 PcieRpXHotPlug
172 The event is triggered when PCIE root port Hot-Plug Presence Detect.
173 **/
174 PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister;
175 /**
176 PcieRpXLinkActive
177 The event is triggered when Hot-Plug Link Active State Changed.
178 **/
179 PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister;
180 /**
181 PcieRpXLinkEq
182 The event is triggered when Device Requests Software Link Equalization.
183 **/
184 PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister;
185 };
186
187 /**
188 PCH PCIE SMI dispatch revision number
189
190 Revision 1: Initial version
191 **/
192 #define PCH_PCIE_SMI_DISPATCH_REVISION 1
193
194 #endif
_PCH_PCIE_SMI_DISPATCH_PROTOCOL::LinkEqRegister
PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister
PcieRpXLinkEq The event is triggered when Device Requests Software Link Equalization.
Definition: PchPcieSmiDispatch.h:184
_PCH_PCIE_SMI_DISPATCH_PROTOCOL::LinkActiveRegister
PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister
PcieRpXLinkActive The event is triggered when Hot-Plug Link Active State Changed.
Definition: PchPcieSmiDispatch.h:179
CpuRpIndex0
@ CpuRpIndex0
Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between silico...
Definition: PchPcieSmiDispatch.h:78
PCIE_COMBINED_RPINDEX
PCIE_COMBINED_RPINDEX
Definition: PchPcieSmiDispatch.h:48
_PCH_PCIE_SMI_DISPATCH_PROTOCOL::UnRegister
PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.
Definition: PchPcieSmiDispatch.h:169
_PCH_PCIE_SMI_DISPATCH_PROTOCOL
Interface structure for PCH PCIE SMIs Dispatch Protocol The PCH PCIE SMI DISPATCH PROTOCOL provides t...
Definition: PchPcieSmiDispatch.h:160
PCH_PCIE_SMI_DISPATCH_UNREGISTER
EFI_STATUS(* PCH_PCIE_SMI_DISPATCH_UNREGISTER)(IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent PCIE SMM driver.
Definition: PchPcieSmiDispatch.h:150
_PCH_PCIE_SMI_DISPATCH_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: PchPcieSmiDispatch.h:165
PCH_PCIE_SMI_RP_DISPATCH_REGISTER
EFI_STATUS(* PCH_PCIE_SMI_RP_DISPATCH_REGISTER)(IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, IN UINTN RpIndex, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH PCIERP SMI events.
Definition: PchPcieSmiDispatch.h:128
PCH_PCIE_SMI_RP_DISPATCH_CALLBACK
VOID(* PCH_PCIE_SMI_RP_DISPATCH_CALLBACK)(IN EFI_HANDLE DispatchHandle, IN PCH_PCIE_SMI_RP_CONTEXT *RpContext)
Callback function for an PCH PCIE RP SMI handler dispatch.
Definition: PchPcieSmiDispatch.h:104
_PCH_PCIE_SMI_DISPATCH_PROTOCOL::HotPlugRegister
PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister
PcieRpXHotPlug The event is triggered when PCIE root port Hot-Plug Presence Detect.
Definition: PchPcieSmiDispatch.h:174
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieStorageDetectHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
PchPcieStorageDetectHob.h File Reference

Definitions required to create PcieStorageInfoHob. More...

#include "PchLimits.h"
Include dependency graph for PchPcieStorageDetectHob.h:

Go to the source code of this file.

Detailed Description

Definitions required to create PcieStorageInfoHob.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcieStorageDetectHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieStorageDetectHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PchPcieStorageDetectHob.h
Go to the documentation of this file.
1 /** @file
2
3 Definitions required to create PcieStorageInfoHob
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2016 - 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _PCH_PCIE_STORAGE_DETECT_HOB_
38 #define _PCH_PCIE_STORAGE_DETECT_HOB_
39
40 #include "PchLimits.h"
41
42 #define PCIE_STORAGE_INFO_HOB_REVISION 1
43
44 extern EFI_GUID gPchPcieStorageDetectHobGuid;
45
46 typedef enum {
47 RstLinkWidthX1 = 1,
48 RstLinkWidthX2 = 2,
49 RstLinkWidthX4 = 4
50 } RST_LINK_WIDTH;
51
52 //
53 // Stores information about connected PCIe storage devices used later by BIOS setup and RST remapping
54 //
55 #pragma pack(1)
56 typedef struct {
57 UINT8 Revision;
58
59 //
60 // Stores the number of root ports occupied by a connected storage device, values from RST_LINK_WIDTH are supported
61 //
62 UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS];
63
64 //
65 // Programming interface value for a given device, 0x02 - NVMe or RAID, 0x1 - AHCI storage, 0x0 - no device connected
66 //
67 UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS];
68
69 //
70 // Stores information about cycle router number under a given PCIe controller
71 //
72 UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS];
73 } PCIE_STORAGE_INFO_HOB;
74 #pragma pack()
75 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcrLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Macros | Functions
PchPcrLib.h File Reference

Header file for PchPcrLib. More...

#include <PchReservedResources.h>
Include dependency graph for PchPcrLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
Definition for PCR address The PCR address is used to the PCR MMIO programming. More...
#define | PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
PCH PCR boot script accessing macro Those macros are only available for DXE phase.

Functions

UINT32 | PchPcrRead32 (IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register. More...
UINT16 | PchPcrRead16 (IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register. More...
UINT8 | PchPcrRead8 (IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register. More...
UINT32 | PchPcrWrite32 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 InData)
Write PCR register. More...
UINT16 | PchPcrWrite16 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT16 InData)
Write PCR register. More...
UINT8 | PchPcrWrite8 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT8 InData)
Write PCR register. More...
UINT32 | PchPcrAndThenOr32 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write PCR register. More...
UINT32 | PchPcrAndThenOr32WithReadback (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write PCR register and read back. More...
UINT16 | PchPcrAndThenOr16 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT16 AndData, IN UINT16 OrData)
Write PCR register. More...
UINT8 | PchPcrAndThenOr8 (IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT8 AndData, IN UINT8 OrData)
Write PCR register. More...
PCH_SBI_PID | PchPcrGetPid (PCH_IP_PID_ENUM IpEnum)
Get PCH IP PID number. More...
EFI_STATUS | SetInterruptPin (IN PCH_DEVICE_SELECTION DeviceSel, IN UINT8 InterruptPin)
Configure device interrupts. More...

Detailed Description

Header file for PchPcrLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPcrLib.h.

Macro Definition Documentation

◆ PCH_PCR_ADDRESS

#define PCH_PCR_ADDRESS | ( | Pid,
 |  | Offset
 | ) | (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))

Definition for PCR address The PCR address is used to the PCR MMIO programming.

SBREG_BAR_20BITADDRESS is configured by SoC

SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing. +------------------------------------------------------------------------------------------—+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] | +-------------—+--------------------—+--------------—+-------------------------------—+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] | +------------------------------------------------------------------------------------------—+

SBREG_BAR_20BITADDRESS=0 +------------------------------------------------------------------------------------------—+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] | +-------------—+--------------------—+--------------—+-------------------------------—+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] | +------------------------------------------------------------------------------------------—+

Definition at line 60 of file PchPcrLib.h.

Function Documentation

◆ PchPcrAndThenOr16()

UINT16 PchPcrAndThenOr16 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT16 | AndData,
 |  | IN UINT16 | OrData
 | ) |  |

Write PCR register.

It programs PCR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ PchPcrAndThenOr32()

UINT32 PchPcrAndThenOr32 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | AndData,
 |  | IN UINT32 | OrData
 | ) |  |

Write PCR register.

It programs PCR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ PchPcrAndThenOr32WithReadback()

UINT32 PchPcrAndThenOr32WithReadback | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | AndData,
 |  | IN UINT32 | OrData
 | ) |  |

Write PCR register and read back.

The read back ensures the PCR cycle is completed before next operation. It programs PCR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT32 Value read back from the register

◆ PchPcrAndThenOr8()

UINT8 PchPcrAndThenOr8 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT8 | AndData,
 |  | IN UINT8 | OrData
 | ) |  |

Write PCR register.

It programs PCR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | AndData | AND Data. Must be the same size as Size parameter.
[in] | OrData | OR Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register

◆ PchPcrGetPid()

PCH_SBI_PID PchPcrGetPid ( PCH_IP_PID_ENUM IpEnum )

Get PCH IP PID number.

Parameters
[in] IpEnum PCH IP in PCH_IP_PID_ENUM
Return values
0 PID of this IP is not supported !0 PID of the IP.

◆ PchPcrRead16()

UINT16 PchPcrRead16 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset
 | ) |  |

Read PCR register.

It returns PCR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT16 PCR register value.

◆ PchPcrRead32()

UINT32 PchPcrRead32 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset
 | ) |  |

Read PCR register.

It returns PCR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT32 PCR register value.

◆ PchPcrRead8()

UINT8 PchPcrRead8 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset
 | ) |  |

Read PCR register.

It returns PCR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of this Port ID
Return values
UINT8 PCR register value

◆ PchPcrWrite16()

UINT16 PchPcrWrite16 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT16 | InData
 | ) |  |

Write PCR register.

It programs PCR register and size in 2bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT16 Value written to register

◆ PchPcrWrite32()

UINT32 PchPcrWrite32 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | InData
 | ) |  |

Write PCR register.

It programs PCR register and size in 4bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT32 Value written to register

◆ PchPcrWrite8()

UINT8 PchPcrWrite8 | ( | IN PCH_SBI_PID | Pid,
 |  | IN UINT32 | Offset,
 |  | IN UINT8 | InData
 | ) |  |

Write PCR register.

It programs PCR register and size in 1bytes. The Offset should not exceed 0xFFFF and must be aligned with size.

Parameters
[in] | Pid | Port ID
[in] | Offset | Register offset of Port ID.
[in] | Data | Input Data. Must be the same size as Size parameter.
Return values
UINT8 Value written to register

◆ SetInterruptPin()

EFI_STATUS SetInterruptPin | ( | IN PCH_DEVICE_SELECTION | DeviceSel,
 |  | IN UINT8 | InterruptPin
 | ) |  |

Configure device interrupts.

Parameters
[in] | DeviceSel | Device to be configured
[in] | InterruptPin | Interrupt Pin to set
Return values
EFI_STATUS | Operation Status
EFI_INVALID_PARAMETER | Wrong DeviceSel parameter
EFI_DEVICE_ERROR | Not able to write data
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcrLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PchPcrLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PchPcrLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PCR_LIB_H_
36 #define _PCH_PCR_LIB_H_
37
38 #include <PchReservedResources.h>
39
40 /**
41 Definition for PCR address
42 The PCR address is used to the PCR MMIO programming
43
44 SBREG_BAR_20BITADDRESS is configured by SoC
45
46 SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
47 +---------------------------------------------------------------------------------------------+
48 | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
49 +----------------+-----------------------+-----------------+----------------------------------+
50 | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
51 +---------------------------------------------------------------------------------------------+
52
53 SBREG_BAR_20BITADDRESS=0
54 +---------------------------------------------------------------------------------------------+
55 | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
56 +----------------+-----------------------+-----------------+----------------------------------+
57 | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
58 +---------------------------------------------------------------------------------------------+
59 **/
60 #define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
61
62 /**
63 PCH PCR boot script accessing macro
64 Those macros are only available for DXE phase.
65 **/
66 #define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
67 S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
68
69 #define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
70 S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
71
72 #define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
73 S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
74
75 typedef UINT8 PCH_SBI_PID;
76
77 /**
78 Read PCR register.
79 It returns PCR register and size in 4bytes.
80 The Offset should not exceed 0xFFFF and must be aligned with size.
81
82 @param[in] Pid Port ID
83 @param[in] Offset Register offset of this Port ID
84
85 @retval UINT32 PCR register value.
86 **/
87 UINT32
88 PchPcrRead32 (
89 IN PCH_SBI_PID Pid,
90 IN UINT32 Offset
91 );
92
93 /**
94 Read PCR register.
95 It returns PCR register and size in 2bytes.
96 The Offset should not exceed 0xFFFF and must be aligned with size.
97
98 @param[in] Pid Port ID
99 @param[in] Offset Register offset of this Port ID
100
101 @retval UINT16 PCR register value.
102 **/
103 UINT16
104 PchPcrRead16 (
105 IN PCH_SBI_PID Pid,
106 IN UINT32 Offset
107 );
108
109 /**
110 Read PCR register.
111 It returns PCR register and size in 1bytes.
112 The Offset should not exceed 0xFFFF and must be aligned with size.
113
114 @param[in] Pid Port ID
115 @param[in] Offset Register offset of this Port ID
116
117 @retval UINT8 PCR register value
118 **/
119 UINT8
120 PchPcrRead8 (
121 IN PCH_SBI_PID Pid,
122 IN UINT32 Offset
123 );
124
125 /**
126 Write PCR register.
127 It programs PCR register and size in 4bytes.
128 The Offset should not exceed 0xFFFF and must be aligned with size.
129
130 @param[in] Pid Port ID
131 @param[in] Offset Register offset of Port ID.
132 @param[in] Data Input Data. Must be the same size as Size parameter.
133
134 @retval UINT32 Value written to register
135 **/
136 UINT32
137 PchPcrWrite32 (
138 IN PCH_SBI_PID Pid,
139 IN UINT32 Offset,
140 IN UINT32 InData
141 );
142
143 /**
144 Write PCR register.
145 It programs PCR register and size in 2bytes.
146 The Offset should not exceed 0xFFFF and must be aligned with size.
147
148 @param[in] Pid Port ID
149 @param[in] Offset Register offset of Port ID.
150 @param[in] Data Input Data. Must be the same size as Size parameter.
151
152 @retval UINT16 Value written to register
153 **/
154 UINT16
155 PchPcrWrite16 (
156 IN PCH_SBI_PID Pid,
157 IN UINT32 Offset,
158 IN UINT16 InData
159 );
160
161 /**
162 Write PCR register.
163 It programs PCR register and size in 1bytes.
164 The Offset should not exceed 0xFFFF and must be aligned with size.
165
166 @param[in] Pid Port ID
167 @param[in] Offset Register offset of Port ID.
168 @param[in] Data Input Data. Must be the same size as Size parameter.
169
170 @retval UINT8 Value written to register
171 **/
172 UINT8
173 PchPcrWrite8 (
174 IN PCH_SBI_PID Pid,
175 IN UINT32 Offset,
176 IN UINT8 InData
177 );
178
179 /**
180 Write PCR register.
181 It programs PCR register and size in 4bytes.
182 The Offset should not exceed 0xFFFF and must be aligned with size.
183
184 @param[in] Pid Port ID
185 @param[in] Offset Register offset of Port ID.
186 @param[in] AndData AND Data. Must be the same size as Size parameter.
187 @param[in] OrData OR Data. Must be the same size as Size parameter.
188
189 @retval UINT32 Value written to register
190
191 **/
192 UINT32
193 PchPcrAndThenOr32 (
194 IN PCH_SBI_PID Pid,
195 IN UINT32 Offset,
196 IN UINT32 AndData,
197 IN UINT32 OrData
198 );
199
200 /**
201 Write PCR register and read back.
202 The read back ensures the PCR cycle is completed before next operation.
203 It programs PCR register and size in 4bytes.
204 The Offset should not exceed 0xFFFF and must be aligned with size.
205
206 @param[in] Pid Port ID
207 @param[in] Offset Register offset of Port ID.
208 @param[in] AndData AND Data. Must be the same size as Size parameter.
209 @param[in] OrData OR Data. Must be the same size as Size parameter.
210
211 @retval UINT32 Value read back from the register
212 **/
213 UINT32
214 PchPcrAndThenOr32WithReadback (
215 IN PCH_SBI_PID Pid,
216 IN UINT32 Offset,
217 IN UINT32 AndData,
218 IN UINT32 OrData
219 );
220
221 /**
222 Write PCR register.
223 It programs PCR register and size in 2bytes.
224 The Offset should not exceed 0xFFFF and must be aligned with size.
225
226 @param[in] Pid Port ID
227 @param[in] Offset Register offset of Port ID.
228 @param[in] AndData AND Data. Must be the same size as Size parameter.
229 @param[in] OrData OR Data. Must be the same size as Size parameter.
230
231 @retval UINT16 Value written to register
232
233 **/
234 UINT16
235 PchPcrAndThenOr16 (
236 IN PCH_SBI_PID Pid,
237 IN UINT32 Offset,
238 IN UINT16 AndData,
239 IN UINT16 OrData
240 );
241
242 /**
243 Write PCR register.
244 It programs PCR register and size in 1bytes.
245 The Offset should not exceed 0xFFFF and must be aligned with size.
246
247 @param[in] Pid Port ID
248 @param[in] Offset Register offset of Port ID.
249 @param[in] AndData AND Data. Must be the same size as Size parameter.
250 @param[in] OrData OR Data. Must be the same size as Size parameter.
251
252 @retval UINT8 Value written to register
253
254 **/
255 UINT8
256 PchPcrAndThenOr8 (
257 IN PCH_SBI_PID Pid,
258 IN UINT32 Offset,
259 IN UINT8 AndData,
260 IN UINT8 OrData
261 );
262
263
264 typedef enum {
265 PchIpDmi = 1,
266 PchIpIclk,
267 } PCH_IP_PID_ENUM;
268
269 #define PCH_INVALID_PID 0
270
271 /**
272 Get PCH IP PID number
273
274 @param[in] IpEnum PCH IP in PCH_IP_PID_ENUM
275
276 @retval 0 PID of this IP is not supported
277 !0 PID of the IP.
278 **/
279 PCH_SBI_PID
280 PchPcrGetPid (
281 PCH_IP_PID_ENUM IpEnum
282 );
283
284 typedef enum {
285 PchSelectSolDevice,
286 PchSelectHeci1Device,
287 PchSelectHeci2Device,
288 PchSelectHeci3Device,
289 PchSelectHeci4Device,
290 PchSelectIderDevice,
291 PchSelectMax,
292 } PCH_DEVICE_SELECTION;
293
294 /**
295 Configure device interrupts
296
297 @param[in] DeviceSel Device to be configured
298 @param[in] InterruptPin Interrupt Pin to set
299
300 @retval EFI_STATUS Operation Status
301 @retval EFI_INVALID_PARAMETER Wrong DeviceSel parameter
302 @retval EFI_DEVICE_ERROR Not able to write data
303 */
304 EFI_STATUS
305 SetInterruptPin (
306 IN PCH_DEVICE_SELECTION DeviceSel,
307 IN UINT8 InterruptPin
308 );
309
310 #endif // _PCH_PCR_LIB_H_
PchPcrRead8
UINT8 PchPcrRead8(IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register.
PchPcrWrite32
UINT32 PchPcrWrite32(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 InData)
Write PCR register.
SetInterruptPin
EFI_STATUS SetInterruptPin(IN PCH_DEVICE_SELECTION DeviceSel, IN UINT8 InterruptPin)
Configure device interrupts.
PchPcrGetPid
PCH_SBI_PID PchPcrGetPid(PCH_IP_PID_ENUM IpEnum)
Get PCH IP PID number.
PchPcrAndThenOr32WithReadback
UINT32 PchPcrAndThenOr32WithReadback(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write PCR register and read back.
PchPcrAndThenOr8
UINT8 PchPcrAndThenOr8(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT8 AndData, IN UINT8 OrData)
Write PCR register.
PchPcrWrite8
UINT8 PchPcrWrite8(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT8 InData)
Write PCR register.
PchPcrRead16
UINT16 PchPcrRead16(IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register.
PchPcrRead32
UINT32 PchPcrRead32(IN PCH_SBI_PID Pid, IN UINT32 Offset)
Read PCR register.
PchPcrWrite16
UINT16 PchPcrWrite16(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT16 InData)
Write PCR register.
PchPcrAndThenOr16
UINT16 PchPcrAndThenOr16(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT16 AndData, IN UINT16 OrData)
Write PCR register.
PchPcrAndThenOr32
UINT32 PchPcrAndThenOr32(IN PCH_SBI_PID Pid, IN UINT32 Offset, IN UINT32 AndData, IN UINT32 OrData)
Write PCR register.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes
PchPolicy.h File Reference

Interface definition details between Pch and platform drivers during DXE phase. More...

#include <ConfigBlock.h>
#include <Library/ConfigBlockLib.h>
#include "../IncludePrivate/PchConfigHob.h"
#include <Library/HobLib.h>
Include dependency graph for PchPolicy.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_POLICY_PROTOCOL
PCH DXE Policy. More...

Detailed Description

Interface definition details between Pch and platform drivers during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicy.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchPolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details between Pch and platform drivers during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_POLICY_H_
36 #define _PCH_POLICY_H_
37
38 #include <ConfigBlock.h>
39 #include <Library/ConfigBlockLib.h>
40 //#include <PchConfigHob.h>
41 #include "../IncludePrivate/PchConfigHob.h" // To Be corrected
42 #include <Library/HobLib.h>
43
44 extern EFI_GUID gPchPolicyProtocolGuid;
45
46 #define PCH_POLICY_PROTOCOL_REVISION 1
47
48
49 /**
50 PCH DXE Policy
51
52 The PCH_POLICY_PROTOCOL producer drvier is recommended to
53 set all the PCH_POLICY_PROTOCOL size buffer zero before init any member parameter,
54 this clear step can make sure no random value for those unknown new version parameters.
55
56 Make sure to update the Revision if any change to the protocol, including the existing
57 internal structure definations.\n
58 Note: Here revision will be bumped up when adding/removing any config block under this structure.\n
59 <b>Revision 1</b>:
60 - Initial version.
61 **/
62 typedef struct {
63 CONFIG_BLOCK_TABLE_HEADER TableHeader;
64 /*
65 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
66 */
67 } PCH_POLICY_PROTOCOL;
68
69 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
PCH_POLICY_PROTOCOL
PCH DXE Policy.
Definition: PchPolicy.h:62
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicyCommon.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchPolicyCommon.h File Reference

PCH configuration based on PCH policy. More...

#include <ConfigBlock.h>
#include <UsbConfig.h>
#include <Usb2PhyConfig.h>
#include <Usb3HsioConfig.h>
#include "PchLimits.h"
#include "ConfigBlock/PchGeneralConfig.h"
#include <PchPcieRpConfig.h>
#include <IoApicConfig.h>
#include <SataConfig.h>
#include <RstConfig.h>
#include <PchDmiConfig.h>
#include <FlashProtectionConfig.h>
#include <InterruptConfig.h>
#include <HdAudioConfig.h>
#include <IshConfig.h>
#include <GbeConfig.h>
#include <TsnConfig.h>
#include "ConfigBlock/LockDownConfig.h"
#include "P2sbConfig.h"
#include <PmConfig.h>
#include <ScsConfig.h>
#include <SerialIoConfig.h>
#include <ThcConfig.h>
#include <ThermalConfig.h>
#include <EspiConfig.h>
#include <CnviConfig.h>
#include <IehConfig.h>
#include <PsfConfig.h>
#include <FusaConfig.h>
#include <FivrConfig.h>
#include <AdrConfig.h>
#include <RtcConfig.h>
#include <HybridStorageConfig.h>
#include <SpiConfig.h>
Include dependency graph for PchPolicyCommon.h:

Go to the source code of this file.

Detailed Description

PCH configuration based on PCH policy.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPolicyCommon.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicyCommon.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchPolicyCommon.h
Go to the documentation of this file.
1 /** @file
2 PCH configuration based on PCH policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_POLICY_COMMON_H_
36 #define _PCH_POLICY_COMMON_H_
37
38 #include <ConfigBlock.h>
39 #include <UsbConfig.h>
40 #include <Usb2PhyConfig.h>
41 #include <Usb3HsioConfig.h>
42
43 #include "PchLimits.h"
44 #include "ConfigBlock/PchGeneralConfig.h"
45 #include <PchPcieRpConfig.h>
46 #include <IoApicConfig.h>
47 #include <SataConfig.h>
48 #include <RstConfig.h>
49 #include <PchDmiConfig.h>
50 #include <FlashProtectionConfig.h>
51 #include <InterruptConfig.h>
52 #include <HdAudioConfig.h>
53 #include <IshConfig.h>
54 #include <GbeConfig.h>
55 #include <TsnConfig.h>
56 #include "ConfigBlock/LockDownConfig.h"
57 #include "P2sbConfig.h"
58 #include <PmConfig.h>
59 #include <ScsConfig.h>
60 #include <SerialIoConfig.h>
61 #include <ThcConfig.h>
62 #include <ThermalConfig.h>
63 #include <EspiConfig.h>
64 #include <CnviConfig.h>
65 #include <IehConfig.h>
66 #include <PsfConfig.h>
67 #include <FusaConfig.h>
68 #include <FivrConfig.h>
69 #include <AdrConfig.h>
70 #include <RtcConfig.h>
71 #include <HybridStorageConfig.h>
72 #include <SpiConfig.h>
73
74 #ifndef FORCE_ENABLE
75 #define FORCE_ENABLE 1
76 #endif
77 #ifndef FORCE_DISABLE
78 #define FORCE_DISABLE 2
79 #endif
80 #ifndef PLATFORM_POR
81 #define PLATFORM_POR 0
82 #endif
83
84
85 #endif // _PCH_POLICY_COMMON_H_
TsnConfig.h
TSN Config policy.
ThcConfig.h
Touch Host Controller policy.
PsfConfig.h
Primary Sideband Fabric policy.
ConfigBlock.h
Header file for Config Block Lib implementation.
IoApicConfig.h
IoApic policy.
HdAudioConfig.h
HDAUDIO policy.
GbeConfig.h
Gigabit Ethernet policy.
FusaConfig.h
Functional Safety policy.
SataConfig.h
Sata policy.
FlashProtectionConfig.h
FlashProtection policy.
HybridStorageConfig.h
Hybrid Storage policy.
AdrConfig.h
ADR policy.
LockDownConfig.h
Lock down policy.
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
P2sbConfig.h
P2sb policy.
EspiConfig.h
Espi policy.
IehConfig.h
Integrated Error Handler policy.
CnviConfig.h
CNVi policy.
SerialIoConfig.h
Serial IO policy.
RtcConfig.h
RTC policy.
ScsConfig.h
Scs policy.
InterruptConfig.h
Interrupt policy.
PchPcieRpConfig.h
PCH Pcie root port policy.
PchGeneralConfig.h
PCH General policy.
PmConfig.h
Power Management policy.
Usb3HsioConfig.h
USB3 Mod PHY configuration policy.
ThermalConfig.h
Thermal policy.
PchDmiConfig.h
DMI policy.
Usb2PhyConfig.h
USB2 PHY configuration policy.
FivrConfig.h
PCH FIVR policy.
SpiConfig.h
PCH SPI Flash Controller config block.
RstConfig.h
Rst policy.
IshConfig.h
ISH policy.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Functions
PchPolicyLib.h File Reference

Prototype of the PeiPchPolicy library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for PchPolicyLib.h:

Go to the source code of this file.

Functions

VOID | PchPreMemPrintPolicyPpi (IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole PCH_PREMEM_POLICY_PPI and serial out. More...
VOID | PchPrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
Print whole SI_POLICY_PPI and serial out. More...
UINT16 | PchGetPreMemConfigBlockTotalSize (VOID)
Get PCH PREMEM config block table total size. More...
UINT16 | PchGetConfigBlockTotalSize (VOID)
Get PCH config block table total size. More...
EFI_STATUS | PchAddPreMemConfigBlocks (IN VOID *ConfigBlockTableAddress)
PchAddPreMemConfigBlocks add all PCH config blocks. More...
EFI_STATUS | PchAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
PchAddConfigBlocks add all PCH config blocks. More...
SATA_CONFIG * | GetPchSataConfig (IN SI_POLICY_PPI *SiPolicy, IN UINT32 SataCtrlIndex)
Get Sata Config Policy. More...
RST_CONFIG * | GetPchRstConfig (IN SI_POLICY_PPI *SiPolicy, IN UINT32 SataCtrlIndex)
Get Rst Config Policy. More...
PCH_HSIO_SATA_PREMEM_CONFIG * | GetPchHsioSataPreMemConfig (IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy, IN UINT32 SataCtrlIndex)
Get Hsio Sata Pre Mem Config Policy. More...

Detailed Description

Prototype of the PeiPchPolicy library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file PchPolicyLib.h.

Function Documentation

◆ GetPchHsioSataPreMemConfig()

PCH_HSIO_SATA_PREMEM_CONFIG* GetPchHsioSataPreMemConfig | ( | IN SI_PREMEM_POLICY_PPI * | SiPreMemPolicy,
 |  | IN UINT32 | SataCtrlIndex
 | ) |  |

Get Hsio Sata Pre Mem Config Policy.

Parameters
[in] | SiPolicy | The RC Policy PPI instance
[in] | SataCtrlIndex | SATA controller index
Return values
Pointer to Hsio Sata Pre Mem Config Policy

◆ GetPchRstConfig()

RST_CONFIG* GetPchRstConfig | ( | IN SI_POLICY_PPI * | SiPolicy,
 |  | IN UINT32 | SataCtrlIndex
 | ) |  |

Get Rst Config Policy.

Parameters
[in] | SiPolicy | The RC Policy PPI instance
[in] | SataCtrlIndex | SATA controller index
Return values
RstConfig Pointer to Rst Config Policy

◆ GetPchSataConfig()

SATA_CONFIG* GetPchSataConfig | ( | IN SI_POLICY_PPI * | SiPolicy,
 |  | IN UINT32 | SataCtrlIndex
 | ) |  |

Get Sata Config Policy.

Parameters
[in] | SiPolicy | The RC Policy PPI instance
[in] | SataCtrlIndex | SATA controller index
Return values
SataConfig Pointer to Sata Config Policy

◆ PchAddConfigBlocks()

EFI_STATUS PchAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

PchAddConfigBlocks add all PCH config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add PCH config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ PchAddPreMemConfigBlocks()

EFI_STATUS PchAddPreMemConfigBlocks ( IN VOID * ConfigBlockTableAddress )

PchAddPreMemConfigBlocks add all PCH config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add PCH config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ PchGetConfigBlockTotalSize()

UINT16 PchGetConfigBlockTotalSize ( VOID )

Get PCH config block table total size.

Return values
Size of PCH config block table

◆ PchGetPreMemConfigBlockTotalSize()

UINT16 PchGetPreMemConfigBlockTotalSize ( VOID )

Get PCH PREMEM config block table total size.

Return values
Size of PCH PREMEM config block table

◆ PchPreMemPrintPolicyPpi()

VOID PchPreMemPrintPolicyPpi ( IN SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

Print whole PCH_PREMEM_POLICY_PPI and serial out.

Parameters
[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance

◆ PchPrintPolicyPpi()

VOID PchPrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

Print whole SI_POLICY_PPI and serial out.

Parameters
[in] SiPolicyPpi The RC Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the PeiPchPolicy library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _PEI_PCH_POLICY_LIB_H_
36 #define _PEI_PCH_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39
40 /**
41 Print whole PCH_PREMEM_POLICY_PPI and serial out.
42
43 @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
44 **/
45 VOID
46 EFIAPI
47 PchPreMemPrintPolicyPpi (
48 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
49 );
50
51 /**
52 Print whole SI_POLICY_PPI and serial out.
53
54 @param[in] SiPolicyPpi The RC Policy PPI instance
55 **/
56 VOID
57 EFIAPI
58 PchPrintPolicyPpi (
59 IN SI_POLICY_PPI *SiPolicyPpi
60 );
61
62 /**
63 Get PCH PREMEM config block table total size.
64
65 @retval Size of PCH PREMEM config block table
66 **/
67 UINT16
68 EFIAPI
69 PchGetPreMemConfigBlockTotalSize (
70 VOID
71 );
72
73 /**
74 Get PCH config block table total size.
75
76 @retval Size of PCH config block table
77 **/
78 UINT16
79 EFIAPI
80 PchGetConfigBlockTotalSize (
81 VOID
82 );
83
84 /**
85 PchAddPreMemConfigBlocks add all PCH config blocks.
86
87 @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
88
89 @retval EFI_SUCCESS The policy default is initialized.
90 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
91 **/
92 EFI_STATUS
93 EFIAPI
94 PchAddPreMemConfigBlocks (
95 IN VOID *ConfigBlockTableAddress
96 );
97
98 /**
99 PchAddConfigBlocks add all PCH config blocks.
100
101 @param[in] ConfigBlockTableAddress The pointer to add PCH config blocks
102
103 @retval EFI_SUCCESS The policy default is initialized.
104 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
105 **/
106 EFI_STATUS
107 EFIAPI
108 PchAddConfigBlocks (
109 IN VOID *ConfigBlockTableAddress
110 );
111
112 /**
113 Get Sata Config Policy
114
115 @param[in] SiPolicy The RC Policy PPI instance
116 @param[in] SataCtrlIndex SATA controller index
117
118 @retval SataConfig Pointer to Sata Config Policy
119 **/
120 SATA_CONFIG *
121 GetPchSataConfig (
122 IN SI_POLICY_PPI *SiPolicy,
123 IN UINT32 SataCtrlIndex
124 );
125
126 /**
127 Get Rst Config Policy
128
129 @param[in] SiPolicy The RC Policy PPI instance
130 @param[in] SataCtrlIndex SATA controller index
131
132 @retval RstConfig Pointer to Rst Config Policy
133 **/
134 RST_CONFIG *
135 GetPchRstConfig (
136 IN SI_POLICY_PPI *SiPolicy,
137 IN UINT32 SataCtrlIndex
138 );
139
140 /**
141 Get Hsio Sata Pre Mem Config Policy
142
143 @param[in] SiPolicy The RC Policy PPI instance
144 @param[in] SataCtrlIndex SATA controller index
145
146 @retval Pointer to Hsio Sata Pre Mem Config Policy
147 **/
148 PCH_HSIO_SATA_PREMEM_CONFIG *
149 GetPchHsioSataPreMemConfig (
150 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
151 IN UINT32 SataCtrlIndex
152 );
153
154 #endif // _PEI_PCH_POLICY_LIB_H_
GetPchHsioSataPreMemConfig
PCH_HSIO_SATA_PREMEM_CONFIG * GetPchHsioSataPreMemConfig(IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy, IN UINT32 SataCtrlIndex)
Get Hsio Sata Pre Mem Config Policy.
PchAddPreMemConfigBlocks
EFI_STATUS PchAddPreMemConfigBlocks(IN VOID *ConfigBlockTableAddress)
PchAddPreMemConfigBlocks add all PCH config blocks.
GetPchRstConfig
RST_CONFIG * GetPchRstConfig(IN SI_POLICY_PPI *SiPolicy, IN UINT32 SataCtrlIndex)
Get Rst Config Policy.
GetPchSataConfig
SATA_CONFIG * GetPchSataConfig(IN SI_POLICY_PPI *SiPolicy, IN UINT32 SataCtrlIndex)
Get Sata Config Policy.
SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers.
Definition: SataConfig.h:134
RST_CONFIG
Rapid Storage Technology settings.
Definition: RstConfig.h:84
PchPrintPolicyPpi
VOID PchPrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
Print whole SI_POLICY_PPI and serial out.
PchPreMemPrintPolicyPpi
VOID PchPreMemPrintPolicyPpi(IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole PCH_PREMEM_POLICY_PPI and serial out.
PchGetPreMemConfigBlockTotalSize
UINT16 PchGetPreMemConfigBlockTotalSize(VOID)
Get PCH PREMEM config block table total size.
PchGetConfigBlockTotalSize
UINT16 PchGetConfigBlockTotalSize(VOID)
Get PCH config block table total size.
PCH_HSIO_SATA_PREMEM_CONFIG
The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
Definition: HsioSataConfig.h:82
PchAddConfigBlocks
EFI_STATUS PchAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
PchAddConfigBlocks add all PCH config blocks.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPreMemPolicyCommon.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Classes | Macros | Typedefs
PchPreMemPolicyCommon.h File Reference

PCH configuration based on PCH policy. More...

#include <ConfigBlock.h>
#include "PchLimits.h"
#include "ConfigBlock/PchGeneralConfig.h"
#include <DciConfig.h>
#include <WatchDogConfig.h>
#include <SmbusConfig.h>
#include <LpcConfig.h>
#include <HsioPcieConfig.h>
#include <HsioSataConfig.h>
#include <PchDmiConfig.h>
#include <HsioConfig.h>
Include dependency graph for PchPreMemPolicyCommon.h:

Go to the source code of this file.

Classes

struct _PCH_PREMEM_POLICY
PCH Policy PPI
All PCH config block change history will be listed here

. More...

Macros

#define PCH_PREMEM_POLICY_REVISION 1
PCH Policy revision number Any backwards compatible changes to this structure will result in an update in the revision number.

Typedefs

typedef struct _PCH_PREMEM_POLICY PCH_PREMEM_POLICY
PCH Policy PPI
All PCH config block change history will be listed here

. More...

Detailed Description

PCH configuration based on PCH policy.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchPreMemPolicyCommon.h.

Typedef Documentation

◆ PCH_PREMEM_POLICY

typedef struct _PCH_PREMEM_POLICY PCH_PREMEM_POLICY

PCH Policy PPI
All PCH config block change history will be listed here

.

  • Revision 1:
    • Initial version.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPreMemPolicyCommon.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchPreMemPolicyCommon.h
Go to the documentation of this file.
1 /** @file
2 PCH configuration based on PCH policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_PREMEM_POLICY_COMMON_H_
36 #define _PCH_PREMEM_POLICY_COMMON_H_
37
38 #include <ConfigBlock.h>
39
40 #include "PchLimits.h"
41 #include "ConfigBlock/PchGeneralConfig.h"
42 #include <DciConfig.h>
43 #include <WatchDogConfig.h>
44 #include <SmbusConfig.h>
45 #include <LpcConfig.h>
46 #include <HsioPcieConfig.h>
47 #include <HsioSataConfig.h>
48 #include <PchDmiConfig.h>
49 #include <HsioConfig.h>
50
51 #pragma pack (push,1)
52
53 #ifndef FORCE_ENABLE
54 #define FORCE_ENABLE 1
55 #endif
56 #ifndef FORCE_DISABLE
57 #define FORCE_DISABLE 2
58 #endif
59 #ifndef PLATFORM_POR
60 #define PLATFORM_POR 0
61 #endif
62
63 /**
64 PCH Policy revision number
65 Any backwards compatible changes to this structure will result in an update in the revision number
66 **/
67 #define PCH_PREMEM_POLICY_REVISION 1
68
69 /**
70 PCH Policy PPI\n
71 All PCH config block change history will be listed here\n\n
72
73 - <b>Revision 1</b>:
74 - Initial version.\n
75 **/
76 typedef struct _PCH_PREMEM_POLICY {
77 CONFIG_BLOCK_TABLE_HEADER TableHeader;
78 /*
79 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
80 */
81 } PCH_PREMEM_POLICY;
82
83 #pragma pack (pop)
84
85 #endif // _PCH_PREMEM_POLICY_COMMON_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
HsioConfig.h
HSIO policy.
SmbusConfig.h
Smbus policy.
PCH_PREMEM_POLICY
struct _PCH_PREMEM_POLICY PCH_PREMEM_POLICY
PCH Policy PPI All PCH config block change history will be listed here .
DciConfig.h
Dci policy.
PchGeneralConfig.h
PCH General policy.
HsioPcieConfig.h
HSIO pcie policy.
_PCH_PREMEM_POLICY
PCH Policy PPI All PCH config block change history will be listed here .
Definition: PchPreMemPolicyCommon.h:76
PchDmiConfig.h
DMI policy.
HsioSataConfig.h
Hsio Sata policy.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
LpcConfig.h
Lpc policy.
WatchDogConfig.h
WatchDog policy.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
Macros
PchRegs.h File Reference

Generic register definitions for PCH. More...

Go to the source code of this file.

Macros

#define | DEFAULT_PCI_SEGMENT_NUMBER_PCH 0
The default PCH PCI segment and bus number.
#define | V_PCH_INTEL_VENDOR_ID 0x8086
Default Intel PCH Vendor ID.
#define | V_PCH_DEFAULT_SID 0x7270
Default Intel PCH Subsystem ID.
#define | V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16))
Default INTEL PCH Vendor ID and Subsystem ID.

Detailed Description

Generic register definitions for PCH.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
PchRegs.h
Go to the documentation of this file.
1 /** @file
2 Generic register definitions for PCH.
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2017 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_REGS_H_
65 #define _PCH_REGS_H_
66
67 ///
68 /// The default PCH PCI segment and bus number
69 ///
70 #define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0
71 #define DEFAULT_PCI_BUS_NUMBER_PCH 0
72
73 //
74 // Default Vendor ID and Subsystem ID
75 //
76 #define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor ID
77 #define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsystem ID
78 #define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID << 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID
79
80 #endif //_PCH_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsClk.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
PchRegsClk.h File Reference

Register names for iCLK device. More...

Go to the source code of this file.

Detailed Description

Register names for iCLK device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file PchRegsClk.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsClk.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
PchRegsClk.h
Go to the documentation of this file.
1 /** @file
2 Register names for iCLK device
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2017 - 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification
63 **/
64 #ifndef _PCH_REGS_ICLK_H_
65 #define _PCH_REGS_ICLK_H_
66
67 #define R_ICLK_PCR_CMU_ONE_DWORD25 0x22E4
68 #define R_ICLK_PCR_CMU_ONE_DWORD26 0x22E8
69 #define S_ICLK_PCR_MUXSEL_BITS_PER_FIELD 4 // CLKREQ number is encoded in 4 bits
70 #define B_ICLK_PCR_MUXSEL_BITS_PER_FIELD 0xF // CLKREQ number is encoded in 4 bits
71 #define S_ICLK_PCR_MUXSEL_FIELDS_PER_REG 8 // each CMU_ONE_DWORD register contains bitfields for 8 CLK_SRC
72
73 #define R_ICLK_PCR_BIOS_BUFFEN 0x8080
74 #define N_ICLK_PCR_BIOS_BUFFEN_SRC0 2
75 #define R_ICLK_PCR_BIOS_BUFFEN_H 0x8084
76 #define N_ICLK_PCR_BIOS_BUFFEN_H_SRC7 1
77 #define R_ICLK_PCR_SRC_MUXSEL 0x8104
78 #define R_ICLK_PCR_SRC_MUXSEL_26 0x8108
79 #define R_ICLK_PCR_SRC_MUXSEL_34 0x810C
80 #define R_ICLK_PCR_SRC_MUXSEL_42 0x8110
81 #define R_ICLK_PCR_SRC_MUXSEL_50 0x8114
82 #define S_ICLK_PCR_SRC_MUXSEL_FIELDS_PER_REG 4
83 #define B_ICLK_PCR_SRC_MUXSEL_BITS_PER_FIELD 0x1F
84 #endif // _PCH_REGS_ICLK_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsLpc.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PchRegsLpc.h File Reference

Register names for PCH LPC/eSPI device. More...

Go to the source code of this file.

Macros

#define | B_LPC_CFG_IOE_ME2 BIT13
Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC.
#define | B_LPC_CFG_IOE_SE BIT12
Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
#define | B_LPC_CFG_IOE_ME1 BIT11
Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC.
#define | B_LPC_CFG_IOE_KE BIT10
Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
#define | B_LPC_CFG_IOE_HGE BIT9
High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC.
#define | B_LPC_CFG_IOE_LGE BIT8
Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC.
#define | B_LPC_CFG_IOE_FDE BIT3
Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE.
#define | B_LPC_CFG_IOE_PPE BIT2
Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
#define | B_LPC_CFG_IOE_CBE BIT1
Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
#define | B_LPC_CFG_IOE_CAE BIT0
Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
#define | R_LPC_CFG_BDE 0xD8
BIOS decode enable.
#define | V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000
PCH Integrated Graphics Support Capability.
#define | B_LPC_CFG_FVEC3_DCMI_CAP BIT13
Data Center Manageability Interface (DCMI) Capability.
#define | B_LPC_CFG_FVEC3_NM_CAP BIT12
Node Manager Capability.
#define | R_LPC_CFG_BC 0xDC
Bios Control.
#define | B_LPC_CFG_BC_BILD BIT7
BIOS Interface Lock-Down.
#define | B_LPC_CFG_BC_BBS BIT6
Boot BIOS strap.
#define | V_LPC_CFG_BC_BBS_SPI 0
Boot BIOS strapped to SPI.
#define | V_LPC_CFG_BC_BBS_LPC 1
Boot BIOS strapped to LPC.
#define | B_LPC_CFG_BC_EISS BIT5
Enable InSMM.STS.
#define | B_LPC_CFG_BC_TS BIT4
Top Swap.
#define | B_LPC_CFG_BC_LE BIT1
Lock Enable.
#define | B_LPC_CFG_BC_WPD BIT0
Write Protect Disable.
#define | R_ESPI_CFG_PCBC 0xDC
Peripheral Channel BIOS Control.
#define | S_ESPI_CFG_PCBC 4
Peripheral Channel BIOS Control register size.
#define | B_ESPI_CFG_PCBC_BWRE BIT11
BIOS Write Report Enable.
#define | N_ESPI_CFG_PCBC_BWRE 11
BIOS Write Report Enable bit position.
#define | B_ESPI_CFG_PCBC_BWRS BIT10
BIOS Write Report Status.
#define | N_ESPI_CFG_PCBC_BWRS 10
BIOS Write Report Status bit position.
#define | B_ESPI_CFG_PCBC_BWPDS BIT8
BIOS Write Protect Disable Status.
#define | N_ESPI_CFG_PCBC_BWPDS 8
BIOS Write Protect Disable Status bit position.
#define | B_ESPI_CFG_PCBC_BILD BIT7
BIOS Interface Lock-Down.
#define | B_ESPI_CFG_PCBC_EISS BIT5
Enable InSMM.STS.
#define | B_ESPI_CFG_PCBC_ESPI_EN BIT2
eSPI Enable Pin Strap
#define | B_ESPI_CFG_PCBC_LE BIT1
Lock Enable.
#define | R_ESPI_SLAVE_CHA_0_CAP_AND_CONF 0x10
Channel 0 Capabilities and Configurations.
#define | B_ESPI_SLAVE_BME BIT2
Bus Requester Enable.
#define | R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000
Responder Configuration Register and Link Control.
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31
Responder Configuration Register Access Enable.
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28)
Responder Configuration Register Access Status.
#define | N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28
Responder Configuration Register Access Status bit position.
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27
IOSF-SB eSPI Link Configuration Lock.
#define | V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7
No errors (transaction completed successfully)
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19)
Responder ID.
#define | N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19
Responder ID bit position.
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16)
Responder Configuration Register Access Type.
#define | N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16
Responder Configuration Register Access Type bit position.
#define | V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0
Responder Configuration register read from address SCRA[11:0].
#define | V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1
Responder Configuration register write to address SCRA[11:0].
#define | V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2
Responder Status register read.
#define | V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3
In-Band reset.
#define | B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF
Responder Configuration Register Address.
#define | R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004
Responder Configuration Register Data.
#define | R_ESPI_PCR_PCERR_SLV0 0x4020
Peripheral Channel Error for Responder 0.
#define | B_ESPI_PCR_PCERR_PCFEE (BIT6 | BIT5)
Peripheral Channel Fatal Error Reporting bits.
#define | N_ESPI_PCR_PCERR_PCFEE 5
Peripheral Channel Fatal Error Reporting bit position.
#define | V_ESPI_PCR_PCERR_PCFEE_SERR 2
Enable Fatal Error Reporting as SERR.
#define | B_ESPI_PCR_PCERR_SLV0_PMMA BIT7
PLCC Misaligned Memory Access.
#define | B_ESPI_PCR_PCERR_PCNFES BIT12
Peripheral Channel Non-Fatal Status.
#define | B_ESPI_PCR_PCERR_PCNFEE (BIT14 | BIT13)
Peripheral Channel Non-Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_PCERR_PCNFEE 13
Peripheral Channel Non-Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_PCERR_PCNFEE_SERR 2
Enable Non-Fatal Error Reporting as SERR.
#define | B_ESPI_PCR_PCERR_PCURD BIT24
Peripheral Channel Unsupported Request Detected.
#define | B_ESPI_PCR_PCERR_PCURRE BIT25
Peripheral Channel Unsupported Request Reporting Enable.
#define | B_ESPI_PCR_PCERR_PCRMTARE (BIT27 | BIT26)
Peripheral Channel Received Target or Target Abort Reporting bits.
#define | N_ESPI_PCR_PCERR_PCRMTARE 26
Peripheral Channel Received Target or Target Abort Reporting bit position.
#define | V_ESPI_PCR_PCERR_PCRMTARE_SERR 2
Enable RMA or RTA Reporting as SERR.
#define | R_ESPI_PCR_PCERR_SLV1 0x4024
Peripheral Channel Error for Responder 1.
#define | R_ESPI_PCR_VWERR_SLV0 0x4030
Virtual Wire Channel Error for Responder 0.
#define | B_ESPI_PCR_VWERR_SLV0_VWHC10OE BIT25
Requester HOST_C10 (Virtual Wire) to Responder Enable (VWHC10OE)
#define | B_ESPI_PCR_VWERR_VWNFEE (BIT14 | BIT13)
Virtual Wire Channel Non-Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_VWERR_VWNFEE 13
Virtual Wire Channel Non-Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_VWERR_VWNFEE_SERR 2
Enable Non-Fatal Error Reporting as SERR.
#define | B_ESPI_PCR_VWERR_VWFEE (BIT6 | BIT5)
Virtual Wire Channel Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_VWERR_VWFEE 5
Virtual Wire Channel Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_VWERR_VWFEE_SERR 2
Enable Fatal Error Reporting as SERR.
#define | R_ESPI_PCR_VWERR_SLV1 0x4034
Virtual Wire Channel Error for Responder 1.
#define | R_ESPI_PCR_FCERR_SLV0 0x4040
Flash Access Channel Error for Responder 0.
#define | B_ESPI_PCR_FCERR_SLV0_FCFEE (BIT6 | BIT5)
Flash Access Channel Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_FCERR_SLV0_FCFEE 5
Flash Access Channel Fatal Error Reporting bit position.
#define | V_ESPI_PCR_FCERR_SLV0_FCFEE_SERR 2
Enable Fatal Error Reporting as SERR.
#define | B_ESPI_PCR_FCERR_SLV0_FCNFEE (BIT14 | BIT13)
Flash Access Channel Non-Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_FCERR_SLV0_FCNFEE 13
Flash Access Channel Non-Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_FCERR_SLV0_FCNFEE_SERR 2
Enable Non-Fatal Error Reporting as SERR.
#define | B_ESPI_PCR_FCERR_SAFBLK BIT17
SAF Blocked (SAFBLK)
#define | B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13)
Non-Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_XERR_XNFEE 13
Non-Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_XERR_XNFEE_SMI 3
Enable Non-Fatal Error Reporting as SMI.
#define | B_ESPI_PCR_XERR_XNFES BIT12
Fatal Error Status.
#define | B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5)
Fatal Error Reporting Enable bits.
#define | N_ESPI_PCR_XERR_XFEE 5
Fatal Error Reporting Enable bit position.
#define | V_ESPI_PCR_XERR_XFEE_SMI 3
Enable Fatal Error Reporting as SMI.
#define | B_ESPI_PCR_XERR_XFES BIT4
Fatal Error Status.
#define | S_ESPI_PCR_XERR 4
Channel register sizes.
#define | B_ESPI_PCR_PCERR_SLV0_PCURD BIT24
Peripheral Channel Unsupported Request Detected.
#define | R_ESPI_PCR_LNKERR_SLV0 0x4050
Link Error for Responder 0.
#define | S_ESPI_PCR_LNKERR_SLV0 4
Link Error for Responder 0 register size.
#define | B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31
eSPI Link and Responder Channel Recovery Required
#define | B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21)
Fatal Error Type 1 Reporting Enable.
#define | N_ESPI_PCR_LNKERR_SLV0_LFET1E 21
Fatal Error Type 1 Reporting Enable bit position.
#define | V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3
Enable Fatal Error Type 1 Reporting as SMI.
#define | V_ESPI_PCR_LNKERR_SLV0_LFER1E_SERR 2
Enable Fatal Error Type 1 Reporting as SERR.
#define | B_ESPI_PCR_LNKERR_SLV1_LFET1E (BIT22 | BIT21)
Fatal Error Type 1 Reporting Enable.
#define | N_ESPI_PCR_LNKERR_SLV1_LFET1E 21
Fatal Error Type 1 Reporting Enable bit position.
#define | V_ESPI_PCR_LNKERR_SLV1_LFET1E_SMI 3
Enable Fatal Error Type 1 Reporting as SMI.
#define | V_ESPI_PCR_LNKERR_SLV1_LFER1E_SERR 2
Enable Fatal Error Type 1 Reporting as SERR.
#define | B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20
Link Fatal Error Type 1 Status.
#define | R_ESPI_PCR_LNKERR_SLV1 0x4054
Link Error for Responder 1.
#define | R_ESPI_PCR_CFG_VAL 0xC00C
ESPI Enabled Strap.
#define | B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0
ESPI Enabled Strap bit position.
#define | R_ESPI_PCR_SOFTSTRAPS 0xC210
eSPI Sofstraps Register 0
#define | B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12
CS1# Enable.

Detailed Description

Register names for PCH LPC/eSPI device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchRegsLpc.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsLpc.h Source File

  • Intel
  • ClientOneSiliconPkg
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  • Register
PchRegsLpc.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH LPC/eSPI device
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_REGS_LPC_H_
65 #define _PCH_REGS_LPC_H_
66
67 #define B_LPC_CFG_DID 0xFFE0
68
69 //
70 // PCI to LPC Bridge Registers
71 //
72
73 #define R_LPC_CFG_IOD 0x80
74 #define B_LPC_CFG_IOD_FDD BIT12
75 #define N_LPC_CFG_IOD_FDD 12
76 #define V_LPC_CFG_IOD_FDD_3F0 0
77 #define V_LPC_CFG_IOD_FDD_370 1
78 #define B_LPC_CFG_IOD_LPT (BIT9 | BIT8)
79 #define N_LPC_CFG_IOD_LPT 8
80 #define V_LPC_CFG_IOD_LPT_378 0
81 #define V_LPC_CFG_IOD_LPT_278 1
82 #define V_LPC_CFG_IOD_LPT_3BC 2
83 #define B_LPC_CFG_IOD_COMB (BIT6 | BIT5 |BIT4)
84 #define N_LPC_CFG_IOD_COMB 4
85 #define V_LPC_CFG_IOD_COMB_3F8 0
86 #define V_LPC_CFG_IOD_COMB_2F8 1
87 #define V_LPC_CFG_IOD_COMB_220 2
88 #define V_LPC_CFG_IOD_COMB_228 3
89 #define V_LPC_CFG_IOD_COMB_238 4
90 #define V_LPC_CFG_IOD_COMB_2E8 5
91 #define V_LPC_CFG_IOD_COMB_338 6
92 #define V_LPC_CFG_IOD_COMB_3E8 7
93 #define B_LPC_CFG_IOD_COMA (BIT2 | BIT1 | BIT0)
94 #define N_LPC_CFG_IOD_COMA 0
95 #define V_LPC_CFG_IOD_COMA_3F8 0
96 #define V_LPC_CFG_IOD_COMA_2F8 1
97 #define V_LPC_CFG_IOD_COMA_220 2
98 #define V_LPC_CFG_IOD_COMA_228 3
99 #define V_LPC_CFG_IOD_COMA_238 4
100 #define V_LPC_CFG_IOD_COMA_2E8 5
101 #define V_LPC_CFG_IOD_COMA_338 6
102 #define V_LPC_CFG_IOD_COMA_3E8 7
103 #define R_LPC_CFG_IOE 0x82
104 #define B_LPC_CFG_IOE_ME2 BIT13 ///< Microcontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC
105 #define B_LPC_CFG_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
106 #define B_LPC_CFG_IOE_ME1 BIT11 ///< Microcontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LPC.
107 #define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
108 #define B_LPC_CFG_IOE_HGE BIT9 ///< High Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LPC.
109 #define B_LPC_CFG_IOE_LGE BIT8 ///< Low Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC.
110 #define B_LPC_CFG_IOE_FDE BIT3 ///< Floppy Drive Enable, Enables decoding of the FDD range to LPC. Range is selected by LIOD.FDE
111 #define B_LPC_CFG_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
112 #define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
113 #define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
114 #define R_LPC_CFG_GEN1_DEC 0x84
115 #define R_LPC_CFG_GEN2_DEC 0x88
116 #define R_LPC_CFG_GEN3_DEC 0x8C
117 #define R_LPC_CFG_GEN4_DEC 0x90
118 #define B_LPC_CFG_GENX_DEC_ADDR_MASK 0x00FC0000
119 #define N_LPC_CFG_GENX_DEC_ADDR_MASK 18
120 #define B_LPC_CFG_GENX_DEC_ADDR 0xFFFC
121 #define N_LPC_CFG_GENX_DEC_ADDR 2
122 #define B_LPC_CFG_GENX_DEC_EN 0x00000001
123 #define R_LPC_CFG_ULKMC 0x94
124 #define B_LPC_CFG_ULKMC_SMIBYENDPS BIT15
125 #define B_LPC_CFG_ULKMC_TRAPBY64W BIT11
126 #define B_LPC_CFG_ULKMC_TRAPBY64R BIT10
127 #define B_LPC_CFG_ULKMC_TRAPBY60W BIT9
128 #define B_LPC_CFG_ULKMC_TRAPBY60R BIT8
129 #define B_LPC_CFG_ULKMC_SMIATENDPS BIT7
130 #define B_LPC_CFG_ULKMC_PSTATE BIT6
131 #define B_LPC_CFG_ULKMC_A20PASSEN BIT5
132 #define B_LPC_CFG_ULKMC_USBSMIEN BIT4
133 #define B_LPC_CFG_ULKMC_64WEN BIT3
134 #define B_LPC_CFG_ULKMC_64REN BIT2
135 #define B_LPC_CFG_ULKMC_60WEN BIT1
136 #define B_LPC_CFG_ULKMC_60REN BIT0
137 #define R_LPC_CFG_LGMR 0x98
138 #define B_LPC_CFG_LGMR_MA 0xFFFF0000
139 #define B_LPC_CFG_LGMR_LMRD_EN BIT0
140 #define R_ESPI_CFG_CS1IORE 0xA0
141 #define R_ESPI_CFG_CS1IORE_DPCS1RE BIT14
142 #define R_ESPI_CFG_CS1GIR1 0xA4
143 #define R_ESPI_CFG_CS1GMR1 0xA8
144
145 #define R_LPC_CFG_FWH_BIOS_SEL 0xD0
146 #define B_LPC_CFG_FWH_BIOS_SEL_F8 0xF0000000
147 #define B_LPC_CFG_FWH_BIOS_SEL_F0 0x0F000000
148 #define B_LPC_CFG_FWH_BIOS_SEL_E8 0x00F00000
149 #define B_LPC_CFG_FWH_BIOS_SEL_E0 0x000F0000
150 #define B_LPC_CFG_FWH_BIOS_SEL_D8 0x0000F000
151 #define B_LPC_CFG_FWH_BIOS_SEL_D0 0x00000F00
152 #define B_LPC_CFG_FWH_BIOS_SEL_C8 0x000000F0
153 #define B_LPC_CFG_FWH_BIOS_SEL_C0 0x0000000F
154 #define R_LPC_CFG_FWH_BIOS_SEL2 0xD4
155 #define B_LPC_CFG_FWH_BIOS_SEL2_70 0xF000
156 #define B_LPC_CFG_FWH_BIOS_SEL2_60 0x0F00
157 #define B_LPC_CFG_FWH_BIOS_SEL2_50 0x00F0
158 #define B_LPC_CFG_FWH_BIOS_SEL2_40 0x000F
159 #define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
160 #define B_LPC_CFG_BDE_F8 BIT15
161 #define B_LPC_CFG_BDE_F0 BIT14
162 #define B_LPC_CFG_BDE_E8 BIT13
163 #define B_LPC_CFG_BDE_E0 BIT12
164 #define B_LPC_CFG_BDE_D8 BIT11
165 #define B_LPC_CFG_BDE_D0 BIT10
166 #define B_LPC_CFG_BDE_C8 BIT9
167 #define B_LPC_CFG_BDE_C0 BIT8
168 #define B_LPC_CFG_BDE_LEG_F BIT7
169 #define B_LPC_CFG_BDE_LEG_E BIT6
170 #define B_LPC_CFG_BDE_70 BIT3
171 #define B_LPC_CFG_BDE_60 BIT2
172 #define B_LPC_CFG_BDE_50 BIT1
173 #define B_LPC_CFG_BDE_40 BIT0
174 #define B_LPC_CFG_FVEC0_USB_PORT_CAP (BIT11 | BIT10)
175 #define V_LPC_CFG_FVEC0_USB_14_PORT 0x00000000
176 #define V_LPC_CFG_FVEC0_USB_12_PORT 0x00000400
177 #define V_LPC_CFG_FVEC0_USB_10_PORT 0x00000800
178 #define B_LPC_CFG_FVEC0_SATA_RAID_CAP BIT7
179 #define B_LPC_CFG_FVEC0_SATA_PORT23_CAP BIT6
180 #define B_LPC_CFG_FVEC0_SATA_PORT1_6GB_CAP BIT3
181 #define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP BIT2
182 #define B_LPC_CFG_FVEC0_PCI_CAP BIT1
183 #define R_LPC_CFG_FVEC1 0x01
184 #define B_LPC_CFG_FVEC1_USB_R_CAP BIT22
185 #define R_LPC_CFG_FVEC2 0x02
186 #define V_LPC_CFG_FVEC2_PCIE_PORT78_CAP 0x00200000
187 #define V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Integrated Graphics Support Capability
188 #define R_LPC_CFG_FVEC3 0x03
189 #define B_LPC_CFG_FVEC3_DCMI_CAP BIT13 ///< Data Center Manageability Interface (DCMI) Capability
190 #define B_LPC_CFG_FVEC3_NM_CAP BIT12 ///< Node Manager Capability
191
192 #define R_LPC_CFG_MDAP 0xC0
193 #define B_LPC_CFG_MDAP_POLICY_EN BIT31
194 #define B_LPC_CFG_MDAP_PDMA_EN BIT30
195 #define B_LPC_CFG_MDAP_VALUE 0x0001FFFF
196
197 //
198 // APM Registers
199 //
200 #define R_PCH_IO_APM_CNT 0xB2
201 #define R_PCH_IO_APM_STS 0xB3
202
203 #define R_LPC_CFG_BC 0xDC ///< Bios Control
204 #define S_LPC_CFG_BC 1
205 #define B_LPC_CFG_BC_BILD BIT7 ///< BIOS Interface Lock-Down
206 #define B_LPC_CFG_BC_BBS BIT6 ///< Boot BIOS strap
207 #define N_LPC_CFG_BC_BBS 6
208 #define V_LPC_CFG_BC_BBS_SPI 0 ///< Boot BIOS strapped to SPI
209 #define V_LPC_CFG_BC_BBS_LPC 1 ///< Boot BIOS strapped to LPC
210 #define B_LPC_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
211 #define B_LPC_CFG_BC_TS BIT4 ///< Top Swap
212 #define B_LPC_CFG_BC_LE BIT1 ///< Lock Enable
213 #define N_LPC_CFG_BC_LE 1
214 #define B_LPC_CFG_BC_WPD BIT0 ///< Write Protect Disable
215
216 #define R_ESPI_CFG_PCBC 0xDC ///< Peripheral Channel BIOS Control
217 #define S_ESPI_CFG_PCBC 4 ///< Peripheral Channel BIOS Control register size
218 #define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIOS Write Report Enable
219 #define N_ESPI_CFG_PCBC_BWRE 11 ///< BIOS Write Report Enable bit position
220 #define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS Write Report Status
221 #define N_ESPI_CFG_PCBC_BWRS 10 ///< BIOS Write Report Status bit position
222 #define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status
223 #define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position
224 #define B_ESPI_CFG_PCBC_BILD BIT7 ///< BIOS Interface Lock-Down
225 #define B_ESPI_CFG_PCBC_EISS BIT5 ///< Enable InSMM.STS
226 #define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
227 #define B_ESPI_CFG_PCBC_LE BIT1 ///< Lock Enable
228 #define N_ESPI_CFG_PCBC_LE 1
229
230 //
231 // eSPI Responder registers
232 //
233 #define R_ESPI_SLAVE_CHA_0_CAP_AND_CONF 0x10 ///< Channel 0 Capabilities and Configurations
234 #define B_ESPI_SLAVE_BME BIT2 ///< Bus Requester Enable
235
236 //
237 // Processor interface registers
238 //
239 #define R_PCH_IO_NMI_SC 0x61
240 #define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7
241 #define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6
242 #define B_PCH_IO_NMI_SC_TMR2_OUT_STS BIT5
243 #define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4
244 #define B_PCH_IO_NMI_SC_IOCHK_NMI_EN BIT3
245 #define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2
246 #define B_PCH_IO_NMI_SC_SPKR_DAT_EN BIT1
247 #define B_PCH_IO_NMI_SC_TIM_CNT2_EN BIT0
248 #define R_PCH_IO_NMI_EN 0x70
249 #define B_PCH_IO_NMI_EN_NMI_EN BIT7
250
251 //
252 // Reset Generator I/O Port
253 //
254 #define R_PCH_IO_RST_CNT 0xCF9
255 #define B_PCH_IO_RST_CNT_FULL_RST BIT3
256 #define B_PCH_IO_RST_CNT_RST_CPU BIT2
257 #define B_PCH_IO_RST_CNT_SYS_RST BIT1
258 #define V_PCH_IO_RST_CNT_FULLRESET 0x0E
259 #define V_PCH_IO_RST_CNT_HARDRESET 0x06
260 #define V_PCH_IO_RST_CNT_SOFTRESET 0x04
261 #define V_PCH_IO_RST_CNT_HARDSTARTSTATE 0x02
262 #define V_PCH_IO_RST_CNT_SOFTSTARTSTATE 0x00
263
264 //
265 // LPC PCR Registers
266 //
267 #define R_LPC_PCR_HVMTCTL 0x3410
268 #define R_LPC_PCR_GCFD 0x3418
269 #define R_LPC_PCR_PRC 0x341C
270 #define R_LPC_PCR_PCT 0x3420
271 #define R_LPC_PCR_SCT 0x3424
272 #define R_LPC_PCR_LPCCT 0x3428
273 #define R_LPC_PCR_ULTOR 0x3500
274
275 //
276 // eSPI PCR Registers
277 //
278 #define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///< Responder Configuration Register and Link Control
279 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///< Responder Configuration Register Access Enable
280 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Responder Configuration Register Access Status
281 #define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///< Responder Configuration Register Access Status bit position
282 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock
283 #define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully)
284 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Responder ID
285 #define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///< Responder ID bit position
286 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Responder Configuration Register Access Type
287 #define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///< Responder Configuration Register Access Type bit position
288 #define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0 ///< Responder Configuration register read from address SCRA[11:0]
289 #define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1 ///< Responder Configuration register write to address SCRA[11:0]
290 #define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2 ///< Responder Status register read
291 #define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3 ///< In-Band reset
292 #define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Responder Configuration Register Address
293 #define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///< Responder Configuration Register Data
294
295 #define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Responder 0
296 #define B_ESPI_PCR_PCERR_PCFEE (BIT6 | BIT5) ///< Peripheral Channel Fatal Error Reporting bits
297 #define N_ESPI_PCR_PCERR_PCFEE 5 ///< Peripheral Channel Fatal Error Reporting bit position
298 #define V_ESPI_PCR_PCERR_PCFEE_SERR 2 ///< Enable Fatal Error Reporting as SERR
299 #define B_ESPI_PCR_PCERR_SLV0_PMMA BIT7 ///< PLCC Misaligned Memory Access
300 #define B_ESPI_PCR_PCERR_PCNFES BIT12 ///< Peripheral Channel Non-Fatal Status
301 #define B_ESPI_PCR_PCERR_PCNFEE (BIT14 | BIT13) ///< Peripheral Channel Non-Fatal Error Reporting Enable bits
302 #define N_ESPI_PCR_PCERR_PCNFEE 13 ///< Peripheral Channel Non-Fatal Error Reporting Enable bit position
303 #define V_ESPI_PCR_PCERR_PCNFEE_SERR 2 ///< Enable Non-Fatal Error Reporting as SERR
304 #define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
305 #define B_ESPI_PCR_PCERR_PCURRE BIT25 ///< Peripheral Channel Unsupported Request Reporting Enable
306 #define B_ESPI_PCR_PCERR_PCRMTARE (BIT27 | BIT26) ///< Peripheral Channel Received Target or Target Abort Reporting bits
307 #define N_ESPI_PCR_PCERR_PCRMTARE 26 ///< Peripheral Channel Received Target or Target Abort Reporting bit position
308 #define V_ESPI_PCR_PCERR_PCRMTARE_SERR 2 ///< Enable RMA or RTA Reporting as SERR
309 #define R_ESPI_PCR_PCERR_SLV1 0x4024 ///< Peripheral Channel Error for Responder 1
310 #define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Responder 0
311 #define B_ESPI_PCR_VWERR_SLV0_VWHC10OE BIT25 ///< Requester HOST_C10 (Virtual Wire) to Responder Enable (VWHC10OE)
312 #define B_ESPI_PCR_VWERR_VWNFEE (BIT14 | BIT13) ///< Virtual Wire Channel Non-Fatal Error Reporting Enable bits
313 #define N_ESPI_PCR_VWERR_VWNFEE 13 ///< Virtual Wire Channel Non-Fatal Error Reporting Enable bit position
314 #define V_ESPI_PCR_VWERR_VWNFEE_SERR 2 ///< Enable Non-Fatal Error Reporting as SERR
315 #define B_ESPI_PCR_VWERR_VWFEE (BIT6 | BIT5) ///< Virtual Wire Channel Fatal Error Reporting Enable bits
316 #define N_ESPI_PCR_VWERR_VWFEE 5 ///< Virtual Wire Channel Fatal Error Reporting Enable bit position
317 #define V_ESPI_PCR_VWERR_VWFEE_SERR 2 ///< Enable Fatal Error Reporting as SERR
318 #define R_ESPI_PCR_VWERR_SLV1 0x4034 ///< Virtual Wire Channel Error for Responder 1
319 #define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Responder 0
320 #define B_ESPI_PCR_FCERR_SLV0_FCFEE (BIT6 | BIT5) ///< Flash Access Channel Fatal Error Reporting Enable bits
321 #define N_ESPI_PCR_FCERR_SLV0_FCFEE 5 ///< Flash Access Channel Fatal Error Reporting bit position
322 #define V_ESPI_PCR_FCERR_SLV0_FCFEE_SERR 2 ///< Enable Fatal Error Reporting as SERR
323 #define B_ESPI_PCR_FCERR_SLV0_FCNFEE (BIT14 | BIT13) ///< Flash Access Channel Non-Fatal Error Reporting Enable bits
324 #define N_ESPI_PCR_FCERR_SLV0_FCNFEE 13 ///< Flash Access Channel Non-Fatal Error Reporting Enable bit position
325 #define V_ESPI_PCR_FCERR_SLV0_FCNFEE_SERR 2 ///< Enable Non-Fatal Error Reporting as SERR
326 #define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blocked (SAFBLK)
327 #define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits
328 #define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position
329 #define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI
330 #define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal Error Status
331 #define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
332 #define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position
333 #define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI
334 #define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error Status
335 #define S_ESPI_PCR_XERR 4 ///< Channel register sizes
336 #define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
337 #define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Error for Responder 0
338 #define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Error for Responder 0 register size
339 #define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Responder Channel Recovery Required
340 #define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
341 #define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
342 #define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
343 #define V_ESPI_PCR_LNKERR_SLV0_LFER1E_SERR 2 ///< Enable Fatal Error Type 1 Reporting as SERR
344 #define B_ESPI_PCR_LNKERR_SLV1_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
345 #define N_ESPI_PCR_LNKERR_SLV1_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
346 #define V_ESPI_PCR_LNKERR_SLV1_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
347 #define V_ESPI_PCR_LNKERR_SLV1_LFER1E_SERR 2 ///< Enable Fatal Error Type 1 Reporting as SERR
348 #define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status
349 #define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Error for Responder 1
350 #define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
351 #define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
352 #define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
353 #define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
354
355 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsSmbus.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
Macros
PchRegsSmbus.h File Reference

Register names for PCH Smbus Device. More...

Go to the source code of this file.

Macros

#define | R_SMBUS_IO_HSTS 0x00
Host Status Register R/W.
#define | R_SMBUS_IO_HCTL 0x02
Host Control Register R/W.
#define | R_SMBUS_IO_HCMD 0x03
Host Command Register R/W.
#define | R_SMBUS_IO_TSA 0x04
Transmit Target Address Register R/W.
#define | R_SMBUS_IO_HD0 0x05
Data 0 Register R/W.
#define | R_SMBUS_IO_HD1 0x06
Data 1 Register R/W.
#define | R_SMBUS_IO_HBD 0x07
Host Block Data Register R/W.
#define | R_SMBUS_IO_PEC 0x08
Packet Error Check Data Register R/W.
#define | R_SMBUS_IO_RSA 0x09
Receive Slave Address Register R/W.
#define | R_SMBUS_IO_SD 0x0A
Receive Slave Data Register R/W.
#define | R_SMBUS_IO_AUXS 0x0C
Auxiliary Status Register R/WC.
#define | B_SMBUS_IO_STCO 0x02
SMBus TCO Mode.
#define | R_SMBUS_IO_AUXC 0x0D
Auxiliary Control Register R/W.
#define | R_SMBUS_IO_SMLC 0x0E
SMLINK Pin Control Register R/W.
#define | R_SMBUS_IO_SMBC 0x0F
SMBus Pin Control Register R/W.
#define | R_SMBUS_IO_SSTS 0x10
Target Status Register R/WC.
#define | R_SMBUS_IO_SCMD 0x11
Target Command Register R/W.
#define | R_SMBUS_IO_NDA 0x14
Notify Device Address Register RO.
#define | R_SMBUS_IO_NDLB 0x16
Notify Data Low Byte Register RO.
#define | R_SMBUS_IO_NDHB 0x17
Notify Data High Byte Register RO.
#define | R_SMBUS_PCR_TCOCFG 0x00
TCO Configuration register.
#define | B_SMBUS_PCR_TCOCFG_IE BIT7
TCO IRQ Enable.
#define | B_SMBUS_PCR_TCOCFG_IS (BIT2 | BIT1 | BIT0)
TCO IRQ Select.
#define | V_SMBUS_PCR_TCOCFG_IRQ_20 0x04
only if APIC enabled
#define | V_SMBUS_PCR_TCOCFG_IRQ_21 0x05
only if APIC enabled
#define | V_SMBUS_PCR_TCOCFG_IRQ_22 0x06
only if APIC enabled
#define | V_SMBUS_PCR_TCOCFG_IRQ_23 0x07
only if APIC enabled
#define | R_SMBUS_PCR_SMBTM 0x04
SMBus Test Mode.
#define | B_SMBUS_PCR_SMBTM_SMBCT BIT1
SMBus Counter.
#define | B_SMBUS_PCR_SMBTM_SMBDG BIT0
SMBus Deglitch.
#define | R_SMBUS_PCR_SCTM 0x08
Short Counter Test Mode.
#define | B_SMBUS_PCR_SCTM_SSU BIT31
Simulation Speed-Up.
#define | R_SMBUS_PCR_GC 0x0C
General Control.
#define | B_SMBUS_PCR_GC_FD BIT0
Function Disable.
#define | B_SMBUS_PCR_GC_SMBSCGE BIT2
SMB Static Clock Gating Enable.
#define | R_SMBUS_PCR_PCE 0x10
Power Control Enable.
#define | B_SMBUS_PCR_PCE_HAE BIT5
Hardware Autonomous Enable.

Detailed Description

Register names for PCH Smbus Device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchRegsSmbus.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchRegsSmbus.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
PchRegsSmbus.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH Smbus Device.
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _PCH_REGS_SMBUS_H_
65 #define _PCH_REGS_SMBUS_H_
66
67 //
68 // SMBus Controller Registers
69 //
70 #define R_SMBUS_CFG_BASE 0x20
71 #define V_SMBUS_CFG_BASE_SIZE (1 << 5)
72 #define B_SMBUS_CFG_BASE_BAR 0x0000FFE0
73 #define R_SMBUS_CFG_HOSTC 0x40
74 #define B_SMBUS_CFG_HOSTC_SPDWD BIT4
75 #define B_SMBUS_CFG_HOSTC_SSRESET BIT3
76 #define B_SMBUS_CFG_HOSTC_I2C_EN BIT2
77 #define B_SMBUS_CFG_HOSTC_SMI_EN BIT1
78 #define B_SMBUS_CFG_HOSTC_HST_EN BIT0
79 #define R_SMBUS_CFG_TCOBASE 0x50
80 #define B_SMBUS_CFG_TCOBASE_BAR 0x0000FFE0
81 #define R_SMBUS_CFG_TCOCTL 0x54
82 #define B_SMBUS_CFG_TCOCTL_TCO_BASE_EN BIT8
83 #define B_SMBUS_CFG_TCOCTL_TCO_BASE_LOCK BIT0
84 #define R_SMBUS_CFG_64 0x64
85 #define R_SMBUS_CFG_80 0x80
86
87 //
88 // SMBus I/O Registers
89 //
90 #define R_SMBUS_IO_HSTS 0x00 ///< Host Status Register R/W
91 #define B_SMBUS_IO_HBSY 0x01
92 #define B_SMBUS_IO_INTR 0x02
93 #define B_SMBUS_IO_DERR 0x04
94 #define B_SMBUS_IO_BERR 0x08
95 #define B_SMBUS_IO_FAIL 0x10
96 #define B_SMBUS_IO_SMBALERT_STS 0x20
97 #define B_SMBUS_IO_IUS 0x40
98 #define B_SMBUS_IO_BYTE_DONE_STS 0x80
99 #define B_SMBUS_IO_ERROR (B_SMBUS_IO_DERR | B_SMBUS_IO_BERR | B_SMBUS_IO_FAIL)
100 #define B_SMBUS_IO_HSTS_ALL 0xFF
101 #define R_SMBUS_IO_HCTL 0x02 ///< Host Control Register R/W
102 #define B_SMBUS_IO_INTREN 0x01
103 #define B_SMBUS_IO_KILL 0x02
104 #define B_SMBUS_IO_SMB_CMD 0x1C
105 #define V_SMBUS_IO_SMB_CMD_QUICK 0x00
106 #define V_SMBUS_IO_SMB_CMD_BYTE 0x04
107 #define V_SMBUS_IO_SMB_CMD_BYTE_DATA 0x08
108 #define V_SMBUS_IO_SMB_CMD_WORD_DATA 0x0C
109 #define V_SMBUS_IO_SMB_CMD_PROCESS_CALL 0x10
110 #define V_SMBUS_IO_SMB_CMD_BLOCK 0x14
111 #define V_SMBUS_IO_SMB_CMD_IIC_READ 0x18
112 #define V_SMBUS_IO_SMB_CMD_BLOCK_PROCESS 0x1C
113 #define B_SMBUS_IO_LAST_BYTE 0x20
114 #define B_SMBUS_IO_START 0x40
115 #define B_SMBUS_IO_PEC_EN 0x80
116 #define R_SMBUS_IO_HCMD 0x03 ///< Host Command Register R/W
117 #define R_SMBUS_IO_TSA 0x04 ///< Transmit Target Address Register R/W
118 #define B_SMBUS_IO_RW_SEL 0x01
119 #define B_SMBUS_IO_READ 0x01 // RW
120 #define B_SMBUS_IO_WRITE 0x00 // RW
121 #define B_SMBUS_IO_ADDRESS 0xFE
122 #define R_SMBUS_IO_HD0 0x05 ///< Data 0 Register R/W
123 #define R_SMBUS_IO_HD1 0x06 ///< Data 1 Register R/W
124 #define R_SMBUS_IO_HBD 0x07 ///< Host Block Data Register R/W
125 #define R_SMBUS_IO_PEC 0x08 ///< Packet Error Check Data Register R/W
126 #define R_SMBUS_IO_RSA 0x09 ///< Receive Slave Address Register R/W
127 #define B_SMBUS_IO_DEV_ADDR 0x7F
128 #define R_SMBUS_IO_SD 0x0A ///< Receive Slave Data Register R/W
129 #define R_SMBUS_IO_AUXS 0x0C ///< Auxiliary Status Register R/WC
130 #define B_SMBUS_IO_CRCE 0x01
131 #define B_SMBUS_IO_STCO 0x02 ///< SMBus TCO Mode
132 #define R_SMBUS_IO_AUXC 0x0D ///< Auxiliary Control Register R/W
133 #define B_SMBUS_IO_AAC 0x01
134 #define B_SMBUS_IO_E32B 0x02
135 #define R_SMBUS_IO_SMLC 0x0E ///< SMLINK Pin Control Register R/W
136 #define B_SMBUS_IO_SMLINK0_CUR_STS 0x01
137 #define B_SMBUS_IO_SMLINK1_CUR_STS 0x02
138 #define B_SMBUS_IO_SMLINK_CLK_CTL 0x04
139 #define R_SMBUS_IO_SMBC 0x0F ///< SMBus Pin Control Register R/W
140 #define B_SMBUS_IO_SMBCLK_CUR_STS 0x01
141 #define B_SMBUS_IO_SMBDATA_CUR_STS 0x02
142 #define B_SMBUS_IO_SMBCLK_CTL 0x04
143 #define R_SMBUS_IO_SSTS 0x10 ///< Target Status Register R/WC
144 #define B_SMBUS_IO_HOST_NOTIFY_STS 0x01
145 #define R_SMBUS_IO_SCMD 0x11 ///< Target Command Register R/W
146 #define B_SMBUS_IO_HOST_NOTIFY_INTREN 0x01
147 #define B_SMBUS_IO_HOST_NOTIFY_WKEN 0x02
148 #define B_SMBUS_IO_SMBALERT_DIS 0x04
149 #define R_SMBUS_IO_NDA 0x14 ///< Notify Device Address Register RO
150 #define B_SMBUS_IO_DEVICE_ADDRESS 0xFE
151 #define R_SMBUS_IO_NDLB 0x16 ///< Notify Data Low Byte Register RO
152 #define R_SMBUS_IO_NDHB 0x17 ///< Notify Data High Byte Register RO
153
154 //
155 // SMBus Private Config Registers
156 // (PID:SMB)
157 //
158 #define R_SMBUS_PCR_TCOCFG 0x00 ///< TCO Configuration register
159 #define B_SMBUS_PCR_TCOCFG_IE BIT7 ///< TCO IRQ Enable
160 #define B_SMBUS_PCR_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///< TCO IRQ Select
161 #define V_SMBUS_PCR_TCOCFG_IRQ_9 0x00
162 #define V_SMBUS_PCR_TCOCFG_IRQ_10 0x01
163 #define V_SMBUS_PCR_TCOCFG_IRQ_11 0x02
164 #define V_SMBUS_PCR_TCOCFG_IRQ_20 0x04 ///< only if APIC enabled
165 #define V_SMBUS_PCR_TCOCFG_IRQ_21 0x05 ///< only if APIC enabled
166 #define V_SMBUS_PCR_TCOCFG_IRQ_22 0x06 ///< only if APIC enabled
167 #define V_SMBUS_PCR_TCOCFG_IRQ_23 0x07 ///< only if APIC enabled
168 #define R_SMBUS_PCR_SMBTM 0x04 ///< SMBus Test Mode
169 #define B_SMBUS_PCR_SMBTM_SMBCT BIT1 ///< SMBus Counter
170 #define B_SMBUS_PCR_SMBTM_SMBDG BIT0 ///< SMBus Deglitch
171 #define R_SMBUS_PCR_SCTM 0x08 ///< Short Counter Test Mode
172 #define B_SMBUS_PCR_SCTM_SSU BIT31 ///< Simulation Speed-Up
173 #define R_SMBUS_PCR_GC 0x0C ///< General Control
174 #define B_SMBUS_PCR_GC_FD BIT0 ///< Function Disable
175 #define B_SMBUS_PCR_GC_SMBSCGE BIT2 ///< SMB Static Clock Gating Enable
176 #define R_SMBUS_PCR_PCE 0x10 ///< Power Control Enable
177 #define B_SMBUS_PCR_PCE_HAE BIT5 ///< Hardware Autonomous Enable
178
179 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchResetPlatformSpecific.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchResetPlatformSpecific.h File Reference

PCH Reset Platform Specific definitions. More...

Go to the source code of this file.

Detailed Description

PCH Reset Platform Specific definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchResetPlatformSpecific.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchResetPlatformSpecific.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
PchResetPlatformSpecific.h
Go to the documentation of this file.
1 /** @file
2 PCH Reset Platform Specific definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_
36 #define _PCH_RESET_PLATFORM_SPECIFIC_H_
37
38 #define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET"
39 #define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) / sizeof (UINT16))
40
41 extern EFI_GUID gPchGlobalResetGuid;
42
43 typedef struct _RESET_DATA {
44 CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH];
45 EFI_GUID Guid;
46 } PCH_RESET_DATA;
47
48 #endif // _PCH_RESET_PLATFORM_SPECIFIC_H_
49
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmiDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Macros | Typedefs
PchSmiDispatch.h File Reference

APIs of PCH SMI Dispatch Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_SMI_DISPATCH_PROTOCOL
Interface structure for PCH specific SMIs Dispatch Protocol The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs. More...

Macros

#define PCH_SMI_DISPATCH_REVISION 1
PCH SMI dispatch revision number. More...

Typedefs

typedef VOID(* | PCH_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)
Callback function for an PCH SMI handler dispatch. More...
typedef EFI_STATUS(* | PCH_SMI_DISPATCH_REGISTER) (IN PCH_SMI_DISPATCH_PROTOCOL *This, IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for specific PCH SMI dispatch event. More...
typedef EFI_STATUS(* | PCH_SMI_DISPATCH_UNREGISTER) (IN PCH_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent SMM driver. More...

Detailed Description

APIs of PCH SMI Dispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchSmiDispatch.h.

Macro Definition Documentation

◆ PCH_SMI_DISPATCH_REVISION

#define PCH_SMI_DISPATCH_REVISION 1

PCH SMI dispatch revision number.

Revision 1: Initial version

Definition at line 158 of file PchSmiDispatch.h.

Typedef Documentation

◆ PCH_SMI_DISPATCH_CALLBACK

typedef VOID( * PCH_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)

Callback function for an PCH SMI handler dispatch.

Parameters
[in] DispatchHandle The unique handle assigned to this handler by register function.

Definition at line 59 of file PchSmiDispatch.h.

◆ PCH_SMI_DISPATCH_REGISTER

typedef EFI_STATUS( * PCH_SMI_DISPATCH_REGISTER) (IN PCH_SMI_DISPATCH_PROTOCOL *This, IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)

Register a child SMI source dispatch function for specific PCH SMI dispatch event.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchFunction | Pointer to dispatch function to be invoked for this SMI source
[out] | DispatchHandle | Handle of dispatch function, for when interfacing with the parent SMM driver.
Return values
EFI_SUCCESS | The dispatch function has been successfully registered and the SMI source has been enabled.
EFI_DEVICE_ERROR | The driver was unable to enable the SMI source.
EFI_OUT_OF_RESOURCES | Not enough memory (system or SMM) to manage this child.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 80 of file PchSmiDispatch.h.

◆ PCH_SMI_DISPATCH_UNREGISTER

typedef EFI_STATUS( * PCH_SMI_DISPATCH_UNREGISTER) (IN PCH_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

Unregister a child SMI source dispatch function with a parent SMM driver.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchHandle | Handle of dispatch function to deregister.
Return values
EFI_SUCCESS | The dispatch function has been successfully unregistered and the SMI source has been disabled if there are no other registered child dispatch functions for this SMI source.
EFI_INVALID_PARAMETER | Handle is invalid.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 101 of file PchSmiDispatch.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmiDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchSmiDispatch.h
Go to the documentation of this file.
1 /** @file
2 APIs of PCH SMI Dispatch Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_
36 #define _PCH_SMI_DISPATCH_PROTOCOL_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gPchSmiDispatchProtocolGuid;
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL;
47
48 //
49 // Member functions
50 //
51
52 /**
53 Callback function for an PCH SMI handler dispatch.
54
55 @param[in] DispatchHandle The unique handle assigned to this handler by register function.
56
57 **/
58 typedef
59 VOID
60 (EFIAPI *PCH_SMI_DISPATCH_CALLBACK) (
61 IN EFI_HANDLE DispatchHandle
62 );
63
64 /**
65 Register a child SMI source dispatch function for specific PCH SMI dispatch event.
66
67 @param[in] This Protocol instance pointer.
68 @param[in] DispatchFunction Pointer to dispatch function to be invoked for
69 this SMI source
70 @param[out] DispatchHandle Handle of dispatch function, for when interfacing
71 with the parent SMM driver.
72
73 @retval EFI_SUCCESS The dispatch function has been successfully
74 registered and the SMI source has been enabled.
75 @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
76 @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
77 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
78 **/
79 typedef
80 EFI_STATUS
81 (EFIAPI *PCH_SMI_DISPATCH_REGISTER) (
82 IN PCH_SMI_DISPATCH_PROTOCOL *This,
83 IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction,
84 OUT EFI_HANDLE *DispatchHandle
85 );
86
87 /**
88 Unregister a child SMI source dispatch function with a parent SMM driver
89
90 @param[in] This Protocol instance pointer.
91 @param[in] DispatchHandle Handle of dispatch function to deregister.
92
93 @retval EFI_SUCCESS The dispatch function has been successfully
94 unregistered and the SMI source has been disabled
95 if there are no other registered child dispatch
96 functions for this SMI source.
97 @retval EFI_INVALID_PARAMETER Handle is invalid.
98 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
99 **/
100 typedef
101 EFI_STATUS
102 (EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) (
103 IN PCH_SMI_DISPATCH_PROTOCOL *This,
104 IN EFI_HANDLE DispatchHandle
105 );
106
107 /**
108 Interface structure for PCH specific SMIs Dispatch Protocol
109 The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs.
110 It contains legacy SMIs and new PCH SMI types like:
111 SerialIrq, McSmi, Smbus, ...
112 **/
113 struct _PCH_SMI_DISPATCH_PROTOCOL {
114 /**
115 This member specifies the revision of this structure. This field is used to
116 indicate backwards compatible changes to the protocol.
117 **/
118 UINT8 Revision;
119 /**
120 Smi unregister function for PCH SMI DISPATCH PROTOCOL.
121 **/
122 PCH_SMI_DISPATCH_UNREGISTER UnRegister;
123 /**
124 SerialIrq
125 The event is triggered while the SMI# was caused by the SERIRQ decoder.
126 **/
127 PCH_SMI_DISPATCH_REGISTER SerialIrqRegister;
128 /**
129 McSmi
130 The event is triggered if there has been an access to the power management
131 microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit
132 in the LPC Bridge I/O Enables configuration register is 1 .
133 **/
134 PCH_SMI_DISPATCH_REGISTER McSmiRegister;
135 /**
136 SmBus
137 The event is triggered while the SMI# was caused by:
138 1. The SMBus target receiving a message that an SMI# should be caused, or
139 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
140 SMBALERT_DIS bit is cleared, or
141 3. The SMBus target receiving a Host Notify message and the HOST_NOTIFY_INTREN and
142 the SMB_SMI_EN bits are set, or
143 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state.
144 **/
145 PCH_SMI_DISPATCH_REGISTER SmbusRegister;
146 /**
147 SPI Asynchronous
148 When registered, the flash controller will generate an SMI when it blocks a BIOS write or erase.
149 **/
150 PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister;
151 };
152
153 /**
154 PCH SMI dispatch revision number
155
156 Revision 1: Initial version
157 **/
158 #define PCH_SMI_DISPATCH_REVISION 1
159
160 #endif
_PCH_SMI_DISPATCH_PROTOCOL::SmbusRegister
PCH_SMI_DISPATCH_REGISTER SmbusRegister
SmBus The event is triggered while the SMI# was caused by:
Definition: PchSmiDispatch.h:145
_PCH_SMI_DISPATCH_PROTOCOL
Interface structure for PCH specific SMIs Dispatch Protocol The PCH SMI DISPATCH PROTOCOL provides th...
Definition: PchSmiDispatch.h:113
PCH_SMI_DISPATCH_REGISTER
EFI_STATUS(* PCH_SMI_DISPATCH_REGISTER)(IN PCH_SMI_DISPATCH_PROTOCOL *This, IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for specific PCH SMI dispatch event.
Definition: PchSmiDispatch.h:81
_PCH_SMI_DISPATCH_PROTOCOL::UnRegister
PCH_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH SMI DISPATCH PROTOCOL.
Definition: PchSmiDispatch.h:122
_PCH_SMI_DISPATCH_PROTOCOL::McSmiRegister
PCH_SMI_DISPATCH_REGISTER McSmiRegister
McSmi The event is triggered if there has been an access to the power management microcontroller rang...
Definition: PchSmiDispatch.h:134
PCH_SMI_DISPATCH_CALLBACK
VOID(* PCH_SMI_DISPATCH_CALLBACK)(IN EFI_HANDLE DispatchHandle)
Callback function for an PCH SMI handler dispatch.
Definition: PchSmiDispatch.h:60
_PCH_SMI_DISPATCH_PROTOCOL::SpiAsyncRegister
PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister
SPI Asynchronous When registered, the flash controller will generate an SMI when it blocks a BIOS wri...
Definition: PchSmiDispatch.h:150
_PCH_SMI_DISPATCH_PROTOCOL::SerialIrqRegister
PCH_SMI_DISPATCH_REGISTER SerialIrqRegister
SerialIrq The event is triggered while the SMI# was caused by the SERIRQ decoder.
Definition: PchSmiDispatch.h:127
PCH_SMI_DISPATCH_UNREGISTER
EFI_STATUS(* PCH_SMI_DISPATCH_UNREGISTER)(IN PCH_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent SMM driver.
Definition: PchSmiDispatch.h:102
_PCH_SMI_DISPATCH_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: PchSmiDispatch.h:118
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmControlLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Functions
PchSmmControlLib.h File Reference

Header file for SMM Control PEI Library. More...

Go to the source code of this file.

Functions

EFI_STATUS PchSmmControlInit (VOID)
This function install PEI SMM Control PPI. More...

Detailed Description

Header file for SMM Control PEI Library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file PchSmmControlLib.h.

Function Documentation

◆ PchSmmControlInit()

EFI_STATUS PchSmmControlInit ( VOID )

This function install PEI SMM Control PPI.

Return values
EFI_STATUS Results of the installation of the SMM Control PPI
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmControlLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
PchSmmControlLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMM Control PEI Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _PCH_SMM_CONTROL_LIB_H_
36 #define _PCH_SMM_CONTROL_LIB_H_
37
38 /**
39 This function install PEI SMM Control PPI
40
41 @retval EFI_STATUS Results of the installation of the SMM Control PPI
42 **/
43 EFI_STATUS
44 EFIAPI
45 PchSmmControlInit (
46 VOID
47 );
48
49 #endif
PchSmmControlInit
EFI_STATUS PchSmmControlInit(VOID)
This function install PEI SMM Control PPI.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmIoTrapControl.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Typedefs
PchSmmIoTrapControl.h File Reference

PCH SMM IO Trap Control Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL
Interface structure for the SMM IO trap pause and resume protocol This protocol provides the functions to runtime control the IoTrap SMI enabled/disable. More...

Typedefs

typedef EFI_STATUS(* PCH_SMM_IO_TRAP_CONTROL_FUNCTION) (IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
The Prototype of Pause and Resume IoTrap callback function. More...

Detailed Description

PCH SMM IO Trap Control Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2013 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchSmmIoTrapControl.h.

Typedef Documentation

◆ PCH_SMM_IO_TRAP_CONTROL_FUNCTION

typedef EFI_STATUS( * PCH_SMM_IO_TRAP_CONTROL_FUNCTION) (IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

The Prototype of Pause and Resume IoTrap callback function.

Parameters
[in] | This | Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance.
[in] | DispatchHandle | Handle of the child service to change state.
Return values
EFI_SUCCESS | This operation is complete.
EFI_INVALID_PARAMETER | The DispatchHandle is invalid.
EFI_ACCESS_DENIED | The SMI status is alrady PAUSED/RESUMED.

Definition at line 68 of file PchSmmIoTrapControl.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmIoTrapControl.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchSmmIoTrapControl.h
Go to the documentation of this file.
1 /** @file
2 PCH SMM IO Trap Control Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2013 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_SMM_IO_TRAP_CONTROL_H_
36 #define _PCH_SMM_IO_TRAP_CONTROL_H_
37
38
39 //
40 // Extern the GUID for protocol users.
41 //
42 extern EFI_GUID gPchSmmIoTrapControlGuid;
43
44 //
45 // Forward reference for ANSI C compatibility
46 //
47 typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL;
48
49 //
50 // Related Definitions
51 //
52
53 //
54 // Member functions
55 //
56
57 /**
58 The Prototype of Pause and Resume IoTrap callback function.
59
60 @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance.
61 @param[in] DispatchHandle Handle of the child service to change state.
62
63 @retval EFI_SUCCESS This operation is complete.
64 @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.
65 @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED.
66 **/
67 typedef
68 EFI_STATUS
69 (EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) (
70 IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This,
71 IN EFI_HANDLE DispatchHandle
72 );
73
74 /**
75 Interface structure for the SMM IO trap pause and resume protocol
76 This protocol provides the functions to runtime control the IoTrap SMI enabled/disable.
77 This applys the capability to the DispatchHandle which returned by IoTrap callback
78 registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0.
79 Besides, when S3 resuem, it only restores the state of IoTrap callback registration.
80 The Paused/Resume state won't be restored after S3 resume.
81 **/
82 struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL {
83 /**
84 This runtime pauses a registered IoTrap handler.
85 **/
86 PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause;
87 /**
88 This runtime resumes a registered IoTrap handler.
89 **/
90 PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume;
91 };
92
93 #endif
_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL::Pause
PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause
This runtime pauses a registered IoTrap handler.
Definition: PchSmmIoTrapControl.h:86
_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL
Interface structure for the SMM IO trap pause and resume protocol This protocol provides the function...
Definition: PchSmmIoTrapControl.h:82
_PCH_SMM_IO_TRAP_CONTROL_PROTOCOL::Resume
PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume
This runtime resumes a registered IoTrap handler.
Definition: PchSmmIoTrapControl.h:90
PCH_SMM_IO_TRAP_CONTROL_FUNCTION
EFI_STATUS(* PCH_SMM_IO_TRAP_CONTROL_FUNCTION)(IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
The Prototype of Pause and Resume IoTrap callback function.
Definition: PchSmmIoTrapControl.h:69
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmPeriodicTimerControl.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Typedefs
PchSmmPeriodicTimerControl.h File Reference

PCH SMM Periodic Timer Control Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
Interface structure for the SMM PERIODIC TIMER pause and resume protocol This protocol provides the functions to runtime control the SM periodic timer enabled/disable. More...

Typedefs

typedef EFI_STATUS(* PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) (IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
The Prototype of Pause and Resume SMM PERIODIC TIMER function. More...

Detailed Description

PCH SMM Periodic Timer Control Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchSmmPeriodicTimerControl.h.

Typedef Documentation

◆ PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION

typedef EFI_STATUS( * PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) (IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

The Prototype of Pause and Resume SMM PERIODIC TIMER function.

Parameters
[in] | This | Pointer to the PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance.
[in] | DispatchHandle | Handle of the child service to change state.
Return values
EFI_SUCCESS | This operation is complete.
EFI_INVALID_PARAMETER | The DispatchHandle is invalid.
EFI_ACCESS_DENIED | The SMI status is alrady PAUSED/RESUMED.

Definition at line 68 of file PchSmmPeriodicTimerControl.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchSmmPeriodicTimerControl.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchSmmPeriodicTimerControl.h
Go to the documentation of this file.
1 /** @file
2 PCH SMM Periodic Timer Control Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
36 #define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
37
38
39 //
40 // Extern the GUID for protocol users.
41 //
42 extern EFI_GUID gPchSmmPeriodicTimerControlGuid;
43
44 //
45 // Forward reference for ANSI C compatibility
46 //
47 typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL;
48
49 //
50 // Related Definitions
51 //
52
53 //
54 // Member functions
55 //
56
57 /**
58 The Prototype of Pause and Resume SMM PERIODIC TIMER function.
59
60 @param[in] This Pointer to the PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance.
61 @param[in] DispatchHandle Handle of the child service to change state.
62
63 @retval EFI_SUCCESS This operation is complete.
64 @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.
65 @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED.
66 **/
67 typedef
68 EFI_STATUS
69 (EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) (
70 IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This,
71 IN EFI_HANDLE DispatchHandle
72 );
73
74 /**
75 Interface structure for the SMM PERIODIC TIMER pause and resume protocol
76 This protocol provides the functions to runtime control the SM periodic timer enabled/disable.
77 This applies the capability to the DispatchHandle which returned by SMM periodic timer callback
78 registration.
79 Besides, when S3 resume, it only restores the state of callback registration.
80 The Paused/Resume state won't be restored after S3 resume.
81 **/
82 struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL {
83 /**
84 This runtime pauses the registered periodic timer handler.
85 **/
86 PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause;
87 /**
88 This runtime resumes the registered periodic timer handler.
89 **/
90 PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume;
91 };
92
93 #endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL
Interface structure for the SMM PERIODIC TIMER pause and resume protocol This protocol provides the f...
Definition: PchSmmPeriodicTimerControl.h:82
_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL::Pause
PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause
This runtime pauses the registered periodic timer handler.
Definition: PchSmmPeriodicTimerControl.h:86
_PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL::Resume
PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume
This runtime resumes the registered periodic timer handler.
Definition: PchSmmPeriodicTimerControl.h:90
PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION
EFI_STATUS(* PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION)(IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
The Prototype of Pause and Resume SMM PERIODIC TIMER function.
Definition: PchSmmPeriodicTimerControl.h:69
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchTcoSmiDispatch.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Classes | Macros | Typedefs
PchTcoSmiDispatch.h File Reference

APIs of PCH TCO SMI Dispatch Protocol. More...

Go to the source code of this file.

Classes

struct _PCH_TCO_SMI_DISPATCH_PROTOCOL
Interface structure for PCH TCO SMIs Dispatch Protocol The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs. More...

Macros

#define PCH_TCO_SMI_DISPATCH_REVISION 2
PCH TCO SMI dispatch revision number. More...

Typedefs

typedef VOID(* | PCH_TCO_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)
Callback function for an PCH TCO SMI handler dispatch. More...
typedef EFI_STATUS(* | PCH_TCO_SMI_DISPATCH_REGISTER) (IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH TCO SMI events. More...
typedef EFI_STATUS(* | PCH_TCO_SMI_DISPATCH_UNREGISTER) (IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent TCO SMM driver. More...

Detailed Description

APIs of PCH TCO SMI Dispatch Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PchTcoSmiDispatch.h.

Macro Definition Documentation

◆ PCH_TCO_SMI_DISPATCH_REVISION

#define PCH_TCO_SMI_DISPATCH_REVISION 2

PCH TCO SMI dispatch revision number.

Revision 1: Initial version Revision 2: Add NEWCENTURY support

Definition at line 176 of file PchTcoSmiDispatch.h.

Typedef Documentation

◆ PCH_TCO_SMI_DISPATCH_CALLBACK

typedef VOID( * PCH_TCO_SMI_DISPATCH_CALLBACK) (IN EFI_HANDLE DispatchHandle)

Callback function for an PCH TCO SMI handler dispatch.

Parameters
[in] DispatchHandle The unique handle assigned to this handler by register function.

Definition at line 59 of file PchTcoSmiDispatch.h.

◆ PCH_TCO_SMI_DISPATCH_REGISTER

typedef EFI_STATUS( * PCH_TCO_SMI_DISPATCH_REGISTER) (IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)

Register a child SMI source dispatch function for PCH TCO SMI events.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchFunction | Pointer to dispatch function to be invoked for this SMI source
[out] | DispatchHandle | Handle of dispatch function, for when interfacing with the parent SMM driver.
Return values
EFI_SUCCESS | The dispatch function has been successfully registered and the SMI source has been enabled.
EFI_DEVICE_ERROR | The driver was unable to enable the SMI source.
EFI_OUT_OF_RESOURCES | Not enough memory (system or SMM) to manage this child.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 80 of file PchTcoSmiDispatch.h.

◆ PCH_TCO_SMI_DISPATCH_UNREGISTER

typedef EFI_STATUS( * PCH_TCO_SMI_DISPATCH_UNREGISTER) (IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)

Unregister a child SMI source dispatch function with a parent TCO SMM driver.

Parameters
[in] | This | Protocol instance pointer.
[in] | DispatchHandle | Handle of dispatch function to deregister.
Return values
EFI_SUCCESS | The dispatch function has been successfully unregistered and the SMI source has been disabled if there are no other registered child dispatch functions for this SMI source.
EFI_INVALID_PARAMETER | Handle is invalid.
EFI_ACCESS_DENIED | Return access denied if the EndOfDxe event has been triggered

Definition at line 101 of file PchTcoSmiDispatch.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchTcoSmiDispatch.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
PchTcoSmiDispatch.h
Go to the documentation of this file.
1 /** @file
2 APIs of PCH TCO SMI Dispatch Protocol.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_
36 #define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gPchTcoSmiDispatchProtocolGuid;
42
43 //
44 // Forward reference for ANSI C compatibility
45 //
46 typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL;
47
48 //
49 // Member functions
50 //
51
52 /**
53 Callback function for an PCH TCO SMI handler dispatch.
54
55 @param[in] DispatchHandle The unique handle assigned to this handler by register function.
56
57 **/
58 typedef
59 VOID
60 (EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) (
61 IN EFI_HANDLE DispatchHandle
62 );
63
64 /**
65 Register a child SMI source dispatch function for PCH TCO SMI events.
66
67 @param[in] This Protocol instance pointer.
68 @param[in] DispatchFunction Pointer to dispatch function to be invoked for
69 this SMI source
70 @param[out] DispatchHandle Handle of dispatch function, for when interfacing
71 with the parent SMM driver.
72
73 @retval EFI_SUCCESS The dispatch function has been successfully
74 registered and the SMI source has been enabled.
75 @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
76 @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
77 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
78 **/
79 typedef
80 EFI_STATUS
81 (EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) (
82 IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,
83 IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction,
84 OUT EFI_HANDLE *DispatchHandle
85 );
86
87 /**
88 Unregister a child SMI source dispatch function with a parent TCO SMM driver
89
90 @param[in] This Protocol instance pointer.
91 @param[in] DispatchHandle Handle of dispatch function to deregister.
92
93 @retval EFI_SUCCESS The dispatch function has been successfully
94 unregistered and the SMI source has been disabled
95 if there are no other registered child dispatch
96 functions for this SMI source.
97 @retval EFI_INVALID_PARAMETER Handle is invalid.
98 @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
99 **/
100 typedef
101 EFI_STATUS
102 (EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) (
103 IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,
104 IN EFI_HANDLE DispatchHandle
105 );
106
107 /**
108 Interface structure for PCH TCO SMIs Dispatch Protocol
109 The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs.
110 It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, and BiowWp.
111 **/
112 struct _PCH_TCO_SMI_DISPATCH_PROTOCOL {
113 /**
114 This member specifies the revision of this structure. This field is used to
115 indicate backwards compatible changes to the protocol.
116 **/
117 UINT8 Revision;
118 /**
119 Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL.
120 **/
121 PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister;
122 /**
123 Mch
124 The event is triggered when PCH received a DMI special cycle message using DMI indicating that
125 it wants to cause an SMI.
126 The software must read the processor to determine the reason for the SMI.
127 **/
128 PCH_TCO_SMI_DISPATCH_REGISTER MchRegister;
129 /**
130 TcoTimeout
131 The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reaching 0.
132 **/
133 PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister;
134 /**
135 OsTco
136 The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h).
137 **/
138 PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister;
139 /**
140 Nmi
141 The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherwise have
142 caused an NMI (because NMI2SMI_EN is set)
143 **/
144 PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister;
145 /**
146 IntruderDectect
147 The event is triggered by PCH to indicate that an intrusion was detected.
148 **/
149 PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister;
150 /**
151 SpiBiosWp
152 This event is triggered when SMI# was caused by the TCO logic and
153 SPI flash controller asserted Synchronous SMI by BIOS lock enable set.
154 **/
155 PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister;
156 /**
157 LpcBiosWp
158 This event is triggered when SMI# was caused by the TCO logic and
159 LPC/eSPI BIOS lock enable set.
160 **/
161 PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister;
162 /**
163 NewCentury
164 This event is triggered when SMI# was caused by the TCO logic and
165 year of RTC date rolls over a century (99 to 00).
166 **/
167 PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister;
168 };
169
170 /**
171 PCH TCO SMI dispatch revision number
172
173 Revision 1: Initial version
174 Revision 2: Add NEWCENTURY support
175 **/
176 #define PCH_TCO_SMI_DISPATCH_REVISION 2
177
178 #endif
_PCH_TCO_SMI_DISPATCH_PROTOCOL::OsTcoRegister
PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister
OsTco The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOB...
Definition: PchTcoSmiDispatch.h:138
_PCH_TCO_SMI_DISPATCH_PROTOCOL::LpcBiosWpRegister
PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister
LpcBiosWp This event is triggered when SMI# was caused by the TCO logic and LPC/eSPI BIOS lock enable...
Definition: PchTcoSmiDispatch.h:161
PCH_TCO_SMI_DISPATCH_REGISTER
EFI_STATUS(* PCH_TCO_SMI_DISPATCH_REGISTER)(IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, OUT EFI_HANDLE *DispatchHandle)
Register a child SMI source dispatch function for PCH TCO SMI events.
Definition: PchTcoSmiDispatch.h:81
_PCH_TCO_SMI_DISPATCH_PROTOCOL::NewCenturyRegister
PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister
NewCentury This event is triggered when SMI# was caused by the TCO logic and year of RTC date rolls o...
Definition: PchTcoSmiDispatch.h:167
_PCH_TCO_SMI_DISPATCH_PROTOCOL::TcoTimeoutRegister
PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister
TcoTimeout The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reachin...
Definition: PchTcoSmiDispatch.h:133
_PCH_TCO_SMI_DISPATCH_PROTOCOL::IntruderDetRegister
PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister
IntruderDectect The event is triggered by PCH to indicate that an intrusion was detected.
Definition: PchTcoSmiDispatch.h:149
PCH_TCO_SMI_DISPATCH_UNREGISTER
EFI_STATUS(* PCH_TCO_SMI_DISPATCH_UNREGISTER)(IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, IN EFI_HANDLE DispatchHandle)
Unregister a child SMI source dispatch function with a parent TCO SMM driver.
Definition: PchTcoSmiDispatch.h:102
PCH_TCO_SMI_DISPATCH_CALLBACK
VOID(* PCH_TCO_SMI_DISPATCH_CALLBACK)(IN EFI_HANDLE DispatchHandle)
Callback function for an PCH TCO SMI handler dispatch.
Definition: PchTcoSmiDispatch.h:60
_PCH_TCO_SMI_DISPATCH_PROTOCOL::NmiRegister
PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister
Nmi The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherw...
Definition: PchTcoSmiDispatch.h:144
_PCH_TCO_SMI_DISPATCH_PROTOCOL::MchRegister
PCH_TCO_SMI_DISPATCH_REGISTER MchRegister
Mch The event is triggered when PCH received a DMI special cycle message using DMI indicating that it...
Definition: PchTcoSmiDispatch.h:128
_PCH_TCO_SMI_DISPATCH_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: PchTcoSmiDispatch.h:117
_PCH_TCO_SMI_DISPATCH_PROTOCOL
Interface structure for PCH TCO SMIs Dispatch Protocol The PCH TCO SMI DISPATCH PROTOCOL provides the...
Definition: PchTcoSmiDispatch.h:112
_PCH_TCO_SMI_DISPATCH_PROTOCOL::SpiBiosWpRegister
PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister
SpiBiosWp This event is triggered when SMI# was caused by the TCO logic and SPI flash controller asse...
Definition: PchTcoSmiDispatch.h:155
_PCH_TCO_SMI_DISPATCH_PROTOCOL::UnRegister
PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister
Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL.
Definition: PchTcoSmiDispatch.h:121
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
Classes | Enumerations
PcieConfig.h File Reference

PCIe Config Block. More...

#include <CpuPcieInfo.h>
Include dependency graph for PcieConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters. More...
struct | PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings. More...
struct | PCIE_COMMON_CONFIG
PCIe Common Config. More...
struct | PCIE_DEVICE_OVERRIDE
PCIe device table entry entry. More...

Enumerations

enum | PCIE_FORM_FACTOR
Specifies the form factor that the slot implements. More...
enum | PCIE_LINK_EQ_METHOD
enum | PCIE_LINK_EQ_MODE

Detailed Description

PCIe Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieConfig.h.

Enumeration Type Documentation

◆ PCIE_FORM_FACTOR

enum PCIE_FORM_FACTOR

Specifies the form factor that the slot implements.

For custom form factors that do not require any special handling please set PcieFormFactorOther.

Definition at line 103 of file PcieConfig.h.

◆ PCIE_LINK_EQ_METHOD

enum PCIE_LINK_EQ_METHOD
Enumerator
PcieLinkHardwareEq | Hardware is responsible for performing coefficient/preset search.
PcieLinkFixedEq | No coefficient/preset search is performed. Fixed values are used.

Definition at line 114 of file PcieConfig.h.

◆ PCIE_LINK_EQ_MODE

enum PCIE_LINK_EQ_MODE
Enumerator
PcieLinkEqPresetMode | Use presets during PCIe link equalization.
PcieLinkEqCoefficientMode | Use coefficients during PCIe link equalization.

Definition at line 119 of file PcieConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
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  • ConfigBlock
  • PcieRp
PcieConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIe Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_CONFIG_H_
36 #define _PCIE_CONFIG_H_
37 #include <CpuPcieInfo.h>
38
39 #define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
40 #define PCIE_LINK_EQ_PRESETS_MAX 11
41 extern EFI_GUID gPcieConfigGuid;
42
43 #pragma pack (push,1)
44
45 enum PCIE_COMPLETION_TIMEOUT {
46 PcieCompletionTO_Default,
47 PcieCompletionTO_50_100us,
48 PcieCompletionTO_1_10ms,
49 PcieCompletionTO_16_55ms,
50 PcieCompletionTO_65_210ms,
51 PcieCompletionTO_260_900ms,
52 PcieCompletionTO_1_3P5s,
53 PcieCompletionTO_4_13s,
54 PcieCompletionTO_17_64s,
55 PcieCompletionTO_Disabled
56 };
57
58 typedef enum {
59 PcieAuto,
60 PcieGen1,
61 PcieGen2,
62 PcieGen3,
63 PcieGen4,
64 PcieGen5
65 } PCIE_SPEED;
66
67 typedef enum {
68 PcieDisabled,
69 PcieL1SUB_1,
70 PcieL1SUB_1_2
71 }L1_SUBSTATES;
72
73 /**
74 Represent lane specific PCIe Gen3 equalization parameters.
75 **/
76 typedef struct {
77 UINT8 Cm; ///< Coefficient C-1
78 UINT8 Cp; ///< Coefficient C+1
79 UINT8 Rsvd0[2]; ///< Reserved bytes
80 } PCIE_EQ_PARAM;
81
82 typedef struct {
83 UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
84 UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
85 UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
86 UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
87 UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
88 UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
89 UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
90 UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
91 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
92 UINT8 ForceLtrOverride;
93 UINT16 RsvdByte1;
94 } PCIE_LTR_CONFIG;
95
96
97 /**
98 Specifies the form factor that the slot
99 implements. For custom form factors that
100 do not require any special handling please
101 set PcieFormFactorOther.
102 **/
103 typedef enum {
104 PcieFormFactorOther = 0,
105 PcieFormFactorCem,
106 PcieFormFactorMiniPci,
107 PcieFormFactorM2,
108 PcieFormFactorOcuLink,
109 PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
110 PcieFormFactorExpressCard,
111 PcieFormFactorU2 // Also known as SF-8639
112 } PCIE_FORM_FACTOR;
113
114 typedef enum {
115 PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
116 PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
117 } PCIE_LINK_EQ_METHOD;
118
119 typedef enum {
120 PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
121 PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
122 } PCIE_LINK_EQ_MODE;
123
124 typedef struct {
125 UINT32 PreCursor; ///< Pre-cursor coefficient
126 UINT32 PostCursor; ///< Post-cursor coefficient
127 } PCIE_LINK_EQ_COEFFICIENTS;
128
129 /**
130 PCIe Link EQ Platform Settings
131 **/
132 typedef struct {
133 UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
134 UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
135 /**
136 Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
137 If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
138 <b>0: Disabled</b>; 1: Enabled
139 **/
140 UINT8 LocalTransmitterOverrideEnable;
141 /**
142 Tells BIOS how many presets/coefficients should be used during link EQ.
143 Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
144 **/
145 UINT8 Ph3NumberOfPresetsOrCoefficients;
146
147 PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
148 UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
149 UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
150 UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
151 /**
152 Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
153 Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
154 Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
155 **/
156 UINT32 Ph2LocalTransmitterOverridePreset;
157 UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
158 UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
159 /**
160 PCIe Equalization Phase 3 Enable Control
161 - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
162 - Enabled (0x1) : Enable phase 3
163 **/
164 UINT8 EqPh3Bypass;
165 /**
166 PCIe Equalization Phase 2-3 Enable Control
167 - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
168 - Enabled (0x1) : Enable Phase 2 - Phase 3
169 **/
170 UINT8 EqPh23Bypass;
171 UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
172 } PCIE_LINK_EQ_PLATFORM_SETTINGS;
173
174 //Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
175 typedef struct {
176 UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
177 UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
178 UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
179 UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
180 //
181 // Error handlings
182 //
183 UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
184 UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
185 UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
186 UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
187 UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
188 UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
189 UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
190 UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
191 /**
192 Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
193 Changes Max Payload Size Supported field in Device Capabilities of the root port.
194 **/
195 UINT32 MaxPayload : 2;
196 UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
197 UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
198 /**
199 Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
200 Built-in is incompatible with hotplug-capable ports.
201 **/
202 UINT32 SlotImplemented : 1;
203 UINT32 PtmEnabled : 1; ///< Enables PTM capability
204 UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
205 UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
206 /**
207 Probe CLKREQ# signal before enabling CLKREQ# based power management.
208 Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
209 to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
210 In particular this helps to avoid issues with open-ended PCIe slots.
211 This is only applicable to non hot-plug ports.
212 <b>0: Disable</b>; 1: Enable.
213 **/
214 UINT32 ClkReqDetect : 1;
215 /**
216 Set if the slot supports manually operated retention latch.
217 **/
218 UINT32 MrlSensorPresent : 1;
219 UINT32 RelaxedOrder : 1;
220 UINT32 NoSnoop : 1;
221 ///
222 /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
223 ///
224 UINT32 EnablePeerMemoryWrite : 1;
225 ///
226 /// This member describes whether the PCI Express Clock Gating for each root port
227 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
228 ///
229 UINT32 ClockGating : 1;
230 ///
231 /// This member describes whether the PCI Express Power Gating for each root port
232 /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
233 ///
234 UINT32 PowerGating : 1;
235 UINT32 RsvdBits0 : 25; ///< Reserved bits.
236 /**
237 PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
238 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
239 **/
240 UINT8 Gen3EqPh3Method;
241 UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
242 UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
243 //
244 // Power Management
245 //
246 UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
247 UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
248 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
249 UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
250 UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
251 /**
252 <b>(Test)</b>
253 Forces LTR override to be permanent
254 The default way LTR override works is:
255 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
256 This settings allows force override of LTR mechanism. If it's enabled, then:
257 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
258 **/
259 PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
260 /**
261 The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
262 before assuming there is no device and potentially disabling the port.
263 It's assumed that the link will exit detect state before root port initialization (sufficient time
264 elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
265 if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
266 In case of non-common clock enabled the default timout is 15ms.
267 <b>Default: 0</b>
268 **/
269 UINT16 DetectTimeoutMs;
270 UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
271 UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
272 UINT8 LinkDownGpios;
273 ///
274 /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
275 ///
276 UINT8 OverrideEqualizationDefaults;
277 UINT8 Reserved[2];
278 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
279 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
280 PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
281 } PCIE_ROOT_PORT_COMMON_CONFIG;
282
283 /**
284 PCIe Common Config
285 @note This structure will be expanded to hold all common PCIe policies between SA and PCH
286 **/
287 typedef struct {
288 /**
289 RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
290 A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
291 BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
292 - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
293 This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
294 - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
295 That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
296 NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
297 In other words, it only affects ports that would become hidden because they have no device connected.
298 NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
299 be used when each one of root ports 1, 9, 17:
300 - is configured as PCIe and has correctly configured ClkReq signal, or
301 - does not own any mPhy lanes (they are configured as SATA or USB)
302 **/
303 UINT32 RpFunctionSwap : 1;
304 /**
305 Compliance Test Mode shall be enabled when using Compliance Load Board.
306 <b>0: Disable</b>, 1: Enable
307 **/
308 UINT32 ComplianceTestMode : 1;
309 UINT32 RsvdBits0 : 30; ///< Reserved bits
310 ///
311 /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
312 ///
313 UINT8 EnablePort8xhDecode;
314 UINT8 RsvdBytes0[3];
315 ///
316 /// List of coefficients used during equalization (applicable to both software and hardware EQ)
317 /// Deprecated Policy
318 ///
319 PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
320 } PCIE_COMMON_CONFIG;
321
322 typedef struct {
323 PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
324 PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
325 PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
326 } PCIE_COMMON_CONFIG2;
327
328
329 /**
330 PCIe device table entry entry
331
332 The PCIe device table is being used to override PCIe device ASPM settings.
333 To take effect table consisting of such entries must be instelled as PPI
334 on gPchPcieDeviceTablePpiGuid.
335 Last entry VendorId must be 0.
336 **/
337 typedef struct {
338 UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
339 UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
340 UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
341 UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
342 UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
343 UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
344 ///< Bit 1 must be set in OverrideConfig for this field to take effect
345 UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
346 /**
347 The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
348 This field can be zero if only the L1 Substate value is going to be override.
349 **/
350 UINT16 L1SubstatesCapOffset;
351 /**
352 L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
353 Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
354 Only bit [3:0] are applicable. Other bits are ignored.
355 **/
356 UINT8 L1SubstatesCapMask;
357 /**
358 L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
359 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
360 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
361 and only L1SubstatesCapOffset is override.
362 **/
363 UINT8 L1sCommonModeRestoreTime;
364 /**
365 L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
366 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
367 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
368 and only L1SubstatesCapOffset is override.
369 **/
370 UINT8 L1sTpowerOnScale;
371 /**
372 L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
373 L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
374 If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
375 and only L1SubstatesCapOffset is override.
376 **/
377 UINT8 L1sTpowerOnValue;
378
379 /**
380 SnoopLatency bit definition
381 Note: All Reserved bits must be set to 0
382
383 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
384 When clear values in bits 9:0 will be ignored
385 BITS[14:13] - Reserved
386 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
387 000b - 1 ns
388 001b - 32 ns
389 010b - 1024 ns
390 011b - 32,768 ns
391 100b - 1,048,576 ns
392 101b - 33,554,432 ns
393 110b - Reserved
394 111b - Reserved
395 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
396 the scale in bits 12:10
397
398 This field takes effect only if bit 3 is set in OverrideConfig.
399 **/
400 UINT16 SnoopLatency;
401 /**
402 NonSnoopLatency bit definition
403 Note: All Reserved bits must be set to 0
404
405 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
406 When clear values in bits 9:0 will be ignored
407 BITS[14:13] - Reserved
408 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
409 000b - 1 ns
410 001b - 32 ns
411 010b - 1024 ns
412 011b - 32,768 ns
413 100b - 1,048,576 ns
414 101b - 33,554,432 ns
415 110b - Reserved
416 111b - Reserved
417 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
418 the scale in bits 12:10
419
420 This field takes effect only if bit 3 is set in OverrideConfig.
421 **/
422 UINT16 NonSnoopLatency;
423
424 /**
425 Forces LTR override to be permanent
426 The default way LTR override works is:
427 rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
428 This settings allows force override of LTR mechanism. If it's enabled, then:
429 rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
430 **/
431 UINT8 ForceLtrOverride;
432 UINT8 Reserved[3];
433 } PCIE_DEVICE_OVERRIDE;
434
435 #pragma pack (pop)
436 #endif // _PCIE_CONFIG_H_
PCIE_DEVICE_OVERRIDE::BaseClassCode
UINT8 BaseClassCode
The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class.
Definition: PcieConfig.h:341
PCIE_LINK_EQ_MODE
PCIE_LINK_EQ_MODE
Definition: PcieConfig.h:119
PCIE_LINK_EQ_PLATFORM_SETTINGS::RemotePresetCoeffoverride
UINT8 RemotePresetCoeffoverride
Remote Transmitter Preset Coefficient Override for single PCIe speed.
Definition: PcieConfig.h:158
PcieLinkFixedEq
@ PcieLinkFixedEq
No coefficient/preset search is performed. Fixed values are used.
Definition: PcieConfig.h:116
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh3Bypass
UINT8 EqPh3Bypass
PCIe Equalization Phase 3 Enable Control.
Definition: PcieConfig.h:164
PCIE_COMMON_CONFIG::ComplianceTestMode
UINT32 ComplianceTestMode
Compliance Test Mode shall be enabled when using Compliance Load Board.
Definition: PcieConfig.h:308
PCIE_DEVICE_OVERRIDE::SnoopLatency
UINT16 SnoopLatency
SnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:400
PCIE_DEVICE_OVERRIDE::DeviceId
UINT16 DeviceId
The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID.
Definition: PcieConfig.h:339
PCIE_DEVICE_OVERRIDE::L1sTpowerOnValue
UINT8 L1sTpowerOnValue
L1 Substate Port Tpower_on Value Override.
Definition: PcieConfig.h:377
PCIE_DEVICE_OVERRIDE::L1SubstatesCapOffset
UINT16 L1SubstatesCapOffset
The L1Substates Capability Offset Override.
Definition: PcieConfig.h:350
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMode
UINT8 PcieLinkEqMode
Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details ...
Definition: PcieConfig.h:134
PCIE_DEVICE_OVERRIDE::L1SubstatesCapMask
UINT8 L1SubstatesCapMask
L1 Substate Capability Mask.
Definition: PcieConfig.h:356
PCIE_EQ_PARAM
Represent lane specific PCIe Gen3 equalization parameters.
Definition: PcieConfig.h:76
PcieLinkEqPresetMode
@ PcieLinkEqPresetMode
Use presets during PCIe link equalization.
Definition: PcieConfig.h:120
PCIE_LINK_EQ_PLATFORM_SETTINGS::EqPh23Bypass
UINT8 EqPh23Bypass
PCIe Equalization Phase 2-3 Enable Control.
Definition: PcieConfig.h:170
PCIE_COMMON_CONFIG::RpFunctionSwap
UINT32 RpFunctionSwap
RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is ...
Definition: PcieConfig.h:303
PCIE_DEVICE_OVERRIDE::ForceLtrOverride
UINT8 ForceLtrOverride
Forces LTR override to be permanent The default way LTR override works is: rootport uses LTR override...
Definition: PcieConfig.h:431
PCIE_COMMON_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PcieConfig.h:309
PCIE_EQ_PARAM::Cp
UINT8 Cp
Coefficient C+1.
Definition: PcieConfig.h:78
PCIE_LINK_EQ_PLATFORM_SETTINGS::PCETTimer
UINT32 PCETTimer
PCET Timer value for single PCIe speed.
Definition: PcieConfig.h:157
PCIE_DEVICE_OVERRIDE::SubClassCode
UINT8 SubClassCode
The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class.
Definition: PcieConfig.h:342
PCIE_LINK_EQ_PLATFORM_SETTINGS::PcieLinkEqMethod
UINT8 PcieLinkEqMethod
Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for...
Definition: PcieConfig.h:133
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph2LocalTransmitterOverridePreset
UINT32 Ph2LocalTransmitterOverridePreset
Specifies the preset that should be used during local transmitter override during phase 2 of EQ proce...
Definition: PcieConfig.h:156
PCIE_DEVICE_OVERRIDE::OverrideConfig
UINT16 OverrideConfig
The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
Definition: PcieConfig.h:345
PcieLinkHardwareEq
@ PcieLinkHardwareEq
Hardware is responsible for performing coefficient/preset search.
Definition: PcieConfig.h:115
PcieLinkEqCoefficientMode
@ PcieLinkEqCoefficientMode
Use coefficients during PCIe link equalization.
Definition: PcieConfig.h:121
PCIE_DEVICE_OVERRIDE::RevId
UINT8 RevId
The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings.
Definition: PcieConfig.h:340
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1DownstreamPortTransmitterPreset
UINT32 Ph1DownstreamPortTransmitterPreset
Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equali...
Definition: PcieConfig.h:149
PCIE_DEVICE_OVERRIDE::VendorId
UINT16 VendorId
The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID.
Definition: PcieConfig.h:338
PCIE_DEVICE_OVERRIDE::NonSnoopLatency
UINT16 NonSnoopLatency
NonSnoopLatency bit definition Note: All Reserved bits must be set to 0.
Definition: PcieConfig.h:422
PCIE_LINK_EQ_PLATFORM_SETTINGS::TsLockTimer
UINT8 TsLockTimer
8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
Definition: PcieConfig.h:171
PCIE_COMMON_CONFIG
PCIe Common Config.
Definition: PcieConfig.h:287
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph1UpstreamPortTransmitterPreset
UINT32 Ph1UpstreamPortTransmitterPreset
Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equaliza...
Definition: PcieConfig.h:150
PCIE_LINK_EQ_METHOD
PCIE_LINK_EQ_METHOD
Definition: PcieConfig.h:114
PCIE_DEVICE_OVERRIDE::L1sTpowerOnScale
UINT8 L1sTpowerOnScale
L1 Substate Port Tpower_on Scale Override.
Definition: PcieConfig.h:370
PCIE_LINK_EQ_PLATFORM_SETTINGS
PCIe Link EQ Platform Settings.
Definition: PcieConfig.h:132
PCIE_LINK_EQ_PLATFORM_SETTINGS::LocalTransmitterOverrideEnable
UINT8 LocalTransmitterOverrideEnable
Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
Definition: PcieConfig.h:140
PCIE_DEVICE_OVERRIDE::L1sCommonModeRestoreTime
UINT8 L1sCommonModeRestoreTime
L1 Substate Port Common Mode Restore Time Override.
Definition: PcieConfig.h:363
PCIE_COMMON_CONFIG::EnablePort8xhDecode
UINT8 EnablePort8xhDecode
(Test) This member describes whether PCIE root port Port 8xh Decode is enabled.
Definition: PcieConfig.h:313
PCIE_DEVICE_OVERRIDE
PCIe device table entry entry.
Definition: PcieConfig.h:337
PCIE_EQ_PARAM::Cm
UINT8 Cm
Coefficient C-1.
Definition: PcieConfig.h:77
PCIE_DEVICE_OVERRIDE::EndPointAspm
UINT8 EndPointAspm
Override device ASPM (see: PCH_PCIE_ASPM_CONTROL) Bit 1 must be set in OverrideConfig for this field ...
Definition: PcieConfig.h:343
PCIE_LINK_EQ_PLATFORM_SETTINGS::Ph3NumberOfPresetsOrCoefficients
UINT8 Ph3NumberOfPresetsOrCoefficients
Tells BIOS how many presets/coefficients should be used during link EQ.
Definition: PcieConfig.h:145
PCIE_FORM_FACTOR
PCIE_FORM_FACTOR
Specifies the form factor that the slot implements.
Definition: PcieConfig.h:103
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieDxeConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
PcieDxeConfig.h File Reference

PCIE DXE policy definitions. More...

#include "CpuPcieInfo.h"
Include dependency graph for PcieDxeConfig.h:
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Classes

struct | CPU_PCIE_PWR_OPT
PCIE Power Optimizer config. More...
struct | PCIE_DXE_CONFIG
The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control for PEG ASPM. More...

Detailed Description

PCIE DXE policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieDxeConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieDxeConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
PcieDxeConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIE DXE policy definitions
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_DXE_CONFIG_H_
36 #define _PCIE_DXE_CONFIG_H_
37
38 #include "CpuPcieInfo.h"
39
40 #pragma pack(push, 1)
41
42 #define PCIE_DXE_CONFIG_REVISION 2
43
44 typedef struct {
45 UINT16 VendorId; ///< Offset 0 PCI Config space offset 0
46 UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2
47 /**
48 Offset 4:
49 SnoopLatency bit definition
50 Note: All Reserved bits must be set to 0
51
52 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
53 When clear values in bits 9:0 will be ignored
54 BIT[14] - Should be set to 0b
55 BIT[13] - Reserved
56 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
57 000b - 1 ns
58 001b - 32 ns
59 010b - 1024 ns
60 011b - 32,768 ns
61 100b - 1,048,576 ns
62 101b - 33,554,432 ns
63 110b - Reserved
64 111b - Reserved
65 BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
66 the scale in bits 12:10
67 **/
68 UINT16 SnoopLatency;
69 /**
70 Offset 6:
71 NonSnoopLatency bit definition
72 Note: All Reserved bits must be set to 0
73
74 BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
75 When clear values in bits 9:0 will be ignored
76 BIT[14] - Should be set to 0b
77 BIT[13] - Reserved
78 BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
79 000b - 1 ns
80 001b - 32 ns
81 010b - 1024 ns
82 011b - 32,768 ns
83 100b - 1,048,576 ns
84 101b - 33,554,432 ns
85 110b - Reserved
86 111b - Reserved
87 BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
88 the scale in bits 12:10
89 **/
90 UINT16 NonSnoopLatency;
91 UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means all steppings
92 UINT8 Rsvd0[3]; ///< Offset 9
93 } PCIE_LTR_DEV_INFO;
94
95 ///
96 /// PCIE Power Optimizer config
97 ///
98 typedef struct {
99 UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <b>0x0846=70us</b>
100 UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latency: <b>0x0846=70us</b>
101 UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=Disable, <b>1=Enable</b>
102 UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=Disable, <b>1=Enable</b>
103 UINT8 Rsvd0[2]; ///< Offset 6 Reserved
104 } CPU_PCIE_PWR_OPT;
105
106
107 /**
108 The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control
109 for PEG ASPM.
110 The data elements should be initialized by a Platform Module.\n
111 @note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
112 <b>Revision 1</b>:
113 - Initial version.
114 <b>Revision 2</b>:
115 - Adding PEG RTD3 Support Setup Variable
116 <b>Revision 3</b>:
117 - Adding CPU PCIE RTD3 Support Setup Variable
118 - Deprecating PEG RTD3 Support Setup Variable
119 <b>Revision 4</b>:
120 - Deprecating CPU PCIE RTD3 Support Setup Variable
121 **/
122 typedef struct {
123 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
124 /**
125 Offset 28: This field is used to describe the ASPM control for PEG Ports\n
126 0=ASPM Disabled, 1=ASPM L0s Enabled, 2=ASPM L1 Enabled, 3=ASPM L0sL1 Enabled, <b>4=ASPM AUTO</b>
127 **/
128 UINT8 PegAspm[SA_PEG_MAX_FUN];
129 /**
130 Offset 32: PCIe Hot Plug Enable/Disable. It has 2 policies.
131 - <b>Disabled (0x0)</b> : No hotplug.
132 - Enabled (0x1) : Bios assist hotplug.
133 **/
134 UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];
135 CPU_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 36: This field is used to describe the PCIe LTR/OBFF relevant settings
136 UINT32 PegRtd3; /// Deprecated Policy
137 UINT8 CpuPcieRtd3; ///< Enable/Disable RTD3 Support for CPU PCIE. 0=Disable and 1=Enable (default) // Deprecated Policy
138 UINT8 Rsvd3[3];
139 } PCIE_DXE_CONFIG;
140 #pragma pack(pop)
141
142 #endif // _PCIE_DXE_CONFIG_H_
PCIE_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: PcieDxeConfig.h:123
CPU_PCIE_PWR_OPT::LtrMaxSnoopLatency
UINT16 LtrMaxSnoopLatency
Offset 0 LTR Maximum Snoop Latency: 0x0846=70us
Definition: PcieDxeConfig.h:99
CPU_PCIE_PWR_OPT
PCIE Power Optimizer config.
Definition: PcieDxeConfig.h:98
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_DXE_CONFIG::CpuPcieRtd3
UINT8 CpuPcieRtd3
Deprecated Policy.
Definition: PcieDxeConfig.h:137
CPU_PCIE_PWR_OPT::LtrMaxNoSnoopLatency
UINT16 LtrMaxNoSnoopLatency
Offset 2 LTR Maximum Non-Snoop Latency: 0x0846=70us
Definition: PcieDxeConfig.h:100
PCIE_DXE_CONFIG
The PCI Express Configuration info includes PCI Resources Range Base and Limits and the control for P...
Definition: PcieDxeConfig.h:122
CPU_PCIE_PWR_OPT::ObffEnable
UINT8 ObffEnable
Offset 4 LTR enable/disable: 0=Disable, 1=Enable
Definition: PcieDxeConfig.h:101
CPU_PCIE_PWR_OPT::LtrEnable
UINT8 LtrEnable
Offset 5 LTR enable/disable: 0=Disable, 1=Enable
Definition: PcieDxeConfig.h:102
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieHelperLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PcieHelperLib.h File Reference

Header file for PCI Express helpers base library. More...

#include <PcieRegs.h>
#include <Library/PciSegmentLib.h>
#include <Uefi/UefiBaseType.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <IndustryStandard/Pci.h>
Include dependency graph for PcieHelperLib.h:
This graph shows which files directly or indirectly include this file:

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Functions

UINT8 | PcieBaseFindCapId (IN UINT64 DeviceBase, IN UINT8 CapId)
Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability. More...
UINT8 | PcieFindCapId (IN UINT8 Segment, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 CapId)
Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability. More...
UINT16 | PcieBaseFindExtendedCapId (IN UINT64 DeviceBase, IN UINT16 CapId)
Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error Reporting Capability 0x0002 = Virtual Channel Capability 0x0003 = Device Serial Number Capability 0x0004 = Power Budgeting Capability. More...
UINT16 | PcieFindExtendedCapId (IN UINT8 Segment, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT16 CapId)
Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error Rreporting Capability 0x0002 = Virtual Channel Capability 0x0003 = Device Serial Number Capability 0x0004 = Power Budgeting Capability. More...
UINT64 | PcieRpSetSubordSecondBus (IN UINT64 RpBase, IN UINT8 Segment, IN UINT8 TempPciBus)
This function assigns Subordinate Bus Number and Secondary Bus Number. More...
VOID | PcieRpClearSubordSecondBus (IN UINT64 RpBase)
Clear Subordinate Bus Number and Secondary Bus Number. More...

Detailed Description

Header file for PCI Express helpers base library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieHelperLib.h.

Function Documentation

◆ PcieBaseFindCapId()

UINT8 PcieBaseFindCapId | ( | IN UINT64 | DeviceBase,
 |  | IN UINT8 | CapId
 | ) |  |

Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability.

Parameters
[in] | DeviceBase | device's base address
[in] | CapId | CAPID to search for
Return values
0 | CAPID not found
Other | CAPID found, Offset of desired CAPID

◆ PcieBaseFindExtendedCapId()

UINT16 PcieBaseFindExtendedCapId | ( | IN UINT64 | DeviceBase,
 |  | IN UINT16 | CapId
 | ) |  |

Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error Reporting Capability 0x0002 = Virtual Channel Capability 0x0003 = Device Serial Number Capability 0x0004 = Power Budgeting Capability.

Parameters
[in] | DeviceBase | device base address
[in] | CapId | Extended CAPID to search for
Return values
0 | CAPID not found, this includes situation where device doesn't exist
Other | CAPID found, Offset of desired CAPID

◆ PcieFindCapId()

UINT8 PcieFindCapId | ( | IN UINT8 | Segment,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT8 | CapId
 | ) |  |

Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = Slot Identification 0x05 = MSI Capability 0x10 = PCI Express Capability.

Parameters
[in] | Segment | Pci Segment Number
[in] | Bus | Pci Bus Number
[in] | Device | Pci Device Number
[in] | Function | Pci Function Number
[in] | CapId | CAPID to search for
Return values
0 | CAPID not found
Other | CAPID found, Offset of desired CAPID

◆ PcieFindExtendedCapId()

UINT16 PcieFindExtendedCapId | ( | IN UINT8 | Segment,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT16 | CapId
 | ) |  |

Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error Rreporting Capability 0x0002 = Virtual Channel Capability 0x0003 = Device Serial Number Capability 0x0004 = Power Budgeting Capability.

Parameters
[in] | Segment | Pci Segment Number
[in] | Bus | Pci Bus Number
[in] | Device | Pci Device Number
[in] | Function | Pci Function Number
[in] | CapId | Extended CAPID to search for
Return values
0 | CAPID not found
Other | CAPID found, Offset of desired CAPID

◆ PcieRpClearSubordSecondBus()

VOID PcieRpClearSubordSecondBus ( IN UINT64 RpBase )

Clear Subordinate Bus Number and Secondary Bus Number.

Parameters
[in] RpBase Root Port PCI base address

◆ PcieRpSetSubordSecondBus()

UINT64 PcieRpSetSubordSecondBus | ( | IN UINT64 | RpBase,
 |  | IN UINT8 | Segment,
 |  | IN UINT8 | TempPciBus
 | ) |  |

This function assigns Subordinate Bus Number and Secondary Bus Number.

Parameters
[in] | RpBase | Root Port PCI base address
[in] | Segment | PCIe Root port PCI Segment
[in] | TempPciBus | Temporary PCI bus number
Return values
UINT64 Assigned sub bus base address
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieHelperLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PcieHelperLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PCI Express helpers base library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_HELPER_LIB_H_
36 #define _PCIE_HELPER_LIB_H_
37
38 #include <PcieRegs.h>
39 #include <Library/PciSegmentLib.h>
40 #include <Uefi/UefiBaseType.h>
41 #include <Library/BaseLib.h>
42 #include <Library/DebugLib.h>
43 #include <IndustryStandard/Pci.h>
44
45 /**
46 Find the Offset to a given Capabilities ID
47 CAPID list:
48 0x01 = PCI Power Management Interface
49 0x04 = Slot Identification
50 0x05 = MSI Capability
51 0x10 = PCI Express Capability
52
53 @param[in] DeviceBase device's base address
54 @param[in] CapId CAPID to search for
55
56 @retval 0 CAPID not found
57 @retval Other CAPID found, Offset of desired CAPID
58 **/
59 UINT8
60 PcieBaseFindCapId (
61 IN UINT64 DeviceBase,
62 IN UINT8 CapId
63 );
64
65 /**
66 Find the Offset to a given Capabilities ID
67 CAPID list:
68 0x01 = PCI Power Management Interface
69 0x04 = Slot Identification
70 0x05 = MSI Capability
71 0x10 = PCI Express Capability
72
73 @param[in] Segment Pci Segment Number
74 @param[in] Bus Pci Bus Number
75 @param[in] Device Pci Device Number
76 @param[in] Function Pci Function Number
77 @param[in] CapId CAPID to search for
78
79 @retval 0 CAPID not found
80 @retval Other CAPID found, Offset of desired CAPID
81 **/
82 UINT8
83 PcieFindCapId (
84 IN UINT8 Segment,
85 IN UINT8 Bus,
86 IN UINT8 Device,
87 IN UINT8 Function,
88 IN UINT8 CapId
89 );
90
91 /**
92 Search and return the offset of desired Pci Express Capability ID
93 CAPID list:
94 0x0001 = Advanced Error Reporting Capability
95 0x0002 = Virtual Channel Capability
96 0x0003 = Device Serial Number Capability
97 0x0004 = Power Budgeting Capability
98
99 @param[in] DeviceBase device base address
100 @param[in] CapId Extended CAPID to search for
101
102 @retval 0 CAPID not found, this includes situation where device doesn't exist
103 @retval Other CAPID found, Offset of desired CAPID
104 **/
105 UINT16
106 PcieBaseFindExtendedCapId (
107 IN UINT64 DeviceBase,
108 IN UINT16 CapId
109 );
110
111 /**
112 Search and return the offset of desired Pci Express Capability ID
113 CAPID list:
114 0x0001 = Advanced Error Rreporting Capability
115 0x0002 = Virtual Channel Capability
116 0x0003 = Device Serial Number Capability
117 0x0004 = Power Budgeting Capability
118
119 @param[in] Segment Pci Segment Number
120 @param[in] Bus Pci Bus Number
121 @param[in] Device Pci Device Number
122 @param[in] Function Pci Function Number
123 @param[in] CapId Extended CAPID to search for
124
125 @retval 0 CAPID not found
126 @retval Other CAPID found, Offset of desired CAPID
127 **/
128 UINT16
129 PcieFindExtendedCapId (
130 IN UINT8 Segment,
131 IN UINT8 Bus,
132 IN UINT8 Device,
133 IN UINT8 Function,
134 IN UINT16 CapId
135 );
136
137 /*
138 Checks device's Slot Clock Configuration
139
140 @param[in] Base device's base address
141 @param[in] PcieCapOffset devices Pci express capability list register offset
142
143 @retval TRUE when device device uses slot clock, FALSE otherwise
144 */
145 BOOLEAN
146 GetScc (
147 UINT64 Base,
148 UINT8 PcieCapOffset
149 );
150
151 /*
152 Sets Common Clock Configuration bit for given device.
153 @param[in] PcieCapOffset devices Pci express capability list register offset
154 @param[in] Base device's base address
155 */
156 VOID
157 EnableCcc (
158 UINT64 Base,
159 UINT8 PcieCapOffset
160 );
161
162 /*
163 Retrains link behind given device.
164 It only makes sense to call it for downstream ports.
165 If called for upstream port nothing will happen, it won't enter infinite loop.
166
167 @param[in] Base device's base address
168 @param[in] PcieCapOffset devices Pci express capability list register offset
169 @param[boolean] WaitUnitlDone when TRUE, function waits until link has retrained
170 */
171 VOID
172 RetrainLink (
173 UINT64 Base,
174 UINT8 PcieCapOffset,
175 BOOLEAN WaitUntilDone
176 );
177
178 /*
179 Checks if device at given address exists
180
181 @param[in] Base device's base address
182
183 @retval TRUE when device exists; FALSE otherwise
184 */
185 BOOLEAN
186 IsDevicePresent (
187 UINT64 Base
188 );
189
190 /*
191 Checks if device is a multifunction device
192
193 @param[in] Base device's base address
194
195 @retval TRUE if multifunction; FALSE otherwise
196 */
197 BOOLEAN
198 IsMultifunctionDevice (
199 UINT64 Base
200 );
201
202 /**
203 This function assigns Subordinate Bus Number and Secondary Bus Number.
204
205 @param[in] RpBase Root Port PCI base address
206 @param[in] Segment PCIe Root port PCI Segment
207 @param[in] TempPciBus Temporary PCI bus number
208 @retval UINT64 Assigned sub bus base address
209 **/
210 UINT64
211 PcieRpSetSubordSecondBus (
212 IN UINT64 RpBase,
213 IN UINT8 Segment,
214 IN UINT8 TempPciBus
215 );
216
217 /**
218 Clear Subordinate Bus Number and Secondary Bus Number.
219
220 @param[in] RpBase Root Port PCI base address
221 **/
222 VOID
223 PcieRpClearSubordSecondBus (
224 IN UINT64 RpBase
225 );
226 #endif // _PCIE_HELPER_LIB_H_
PcieRpClearSubordSecondBus
VOID PcieRpClearSubordSecondBus(IN UINT64 RpBase)
Clear Subordinate Bus Number and Secondary Bus Number.
PcieRegs.h
Register names for PCIE standard register.
PcieFindExtendedCapId
UINT16 PcieFindExtendedCapId(IN UINT8 Segment, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT16 CapId)
Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error...
PcieBaseFindCapId
UINT8 PcieBaseFindCapId(IN UINT64 DeviceBase, IN UINT8 CapId)
Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = S...
PcieFindCapId
UINT8 PcieFindCapId(IN UINT8 Segment, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 CapId)
Find the Offset to a given Capabilities ID CAPID list: 0x01 = PCI Power Management Interface 0x04 = S...
PcieRpSetSubordSecondBus
UINT64 PcieRpSetSubordSecondBus(IN UINT64 RpBase, IN UINT8 Segment, IN UINT8 TempPciBus)
This function assigns Subordinate Bus Number and Secondary Bus Number.
PcieBaseFindExtendedCapId
UINT16 PcieBaseFindExtendedCapId(IN UINT64 DeviceBase, IN UINT16 CapId)
Search and return the offset of desired Pci Express Capability ID CAPID list: 0x0001 = Advanced Error...
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PciePeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3
Classes
PciePeiConfig.h File Reference

Policy definition for PCIe Config Block. More...

#include <Library/GpioLib.h>
#include <Register/SaRegsHostBridge.h>
Include dependency graph for PciePeiConfig.h:

Go to the source code of this file.

Classes

struct PCIE_PEI_CONFIG
PCI Express and DMI controller configuration - PostMem
. More...

Detailed Description

Policy definition for PCIe Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PciePeiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PciePeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3
PciePeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy definition for PCIe Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_PEI_CONFIG_H_
36 #define _PCIE_PEI_CONFIG_H_
37
38 #include <Library/GpioLib.h>
39 #include <Register/SaRegsHostBridge.h>
40
41 #pragma pack(push, 1)
42
43 #define PCIE_PEI_CONFIG_REVISION 1
44
45 /**
46 PCI Express and DMI controller configuration - PostMem\n
47 @note <b>Optional.</b> These policies will be ignored if there is no PEG port present on board.
48 <b>Revision 1</b>:
49 - Initial version.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
53 /**
54 Offset 28:0
55 <b>(Test)</b>DMI Extended Sync Control
56 - <b>Disabled</b> (0x0) : Disable DMI Extended Sync (Default)
57 - Enabled (0x1) : Enable DMI Extended Sync
58 **/
59 UINT32 DmiExtSync : 1;
60 /**
61 Offset 28:1
62 <b>(Test)</b>DMI IOT Control
63 - <b>Disabled</b> (0x0) : Disable DMI IOT (Default)
64 - Enabled (0x1) : Enable DMI IOT
65 **/
66 UINT32 DmiIot : 1;
67 UINT32 RsvdBits1 : 30; ///< Offset 28:2-31 :Reserved for future use.
68 UINT8 DmiAspm; ///< Offset 32 This field is used to describe the ASPM control for DMI: <b>3=PcieAspmL0sL1</b>, 2=PcieAspmL1, 1=PcieAspmL0s, 0=PcieAspmDisabled.
69 UINT8 Rsvd1[1]; ///< Offset 33 to 35
70 UINT8 PegDeEmphasis[SA_PEG_MAX_FUN_GEN3]; ///< Offset 36 This field is used to describe the DeEmphasis control for PEG (-6 dB and -3.5 dB are the options)SA_PEG_MAX_FUN = 3 for CFL and SA_PEG_MAX_FUN = 4 for CNL, offsets are adjusted accordingly
71 UINT8 PegMaxPayload[SA_PEG_MAX_FUN_GEN3]; ///< <b>(Test)</b> Offset 39/40 This field is used to describe the PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B)
72 /**
73 PCIe Slot Power Capabilities. SlotPowerLimitValue in combination with SlotPowerLimitScale specifies the upper limit on power supplied by slot.
74 **/
75 UINT8 PegSlotPowerLimitValue[SA_PEG_MAX_FUN_GEN3]; ///< Offset 42/44 8 bit value
76 UINT8 PegSlotPowerLimitScale[SA_PEG_MAX_FUN_GEN3]; ///< Offset 45/48 2 bit value: <b>00 = 1.0x</b>, 01 = 0.1x, 10 = 0.01x and 11 = 0.001x
77 /**
78 Offset 48/52
79 PCIe Physical Slot Number (13 bit value). Indicates the physical slot number attached to the port.
80 **/
81 UINT16 PegPhysicalSlotNumber[SA_PEG_MAX_FUN_GEN3];
82 } PCIE_PEI_CONFIG;
83 #pragma pack(pop)
84
85 #endif // _PCIE_PEI_CONFIG_H_
GpioLib.h
Header file for GpioLib.
PCIE_PEI_CONFIG
PCI Express and DMI controller configuration - PostMem .
Definition: PciePeiConfig.h:51
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: PciePeiConfig.h:52
PCIE_PEI_CONFIG::DmiExtSync
UINT32 DmiExtSync
Offset 28:0 (Test)DMI Extended Sync Control.
Definition: PciePeiConfig.h:59
PCIE_PEI_CONFIG::DmiIot
UINT32 DmiIot
Offset 28:1 (Test)DMI IOT Control.
Definition: PciePeiConfig.h:66
PCIE_PEI_CONFIG::DmiAspm
UINT8 DmiAspm
Offset 32 This field is used to describe the ASPM control for DMI: 3=PcieAspmL0sL1,...
Definition: PciePeiConfig.h:68
PCIE_PEI_CONFIG::RsvdBits1
UINT32 RsvdBits1
Offset 28:2-31 :Reserved for future use.
Definition: PciePeiConfig.h:67
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PciePreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
Classes
PciePreMemConfig.h File Reference

PCIe Config Block PreMem. More...

Go to the source code of this file.

Classes

struct | PCIE_IMR_CONFIG
PCIe IMR Config. More...
struct | PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version. More...

Detailed Description

PCIe Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PciePreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PciePreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PciePreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 PCIe Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_PREMEM_CONFIG_H_
36 #define _PCIE_PREMEM_CONFIG_H_
37
38 #define PCIE_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gPciePreMemConfigGuid;
41
42 typedef enum {
43 ImrRpLocationPch,
44 ImrRpLocationSa,
45 ImrRpLocationMax
46 } PCIE_IMR_ROOT_PORT_LOCATION;
47
48 #pragma pack (push,1)
49
50 /**
51 PCIe IMR Config
52 **/
53 typedef struct {
54 UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
55 UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
56 UINT16 ImrSize; ///< PCIe IMR size in megabytes
57 UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
58 UINT8 Rsvd0[3];
59 } PCIE_IMR_CONFIG;
60
61 /**
62 PCIe Pre-Memory Configuration
63 <b>Revision 1</b>: - Initial version.
64 **/
65 typedef struct {
66 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
67 PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
68 } PCIE_PREMEM_CONFIG;
69
70 #pragma pack (pop)
71 #endif // _PCIE_PREMEM_CONFIG_H_
PCIE_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: PciePreMemConfig.h:66
PCIE_IMR_CONFIG::ImrRpLocation
UINT8 ImrRpLocation
0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port locati...
Definition: PciePreMemConfig.h:55
PCIE_IMR_CONFIG
PCIe IMR Config.
Definition: PciePreMemConfig.h:53
PCIE_PREMEM_CONFIG
PCIe Pre-Memory Configuration Revision 1: - Initial version.
Definition: PciePreMemConfig.h:65
PCIE_IMR_CONFIG::ImrSize
UINT16 ImrSize
PCIe IMR size in megabytes.
Definition: PciePreMemConfig.h:56
PCIE_PREMEM_CONFIG::PcieImr
PCIE_IMR_CONFIG PcieImr
IMR Configuration.
Definition: PciePreMemConfig.h:67
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCIE_IMR_CONFIG::ImrRpSelection
UINT8 ImrRpSelection
Index of root port that is selected for PCIe IMR (0 based)
Definition: PciePreMemConfig.h:57
PCIE_IMR_CONFIG::ImrEnabled
UINT8 ImrEnabled
PCIe IMR. 0: Disable; 1: Enable.
Definition: PciePreMemConfig.h:54
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros
PcieRegs.h File Reference

Register names for PCIE standard register. More...

#include <IndustryStandard/Pci30.h>
Include dependency graph for PcieRegs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | R_PCI_BRIDGE_BNUM 0x18
Bus Number Register.
#define | B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000
Subordinate Bus Number.
#define | B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00
Secondary Bus Number.
#define | B_PCI_BRIDGE_BNUM_PBN 0x000000FF
Primary Bus Number.
#define | R_PCI_BRIDGE_IOBL 0x1C
I/O Base and Limit Register.
#define | R_PCI_BRIDGE_MBL 0x20
Memory Base and Limit Register.
#define | B_PCI_BRIDGE_MBL_ML 0xFFF00000
Memory Limit.
#define | B_PCI_BRIDGE_MBL_MB 0x0000FFF0
Memory Base.
#define | R_PCI_BRIDGE_PMBL 0x24
Prefetchable Memory Base and Limit Register.
#define | B_PCI_BRIDGE_PMBL_PML 0xFFF00000
Prefetchable Memory Limit.
#define | B_PCI_BRIDGE_PMBL_I64L 0x000F0000
64-bit Indicator
#define | B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0
Prefetchable Memory Base.
#define | B_PCI_BRIDGE_PMBL_I64B 0x0000000F
64-bit Indicator
#define | R_PCI_BRIDGE_PMBU32 0x28
Prefetchable Memory Base Upper 32-Bit Register.
#define | R_PCI_BRIDGE_PMLU32 0x2C
Prefetchable Memory Limit Upper 32-Bit Register.
#define | R_PCI_CARDBUS_BRIDGE_SVID 0x40
Subsystem Vendor ID.
#define | R_PCIE_CAP_ID_OFFSET 0x00
Capability ID.
#define | R_PCIE_CAP_NEXT_PRT_OFFSET 0x01
Next Capability Capability ID Pointer.
#define | R_PCIE_XCAP_OFFSET 0x02
PCI Express Capabilities Register (Offset 02h)
#define | B_PCIE_XCAP_SI BIT8
Slot Implemented.
#define | B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4)
Device/Port Type.
#define | R_PCIE_DCAP_OFFSET 0x04
Device Capabilities Register (Offset 04h)
#define | B_PCIE_DCAP_RBER BIT15
Role-Based Error Reporting.
#define | B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9)
Endpoint L1 Acceptable Latency.
#define | B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6)
Endpoint L0s Acceptable Latency.
#define | B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0)
Max_Payload_Size Supported.
#define | R_PCIE_DCTL_OFFSET 0x08
Device Control Register (Offset 08h)
#define | B_PCIE_DCTL_NS BIT11
Enable No Snoop.
#define | B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5)
Max_Payload_Size.
#define | B_PCIE_DCTL_RO BIT4
Enable Relaxed Ordering.
#define | B_PCIE_DCTL_URE BIT3
Unsupported Request Reporting Enable.
#define | B_PCIE_DCTL_FEE BIT2
Fatal Error Reporting Enable.
#define | B_PCIE_DCTL_NFE BIT1
Non-Fatal Error Reporting Enable.
#define | B_PCIE_DCTL_CEE BIT0
Correctable Error Reporting Enable.
#define | R_PCIE_DSTS_OFFSET 0x0A
Device Status Register (Offset 0Ah)
#define | B_PCIE_DSTS_TDP BIT5
Transactions Pending.
#define | B_PCIE_DSTS_APD BIT4
AUX Power Detected.
#define | B_PCIE_DSTS_URD BIT3
Unsupported Request Detected.
#define | B_PCIE_DSTS_FED BIT2
Fatal Error Detected.
#define | B_PCIE_DSTS_NFED BIT1
Non-Fatal Error Detected.
#define | B_PCIE_DSTS_CED BIT0
Correctable Error Detected.
#define | R_PCIE_LCAP_OFFSET 0x0C
Link Capabilities Register (Offset 0Ch)
#define | B_PCIE_LCAP_ASPMOC BIT22
ASPM Optionality Compliance.
#define | B_PCIE_LCAP_CPM BIT18
Clock Power Management.
#define | B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15)
L1 Exit Latency.
#define | B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12)
L0s Exit Latency.
#define | B_PCIE_LCAP_APMS (BIT11 | BIT10)
Active State Power Management (ASPM) Support.
#define | B_PCIE_LCAP_MLW 0x000003F0
Maximum Link Width.
#define | B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0)
Max Link Speed.
#define | R_PCIE_LCTL_OFFSET 0x10
Link Control Register (Offset 10h)
#define | B_PCIE_LCTL_ECPM BIT8
Enable Clock Power Management.
#define | B_PCIE_LCTL_ES BIT7
Extended Synch.
#define | B_PCIE_LCTL_CCC BIT6
Common Clock Configuration.
#define | B_PCIE_LCTL_RL BIT5
Retrain Link.
#define | B_PCIE_LCTL_LD BIT4
Link Disable.
#define | B_PCIE_LCTL_ASPM (BIT1 | BIT0)
Active State Power Management (ASPM) Control.
#define | R_PCIE_LSTS_OFFSET 0x12
Link Status Register (Offset 12h)
#define | B_PCIE_LSTS_LA BIT13
Data Link Layer Link Active.
#define | B_PCIE_LSTS_SCC BIT12
Slot Clock Configuration.
#define | B_PCIE_LSTS_LT BIT11
Link Training.
#define | B_PCIE_LSTS_NLW 0x03F0
Negotiated Link Width.
#define | B_PCIE_LSTS_CLS 0x000F
Current Link Speed.
#define | R_PCIE_SLCAP_OFFSET 0x14
Slot Capabilities Register (Offset 14h)
#define | B_PCIE_SLCAP_PSN 0xFFF80000
Physical Slot Number.
#define | N_PCIE_SLCAP_PSN 19
Physical Slot Number.
#define | B_PCIE_SLCAP_SLS 0x00018000
Slot Power Limit Scale.
#define | N_PCIE_SLCAP_SLS 15
Slot Power Limit Scale.
#define | B_PCIE_SLCAP_SLV 0x00007F80
Slot Power Limit Value.
#define | N_PCIE_SLCAP_SLV 7
Slot Power Limit Value.
#define | B_PCIE_SLCAP_HPC BIT6
Hot-Plug Capable.
#define | B_PCIE_SLCAP_HPS BIT5
Hot-Plug Surprise.
#define | B_PCIE_SLCAP_PIP BIT4
Power indicator present.
#define | B_PCIE_SLCAP_AIP BIT3
Attention indicator present.
#define | B_PCIE_SLCAP_MRLSP BIT2
MRL Sensor present.
#define | B_PCIE_SLCAP_PCP BIT1
Power controller present.
#define | B_PCIE_SLCAP_ABP BIT0
Attention button present.
#define | R_PCIE_SLCTL_OFFSET 0x18
Slot Control Register (Offset 18h)
#define | B_PCIE_SLCTL_HPE BIT5
Hot Plug Interrupt Enable.
#define | B_PCIE_SLCTL_PDE BIT3
Presence Detect Changed Enable.
#define | R_PCIE_SLSTS_OFFSET 0x1A
Slot Status Register (Offset 1Ah)
#define | B_PCIE_SLSTS_PDS BIT6
Presence Detect State.
#define | B_PCIE_SLSTS_PDC BIT3
Presence Detect Changed.
#define | R_PCIE_RCTL_OFFSET 0x1C
Root Control Register (Offset 1Ch)
#define | B_PCIE_RCTL_PIE BIT3
PME Interrupt Enable.
#define | B_PCIE_RCTL_SFE BIT2
System Error on Fatal Error Enable.
#define | B_PCIE_RCTL_SNE BIT1
System Error on Non-Fatal Error Enable.
#define | B_PCIE_RCTL_SCE BIT0
System Error on Correctable Error Enable.
#define | R_PCIE_RSTS_OFFSET 0x20
Root Status Register (Offset 20h)
#define | R_PCIE_DCAP2_OFFSET 0x24
Device Capabilities 2 Register (Offset 24h)
#define | B_PCIE_DCAP2_OBFFS (BIT19 | BIT18)
OBFF Supported.
#define | B_PCIE_DCAP2_LTRMS BIT11
LTR Mechanism Supported.
#define | B_PCIE_DCAP2_PX10BTCS BIT16
10-Bit Tag Completer Support
#define | B_PCIE_DCAP2_PX10BTRS BIT17
10-Bit Tag Requester Support
#define | R_PCIE_DCTL2_OFFSET 0x28
Device Control 2 Register (Offset 28h)
#define | B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13)
OBFF Enable.
#define | V_PCIE_DCTL2_OBFFEN_DIS 0
Disabled.
#define | V_PCIE_DCTL2_OBFFEN_WAKE 3
Enabled using WAKE# signaling.
#define | B_PCIE_DCTL2_PX10BTRE BIT12
10-Bit Tag Requester Enable
#define | B_PCIE_DCTL2_LTREN BIT10
LTR Mechanism Enable.
#define | B_PCIE_DCTL2_AEB BIT7
AtomicOP Egress Blocking Enable.
#define | B_PCIE_DCTL2_CTD BIT4
Completion Timeout Disable.
#define | B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0)
Completion Timeout Value.
#define | R_PCIE_LCTL2_OFFSET 0x30
Link Control 2 Register (Offset 30h)
#define | B_PCIE_LCTL2_SD BIT6
Selectable de-emphasis (0 = -6dB, 1 = -3.5dB)
#define | B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0)
Target Link Speed.
#define | R_PCIE_LSTS2_OFFSET 0x32
Link Status 2 Register (Offset 32h)
#define | B_PCIE_LSTS2_LER BIT5
Link Equalization Request.
#define | B_PCIE_LSTS2_EQP3S BIT4
Equalization Phase 3 Successful.
#define | B_PCIE_LSTS2_EQP2S BIT3
Equalization Phase 2 Successful.
#define | B_PCIE_LSTS2_EQP1S BIT2
Equalization Phase 1 Successful.
#define | B_PCIE_LSTS2_EC BIT1
Equalization Complete.
#define | B_PCIE_LSTS2_CDL BIT0
Current De-emphasis Level.
#define | R_PCIE_PMC_OFFSET 0x02
Power Management Capabilities Register.
#define | B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11)
PME Support.
#define | B_PCIE_PMC_PMEC BIT3
PME Clock.
#define | R_PCIE_PMCS_OFFST 0x04
Power Management Status/Control Register.
#define | B_PCIE_PMCS_BPCE BIT23
Bus Power/Clock Control Enable.
#define | B_PCIE_PMCS_B23S BIT22
B2/B3 Support.
#define | B_PCIE_PMCS_PMES BIT15
PME_Status.
#define | B_PCIE_PMCS_PMEE BIT8
PME Enable.
#define | B_PCIE_PMCS_NSR BIT3
No Soft Reset.
#define | B_PCIE_PMCS_PS (BIT1 | BIT0)
Power State.
#define | R_PCIE_SUBSYSTEM_VENDOR_ID_OFFSET 0x04
Subsystem Vendor IDs.
#define | B_PCIE_EXCAP_NCO 0xFFF00000
Next Capability Offset.
#define | B_PCIE_EXCAP_CV 0x000F0000
Capability Version.
#define | B_PCIE_EXCAP_CID 0x0000FFFF
Capability ID.
#define | V_PCIE_EX_AEC_CID 0x0001
Capability ID.
#define | R_PCIE_EX_UEM_OFFSET 0x08
Uncorrectable Error Mask Register.
#define | B_PCIE_EX_UEM_CT BIT14
Completion Timeout Mask.
#define | B_PCIE_EX_UEM_UC BIT16
Unexpected Completion.
#define | V_PCIE_EX_VC_CID 0x0002
Capability ID.
#define | V_PCIE_EX_ACS_CID 0x000D
Capability ID.
#define | R_PCIE_EX_ACSCAPR_OFFSET 0x04
ACS Capability Register.
#define | V_PCIE_EX_SPE_CID 0x0019
Capability ID.
#define | R_PCIE_EX_LCTL3_OFFSET 0x04
Link Control 3 Register.
#define | B_PCIE_EX_LCTL3_PE BIT0
Perform Equalization.
#define | R_PCIE_EX_LES_OFFSET 0x08
Lane Error Status.
#define | R_PCIE_EX_L01EC_OFFSET 0x0C
Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch)
#define | B_PCIE_EX_L01EC_UPL1TP 0x0F000000
Upstream Port Lane 1 Transmitter Preset.
#define | B_PCIE_EX_L01EC_DPL1TP 0x000F0000
Downstream Port Lane 1 Transmitter Preset.
#define | B_PCIE_EX_L01EC_UPL0TP 0x00000F00
Upstream Port Transmitter Preset.
#define | B_PCIE_EX_L01EC_DPL0TP 0x0000000F
Downstream Port Transmitter Preset.
#define | R_PCIE_EX_L23EC_OFFSET 0x10
Lane 2 and Lane 3 Equalization Control Register (Offset 10h)
#define | B_PCIE_EX_L23EC_UPL3TP 0x0F000000
Upstream Port Lane 3 Transmitter Preset.
#define | B_PCIE_EX_L23EC_DPL3TP 0x000F0000
Downstream Port Lane 3 Transmitter Preset.
#define | B_PCIE_EX_L23EC_UPL2TP 0x00000F00
Upstream Port Lane 2 Transmitter Preset.
#define | B_PCIE_EX_L23EC_DPL2TP 0x0000000F
Downstream Port Lane 2 Transmitter Preset.
#define | V_PCIE_EX_DPC_CID 0x001D
Capability ID.
#define | V_PCIE_EX_L1S_CID 0x001E
Capability ID.
#define | R_PCIE_EX_L1SCAP_OFFSET 0x04
L1 Sub-States Capabilities.
#define | B_PCIE_EX_L1SCAP_L1SSES BIT5
CLKREQ Acceleration Supported.
#define | B_PCIE_EX_L1SCAP_L1PSS BIT4
L1 PM substates supported.
#define | B_PCIE_EX_L1SCAP_AL1SS BIT3
ASPM L1.1 supported.
#define | B_PCIE_EX_L1SCAP_AL12S BIT2
ASPM L1.2 supported.
#define | B_PCIE_EX_L1SCAP_PPL11S BIT1
PCI-PM L1.1 supported.
#define | B_PCIE_EX_L1SCAP_PPL12S BIT0
PCI-PM L1.2 supported.
#define | R_PCIE_EX_L1SCTL1_OFFSET 0x08
L1 Sub-States Control 1.
#define | B_PCIE_EX_L1SCTL1_L12LTRTLSV 0xE0000000
L1.2 LTR Threshold Latency Scale Value.
#define | B_PCIE_EX_L1SCTL1_L12LTRTLV 0x03FF0000
L1.2 LTR Threshold Latency Value.
#define | R_PCIE_EX_L1SCTL2_OFFSET 0x0C
L1 Sub-States Control 2.
#define | V_PCIE_EX_PTM_CID 0x001F
Capability ID.
#define | R_PCIE_EX_PTMCAP_OFFSET 0x04
PTM Capabilities.
#define | B_PCIE_EX_PTMCAP_PTMRC BIT2
PTM Root Capable.
#define | B_PCIE_EX_PTMCAP_PTMRSPC BIT1
PTM Responder Capable.
#define | R_PCIE_EX_PTMCTL_OFFSET 0x08
PTM Control Register.
#define | R_BASE_ADDRESS_OFFSET_0 0x0010
Base Address Register 0.
#define | R_BASE_ADDRESS_OFFSET_1 0x0014
Base Address Register 1.
#define | R_BASE_ADDRESS_OFFSET_2 0x0018
Base Address Register 2.
#define | R_BASE_ADDRESS_OFFSET_3 0x001C
Base Address Register 3.
#define | R_BASE_ADDRESS_OFFSET_4 0x0020
Base Address Register 4.
#define | R_BASE_ADDRESS_OFFSET_5 0x0024
Base Address Register 5.
#define | V_PCIE_EX_DLFECH_CID 0x0025
Capability ID.
#define | V_PCIE_EX_PL16GECH_CID 0x0026
Capability ID.
#define | V_PCIE_EX_PL16MECH_CID 0x0027
Capability ID.
#define | V_PCIE_EX_IDEEXTCAPHDR_CID 0x0030
Capability ID.
#define | V_PCIE_EX_G5ECH_CID 0x002A
Capability ID.
#define | V_PCIE_EX_APEC_CID 0x002B
Capability ID.
#define | V_PCIE_FPBCAP_CID 0x0015
Capability ID.

Detailed Description

Register names for PCIE standard register.

Conventions:

  • Prefixes: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register sizes Definitions beginning with "N_" are the bit position
Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieRegs.h Source File

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PcieRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCIE standard register
3
4 Conventions:
5
6 - Prefixes:
7 Definitions beginning with "R_" are registers
8 Definitions beginning with "B_" are bits within registers
9 Definitions beginning with "V_" are meaningful values within the bits
10 Definitions beginning with "S_" are register sizes
11 Definitions beginning with "N_" are the bit position
12
13 @copyright
14 INTEL CONFIDENTIAL
15 Copyright 2014 - 2021 Intel Corporation.
16
17 The source code contained or described herein and all documents related to the
18 source code ("Material") are owned by Intel Corporation or its suppliers or
19 licensors. Title to the Material remains with Intel Corporation or its suppliers
20 and licensors. The Material may contain trade secrets and proprietary and
21 confidential information of Intel Corporation and its suppliers and licensors,
22 and is protected by worldwide copyright and trade secret laws and treaty
23 provisions. No part of the Material may be used, copied, reproduced, modified,
24 published, uploaded, posted, transmitted, distributed, or disclosed in any way
25 without Intel's prior express written permission.
26
27 No license under any patent, copyright, trade secret or other intellectual
28 property right is granted to or conferred upon you by disclosure or delivery
29 of the Materials, either expressly, by implication, inducement, estoppel or
30 otherwise. Any license under such intellectual property rights must be
31 express and approved by Intel in writing.
32
33 Unless otherwise agreed by Intel in writing, you may not remove or alter
34 this notice or any other notice embedded in Materials by Intel or
35 Intel's suppliers or licensors in any way.
36
37 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
38 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
39 the terms of your license agreement with Intel or your vendor. This file may
40 be modified by the user, subject to additional terms of the license agreement.
41
42 @par Specification Reference:
43 **/
44 #ifndef _PCIE_REGS_H_
45 #define _PCIE_REGS_H_
46
47 #include <IndustryStandard/Pci30.h>
48
49 //
50 // PCI type 0 Header
51 //
52 #define R_PCI_PI_OFFSET 0x09
53 #define R_PCI_SCC_OFFSET 0x0A
54 #define R_PCI_BCC_OFFSET 0x0B
55
56 #define R_PCI_BAR0_OFFSET 0x10
57 #define R_PCI_BAR5_OFFSET 0x24
58
59 //
60 // PCI type 1 Header
61 //
62 #define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Register
63 #define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordinate Bus Number
64 #define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondary Bus Number
65 #define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary Bus Number
66 #define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN | B_PCI_BRIDGE_BNUM_SCBN)
67
68 #define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and Limit Register
69
70 #define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base and Limit Register
71 #define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory Limit
72 #define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory Base
73
74 #define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable Memory Base and Limit Register
75 #define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetchable Memory Limit
76 #define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit Indicator
77 #define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetchable Memory Base
78 #define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit Indicator
79
80 #define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable Memory Base Upper 32-Bit Register
81 #define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF
82
83 #define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable Memory Limit Upper 32-Bit Register
84 #define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF
85
86 //
87 // PCI type 2 Header
88 //
89 #define R_PCI_CARDBUS_BRIDGE_SVID 0x40 ///< Subsystem Vendor ID
90
91 //
92 // PCIE capabilities register
93 //
94 #define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID
95 #define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capability Capability ID Pointer
96
97 //
98 // PCI Express Capability List Register (CAPID:10h)
99 //
100 #define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Capabilities Register (Offset 02h)
101 #define S_PCIE_XCAP 2
102 #define B_PCIE_XCAP_SI BIT8 ///< Slot Implemented
103 #define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BIT4) ///< Device/Port Type
104 #define N_PCIE_XCAP_DT 4
105
106 #define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabilities Register (Offset 04h)
107 #define S_PCIE_DCAP 4
108 #define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Error Reporting
109 #define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) ///< Endpoint L1 Acceptable Latency
110 #define N_PCIE_DCAP_E1AL 9
111 #define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///< Endpoint L0s Acceptable Latency
112 #define N_PCIE_DCAP_E0AL 6
113 #define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///< Max_Payload_Size Supported
114
115 #define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control Register (Offset 08h)
116 #define B_PCIE_DCTL_NS BIT11 ///< Enable No Snoop
117 #define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///< Max_Payload_Size
118 #define N_PCIE_DCTL_MPS 5
119 #define B_PCIE_DCTL_RO BIT4 ///< Enable Relaxed Ordering
120 #define B_PCIE_DCTL_URE BIT3 ///< Unsupported Request Reporting Enable
121 #define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Reporting Enable
122 #define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Error Reporting Enable
123 #define B_PCIE_DCTL_CEE BIT0 ///< Correctable Error Reporting Enable
124
125 #define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status Register (Offset 0Ah)
126 #define B_PCIE_DSTS_TDP BIT5 ///< Transactions Pending
127 #define B_PCIE_DSTS_APD BIT4 ///< AUX Power Detected
128 #define B_PCIE_DSTS_URD BIT3 ///< Unsupported Request Detected
129 #define B_PCIE_DSTS_FED BIT2 ///< Fatal Error Detected
130 #define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Error Detected
131 #define B_PCIE_DSTS_CED BIT0 ///< Correctable Error Detected
132
133 #define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilities Register (Offset 0Ch)
134 #define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optionality Compliance
135 #define B_PCIE_LCAP_CPM BIT18 ///< Clock Power Management
136 #define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) ///< L1 Exit Latency
137 #define N_PCIE_LCAP_EL1 15
138 #define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) ///< L0s Exit Latency
139 #define N_PCIE_LCAP_EL0 12
140 #define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Active State Power Management (ASPM) Support
141 #define B_PCIE_LCAP_APMS_L0S BIT10
142 #define B_PCIE_LCAP_APMS_L1 BIT11
143 #define N_PCIE_LCAP_APMS 10
144 #define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum Link Width
145 #define N_PCIE_LCAP_MLW 4
146 #define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Max Link Speed
147 #define V_PCIE_LCAP_MLS_GEN3 3
148 #define V_PCIE_LCAP_MLS_GEN4 4
149 #define V_PCIE_LCAP_MLS_GEN5 5
150
151 #define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control Register (Offset 10h)
152 #define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock Power Management
153 #define B_PCIE_LCTL_ES BIT7 ///< Extended Synch
154 #define B_PCIE_LCTL_CCC BIT6 ///< Common Clock Configuration
155 #define B_PCIE_LCTL_RL BIT5 ///< Retrain Link
156 #define B_PCIE_LCTL_LD BIT4 ///< Link Disable
157 #define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Active State Power Management (ASPM) Control
158 #define V_PCIE_LCTL_ASPM_L0S 1
159 #define V_PCIE_LCTL_ASPM_L1 2
160 #define V_PCIE_LCTL_ASPM_L0S_L1 3
161
162 #define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Register (Offset 12h)
163 #define B_PCIE_LSTS_LA BIT13 ///< Data Link Layer Link Active
164 #define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Configuration
165 #define B_PCIE_LSTS_LT BIT11 ///< Link Training
166 #define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated Link Width
167 #define N_PCIE_LSTS_NLW 4
168 #define V_PCIE_LSTS_NLW_1 0x0010
169 #define V_PCIE_LSTS_NLW_2 0x0020
170 #define V_PCIE_LSTS_NLW_4 0x0040
171 #define B_PCIE_LSTS_CLS 0x000F ///< Current Link Speed
172 #define V_PCIE_LSTS_CLS_GEN1 1
173 #define V_PCIE_LSTS_CLS_GEN2 2
174 #define V_PCIE_LSTS_CLS_GEN3 3
175
176 #define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilities Register (Offset 14h)
177 #define S_PCIE_SLCAP 4
178 #define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical Slot Number
179 #define N_PCIE_SLCAP_PSN 19 ///< Physical Slot Number
180 #define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Power Limit Scale
181 #define N_PCIE_SLCAP_SLS 15 ///< Slot Power Limit Scale
182 #define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Power Limit Value
183 #define N_PCIE_SLCAP_SLV 7 ///< Slot Power Limit Value
184 #define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capable
185 #define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surprise
186 #define B_PCIE_SLCAP_PIP BIT4 ///< Power indicator present
187 #define B_PCIE_SLCAP_AIP BIT3 ///< Attention indicator present
188 #define B_PCIE_SLCAP_MRLSP BIT2 ///< MRL Sensor present
189 #define B_PCIE_SLCAP_PCP BIT1 ///< Power controller present
190 #define B_PCIE_SLCAP_ABP BIT0 ///< Attention button present
191
192 #define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control Register (Offset 18h)
193 #define S_PCIE_SLCTL 2
194 #define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Interrupt Enable
195 #define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detect Changed Enable
196
197 #define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Register (Offset 1Ah)
198 #define S_PCIE_SLSTS 2
199 #define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detect State
200 #define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detect Changed
201
202 #define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control Register (Offset 1Ch)
203 #define S_PCIE_RCTL 2
204 #define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt Enable
205 #define B_PCIE_RCTL_SFE BIT2 ///< System Error on Fatal Error Enable
206 #define B_PCIE_RCTL_SNE BIT1 ///< System Error on Non-Fatal Error Enable
207 #define B_PCIE_RCTL_SCE BIT0 ///< System Error on Correctable Error Enable
208
209 #define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Register (Offset 20h)
210 #define S_PCIE_RSTS 4
211
212 #define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabilities 2 Register (Offset 24h)
213 #define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBFF Supported
214 #define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism Supported
215 #define B_PCIE_DCAP2_PX10BTCS BIT16 ///< 10-Bit Tag Completer Support
216 #define B_PCIE_DCAP2_PX10BTRS BIT17 ///< 10-Bit Tag Requester Support
217
218 #define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control 2 Register (Offset 28h)
219 #define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBFF Enable
220 #define N_PCIE_DCTL2_OBFFEN 13
221 #define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled
222 #define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAKE# signaling
223 #define B_PCIE_DCTL2_PX10BTRE BIT12 ///< 10-Bit Tag Requester Enable
224 #define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism Enable
225 #define B_PCIE_DCTL2_AEB BIT7 ///< AtomicOP Egress Blocking Enable
226 #define B_PCIE_DCTL2_CTD BIT4 ///< Completion Timeout Disable
227 #define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BIT0) ///< Completion Timeout Value
228 #define V_PCIE_DCTL2_CTV_DEFAULT 0x0
229 #define V_PCIE_DCTL2_CTV_40MS_50MS 0x5
230 #define V_PCIE_DCTL2_CTV_160MS_170MS 0x6
231 #define V_PCIE_DCTL2_CTV_400MS_500MS 0x9
232 #define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA
233
234 #define R_PCIE_LCAP2_OFFSET 0x2C
235 #define B_PCIE_LCAP2_TRPDS BIT24
236 #define B_PCIE_LCAP2_RPDS BIT23
237 #define B_PCIE_LCAP2_LSOSRSS 0x7F0000
238 #define N_PCIE_LCAP2_LSOSRSS 16
239 #define B_PCIE_LCAP2_LSOSGSSV 0xFE00
240 #define N_PCIE_LCAP2_LSOSGSSV 9
241 #define B_PCIE_LCAP2_CS BIT8
242 #define N_PCIE_LCAP2_CS 8
243 #define B_PCIE_LCAP2_SLSV BIT1
244 #define N_PCIE_LCAP2_SLSV 1
245
246 #define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2 Register (Offset 30h)
247 #define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-emphasis (0 = -6dB, 1 = -3.5dB)
248 #define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BIT0) ///< Target Link Speed
249 #define V_PCIE_LCTL2_TLS_GEN1 1
250 #define V_PCIE_LCTL2_TLS_GEN2 2
251 #define V_PCIE_LCTL2_TLS_GEN3 3
252 #define V_PCIE_LCTL2_TLS_GEN4 4
253 #define V_PCIE_LCTL2_TLS_GEN5 5
254
255 #define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 Register (Offset 32h)
256 #define B_PCIE_LSTS2_LER BIT5 ///< Link Equalization Request
257 #define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization Phase 3 Successful
258 #define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization Phase 2 Successful
259 #define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization Phase 1 Successful
260 #define B_PCIE_LSTS2_EC BIT1 ///< Equalization Complete
261 #define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emphasis Level
262
263 #define R_PCIE_FPBCAPR 0xBA4
264 #define B_FPBCAPR_FPBRIDS BIT0
265 #define B_FPBCAPR_FPBMEMLS BIT1
266 #define B_FPBCAPR_FPBMEMLS_OFFSET 1
267 #define B_FPBCAPR_FPBMEMHS BIT2
268 #define B_FPBCAPR_FPBMEMHS_OFFSET 2
269 #define B_FPBCAPR_FPBRIDVECSIZES_MASK 0x700
270 #define N_FPBCAPR_FPBRIDVECSIZES_OFFSET 8
271 #define V_FPBCAPR_FPBRIDVECSIZES 0x2
272 #define B_FPBCAPR_FPBMEMLVECSIZES_MASK 0x70000
273 #define N_FPBCAPR_FPBMEMLVECSIZES_OFFSET 16
274 #define V_FPBCAPR_FPBMEMLVECSIZES 0x1
275 #define B_FPBCAPR_FPBMEMHVECSIZES_MASK 0x7000000
276 #define N_FPBCAPR_FPBMEMHVECSIZES_OFFSET 24
277 #define V_FPBCAPR_FPBMEMHVECSIZES 0x0
278
279 #define V_PCIE_SVCAP_CID 0x0D
280 #define V_PCIE_MID_CID 0x05
281 #define V_PCIE_XCAP_CV 0x02
282 #define V_PCIE_CLIST_CID 0x10
283
284 //
285 // PCI Power Management Capability (CAPID:01h)
286 //
287 #define R_PCIE_PMC_OFFSET 0x02 ///< Power Management Capabilities Register
288 #define S_PCIE_PMC 2
289 #define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 | BIT12 | BIT11) ///< PME Support
290 #define B_PCIE_PMC_PMEC BIT3 ///< PME Clock
291
292 #define R_PCIE_PMCS_OFFST 0x04 ///< Power Management Status/Control Register
293 #define S_PCIE_PMCS 4
294 #define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clock Control Enable
295 #define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support
296 #define B_PCIE_PMCS_PMES BIT15 ///< PME_Status
297 #define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable
298 #define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset
299 #define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power State
300 #define V_PCIE_PMCS_PS_D0 0
301 #define V_PCIE_PMCS_PS_D3H 3
302
303 //
304 // PCI Subsystem Vendor Capability
305 //
306 #define PCI_CAP_ID_SUBSYSTEM_VENDOR 0x0D
307 #define R_PCIE_SUBSYSTEM_VENDOR_ID_OFFSET 0x04 ///< Subsystem Vendor IDs
308
309
310 //
311 // PCIE Extension Capability Register
312 //
313 #define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Capability Offset
314 #define N_PCIE_EXCAP_NCO 20
315 #define V_PCIE_EXCAP_NCO_LISTEND 0
316 #define B_PCIE_EXCAP_CV 0x000F0000 ///< Capability Version
317 #define N_PCIE_EXCAP_CV 16
318 #define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capability ID
319
320 //
321 // Advanced Error Reporting Capability (CAPID:0001h)
322 //
323 #define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID
324 #define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable Error Mask Register
325 #define B_PCIE_EX_UEM_CT BIT14 ///< Completion Timeout Mask
326 #define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Completion
327
328 //
329 //VC capabilty register (CAPID:0002h)
330 //
331 #define V_PCIE_EX_VC_CID 0x0002 ///< Capability ID
332
333 //
334 // ACS Extended Capability (CAPID:000Dh)
335 //
336 #define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID
337 #define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability Register
338 //#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control Register (NOTE: register size in PCIE spce is not match the PCH register size)
339
340
341 //
342 // Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h)
343 //
344 #define R_PCIE_LTRECH_CID 0x0018
345
346 #define R_PCIE_LTRECH_MSLR_OFFSET 0x04
347 #define B_PCIE_LTRECH_MSLR_VALUE 0x3FF
348 #define N_PCIE_LTRECH_MSLR_VALUE 0
349 #define B_PCIE_LTRECH_MSLR_SCALE 0x1C00
350 #define N_PCIE_LTRECH_MSLR_SCALE 10
351
352 #define R_PCIE_LTRECH_MNSLR_OFFSET 0x06
353 #define B_PCIE_LTRECH_MNSLR_VALUE 0x3FF
354 #define N_PCIE_LTRECH_MNSLR_VALUE 0
355 #define B_PCIE_LTRECH_MNSLR_SCALE 0x1C00
356 #define N_PCIE_LTRECH_MNSLR_SCALE 10
357
358 //
359 // Secondary PCI Express Extended Capability Header (CAPID:0019h)
360 //
361 #define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID
362 #define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3 Register
363 #define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equalization
364 #define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Status
365 #define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan 1 Equalization Control Register (Offset 0Ch)
366 #define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream Port Lane 1 Transmitter Preset
367 #define N_PCIE_EX_L01EC_UPL1TP 24
368 #define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstream Port Lane 1 Transmitter Preset
369 #define N_PCIE_EX_L01EC_DPL1TP 16
370 #define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream Port Transmitter Preset
371 #define N_PCIE_EX_L01EC_UPL0TP 8
372 #define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstream Port Transmitter Preset
373 #define N_PCIE_EX_L01EC_DPL0TP 0
374
375 #define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lane 3 Equalization Control Register (Offset 10h)
376 #define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream Port Lane 3 Transmitter Preset
377 #define N_PCIE_EX_L23EC_UPL3TP 24
378 #define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstream Port Lane 3 Transmitter Preset
379 #define N_PCIE_EX_L23EC_DPL3TP 16
380 #define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream Port Lane 2 Transmitter Preset
381 #define N_PCIE_EX_L23EC_UPL2TP 8
382 #define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstream Port Lane 2 Transmitter Preset
383 #define N_PCIE_EX_L23EC_DPL2TP 0
384
385 //
386 // Downstream Port Containment Extended Capability register (CAPID:001Dh)
387 //
388 #define V_PCIE_EX_DPC_CID 0x001D ///< Capability ID
389 #define R_PCIE_EX_DPC_CAP_OFFSET 0x04
390 #define R_PCIE_EX_DPCCAPR_OFFSET 0x4
391 #define R_PCIE_EX_DPCCTRL_OFFSET 0x6
392 #define R_PCIE_EX_DPCSR_OFFSET 0x8
393 #define R_PCIE_EX_DPCESIDR_OFFSET 0xA
394 #define R_PCIE_EX_RPPIOSR_OFFSET 0xC
395 #define R_PCIE_EX_RPPIOMR_OFFSET 0x10
396 #define R_PCIE_EX_RPPIOVR_OFFSET 0x14
397 #define R_PCIE_EX_RPPIOSER_OFFSET 0x18
398 #define R_PCIE_EX_RPPIOER_OFFSET 0x1C
399 #define R_PCIE_EX_RPPIOHLR_OFFSET 0x20
400
401 //
402 // L1 Sub-States Extended Capability Register (CAPID:001Eh)
403 //
404 #define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID
405 #define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States Capabilities
406 #define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpower_on value
407 #define N_PCIE_EX_L1SCAP_PTV 19
408 #define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpower_on scale
409 #define N_PCIE_EX_L1SCAP_PTPOS 16
410 #define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mode Restore time
411 #define N_PCIE_EX_L1SCAP_CMRT 8
412 #define V_PCIE_EX_L1SCAP_PTPOS_2us 0
413 #define V_PCIE_EX_L1SCAP_PTPOS_10us 1
414 #define V_PCIE_EX_L1SCAP_PTPOS_100us 2
415 #define B_PCIE_EX_L1SCAP_L1SSES BIT5 ///< CLKREQ Acceleration Supported
416 #define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates supported
417 #define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supported
418 #define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supported
419 #define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 supported
420 #define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 supported
421 #define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States Control 1
422 #define B_PCIE_EX_L1SCTL1_L1SSEIE BIT4
423 #define B_PCIE_EX_L1SCTL1_L12LTRTLSV 0xE0000000 ///< L1.2 LTR Threshold Latency Scale Value
424 #define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29
425 #define B_PCIE_EX_L1SCTL1_L12LTRTLV 0x03FF0000 ///< L1.2 LTR Threshold Latency Value
426 #define N_PCIE_EX_L1SCTL1_L12LTRTLV 16
427 #define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States Control 2
428 #define N_PCIE_EX_L1SCTL2_POWT 3
429 #define B_PCIE_EX_CTRL2_PMETOFD BIT6
430
431 //
432 // PTM Extended Capability Register (CAPID:001Fh)
433 //
434 #define V_PCIE_EX_PTM_CID 0x001F ///< Capability ID
435 #define R_PCIE_EX_PTMCAP_OFFSET 0x04 ///< PTM Capabilities
436 #define B_PCIE_EX_PTMCAP_PTMRC BIT2 ///< PTM Root Capable
437 #define B_PCIE_EX_PTMCAP_PTMRSPC BIT1 ///< PTM Responder Capable
438 #define R_PCIE_EX_PTMCTL_OFFSET 0x08 ///< PTM Control Register
439
440 //
441 // Base Address Offset
442 //
443 #define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address Register 0
444 #define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address Register 1
445 #define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address Register 2
446 #define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address Register 3
447 #define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address Register 4
448 #define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address Register 5
449 #define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)
450 #define B_PCI_BAR_MEMORY_TYPE_64 BIT2
451
452 //
453 // Data Link Feature Extended Capability Header (CAPID:0025h)
454 //
455 #define V_PCIE_EX_DLFECH_CID 0x0025 ///< Capability ID
456
457 //
458 // Physical Layer 16.0 GT/s Extended Capability Header (CAPID:0026h)
459 //
460 #define V_PCIE_EX_PL16GECH_CID 0x0026 ///< Capability ID
461
462 //
463 // Physical Layer 16.0 GT/s Margining Extended Capability Header (CAPID:0027h)
464 //
465 #define V_PCIE_EX_PL16MECH_CID 0x0027 ///< Capability ID
466
467 //
468 // Physical Layer 16.0 GT/s Margining Extended Capability Header (CAPID:0030h) (RPL)
469 //
470 #define V_PCIE_EX_IDEEXTCAPHDR_CID 0x0030 ///< Capability ID
471
472 //
473 // Physical Layer 32.0 GT/s Extended Capability Header (CAPID:002Ah)
474 //
475 #define V_PCIE_EX_G5ECH_CID 0x002A ///< Capability ID
476
477 //
478 // Alternate Protocol Extended Capability Header (CAPID:002Bh)
479 //
480 #define V_PCIE_EX_APEC_CID 0x002B ///< Capability ID
481
482 //
483 // Flattening Portal Bridge Capability Header (CAPID:0015h)
484 //
485 #define V_PCIE_FPBCAP_CID 0x0015 ///< Capability ID
486 #define R_PCIE_FPBCAP 0xBA0
487 #define N_PCIE_FPBCAP_NCO_OFFSET 8
488 #define B_PCIE_FPBCAP_NCO_MASK 0xFF00
489 #define N_PCIE_FPBCAP_CID_OFFSET 0
490 #define B_PCIE_FPBCAP_CID_MASK 0xFF
491
492 //
493 // PCI Express Extended Capability Header
494 //
495 #define R_PCIE_CFG_EXCAP_OFFSET 0x100
496
497 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieRpMacroDefinition.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
PcieRpMacroDefinition.h File Reference

This file contains definitions of PCIE RP MACRO. More...

Go to the source code of this file.

Detailed Description

This file contains definitions of PCIE RP MACRO.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PcieRpMacroDefinition.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieRpMacroDefinition.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PcieRpMacroDefinition.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of PCIE RP MACRO.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PCIE_RP_MACRO_DEFINITION_H
36 #define _PCIE_RP_MACRO_DEFINITION_H
37
38 //
39 // PCIE RP Type MACRO Definitions
40 //
41
42
43 // Defining MACRO Value for PCH PCIE RP Type.
44 #ifndef PCIE_RP_TYPE_PCH
45 #define PCIE_RP_TYPE_PCH 0x02
46 #endif
47
48 // Defining MACRO Value for CPU PCIE RP Type.
49 #ifndef PCIE_RP_TYPE_CPU
50 #define PCIE_RP_TYPE_CPU 0x04
51 #endif
52
53 // Defining MACRO Value for ITBT PCIE RP Type.
54 #ifndef PCIE_RP_TYPE_ITBT
55 #define PCIE_RP_TYPE_ITBT 0x08
56 #endif
57
58
59 //
60 // PCIE EP Type MACRO Definitions
61 //
62
63 // Note:- Defining only those EndPoint Device Type Macro, those doesn't fully
64 // compliance with PCIE Standard Power Sequence. For these device we might need
65 // additional flow in Power Sequence.
66
67
68 // Defining MACRO Value for Generic PCIE EP Type.
69 #ifndef PCIE_EP_TYPE_GENERIC_PCIE
70 #define PCIE_EP_TYPE_GENERIC_PCIE 0x02
71 #endif
72
73 // Defining MACRO Value for Discrete Thunderbolt EP Type.
74 #ifndef PCIE_EP_TYPE_DTBT
75 #define PCIE_EP_TYPE_DTBT 0x04
76 #endif
77
78 // Defining MACRO Value for Invalid EP Type.
79 #ifndef PCIE_EP_TYPE_INVALID
80 #define PCIE_EP_TYPE_INVALID 0xFF
81 #endif
82
83 #endif // _PCIE_RP_MACRO_DEFINITION_H
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiAmtPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiAmtPolicyLib.h File Reference

Prototype of the AmtPolicyLibPei library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for PeiAmtPolicyLib.h:

Go to the source code of this file.

Functions

VOID | AmtPrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
Print AMT config block and serial out. More...
UINT16 | AmtGetConfigBlockTotalSize (VOID)
Get AMT config block table total size. More...
EFI_STATUS | AmtAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
AmtAddConfigBlocks add all AMT config blocks. More...

Detailed Description

Prototype of the AmtPolicyLibPei library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiAmtPolicyLib.h.

Function Documentation

◆ AmtAddConfigBlocks()

EFI_STATUS AmtAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

AmtAddConfigBlocks add all AMT config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add AMT config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ AmtGetConfigBlockTotalSize()

UINT16 AmtGetConfigBlockTotalSize ( VOID )

Get AMT config block table total size.

Return values
Size of AMT config block table

◆ AmtPrintPolicyPpi()

VOID AmtPrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

Print AMT config block and serial out.

Parameters
[in] SiPolicyPpi The RC Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiAmtPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiAmtPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the AmtPolicyLibPei library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_AMT_POLICY_LIB_H_
36 #define _PEI_AMT_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39
40 /**
41 Print AMT config block and serial out.
42
43 @param[in] SiPolicyPpi The RC Policy PPI instance
44 **/
45 VOID
46 EFIAPI
47 AmtPrintPolicyPpi (
48 IN SI_POLICY_PPI *SiPolicyPpi
49 );
50
51 /**
52 Get AMT config block table total size.
53
54 @retval Size of AMT config block table
55 **/
56 UINT16
57 EFIAPI
58 AmtGetConfigBlockTotalSize (
59 VOID
60 );
61
62 /**
63 AmtAddConfigBlocks add all AMT config blocks.
64
65 @param[in] ConfigBlockTableAddress The pointer to add AMT config blocks
66
67 @retval EFI_SUCCESS The policy default is initialized.
68 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
69 **/
70 EFI_STATUS
71 EFIAPI
72 AmtAddConfigBlocks (
73 IN VOID *ConfigBlockTableAddress
74 );
75
76 #endif // _PEI_AMT_POLICY_LIB_H_
AmtGetConfigBlockTotalSize
UINT16 AmtGetConfigBlockTotalSize(VOID)
Get AMT config block table total size.
AmtPrintPolicyPpi
VOID AmtPrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
Print AMT config block and serial out.
AmtAddConfigBlocks
EFI_STATUS AmtAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
AmtAddConfigBlocks add all AMT config blocks.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiDxeSmmReserveMmio64SizeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiDxeSmmReserveMmio64SizeLib.h File Reference

PEI/DXE/SMM library for reserved 64-bit MMIO space. More...

Go to the source code of this file.

Functions

UINT64 ReserveMmio64Size (VOID)
The function return the 64 bit MMIO size to reserve. More...

Detailed Description

PEI/DXE/SMM library for reserved 64-bit MMIO space.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiDxeSmmReserveMmio64SizeLib.h.

Function Documentation

◆ ReserveMmio64Size()

UINT64 ReserveMmio64Size ( VOID )

The function return the 64 bit MMIO size to reserve.

Return values
The 64-bit MMIO size
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiDxeSmmReserveMmio64SizeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiDxeSmmReserveMmio64SizeLib.h
Go to the documentation of this file.
1 /** @file
2 PEI/DXE/SMM library for reserved 64-bit MMIO space.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
37 #define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
38
39 /**
40 The function return the 64 bit MMIO size to reserve.
41
42 @retval The 64-bit MMIO size
43 **/
44 UINT64
45 ReserveMmio64Size (
46 VOID
47 );
48
49 #endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
ReserveMmio64Size
UINT64 ReserveMmio64Size(VOID)
The function return the 64 bit MMIO size to reserve.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Classes | Typedefs
PeiITbtConfig.h File Reference

Header file for TBT PEI Policy. More...

#include <ConfigBlock.h>
#include <TcssInfo.h>
#include <PeiITbtGenericStructure.h>
Include dependency graph for PeiITbtConfig.h:

Go to the source code of this file.

Classes

struct _PEI_ITBT_CONFIG
ITBT PEI configuration
Revision 1: More...

Typedefs

typedef struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG
ITBT PEI configuration
Revision 1: More...

Detailed Description

Header file for TBT PEI Policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtConfig.h.

Typedef Documentation

◆ PEI_ITBT_CONFIG

typedef struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG

ITBT PEI configuration
Revision 1:

  • Initial version. Revision 2:
  • Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
PeiITbtConfig.h
Go to the documentation of this file.
1 /** @file
2 Header file for TBT PEI Policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_ITBT_CONFIG_H_
37 #define _PEI_ITBT_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #include <TcssInfo.h>
41 #include <PeiITbtGenericStructure.h>
42
43 #pragma pack(push, 1)
44 #define PEI_ITBT_CONFIG_REVISION 2
45
46 /**
47 ITBT PEI configuration\n
48 <b>Revision 1</b>:
49 - Initial version.
50 <b>Revision 2</b>:
51 - Add ITbtPcieTunnelingForUsb4, deprecated ITbtSecurityLevel.
52 **/
53 typedef struct _PEI_ITBT_CONFIG {
54 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
55 ITBT_GENERIC_CONFIG ITbtGenericConfig; ///< ITbt Common Configuration
56 ITBT_ROOTPORT_CONFIG ITbtRootPortConfig [MAX_ITBT_PCIE_PORT]; ///< iTbt Root Port Configuration
57 UINT16 ITbtDmaLtr [MAX_HOST_ITBT_DMA_NUMBER]; ///< iTbt Host controller DMA LTR value
58 } PEI_ITBT_CONFIG;
59 #pragma pack(pop)
60
61 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
_PEI_ITBT_CONFIG::ITbtGenericConfig
ITBT_GENERIC_CONFIG ITbtGenericConfig
ITbt Common Configuration.
Definition: PeiITbtConfig.h:55
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_PEI_ITBT_CONFIG
ITBT PEI configuration Revision 1:
Definition: PeiITbtConfig.h:53
_PEI_ITBT_CONFIG::ITbtDmaLtr
UINT16 ITbtDmaLtr[MAX_HOST_ITBT_DMA_NUMBER]
iTbt Host controller DMA LTR value
Definition: PeiITbtConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PeiITbtGenericStructure.h
ITBT Policy definition to be referred in both PEI and DXE phase.
_PEI_ITBT_CONFIG::ITbtRootPortConfig
ITBT_ROOTPORT_CONFIG ITbtRootPortConfig[MAX_ITBT_PCIE_PORT]
iTbt Root Port Configuration
Definition: PeiITbtConfig.h:56
PEI_ITBT_CONFIG
struct _PEI_ITBT_CONFIG PEI_ITBT_CONFIG
ITBT PEI configuration Revision 1:
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
_PEI_ITBT_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: PeiITbtConfig.h:54
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtGenericStructure.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Typedefs
PeiITbtGenericStructure.h File Reference

ITBT Policy definition to be referred in both PEI and DXE phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | _ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure More...
struct | _ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB. More...

Typedefs

typedef struct _ITBT_ROOTPORT_CONFIG | ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
typedef struct _ITBT_GENERIC_CONFIG | ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB.

Detailed Description

ITBT Policy definition to be referred in both PEI and DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtGenericStructure.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtGenericStructure.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PeiITbtGenericStructure.h
Go to the documentation of this file.
1 /** @file
2 ITBT Policy definition to be referred in both PEI and DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _ITBT_POLICY_GENERIC_H_
37 #define _ITBT_POLICY_GENERIC_H_
38
39 #pragma pack(push, 1)
40
41 ///
42 /// iTBT RootPort Data Structure
43 ///
44 typedef struct _ITBT_ROOTPORT_CONFIG{
45 UINT8 ITbtPcieRootPortEn; ///< Disable/Enable iTBT PCIe Root Port
46 UINT8 Reserved[3]; ///< Reserved for DWORD alignment
47 } ITBT_ROOTPORT_CONFIG;
48
49 ///
50 /// ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and HOB
51 ///
52 typedef struct _ITBT_GENERIC_CONFIG{
53 /**
54 Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for execution of following
55 mailbox communication.
56 After applying Force Power Thunderbolt BIOS shall poll for iTBT readiness for mailbox communication
57 If TBT cable is disconnected, iTBT microcontrollers are in lower power state.
58 To ensure successful mailbox execution, independently on presence of TBT cable, TBT BIOS shall bring iTBT
59 microcontrollers up by applying Force Power. iTBT microcontrollers will wake up either due to TBT cable presence or
60 Force Power event.
61 <b>(Test)</b>
62 <b> default is 500 ms </b>
63 **/
64 UINT16 ITbtForcePowerOnTimeoutInMs;
65 /**
66 Timeout value while sending connect topology mailbox command in order to bring all connected TBT devices are available
67 on PCIe before BIOS will enumerate them in BDS
68 <b>(Test)</b>
69 <b> default is 5000 ms </b>
70 **/
71 UINT16 ITbtConnectTopologyTimeoutInMs;
72 UINT8 ITbtSecurityLevel; ///< iTbt Security Level <b>Deprecated</b>
73 UINT8 ITbtPcieTunnelingForUsb4; ///< Disable/Enable PCIe tunneling for USB4. <b>default is enable</b>
74 UINT8 Usb4CmMode; ///< USB4 CM mode
75 UINT8 Reserved[1]; ///< Reserved for DWORD alignment
76 } ITBT_GENERIC_CONFIG;
77
78 #pragma pack(pop)
79
80 #endif
_ITBT_GENERIC_CONFIG::ITbtForcePowerOnTimeoutInMs
UINT16 ITbtForcePowerOnTimeoutInMs
Timeout value for forcing power iTBT controller on every boot/reboot/Sx exit as a precondition for ex...
Definition: PeiITbtGenericStructure.h:64
_ITBT_ROOTPORT_CONFIG::ITbtPcieRootPortEn
UINT8 ITbtPcieRootPortEn
Disable/Enable iTBT PCIe Root Port.
Definition: PeiITbtGenericStructure.h:45
_ITBT_ROOTPORT_CONFIG::Reserved
UINT8 Reserved[3]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:46
_ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
Definition: PeiITbtGenericStructure.h:44
_ITBT_GENERIC_CONFIG::Usb4CmMode
UINT8 Usb4CmMode
USB4 CM mode.
Definition: PeiITbtGenericStructure.h:74
_ITBT_GENERIC_CONFIG::ITbtConnectTopologyTimeoutInMs
UINT16 ITbtConnectTopologyTimeoutInMs
Timeout value while sending connect topology mailbox command in order to bring all connected TBT devi...
Definition: PeiITbtGenericStructure.h:71
_ITBT_GENERIC_CONFIG::ITbtSecurityLevel
UINT8 ITbtSecurityLevel
iTbt Security Level Deprecated
Definition: PeiITbtGenericStructure.h:72
ITBT_GENERIC_CONFIG
struct _ITBT_GENERIC_CONFIG ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
_ITBT_GENERIC_CONFIG::ITbtPcieTunnelingForUsb4
UINT8 ITbtPcieTunnelingForUsb4
Disable/Enable PCIe tunneling for USB4. default is enable
Definition: PeiITbtGenericStructure.h:73
_ITBT_GENERIC_CONFIG
ITBT Controller Data Structure to be used cross to RP and controller to be shared by CONFIG_BLOCK and...
Definition: PeiITbtGenericStructure.h:52
ITBT_ROOTPORT_CONFIG
struct _ITBT_ROOTPORT_CONFIG ITBT_ROOTPORT_CONFIG
iTBT RootPort Data Structure
_ITBT_GENERIC_CONFIG::Reserved
UINT8 Reserved[1]
Reserved for DWORD alignment.
Definition: PeiITbtGenericStructure.h:75
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiITbtPolicyLib.h File Reference

Prototype of the PeiITbtPolicyLib library. More...

#include <Ppi/SiPolicy.h>
#include <Library/ConfigBlockLib.h>
#include <TcssDataHob.h>
Include dependency graph for PeiITbtPolicyLib.h:

Go to the source code of this file.

Functions

VOID | ITbtPrintPolicy (IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase PreMem policy. More...
UINT16 | ITbtGetConfigBlockTotalSize (VOID)
Get TBT config block table total size. More...
EFI_STATUS | ITbtAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
ITbtAddConfigBlocks add all TBT config blocks. More...

Detailed Description

Prototype of the PeiITbtPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiITbtPolicyLib.h.

Function Documentation

◆ ITbtAddConfigBlocks()

EFI_STATUS ITbtAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

ITbtAddConfigBlocks add all TBT config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add TBT config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ ITbtGetConfigBlockTotalSize()

UINT16 ITbtGetConfigBlockTotalSize ( VOID )

Get TBT config block table total size.

Return values
Size of TBT config block table

◆ ITbtPrintPolicy()

VOID ITbtPrintPolicy ( IN SI_POLICY_PPI * SiPolicyPpi )

This function prints the PEI phase PreMem policy.

Parameters
[in] SiPolicyPpi Instance of SI_POLICY_PPI
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiITbtPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiITbtPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the PeiITbtPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_TBT_POLICY_LIB_H_
36 #define _PEI_TBT_POLICY_LIB_H_
37 #include <Ppi/SiPolicy.h>
38 #include <Library/ConfigBlockLib.h>
39 #include <TcssDataHob.h>
40
41 /**
42 This function prints the PEI phase PreMem policy.
43
44 @param[in] SiPolicyPpi Instance of SI_POLICY_PPI
45 **/
46 VOID
47 EFIAPI
48 ITbtPrintPolicy (
49 IN SI_POLICY_PPI *SiPolicyPpi
50 );
51
52 /**
53 Get TBT config block table total size.
54
55 @retval Size of TBT config block table
56 **/
57 UINT16
58 EFIAPI
59 ITbtGetConfigBlockTotalSize (
60 VOID
61 );
62
63 /**
64 ITbtAddConfigBlocks add all TBT config blocks.
65
66 @param[in] ConfigBlockTableAddress The pointer to add TBT config blocks
67
68 @retval EFI_SUCCESS The policy default is initialized.
69 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
70 **/
71 EFI_STATUS
72 EFIAPI
73 ITbtAddConfigBlocks (
74 IN VOID *ConfigBlockTableAddress
75 );
76 #endif // _DXE_TBT_POLICY_LIB_H_
TcssDataHob.h
This file contains definitions of TCSS Data.
ITbtAddConfigBlocks
EFI_STATUS ITbtAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
ITbtAddConfigBlocks add all TBT config blocks.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
ITbtGetConfigBlockTotalSize
UINT16 ITbtGetConfigBlockTotalSize(VOID)
Get TBT config block table total size.
ITbtPrintPolicy
VOID ITbtPrintPolicy(IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase PreMem policy.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiMeLib.h File Reference

Header file for PEI Me functionality. More...

#include <BupMsgs.h>
#include <MkhiMsgs.h>
#include <Register/MeRegs.h>
#include <MeBiosPayloadData.h>
#include <IccMsgs.h>
Include dependency graph for PeiMeLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | PeiHeciSendCbmResetRequest (IN UINT8 ResetOrigin, IN UINT8 ResetType)
Send Core BIOS Reset Request Message through HECI to reset the system. More...
EFI_STATUS | PeiHeciGetFwCapsSkuMsg (OUT MEFWCAPS_SKU *RuleData)
Send Get Firmware SKU Request to ME. More...
EFI_STATUS | PeiHeciGetPlatformTypeMsg (OUT PLATFORM_TYPE_RULE_DATA *RuleData)
This message is sent by the BIOS or IntelR MEBX. More...
EFI_STATUS | PeiHeciGetFwFeatureStateMsg (OUT MEFWCAPS_SKU *RuleData)
The Get FW Feature Status message is based on MKHI interface. More...
EFI_STATUS | PeiHeciGetUnconfigOnRtcClearDisableMsg (OUT UINT32 *RuleData)
This message is sent by the BIOS in PEI phase to query ME Unconfig on RTC Clear Disable state. More...
EFI_STATUS | PeiHeciGetAmtBiosSyncInfo (OUT AMT_BIOS_SYNC_INFO *RuleData)
This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state. More...
EFI_STATUS | PeiHeciFwCapsSetRuleData (IN UINT32 RuleId, IN UINT8 RuleDataLength, IN UINT32 RuleData)
Send Set Rule Data Request to CSME. More...
EFI_STATUS | PeiHeciSetUnconfigOnRtcClearDisableMsg (IN UINT32 RuleData)
This message is sent by the BIOS in PEI phase to set ME Unconfig on RTC Clear Disable state. More...
EFI_STATUS | PeiHeciRequestDeviceOwnership (VOID)
Sends the NVM request device ownership message. More...
EFI_STATUS | PeiHeciDnxReqSet (OUT UINT32 *BiosAction)
Send DNX Request Set message. More...
EFI_STATUS | PeiHeciGetUnconfigureStatus (OUT UINT8 *UnconfigStatus)
Get ME Unconfiguration Status. More...
EFI_STATUS | PeiHeciSendDid (IN UINT32 ImrBaseLow, IN UINT32 ImrBaseHigh, IN UINT8 MemStatus, OUT UINT8 *MkhiResult, OUT UINT8 *Flags, OUT UINT8 *BiosAction, OUT UINT32 *PciImrBaseLow, OUT UINT32 *PciImrBaseHigh)
Send DRAM init done message through HECI to inform ME of memory initialization done. More...
EFI_STATUS | PeiHeciGetMbpMsg (OUT UINT32 *MbpEntriesNumber, IN OUT UINT32 *MbpItems, IN BOOLEAN SkibMbp)
Send Get MBP from FW. More...
EFI_STATUS | PeiHeciTerminateHeci (VOID)
Send command to terminate HECI communication in ME Debug Mode. More...
EFI_STATUS | PeiHeciGetImrSizeMsg (IN UINT32 BiosImrDisableMask0, IN UINT32 BiosImrDisableMask1, IN UINT32 PciImrSize, OUT UINT8 *MkhiResult, OUT UINT32 *ImrsSize, OUT UINT32 *Alignment)
This message is sent by the BIOS to retrieve from CSME total size of IMRs. More...
EFI_STATUS | PeiHeciBupManufacturingResetAndHalt (VOID)
Send Manufacturing Reset and Halt. More...
EFI_STATUS | PeiHeciGetErLog (OUT UINT8 *EventLogBuffer, IN UINT32 RemainingBufSize, IN OUT UINT32 *ReceivedLogSize, IN OUT UINT8 *LogEntryIndex, OUT UINT8 *RemainingEntries)
This function sends a command to CSME to get Log information of Measurements provided in CSME Extend Registers for BIOS to extend to TPM-PCR registers. More...
EFI_STATUS | PeiHeciSetEDebugModeState (IN BOOLEAN State)
Send Set eDebug Mode State. More...
EFI_STATUS | PeiHeciDataClear (VOID)
This command is sent by the BIOS to switch clear CSME data to image creation state. More...
EFI_STATUS | PeiHeciGetFwPayload (IN UINT32 LoadRequest, IN UINT32 BufferAddressLow, IN UINT32 BufferAddressHigh, IN OUT UINT32 *BufferSize, OUT UINT32 *IpLoaderStatus, OUT UINT8 *HashType, OUT UINT8 *Hash)
This message is sent by the BIOS to tell CSME that Buffer has been allocated for payload to be copied. More...
EFI_STATUS | PeiHeciGetDebugTokenData (OUT DEBUG_TOKEN_KNOB_DATA *KnobData)
This message is sent by the BIOS to retrieve debug token data from CSME. More...
EFI_STATUS | PeiHeciGetBiosSeed (IN SEED_PROPERTIES *BiosSeedProperties, IN UINT8 LockSeedGeneration, OUT UINT32 *EphemeralKeyCounter, OUT SEED_INFO *BiosSeedInfo, OUT UINT8 *BiosSeed)
This message is sent by the BIOS to retrieve device specific seed from CSME. More...
EFI_STATUS | PeiHeciIccBclkMsg (OUT UINT8 *WarmResetRequired)
Send ICC request through HECI to query if CSME FW requires the warm reset flow from a previous boot. More...
EFI_STATUS | PeiHeciReadFromMphy (OUT UINT8 *Data, IN UINT32 DataSize)
Get the Mphy data from CSME. More...
EFI_STATUS | PeiHeciSendHostResetNotificationMsg (VOID)
Send Host Reset Notification Message to determine if warm reset is required. More...
EFI_STATUS | HeciGetMkhiVersion (OUT MKHI_VERSION *MkhiVersion)
Get MKHI (Management Engine Kernel Host Interface) Version. More...
EFI_STATUS | PeiHeciReadChipsetInitMsg (IN OUT UINT8 *ChipsetInitTable, IN OUT UINT32 *ChipsetInitTableLen)
Reads the ChipsetInit table from the CSME FW. More...
EFI_STATUS | PeiHeciWriteChipsetInitMsg (IN UINT8 *ChipsetInitTable, IN UINT32 ChipsetInitTableLen)
Send the required system ChipsetInit Table to CSME FW. More...
EFI_STATUS | PeiHeciSetFileExMsg (IN UINT32 FileId, IN UINT32 Offset, IN UINT32 DataSize, IN UINT8 Flags, IN UINT8 *DataBuffer)
This message is sent by the BIOS to save data in a file stored in ME firmware NVM. More...
EFI_STATUS | PeiHeciCommitFilesMsg (VOID)
This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit previously set files. More...
BOOLEAN | MeHeciTimeoutsEnabled (VOID)
Read the ME policy to see if HECI timeouts are enabled. More...
BOOLEAN | MeHeciFullTrace (VOID)
Read the ME policy to see if Heci Full Trace are enabled. More...
BOOLEAN | MeHeci2Enabled (VOID)
Check if HECI2 should be removed from PCI space or not. More...
BOOLEAN | MeHeciMessageCheckEnabled (VOID)
Read the ME policy to see if HECI message check is enabled for Bios Boot Path. More...
BOOLEAN | MeMbpHobSkipped (VOID)
Read the ME policy to see if MBP HOB is skipped. More...
UINT32 | MeGetHeciBarAddress (IN ME_DEVICE MeDev)
Get default Heci1 BAR address from policy. More...
BOOLEAN | MeHeciD0I3Enabled (VOID)
Read the ME policy to see if D0I3 for HECI devices are enabled. More...
BOOLEAN | MeIsEnforceEDebugModeEnabled (VOID)
Read the ME policy to see if Enforcing Enhanced Debug Mode is enabled. More...
BOOLEAN | MeEndOfPostEnabled (VOID)
Check if End of Post Message is enabled in setup options. More...
BOOLEAN | MeIsAfterEndOfPost (VOID)
Checks if EndOfPost event already happened. More...
VOID | MeSetEndOfPostDone (VOID)
Set EndOfPost done.
VOID | RegisterMeReset (VOID)
Install ME call back function for reset2 ppi.
EFI_STATUS | InstallHeciPpi (VOID)
Install Heci PPIs needed in PEI phase. More...
EFI_STATUS | PeiHeciGetSoftStrpConfigMsg (IN UINT16 NumberOfControllers, IN OUT UINT8 *ControllerConfig)
Retrieves information on whether Pcie root port configuration SoftStrap override is being done or not. More...
EFI_STATUS | PeiHeciOverrideSoftStrapMsg (IN UINT16 NumberOfControllers, IN UINT8 OverrideMask)
Set Pcie Root port configuration SoftStrap override for the specified Pcie Root Port controller. More...
EFI_STATUS | PeiHeciGetRpmcStatus (OUT RP_STATUS_2 *RpStatus)
This message is sent by the BIOS to retrieve RPMC status data from CSME. More...

Detailed Description

Header file for PEI Me functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiMeLib.h.

Function Documentation

◆ HeciGetMkhiVersion()

EFI_STATUS HeciGetMkhiVersion ( OUT MKHI_VERSION * MkhiVersion )

Get MKHI (Management Engine Kernel Host Interface) Version.

Parameters
[out] MkhiVersion MKHI Version
Return values
EFI_UNSUPPORTED | Can't localize HECI protocol
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ InstallHeciPpi()

EFI_STATUS InstallHeciPpi ( VOID )

Install Heci PPIs needed in PEI phase.

Return values
EFI_SUCCESS | The function completed successfully.
EFI_DEVICE_ERROR | ME FPT is bad

◆ MeEndOfPostEnabled()

BOOLEAN MeEndOfPostEnabled ( VOID )

Check if End of Post Message is enabled in setup options.

Return values
FALSE | EndOfPost is disabled.
TRUE | EndOfPost is enabled.

◆ MeGetHeciBarAddress()

UINT32 MeGetHeciBarAddress ( IN ME_DEVICE MeDev )

Get default Heci1 BAR address from policy.

Parameters
[in] MeDev The ME device to be accessed.
Return values
32-bit BAR address

◆ MeHeci2Enabled()

BOOLEAN MeHeci2Enabled ( VOID )

Check if HECI2 should be removed from PCI space or not.

Return values
FALSE | HECI2 should be Disabled and removed from PCI space
TRUE | HECI2 should be enabled and not removed from PCI space

◆ MeHeciD0I3Enabled()

BOOLEAN MeHeciD0I3Enabled ( VOID )

Read the ME policy to see if D0I3 for HECI devices are enabled.

Return values
TRUE | D0I3 for HECI devices are enabled
FALSE | D0I3 for HECI devices are disabled

◆ MeHeciFullTrace()

BOOLEAN MeHeciFullTrace ( VOID )

Read the ME policy to see if Heci Full Trace are enabled.

Return values
TRUE | HECI full trace in the log is enabled
FALSE | HECI full trace in the log is disabled

◆ MeHeciMessageCheckEnabled()

BOOLEAN MeHeciMessageCheckEnabled ( VOID )

Read the ME policy to see if HECI message check is enabled for Bios Boot Path.

Return values
TRUE | HECI message check is enabled
FALSE | HECI message check is disabled

◆ MeHeciTimeoutsEnabled()

BOOLEAN MeHeciTimeoutsEnabled ( VOID )

Read the ME policy to see if HECI timeouts are enabled.

Return values
TRUE | Timeout is enabled
FALSE | Timeout is disabled

◆ MeIsAfterEndOfPost()

BOOLEAN MeIsAfterEndOfPost ( VOID )

Checks if EndOfPost event already happened.

Return values
TRUE | End of post already happened
FALSE | End of post did not happen yet

◆ MeIsEnforceEDebugModeEnabled()

BOOLEAN MeIsEnforceEDebugModeEnabled ( VOID )

Read the ME policy to see if Enforcing Enhanced Debug Mode is enabled.

Return values
TRUE | ME should enter Enhanced Debug Mode
FALSE | ME should not enter Enhanced Debug Mode

◆ MeMbpHobSkipped()

BOOLEAN MeMbpHobSkipped ( VOID )

Read the ME policy to see if MBP HOB is skipped.

Return values
TRUE | MBP HOB is skipped
FALSE | MBP HOB is not skipped

◆ PeiHeciBupManufacturingResetAndHalt()

EFI_STATUS PeiHeciBupManufacturingResetAndHalt ( VOID )

Send Manufacturing Reset and Halt.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciCommitFilesMsg()

EFI_STATUS PeiHeciCommitFilesMsg ( VOID )

This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit previously set files.

Caller shold invoke global reset afterwards.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciDataClear()

EFI_STATUS PeiHeciDataClear ( VOID )

This command is sent by the BIOS to switch clear CSME data to image creation state.

After the command success, platform reset is expected.

Return values
EFI_SUCCESS | Command succeeded.
EFI_UNSUPPORTED | Get ME mode fail.
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout or transition failed within allowed time limit

◆ PeiHeciDnxReqSet()

EFI_STATUS PeiHeciDnxReqSet ( OUT UINT32 * BiosAction )

Send DNX Request Set message.

Parameters
[out] BiosAction Requested Bios Action: 0 - Continue Post 1 - Reset Required
Return values
EFI_SUCCESS | Command succeeded
EFI_INVALID_PARAMETER | Invalid input parameter
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciFwCapsSetRuleData()

EFI_STATUS PeiHeciFwCapsSetRuleData | ( | IN UINT32 | RuleId,
 |  | IN UINT8 | RuleDataLength,
 |  | IN UINT32 | RuleData
 | ) |  |

Send Set Rule Data Request to CSME.

Parameters
[in] | RuleId | Identifies the rule which data needs to be changed.
[in] | RuleDataLength | Rule Data Length.
[in] | RuleData | Pointer to new rule data.
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetAmtBiosSyncInfo()

EFI_STATUS PeiHeciGetAmtBiosSyncInfo ( OUT AMT_BIOS_SYNC_INFO * RuleData )

This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state.

The firmware will respond to AMT BIOS SYNC INFO message even after the End of Post.

Parameters
[out] RuleData
See also
AMT_BIOS_SYNC_INFO
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetBiosSeed()

EFI_STATUS PeiHeciGetBiosSeed | ( | IN SEED_PROPERTIES * | BiosSeedProperties,
 |  | IN UINT8 | LockSeedGeneration,
 |  | OUT UINT32 * | EphemeralKeyCounter,
 |  | OUT SEED_INFO * | BiosSeedInfo,
 |  | OUT UINT8 * | BiosSeed
 | ) |  |

This message is sent by the BIOS to retrieve device specific seed from CSME.

Parameters
[in] | BiosSeedProperties | Seed properties
[in] | LockSeedGeneration | 0 - No lock 1 - Explicit lock requested by BIOS
[out] | EphemeralKeyCounter | Random counter to be used with ephemeral key for trusted channel
[out] | BiosSeedInfo | Seed information
[out] | BiosSeed | BIOS seed. If BIOS requested 32 bytes only, then the CSME will return the seed in first 32 bytes and fill rest of buffer by 0
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_NOT_FOUND | Couldn't locate HeciPpi or debug token data
EFI_INVALID_PARAMETER | Parameter invalid

◆ PeiHeciGetDebugTokenData()

EFI_STATUS PeiHeciGetDebugTokenData ( OUT DEBUG_TOKEN_KNOB_DATA * KnobData )

This message is sent by the BIOS to retrieve debug token data from CSME.

Parameters
[out] KnobData Debug Token Knob Data
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_NOT_FOUND | Couldn't locate HeciPpi or debug token data
EFI_INVALID_PARAMETER | Parameter invalid

◆ PeiHeciGetErLog()

EFI_STATUS PeiHeciGetErLog | ( | OUT UINT8 * | EventLogBuffer,
 |  | IN UINT32 | RemainingBufSize,
 |  | IN OUT UINT32 * | ReceivedLogSize,
 |  | IN OUT UINT8 * | LogEntryIndex,
 |  | OUT UINT8 * | RemainingEntries
 | ) |  |

This function sends a command to CSME to get Log information of Measurements provided in CSME Extend Registers for BIOS to extend to TPM-PCR registers.

Parameters
[out] | EventLogBuffer | Pointer to received Event log buffer
[in] | RemainingBufSize | Size of available buffer to collect event log
[in,out] | ReceivedLogSize | Size of received event log
[in,out] | LogEntryIndex | On input - Index of first / starting log entry in the buffer. On output - Index of last log entry returned
[out] | RemainingEntries | Pointer to Remaining Entries (0 - no more entries in a log; 1 - additional iteration(s) is(are) required)
Return values
EFI_SUCCESS | Log received successfully
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout or transition failed within allowed time limit

◆ PeiHeciGetFwCapsSkuMsg()

EFI_STATUS PeiHeciGetFwCapsSkuMsg ( OUT MEFWCAPS_SKU * RuleData )

Send Get Firmware SKU Request to ME.

Parameters
[out] RuleData ME Firmware Capability SKU
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetFwFeatureStateMsg()

EFI_STATUS PeiHeciGetFwFeatureStateMsg ( OUT MEFWCAPS_SKU * RuleData )

The Get FW Feature Status message is based on MKHI interface.

This command is used by BIOS/IntelR MEBX to get firmware runtime status. The GET FW RUNTIME STATUS message doesn't need to check the HFS.FWInitComplete value before sending the command. It means this message can be sent regardless of HFS.FWInitComplete.

Parameters
[out] RuleData ME Firmware Capability SKU
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetFwPayload()

EFI_STATUS PeiHeciGetFwPayload | ( | IN UINT32 | LoadRequest,
 |  | IN UINT32 | BufferAddressLow,
 |  | IN UINT32 | BufferAddressHigh,
 |  | IN OUT UINT32 * | BufferSize,
 |  | OUT UINT32 * | IpLoaderStatus,
 |  | OUT UINT8 * | HashType,
 |  | OUT UINT8 * | Hash
 | ) |  |

This message is sent by the BIOS to tell CSME that Buffer has been allocated for payload to be copied.

Parameters
[in] | LoadRequest | IP information for which firmware has to be loaded
[in] | BufferAddressLow | Lower DRAM address of the buffer
[in] | BufferAddressHigh | Upper DRAM address of the buffer
[in,out] | BufferSize | On input, BufferSize is size of Buffer allocated by Bios.On output, actual PayloadSize copied by ME
[out] | IpLoaderStatus | IP Loading status from CSME
[out] | HashType | Hash algorithm used for message digest
[out] | Hash | Hash Value
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_UNSUPPORTED | Current ME mode doesn't support sending this message through this HECI or Input parameters are not valid.
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_INVALID_PARAMETER | Parameter invalid

◆ PeiHeciGetImrSizeMsg()

EFI_STATUS PeiHeciGetImrSizeMsg | ( | IN UINT32 | BiosImrDisableMask0,
 |  | IN UINT32 | BiosImrDisableMask1,
 |  | IN UINT32 | PciImrSize,
 |  | OUT UINT8 * | MkhiResult,
 |  | OUT UINT32 * | ImrsSize,
 |  | OUT UINT32 * | Alignment
 | ) |  |

This message is sent by the BIOS to retrieve from CSME total size of IMRs.

BIOS needs to provide mask of disabled IMRs and requested size for PCIe IMR.

Parameters
[in] | BiosImrDisableMask0 | Low DWORD of BIOS IMR Disable mask
[in] | BiosImrDisableMask1 | High DWORD of BIOS IMR Disable mask
[in] | PciImrSize | Requested IMR size for PCI
[out] | MkhiResult | MKHI Error Code
[out] | ImrsSize | Total IMR size
[out] | Alignment | Required address alignment
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciGetMbpMsg()

EFI_STATUS PeiHeciGetMbpMsg | ( | OUT UINT32 * | MbpEntriesNumber,
 |  | IN OUT UINT32 * | MbpItems,
 |  | IN BOOLEAN | SkibMbp
 | ) |  |

Send Get MBP from FW.

Parameters
[out] | MbpEntriesNumber | Number of MBP entries
[in,out] | MbpItems | MBP items of the response @paran[in] SkipMbp Skip MBP
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetPlatformTypeMsg()

EFI_STATUS PeiHeciGetPlatformTypeMsg ( OUT PLATFORM_TYPE_RULE_DATA * RuleData )

This message is sent by the BIOS or IntelR MEBX.

One of usages is to utilize this command to determine if the platform runs in Consumer or Corporate SKU size firmware.

Parameters
[out] RuleData Including PlatformBrand, IntelMeFwImageType, SuperSku, and PlatformTargetUsageType
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetRpmcStatus()

EFI_STATUS PeiHeciGetRpmcStatus ( OUT RP_STATUS_2 * RpStatus )

This message is sent by the BIOS to retrieve RPMC status data from CSME.

Parameters
[out] RpStatus RPMC status data
Return values
EFI_SUCCESS | Command succeeded
EFI_NOT_FOUND | Couldn't locate HeciPpi
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI
EFI_INVALID_PARAMETER | Parameter invalid

◆ PeiHeciGetSoftStrpConfigMsg()

EFI_STATUS PeiHeciGetSoftStrpConfigMsg | ( | IN UINT16 | NumberOfControllers,
 |  | IN OUT UINT8 * | ControllerConfig
 | ) |  |

Retrieves information on whether Pcie root port configuration SoftStrap override is being done or not.

Parameters
[in] | NumberOfControllers | On input, it is the number of controllers caller expects.
[in,out] | ControllerConfig | Pointer to the controller config message.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI
EFI_OUT_OF_RESOURCES | Unable to allocate required resources

◆ PeiHeciGetUnconfigOnRtcClearDisableMsg()

EFI_STATUS PeiHeciGetUnconfigOnRtcClearDisableMsg ( OUT UINT32 * RuleData )

This message is sent by the BIOS in PEI phase to query ME Unconfig on RTC Clear Disable state.

Parameters
[out] RuleData 1 - Unconfig on RTC clear is disabled 0 - Unconfig on RTC clear is enabled
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciGetUnconfigureStatus()

EFI_STATUS PeiHeciGetUnconfigureStatus ( OUT UINT8 * UnconfigStatus )

Get ME Unconfiguration Status.

Parameters
[out] UnconfigStatus Unconfiguration Status: 0x01 - Unconfiguration in progress 0x02 - No unconfigure w/o password to be processed 0x03 - CSME finished processing unconfigure w/o password 0x80 - Error encountered by CSME during unconfigure w/o password
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciIccBclkMsg()

EFI_STATUS PeiHeciIccBclkMsg ( OUT UINT8 * WarmResetRequired )

Send ICC request through HECI to query if CSME FW requires the warm reset flow from a previous boot.

Parameters
[out] WarmResetRequired 1 - CSME requires a warm reset to complete BCLK ramp en flow
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciOverrideSoftStrapMsg()

EFI_STATUS PeiHeciOverrideSoftStrapMsg | ( | IN UINT16 | NumberOfControllers,
 |  | IN UINT8 | OverrideMask
 | ) |  |

Set Pcie Root port configuration SoftStrap override for the specified Pcie Root Port controller.

Parameters
[in] | NumberOfControllers | On input, it is the number of controllers caller expects.
[in] | OverrideMask | Mask with RpController where Hybrid Storage is present and softstraps need to be overridden
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_UNSUPPORTED | Current ME mode doesn't support send this message through this HECI
EFI_OUT_OF_RESOURCES | Unable to allocate required resources

◆ PeiHeciReadChipsetInitMsg()

EFI_STATUS PeiHeciReadChipsetInitMsg | ( | IN OUT UINT8 * | ChipsetInitTable,
 |  | IN OUT UINT32 * | ChipsetInitTableLen
 | ) |  |

Reads the ChipsetInit table from the CSME FW.

Parameters
[in,out] | ChipsetInitTable | Pointer to buffer for the required system ChipsetInit Table.
[in,out] | ChipsetInitTableLen | Pointer to the length of the table in bytes
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciReadFromMphy()

EFI_STATUS PeiHeciReadFromMphy | ( | OUT UINT8 * | Data,
 |  | IN UINT32 | DataSize
 | ) |  |

Get the Mphy data from CSME.

Parameters
[out] | Data | Pointer to the data buffer.
[in] | DataSize | Pointer to the length of the table in bytes
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_OUT_OF_RESOURCES | HECI Could not allocate Memory
EFI_NOT_FOUND | Couldn't locate HeciPpi.

◆ PeiHeciRequestDeviceOwnership()

EFI_STATUS PeiHeciRequestDeviceOwnership ( VOID )

Sends the NVM request device ownership message.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciSendCbmResetRequest()

EFI_STATUS PeiHeciSendCbmResetRequest | ( | IN UINT8 | ResetOrigin,
 |  | IN UINT8 | ResetType
 | ) |  |

Send Core BIOS Reset Request Message through HECI to reset the system.

Parameters
[in] | ResetOrigin | Reset source
[in] | ResetType | Global or Host reset
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_NOT_FOUND | No ME present
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciSendDid()

EFI_STATUS PeiHeciSendDid | ( | IN UINT32 | ImrBaseLow,
 |  | IN UINT32 | ImrBaseHigh,
 |  | IN UINT8 | MemStatus,
 |  | OUT UINT8 * | MkhiResult,
 |  | OUT UINT8 * | Flags,
 |  | OUT UINT8 * | BiosAction,
 |  | OUT UINT32 * | PciImrBaseLow,
 |  | OUT UINT32 * | PciImrBaseHigh
 | ) |  |

Send DRAM init done message through HECI to inform ME of memory initialization done.

Parameters
[in] | ImrBaseLow | Base address for IMR region (Low DWORD)
[in] | ImrBaseHigh | Base address for IMR region (High DWORD)
[in] | MemStatus | Memory init status
[out] | MkhiResult | MKHI Error Code
[out] | Flags | Flags
[out] | BiosAction | ME response to DID
[out] | PciImrBaseLow | Base address for PCI IMR (Low DWORD)
[out] | PciImrBaseHigh | Base address for PCI IMR (High DWORD)
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout

◆ PeiHeciSendHostResetNotificationMsg()

EFI_STATUS PeiHeciSendHostResetNotificationMsg ( VOID )

Send Host Reset Notification Message to determine if warm reset is required.

Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciSetEDebugModeState()

EFI_STATUS PeiHeciSetEDebugModeState ( IN BOOLEAN State )

Send Set eDebug Mode State.

Parameters
[in] State EDebug Mode state to be set: TRUE - Enable eDebug State FALSE - Disable eDebug State
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge
EFI_NOT_FOUND | Couldn't locate HeciPpi.

◆ PeiHeciSetFileExMsg()

EFI_STATUS PeiHeciSetFileExMsg | ( | IN UINT32 | FileId,
 |  | IN UINT32 | Offset,
 |  | IN UINT32 | DataSize,
 |  | IN UINT8 | Flags,
 |  | IN UINT8 * | DataBuffer
 | ) |  |

This message is sent by the BIOS to save data in a file stored in ME firmware NVM.

Parameters
[in] | FileId | Id Number of file to write
[in] | Offset | File offset
[in] | DataSize | Size of data to write
[in] | Flags | Flags
[in] | *DataBuffer | Pointer to the data buffer
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_OUT_OF_RESOURCES | Cannot allocate memory
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciSetUnconfigOnRtcClearDisableMsg()

EFI_STATUS PeiHeciSetUnconfigOnRtcClearDisableMsg ( IN UINT32 RuleData )

This message is sent by the BIOS in PEI phase to set ME Unconfig on RTC Clear Disable state.

Parameters
[in] RuleData 1 - Disable Unconfig on RTC clear 0 - Enable Unconfig on RTC clear
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function or EOP was sent
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciTerminateHeci()

EFI_STATUS PeiHeciTerminateHeci ( VOID )

Send command to terminate HECI communication in ME Debug Mode.

Return values
EFI_SUCCESS | Command succeeded
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_BUFFER_TOO_SMALL | Message Buffer is too small for the Acknowledge

◆ PeiHeciWriteChipsetInitMsg()

EFI_STATUS PeiHeciWriteChipsetInitMsg | ( | IN UINT8 * | ChipsetInitTable,
 |  | IN UINT32 | ChipsetInitTableLen
 | ) |  |

Send the required system ChipsetInit Table to CSME FW.

Parameters
[in] | ChipsetInitTable | The ChipsetInitSyncMsg HDR and the required system ChipsetInit Table.
[in] | ChipsetInitTableLen | Length of the table in bytes
Return values
EFI_UNSUPPORTED | Current ME mode doesn't support this function
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
EFI_TIMEOUT | HECI does not return the buffer before timeout
EFI_OUT_OF_RESOURCES | HECI Could not allocate Memory
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiMeLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PEI Me functionality
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2006 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_ME_LIB_H_
36 #define _PEI_ME_LIB_H_
37
38 #include <BupMsgs.h>
39 #include <MkhiMsgs.h>
40 #include <Register/MeRegs.h>
41 #include <MeBiosPayloadData.h>
42 #include <IccMsgs.h>
43
44 #define ME_STATE_STALL_1_SECOND 1000000
45 #define MSG_MAX_WAIT_TIMEOUT 5
46
47 //
48 // Prototype for HECI message PEI phase
49 //
50
51 //
52 // ME Client - MKHI
53 //
54
55 //
56 // MKHI_CBM_GROUP_ID = 0x00
57 //
58
59 /**
60 Send Core BIOS Reset Request Message through HECI to reset the system.
61
62 @param[in] ResetOrigin Reset source
63 @param[in] ResetType Global or Host reset
64
65 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
66 @retval EFI_SUCCESS Command succeeded
67 @retval EFI_NOT_FOUND No ME present
68 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
69 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
70 **/
71 EFI_STATUS
72 PeiHeciSendCbmResetRequest (
73 IN UINT8 ResetOrigin,
74 IN UINT8 ResetType
75 );
76
77 //
78 // MKHI_FWCAPS_GROUP_ID = 0x03
79 //
80
81 /**
82 Send Get Firmware SKU Request to ME
83
84 @param[out] RuleData ME Firmware Capability SKU
85
86 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
87 @retval EFI_SUCCESS Command succeeded
88 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
89 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
90 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
91 **/
92 EFI_STATUS
93 PeiHeciGetFwCapsSkuMsg (
94 OUT MEFWCAPS_SKU *RuleData
95 );
96
97 /**
98 This message is sent by the BIOS or IntelR MEBX. One of usages is to utilize
99 this command to determine if the platform runs in Consumer or Corporate SKU
100 size firmware.
101
102 @param[out] RuleData Including PlatformBrand, IntelMeFwImageType,
103 SuperSku, and PlatformTargetUsageType
104
105 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
106 @retval EFI_SUCCESS Command succeeded
107 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
108 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
109 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
110 **/
111 EFI_STATUS
112 PeiHeciGetPlatformTypeMsg (
113 OUT PLATFORM_TYPE_RULE_DATA *RuleData
114 );
115
116 /**
117 The Get FW Feature Status message is based on MKHI interface.
118 This command is used by BIOS/IntelR MEBX to get firmware runtime status.
119 The GET FW RUNTIME STATUS message doesn't need to check the HFS.FWInitComplete
120 value before sending the command.
121 It means this message can be sent regardless of HFS.FWInitComplete.
122
123 @param[out] RuleData ME Firmware Capability SKU
124
125 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
126 @retval EFI_SUCCESS Command succeeded
127 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
128 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
129 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
130 **/
131 EFI_STATUS
132 PeiHeciGetFwFeatureStateMsg (
133 OUT MEFWCAPS_SKU *RuleData
134 );
135
136 /**
137 This message is sent by the BIOS in PEI phase to query
138 ME Unconfig on RTC Clear Disable state.
139
140 @param[out] RuleData 1 - Unconfig on RTC clear is disabled
141 0 - Unconfig on RTC clear is enabled
142
143 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
144 @retval EFI_SUCCESS Command succeeded
145 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
146 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
147 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
148 **/
149 EFI_STATUS
150 PeiHeciGetUnconfigOnRtcClearDisableMsg (
151 OUT UINT32 *RuleData
152 );
153
154 /**
155 This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning state.
156 The firmware will respond to AMT BIOS SYNC INFO message even after the End of Post.
157
158 @param[out] RuleData @see AMT_BIOS_SYNC_INFO
159
160 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
161 @retval EFI_SUCCESS Command succeeded
162 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
163 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
164 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
165 **/
166 EFI_STATUS
167 PeiHeciGetAmtBiosSyncInfo (
168 OUT AMT_BIOS_SYNC_INFO *RuleData
169 );
170
171 /**
172 Send Set Rule Data Request to CSME
173
174 @param[in] RuleId Identifies the rule which data needs to be changed.
175 @param[in] RuleDataLength Rule Data Length.
176 @param[in] RuleData Pointer to new rule data.
177
178 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
179 @retval EFI_SUCCESS Command succeeded
180 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
181 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
182 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
183 **/
184 EFI_STATUS
185 PeiHeciFwCapsSetRuleData (
186 IN UINT32 RuleId,
187 IN UINT8 RuleDataLength,
188 IN UINT32 RuleData
189 );
190
191 /**
192 This message is sent by the BIOS in PEI phase to set
193 ME Unconfig on RTC Clear Disable state.
194
195 @param[in] RuleData 1 - Disable Unconfig on RTC clear
196 0 - Enable Unconfig on RTC clear
197
198 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function or EOP was sent
199 @retval EFI_SUCCESS Command succeeded
200 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
201 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
202 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
203 **/
204 EFI_STATUS
205 PeiHeciSetUnconfigOnRtcClearDisableMsg (
206 IN UINT32 RuleData
207 );
208
209 //
210 // MKHI_MCA_GROUP_ID = 0x0A
211 //
212
213 /**
214 Sends the NVM request device ownership message.
215
216 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
217 @retval EFI_SUCCESS Command succeeded
218 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
219 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
220 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
221 **/
222 EFI_STATUS
223 PeiHeciRequestDeviceOwnership (
224 VOID
225 );
226
227 //
228 // MKHI_DNX_GROUP_ID = 0x0D
229 //
230
231 /**
232 Send DNX Request Set message.
233
234 @param[out] BiosAction Requested Bios Action:
235 0 - Continue Post
236 1 - Reset Required
237
238 @retval EFI_SUCCESS Command succeeded
239 @retval EFI_INVALID_PARAMETER Invalid input parameter
240 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
241 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
242 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
243 **/
244 EFI_STATUS
245 PeiHeciDnxReqSet (
246 OUT UINT32 *BiosAction
247 );
248
249 //
250 // MKHI_GEN_GROUP_ID = 0xFF
251 //
252
253 /**
254 Get ME Unconfiguration Status.
255
256 @param[out] UnconfigStatus Unconfiguration Status:
257 0x01 - Unconfiguration in progress
258 0x02 - No unconfigure w/o password to be processed
259 0x03 - CSME finished processing unconfigure w/o password
260 0x80 - Error encountered by CSME during unconfigure w/o password
261
262 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
263 @retval EFI_SUCCESS Command succeeded
264 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
265 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
266 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
267 **/
268 EFI_STATUS
269 PeiHeciGetUnconfigureStatus (
270 OUT UINT8* UnconfigStatus
271 );
272
273 //
274 // BUP_COMMON_GROUP_ID = 0xF0
275 //
276
277 /**
278 Send DRAM init done message through HECI to inform ME of memory initialization done.
279
280 @param[in] ImrBaseLow Base address for IMR region (Low DWORD)
281 @param[in] ImrBaseHigh Base address for IMR region (High DWORD)
282 @param[in] MemStatus Memory init status
283 @param[out] MkhiResult MKHI Error Code
284 @param[out] Flags Flags
285 @param[out] BiosAction ME response to DID
286 @param[out] PciImrBaseLow Base address for PCI IMR (Low DWORD)
287 @param[out] PciImrBaseHigh Base address for PCI IMR (High DWORD)
288 @retval EFI_SUCCESS Command succeeded
289 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
290 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
291 **/
292 EFI_STATUS
293 PeiHeciSendDid (
294 IN UINT32 ImrBaseLow,
295 IN UINT32 ImrBaseHigh,
296 IN UINT8 MemStatus,
297 OUT UINT8 *MkhiResult,
298 OUT UINT8 *Flags,
299 OUT UINT8 *BiosAction,
300 OUT UINT32 *PciImrBaseLow,
301 OUT UINT32 *PciImrBaseHigh
302 );
303
304 /**
305 Send Get MBP from FW
306
307 @param[out] MbpEntriesNumber Number of MBP entries
308 @param[in, out] MbpItems MBP items of the response
309 @paran[in] SkipMbp Skip MBP
310
311 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
312 @retval EFI_SUCCESS Command succeeded
313 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
314 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
315 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
316 **/
317 EFI_STATUS
318 PeiHeciGetMbpMsg (
319 OUT UINT32 *MbpEntriesNumber,
320 IN OUT UINT32 *MbpItems,
321 IN BOOLEAN SkibMbp
322 );
323
324 /**
325 Send command to terminate HECI communication in ME Debug Mode.
326
327 @retval EFI_SUCCESS Command succeeded
328 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
329 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
330 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
331 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
332 **/
333 EFI_STATUS
334 PeiHeciTerminateHeci (
335 VOID
336 );
337
338 /**
339 This message is sent by the BIOS to retrieve from CSME total size of IMRs.
340 BIOS needs to provide mask of disabled IMRs and requested size for PCIe IMR.
341
342 @param[in] BiosImrDisableMask0 Low DWORD of BIOS IMR Disable mask
343 @param[in] BiosImrDisableMask1 High DWORD of BIOS IMR Disable mask
344 @param[in] PciImrSize Requested IMR size for PCI
345 @param[out] MkhiResult MKHI Error Code
346 @param[out] ImrsSize Total IMR size
347 @param[out] Alignment Required address alignment
348
349 @retval EFI_SUCCESS Command succeeded
350 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
351 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
352 **/
353 EFI_STATUS
354 PeiHeciGetImrSizeMsg (
355 IN UINT32 BiosImrDisableMask0,
356 IN UINT32 BiosImrDisableMask1,
357 IN UINT32 PciImrSize,
358 OUT UINT8 *MkhiResult,
359 OUT UINT32 *ImrsSize,
360 OUT UINT32 *Alignment
361 );
362
363 /**
364 Send Manufacturing Reset and Halt
365
366 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
367 @retval EFI_SUCCESS Command succeeded
368 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
369 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
370 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
371 **/
372 EFI_STATUS
373 PeiHeciBupManufacturingResetAndHalt (
374 VOID
375 );
376
377 /**
378 This function sends a command to CSME to get Log information of Measurements provided in
379 CSME Extend Registers for BIOS to extend to TPM-PCR registers.
380
381 @param[out] EventLogBuffer Pointer to received Event log buffer
382 @param[in] RemainingBufSize Size of available buffer to collect event log
383 @param[in, out] ReceivedLogSize Size of received event log
384 @param[in, out] LogEntryIndex On input - Index of first / starting log entry in the buffer. On output - Index of last log entry returned
385 @param[out] RemainingEntries Pointer to Remaining Entries (0 - no more entries in a log; 1 - additional iteration(s) is(are) required)
386
387 @retval EFI_SUCCESS Log received successfully
388 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
389 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
390 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
391 @retval EFI_TIMEOUT HECI does not return the buffer before timeout or transition failed within allowed time limit
392 **/
393 EFI_STATUS
394 PeiHeciGetErLog (
395 OUT UINT8 *EventLogBuffer,
396 IN UINT32 RemainingBufSize,
397 IN OUT UINT32 *ReceivedLogSize,
398 IN OUT UINT8 *LogEntryIndex,
399 OUT UINT8 *RemainingEntries
400 );
401
402 /**
403 Send Set eDebug Mode State.
404
405 @param[in] State EDebug Mode state to be set:
406 TRUE - Enable eDebug State
407 FALSE - Disable eDebug State
408
409 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
410 @retval EFI_SUCCESS Command succeeded
411 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
412 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
413 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
414 @retval EFI_NOT_FOUND Couldn't locate HeciPpi.
415 **/
416 EFI_STATUS
417 PeiHeciSetEDebugModeState (
418 IN BOOLEAN State
419 );
420
421 /**
422 This command is sent by the BIOS to switch clear CSME data to image creation state.
423 After the command success, platform reset is expected.
424
425 @retval EFI_SUCCESS Command succeeded.
426 @retval EFI_UNSUPPORTED Get ME mode fail.
427 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
428 @retval EFI_TIMEOUT HECI does not return the buffer before timeout or transition failed
429 within allowed time limit
430 **/
431 EFI_STATUS
432 PeiHeciDataClear (
433 VOID
434 );
435
436 /**
437 This message is sent by the BIOS to tell CSME that Buffer has been allocated for payload to be copied.
438
439 @param[in] LoadRequest IP information for which firmware has to be loaded
440 @param[in] BufferAddressLow Lower DRAM address of the buffer
441 @param[in] BufferAddressHigh Upper DRAM address of the buffer
442 @param[in, out] BufferSize On input, BufferSize is size of Buffer allocated by Bios.On output, actual PayloadSize copied by ME
443 @param[out] IpLoaderStatus IP Loading status from CSME
444 @param[out] HashType Hash algorithm used for message digest
445 @param[out] Hash Hash Value
446
447 @retval EFI_SUCCESS Command succeeded
448 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
449 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
450 @retval EFI_UNSUPPORTED Current ME mode doesn't support sending this message through this HECI or Input parameters are not valid.
451 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
452 @retval EFI_INVALID_PARAMETER Parameter invalid
453 **/
454 EFI_STATUS
455 PeiHeciGetFwPayload (
456 IN UINT32 LoadRequest,
457 IN UINT32 BufferAddressLow,
458 IN UINT32 BufferAddressHigh,
459 IN OUT UINT32 *BufferSize,
460 OUT UINT32 *IpLoaderStatus,
461 OUT UINT8 *HashType,
462 OUT UINT8 *Hash
463 );
464
465 /**
466 This message is sent by the BIOS to retrieve debug token data from CSME.
467
468 @param[out] KnobData Debug Token Knob Data
469
470 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
471 @retval EFI_SUCCESS Command succeeded
472 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
473 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
474 @retval EFI_NOT_FOUND Couldn't locate HeciPpi or debug token data
475 @retval EFI_INVALID_PARAMETER Parameter invalid
476 **/
477 EFI_STATUS
478 PeiHeciGetDebugTokenData (
479 OUT DEBUG_TOKEN_KNOB_DATA *KnobData
480 );
481
482 /**
483 This message is sent by the BIOS to retrieve device specific seed from CSME.
484
485 @param[in] BiosSeedProperties Seed properties
486 @param[in] LockSeedGeneration 0 - No lock
487 1 - Explicit lock requested by BIOS
488 @param[out] EphemeralKeyCounter Random counter to be used with ephemeral key for trusted channel
489 @param[out] BiosSeedInfo Seed information
490 @param[out] BiosSeed BIOS seed. If BIOS requested 32 bytes only, then the CSME will
491 return the seed in first 32 bytes and fill rest of buffer by 0
492
493 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
494 @retval EFI_SUCCESS Command succeeded
495 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
496 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
497 @retval EFI_NOT_FOUND Couldn't locate HeciPpi or debug token data
498 @retval EFI_INVALID_PARAMETER Parameter invalid
499 **/
500 EFI_STATUS
501 PeiHeciGetBiosSeed (
502 IN SEED_PROPERTIES *BiosSeedProperties,
503 IN UINT8 LockSeedGeneration,
504 OUT UINT32 *EphemeralKeyCounter,
505 OUT SEED_INFO *BiosSeedInfo,
506 OUT UINT8 *BiosSeed
507 );
508
509 //
510 // BUP_ICC_GROUP_ID = 0xF1
511 //
512
513 /**
514 Send ICC request through HECI to query if CSME FW requires the warm reset flow from a previous boot.
515
516 @param[out] WarmResetRequired 1 - CSME requires a warm reset to complete BCLK ramp en flow
517
518 @retval EFI_SUCCESS Command succeeded
519 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
520 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
521 **/
522 EFI_STATUS
523 PeiHeciIccBclkMsg (
524 OUT UINT8 *WarmResetRequired
525 );
526
527 //
528 // BUP_MPHY_GROUP_ID = 0xF2
529 //
530
531 /**
532 Get the Mphy data from CSME
533
534 @param[out] Data Pointer to the data buffer.
535 @param[in] DataSize Pointer to the length of the table in bytes
536
537 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
538 @retval EFI_SUCCESS Command succeeded
539 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
540 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
541 @retval EFI_OUT_OF_RESOURCES HECI Could not allocate Memory
542 @retval EFI_NOT_FOUND Couldn't locate HeciPpi.
543 **/
544 EFI_STATUS
545 PeiHeciReadFromMphy (
546 OUT UINT8 *Data,
547 IN UINT32 DataSize
548 );
549
550 //
551 // BUP_PM_GROUP_ID = 0xF3
552 //
553
554 /**
555 Send Host Reset Notification Message to determine if warm reset is required.
556
557 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
558 @retval EFI_SUCCESS Command succeeded
559 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
560 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
561 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
562 **/
563 EFI_STATUS
564 PeiHeciSendHostResetNotificationMsg (
565 VOID
566 );
567
568 //
569 // MKHI_GEN_GROUP_ID = 0xFF
570 //
571
572 /**
573 Get MKHI (Management Engine Kernel Host Interface) Version.
574
575 @param[out] MkhiVersion MKHI Version
576
577 @retval EFI_UNSUPPORTED Can't localize HECI protocol
578 @retval EFI_SUCCESS Command succeeded
579 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
580 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
581 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
582 **/
583 EFI_STATUS
584 HeciGetMkhiVersion (
585 OUT MKHI_VERSION *MkhiVersion
586 );
587
588 //
589 // Interface functions of HeciMsgLib
590 //
591
592 //
593 // ME Client - Integrated Clock Chip (ICC)
594 //
595
596 /**
597 Reads the ChipsetInit table from the CSME FW.
598
599 @param[in, out] ChipsetInitTable Pointer to buffer for the required system ChipsetInit Table.
600 @param[in, out] ChipsetInitTableLen Pointer to the length of the table in bytes
601
602 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
603 @retval EFI_SUCCESS Command succeeded
604 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
605 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
606 **/
607 EFI_STATUS
608 PeiHeciReadChipsetInitMsg (
609 IN OUT UINT8 *ChipsetInitTable,
610 IN OUT UINT32 *ChipsetInitTableLen
611 );
612
613 /**
614 Send the required system ChipsetInit Table to CSME FW.
615
616 @param[in] ChipsetInitTable The ChipsetInitSyncMsg HDR and the required system ChipsetInit Table.
617 @param[in] ChipsetInitTableLen Length of the table in bytes
618
619 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
620 @retval EFI_SUCCESS Command succeeded
621 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
622 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
623 @retval EFI_OUT_OF_RESOURCES HECI Could not allocate Memory
624 **/
625 EFI_STATUS
626 PeiHeciWriteChipsetInitMsg (
627 IN UINT8 *ChipsetInitTable,
628 IN UINT32 ChipsetInitTableLen
629 );
630
631 /**
632 This message is sent by the BIOS to save data in a file stored in ME firmware NVM.
633
634 @param[in] FileId Id Number of file to write
635 @param[in] Offset File offset
636 @param[in] DataSize Size of data to write
637 @param[in] Flags Flags
638 @param[in] *DataBuffer Pointer to the data buffer
639
640 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
641 @retval EFI_SUCCESS Command succeeded
642 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
643 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
644 @retval EFI_OUT_OF_RESOURCES Cannot allocate memory
645 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
646 **/
647 EFI_STATUS
648 PeiHeciSetFileExMsg (
649 IN UINT32 FileId,
650 IN UINT32 Offset,
651 IN UINT32 DataSize,
652 IN UINT8 Flags,
653 IN UINT8 *DataBuffer
654 );
655
656 /**
657 This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to
658 commit previously set files. Caller shold invoke global reset afterwards.
659
660 @retval EFI_UNSUPPORTED Current ME mode doesn't support this function
661 @retval EFI_SUCCESS Command succeeded
662 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
663 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
664 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
665 **/
666 EFI_STATUS
667 PeiHeciCommitFilesMsg (
668 VOID
669 );
670
671 //
672 // Prototype for ME Policy PEI phase
673 //
674
675 /**
676 Read the ME policy to see if HECI timeouts are enabled.
677
678 @retval TRUE Timeout is enabled
679 @retval FALSE Timeout is disabled
680 **/
681 BOOLEAN
682 MeHeciTimeoutsEnabled (
683 VOID
684 );
685
686 /**
687 Read the ME policy to see if Heci Full Trace are enabled.
688
689 @retval TRUE HECI full trace in the log is enabled
690 @retval FALSE HECI full trace in the log is disabled
691 **/
692 BOOLEAN
693 MeHeciFullTrace (
694 VOID
695 );
696
697 /**
698 Check if HECI2 should be removed from PCI space or not
699
700 @retval FALSE HECI2 should be Disabled and removed from PCI space
701 @retval TRUE HECI2 should be enabled and not removed from PCI space
702 **/
703 BOOLEAN
704 MeHeci2Enabled (
705 VOID
706 );
707
708 /**
709 Read the ME policy to see if HECI message check is enabled for Bios Boot Path.
710
711 @retval TRUE HECI message check is enabled
712 @retval FALSE HECI message check is disabled
713 **/
714 BOOLEAN
715 MeHeciMessageCheckEnabled (
716 VOID
717 );
718
719 /**
720 Read the ME policy to see if MBP HOB is skipped.
721
722 @retval TRUE MBP HOB is skipped
723 @retval FALSE MBP HOB is not skipped
724 **/
725 BOOLEAN
726 MeMbpHobSkipped (
727 VOID
728 );
729
730 /**
731 Get default Heci1 BAR address from policy.
732
733 @param[in] MeDev The ME device to be accessed.
734
735 @retval 32-bit BAR address
736 **/
737 UINT32
738 MeGetHeciBarAddress (
739 IN ME_DEVICE MeDev
740 );
741
742 /**
743 Read the ME policy to see if D0I3 for HECI devices are enabled.
744
745 @retval TRUE D0I3 for HECI devices are enabled
746 @retval FALSE D0I3 for HECI devices are disabled
747 **/
748 BOOLEAN
749 MeHeciD0I3Enabled (
750 VOID
751 );
752
753 /**
754 Read the ME policy to see if Enforcing Enhanced Debug Mode is enabled.
755
756 @retval TRUE ME should enter Enhanced Debug Mode
757 @retval FALSE ME should not enter Enhanced Debug Mode
758 **/
759 BOOLEAN
760 MeIsEnforceEDebugModeEnabled (
761 VOID
762 );
763
764 /**
765 Check if End of Post Message is enabled in setup options.
766
767 @retval FALSE EndOfPost is disabled.
768 @retval TRUE EndOfPost is enabled.
769 **/
770 BOOLEAN
771 MeEndOfPostEnabled (
772 VOID
773 );
774
775 /**
776 Checks if EndOfPost event already happened
777
778 @retval TRUE End of post already happened
779 @retval FALSE End of post did not happen yet
780 **/
781 BOOLEAN
782 MeIsAfterEndOfPost (
783 VOID
784 );
785
786 /**
787 Set EndOfPost done
788 **/
789 VOID
790 MeSetEndOfPostDone (
791 VOID
792 );
793
794 /**
795 Install ME call back function for reset2 ppi.
796
797 **/
798 VOID
799 RegisterMeReset (
800 VOID
801 );
802
803 /**
804 Install Heci PPIs needed in PEI phase
805
806 @retval EFI_SUCCESS The function completed successfully.
807 @retval EFI_DEVICE_ERROR ME FPT is bad
808 **/
809 EFI_STATUS
810 InstallHeciPpi (
811 VOID
812 );
813
814
815 /**
816 Retrieves information on whether Pcie root port configuration SoftStrap override is being done or not
817
818 @param[in] NumberOfControllers On input, it is the number of controllers caller expects.
819 @param[in, out] ControllerConfig Pointer to the controller config message.
820
821 @retval EFI_SUCCESS Command succeeded
822 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
823 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
824 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
825 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
826 @retval EFI_OUT_OF_RESOURCES Unable to allocate required resources
827 **/
828 EFI_STATUS
829 PeiHeciGetSoftStrpConfigMsg (
830 IN UINT16 NumberOfControllers,
831 IN OUT UINT8 *ControllerConfig
832 );
833
834 /**
835 Set Pcie Root port configuration SoftStrap override for the specified Pcie Root Port controller
836
837 @param[in] NumberOfControllers On input, it is the number of controllers caller expects.
838 @param[in] OverrideMask Mask with RpController where Hybrid Storage is present and softstraps need to be overridden
839
840 @retval EFI_SUCCESS Command succeeded
841 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
842 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
843 @retval EFI_BUFFER_TOO_SMALL Message Buffer is too small for the Acknowledge
844 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
845 @retval EFI_OUT_OF_RESOURCES Unable to allocate required resources
846 **/
847 EFI_STATUS
848 PeiHeciOverrideSoftStrapMsg (
849 IN UINT16 NumberOfControllers,
850 IN UINT8 OverrideMask
851 );
852
853 /**
854 This message is sent by the BIOS to retrieve RPMC status data from CSME.
855
856 @param[out] RpStatus RPMC status data
857
858 @retval EFI_SUCCESS Command succeeded
859 @retval EFI_NOT_FOUND Couldn't locate HeciPpi
860 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
861 @retval EFI_TIMEOUT HECI does not return the buffer before timeout
862 @retval EFI_UNSUPPORTED Current ME mode doesn't support send this message through this HECI
863 @retval EFI_INVALID_PARAMETER Parameter invalid
864 **/
865 EFI_STATUS
866 EFIAPI
867 PeiHeciGetRpmcStatus (
868 OUT RP_STATUS_2 *RpStatus
869 );
870 #endif
PeiHeciSetEDebugModeState
EFI_STATUS PeiHeciSetEDebugModeState(IN BOOLEAN State)
Send Set eDebug Mode State.
MeHeciMessageCheckEnabled
BOOLEAN MeHeciMessageCheckEnabled(VOID)
Read the ME policy to see if HECI message check is enabled for Bios Boot Path.
PeiHeciTerminateHeci
EFI_STATUS PeiHeciTerminateHeci(VOID)
Send command to terminate HECI communication in ME Debug Mode.
MeHeci2Enabled
BOOLEAN MeHeci2Enabled(VOID)
Check if HECI2 should be removed from PCI space or not.
MeHeciTimeoutsEnabled
BOOLEAN MeHeciTimeoutsEnabled(VOID)
Read the ME policy to see if HECI timeouts are enabled.
IccMsgs.h
ICC Messages.
MeEndOfPostEnabled
BOOLEAN MeEndOfPostEnabled(VOID)
Check if End of Post Message is enabled in setup options.
InstallHeciPpi
EFI_STATUS InstallHeciPpi(VOID)
Install Heci PPIs needed in PEI phase.
PeiHeciReadChipsetInitMsg
EFI_STATUS PeiHeciReadChipsetInitMsg(IN OUT UINT8 *ChipsetInitTable, IN OUT UINT32 *ChipsetInitTableLen)
Reads the ChipsetInit table from the CSME FW.
MeMbpHobSkipped
BOOLEAN MeMbpHobSkipped(VOID)
Read the ME policy to see if MBP HOB is skipped.
PeiHeciSendDid
EFI_STATUS PeiHeciSendDid(IN UINT32 ImrBaseLow, IN UINT32 ImrBaseHigh, IN UINT8 MemStatus, OUT UINT8 *MkhiResult, OUT UINT8 *Flags, OUT UINT8 *BiosAction, OUT UINT32 *PciImrBaseLow, OUT UINT32 *PciImrBaseHigh)
Send DRAM init done message through HECI to inform ME of memory initialization done.
PeiHeciGetFwPayload
EFI_STATUS PeiHeciGetFwPayload(IN UINT32 LoadRequest, IN UINT32 BufferAddressLow, IN UINT32 BufferAddressHigh, IN OUT UINT32 *BufferSize, OUT UINT32 *IpLoaderStatus, OUT UINT8 *HashType, OUT UINT8 *Hash)
This message is sent by the BIOS to tell CSME that Buffer has been allocated for payload to be copied...
HeciGetMkhiVersion
EFI_STATUS HeciGetMkhiVersion(OUT MKHI_VERSION *MkhiVersion)
Get MKHI (Management Engine Kernel Host Interface) Version.
PeiHeciSetUnconfigOnRtcClearDisableMsg
EFI_STATUS PeiHeciSetUnconfigOnRtcClearDisableMsg(IN UINT32 RuleData)
This message is sent by the BIOS in PEI phase to set ME Unconfig on RTC Clear Disable state.
PeiHeciCommitFilesMsg
EFI_STATUS PeiHeciCommitFilesMsg(VOID)
This message is sent by the BIOS after HeciSetFileExMsg to notify ME firmware that it needs to commit...
PeiHeciDataClear
EFI_STATUS PeiHeciDataClear(VOID)
This command is sent by the BIOS to switch clear CSME data to image creation state.
PeiHeciReadFromMphy
EFI_STATUS PeiHeciReadFromMphy(OUT UINT8 *Data, IN UINT32 DataSize)
Get the Mphy data from CSME.
PeiHeciIccBclkMsg
EFI_STATUS PeiHeciIccBclkMsg(OUT UINT8 *WarmResetRequired)
Send ICC request through HECI to query if CSME FW requires the warm reset flow from a previous boot.
MeSetEndOfPostDone
VOID MeSetEndOfPostDone(VOID)
Set EndOfPost done.
MeHeciFullTrace
BOOLEAN MeHeciFullTrace(VOID)
Read the ME policy to see if Heci Full Trace are enabled.
MeIsAfterEndOfPost
BOOLEAN MeIsAfterEndOfPost(VOID)
Checks if EndOfPost event already happened.
PeiHeciGetImrSizeMsg
EFI_STATUS PeiHeciGetImrSizeMsg(IN UINT32 BiosImrDisableMask0, IN UINT32 BiosImrDisableMask1, IN UINT32 PciImrSize, OUT UINT8 *MkhiResult, OUT UINT32 *ImrsSize, OUT UINT32 *Alignment)
This message is sent by the BIOS to retrieve from CSME total size of IMRs.
PeiHeciSendHostResetNotificationMsg
EFI_STATUS PeiHeciSendHostResetNotificationMsg(VOID)
Send Host Reset Notification Message to determine if warm reset is required.
PeiHeciGetRpmcStatus
EFI_STATUS PeiHeciGetRpmcStatus(OUT RP_STATUS_2 *RpStatus)
This message is sent by the BIOS to retrieve RPMC status data from CSME.
MkhiMsgs.h
MKHI Messages.
PeiHeciGetErLog
EFI_STATUS PeiHeciGetErLog(OUT UINT8 *EventLogBuffer, IN UINT32 RemainingBufSize, IN OUT UINT32 *ReceivedLogSize, IN OUT UINT8 *LogEntryIndex, OUT UINT8 *RemainingEntries)
This function sends a command to CSME to get Log information of Measurements provided in CSME Extend ...
MeRegs.h
Register definition for ME Devices.
PeiHeciGetDebugTokenData
EFI_STATUS PeiHeciGetDebugTokenData(OUT DEBUG_TOKEN_KNOB_DATA *KnobData)
This message is sent by the BIOS to retrieve debug token data from CSME.
MeHeciD0I3Enabled
BOOLEAN MeHeciD0I3Enabled(VOID)
Read the ME policy to see if D0I3 for HECI devices are enabled.
PeiHeciGetFwCapsSkuMsg
EFI_STATUS PeiHeciGetFwCapsSkuMsg(OUT MEFWCAPS_SKU *RuleData)
Send Get Firmware SKU Request to ME.
PeiHeciGetUnconfigOnRtcClearDisableMsg
EFI_STATUS PeiHeciGetUnconfigOnRtcClearDisableMsg(OUT UINT32 *RuleData)
This message is sent by the BIOS in PEI phase to query ME Unconfig on RTC Clear Disable state.
PeiHeciGetUnconfigureStatus
EFI_STATUS PeiHeciGetUnconfigureStatus(OUT UINT8 *UnconfigStatus)
Get ME Unconfiguration Status.
PeiHeciGetAmtBiosSyncInfo
EFI_STATUS PeiHeciGetAmtBiosSyncInfo(OUT AMT_BIOS_SYNC_INFO *RuleData)
This message is sent by the BIOS on the boot where the host wants to get the firmware provisioning st...
PeiHeciFwCapsSetRuleData
EFI_STATUS PeiHeciFwCapsSetRuleData(IN UINT32 RuleId, IN UINT8 RuleDataLength, IN UINT32 RuleData)
Send Set Rule Data Request to CSME.
PeiHeciOverrideSoftStrapMsg
EFI_STATUS PeiHeciOverrideSoftStrapMsg(IN UINT16 NumberOfControllers, IN UINT8 OverrideMask)
Set Pcie Root port configuration SoftStrap override for the specified Pcie Root Port controller.
ME_DEVICE
ME_DEVICE
CSME PCI devices should be numbered according to their PCI function number HECI1 = 0,...
Definition: MeChipsetLib.h:45
PeiHeciDnxReqSet
EFI_STATUS PeiHeciDnxReqSet(OUT UINT32 *BiosAction)
Send DNX Request Set message.
PeiHeciRequestDeviceOwnership
EFI_STATUS PeiHeciRequestDeviceOwnership(VOID)
Sends the NVM request device ownership message.
MeBiosPayloadData.h
Interface definition details for MBP.
PeiHeciGetFwFeatureStateMsg
EFI_STATUS PeiHeciGetFwFeatureStateMsg(OUT MEFWCAPS_SKU *RuleData)
The Get FW Feature Status message is based on MKHI interface.
PeiHeciGetSoftStrpConfigMsg
EFI_STATUS PeiHeciGetSoftStrpConfigMsg(IN UINT16 NumberOfControllers, IN OUT UINT8 *ControllerConfig)
Retrieves information on whether Pcie root port configuration SoftStrap override is being done or not...
PeiHeciWriteChipsetInitMsg
EFI_STATUS PeiHeciWriteChipsetInitMsg(IN UINT8 *ChipsetInitTable, IN UINT32 ChipsetInitTableLen)
Send the required system ChipsetInit Table to CSME FW.
PeiHeciGetMbpMsg
EFI_STATUS PeiHeciGetMbpMsg(OUT UINT32 *MbpEntriesNumber, IN OUT UINT32 *MbpItems, IN BOOLEAN SkibMbp)
Send Get MBP from FW.
PeiHeciSetFileExMsg
EFI_STATUS PeiHeciSetFileExMsg(IN UINT32 FileId, IN UINT32 Offset, IN UINT32 DataSize, IN UINT8 Flags, IN UINT8 *DataBuffer)
This message is sent by the BIOS to save data in a file stored in ME firmware NVM.
PeiHeciSendCbmResetRequest
EFI_STATUS PeiHeciSendCbmResetRequest(IN UINT8 ResetOrigin, IN UINT8 ResetType)
Send Core BIOS Reset Request Message through HECI to reset the system.
MEFWCAPS_SKU
Get Firmware Capability.
Definition: MkhiMsgs.h:404
MeGetHeciBarAddress
UINT32 MeGetHeciBarAddress(IN ME_DEVICE MeDev)
Get default Heci1 BAR address from policy.
BupMsgs.h
BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW.
PeiHeciGetPlatformTypeMsg
EFI_STATUS PeiHeciGetPlatformTypeMsg(OUT PLATFORM_TYPE_RULE_DATA *RuleData)
This message is sent by the BIOS or IntelR MEBX.
PeiHeciGetBiosSeed
EFI_STATUS PeiHeciGetBiosSeed(IN SEED_PROPERTIES *BiosSeedProperties, IN UINT8 LockSeedGeneration, OUT UINT32 *EphemeralKeyCounter, OUT SEED_INFO *BiosSeedInfo, OUT UINT8 *BiosSeed)
This message is sent by the BIOS to retrieve device specific seed from CSME.
MeIsEnforceEDebugModeEnabled
BOOLEAN MeIsEnforceEDebugModeEnabled(VOID)
Read the ME policy to see if Enforcing Enhanced Debug Mode is enabled.
RegisterMeReset
VOID RegisterMeReset(VOID)
Install ME call back function for reset2 ppi.
PeiHeciBupManufacturingResetAndHalt
EFI_STATUS PeiHeciBupManufacturingResetAndHalt(VOID)
Send Manufacturing Reset and Halt.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMemPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiMemPolicyLib.h File Reference

Header file for the PeiMemPolicyLib library. More...

#include <CpuRegs.h>
#include <Ppi/SiPolicy.h>
#include <SaDataHob.h>
#include <Library/DebugLib.h>
#include <Library/BaseLib.h>
#include <Library/IoLib.h>
#include <Library/SmbusLib.h>
#include <Library/PcdLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/PciSegmentLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/CpuPlatformLib.h>
#include <Library/ConfigBlockLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/SiConfigBlockLib.h>
Include dependency graph for PeiMemPolicyLib.h:

Go to the source code of this file.

Functions

VOID | LoadMemConfigNoCrcDefault (IN VOID *ConfigBlockPointer)
Load Config block default. More...
VOID | LoadMemConfigDefault (IN VOID *ConfigBlockPointer)
Load Config block default. More...
VOID | MrcLoadSamplePolicyPreMem (IN VOID *ConfigBlockTableAddress)
Load some policy default for reference board. More...
UINT16 | MrcGetConfigBlockTotalSizePreMem (VOID)
Get Mrc config block table total size. More...
EFI_STATUS | MrcAddConfigBlocksPreMem (IN VOID *ConfigBlockTableAddress)
MrcAddConfigBlocksPreMem add all Mrc PEI PreMem config block. More...
VOID | MrcPrintPolicyPpiPreMem (IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem Mrc policy. More...

Detailed Description

Header file for the PeiMemPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiMemPolicyLib.h.

Function Documentation

◆ LoadMemConfigDefault()

VOID LoadMemConfigDefault ( IN VOID * ConfigBlockPointer )

Load Config block default.

Parameters
[in] ConfigBlockPointer Pointer to config block

◆ LoadMemConfigNoCrcDefault()

VOID LoadMemConfigNoCrcDefault ( IN VOID * ConfigBlockPointer )

Load Config block default.

Parameters
[in] ConfigBlockPointer Pointer to config block

◆ MrcAddConfigBlocksPreMem()

EFI_STATUS MrcAddConfigBlocksPreMem ( IN VOID * ConfigBlockTableAddress )

MrcAddConfigBlocksPreMem add all Mrc PEI PreMem config block.

Parameters
[in] ConfigBlockTableAddress The pointer to add Mrc config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MrcGetConfigBlockTotalSizePreMem()

UINT16 MrcGetConfigBlockTotalSizePreMem ( VOID )

Get Mrc config block table total size.

Return values
Size of Mrc config block table

◆ MrcLoadSamplePolicyPreMem()

VOID MrcLoadSamplePolicyPreMem ( IN VOID * ConfigBlockTableAddress )

Load some policy default for reference board.

Parameters
[in] ConfigBlockTableAddress The pointer for Mrc config blocks

◆ MrcPrintPolicyPpiPreMem()

VOID MrcPrintPolicyPpiPreMem ( IN SI_PREMEM_POLICY_PPI * SiPolicyPreMemPpi )

This function prints the PEI phase PreMem Mrc policy.

Parameters
[in] SiPolicyPreMemPpi The MRC PreMem Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMemPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiMemPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for the PeiMemPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_MEM_POLICY_LIB_H_
36 #define _PEI_MEM_POLICY_LIB_H_
37
38 #include <CpuRegs.h>
39 #include <Ppi/SiPolicy.h>
40 #include <SaDataHob.h>
41 #include <Library/DebugLib.h>
42 #include <Library/BaseLib.h>
43 #include <Library/IoLib.h>
44 #include <Library/SmbusLib.h>
45 #include <Library/PcdLib.h>
46 #include <Library/PeiServicesLib.h>
47 #include <Library/BaseMemoryLib.h>
48 #include <Library/PciSegmentLib.h>
49 #include <Library/MemoryAllocationLib.h>
50 #include <Library/CpuPlatformLib.h>
51 #include <Library/ConfigBlockLib.h>
52 #include <Ppi/SiPolicy.h>
53 #include <Library/PeiSaPolicyLib.h>
54 #include <Library/SiConfigBlockLib.h>
55
56 /**
57 Load Config block default
58
59 @param[in] ConfigBlockPointer Pointer to config block
60 **/
61 VOID
62 LoadMemConfigNoCrcDefault (
63 IN VOID *ConfigBlockPointer
64 );
65
66 /**
67 Load Config block default
68
69 @param[in] ConfigBlockPointer Pointer to config block
70 **/
71 VOID
72 LoadMemConfigDefault (
73 IN VOID *ConfigBlockPointer
74 );
75
76 /**
77 Load some policy default for reference board.
78
79 @param[in] ConfigBlockTableAddress The pointer for Mrc config blocks
80
81 **/
82 VOID
83 MrcLoadSamplePolicyPreMem (
84 IN VOID *ConfigBlockTableAddress
85 );
86
87 /**
88 Get Mrc config block table total size.
89
90 @retval Size of Mrc config block table
91 **/
92 UINT16
93 EFIAPI
94 MrcGetConfigBlockTotalSizePreMem (
95 VOID
96 );
97
98 /**
99 MrcAddConfigBlocksPreMem add all Mrc PEI PreMem config block.
100
101 @param[in] ConfigBlockTableAddress The pointer to add Mrc config blocks
102
103 @retval EFI_SUCCESS The policy default is initialized.
104 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
105 **/
106 EFI_STATUS
107 EFIAPI
108 MrcAddConfigBlocksPreMem(
109 IN VOID *ConfigBlockTableAddress
110 );
111
112 /**
113 This function prints the PEI phase PreMem Mrc policy.
114
115 @param[in] SiPolicyPreMemPpi The MRC PreMem Policy PPI instance
116 **/
117 VOID
118 EFIAPI
119 MrcPrintPolicyPpiPreMem(
120 IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
121 );
122 #endif // _PEI_MEM_POLICY_LIB_H_
123
MrcPrintPolicyPpiPreMem
VOID MrcPrintPolicyPpiPreMem(IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem Mrc policy.
LoadMemConfigNoCrcDefault
VOID LoadMemConfigNoCrcDefault(IN VOID *ConfigBlockPointer)
Load Config block default.
MrcGetConfigBlockTotalSizePreMem
UINT16 MrcGetConfigBlockTotalSizePreMem(VOID)
Get Mrc config block table total size.
CpuPlatformLib.h
Header file for CpuPlatform Lib.
LoadMemConfigDefault
VOID LoadMemConfigDefault(IN VOID *ConfigBlockPointer)
Load Config block default.
MrcLoadSamplePolicyPreMem
VOID MrcLoadSamplePolicyPreMem(IN VOID *ConfigBlockTableAddress)
Load some policy default for reference board.
MrcAddConfigBlocksPreMem
EFI_STATUS MrcAddConfigBlocksPreMem(IN VOID *ConfigBlockTableAddress)
MrcAddConfigBlocksPreMem add all Mrc PEI PreMem config block.
CpuRegs.h
Register names for CPU registers.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
SaDataHob.h
The GUID definition for SaDataHob.
SiConfigBlockLib.h
Prototype of the SiConfigBlockLib library.
PeiSaPolicyLib.h
Prototype of the PeiSaPolicy library.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMePolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiMePolicyLib.h File Reference

Prototype of the MePolicyLibPei library. More...

#include <Ppi/SiPolicy.h>
#include <Library/ConfigBlockLib.h>
Include dependency graph for PeiMePolicyLib.h:

Go to the source code of this file.

Functions

VOID | MePrintPolicyPpiPreMem (IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem policy. More...
VOID | MePrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase policy. More...
UINT16 | MeGetConfigBlockTotalSize (VOID)
Get Me config block table total size. More...
UINT16 | MeGetConfigBlockTotalSizePreMem (VOID)
Get ME config block table total size. More...
EFI_STATUS | MeAddConfigBlocksPreMem (IN VOID *ConfigBlockTableAddress)
MeAddConfigBlocksPreMem add all ME config blocks. More...
EFI_STATUS | MeAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
MeAddConfigBlocks add all ME config blocks. More...

Detailed Description

Prototype of the MePolicyLibPei library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiMePolicyLib.h.

Function Documentation

◆ MeAddConfigBlocks()

EFI_STATUS MeAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

MeAddConfigBlocks add all ME config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add ME config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MeAddConfigBlocksPreMem()

EFI_STATUS MeAddConfigBlocksPreMem ( IN VOID * ConfigBlockTableAddress )

MeAddConfigBlocksPreMem add all ME config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add ME config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MeGetConfigBlockTotalSize()

UINT16 MeGetConfigBlockTotalSize ( VOID )

Get Me config block table total size.

Return values
Size of Me config block table

◆ MeGetConfigBlockTotalSizePreMem()

UINT16 MeGetConfigBlockTotalSizePreMem ( VOID )

Get ME config block table total size.

Return values
Size of ME config block table

◆ MePrintPolicyPpi()

VOID MePrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

This function prints the PEI phase policy.

Parameters
[in] SiPolicyPpi The RC Policy PPI instance

◆ MePrintPolicyPpiPreMem()

VOID MePrintPolicyPpiPreMem ( IN SI_PREMEM_POLICY_PPI * SiPolicyPreMemPpi )

This function prints the PEI phase PreMem policy.

Parameters
[in] SiPolicyPreMemPpi The RC PreMem Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMePolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiMePolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the MePolicyLibPei library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_ME_POLICY_LIB_H_
36 #define _PEI_ME_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39 #include <Library/ConfigBlockLib.h>
40
41 /**
42 This function prints the PEI phase PreMem policy.
43
44 @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI instance
45 **/
46 VOID
47 EFIAPI
48 MePrintPolicyPpiPreMem (
49 IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
50 );
51
52 /**
53 This function prints the PEI phase policy.
54
55 @param[in] SiPolicyPpi The RC Policy PPI instance
56 **/
57 VOID
58 EFIAPI
59 MePrintPolicyPpi (
60 IN SI_POLICY_PPI *SiPolicyPpi
61 );
62
63 /**
64 Get Me config block table total size.
65
66 @retval Size of Me config block table
67 **/
68 UINT16
69 EFIAPI
70 MeGetConfigBlockTotalSize (
71 VOID
72 );
73
74 /**
75 Get ME config block table total size.
76
77 @retval Size of ME config block table
78 **/
79 UINT16
80 EFIAPI
81 MeGetConfigBlockTotalSizePreMem (
82 VOID
83 );
84
85 /**
86 MeAddConfigBlocksPreMem add all ME config blocks.
87
88 @param[in] ConfigBlockTableAddress The pointer to add ME config blocks
89
90 @retval EFI_SUCCESS The policy default is initialized.
91 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
92 **/
93 EFI_STATUS
94 EFIAPI
95 MeAddConfigBlocksPreMem (
96 IN VOID *ConfigBlockTableAddress
97 );
98
99 /**
100 MeAddConfigBlocks add all ME config blocks.
101
102 @param[in] ConfigBlockTableAddress The pointer to add ME config blocks
103
104 @retval EFI_SUCCESS The policy default is initialized.
105 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
106 **/
107 EFI_STATUS
108 EFIAPI
109 MeAddConfigBlocks (
110 IN VOID *ConfigBlockTableAddress
111 );
112
113 #endif // _PEI_ME_POLICY_LIB_H_
MeAddConfigBlocksPreMem
EFI_STATUS MeAddConfigBlocksPreMem(IN VOID *ConfigBlockTableAddress)
MeAddConfigBlocksPreMem add all ME config blocks.
MeGetConfigBlockTotalSize
UINT16 MeGetConfigBlockTotalSize(VOID)
Get Me config block table total size.
MePrintPolicyPpiPreMem
VOID MePrintPolicyPpiPreMem(IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem policy.
MePrintPolicyPpi
VOID MePrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase policy.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
MeAddConfigBlocks
EFI_STATUS MeAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
MeAddConfigBlocks add all ME config blocks.
MeGetConfigBlockTotalSizePreMem
UINT16 MeGetConfigBlockTotalSizePreMem(VOID)
Get ME config block table total size.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMeServerPreMemPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiMeServerPreMemPolicyLib.h File Reference

Prototype of the MeServerPolicyLibPei library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for PeiMeServerPreMemPolicyLib.h:

Go to the source code of this file.

Functions

VOID | MeServerPreMemPrintPolicyPpi (IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
Print PEI ME Server Config Block (pre mem) More...
VOID | MeServedrPrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
Print PEI ME Server Config Block (post mem) More...
UINT16 | MeServerPreMemGetConfigBlockTotalSize (VOID)
Get ME Server config block table total size. More...
EFI_STATUS | MeServerPreMemAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
MeServerPreMemAddConfigBlocks add all ME Server config blocks. More...

Detailed Description

Prototype of the MeServerPolicyLibPei library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiMeServerPreMemPolicyLib.h.

Function Documentation

◆ MeServedrPrintPolicyPpi()

VOID MeServedrPrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

Print PEI ME Server Config Block (post mem)

Parameters
[in] SiPolicyPreMemPpi The RC Policy PPI instance

◆ MeServerPreMemAddConfigBlocks()

EFI_STATUS MeServerPreMemAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

MeServerPreMemAddConfigBlocks add all ME Server config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add ME Server config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ MeServerPreMemGetConfigBlockTotalSize()

UINT16 MeServerPreMemGetConfigBlockTotalSize ( VOID )

Get ME Server config block table total size.

Return values
Size of ME Server config block table

◆ MeServerPreMemPrintPolicyPpi()

VOID MeServerPreMemPrintPolicyPpi ( IN SI_PREMEM_POLICY_PPI * SiPolicyPreMemPpi )

Print PEI ME Server Config Block (pre mem)

Parameters
[in] SiPolicyPreMemPpi The RC Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiMeServerPreMemPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiMeServerPreMemPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the MeServerPolicyLibPei library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_ME_SERVER_PRE_MEM_POLICY_LIB_H_
36 #define _PEI_ME_SERVER_PRE_MEM_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39
40 /**
41 Print PEI ME Server Config Block (pre mem)
42
43 @param[in] SiPolicyPreMemPpi The RC Policy PPI instance
44 **/
45 VOID
46 EFIAPI
47 MeServerPreMemPrintPolicyPpi (
48 IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
49 );
50
51 /**
52 Print PEI ME Server Config Block (post mem)
53
54 @param[in] SiPolicyPreMemPpi The RC Policy PPI instance
55 **/
56 VOID
57 EFIAPI
58 MeServedrPrintPolicyPpi (
59 IN SI_POLICY_PPI *SiPolicyPpi
60 );
61
62 /**
63 Get ME Server config block table total size.
64
65 @retval Size of ME Server config block table
66 **/
67 UINT16
68 EFIAPI
69 MeServerPreMemGetConfigBlockTotalSize (
70 VOID
71 );
72
73 /**
74 MeServerPreMemAddConfigBlocks add all ME Server config blocks.
75
76 @param[in] ConfigBlockTableAddress The pointer to add ME Server config blocks
77
78 @retval EFI_SUCCESS The policy default is initialized.
79 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
80 **/
81 EFI_STATUS
82 EFIAPI
83 MeServerPreMemAddConfigBlocks (
84 IN VOID *ConfigBlockTableAddress
85 );
86
87 #endif // _PEI_ME_SERVER_PRE_MEM_POLICY_LIB_H_
MeServerPreMemPrintPolicyPpi
VOID MeServerPreMemPrintPolicyPpi(IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
Print PEI ME Server Config Block (pre mem)
MeServerPreMemAddConfigBlocks
EFI_STATUS MeServerPreMemAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
MeServerPreMemAddConfigBlocks add all ME Server config blocks.
MeServedrPrintPolicyPpi
VOID MeServedrPrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
Print PEI ME Server Config Block (post mem)
MeServerPreMemGetConfigBlockTotalSize
UINT16 MeServerPreMemGetConfigBlockTotalSize(VOID)
Get ME Server config block table total size.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPcieRpLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiPcieRpLib.h File Reference

Header file for PEI PCIe functionality. More...

Go to the source code of this file.

Functions

UINT8 | GetPcieImrPortNumber (VOID)
Read the PCIe PreMem policy to check port number for PCIe IMR. More...
BOOLEAN | IsPcieImrEnabled (VOID)
Read the PCIe Premem policy to see if PCIe IMR is enabled. More...
UINT8 | GetPcieImrPortLocation (VOID)
Read the PCIE policy to check port Location for PCIe IMR. More...
UINT16 | GetPcieImrSize (VOID)
Read the PCIe policy to get PCIe IMR Size. More...
VOID | BuildPciImrHob (UINT32 BaseLow, UINT32 BaseHigh)
This function puts PCIe IMR related information into HOB. More...

Detailed Description

Header file for PEI PCIe functionality.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiPcieRpLib.h.

Function Documentation

◆ BuildPciImrHob()

VOID BuildPciImrHob | ( | UINT32 | BaseLow,
 |  | UINT32 | BaseHigh
 | ) |  |

This function puts PCIe IMR related information into HOB.

Parameters
[in] | BaseLow | lower 32 bits of PCIe IMR address
[in] | BaseHigh | higher 32 bits of PCIe IMR address

◆ GetPcieImrPortLocation()

UINT8 GetPcieImrPortLocation ( VOID )

Read the PCIE policy to check port Location for PCIe IMR.

Return values
RootPort Location

◆ GetPcieImrPortNumber()

UINT8 GetPcieImrPortNumber ( VOID )

Read the PCIe PreMem policy to check port number for PCIe IMR.

Return values
port number

◆ GetPcieImrSize()

UINT16 GetPcieImrSize ( VOID )

Read the PCIe policy to get PCIe IMR Size.

Return values
PcieImrSize Size of PCIe Imr in MB

◆ IsPcieImrEnabled()

BOOLEAN IsPcieImrEnabled ( VOID )

Read the PCIe Premem policy to see if PCIe IMR is enabled.

Return values
TRUE | PCIe IMR is enabled
FALSE | PCIe IMR is disabled
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPcieRpLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiPcieRpLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PEI PCIe functionality
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_PCIE_LIB_H_
36 #define _PEI_PCIE_LIB_H_
37
38 extern EFI_GUID gPciImrHobGuid;
39
40 typedef struct {
41 EFI_HOB_GUID_TYPE Header;
42 UINT64 PciImrBase;
43 } PCI_IMR_HOB;
44
45 /**
46 Read the PCIe PreMem policy to check port number for PCIe IMR
47
48 @retval port number
49 **/
50 UINT8
51 GetPcieImrPortNumber (
52 VOID
53 );
54
55 /**
56 Read the PCIe Premem policy to see if PCIe IMR is enabled.
57
58 @retval TRUE PCIe IMR is enabled
59 @retval FALSE PCIe IMR is disabled
60 **/
61 BOOLEAN
62 IsPcieImrEnabled (
63 VOID
64 );
65
66 /**
67 Read the PCIE policy to check port Location for PCIe IMR
68
69 @retval RootPort Location
70 **/
71 UINT8
72 GetPcieImrPortLocation (
73 VOID
74 );
75
76 /**
77 Read the PCIe policy to get PCIe IMR Size.
78
79 @retval PcieImrSize Size of PCIe Imr in MB
80 **/
81 UINT16
82 GetPcieImrSize (
83 VOID
84 );
85
86 /**
87 This function puts PCIe IMR related information into HOB
88
89 @param[in] BaseLow lower 32 bits of PCIe IMR address
90 @param[in] BaseHigh higher 32 bits of PCIe IMR address
91 **/
92 VOID
93 BuildPciImrHob (
94 UINT32 BaseLow,
95 UINT32 BaseHigh
96 );
97
98 #endif
GetPcieImrSize
UINT16 GetPcieImrSize(VOID)
Read the PCIe policy to get PCIe IMR Size.
GetPcieImrPortLocation
UINT8 GetPcieImrPortLocation(VOID)
Read the PCIE policy to check port Location for PCIe IMR.
GetPcieImrPortNumber
UINT8 GetPcieImrPortNumber(VOID)
Read the PCIe PreMem policy to check port number for PCIe IMR.
IsPcieImrEnabled
BOOLEAN IsPcieImrEnabled(VOID)
Read the PCIe Premem policy to see if PCIe IMR is enabled.
BuildPciImrHob
VOID BuildPciImrHob(UINT32 BaseLow, UINT32 BaseHigh)
This function puts PCIe IMR related information into HOB.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPreMemSiDefaultPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiPreMemSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_PREMEM_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiPreMemSiDefaultPolicy.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPreMemSiDefaultPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiPreMemSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_PREMEM_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
57 };
58
59 extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiPreMemSiDefaultPolicy.h:55
_PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI::PeiPreMemPolicyInit
PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit
PeiPreMemPolicyInit()
Definition: PeiPreMemSiDefaultPolicy.h:56
PEI_PREMEM_POLICY_INIT
EFI_STATUS(* PEI_PREMEM_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiPreMemSiDefaultPolicy.h:48
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPreMemSiPolicyPrint.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiPreMemSiPolicyPrint.h File Reference

This file defines the PPI to print PEI Silicon PreMem Policy settings. More...

Go to the source code of this file.

Detailed Description

This file defines the PPI to print PEI Silicon PreMem Policy settings.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file PeiPreMemSiPolicyPrint.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiPreMemSiPolicyPrint.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiPreMemSiPolicyPrint.h
Go to the documentation of this file.
1 /** @file
2 This file defines the PPI to print PEI Silicon PreMem Policy settings.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32 **/
33
34 #ifndef PEI_PREMEM_SI_POLICY_PRINT_PPI_H_
35 #define PEI_PREMEM_SI_POLICY_PRINT_PPI_H_
36
37 //
38 // This PPI provides a function to print Si PreMem policy settings
39 //
40 typedef
41 EFI_STATUS
42 (EFIAPI *PEI_PREMEM_POLICY_PRINT) (
43 VOID
44 );
45
46 typedef struct _PEI_PREMEM_SI_POLICY_PRINT_PPI {
47 PEI_PREMEM_POLICY_PRINT PeiPreMemPolicyPrint;
48 } PEI_PREMEM_SI_POLICY_PRINT_PPI;
49
50 extern EFI_GUID gSiPreMemPolicyPrintPpiGuid;
51
52 #endif // PEI_PREMEM_SI_POLICY_PRINT_PPI_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSaPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
Functions
PeiSaPolicyLib.h File Reference

Prototype of the PeiSaPolicy library. More...

#include <Ppi/SiPolicy.h>
#include <Library/ConfigBlockLib.h>
Include dependency graph for PeiSaPolicyLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

VOID | SaPrintPolicyPpiPreMem (IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem policy. More...
VOID | SaPrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase policy. More...
UINT16 | SaGetConfigBlockTotalSize (VOID)
Get SA config block table total size. More...
UINT16 | SaGetConfigBlockTotalSizePreMem (VOID)
Get SA config block table total size. More...
EFI_STATUS | SaAddConfigBlocksPreMem (IN VOID *ConfigBlockTableAddress)
SaAddConfigBlocksPreMem add all SA config blocks. More...
EFI_STATUS | SaAddConfigBlocks (IN VOID *ConfigBlockTableAddress)
SaAddConfigBlocks add all SA config blocks. More...

Detailed Description

Prototype of the PeiSaPolicy library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiSaPolicyLib.h.

Function Documentation

◆ SaAddConfigBlocks()

EFI_STATUS SaAddConfigBlocks ( IN VOID * ConfigBlockTableAddress )

SaAddConfigBlocks add all SA config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add SA config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SaAddConfigBlocksPreMem()

EFI_STATUS SaAddConfigBlocksPreMem ( IN VOID * ConfigBlockTableAddress )

SaAddConfigBlocksPreMem add all SA config blocks.

Parameters
[in] ConfigBlockTableAddress The pointer to add SA config blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SaGetConfigBlockTotalSize()

UINT16 SaGetConfigBlockTotalSize ( VOID )

Get SA config block table total size.

Return values
Size of SA config block table

◆ SaGetConfigBlockTotalSizePreMem()

UINT16 SaGetConfigBlockTotalSizePreMem ( VOID )

Get SA config block table total size.

Return values
Size of SA config block table

◆ SaPrintPolicyPpi()

VOID SaPrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

This function prints the PEI phase policy.

Parameters
[in] SiPolicyPpi The RC Policy PPI instance

◆ SaPrintPolicyPpiPreMem()

VOID SaPrintPolicyPpiPreMem ( IN SI_PREMEM_POLICY_PPI * SiPolicyPreMemPpi )

This function prints the PEI phase PreMem policy.

Parameters
[in] SiPolicyPreMemPpi The RC PreMem Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSaPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
PeiSaPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the PeiSaPolicy library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_SA_POLICY_LIB_H_
36 #define _PEI_SA_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39 #include <Library/ConfigBlockLib.h>
40
41 /**
42 This function prints the PEI phase PreMem policy.
43
44 @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI instance
45 **/
46 VOID
47 EFIAPI
48 SaPrintPolicyPpiPreMem (
49 IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi
50 );
51
52 /**
53 This function prints the PEI phase policy.
54
55 @param[in] SiPolicyPpi The RC Policy PPI instance
56 **/
57 VOID
58 EFIAPI
59 SaPrintPolicyPpi (
60 IN SI_POLICY_PPI *SiPolicyPpi
61 );
62
63 /**
64 Get SA config block table total size.
65
66 @retval Size of SA config block table
67 **/
68 UINT16
69 EFIAPI
70 SaGetConfigBlockTotalSize (
71 VOID
72 );
73
74 /**
75 Get SA config block table total size.
76
77 @retval Size of SA config block table
78 **/
79 UINT16
80 EFIAPI
81 SaGetConfigBlockTotalSizePreMem (
82 VOID
83 );
84
85 /**
86 SaAddConfigBlocksPreMem add all SA config blocks.
87
88 @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
89
90 @retval EFI_SUCCESS The policy default is initialized.
91 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
92 **/
93 EFI_STATUS
94 EFIAPI
95 SaAddConfigBlocksPreMem (
96 IN VOID *ConfigBlockTableAddress
97 );
98
99 /**
100 SaAddConfigBlocks add all SA config blocks.
101
102 @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
103
104 @retval EFI_SUCCESS The policy default is initialized.
105 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
106 **/
107 EFI_STATUS
108 EFIAPI
109 SaAddConfigBlocks (
110 IN VOID *ConfigBlockTableAddress
111 );
112
113 #endif // _PEI_SA_POLICY_LIBRARY_H_
SaPrintPolicyPpi
VOID SaPrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
This function prints the PEI phase policy.
SaAddConfigBlocksPreMem
EFI_STATUS SaAddConfigBlocksPreMem(IN VOID *ConfigBlockTableAddress)
SaAddConfigBlocksPreMem add all SA config blocks.
SaGetConfigBlockTotalSizePreMem
UINT16 SaGetConfigBlockTotalSizePreMem(VOID)
Get SA config block table total size.
SaPrintPolicyPpiPreMem
VOID SaPrintPolicyPpiPreMem(IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi)
This function prints the PEI phase PreMem policy.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
SaAddConfigBlocks
EFI_STATUS SaAddConfigBlocks(IN VOID *ConfigBlockTableAddress)
SaAddConfigBlocks add all SA config blocks.
SaGetConfigBlockTotalSize
UINT16 SaGetConfigBlockTotalSize(VOID)
Get SA config block table total size.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiDefaultPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
PeiSiDefaultPolicy.h File Reference

This file defines the function to initialize default silicon policy PPI. More...

Go to the source code of this file.

Classes

struct _PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy. More...

Typedefs

typedef EFI_STATUS(* PEI_POLICY_INIT) (VOID)
Initialize and install default silicon policy PPI.

Detailed Description

This file defines the function to initialize default silicon policy PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiDefaultPolicy.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiDefaultPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiSiDefaultPolicy.h
Go to the documentation of this file.
1 /** @file
2 This file defines the function to initialize default silicon policy PPI.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
36 #define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
37
38 //
39 // Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
40 //
41 typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
42
43 /**
44 Initialize and install default silicon policy PPI
45 **/
46 typedef
47 EFI_STATUS
48 (EFIAPI *PEI_POLICY_INIT) (
49 VOID
50 );
51
52 ///
53 /// This PPI provides function to install default silicon policy
54 ///
55 struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
56 PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
57 };
58
59 extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
60
61 #endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
_PEI_SI_DEFAULT_POLICY_INIT_PPI
This PPI provides function to install default silicon policy.
Definition: PeiSiDefaultPolicy.h:55
_PEI_SI_DEFAULT_POLICY_INIT_PPI::PeiPolicyInit
PEI_POLICY_INIT PeiPolicyInit
PeiPolicyInit()
Definition: PeiSiDefaultPolicy.h:56
PEI_POLICY_INIT
EFI_STATUS(* PEI_POLICY_INIT)(VOID)
Initialize and install default silicon policy PPI.
Definition: PeiSiDefaultPolicy.h:48
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiPolicyPrint.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiSiPolicyPrint.h File Reference

This file defines the PPI to print PEI Silicon Policy settings. More...

Go to the source code of this file.

Detailed Description

This file defines the PPI to print PEI Silicon Policy settings.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Definition in file PeiSiPolicyPrint.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiPolicyPrint.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PeiSiPolicyPrint.h
Go to the documentation of this file.
1 /** @file
2 This file defines the PPI to print PEI Silicon Policy settings.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32 **/
33
34 #ifndef PEI_SI_POLICY_PRINT_PPI_H_
35 #define PEI_SI_POLICY_PRINT_PPI_H_
36
37 //
38 // This PPI provides a function to print Si PreMem policy settings
39 //
40 typedef
41 EFI_STATUS
42 (EFIAPI *PEI_POLICY_PRINT) (
43 VOID
44 );
45
46 typedef struct _PEI_SI_POLICY_PRINT_PPI {
47 PEI_POLICY_PRINT PeiPolicyPrint;
48 } PEI_SI_POLICY_PRINT_PPI;
49
50 extern EFI_GUID gSiPolicyPrintPpiGuid;
51
52 #endif // PEI_SI_POLICY_PRINT_PPI_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiPolicyUpdateLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiSiPolicyUpdateLib.h File Reference

Header file for PEI SiPolicyUpdate Library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for PeiSiPolicyUpdateLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | PolicyDefaultCheckInit ()
This function performs Initinalize global variable for PolicyDefaultCheck using. More...
BOOLEAN | IsPolicyDefaultCheckRequired ()
This function performs Check First Boot and Rvp Support to see if Policy Default Check Required. More...
EFI_STATUS | UpdatePeiSiPolicyPreMem (VOID)
This function performs Silicon PEI Policy initialization. More...
EFI_STATUS | UpdatePeiSiPolicy (VOID)
This function performs Silicon PEI Policy initialization. More...
EFI_STATUS | UpdatePeiCpuPolicy (VOID)
This function performs CPU PEI Policy initialization in Post-memory. More...
EFI_STATUS | UpdatePeiCpuPolicyPreMem (VOID)
This function performs CPU PEI Policy initialization in PreMem. More...
EFI_STATUS | UpdatePeiSaPolicy (VOID)
This function performs SA PEI Policy initialization. More...
EFI_STATUS | UpdatePeiSaPolicyPreMem (VOID)
This function performs SA PEI Policy initialization for PreMem. More...
EFI_STATUS | UpdatePeiPchPolicy (VOID)
This function performs PCH PEI Policy initialization. More...
EFI_STATUS | UpdatePeiPchPolicyPreMem (VOID)
This function performs PCH PEI Policy initialization. More...
EFI_STATUS | UpdatePeiMePolicy (VOID)
Update the ME Policy Library. More...
EFI_STATUS | UpdatePeiMePolicyPreMem (VOID)
Update the ME Policy Library. More...
EFI_STATUS | UpdatePeiAmtPolicy (VOID)
Install the Active Management Policy Ppi Library. More...
EFI_STATUS | UpdatePeiTbtPolicy (VOID)
Update the TBT Policy Library. More...
EFI_STATUS | UpdatePeiMeServerPreMemPolicy (IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy)
Update the ME Server Policy Ppi (pre mem) More...
EFI_STATUS | UpdatePeiMeServerPolicy (IN OUT SI_POLICY_PPI *SiPolicyPpi)
Update the ME Server Policy Ppi (post mem) More...

Detailed Description

Header file for PEI SiPolicyUpdate Library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiSiPolicyUpdateLib.h.

Function Documentation

◆ IsPolicyDefaultCheckRequired()

BOOLEAN IsPolicyDefaultCheckRequired ( )

This function performs Check First Boot and Rvp Support to see if Policy Default Check Required.

Return values
BOOLEAN Required TURE or FALSE

◆ PolicyDefaultCheckInit()

EFI_STATUS PolicyDefaultCheckInit ( )

This function performs Initinalize global variable for PolicyDefaultCheck using.

Return values
EFI_SUCCESS The function completed successfully

◆ UpdatePeiAmtPolicy()

EFI_STATUS UpdatePeiAmtPolicy ( VOID )

Install the Active Management Policy Ppi Library.

Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.

◆ UpdatePeiCpuPolicy()

EFI_STATUS UpdatePeiCpuPolicy ( VOID )

This function performs CPU PEI Policy initialization in Post-memory.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver

◆ UpdatePeiCpuPolicyPreMem()

EFI_STATUS UpdatePeiCpuPolicyPreMem ( VOID )

This function performs CPU PEI Policy initialization in PreMem.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver

◆ UpdatePeiMePolicy()

EFI_STATUS UpdatePeiMePolicy ( VOID )

Update the ME Policy Library.

Return values
EFI_SUCCESS | Update complete.
Others | Update unsuccessful.

◆ UpdatePeiMePolicyPreMem()

EFI_STATUS UpdatePeiMePolicyPreMem ( VOID )

Update the ME Policy Library.

Return values
EFI_SUCCESS Update complete.

◆ UpdatePeiMeServerPolicy()

EFI_STATUS UpdatePeiMeServerPolicy ( IN OUT SI_POLICY_PPI * SiPolicyPpi )

Update the ME Server Policy Ppi (post mem)

Parameters
[in,out] SiPolicyPpi PEI Si Policy
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
EFI_INVALID_PARAMETER | Wrong pointer passed to the function

◆ UpdatePeiMeServerPreMemPolicy()

EFI_STATUS UpdatePeiMeServerPreMemPolicy ( IN OUT SI_PREMEM_POLICY_PPI * SiPreMemPolicy )

Update the ME Server Policy Ppi (pre mem)

Parameters
[in,out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
Return values
EFI_SUCCESS | Initialization complete.
EFI_UNSUPPORTED | The chipset is unsupported by this driver.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver.
EFI_DEVICE_ERROR | Device error, driver exits abnormally.
EFI_INVALID_PARAMETER | Wrong pointer passed to the function

◆ UpdatePeiPchPolicy()

EFI_STATUS UpdatePeiPchPolicy ( VOID )

This function performs PCH PEI Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver

◆ UpdatePeiPchPolicyPreMem()

EFI_STATUS UpdatePeiPchPolicyPreMem ( VOID )

This function performs PCH PEI Policy initialization.

Return values
EFI_SUCCESS | The PPI is installed and initialized.
EFI | ERRORS The PPI is not successfully installed.
EFI_OUT_OF_RESOURCES | Do not have enough resources to initialize the driver

◆ UpdatePeiSaPolicy()

EFI_STATUS UpdatePeiSaPolicy ( VOID )

This function performs SA PEI Policy initialization.

Return values
EFI_SUCCESS The PPI is installed and initialized.

◆ UpdatePeiSaPolicyPreMem()

EFI_STATUS UpdatePeiSaPolicyPreMem ( VOID )

This function performs SA PEI Policy initialization for PreMem.

Return values
EFI_SUCCESS Update complete.

◆ UpdatePeiSiPolicy()

EFI_STATUS UpdatePeiSiPolicy ( VOID )

This function performs Silicon PEI Policy initialization.

Return values
EFI_SUCCESS The function completed successfully

◆ UpdatePeiSiPolicyPreMem()

EFI_STATUS UpdatePeiSiPolicyPreMem ( VOID )

This function performs Silicon PEI Policy initialization.

Return values
EFI_SUCCESS The function completed successfully

◆ UpdatePeiTbtPolicy()

EFI_STATUS UpdatePeiTbtPolicy ( VOID )

Update the TBT Policy Library.

Return values
EFI_SUCCESS Update complete.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiSiPolicyUpdateLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiSiPolicyUpdateLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PEI SiPolicyUpdate Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
37 #define _PEI_SI_POLICY_UPDATE_LIB_H_
38
39 #include <Ppi/SiPolicy.h>
40
41 /**
42 This function performs Initinalize global variable for PolicyDefaultCheck using
43
44 @retval EFI_SUCCESS The function completed successfully
45 **/
46 EFI_STATUS
47 EFIAPI
48 PolicyDefaultCheckInit (
49 );
50
51 /**
52 This function performs Check First Boot and Rvp Support to see if Policy Default Check Required
53
54 @retval BOOLEAN Required TURE or FALSE
55 **/
56 BOOLEAN
57 EFIAPI
58 IsPolicyDefaultCheckRequired (
59 );
60
61 /**
62 This function performs Silicon PEI Policy initialization.
63
64 @retval EFI_SUCCESS The function completed successfully
65 **/
66 EFI_STATUS
67 EFIAPI
68 UpdatePeiSiPolicyPreMem (
69 VOID
70 );
71
72 /**
73 This function performs Silicon PEI Policy initialization.
74
75 @retval EFI_SUCCESS The function completed successfully
76 **/
77 EFI_STATUS
78 EFIAPI
79 UpdatePeiSiPolicy (
80 VOID
81 );
82
83 /**
84 This function performs CPU PEI Policy initialization in Post-memory.
85
86 @retval EFI_SUCCESS The PPI is installed and initialized.
87 @retval EFI ERRORS The PPI is not successfully installed.
88 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
89 **/
90 EFI_STATUS
91 EFIAPI
92 UpdatePeiCpuPolicy (
93 VOID
94 );
95
96 /**
97 This function performs CPU PEI Policy initialization in PreMem.
98
99 @retval EFI_SUCCESS The PPI is installed and initialized.
100 @retval EFI ERRORS The PPI is not successfully installed.
101 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
102 **/
103 EFI_STATUS
104 EFIAPI
105 UpdatePeiCpuPolicyPreMem (
106 VOID
107 );
108
109
110 /**
111 This function performs SA PEI Policy initialization.
112
113 @retval EFI_SUCCESS The PPI is installed and initialized.
114 **/
115 EFI_STATUS
116 EFIAPI
117 UpdatePeiSaPolicy (
118 VOID
119 );
120
121 /**
122 This function performs SA PEI Policy initialization for PreMem.
123
124 @retval EFI_SUCCESS Update complete.
125 **/
126 EFI_STATUS
127 EFIAPI
128 UpdatePeiSaPolicyPreMem (
129 VOID
130 );
131
132 /**
133 This function performs PCH PEI Policy initialization.
134
135 @retval EFI_SUCCESS The PPI is installed and initialized.
136 @retval EFI ERRORS The PPI is not successfully installed.
137 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
138 **/
139 EFI_STATUS
140 EFIAPI
141 UpdatePeiPchPolicy (
142 VOID
143 );
144
145 /**
146 This function performs PCH PEI Policy initialization.
147
148 @retval EFI_SUCCESS The PPI is installed and initialized.
149 @retval EFI ERRORS The PPI is not successfully installed.
150 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
151 **/
152 EFI_STATUS
153 EFIAPI
154 UpdatePeiPchPolicyPreMem (
155 VOID
156 );
157
158 /**
159 Update the ME Policy Library
160
161 @retval EFI_SUCCESS Update complete.
162 @retval Others Update unsuccessful.
163 **/
164 EFI_STATUS
165 EFIAPI
166 UpdatePeiMePolicy (
167 VOID
168 );
169
170 /**
171 Update the ME Policy Library
172
173 @retval EFI_SUCCESS Update complete.
174 **/
175 EFI_STATUS
176 EFIAPI
177 UpdatePeiMePolicyPreMem (
178 VOID
179 );
180
181 /**
182 Install the Active Management Policy Ppi Library
183
184 @retval EFI_SUCCESS Initialization complete.
185 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
186 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
187 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
188 **/
189 EFI_STATUS
190 EFIAPI
191 UpdatePeiAmtPolicy (
192 VOID
193 );
194
195 /**
196 Update the TBT Policy Library
197
198 @retval EFI_SUCCESS Update complete.
199 **/
200 EFI_STATUS
201 EFIAPI
202 UpdatePeiTbtPolicy (
203 VOID
204 );
205
206 /**
207 Update the ME Server Policy Ppi (pre mem)
208
209 @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
210
211 @retval EFI_SUCCESS Initialization complete.
212 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
213 @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
214 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
215 @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
216 **/
217 EFI_STATUS
218 UpdatePeiMeServerPreMemPolicy (
219 IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
220 );
221
222 /**
223 Update the ME Server Policy Ppi (post mem)
224
225 @param[in, out] SiPolicyPpi PEI Si Policy
226
227 @retval EFI_SUCCESS Initialization complete.
228 @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
229 @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
230 @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
231 **/
232 EFI_STATUS
233 UpdatePeiMeServerPolicy (
234 IN OUT SI_POLICY_PPI *SiPolicyPpi
235 );
236 #endif
UpdatePeiPchPolicyPreMem
EFI_STATUS UpdatePeiPchPolicyPreMem(VOID)
This function performs PCH PEI Policy initialization.
IsPolicyDefaultCheckRequired
BOOLEAN IsPolicyDefaultCheckRequired()
This function performs Check First Boot and Rvp Support to see if Policy Default Check Required.
UpdatePeiMeServerPolicy
EFI_STATUS UpdatePeiMeServerPolicy(IN OUT SI_POLICY_PPI *SiPolicyPpi)
Update the ME Server Policy Ppi (post mem)
UpdatePeiSaPolicy
EFI_STATUS UpdatePeiSaPolicy(VOID)
This function performs SA PEI Policy initialization.
UpdatePeiCpuPolicyPreMem
EFI_STATUS UpdatePeiCpuPolicyPreMem(VOID)
This function performs CPU PEI Policy initialization in PreMem.
UpdatePeiSiPolicyPreMem
EFI_STATUS UpdatePeiSiPolicyPreMem(VOID)
This function performs Silicon PEI Policy initialization.
UpdatePeiPchPolicy
EFI_STATUS UpdatePeiPchPolicy(VOID)
This function performs PCH PEI Policy initialization.
UpdatePeiSaPolicyPreMem
EFI_STATUS UpdatePeiSaPolicyPreMem(VOID)
This function performs SA PEI Policy initialization for PreMem.
UpdatePeiMeServerPreMemPolicy
EFI_STATUS UpdatePeiMeServerPreMemPolicy(IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy)
Update the ME Server Policy Ppi (pre mem)
UpdatePeiMePolicy
EFI_STATUS UpdatePeiMePolicy(VOID)
Update the ME Policy Library.
UpdatePeiAmtPolicy
EFI_STATUS UpdatePeiAmtPolicy(VOID)
Install the Active Management Policy Ppi Library.
UpdatePeiMePolicyPreMem
EFI_STATUS UpdatePeiMePolicyPreMem(VOID)
Update the ME Policy Library.
PolicyDefaultCheckInit
EFI_STATUS PolicyDefaultCheckInit()
This function performs Initinalize global variable for PolicyDefaultCheck using.
UpdatePeiCpuPolicy
EFI_STATUS UpdatePeiCpuPolicy(VOID)
This function performs CPU PEI Policy initialization in Post-memory.
UpdatePeiTbtPolicy
EFI_STATUS UpdatePeiTbtPolicy(VOID)
Update the TBT Policy Library.
UpdatePeiSiPolicy
EFI_STATUS UpdatePeiSiPolicy(VOID)
This function performs Silicon PEI Policy initialization.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiTbtTaskDispatchLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Enumerations | Functions
PeiTbtTaskDispatchLib.h File Reference

PEI TBT Task Dispatch library Header file. More...

#include <Library/PeiServicesLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/GpioLib.h>
#include <Library/IoLib.h>
#include <Library/PciSegmentLib.h>
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
Include dependency graph for PeiTbtTaskDispatchLib.h:

Go to the source code of this file.

Enumerations

enum TBT_BOOT_MODE

Functions

TBT_BOOT_MODE | TbtGetBootMode (VOID)
Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE. More...
VOID | TbtTaskDistpach (IN TBT_CALL_TABLE_ENTRY *TbtCallTable, IN VOID *PeiTbtConfig)
TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY. More...

Detailed Description

PEI TBT Task Dispatch library Header file.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiTbtTaskDispatchLib.h.

Enumeration Type Documentation

◆ TBT_BOOT_MODE

enum TBT_BOOT_MODE
Enumerator
TBT_NULL | All policy flags turned off.
TBT_NORMAL | Execute TBT function on cold reset.
TBT_S3 | Execute TBT function on S3 exit.
TBT_S4 | Execute TBT function on S4 exit.
TBT_ALL | Execute TBT function always.

Definition at line 54 of file PeiTbtTaskDispatchLib.h.

Function Documentation

◆ TbtGetBootMode()

TBT_BOOT_MODE TbtGetBootMode ( VOID )

Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE.

Return values
TBT_BOOT_MODE Mode to be used to execute corresponding TBT tasks.

◆ TbtTaskDistpach()

VOID TbtTaskDistpach | ( | IN TBT_CALL_TABLE_ENTRY * | TbtCallTable,
 |  | IN VOID * | PeiTbtConfig
 | ) |  |

TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY.

Parameters
[in] | TBT_CALL_TABLE_ENTRY | TbtCallTable
[in] | VOID | PeiTbtConfig
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiTbtTaskDispatchLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiTbtTaskDispatchLib.h
Go to the documentation of this file.
1 /**@file
2 PEI TBT Task Dispatch library Header file
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__
36 #define __PEI_TBT_TASK_DISPATCH_LIB_H__
37
38 #include <Library/PeiServicesLib.h>
39 #include <Library/MemoryAllocationLib.h>
40 #include <Library/BaseMemoryLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/GpioLib.h>
43 #include <Library/IoLib.h>
44 #include <Library/PciSegmentLib.h>
45 #include <Library/HobLib.h>
46 #include <Library/PcdLib.h>
47
48 typedef
49 EFI_STATUS
50 (EFIAPI *TBT_TASK) (
51 VOID *PeiTbtConfig
52 );
53
54 typedef enum {
55 TBT_NULL, ///< All policy flags turned off.
56 TBT_NORMAL = (1 << 0), ///< Execute TBT function on cold reset.
57 TBT_S3 = (1 << 1), ///< Execute TBT function on S3 exit.
58 TBT_S4 = (1 << 2), ///< Execute TBT function on S4 exit.
59 TBT_ALL = MAX_UINTN ///< Execute TBT function always.
60 } TBT_BOOT_MODE;
61
62 typedef struct {
63 TBT_TASK TbtTask; ///< Ptr to function to execute, with parameter list.
64 TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on TbtBootModeFlag
65 CHAR8 *String; ///< Output string describing this task.
66 } TBT_CALL_TABLE_ENTRY;
67
68 /**
69 Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE
70
71 @retval TBT_BOOT_MODE Mode to be used to execute corresponding TBT tasks.
72 **/
73 TBT_BOOT_MODE
74 TbtGetBootMode (
75 VOID
76 );
77
78 /**
79 TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY
80
81 @param[in] TBT_CALL_TABLE_ENTRY TbtCallTable
82 @param[in] VOID PeiTbtConfig
83 **/
84 VOID
85 TbtTaskDistpach (
86 IN TBT_CALL_TABLE_ENTRY *TbtCallTable,
87 IN VOID *PeiTbtConfig
88 );
89 #endif
GpioLib.h
Header file for GpioLib.
TBT_ALL
@ TBT_ALL
Execute TBT function always.
Definition: PeiTbtTaskDispatchLib.h:59
TBT_NORMAL
@ TBT_NORMAL
Execute TBT function on cold reset.
Definition: PeiTbtTaskDispatchLib.h:56
TBT_BOOT_MODE
TBT_BOOT_MODE
Definition: PeiTbtTaskDispatchLib.h:54
TbtGetBootMode
TBT_BOOT_MODE TbtGetBootMode(VOID)
Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE.
TBT_NULL
@ TBT_NULL
All policy flags turned off.
Definition: PeiTbtTaskDispatchLib.h:55
TBT_S3
@ TBT_S3
Execute TBT function on S3 exit.
Definition: PeiTbtTaskDispatchLib.h:57
TbtTaskDistpach
VOID TbtTaskDistpach(IN TBT_CALL_TABLE_ENTRY *TbtCallTable, IN VOID *PeiTbtConfig)
TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY.
TBT_S4
@ TBT_S4
Execute TBT function on S4 exit.
Definition: PeiTbtTaskDispatchLib.h:58
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiVrDomainLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PeiVrDomainLib.h File Reference

Define Maximum Number of Voltage Regulator Domains. More...

Go to the source code of this file.

Functions

UINT16 GetMaxNumVrs (VOID)
Returns the maximum number of voltage regulator domains. More...

Detailed Description

Define Maximum Number of Voltage Regulator Domains.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PeiVrDomainLib.h.

Function Documentation

◆ GetMaxNumVrs()

UINT16 GetMaxNumVrs ( VOID )

Returns the maximum number of voltage regulator domains.

Return values
Maximum Number of VR Domains
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PeiVrDomainLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PeiVrDomainLib.h
Go to the documentation of this file.
1 /** @file
2 Define Maximum Number of Voltage Regulator Domains.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_VR_DOMAIN_LIB_H
37 #define _PEI_VR_DOMAIN_LIB_H
38
39 /**
40 Returns the maximum number of voltage regulator domains.
41
42 @retval Maximum Number of VR Domains
43 **/
44 UINT16
45 GetMaxNumVrs (
46 VOID
47 );
48
49 #endif //_PEI_VR_DOMAIN_LIB_H
GetMaxNumVrs
UINT16 GetMaxNumVrs(VOID)
Returns the maximum number of voltage regulator domains.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformMeHook.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs
PlatformMeHook.h File Reference

Interface definition details for platform hook support to ME module during DXE phase. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _PLATFORM_ME_HOOK_PROTOCOL
Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM before perform reset command through Heci. More...

Macros

#define PLATFORM_ME_HOOK_PROTOCOL_REVISION 1
ME Hook provided by platform for DXE phase This protocol provides an interface to hook reference code by OEM.

Typedefs

typedef EFI_STATUS(* | PLATFORM_ME_HOOK_PRE_GLOBAL_RESET) (VOID)
Platform hook before BIOS sends Global Reset Heci Message to ME. More...
typedef struct _PLATFORM_ME_HOOK_PROTOCOL | PLATFORM_ME_HOOK_PROTOCOL
Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM before perform reset command through Heci.

Detailed Description

Interface definition details for platform hook support to ME module during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PlatformMeHook.h.

Typedef Documentation

◆ PLATFORM_ME_HOOK_PRE_GLOBAL_RESET

typedef EFI_STATUS( * PLATFORM_ME_HOOK_PRE_GLOBAL_RESET) (VOID)

Platform hook before BIOS sends Global Reset Heci Message to ME.

Return values
EFI Status Code

Definition at line 52 of file PlatformMeHook.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformMeHook.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
PlatformMeHook.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details for platform hook support to ME module during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PLATFORM_ME_HOOK_H_
36 #define _PLATFORM_ME_HOOK_H_
37
38 ///
39 /// ME Hook provided by platform for DXE phase
40 /// This protocol provides an interface to hook reference code by OEM.
41 ///
42
43 #define PLATFORM_ME_HOOK_PROTOCOL_REVISION 1
44
45 /**
46 Platform hook before BIOS sends Global Reset Heci Message to ME
47
48
49 @retval EFI Status Code
50 **/
51 typedef
52 EFI_STATUS
53 (EFIAPI *PLATFORM_ME_HOOK_PRE_GLOBAL_RESET) (
54 VOID
55 )
56 ;
57
58 ///
59 /// Platform Intel ME Hook Protocol
60 /// This protocol provides an interface to hook reference code by OEM before perform reset command through Heci.
61 ///
62 typedef struct _PLATFORM_ME_HOOK_PROTOCOL {
63 ///
64 /// Function pointer for the hook called before BIOS sends Global Reset Heci Message to ME
65 ///
66 PLATFORM_ME_HOOK_PRE_GLOBAL_RESET PreGlobalReset;
67 } PLATFORM_ME_HOOK_PROTOCOL;
68
69 extern EFI_GUID gPlatformMeHookProtocolGuid;
70
71 #endif
_PLATFORM_ME_HOOK_PROTOCOL::PreGlobalReset
PLATFORM_ME_HOOK_PRE_GLOBAL_RESET PreGlobalReset
Function pointer for the hook called before BIOS sends Global Reset Heci Message to ME.
Definition: PlatformMeHook.h:66
PLATFORM_ME_HOOK_PRE_GLOBAL_RESET
EFI_STATUS(* PLATFORM_ME_HOOK_PRE_GLOBAL_RESET)(VOID)
Platform hook before BIOS sends Global Reset Heci Message to ME.
Definition: PlatformMeHook.h:53
_PLATFORM_ME_HOOK_PROTOCOL
Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM bef...
Definition: PlatformMeHook.h:62
PLATFORM_ME_HOOK_PROTOCOL
struct _PLATFORM_ME_HOOK_PROTOCOL PLATFORM_ME_HOOK_PROTOCOL
Platform Intel ME Hook Protocol This protocol provides an interface to hook reference code by OEM bef...
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetFilter.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
PlatformSpecificResetFilter.h File Reference

This Protocol provides services to register a platform specific reset filter for ResetSystem(). More...

#include <Protocol/ResetNotification.h>
Include dependency graph for PlatformSpecificResetFilter.h:

Go to the source code of this file.

Detailed Description

This Protocol provides services to register a platform specific reset filter for ResetSystem().

A reset filter evaluates the parameters passed to ResetSystem() and converts a ResetType of EfiResetPlatformSpecific to a non-platform specific reset type. The registered filters are processed before the UEFI 2.7 Reset Notifications.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file PlatformSpecificResetFilter.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetFilter.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
PlatformSpecificResetFilter.h
Go to the documentation of this file.
1 /** @file
2 This Protocol provides services to register a platform specific reset filter
3 for ResetSystem(). A reset filter evaluates the parameters passed to
4 ResetSystem() and converts a ResetType of EfiResetPlatformSpecific to a
5 non-platform specific reset type. The registered filters are processed before
6 the UEFI 2.7 Reset Notifications.
7
8 @copyright
9 INTEL CONFIDENTIAL
10 Copyright (c) 2017 Intel Corporation. All rights reserved.<BR>
11 This program and the accompanying materials are licensed and made available under
12 the terms and conditions of the BSD License that accompanies this distribution.
13 The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php.
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 **/
20
21 #ifndef _PLATFORM_SPECIFIC_RESET_FILTER_PROTOCOL_H_
22 #define _PLATFORM_SPECIFIC_RESET_FILTER_PROTOCOL_H_
23
24 #include <Protocol/ResetNotification.h>
25
26 #define EDKII_PLATFORM_SPECIFIC_RESET_FILTER_PROTOCOL_GUID \
27 { 0x695d7835, 0x8d47, 0x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } }
28
29 typedef EFI_RESET_NOTIFICATION_PROTOCOL EDKII_PLATFORM_SPECIFIC_RESET_FILTER_PROTOCOL;
30
31 extern EFI_GUID gEdkiiPlatformSpecificResetFilterProtocolGuid;
32
33 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetHandler.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi/PlatformSpecificResetHandler.h File Reference

This PPI provides services to register a platform specific handler for ResetSystem(). More...

#include <Protocol/ResetNotification.h>
Include dependency graph for Ppi/PlatformSpecificResetHandler.h:

Go to the source code of this file.

Detailed Description

This PPI provides services to register a platform specific handler for ResetSystem().

The registered handlers are processed after EDKII_PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI notifications.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 - 2018 Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file Ppi/PlatformSpecificResetHandler.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetHandler.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi/PlatformSpecificResetHandler.h
Go to the documentation of this file.
1 /** @file
2 This PPI provides services to register a platform specific handler for
3 ResetSystem(). The registered handlers are processed after
4 EDKII_PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI notifications.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright (c) 2017 - 2018 Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials are licensed and made available under
10 the terms and conditions of the BSD License that accompanies this distribution.
11 The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php.
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #ifndef _PLATFORM_SPECIFIC_RESET_HANDLER_PPI_H_
20 #define _PLATFORM_SPECIFIC_RESET_HANDLER_PPI_H_
21
22 #include <Protocol/ResetNotification.h>
23
24 #define EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PPI_GUID \
25 { 0x75cf14ae, 0x3441, 0x49dc, { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } }
26
27 typedef EFI_RESET_NOTIFICATION_PROTOCOL EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PPI;
28
29 extern EFI_GUID gEdkiiPlatformSpecificResetHandlerPpiGuid;
30
31 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetHandler.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol/PlatformSpecificResetHandler.h File Reference

This protocol provides services to register a platform specific handler for ResetSystem(). More...

#include <Protocol/ResetNotification.h>
Include dependency graph for Protocol/PlatformSpecificResetHandler.h:

Go to the source code of this file.

Detailed Description

This protocol provides services to register a platform specific handler for ResetSystem().

The registered handlers are called after the UEFI 2.7 Reset Notifications are processed

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file Protocol/PlatformSpecificResetHandler.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetHandler.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol/PlatformSpecificResetHandler.h
Go to the documentation of this file.
1 /** @file
2 This protocol provides services to register a platform specific handler for
3 ResetSystem(). The registered handlers are called after the UEFI 2.7 Reset
4 Notifications are processed
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright (c) 2017 Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials are licensed and made available under
10 the terms and conditions of the BSD License that accompanies this distribution.
11 The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php.
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #ifndef _PLATFORM_SPECIFIC_RESET_HANDLER_PROTOCOL_H_
20 #define _PLATFORM_SPECIFIC_RESET_HANDLER_PROTOCOL_H_
21
22 #include <Protocol/ResetNotification.h>
23
24 #define EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PROTOCOL_GUID \
25 { 0x2df6ba0b, 0x7092, 0x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } }
26
27 typedef EFI_RESET_NOTIFICATION_PROTOCOL EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PROTOCOL;
28
29 extern EFI_GUID gEdkiiPlatformSpecificResetHandlerProtocolGuid;
30
31 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetNotification.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PlatformSpecificResetNotification.h File Reference

This PPI provides services to register a platform specific notification callback for ResetSystem(). More...

#include <Protocol/ResetNotification.h>
Include dependency graph for PlatformSpecificResetNotification.h:

Go to the source code of this file.

Detailed Description

This PPI provides services to register a platform specific notification callback for ResetSystem().

The registered handlers are processed after EDKII_PLATFORM_SPECIFIC_RESET_FILTER_PPI notifications and before EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PPI notifications.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2017 - 2018 Intel Corporation. All rights reserved.
Copyright (c) 2017 Microsoft Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file PlatformSpecificResetNotification.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PlatformSpecificResetNotification.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
PlatformSpecificResetNotification.h
Go to the documentation of this file.
1 /** @file
2 This PPI provides services to register a platform specific notification callback for
3 ResetSystem(). The registered handlers are processed after
4 EDKII_PLATFORM_SPECIFIC_RESET_FILTER_PPI notifications and before
5 EDKII_PLATFORM_SPECIFIC_RESET_HANDLER_PPI notifications.
6
7 @copyright
8 INTEL CONFIDENTIAL
9 Copyright (c) 2017 - 2018 Intel Corporation. All rights reserved.<BR>
10 Copyright (c) 2017 Microsoft Corporation. All rights reserved.<BR>
11
12 This program and the accompanying materials are licensed and made available under
13 the terms and conditions of the BSD License that accompanies this distribution.
14 The full text of the license may be found at
15 http://opensource.org/licenses/bsd-license.php.
16
17 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19
20 **/
21
22 #ifndef _PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI_H_
23 #define _PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI_H_
24
25 #include <Protocol/ResetNotification.h>
26
27 #define EDKII_PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI_GUID \
28 { 0xe09f355d, 0xdae8, 0x4910, { 0xb1, 0x4a, 0x92, 0x78, 0x0f, 0xdc, 0xf7, 0xcb } }
29
30 typedef EFI_RESET_NOTIFICATION_PROTOCOL EDKII_PLATFORM_SPECIFIC_RESET_NOTIFICATION_PPI;
31
32 extern EFI_GUID gEdkiiPlatformSpecificResetNotificationPpiGuid;
33
34 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmcLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PmcLib.h File Reference

Header file for PmcLib. More...

#include <PmConfig.h>
Include dependency graph for PmcLib.h:

Go to the source code of this file.

Functions

UINT16 | PmcGetAcpiBase (VOID)
Get PCH ACPI base address. More...
UINT32 | PmcGetPwrmBase (VOID)
Get PCH PWRM base address. More...
VOID | PmcSetTPch25Timing (IN PMC_TPCH25_TIMING TimingValue)
This function sets tPCH25 timing. More...
BOOLEAN | PmcIsRtcBatteryGood (VOID)
This function checks if RTC Power Failure occurred by reading RTC_PWR_FLR bit. More...
BOOLEAN | PmcIsPowerFailureDetected (VOID)
This function checks if Power Failure occurred by reading PWR_FLR bit. More...
BOOLEAN | PmcIsSusPowerFailureDetected (VOID)
This function checks if Power Failure occurred by reading SUS_PWR_FLR bit. More...
VOID | PmcClearPowerFailureStatus (VOID)
This function clears Power Failure status (PWR_FLR)
VOID | PmcClearGlobalResetStatus (VOID)
This function clears Global Reset status (GBL_RST_STS)
VOID | PmcClearHostResetStatus (VOID)
This function clears Host Reset status (HOST_RST_STS)
VOID | PmcClearSusPowerFailureStatus (VOID)
This function clears SUS Power Failure status (SUS_PWR_FLR)
VOID | PmcSetPlatformStateAfterPowerFailure (IN UINT8 PowerStateAfterG3)
This function sets state to which platform will get after power is reapplied. More...
VOID | PmcEnablePowerButtonSmi (VOID)
This function enables Power Button SMI.
VOID | PmcDisablePowerButtonSmi (VOID)
This function disables Power Button SMI.
UINT32 | PmcGetTimerCount (VOID)
This function reads PM Timer Count driven by 3.579545 MHz clock. More...
PMC_SLEEP_STATE | PmcGetSleepTypeAfterWake (VOID)
Get Sleep Type that platform has waken from. More...
VOID | PmcClearWakeStatus (VOID)
Clear PMC Wake Status.
VOID | PmcSetSleepState (PMC_SLEEP_STATE SleepState)
Configure sleep state. More...
BOOLEAN | PmcIsPowerButtonOverrideDetected (VOID)
Check if platform boots after shutdown caused by power button override event. More...
EFI_STATUS | PmcCrashLogDiscovery (OUT PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
This function sends PMC IPC CrashLog Discovery Command. More...
EFI_STATUS | PmcCrashLogDisable (VOID)
This function sends PMC IPC CrashLog Disable Command. More...
EFI_STATUS | PmcCrashLogClear (VOID)
This function sends PMC IPC to clear CrashLog from PMC SSRAM area. More...
EFI_STATUS | PmcCrashLogOnAllReset (VOID)
This function sends PMC IPC to populate CrashLog on all reboot. More...
EFI_STATUS | PmcCrashLogReArm (VOID)
This function sends PMC IPC Crashlog Re-arm command. More...
EFI_STATUS | PmcCrashLogProgramGlobalResetTriggerEnableMask (IN PMC_GLOBAL_RESET_MASK PmcGlobalResetMask, IN PMC_GLOBAL_RESET_MASK1 PmcGlobalResetMask1)
Program the crashlog global reset trigger enable mask. More...
EFI_STATUS | PmcCrashLogRestoreGlobalResetTriggerMask (VOID)
Restore the default value of the global reset trigger enable mask. More...
EFI_STATUS | PmcCrashLogReadGlobalResetTriggerMask (OUT PMC_GLOBAL_RESET_MASK *PmcGlobalResetMask, OUT PMC_GLOBAL_RESET_MASK1 *PmcGlobalResetMask1)
Read the PMC global reset mask. More...
VOID | PmcSetDramInitScratchpad (VOID)
This function will set the DISB - DRAM Initialization Scratchpad Bit.
BOOLEAN | PmcIsGblSmiEn (VOID)
Check global SMI enable is set. More...
BOOLEAN | PmcIsSmiLockSet (VOID)
This function checks if SMI Lock is set. More...
BOOLEAN | PmcIsDebugModeLocked (VOID)
This function checks if Debug Mode is locked. More...
BOOLEAN | PmcIsSetStrapMsgInterfaceLocked (VOID)
This function checks PMC Set Strap Message interface lock. More...
BOOLEAN | PmcIsFivrConfigLocked (VOID)
This function verify VR Config Bit is Locked. More...
VOID | CheckPowerOffNow (VOID)
Check if user wants to turn off in PEI phase.
VOID | ClearSmiAndWake (VOID)
Clear any SMI status or wake status left from boot.
BOOLEAN | PmcIsDwrBootMode (VOID)
Function to check if Dirty Warm Reset occurs (Global Reset has been converted to Host Reset) More...
VOID | PmcSetSwGpeSts (VOID)
Sets the GPE Ctrl bit to generate a _GPE._L62 SCI to an ACPI OS.
BOOLEAN | PmcDetectIntegratedClockSource (VOID)
Read Cpu BCLK source comes from. More...
EFI_STATUS | PmcReadLpmReqData (OUT UINT32 *LpmReqData, IN UINT32 BufLen)
Read Low Power Mode Requirement registers by PMC IPC interface, and store read data to the output buffer. More...
EFI_STATUS | PmicRead8 (IN UINT32 RegisterOffset, OUT UINT8 *Value, IN UINT8 PmicId)
Reads an 8-bit PMIC register of CastroCove. More...
EFI_STATUS | PmicWrite8 (IN UINT32 RegisterOffset, IN UINT8 Value, IN UINT8 PmicId)
Writes an 8-bit PMIC register of CastroCove with a 8-bit value. More...
EFI_STATUS | PmicWriteLock (VOID)
Set OTP memory is write-locked. More...

Detailed Description

Header file for PmcLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PmcLib.h.

Function Documentation

◆ PmcCrashLogClear()

EFI_STATUS PmcCrashLogClear ( VOID )

This function sends PMC IPC to clear CrashLog from PMC SSRAM area.

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Crash Log Clear command failed with an error
EFI_TIMEOUT | Crash Log Clear command did not complete

◆ PmcCrashLogDisable()

EFI_STATUS PmcCrashLogDisable ( VOID )

This function sends PMC IPC CrashLog Disable Command.

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Crash Log Disable command failed with an error
EFI_TIMEOUT | Crash Log Disable command did not complete

◆ PmcCrashLogDiscovery()

EFI_STATUS PmcCrashLogDiscovery ( OUT PMC_IPC_DISCOVERY_BUF * DiscoveryBuffer )

This function sends PMC IPC CrashLog Discovery Command.

Parameters
[out] DiscoveryBuffer Pointer to CrashLog Discovery Data
Return values
EFI_SUCCESS | Command was executed successfully
EFI_INVALID_PARAMETER | NULL argument
EFI_DEVICE_ERROR | Crash Log Discovery command failed with an error
EFI_TIMEOUT | Crash Log Discovery command did not complete

◆ PmcCrashLogOnAllReset()

EFI_STATUS PmcCrashLogOnAllReset ( VOID )

This function sends PMC IPC to populate CrashLog on all reboot.

The SSRAM area will be cleared on G3 by PMC automatically

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Crash Log command failed with an error
EFI_TIMEOUT | Crash Log command did not complete

◆ PmcCrashLogProgramGlobalResetTriggerEnableMask()

EFI_STATUS PmcCrashLogProgramGlobalResetTriggerEnableMask | ( | IN PMC_GLOBAL_RESET_MASK | PmcGlobalResetMask,
 |  | IN PMC_GLOBAL_RESET_MASK1 | PmcGlobalResetMask1
 | ) |  |

Program the crashlog global reset trigger enable mask.

Parameters
[in] | PmcGlobalResetMask | Global reset mask
[in] | PmcGlobalResetMask1 | Global reset mask 1
Return values
Result of the IPC command send

◆ PmcCrashLogReadGlobalResetTriggerMask()

EFI_STATUS PmcCrashLogReadGlobalResetTriggerMask | ( | OUT PMC_GLOBAL_RESET_MASK * | PmcGlobalResetMask,
 |  | OUT PMC_GLOBAL_RESET_MASK1 * | PmcGlobalResetMask1
 | ) |  |

Read the PMC global reset mask.

Parameters
[out] | PmcGlobalResetMask | Global reset mask
[out] | PmcGlobalResetMask1 | Global reset mask 1
Return values
Result of the IPC command send

◆ PmcCrashLogReArm()

EFI_STATUS PmcCrashLogReArm ( VOID )

This function sends PMC IPC Crashlog Re-arm command.

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Crash Log command failed with an error
EFI_TIMEOUT | Crash Log command did not complete

◆ PmcCrashLogRestoreGlobalResetTriggerMask()

EFI_STATUS PmcCrashLogRestoreGlobalResetTriggerMask ( VOID )

Restore the default value of the global reset trigger enable mask.

Return values
Result of the IPC command send

◆ PmcDetectIntegratedClockSource()

BOOLEAN PmcDetectIntegratedClockSource ( VOID )

Read Cpu BCLK source comes from.

@reval TRUE BCLK from integrated clock @reval FALSE BCLK from discrete clock

◆ PmcGetAcpiBase()

UINT16 PmcGetAcpiBase ( VOID )

Get PCH ACPI base address.

Return values
Address Address of PWRM base address.

◆ PmcGetPwrmBase()

UINT32 PmcGetPwrmBase ( VOID )

Get PCH PWRM base address.

Return values
Address Address of PWRM base address.

◆ PmcGetSleepTypeAfterWake()

PMC_SLEEP_STATE PmcGetSleepTypeAfterWake ( VOID )

Get Sleep Type that platform has waken from.

Return values
SleepType Sleep Type

◆ PmcGetTimerCount()

UINT32 PmcGetTimerCount ( VOID )

This function reads PM Timer Count driven by 3.579545 MHz clock.

Return values
PM Timer Count

◆ PmcIsDebugModeLocked()

BOOLEAN PmcIsDebugModeLocked ( VOID )

This function checks if Debug Mode is locked.

Return values
Debug Mode Lock state

◆ PmcIsDwrBootMode()

BOOLEAN PmcIsDwrBootMode ( VOID )

Function to check if Dirty Warm Reset occurs (Global Reset has been converted to Host Reset)

@reval TRUE DWR occurs @reval FALSE Normal boot flow

◆ PmcIsFivrConfigLocked()

BOOLEAN PmcIsFivrConfigLocked ( VOID )

This function verify VR Config Bit is Locked.

Return values
TRUE | VR Config Bit is Locked.
FALSE | VR Config Bit is Unlocked.

◆ PmcIsGblSmiEn()

BOOLEAN PmcIsGblSmiEn ( VOID )

Check global SMI enable is set.

Return values
TRUE Global SMI enable is set FALSE Global SMI enable is not set

◆ PmcIsPowerButtonOverrideDetected()

BOOLEAN PmcIsPowerButtonOverrideDetected ( VOID )

Check if platform boots after shutdown caused by power button override event.

Return values
TRUE | Power Button Override occurred in last system boot
FALSE | Power Button Override didn't occur

◆ PmcIsPowerFailureDetected()

BOOLEAN PmcIsPowerFailureDetected ( VOID )

This function checks if Power Failure occurred by reading PWR_FLR bit.

Return values
Power Failure state

◆ PmcIsRtcBatteryGood()

BOOLEAN PmcIsRtcBatteryGood ( VOID )

This function checks if RTC Power Failure occurred by reading RTC_PWR_FLR bit.

Return values
RTC Power Failure state: TRUE - Battery is always present. FALSE - CMOS is cleared.

◆ PmcIsSetStrapMsgInterfaceLocked()

BOOLEAN PmcIsSetStrapMsgInterfaceLocked ( VOID )

This function checks PMC Set Strap Message interface lock.

Return values
State of PMC Set Strap Message Interface lock

◆ PmcIsSmiLockSet()

BOOLEAN PmcIsSmiLockSet ( VOID )

This function checks if SMI Lock is set.

Return values
SMI Lock state

◆ PmcIsSusPowerFailureDetected()

BOOLEAN PmcIsSusPowerFailureDetected ( VOID )

This function checks if Power Failure occurred by reading SUS_PWR_FLR bit.

Return values
SUS Power Failure state

◆ PmcReadLpmReqData()

EFI_STATUS PmcReadLpmReqData | ( | OUT UINT32 * | LpmReqData,
 |  | IN UINT32 | BufLen
 | ) |  |

Read Low Power Mode Requirement registers by PMC IPC interface, and store read data to the output buffer.

Parameters
[OUT] | LpmReqData Point to buffer (caller allocated) where LPM requirement data being stored.
[IN] | BufLen Length of Buffer which param LpmReqData point to

@reval EFI_SUCCESS Function was executed successfully @reval EFI_INVALID_PARAMETER Parameters are invalid @reval EFI_DEVICE_ERROR Fail to read LPM requirement data

◆ PmcSetPlatformStateAfterPowerFailure()

VOID PmcSetPlatformStateAfterPowerFailure ( IN UINT8 PowerStateAfterG3 )

This function sets state to which platform will get after power is reapplied.

Parameters
[in] PowerStateAfterG3 0: S0 state (boot) 1: S5/S4 State

◆ PmcSetSleepState()

VOID PmcSetSleepState ( PMC_SLEEP_STATE SleepState )

Configure sleep state.

Parameters
[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE

◆ PmcSetTPch25Timing()

VOID PmcSetTPch25Timing ( IN PMC_TPCH25_TIMING TimingValue )

This function sets tPCH25 timing.

Parameters
[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms)

◆ PmicRead8()

EFI_STATUS PmicRead8 | ( | IN UINT32 | RegisterOffset,
 |  | OUT UINT8 * | Value,
 |  | IN UINT8 | PmicId
 | ) |  |

Reads an 8-bit PMIC register of CastroCove.

Reads the 8-bit PMIC register specified by RegisterOffset input field. The operation status is returned.

Parameters
[in] | RegisterOffset | - The PMIC register to read
[out] | Value | - The value read from the PMIC register
Return values
EFI_SUCCESS | - Read bytes from PMIC device successfully
Others | - Status depends on IPC operation

◆ PmicWrite8()

EFI_STATUS PmicWrite8 | ( | IN UINT32 | RegisterOffset,
 |  | IN UINT8 | Value,
 |  | IN UINT8 | PmicId
 | ) |  |

Writes an 8-bit PMIC register of CastroCove with a 8-bit value.

Writes the 8-bit PMIC register specified by RegisterOffset input field with the value specified by Value and return the operation status.

Parameters
[in] | RegisterOffset | - The PMIC register to write.
[in] | Value | - The value to write to the PMIC register
Return values
EFI_SUCCESS | - Write bytes to PMIC device successfully
Others | - Status depends on IPC operation

◆ PmicWriteLock()

EFI_STATUS PmicWriteLock ( VOID )

Set OTP memory is write-locked.

Parameters
[in] - None
Return values
EFI_SUCCESS | - Write bytes to PMIC device successfully
Others | - Status depends on IPC operation
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmcLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PmcLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for PmcLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PMC_LIB_H_
36 #define _PMC_LIB_H_
37
38 #include <PmConfig.h>
39
40 #pragma pack(1)
41
42 typedef enum {
43 PmcTPch25_10us = 0,
44 PmcTPch25_100us,
45 PmcTPch25_1ms,
46 PmcTPch25_10ms,
47 } PMC_TPCH25_TIMING;
48
49 typedef enum {
50 PmcNotASleepState,
51 PmcInS0State,
52 PmcS1SleepState,
53 PmcS2SleepState,
54 PmcS3SleepState,
55 PmcS4SleepState,
56 PmcS5SleepState,
57 PmcUndefinedState,
58 } PMC_SLEEP_STATE;
59
60 typedef struct {
61 UINT32 Buf0;
62 UINT32 Buf1;
63 UINT32 Buf2;
64 UINT32 Buf3;
65 } PMC_IPC_COMMAND_BUFFER;
66
67 //
68 // Structure to Check different attributes for CrashLog supported by PMC.
69 //
70 typedef union {
71 struct {
72 UINT32 Avail : 1; ///< CrashLog feature availability bit
73 UINT32 Dis : 1; ///< CrasLog Disable bit
74 UINT32 Rsvd : 2; ///< Reserved
75 UINT32 Size : 12; ///< CrasLog data size. (If it is zero, use default size 0xC00)
76 UINT32 BaseOffset : 16; ///< Start offset of CrashLog in PMC SSRAM
77 } Bits;
78 struct {
79 UINT32 Avail : 1; ///< CrashLog feature availability bit
80 UINT32 Dis : 1; ///< CrasLog Disable bit
81 UINT32 Mech : 2; ///< CrashLog mechanism
82 UINT32 ManuTri : 1; ///< Manul trigger command.
83 UINT32 Clr : 1; ///< Clear Command
84 UINT32 AllReset : 1; ///< Trigger on all reset command
85 UINT32 ReArm : 1; ///< Re-arm command
86 UINT32 GlbRstTriggerMask : 1; ///< Global reset trigger mask supported
87 UINT32 Rsvd : 18; ///< Pch Specific reserved
88 UINT32 GlbRstTriggerMaskSts : 1; ///< Global reset trigger mask status
89 UINT32 CrashLogReq: 1; ///< Crash log requestor flow
90 UINT32 TriArmedSts: 1; ///< Trigger armed status, re-arm indication bit.
91 UINT32 TriAllReset: 1; ///< Trigger on all resets status
92 UINT32 CrashDisSts: 1; ///< Crash log disabled status
93 UINT32 PchRsvd : 16; ///< Pch Specific reserved
94 UINT32 DesTableOffset: 16; ///< Descriptor Table offset
95 } Bits64;
96 UINT32 Uint32;
97 UINT64 Uint64;
98 } PMC_IPC_DISCOVERY_BUF;
99
100 typedef union {
101 struct {
102 UINT32 Offset : 16;
103 UINT32 Size : 16;
104 } Info;
105 UINT32 Uint32;
106 } PMC_CRASHLOG_RECORDS;
107
108 typedef struct PmcCrashLogLink {
109 PMC_CRASHLOG_RECORDS Record;
110 UINT64 AllocateAddress;
111 struct PmcCrashLogLink *Next;
112 } PMC_CRASHLOG_LINK;
113
114 #pragma pack()
115
116 /**
117 Get PCH ACPI base address.
118
119 @retval Address Address of PWRM base address.
120 **/
121 UINT16
122 PmcGetAcpiBase (
123 VOID
124 );
125
126 /**
127 Get PCH PWRM base address.
128
129 @retval Address Address of PWRM base address.
130 **/
131 UINT32
132 PmcGetPwrmBase (
133 VOID
134 );
135
136 /**
137 This function sets tPCH25 timing
138
139 @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms)
140 **/
141 VOID
142 PmcSetTPch25Timing (
143 IN PMC_TPCH25_TIMING TimingValue
144 );
145
146 /**
147 This function checks if RTC Power Failure occurred by
148 reading RTC_PWR_FLR bit
149
150 @retval RTC Power Failure state: TRUE - Battery is always present.
151 FALSE - CMOS is cleared.
152 **/
153 BOOLEAN
154 PmcIsRtcBatteryGood (
155 VOID
156 );
157
158 /**
159 This function checks if Power Failure occurred by
160 reading PWR_FLR bit
161
162 @retval Power Failure state
163 **/
164 BOOLEAN
165 PmcIsPowerFailureDetected (
166 VOID
167 );
168
169 /**
170 This function checks if Power Failure occurred by
171 reading SUS_PWR_FLR bit
172
173 @retval SUS Power Failure state
174 **/
175 BOOLEAN
176 PmcIsSusPowerFailureDetected (
177 VOID
178 );
179
180 /**
181 This function clears Power Failure status (PWR_FLR)
182 **/
183 VOID
184 PmcClearPowerFailureStatus (
185 VOID
186 );
187
188 /**
189 This function clears Global Reset status (GBL_RST_STS)
190 **/
191 VOID
192 PmcClearGlobalResetStatus (
193 VOID
194 );
195
196 /**
197 This function clears Host Reset status (HOST_RST_STS)
198 **/
199 VOID
200 PmcClearHostResetStatus (
201 VOID
202 );
203
204 /**
205 This function clears SUS Power Failure status (SUS_PWR_FLR)
206 **/
207 VOID
208 PmcClearSusPowerFailureStatus (
209 VOID
210 );
211
212 /**
213 This function sets state to which platform will get after power is reapplied
214
215 @param[in] PowerStateAfterG3 0: S0 state (boot)
216 1: S5/S4 State
217 **/
218 VOID
219 PmcSetPlatformStateAfterPowerFailure (
220 IN UINT8 PowerStateAfterG3
221 );
222
223 /**
224 This function enables Power Button SMI
225 **/
226 VOID
227 PmcEnablePowerButtonSmi (
228 VOID
229 );
230
231 /**
232 This function disables Power Button SMI
233 **/
234 VOID
235 PmcDisablePowerButtonSmi (
236 VOID
237 );
238
239 /**
240 This function reads PM Timer Count driven by 3.579545 MHz clock
241
242 @retval PM Timer Count
243 **/
244 UINT32
245 PmcGetTimerCount (
246 VOID
247 );
248
249 /**
250 Get Sleep Type that platform has waken from
251
252 @retval SleepType Sleep Type
253 **/
254 PMC_SLEEP_STATE
255 PmcGetSleepTypeAfterWake (
256 VOID
257 );
258
259 /**
260 Clear PMC Wake Status
261 **/
262 VOID
263 PmcClearWakeStatus (
264 VOID
265 );
266
267 /**
268 Configure sleep state
269
270 @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE
271 **/
272 VOID
273 PmcSetSleepState (
274 PMC_SLEEP_STATE SleepState
275 );
276
277 /**
278 Check if platform boots after shutdown caused by power button override event
279
280 @retval TRUE Power Button Override occurred in last system boot
281 @retval FALSE Power Button Override didn't occur
282 **/
283 BOOLEAN
284 PmcIsPowerButtonOverrideDetected (
285 VOID
286 );
287
288 /**
289 This function sends PMC IPC CrashLog Discovery Command
290
291 @param[out] DiscoveryBuffer Pointer to CrashLog Discovery Data
292
293 @retval EFI_SUCCESS Command was executed successfully
294 @retval EFI_INVALID_PARAMETER NULL argument
295 @retval EFI_DEVICE_ERROR Crash Log Discovery command failed with an error
296 @retval EFI_TIMEOUT Crash Log Discovery command did not complete
297 **/
298 EFI_STATUS
299 PmcCrashLogDiscovery (
300 OUT PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer
301 );
302
303 /**
304 This function sends PMC IPC CrashLog Disable Command
305
306 @retval EFI_SUCCESS Command was executed successfully
307 @retval EFI_DEVICE_ERROR Crash Log Disable command failed with an error
308 @retval EFI_TIMEOUT Crash Log Disable command did not complete
309 **/
310 EFI_STATUS
311 PmcCrashLogDisable (
312 VOID
313 );
314
315 /**
316 This function sends PMC IPC to clear CrashLog from PMC SSRAM area
317
318 @retval EFI_SUCCESS Command was executed successfully
319 @retval EFI_DEVICE_ERROR Crash Log Clear command failed with an error
320 @retval EFI_TIMEOUT Crash Log Clear command did not complete
321 **/
322 EFI_STATUS
323 PmcCrashLogClear (
324 VOID
325 );
326
327 /**
328 This function sends PMC IPC to populate CrashLog on all reboot. The SSRAM area will be cleared on G3 by PMC automatically
329
330 @retval EFI_SUCCESS Command was executed successfully
331 @retval EFI_DEVICE_ERROR Crash Log command failed with an error
332 @retval EFI_TIMEOUT Crash Log command did not complete
333 **/
334 EFI_STATUS
335 PmcCrashLogOnAllReset (
336 VOID
337 );
338
339 /**
340 This function sends PMC IPC Crashlog Re-arm command
341
342 @retval EFI_SUCCESS Command was executed successfully
343 @retval EFI_DEVICE_ERROR Crash Log command failed with an error
344 @retval EFI_TIMEOUT Crash Log command did not complete
345 **/
346 EFI_STATUS
347 PmcCrashLogReArm (
348 VOID
349 );
350
351 /**
352 Program the crashlog global reset trigger enable mask
353
354 @param[in] PmcGlobalResetMask Global reset mask
355 @param[in] PmcGlobalResetMask1 Global reset mask 1
356
357 @retval Result of the IPC command send
358 **/
359 EFI_STATUS
360 PmcCrashLogProgramGlobalResetTriggerEnableMask (
361 IN PMC_GLOBAL_RESET_MASK PmcGlobalResetMask,
362 IN PMC_GLOBAL_RESET_MASK1 PmcGlobalResetMask1
363 );
364
365 /**
366 Restore the default value of the global reset trigger enable mask
367
368 @retval Result of the IPC command send
369 **/
370 EFI_STATUS
371 PmcCrashLogRestoreGlobalResetTriggerMask (
372 VOID
373 );
374
375 /**
376 Read the PMC global reset mask
377
378 @param[out] PmcGlobalResetMask Global reset mask
379 @param[out] PmcGlobalResetMask1 Global reset mask 1
380
381 @retval Result of the IPC command send
382 **/
383 EFI_STATUS
384 PmcCrashLogReadGlobalResetTriggerMask (
385 OUT PMC_GLOBAL_RESET_MASK *PmcGlobalResetMask,
386 OUT PMC_GLOBAL_RESET_MASK1 *PmcGlobalResetMask1
387 );
388
389 /**
390 This function will set the DISB - DRAM Initialization Scratchpad Bit.
391 **/
392 VOID
393 PmcSetDramInitScratchpad (
394 VOID
395 );
396
397 /**
398 Check global SMI enable is set
399
400 @retval TRUE Global SMI enable is set
401 FALSE Global SMI enable is not set
402 **/
403 BOOLEAN
404 PmcIsGblSmiEn (
405 VOID
406 );
407
408 /**
409 This function checks if SMI Lock is set
410
411 @retval SMI Lock state
412 **/
413 BOOLEAN
414 PmcIsSmiLockSet (
415 VOID
416 );
417
418 /**
419 This function checks if Debug Mode is locked
420
421 @retval Debug Mode Lock state
422 **/
423 BOOLEAN
424 PmcIsDebugModeLocked (
425 VOID
426 );
427
428 /**
429 This function checks PMC Set Strap Message interface lock
430
431 @retval State of PMC Set Strap Message Interface lock
432 **/
433 BOOLEAN
434 PmcIsSetStrapMsgInterfaceLocked (
435 VOID
436 );
437
438 /**
439 This function verify VR Config Bit is Locked
440
441 @retval TRUE VR Config Bit is Locked.
442 @retval FALSE VR Config Bit is Unlocked.
443 **/
444 BOOLEAN
445 PmcIsFivrConfigLocked (
446 VOID
447 );
448
449 /**
450 Check if user wants to turn off in PEI phase
451
452 **/
453 VOID
454 CheckPowerOffNow(
455 VOID
456 );
457
458
459 /**
460 Clear any SMI status or wake status left from boot.
461 **/
462 VOID
463 ClearSmiAndWake (
464 VOID
465 );
466
467 /**
468 Function to check if Dirty Warm Reset occurs
469 (Global Reset has been converted to Host Reset)
470
471 @reval TRUE DWR occurs
472 @reval FALSE Normal boot flow
473 **/
474 BOOLEAN
475 PmcIsDwrBootMode (
476 VOID
477 );
478
479 /**
480 Sets the GPE Ctrl bit to generate a _GPE._L62 SCI to an ACPI OS
481 **/
482 VOID
483 PmcSetSwGpeSts (
484 VOID
485 );
486
487 /**
488 Read Cpu BCLK source comes from
489
490 @reval TRUE BCLK from integrated clock
491 @reval FALSE BCLK from discrete clock
492 **/
493 BOOLEAN
494 PmcDetectIntegratedClockSource (
495 VOID
496 );
497
498 /**
499 Read Low Power Mode Requirement registers by PMC IPC interface,
500 and store read data to the output buffer.
501
502 @param[OUT] LpmReqData Point to buffer (caller allocated) where LPM requirement data being stored.
503 @param[IN] BufLen Length of Buffer which param LpmReqData point to
504
505 @reval EFI_SUCCESS Function was executed successfully
506 @reval EFI_INVALID_PARAMETER Parameters are invalid
507 @reval EFI_DEVICE_ERROR Fail to read LPM requirement data
508 **/
509 EFI_STATUS
510 PmcReadLpmReqData (
511 OUT UINT32 *LpmReqData,
512 IN UINT32 BufLen
513 );
514
515 /**
516 Reads an 8-bit PMIC register of CastroCove.
517
518 Reads the 8-bit PMIC register specified by RegisterOffset input field.
519 The operation status is returned.
520
521 @param[in] RegisterOffset - The PMIC register to read
522 @param[out] Value - The value read from the PMIC register
523
524 @retval EFI_SUCCESS - Read bytes from PMIC device successfully
525 @retval Others - Status depends on IPC operation
526 **/
527 EFI_STATUS
528 EFIAPI
529 PmicRead8 (
530 IN UINT32 RegisterOffset,
531 OUT UINT8 *Value,
532 IN UINT8 PmicId
533 );
534
535 /**
536 Writes an 8-bit PMIC register of CastroCove with a 8-bit value.
537
538 Writes the 8-bit PMIC register specified by RegisterOffset input field with the value specified
539 by Value and return the operation status.
540
541 @param[in] RegisterOffset - The PMIC register to write.
542 @param[in] Value - The value to write to the PMIC register
543
544 @retval EFI_SUCCESS - Write bytes to PMIC device successfully
545 @retval Others - Status depends on IPC operation
546 **/
547 EFI_STATUS
548 EFIAPI
549 PmicWrite8 (
550 IN UINT32 RegisterOffset,
551 IN UINT8 Value,
552 IN UINT8 PmicId
553 );
554
555 /**
556 Set OTP memory is write-locked
557
558 @param[in] - None
559
560 @retval EFI_SUCCESS - Write bytes to PMIC device successfully
561 @retval Others - Status depends on IPC operation
562 **/
563 EFI_STATUS
564 EFIAPI
565 PmicWriteLock (
566 VOID
567 );
568
569 #endif // _PMC_LIB_H_
PmcCrashLogDisable
EFI_STATUS PmcCrashLogDisable(VOID)
This function sends PMC IPC CrashLog Disable Command.
PmcIsDwrBootMode
BOOLEAN PmcIsDwrBootMode(VOID)
Function to check if Dirty Warm Reset occurs (Global Reset has been converted to Host Reset)
ClearSmiAndWake
VOID ClearSmiAndWake(VOID)
Clear any SMI status or wake status left from boot.
PmcGetSleepTypeAfterWake
PMC_SLEEP_STATE PmcGetSleepTypeAfterWake(VOID)
Get Sleep Type that platform has waken from.
PmcIsSusPowerFailureDetected
BOOLEAN PmcIsSusPowerFailureDetected(VOID)
This function checks if Power Failure occurred by reading SUS_PWR_FLR bit.
PmcIsSmiLockSet
BOOLEAN PmcIsSmiLockSet(VOID)
This function checks if SMI Lock is set.
PmcIsRtcBatteryGood
BOOLEAN PmcIsRtcBatteryGood(VOID)
This function checks if RTC Power Failure occurred by reading RTC_PWR_FLR bit.
PmcIsDebugModeLocked
BOOLEAN PmcIsDebugModeLocked(VOID)
This function checks if Debug Mode is locked.
PmcDetectIntegratedClockSource
BOOLEAN PmcDetectIntegratedClockSource(VOID)
Read Cpu BCLK source comes from.
PmcCrashLogOnAllReset
EFI_STATUS PmcCrashLogOnAllReset(VOID)
This function sends PMC IPC to populate CrashLog on all reboot.
PmcCrashLogDiscovery
EFI_STATUS PmcCrashLogDiscovery(OUT PMC_IPC_DISCOVERY_BUF *DiscoveryBuffer)
This function sends PMC IPC CrashLog Discovery Command.
PmcGetTimerCount
UINT32 PmcGetTimerCount(VOID)
This function reads PM Timer Count driven by 3.579545 MHz clock.
PmicWriteLock
EFI_STATUS PmicWriteLock(VOID)
Set OTP memory is write-locked.
PmcIsPowerFailureDetected
BOOLEAN PmcIsPowerFailureDetected(VOID)
This function checks if Power Failure occurred by reading PWR_FLR bit.
PmcGetPwrmBase
UINT32 PmcGetPwrmBase(VOID)
Get PCH PWRM base address.
PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register.
Definition: PmConfig.h:152
CheckPowerOffNow
VOID CheckPowerOffNow(VOID)
Check if user wants to turn off in PEI phase.
PmcClearPowerFailureStatus
VOID PmcClearPowerFailureStatus(VOID)
This function clears Power Failure status (PWR_FLR)
PmicRead8
EFI_STATUS PmicRead8(IN UINT32 RegisterOffset, OUT UINT8 *Value, IN UINT8 PmicId)
Reads an 8-bit PMIC register of CastroCove.
PmcClearHostResetStatus
VOID PmcClearHostResetStatus(VOID)
This function clears Host Reset status (HOST_RST_STS)
PmicWrite8
EFI_STATUS PmicWrite8(IN UINT32 RegisterOffset, IN UINT8 Value, IN UINT8 PmicId)
Writes an 8-bit PMIC register of CastroCove with a 8-bit value.
PmcClearSusPowerFailureStatus
VOID PmcClearSusPowerFailureStatus(VOID)
This function clears SUS Power Failure status (SUS_PWR_FLR)
PmcCrashLogProgramGlobalResetTriggerEnableMask
EFI_STATUS PmcCrashLogProgramGlobalResetTriggerEnableMask(IN PMC_GLOBAL_RESET_MASK PmcGlobalResetMask, IN PMC_GLOBAL_RESET_MASK1 PmcGlobalResetMask1)
Program the crashlog global reset trigger enable mask.
PmcClearGlobalResetStatus
VOID PmcClearGlobalResetStatus(VOID)
This function clears Global Reset status (GBL_RST_STS)
PmcSetPlatformStateAfterPowerFailure
VOID PmcSetPlatformStateAfterPowerFailure(IN UINT8 PowerStateAfterG3)
This function sets state to which platform will get after power is reapplied.
PmcSetSwGpeSts
VOID PmcSetSwGpeSts(VOID)
Sets the GPE Ctrl bit to generate a _GPE._L62 SCI to an ACPI OS.
PmcGetAcpiBase
UINT16 PmcGetAcpiBase(VOID)
Get PCH ACPI base address.
PmcIsFivrConfigLocked
BOOLEAN PmcIsFivrConfigLocked(VOID)
This function verify VR Config Bit is Locked.
PmConfig.h
Power Management policy.
PmcIsPowerButtonOverrideDetected
BOOLEAN PmcIsPowerButtonOverrideDetected(VOID)
Check if platform boots after shutdown caused by power button override event.
PmcIsSetStrapMsgInterfaceLocked
BOOLEAN PmcIsSetStrapMsgInterfaceLocked(VOID)
This function checks PMC Set Strap Message interface lock.
PmcDisablePowerButtonSmi
VOID PmcDisablePowerButtonSmi(VOID)
This function disables Power Button SMI.
PmcIsGblSmiEn
BOOLEAN PmcIsGblSmiEn(VOID)
Check global SMI enable is set.
PmcCrashLogReArm
EFI_STATUS PmcCrashLogReArm(VOID)
This function sends PMC IPC Crashlog Re-arm command.
PmcReadLpmReqData
EFI_STATUS PmcReadLpmReqData(OUT UINT32 *LpmReqData, IN UINT32 BufLen)
Read Low Power Mode Requirement registers by PMC IPC interface, and store read data to the output buf...
PmcSetDramInitScratchpad
VOID PmcSetDramInitScratchpad(VOID)
This function will set the DISB - DRAM Initialization Scratchpad Bit.
PmcSetTPch25Timing
VOID PmcSetTPch25Timing(IN PMC_TPCH25_TIMING TimingValue)
This function sets tPCH25 timing.
PmcCrashLogRestoreGlobalResetTriggerMask
EFI_STATUS PmcCrashLogRestoreGlobalResetTriggerMask(VOID)
Restore the default value of the global reset trigger enable mask.
PmcSetSleepState
VOID PmcSetSleepState(PMC_SLEEP_STATE SleepState)
Configure sleep state.
PmcCrashLogClear
EFI_STATUS PmcCrashLogClear(VOID)
This function sends PMC IPC to clear CrashLog from PMC SSRAM area.
PmcEnablePowerButtonSmi
VOID PmcEnablePowerButtonSmi(VOID)
This function enables Power Button SMI.
PmcClearWakeStatus
VOID PmcClearWakeStatus(VOID)
Clear PMC Wake Status.
PmcCrashLogReadGlobalResetTriggerMask
EFI_STATUS PmcCrashLogReadGlobalResetTriggerMask(OUT PMC_GLOBAL_RESET_MASK *PmcGlobalResetMask, OUT PMC_GLOBAL_RESET_MASK1 *PmcGlobalResetMask1)
Read the PMC global reset mask.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Classes | Enumerations
PmConfig.h File Reference

Power Management policy. More...

#include <ConfigBlock.h>
Include dependency graph for PmConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events. More...
union | PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config. More...
union | PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register. More...
struct | PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings. More...
struct | BCLK_CONFIG
BCLK configuration. More...

Enumerations

enum PCH_SLP_S4_MIN_ASSERT

Detailed Description

Power Management policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PmConfig.h.

Enumeration Type Documentation

◆ PCH_SLP_S4_MIN_ASSERT

enum PCH_SLP_S4_MIN_ASSERT
Enumerator
PchSlpS4PchTime

The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.

Definition at line 83 of file PmConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
PmConfig.h
Go to the documentation of this file.
1 /** @file
2 Power Management policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PM_CONFIG_H_
36 #define _PM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define PCH_PM_CONFIG_REVISION 5
41 extern EFI_GUID gPmConfigGuid;
42
43 #define BCLK_CONFIG_REVISION 1
44 extern EFI_GUID gBclkConfigGuid;
45
46 #pragma pack (push,1)
47
48 /**
49 This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
50 **/
51 typedef struct {
52 /**
53 Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
54 When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
55 When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
56 **/
57 UINT32 PmeB0S5Dis : 1;
58 UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
59 UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
60 UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
61 UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
62 UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
63 UINT32 RsvdBits0 : 26;
64 } PCH_WAKE_CONFIG;
65
66 typedef enum {
67 PchDeepSxPolDisable,
68 PchDpS5BatteryEn,
69 PchDpS5AlwaysEn,
70 PchDpS4S5BatteryEn,
71 PchDpS4S5AlwaysEn,
72 PchDpS3S4S5BatteryEn,
73 PchDpS3S4S5AlwaysEn
74 } PCH_DEEP_SX_CONFIG;
75
76 typedef enum {
77 PchSlpS360us = 1,
78 PchSlpS31ms,
79 PchSlpS350ms,
80 PchSlpS32s
81 } PCH_SLP_S3_MIN_ASSERT;
82
83 typedef enum {
84 PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
85 PchSlpS41s,
86 PchSlpS42s,
87 PchSlpS43s,
88 PchSlpS44s
89 } PCH_SLP_S4_MIN_ASSERT;
90
91 typedef enum {
92 PchSlpSus0ms = 1,
93 PchSlpSus500ms,
94 PchSlpSus1s,
95 PchSlpSus4s,
96 } PCH_SLP_SUS_MIN_ASSERT;
97
98 typedef enum {
99 PchSlpA0ms = 1,
100 PchSlpA4s,
101 PchSlpA98ms,
102 PchSlpA2s,
103 } PCH_SLP_A_MIN_ASSERT;
104
105 typedef enum {
106 S0ixDisQNoChange,
107 S0ixDisQDciOob,
108 S0ixDisQUsb2Dbc,
109 S0ixDisQMax,
110 } S0IX_DISQ_PROBE_TYPE;
111
112 /**
113 Low Power Mode Enable config.
114 Used to configure if respective S0i2/3 sub-states are to be supported
115 by the platform. Each bit corresponds to one LPM state - LPMx->BITx.
116 Some sub-states will require external FETs controlled by EXT_PWR_GATE#/EXT_PWR_GATE2# pins
117 to gate v1p05-PHY or v1p05-IS supplies
118 **/
119 typedef union {
120 struct {
121 UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable
122 UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable
123 /**
124 LPM2 - S0i2.2 Enable.
125 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
126 Refer to V1p05PhyExtFetControlEn.
127 **/
128 UINT32 S0i2p2En : 1;
129 UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable
130 UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable
131 UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable
132 /**
133 LPM5 - S0i3.3 Enable.
134 Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.
135 Refer to V1p05PhyExtFetControlEn.
136 **/
137 UINT32 S0i3p3En : 1;
138 /**
139 LPM7 - S0i3.4 Enable.
140 Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.
141 Refer to V1p05IsExtFetControlEn.
142 **/
143 UINT32 S0i3p4En : 1;
144 UINT32 Reserved : 24; ///< Reserved
145 } Field;
146 UINT32 Val;
147 } PMC_LPM_S0IX_SUB_STATE_EN;
148
149 /**
150 Description of Global Reset Trigger/Event Mask register
151 **/
152 typedef union {
153 struct {
154 UINT32 Reserved1 : 1;
155 UINT32 Pbo : 1;
156 UINT32 PmcUncErr : 1;
157 UINT32 PchThrm : 1;
158 UINT32 MePbo : 1;
159 UINT32 CpuThrm : 1;
160 UINT32 Megbl : 1;
161 UINT32 LtReset : 1;
162 UINT32 PmcWdt : 1;
163 UINT32 MeWdt : 1;
164 UINT32 PmcFw : 1;
165 UINT32 PchpwrFlr : 1;
166 UINT32 SyspwrFlr : 1;
167 UINT32 Reserved2 : 1;
168 UINT32 MiaUxsErr : 1;
169 UINT32 MiaUxErr : 1;
170 UINT32 CpuThrmWdt : 1;
171 UINT32 MeUncErr : 1;
172 UINT32 AdrGpio : 1;
173 UINT32 OcwdtNoicc : 1;
174 UINT32 OcwdtIcc : 1;
175 UINT32 CseHecUncErr : 1;
176 UINT32 PmcSramUncErr : 1;
177 UINT32 PmcIromParity : 1;
178 UINT32 PmcRfFusaErr : 1;
179 UINT32 Reserved3 : 4;
180 UINT32 PpbrParityErr : 1;
181 UINT32 Reserved4 : 2;
182 } Field;
183 UINT32 Value;
184 } PMC_GLOBAL_RESET_MASK;
185
186 typedef union {
187 struct {
188 UINT32 HostResetTimeout : 1;
189 UINT32 SxEntryTimeout : 1;
190 UINT32 HostRstProm : 1;
191 UINT32 HsmbMsg : 1;
192 UINT32 Pmc3Strike : 1;
193 UINT32 FwGblrstScratch5 : 1;
194 UINT32 PmcDmaTimeout : 1;
195 UINT32 EspiType7 : 1;
196 UINT32 EspiType8 : 1;
197 UINT32 FwGblRstScratch10 : 1;
198 UINT32 FwGblRstScratch11 : 1;
199 UINT32 LpmFwErr : 1;
200 UINT32 BscanMode : 1;
201 UINT32 SlpLvlRspErr : 1;
202 UINT32 FwGblrstScratch15 : 1;
203 UINT32 FwGblrstScratch16 : 1;
204 UINT32 FwGblrstScratch17 : 1;
205 UINT32 FwGblrstScratch18 : 1;
206 UINT32 FwGblrstScratch19 : 1;
207 UINT32 FwGblrstScratch20 : 1;
208 UINT32 FwGblrstScratch21 : 1;
209 UINT32 FwGblrstScratch22 : 1;
210 UINT32 FwGblrstScratch23 : 1;
211 UINT32 Rsvd : 9;
212 } Field;
213 UINT32 Value;
214 } PMC_GLOBAL_RESET_MASK1;
215
216 /**
217 The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
218 The PowerResetStatusClear field would clear the Power/Reset status bits, please
219 set the bits if you want PCH Init driver to clear it, if you want to check the
220 status later then clear the bits.
221
222 <b>Revision 1</b>:
223 - Initial version.
224 <b>Revision 2</b>
225 - Added C10DynamicThresholdAdjustment
226 <b>Revision 3</b>:
227 - Added SkipVccInConfig
228 **/
229 typedef struct {
230 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
231
232 PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
233 UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
234 UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
235 UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
236 UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
237 UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
238 UINT32 RsvdBits0 : 12;
239 /**
240 This member describes whether or not the LPC ClockRun feature of PCH should
241 be enabled. <b>0: Disable</b>; 1: Enable
242 **/
243 UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
244 /**
245 Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
246 Configure On DC PHY Power Diable according to policy SlpLanLowDc.
247 When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
248 This indicates that LAN PHY should be powered off on battery mode.
249 This will override the DC_PP_DIS setting by WolEnableOverride.
250 **/
251 UINT32 SlpLanLowDc : 1;
252 /**
253 PCH power button override period.
254 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
255 <b>Default is 0: 4s</b>
256 **/
257 UINT32 PwrBtnOverridePeriod : 3;
258 /**
259 <b>(Test)</b>
260 Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
261 Enery Report is must have feature. Wihtout Energy Report, the performance report
262 by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
263 in power/performance management algorithm.
264 If for some reason PCH energy report is too high, which forces CPU to try to reduce
265 its power by throttling, then it could try to disable Energy Report to do first debug.
266 This might be due to energy scaling factors are not correct or the LPM settings are not
267 kicking in.
268 **/
269 UINT32 DisableEnergyReport : 1;
270 /**
271 When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
272 When set to Enable, PCH will not pull down AC_PRESENT.
273 This setting is ignored when DeepSx is not supported.
274 Default is <b>0:Disable</b>
275 **/
276 UINT32 DisableDsxAcPresentPulldown : 1;
277 /**
278 Power button native mode disable.
279 While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
280 While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
281 <b>Default is FALSE.</b>
282 **/
283 UINT32 DisableNativePowerButton : 1;
284 UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
285 UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
286 /*
287 Set true to enable TCO timer.
288 When FALSE, it disables PCH ACPI timer, and stops TCO timer.
289 @note: This will have significant power impact when it's enabled.
290 If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
291 and WDAT table must not be exposed to the OS.
292 <b>0: Disable</b>, 1: Enable
293 */
294 UINT32 EnableTcoTimer : 1;
295 /*
296 When VRAlert# feature pin is enabled and its state is '0',
297 the PMC requests throttling to a T3 Tstate to the PCH throttling unit.
298 <b>0: Disable</b>; 1: Enable.
299 */
300 UINT32 VrAlert : 1;
301 /**
302 Decide if PS_ON is to be enabled. This is available on desktop only.
303 PS_ON is a new C10 state from the CPU on desktop SKUs that enables a
304 lower power target that will be required by the California Energy
305 Commission (CEC). When FALSE, PS_ON is to be disabled.}
306 <b>0: Disable</b>; 1: Enable.
307 **/
308 UINT32 PsOnEnable : 1;
309 /**
310 Enable/Disable platform support for CPU_C10_GATE# pin to control gating
311 of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs
312 to be set if board design includes support for CPU_C10_GATE# pin.
313 0: Disable; <b>1: Enable</b>
314 **/
315 UINT32 CpuC10GatePinEnable : 1;
316 /**
317 Control whether to enable PMC debug messages to Trace Hub.
318 When Enabled, PMC HW will send debug messages to trace hub;
319 When Disabled, PMC HW will never send debug meesages to trace hub.
320 @note: When enabled, system may not enter S0ix
321 <b>0: Disable</b>; 1: Enable.
322 **/
323 UINT32 PmcDbgMsgEn : 1;
324 /**
325 Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
326 EXT_PWR_GATE# signal (if supported on platform) can be used to
327 control external FET for power gating ModPHY
328 @note: This setting is not supported and ignored on PCH-H
329 0: Disable; <b>1: Enable</b>.
330 **/
331 UINT32 ModPhySusPgEnable : 1;
332 /**
333 <b>(Test)</b>
334 This policy option enables USB2 PHY SUS Well Power Gating functionality.
335 @note: This setting is not supported and ignored on PCH-H
336 0: disable USB2 PHY SUS Well Power Gating
337 <b>1: enable USB2 PHY SUS Well Power Gating</b>
338 **/
339 UINT32 Usb2PhySusPgEnable : 1;
340 /**
341 Enable Os Idle Mode.
342 0: Disable; <b>1: Enable</b>.
343 **/
344 UINT32 OsIdleEnable : 1;
345 /**
346 Enable control using EXT_PWR_GATE# pin of external FET
347 to power gate v1p05-PHY
348 <b>0: Disable</b>; 1: Enable.
349 **/
350 UINT32 V1p05PhyExtFetControlEn : 1;
351 /**
352 Enable control using EXT_PWR_GATE2# pin of external FET
353 to power gate v1p05-IS supply
354 <b>0: Disable</b>; 1: Enable.
355 **/
356 UINT32 V1p05IsExtFetControlEn : 1;
357 /**
358 Enable/Disable the Low Power Mode Host S0ix Auto-Demotion
359 feature. This feature enables the PMC to autonomously manage
360 the deepest allowed S0ix substate to combat thrashing between
361 power management states.
362 0: Disable; <b>1: Enable</b>.
363 **/
364 UINT32 S0ixAutoDemotion : 1;
365 /**
366 Enable/Disable Latch Events C10 Exit. When this bit is set to 1,
367 SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured
368 on C10 exit (instead of C10 entry which is default)
369 <b>0: Disable</b>; 1: Enable.
370 **/
371 UINT32 LatchEventsC10Exit : 1;
372 UINT32 RsvdBits1 : 10;
373 /*
374 Power button debounce configuration
375 Debounce time can be specified in microseconds. Only certain values according
376 to below formula are supported:
377 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period).
378 RTC clock with f = 32 KHz is used for glitch filter.
379 DebounceTime = (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).
380 Supported DebounceTime values are following:
381 DebounceTime = 0 -> Debounce feature disabled
382 DebounceTime > 0 && < 250us -> Not supported
383 DebounceTime = 250us - 1024000us -> Supported range (DebounceTime = 250us * 2^n)
384 For values not supported by HW, they will be rounded down to closest supported one
385 <b>Default is 0</b>
386 */
387 UINT32 PowerButtonDebounce;
388 /**
389 Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
390 for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
391 <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
392 And make sure the setting correct, which never less than the following register.
393 - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
394 - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
395 - PWRM_CFG.SLP_A_MIN_ASST_WDTH
396 - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
397 **/
398 UINT8 PchPwrCycDur;
399 /**
400 Specifies the Pcie Pll Spread Spectrum Percentage
401 The value of this policy is in 1/10th percent units.
402 Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
403 A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
404 The default is <b>0xFF: AUTO - No BIOS override</b>.
405 **/
406 UINT8 PciePllSsc;
407 /**
408 Tells BIOS to enable C10 dynamic threshold adjustment mode.
409 BIOS will only attemt to enable it on PCH SKUs which support it.
410 **/
411 UINT8 C10DynamicThresholdAdjustment;
412 UINT8 Rsvd0[1]; ///< Reserved bytes
413 /**
414 <b>(Test)</b>
415 Low Power Mode Enable/Disable config.
416 Configure if respective S0i2/3 sub-states are to be supported
417 by the platform. By default all sub-states are enabled but
418 for test purpose respective states can be disabled.
419 <b>Default is 0xFF</b>
420 **/
421 PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;
422 /*
423 Set true to enable Timed GPIO 0 timer.
424 <b>0: Disable</b>, 1: Enable
425 */
426 UINT32 EnableTimedGpio0 : 1;
427 /*
428 Set true to enable Timed GPIO 1 timer.
429 <b>0: Disable</b>, 1: Enable
430 */
431 UINT32 EnableTimedGpio1 : 1;
432 /*
433 Set true to enable Demoted (Dirty) Warm reset.
434 <b>0: Disable</b>, 1: Enable
435 */
436 UINT32 DirtyWarmResetEnable : 1;
437 UINT32 Rsvdbits2 : 29;
438
439 /**
440 Set true to enable override of Global Reset Event/Trigger masks.
441 Values from GlobalResetTriggerMask and GlobalResetEventMask will
442 be used as override value.
443 <b>0: Disable</b>, 1: Enable
444 **/
445 UINT8 GlobalResetMasksOverride;
446 UINT8 Rsvd1[3]; ///< Reserved bytes
447 /*
448 Mask for enabling Global Reset Trigger prevention
449 */
450 PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;
451 /*
452 Mask for enabling Global Reset Event prevention
453 */
454 PMC_GLOBAL_RESET_MASK GlobalResetEventMask;
455 /**
456 PMC Therm Timer Delay Register (THERM_TIMER_DELAY). Unit in us(microseconds).
457 Adding delay time between CPU thermal trip propagating through PCH and PCH generating a Global Reset
458 <b>Default is 500</b>
459 **/
460 UINT32 ThermTimerDelay : 10;
461 UINT32 SkipVccInConfig : 1;
462 UINT32 Rsvdbits3 : 21;
463 } PCH_PM_CONFIG;
464
465 /**
466 BCLK configuration. Only available on projects with SOC and CPU BCLK supported.
467 **/
468 typedef struct {
469 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
470
471 /**
472 Controls enable status of SOC BCLK.
473 <b>0: HW default</b>, 1: Force enable, 2: Force disable
474 **/
475 UINT8 SocBclkPllOn;
476 /**
477 Controls enable status of CPU BCLK.
478 <b>0: HW default</b>, 1: Force enable, 2: Force disable
479 **/
480 UINT8 CpuBclkPllOn;
481 UINT8 Rsvd[2];
482 } BCLK_CONFIG;
483
484 #pragma pack (pop)
485
486 #endif // _PM_CONFIG_H_
PCH_PM_CONFIG::PchPwrCycDur
UINT8 PchPwrCycDur
Reset Power Cycle Duration could be customized in the unit of second.
Definition: PmConfig.h:398
PCH_PM_CONFIG::C10DynamicThresholdAdjustment
UINT8 C10DynamicThresholdAdjustment
Tells BIOS to enable C10 dynamic threshold adjustment mode.
Definition: PmConfig.h:411
PCH_WAKE_CONFIG::LanWakeFromDeepSx
UINT32 LanWakeFromDeepSx
Determine if enable LAN to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:62
ConfigBlock.h
Header file for Config Block Lib implementation.
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p1En
UINT32 S0i3p1En
LPM4 - S0i3.1 Enable.
Definition: PmConfig.h:130
PCH_PM_CONFIG::PchDeepSxPol
UINT32 PchDeepSxPol
Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxPolDisable.
Definition: PmConfig.h:233
PCH_WAKE_CONFIG
This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL,...
Definition: PmConfig.h:51
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p4En
UINT32 S0i3p4En
LPM7 - S0i3.4 Enable.
Definition: PmConfig.h:143
PCH_WAKE_CONFIG::PcieWakeFromDeepSx
UINT32 PcieWakeFromDeepSx
Determine if enable PCIe to wake from deep Sx. 0: Disable; 1: Enable.
Definition: PmConfig.h:59
BCLK_CONFIG::CpuBclkPllOn
UINT8 CpuBclkPllOn
Controls enable status of CPU BCLK.
Definition: PmConfig.h:480
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p2En
UINT32 S0i2p2En
LPM2 - S0i2.2 Enable.
Definition: PmConfig.h:128
PCH_PM_CONFIG::OsIdleEnable
UINT32 OsIdleEnable
Enable Os Idle Mode.
Definition: PmConfig.h:344
PCH_PM_CONFIG::PsOnEnable
UINT32 PsOnEnable
Decide if PS_ON is to be enabled.
Definition: PmConfig.h:308
PCH_PM_CONFIG::PchSlpS4MinAssert
UINT32 PchSlpS4MinAssert
SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value....
Definition: PmConfig.h:235
PCH_PM_CONFIG::S0ixAutoDemotion
UINT32 S0ixAutoDemotion
Enable/Disable the Low Power Mode Host S0ix Auto-Demotion feature.
Definition: PmConfig.h:364
PCH_PM_CONFIG::DisableNativePowerButton
UINT32 DisableNativePowerButton
Power button native mode disable.
Definition: PmConfig.h:283
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p3En
UINT32 S0i3p3En
LPM5 - S0i3.3 Enable.
Definition: PmConfig.h:137
PCH_PM_CONFIG::SlpStrchSusUp
UINT32 SlpStrchSusUp
This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
Definition: PmConfig.h:243
PMC_GLOBAL_RESET_MASK
Description of Global Reset Trigger/Event Mask register.
Definition: PmConfig.h:152
PCH_PM_CONFIG::LpmS0ixSubStateEnable
PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable
(Test) Low Power Mode Enable/Disable config.
Definition: PmConfig.h:421
PCH_PM_CONFIG::Usb2PhySusPgEnable
UINT32 Usb2PhySusPgEnable
(Test) This policy option enables USB2 PHY SUS Well Power Gating functionality.
Definition: PmConfig.h:339
PCH_PM_CONFIG::PciePllSsc
UINT8 PciePllSsc
Specifies the Pcie Pll Spread Spectrum Percentage The value of this policy is in 1/10th percent units...
Definition: PmConfig.h:406
PCH_PM_CONFIG::PchSlpS3MinAssert
UINT32 PchSlpS3MinAssert
SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value....
Definition: PmConfig.h:234
PCH_PM_CONFIG::SlpLanLowDc
UINT32 SlpLanLowDc
Enable/Disable SLP_LAN# Low on DC Power.
Definition: PmConfig.h:251
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_PM_CONFIG::ThermTimerDelay
UINT32 ThermTimerDelay
PMC Therm Timer Delay Register (THERM_TIMER_DELAY).
Definition: PmConfig.h:460
PCH_PM_CONFIG::WakeConfig
PCH_WAKE_CONFIG WakeConfig
Specify Wake Policy.
Definition: PmConfig.h:232
PCH_PM_CONFIG::WolOvrWkSts
UINT32 WolOvrWkSts
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:285
PCH_SLP_S4_MIN_ASSERT
PCH_SLP_S4_MIN_ASSERT
Definition: PmConfig.h:83
BCLK_CONFIG
BCLK configuration.
Definition: PmConfig.h:468
PCH_PM_CONFIG::MeWakeSts
UINT32 MeWakeSts
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; 1: Enable.
Definition: PmConfig.h:284
PCH_PM_CONFIG::PchSlpAMinAssert
UINT32 PchSlpAMinAssert
SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value....
Definition: PmConfig.h:237
PCH_WAKE_CONFIG::WoWlanDeepSxEnable
UINT32 WoWlanDeepSxEnable
Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register...
Definition: PmConfig.h:61
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p1En
UINT32 S0i2p1En
LPM1 - S0i2.1 Enable.
Definition: PmConfig.h:122
PCH_PM_CONFIG
The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
Definition: PmConfig.h:229
PCH_PM_CONFIG::DisableDsxAcPresentPulldown
UINT32 DisableDsxAcPresentPulldown
When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
Definition: PmConfig.h:276
PCH_PM_CONFIG::GlobalResetMasksOverride
UINT8 GlobalResetMasksOverride
Set true to enable override of Global Reset Event/Trigger masks.
Definition: PmConfig.h:445
PMC_LPM_S0IX_SUB_STATE_EN
Low Power Mode Enable config.
Definition: PmConfig.h:119
PCH_PM_CONFIG::V1p05IsExtFetControlEn
UINT32 V1p05IsExtFetControlEn
Enable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS supply 0: Disable; 1: ...
Definition: PmConfig.h:356
PMC_LPM_S0IX_SUB_STATE_EN::Reserved
UINT32 Reserved
Reserved.
Definition: PmConfig.h:144
PCH_PM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:230
PCH_PM_CONFIG::LatchEventsC10Exit
UINT32 LatchEventsC10Exit
Enable/Disable Latch Events C10 Exit.
Definition: PmConfig.h:371
PchSlpS4PchTime
@ PchSlpS4PchTime
The time defined in PCH EDS Power Sequencing and Reset Signal Timings table.
Definition: PmConfig.h:84
PCH_WAKE_CONFIG::WolEnableOverride
UINT32 WolEnableOverride
Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register...
Definition: PmConfig.h:58
PCH_PM_CONFIG::ModPhySusPgEnable
UINT32 ModPhySusPgEnable
Enable/Disable ModPHY SUS Power Domain Dynamic Gating.
Definition: PmConfig.h:331
BCLK_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PmConfig.h:469
PCH_WAKE_CONFIG::WoWlanEnable
UINT32 WoWlanEnable
Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register....
Definition: PmConfig.h:60
PMC_LPM_S0IX_SUB_STATE_EN::S0i2p0En
UINT32 S0i2p0En
LPM0 - S0i2.0 Enable.
Definition: PmConfig.h:121
PCH_WAKE_CONFIG::PmeB0S5Dis
UINT32 PmeB0S5Dis
Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
Definition: PmConfig.h:57
BCLK_CONFIG::SocBclkPllOn
UINT8 SocBclkPllOn
Controls enable status of SOC BCLK.
Definition: PmConfig.h:475
PCH_PM_CONFIG::DisableEnergyReport
UINT32 DisableEnergyReport
(Test) Disable/Enable PCH to CPU enery report feature.
Definition: PmConfig.h:269
PCH_PM_CONFIG::PmcDbgMsgEn
UINT32 PmcDbgMsgEn
Control whether to enable PMC debug messages to Trace Hub.
Definition: PmConfig.h:323
PCH_PM_CONFIG::PwrBtnOverridePeriod
UINT32 PwrBtnOverridePeriod
PCH power button override period.
Definition: PmConfig.h:257
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p2En
UINT32 S0i3p2En
LPM5 - S0i3.2 Enable.
Definition: PmConfig.h:131
PCH_PM_CONFIG::PchSlpSusMinAssert
UINT32 PchSlpSusMinAssert
SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value....
Definition: PmConfig.h:236
PCH_PM_CONFIG::CpuC10GatePinEnable
UINT32 CpuC10GatePinEnable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails...
Definition: PmConfig.h:315
PCH_PM_CONFIG::V1p05PhyExtFetControlEn
UINT32 V1p05PhyExtFetControlEn
Enable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY 0: Disable; 1: Enable.
Definition: PmConfig.h:350
PMC_LPM_S0IX_SUB_STATE_EN::S0i3p0En
UINT32 S0i3p0En
LPM3 - S0i3.0 Enable.
Definition: PmConfig.h:129
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmcRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PmcRegs.h File Reference

Register names for PCH PMC device. More...

Go to the source code of this file.

Macros

#define | R_PMC_PWRM_TGPIOCTL0 0x1210
Timed GPIO Control 0.
#define | R_PMC_PWRM_TGPIOCTL1 0x1310
Timed GPIO Control 1.
#define | R_PMC_CFG_BAR 0x10
32-bit Base Address Register
#define | B_PMC_CFG_PWRM_BASE_MASK 0xFFFF0000
PWRM must be 64KB alignment to align the source decode.
#define | R_PMC_CFG_ACTL 0x44
In IBL the register has been moved from MMIO to PCIe config space.
#define | B_PMC_CFG_ACTL_PWRM_EN BIT8
PWRM enable.
#define | B_PMC_CFG_ACTL_ACPI_EN BIT7
ACPI eanble.
#define | B_PMC_CFG_ACTL_SCIS (BIT2 | BIT1 | BIT0)
SCI IRQ select.
#define | R_ACPI_IO_PM1_CNT 0x04
Power Management 1 Control.
#define | B_ACPI_IO_PM1_CNT_SLP_EN BIT13
Sleep Enable.
#define | B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)
Sleep Type.
#define | B_ACPI_IO_PM1_CNT_SCI_EN BIT0
SCI Enable.
#define | R_ACPI_IO_PM1_TMR 0x08
Power Management 1 Timer.
#define | B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF
Timer Value.
#define | V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000
The timer is 24 bit overflow.
#define | R_ACPI_IO_THERM_TIMER_DELAY 0x20
Therm Timer Delay Register.
#define | R_ACPI_IO_SMI_EN 0x30
SMI Control and Enable.
#define | B_ACPI_IO_SMI_EN_BIOS_RLS BIT7
BIOS_RLS.
#define | B_ACPI_IO_SMI_EN_EOS BIT1
End of SMI.
#define | R_ACPI_IO_SMI_STS 0x34
SMI Status Register.
#define | R_ACPI_IO_GPE_CTRL 0x40
General Purpose Event Control.
#define | B_ACPI_IO_GPE_CTRL_SWGPE_CTRL BIT17
Software GPE Control.
#define | R_ACPI_IO_DEVTRAP_STS 0x44
Device Trap Status Register.
#define | B_ACPI_IO_DEVTRAP_STS_D12_TRP_STS BIT12
D12 Trap Status.
#define | B_ACPI_IO_DEVTRAP_STS_D9_TRP_STS BIT9
D9 Trap Status.
#define | B_ACPI_IO_DEVTRAP_STS_D8_TRP_STS BIT8
D8 Trap Status.
#define | B_ACPI_IO_DEVTRAP_STS_D7_TRP_STS BIT7
D7 Trap Status.
#define | B_ACPI_IO_DEVTRAP_STS_D6_TRP_STS BIT6
D6 Trap Status.
#define | R_ACPI_IO_OC_WDT_CTL 0x54
Over-Clocking WDT Control.
#define | B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV_STS BIT25
Over-Clocking WDT ICC Survivability Impact.
#define | B_ACPI_IO_OC_WDT_CTL_OC_WDT_NO_ICCSURV_STS BIT24
Over-Clocking WDT Non-ICC Survivability Mode Timeout Status.
#define | B_ACPI_IO_OC_WDT_CTL_OC_WDT_FORCE_ALL BIT15
Over-Clocking WDT Force All.
#define | B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV BIT13
Over-Clocking WDT ICC Survivability Impact.
#define | B_ACPI_IO_OC_WDT_CTL_OC_WDT_CTL_LCK BIT12
OC_WDT_CTL Register Lock.
#define | R_ACPI_IO_GPE0_STS_31_0 0x60
General Purpose Event 0 Status [31:0].
#define | R_ACPI_IO_GPE0_STS_127_96 0x6C
General Purpose Event 0 Status [127:96].
#define | B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17
USB Connection in/after DeepSx Status.
#define | R_ACPI_IO_GPE0_EN_127_96 0x7C
General Purpose Event 0 Enable [127:96].
#define | B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17
USB Connection in/after DeepSx Enable.
#define | R_PMC_PWRM_IPC_CMD 0x00
IPC Command.
#define | N_PMC_PWRM_IPC_CMD_CMD_ID 12
IPC command.cmd.ID.
#define | N_PMC_PWRM_IPC_CMD_SIZE 16
IPC command.size.
#define | N_PMC_PWRM_IPC_CMD_COMMAND 0
IPC command.cmd.Command.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_GEN_COMM 0xA0
IPC command for General PMC Communication.
#define | V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2
IPC subcommand to Read PMC address space using WBUF0.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL 0xA1
IPC commmand to control S0ix policies.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_SNDW_RCOMP 0xA2
IPC commmand to control platform Soundwire buffer RCOMP.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_FIVR 0xA3
IPC commmand to control FIVR Configuration.
#define | V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC 0
IPC subcommand to control RFI Control 0 register logic write.
#define | V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC 1
IPC subcommand to control RFI Control 4 register logic write.
#define | V_PMC_PWRM_IPC_SUBCMD_EMI_CTRL0_LOGIC 2
IPC subcommand to control EMI Control 0 register logic write.
#define | V_PMC_PWRM_IPC_SUBCMD_FFFC_FAULT_STATUS 3
IPC subcommand to control FFFC_FAULT_STATUS register logic read.
#define | V_PMC_PWRM_IPC_SUBCMD_FFFC_RFI_STATUS 4
IPC subcommand to control FFFC_RFI_STATUS register logic read.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_READ 0x00
IPC subcommand to read FIVR Register.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE 0x01
IPC subcommand to write FIVR Register and fuse SRAM/DCCM.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_DFX_PWR_STATE 0xA4
IPC commmand to control DFX Power State.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_CRASHLOG 0xA6
CrashLog Command.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_ME_DISABLE 0xA9
IPC command to disable ME devices.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_PMC_PRV_REG_ACCESS 0xAB
IPC command from proxy access to PMC private registers.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_SSC_STATE 0xAE
IPC command to control SA SSC enable/disable.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_IO_MARGINING_ENABLE 0xAF
IPC command to enable I/O Margin tool support.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISCOVERY 0x01
CrashLog Discovery SubCommand.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISABLE 0x02
Disable CrashLog SubCommand.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ERASE 0x04
Clear CrashLog record SubCommand.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ON_RESET 0x05
Collect on all resets SubCommand.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_RE_ARM 0x06
Re-arm SubCommand to ensure that a trigger command only executed on time per boot.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_PROGRAM_TRIGGER_ENABLES 0x8
Program global reset trigger enable mask.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_READ_TRIGGER_ENABLES 0x9
Read global reset trigger enable mask.
#define | V_PMC_PWRM_IPC_SRC_CLK_CMD 0xA8
IPC to PMC SRCCLK command.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_PROXY 0xAA
Proxy access to SOC registers.
#define | V_PMC_PWRM_IPC_SRC_CLK_PORT_MAPPING_CMD 0xAC
IPC to PMC SRCCLK and port mapping command.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ 0
Read command.
#define | V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI 2
parameter to access NMI control register
#define | V_PMC_PWRM_IPC_CMD_COMMAND_CPU_STRAP 0xB1
IPC command for CPU straps.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_LOCK 0
IPC subcommand to lock CPU straps.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_WRITE 1
IPC subcommand to write CPU straps.
#define | V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS 0xD0
IPC command for Bios Reset Completion Status.
#define | V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_PCI_ENUM BIT0
IPC command for Bios Reset Completion Status Pci Enumeration Done.
#define | V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_MEM_CAL BIT1
IPC command for Bios Reset Completion Status Memory Calibration Done.
#define | R_PMC_PWRM_IPC_STS 0x04
IPC Status.
#define | B_PMC_PWRM_IPC_STS_BUSY BIT0
IPC Status Busy Bit.
#define | B_PMC_PWRM_IPC_STS_ERROR BIT1
IPC Status Error Bit.
#define | R_PMC_PWRM_IPC_WBUF0 0x80
IPC Write Buffer.
#define | R_PMC_PWRM_IPC_WBUF1 0x84
IPC Write Buffer.
#define | R_PMC_PWRM_IPC_WBUF2 0x88
IPC Write Buffer.
#define | R_PMC_PWRM_IPC_WBUF3 0x8C
IPC Write Buffer.
#define | R_PMC_PWRM_IPC_RBUF0 0x90
IPC Read Buffer.
#define | R_PMC_PWRM_IPC_RBUF1 0x94
IPC Read Buffer.
#define | R_PMC_PWRM_IPC_RBUF2 0x98
IPC Read Buffer.
#define | R_PMC_PWRM_IPC_RBUF3 0x9C
IPC Read Buffer.
#define | R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_BUILD 0x30
OEM_CHIPSETINIT_VERSION_1 Build.
#define | R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_HOT_FIX 0x32
OEM_CHIPSETINIT_VERSION_1 HotFix.
#define | R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MINOR 0x34
OEM_CHIPSETINIT_VERSION_2 Minor Version.
#define | R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MAJOR 0x36
OEM_CHIPSETINIT_VERSION_2 Major Version.
#define | R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_BUILD 0x48
INTEL_CHIPSETINIT_VERSION_1 Build.
#define | R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_HOT_FIX 0x4A
INTEL_CHIPSETINIT_VERSION_1 HotFix.
#define | R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MINOR 0x4C
INTEL_CHIPSETINIT_VERSION_2 Minor Version.
#define | R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MAJOR 0x4E
INTEL_CHIPSETINIT_VERSION_2 Major Version.
#define | R_PMC_PWRM_GEN_PMCON_A 0x1020
General PM Configuration A.
#define | B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS BIT30
DC PHY Power Disable.
#define | B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS BIT29
Deep-Sx PHY Power Disable.
#define | B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN BIT28
After G3 PHY Power Enable.
#define | B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN BIT27
Sx PHY Power Enable.
#define | B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24
Global Reset Status.
#define | B_PMC_PWRM_GEN_PMCON_A_DISB BIT23
DRAM Initialization Scratchpad Bit.
#define | B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT22
Allow OPI PLL Shutdown in C0.
#define | B_PMC_PWRM_GEN_PMCON_A_MEM_SR BIT21
Memory Placed in Self-Refresh.
#define | B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT20
Allow SPXB Clock Gating in C0.
#define | B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19
Allow L1.LOW Entry During C0.
#define | B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18
Minimum SLP_S4# Assertion Width Violation Status.
#define | B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT17
Allow L1.LOW Entry with OPI Voltage On.
#define | B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16
SUS Well Power Failure.
#define | B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS BIT15
PME B0 S5 Disable.
#define | B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT13
Allow L1.LOW Entry with CPU BCLK REQ Asserted.
#define | B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9
Host Reset Status.
#define | B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8
ESPI SMI Lock.
#define | B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1)
Period SMI Select.
#define | R_PMC_PWRM_GEN_PMCON_B 0x1024
General PM Configuration B.
#define | B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18
SLP_Sx# Stretching Policy Lock-Down.
#define | B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD BIT13
WOL Enable Override.
#define | B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN BIT10
BIOS PCI Express Enable.
#define | B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9
Power Button Level.
#define | B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4
SMI Lock.
#define | R_PMC_PWRM_CRID 0x1030
Configured Revision ID.
#define | B_PMC_PWRM_CRID_RID_SEL (BIT1 | BIT0)
RID Select(RID_SEL)
#define | B_PMC_PWRM_CRID_CRID_LK BIT31
CRID Lock.
#define | R_PMC_PWRM_ETR3 0x1048
Extended Test Mode Register 3.
#define | B_PMC_PWRM_ETR3_CF9LOCK BIT31
CF9h Lockdown.
#define | B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT BIT30
Latch Events C10 exit.
#define | B_PMC_PWRM_ETR3_CF9GR BIT20
CF9h Global Reset.
#define | B_PMC_PWRM_ETR3_CWORWRE BIT18
CF9h Without Resume Well Reset Enable.
#define | R_PMC_PWRM_SSML 0x104C
SET STRAP MSG LOCK.
#define | B_PMC_PWRM_SSML_SSL BIT0
Set_Strap Lock.
#define | R_PMC_PWRM_SSMC 0x1050
SET STRAP MSG CONTROL.
#define | B_PMC_PWRM_SSMC_SSMS BIT0
Set_Strap Mux Select.
#define | R_PMC_PWRM_SSMD 0x1054
SET STRAP MSG DATA.
#define | R_PMC_PWRM_SSMD_DW2 0x1058
SET STRAP MSG DATA.
#define | R_PMC_PWRM_SSMD_DW3 0x105C
SET STRAP MSG DATA.
#define | R_PMC_PWRM_BIOS_SCRATCHPAD_2 0x1098
Scratchpad For Sharing Data Between BIOS And PMC Firmware.
#define | R_PMC_PWRM_CRID_UIP 0x10B0
Configured Revision ID.
#define | B_PMC_PWRM_CRID_UIP_CRID_UIP BIT0
CRID Update in Progress.
#define | R_PMC_PWRM_MODPHY_PM_CFG1 0x10C0
ModPHY Power Management Configuration Reg 1.
#define | R_PMC_PWRM_MODPHY_PM_CFG2 0x10C4
ModPHY Power Management Configuration Reg 2.
#define | R_PMC_PWRM_MODPHY_PM_CFG3 0x10C8
ModPHY Power Management Configuration Reg 3.
#define | B_PMC_PWRM_MODPHY_PM_CFG3_MLSPDDGE BIT30
ModPHY Lane SUS Power Domain Dynamic Gating Enable.
#define | B_PMC_PWRM_MODPHY_PM_CFG3_MPLSPDDGE BIT1
ModPHY Per-Lane SUS Power Domain Dynamic Gating Enable.
#define | B_PMC_PWRM_MODPHY_PM_CFG3_C10_QUAL_MPHYPG BIT0
C10 qualifier for MPHY power gating.
#define | R_PMC_PWRM_MODPHY_PM_CFG5 0x10D0
ModPHY Power Management Configuration Reg 5.
#define | B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS BIT16
UFS ModPHY SPD RT Request.
#define | B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI BIT15
xDCI ModPHY SPD RT Request
#define | B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI BIT14
xHCI ModPHY SPD RT Request
#define | B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE BIT13
GbE ModPHY SPD RT Request.
#define | B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA BIT12
SATA ModPHY SPD RT Request.
#define | R_PMC_PWRM_MODPHY_PM_CFG6 0x10D4
ModPHY Power Management Configuration Reg 6.
#define | R_PMC_PWRM_CPPM_MPG_POL1A 0x10E0
CPPM ModPHY Gating Policy Reg 1.
#define | B_PMC_PWRM_CPPM_MPG_POL1A_CPPM_MPHY_QUAL BIT30
CPPM Shutdown Qualifier Enable for ModPHY.
#define | B_PMC_PWRM_CPPM_MPG_POL1A_LT_MPHY_SEL BIT29
ASLT/PLT Selection for ModPHY.
#define | B_PMC_PWRM_CPPM_MPG_POL1A_LTR_MPHY_THRESH (0x000001FF)
LTR Threshold for ModPHY, [8:0].
#define | R_PMC_PWRM_WADT_AC 0x1800
Wake Alarm Device Timer: AC.
#define | R_PMC_PWRM_PRSTS 0x1810
Power and Reset Status.
#define | B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS BIT5
Wake On LAN Override Wake Status.
#define | R_PMC_PWRM_PM_CFG 0x1818
Power Management Configuration Reg 1.
#define | B_PMC_PWRM_PM_CFG_ALLOW_24_OSC_SD BIT29
Allow 24MHz Crystal Oscillator Shutdown.
#define | B_PMC_PWRM_PM_CFG_DBG_MODE_LOCK BIT27
Debug Mode Lock.
#define | B_PMC_PWRM_PM_CFG_ALLOW_USB2_CORE_PG BIT25
Allow USB2 PHY Core Power Gating.
#define | B_PMC_PWRM_PM_CFG_ER_LOCK BIT24
Energy Reporting Lock.
#define | B_PMC_PWRM_PM_CFG_PMC_READ_DISABLE BIT22
Disable Reads to PMC.
#define | B_PMC_PWRM_PM_CFG_SSMAW_MASK (BIT19 | BIT18)
SLP_SUS# Min Assertion Width.
#define | V_PMC_PWRM_PM_CFG_SSMAW_4S (BIT19 | BIT18)
4 seconds
#define | V_PMC_PWRM_PM_CFG_SSMAW_1S BIT19
1 second
#define | V_PMC_PWRM_PM_CFG_SSMAW_0_5S BIT18
0.5 second (500ms)
#define | V_PMC_PWRM_PM_CFG_SSMAW_0S 0
0 second
#define | B_PMC_PWRM_PM_CFG_SAMAW_MASK (BIT17 | BIT16)
SLP_A# Min Assertion Width.
#define | V_PMC_PWRM_PM_CFG_SAMAW_2S (BIT17 | BIT16)
2 seconds
#define | V_PMC_PWRM_PM_CFG_SAMAW_98ms BIT17
98ms
#define | V_PMC_PWRM_PM_CFG_SAMAW_4S BIT16
4 seconds
#define | V_PMC_PWRM_PM_CFG_SAMAW_0S 0
0 second
#define | B_PMC_PWRM_PM_CFG_RPCD_MASK (BIT9 | BIT8)
Reset Power Cycle Duration.
#define | V_PMC_PWRM_PM_CFG_RPCD_1S (BIT9 | BIT8)
1-2 seconds
#define | V_PMC_PWRM_PM_CFG_RPCD_2S BIT9
2-3 seconds
#define | V_PMC_PWRM_PM_CFG_RPCD_3S BIT8
3-4 seconds
#define | V_PMC_PWRM_PM_CFG_RPCD_4S 0
4-5 seconds (Default)
#define | B_PMC_PWRM_PM_CFG_COCS BIT5
CPU OC Strap.
#define | B_PMC_PWRM_PM_CFG_ER_EN BIT2
Energy Reporting Enable.
#define | B_PMC_PWRM_PM_CFG_TIMING_TPCH25 (BIT1 | BIT0)
tPCH25 timing
#define | R_PMC_PWRM_S3_PWRGATE_POL 0x1828
S3 Power Gating Policies.
#define | B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS BIT1
S3 Power Gate Enable in DC Mode: SUS Well.
#define | B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS BIT0
S3 Power Gate Enable in AC Mode: SUS Well.
#define | R_PMC_PWRM_S4_PWRGATE_POL 0x182C
S4 Power Gating Policies.
#define | B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS BIT1
S4 Power Gate Enable in DC Mode: SUS Well.
#define | B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS BIT0
S4 Power Gate Enable in AC Mode: SUS Well.
#define | R_PMC_PWRM_S5_PWRGATE_POL 0x1830
S5 Power Gating Policies.
#define | B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS BIT15
S5 Power Gate Enable in DC Mode: SUS Well.
#define | B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS BIT14
S5 Power Gate Enable in AC Mode: SUS Well.
#define | R_PMC_PWRM_DSX_CFG 0x1834
DeepSx Configuration.
#define | B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2
WAKE# Pin DeepSx Enable.
#define | B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1
AC_PRESENT Pin Pulldown in DeepSx Disable.
#define | B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0
LAN_WAKE Pin DeepSx Enable.
#define | R_PMC_PWRM_PM_CFG2 0x183C
Power Management Configuration Reg 2.
#define | B_PMC_PWRM_PM_CFG2_PBOP (BIT31 | BIT30 | BIT29)
Power Button Override Period.
#define | N_PMC_PWRM_PM_CFG2_PBOP 29
Power Button Override Period (PBOP)
#define | B_PMC_PWRM_PM_CFG2_PB_DIS BIT28
Power Button Native Mode Disable.
#define | B_PMC_PWRM_PM_CFG2_EN_DBG_MSG BIT27
Enable Debug Messaging.
#define | B_PMC_PWRM_PM_CFG2_DRAM_RESET_CTL BIT26
DRAM_RESET# Control.
#define | R_PMC_PWRM_EN_SN_SLOW_RING 0x1848
Enable Snoop Request to SLOW_RING.
#define | R_PMC_PWRM_EN_SN_SLOW_RING2 0x184C
Enable Snoop Request to SLOW_RING 2nd Reg.
#define | R_PMC_PWRM_EN_SN_SA 0x1850
Enable Snoop Request to SA.
#define | R_PMC_PWRM_EN_SN_SA2 0x1854
Enable Snoop Request to SA 2nd Reg.
#define | R_PMC_PWRM_EN_SN_SLOW_RING_CF 0x1858
Enable Snoop Request to SLOW_RING_CF.
#define | R_PMC_PWRM_EN_NS_SA 0x1868
Enable Non-Snoop Request to SA.
#define | R_PMC_PWRM_EN_CW_SLOW_RING 0x1880
Enable Clock Wake to SLOW_RING.
#define | R_PMC_PWRM_EN_CW_SLOW_RING2 0x1884
Enable Clock Wake to SLOW_RING 2nd Reg.
#define | R_PMC_PWRM_EN_CW_SA 0x1888
Enable Clock Wake to SA.
#define | R_PMC_PWRM_EN_CW_SA2 0x188C
Enable Clock Wake to SA 2nd Reg.
#define | R_PMC_PWRM_EN_CW_SLOW_RING_CF 0x1898
Enable Clock Wake to SLOW_RING_CF.
#define | R_PMC_PWRM_EN_PA_SLOW_RING 0x18A8
Enable Pegged Active to SLOW_RING.
#define | R_PMC_PWRM_EN_PA_SLOW_RING2 0x18AC
Enable Pegged Active to SLOW_RING 2nd Reg.
#define | B_PMC_PWRM_EN_PA_SLOW_RING2_GBETSN BIT26
GBETSN Pegged Active to SLOW_RING.
#define | R_PMC_PWRM_EN_PA_SA_0 0x18B0
EN_PA_SA - Register 0.
#define | R_PMC_PWRM_EN_PA_SA_02 0x18B4
EN_PA_SA - Register 0.
#define | R_PMC_PWRM_EN_MISC_EVENT 0x18C0
Enable Misc PM_SYNC Events.
#define | R_PMC_PWRM_SLP_S0_RESIDENCY 0x193C
SLP_S0 Residency.
#define | B_PMC_PWRM_PM_SYNC_MISC_CFG_PM_SYNC_LOCK BIT15
PM_SYNC Configuration Lock.
#define | R_PMC_PWRM_PM_SYNC_STATE_HYS 0x18D0
PM_SYNC State Hysteresis.
#define | R_PMC_PWRM_PM_SYNC_MODE 0x18D4
PM_SYNC Pin Mode.
#define | R_PMC_PWRM_PM_CFG3 0x18E0
Power Management Configuration Reg 3.
#define | B_PMC_PWRM_PM_CFG3_SYS_RST_SUP BIT22
Sys Reset# Suppression.
#define | B_PMC_PWRM_PM_CFG3_HOST_WLAN_PP_EN BIT17
Host Wireless LAN Phy Power Enable.
#define | B_PMC_PWRM_PM_CFG3_DSX_WLAN_PP_EN BIT16
Deep-Sx WLAN Phy Power Enable.
#define | B_PMC_PWRM_PM_CFG3_HOST_MISC_CORE_CFG_CPU_VCC_MAP BIT2
Enable CPU Vcc Mapping.
#define | R_PMC_PWRM_PM_CFG4 0x18E8
Power Management Configuration Reg 4.
#define | B_PMC_PWRM_PM_CFG4_U2_PHY_PG_EN BIT30
USB2 PHY SUS Well Power Gating Enable.
#define | B_PMC_PWRM_CFG4_SLPS0_PSON_TMR (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | BIT23)
SLPS0_PSON_TMR.
#define | B_PMC_PWRM_CFG4_PSON_SLPS0_TMR (BIT22 | BIT21 | BIT20 | BIT19 | BIT18)
PSON_SLPS0_TMR.
#define | B_PMC_PWRM_PM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF)
CPU I/O VR Ramp Duration, [8:0].
#define | R_PMC_PWRM_CPU_EPOC 0x18EC
CPU Early Power-on Configuration.
#define | R_PMC_PWRM_ADR_EN 0x18F0
ADR Enable.
#define | B_PMC_PWRM_ADR_EN_ADR_GPIO_SEL (BIT31 | BIT30)
ADR GPIO Selection.
#define | B_PMC_PWRM_ADR_EN_HPR_ADR_EN BIT28
Host Partition Reset ADR Enable.
#define | B_PMC_PWRM_ADR_EN_ADR_PLT_ACK_EN BIT26
ADR Pltaform Acknowledge Enable.
#define | B_PMC_PWRM_ADR_EN_ADR_FEAT_EN BIT0
ADR Feature Enable.
#define | R_PMC_PWRM_ACPI_TMR_CTL 0x18FC
ACPI Timer Control.
#define | R_PMC_PWRM_ADR_GEN_CFG 0x196C
ADR General Configuration Register.
#define | R_PMC_PWRM_ADR_GEN_CFG_V2 0x1908
ADR General Configuration Register Version 2.
#define | B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_SCALE (BIT28|BIT27|BIT26)
ADR Timer Scale.
#define | B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_EN BIT19
ADR Phase 2 Enable.
#define | B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_TOV (BIT18|BIT17|BIT16|BIT15|BIT14|BIT13|BIT12|BIT11)
ADR Timer Base.
#define | B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_SCALE (BIT10|BIT9|BIT8)
ADR Timer Scale (Tick Frequency)
#define | B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_TOV (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0)
ADR Timer Base.
#define | R_PMC_PWRM_GBL2HOST_EN 0x190C
Global to Host Reset Enable.
#define | B_PMC_PWRM_GBL2HOST_EN_HOST_RESET_TIMEOUT BIT0
Global to Host for Host Partition Reset Timeout.
#define | R_PMC_PWRM_GPIO_CFG 0x1920
GPIO Configuration.
#define | B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)
GPIO Group to GPE_DW2 assignment encoding.
#define | B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4)
GPIO Group to GPE_DW1 assignment encoding.
#define | B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0)
GPIO Group to GPE_DW0 assignment encoding.
#define | R_PMC_PWRM_GBLRST_CAUSE0 0x1924
Global Reset Causes 0.
#define | R_PMC_PWRM_PMLDOCTRL 0x1A00
PMC LDO Control Register.
#define | R_PMC_PWRM_GBLRST_CAUSE1 0X1928
Global Reset Causes 1.
#define | R_PMC_PWRM_HPR_CAUSE0 0x192C
Host Partition Reset Causes.
#define | B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15
Global Reset Converted to Host Reset.
#define | R_PMC_PWRM_ADR_CTRL_STS 0x1960
ADR Control and Status.
#define | B_PMC_PWRM_ADR_CTRL_STS_ADR_RST_STS BIT0
ADR Reset Status.
#define | R_PMC_PWRM_ADR_GBLRST_EN_0 0x191C
ADR Global Reset Enable 0.
#define | R_PMC_PWRM_S0IX_LDO_OFF_COUNT 0x1A04
PMC LDO S0ix Shutdown Count Register.
#define | R_PMC_PWRM_S0_LDO_OFF_COUNT 0x1A08
PMC LDO S0 Shutdown Count Register.
#define | R_PMC_PWRM_LTR_IGN 0x1B0C
LTR Ignore.
#define | R_PMC_PWRM_OBFF_CFG 0x1B14
OBFF Configuration.
#define | R_PMC_PWRM_CPPMVRIC 0x1B1C
CPPM VR Idle Control 1.
#define | R_PMC_PWRM_CPPM_MISC_CFG 0x1B20
CPPM Miscellaneous Configuration.
#define | R_PMC_PWRM_CPPM_CG_POL1A 0x1B24
CPPM Clock Gating Policy Reg 1.
#define | R_PMC_PWRM_CPPM_CG_POL1B 0x1B28
CPPM Clock Gating Policy Reg 1.
#define | B_PMC_PWRM_CPPM_FIVR_POL1B_TNTE_FIVR_VOLT_PRE_WAKE 0x1FFFF
TNTE PreWake for FIVR Voltage.
#define | R_PMC_PWRM_CPPM_CG_POL2A 0x1B40
CPPM Clock Gating Policy Reg 2.
#define | R_PMC_PWRM_CPPM_CG_POL3A 0x1BA8
CPPM Clock Gating Policy Reg 3.
#define | B_PMC_PWRM_CPPM_CG_POL1A_LT_G1_SEL BIT29
ASLT/PLT Selection for Clock Source Group x.
#define | B_PMC_PWRM_CPPM_CG_POL1A_CPPM_G1_QUAL BIT30
CPPM Shutdown Qualifier Enable for Clock Source Group x.
#define | B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH (0x000001FF)
LTR Threshold for Clock Source Group X, [8:0].
#define | B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH_V2 (0x0000FFFF)
LTR Threshold for Clock Source Group X, [15:0].
#define | R_PMC_PWRM_CPPMFALIGNCTL_1 0x1BD0
CPPM Forced Alignment Control 1.
#define | R_PMC_PWRM_ACTL 0x1BD8
ACPI Control.
#define | B_PMC_PWRM_ACPI_SCIS (BIT2 | BIT1 | BIT0)
SCI IRQ select.
#define | R_PMC_PWRM_BM_CX_CNF 0x1BDC
in CNL this is PWRM register
#define | R_PMC_PWRM_CS_SD_CTL1 0x1BE8
Clock Source Shutdown Control Reg 1.
#define | B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20)
Clock Source 5 Control Configuration.
#define | B_PMC_PWRM_CS_SD_CTL1_CS_XTAL_CTL_CFG (BIT18 | BIT17 | BIT16)
Clock Source XTAL Control Configuration.
#define | B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0)
Clock Source 1 Control Configuration.
#define | R_PMC_PWRM_CS_SD_CTL2 0x1BEC
Clock Source Shutdown Control Reg 1.
#define | R_PMC_PWRM_LPM_ADEM_HOST_CTRL 0x1C20
Low Power Mode Auto-Demotion Host Control.
#define | B_PMC_PWRM_LPM_ADEM_HOST_CTRL_EN BIT0
Low Power Mode Auto-Demotion Host Enable.
#define | R_PMC_PWRM_LPM_EN 0x1C78
Low Power Mode Enable.
#define | R_PMC_PWRM_LPM_EN_V2 0x179C
Low Power Mode Enable- version 2.
#define | R_PMC_PWRM_LPM_EN_V3 0x1798
Low Power Mode Enable- version 3.
#define | R_PMC_PWRM_LPM_PRI 0x1C7C
Low Power Mode Priority.
#define | R_PMC_PWRM_LPM_PRI_V4 0x1C9C
Low Power Mode Priority- version 4.
#define | R_PMC_PWRM_CS_SD_OVR_EN 0x1F54
Clock Source Override Enable Control Reg.
#define | B_PMC_PWRM_CS_ACRO_CRO_OVR_EN BIT0
Disable ACRO from LTR comparisons.
#define | R_PMC_PWRM_ST_PG_FDIS_PMC_0_V2 0x1E20
Static Function Disable Control Register 0- veriosn 2.
#define | R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20
Static PG Related Function Disable Register 1.
#define | R_PMC_PWRM_ST_PG_FDIS_PMC_1_V2 0x1E24
Static PG Related Function Disable Register 1- version 2.
#define | B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31
Static Function Disable Lock (ST_FDIS_LK)
#define | R_PMC_PWRM_ST_PG_FDIS_PMC_2 0x1E24
Static Function Disable Control Register 2.
#define | R_PMC_PWRM_ST_PG_FDIS_PMC_2_V2 0x1E28
Static Function Disable Control Register 2- veriosn 2.
#define | R_PMC_PWRM_BCLK_CFG 0x1F60
BCLK PLLs Configuration.
#define | R_PMC_PWRM_LPM0_REQ_0 0x1000
Low Power Mode 0 Requirements Reg 0.
#define | R_PMC_PWRM_LPM7_REQ_5 0x1164
Low Power Mode 7 Requirements Reg 5.
#define | V_PMC_PWRM_IPC_CMD_COMMAND_PMIC 0xC0
IPC commmand to configure PMIC.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC1_I2C 0x00
SubCommand to read PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC1_I2C 0x01
SubCommand to write PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC2_I2C 0x03
SubCommand to read PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC2_I2C 0x04
SubCommand to read PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC3_I2C 0x06
SubCommand to read PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC3_I2C 0x07
SubCommand to read PMIC I2C.
#define | V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_LOCK_ENABLE_PMIC_I2C 0xF
SubCommand to PMC write lock enable.
#define | R_PMC_SOFT_STRAP_7 0x091C
This register reflects the value pulled from SMIP or SoftStrap.
#define | B_PMC_DEF_CPU_BCLK_CFG (BIT15 | BIT14)
This value is used to tell the CPU how it should configure the CPU BCLK PLL.
#define | N_PMC_DEF_CPU_BCLK_CFG 14
This value is used to shift B_PMC_DEF_CPU_BCLK_CFG.
#define | V_PMC_DEF_CPU_BCLK_CFG_INTEGRATED (0x00008000)
BIT[15:14] = {10b}, BCLK source is integrated. BIT[15:14] = {00b}, BCLK source is external.

Detailed Description

Register names for PCH PMC device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
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Specification

Definition in file PmcRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PmcRegs.h Source File

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  • Register
PmcRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH PMC device
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification
63 **/
64 #ifndef _PCH_REGS_PMC_H_
65 #define _PCH_REGS_PMC_H_
66
67 #define R_PMC_PWRM_TGPIOCTL0 0x1210 ///< Timed GPIO Control 0
68 #define R_PMC_PWRM_TGPIOCTL1 0x1310 ///< Timed GPIO Control 1
69
70 //
71 // PCIe config space registers
72 //
73 #define R_PMC_CFG_BAR 0x10 ///< 32-bit Base Address Register
74 #define B_PMC_CFG_PWRM_BASE_MASK 0xFFFF0000 ///< PWRM must be 64KB alignment to align the source decode.
75
76 #define R_PMC_CFG_ACTL 0x44 ///< In IBL the register has been moved from MMIO to PCIe config space
77 #define B_PMC_CFG_ACTL_PWRM_EN BIT8 ///< PWRM enable
78 #define B_PMC_CFG_ACTL_ACPI_EN BIT7 ///< ACPI eanble
79 #define B_PMC_CFG_ACTL_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select
80
81 //
82 // ACPI and legacy I/O register offsets from ACPIBASE
83 //
84 #define R_ACPI_IO_PM1_STS 0x00
85 #define S_ACPI_IO_PM1_STS 2
86 #define B_ACPI_IO_PM1_STS_WAK BIT15
87 #define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14
88 #define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
89 #define B_ACPI_IO_PM1_STS_RTC BIT10
90 #define B_ACPI_IO_PM1_STS_PWRBTN BIT8
91 #define B_ACPI_IO_PM1_STS_GBL BIT5
92 #define B_ACPI_IO_PM1_STS_BM BIT4
93 #define B_ACPI_IO_PM1_STS_TMROF BIT0
94 #define N_ACPI_IO_PM1_STS_RTC 10
95 #define N_ACPI_IO_PM1_STS_PWRBTN 8
96 #define N_ACPI_IO_PM1_STS_TMROF 0
97
98 #define R_ACPI_IO_PM1_EN 0x02
99 #define S_ACPI_IO_PM1_EN 2
100 #define B_ACPI_IO_PM1_EN_RTC BIT10
101 #define B_ACPI_IO_PM1_EN_PWRBTN BIT8
102 #define N_ACPI_IO_PM1_EN_RTC 10
103 #define N_ACPI_IO_PM1_EN_PWRBTN 8
104 #define N_ACPI_IO_PM1_EN_TMROF 0
105
106 #define R_ACPI_IO_PM1_CNT 0x04 ///< Power Management 1 Control
107 #define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 ///< Sleep Enable
108 #define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type
109 #define V_ACPI_IO_PM1_CNT_S0 0
110 #define V_ACPI_IO_PM1_CNT_S1 BIT10
111 #define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
112 #define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
113 #define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
114 #define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 ///< SCI Enable
115
116 #define R_ACPI_IO_PM1_TMR 0x08 ///< Power Management 1 Timer
117 #define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF ///< Timer Value
118 #define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
119
120 #define R_ACPI_IO_THERM_TIMER_DELAY 0x20 ///< Therm Timer Delay Register
121
122 #define R_ACPI_IO_SMI_EN 0x30 ///< SMI Control and Enable
123 #define S_ACPI_IO_SMI_EN 4
124 #define B_ACPI_IO_SMI_EN_ESPI_SMI BIT28
125 #define B_ACPI_IO_SMI_EN_INTEL_USB2 BIT18
126 #define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
127 #define B_ACPI_IO_SMI_EN_PERIODIC BIT14
128 #define B_ACPI_IO_SMI_EN_TCO BIT13
129 #define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7 ///< BIOS_RLS
130 #define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
131 #define B_ACPI_IO_SMI_EN_APMC BIT5
132 #define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4
133 #define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
134 #define B_ACPI_IO_SMI_EN_BIOS BIT2
135 #define B_ACPI_IO_SMI_EN_EOS BIT1 ///< End of SMI
136 #define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
137 #define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
138 #define N_ACPI_IO_SMI_EN_ESPI 28
139 #define N_ACPI_IO_SMI_EN_PERIODIC 14
140 #define N_ACPI_IO_SMI_EN_TCO 13
141 #define N_ACPI_IO_SMI_EN_MCSMI 11
142 #define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
143 #define N_ACPI_IO_SMI_EN_APMC 5
144 #define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
145 #define N_ACPI_IO_SMI_EN_LEGACY_USB 3
146
147 #define R_ACPI_IO_SMI_STS 0x34 ///< SMI Status Register
148 #define S_ACPI_IO_SMI_STS 4
149 #define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
150 #define B_ACPI_IO_SMI_STS_SMBUS BIT16
151 #define B_ACPI_IO_SMI_STS_PERIODIC BIT14
152 #define B_ACPI_IO_SMI_STS_TCO BIT13
153 #define B_ACPI_IO_SMI_STS_MCSMI BIT11
154 #define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6
155 #define B_ACPI_IO_SMI_STS_APM BIT5
156 #define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4
157 #define B_ACPI_IO_SMI_STS_BIOS BIT2
158 #define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
159 #define N_ACPI_IO_SMI_STS_ESPI 28
160 #define N_ACPI_IO_SMI_STS_SPI 26
161 #define N_ACPI_IO_SMI_STS_MONITOR 21
162 #define N_ACPI_IO_SMI_STS_PCI_EXP 20
163 #define N_ACPI_IO_SMI_STS_SMBUS 16
164 #define N_ACPI_IO_SMI_STS_SERIRQ 15
165 #define N_ACPI_IO_SMI_STS_PERIODIC 14
166 #define N_ACPI_IO_SMI_STS_TCO 13
167 #define N_ACPI_IO_SMI_STS_MCSMI 11
168 #define N_ACPI_IO_SMI_STS_GPIO_SMI 10
169 #define N_ACPI_IO_SMI_STS_GPE0 9
170 #define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
171 #define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
172 #define N_ACPI_IO_SMI_STS_APM 5
173 #define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
174 #define N_ACPI_IO_SMI_STS_LEGACY_USB 3
175
176 #define R_ACPI_IO_GPE_CTRL 0x40 ///< General Purpose Event Control
177 #define B_ACPI_IO_GPE_CTRL_SWGPE_CTRL BIT17 ///< Software GPE Control
178
179 #define R_ACPI_IO_DEVTRAP_STS 0x44 ///< Device Trap Status Register
180 #define B_ACPI_IO_DEVTRAP_STS_D12_TRP_STS BIT12 ///< D12 Trap Status
181 #define B_ACPI_IO_DEVTRAP_STS_D9_TRP_STS BIT9 ///< D9 Trap Status
182 #define B_ACPI_IO_DEVTRAP_STS_D8_TRP_STS BIT8 ///< D8 Trap Status
183 #define B_ACPI_IO_DEVTRAP_STS_D7_TRP_STS BIT7 ///< D7 Trap Status
184 #define B_ACPI_IO_DEVTRAP_STS_D6_TRP_STS BIT6 ///< D6 Trap Status
185
186 #define R_ACPI_IO_OC_WDT_CTL 0x54 ///< Over-Clocking WDT Control
187 #define B_ACPI_IO_OC_WDT_CTL_RLD BIT31
188 #define B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV_STS BIT25 ///< Over-Clocking WDT ICC Survivability Impact
189 #define B_ACPI_IO_OC_WDT_CTL_OC_WDT_NO_ICCSURV_STS BIT24 ///< Over-Clocking WDT Non-ICC Survivability Mode Timeout Status
190 #define B_ACPI_IO_OC_WDT_CTL_FAILURE_STS BIT23
191 #define B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS BIT22
192 #define B_ACPI_IO_OC_WDT_CTL_ALLOW_UNXP_RESET_STS BIT21
193 #define B_ACPI_IO_OC_WDT_CTL_OC_WDT_FORCE_ALL BIT15 ///< Over-Clocking WDT Force All
194 #define B_ACPI_IO_OC_WDT_CTL_EN BIT14
195 #define B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV BIT13 ///< Over-Clocking WDT ICC Survivability Impact
196 #define B_ACPI_IO_OC_WDT_CTL_OC_WDT_CTL_LCK BIT12 ///< OC_WDT_CTL Register Lock
197 #define B_ACPI_IO_OC_WDT_CTL_TOV_MASK 0x3FF
198 #define B_ACPI_IO_OC_WDT_CTL_AFTER_POST 0x3F0000
199 #define V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE 1
200 #define V_ACPI_IO_OC_WDT_CTL_STATUS_OK 0
201
202 #define R_ACPI_IO_GPE0_STS_31_0 0x60 ///< General Purpose Event 0 Status [31:0]
203 #define R_ACPI_IO_GPE0_STS_127_96 0x6C ///< General Purpose Event 0 Status [127:96]
204 #define S_ACPI_IO_GPE0_STS_127_96 4
205 #define B_ACPI_IO_GPE0_STS_127_96_CPU_WAKE_EN BIT19
206 #define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
207 #define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17 ///< USB Connection in/after DeepSx Status
208 #define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16
209 #define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15
210 #define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13
211 #define B_ACPI_IO_GPE0_STS_127_96_PME BIT11
212 #define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10
213 #define B_ACPI_IO_GPE0_STS_127_96_PCI_EXP BIT9
214 #define B_ACPI_IO_GPE0_STS_127_96_RI BIT8
215 #define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7
216 #define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2
217 #define B_ACPI_IO_GPE0_STS_127_96_HOT_PLUG BIT1
218 #define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
219 #define N_ACPI_IO_GPE0_STS_127_96_PME 11
220
221 #define R_ACPI_IO_GPE0_EN_127_96 0x7C ///< General Purpose Event 0 Enable [127:96]
222 #define S_ACPI_IO_GPE0_EN_127_96 4
223 #define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
224 #define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17 ///< USB Connection in/after DeepSx Enable
225 #define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16
226 #define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13
227 #define B_ACPI_IO_GPE0_EN_127_96_PME BIT11
228 #define B_ACPI_IO_GPE0_EN_127_96_PCI_EXP BIT9
229 #define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
230 #define N_ACPI_IO_GPE0_EN_127_96_PME 11
231 #define N_ACPI_IO_GPE0_EN_127_96_BATLOW 10
232 #define N_ACPI_IO_GPE0_EN_127_96_PCI_EXP 9
233 #define N_ACPI_IO_GPE0_EN_127_96_RI 8
234 #define N_ACPI_IO_GPE0_EN_127_96_TC0SCI 6
235 #define N_ACPI_IO_GPE0_EN_127_96_SWGPE 2
236 #define N_ACPI_IO_GPE0_EN_127_96_HOT_PLUG 1
237
238 //
239 // PWRM Registers for IPC interface
240 //
241 #define R_PMC_PWRM_IPC_CMD 0x00 ///< IPC Command
242 #define N_PMC_PWRM_IPC_CMD_CMD_ID 12 ///< IPC command.cmd.ID
243 #define N_PMC_PWRM_IPC_CMD_SIZE 16 ///< IPC command.size
244 #define N_PMC_PWRM_IPC_CMD_COMMAND 0 ///< IPC command.cmd.Command
245 #define V_PMC_PWRM_IPC_CMD_COMMAND_GEN_COMM 0xA0 ///< IPC command for General PMC Communication
246 #define V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ 2 ///< IPC subcommand to Read PMC address space using WBUF0
247 #define V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL 0xA1 ///< IPC commmand to control S0ix policies
248 #define V_PMC_PWRM_IPC_CMD_COMMAND_SNDW_RCOMP 0xA2 ///< IPC commmand to control platform Soundwire buffer RCOMP
249 #define V_PMC_PWRM_IPC_CMD_COMMAND_FIVR 0xA3 ///< IPC commmand to control FIVR Configuration
250 #define V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC 0 ///< IPC subcommand to control RFI Control 0 register logic write
251 #define V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC 1 ///< IPC subcommand to control RFI Control 4 register logic write
252 #define V_PMC_PWRM_IPC_SUBCMD_EMI_CTRL0_LOGIC 2 ///< IPC subcommand to control EMI Control 0 register logic write
253 #define V_PMC_PWRM_IPC_SUBCMD_FFFC_FAULT_STATUS 3 ///< IPC subcommand to control FFFC_FAULT_STATUS register logic read
254 #define V_PMC_PWRM_IPC_SUBCMD_FFFC_RFI_STATUS 4 ///< IPC subcommand to control FFFC_RFI_STATUS register logic read
255 #define V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_READ 0x00 ///< IPC subcommand to read FIVR Register
256 #define V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE 0x01 ///< IPC subcommand to write FIVR Register and fuse SRAM/DCCM
257 #define V_PMC_PWRM_IPC_CMD_COMMAND_DFX_PWR_STATE 0xA4 ///< IPC commmand to control DFX Power State
258 #define V_PMC_PWRM_IPC_CMD_COMMAND_CRASHLOG 0xA6 ///< CrashLog Command
259 #define V_PMC_PWRM_IPC_CMD_COMMAND_ME_DISABLE 0xA9 ///< IPC command to disable ME devices
260 #define V_PMC_PWRM_IPC_CMD_COMMAND_PMC_PRV_REG_ACCESS 0xAB ///< IPC command from proxy access to PMC private registers
261 #define V_PMC_PWRM_ID_GBLRST_TRIG_MASK0 0x0
262 #define V_PMC_PWRM_ID_GBLRST_EVENT_MASK0 0x1
263 #define V_PMC_PWRM_ID_GBLRST_MAX 0x2
264 #define V_PMC_PWRM_IPC_CMD_COMMAND_SSC_STATE 0xAE ///< IPC command to control SA SSC enable/disable
265 #define V_PMC_PWRM_IPC_CMD_COMMAND_IO_MARGINING_ENABLE 0xAF ///< IPC command to enable I/O Margin tool support
266 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISCOVERY 0x01 ///< CrashLog Discovery SubCommand
267 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISABLE 0x02 ///< Disable CrashLog SubCommand
268 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ERASE 0x04 ///< Clear CrashLog record SubCommand
269 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ON_RESET 0x05 ///< Collect on all resets SubCommand
270 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_RE_ARM 0x06 ///< Re-arm SubCommand to ensure that a trigger command only executed on time per boot
271 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_PROGRAM_TRIGGER_ENABLES 0x8 ///< Program global reset trigger enable mask
272 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_READ_TRIGGER_ENABLES 0x9 ///< Read global reset trigger enable mask
273 #define V_PMC_PWRM_IPC_SRC_CLK_CMD 0xA8 ///< IPC to PMC SRCCLK command
274 #define V_PMC_PWRM_IPC_CMD_COMMAND_PROXY 0xAA ///< Proxy access to SOC registers
275 #define V_PMC_PWRM_IPC_SRC_CLK_PORT_MAPPING_CMD 0xAC ///< IPC to PMC SRCCLK and port mapping command
276 #define V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ 0 ///< Read command
277 #define V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI 2 ///< parameter to access NMI control register
278 #define V_PMC_PWRM_IPC_CMD_WBUF0_SET_STRAP_MSG_DW1 0xAA4
279 #define V_PMC_PWRM_IPC_CMD_WBUF0_SET_STRAP_MSG_DW2 0xAA8
280 #define V_PMC_PWRM_IPC_CMD_COMMAND_CPU_STRAP 0xB1 ///< IPC command for CPU straps
281 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_LOCK 0 ///< IPC subcommand to lock CPU straps
282 #define V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_WRITE 1 ///< IPC subcommand to write CPU straps
283 #define V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS 0xD0 ///< IPC command for Bios Reset Completion Status
284 #define V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_PCI_ENUM BIT0 ///< IPC command for Bios Reset Completion Status Pci Enumeration Done
285 #define V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_MEM_CAL BIT1 ///< IPC command for Bios Reset Completion Status Memory Calibration Done
286 #define R_PMC_PWRM_IPC_STS 0x04 ///< IPC Status
287 #define B_PMC_PWRM_IPC_STS_BUSY BIT0 ///< IPC Status Busy Bit
288 #define B_PMC_PWRM_IPC_STS_ERROR BIT1 ///< IPC Status Error Bit
289 #define R_PMC_PWRM_IPC_WBUF0 0x80 ///< IPC Write Buffer
290 #define R_PMC_PWRM_IPC_WBUF1 0x84 ///< IPC Write Buffer
291 #define R_PMC_PWRM_IPC_WBUF2 0x88 ///< IPC Write Buffer
292 #define R_PMC_PWRM_IPC_WBUF3 0x8C ///< IPC Write Buffer
293 #define R_PMC_PWRM_IPC_RBUF0 0x90 ///< IPC Read Buffer
294 #define R_PMC_PWRM_IPC_RBUF1 0x94 ///< IPC Read Buffer
295 #define R_PMC_PWRM_IPC_RBUF2 0x98 ///< IPC Read Buffer
296 #define R_PMC_PWRM_IPC_RBUF3 0x9C ///< IPC Read Buffer
297
298 //
299 // PMC SSRAM Registers
300 //
301 #define R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_BUILD 0x30 ///< OEM_CHIPSETINIT_VERSION_1 Build
302 #define R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_HOT_FIX 0x32 ///< OEM_CHIPSETINIT_VERSION_1 HotFix
303 #define R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MINOR 0x34 ///< OEM_CHIPSETINIT_VERSION_2 Minor Version
304 #define R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MAJOR 0x36 ///< OEM_CHIPSETINIT_VERSION_2 Major Version
305 #define R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_BUILD 0x48 ///< INTEL_CHIPSETINIT_VERSION_1 Build
306 #define R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_HOT_FIX 0x4A ///< INTEL_CHIPSETINIT_VERSION_1 HotFix
307 #define R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MINOR 0x4C ///< INTEL_CHIPSETINIT_VERSION_2 Minor Version
308 #define R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MAJOR 0x4E ///< INTEL_CHIPSETINIT_VERSION_2 Major Version
309
310 //
311 // PWRM Registers
312 //
313 #define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< General PM Configuration A
314 #define B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS BIT30 ///< DC PHY Power Disable
315 #define B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS BIT29 ///< Deep-Sx PHY Power Disable
316 #define B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN BIT28 ///< After G3 PHY Power Enable
317 #define B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN BIT27 ///< Sx PHY Power Enable
318 #define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24 ///< Global Reset Status
319 #define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23 ///< DRAM Initialization Scratchpad Bit
320 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT22 ///< Allow OPI PLL Shutdown in C0
321 #define B_PMC_PWRM_GEN_PMCON_A_MEM_SR BIT21 ///< Memory Placed in Self-Refresh
322 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT20 ///< Allow SPXB Clock Gating in C0
323 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19 ///< Allow L1.LOW Entry During C0
324 #define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18 ///< Minimum SLP_S4# Assertion Width Violation Status
325 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT17 ///< Allow L1.LOW Entry with OPI Voltage On
326 #define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16 ///< SUS Well Power Failure
327 #define B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS BIT15 ///< PME B0 S5 Disable
328 #define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14
329 #define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT13 ///< Allow L1.LOW Entry with CPU BCLK REQ Asserted
330 #define B_PMC_PWRM_GEN_PMCON_A_DISABLE_SX_STRETCH BIT12
331 #define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9 ///< Host Reset Status
332 #define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 ///< ESPI SMI Lock
333 #define B_PMC_PWRM_GEN_PMCON_A_SLP_S4_ASE BIT3
334 #define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0
335 #define B_PMC_PWRM_GEN_PMCON_A_SLP_S3_MAW 0xC00
336 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S3_MAW_60US 0x000
337 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S3_MAW_1MS 0x400
338 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S3_MAW_50MS 0x800
339 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S3_MAW_2S 0xC00
340 #define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
341 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
342 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
343 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
344 #define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
345 #define B_PMC_PWRM_GEN_PMCON_A_SLP_S4_MAW 0x30
346 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S4_MAW_1S 0x30
347 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S4_MAW_2S 0x20
348 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S4_MAW_3S 0x10
349 #define V_PMC_PWRM_GEN_PMCON_A_SLP_S4_MAW_4S 0x00
350 #define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) ///< Period SMI Select
351 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
352 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
353 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
354 #define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
355
356 #define R_PMC_PWRM_GEN_PMCON_B 0x1024 ///< General PM Configuration B
357 #define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 ///< SLP_Sx# Stretching Policy Lock-Down
358 #define B_PMC_PWRM_GEN_PMCON_B_FIVR_LOCK BIT17
359 #define B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD BIT13 ///< WOL Enable Override
360 #define B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN BIT10 ///< BIOS PCI Express Enable
361 #define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9 ///< Power Button Level
362 #define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4 ///< SMI Lock
363 #define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2
364
365 #define R_PMC_PWRM_CRID 0x1030 ///< Configured Revision ID
366 #define B_PMC_PWRM_CRID_RID_SEL (BIT1 | BIT0) ///< RID Select(RID_SEL)
367 #define V_PMC_PWRM_CRID_RID_SEL_REVISIONID 0
368 #define V_PMC_PWRM_CRID_RID_SEL_CRID0 1
369 #define B_PMC_PWRM_CRID_CRID_LK BIT31 ///< CRID Lock
370
371 #define R_PMC_PWRM_ETR3 0x1048 ///< Extended Test Mode Register 3
372 #define B_PMC_PWRM_ETR3_CF9LOCK BIT31 ///< CF9h Lockdown
373 #define B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT BIT30 ///< Latch Events C10 exit
374 #define B_PMC_PWRM_ETR3_CF9GR BIT20 ///< CF9h Global Reset
375 #define B_PMC_PWRM_ETR3_CWORWRE BIT18 ///< CF9h Without Resume Well Reset Enable
376 #define B_PMC_PWRM_THROT_1_VR_ALERT BIT0
377
378 #define R_PMC_PWRM_SSML 0x104C ///< SET STRAP MSG LOCK
379 #define B_PMC_PWRM_SSML_SSL BIT0 ///< Set_Strap Lock
380 #define R_PMC_PWRM_SSMC 0x1050 ///< SET STRAP MSG CONTROL
381 #define B_PMC_PWRM_SSMC_SSMS BIT0 ///< Set_Strap Mux Select
382 #define R_PMC_PWRM_SSMD 0x1054 ///< SET STRAP MSG DATA
383 #define R_PMC_PWRM_SSMD_DW2 0x1058 ///< SET STRAP MSG DATA
384 #define R_PMC_PWRM_SSMD_DW3 0x105C ///< SET STRAP MSG DATA
385
386 #define R_PMC_PWRM_BIOS_SCRATCHPAD_2 0x1098 ///< Scratchpad For Sharing Data Between BIOS And PMC Firmware
387
388 #define R_PMC_PWRM_CRID_UIP 0x10B0 ///< Configured Revision ID
389 #define B_PMC_PWRM_CRID_UIP_CRID_UIP BIT0 ///< CRID Update in Progress
390
391 #define R_PMC_PWRM_MODPHY_PM_CFG1 0x10C0 ///< ModPHY Power Management Configuration Reg 1
392 #define R_PMC_PWRM_MODPHY_PM_CFG2 0x10C4 ///< ModPHY Power Management Configuration Reg 2
393
394 #define R_PMC_PWRM_MODPHY_PM_CFG3 0x10C8 ///< ModPHY Power Management Configuration Reg 3
395 #define B_PMC_PWRM_MODPHY_PM_CFG3_MLSPDDGE BIT30 ///< ModPHY Lane SUS Power Domain Dynamic Gating Enable
396 #define B_PMC_PWRM_MODPHY_PM_CFG3_MPLSPDDGE BIT1 ///< ModPHY Per-Lane SUS Power Domain Dynamic Gating Enable
397 #define B_PMC_PWRM_MODPHY_PM_CFG3_C10_QUAL_MPHYPG BIT0 ///< C10 qualifier for MPHY power gating
398
399 #define R_PMC_PWRM_MODPHY_PM_CFG5 0x10D0 ///< ModPHY Power Management Configuration Reg 5
400 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS2 BIT26
401 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D0 BIT17
402 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS BIT16 ///< UFS ModPHY SPD RT Request
403 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI BIT15 ///< xDCI ModPHY SPD RT Request
404 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI BIT14 ///< xHCI ModPHY SPD RT Request
405 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE BIT13 ///< GbE ModPHY SPD RT Request
406 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA BIT12 ///< SATA ModPHY SPD RT Request
407 #define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A0 BIT0
408 #define R_PMC_PWRM_MODPHY_PM_CFG6 0x10D4 ///< ModPHY Power Management Configuration Reg 6
409
410 #define R_PMC_PWRM_CPPM_MPG_POL1A 0x10E0 ///< CPPM ModPHY Gating Policy Reg 1
411 #define B_PMC_PWRM_CPPM_MPG_POL1A_CPPM_MPHY_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for ModPHY
412 #define B_PMC_PWRM_CPPM_MPG_POL1A_LT_MPHY_SEL BIT29 ///< ASLT/PLT Selection for ModPHY
413 #define B_PMC_PWRM_CPPM_MPG_POL1A_LTR_MPHY_THRESH (0x000001FF) ///< LTR Threshold for ModPHY, [8:0]
414
415 #define R_PMC_PWRM_EXT_V1P05_VR_CONFIG 0x11C0
416 #define R_PMC_PWRM_VCCIN_AUX_CFG1 0x11D0
417 #define R_PMC_PWRM_VCCIN_AUX_CFG2 0x11D4
418
419 #define R_PMC_PWRM_WINIDLE_BIOS_ENABLE 0x1400
420 #define B_PMC_PWRM_WINIDLE_BIOS_ENABLE_WI_LOCK BIT31
421 #define B_PMC_PWRM_WINIDLE_BIOS_ENABLE_WI_ENABLE BIT0
422
423 #define R_PMC_PWRM_WADT_AC 0x1800 ///< Wake Alarm Device Timer: AC
424 #define R_PMC_PWRM_PRSTS 0x1810 ///< Power and Reset Status
425 #define B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 ///< Wake On LAN Override Wake Status
426 #define B_PMC_PWRM_PRSTS_FIELD_1 BIT4
427 #define B_PMC_PWRM_PRSTS_ME_WAKE_STS BIT0
428
429 #define R_PMC_PWRM_PWR_CTL 0x1814
430 #define R_PMC_PWRM_PM_CFG 0x1818 ///< Power Management Configuration Reg 1
431 #define B_PMC_PWRM_PM_CFG_ALLOW_24_OSC_SD BIT29 ///< Allow 24MHz Crystal Oscillator Shutdown
432 #define B_PMC_PWRM_PM_CFG_DBG_MODE_LOCK BIT27 ///< Debug Mode Lock
433 #define B_PMC_PWRM_PM_CFG_ALLOW_USB2_CORE_PG BIT25 ///< Allow USB2 PHY Core Power Gating
434 #define B_PMC_PWRM_PM_CFG_ER_LOCK BIT24 ///< Energy Reporting Lock
435 #define B_PMC_PWRM_PM_CFG_PMC_READ_DISABLE BIT22 ///< Disable Reads to PMC
436 #define B_PMC_PWRM_PM_CFG_SSMAW_MASK (BIT19 | BIT18) ///< SLP_SUS# Min Assertion Width
437 #define V_PMC_PWRM_PM_CFG_SSMAW_4S (BIT19 | BIT18) ///< 4 seconds
438 #define V_PMC_PWRM_PM_CFG_SSMAW_1S BIT19 ///< 1 second
439 #define V_PMC_PWRM_PM_CFG_SSMAW_0_5S BIT18 ///< 0.5 second (500ms)
440 #define V_PMC_PWRM_PM_CFG_SSMAW_0S 0 ///< 0 second
441 #define B_PMC_PWRM_PM_CFG_SAMAW_MASK (BIT17 | BIT16) ///< SLP_A# Min Assertion Width
442 #define V_PMC_PWRM_PM_CFG_SAMAW_2S (BIT17 | BIT16) ///< 2 seconds
443 #define V_PMC_PWRM_PM_CFG_SAMAW_98ms BIT17 ///< 98ms
444 #define V_PMC_PWRM_PM_CFG_SAMAW_4S BIT16 ///< 4 seconds
445 #define V_PMC_PWRM_PM_CFG_SAMAW_0S 0 ///< 0 second
446 #define B_PMC_PWRM_PM_CFG_RPCD_MASK (BIT9 | BIT8) ///< Reset Power Cycle Duration
447 #define V_PMC_PWRM_PM_CFG_RPCD_1S (BIT9 | BIT8) ///< 1-2 seconds
448 #define V_PMC_PWRM_PM_CFG_RPCD_2S BIT9 ///< 2-3 seconds
449 #define V_PMC_PWRM_PM_CFG_RPCD_3S BIT8 ///< 3-4 seconds
450 #define V_PMC_PWRM_PM_CFG_RPCD_4S 0 ///< 4-5 seconds (Default)
451 #define B_PMC_PWRM_PM_CFG_COCS BIT5 ///< CPU OC Strap
452 #define B_PMC_PWRM_PM_CFG_ER_EN BIT2 ///< Energy Reporting Enable
453 #define B_PMC_PWRM_PM_CFG_TIMING_TPCH25 (BIT1 | BIT0) ///< tPCH25 timing
454
455 #define R_PMC_PWRM_S3_PWRGATE_POL 0x1828 ///< S3 Power Gating Policies
456 #define B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS BIT1 ///< S3 Power Gate Enable in DC Mode: SUS Well
457 #define B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS BIT0 ///< S3 Power Gate Enable in AC Mode: SUS Well
458
459 #define R_PMC_PWRM_S4_PWRGATE_POL 0x182C ///< S4 Power Gating Policies
460 #define B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS BIT1 ///< S4 Power Gate Enable in DC Mode: SUS Well
461 #define B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS BIT0 ///< S4 Power Gate Enable in AC Mode: SUS Well
462
463 #define R_PMC_PWRM_S5_PWRGATE_POL 0x1830 ///< S5 Power Gating Policies
464 #define B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS BIT15 ///< S5 Power Gate Enable in DC Mode: SUS Well
465 #define B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS BIT14 ///< S5 Power Gate Enable in AC Mode: SUS Well
466
467 #define R_PMC_PWRM_DSX_CFG 0x1834 ///< DeepSx Configuration
468 #define B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 ///< WAKE# Pin DeepSx Enable
469 #define B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 ///< AC_PRESENT Pin Pulldown in DeepSx Disable
470 #define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 ///< LAN_WAKE Pin DeepSx Enable
471
472 #define R_PMC_PWRM_PM_CFG2 0x183C ///< Power Management Configuration Reg 2
473 #define B_PMC_PWRM_PM_CFG2_PBOP (BIT31 | BIT30 | BIT29) ///< Power Button Override Period
474 #define N_PMC_PWRM_PM_CFG2_PBOP 29 ///< Power Button Override Period (PBOP)
475 #define B_PMC_PWRM_PM_CFG2_PB_DIS BIT28 ///< Power Button Native Mode Disable
476 #define B_PMC_PWRM_PM_CFG2_EN_DBG_MSG BIT27 ///< Enable Debug Messaging
477 #define B_PMC_PWRM_PM_CFG2_DRAM_RESET_CTL BIT26 ///< DRAM_RESET# Control
478 #define N_PMC_PWRM_PM_CFG2_DRAM_RESET_CTL 26
479
480 #define R_PMC_PWRM_EN_SN_SLOW_RING 0x1848 ///< Enable Snoop Request to SLOW_RING
481 #define R_PMC_PWRM_EN_SN_SLOW_RING2 0x184C ///< Enable Snoop Request to SLOW_RING 2nd Reg
482 #define R_PMC_PWRM_EN_SN_SA 0x1850 ///< Enable Snoop Request to SA
483 #define R_PMC_PWRM_EN_SN_SA2 0x1854 ///< Enable Snoop Request to SA 2nd Reg
484 #define R_PMC_PWRM_EN_SN_SLOW_RING_CF 0x1858 ///< Enable Snoop Request to SLOW_RING_CF
485 #define R_PMC_PWRM_EN_NS_SA 0x1868 ///< Enable Non-Snoop Request to SA
486 #define R_PMC_PWRM_EN_CW_SLOW_RING 0x1880 ///< Enable Clock Wake to SLOW_RING
487 #define R_PMC_PWRM_EN_CW_SLOW_RING2 0x1884 ///< Enable Clock Wake to SLOW_RING 2nd Reg
488 #define R_PMC_PWRM_EN_CW_SA 0x1888 ///< Enable Clock Wake to SA
489 #define R_PMC_PWRM_EN_CW_SA2 0x188C ///< Enable Clock Wake to SA 2nd Reg
490 #define R_PMC_PWRM_EN_CW_SLOW_RING_CF 0x1898 ///< Enable Clock Wake to SLOW_RING_CF
491 #define R_PMC_PWRM_EN_PA_SLOW_RING 0x18A8 ///< Enable Pegged Active to SLOW_RING
492 #define R_PMC_PWRM_EN_PA_SLOW_RING2 0x18AC ///< Enable Pegged Active to SLOW_RING 2nd Reg
493 #define B_PMC_PWRM_EN_PA_SLOW_RING2_GBETSN BIT26 ///< GBETSN Pegged Active to SLOW_RING
494 #define R_PMC_PWRM_EN_PA_SA_0 0x18B0 ///< EN_PA_SA - Register 0
495 #define R_PMC_PWRM_EN_PA_SA_02 0x18B4 ///< EN_PA_SA - Register 0
496 #define R_PMC_PWRM_EN_MISC_EVENT 0x18C0 ///< Enable Misc PM_SYNC Events
497 #define R_PMC_PWRM_PMSYNC_TPR_CONFIG 0x18C4
498 #define R_PMC_PWRM_SLP_S0_RESIDENCY 0x193C ///< SLP_S0 Residency
499 #define R_PMC_PWRM_PS_ON_COUNTER 0x18F8
500
501 #define R_PMC_PWRM_PM_SYNC_MISC_CFG 0x18C8
502 #define B_PMC_PWRM_PM_SYNC_MISC_CFG_PCH2CPU_TT_EN BIT26
503 #define B_PMC_PWRM_PM_SYNC_MISC_CFG_PCH2CPU_TT_STATE (BIT25 | BIT24)
504 #define N_PMC_PWRM_PM_SYNC_MISC_CFG_PCH2CPU_TT_STATE 24
505 #define V_PMC_PWRM_PM_SYNC_MISC_CFG_PCH2CPU_TT_STATE_1 1
506 #define B_PMC_PWRM_PM_SYNC_MISC_CFG_PM_SYNC_LOCK BIT15 ///< PM_SYNC Configuration Lock
507
508 #define R_PMC_PWRM_PM_SYNC_STATE_HYS 0x18D0 ///< PM_SYNC State Hysteresis
509 #define R_PMC_PWRM_PM_SYNC_MODE 0x18D4 ///< PM_SYNC Pin Mode
510
511 #define R_PMC_PWRM_PM_CFG3 0x18E0 ///< Power Management Configuration Reg 3
512 #define B_PMC_PWRM_PM_CFG3_SYS_RST_SUP BIT22 ///< Sys Reset# Suppression
513 #define B_PMC_PWRM_PM_CFG3_HOST_WLAN_PP_EN BIT17 ///< Host Wireless LAN Phy Power Enable
514 #define B_PMC_PWRM_PM_CFG3_DSX_WLAN_PP_EN BIT16 ///< Deep-Sx WLAN Phy Power Enable
515 #define B_PMC_PWRM_PM_CFG3_HOST_MISC_CORE_CFG_CPU_VCC_MAP BIT2 ///< Enable CPU Vcc Mapping
516
517 #define R_PMC_PWRM_PM_CFG4 0x18E8 ///< Power Management Configuration Reg 4
518 #define B_PMC_PWRM_PM_CFG4_U2_PHY_PG_EN BIT30 ///< USB2 PHY SUS Well Power Gating Enable
519 #define B_PMC_PWRM_CFG4_SLPS0_PSON_TMR (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24 | BIT23) ///< SLPS0_PSON_TMR
520 #define N_PMC_PWRM_CFG4_SLPS0_PSON_TMR 23
521 #define V_PMC_PWRM_CFG4_SLPS0_PSON_TMR_15_5MS 0x1F
522 #define B_PMC_PWRM_CFG4_PSON_SLPS0_TMR (BIT22 | BIT21 | BIT20 | BIT19 | BIT18) ///< PSON_SLPS0_TMR
523 #define N_PMC_PWRM_CFG4_PSON_SLPS0_TMR 18
524 #define V_PMC_PWRM_CFG4_PSON_SLPS0_TMR_620MS 0x1F
525 #define B_PMC_PWRM_PM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) ///< CPU I/O VR Ramp Duration, [8:0]
526 #define N_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0
527
528 #define R_PMC_PWRM_CPU_EPOC 0x18EC ///< CPU Early Power-on Configuration
529 #define N_PMC_PWRM_CPU_EPOC_DATA_17 17
530 #define N_PMC_PWRM_CPU_EPOC_DATA_20 20
531
532 #define R_PMC_PWRM_ADR_EN 0x18F0 ///< ADR Enable
533 #define B_PMC_PWRM_ADR_EN_ADR_GPIO_SEL (BIT31 | BIT30) ///< ADR GPIO Selection
534 #define N_PMC_PWRM_ADR_GPIO_SEL 30
535 #define V_PMC_PWRM_ADR_GPIO_B 0x1
536 #define V_PMC_PWRM_ADR_GPIO_C 0x2
537 #define B_PMC_PWRM_ADR_EN_HPR_ADR_EN BIT28 ///< Host Partition Reset ADR Enable
538 #define B_PMC_PWRM_ADR_EN_ADR_PLT_ACK_EN BIT26 ///< ADR Pltaform Acknowledge Enable
539 #define B_PMC_PWRM_ADR_EN_ADR_FEAT_EN BIT0 ///< ADR Feature Enable
540
541 #define R_PMC_PWRM_PM_SYNC_MODE_C0 0x18F4
542 #define R_PMC_PWRM_ACPI_TMR_CTL 0x18FC ///< ACPI Timer Control
543 #define B_PMC_PWRM_ACPI_TMR_CTL_DIS BIT1
544
545 #define R_PMC_PWRM_VR_MISC_CTL 0x1900
546
547 #define R_PMC_PWRM_ADR_GEN_CFG 0x196C ///< ADR General Configuration Register
548 #define R_PMC_PWRM_ADR_GEN_CFG_V2 0x1908 ///< ADR General Configuration Register Version 2
549 #define B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_SCALE (BIT28|BIT27|BIT26) ///< ADR Timer Scale
550 #define N_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_SCALE 26
551 #define B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_EN BIT19 ///< ADR Phase 2 Enable
552 #define B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_TOV (BIT18|BIT17|BIT16|BIT15|BIT14|BIT13|BIT12|BIT11) ///< ADR Timer Base
553 #define N_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_TOV 11
554 #define B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_SCALE (BIT10|BIT9|BIT8) ///< ADR Timer Scale (Tick Frequency)
555 #define N_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_SCALE 8
556 #define B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_TOV (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) ///< ADR Timer Base
557 #define N_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_TOV 0
558
559 #define R_PMC_PWRM_GBL2HOST_EN 0x190C ///< Global to Host Reset Enable
560 #define B_PMC_PWRM_GBL2HOST_EN_HOST_RESET_TIMEOUT BIT0 ///< Global to Host for Host Partition Reset Timeout
561
562 #define R_PMC_PWRM_GPIO_CFG 0x1920 ///< GPIO Configuration
563 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10 | BIT9 | BIT8)///< GPIO Group to GPE_DW2 assignment encoding
564 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8
565 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 | BIT5 | BIT4) ///< GPIO Group to GPE_DW1 assignment encoding
566 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4
567 #define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 | BIT1 | BIT0) ///< GPIO Group to GPE_DW0 assignment encoding
568 #define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0
569
570 #define R_PMC_PWRM_GBLRST_CAUSE0 0x1924 ///< Global Reset Causes 0
571 #define R_PMC_PWRM_PMLDOCTRL 0x1A00 ///< PMC LDO Control Register
572 #define B_PMC_PWRM_PMDLOCTRL_U31P2_LDODSEN BIT24
573 #define B_PMC_PWRM_PMLDOCTRL_CNVIP24LDOLPEN BIT9
574 #define B_PMC_PWRM_PMLDOCTRL_USB2TS1P3LDODSEN BIT0
575
576 #define R_PMC_PWRM_GBLRST_CAUSE1 0X1928 ///< Global Reset Causes 1
577
578 #define R_PMC_PWRM_HPR_CAUSE0 0x192C ///< Host Partition Reset Causes
579 #define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< Global Reset Converted to Host Reset
580
581 #define R_PMC_PWRM_CORE_SPARE_GCR 0x195C
582
583 #define R_PMC_PWRM_ADR_CTRL_STS 0x1960 ///< ADR Control and Status
584 #define B_PMC_PWRM_ADR_CTRL_STS_ADR_RST_STS BIT0 ///< ADR Reset Status
585
586 #define R_PMC_PWRM_ADR_GBLRST_EN_0 0x191C ///< ADR Global Reset Enable 0
587
588 #define R_PMC_PWRM_S0IX_LDO_OFF_COUNT 0x1A04 ///< PMC LDO S0ix Shutdown Count Register
589 #define B_PMC_PWRM_S0IX_LDO_OFF_COUNT_LOCK BIT31
590 #define R_PMC_PWRM_S0_LDO_OFF_COUNT 0x1A08 ///< PMC LDO S0 Shutdown Count Register
591 #define B_PMC_PWRM_S0_LDO_OFF_COUNT_LOCK BIT31
592
593 #define R_PMC_PWRM_LTR_IGN 0x1B0C ///< LTR Ignore
594 #define R_PMC_PWRM_OBFF_CFG 0x1B14 ///< OBFF Configuration
595 #define R_PMC_PWRM_CPPMVRIC 0x1B1C ///< CPPM VR Idle Control 1
596 #define R_PMC_PWRM_CPPM_MISC_CFG 0x1B20 ///< CPPM Miscellaneous Configuration
597 #define R_PMC_PWRM_CPPM_CG_POL1A 0x1B24 ///< CPPM Clock Gating Policy Reg 1
598 #define R_PMC_PWRM_CPPM_CG_POL1B 0x1B28 ///< CPPM Clock Gating Policy Reg 1
599 #define R_PMC_PWRM_CPPM_CG_POL2B 0x1B30
600 #define R_PMC_PWRM_CPPM_CG_POL3B 0x1B38
601 #define B_PMC_PWRM_CPPM_FIVR_POL1B_TNTE_FIVR_VOLT_PRE_WAKE 0x1FFFF ///< TNTE PreWake for FIVR Voltage
602 #define R_PMC_PWRM_CPPM_CG_POL2A 0x1B40 ///< CPPM Clock Gating Policy Reg 2
603 #define R_PMC_PWRM_CPPM_CG_POL2A_V2 0x1B2C
604
605 #define R_PMC_PWRM_CPPM_CG_POL3A 0x1BA8 ///< CPPM Clock Gating Policy Reg 3
606 #define R_PMC_PWRM_CPPM_CG_POL3A_V2 0x1B34
607 #define B_PMC_PWRM_CPPM_CG_POL1A_LT_G1_SEL BIT29 ///< ASLT/PLT Selection for Clock Source Group x
608 #define B_PMC_PWRM_CPPM_CG_POL1A_CPPM_G1_QUAL BIT30 ///< CPPM Shutdown Qualifier Enable for Clock Source Group x
609 #define B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH (0x000001FF) ///< LTR Threshold for Clock Source Group X, [8:0]
610 #define B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH_V2 (0x0000FFFF) ///< LTR Threshold for Clock Source Group X, [15:0]
611
612 #define R_PMC_PWRM_CPPMFALIGNCTL_1 0x1BD0 ///< CPPM Forced Alignment Control 1
613 #define R_PMC_PWRM_CPPM_CG_POL4A 0x1B3C
614
615 #define R_PMC_PWRM_ACTL 0x1BD8 ///< ACPI Control
616 #define B_PMC_PWRM_ACPI_SCIS (BIT2 | BIT1 | BIT0) ///< SCI IRQ select
617 #define V_PMC_PWRM_ACPI_SCIS_IRQ9 0
618 #define V_PMC_PWRM_ACPI_SCIS_IRQ10 1
619 #define V_PMC_PWRM_ACPI_SCIS_IRQ11 2
620 #define V_PMC_PWRM_ACPI_SCIS_IRQ20 4
621 #define V_PMC_PWRM_ACPI_SCIS_IRQ21 5
622 #define V_PMC_PWRM_ACPI_SCIS_IRQ22 6
623 #define V_PMC_PWRM_ACPI_SCIS_IRQ23 7
624
625 #define R_PMC_PWRM_BM_CX_CNF 0x1BDC ///< in CNL this is PWRM register
626 #define B_PMC_PWRM_BM_CX_CNF_PHOLD_BM_STS_BLOCK BIT14
627 #define B_PMC_PWRM_BM_CX_CNF_BM_STS_ZERO_EN BIT10
628 #define B_PMC_PWRM_BM_CX_CNF_PM_SYNC_MSG_MODE BIT9
629
630 #define R_PMC_PWRM_THROT_1 0x1BE0
631 #define B_PMC_PWRM_THROT_1_VR_ALERT BIT0
632
633 #define R_PMC_PWRM_CS_SD_CTL1 0x1BE8 ///< Clock Source Shutdown Control Reg 1
634 #define B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21 | BIT20) ///< Clock Source 5 Control Configuration
635 #define N_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20
636 #define B_PMC_PWRM_CS_SD_CTL1_CS_XTAL_CTL_CFG (BIT18 | BIT17 | BIT16) ///< Clock Source XTAL Control Configuration
637 #define N_PMC_PWRM_CS_SD_CTL1_CS_XTAL_CTL_CFG 16
638 #define B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 | BIT0) ///< Clock Source 1 Control Configuration
639
640 #define R_PMC_PWRM_CS_SD_CTL2 0x1BEC ///< Clock Source Shutdown Control Reg 1
641
642 #define R_PMC_PWRM_LPM_ADEM_HOST_CTRL 0x1C20 ///< Low Power Mode Auto-Demotion Host Control
643 #define R_PMC_PWRM_LPM_ADEM_HOST_CTRL_V2 0x1700
644 #define R_PMC_PWRM_LPM_ADEM_HOST_CTRL_V3 0x16F4
645 #define B_PMC_PWRM_LPM_ADEM_HOST_CTRL_EN BIT0 ///< Low Power Mode Auto-Demotion Host Enable
646
647 #define R_PMC_PWRM_LPM_EN 0x1C78 ///< Low Power Mode Enable
648 #define R_PMC_PWRM_LPM_EN_V2 0x179C ///< Low Power Mode Enable- version 2
649 #define R_PMC_PWRM_LPM_EN_V3 0x1798 ///< Low Power Mode Enable- version 3
650 #define R_PMC_PWRM_LPM_PRI 0x1C7C ///< Low Power Mode Priority
651 #define R_PMC_PWRM_LPM_PRI_V2 0x17A0
652 #define R_PMC_PWRM_LPM_PRI_V3 0x179C
653 #define R_PMC_PWRM_LPM_PRI_V4 0x1C9C ///< Low Power Mode Priority- version 4
654
655 #define R_PMC_PWRM_CS_SD_OVR_EN 0x1F54 ///< Clock Source Override Enable Control Reg
656 #define B_PMC_PWRM_CS_ACRO_CRO_OVR_EN BIT0 ///< Disable ACRO from LTR comparisons
657
658 #define R_PMC_PWRM_HSWPGCR1 0x1DD0
659 #define B_PMC_PWRM_SW_PG_CTRL_LOCK BIT31
660 #define B_PMC_PWRM_NPK_VNN_SW_PG_CTRL BIT0
661
662 #define R_PMC_PWRM_1E00 0x1E00
663 #define R_PMC_PWRM_1E04 0x1E04
664 #define B_PMC_PWRM_1E04_CX_QUAL_EN_SBR BIT29
665 #define B_PMC_PWRM_1E04_ALL_SBR_IDLE_QUAL_EN BIT31
666
667 #define R_PMC_PWRM_ST_PG_FDIS_PMC_0_V2 0x1E20 ///< Static Function Disable Control Register 0- veriosn 2
668
669 #define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< Static PG Related Function Disable Register 1
670 #define R_PMC_PWRM_ST_PG_FDIS_PMC_1_V2 0x1E24 ///< Static PG Related Function Disable Register 1- version 2
671 #define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Static Function Disable Lock (ST_FDIS_LK)
672
673 #define R_PMC_PWRM_ST_PG_FDIS_PMC_2 0x1E24 ///< Static Function Disable Control Register 2
674 #define R_PMC_PWRM_ST_PG_FDIS_PMC_2_V2 0x1E28 ///< Static Function Disable Control Register 2- veriosn 2
675
676 #define R_PMC_PWRM_TNTE_RTC_ERROR_LOAD_OFFSET 0x1F00
677
678 #define R_PMC_PWRM_TNTE_CTL_CFG 0x1F5C
679
680 #define R_PMC_PWRM_BCLK_CFG 0x1F60 ///< BCLK PLLs Configuration
681 #define B_PMC_PWRM_BCLK_CFG_CPU_BCLK_OVR_VAL BIT2
682 #define B_PMC_PWRM_BCLK_CFG_CPU_BCLK_OVR_EN BIT3
683 #define B_PMC_PWRM_BCLK_CFG_SOC_BCLK_OVR_VAL BIT4
684 #define B_PMC_PWRM_BCLK_CFG_SOC_BCLK_OVR_EN BIT5
685
686 #define R_PMC_PWRM_VGPIO_BAR_LO 0x2000
687 #define R_PMC_PWRM_VGPIO_CFG 0x2010
688 #define B_PMC_PWRM_VGPIO_CFG_VGPIO_eSPI_MODE BIT0
689
690 //
691 // Low Power Mode requirements - 1st register
692 //
693 #define R_PMC_PWRM_LPM0_REQ_0 0x1000 ///<Low Power Mode 0 Requirements Reg 0
694 //
695 // Low Power Mode requirements - End register
696 //
697 #define R_PMC_PWRM_LPM7_REQ_5 0x1164 ///<Low Power Mode 7 Requirements Reg 5
698 //
699 // Low Power Mode requirements - data length (byte)
700 //
701 #define V_PMC_PWRM_LPM_REQ_DATA_LEN 192
702 //
703 // Low Power Mode requirements - data length (bit)
704 //
705 #define V_PMC_PWRM_LPM_REQ_BITS_DATA_LEN 1536
706
707 //
708 // PWRM Registers for IPC interface
709 //
710
711 #define V_PMC_PWRM_IPC_CMD_COMMAND_PMIC 0xC0 ///< IPC commmand to configure PMIC
712 #define V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC1_I2C 0x00 ///< SubCommand to read PMIC I2C
713 #define V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC1_I2C 0x01 ///< SubCommand to write PMIC I2C
714 #define V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC2_I2C 0x03 ///< SubCommand to read PMIC I2C
715 #define V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC2_I2C 0x04 ///< SubCommand to read PMIC I2C
716 #define V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC3_I2C 0x06 ///< SubCommand to read PMIC I2C
717 #define V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC3_I2C 0x07 ///< SubCommand to read PMIC I2C
718
719 #define V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_LOCK_ENABLE_PMIC_I2C 0xF ///< SubCommand to PMC write lock enable
720
721 //
722 // GPE interrupts definitons
723 //
724 #define GPE_PCI_EXP 0x69
725 #define GPE_PME_B0 0x6D
726
727 #define R_PMC_SOFT_STRAP_7 0x091C ///< This register reflects the value pulled from SMIP or SoftStrap.
728 #define B_PMC_DEF_CPU_BCLK_CFG (BIT15 | BIT14) ///< This value is used to tell the CPU how it should configure the CPU BCLK PLL.
729 #define N_PMC_DEF_CPU_BCLK_CFG 14 ///< This value is used to shift B_PMC_DEF_CPU_BCLK_CFG
730 #define V_PMC_DEF_CPU_BCLK_CFG_INTEGRATED (0x00008000) ///< BIT[15:14] = {10b}, BCLK source is integrated. BIT[15:14] = {00b}, BCLK source is external.
731 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PostCodeToScratchPadLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PostCodeToScratchPadLib.h File Reference

Header file for writing the postcode value into scratchpad register. More...

Go to the source code of this file.

Functions

VOID SetPostCodeToScratchPad (UINTN PostCode)
Write the postcode value into scratchpad register. More...

Detailed Description

Header file for writing the postcode value into scratchpad register.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains 'Framework Code' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may not be modified, except as allowed by additional terms of your license agreement.

Specification Reference:

Definition in file PostCodeToScratchPadLib.h.

Function Documentation

◆ SetPostCodeToScratchPad()

VOID SetPostCodeToScratchPad ( UINTN PostCode )

Write the postcode value into scratchpad register.

Parameters
[in] PostCode - The postcode value to save to scratchpad register
Return values
None
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PostCodeToScratchPadLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PostCodeToScratchPadLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for writing the postcode value into scratchpad register.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains 'Framework Code' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may not be
30 modified, except as allowed by additional terms of your license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _POSTCODE_TO_SCRATCHPAD_H
35 #define _POSTCODE_TO_SCRATCHPAD_H
36
37 /**
38 Write the postcode value into scratchpad register
39
40 @param[in] PostCode - The postcode value to save to scratchpad register
41
42 @retval None
43 **/
44 VOID
45 EFIAPI
46 SetPostCodeToScratchPad (
47 UINTN PostCode
48 );
49
50 #endif
SetPostCodeToScratchPad
VOID SetPostCodeToScratchPad(UINTN PostCode)
Write the postcode value into scratchpad register.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PreSiliconEnvDetectLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PreSiliconEnvDetectLib.h File Reference

Prototype of the PreSiliconEnvDetectLib library. More...

Go to the source code of this file.

Functions

BOOLEAN | IsSimicsEnvironment (VOID)
Check if currently run in Simics environment or not. More...
BOOLEAN | IsHfpgaEnvironment (VOID)
Check if currently run in HFPGA environment or not. More...
BOOLEAN | IsHSLEEnvironment (VOID)
Check if currently run in HSLE environment or not. More...
BOOLEAN | IsHSLEEnvironment_UPF (VOID)
Check if currently run in HSLE UPF environment or not. More...

Detailed Description

Prototype of the PreSiliconEnvDetectLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PreSiliconEnvDetectLib.h.

Function Documentation

◆ IsHfpgaEnvironment()

BOOLEAN IsHfpgaEnvironment ( VOID )

Check if currently run in HFPGA environment or not.

Return values
TRUE | Run in HFPGA environment
FALSE | Not run in HFPGA environment

◆ IsHSLEEnvironment()

BOOLEAN IsHSLEEnvironment ( VOID )

Check if currently run in HSLE environment or not.

Return values
TRUE | Run in HSLE environment
FALSE | Not run in HSLE environment

◆ IsHSLEEnvironment_UPF()

BOOLEAN IsHSLEEnvironment_UPF ( VOID )

Check if currently run in HSLE UPF environment or not.

Return values
TRUE | Run in HSLE UPF environment
FALSE | Not run in HSLE UPF environment

◆ IsSimicsEnvironment()

BOOLEAN IsSimicsEnvironment ( VOID )

Check if currently run in Simics environment or not.

Return values
TRUE | Run in Simics environment
FALSE | Not run in Simics environment
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PreSiliconEnvDetectLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PreSiliconEnvDetectLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the PreSiliconEnvDetectLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PRESILICON_ENV_DETECT_LIB_H_
36 #define _PRESILICON_ENV_DETECT_LIB_H_
37
38 /**
39 Check if currently run in Simics environment or not.
40
41 @retval TRUE Run in Simics environment
42 @retval FALSE Not run in Simics environment
43 **/
44 BOOLEAN
45 IsSimicsEnvironment (
46 VOID
47 );
48
49 /**
50 Check if currently run in HFPGA environment or not.
51
52 @retval TRUE Run in HFPGA environment
53 @retval FALSE Not run in HFPGA environment
54 **/
55 BOOLEAN
56 IsHfpgaEnvironment (
57 VOID
58 );
59
60 /**
61 Check if currently run in HSLE environment or not.
62
63 @retval TRUE Run in HSLE environment
64 @retval FALSE Not run in HSLE environment
65 **/
66 BOOLEAN
67 IsHSLEEnvironment (
68 VOID
69 );
70
71 /**
72 Check if currently run in HSLE UPF environment or not.
73
74 @retval TRUE Run in HSLE UPF environment
75 @retval FALSE Not run in HSLE UPF environment
76 **/
77 BOOLEAN
78 IsHSLEEnvironment_UPF (
79 VOID
80 );
81 #endif // _PRESILICON_ENV_DETECT_LIB_H_
IsHSLEEnvironment
BOOLEAN IsHSLEEnvironment(VOID)
Check if currently run in HSLE environment or not.
IsHSLEEnvironment_UPF
BOOLEAN IsHSLEEnvironment_UPF(VOID)
Check if currently run in HSLE UPF environment or not.
IsSimicsEnvironment
BOOLEAN IsSimicsEnvironment(VOID)
Check if currently run in Simics environment or not.
IsHfpgaEnvironment
BOOLEAN IsHfpgaEnvironment(VOID)
Check if currently run in HFPGA environment or not.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsfConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
Classes
PsfConfig.h File Reference

Primary Sideband Fabric policy. More...

#include <ConfigBlock.h>
Include dependency graph for PsfConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PSF_CONFIG
The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric. More...

Detailed Description

Primary Sideband Fabric policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PsfConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsfConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
PsfConfig.h
Go to the documentation of this file.
1 /** @file
2 Primary Sideband Fabric policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PSF_CONFIG_H_
37 #define _PSF_CONFIG_H_
38
39 #include <ConfigBlock.h>
40 #define PSF_CONFIG_REVISION 1
41 extern EFI_GUID gPsfConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 The PSF_CONFIG block describes the expected configuration of the Primary
47 Sideband Fabric.
48 **/
49 typedef struct {
50 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
51 /**
52 Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable
53 some psf power management features. <b>0: Disable</b>; 1: Enable.
54 **/
55 UINT32 TccEnable : 1;
56 UINT32 RsvdBits0 : 31; ///< Reserved bits
57 } PSF_CONFIG;
58
59 #pragma pack (pop)
60
61 #endif // _PSF_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
PSF_CONFIG
The PSF_CONFIG block describes the expected configuration of the Primary Sideband Fabric.
Definition: PsfConfig.h:49
PSF_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: PsfConfig.h:50
PSF_CONFIG::TccEnable
UINT32 TccEnable
Psf Tcc (Time Coordinated Computing) Enable will decrease psf transaction latency by disable some psf...
Definition: PsfConfig.h:55
PSF_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: PsfConfig.h:56
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsrMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
PsrMsgs.h File Reference

Definitions for querying PSR message. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Detailed Description

Definitions for querying PSR message.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PsrMsgs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsrMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
PsrMsgs.h
Go to the documentation of this file.
1 /** @file
2 Definitions for querying PSR message
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PSR_MSG_H_
37 #define _PSR_MSG_H_
38
39 #define PSR_GENESIS_SIZE 1288
40 #define PSR_LEDGER_SIZE 16
41 #define PSR_EVENT_SIZE 12
42 #define PSR_MAX_EVENT_COUNT 100
43 #define PSR_MAX_CERT_CHAIN_SIZE 3000
44 #define PSR_ODCA_CHAIN_LEN 4
45 #define PSR_MAX_SIGNATURE_LENGTH 512
46 #define NONCE_MAXSIZE 20
47 #define PSR_SHA512_LEN_BYTES 512
48 #define PSR_PLATFORM_ID_LENGTH 64
49
50 //PSR Commands
51 #define GET_PSR_REQUEST_CMD 0x0A
52 #define PSR_INFORM_CHASSIS_INTRUSION_CMD 0x0B
53
54 #pragma pack(1)
55
56 typedef struct {
57 UINT16 Major;
58 UINT16 Minor;
59 } PSR_VERSION;
60
61 typedef struct {
62 UINT16 Major;
63 UINT16 Minor;
64 UINT16 Hotfix;
65 UINT16 Build;
66 } CSME_FW_VERSION;
67
68 #ifndef VFRCOMPILE
69
70 typedef enum {
71 Ecdsa384WithSha384 = 0,
72 } LOG_SIGNING_MECHANISM;
73
74 typedef enum {
75 PsrStatusSuccess,
76 PsrStatusFeatureNotSupported,
77 PsrStatusUpidDisabled,
78 PsrStatusActionNotAllowed,
79 PsrStatusInvalidInputParameter,
80 PsrStatusInternalError,
81 PsrStatusNotAllowedAfterEop,
82 } PSR_STATUS;
83
84 typedef enum {
85 PsrLogStateNotStarted = 0, /* Default value */
86 PsrLogStateStarted,
87 PsrLogStateStopped,
88 } PSR_LOGGING_STATUS;
89
90 typedef struct {
91 UINT8 Command;
92 UINT8 Reserved;
93 UINT16 ByteCount;
94 } PSR_HECI_HEADER;
95
96 typedef struct {
97 PSR_HECI_HEADER Header;
98 UINT8 UserNonce[NONCE_MAXSIZE];
99 } PSR_REQUEST;
100
101 typedef struct {
102 UINT8 Psrid[16];
103 UINT8 Upid[PSR_PLATFORM_ID_LENGTH];
104 UINT8 GenesisBuffer[PSR_GENESIS_SIZE];
105 UINT32 Ledger[PSR_LEDGER_SIZE];
106 UINT32 TotalEventCount;
107 UINT8 EventsBuffer[(PSR_EVENT_SIZE * PSR_MAX_EVENT_COUNT)];
108 } PLATFORM_SERVICE_RECORD;
109
110 typedef struct {
111 PSR_VERSION PsrVersion;
112 PLATFORM_SERVICE_RECORD Psr;
113 UINT8 PsrHash[PSR_SHA512_LEN_BYTES];
114 UINT8 UserNonce[NONCE_MAXSIZE];
115 UINT8 CsmeNonce[NONCE_MAXSIZE];
116 CSME_FW_VERSION FwVersion;
117 LOG_SIGNING_MECHANISM SignatureMechanism;
118 UINT8 Signature[PSR_MAX_SIGNATURE_LENGTH];
119 UINT16 LengthsOfCertificate[PSR_ODCA_CHAIN_LEN];
120 UINT8 Certificates[PSR_MAX_CERT_CHAIN_SIZE];
121 } PSR_DATA;
122
123 typedef struct {
124 PSR_HECI_HEADER Header;
125 PSR_STATUS Status;
126 PSR_LOGGING_STATUS PsrLoggingStatus;
127 PSR_DATA PsrData;
128 } PSR_RESPONSE;
129
130 typedef union {
131 PSR_REQUEST Request;
132 PSR_RESPONSE Response;
133 } GET_PSR_BUFFER;
134
135 typedef struct {
136 PSR_HECI_HEADER Header;
137 } PSR_CHASSIS_INTRUSION_DET_EVENT_REQUEST;
138
139 #endif //VFRCOMPILE
140
141 #pragma pack()
142
143 #endif // _PSR_MSG_H_
144
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsthLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PsthLib.h File Reference

This file provides PSTH public library. More...

Go to the source code of this file.

Functions

VOID PsthGetIoTrapResourceSetting (IN OUT IOTRAP_RESOURCE_SETTING *IoTrapResources)
Get IOTRAP resource settings. More...

Detailed Description

This file provides PSTH public library.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PsthLib.h.

Function Documentation

◆ PsthGetIoTrapResourceSetting()

VOID PsthGetIoTrapResourceSetting ( IN OUT IOTRAP_RESOURCE_SETTING * IoTrapResources )

Get IOTRAP resource settings.

Parameters
[in,out] IoTrapResources Point to IOTRAP_RESOURCE_SETTING.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PsthLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PsthLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides PSTH public library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PSTH_LIB_H_
36 #define _PSTH_LIB_H_
37
38 #define IOTRAP_ENTRY_MAX 4
39
40 typedef struct {
41 UINT16 Base;
42 UINT16 Length;
43 } IOTRAP_RESOURCE_ENTRY;
44
45 typedef struct {
46 IOTRAP_RESOURCE_ENTRY IoTrapResourceEntry[IOTRAP_ENTRY_MAX];
47 } IOTRAP_RESOURCE_SETTING;
48
49 /**
50 Get IOTRAP resource settings
51
52 @param[in out] IoTrapResources Point to IOTRAP_RESOURCE_SETTING.
53 **/
54 VOID
55 PsthGetIoTrapResourceSetting (
56 IN OUT IOTRAP_RESOURCE_SETTING *IoTrapResources
57 );
58
59 #endif // _PSTH_LIB_H_
PsthGetIoTrapResourceSetting
VOID PsthGetIoTrapResourceSetting(IN OUT IOTRAP_RESOURCE_SETTING *IoTrapResources)
Get IOTRAP resource settings.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PttHeciLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
PttHeciLib.h File Reference

Platform Trust Technology (PTT) HECI SkuMgr Library. More...

Go to the source code of this file.

Functions

EFI_STATUS | PttHeciGetCapability (OUT BOOLEAN *PttCapability)
Checks whether ME FW has the Platform Trust Technology capability. More...
EFI_STATUS | PttHeciGetState (OUT BOOLEAN *IsPttEnabledState)
Checks Platform Trust Technology enablement state. More...
EFI_STATUS | PttHeciSetState (IN BOOLEAN PttEnabledState)
Changes current Platform Trust Technology state. More...
EFI_STATUS | PttHeciUpdateState (IN BOOLEAN NewPttState)
Updates Platform Trust Technology state to new state. More...

Detailed Description

Platform Trust Technology (PTT) HECI SkuMgr Library.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file PttHeciLib.h.

Function Documentation

◆ PttHeciGetCapability()

EFI_STATUS PttHeciGetCapability ( OUT BOOLEAN * PttCapability )

Checks whether ME FW has the Platform Trust Technology capability.

Parameters
[out] PttCapability TRUE if PTT is supported, FALSE otherwise.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally

◆ PttHeciGetState()

EFI_STATUS PttHeciGetState ( OUT BOOLEAN * IsPttEnabledState )

Checks Platform Trust Technology enablement state.

Parameters
[out] IsPttEnabledState TRUE if PTT is enabled, FALSE otherwise.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally

◆ PttHeciSetState()

EFI_STATUS PttHeciSetState ( IN BOOLEAN PttEnabledState )

Changes current Platform Trust Technology state.

Parameters
[in] PttEnabledState TRUE to enable, FALSE to disable.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally

◆ PttHeciUpdateState()

EFI_STATUS PttHeciUpdateState ( IN BOOLEAN NewPttState )

Updates Platform Trust Technology state to new state.

Parameters
[in] NewPttState TRUE to enable, FALSE to disable.
Return values
EFI_SUCCESS | Command succeeded
EFI_DEVICE_ERROR | HECI Device error, command aborts abnormally
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PttHeciLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
PttHeciLib.h
Go to the documentation of this file.
1 /** @file
2 Platform Trust Technology (PTT) HECI SkuMgr Library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PTT_HECI_LIB_H_
36 #define _PTT_HECI_LIB_H_
37
38 /**
39 Checks whether ME FW has the Platform Trust Technology capability.
40
41 @param[out] PttCapability TRUE if PTT is supported, FALSE otherwise.
42
43 @retval EFI_SUCCESS Command succeeded
44 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
45 **/
46 EFI_STATUS
47 EFIAPI
48 PttHeciGetCapability (
49 OUT BOOLEAN *PttCapability
50 );
51
52 /**
53 Checks Platform Trust Technology enablement state.
54
55 @param[out] IsPttEnabledState TRUE if PTT is enabled, FALSE otherwise.
56
57 @retval EFI_SUCCESS Command succeeded
58 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
59 **/
60 EFI_STATUS
61 EFIAPI
62 PttHeciGetState (
63 OUT BOOLEAN *IsPttEnabledState
64 );
65
66 /**
67 Changes current Platform Trust Technology state.
68
69 @param[in] PttEnabledState TRUE to enable, FALSE to disable.
70
71 @retval EFI_SUCCESS Command succeeded
72 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
73 **/
74 EFI_STATUS
75 EFIAPI
76 PttHeciSetState (
77 IN BOOLEAN PttEnabledState
78 );
79
80 /**
81 Updates Platform Trust Technology state to new state.
82
83 @param[in] NewPttState TRUE to enable, FALSE to disable.
84
85 @retval EFI_SUCCESS Command succeeded
86 @retval EFI_DEVICE_ERROR HECI Device error, command aborts abnormally
87 **/
88 EFI_STATUS
89 EFIAPI
90 PttHeciUpdateState (
91 IN BOOLEAN NewPttState
92 );
93
94 #endif
PttHeciGetCapability
EFI_STATUS PttHeciGetCapability(OUT BOOLEAN *PttCapability)
Checks whether ME FW has the Platform Trust Technology capability.
PttHeciSetState
EFI_STATUS PttHeciSetState(IN BOOLEAN PttEnabledState)
Changes current Platform Trust Technology state.
PttHeciGetState
EFI_STATUS PttHeciGetState(OUT BOOLEAN *IsPttEnabledState)
Checks Platform Trust Technology enablement state.
PttHeciUpdateState
EFI_STATUS PttHeciUpdateState(IN BOOLEAN NewPttState)
Updates Platform Trust Technology state to new state.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PttPtpRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
PttPtpRegs.h File Reference

Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface). More...

Go to the source code of this file.

Macros

#define | R_LT_UCS 0xFED30880
LT public space registers.
#define | R_PTT_HCI_BASE_ADDRESS 0xFED40000
FTPM HCI register base address.
#define | V_FTIF_FTPM_PRESENT 0x00070000
FTIF PTT present value.
#define | V_FTIF_SPI_DTPM_PRESENT 0x00050000
FTIF SPI dTPM present value.
#define | FTIF_FT_LOC_MASK (BIT18 | BIT17 | BIT16)
FTIF TPM Location Mask.
#define | B_CRB_CONTROL_STS_TPM_STATUS 0x00000001
BIT0.
#define | B_CRB_CONTROL_STS_TPM_IDLE 0x00000002
BIT1.
#define | B_CRB_CONTROL_REQ_COMMAND_READY 0x00000001
BIT0.
#define | B_CRB_CONTROL_REQ_GO_IDLE 0x00000002
BIT1.
#define | B_CRB_CONTROL_START 0x00000001
BIT0.
#define | B_CRB_LOCALITY_STS_GRANTED 0x00000001
BIT0.
#define | B_CRB_LOCALITY_STS_BEEN_SEIZED 0x00000002
BIT1.
#define | B_CRB_LOCALITY_CTL_REQUEST_ACCESS 0x00000001
BIT0.
#define | B_CRB_LOCALITY_CTL_RELINQUISH 0x00000002
BIT1.
#define | B_CRB_LOCALITY_CTL_SEIZE 0x00000004
BIT2.
#define | B_CRB_LOCALITY_STATE_TPM_ESTABLISHED 0x00000001
BIT0.
#define | B_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED 0x00000002
BIT1.
#define | B_CRB_LOCALITY_STATE_REGISTER_VALID 0x00000080
BIT7.
#define | V_PTT_HCI_IGNORE_BITS 0x00000000
Ignore bit setting mask for WaitRegisterBits.
#define | V_PTT_HCI_ALL_BITS_CLEAR 0xFFFFFFFF
All bits clear mask for WaitRegisterBits.
#define | S_PTT_HCI_CRB_LENGTH 3968
Max FTPM command/response buffer length. More...

Detailed Description

Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface).

Conventions:

  • Prefixes: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values of bits within the registers Definitions beginning with "S_" are register sizes Definitions beginning with "N_" are the bit position
Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file PttPtpRegs.h.

Macro Definition Documentation

◆ S_PTT_HCI_CRB_LENGTH

#define S_PTT_HCI_CRB_LENGTH 3968

Max FTPM command/response buffer length.

0xFED40080:0xFED40FFF = 3968 Bytes

Definition at line 161 of file PttPtpRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PttPtpRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
PttPtpRegs.h
Go to the documentation of this file.
1 /** @file
2 Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface).
3
4 Conventions:
5
6 - Prefixes:
7 Definitions beginning with "R_" are registers
8 Definitions beginning with "B_" are bits within registers
9 Definitions beginning with "V_" are meaningful values of bits within the registers
10 Definitions beginning with "S_" are register sizes
11 Definitions beginning with "N_" are the bit position
12
13 @copyright
14 INTEL CONFIDENTIAL
15 Copyright 2012 - 2016 Intel Corporation.
16
17 The source code contained or described herein and all documents related to the
18 source code ("Material") are owned by Intel Corporation or its suppliers or
19 licensors. Title to the Material remains with Intel Corporation or its suppliers
20 and licensors. The Material may contain trade secrets and proprietary and
21 confidential information of Intel Corporation and its suppliers and licensors,
22 and is protected by worldwide copyright and trade secret laws and treaty
23 provisions. No part of the Material may be used, copied, reproduced, modified,
24 published, uploaded, posted, transmitted, distributed, or disclosed in any way
25 without Intel's prior express written permission.
26
27 No license under any patent, copyright, trade secret or other intellectual
28 property right is granted to or conferred upon you by disclosure or delivery
29 of the Materials, either expressly, by implication, inducement, estoppel or
30 otherwise. Any license under such intellectual property rights must be
31 express and approved by Intel in writing.
32
33 Unless otherwise agreed by Intel in writing, you may not remove or alter
34 this notice or any other notice embedded in Materials by Intel or
35 Intel's suppliers or licensors in any way.
36
37 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
38 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
39 the terms of your license agreement with Intel or your vendor. This file may
40 be modified by the user, subject to additional terms of the license agreement.
41
42 @par Specification
43 **/
44 #ifndef _PTT_HCI_REGS_H_
45 #define _PTT_HCI_REGS_H_
46
47 ///
48 /// LT public space registers
49 ///
50 #define R_LT_UCS 0xFED30880
51 #define R_LT_EXISTS 0xFED30010
52
53 ///
54 /// FTPM HCI register base address
55 ///
56 #define R_PTT_HCI_BASE_ADDRESS 0xFED40000
57 #define R_PTT_TXT_STS_FTIF 0xFED30800
58
59 ///
60 /// FTIF PTT present value
61 ///
62 #define V_FTIF_FTPM_PRESENT 0x00070000
63 ///
64 /// FTIF SPI dTPM present value
65 ///
66 #define V_FTIF_SPI_DTPM_PRESENT 0x00050000
67 ///
68 /// FTIF TPM Location Mask
69 ///
70 #define FTIF_FT_LOC_MASK (BIT18 | BIT17 | BIT16)
71
72 //
73 // FTPM HCI Control Area
74 //
75 #define R_PTT_LOCALITY_STATE 0x00
76 #define R_TPM_LOCALITY_CONTROL 0X08
77 #define R_TPM_LOCALITY_STATUS 0x0C
78 #define R_TPM_INTERFACE_ID 0x30
79 #define R_CRB_CONTROL_EXT 0x38
80 #define R_CRB_CONTROL_REQ 0x40
81 #define R_CRB_CONTROL_STS 0x44
82 #define R_CRB_CONTROL_CANCEL 0x48
83 #define R_CRB_CONTROL_START 0x4C
84 #define R_CRB_CONTROL_INT 0x50
85 #define R_CRB_CONTROL_CMD_SIZE 0x58
86 #define R_CRB_CONTROL_CMD_LOW 0x5C
87 #define R_CRB_CONTROL_CMD_HIGH 0x60
88 #define R_CRB_CONTROL_RESPONSE_SIZE 0x64
89 #define R_CRB_CONTROL_RESPONSE_ADDR 0x68
90 #define R_CRB_DATA_BUFFER 0x80
91
92 //
93 // R_CRB_CONTROL_STS Bits
94 //
95 #define B_CRB_CONTROL_STS_TPM_STATUS 0x00000001 ///< BIT0
96 #define B_CRB_CONTROL_STS_TPM_IDLE 0x00000002 ///< BIT1
97
98 //
99 // R_CRB_CONTROL_REQ Bits
100 //
101 #define B_CRB_CONTROL_REQ_COMMAND_READY 0x00000001 ///< BIT0
102 #define B_CRB_CONTROL_REQ_GO_IDLE 0x00000002 ///< BIT1
103
104 //
105 // R_CRB_CONTROL_START Bits
106 //
107 #define B_CRB_CONTROL_START 0x00000001 ///< BIT0
108
109 //
110 // R_TPM_LOCALITY_STATUS Bits
111 //
112 #define B_CRB_LOCALITY_STS_GRANTED 0x00000001 ///< BIT0
113 #define B_CRB_LOCALITY_STS_BEEN_SEIZED 0x00000002 ///< BIT1
114
115 //
116 // R_TPM_LOCALITY_CONTROL Bits
117 //
118 #define B_CRB_LOCALITY_CTL_REQUEST_ACCESS 0x00000001 ///< BIT0
119 #define B_CRB_LOCALITY_CTL_RELINQUISH 0x00000002 ///< BIT1
120 #define B_CRB_LOCALITY_CTL_SEIZE 0x00000004 ///< BIT2
121
122 //
123 // R_PTT_LOCALITY_STATE Bits
124 //
125 #define B_CRB_LOCALITY_STATE_TPM_ESTABLISHED 0x00000001 ///< BIT0
126 #define B_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED 0x00000002 ///< BIT1
127 #define B_CRB_LOCALITY_STATE_REGISTER_VALID 0x00000080 ///< BIT7
128
129 //
130 // R_PTT_LOCALITY_STATE Mask Values
131 //
132 #define V_CRB_LOCALITY_STATE_ACTIVE_LOC_MASK 0x0000001C /// Bits [4:2]
133
134 //
135 // R_PTT_RESERVED
136 //
137 #define B_PTT_RESERVED_BIT 0x00080000 /// Bit [19]
138
139 //
140 // Value written to R_PTT_HCI_CMD and CA_START
141 // to indicate that a command is available for processing
142 //
143 #define V_PTT_HCI_COMMAND_AVAILABLE_START 0x00000001
144 #define V_PTT_HCI_COMMAND_AVAILABLE_CMD 0x00000000
145 #define V_PTT_HCI_BUFFER_ADDRESS_RDY 0x00000003
146
147 ///
148 /// Ignore bit setting mask for WaitRegisterBits
149 ///
150 #define V_PTT_HCI_IGNORE_BITS 0x00000000
151
152 ///
153 /// All bits clear mask for WaitRegisterBits
154 ///
155 #define V_PTT_HCI_ALL_BITS_CLEAR 0xFFFFFFFF
156 #define V_PTT_HCI_START_CLEAR 0x00000001
157
158 ///
159 /// Max FTPM command/response buffer length
160 ///
161 #define S_PTT_HCI_CRB_LENGTH 3968 ///< 0xFED40080:0xFED40FFF = 3968 Bytes
162
163 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ResetSystemLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ResetSystemLib.h File Reference

System reset Library Services. More...

Go to the source code of this file.

Functions

VOID | ResetCold (VOID)
This function causes a system-wide reset (cold reset), in which all circuitry within the system returns to its initial state. More...
VOID | ResetWarm (VOID)
This function causes a system-wide initialization (warm reset), in which all processors are set to their initial state. More...
VOID | ResetShutdown (VOID)
This function causes the system to enter a power state equivalent to the ACPI G2/S5 or G3 states. More...
VOID | EnterS3WithImmediateWake (VOID)
This function causes the system to enter S3 and then wake up immediately. More...
VOID | ResetPlatformSpecific (IN UINTN DataSize, IN VOID *ResetData)
This function causes a systemwide reset. More...

Detailed Description

System reset Library Services.

This library class defines a set of methods that reset the whole system.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file ResetSystemLib.h.

Function Documentation

◆ EnterS3WithImmediateWake()

VOID EnterS3WithImmediateWake ( VOID )

This function causes the system to enter S3 and then wake up immediately.

If this function returns, it means that the system does not support S3 feature.

◆ ResetCold()

VOID ResetCold ( VOID )

This function causes a system-wide reset (cold reset), in which all circuitry within the system returns to its initial state.

This type of reset is asynchronous to system operation and operates without regard to cycle boundaries.

If this function returns, it means that the system does not support cold reset.

◆ ResetPlatformSpecific()

VOID ResetPlatformSpecific | ( | IN UINTN | DataSize,
 |  | IN VOID * | ResetData
 | ) |  |

This function causes a systemwide reset.

The exact type of the reset is defined by the EFI_GUID that follows the Null-terminated Unicode string passed into ResetData. If the platform does not recognize the EFI_GUID in ResetData the platform must pick a supported reset type to perform.The platform may optionally log the parameters from any non-normal reset that occurs.

Parameters
[in] | DataSize | The size, in bytes, of ResetData.
[in] | ResetData | The data buffer starts with a Null-terminated string, followed by the EFI_GUID.

◆ ResetShutdown()

VOID ResetShutdown ( VOID )

This function causes the system to enter a power state equivalent to the ACPI G2/S5 or G3 states.

If this function returns, it means that the system does not support shutdown reset.

◆ ResetWarm()

VOID ResetWarm ( VOID )

This function causes a system-wide initialization (warm reset), in which all processors are set to their initial state.

Pending cycles are not corrupted.

If this function returns, it means that the system does not support warm reset.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ResetSystemLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ResetSystemLib.h
Go to the documentation of this file.
1 /** @file
2 System reset Library Services. This library class defines a set of
3 methods that reset the whole system.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License that accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php.
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef __RESET_SYSTEM_LIB_H__
19 #define __RESET_SYSTEM_LIB_H__
20
21 /**
22 This function causes a system-wide reset (cold reset), in which
23 all circuitry within the system returns to its initial state. This type of reset
24 is asynchronous to system operation and operates without regard to
25 cycle boundaries.
26
27 If this function returns, it means that the system does not support cold reset.
28 **/
29 VOID
30 EFIAPI
31 ResetCold (
32 VOID
33 );
34
35 /**
36 This function causes a system-wide initialization (warm reset), in which all processors
37 are set to their initial state. Pending cycles are not corrupted.
38
39 If this function returns, it means that the system does not support warm reset.
40 **/
41 VOID
42 EFIAPI
43 ResetWarm (
44 VOID
45 );
46
47 /**
48 This function causes the system to enter a power state equivalent
49 to the ACPI G2/S5 or G3 states.
50
51 If this function returns, it means that the system does not support shutdown reset.
52 **/
53 VOID
54 EFIAPI
55 ResetShutdown (
56 VOID
57 );
58
59 /**
60 This function causes the system to enter S3 and then wake up immediately.
61
62 If this function returns, it means that the system does not support S3 feature.
63 **/
64 VOID
65 EFIAPI
66 EnterS3WithImmediateWake (
67 VOID
68 );
69
70 /**
71 This function causes a systemwide reset. The exact type of the reset is
72 defined by the EFI_GUID that follows the Null-terminated Unicode string passed
73 into ResetData. If the platform does not recognize the EFI_GUID in ResetData
74 the platform must pick a supported reset type to perform.The platform may
75 optionally log the parameters from any non-normal reset that occurs.
76
77 @param[in] DataSize The size, in bytes, of ResetData.
78 @param[in] ResetData The data buffer starts with a Null-terminated string,
79 followed by the EFI_GUID.
80 **/
81 VOID
82 EFIAPI
83 ResetPlatformSpecific (
84 IN UINTN DataSize,
85 IN VOID *ResetData
86 );
87
88 #endif
ResetShutdown
VOID ResetShutdown(VOID)
This function causes the system to enter a power state equivalent to the ACPI G2/S5 or G3 states.
ResetPlatformSpecific
VOID ResetPlatformSpecific(IN UINTN DataSize, IN VOID *ResetData)
This function causes a systemwide reset.
EnterS3WithImmediateWake
VOID EnterS3WithImmediateWake(VOID)
This function causes the system to enter S3 and then wake up immediately.
ResetWarm
VOID ResetWarm(VOID)
This function causes a system-wide initialization (warm reset), in which all processors are set to th...
ResetCold
VOID ResetCold(VOID)
This function causes a system-wide reset (cold reset), in which all circuitry within the system retur...
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RstConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
Classes
RstConfig.h File Reference

Rst policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
Include dependency graph for RstConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use this feature, Intel RST Driver is required. More...
struct | RST_CONFIG
Rapid Storage Technology settings. More...

Detailed Description

Rst policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RstConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RstConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
RstConfig.h
Go to the documentation of this file.
1 /** @file
2 Rst policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RST_CONFIG_H_
36 #define _RST_CONFIG_H_
37 #include <PchLimits.h>
38 #include <ConfigBlock.h>
39
40 #define RST_CONFIG_REVISION 1
41 extern EFI_GUID gRstConfigGuid;
42
43 #pragma pack (push,1)
44
45 typedef enum {
46 SataOromDelay2sec,
47 SataOromDelay4sec,
48 SataOromDelay6sec,
49 SataOromDelay8sec
50 } SATA_OROM_DELAY;
51
52 /**
53 This structure describes the details of Intel RST for PCIe Storage remapping
54 Note: In order to use this feature, Intel RST Driver is required
55 **/
56 typedef struct {
57 /**
58 This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
59 Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
60 Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
61 **/
62 UINT32 Enable : 1;
63 /**
64 Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
65 The supported ports for PCIe Storage remapping is different depend on the platform and cycle router
66 **/
67 UINT32 RstPcieStoragePort : 5;
68 /**
69 PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
70 before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
71 Default value is <b>100ms</b>.
72 **/
73 UINT32 DeviceResetDelay : 8;
74 UINT32 RsvdBits0 : 18; ///< Reserved bits
75
76 } RST_HARDWARE_REMAPPED_STORAGE_CONFIG;
77
78 /**
79 Rapid Storage Technology settings.
80
81 <b>Revision 1</b>:
82 - Initial version.
83 **/
84 typedef struct {
85 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
86
87 UINT32 Raid0 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID0
88 UINT32 Raid1 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID1
89 UINT32 Raid10 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID10
90 UINT32 Raid5 : 1; ///< 0 : Disable; <b>1 : Enable</b> RAID5
91 UINT32 Irrt : 1; ///< 0 : Disable; <b>1 : Enable</b> Intel Rapid Recovery Technology
92 UINT32 OromUiBanner : 1; ///< 0 : Disable; <b>1 : Enable</b> OROM UI and BANNER
93 UINT32 OromUiDelay : 2; ///< <b>00b : 2 secs</b>; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
94 UINT32 HddUnlock : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the HDD password unlock in the OS is enabled
95 UINT32 LedLocate : 1; ///< 0 : Disable; <b>1 : Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
96 UINT32 IrrtOnly : 1; ///< 0 : Disable; <b>1 : Enable</b>. Allow only IRRT drives to span internal and external ports
97 UINT32 SmartStorage : 1; ///< 0 : Disable; <b>1 : Enable</b> RST Smart Storage caching Bit
98 UINT32 LegacyOrom : 1; ///< <b>0 : Disable</b>; 1 : Enable RST Legacy OROM
99 UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
100 UINT32 CpuAttachedStorage : 1; ///< 0: Disable; <b>1: Enable</b> CPU Attached Storage
101 UINT32 RsvdBits0 : 17; ///< Reserved Bits
102 /**
103 This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
104 Note: RST for PCIe Sorage remapping is supported only for first SATA controller if more controllers are available
105 **/
106 RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
107 } RST_CONFIG;
108
109 #pragma pack (pop)
110 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
RST_CONFIG::OromUiBanner
UINT32 OromUiBanner
0 : Disable; 1 : Enable OROM UI and BANNER
Definition: RstConfig.h:92
RST_CONFIG::LegacyOrom
UINT32 LegacyOrom
0 : Disable; 1 : Enable RST Legacy OROM
Definition: RstConfig.h:98
RST_CONFIG::HddUnlock
UINT32 HddUnlock
0 : Disable; 1 : Enable. Indicates that the HDD password unlock in the OS is enabled
Definition: RstConfig.h:94
RST_CONFIG::SmartStorage
UINT32 SmartStorage
0 : Disable; 1 : Enable RST Smart Storage caching Bit
Definition: RstConfig.h:97
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::DeviceResetDelay
UINT32 DeviceResetDelay
PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled...
Definition: RstConfig.h:73
RST_CONFIG::CpuAttachedStorage
UINT32 CpuAttachedStorage
0: Disable; 1: Enable CPU Attached Storage
Definition: RstConfig.h:100
RST_HARDWARE_REMAPPED_STORAGE_CONFIG
This structure describes the details of Intel RST for PCIe Storage remapping Note: In order to use th...
Definition: RstConfig.h:56
RST_CONFIG::Raid10
UINT32 Raid10
0 : Disable; 1 : Enable RAID10
Definition: RstConfig.h:89
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RST_CONFIG
Rapid Storage Technology settings.
Definition: RstConfig.h:84
RST_CONFIG::Raid0
UINT32 Raid0
0 : Disable; 1 : Enable RAID0
Definition: RstConfig.h:87
RST_CONFIG::LedLocate
UINT32 LedLocate
0 : Disable; 1 : Enable. Indicates that the LED/SGPIO hardware is attached and ping to locate feature...
Definition: RstConfig.h:95
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RstPcieStoragePort
UINT32 RstPcieStoragePort
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect) The supported po...
Definition: RstConfig.h:67
RST_CONFIG::IrrtOnly
UINT32 IrrtOnly
0 : Disable; 1 : Enable. Allow only IRRT drives to span internal and external ports
Definition: RstConfig.h:96
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::Enable
UINT32 Enable
This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled.
Definition: RstConfig.h:62
RST_CONFIG::OptaneMemory
UINT32 OptaneMemory
0: Disable; 1: Enable RST Optane(TM) Memory
Definition: RstConfig.h:99
RST_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved Bits.
Definition: RstConfig.h:101
RST_CONFIG::Irrt
UINT32 Irrt
0 : Disable; 1 : Enable Intel Rapid Recovery Technology
Definition: RstConfig.h:91
RST_HARDWARE_REMAPPED_STORAGE_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: RstConfig.h:74
RST_CONFIG::OromUiDelay
UINT32 OromUiDelay
00b : 2 secs; 01b : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)
Definition: RstConfig.h:93
RST_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RstConfig.h:85
RST_CONFIG::Raid1
UINT32 Raid1
0 : Disable; 1 : Enable RAID1
Definition: RstConfig.h:88
RST_CONFIG::Raid5
UINT32 Raid5
0 : Disable; 1 : Enable RAID5
Definition: RstConfig.h:90
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RstCrLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
RstCrLib.h File Reference

Header file for RstCrLib. More...

Go to the source code of this file.

Functions

UINT8 RstGetCycleRouterNumber (IN UINT32 RootPortNum)
Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type. More...

Detailed Description

Header file for RstCrLib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RstCrLib.h.

Function Documentation

◆ RstGetCycleRouterNumber()

UINT8 RstGetCycleRouterNumber ( IN UINT32 RootPortNum )

Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type.

Parameters
[in] RootPortNum Root Port Number
Returns
The RST PCIe Storage Cycle Router Number
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RstCrLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
RstCrLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for RstCrLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RST_CR_LIB_H_
36 #define _RST_CR_LIB_H_
37
38 #define RST_PCIE_STORAGE_CR_1 0
39 #define RST_PCIE_STORAGE_CR_2 1
40 #define RST_PCIE_STORAGE_CR_3 2
41 #define RST_PCIE_STORAGE_CR_INVALID 99
42
43 /**
44 Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type
45
46 @param[in] RootPortNum Root Port Number
47
48 @return The RST PCIe Storage Cycle Router Number
49 **/
50 UINT8
51 RstGetCycleRouterNumber (
52 IN UINT32 RootPortNum
53 );
54 #endif
RstGetCycleRouterNumber
UINT8 RstGetCycleRouterNumber(IN UINT32 RootPortNum)
Check the RST PCIe Storage Cycle Router number according to the root port number and PCH type.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
RtcAccessLib.h File Reference

RTC library header for abstraction of RTC PCR registers access. More...

Go to the source code of this file.

Functions

BOOLEAN RtcIsBiosInterfaceLock (VOID)
Check RTC BIOS interface is locked. More...

Detailed Description

RTC library header for abstraction of RTC PCR registers access.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RtcAccessLib.h.

Function Documentation

◆ RtcIsBiosInterfaceLock()

BOOLEAN RtcIsBiosInterfaceLock ( VOID )

Check RTC BIOS interface is locked.

Return values
TRUE RTC BIOS interface is locked FALSE RTC BIOS interface is not locked
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
RtcAccessLib.h
Go to the documentation of this file.
1 /** @file
2 RTC library header for abstraction of RTC PCR registers access
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RTC_ACCESS_LIB_H_
36 #define _RTC_ACCESS_LIB_H_
37
38 /**
39 Check RTC BIOS interface is locked
40
41 @retval TRUE RTC BIOS interface is locked
42 FALSE RTC BIOS interface is not locked
43 **/
44 BOOLEAN
45 RtcIsBiosInterfaceLock (
46 VOID
47 );
48
49 #endif // _RTC_ACCESS_LIB_H_
50
RtcIsBiosInterfaceLock
BOOLEAN RtcIsBiosInterfaceLock(VOID)
Check RTC BIOS interface is locked.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Classes
RtcConfig.h File Reference

RTC policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration. More...

Detailed Description

RTC policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RtcConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
RtcConfig.h
Go to the documentation of this file.
1 /** @file
2 RTC policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _RTC_CONFIG_H_
36 #define _RTC_CONFIG_H_
37
38 #define RTC_CONFIG_REVISION 1
39 extern EFI_GUID gRtcConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 The RTC_CONFIG block describes the expected configuration of RTC configuration.
45 **/
46 typedef struct {
47 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
48 /**
49 When set, prevents RTC TS (BUC.TS) from being changed.
50 This BILD bit has different function compared to LPC/eSPI, SPI.
51 0: Disabled; <b>1: Enabled</b>
52 **/
53 UINT32 BiosInterfaceLock : 1;
54 /**
55 When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
56 and cannot be accessed.
57 Writes will be droipped and reads will not return any guaranteed data.
58 0: Disabled; <b>1: Enabled</b>
59 **/
60 UINT32 MemoryLock : 1;
61 UINT32 RsvdBits0 : 30;
62 } RTC_CONFIG;
63
64 #pragma pack (pop)
65
66 #endif // _RTC_CONFIG_H_
RTC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: RtcConfig.h:47
RTC_CONFIG
The RTC_CONFIG block describes the expected configuration of RTC configuration.
Definition: RtcConfig.h:46
RTC_CONFIG::BiosInterfaceLock
UINT32 BiosInterfaceLock
When set, prevents RTC TS (BUC.TS) from being changed.
Definition: RtcConfig.h:53
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
RTC_CONFIG::MemoryLock
UINT32 MemoryLock
When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked and cannot be accessed.
Definition: RtcConfig.h:60
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
RtcRegs.h File Reference

Register names for RTC device. More...

Go to the source code of this file.

Macros

#define | R_RTC_PCR_CONF 0x3400
RTC Configuration register.
#define | B_RTC_PCR_CONF_BILD BIT31
BIOS Interface Lock-Down.
#define | B_RTC_PCR_CONF_HPM_HW_DIS BIT6
RTC High Power Mode HW Disable.
#define | B_RTC_PCR_CONF_UCMOS_LOCK BIT4
Upper 128 Byte Lock.
#define | B_RTC_PCR_CONF_LCMOS_LOCK BIT3
Lower 128 Byte Lock.
#define | B_RTC_PCR_CONF_UCMOS_EN BIT2
Upper CMOS bank enable.
#define | R_RTC_PCR_BUC 0x3414
Backed Up Control.
#define | B_RTC_PCR_BUC_DSO BIT4
Daylight Savings Override.
#define | B_RTC_PCR_BUC_TS BIT0
Top Swap.
#define | R_RTC_PCR_RTCDCG 0x3418
RTC Dynamic Clock Gating Control.
#define | B_RTC_PCR_RTCDCG_RTCPGCBDCGEN BIT2
pgcb_clk (12Mhz) Dynamic Clock Gate Enable
#define | B_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1
ipciclk_clk (24 MHz) Dynamic Clock Gate Enable
#define | B_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0
rosc_side_clk (120 MHz) Dynamic Clock Gate Enable

Detailed Description

Register names for RTC device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file RtcRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): RtcRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
RtcRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for RTC device
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2018 - 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _REGS_RTC_H_
65 #define _REGS_RTC_H_
66
67 #define R_RTC_IO_INDEX 0x70
68 #define R_RTC_IO_TARGET 0x71
69 #define R_RTC_IO_EXT_INDEX 0x72
70 #define R_RTC_IO_EXT_TARGET 0x73
71 #define R_RTC_IO_INDEX_ALT 0x74
72 #define R_RTC_IO_TARGET_ALT 0x75
73 #define R_RTC_IO_EXT_INDEX_ALT 0x76
74 #define R_RTC_IO_EXT_TARGET_ALT 0x77
75 #define R_RTC_IO_REGA 0x0A
76 #define B_RTC_IO_REGA_UIP BIT7
77 #define R_RTC_IO_REGB 0x0B
78 #define B_RTC_IO_REGB_SET 0x80
79 #define B_RTC_IO_REGB_PIE 0x40
80 #define B_RTC_IO_REGB_AIE 0x20
81 #define B_RTC_IO_REGB_UIE 0x10
82 #define B_RTC_IO_REGB_DM 0x04
83 #define B_RTC_IO_REGB_HOURFORM 0x02
84 #define R_RTC_IO_REGC 0x0C
85 #define R_RTC_IO_REGD 0x0D
86
87 //
88 // Private Configuration Register
89 // RTC PCRs (PID:RTC)
90 //
91 #define R_RTC_PCR_CONF 0x3400 ///< RTC Configuration register
92 #define B_RTC_PCR_CONF_BILD BIT31 ///< BIOS Interface Lock-Down
93 #define B_RTC_PCR_CONF_HPM_HW_DIS BIT6 ///< RTC High Power Mode HW Disable
94 #define B_RTC_PCR_CONF_UCMOS_LOCK BIT4 ///< Upper 128 Byte Lock
95 #define B_RTC_PCR_CONF_LCMOS_LOCK BIT3 ///< Lower 128 Byte Lock
96 #define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///< Upper CMOS bank enable
97 #define R_RTC_PCR_BUC 0x3414 ///< Backed Up Control
98 #define B_RTC_PCR_BUC_DSO BIT4 ///< Daylight Savings Override
99 #define B_RTC_PCR_BUC_TS BIT0 ///< Top Swap
100 #define R_RTC_PCR_RTCDCG 0x3418 ///< RTC Dynamic Clock Gating Control
101 #define B_RTC_PCR_RTCDCG_RTCPGCBDCGEN BIT2 ///< pgcb_clk (12Mhz) Dynamic Clock Gate Enable
102 #define B_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ipciclk_clk (24 MHz) Dynamic Clock Gate Enable
103 #define B_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0 ///< rosc_side_clk (120 MHz) Dynamic Clock Gate Enable
104 #define R_RTC_PCR_3F00 0x3F00
105
106 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Classes
SaDataHob.h File Reference

The GUID definition for SaDataHob. More...

#include <Base.h>
#include <CpuPcieInfo.h>
#include <Library/PcdLib.h>
Include dependency graph for SaDataHob.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SA_DATA_HOB
System Agent Data Hob. More...

Detailed Description

The GUID definition for SaDataHob.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaDataHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
SaDataHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for SaDataHob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_DATA_HOB_H_
36 #define _SA_DATA_HOB_H_
37
38 #include <Base.h>
39 #include <CpuPcieInfo.h>
40 #include <Library/PcdLib.h>
41
42 extern EFI_GUID gSaDataHobGuid;
43 #pragma pack (push,1)
44
45 ///
46 /// System Agent Data Hob
47 ///
48 typedef struct {
49 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaDataHobGuid
50 UINT8 PrimaryDisplay;
51 BOOLEAN ResizableBarSupport; ///< Resizable BAR Support
52 UINT8 Rsvd1[2]; ///< Reserved for future use
53 } SA_DATA_HOB;
54
55 #pragma pack (pop)
56 #endif
SA_DATA_HOB
System Agent Data Hob.
Definition: SaDataHob.h:48
SA_DATA_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
GUID Hob type structure for gSaDataHobGuid.
Definition: SaDataHob.h:49
SA_DATA_HOB::ResizableBarSupport
BOOLEAN ResizableBarSupport
Resizable BAR Support.
Definition: SaDataHob.h:51
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaMiscPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
SaMiscPeiConfig.h File Reference

Policy details for miscellaneous configuration in System Agent. More...

Go to the source code of this file.

Classes

struct SA_MISC_PEI_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem. More...

Detailed Description

Policy details for miscellaneous configuration in System Agent.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaMiscPeiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaMiscPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
SaMiscPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy details for miscellaneous configuration in System Agent
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_MISC_PEI_CONFIG_H_
36 #define _SA_MISC_PEI_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 #define SA_MISC_PEI_CONFIG_REVISION 1
41
42 /**
43 This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.\n
44 <b>Revision 1</b>:
45 - Initial version.
46 **/
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
49 } SA_MISC_PEI_CONFIG;
50 #pragma pack(pop)
51
52 #endif // _SA_MISC_PEI_CONFIG_H_
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SA_MISC_PEI_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Post-Mem.
Definition: SaMiscPeiConfig.h:47
SA_MISC_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: SaMiscPeiConfig.h:48
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaMiscPeiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
Classes
SaMiscPeiPreMemConfig.h File Reference

Policy details for miscellaneous configuration in System Agent. More...

Go to the source code of this file.

Classes

struct SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming different System Agent BARs, TsegSize, MmioSize required etc. More...

Detailed Description

Policy details for miscellaneous configuration in System Agent.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaMiscPeiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaMiscPeiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
SaMiscPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Policy details for miscellaneous configuration in System Agent
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_
36 #define _SA_MISC_PEI_PREMEM_CONFIG_H_
37
38 #pragma pack(push, 1)
39
40 #ifndef MEM_CFG_MAX_SOCKETS
41 #define MEM_CFG_MAX_SOCKETS 16
42 #endif
43
44 #define SA_MISC_PEI_PREMEM_CONFIG_REVISION 5
45
46 /**
47 This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like programming
48 different System Agent BARs, TsegSize, MmioSize required etc.
49 <b>Revision 1</b>:
50 - Initial version.
51 <b>Revision 2</b>:
52 - Deprecate IedSize.
53 <b>Revision 3</b>:
54 - Adding ResizableBarSupport.
55 **/
56 typedef struct {
57 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
58 /**
59 Offset 28 Memory DIMMs' SPD address for reading SPD data.
60 TGL Mapping
61 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
62 1 - Controller 0 Channel 0 Dimm 1 - DDR4
63 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
64 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC
65 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
66 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
67 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5
68 9 - Controller 1 Channel 0 Dimm 1 - DDR4
69 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5
70 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC
71 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5
72 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5
73 **/
74 UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS];
75 VOID *S3DataPtr; ///< Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled with proper S3 resume data on a resume path
76 UINT32 SmbusBar; ///< Offset 48 Address of System Agent SMBUS BAR: <b>0xEFA0</b>
77 /**
78 Offset 52 Size of TSEG in bytes. (Must be power of 2)
79 <b>0x400000</b>: 4MB for Release build (When IED enabled, it will be 8MB)
80 0x1000000 : 16MB for Debug build (Regardless IED enabled or disabled)
81 **/
82 UINT32 TsegSize;
83 /**
84 Offset 56
85 <b>(Test)</b> Size of IED region in bytes.
86 <b>0</b> : IED Disabled (no memory occupied)
87 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG)
88 <b>Note: Enabling IED may also enlarge TsegSize together.</b>
89 @deprecated
90 **/
91 UINT32 IedSize;
92 UINT32 SkipExtGfxScan:1; ///< <b>(Test)</b> OFfset 60:0 :1=Skip External Gfx Device Scan; <b>0=Scan for external graphics devices</b>. Set this policy to skip External Graphics card scanning if the platform uses Internal Graphics only.
93 UINT32 BdatEnable:1; ///< Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: <b>0=FALSE</b>, 1=TRUE.
94 UINT32 TxtImplemented:1; ///< OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin completed: <b>0=Run without waiting for TXT</b>, 1=Run after TXT initialization by callback
95 /**
96 Offset 60:3 :
97 <b>(Test)</b> Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs
98
99 When enabled, if the primary graphics device is an external discrete graphics device, Si will scan the
100 graphics device for legacy only VGA OpROMs.
101
102 This is intended to ease the implementation of a BIOS feature to automatically enable CSM if the Primary Gfx device
103 only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling CSM won't result in no video being displayed.
104 This is useful for platforms that implement PCIe slots that allow the end user to install an arbitrary Gfx device.
105
106 This setting will only take effect if SkipExtGfxScan == 0. It is ignored otherwise.
107
108 - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Default)
109 - <b>Enabled</b> (0x1) : Scan External Gfx for Legacy Only VGA OpROM
110 **/
111 UINT32 ScanExtGfxForLegacyOpRom:1;
112 UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved for future use
113 UINT8 UserBd; ///< Offset 64 <b>0=Mobile/Mobile Halo</b>, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3, 6=ULT/ULX/Mobile Halo Type4, 8=UP Server
114 UINT8 LockPTMregs; ///< <b>(Test)</b> Offset 65 Lock PCU Thermal Management registers: 0=FALSE, <b>1=TRUE</b>
115 UINT8 BdatTestType; ///< Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populated in the BIOS Data ACPI Tables: <b>0=RMT</b>, 1=RMT Per Bit, 2=Margin 2D.
116 UINT8 CridEnable; ///< Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibility Revision ID (CRID) feature: <b>0=FALSE</b>, 1=TRUE
117 UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
118 UINT32 OpRomScanTempMmioBar; ///< <b>(Test)</b> Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!
119 UINT32 OpRomScanTempMmioLimit; ///< <b>(Test)</b> Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >= 16MB!
120 UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used. Originally it is retrieved from AcpiVariableCompatibility variable.
121 UINT64 SystemMemoryLength; ///< Offset 88 Total system memory length from previous boot, this is required for S3 resume. Originally it is retrieved from AcpiVariableCompatibility variable.
122
123 UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocating onto the ring and into LLC.
124 UINT8 FirstDimmBitMask; ///< Offset 97: Defines which DIMM should be populated first on a 2DPC board.
125 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
126 ///< For each MC, the first DIMM to be populated should be set to '1'.
127 ///< Note: this mask is only for non-ECC DIMM.
128 UINT8 FirstDimmBitMaskEcc; ///< Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.
129 ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
130 ///< For each MC, the first DIMM to be populated should be set to '1'.
131 ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
132 ///< be populated firstly.
133 ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
134
135 UINT8 Reserved1[1]; ///< Reserved for config block alignment.
136
137
138 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
139 UINT8 Rsvd[4]; ///< Reserved for config block alignment.
140 UINT8 ResizableBarSupport;
141
142 UINT8 Rsrvd1[7];
143 } SA_MISC_PEI_PREMEM_CONFIG;
144 #pragma pack(pop)
145
146 #endif // _SA_MISC_PEI_PREMEM_CONFIG_H_
SA_MISC_PEI_PREMEM_CONFIG::BdatTestType
UINT8 BdatTestType
Offset 66 When BdatEnable is set to TRUE, this option selects the type of data which will be populate...
Definition: SaMiscPeiPreMemConfig.h:115
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioLimit
UINT32 OpRomScanTempMmioLimit
(Test) Offset 76 Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feature....
Definition: SaMiscPeiPreMemConfig.h:119
SA_MISC_PEI_PREMEM_CONFIG::UserBd
UINT8 UserBd
Offset 64 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 2=Desktop 2DPC DDR5, 5=ULT/ULX/Mobile Halo Type3,...
Definition: SaMiscPeiPreMemConfig.h:113
SA_MISC_PEI_PREMEM_CONFIG::SystemMemoryLength
UINT64 SystemMemoryLength
Offset 88 Total system memory length from previous boot, this is required for S3 resume....
Definition: SaMiscPeiPreMemConfig.h:121
SA_MISC_PEI_PREMEM_CONFIG::LockPTMregs
UINT8 LockPTMregs
(Test) Offset 65 Lock PCU Thermal Management registers: 0=FALSE, 1=TRUE
Definition: SaMiscPeiPreMemConfig.h:114
SA_MISC_PEI_PREMEM_CONFIG::OpRomScanTempMmioBar
UINT32 OpRomScanTempMmioBar
(Test) Offset 72 Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExtGfxForLega...
Definition: SaMiscPeiPreMemConfig.h:118
SA_MISC_PEI_PREMEM_CONFIG::SmbusBar
UINT32 SmbusBar
Offset 48 Address of System Agent SMBUS BAR: 0xEFA0
Definition: SaMiscPeiPreMemConfig.h:76
SA_MISC_PEI_PREMEM_CONFIG::S3DataPtr
VOID * S3DataPtr
Offset 44 Memory data save pointer for S3 resume. The memory space should be allocated and filled wit...
Definition: SaMiscPeiPreMemConfig.h:75
SA_MISC_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: SaMiscPeiPreMemConfig.h:57
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SA_MISC_PEI_PREMEM_CONFIG::IedSize
UINT32 IedSize
Offset 56 (Test) Size of IED region in bytes.
Definition: SaMiscPeiPreMemConfig.h:91
SA_MISC_PEI_PREMEM_CONFIG::TsegSize
UINT32 TsegSize
Offset 52 Size of TSEG in bytes.
Definition: SaMiscPeiPreMemConfig.h:82
SA_MISC_PEI_PREMEM_CONFIG::BdatEnable
UINT32 BdatEnable
Offset 60:1 :This field enables the generation of the BIOS DATA ACPI Tables: 0=FALSE,...
Definition: SaMiscPeiPreMemConfig.h:93
SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMask
UINT8 FirstDimmBitMask
Offset 97: Defines which DIMM should be populated first on a 2DPC board.
Definition: SaMiscPeiPreMemConfig.h:124
SA_MISC_PEI_PREMEM_CONFIG::ScanExtGfxForLegacyOpRom
UINT32 ScanExtGfxForLegacyOpRom
Offset 60:3 : (Test) Scan External Discrete Graphics Devices for Legacy Only VGA OpROMs.
Definition: SaMiscPeiPreMemConfig.h:111
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemorySize
UINT32 AcpiReservedMemorySize
Offset 68 The Size of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:117
SA_MISC_PEI_PREMEM_CONFIG::FirstDimmBitMaskEcc
UINT8 FirstDimmBitMaskEcc
Offset 98: Defines which ECC DIMM should be populated first on a 2DPC board.
Definition: SaMiscPeiPreMemConfig.h:128
SA_MISC_PEI_PREMEM_CONFIG::WrcFeatureEnable
UINT8 WrcFeatureEnable
Offset 96: Enable/Disable WRC (Write Cache) feature of IOP. When enabled, supports IO devices allocat...
Definition: SaMiscPeiPreMemConfig.h:123
SA_MISC_PEI_PREMEM_CONFIG
This configuration block is to configure SA Miscellaneous variables during PEI Pre-Mem phase like pro...
Definition: SaMiscPeiPreMemConfig.h:56
SA_MISC_PEI_PREMEM_CONFIG::AcpiReservedMemoryBase
UINT64 AcpiReservedMemoryBase
Offset 80 The Base address of a Reserved memory buffer allocated in previous boot for S3 resume used....
Definition: SaMiscPeiPreMemConfig.h:120
SA_MISC_PEI_PREMEM_CONFIG::TxtImplemented
UINT32 TxtImplemented
OFfset 60:2 :This field currently is used to tell MRC if it should run after TXT initializatoin compl...
Definition: SaMiscPeiPreMemConfig.h:94
SA_MISC_PEI_PREMEM_CONFIG::CridEnable
UINT8 CridEnable
Offset 67 For Platforms supporting Intel(R) SIPP, this policy is use control enable/disable Compatibi...
Definition: SaMiscPeiPreMemConfig.h:116
SA_MISC_PEI_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Offset 60:4 :Reserved for future use.
Definition: SaMiscPeiPreMemConfig.h:112
SA_MISC_PEI_PREMEM_CONFIG::SkipExtGfxScan
UINT32 SkipExtGfxScan
(Test) OFfset 60:0 :1=Skip External Gfx Device Scan; 0=Scan for external graphics devices....
Definition: SaMiscPeiPreMemConfig.h:92
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPcieDmiRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
SaPcieDmiRegs.h File Reference

Register names for SA DMI and PEG. More...

Go to the source code of this file.

Macros

#define | R_SA_PEG_DID_OFFSET 0x02
Device 1 Register Equates. More...
#define | R_SA_PEG_BCTRL_OFFSET 0x3E
Bridge Control.
#define | R_SA_PEG_SS_OFFSET 0x8C
Subsystem ID.
#define | R_SA_PEG_LCTL_OFFSET 0xB0
Link Control.
#define | R_SA_PEG_LSTS_OFFSET 0xB2
Link Status.
#define | R_SA_PEG_SLOTSTS_OFFSET 0xBA
Slot Status.
#define | R_SA_PEG_DCAP2_OFFSET 0xC4
Device Capability 2.
#define | R_SA_PEG_DCTL2_OFFSET 0xC8
Device Control 2.
#define | R_SA_PEG_VC0RSTS_OFFSET 0x11A
PEG VC0 Resource Status.
#define | R_SA_PEG_L0SLAT_OFFSET 0x22C
PEG L0s Control.
#define | R_SA_PEG_CFG4_OFFSET 0x258
PEG Config 4.
#define | R_SA_PEG_EQPH3_OFFSET 0x384
PEG Phase 3.
#define | R_SA_PEG_AFEBND0CFG1_OFFSET 0x904
PEG AFE Bundle Config 1.
#define | R_SA_PEG_AFEBND0CFG2_OFFSET 0x908
PEG AFE Bundle Config 2.
#define | R_SA_PEG_AFEBND0CFG3_OFFSET 0x90C
PEG AFE Bundle Config 3.
#define | R_SA_PEG_AFEBND0CFG4_OFFSET 0x910
PEG AFE Bundle Config 4.
#define | R_SA_PEG_G3CTL0_OFFSET 0x918
PEG Gen3 Control.
#define | R_SA_PEG_BND0SPARE_OFFSET 0x91C
PEG Bundle 0 Spare Register.
#define | R_SA_PEG_AFELN0CFG0_OFFSET 0xA00
PEG AFE Lane Config 0.
#define | R_SA_PEG_AFELN0CFG1_OFFSET 0xA04
PEG AFE Lane Config 1.
#define | R_SA_PEG_AFEOVR_OFFSET 0xC20
PEG AFE Override.
#define | R_SA_PEG_CMNSPARE_OFFSET 0xC38
PEG Common Spare.
#define | R_SA_PEG_LCTL3_OFFSET 0xD98
PEG Link Control 3.
#define | R_SA_PEG_EQCTL0_1_OFFSET 0xDA0
PEG Lane Equalization.
#define | R_SA_PEG_EQPRESET1_2_OFFSET 0xDC0
PEG Coefficients for P1 and P2.
#define | R_SA_PEG_EQPRESET2_3_4_OFFSET 0xDC4
PEG Coefficients for P2, P3, and P4.
#define | R_SA_PEG_EQPRESET4_5_OFFSET 0xDC8
PEG Coefficients for P4 and P5.
#define | R_SA_PEG_EQPRESET6_7_OFFSET 0xDCC
PEG Coefficients for P6 and P7.
#define | R_SA_PEG_EQPRESET7_8_9_OFFSET 0xDD0
PEG Coefficients for P7, P8, and P9.
#define | R_SA_PEG_EQPRESET9_10_OFFSET 0xDD4
PEG Coefficients for P9 and P10.
#define | R_SA_PEG_EQCFG_OFFSET 0xDD8
PEG Equalization Config.
#define | R_SA_PEG_EQPRESET11_OFFSET 0xDDC
PEG Coefficients for P11.
#define | R_SA_PEG_BND10_CRI2_FUSE_DWORD14_OFFSET 0x2338
PEG Bundle 10(DMI) CRI2 FUSE register DWORD 14.
#define | R_SA_PEG_BND0_CRI0_CR_DWORD22_OFFSET 0x0058
PEG Bundle 0 CRI0 CR register DWORD 22.
#define | R_SA_PEG_BND10_CRI0_CR_DWORD22_OFFSET 0x2258
PEG Bundle 10(DMI) CRI0 CR register DWORD 22.
#define | R_SA_PEG_BND0_CRI2_FUSE_DWORD15_OFFSET 0x013C
PEG Bundle 0 CRI2 FUSE register DWORD 15.
#define | R_SA_PEG_BND10_CRI2_FUSE_DWORD15_OFFSET 0x233C
PEG Bundle 10(DMI) CRI2 FUSE register DWORD 15.
#define | R_SA_PEG_BND0_CRI0_CR_DWORD24_OFFSET 0x0060
PEG Bundle 0 CRI0 CR register DWORD 24.
#define | R_SA_PEG_BND10_CRI0_CR_DWORD24_OFFSET 0x2260
PEG Bundle 10(DMI) CRI0 CR register DWORD 24.
#define | R_SA_PEG_BND0_CRI0_CR_DWORD26_OFFSET 0x0068
PEG Bundle 0 CRI0 CR register DWORD 26.
#define | R_SA_PEG_BND10_CRI0_CR_DWORD26_OFFSET 0x2268
PEG Bundle 10(DMI) CRI0 CR register DWORD 26.
#define | R_SA_PEG_BND0_CRI0_CR_DWORD28_OFFSET 0x0070
PEG Bundle 0 CRI0 CR register DWORD 28.
#define | R_SA_PEG_BND10_CRI0_CR_DWORD28_OFFSET 0x2270
PEG Bundle 10(DMI) CRI0 CR register DWORD 28.
#define | R_SA_PEG_BND10_CRI2_FUSE_DWORD16_OFFSET 0x2340
PEG Bundle 10(DMI) CRI2 FUSE register DWORD 16.

Detailed Description

Register names for SA DMI and PEG.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaPcieDmiRegs.h.

Macro Definition Documentation

◆ R_SA_PEG_DID_OFFSET

#define R_SA_PEG_DID_OFFSET 0x02

Device 1 Register Equates.

Device ID

Definition at line 70 of file SaPcieDmiRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPcieDmiRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SaPcieDmiRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for SA DMI and PEG
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2016 - 2018 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _SA_PCIE_DMI_REGS_H_
65 #define _SA_PCIE_DMI_REGS_H_
66
67 ///
68 /// Device 1 Register Equates
69 ///
70 #define R_SA_PEG_DID_OFFSET 0x02 ///< Device ID
71 #define R_SA_PEG_BCTRL_OFFSET 0x3E ///< Bridge Control
72 #define R_SA_PEG_SS_OFFSET 0x8C ///< Subsystem ID
73 #define R_SA_PEG_LCTL_OFFSET 0xB0 ///< Link Control
74 #define R_SA_PEG_LSTS_OFFSET 0xB2 ///< Link Status
75 #define R_SA_PEG_SLOTSTS_OFFSET 0xBA ///< Slot Status
76 #define R_SA_PEG_DCAP2_OFFSET 0xC4 ///< Device Capability 2
77 #define R_SA_PEG_DCTL2_OFFSET 0xC8 ///< Device Control 2
78 #define R_SA_PEG_VC0RSTS_OFFSET 0x11A ///< PEG VC0 Resource Status
79 #define R_SA_PEG_L0SLAT_OFFSET 0x22C ///< PEG L0s Control
80 #define R_SA_PEG_CFG4_OFFSET 0x258 ///< PEG Config 4
81 #define R_SA_PEG_EQPH3_OFFSET 0x384 ///< PEG Phase 3
82 #define R_SA_PEG_AFEBND0CFG1_OFFSET 0x904 ///< PEG AFE Bundle Config 1
83 #define R_SA_PEG_AFEBND0CFG2_OFFSET 0x908 ///< PEG AFE Bundle Config 2
84 #define R_SA_PEG_AFEBND0CFG3_OFFSET 0x90C ///< PEG AFE Bundle Config 3
85 #define R_SA_PEG_AFEBND0CFG4_OFFSET 0x910 ///< PEG AFE Bundle Config 4
86 #define R_SA_PEG_G3CTL0_OFFSET 0x918 ///< PEG Gen3 Control
87 #define R_SA_PEG_BND0SPARE_OFFSET 0x91C ///< PEG Bundle 0 Spare Register
88 #define R_SA_PEG_AFELN0CFG0_OFFSET 0xA00 ///< PEG AFE Lane Config 0
89 #define R_SA_PEG_AFELN0CFG1_OFFSET 0xA04 ///< PEG AFE Lane Config 1
90 #define R_SA_PEG_AFEOVR_OFFSET 0xC20 ///< PEG AFE Override
91 #define R_SA_PEG_CMNSPARE_OFFSET 0xC38 ///< PEG Common Spare
92 #define R_SA_PEG_LCTL3_OFFSET 0xD98 ///< PEG Link Control 3
93 #define R_SA_PEG_EQCTL0_1_OFFSET 0xDA0 ///< PEG Lane Equalization
94 #define R_SA_PEG_EQPRESET1_2_OFFSET 0xDC0 ///< PEG Coefficients for P1 and P2
95 #define R_SA_PEG_EQPRESET2_3_4_OFFSET 0xDC4 ///< PEG Coefficients for P2, P3, and P4
96 #define R_SA_PEG_EQPRESET4_5_OFFSET 0xDC8 ///< PEG Coefficients for P4 and P5
97 #define R_SA_PEG_EQPRESET6_7_OFFSET 0xDCC ///< PEG Coefficients for P6 and P7
98 #define R_SA_PEG_EQPRESET7_8_9_OFFSET 0xDD0 ///< PEG Coefficients for P7, P8, and P9
99 #define R_SA_PEG_EQPRESET9_10_OFFSET 0xDD4 ///< PEG Coefficients for P9 and P10
100 #define R_SA_PEG_EQCFG_OFFSET 0xDD8 ///< PEG Equalization Config
101 #define R_SA_PEG_EQPRESET11_OFFSET 0xDDC ///< PEG Coefficients for P11
102
103 #define R_SA_PEG_BND10_CRI2_FUSE_DWORD14_OFFSET 0x2338 ///< PEG Bundle 10(DMI) CRI2 FUSE register DWORD 14
104
105 #define R_SA_PEG_BND0_CRI0_CR_DWORD22_OFFSET 0x0058 ///< PEG Bundle 0 CRI0 CR register DWORD 22
106 #define R_SA_PEG_BND10_CRI0_CR_DWORD22_OFFSET 0x2258 ///< PEG Bundle 10(DMI) CRI0 CR register DWORD 22
107
108 #define R_SA_PEG_BND0_CRI2_FUSE_DWORD15_OFFSET 0x013C ///< PEG Bundle 0 CRI2 FUSE register DWORD 15
109 #define R_SA_PEG_BND10_CRI2_FUSE_DWORD15_OFFSET 0x233C ///< PEG Bundle 10(DMI) CRI2 FUSE register DWORD 15
110
111 #define R_SA_PEG_BND0_CRI0_CR_DWORD24_OFFSET 0x0060 ///< PEG Bundle 0 CRI0 CR register DWORD 24
112 #define R_SA_PEG_BND10_CRI0_CR_DWORD24_OFFSET 0x2260 ///< PEG Bundle 10(DMI) CRI0 CR register DWORD 24
113
114 #define R_SA_PEG_BND0_CRI0_CR_DWORD26_OFFSET 0x0068 ///< PEG Bundle 0 CRI0 CR register DWORD 26
115 #define R_SA_PEG_BND10_CRI0_CR_DWORD26_OFFSET 0x2268 ///< PEG Bundle 10(DMI) CRI0 CR register DWORD 26
116
117 #define R_SA_PEG_BND0_CRI0_CR_DWORD28_OFFSET 0x0070 ///< PEG Bundle 0 CRI0 CR register DWORD 28
118 #define R_SA_PEG_BND10_CRI0_CR_DWORD28_OFFSET 0x2270 ///< PEG Bundle 10(DMI) CRI0 CR register DWORD 28
119
120 #define R_SA_PEG_BND10_CRI2_FUSE_DWORD16_OFFSET 0x2340 ///< PEG Bundle 10(DMI) CRI2 FUSE register DWORD 16
121
122 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPlatformLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
Functions
SaPlatformLib.h File Reference

Header file for SaPlatformLib. More...

Go to the source code of this file.

Functions

BOOLEAN | IsMobileSku (VOID)
Checks if SKU is Mobile. More...
BOOLEAN | IsDesktopSku (VOID)
Checks if SKU is Desktop. More...
BOOLEAN | IsHaloSku (VOID)
Checks if SKU is Halo. More...
BOOLEAN | IsServerSku (VOID)
Checks if SKU is Server. More...

Detailed Description

Header file for SaPlatformLib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaPlatformLib.h.

Function Documentation

◆ IsDesktopSku()

BOOLEAN IsDesktopSku ( VOID )

Checks if SKU is Desktop.

Return values
FALSE | SKU is not Desktop
TRUE | SKU is Desktop

◆ IsHaloSku()

BOOLEAN IsHaloSku ( VOID )

Checks if SKU is Halo.

Return values
FALSE | SKU is not Halo
TRUE | SKU is Halo

◆ IsMobileSku()

BOOLEAN IsMobileSku ( VOID )

Checks if SKU is Mobile.

Return values
FALSE | SKU is not Mobile
TRUE | SKU is Mobile

◆ IsServerSku()

BOOLEAN IsServerSku ( VOID )

Checks if SKU is Server.

Return values
FALSE | SKU is not Server
TRUE | SKU is Server
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPlatformLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
SaPlatformLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SaPlatformLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _SA_PLATFORM_LIB_H_
37 #define _SA_PLATFORM_LIB_H_
38
39
40 /**
41 Checks if SKU is Mobile
42
43 @retval FALSE SKU is not Mobile
44 @retval TRUE SKU is Mobile
45 **/
46 BOOLEAN
47 EFIAPI
48 IsMobileSku (
49 VOID
50 );
51
52 /**
53 Checks if SKU is Desktop
54
55 @retval FALSE SKU is not Desktop
56 @retval TRUE SKU is Desktop
57 **/
58 BOOLEAN
59 EFIAPI
60 IsDesktopSku (
61 VOID
62 );
63
64 /**
65 Checks if SKU is Halo
66
67 @retval FALSE SKU is not Halo
68 @retval TRUE SKU is Halo
69 **/
70 BOOLEAN
71 EFIAPI
72 IsHaloSku (
73 VOID
74 );
75
76 /**
77 Checks if SKU is Server
78
79 @retval FALSE SKU is not Server
80 @retval TRUE SKU is Server
81 **/
82 BOOLEAN
83 EFIAPI
84 IsServerSku (
85 VOID
86 );
87
88 #endif
IsMobileSku
BOOLEAN IsMobileSku(VOID)
Checks if SKU is Mobile.
IsDesktopSku
BOOLEAN IsDesktopSku(VOID)
Checks if SKU is Desktop.
IsHaloSku
BOOLEAN IsHaloSku(VOID)
Checks if SKU is Halo.
IsServerSku
BOOLEAN IsServerSku(VOID)
Checks if SKU is Server.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPolicy.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
Classes | Macros | Variables
SaPolicy.h File Reference

Interface definition details between System Agent and platform drivers during DXE phase. More...

#include <ConfigBlock.h>
#include <Library/ConfigBlockLib.h>
#include <GraphicsConfig.h>
#include <ConfigBlock/MemoryDxeConfig.h>
#include <ConfigBlock/PcieDxeConfig.h>
#include <VtdConfig.h>
Include dependency graph for SaPolicy.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SA_POLICY_PROTOCOL
SA DXE Policy. More...

Macros

#define | SA_POLICY_PROTOCOL_REVISION 1
Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external modules maybe have consumed this macro in their source code. More...
#define | LTR_MAX_SNOOP_LATENCY_VALUE 0x0846
Intel recommended maximum value for Snoop Latency.
#define | LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846
Intel recommended maximum value for Non-Snoop Latency.

Variables

EFI_GUID gSaPolicyProtocolGuid
Extern the GUID for protocol users.

Detailed Description

Interface definition details between System Agent and platform drivers during DXE phase.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SaPolicy.h.

Macro Definition Documentation

◆ SA_POLICY_PROTOCOL_REVISION

#define SA_POLICY_PROTOCOL_REVISION 1

Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external modules maybe have consumed this macro in their source code.

Directly update the SA_POLICY_PROTOCOL_REVISION version number may cause those external modules to auto mark themselves wrong version info. Always create new version macro for new Policy protocol interface.

Definition at line 61 of file SaPolicy.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SaPolicy.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
SaPolicy.h
Go to the documentation of this file.
1 /** @file
2 Interface definition details between System Agent and platform drivers during DXE phase.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SA_POLICY_H_
36 #define _SA_POLICY_H_
37
38 #include <ConfigBlock.h>
39 #include <Library/ConfigBlockLib.h>
40 #include <GraphicsConfig.h>
41 #include <ConfigBlock/MemoryDxeConfig.h>
42 #include <ConfigBlock/PcieDxeConfig.h>
43 #include <VtdConfig.h>
44
45 ///
46 /// Extern the GUID for protocol users.
47 ///
48 extern EFI_GUID gSaPolicyProtocolGuid;
49 extern EFI_GUID gGraphicsDxeConfigGuid;
50 extern EFI_GUID gPcieDxeConfigGuid;
51 extern EFI_GUID gMemoryDxeConfigGuid;
52 extern EFI_GUID gVtdDxeConfigGuid;
53
54 /**
55 Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external
56 modules maybe have consumed this macro in their source code. Directly
57 update the SA_POLICY_PROTOCOL_REVISION version number may cause those
58 external modules to auto mark themselves wrong version info.
59 Always create new version macro for new Policy protocol interface.
60 **/
61 #define SA_POLICY_PROTOCOL_REVISION 1
62
63 #define CPU_PCIE_DEV_END_OF_TABLE 0xFFFF
64
65 #define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Snoop Latency
66 #define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recommended maximum value for Non-Snoop Latency
67
68
69 /**
70 SA DXE Policy
71
72 The SA_POLICY_PROTOCOL producer drvier is recommended to
73 set all the SA_POLICY_PROTOCOL size buffer zero before init any member parameter,
74 this clear step can make sure no random value for those unknow new version parameters.
75
76 Make sure to update the Revision if any change to the protocol, including the existing
77 internal structure definations.\n
78 Note: Here revision will be bumped up when adding/removing any config block under this structure.\n
79 <b>Revision 1</b>:
80 - Initial version.
81 **/
82 typedef struct {
83 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
84 /*
85 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
86 */
87 } SA_POLICY_PROTOCOL;
88
89 #endif
VtdConfig.h
VT-d policy definitions.
ConfigBlock.h
Header file for Config Block Lib implementation.
SA_POLICY_PROTOCOL
SA DXE Policy.
Definition: SaPolicy.h:82
gSaPolicyProtocolGuid
EFI_GUID gSaPolicyProtocolGuid
Extern the GUID for protocol users.
MemoryDxeConfig.h
Memory DXE Policy definitions.
GraphicsConfig.h
Policy definition for Internal Graphics Config Block.
ConfigBlockLib.h
Header file for Config Block Lib implementation.
PcieDxeConfig.h
PCIE DXE policy definitions.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
SA_POLICY_PROTOCOL::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Offset 0-31.
Definition: SaPolicy.h:83
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
Classes
SataConfig.h File Reference

Sata policy. More...

#include <PchLimits.h>
#include <ConfigBlock.h>
#include <Library/GpioConfig.h>
Include dependency graph for SataConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port. More...
struct | SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization. More...
struct | SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers. More...

Detailed Description

Sata policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SataConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
SataConfig.h
Go to the documentation of this file.
1 /** @file
2 Sata policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SATA_CONFIG_H_
36 #define _SATA_CONFIG_H_
37
38 #include <PchLimits.h>
39 #include <ConfigBlock.h>
40 #include <Library/GpioConfig.h>
41
42 #define SATA_CONFIG_REVISION 1
43 extern EFI_GUID gSataConfigGuid;
44
45 #pragma pack (push,1)
46
47 typedef enum {
48 SataModeAhci,
49 SataModeRaid,
50 SataModeMax
51 } SATA_MODE;
52
53 typedef enum {
54 SataSpeedDefault,
55 SataSpeedGen1,
56 SataSpeedGen2,
57 SataSpeedGen3
58 } SATA_SPEED;
59
60 typedef enum {
61 SataRstMsix,
62 SataRstMsi,
63 SataRstLegacy
64 } SATA_RST_INTERRUPT;
65
66 typedef enum {
67 SataRaidClient,
68 SataRaidAlternate,
69 SataRaidServer
70 } SATA_RAID_DEV_ID;
71
72 /**
73 This structure configures the features, property, and capability for each SATA port.
74 **/
75 typedef struct {
76 /**
77 Enable SATA port.
78 It is highly recommended to disable unused ports for power savings
79 **/
80 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
81 UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
82 UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
83 UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
84 UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
85 UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
86 UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
87 UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
88 UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
89 UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
90 /**
91 Support zero power ODD <b>0: Disable</b>, 1: Enable.
92 This is also used to disable ModPHY dynamic power gate.
93 **/
94 UINT32 ZpOdd : 1;
95 UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default; <b>0x01: GpioResumeReset</b>; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: GpioDswReset
96 UINT32 SataPmPtm : 1; ///< Deprecated
97 UINT32 RxPolarity : 1; ///< <b>0: Disable</b>; 1: Enable; Rx Polarity
98 UINT32 RsvdBits0 : 3; ///< Reserved fields for future expansion w/o protocol change
99 UINT32 DevSlpGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SATA_DEVSLP_x*
100 } PCH_SATA_PORT_CONFIG;
101
102 /**
103 This structure lists PCH supported SATA thermal throttling register setting for customization.
104 The settings is programmed through SATA Index/Data registers.
105 When the SuggestedSetting is enabled, the customized values are ignored.
106 **/
107 typedef struct {
108 UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
109 UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
110 UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
111 UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
112
113 UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
114 UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
115 UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
116 UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
117
118 UINT32 P0Tinact : 2; ///< Port 0 Tinactive
119 UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
120 UINT32 P1Tinact : 2; ///< Port 1 Tinactive
121 UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
122 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
123 UINT32 RsvdBits0 : 9; ///< Reserved bits
124 } SATA_THERMAL_THROTTLING;
125
126 /**
127 The SATA_CONFIG block describes the expected configuration of the SATA controllers.
128
129 <b>Revision 1</b>:
130 - Initial version.
131 <b>Revision 2</b>:
132 - Added DevSlpGpioPinMux.
133 **/
134 typedef struct {
135 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
136 ///
137 /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
138 ///
139 UINT8 Enable;
140 UINT8 TestMode; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
141 UINT8 SalpSupport; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
142 UINT8 PwrOptEnable; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
143 /**
144 EsataSpeedLimit
145 When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
146 Please be noted, this setting could be cleared by HBA reset, which might be issued
147 by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
148 To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
149 setting before and after initialization. For support it after POST, it's dependent on
150 driver's behavior.
151 <b>0: Disable</b>; 1: Enable
152 **/
153 UINT8 EsataSpeedLimit;
154 UINT8 LedEnable; ///< SATA LED indicates SATA controller activity. 0: Disable; <b>1: Enable</b> SATA LED.
155 /**
156 This option allows to configure SATA controller device ID while in RAID mode.
157 Refer to SATA_RAID_DEV_ID enumeration for supported options.
158 Choosing Client will allow RST driver loading, RSTe driver will not be able to load
159 Choosing Alternate will not allow RST inbox driver loading in Windows
160 Choosing Server will allow RSTe driver loading, RST driver will not load
161 <b>0: Client</b>; 1: Alternate; 2: Server
162 **/
163 UINT8 RaidDeviceId;
164 /**
165 Controlls which interrupts will be linked to SATA controller CAP list
166 This option will take effect only if SATA controller is in RAID mode
167 Default: <b>PchSataMsix</b>
168 **/
169 UINT8 SataRstInterrupt;
170
171 /**
172 Determines the system will be configured to which SATA mode.
173 Refer to SATA_MODE enumeration for supported options. Default is <b>SataModeAhci</b>.
174 **/
175 UINT8 SataMode;
176 /**
177 Indicates the maximum speed the SATA controller can support.
178 Refer to SATA_SPEED enumeration for supported options.
179 <b>0h: SataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
180 **/
181 UINT8 SpeedLimit;
182 UINT8 EnclosureSupport; ///< Enclosure Management Support. 0: Disable; 1: Enable
183 /**
184 Controlls whenever Serial GPIO support is enabled for controller
185 <b>0: Disable</b>; 1: Enable
186 **/
187 UINT8 SgpioSupport;
188 /**
189 This member configures the features, property, and capability for each SATA port.
190 **/
191 PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
192 /**
193 This field decides the settings of Sata thermal throttling. When the Suggested Setting
194 is enabled, PCH RC will use the suggested representative values.
195 **/
196 SATA_THERMAL_THROTTLING ThermalThrottling;
197 } SATA_CONFIG;
198
199 #pragma pack (pop)
200
201 #endif // _SATA_CONFIG_H_
SATA_THERMAL_THROTTLING::P1Tinact
UINT32 P1Tinact
Port 1 Tinactive.
Definition: SataConfig.h:120
PCH_SATA_PORT_CONFIG::HotPlug
UINT32 HotPlug
0: Disable; 1: Enable
Definition: SataConfig.h:81
SATA_CONFIG::SpeedLimit
UINT8 SpeedLimit
Indicates the maximum speed the SATA controller can support.
Definition: SataConfig.h:181
ConfigBlock.h
Header file for Config Block Lib implementation.
SATA_THERMAL_THROTTLING::P0Tinact
UINT32 P0Tinact
Port 0 Tinactive.
Definition: SataConfig.h:118
SATA_THERMAL_THROTTLING::P0T2M
UINT32 P0T2M
Port 0 T2 Multipler.
Definition: SataConfig.h:109
SATA_CONFIG::SataRstInterrupt
UINT8 SataRstInterrupt
Controlls which interrupts will be linked to SATA controller CAP list This option will take effect on...
Definition: SataConfig.h:169
PCH_SATA_PORT_CONFIG::RxPolarity
UINT32 RxPolarity
0: Disable; 1: Enable; Rx Polarity
Definition: SataConfig.h:97
SATA_CONFIG::PwrOptEnable
UINT8 PwrOptEnable
0: Disable; 1: Enable SATA Power Optimizer on PCH side.
Definition: SataConfig.h:142
SATA_THERMAL_THROTTLING::P0T3M
UINT32 P0T3M
Port 0 T3 Multipler.
Definition: SataConfig.h:110
GpioConfig.h
Header file for GpioConfig structure used by GPIO library.
SATA_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SataConfig.h:135
PCH_SATA_PORT_CONFIG::External
UINT32 External
0: Disable; 1: Enable
Definition: SataConfig.h:83
SATA_THERMAL_THROTTLING::P1TDisp
UINT32 P1TDisp
Port 1 Tdispatch.
Definition: SataConfig.h:116
SATA_CONFIG::LedEnable
UINT8 LedEnable
SATA LED indicates SATA controller activity. 0: Disable; 1: Enable SATA LED.
Definition: SataConfig.h:154
PCH_SATA_PORT_CONFIG::SataPmPtm
UINT32 SataPmPtm
Deprecated.
Definition: SataConfig.h:96
SATA_CONFIG::SgpioSupport
UINT8 SgpioSupport
Controlls whenever Serial GPIO support is enabled for controller 0: Disable; 1: Enable.
Definition: SataConfig.h:187
SATA_THERMAL_THROTTLING::P0T1M
UINT32 P0T1M
Port 0 T1 Multipler.
Definition: SataConfig.h:108
SATA_THERMAL_THROTTLING::P1T1M
UINT32 P1T1M
Port 1 T1 Multipler.
Definition: SataConfig.h:113
SATA_CONFIG::EnclosureSupport
UINT8 EnclosureSupport
Enclosure Management Support. 0: Disable; 1: Enable.
Definition: SataConfig.h:182
SATA_CONFIG::Enable
UINT8 Enable
This member describes whether or not the SATA controllers should be enabled.
Definition: SataConfig.h:139
SATA_CONFIG
The SATA_CONFIG block describes the expected configuration of the SATA controllers.
Definition: SataConfig.h:134
SATA_THERMAL_THROTTLING::P0TDispFinit
UINT32 P0TDispFinit
Port 0 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:119
PCH_SATA_PORT_CONFIG::InterlockSw
UINT32 InterlockSw
0: Disable; 1: Enable
Definition: SataConfig.h:82
PCH_SATA_PORT_CONFIG::Enable
UINT32 Enable
Enable SATA port.
Definition: SataConfig.h:80
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SATA_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved fields for future expansion w/o protocol change.
Definition: SataConfig.h:98
PCH_SATA_PORT_CONFIG::ZpOdd
UINT32 ZpOdd
Support zero power ODD 0: Disable, 1: Enable.
Definition: SataConfig.h:94
PCH_SATA_PORT_CONFIG::SolidStateDrive
UINT32 SolidStateDrive
0: HDD; 1: SSD
Definition: SataConfig.h:85
PCH_SATA_PORT_CONFIG::DevSlp
UINT32 DevSlp
0: Disable; 1: Enable DEVSLP on the port
Definition: SataConfig.h:86
SATA_CONFIG::RaidDeviceId
UINT8 RaidDeviceId
This option allows to configure SATA controller device ID while in RAID mode.
Definition: SataConfig.h:163
PCH_SATA_PORT_CONFIG::DmVal
UINT32 DmVal
DITO multiplier. Default is 15.
Definition: SataConfig.h:88
SATA_CONFIG::TestMode
UINT8 TestMode
(Test) 0: Disable; 1: Allow entrance to the PCH SATA test modes
Definition: SataConfig.h:140
PCH_SATA_PORT_CONFIG
This structure configures the features, property, and capability for each SATA port.
Definition: SataConfig.h:75
SATA_CONFIG::EsataSpeedLimit
UINT8 EsataSpeedLimit
EsataSpeedLimit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
Definition: SataConfig.h:153
SATA_THERMAL_THROTTLING::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: SataConfig.h:122
SATA_THERMAL_THROTTLING::P1TDispFinit
UINT32 P1TDispFinit
Port 1 Alternate Fast Init Tdispatch.
Definition: SataConfig.h:121
SATA_THERMAL_THROTTLING
This structure lists PCH supported SATA thermal throttling register setting for customization.
Definition: SataConfig.h:107
SATA_CONFIG::SalpSupport
UINT8 SalpSupport
0: Disable; 1: Enable Aggressive Link Power Management
Definition: SataConfig.h:141
PCH_SATA_PORT_CONFIG::DitoVal
UINT32 DitoVal
DEVSLP Idle Timeout (DITO), Default is 625.
Definition: SataConfig.h:89
SATA_THERMAL_THROTTLING::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SataConfig.h:123
SATA_CONFIG::ThermalThrottling
SATA_THERMAL_THROTTLING ThermalThrottling
This field decides the settings of Sata thermal throttling.
Definition: SataConfig.h:196
SATA_CONFIG::SataMode
UINT8 SataMode
Determines the system will be configured to which SATA mode.
Definition: SataConfig.h:175
SATA_THERMAL_THROTTLING::P1T2M
UINT32 P1T2M
Port 1 T2 Multipler.
Definition: SataConfig.h:114
PCH_SATA_PORT_CONFIG::EnableDitoConfig
UINT32 EnableDitoConfig
0: Disable; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
Definition: SataConfig.h:87
SATA_THERMAL_THROTTLING::P0TDisp
UINT32 P0TDisp
Port 0 Tdispatch.
Definition: SataConfig.h:111
PCH_SATA_PORT_CONFIG::DevSlpResetConfig
UINT32 DevSlpResetConfig
0: Hardware default; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatformReset; 0x07: G...
Definition: SataConfig.h:95
SATA_THERMAL_THROTTLING::P1T3M
UINT32 P1T3M
Port 1 T3 Multipler.
Definition: SataConfig.h:115
PCH_SATA_PORT_CONFIG::SpinUp
UINT32 SpinUp
0: Disable; 1: Enable the COMRESET initialization Sequence to the device
Definition: SataConfig.h:84
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SataLib.h File Reference

Header file for SataLib. More...

#include <SataCtrl.h>
Include dependency graph for SataLib.h:

Go to the source code of this file.

Functions

UINT8 | GetSataPortPresentStatus (IN UINT32 SataCtrlIndex)
Get SATA controller's Port Present Status. More...
BOOLEAN | SataControllerFunctionDisableStatus (IN UINT32 SataCtrlIndex)
Get SATA controller Function Disable Status. More...
UINT32 | GetSataAbarSize (IN UINT32 SataCtrlIndex)
Get SATA controller ABAR size. More...
UINT32 | GetSataAhciBase (IN UINT32 SataCtrlIndex)
Get SATA controller AHCI base address. More...

Detailed Description

Header file for SataLib.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2016 - 2020 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification Reference:

Definition in file SataLib.h.

Function Documentation

◆ GetSataAbarSize()

UINT32 GetSataAbarSize ( IN UINT32 SataCtrlIndex )

Get SATA controller ABAR size.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
SATA controller ABAR size

◆ GetSataAhciBase()

UINT32 GetSataAhciBase ( IN UINT32 SataCtrlIndex )

Get SATA controller AHCI base address.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
SATA controller AHCI base address

◆ GetSataPortPresentStatus()

UINT8 GetSataPortPresentStatus ( IN UINT32 SataCtrlIndex )

Get SATA controller's Port Present Status.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
Port Present Status

◆ SataControllerFunctionDisableStatus()

BOOLEAN SataControllerFunctionDisableStatus ( IN UINT32 SataCtrlIndex )

Get SATA controller Function Disable Status.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
0 | SATA Controller is not Function Disabled
1 | SATA Controller is Function Disabled
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SataLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SataLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2016 - 2020 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 @par Specification Reference:
21 **/
22 #ifndef _SATA_LIB_H_
23 #define _SATA_LIB_H_
24
25 #include <SataCtrl.h>
26
27 /**
28 Get SATA controller's Port Present Status
29
30 @param[in] SataCtrlIndex SATA controller index
31
32 @retval Port Present Status
33 **/
34 UINT8
35 GetSataPortPresentStatus (
36 IN UINT32 SataCtrlIndex
37 );
38
39 /**
40 Get SATA controller Function Disable Status
41
42 @param[in] SataCtrlIndex SATA controller index
43
44 @retval 0 SATA Controller is not Function Disabled
45 @retval 1 SATA Controller is Function Disabled
46 **/
47 BOOLEAN
48 SataControllerFunctionDisableStatus (
49 IN UINT32 SataCtrlIndex
50 );
51
52 /**
53 Get SATA controller ABAR size
54
55 @param[in] SataCtrlIndex SATA controller index
56
57 @retval SATA controller ABAR size
58 **/
59 UINT32
60 GetSataAbarSize (
61 IN UINT32 SataCtrlIndex
62 );
63
64 /**
65 Get SATA controller AHCI base address
66
67 @param[in] SataCtrlIndex SATA controller index
68
69 @retval SATA controller AHCI base address
70 **/
71 UINT32
72 GetSataAhciBase (
73 IN UINT32 SataCtrlIndex
74 );
75
76 #endif // _SATA_LIB_H_
GetSataPortPresentStatus
UINT8 GetSataPortPresentStatus(IN UINT32 SataCtrlIndex)
Get SATA controller's Port Present Status.
GetSataAhciBase
UINT32 GetSataAhciBase(IN UINT32 SataCtrlIndex)
Get SATA controller AHCI base address.
SataControllerFunctionDisableStatus
BOOLEAN SataControllerFunctionDisableStatus(IN UINT32 SataCtrlIndex)
Get SATA controller Function Disable Status.
GetSataAbarSize
UINT32 GetSataAbarSize(IN UINT32 SataCtrlIndex)
Get SATA controller ABAR size.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
SataRegs.h File Reference

Register names for SATA controllers. More...

Go to the source code of this file.

Macros

#define | B_SATA_MEM_VS_CAP_NRMBE BIT0
NVM Remap Memory BAR Enable.
#define | V_SATA_MEM_VS_CAP_MSL 0x1EF
Memory Space Limit Field Value.
#define | V_SATA_MEM_VS_CAP_NRMO 0x10
NVM Remapped Memory Offset Field Value.
#define | R_SATA_MEM_RST_PCIE_STORAGE_RCR 0x800
Remap Capability Register.
#define | B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0)
Number of Remapping Supported.
#define | B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0
Number of Remapping Supported (RST PCIe Storage Cycle Router #1)
#define | R_SATA_MEM_RST_PCIE_STORAGE_AMXC 0x808
AHCI MSI-X Configuration.
#define | B_SATA_MEM_RST_PCIE_STORAGE_AMXC_AMXV 0x7FF
AHCI MSI-X Vector.
#define | R_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC 0x880
CR#1 Device Class Code.
#define | B_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_DT BIT31
Device Type.
#define | R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMBL 0x884
CR#1 Device Memory BAR Length.
#define | R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMXC 0x888
CR#1 Device MSI-X Configuration.
#define | V_SATA_MEM_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80
Remapped Configuration for RST PCIe Storage Cycle Router #n.
#define | V_SATA_MEM_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100
Remapped Root Port Offset Value.
#define | R_SATA_CFG_RST_PCIE_STORAGE_GCR 0x300
General Configuration Register.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GCR_CRE BIT0
RST PCIe Storage Cycle Router Enable.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GCR_PLS 0x1FFFFE
PCIe Lane Selected Field.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GCR_PNCAIDL BIT29
Configuration Access Index/Data Lockdown.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GCR_RCL BIT30
Remapping Configuration Lockdown.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GCR_CREL BIT31
RST PCIe Storage Cycle Router Enable Lockdown.
#define | R_SATA_CFG_RST_PCIE_STORAGE_GSR 0x304
General Status Register.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GSR_PLRC 0x1FFFFE
PCIe Lane Remap Capable Field.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCS BIT30
Port Configuration Check Status.
#define | B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCD BIT31
Port Configuration Check Disable.
#define | R_SATA_CFG_RST_PCIE_STORAGE_CAIR 0x308
Configuration Access Index Register.
#define | R_SATA_CFG_RST_PCIE_STORAGE_CADR 0x30C
Configuration Access Data Register.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MBRC 0x310
Memory BAR Remap Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB (BIT19|BIT18|BIT17|BIT16)
Memory BAR Remap Configuration Target Memory BAR.
#define | V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR0 0x4
Memory BAR Remap Configuration Target Memory BAR - BAR0.
#define | V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR5 0x9
Memory BAR Remap Configuration Target Memory BAR - BAR5.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TT BIT20
Remap Configuration Target Type.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MBRC_RE BIT31
Remap Configuration Remap Enable.
#define | R_SATA_CFG_RST_PCIE_STORAGE_IOBRSC 0x320
I/O BAR Remap Source Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_IOBRSC_RE BIT31
I/O BAR Remap Source Configuration Remap Enable.
#define | R_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC 0x338
AHCI Index/Data Pair Capability Remap Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_TCSO 0xFF0000
AHCI Index/Data Pair Capability Remap Configuration Target Capability Structure OffsBet.
#define | B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_RE BIT31
AHCI Index/Data Pair Capability Remap Configuration Remap Enable.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MXCRC 0x33C
MSI-X Capability Remap Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXCRCC_TCSO 0xFF0000
MSI-X Capability Remap Configuration Target Capability Structure Offset.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXCRC_RE BIT31
MSI-X Capability Remap Configuration Remap Enable.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MXTRC 0x340
MSI-X Table Remap Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TBIR 0x07
MSI-X Table Remap Configuration Table BIR.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TO 0xFFFFFFF8
MSI-X Table Remap Configuration Table Offset.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MXTBAR 0x344
MSI-X Table Base Address Register.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXTBAR_TBAV BIT0
MSI-X Table Base Address Register Table Base Address Valid.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MXPRC 0x348
MSI-X PBA Remap Configuration.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TBIR 0x07
MSI-X PBA Remap Configuration Table BIR.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TO 0xFFFFFFF8
MSI-X PBA Remap Configuration Table Offset.
#define | R_SATA_CFG_RST_PCIE_STORAGE_MXPBAR 0x34C
MSI-X PBA Base Address Register.
#define | B_SATA_CFG_RST_PCIE_STORAGE_MXPBAR_TBAV BIT0
MSI-X PBA Base Address Register Table Base Address Valid.
#define | R_SATA_CFG_RST_PCIE_STORAGE_NRDF 0x350
NVM Remapping Device:Function.
#define | R_SATA_CFG_RST_PCIE_STORAGE_EGCR 0x354
Extended General Configuration Register.
#define | B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRDCGE BIT16
RST PCIe Storage Cycle Router Dynamic Clock Gating Enable.
#define | B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRTCGE BIT17
RST PCIe Storage Cycle Router Trunk Clock Gating Enable.
#define | B_SATA_CFG_RST_PCIE_STORAGE_EGCR_ICAS BIT19
IOSF CLKREQ Assertion Select.
#define | B_SATA_CFG_RST_PCIE_STORAGE_EGCR_TSCAS BIT20
To SATA CLKREQ Assertion Select.
#define | R_SATA_CFG_RST_PCIE_STORAGE_SAPI 0x358
Shadowed AHCI Ports Implemented.
#define | R_SATA_CFG_RST_PCIE_STORAGE_RHDF 0x368
Remapping Host Device Function.
#define | R_SATA_CFG_RST_PCIE_STORAGE_CRGC 0xFC0
RST PCIe Storage Cycle Router Global Control.
#define | B_SATA_CFG_RST_PCIE_STORAGE_CRGC_CRAS (BIT1|BIT0)
RST PCIe Storage Cycle Router Global Control Cycle Router Accessibility Select.
#define | R_SATA_CFG_RST_PCIE_STORAGE_FDW0 0xFC4
Fuse DW0.
#define | B_SATA_MEM_AHCI_CAP_SMPS BIT28
Supports Interlock Switch.
#define | B_SATA_MEM_AHCI_CAP_SSS BIT27
Supports Stagger Spin-up.
#define | B_SATA_MEM_AHCI_CAP_SCLO BIT24
Supports Command List Override.
#define | N_SATA_MEM_AHCI_CAP_ISS 20
Interface Speed Support.
#define | B_SATA_MEM_AHCI_CAP_SPM BIT17
Supports Port Multiplier.
#define | B_SATA_MEM_AHCI_CAP_PMD BIT15
PIO Multiple DRQ Block.
#define | B_SATA_MEM_AHCI_CAP_SXS BIT5
External SATA is supported.
#define | B_SATA_MEM_AHCI_CAP2_APST BIT2
Automatic Partial to Slumber Transitions.
#define | R_SATA_MEM_AHCI_SFM 0xC8
RST Feature Capabilities.
#define | B_SATA_MEM_AHCI_PxCMD_ESP BIT21
Used with an external SATA device.
#define | B_SATA_MEM_AHCI_PxCMD_MPSP BIT19
Mechanical Switch Attached to Port.
#define | B_SATA_MEM_AHCI_PxCMD_HPCP BIT18
Hotplug capable.

Detailed Description

Register names for SATA controllers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SataRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SataRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for SATA controllers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2020 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _SATA_REGS_H_
65 #define _SATA_REGS_H_
66
67 //
68 // SATA Controller Common Registers
69 //
70 #define R_SATA_CFG_AHCI_BAR 0x24
71 #define B_SATA_CFG_AHCI_BAR_BA 0xFFFFF800
72 #define V_SATA_CFG_AHCI_BAR_LENGTH 0x800
73 #define N_SATA_CFG_AHCI_BAR_ALIGNMENT 11
74 #define V_SATA_CFG_AHCI_BAR_LENGTH_512K 0x80000
75 #define N_SATA_CFG_AHCI_BAR_ALIGNMENT_512K 19
76 #define R_SATA_CFG_PID 0x70
77 #define V_SATA_CFG_PID_NEXT_0 0xB000
78 #define V_SATA_CFG_PID_NEXT_1 0xA800
79 #define R_SATA_CFG_PMCS 0x74
80 #define R_SATA_CFG_MAP 0x90
81 #define B_SATA_CFG_MAP_PCD 0xFF
82 #define N_SATA_CFG_MAP_SPD 16
83 #define B_SATA_CFG_MAP_SPD7 BIT23
84 #define B_SATA_CFG_MAP_SPD6 BIT22
85 #define B_SATA_CFG_MAP_SPD5 BIT21
86 #define B_SATA_CFG_MAP_SPD4 BIT20
87 #define B_SATA_CFG_MAP_SPD3 BIT19
88 #define B_SATA_CFG_MAP_SPD2 BIT18
89 #define B_SATA_CFG_MAP_SPD1 BIT17
90 #define B_SATA_CFG_MAP_SPD0 BIT16
91 #define B_SATA_CFG_MAP_PORT7_PCD BIT7
92 #define B_SATA_CFG_MAP_PORT6_PCD BIT6
93 #define B_SATA_CFG_MAP_PORT5_PCD BIT5
94 #define B_SATA_CFG_MAP_PORT4_PCD BIT4
95 #define B_SATA_CFG_MAP_PORT3_PCD BIT3
96 #define B_SATA_CFG_MAP_PORT2_PCD BIT2
97 #define B_SATA_CFG_MAP_PORT1_PCD BIT1
98 #define B_SATA_CFG_MAP_PORT0_PCD BIT0
99 #define R_SATA_CFG_PCS 0x94
100 #define B_SATA_CFG_PCS_P7P BIT23
101 #define B_SATA_CFG_PCS_P6P BIT22
102 #define B_SATA_CFG_PCS_P5P BIT21
103 #define B_SATA_CFG_PCS_P4P BIT20
104 #define B_SATA_CFG_PCS_P3P BIT19
105 #define B_SATA_CFG_PCS_P2P BIT18
106 #define B_SATA_CFG_PCS_P1P BIT17
107 #define B_SATA_CFG_PCS_P0P BIT16
108 #define B_SATA_CFG_PCS_P7E BIT7
109 #define B_SATA_CFG_PCS_P6E BIT6
110 #define B_SATA_CFG_PCS_P5E BIT5
111 #define B_SATA_CFG_PCS_P4E BIT4
112 #define B_SATA_CFG_PCS_P3E BIT3
113 #define B_SATA_CFG_PCS_P2E BIT2
114 #define B_SATA_CFG_PCS_P1E BIT1
115 #define B_SATA_CFG_PCS_P0E BIT0
116 #define B_SATA_CFG_PCS_PXE_MASK 0xFF
117 #define R_SATA_CFG_SATAGC 0x9C
118 #define B_SATA_CFG_SATAGC_REGLOCK BIT31
119 #define B_SATA_CFG_SATAGC_SMS_MASK BIT16
120 #define N_SATA_CFG_SATAGC_SMS_MASK 16
121 #define V_SATA_CFG_SATAGC_SMS_AHCI 0x0
122 #define V_SATA_CFG_SATAGC_SMS_RAID 0x1
123 #define B_SATA_CFG_SATAGC_DPPEE BIT15
124 #define B_SATA_CFG_SATAGC_CPEE BIT11
125 #define B_SATA_CFG_SATAGC_AIE BIT7
126 #define B_SATA_CFG_SATAGC_AIES BIT6
127 #define B_SATA_CFG_SATAGC_MSS (BIT4 | BIT3)
128 #define V_SATA_CFG_SATAGC_MSS_8K 0x2
129 #define N_SATA_CFG_SATAGC_MSS 3
130 #define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)
131 #define V_SATA_CFG_SATAGC_ASSEL_2K 0x0
132 #define V_SATA_CFG_SATAGC_ASSEL_16K 0x1
133 #define V_SATA_CFG_SATAGC_ASSEL_32K 0x2
134 #define V_SATA_CFG_SATAGC_ASSEL_64K 0x3
135 #define V_SATA_CFG_SATAGC_ASSEL_128K 0x4
136 #define V_SATA_CFG_SATAGC_ASSEL_256K 0x5
137 #define V_SATA_CFG_SATAGC_ASSEL_512K 0x6
138
139 #define R_SATA_CFG_SIRI 0xA0
140 #define R_SATA_CFG_SIRD 0xA4
141 #define R_SATA_CFG_SIR_0C 0x0C
142 #define R_SATA_CFG_SIR_50 0x50
143 #define R_SATA_CFG_SIR_54 0x54
144 #define R_SATA_CFG_SIR_58 0x58
145 #define R_SATA_CFG_SIR_5C 0x5C
146 #define R_SATA_CFG_SIR_60 0x60
147 #define R_SATA_CFG_SIR_64 0x64
148 #define R_SATA_CFG_SIR_68 0x68
149 #define R_SATA_CFG_SIR_6C 0x6C
150 #define R_SATA_CFG_SIR_70 0x70
151 #define R_SATA_CFG_SIR_80 0x80
152 #define R_SATA_CFG_SIR_84 0x84
153 #define R_SATA_CFG_SIR_8C 0x8C
154 #define R_SATA_CFG_SIR_90 0x90
155 #define R_SATA_CFG_SIR_98 0x98
156 #define R_SATA_CFG_SIR_9C 0x9C
157 #define R_SATA_CFG_SIR_A0 0xA0
158 #define B_SATA_CFG_SIR_A0_CWICBRLMAX 0x1F
159 #define N_SATA_CFG_SIR_A0_CWICBRLMAX 24
160 #define B_SATA_CFG_SIR_A0_CWCIBRUMIN 0x3F
161 #define N_SATA_CFG_SIR_A0_CWCIBRUMIN 18
162 #define R_SATA_CFG_SIR_A4 0xA4
163 #define R_SATA_CFG_SIR_A8 0xA8
164 #define R_SATA_CFG_SIR_C4 0xC4
165 #define B_SATA_CFG_SIR_C4_TCLKSNACK_CP (BIT27 | BIT26)
166 #define R_SATA_CFG_SIR_C8 0xC8
167 #define R_SATA_CFG_SIR_CC 0xCC
168 #define R_SATA_CFG_SIR_D0 0xD0
169 #define N_SATA_CFG_SIR_D0_LAT_VAL 0
170 #define N_SATA_CFG_SIR_D0_LAT_SCALE 10
171 #define B_SATA_CFG_SIR_D0_LAT_REQ BIT15
172 #define R_SATA_CFG_SIR_D4 0xD4
173 #define B_SATA_CFG_SIR_D4_CIGMAX 0x3F
174 #define N_SATA_CFG_SIR_D4_CIGMAX 24
175 #define B_SATA_CFG_SIR_D4_CIGMIN 0x3F
176 #define N_SATA_CFG_SIR_D4_CIGMIN 16
177 #define B_SATA_CFG_SIR_D4_CWGMAX 0x1F
178 #define N_SATA_CFG_SIR_D4_CWGMAX 8
179 #define B_SATA_CFG_SIR_D4_CWGMIN 0x1F
180 #define N_SATA_CFG_SIR_D4_CWGMIN 0
181 #define R_SATA_CFG_CR0 0xA8
182 #define R_SATA_CFG_CR1 0xAC
183 #define B_SATA_CFG_CR1_BAROFST 0xFFF0
184 #define B_SATA_CFG_CR1_BARLOC 0x000F
185 #define R_SATA_CFG_FLR_CID 0xB0
186 #define B_SATA_CFG_FLR_CID 0x00FF
187 #define V_SATA_CFG_FLR_CID_1 0x0009
188 #define V_SATA_CFG_FLR_CID_0 0x0013
189 #define R_SATA_CFG_FLR_CLV 0xB2
190 #define B_SATA_CFG_FLR_CLV_FLRC_FLRCSSEL_0 BIT9
191 #define B_SATA_CFG_FLR_CLV_TXPC_FLRCSSEL_0 BIT8
192 #define V_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL 0x0006
193 #define R_SATA_CFG_FLRC 0xB4
194 #define B_SATA_CFG_FLRC_TXP BIT8
195 #define B_SATA_CFG_FLRC_INITFLR BIT0
196 #define R_SATA_CFG_MXID 0xD0
197 #define N_SATA_CFG_MXID_NEXT 8
198 #define R_SATA_CFG_MXT 0xD4
199 #define R_SATA_CFG_MXP 0xD8
200
201 #define R_SATA_MEM_VS_CAP 0xA4
202 #define B_SATA_MEM_VS_CAP_NRMBE BIT0 ///< NVM Remap Memory BAR Enable
203 #define N_SATA_MEM_VS_CAP_MSL 1
204 #define V_SATA_MEM_VS_CAP_MSL 0x1EF ///< Memory Space Limit Field Value
205 #define N_SATA_MEM_VS_CAP_NRMO 16
206 #define V_SATA_MEM_VS_CAP_NRMO 0x10 ///< NVM Remapped Memory Offset Field Value
207
208 //
209 // RST PCIe Storage Remapping Registers
210 //
211 #define R_SATA_MEM_RST_PCIE_STORAGE_RCR 0x800 ///< Remap Capability Register
212 #define B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) ///< Number of Remapping Supported
213 #define B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 ///< Number of Remapping Supported (RST PCIe Storage Cycle Router #1)
214 #define R_SATA_MEM_RST_PCIE_STORAGE_AMXC 0x808 ///< AHCI MSI-X Configuration
215 #define B_SATA_MEM_RST_PCIE_STORAGE_AMXC_AMXV 0x7FF ///< AHCI MSI-X Vector
216 #define R_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC 0x880 ///< CR#1 Device Class Code
217 #define N_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_SCC 8
218 #define N_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_BCC 16
219 #define B_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 ///< Device Type
220 #define R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMBL 0x884 ///< CR#1 Device Memory BAR Length
221 #define R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMXC 0x888 ///< CR#1 Device MSI-X Configuration
222 #define N_SATA_MEM_RST_PCIE_STORAGE_CR1_DMXC_MXEV 16
223 #define V_SATA_MEM_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 ///< Remapped Configuration for RST PCIe Storage Cycle Router #n
224 #define V_SATA_MEM_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 ///< Remapped Root Port Offset Value
225 #define R_SATA_CFG_RST_PCIE_STORAGE_GCR 0x300 ///< General Configuration Register
226 #define B_SATA_CFG_RST_PCIE_STORAGE_GCR_CRE BIT0 ///< RST PCIe Storage Cycle Router Enable
227 #define B_SATA_CFG_RST_PCIE_STORAGE_GCR_PLS 0x1FFFFE ///< PCIe Lane Selected Field
228 #define B_SATA_CFG_RST_PCIE_STORAGE_GCR_PNCAIDL BIT29 ///< Configuration Access Index/Data Lockdown
229 #define B_SATA_CFG_RST_PCIE_STORAGE_GCR_RCL BIT30 ///< Remapping Configuration Lockdown
230 #define B_SATA_CFG_RST_PCIE_STORAGE_GCR_CREL BIT31 ///< RST PCIe Storage Cycle Router Enable Lockdown
231 #define R_SATA_CFG_RST_PCIE_STORAGE_GSR 0x304 ///< General Status Register
232 #define B_SATA_CFG_RST_PCIE_STORAGE_GSR_PLRC 0x1FFFFE ///< PCIe Lane Remap Capable Field
233 #define B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCS BIT30 ///< Port Configuration Check Status
234 #define B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCD BIT31 ///< Port Configuration Check Disable
235 #define R_SATA_CFG_RST_PCIE_STORAGE_CAIR 0x308 ///< Configuration Access Index Register
236 #define R_SATA_CFG_RST_PCIE_STORAGE_CADR 0x30C ///< Configuration Access Data Register
237 #define R_SATA_CFG_RST_PCIE_STORAGE_MBRC 0x310 ///< Memory BAR Remap Configuration
238 #define B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB (BIT19|BIT18|BIT17|BIT16) ///< Memory BAR Remap Configuration Target Memory BAR
239 #define N_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB 16
240 #define V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR0 0x4 ///< Memory BAR Remap Configuration Target Memory BAR - BAR0
241 #define V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR5 0x9 ///< Memory BAR Remap Configuration Target Memory BAR - BAR5
242 #define B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TT BIT20 ///< Remap Configuration Target Type
243 #define B_SATA_CFG_RST_PCIE_STORAGE_MBRC_RE BIT31 ///< Remap Configuration Remap Enable
244 #define R_SATA_CFG_RST_PCIE_STORAGE_IOBRSC 0x320 ///< I/O BAR Remap Source Configuration
245 #define B_SATA_CFG_RST_PCIE_STORAGE_IOBRSC_RE BIT31 ///< I/O BAR Remap Source Configuration Remap Enable
246 #define R_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC 0x338 ///< AHCI Index/Data Pair Capability Remap Configuration
247 #define B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_TCSO 0xFF0000 ///< AHCI Index/Data Pair Capability Remap Configuration Target Capability Structure OffsBet
248 #define N_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_TCSO 16
249 #define B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_RE BIT31 ///< AHCI Index/Data Pair Capability Remap Configuration Remap Enable
250 #define R_SATA_CFG_RST_PCIE_STORAGE_MXCRC 0x33C ///< MSI-X Capability Remap Configuration
251 #define B_SATA_CFG_RST_PCIE_STORAGE_MXCRCC_TCSO 0xFF0000 ///< MSI-X Capability Remap Configuration Target Capability Structure Offset
252 #define N_SATA_CFG_RST_PCIE_STORAGE_MXCRCC_TCSO 16
253 #define B_SATA_CFG_RST_PCIE_STORAGE_MXCRC_RE BIT31 ///< MSI-X Capability Remap Configuration Remap Enable
254 #define R_SATA_CFG_RST_PCIE_STORAGE_MXTRC 0x340 ///< MSI-X Table Remap Configuration
255 #define B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TBIR 0x07 ///< MSI-X Table Remap Configuration Table BIR
256 #define B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TO 0xFFFFFFF8 ///< MSI-X Table Remap Configuration Table Offset
257 #define R_SATA_CFG_RST_PCIE_STORAGE_MXTBAR 0x344 ///< MSI-X Table Base Address Register
258 #define B_SATA_CFG_RST_PCIE_STORAGE_MXTBAR_TBAV BIT0 ///< MSI-X Table Base Address Register Table Base Address Valid
259 #define R_SATA_CFG_RST_PCIE_STORAGE_MXPRC 0x348 ///< MSI-X PBA Remap Configuration
260 #define B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TBIR 0x07 ///< MSI-X PBA Remap Configuration Table BIR
261 #define B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TO 0xFFFFFFF8 ///< MSI-X PBA Remap Configuration Table Offset
262 #define R_SATA_CFG_RST_PCIE_STORAGE_MXPBAR 0x34C ///< MSI-X PBA Base Address Register
263 #define B_SATA_CFG_RST_PCIE_STORAGE_MXPBAR_TBAV BIT0 ///< MSI-X PBA Base Address Register Table Base Address Valid
264 #define R_SATA_CFG_RST_PCIE_STORAGE_NRDF 0x350 ///< NVM Remapping Device:Function
265 #define R_SATA_CFG_RST_PCIE_STORAGE_EGCR 0x354 ///< Extended General Configuration Register
266 #define B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRDCGE BIT16 ///< RST PCIe Storage Cycle Router Dynamic Clock Gating Enable
267 #define B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRTCGE BIT17 ///< RST PCIe Storage Cycle Router Trunk Clock Gating Enable
268 #define B_SATA_CFG_RST_PCIE_STORAGE_EGCR_ICAS BIT19 ///< IOSF CLKREQ Assertion Select
269 #define B_SATA_CFG_RST_PCIE_STORAGE_EGCR_TSCAS BIT20 ///< To SATA CLKREQ Assertion Select
270 #define R_SATA_CFG_RST_PCIE_STORAGE_SAPI 0x358 ///< Shadowed AHCI Ports Implemented
271 #define R_SATA_CFG_RST_PCIE_STORAGE_RHDF 0x368 ///< Remapping Host Device Function
272 #define R_SATA_CFG_RST_PCIE_STORAGE_CRGC 0xFC0 ///< RST PCIe Storage Cycle Router Global Control
273 #define B_SATA_CFG_RST_PCIE_STORAGE_CRGC_CRAS (BIT1|BIT0) ///< RST PCIe Storage Cycle Router Global Control Cycle Router Accessibility Select
274 #define R_SATA_CFG_RST_PCIE_STORAGE_FDW0 0xFC4 ///< Fuse DW0
275
276 //
277 // AHCI BAR Area related Registers
278 //
279 #define R_SATA_MEM_AHCI_CAP 0x0
280 #define B_SATA_MEM_AHCI_CAP_SMPS BIT28 ///< Supports Interlock Switch
281 #define B_SATA_MEM_AHCI_CAP_SSS BIT27 ///< Supports Stagger Spin-up
282 #define B_SATA_MEM_AHCI_CAP_SALP BIT26
283 #define B_SATA_MEM_AHCI_CAP_SAL BIT25
284 #define B_SATA_MEM_AHCI_CAP_SCLO BIT24 ///< Supports Command List Override
285 #define B_SATA_MEM_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20)
286 #define N_SATA_MEM_AHCI_CAP_ISS 20 ///< Interface Speed Support
287 #define V_SATA_MEM_AHCI_CAP_ISS_1_5_G 0x01
288 #define V_SATA_MEM_AHCI_CAP_ISS_3_0_G 0x02
289 #define V_SATA_MEM_AHCI_CAP_ISS_6_0_G 0x03
290 #define B_SATA_MEM_AHCI_CAP_SNZO BIT19
291 #define B_SATA_MEM_AHCI_CAP_SAM BIT18
292 #define B_SATA_MEM_AHCI_CAP_SPM BIT17 ///< Supports Port Multiplier
293 #define B_SATA_MEM_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Block
294 #define B_SATA_MEM_AHCI_CAP_SSC BIT14
295 #define B_SATA_MEM_AHCI_CAP_PSC BIT13
296 #define B_SATA_MEM_AHCI_CAP_NCS 0x1F00
297 #define B_SATA_MEM_AHCI_CAP_CCCS BIT7
298 #define B_SATA_MEM_AHCI_CAP_EMS BIT6
299 #define B_SATA_MEM_AHCI_CAP_SXS BIT5 ///< External SATA is supported
300 #define B_SATA_MEM_AHCI_CAP_NPS 0x001F
301
302 #define R_SATA_MEM_AHCI_GHC 0x04
303 #define B_SATA_MEM_AHCI_GHC_AE BIT31
304 #define B_SATA_MEM_AHCI_GHC_MRSM BIT2
305 #define B_SATA_MEM_AHCI_GHC_IE BIT1
306 #define B_SATA_MEM_AHCI_GHC_HR BIT0
307
308 #define R_SATA_MEM_AHCI_IS 0x08
309 #define B_SATA_MEM_AHCI_IS_PORT7 BIT7
310 #define B_SATA_MEM_AHCI_IS_PORT6 BIT6
311 #define B_SATA_MEM_AHCI_IS_PORT5 BIT5
312 #define B_SATA_MEM_AHCI_IS_PORT4 BIT4
313 #define B_SATA_MEM_AHCI_IS_PORT3 BIT3
314 #define B_SATA_MEM_AHCI_IS_PORT2 BIT2
315 #define B_SATA_MEM_AHCI_IS_PORT1 BIT1
316 #define B_SATA_MEM_AHCI_IS_PORT0 BIT0
317 #define R_SATA_MEM_AHCI_PI 0x0C
318 #define B_SATA_MEM_AHCI_PI_PORT_MASK 0xFF
319 #define B_SATA_MEM_PORT7_IMPLEMENTED BIT7
320 #define B_SATA_MEM_PORT6_IMPLEMENTED BIT6
321 #define B_SATA_MEM_PORT5_IMPLEMENTED BIT5
322 #define B_SATA_MEM_PORT4_IMPLEMENTED BIT4
323 #define B_SATA_MEM_PORT3_IMPLEMENTED BIT3
324 #define B_SATA_MEM_PORT2_IMPLEMENTED BIT2
325 #define B_SATA_MEM_PORT1_IMPLEMENTED BIT1
326 #define B_SATA_MEM_PORT0_IMPLEMENTED BIT0
327 #define R_SATA_MEM_AHCI_EM_LOC 0x1C
328 #define B_SATA_MEM_AHCI_EM_LOC_OFST 0xFFFF0000
329 #define B_SATA_MEM_AHCI_EM_LOC_SZ 0x0000FFFF
330 #define R_SATA_MEM_AHCI_CAP2 0x24
331 #define B_SATA_MEM_AHCI_CAP2_DESO BIT5
332 #define B_SATA_MEM_AHCI_CAP2_SADM BIT4
333 #define B_SATA_MEM_AHCI_CAP2_SDS BIT3
334 #define B_SATA_MEM_AHCI_CAP2_APST BIT2 ///< Automatic Partial to Slumber Transitions
335 #define R_SATA_MEM_AHCI_SFM 0xC8 ///< RST Feature Capabilities
336 #define B_SATA_MEM_AHCI_SFM_CPU_STORAGE BIT14
337 #define B_SATA_MEM_AHCI_SFM_OMA BIT13
338 #define B_SATA_MEM_AHCI_SFM_LEGACY BIT12
339 #define B_SATA_MEM_AHCI_SFM_OUD (BIT11 | BIT10)
340 #define N_SATA_MEM_AHCI_SFM_OUD 10
341 #define B_SATA_MEM_AHCI_SFM_SEREQ BIT9
342 #define B_SATA_MEM_AHCI_SFM_IROES BIT8
343 #define B_SATA_MEM_AHCI_SFM_LEDL BIT7
344 #define B_SATA_MEM_AHCI_SFM_HDDLK BIT6
345 #define B_SATA_MEM_AHCI_SFM_IRSTOROM BIT5
346 #define B_SATA_MEM_AHCI_SFM_RSTE BIT4
347 #define B_SATA_MEM_AHCI_SFM_R5E BIT3
348 #define B_SATA_MEM_AHCI_SFM_R10E BIT2
349 #define B_SATA_MEM_AHCI_SFM_R1E BIT1
350 #define B_SATA_MEM_AHCI_SFM_R0E BIT0
351 #define B_SATA_MEM_AHCI_SFM_LOWBYTES 0x1FF
352 #define R_SATA_MEM_AHCI_P0CMD 0x118
353 #define R_SATA_MEM_AHCI_P1CMD 0x198
354 #define R_SATA_MEM_AHCI_P2CMD 0x218
355 #define R_SATA_MEM_AHCI_P3CMD 0x298
356 #define R_SATA_MEM_AHCI_P4CMD 0x318
357 #define R_SATA_MEM_AHCI_P5CMD 0x398
358 #define R_SATA_MEM_AHCI_P6CMD 0x418
359 #define R_SATA_MEM_AHCI_P7CMD 0x498
360 #define R_SATA_MEM_AHCI_P0DEVSLP 0x144
361 #define R_SATA_MEM_AHCI_P1DEVSLP 0x1C4
362 #define R_SATA_MEM_AHCI_P2DEVSLP 0x244
363 #define R_SATA_MEM_AHCI_P3DEVSLP 0x2C4
364 #define R_SATA_MEM_AHCI_P4DEVSLP 0x344
365 #define R_SATA_MEM_AHCI_P5DEVSLP 0x3C4
366 #define R_SATA_MEM_AHCI_P6DEVSLP 0x444
367 #define R_SATA_MEM_AHCI_P7DEVSLP 0x4C4
368 #define B_SATA_MEM_AHCI_PxDEVSLP_DSP BIT1
369 #define B_SATA_MEM_AHCI_PxDEVSLP_ADSE BIT0
370 #define B_SATA_MEM_AHCI_PxDEVSLP_DITO_MASK 0x01FF8000
371 #define V_SATA_MEM_AHCI_PxDEVSLP_DITO_625 0x01388000
372 #define B_SATA_MEM_AHCI_PxDEVSLP_DM_MASK 0x1E000000
373 #define V_SATA_MEM_AHCI_PxDEVSLP_DM_16 0x1E000000
374 #define B_SATA_MEM_AHCI_PxCMD_ICC (BIT31 | BIT30 | BIT29 | BIT28)
375 #define B_SATA_MEM_AHCI_PxCMD_MASK (BIT27 | BIT26 | BIT22 | BIT21 | BIT19 | BIT18)
376 #define B_SATA_MEM_AHCI_PxCMD_ASP BIT27
377 #define B_SATA_MEM_AHCI_PxCMD_ALPE BIT26
378 #define B_SATA_MEM_AHCI_PxCMD_DLAE BIT25
379 #define B_SATA_MEM_AHCI_PxCMD_ATAPI BIT24
380 #define B_SATA_MEM_AHCI_PxCMD_APSTE BIT23
381 #define B_SATA_MEM_AHCI_PxCMD_ESP BIT21 ///< Used with an external SATA device
382 #define B_SATA_MEM_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch Attached to Port
383 #define B_SATA_MEM_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable
384 #define B_SATA_MEM_AHCI_PxCMD_CR BIT15
385 #define B_SATA_MEM_AHCI_PxCMD_FR BIT14
386 #define B_SATA_MEM_AHCI_PxCMD_ISS BIT13
387 #define B_SATA_MEM_AHCI_PxCMD_CCS 0x00001F00
388 #define B_SATA_MEM_AHCI_PxCMD_FRE BIT4
389 #define B_SATA_MEM_AHCI_PxCMD_CLO BIT3
390 #define B_SATA_MEM_AHCI_PxCMD_POD BIT2
391 #define B_SATA_MEM_AHCI_PxCMD_SUD BIT1
392 #define B_SATA_MEM_AHCI_PxCMD_ST BIT0
393 #define R_SATA_MEM_AHCI_P0SCTL 0x12C
394 #define R_SATA_MEM_AHCI_P1SCTL 0x1AC
395 #define R_SATA_MEM_AHCI_P2SCTL 0x22C
396 #define R_SATA_MEM_AHCI_P3SCTL 0x2AC
397 #define R_SATA_MEM_AHCI_P4SCTL 0x32C
398 #define R_SATA_MEM_AHCI_P5SCTL 0x3AC
399 #define R_SATA_MEM_AHCI_P6SCTL 0x42C
400 #define B_SATA_MEM_AHCI_PXSCTL_IPM 0x00000F00
401 #define V_SATA_MEM_AHCI_PXSCTL_IPM_0 0x00000000
402 #define V_SATA_MEM_AHCI_PXSCTL_IPM_1 0x00000100
403 #define V_SATA_MEM_AHCI_PXSCTL_IPM_2 0x00000200
404 #define V_SATA_MEM_AHCI_PXSCTL_IPM_3 0x00000300
405 #define B_SATA_MEM_AHCI_PXSCTL_SPD 0x000000F0
406 #define V_SATA_MEM_AHCI_PXSCTL_SPD_0 0x00000000
407 #define V_SATA_MEM_AHCI_PXSCTL_SPD_1 0x00000010
408 #define V_SATA_MEM_AHCI_PXSCTL_SPD_2 0x00000020
409 #define V_SATA_MEM_AHCI_PXSCTL_SPD_3 0x00000030
410 #define B_SATA_MEM_AHCI_PXSCTL_DET 0x0000000F
411 #define V_SATA_MEM_AHCI_PXSCTL_DET_0 0x00000000
412 #define V_SATA_MEM_AHCI_PXSCTL_DET_1 0x00000001
413 #define V_SATA_MEM_AHCI_PXSCTL_DET_4 0x00000004
414
415 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataSocLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SataSocLib.h File Reference

Header file for SATA SoC library. More...

#include <SataCtrl.h>
#include <Base.h>
#include <Uefi/UefiBaseType.h>
Include dependency graph for SataSocLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | SataGetController (IN UINT32 SataCtrlIndex, OUT SATA_CONTROLLER *SataController)
Get SATA controller instance. More...
UINT8 | MaxSataControllerNum (VOID)
Get Maximum Sata Controller Number. More...
UINT8 | MaxSataPortNum (IN UINT32 SataCtrlIndex)
Get Maximum Sata Port Number. More...
BOOLEAN | IsRemappingSupportedOnSata (IN UINT32 SataCtrlIndex)
Check if SATA controller supports RST remapping. More...
BOOLEAN | IsSataPowerGatingSupported (IN UINT32 SataCtrlIndex)
Checks if SoC supports the SATA PGD power down on given SATA controller. More...

Detailed Description

Header file for SATA SoC library.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2020 - 2021 Intel Corporation. All rights reserved This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by the license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation. This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.
Specification Reference:

Definition in file SataSocLib.h.

Function Documentation

◆ IsRemappingSupportedOnSata()

BOOLEAN IsRemappingSupportedOnSata ( IN UINT32 SataCtrlIndex )

Check if SATA controller supports RST remapping.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
TRUE | Controller supports remapping
FALSE | Controller does not support remapping

◆ IsSataPowerGatingSupported()

BOOLEAN IsSataPowerGatingSupported ( IN UINT32 SataCtrlIndex )

Checks if SoC supports the SATA PGD power down on given SATA controller.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
TRUE | SATA PGD power down supported
FALSE | SATA PGD power down not supported

◆ MaxSataControllerNum()

UINT8 MaxSataControllerNum ( VOID )

Get Maximum Sata Controller Number.

Return values
Maximum Sata Controller Number

◆ MaxSataPortNum()

UINT8 MaxSataPortNum ( IN UINT32 SataCtrlIndex )

Get Maximum Sata Port Number.

Parameters
[in] SataCtrlIndex SATA controller index
Return values
Maximum Sata Port Number

◆ SataGetController()

EFI_STATUS SataGetController | ( | IN UINT32 | SataCtrlIndex,
 |  | OUT SATA_CONTROLLER * | SataController
 | ) |  |

Get SATA controller instance.

Parameters
[in] | SataCtrlIndex | SATA controller index
[out] | SataController | Pointer to SATA controller structure
Return values
EFI_SUCCESS - Completted successfully EFI_INVALID_PARAMETER - SataController NULL or SataCtrlIndex out of the range
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SataSocLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SataSocLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SATA SoC library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2020 - 2021 Intel Corporation. All rights reserved
7 This software and associated documentation (if any) is furnished
8 under a license and may only be used or copied in accordance
9 with the terms of the license. Except as permitted by the
10 license, no part of this software or documentation may be
11 reproduced, stored in a retrieval system, or transmitted in any
12 form or by any means without the express written consent of
13 Intel Corporation.
14 This file contains an 'Intel Peripheral Driver' and is uniquely
15 identified as "Intel Reference Module" and is licensed for Intel
16 CPUs and chipsets under the terms of your license agreement with
17 Intel or your vendor. This file may be modified by the user, subject
18 to additional terms of the license agreement.
19
20 @par Specification Reference:
21 **/
22 #ifndef _SATA_SOC_LIB_H_
23 #define _SATA_SOC_LIB_H_
24
25 #include <SataCtrl.h>
26 #include <Base.h>
27 #include <Uefi/UefiBaseType.h>
28
29 #define SATA_1_CONTROLLER_INDEX 0
30 #define SATA_2_CONTROLLER_INDEX 1
31 #define SATA_3_CONTROLLER_INDEX 2
32
33 /**
34 Get SATA controller instance
35
36 @param[in] SataCtrlIndex SATA controller index
37 @param[out] SataController Pointer to SATA controller structure
38
39 @retval EFI_SUCCESS - Completted successfully
40 EFI_INVALID_PARAMETER - SataController NULL or SataCtrlIndex out of the range
41 **/
42 EFI_STATUS
43 SataGetController (
44 IN UINT32 SataCtrlIndex,
45 OUT SATA_CONTROLLER *SataController
46 );
47
48 /**
49 Get Maximum Sata Controller Number
50
51 @retval Maximum Sata Controller Number
52 **/
53 UINT8
54 MaxSataControllerNum (
55 VOID
56 );
57
58 /**
59 Get Maximum Sata Port Number
60
61 @param[in] SataCtrlIndex SATA controller index
62
63 @retval Maximum Sata Port Number
64 **/
65 UINT8
66 MaxSataPortNum (
67 IN UINT32 SataCtrlIndex
68 );
69
70 /**
71 Check if SATA controller supports RST remapping
72
73 @param[in] SataCtrlIndex SATA controller index
74
75 @retval TRUE Controller supports remapping
76 @retval FALSE Controller does not support remapping
77 **/
78 BOOLEAN
79 IsRemappingSupportedOnSata (
80 IN UINT32 SataCtrlIndex
81 );
82
83 /**
84 Checks if SoC supports the SATA PGD power down on given
85 SATA controller.
86
87 @param[in] SataCtrlIndex SATA controller index
88
89 @retval TRUE SATA PGD power down supported
90 @retval FALSE SATA PGD power down not supported
91 **/
92 BOOLEAN
93 IsSataPowerGatingSupported (
94 IN UINT32 SataCtrlIndex
95 );
96
97 #endif // _SATA_SOC_LIB_H_
IsSataPowerGatingSupported
BOOLEAN IsSataPowerGatingSupported(IN UINT32 SataCtrlIndex)
Checks if SoC supports the SATA PGD power down on given SATA controller.
SataGetController
EFI_STATUS SataGetController(IN UINT32 SataCtrlIndex, OUT SATA_CONTROLLER *SataController)
Get SATA controller instance.
MaxSataPortNum
UINT8 MaxSataPortNum(IN UINT32 SataCtrlIndex)
Get Maximum Sata Port Number.
MaxSataControllerNum
UINT8 MaxSataControllerNum(VOID)
Get Maximum Sata Controller Number.
IsRemappingSupportedOnSata
BOOLEAN IsRemappingSupportedOnSata(IN UINT32 SataCtrlIndex)
Check if SATA controller supports RST remapping.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ScsConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Scs
Classes
ScsConfig.h File Reference

Scs policy. More...

#include <ConfigBlock.h>
#include <PchLimits.h>
Include dependency graph for ScsConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SCS_SD_DLL
This structre holds the DLL configuration register values that will be programmed by RC if EnableCustomDlls field is set to TRUE. More...
struct | MUX_GPIO_PARAM
SD GPIO settings. More...

Detailed Description

Scs policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ScsConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ScsConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Scs
ScsConfig.h
Go to the documentation of this file.
1 /** @file
2 Scs policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SCS_CONFIG_H_
36 #define _SCS_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <PchLimits.h>
40
41 #define SCS_SDCARD_CONFIG_REVISION 1
42 #define SCS_EMMC_CONFIG_REVISION 1
43 #define SCS_UFS_CONFIG_REVISION 1
44 #define SCS_EMMC_DXE_CONFIG_REVISION 1
45 #define SCS_SDCARD_MAX_DATA_GPIOS 4
46 #define SCS_EMMC_MAX_DATA_GPIOS 8
47 extern EFI_GUID gSdCardConfigGuid;
48 extern EFI_GUID gEmmcConfigGuid;
49 extern EFI_GUID gUfsConfigGuid;
50 extern EFI_GUID gEmmcDxeConfigGuid;
51
52 #pragma pack (push,1)
53
54 /**
55 This structre holds the DLL configuration
56 register values that will be programmed by RC
57 if EnableCustomDlls field is set to TRUE. Those
58 policies should be used by platform if default values
59 provided by RC are not sufficient to provide stable operation
60 at all supported spped modes. RC will blindly set the DLL values
61 as provided in this structre.
62
63 For help with obtaining valid DLL values for your platform please
64 contact enabling support.
65 **/
66 typedef struct {
67 UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control
68 UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control 1
69 UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control 2
70 UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay Control 1
71 UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay Control 2
72 UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Control, valid only for eMMC
73 } SCS_SD_DLL;
74
75 /**
76 SD GPIO settings
77 **/
78 typedef struct {
79 /**
80 GPIO signals pin muxing settings. If signal can be enable only on a single pin
81 then this parameter should be set to 0. Refer to GPIO_*_MUXING_SDCARD_*x_* in GpioPins*.h
82 for supported settings on a given platform
83 **/
84 UINT32 PinMux;
85 /**
86 GPIO Pads Internal Termination.
87 For more information please see Platform Design Guide.
88 Check GPIO_ELECTRICAL_CONFIG for reference
89 **/
90 UINT32 PadTermination;
91 } MUX_GPIO_PARAM;
92
93 typedef struct {
94 MUX_GPIO_PARAM PowerEnable;
95 MUX_GPIO_PARAM Cmd;
96 MUX_GPIO_PARAM Data[SCS_SDCARD_MAX_DATA_GPIOS];
97 MUX_GPIO_PARAM Cdb;
98 MUX_GPIO_PARAM Clk;
99 MUX_GPIO_PARAM Wp;
100 } SCS_SDCARD_GPIO_CONFIG;
101
102 typedef struct {
103 MUX_GPIO_PARAM Cmd;
104 MUX_GPIO_PARAM Data[SCS_EMMC_MAX_DATA_GPIOS];
105 MUX_GPIO_PARAM Rclk;
106 MUX_GPIO_PARAM Clk;
107 MUX_GPIO_PARAM Resetb;
108 } SCS_EMMC_GPIO_CONFIG;
109
110 typedef struct {
111 CONFIG_BLOCK_HEADER Header;
112
113 UINT32 Enable : 1; ///< Enable/Disable SdCard 0: Disabled, <b>1: Enabled</b>
114 UINT32 PowerEnableActiveHigh : 1; ///< Determine SD_PWREN# polarity 0: Active low, <b>1: Active high</b>
115 UINT32 UseCustomDlls : 1; ///< Use tuned DLL values from policy <b>0: Use default DLL</b>, 1: Use values from TunedDllValues field
116 UINT32 Reserved : 29;
117 SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL values for SD card
118 SCS_SDCARD_GPIO_CONFIG GpioConfig;
119 } SCS_SDCARD_CONFIG;
120
121 typedef struct {
122 UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value
123 UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value
124 UINT32 Reserved : 18;
125 } SCS_EMMC_TUNED_DLL;
126
127 typedef struct {
128 CONFIG_BLOCK_HEADER Header;
129
130 UINT32 Enable : 1; ///< Enable/Disable eMMC 0: Disabled, <b>1: Enabled</b>
131 UINT32 Hs400Supported : 1; ///< Enable/Disable eMMC HS400 support 0: Disabled, <b>1: Enabled</b>
132 UINT32 UseCustomDlls : 1; ///< Use custom DLL values from policy <b>0: Use default DLL</b>, 1: Use values from TunedDllValues field
133 UINT32 Reserved : 29;
134 SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL values for eMMC ///< Structure containing tuned DLL settings for eMMC
135 SCS_EMMC_GPIO_CONFIG GpioConfig;
136 } SCS_EMMC_CONFIG;
137
138 typedef enum {
139 DriverStrength33Ohm = 0,
140 DriverStrength40Ohm,
141 DriverStrength50Ohm
142 } SCS_EMMC_DRIVER_STRENGTH;
143
144 typedef struct {
145 UINT32 TuningSuccessful : 1; ///< Informs software tuning module about previous software tuning status.
146 UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value returned from software tuning module
147 UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value returned from software tuning module
148 UINT32 Reserved : 17;
149 } SCS_EMMC_SOFTWARE_TUNING_RESULTS;
150
151 typedef struct {
152 CONFIG_BLOCK_HEADER Header;
153
154 UINT32 EnableSoftwareHs400Tuning : 1; ///< Enable/Disable software eMMC HS400 tuning: <b>0 - Disable</b>, 1 - Enable
155 UINT32 DriverStrength : 2; ///< I/O driver strength: 0 - 33 Ohm, <b>1 - 40 Ohm</b>, 2 - 50 Ohm
156 UINT32 Reserved : 29;
157 EFI_LBA TuningLba; ///< Specifies LBA which will be used during software tuning process.
158 SCS_EMMC_SOFTWARE_TUNING_RESULTS PreviousTuningResults; ///< Informes software tuning module about previous software tuning results.} SCS_EMMC_DXE_CONFIG;
159 } SCS_EMMC_DXE_CONFIG;
160
161 typedef struct {
162 UINT32 Enable : 1; ///< Enable/Disable UFS controller 0: Disabled, <b>1: Enabled</b>
163 UINT32 InlineEncryption : 1; ///< Enable/Disable UFS Inline Encryption feature. 0: Disabled, 1: Enabled
164 UINT32 Reserved : 30;
165 } SCS_UFS_CONTROLLER_CONFIG;
166
167 typedef struct {
168 CONFIG_BLOCK_HEADER Header;
169
170 SCS_UFS_CONTROLLER_CONFIG UfsControllerConfig[PCH_MAX_UFS_DEV_NUM]; ///< Array of SCS_UFS_CONTROLLER_CONFIG stuctures
171 } SCS_UFS_CONFIG;
172
173 #pragma pack (pop)
174
175 #endif // _SCS_CONFIG_H_
ConfigBlock.h
Header file for Config Block Lib implementation.
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
MUX_GPIO_PARAM::PadTermination
UINT32 PadTermination
GPIO Pads Internal Termination.
Definition: ScsConfig.h:90
MUX_GPIO_PARAM
SD GPIO settings.
Definition: ScsConfig.h:78
SCS_SD_DLL
This structre holds the DLL configuration register values that will be programmed by RC if EnableCust...
Definition: ScsConfig.h:66
MUX_GPIO_PARAM::PinMux
UINT32 PinMux
GPIO signals pin muxing settings.
Definition: ScsConfig.h:84
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ScsInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
ScsInfoHob.h File Reference

The GUID definition for HOBs for SCS. More...

#include <PchLimits.h>
Include dependency graph for ScsInfoHob.h:

Go to the source code of this file.

Detailed Description

The GUID definition for HOBs for SCS.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ScsInfoHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ScsInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
ScsInfoHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for HOBs for SCS
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _SCS_INFO_HOB_H_
37 #define _SCS_INFO_HOB_H_
38
39 #include <PchLimits.h>
40
41 extern EFI_GUID gScsInfoHobGuid;
42
43 typedef struct {
44 UINT32 Supported : 1; ///< TRUE if UFS is supported by current hardware configuration
45 UINT32 Reserved : 31;
46 } SCS_UFS_INFO;
47
48 typedef struct {
49 UINT32 Supported : 1; ///< TRUE if SdCard is supported by current hardware configuration
50 UINT32 Reserved : 31;
51 } SCS_SDCARD_INFO;
52
53 typedef struct {
54 UINT32 Supported : 1; ///< TRUE if eMMC is supported by current hardware configuration
55 UINT32 Reserved : 31;
56 } SCS_EMMC_INFO;
57
58 typedef struct {
59 SCS_EMMC_INFO EmmcInfo;
60 SCS_SDCARD_INFO SdCardInfo;
61 SCS_UFS_INFO UfsInfo[PCH_MAX_UFS_DEV_NUM];
62 } SCS_INFO_HOB;
63
64 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SecPlatformLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SecPlatformLib.h File Reference

Prototype of SEC Platform hook library. More...

#include <Ppi/SecPlatformInformation.h>
#include <Ppi/SecPerformance.h>
Include dependency graph for SecPlatformLib.h:

Go to the source code of this file.

Functions

EFI_PEI_PPI_DESCRIPTOR * | SecPlatformMain (IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData)
A developer supplied function to perform platform specific operations. More...
EFI_STATUS | SecPlatformInformation (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
This interface conveys state information out of the Security (SEC) phase into PEI. More...
EFI_STATUS | SecGetPerformance (IN CONST EFI_PEI_SERVICES **PeiServices, IN PEI_SEC_PERFORMANCE_PPI *This, OUT FIRMWARE_SEC_PERFORMANCE *Performance)
This interface conveys performance information out of the Security (SEC) phase into PEI. More...

Detailed Description

Prototype of SEC Platform hook library.

Copyright
INTEL CONFIDENTIAL Copyright 2008 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SecPlatformLib.h.

Function Documentation

◆ SecGetPerformance()

EFI_STATUS SecGetPerformance | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN PEI_SEC_PERFORMANCE_PPI * | This,
 |  | OUT FIRMWARE_SEC_PERFORMANCE * | Performance
 | ) |  |

This interface conveys performance information out of the Security (SEC) phase into PEI.

This service is published by the SEC phase. The SEC phase handoff has an optional EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the PEI Foundation. As such, if the platform supports collecting performance data in SEC, this information is encapsulated into the data structure abstracted by this service. This information is collected for the boot-strap processor (BSP) on IA-32.

Parameters
[in] | PeiServices | The pointer to the PEI Services Table.
[in] | This | The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
[out] | Performance | The pointer to performance data collected in SEC phase.
Return values
EFI_SUCCESS The data was successfully returned.

◆ SecPlatformInformation()

EFI_STATUS SecPlatformInformation | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD * | PlatformInformationRecord
 | ) |  |

This interface conveys state information out of the Security (SEC) phase into PEI.

Parameters
PeiServices | Pointer to the PEI Services Table.
StructureSize | Pointer to the variable describing size of the input buffer.
PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.

◆ SecPlatformMain()

EFI_PEI_PPI_DESCRIPTOR* SecPlatformMain ( IN OUT EFI_SEC_PEI_HAND_OFF * SecCoreData )

A developer supplied function to perform platform specific operations.

It's a developer supplied function to perform any operations appropriate to a given platform. It's invoked just before passing control to PEI core by SEC core. Platform developer may modify the SecCoreData passed to PEI Core. It returns a platform specific PPI list that platform wishes to pass to PEI core. The Generic SEC core module will merge this list to join the final list passed to PEI core.

Parameters
SecCoreData The same parameter as passing to PEI core. It could be overridden by this function.
Returns
The platform specific PPI list to be passed to PEI core or NULL if there is no need of such platform specific PPI list.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SecPlatformLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SecPlatformLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of SEC Platform hook library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2008 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33
34 **/
35
36 #ifndef _SEC_PLATFORM_LIB_H_
37 #define _SEC_PLATFORM_LIB_H_
38
39 #include <Ppi/SecPlatformInformation.h>
40 #include <Ppi/SecPerformance.h>
41
42 /**
43 A developer supplied function to perform platform specific operations.
44
45 It's a developer supplied function to perform any operations appropriate to a
46 given platform. It's invoked just before passing control to PEI core by SEC
47 core. Platform developer may modify the SecCoreData passed to PEI Core.
48 It returns a platform specific PPI list that platform wishes to pass to PEI core.
49 The Generic SEC core module will merge this list to join the final list passed to
50 PEI core.
51
52 @param SecCoreData The same parameter as passing to PEI core. It
53 could be overridden by this function.
54
55 @return The platform specific PPI list to be passed to PEI core or
56 NULL if there is no need of such platform specific PPI list.
57
58 **/
59 EFI_PEI_PPI_DESCRIPTOR *
60 EFIAPI
61 SecPlatformMain (
62 IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
63 );
64
65
66 /**
67 This interface conveys state information out of the Security (SEC) phase into PEI.
68
69 @param PeiServices Pointer to the PEI Services Table.
70 @param StructureSize Pointer to the variable describing size of the input buffer.
71 @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
72
73 @retval EFI_SUCCESS The data was successfully returned.
74 @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
75
76 **/
77 EFI_STATUS
78 EFIAPI
79 SecPlatformInformation (
80 IN CONST EFI_PEI_SERVICES **PeiServices,
81 IN OUT UINT64 *StructureSize,
82 OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
83 );
84
85 /**
86 This interface conveys performance information out of the Security (SEC) phase into PEI.
87
88 This service is published by the SEC phase. The SEC phase handoff has an optional
89 EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
90 PEI Foundation. As such, if the platform supports collecting performance data in SEC,
91 this information is encapsulated into the data structure abstracted by this service.
92 This information is collected for the boot-strap processor (BSP) on IA-32.
93
94 @param[in] PeiServices The pointer to the PEI Services Table.
95 @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
96 @param[out] Performance The pointer to performance data collected in SEC phase.
97
98 @retval EFI_SUCCESS The data was successfully returned.
99 **/
100 EFI_STATUS
101 EFIAPI
102 SecGetPerformance (
103 IN CONST EFI_PEI_SERVICES **PeiServices,
104 IN PEI_SEC_PERFORMANCE_PPI *This,
105 OUT FIRMWARE_SEC_PERFORMANCE *Performance
106 );
107
108 #endif
109
SecPlatformMain
EFI_PEI_PPI_DESCRIPTOR * SecPlatformMain(IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData)
A developer supplied function to perform platform specific operations.
SecGetPerformance
EFI_STATUS SecGetPerformance(IN CONST EFI_PEI_SERVICES **PeiServices, IN PEI_SEC_PERFORMANCE_PPI *This, OUT FIRMWARE_SEC_PERFORMANCE *Performance)
This interface conveys performance information out of the Security (SEC) phase into PEI.
SecPlatformInformation
EFI_STATUS SecPlatformInformation(IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
This interface conveys state information out of the Security (SEC) phase into PEI.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SerialIoAccessLib.h File Reference

Header file for Serial Io Common Lib. More...

Go to the source code of this file.

Functions

UINT64 | GetSerialIoBar (IN UINT64 PciCfgBase)
Returns BAR0. More...
UINT64 | GetSerialIoI2cPciCfg (IN UINT8 I2cNumber)
Returns I2C Pci Config Space. More...
UINT64 | GetSerialIoSpiPciCfg (IN UINT8 SpiNumber)
Returns SPI Pci Config Space. More...
UINT64 | GetSerialIoUartPciCfg (IN UINT8 UartNumber)
Returns UART Pci Config Space. More...
BOOLEAN | IsSerialIoI2cDeviceId (IN UINT16 PciDevId, OUT UINT8 *I2cNumber)
Checks if Device with given PciDeviceId is one of SerialIo I2C controllers If yes, its number is returned through I2cIndex parameter, otherwise I2cIndex is not updated. More...
BOOLEAN | IsSerialIoI2cFunction0Enabled (IN UINT8 I2cIndex)
Checks if I2c is Function 0 Enabled. More...
BOOLEAN | IsSerialIoUartFunction0Enabled (IN UINT8 UartIndex)
Checks if Uart is Function 0 Enabled. More...
BOOLEAN | IsSerialIoSpiFunction0Enabled (IN UINT8 SpiIndex)
Checks if Spi is Function 0 Enabled. More...

Detailed Description

Header file for Serial Io Common Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file SerialIoAccessLib.h.

Function Documentation

◆ GetSerialIoBar()

UINT64 GetSerialIoBar ( IN UINT64 PciCfgBase )

Returns BAR0.

Parameters
[in] PciCfgBase Pci Config Base
Return values
64bit MMIO BAR Address

◆ GetSerialIoI2cPciCfg()

UINT64 GetSerialIoI2cPciCfg ( IN UINT8 I2cNumber )

Returns I2C Pci Config Space.

Parameters
[in] I2cNumber I2C Number
Return values
I2C Pci Config Space Address

◆ GetSerialIoSpiPciCfg()

UINT64 GetSerialIoSpiPciCfg ( IN UINT8 SpiNumber )

Returns SPI Pci Config Space.

Parameters
[in] SpiNumber SPI Number
Return values
SPI Pci Config Space Address

◆ GetSerialIoUartPciCfg()

UINT64 GetSerialIoUartPciCfg ( IN UINT8 UartNumber )

Returns UART Pci Config Space.

Parameters
[in] UartNumber UART Number
Return values
UART Pci Config Space Address

◆ IsSerialIoI2cDeviceId()

BOOLEAN IsSerialIoI2cDeviceId | ( | IN UINT16 | PciDevId,
 |  | OUT UINT8 * | I2cNumber
 | ) |  |

Checks if Device with given PciDeviceId is one of SerialIo I2C controllers If yes, its number is returned through I2cIndex parameter, otherwise I2cIndex is not updated.

Parameters
[in] | PciDevId | Device ID
[out] | I2cNumber | Number of SerialIo I2C controller
Return values
TRUE | yes it is a SerialIo I2C controller
FALSE | no it isn't a SerialIo I2C controller

◆ IsSerialIoI2cFunction0Enabled()

BOOLEAN IsSerialIoI2cFunction0Enabled ( IN UINT8 I2cIndex )

Checks if I2c is Function 0 Enabled.

Parameters
[in] I2cIndex Number of the SerialIo I2C controller
Return values
TRUE | Enabled
FALSE | Disabled

◆ IsSerialIoSpiFunction0Enabled()

BOOLEAN IsSerialIoSpiFunction0Enabled ( IN UINT8 SpiIndex )

Checks if Spi is Function 0 Enabled.

Parameters
[in] SpiIndex Number of the SerialIo Spi controller
Return values
TRUE | Enabled
FALSE | Disabled

◆ IsSerialIoUartFunction0Enabled()

BOOLEAN IsSerialIoUartFunction0Enabled ( IN UINT8 UartIndex )

Checks if Uart is Function 0 Enabled.

Parameters
[in] UartIndex Number of the SerialIo Uart controller
Return values
TRUE | Enabled
FALSE | Disabled
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoAccessLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Serial Io Common Lib
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _SERIAL_IO_ACCESS_LIB_H_
36 #define _SERIAL_IO_ACCESS_LIB_H_
37
38 /**
39 Returns BAR0
40
41 @param[in] PciCfgBase Pci Config Base
42
43 @retval 64bit MMIO BAR Address
44 **/
45 UINT64
46 GetSerialIoBar (
47 IN UINT64 PciCfgBase
48 );
49
50 /**
51 Returns I2C Pci Config Space
52
53 @param[in] I2cNumber I2C Number
54
55 @retval I2C Pci Config Space Address
56 **/
57 UINT64
58 GetSerialIoI2cPciCfg (
59 IN UINT8 I2cNumber
60 );
61
62 /**
63 Returns SPI Pci Config Space
64
65 @param[in] SpiNumber SPI Number
66
67 @retval SPI Pci Config Space Address
68 **/
69 UINT64
70 GetSerialIoSpiPciCfg (
71 IN UINT8 SpiNumber
72 );
73
74 /**
75 Returns UART Pci Config Space
76
77 @param[in] UartNumber UART Number
78
79 @retval UART Pci Config Space Address
80 **/
81 UINT64
82 GetSerialIoUartPciCfg (
83 IN UINT8 UartNumber
84 );
85
86 /**
87 Checks if Device with given PciDeviceId is one of SerialIo I2C controllers
88 If yes, its number is returned through I2cIndex parameter, otherwise I2cIndex is not updated
89
90 @param[in] PciDevId Device ID
91 @param[out] I2cNumber Number of SerialIo I2C controller
92
93 @retval TRUE yes it is a SerialIo I2C controller
94 @retval FALSE no it isn't a SerialIo I2C controller
95 **/
96 BOOLEAN
97 IsSerialIoI2cDeviceId (
98 IN UINT16 PciDevId,
99 OUT UINT8 *I2cNumber
100 );
101
102 /**
103 Checks if I2c is Function 0 Enabled
104
105 @param[in] I2cIndex Number of the SerialIo I2C controller
106
107 @retval TRUE Enabled
108 @retval FALSE Disabled
109 **/
110 BOOLEAN
111 IsSerialIoI2cFunction0Enabled (
112 IN UINT8 I2cIndex
113 );
114
115 /**
116 Checks if Uart is Function 0 Enabled
117
118 @param[in] UartIndex Number of the SerialIo Uart controller
119
120 @retval TRUE Enabled
121 @retval FALSE Disabled
122 **/
123 BOOLEAN
124 IsSerialIoUartFunction0Enabled (
125 IN UINT8 UartIndex
126 );
127
128 /**
129 Checks if Spi is Function 0 Enabled
130
131 @param[in] SpiIndex Number of the SerialIo Spi controller
132
133 @retval TRUE Enabled
134 @retval FALSE Disabled
135 **/
136 BOOLEAN
137 IsSerialIoSpiFunction0Enabled (
138 IN UINT8 SpiIndex
139 );
140
141 #endif // _SERIAL_IO_ACCESS_LIB_H_
IsSerialIoSpiFunction0Enabled
BOOLEAN IsSerialIoSpiFunction0Enabled(IN UINT8 SpiIndex)
Checks if Spi is Function 0 Enabled.
GetSerialIoSpiPciCfg
UINT64 GetSerialIoSpiPciCfg(IN UINT8 SpiNumber)
Returns SPI Pci Config Space.
GetSerialIoUartPciCfg
UINT64 GetSerialIoUartPciCfg(IN UINT8 UartNumber)
Returns UART Pci Config Space.
IsSerialIoI2cDeviceId
BOOLEAN IsSerialIoI2cDeviceId(IN UINT16 PciDevId, OUT UINT8 *I2cNumber)
Checks if Device with given PciDeviceId is one of SerialIo I2C controllers If yes,...
GetSerialIoI2cPciCfg
UINT64 GetSerialIoI2cPciCfg(IN UINT8 I2cNumber)
Returns I2C Pci Config Space.
IsSerialIoUartFunction0Enabled
BOOLEAN IsSerialIoUartFunction0Enabled(IN UINT8 UartIndex)
Checks if Uart is Function 0 Enabled.
GetSerialIoBar
UINT64 GetSerialIoBar(IN UINT64 PciCfgBase)
Returns BAR0.
IsSerialIoI2cFunction0Enabled
BOOLEAN IsSerialIoI2cFunction0Enabled(IN UINT8 I2cIndex)
Checks if I2c is Function 0 Enabled.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
Classes
SerialIoConfig.h File Reference

Serial IO policy. More...

#include <SerialIoDevices.h>
Include dependency graph for SerialIoConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers. More...

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIoConfig.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_CONFIG_H_
36 #define _SERIAL_IO_CONFIG_H_
37
38 #define SERIAL_IO_CONFIG_REVISION 2
39 extern EFI_GUID gSerialIoConfigGuid;
40
41 #include <SerialIoDevices.h>
42
43 #pragma pack (push,1)
44
45 /**
46 The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
47
48 <b>Revision 1:</b>
49 - Inital version.
50 <b>Revision 2:</b>
51 - Modified SPI Config to support pinmux functionality.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
55 SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
56 SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
57 SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
58 } SERIAL_IO_CONFIG;
59
60 #pragma pack (pop)
61
62 #endif // _SERIAL_IO_CONFIG_H_
SerialIoDevices.h
Serial IO policy.
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:236
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:94
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SERIAL_IO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SerialIoConfig.h:54
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:174
SERIAL_IO_CONFIG
The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers.
Definition: SerialIoConfig.h:53
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoDevices.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Enumerations
SerialIoDevices.h File Reference

Serial IO policy. More...

#include <Protocol/SerialIo.h>
#include <PchLimits.h>
Include dependency graph for SerialIoDevices.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SPI_PIN_MUX
SPI signals pin muxing settings. More...
struct | SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller. More...
struct | SERIAL_IO_UART_ATTRIBUTES
UART Settings. More...
struct | UART_PIN_MUX
UART signals pin muxing settings. More...
struct | SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration. More...
struct | I2C_PIN_MUX
I2C signals pin muxing settings. More...
struct | SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration. More...

Enumerations

enum | SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller. More...
enum | SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
enum | SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller. More...
enum | SERIAL_IO_UART_PG
enum | SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller. More...

Detailed Description

Serial IO policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoDevices.h.

Enumeration Type Documentation

◆ SERIAL_IO_I2C_MODE

enum SERIAL_IO_I2C_MODE

Available working modes for SerialIo I2C Host Controller.

 0: SerialIoI2cDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoI2cPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoI2cHidden;
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.

Definition at line 217 of file SerialIoDevices.h.

◆ SERIAL_IO_SPI_MODE

enum SERIAL_IO_SPI_MODE

Available working modes for SerialIo SPI Host Controller.

 0: SerialIoSpiDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoSpiPci;

  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoSpiHidden;
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.

Definition at line 65 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_MODE

enum SERIAL_IO_UART_MODE

Available working modes for SerialIo UART Host Controller.

 0: SerialIoUartDisabled;
    - Device is placed in D3
    - Gpio configuration is skipped
    - PSF:
    !important! If given device is Function 0 and other higher functions on given device
                are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
                This is needed to allow PCI enumerator access functions above 0 in a multifunction device.

1: SerialIoUartPci;

  • Designated for Serial IO UART OS driver usage
  • Gpio pin configuration in native mode for each assigned pin
  • Device will be enabled in PSF
  • Only BAR0 will be enabled 2: SerialIoUartHidden;
  • Designated for BIOS and/or DBG2 OS kernel debug
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
    Note
    If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space. 3: SerialIoUartCom;
  • Designated for 16550/PNP0501 compatible COM device
  • Gpio pin configuration in native mode for each assigned pin
  • Device disabled in the PSF
  • Both BARs are enabled, BAR1 becomes devices Pci Config Space
  • BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC 4: SerialIoUartSkipInit;
  • Gpio configuration is skipped
  • PSF configuration is skipped
  • BAR assignemnt is skipped
  • D-satate setting is skipped

Definition at line 140 of file SerialIoDevices.h.

◆ SERIAL_IO_UART_PG

enum SERIAL_IO_UART_PG
Enumerator
SerialIoUartPgDisabled | No _PS0/_PS3 support, device left in D0, after initialization.
SerialIoUartPgEnabled | In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPci Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only.
SerialIoUartPgAuto | _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,

Definition at line 183 of file SerialIoDevices.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoDevices.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SerialIoDevices.h
Go to the documentation of this file.
1 /** @file
2 Serial IO policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SERIAL_IO_DEVICES_H_
36 #define _SERIAL_IO_DEVICES_H_
37
38 #include <Protocol/SerialIo.h>
39 #include <PchLimits.h>
40
41 #pragma pack (push,1)
42
43 /**
44 Available working modes for SerialIo SPI Host Controller
45
46 0: SerialIoSpiDisabled;
47 - Device is placed in D3
48 - Gpio configuration is skipped
49 - PSF:
50 !important! If given device is Function 0 and other higher functions on given device
51 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
52 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
53 <b>1: SerialIoSpiPci;</b>
54 - Gpio pin configuration in native mode for each assigned pin
55 - Device will be enabled in PSF
56 - Only BAR0 will be enabled
57 2: SerialIoSpiHidden;
58 - Gpio pin configuration in native mode for each assigned pin
59 - Device disabled in the PSF
60 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
61 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
62 @note
63 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
64 **/
65 typedef enum {
66 SerialIoSpiDisabled,
67 SerialIoSpiPci,
68 SerialIoSpiHidden
69 } SERIAL_IO_SPI_MODE;
70
71 /**
72 Used to set Inactive/Idle polarity of Spi Chip Select
73 **/
74 typedef enum {
75 SerialIoSpiCsActiveLow = 0,
76 SerialIoSpiCsActiveHigh = 1
77 } SERIAL_IO_CS_POLARITY;
78
79 /**
80 SPI signals pin muxing settings. If signal can be enable only on a single pin
81 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
82 for supported settings on a given platform
83 **/
84 typedef struct {
85 UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
86 UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
87 UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
88 UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
89 } SPI_PIN_MUX;
90
91 /**
92 The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
93 **/
94 typedef struct {
95 UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
96 UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
97 UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
98 UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
99 UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
100 UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
101 SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
102 } SERIAL_IO_SPI_CONFIG;
103
104 /**
105 Available working modes for SerialIo UART Host Controller
106
107 0: SerialIoUartDisabled;
108 - Device is placed in D3
109 - Gpio configuration is skipped
110 - PSF:
111 !important! If given device is Function 0 and other higher functions on given device
112 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
113 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
114 <b>1: SerialIoUartPci;</b>
115 - Designated for Serial IO UART OS driver usage
116 - Gpio pin configuration in native mode for each assigned pin
117 - Device will be enabled in PSF
118 - Only BAR0 will be enabled
119 2: SerialIoUartHidden;
120 - Designated for BIOS and/or DBG2 OS kernel debug
121 - Gpio pin configuration in native mode for each assigned pin
122 - Device disabled in the PSF
123 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
124 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
125 @note
126 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
127 3: SerialIoUartCom;
128 - Designated for 16550/PNP0501 compatible COM device
129 - Gpio pin configuration in native mode for each assigned pin
130 - Device disabled in the PSF
131 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
132 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
133 4: SerialIoUartSkipInit;
134 - Gpio configuration is skipped
135 - PSF configuration is skipped
136 - BAR assignemnt is skipped
137 - D-satate setting is skipped
138
139 **/
140 typedef enum {
141 SerialIoUartDisabled,
142 SerialIoUartPci,
143 SerialIoUartHidden,
144 SerialIoUartCom,
145 SerialIoUartSkipInit
146 } SERIAL_IO_UART_MODE;
147
148 /**
149 UART Settings
150 **/
151 typedef struct {
152 UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
153 UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
154 UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
155 UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
156 UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
157 } SERIAL_IO_UART_ATTRIBUTES;
158
159 /**
160 UART signals pin muxing settings. If signal can be enable only on a single pin
161 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
162 for supported settings on a given platform
163 **/
164 typedef struct {
165 UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
166 UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
167 UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
168 UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
169 } UART_PIN_MUX;
170
171 /**
172 Serial IO UART Controller Configuration
173 **/
174 typedef struct {
175 SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
176 UART_PIN_MUX PinMux; ///< UART pin mux configuration
177 UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
178 UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
179 UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
180 UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
181 } SERIAL_IO_UART_CONFIG;
182
183 typedef enum {
184 SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
185 /**
186 In mode: SerialIoUartCom;
187 _PS0/_PS3 that supports getting device out of reset
188 In mode: SerialIoUartPci
189 Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
190 **/
191 SerialIoUartPgEnabled,
192 SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
193 } SERIAL_IO_UART_PG;
194
195 /**
196 Available working modes for SerialIo I2C Host Controller
197
198 0: SerialIoI2cDisabled;
199 - Device is placed in D3
200 - Gpio configuration is skipped
201 - PSF:
202 !important! If given device is Function 0 and other higher functions on given device
203 are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
204 This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
205 <b>1: SerialIoI2cPci;</b>
206 - Gpio pin configuration in native mode for each assigned pin
207 - Device will be enabled in PSF
208 - Only BAR0 will be enabled
209 2: SerialIoI2cHidden;
210 - Gpio pin configuration in native mode for each assigned pin
211 - Device disabled in the PSF
212 - Both BARs are enabled, BAR1 becomes devices Pci Config Space
213 - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
214 @note
215 If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
216 **/
217 typedef enum {
218 SerialIoI2cDisabled,
219 SerialIoI2cPci,
220 SerialIoI2cHidden
221 } SERIAL_IO_I2C_MODE;
222
223 /**
224 I2C signals pin muxing settings. If signal can be enable only on a single pin
225 then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
226 for supported settings on a given platform
227 **/
228 typedef struct {
229 UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
230 UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
231 } I2C_PIN_MUX;
232
233 /**
234 Serial IO I2C Controller Configuration
235 **/
236 typedef struct {
237 UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
238 /**
239 I2C Pads Internal Termination.
240 For more information please see Platform Design Guide.
241 Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
242 <b>GpioTermNone: No termination</b>,
243 GpioTermWpu1K: 1kOhm weak pull-up,
244 GpioTermWpu5K: 5kOhm weak pull-up,
245 GpioTermWpu20K: 20kOhm weak pull-up
246 **/
247 UINT8 PadTermination;
248 UINT8 Reserved[2];
249 I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
250 } SERIAL_IO_I2C_CONFIG;
251
252
253 #pragma pack (pop)
254
255 #endif // _SERIAL_IO_DEVICES_H_
SERIAL_IO_UART_ATTRIBUTES::BaudRate
UINT32 BaudRate
115200 Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
Definition: SerialIoDevices.h:152
SERIAL_IO_UART_CONFIG::Attributes
SERIAL_IO_UART_ATTRIBUTES Attributes
see SERIAL_IO_UART_ATTRIBUTES
Definition: SerialIoDevices.h:175
SERIAL_IO_SPI_CONFIG::DefaultCsOutput
UINT8 DefaultCsOutput
0 = CS0 CS1, CS2, CS3. Default CS used by the SPI HC
Definition: SerialIoDevices.h:96
SERIAL_IO_UART_MODE
SERIAL_IO_UART_MODE
Available working modes for SerialIo UART Host Controller.
Definition: SerialIoDevices.h:140
SPI_PIN_MUX::Mosi
UINT32 Mosi
MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*.
Definition: SerialIoDevices.h:88
SERIAL_IO_SPI_CONFIG::PinMux
SPI_PIN_MUX PinMux
SPI Pinmux configuration.
Definition: SerialIoDevices.h:101
SERIAL_IO_UART_CONFIG::Mode
UINT8 Mode
SerialIoUartPci see SERIAL_IO_UART_MODE
Definition: SerialIoDevices.h:177
SERIAL_IO_UART_ATTRIBUTES
UART Settings.
Definition: SerialIoDevices.h:151
SERIAL_IO_UART_ATTRIBUTES::StopBits
UINT8 StopBits
1 - One Stop Bit see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
Definition: SerialIoDevices.h:155
I2C_PIN_MUX
I2C signals pin muxing settings.
Definition: SerialIoDevices.h:228
SERIAL_IO_UART_CONFIG::PowerGating
UINT8 PowerGating
SerialIoUartPgAuto Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:179
SERIAL_IO_I2C_CONFIG
Serial IO I2C Controller Configuration.
Definition: SerialIoDevices.h:236
SERIAL_IO_UART_PG
SERIAL_IO_UART_PG
Definition: SerialIoDevices.h:183
I2C_PIN_MUX::Scl
UINT32 Scl
SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*.
Definition: SerialIoDevices.h:230
SERIAL_IO_UART_CONFIG::PinMux
UART_PIN_MUX PinMux
UART pin mux configuration.
Definition: SerialIoDevices.h:176
UART_PIN_MUX::Rx
UINT32 Rx
RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*.
Definition: SerialIoDevices.h:165
SERIAL_IO_I2C_CONFIG::PadTermination
UINT8 PadTermination
SerialIoI2cPci see SERIAL_IO_I2C_MODE
Definition: SerialIoDevices.h:247
SERIAL_IO_UART_CONFIG::DBG2
UINT8 DBG2
FALSE If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
Definition: SerialIoDevices.h:178
SERIAL_IO_UART_CONFIG::DmaEnable
UINT8 DmaEnable
TRUE Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
Definition: SerialIoDevices.h:180
UART_PIN_MUX::Rts
UINT32 Rts
RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*.
Definition: SerialIoDevices.h:167
SERIAL_IO_SPI_CONFIG
The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller.
Definition: SerialIoDevices.h:94
I2C_PIN_MUX::Sda
UINT32 Sda
SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*.
Definition: SerialIoDevices.h:229
SPI_PIN_MUX::Clk
UINT32 Clk
CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*.
Definition: SerialIoDevices.h:86
SERIAL_IO_SPI_MODE
SERIAL_IO_SPI_MODE
Available working modes for SerialIo SPI Host Controller.
Definition: SerialIoDevices.h:65
UART_PIN_MUX
UART signals pin muxing settings.
Definition: SerialIoDevices.h:164
SPI_PIN_MUX
SPI signals pin muxing settings.
Definition: SerialIoDevices.h:84
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:174
SERIAL_IO_CS_POLARITY
SERIAL_IO_CS_POLARITY
Used to set Inactive/Idle polarity of Spi Chip Select.
Definition: SerialIoDevices.h:74
SPI_PIN_MUX::Miso
UINT32 Miso
MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*.
Definition: SerialIoDevices.h:87
UART_PIN_MUX::Tx
UINT32 Tx
TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*.
Definition: SerialIoDevices.h:166
SERIAL_IO_UART_ATTRIBUTES::DataBits
UINT8 DataBits
8 MdePkg.dec PcdUartDefaultDataBits
Definition: SerialIoDevices.h:154
SERIAL_IO_UART_ATTRIBUTES::Parity
UINT8 Parity
1 - No Parity see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
Definition: SerialIoDevices.h:153
SERIAL_IO_I2C_MODE
SERIAL_IO_I2C_MODE
Available working modes for SerialIo I2C Host Controller.
Definition: SerialIoDevices.h:217
UART_PIN_MUX::Cts
UINT32 Cts
CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*.
Definition: SerialIoDevices.h:168
SERIAL_IO_SPI_CONFIG::CsMode
UINT8 CsMode
0 = HW Control 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
Definition: SerialIoDevices.h:99
SerialIoUartPgEnabled
@ SerialIoUartPgEnabled
In mode: SerialIoUartCom; _PS0/_PS3 that supports getting device out of reset In mode: SerialIoUartPc...
Definition: SerialIoDevices.h:191
SerialIoUartPgAuto
@ SerialIoUartPgAuto
_PS0 and _PS3, detection through ACPI if device was initialized prior to first PG....
Definition: SerialIoDevices.h:192
SerialIoUartPgDisabled
@ SerialIoUartPgDisabled
No _PS0/_PS3 support, device left in D0, after initialization.
Definition: SerialIoDevices.h:184
SERIAL_IO_UART_ATTRIBUTES::AutoFlow
UINT8 AutoFlow
FALSE IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
Definition: SerialIoDevices.h:156
SERIAL_IO_SPI_CONFIG::Mode
UINT8 Mode
SerialIoSpiPci see SERIAL_IO_SPI_MODE
Definition: SerialIoDevices.h:95
SERIAL_IO_SPI_CONFIG::CsState
UINT8 CsState
0 = CS is set to low 1 = CS is set to high
Definition: SerialIoDevices.h:100
SERIAL_IO_I2C_CONFIG::PinMux
I2C_PIN_MUX PinMux
I2C pin mux configuration.
Definition: SerialIoDevices.h:249
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SerialIoI2cLib.h File Reference

Basic I2C Librarary that allows I2C communication throguh Read/Write and Command Block operations. More...

Go to the source code of this file.

Functions

EFI_STATUS | SerialIoI2cWrite (IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN UINT32 WriteLength, IN UINT8 *WriteBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL, IN BOOLEAN Stop, IN BOOLEAN Restart)
Execute an I2C write. More...
EFI_STATUS | SerialIoI2cRead (IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN UINT32 ReadLength, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL, IN BOOLEAN Restart)
Execute an I2C read command. More...
EFI_STATUS | SerialIoI2cBlockWriteRead (IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN SERIALIO_I2C_BLOCK_COMMAND *I2cCommandBlock, IN UINT32 BlockSize, IN UINTN Frequency, IN UINT64 MaxTransactionTimeBudget, IN BOOLEAN DisableI2cAfterTransaction, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL)
Executes a block of I2C read/write and wait commands. More...

Detailed Description

Basic I2C Librarary that allows I2C communication throguh Read/Write and Command Block operations.

Copyright
INTEL CONFIDENTIAL Copyright 2020 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoI2cLib.h.

Function Documentation

◆ SerialIoI2cBlockWriteRead()

EFI_STATUS SerialIoI2cBlockWriteRead | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *I2cNumber | OPTIONAL,
 |  | IN UINT32 | SlaveAddress,
 |  | IN SERIALIO_I2C_BLOCK_COMMAND * | I2cCommandBlock,
 |  | IN UINT32 | BlockSize,
 |  | IN UINTN | Frequency,
 |  | IN UINT64 | MaxTransactionTimeBudget,
 |  | IN BOOLEAN | DisableI2cAfterTransaction,
 |  | IN SERIAL_IO_I2C_TIMING *TimingConfig | OPTIONAL
 | ) |  |

Executes a block of I2C read/write and wait commands.

This is intended to enable or configure devices that require multiple data transactions through a I2C bus. The command structure consists of entries with a command id, input/output data pointer and data count.

The following is an example of a command block: SERIALIO_I2C_BLOCK_COMMAND SampleCommandBlock[] = { { I2cBlockCommandWrite, &gWriteDataBuffer[0], sizeof (gWriteDataBuffer)}, { I2cBlockCommandRead, &gReadDataBuffer[0], 1000}, { I2cBlockCommandWait, NULL, 1000}, { I2cBlockCommandWrite, &gWriteDataBuffer[100], 100} };

Status = SerialIoI2cBlockWriteRead ( PciCfgBase, &I2cNumber, 0x10, SampleCommandBlock, sizeof(SampleCommandBlock)/sizeof(SERIALIO_I2C_BLOCK_COMMAND), Frequency, WAIT_1_SECOND, TRUE, &TimingConfig );

Parameters
[in] | PciCfgBase | Pci Config Base Address of specified I2C controller @Note: If I2C Number is provided this parameter is ignored and can be left as 0
[in] | I2cNumber | Optional: The serial controller to be used
[in] | SlaveAddress | The address for the device
[in] | I2cCommandBlock | Pointer to SERIALIO_I2C_BLOCK_COMMAND structure with all commands and data
[in] | NumofBlocks | Total amount of the command block entries - sizeof(SampleCommandBlock)/sizeof(SERIALIO_I2C_BLOCK_COMMAND)
[in] | Frequency | Bus clock frequency (in kHz)
[in] | MaxTransactionTimeBudget | Maximum Time budget for a single transaction
[in] | DisableI2cAfterTransaction | If TRUE, I2c is disabled after transaction is finished.
[in] | TimingConfig | Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
Return values
EFI_INVALID_PARAMETER | Signals that a command or data count was invalid
EFI_BUFFER_TOO_SMALL | The last command could not be executed since the buffer ended before reading all parameters
EFI_SUCCESS | The command were executed without incident

◆ SerialIoI2cRead()

EFI_STATUS SerialIoI2cRead | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *I2cNumber | OPTIONAL,
 |  | IN UINT32 | SlaveAddress,
 |  | IN UINT32 | ReadLength,
 |  | IN UINT8 * | ReadBuffer,
 |  | IN UINT64 | TimeBudget,
 |  | IN UINTN | Frequency,
 |  | IN SERIAL_IO_I2C_TIMING *TimingConfig | OPTIONAL,
 |  | IN BOOLEAN | Restart
 | ) |  |

Execute an I2C read command.

Addressing mode will defined based upon SlaveAddress and mask: SlaveAdress & 0x80000000 - if true will result in 10bit addressing Refer to: I2C_ADDRESSING_10_BIT

Parameters
[in] | PciCfgBase | Pci Config Base Address of specified I2C controller @Note: If I2C Number is provided this parameter is ignored and can be left as 0
[in] | I2cNumber | Optional: I2C controller applicable on bus 0 only
[in] | SlaveAddress | -Address of the end point device
[in] | ReadLength | Read length of the current transaction
[in] | ReadBuffer | Pointer to data in read buffer
[in] | TimeBudget | Time allotted to verify if I2C is enabled
[in] | Frequency | Bus clock frequency (in kHz)
[in] | TimingConfig | Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
[in] | Restart | Indication if restart is needed, if TRUE will Initialize I2C controller. @Note: Restart is required in first transaction.
Return values
EFI_INVALID_PARAMETER | Invalid length / buffer parameters were passed into this function
EFI_TIMEOUT | Timeout occurred in I2C disable/enable or wrong ENST value
EFI_DEVICE_ERROR | The verification failed
EFI_SUCCESS | Read was successful

◆ SerialIoI2cWrite()

EFI_STATUS SerialIoI2cWrite | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *I2cNumber | OPTIONAL,
 |  | IN UINT32 | SlaveAddress,
 |  | IN UINT32 | WriteLength,
 |  | IN UINT8 * | WriteBuffer,
 |  | IN UINT64 | TimeBudget,
 |  | IN UINTN | Frequency,
 |  | IN SERIAL_IO_I2C_TIMING *TimingConfig | OPTIONAL,
 |  | IN BOOLEAN | Stop,
 |  | IN BOOLEAN | Restart
 | ) |  |

Execute an I2C write.

Addressing mode will defined based upon SlaveAddres and mask: SlaveAdress & 0x80000000 - if true will result in 10bit addressing Refer to: I2C_ADDRESSING_10_BIT

Parameters
[in] | PciCfgBase | Pci Config Base Address of specified I2C controller @Note: If I2C Number is provided this parameter is ignored and can be left as 0
[in] | I2cNumber | Optional: I2C controller applicable on bus 0 only
[in] | SlaveAddress | Address of the end point device
[in] | WriteLength | Write length of the current transaction
[in] | WriteBuffer | Pointer to data in write buffer
[in] | TimeBudget | Time allotted to verify if I2C is enabled
[in] | Frequency | Bus clock frequency (in kHz)
[in] | TimingConfig | Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
[in] | Stop | Issues STOP on the last byte
[in] | Restart | Indication if restart is needed, if TRUE will Initialize I2C controller. @Note: Restart is required in first transaction.
Return values
EFI_INVALID_PARAMETER | Invalid length / buffer parameters were passed into this function
EFI_TIMEOUT | Timeout occurred in I2C disable/enable or wrong ENST value
EFI_DEVICE_ERROR | The verification failed
EFI_SUCCESS | Write was successful
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoI2cLib.h
Go to the documentation of this file.
1 /** @file
2 Basic I2C Librarary that allows I2C communication throguh Read/Write and Command Block operations.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SERIAL_IO_I2C_LIB_H_
36 #define _SERIAL_IO_I2C_LIB_H_
37
38 typedef enum {
39 I2cBlockCommandWait = 0,
40 I2cBlockCommandRead = 1,
41 I2cBlockCommandWrite = 2
42 } SERIAL_IO_I2C_COMMAND;
43
44 typedef struct {
45 UINT8 CmdId;
46 UINT8 *CommandPointer;
47 UINT32 CommandData;
48 } SERIALIO_I2C_BLOCK_COMMAND;
49
50 typedef struct {
51 UINT16 SclHcnt;
52 UINT16 SclLcnt;
53 UINT16 SdaRxHold;
54 UINT16 SdaTxHold;
55 } SERIAL_IO_I2C_TIMING;
56
57 /**
58 Execute an I2C write
59
60 Addressing mode will defined based upon SlaveAddres and mask:
61 SlaveAdress & 0x80000000 - if true will result in 10bit addressing
62 Refer to: I2C_ADDRESSING_10_BIT
63
64 @param[in] PciCfgBase Pci Config Base Address of specified I2C controller
65 @Note: If I2C Number is provided this parameter is ignored and can be left as 0
66 @param[in] I2cNumber Optional: I2C controller applicable on bus 0 only
67 @param[in] SlaveAddress Address of the end point device
68 @param[in] WriteLength Write length of the current transaction
69 @param[in] WriteBuffer Pointer to data in write buffer
70 @param[in] TimeBudget Time allotted to verify if I2C is enabled
71 @param[in] Frequency Bus clock frequency (in kHz)
72 @param[in] TimingConfig Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
73 @param[in] Stop Issues STOP on the last byte
74 @param[in] Restart Indication if restart is needed, if TRUE will Initialize I2C controller.
75 @Note: Restart is required in first transaction.
76
77 @retval EFI_INVALID_PARAMETER Invalid length / buffer parameters were passed into this function
78 @retval EFI_TIMEOUT Timeout occurred in I2C disable/enable or wrong ENST value
79 @retval EFI_DEVICE_ERROR The verification failed
80 @retval EFI_SUCCESS Write was successful
81 **/
82 EFI_STATUS
83 SerialIoI2cWrite (
84 IN UINTN PciCfgBase,
85 IN UINT8 *I2cNumber OPTIONAL,
86 IN UINT32 SlaveAddress,
87 IN UINT32 WriteLength,
88 IN UINT8 *WriteBuffer,
89 IN UINT64 TimeBudget,
90 IN UINTN Frequency,
91 IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL,
92 IN BOOLEAN Stop,
93 IN BOOLEAN Restart
94 );
95
96 /**
97 Execute an I2C read command
98
99 Addressing mode will defined based upon SlaveAddress and mask:
100 SlaveAdress & 0x80000000 - if true will result in 10bit addressing
101 Refer to: I2C_ADDRESSING_10_BIT
102
103 @param[in] PciCfgBase Pci Config Base Address of specified I2C controller
104 @Note: If I2C Number is provided this parameter is ignored and can be left as 0
105 @param[in] I2cNumber Optional: I2C controller applicable on bus 0 only
106 @param[in] SlaveAddress -Address of the end point device
107 @param[in] ReadLength Read length of the current transaction
108 @param[in] ReadBuffer Pointer to data in read buffer
109 @param[in] TimeBudget Time allotted to verify if I2C is enabled
110 @param[in] Frequency Bus clock frequency (in kHz)
111 @param[in] TimingConfig Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
112 @param[in] Restart Indication if restart is needed, if TRUE will Initialize I2C controller.
113 @Note: Restart is required in first transaction.
114
115 @retval EFI_INVALID_PARAMETER Invalid length / buffer parameters were passed into this function
116 @retval EFI_TIMEOUT Timeout occurred in I2C disable/enable or wrong ENST value
117 @retval EFI_DEVICE_ERROR The verification failed
118 @retval EFI_SUCCESS Read was successful
119 **/
120 EFI_STATUS
121 SerialIoI2cRead (
122 IN UINTN PciCfgBase,
123 IN UINT8 *I2cNumber OPTIONAL,
124 IN UINT32 SlaveAddress,
125 IN UINT32 ReadLength,
126 IN UINT8 *ReadBuffer,
127 IN UINT64 TimeBudget,
128 IN UINTN Frequency,
129 IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL,
130 IN BOOLEAN Restart
131 );
132
133 /**
134 Executes a block of I2C read/write and wait commands. This is intended to enable or configure devices that require multiple data transactions through a I2C bus.
135 The command structure consists of entries with a command id, input/output data pointer and data count.
136
137 The following is an example of a command block:
138 SERIALIO_I2C_BLOCK_COMMAND SampleCommandBlock[] = {
139 { I2cBlockCommandWrite, &gWriteDataBuffer[0], sizeof (gWriteDataBuffer)},
140 { I2cBlockCommandRead, &gReadDataBuffer[0], 1000},
141 { I2cBlockCommandWait, NULL, 1000},
142 { I2cBlockCommandWrite, &gWriteDataBuffer[100], 100}
143 };
144
145 Status = SerialIoI2cBlockWriteRead (
146 PciCfgBase,
147 &I2cNumber,
148 0x10,
149 SampleCommandBlock,
150 sizeof(SampleCommandBlock)/sizeof(SERIALIO_I2C_BLOCK_COMMAND),
151 Frequency,
152 WAIT_1_SECOND,
153 TRUE,
154 &TimingConfig
155 );
156
157 @param[in] PciCfgBase Pci Config Base Address of specified I2C controller
158 @Note: If I2C Number is provided this parameter is ignored and can be left as 0
159 @param[in] I2cNumber Optional: The serial controller to be used
160 @param[in] SlaveAddress The address for the device
161 @param[in] I2cCommandBlock Pointer to SERIALIO_I2C_BLOCK_COMMAND structure with all commands and data
162 @param[in] NumofBlocks Total amount of the command block entries - sizeof(SampleCommandBlock)/sizeof(SERIALIO_I2C_BLOCK_COMMAND)
163 @param[in] Frequency Bus clock frequency (in kHz)
164 @param[in] MaxTransactionTimeBudget Maximum Time budget for a single transaction
165 @param[in] DisableI2cAfterTransaction If TRUE, I2c is disabled after transaction is finished.
166 @param[in] TimingConfig Optional: Pointer to struct passed down to override SDA Hold and SCL LCNT/HCNT settings
167
168 @retval EFI_INVALID_PARAMETER Signals that a command or data count was invalid
169 @retval EFI_BUFFER_TOO_SMALL The last command could not be executed since the buffer ended before reading all parameters
170 @retval EFI_SUCCESS The command were executed without incident
171 **/
172 EFI_STATUS
173 SerialIoI2cBlockWriteRead (
174 IN UINTN PciCfgBase,
175 IN UINT8 *I2cNumber OPTIONAL,
176 IN UINT32 SlaveAddress,
177 IN SERIALIO_I2C_BLOCK_COMMAND *I2cCommandBlock,
178 IN UINT32 BlockSize,
179 IN UINTN Frequency,
180 IN UINT64 MaxTransactionTimeBudget,
181 IN BOOLEAN DisableI2cAfterTransaction,
182 IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL
183 );
184
185 #endif //_SERIAL_IO_I2C_LIB_H_
SerialIoI2cBlockWriteRead
EFI_STATUS SerialIoI2cBlockWriteRead(IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN SERIALIO_I2C_BLOCK_COMMAND *I2cCommandBlock, IN UINT32 BlockSize, IN UINTN Frequency, IN UINT64 MaxTransactionTimeBudget, IN BOOLEAN DisableI2cAfterTransaction, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL)
Executes a block of I2C read/write and wait commands.
SerialIoI2cRead
EFI_STATUS SerialIoI2cRead(IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN UINT32 ReadLength, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL, IN BOOLEAN Restart)
Execute an I2C read command.
SerialIoI2cWrite
EFI_STATUS SerialIoI2cWrite(IN UINTN PciCfgBase, IN UINT8 *I2cNumber OPTIONAL, IN UINT32 SlaveAddress, IN UINT32 WriteLength, IN UINT8 *WriteBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN SERIAL_IO_I2C_TIMING *TimingConfig OPTIONAL, IN BOOLEAN Stop, IN BOOLEAN Restart)
Execute an I2C write.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cMasterLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoI2cMasterLib.h File Reference

PEI I2C Initiator module. More...

#include <Ppi/I2cMaster.h>
Include dependency graph for SerialIoI2cMasterLib.h:

Go to the source code of this file.

Detailed Description

PEI I2C Initiator module.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoI2cMasterLib.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cMasterLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoI2cMasterLib.h
Go to the documentation of this file.
1 /** @file
2 PEI I2C Initiator module
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _PEI_I2C_MASTER_LIB_H_
37 #define _PEI_I2C_MASTER_LIB_H_
38
39 #include <Ppi/I2cMaster.h>
40
41 /*
42 Installs I2cMaster PPIs for each I2c controller.
43
44 @param[in] Controller - SerialIo controller number
45
46 */
47 VOID
48 InstallI2cMasterPpi (
49 UINT8 Controller
50 );
51
52 /*
53 Finds I2cMasterPpi instance for a specified controller
54
55 @param[in] Controller - SerialIo controller number
56
57 @retval NULL - couldn't locate I2cMaster Ppi for given controller
58 @retval not-NULL - pointer to I2cMaster Ppi
59 */
60 EFI_PEI_I2C_MASTER_PPI*
61 LocateI2cMasterPpi (
62 UINT8 Controller
63 );
64
65 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoI2cRegs.h File Reference

Register names for Serial IO I2C Controllers. More...

Go to the source code of this file.

Detailed Description

Register names for Serial IO I2C Controllers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoI2cRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoI2cRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoI2cRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Serial IO I2C Controllers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2019 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64
65 #ifndef _SERIAL_IO_I2C_REGS_H_
66 #define _SERIAL_IO_I2C_REGS_H_
67
68 //
69 // I2C Controller
70 // Registers accessed through BAR0 + offset
71 //
72 #define R_I2C_MEM_CON 0x00 // I2c Control
73 #define B_I2C_MEM_MASTER_MODE BIT0
74 #define B_I2C_MEM_RESTART_EN BIT5
75 #define B_I2C_MEM_SLAVE_DISABLE BIT6
76 #define V_I2C_MEM_SPEED_STANDARD 0x02
77 #define V_I2C_MEM_SPEED_FAST 0x04
78 #define V_I2C_MEM_SPEED_HIGH 0x06
79
80 #define R_I2C_MEM_TAR 0x04 // I2c Target Address
81 #define B_I2C_MEM_TAR_10BITADDR_MASTER BIT12
82
83 #define R_I2C_MEM_DATA_CMD 0x10 // I2c Rx/Tx Data Buffer and Command
84 #define B_I2C_MEM_CMD_READ BIT8 // 1 = read, 0 = write
85 #define B_I2C_MEM_CMD_STOP BIT9 // 1 = STOP
86 #define B_I2C_MEM_CMD_RESTART BIT10 // 1 = I2C_RESTART_EN
87 #define V_I2C_MEM_WRITE_CMD_MASK 0xFF
88
89 #define R_I2C_MEM_SS_SCL_HCNT 0x14 // Standard Speed I2c Clock SCL High Count
90 #define R_I2C_MEM_SS_SCL_LCNT 0x18 // Standard Speed I2c Clock SCL Low Count
91 #define R_I2C_MEM_FS_SCL_HCNT 0x1C // Full Speed I2c Clock SCL High Count
92 #define R_I2C_MEM_FS_SCL_LCNT 0x20 // Full Speed I2c Clock SCL Low Count
93 #define R_I2C_MEM_HS_SCL_HCNT 0x24 // High Speed I2c Clock SCL High Count
94 #define R_I2C_MEM_HS_SCL_LCNT 0x28 // High Speed I2c Clock SCL Low Count
95 #define R_I2C_MEM_INTR_STAT 0x2C // I2c Inetrrupt Status
96 #define R_I2C_MEM_INTR_MASK 0x30 // I2c Interrupt Mask
97 #define B_I2C_MEM_INTR_GEN_CALL BIT11 // General call received
98 #define B_I2C_MEM_INTR_START_DET BIT10
99 #define B_I2C_MEM_INTR_STOP_DET BIT9
100 #define B_I2C_MEM_INTR_ACTIVITY BIT8
101 #define B_I2C_MEM_INTR_TX_ABRT BIT6 // Set on NACK
102 #define B_I2C_MEM_INTR_TX_EMPTY BIT4
103 #define B_I2C_MEM_INTR_TX_OVER BIT3
104 #define B_I2C_MEM_INTR_RX_FULL BIT2 // Data bytes in RX FIFO over threshold
105 #define B_I2C_MEM_INTR_RX_OVER BIT1
106 #define B_I2C_MEM_INTR_RX_UNDER BIT0
107 #define R_I2C_MEM_RAW_INTR_STAT 0x34 // I2c Raw Interrupt Status
108 #define R_I2C_MEM_RX_TL 0x38 // I2c Receive FIFO Threshold
109 #define R_I2C_MEM_TX_TL 0x3C // I2c Transmit FIFO Threshold
110 #define R_I2C_MEM_CLR_INTR 0x40 // Clear Combined and Individual Interrupts
111 #define R_I2C_MEM_CLR_RX_UNDER 0x44 // Clear RX_UNDER Interrupt
112 #define R_I2C_MEM_CLR_RX_OVER 0x48 // Clear RX_OVERinterrupt
113 #define R_I2C_MEM_CLR_TX_OVER 0x4C // Clear TX_OVER interrupt
114 #define R_I2C_MEM_CLR_RD_REQ 0x50 // Clear RD_REQ interrupt
115 #define R_I2C_MEM_CLR_TX_ABRT 0x54 // Clear TX_ABRT interrupt
116 #define R_I2C_MEM_CLR_RX_DONE 0x58 // Clear RX_DONE interrupt
117 #define R_I2C_MEM_CLR_ACTIVITY 0x5C // Clear ACTIVITY interrupt
118 #define R_I2C_MEM_CLR_STOP_DET 0x60 // Clear STOP_DET interrupt
119 #define R_I2C_MEM_CLR_START_DET 0x64 // Clear START_DET interrupt
120 #define R_I2C_MEM_CLR_GEN_CALL 0x68 // Clear GEN_CALL interrupt
121 #define R_I2C_MEM_ENABLE 0x6C // I2c Enable
122
123 #define R_I2C_MEM_STATUS 0x70 // I2c Status
124 #define B_I2C_MEM_STATUS_RFF BIT4 // RX FIFO is completely full
125 #define B_I2C_MEM_STATUS_RFNE BIT3 // RX FIFO is not empty
126 #define B_I2C_MEM_STATUS_TFE BIT2 // TX FIFO is completely empty
127 #define B_I2C_MEM_STATUS_TFNF BIT1 // TX FIFO is not full
128 #define B_I2C_MEM_STATUS_ACTIVITY BIT0 // Controller Activity Status.
129
130 #define R_I2C_MEM_TXFLR 0x74 // Transmit FIFO Level Register
131 #define R_I2C_MEM_RXFLR 0x78 // Receive FIFO Level Register
132 #define R_SERIAL_IO_I2C_MEM_SDA_HOLD 0x7C
133 #define V_SERIAL_IO_I2C_MEM_SDA_HOLD_VALUE 0x002C002C
134 #define R_I2C_MEM_TX_ABRT_SOURCE 0x80 // I2c Transmit Abort Status Register
135 #define B_I2C_MEM_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address
136
137 #define R_I2C_MEM_SDA_SETUP 0x94 // I2c SDA Setup Register
138 #define R_I2C_MEM_ACK_GENERAL_CALL 0x98 // I2c ACK General Call Register
139 #define R_I2C_MEM_ENABLE_STATUS 0x9C // I2c Enable Status Register
140 #define B_I2C_MEM_EN BIT0 // I2c enable status
141
142 #define R_I2C_MEM_CLK_GATE 0xC0
143 #define R_I2C_MEM_COMP_PARAM 0xF4 // Component Parameter Register
144 #define R_I2C_MEM_COMP_VERSION 0xF8 // Component Version ID
145 #define R_I2C_MEM_COMP_TYPE 0xFC // Component Type
146
147 #define R_I2C_MEM_GENERAL 0x208 // I2C Convergence Layer General
148 #define B_I2C_MEM_GENERAL_SDA_LINE_STATE BIT26 // I2C SDA Line State: 0 - Low, 1 - High
149 #define B_I2C_MEM_GENERAL_SCL_LINE_STATE BIT24 // I2C SCL Line State: 0 - Low, 1 - High
150
151 #endif // _SERIAL_IO_I2C_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoRegs.h File Reference

Register names for Serial IO Controllers. More...

Go to the source code of this file.

Detailed Description

Register names for Serial IO Controllers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Serial IO Controllers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2019 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _SERIAL_IO_REGS_H_
65 #define _SERIAL_IO_REGS_H_
66
67 //
68 // Serial IO Controllers PCI Configuration Registers
69 // registers accessed using PciD21FxRegBase + offset
70 //
71 #define R_SERIAL_IO_CFG_BAR0_LOW 0x10
72 #define R_SERIAL_IO_CFG_BAR0_HIGH 0x14
73 #define R_SERIAL_IO_CFG_BAR1_LOW 0x18
74 #define R_SERIAL_IO_CFG_BAR1_HIGH 0x1C
75
76 #define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84
77 #define B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST (BIT1| BIT0)
78
79 #define R_SERIAL_IO_CFG_D0I3MAXDEVPG 0xA0
80 #define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PMCRE BIT16
81 #define B_SERIAL_IO_CFG_D0I3MAXDEVPG_I3E BIT17
82 #define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PGE BIT18
83
84 //
85 // Serial IO Controllers MMIO Registers
86 // registers accessed : BAR0 + offset
87 //
88 #define R_SERIAL_IO_MEM_PPR_RESETS 0x204
89 #define B_SERIAL_IO_MEM_PPR_RESETS_FUNC BIT0
90 #define B_SERIAL_IO_MEM_PPR_RESETS_APB BIT1
91 #define B_SERIAL_IO_MEM_PPR_RESETS_IDMA BIT2
92
93 //
94 // Bridge Private Configuration Registers
95 // accessed only through SB messaging. SB access = SerialIo IOSF2OCP Bridge Port ID + offset
96 //
97 #define R_SERIAL_IO_PCR_PMCTL 0x1D0
98 #define V_SERIAL_IO_PCR_PMCTL_PWR_GATING 0x3F
99 //
100 // PCI Config Control
101 //
102 #define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS BIT0
103 #define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_INTR_EN BIT1
104 #define B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS BIT7
105 #define B_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 | BIT8)
106 #define N_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN 8
107 #define V_SERIAL_IO_PCR_PCICFGCTRL_INTA 0x01
108 #define V_SERIAL_IO_PCR_PCICFGCTRL_INTB 0x02
109 #define V_SERIAL_IO_PCR_PCICFGCTRL_INTC 0x03
110 #define V_SERIAL_IO_PCR_PCICFGCTRL_INTD 0x04
111 #define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 0x000FF000
112 #define N_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 12
113 #define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 0x0FF00000
114 #define N_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 20
115 //
116 // General Purpose
117 //
118 #define R_SERIAL_IO_PCR_GPPRVRW2 0x604
119 #define B_SERIAL_IO_PCR_GPPRVRW2_PGCB_FRC_CLK_CP_EN BIT1
120 #define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_EN BIT5
121 #define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN BIT11
122 #define V_SERIAL_IO_PCR_GPPRVRW2_CLK_GATING (B_SERIAL_IO_PCR_GPPRVRW2_PGCB_FRC_CLK_CP_EN | B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_EN | B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN)
123
124 #define R_SERIAL_IO_PCR_GPPRVRW4 0x60C
125 #define B_SERIAL_IO_PCR_GPPRVRW4_I2C6_IO_CONTROL BIT8
126 #define B_SERIAL_IO_PCR_GPPRVRW4_I3C_SLC_CLK_CGC BIT16 // I3C Slice Clock Gate Control [0: Clock Gating Enabled, 1: Force Clock On]
127
128 #endif //_SERIAL_IO_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoSpiLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SerialIoSpiLib.h File Reference

Basic SPI Library that allows SPI communication through Read/Write/WriteRead operations. More...

Go to the source code of this file.

Functions

VOID | SerialIoSpiChipSelectConfig (IN UINT64 SpiBaseAddress, IN UINT8 CsOutput, IN UINT8 CsMode, IN UINT8 CsState, IN UINT8 CsEnableBits, IN UINT8 CsIdlePolarityBits)
Configure Initial Chip Select settings. More...
EFI_STATUS | SerialIoSpiWrite (IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 WriteLength, IN UINT8 *WriteBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI write. More...
EFI_STATUS | SerialIoSpiRead (IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 ReadLength, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI read command. More...
EFI_STATUS | SerialIoSpiWriteRead (IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 TransactionLength, IN UINT8 *WriteBuffer, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI write-read operation. More...

Detailed Description

Basic SPI Library that allows SPI communication through Read/Write/WriteRead operations.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoSpiLib.h.

Function Documentation

◆ SerialIoSpiChipSelectConfig()

VOID SerialIoSpiChipSelectConfig | ( | IN UINT64 | SpiBaseAddress,
 |  | IN UINT8 | CsOutput,
 |  | IN UINT8 | CsMode,
 |  | IN UINT8 | CsState,
 |  | IN UINT8 | CsEnableBits,
 |  | IN UINT8 | CsIdlePolarityBits
 | ) |  |

Configure Initial Chip Select settings.

Parameters
[in] | SpiBaseAddress | - Base Address of SPI Controller
[in] | SpiDeviceConfig | SerialIo SPI Config
[in] | CsOutput | - Default CS used by the SPI HC. 0 = CS0, 1 = CS1, CS2, CS3.
[in] | CsMode | - Sets Chip Select Control mode Hardware or Software. 0 = HW Control, 1 = SW Control
[in] | CsState | - 0 = CS is set to low; 1 = CS is set to high
[in] | CsEnableBits | Bit based Cs Enable setting (BIT0 -> Enable CS0, BIT1 -> Enable CS1 etc.)
[in] | CsIdlePolarityBits | Bit based Cs Polarity - Sets Inactive/Idle polarity of each CS

◆ SerialIoSpiRead()

EFI_STATUS SerialIoSpiRead | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *SpiNumber | OPTIONAL,
 |  | IN UINT32 | ReadLength,
 |  | IN UINT8 * | ReadBuffer,
 |  | IN UINT64 | TimeBudget,
 |  | IN UINTN | Frequency,
 |  | IN UINT8 | ClockIdlePolarity,
 |  | IN UINT8 | ClockPhase,
 |  | IN UINT8 | CsOutputSelect,
 |  | IN UINT8 | CsActivePolarity,
 |  | IN BOOLEAN | AssertCs
 | ) |  |

Execute an SPI read command.

  • Write data is always 0x0
Parameters
[in] | PciCfgBase | Pci Config Base Address of specified SPI controller @Note: If SPI Number is provided this parameter is ignored and can be left as 0
[in] | SpiNumber | Optional: SPI controller applicable on bus 0 only
[in] | ReadLength | Read length of the current transaction
[in] | ReadBuffer | Pointer to data in read buffer
[in] | TimeBudget | Time allotted to verify if SPI is enabled
[in] | Frequency | Bus clock frequency (in Hz)
[in] | ClockIdlePolarity | Clock Idle Polarity 0 = Low, 1 = High
[in] | ClockPhase | 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
[in] | CsOutputSelect | Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
[in] | CsActivePolarity | Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
[in] | AssertCs | FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO) TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
Return values
EFI_INVALID_PARAMETER | Invalid length parameters were passed into this function
EFI_TIMEOUT | Timeout occurred in SPI disable/enable or transaction timeout
EFI_DEVICE_ERROR | The verification failed
EFI_SUCCESS | Read was successful
EFI_BAD_BUFFER_SIZE | Read buffer is NULL

◆ SerialIoSpiWrite()

EFI_STATUS SerialIoSpiWrite | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *SpiNumber | OPTIONAL,
 |  | IN UINT32 | WriteLength,
 |  | IN UINT8 * | WriteBuffer,
 |  | IN UINT64 | TimeBudget,
 |  | IN UINTN | Frequency,
 |  | IN UINT8 | ClockIdlePolarity,
 |  | IN UINT8 | ClockPhase,
 |  | IN UINT8 | CsOutputSelect,
 |  | IN UINT8 | CsActivePolarity,
 |  | IN BOOLEAN | AssertCs
 | ) |  |

Execute an SPI write.

  • Read data is ingnored
Parameters
[in] | PciCfgBase | Pci Config Base Address of specified SPI controller @Note: If SPI Number is provided this parameter is ignored and can be left as 0
[in] | SpiNumber | Optional: SPI controller applicable on bus 0 only
[in] | WriteLength | Write length of the current transaction
[in] | WriteBuffer | Pointer to data in write buffer
[in] | TimeBudget | Time allotted to verify if SPI is enabled
[in] | Frequency | Bus clock frequency (in Hz)
[in] | ClockIdlePolarity | Clock Idle Polarity 0 = Low, 1 = High
[in] | ClockPhase | 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
[in] | CsOutputSelect | Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
[in] | CsActivePolarity | Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
[in] | AssertCs | FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO) TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
Return values
EFI_INVALID_PARAMETER | Invalid length parameters were passed into this function
EFI_TIMEOUT | Timeout occurred in SPI disable/enable or transaction timeout
EFI_DEVICE_ERROR | The verification failed
EFI_SUCCESS | Write was successful
EFI_BAD_BUFFER_SIZE | Write buffer is NULL

◆ SerialIoSpiWriteRead()

EFI_STATUS SerialIoSpiWriteRead | ( | IN UINTN | PciCfgBase,
 |  | IN UINT8 *SpiNumber | OPTIONAL,
 |  | IN UINT32 | TransactionLength,
 |  | IN UINT8 * | WriteBuffer,
 |  | IN UINT8 * | ReadBuffer,
 |  | IN UINT64 | TimeBudget,
 |  | IN UINTN | Frequency,
 |  | IN UINT8 | ClockIdlePolarity,
 |  | IN UINT8 | ClockPhase,
 |  | IN UINT8 | CsOutputSelect,
 |  | IN UINT8 | CsActivePolarity,
 |  | IN BOOLEAN | AssertCs
 | ) |  |

Execute an SPI write-read operation.

Parameters
[in] | PciCfgBase | Pci Config Base Address of specified SPI controller @Note: If SPI Number is provided this parameter is ignored and can be left as 0
[in] | SpiNumber | Optional: SPI controller applicable on bus 0 only
[in] | TransactionLength | Read length of the current transaction
[in] | WriteBuffer | Pointer to data in write buffer
[in] | ReadBuffer | Pointer to data in read buffer
[in] | TimeBudget | Time allotted to verify if SPI is enabled
[in] | Frequency | Bus clock frequency (in Hz)
[in] | ClockIdlePolarity | Clock Idle Polarity 0 = Low, 1 = High
[in] | ClockPhase | 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
[in] | CsOutputSelect | Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
[in] | CsActivePolarity | Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
[in] | AssertCs | FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO) TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
Return values
EFI_INVALID_PARAMETER | Invalid length parameters were passed into this function
EFI_TIMEOUT | Timeout occurred in SPI disable/enable or transaction timeout
EFI_DEVICE_ERROR | The verification failed
EFI_SUCCESS | WriteRead was successful
EFI_BAD_BUFFER_SIZE | One of the buffers is NULL
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoSpiLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoSpiLib.h
Go to the documentation of this file.
1 /** @file
2 Basic SPI Library that allows SPI communication through Read/Write/WriteRead operations.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34
35 #ifndef _SERIAL_IO_SPI_LIB_H_
36 #define _SERIAL_IO_SPI_LIB_H_
37
38 /**
39 Configure Initial Chip Select settings
40
41 @param[in] SpiBaseAddress - Base Address of SPI Controller
42 @param[in] SpiDeviceConfig SerialIo SPI Config
43 @param[in] CsOutput - Default CS used by the SPI HC. 0 = CS0, 1 = CS1, CS2, CS3.
44 @param[in] CsMode - Sets Chip Select Control mode Hardware or Software. 0 = HW Control, 1 = SW Control
45 @param[in] CsState - 0 = CS is set to low; 1 = CS is set to high
46 @param[in] CsEnableBits Bit based Cs Enable setting (BIT0 -> Enable CS0, BIT1 -> Enable CS1 etc.)
47 @param[in] CsIdlePolarityBits Bit based Cs Polarity - Sets Inactive/Idle polarity of each CS
48 **/
49 VOID
50 SerialIoSpiChipSelectConfig (
51 IN UINT64 SpiBaseAddress,
52 IN UINT8 CsOutput,
53 IN UINT8 CsMode,
54 IN UINT8 CsState,
55 IN UINT8 CsEnableBits,
56 IN UINT8 CsIdlePolarityBits
57 );
58
59 /**
60 Execute an SPI write
61 - Read data is ingnored
62
63 @param[in] PciCfgBase Pci Config Base Address of specified SPI controller
64 @Note: If SPI Number is provided this parameter is ignored and can be left as 0
65 @param[in] SpiNumber Optional: SPI controller applicable on bus 0 only
66 @param[in] WriteLength Write length of the current transaction
67 @param[in] WriteBuffer Pointer to data in write buffer
68 @param[in] TimeBudget Time allotted to verify if SPI is enabled
69 @param[in] Frequency Bus clock frequency (in Hz)
70 @param[in] ClockIdlePolarity Clock Idle Polarity 0 = Low, 1 = High
71 @param[in] ClockPhase 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame
72 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
73 @param[in] CsOutputSelect Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
74 @param[in] CsActivePolarity Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
75 @param[in] AssertCs FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO)
76 TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
77
78 @retval EFI_INVALID_PARAMETER Invalid length parameters were passed into this function
79 @retval EFI_TIMEOUT Timeout occurred in SPI disable/enable or transaction timeout
80 @retval EFI_DEVICE_ERROR The verification failed
81 @retval EFI_SUCCESS Write was successful
82 @retval EFI_BAD_BUFFER_SIZE Write buffer is NULL
83 **/
84 EFI_STATUS
85 SerialIoSpiWrite (
86 IN UINTN PciCfgBase,
87 IN UINT8 *SpiNumber OPTIONAL,
88 IN UINT32 WriteLength,
89 IN UINT8 *WriteBuffer,
90 IN UINT64 TimeBudget,
91 IN UINTN Frequency,
92 IN UINT8 ClockIdlePolarity,
93 IN UINT8 ClockPhase,
94 IN UINT8 CsOutputSelect,
95 IN UINT8 CsActivePolarity,
96 IN BOOLEAN AssertCs
97 );
98
99 /**
100 Execute an SPI read command
101 - Write data is always 0x0
102
103 @param[in] PciCfgBase Pci Config Base Address of specified SPI controller
104 @Note: If SPI Number is provided this parameter is ignored and can be left as 0
105 @param[in] SpiNumber Optional: SPI controller applicable on bus 0 only
106 @param[in] ReadLength Read length of the current transaction
107 @param[in] ReadBuffer Pointer to data in read buffer
108 @param[in] TimeBudget Time allotted to verify if SPI is enabled
109 @param[in] Frequency Bus clock frequency (in Hz)
110 @param[in] ClockIdlePolarity Clock Idle Polarity 0 = Low, 1 = High
111 @param[in] ClockPhase 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame
112 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
113 @param[in] CsOutputSelect Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
114 @param[in] CsActivePolarity Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
115 @param[in] AssertCs FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO)
116 TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
117
118 @retval EFI_INVALID_PARAMETER Invalid length parameters were passed into this function
119 @retval EFI_TIMEOUT Timeout occurred in SPI disable/enable or transaction timeout
120 @retval EFI_DEVICE_ERROR The verification failed
121 @retval EFI_SUCCESS Read was successful
122 @retval EFI_BAD_BUFFER_SIZE Read buffer is NULL
123 **/
124 EFI_STATUS
125 SerialIoSpiRead (
126 IN UINTN PciCfgBase,
127 IN UINT8 *SpiNumber OPTIONAL,
128 IN UINT32 ReadLength,
129 IN UINT8 *ReadBuffer,
130 IN UINT64 TimeBudget,
131 IN UINTN Frequency,
132 IN UINT8 ClockIdlePolarity,
133 IN UINT8 ClockPhase,
134 IN UINT8 CsOutputSelect,
135 IN UINT8 CsActivePolarity,
136 IN BOOLEAN AssertCs
137 );
138
139 /**
140 Execute an SPI write-read operation
141
142 @param[in] PciCfgBase Pci Config Base Address of specified SPI controller
143 @Note: If SPI Number is provided this parameter is ignored and can be left as 0
144 @param[in] SpiNumber Optional: SPI controller applicable on bus 0 only
145 @param[in] TransactionLength Read length of the current transaction
146 @param[in] WriteBuffer Pointer to data in write buffer
147 @param[in] ReadBuffer Pointer to data in read buffer
148 @param[in] TimeBudget Time allotted to verify if SPI is enabled
149 @param[in] Frequency Bus clock frequency (in Hz)
150 @param[in] ClockIdlePolarity Clock Idle Polarity 0 = Low, 1 = High
151 @param[in] ClockPhase 0 - Clock is inactive one cycle at the start of a frame and one cycle at the end of a frame
152 1 - Clock is inactive for one halfcycle at the start of a frame and one cycle at the end of a frame
153 @param[in] CsOutputSelect Select which SPI CS Signal is to be driven by the SPI Frame (0 = CS0; 1 = CS1 etc.)
154 @param[in] CsActivePolarity Selects SPI ChipSelect signal polarity, 0 = Low, 1 = High
155 @param[in] AssertCs FALSE - CS will remain in De-Asserted case. Used for scenario when external CS is used (ex GPIO)
156 TRUE - CS either CS0/CS1 will be asserted once SPI transaction starts
157
158 @retval EFI_INVALID_PARAMETER Invalid length parameters were passed into this function
159 @retval EFI_TIMEOUT Timeout occurred in SPI disable/enable or transaction timeout
160 @retval EFI_DEVICE_ERROR The verification failed
161 @retval EFI_SUCCESS WriteRead was successful
162 @retval EFI_BAD_BUFFER_SIZE One of the buffers is NULL
163 **/
164 EFI_STATUS
165 SerialIoSpiWriteRead (
166 IN UINTN PciCfgBase,
167 IN UINT8 *SpiNumber OPTIONAL,
168 IN UINT32 TransactionLength,
169 IN UINT8 *WriteBuffer,
170 IN UINT8 *ReadBuffer,
171 IN UINT64 TimeBudget,
172 IN UINTN Frequency,
173 IN UINT8 ClockIdlePolarity,
174 IN UINT8 ClockPhase,
175 IN UINT8 CsOutputSelect,
176 IN UINT8 CsActivePolarity,
177 IN BOOLEAN AssertCs
178 );
179
180 #endif //_SERIAL_IO_SPI_LIB_H_
SerialIoSpiWriteRead
EFI_STATUS SerialIoSpiWriteRead(IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 TransactionLength, IN UINT8 *WriteBuffer, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI write-read operation.
SerialIoSpiRead
EFI_STATUS SerialIoSpiRead(IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 ReadLength, IN UINT8 *ReadBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI read command.
SerialIoSpiChipSelectConfig
VOID SerialIoSpiChipSelectConfig(IN UINT64 SpiBaseAddress, IN UINT8 CsOutput, IN UINT8 CsMode, IN UINT8 CsState, IN UINT8 CsEnableBits, IN UINT8 CsIdlePolarityBits)
Configure Initial Chip Select settings.
SerialIoSpiWrite
EFI_STATUS SerialIoSpiWrite(IN UINTN PciCfgBase, IN UINT8 *SpiNumber OPTIONAL, IN UINT32 WriteLength, IN UINT8 *WriteBuffer, IN UINT64 TimeBudget, IN UINTN Frequency, IN UINT8 ClockIdlePolarity, IN UINT8 ClockPhase, IN UINT8 CsOutputSelect, IN UINT8 CsActivePolarity, IN BOOLEAN AssertCs)
Execute an SPI write.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoSpiRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoSpiRegs.h File Reference

Register names for Serial IO SPI Controllers. More...

Go to the source code of this file.

Detailed Description

Register names for Serial IO SPI Controllers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoSpiRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoSpiRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoSpiRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Serial IO SPI Controllers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64
65 #ifndef _SERIAL_IO_SPI_REGS_H_
66 #define _SERIAL_IO_SPI_REGS_H_
67
68 //
69 // MMIO
70 //
71 #define R_SERIAL_IO_MEM_SPI_SSCR0 0x00
72 #define V_SERIAL_IO_MEM_SPI_SSCR0_DSS_8 0x07
73 //#define V_SERIAL_IO_MEM_SPI_SSCR0_DSS_16 0x0F
74 #define R_SERIAL_IO_MEM_SPI_SSCR1 0x04
75 #define R_SERIAL_IO_MEM_SPI_SSSR 0x08
76 #define R_SERIAL_IO_MEM_SPI_SSITR 0x0C
77 #define R_SERIAL_IO_MEM_SPI_SSDR 0x10
78 #define R_SERIAL_IO_MEM_SPI_SIRF 0x48
79
80 //
81 // MMIO Convergence Layer
82 //
83 #define R_SERIAL_IO_MEM_SPI_PPR_CLK 0x200
84 #define R_SERIAL_IO_MEM_SPI_CS_CONTROL 0x224
85
86 #endif // _SERIAL_IO_SPI_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartDebugPropertyPcdLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SerialIoUartDebugPropertyPcdLib.h File Reference

SerialIo Uart Debug Property Pcd Library. More...

#include <SerialIoDevices.h>
Include dependency graph for SerialIoUartDebugPropertyPcdLib.h:

Go to the source code of this file.

Functions

VOID | SerialIoUartDebugPcdGetAttributes (IN OUT SERIAL_IO_UART_ATTRIBUTES *Attributes)
Returns UART attributes. More...
UINT8 | SerialIoUartDebugPcdGetControllerNumber (VOID)
Returns Serial Io UART Controller Number used in Debug mode. More...
UINT8 | SerialIoUartDebugPcdGetDebugEnable (VOID)
Returns Serial Io UART Debug Enable. More...
UINT32 | SerialIoUartDebugPcdGetPciDefaultMmioBase (VOID)
Returns Serial Io UART MMIO Base Address. More...
VOID | SerialIoUartDebugPcdGetDeviceConfig (IN OUT SERIAL_IO_UART_CONFIG *Uart, IN OUT UINT8 *UartNumber)
Returns Serial Io UART PinMux Rx GPIO. More...

Detailed Description

SerialIo Uart Debug Property Pcd Library.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoUartDebugPropertyPcdLib.h.

Function Documentation

◆ SerialIoUartDebugPcdGetAttributes()

VOID SerialIoUartDebugPcdGetAttributes ( IN OUT SERIAL_IO_UART_ATTRIBUTES * Attributes )

Returns UART attributes.

Parameters
[in,out] Attributes UART Attributes

◆ SerialIoUartDebugPcdGetControllerNumber()

UINT8 SerialIoUartDebugPcdGetControllerNumber ( VOID )

Returns Serial Io UART Controller Number used in Debug mode.

Return values
ControllerNumber UART Controller Number

◆ SerialIoUartDebugPcdGetDebugEnable()

UINT8 SerialIoUartDebugPcdGetDebugEnable ( VOID )

Returns Serial Io UART Debug Enable.

Return values
0 | - Disabled
1 | - Enabled
2 | - Enabled without initializng

◆ SerialIoUartDebugPcdGetDeviceConfig()

VOID SerialIoUartDebugPcdGetDeviceConfig | ( | IN OUT SERIAL_IO_UART_CONFIG * | Uart,
 |  | IN OUT UINT8 * | UartNumber
 | ) |  |

Returns Serial Io UART PinMux Rx GPIO.

Parameters
[in,out] | Uart | UART Device Configuration
[in,out] | UartNumber | UART Device Number

◆ SerialIoUartDebugPcdGetPciDefaultMmioBase()

UINT32 SerialIoUartDebugPcdGetPciDefaultMmioBase ( VOID )

Returns Serial Io UART MMIO Base Address.

Return values
MMIO Base Address by default in PCI Mode
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartDebugPropertyPcdLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoUartDebugPropertyPcdLib.h
Go to the documentation of this file.
1 /** @file
2
3 SerialIo Uart Debug Property Pcd Library
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2019 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36
37 #ifndef _SERAIL_IO_DEBUG_PROPERTY_PCD_LIB_H_
38 #define _SERAIL_IO_DEBUG_PROPERTY_PCD_LIB_H_
39
40 #include <SerialIoDevices.h>
41
42 /**
43 Returns UART attributes
44
45 @param[in,out] Attributes UART Attributes
46 **/
47 VOID
48 SerialIoUartDebugPcdGetAttributes (
49 IN OUT SERIAL_IO_UART_ATTRIBUTES *Attributes
50 );
51
52 /**
53 Returns Serial Io UART Controller Number used in Debug mode
54
55 @retval ControllerNumber UART Controller Number
56 **/
57 UINT8
58 SerialIoUartDebugPcdGetControllerNumber (
59 VOID
60 );
61
62 /**
63 Returns Serial Io UART Debug Enable
64
65 @retval 0 - Disabled
66 @retval 1 - Enabled
67 @retval 2 - Enabled without initializng
68 **/
69 UINT8
70 SerialIoUartDebugPcdGetDebugEnable (
71 VOID
72 );
73
74 /**
75 Returns Serial Io UART MMIO Base Address
76
77 @retval MMIO Base Address by default in PCI Mode
78 **/
79 UINT32
80 SerialIoUartDebugPcdGetPciDefaultMmioBase (
81 VOID
82 );
83
84 /**
85 Returns Serial Io UART PinMux Rx GPIO
86
87 @param[in,out] Uart UART Device Configuration
88 @param[in,out] UartNumber UART Device Number
89
90 **/
91 VOID
92 SerialIoUartDebugPcdGetDeviceConfig (
93 IN OUT SERIAL_IO_UART_CONFIG *Uart,
94 IN OUT UINT8 *UartNumber
95 );
96
97 #endif //_SERAIL_IO_DEBUG_PROPERTY_PCD_LIB_H_
SerialIoUartDebugPcdGetAttributes
VOID SerialIoUartDebugPcdGetAttributes(IN OUT SERIAL_IO_UART_ATTRIBUTES *Attributes)
Returns UART attributes.
SerialIoUartDebugPcdGetDeviceConfig
VOID SerialIoUartDebugPcdGetDeviceConfig(IN OUT SERIAL_IO_UART_CONFIG *Uart, IN OUT UINT8 *UartNumber)
Returns Serial Io UART PinMux Rx GPIO.
SERIAL_IO_UART_ATTRIBUTES
UART Settings.
Definition: SerialIoDevices.h:151
SerialIoDevices.h
Serial IO policy.
SerialIoUartDebugPcdGetDebugEnable
UINT8 SerialIoUartDebugPcdGetDebugEnable(VOID)
Returns Serial Io UART Debug Enable.
SERIAL_IO_UART_CONFIG
Serial IO UART Controller Configuration.
Definition: SerialIoDevices.h:174
SerialIoUartDebugPcdGetPciDefaultMmioBase
UINT32 SerialIoUartDebugPcdGetPciDefaultMmioBase(VOID)
Returns Serial Io UART MMIO Base Address.
SerialIoUartDebugPcdGetControllerNumber
UINT8 SerialIoUartDebugPcdGetControllerNumber(VOID)
Returns Serial Io UART Controller Number used in Debug mode.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SerialIoUartLib.h File Reference

Header file for Serial IO UART Lib implementation. More...

#include <Protocol/SerialIo.h>
Include dependency graph for SerialIoUartLib.h:

Go to the source code of this file.

Functions

BOOLEAN | SerialIoUartPolling (IN UINT8 UartNumber)
Polls a serial device to see if there is any data waiting or pending for read. More...
UINTN | SerialIoUartWrite (IN UINT8 UartNumber, IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data to serial device. More...
UINTN | SerialIoUartRead (IN UINT8 UartNumber, OUT UINT8 *Buffer, IN UINTN NumberOfBytes, IN BOOLEAN WaitUntilBufferFull)
Read data from serial device and save the data in buffer. More...
VOID | SerialIoUartSetAttributes (IN UINT8 UartNumber, IN UINT64 BaudRate, IN EFI_PARITY_TYPE Parity, IN UINT8 DataBits, IN EFI_STOP_BITS_TYPE StopBits, IN BOOLEAN AutoFlow)
Sets the baud rate, parity, data bits, flow control and stop bits on a serial device. More...
VOID | SerialIoUartDummyRead (IN UINT8 UartNumber)
Dummy Read required after setting/clearing 16550 8bit mode. More...
VOID | SerialIoUartGetOutOfReset (IN UINT64 MmioBaseAddress)
Gets UART out of reset. More...
BOOLEAN | IsSerialIoUartInPciMode (IN UINT8 UartNumber)
Return whether UART is in PCI mode or not. More...
EFI_STATUS | SerialIoUartSetMmioInPciMode (IN UINT8 UartNumber, IN UINT64 MmioBaseAddress)
Assign MMIO Resource in PCI Mode. More...

Detailed Description

Header file for Serial IO UART Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file SerialIoUartLib.h.

Function Documentation

◆ IsSerialIoUartInPciMode()

BOOLEAN IsSerialIoUartInPciMode ( IN UINT8 UartNumber )

Return whether UART is in PCI mode or not.

Parameters
[in] UartNumber UART Number
Return values
TRUE | - UART is in PCI mode
FALSE | - UART is in Hidden mode or disabled

◆ SerialIoUartDummyRead()

VOID SerialIoUartDummyRead ( IN UINT8 UartNumber )

Dummy Read required after setting/clearing 16550 8bit mode.

Parameters
[in] UartNumber UART Number

◆ SerialIoUartGetOutOfReset()

VOID SerialIoUartGetOutOfReset ( IN UINT64 MmioBaseAddress )

Gets UART out of reset.

Parameters
[in] BaseAddress Base address of UART MMIO space

◆ SerialIoUartPolling()

BOOLEAN SerialIoUartPolling ( IN UINT8 UartNumber )

Polls a serial device to see if there is any data waiting or pending for read.

If there is data pending, then TRUE is returned. If there is no data, then FALSE is returned.

Parameters
[in] UartNumber Selects Serial IO UART device
Return values
TRUE | Data is waiting to read from the serial device.
FALSE | There is no data waiting to read from the serial device.

◆ SerialIoUartRead()

UINTN SerialIoUartRead | ( | IN UINT8 | UartNumber,
 |  | OUT UINT8 * | Buffer,
 |  | IN UINTN | NumberOfBytes,
 |  | IN BOOLEAN | WaitUntilBufferFull
 | ) |  |

Read data from serial device and save the data in buffer.

If the buffer is NULL, then return 0; if NumberOfBytes is 0, then return 0.

Parameters
[in] | UartNumber | Selects Serial IO UART device
[out] | Buffer | Pointer to the buffer that will contain the return data
[in] | NumberOfBytes | Number of input bytes to read
[in] | WaitUntilBufferFull | TRUE - function waits until whole buffer is filled. FALSE - function returns as soon as no new characters are available.
Return values
Actual number of bytes raed to serial device.

◆ SerialIoUartSetAttributes()

VOID SerialIoUartSetAttributes | ( | IN UINT8 | UartNumber,
 |  | IN UINT64 | BaudRate,
 |  | IN EFI_PARITY_TYPE | Parity,
 |  | IN UINT8 | DataBits,
 |  | IN EFI_STOP_BITS_TYPE | StopBits,
 |  | IN BOOLEAN | AutoFlow
 | ) |  |

Sets the baud rate, parity, data bits, flow control and stop bits on a serial device.

Parameters
[in] | UartNumber | Selects Serial IO UART device
[in] | BaudRate | The requested baud rate. A BaudRate value of 0 will use the the device's default interface speed.
[in] | Parity | The type of parity to use on this serial device. A Parity value of DefaultParity will use the device's default parity value.
[in] | DataBits | The number of data bits to use on the serial device. A DataBits value of 0 will use the device's default data bit setting.
[in] | StopBits | The number of stop bits to use on this serial device. A StopBits value of DefaultStopBits will use the device's default number of stop bits.
[in] | AutoFlow | Enable/Disable Auto Flow Control

◆ SerialIoUartSetMmioInPciMode()

EFI_STATUS SerialIoUartSetMmioInPciMode | ( | IN UINT8 | UartNumber,
 |  | IN UINT64 | MmioBaseAddress
 | ) |  |

Assign MMIO Resource in PCI Mode.

Parameters
[in] | UartNumber | UART Number
[in] | MmioBaseAddress | Base address of UART MMIO space
Return values
EFI_UNSUPPORTED | SerialIo UART isn't in PCI mode.
EFI_SUCCESS | Finish to set SerialIo UART MMIO in PCI mode.

◆ SerialIoUartWrite()

UINTN SerialIoUartWrite | ( | IN UINT8 | UartNumber,
 |  | IN UINT8 * | Buffer,
 |  | IN UINTN | NumberOfBytes
 | ) |  |

Write data to serial device.

If the buffer is NULL, then return 0; if NumberOfBytes is zero, then return 0.

Parameters
[in] | UartNumber | Selects Serial IO UART device
[in] | Buffer | Data pointer
[in] | NumberOfBytes | Number of output bytes which are cached in Buffer.
Return values
Actual number of bytes written to serial device.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SerialIoUartLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Serial IO UART Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _SERIAL_IO_UART_LIB_H_
36 #define _SERIAL_IO_UART_LIB_H_
37
38 #include <Protocol/SerialIo.h>
39
40 /**
41 Polls a serial device to see if there is any data waiting or pending for read.
42 If there is data pending, then TRUE is returned.
43 If there is no data, then FALSE is returned.
44
45 @param[in] UartNumber Selects Serial IO UART device
46
47 @retval TRUE Data is waiting to read from the serial device.
48 @retval FALSE There is no data waiting to read from the serial device.
49 **/
50 BOOLEAN
51 EFIAPI
52 SerialIoUartPolling (
53 IN UINT8 UartNumber
54 );
55
56 /**
57 Write data to serial device.
58
59 If the buffer is NULL, then return 0;
60 if NumberOfBytes is zero, then return 0.
61
62 @param[in] UartNumber Selects Serial IO UART device
63 @param[in] Buffer Data pointer
64 @param[in] NumberOfBytes Number of output bytes which are cached in Buffer.
65
66 @retval Actual number of bytes written to serial device.
67 **/
68 UINTN
69 EFIAPI
70 SerialIoUartWrite (
71 IN UINT8 UartNumber,
72 IN UINT8 *Buffer,
73 IN UINTN NumberOfBytes
74 );
75
76 /**
77 Read data from serial device and save the data in buffer.
78
79 If the buffer is NULL, then return 0;
80 if NumberOfBytes is 0, then return 0.
81
82 @param[in] UartNumber Selects Serial IO UART device
83 @param[out] Buffer Pointer to the buffer that will contain the return data
84 @param[in] NumberOfBytes Number of input bytes to read
85 @param[in] WaitUntilBufferFull TRUE - function waits until whole buffer is filled.
86 FALSE - function returns as soon as no new characters are available.
87
88 @retval Actual number of bytes raed to serial device.
89 **/
90 UINTN
91 EFIAPI
92 SerialIoUartRead (
93 IN UINT8 UartNumber,
94 OUT UINT8 *Buffer,
95 IN UINTN NumberOfBytes,
96 IN BOOLEAN WaitUntilBufferFull
97 );
98
99
100 /**
101 Sets the baud rate, parity, data bits, flow control and stop bits on a serial device.
102
103 @param[in] UartNumber Selects Serial IO UART device
104 @param[in] BaudRate The requested baud rate. A BaudRate value of 0 will use the the
105 device's default interface speed.
106 @param[in] Parity The type of parity to use on this serial device. A Parity value of
107 DefaultParity will use the device's default parity value.
108 @param[in] DataBits The number of data bits to use on the serial device. A DataBits
109 value of 0 will use the device's default data bit setting.
110 @param[in] StopBits The number of stop bits to use on this serial device. A StopBits
111 value of DefaultStopBits will use the device's default number of
112 stop bits.
113 @param[in] AutoFlow Enable/Disable Auto Flow Control
114 **/
115 VOID
116 SerialIoUartSetAttributes (
117 IN UINT8 UartNumber,
118 IN UINT64 BaudRate,
119 IN EFI_PARITY_TYPE Parity,
120 IN UINT8 DataBits,
121 IN EFI_STOP_BITS_TYPE StopBits,
122 IN BOOLEAN AutoFlow
123 );
124
125 /**
126 Dummy Read required after setting/clearing 16550 8bit mode
127
128 @param[in] UartNumber UART Number
129 **/
130 VOID
131 SerialIoUartDummyRead (
132 IN UINT8 UartNumber
133 );
134
135 /**
136 Gets UART out of reset
137
138 @param[in] BaseAddress Base address of UART MMIO space
139 **/
140 VOID
141 SerialIoUartGetOutOfReset (
142 IN UINT64 MmioBaseAddress
143 );
144
145 /**
146 Return whether UART is in PCI mode or not
147
148 @param[in] UartNumber UART Number
149
150 @retval TRUE - UART is in PCI mode
151 @retval FALSE - UART is in Hidden mode or disabled
152 **/
153 BOOLEAN
154 IsSerialIoUartInPciMode (
155 IN UINT8 UartNumber
156 );
157
158 /**
159 Assign MMIO Resource in PCI Mode.
160
161 @param[in] UartNumber UART Number
162 @param[in] MmioBaseAddress Base address of UART MMIO space
163
164 @retval EFI_UNSUPPORTED SerialIo UART isn't in PCI mode.
165 @retval EFI_SUCCESS Finish to set SerialIo UART MMIO in PCI mode.
166
167 **/
168 EFI_STATUS
169 SerialIoUartSetMmioInPciMode (
170 IN UINT8 UartNumber,
171 IN UINT64 MmioBaseAddress
172 );
173
174 #endif // _SERIAL_IO_UART_LIB_H_
SerialIoUartRead
UINTN SerialIoUartRead(IN UINT8 UartNumber, OUT UINT8 *Buffer, IN UINTN NumberOfBytes, IN BOOLEAN WaitUntilBufferFull)
Read data from serial device and save the data in buffer.
IsSerialIoUartInPciMode
BOOLEAN IsSerialIoUartInPciMode(IN UINT8 UartNumber)
Return whether UART is in PCI mode or not.
SerialIoUartPolling
BOOLEAN SerialIoUartPolling(IN UINT8 UartNumber)
Polls a serial device to see if there is any data waiting or pending for read.
SerialIoUartSetMmioInPciMode
EFI_STATUS SerialIoUartSetMmioInPciMode(IN UINT8 UartNumber, IN UINT64 MmioBaseAddress)
Assign MMIO Resource in PCI Mode.
SerialIoUartDummyRead
VOID SerialIoUartDummyRead(IN UINT8 UartNumber)
Dummy Read required after setting/clearing 16550 8bit mode.
SerialIoUartGetOutOfReset
VOID SerialIoUartGetOutOfReset(IN UINT64 MmioBaseAddress)
Gets UART out of reset.
SerialIoUartWrite
UINTN SerialIoUartWrite(IN UINT8 UartNumber, IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data to serial device.
SerialIoUartSetAttributes
VOID SerialIoUartSetAttributes(IN UINT8 UartNumber, IN UINT64 BaudRate, IN EFI_PARITY_TYPE Parity, IN UINT8 DataBits, IN EFI_STOP_BITS_TYPE StopBits, IN BOOLEAN AutoFlow)
Sets the baud rate, parity, data bits, flow control and stop bits on a serial device.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoUartRegs.h File Reference

Register names for Serial IO UART Controllers. More...

Go to the source code of this file.

Detailed Description

Register names for Serial IO UART Controllers.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SerialIoUartRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIoUartRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
SerialIoUartRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Serial IO UART Controllers
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2018 - 2019 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64
65 #ifndef _SERIAL_IO_UART_REGS_H_
66 #define _SERIAL_IO_UART_REGS_H_
67
68 //
69 // MMIO
70 //
71 #define R_PCH_SERIAL_IO_8BIT_UART_RXBUF 0x00
72 #define R_PCH_SERIAL_IO_8BIT_UART_TXBUF 0x00
73 #define R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW 0x00
74 #define R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH 0x01
75 #define R_PCH_SERIAL_IO_8BIT_UART_FCR 0x02
76 #define R_PCH_SERIAL_IO_8BIT_UART_IIR 0x02
77 #define R_PCH_SERIAL_IO_8BIT_UART_LCR 0x03
78 #define R_PCH_SERIAL_IO_8BIT_UART_MCR 0x04
79 #define R_PCH_SERIAL_IO_8BIT_UART_LSR 0x05
80 #define R_PCH_SERIAL_IO_8BIT_UART_USR 0x1F
81 #define R_PCH_SERIAL_IO_32BIT_UART_CTR 0xFC //Component Type Register contains identification code
82 #define UART_COMPONENT_IDENTIFICATION_CODE 0x44570110
83
84 //
85 // MMIO Convergance Layer
86 //
87 #define R_SERIAL_IO_MEM_PPR_RESETS_8BIT 0x81
88 #define R_SERIAL_IO_MEM_PPR_CLK 0x200
89 #define B_SERIAL_IO_MEM_PPR_CLK_EN BIT0
90 #define B_SERIAL_IO_MEM_PPR_CLK_UPDATE BIT31
91 #define V_SERIAL_IO_MEM_PPR_CLK_M_DIV 0x25A
92 #define V_SERIAL_IO_MEM_PPR_CLK_N_DIV 0x7FFF
93
94
95 //
96 // General Purpose
97 //
98 #define R_SERIAL_IO_PCR_GPPRVRW7 0x618
99 #define B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0
100
101 #endif // _SERIAL_IO_UART_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
Classes
SiConfig.h File Reference

Si Config Block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...
struct | SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID. More...

Detailed Description

Si Config Block.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_CONFIG_H_
36 #define _SI_CONFIG_H_
37
38 #define SI_CONFIG_REVISION 2
39
40 extern EFI_GUID gSiConfigGuid;
41
42
43 #pragma pack (push,1)
44
45 /**
46 The Silicon Policy allows the platform code to publish a set of configuration
47 information that the RC drivers will use to configure the silicon hardware.
48
49 <b>Revision 1</b>: - Initial version.
50 <b>Revision 2</b>: - Deprecate CsmFlag
51 **/
52 typedef struct {
53 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
54 //
55 // Platform specific common policies that used by several silicon components.
56 //
57 UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
58 /**
59 This is used to skip the SSID programming in silicon code.
60 When set to TRUE, silicon code will not do any SSID programming and platform code
61 needs to handle that by itself properly.
62 <b>0: FALSE</b>, 1: TRUE
63 **/
64 UINT8 SkipSsidProgramming; ///< offset 29
65 UINT8 RsvdBytes0[2]; ///< offset 30 - 31
66 /**
67 When SkipSsidProgramming is FALSE, silicon code will use this as default value
68 to program the SVID for all internal devices.
69 <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
70 **/
71 UINT16 CustomizedSvid; ///< offset 32 - 33
72 /**
73 When SkipSsidProgramming is FALSE, silicon code will use this as default value
74 to program the Sid for all internal devices.
75 <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
76 **/
77 UINT16 CustomizedSsid; ///< offset 34 - 35
78 /**
79 SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
80 This is valid when SkipSsidProgramming is FALSE;
81 It doesn't need to contain entries for all Intel internal devices.
82 It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Func# which needs
83 to be overridden.
84 In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId are required.
85 <b>Default is NULL.</b>
86
87 E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0:31:3 to CCCC:DDDD,
88 it can be done in platform like this:
89 STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] = {0};
90
91 VOID SiPolicyUpdate () {
92 UINT32 EntryCount = 0;
93 SiPolicy->SkipSsidProgramming = FALSE;
94 SiPolicy->SsidTablePtr = mSsidTablePtr;
95
96 mSsidTablePtr[EntryCount].Address.Bits.Device = SpiDeviceNumber ();
97 mSsidTablePtr[EntryCount].Address.Bits.Function = SpiFunctionNumber ();
98 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xAAAA;
99 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xBBBB;
100 EntryCount ++;
101 mSsidTablePtr[EntryCount].Address.Bits.Device = HdaDevNumber ();
102 mSsidTablePtr[EntryCount].Address.Bits.Function = HdaFuncNumber ();
103 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId = 0xCCCC;
104 mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId = 0xDDDD;
105 EntryCount ++;
106 ASSERT (EntryCount < SI_MAX_DEVICE_COUNT);
107 SiPolicy->NumberOfSsidTableEntry = EntryCount;
108 }
109 **/
110 UINT32 *SsidTablePtr; ///< offset 36 - 39
111 /**
112 Number of valid enties in SsidTablePtr.
113 This is valid when SkipSsidProgramming is FALSE;
114 <b>Default is 0.</b>
115 **/
116 UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
117 UINT8 RsvdBytes1[2]; ///< offset 42 - 43
118 /**
119 This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
120 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
121 skip setting BIOS_DONE MSR at EndofPei.
122 <b>0: FALSE</b>, 1: TRUE
123 **/
124 UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
125 UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
126 } SI_CONFIG;
127
128 #pragma pack (pop)
129
130 #define DEFAULT_SSVID 0x8086
131 #define DEFAULT_SSDID 0x7270
132 #define SI_MAX_DEVICE_COUNT 70
133
134 ///
135 /// Subsystem Vendor ID / Subsystem ID
136 ///
137 typedef struct {
138 UINT16 SubSystemVendorId;
139 UINT16 SubSystemId;
140 } SVID_SID_VALUE;
141
142 //
143 // Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
144 //
145 typedef struct {
146 union {
147 struct {
148 UINT32 Register:12;
149 UINT32 Function:3;
150 UINT32 Device:5;
151 UINT32 Bus:8;
152 UINT32 Reserved1:4;
153 UINT32 Segment:16;
154 UINT32 Reserved2:16;
155 } Bits;
156 UINT64 SegBusDevFuncRegister;
157 } Address;
158 SVID_SID_VALUE SvidSidValue;
159 UINT32 Reserved;
160 } SVID_SID_INIT_ENTRY;
161
162
163 typedef struct {
164 UINT32 SkipBus;
165 UINT32 SkipDevice;
166 UINT32 SkipFunction;
167 } SVID_SID_SKIP_TABLE;
168
169 #endif // _SI_CONFIG_H_
SI_CONFIG::SkipBiosDoneWhenFwUpdate
UINT8 SkipBiosDoneWhenFwUpdate
This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
Definition: SiConfig.h:124
SI_CONFIG::SsidTablePtr
UINT32 * SsidTablePtr
SsidTablePtr contains the SVID_SID_INIT_ENTRY table.
Definition: SiConfig.h:110
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_CONFIG::CustomizedSsid
UINT16 CustomizedSsid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the Sid for...
Definition: SiConfig.h:77
SI_CONFIG::CsmFlag
UINT8 CsmFlag
offset 28 CSM status flag.
Definition: SiConfig.h:57
SI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiConfig.h:53
SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC...
Definition: SiConfig.h:52
SVID_SID_VALUE
Subsystem Vendor ID / Subsystem ID.
Definition: SiConfig.h:137
SI_CONFIG::CustomizedSvid
UINT16 CustomizedSvid
When SkipSsidProgramming is FALSE, silicon code will use this as default value to program the SVID fo...
Definition: SiConfig.h:71
SI_CONFIG::NumberOfSsidTableEntry
UINT16 NumberOfSsidTableEntry
Number of valid enties in SsidTablePtr.
Definition: SiConfig.h:116
SI_CONFIG::SkipSsidProgramming
UINT8 SkipSsidProgramming
This is used to skip the SSID programming in silicon code.
Definition: SiConfig.h:64
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfigBlockLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SiConfigBlockLib.h File Reference

Prototype of the SiConfigBlockLib library. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

UINT16 | GetComponentConfigBlockTotalSize (IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, IN UINT16 TotalBlockCount)
GetComponentConfigBlockTotalSize get config block table total size. More...
EFI_STATUS | AddComponentConfigBlocks (IN VOID *ConfigBlockTableAddress, IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, IN UINT16 TotalBlockCount)
AddComponentConfigBlocks add all config blocks. More...

Detailed Description

Prototype of the SiConfigBlockLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiConfigBlockLib.h.

Function Documentation

◆ AddComponentConfigBlocks()

EFI_STATUS AddComponentConfigBlocks | ( | IN VOID * | ConfigBlockTableAddress,
 |  | IN COMPONENT_BLOCK_ENTRY * | ComponentBlocks,
 |  | IN UINT16 | TotalBlockCount
 | ) |  |

AddComponentConfigBlocks add all config blocks.

Parameters
[in] | ConfigBlockTableAddress | The pointer to add config blocks
[in] | ComponentBlocks | Config blocks array
[in] | TotalBlockCount | Number of blocks
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ GetComponentConfigBlockTotalSize()

UINT16 GetComponentConfigBlockTotalSize | ( | IN COMPONENT_BLOCK_ENTRY * | ComponentBlocks,
 |  | IN UINT16 | TotalBlockCount
 | ) |  |

GetComponentConfigBlockTotalSize get config block table total size.

Parameters
[in] | ComponentBlocks | Component blocks array
[in] | TotalBlockCount | Number of blocks
Return values
Size of config block table
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfigBlockLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SiConfigBlockLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the SiConfigBlockLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_CONFIG_BLOCK_LIB_H_
36 #define _SI_CONFIG_BLOCK_LIB_H_
37
38
39 typedef
40 VOID
41 (*LOAD_DEFAULT_FUNCTION) (
42 IN VOID *ConfigBlockPointer
43 );
44
45 typedef struct {
46 EFI_GUID *Guid;
47 UINT16 Size;
48 UINT8 Revision;
49 LOAD_DEFAULT_FUNCTION LoadDefault;
50 } COMPONENT_BLOCK_ENTRY;
51
52 /**
53 GetComponentConfigBlockTotalSize get config block table total size.
54
55 @param[in] ComponentBlocks Component blocks array
56 @param[in] TotalBlockCount Number of blocks
57
58 @retval Size of config block table
59 **/
60 UINT16
61 EFIAPI
62 GetComponentConfigBlockTotalSize (
63 IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
64 IN UINT16 TotalBlockCount
65 );
66
67 /**
68 AddComponentConfigBlocks add all config blocks.
69
70 @param[in] ConfigBlockTableAddress The pointer to add config blocks
71 @param[in] ComponentBlocks Config blocks array
72 @param[in] TotalBlockCount Number of blocks
73
74 @retval EFI_SUCCESS The policy default is initialized.
75 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
76 **/
77 EFI_STATUS
78 EFIAPI
79 AddComponentConfigBlocks (
80 IN VOID *ConfigBlockTableAddress,
81 IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
82 IN UINT16 TotalBlockCount
83 );
84 #endif // _SI_CONFIG_BLOCK_LIB_H_
AddComponentConfigBlocks
EFI_STATUS AddComponentConfigBlocks(IN VOID *ConfigBlockTableAddress, IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, IN UINT16 TotalBlockCount)
AddComponentConfigBlocks add all config blocks.
GetComponentConfigBlockTotalSize
UINT16 GetComponentConfigBlockTotalSize(IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, IN UINT16 TotalBlockCount)
GetComponentConfigBlockTotalSize get config block table total size.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfigHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
SiConfigHob.h File Reference

Silicon Config HOB is used for gathering platform related Intel silicon information and config setting. More...

#include <SiPolicyStruct.h>
Include dependency graph for SiConfigHob.h:

Go to the source code of this file.

Detailed Description

Silicon Config HOB is used for gathering platform related Intel silicon information and config setting.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiConfigHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiConfigHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SiConfigHob.h
Go to the documentation of this file.
1 /** @file
2 Silicon Config HOB is used for gathering platform
3 related Intel silicon information and config setting.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2016 - 2017 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _SI_CONFIG_HOB_H_
37 #define _SI_CONFIG_HOB_H_
38
39 #include <SiPolicyStruct.h>
40
41 extern EFI_GUID gSiConfigHobGuid;
42
43 // Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
44 typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
45 #endif
SiPolicyStruct.h
Intel reference code configuration policies.
SI_CONFIG
The Silicon Policy allows the platform code to publish a set of configuration information that the RC...
Definition: SiConfig.h:52
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiFvi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros | Enumerations | Functions
SiFvi.h File Reference

Header file for Reference code Firmware Version Info Init Lib implementation. More...

Go to the source code of this file.

Macros

#define | TO_BE_FILLED 0
Non-static SMBIOS table data to be filled later with a dynamically generated value.
#define | TO_BE_FILLED_STRING " "
Initial value should not be NULL.
#define | NO_STRING_AVAILABLE 0
String references in SMBIOS tables. More...
#define | DEFAULT_FVI_DATA()
The string number for ComponentName and VersionString is always calculated dynamically. More...
#define | CPU_FVI_STRING "Reference Code - CPU"
CPU Data definitions.
#define | ME_FVI_STRING "Reference Code - ME"
ME Data definitions.
#define | PCH_FVI_STRING "Reference Code - PCH"
PCH Data definitions.
#define | SA_FVI_STRING "Reference Code - SA - System Agent"
SA Data definitions.

Enumerations

enum ME_FVI_INDEX

Functions

VOID | BuildFviInfoHob (VOID)
Function definitions. More...
EFI_STATUS | UpdateFviInfo (IN UINT8 SmbiosOemType)
Update All Smbios FVI OEM Type Data. More...

Detailed Description

Header file for Reference code Firmware Version Info Init Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiFvi.h.

Macro Definition Documentation

◆ DEFAULT_FVI_DATA

#define DEFAULT_FVI_DATA ( )
Value:
{ \
TO_BE_FILLED, \
TO_BE_FILLED, \
{ \
TO_BE_FILLED, \
TO_BE_FILLED, \
TO_BE_FILLED, \
TO_BE_FILLED, \
} \
}

The string number for ComponentName and VersionString is always calculated dynamically.

The initial value is ignored and should always be TO_BE_FILLED.

Definition at line 65 of file SiFvi.h.

◆ NO_STRING_AVAILABLE

#define NO_STRING_AVAILABLE 0

String references in SMBIOS tables.

This eliminates the need for pointers. See the DMTF SMBIOS Specification v2.7.1, section 6.1.3.

Definition at line 48 of file SiFvi.h.

Enumeration Type Documentation

◆ ME_FVI_INDEX

enum ME_FVI_INDEX
Enumerator
EnumMeRc

ME Reference Code Version.

EnumMebx
Deprecated:
: MEBx Version
EnumMeFw

ME FW Version.

Definition at line 120 of file SiFvi.h.

Function Documentation

◆ BuildFviInfoHob()

VOID BuildFviInfoHob ( VOID )

Function definitions.

Initialize all Smbios FVI OEM Type Data Hob

◆ UpdateFviInfo()

EFI_STATUS UpdateFviInfo ( IN UINT8 SmbiosOemType )

Update All Smbios FVI OEM Type Data.

Parameters
SmbiosOemType - SMBIOS OEM Type
Return values
EFI_UNSUPPORTED | - Could not locate SMBIOS protocol
EFI_SUCCESS | - Successfully update FVI data
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiFvi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SiFvi.h
Go to the documentation of this file.
1 /** @file
2 Header file for Reference code Firmware Version Info Init Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_FVI_H_
36 #define _SI_FVI_H_
37
38 ///
39 /// Non-static SMBIOS table data to be filled later with a dynamically generated value
40 ///
41 #define TO_BE_FILLED 0
42 #define TO_BE_FILLED_STRING " " ///< Initial value should not be NULL
43
44 ///
45 /// String references in SMBIOS tables. This eliminates the need for pointers.
46 /// See the DMTF SMBIOS Specification v2.7.1, section 6.1.3.
47 ///
48 #define NO_STRING_AVAILABLE 0
49 #define STRING_1 1
50 #define STRING_2 2
51 #define STRING_3 3
52 #define STRING_4 4
53 #define STRING_5 5
54 #define STRING_6 6
55 #define STRING_7 7
56
57 #define FVI_NUMBER_OF_STRINGS 2
58
59 #pragma pack(1)
60
61 ///
62 /// The string number for ComponentName and VersionString is always calculated dynamically.
63 /// The initial value is ignored and should always be TO_BE_FILLED.
64 ///
65 #define DEFAULT_FVI_DATA() \
66 { \
67 TO_BE_FILLED, \
68 TO_BE_FILLED, \
69 { \
70 TO_BE_FILLED, \
71 TO_BE_FILLED, \
72 TO_BE_FILLED, \
73 TO_BE_FILLED, \
74 } \
75 }
76
77 #define FVI_VERSION(Version) \
78 { \
79 TO_BE_FILLED, \
80 TO_BE_FILLED, \
81 Version \
82 }
83
84 #define DEFAULT_FVI_STRINGS(Name) \
85 { \
86 Name ## _FVI_STRING, \
87 NULL \
88 }
89
90 #define DEFAULT_FVI_VERSION \
91 { \
92 0xFF, 0xFF, 0xFF, 0xFFFF \
93 }
94
95 #pragma pack()
96
97 ///
98 /// CPU Data definitions
99 ///
100 #define CPU_FVI_STRING "Reference Code - CPU"
101 #define UCODE_FVI_STRING "uCode Version"
102 #define TXT_FVI_STRING "TXT ACM version"
103
104 typedef enum {
105 CPU_RC_VER= 0,
106 UCODE_VER,
107 TXT_VER
108 } CPU_FVI_INDEX;
109
110 ///
111 /// ME Data definitions
112 ///
113 #define ME_FVI_STRING "Reference Code - ME"
114 #define MEBX_FVI_STRING "MEBx version"
115 #define ME_FW_FVI_STRING "ME Firmware Version"
116 #define ME_FW_CONSUMER_SKU_STRING "Consumer SKU"
117 #define ME_FW_CORPORATE_SKU_STRING "Corporate SKU"
118 #define ME_FW_LITE_SKU_STRING "Lite SKU"
119
120 typedef enum {
121 EnumMeRc = 0, ///< ME Reference Code Version
122 EnumMebx, ///< @deprecated: MEBx Version
123 EnumMeFw ///< ME FW Version
124 } ME_FVI_INDEX;
125
126 ///
127 /// PCH Data definitions
128 ///
129 #define PCH_FVI_STRING "Reference Code - PCH"
130 #define PCH_CRID_STATUS_STRING "PCH-CRID Status"
131 #define PCH_CRID_ORIGINAL_VALUE "PCH-CRID Original Value"
132 #define PCH_CRID_NEW_VALUE "PCH-CRID New Value"
133 #define PCH_CRID_ENABLED "Enabled "
134 #define PCH_CRID_DISABLED "Disabled"
135 #define PCH_HSIO_STRING "PCH Hsio Version"
136 #define RAID_FVI_STRING "OPROM - RST - RAID"
137 #define RST_DRIVER_NAME1 L"Intel RST"
138 #define RST_DRIVER_NAME2 L"Intel(R) RST"
139
140 #define FVI_PCH_ICL_LP_AX_HSIO_VERSION \
141 { \
142 0x4, 0, 0, 0 \
143 }
144
145 typedef enum {
146 RC_VER = 0,
147 PCH_CRID_STATUS,
148 PCH_CRID_ORIGINAL,
149 PCH_CRID_NEW,
150 RAID_VER,
151 HSIO_PCHHAX_VER,
152 HSIO_PCHLPAX_VER
153 } PCH_FVI_INDEX;
154
155 ///
156 /// SA Data definitions
157 ///
158 #define SA_FVI_STRING "Reference Code - SA - System Agent"
159 #define MEM_FVI_STRING "Reference Code - MRC"
160 #define PCIE_FVI_STRING "SA - PCIe Version"
161 #define SA_CRID_STATUS "SA-CRID Status"
162 #define SA_CRID_ORIGINAL_VALUE "SA-CRID Original Value"
163 #define SA_CRID_NEW_VALUE "SA-CRID New Value"
164 #define SA_CRID_ENABLED "Enabled "
165 #define SA_CRID_DISABLED "Disabled"
166 #define VBIOS_FVI_STRING "OPROM - VBIOS"
167 #define IOM_FVI_STRING "IO Manageability Engine FW Version"
168 #define PHY_FVI_STRING "PHY Build Version"
169 #define TBT_FVI_STRING "Thunderbolt(TM) FW Version"
170 #define SAM_FVI_STRING "System Agent Manageability Engine FW Version"
171
172 #define CRID_DATA 0x69
173 #define CRID_LOCK 0x17
174
175 typedef enum {
176 SA_RC_VER = 0,
177 MEM_RC_VER,
178 PCIE_VER,
179 CRID_STATUS,
180 CRID_ORIGINAL,
181 CRID_NEW,
182 VBIOS_VER,
183 IOM_FW_VER,
184 PHY_VER,
185 TBT_FW_VER,
186 SAM_FW_VER
187 } SA_FVI_INDEX;
188
189 ///
190 /// Function definitions
191 ///
192 /**
193 Initialize all Smbios FVI OEM Type Data Hob
194 **/
195 VOID
196 EFIAPI
197 BuildFviInfoHob (
198 VOID
199 );
200
201 /**
202 Update All Smbios FVI OEM Type Data
203
204 @param SmbiosOemType - SMBIOS OEM Type
205
206 @retval EFI_UNSUPPORTED - Could not locate SMBIOS protocol
207 @retval EFI_SUCCESS - Successfully update FVI data
208 **/
209 EFI_STATUS
210 EFIAPI
211 UpdateFviInfo (
212 IN UINT8 SmbiosOemType
213 );
214
215 #endif
EnumMeRc
@ EnumMeRc
ME Reference Code Version.
Definition: SiFvi.h:121
UpdateFviInfo
EFI_STATUS UpdateFviInfo(IN UINT8 SmbiosOemType)
Update All Smbios FVI OEM Type Data.
EnumMeFw
@ EnumMeFw
ME FW Version.
Definition: SiFvi.h:123
ME_FVI_INDEX
ME_FVI_INDEX
Definition: SiFvi.h:120
EnumMebx
@ EnumMebx
Definition: SiFvi.h:122
BuildFviInfoHob
VOID BuildFviInfoHob(VOID)
Function definitions.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiFviLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Classes | Macros | Functions
SiFviLib.h File Reference

Header file for Reference code Firmware Version Info Interface Lib implementation. More...

#include <IndustryStandard/SmBios.h>
Include dependency graph for SiFviLib.h:

Go to the source code of this file.

Classes

struct | RC_VERSION
This structure contains the RC version details for FVI SMBIOS records. More...
struct | FVI_DATA
The string number for ComponentName and VersionString is always calculated dynamically. More...

Macros

#define | TO_BE_FILLED 0
Non-static SMBIOS table data to be filled later with a dynamically generated value.
#define | TO_BE_FILLED_STRING " "
Initial value should not be NULL.
#define | NO_STRING_AVAILABLE 0
String references in SMBIOS tables. More...

Functions

EFI_STATUS AddFviEntry (IN FVI_HEADER Header, IN FVI_DATA *Data, IN FVI_STRINGS *Strings)
Create the Reference code version info as per Firmware Version Info (FVI) Interface Spec v0.8 and add the SMBIOS table using the SMBIOS protocol. More...

Detailed Description

Header file for Reference code Firmware Version Info Interface Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2011 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiFviLib.h.

Macro Definition Documentation

◆ NO_STRING_AVAILABLE

#define NO_STRING_AVAILABLE 0

String references in SMBIOS tables.

This eliminates the need for pointers. See the DMTF SMBIOS Specification v2.7.1, section 6.1.3.

Definition at line 51 of file SiFviLib.h.

Function Documentation

◆ AddFviEntry()

EFI_STATUS AddFviEntry | ( | IN FVI_HEADER | Header,
 |  | IN FVI_DATA * | Data,
 |  | IN FVI_STRINGS * | Strings
 | ) |  |

Create the Reference code version info as per Firmware Version Info (FVI) Interface Spec v0.8 and add the SMBIOS table using the SMBIOS protocol.

Invoke this routine to add the table entry when all the Fvi data is finalized.

  • Precondition
    • EFI_SMBIOS_PROTOCOL in Native mode
    Parameters
    [in] | Header | The expanded header includes the standard SMBIOS table header, plus the Count of the number of elements in the Data and Strings arrays.
    [in] | *Data | Pointer to an array of Data blocks.
    [in] | *Strings | Pointer to an array of Strings. There are FVI_NUMBER_OF_STRINGS * Count strings total.
    Return values
    EFI_SUCCESS | - if the data is successfully reported.
    EFI_OUT_OF_RESOURCES | - if not able to get resources.
    EFI_UNSUPPORTED | - if required DataHub or SMBIOS protocol is not available.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiFviLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SiFviLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Reference code Firmware Version Info Interface Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2011 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_FVI_LIB_H_
36 #define _SI_FVI_LIB_H_
37
38 #include <IndustryStandard/SmBios.h>
39
40
41 ///
42 /// Non-static SMBIOS table data to be filled later with a dynamically generated value
43 ///
44 #define TO_BE_FILLED 0
45 #define TO_BE_FILLED_STRING " " ///< Initial value should not be NULL
46
47 ///
48 /// String references in SMBIOS tables. This eliminates the need for pointers.
49 /// See the DMTF SMBIOS Specification v2.7.1, section 6.1.3.
50 ///
51 #define NO_STRING_AVAILABLE 0
52 #define STRING_1 1
53 #define STRING_2 2
54 #define STRING_3 3
55 #define STRING_4 4
56 #define STRING_5 5
57 #define STRING_6 6
58 #define STRING_7 7
59
60 //
61 // Default FVI smbios type, drivers update it dynamically.
62 //
63 #define DEFAULT_FVI_SMBIOS_TYPE 0xDD
64
65 #pragma pack(1)
66
67 ///
68 /// This structure contains the RC version details for FVI SMBIOS records.
69 ///
70 typedef struct {
71 UINT8 MajorVersion;
72 UINT8 MinorVersion;
73 UINT8 Revision;
74 UINT16 BuildNum;
75 } RC_VERSION;
76
77 typedef struct {
78 SMBIOS_STRUCTURE SmbiosHeader;
79 UINT8 Count; ///< Number of (FVI_DATA) data blocks included
80 } FVI_HEADER;
81
82 ///
83 /// The string number for ComponentName and VersionString is always calculated dynamically.
84 /// The initial value is ignored and should always be TO_BE_FILLED.
85 ///
86 typedef struct {
87 UINT8 ComponentName;
88 UINT8 VersionString;
89 RC_VERSION Version;
90 } FVI_DATA;
91
92 #define FVI_NUMBER_OF_STRINGS 2
93 typedef struct {
94 CHAR8 *ComponentName;
95 CHAR8 *VersionString;
96 } FVI_STRINGS;
97
98 #define DEFAULT_FVI_HEADER_DATA(Data) \
99 { \
100 { \
101 DEFAULT_FVI_SMBIOS_TYPE, \
102 sizeof(FVI_HEADER) + sizeof (Data), \
103 0, \
104 }, \
105 sizeof (Data) / sizeof (FVI_DATA) \
106 }
107
108 #define DEFAULT_FVI_DATA() \
109 { \
110 TO_BE_FILLED, \
111 TO_BE_FILLED, \
112 { \
113 TO_BE_FILLED, \
114 TO_BE_FILLED, \
115 TO_BE_FILLED, \
116 TO_BE_FILLED, \
117 } \
118 }
119
120 #define FVI_VERSION(Version) \
121 { \
122 TO_BE_FILLED, \
123 TO_BE_FILLED, \
124 Version \
125 }
126
127 #define DEFAULT_FVI_STRINGS(Name) \
128 { \
129 Name ## _FVI_STRING, \
130 NULL \
131 }
132
133 #define DEFAULT_FVI_VERSION \
134 { \
135 0xFF, 0xFF, 0xFF, 0xFFFF \
136 }
137 #pragma pack()
138
139 /**
140 Create the Reference code version info as per Firmware Version Info (FVI) Interface Spec v0.8
141 and add the SMBIOS table using the SMBIOS protocol
142
143 Invoke this routine to add the table entry when all the Fvi data is finalized.
144
145 - @pre
146 - EFI_SMBIOS_PROTOCOL in Native mode
147
148 @param[in] Header The expanded header includes the standard SMBIOS table header, plus the Count
149 of the number of elements in the Data and Strings arrays.
150 @param[in] *Data Pointer to an array of Data blocks.
151 @param[in] *Strings Pointer to an array of Strings. There are FVI_NUMBER_OF_STRINGS * Count strings total.
152
153 @retval EFI_SUCCESS - if the data is successfully reported.
154 @retval EFI_OUT_OF_RESOURCES - if not able to get resources.
155 @retval EFI_UNSUPPORTED - if required DataHub or SMBIOS protocol is not available.
156 **/
157 EFI_STATUS
158 AddFviEntry (
159 IN FVI_HEADER Header,
160 IN FVI_DATA *Data,
161 IN FVI_STRINGS *Strings
162 );
163
164 #endif
FVI_DATA
The string number for ComponentName and VersionString is always calculated dynamically.
Definition: SiFviLib.h:86
AddFviEntry
EFI_STATUS AddFviEntry(IN FVI_HEADER Header, IN FVI_DATA *Data, IN FVI_STRINGS *Strings)
Create the Reference code version info as per Firmware Version Info (FVI) Interface Spec v0....
RC_VERSION
This structure contains the RC version details for FVI SMBIOS records.
Definition: SiFviLib.h:70
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiMtrrLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SiMtrrLib.h File Reference

Header file for Silicon code Mtrr Lib implementation. More...

Go to the source code of this file.

Functions

EFI_STATUS MtrrTransfer2DefaultWB (OUT MTRR_SETTINGS *MtrrSetting)
Function attempts to transfer MTRRs default WriteBack and update MTRRs Setting. More...

Detailed Description

Header file for Silicon code Mtrr Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiMtrrLib.h.

Function Documentation

◆ MtrrTransfer2DefaultWB()

EFI_STATUS MtrrTransfer2DefaultWB ( OUT MTRR_SETTINGS * MtrrSetting )

Function attempts to transfer MTRRs default WriteBack and update MTRRs Setting.

Parameters
[out] MtrrSetting - A buffer holding all MTRRs content.
Return values
EFI_SUCCESS - The function completed successfully. EFI_UNSUPPORTED - Mtrr is not supported. EFI_INVALID_PARAMETER - MtrrSetting is NULL.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiMtrrLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SiMtrrLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Silicon code Mtrr Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_MTRR_LIB_H_
36 #define _SI_MTRR_LIB_H_
37
38 /**
39 Function attempts to transfer MTRRs default WriteBack
40 and update MTRRs Setting.
41
42 @param[out] MtrrSetting - A buffer holding all MTRRs content.
43
44 @retval EFI_SUCCESS - The function completed successfully.
45 EFI_UNSUPPORTED - Mtrr is not supported.
46 EFI_INVALID_PARAMETER - MtrrSetting is NULL.
47 **/
48 EFI_STATUS
49 EFIAPI
50 MtrrTransfer2DefaultWB (
51 OUT MTRR_SETTINGS *MtrrSetting
52 );
53
54 #endif
MtrrTransfer2DefaultWB
EFI_STATUS MtrrTransfer2DefaultWB(OUT MTRR_SETTINGS *MtrrSetting)
Function attempts to transfer MTRRs default WriteBack and update MTRRs Setting.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SiPolicyLib.h File Reference

Prototype of the SiPolicyLib library. More...

#include <Ppi/SiPolicy.h>
Include dependency graph for SiPolicyLib.h:

Go to the source code of this file.

Functions

VOID | SiPreMemPrintPolicyPpi (IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole SI_PREMEM_POLICY_PPI and serial out. More...
VOID | SiPrintPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
Print whole SI_POLICY_PPI and serial out. More...
EFI_STATUS | SiCreatePreMemConfigBlocks (OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi)
SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy. More...
EFI_STATUS | SiCreateConfigBlocks (OUT SI_POLICY_PPI **SiPolicyPpi)
SiCreateConfigBlocks creates the config blocksg of Silicon Policy. More...
EFI_STATUS | SiPreMemInstallPolicyPpi (IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. More...
EFI_STATUS | SiPreMemInstallPolicyReadyPpi (VOID)
SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi. More...
EFI_STATUS | SiInstallPolicyPpi (IN SI_POLICY_PPI *SiPolicyPpi)
SiInstallPolicyPpi installs SiPolicyPpi. More...
EFI_STATUS | SiInstallPolicyReadyPpi (VOID)
SiInstallPolicyReadyPpi installs SiPolicyReadyPpi. More...
VOID | DumpSiPolicy (IN SI_POLICY_PPI *SiPolicyPpi)
Print out all silicon policy information. More...

Detailed Description

Prototype of the SiPolicyLib library.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPolicyLib.h.

Function Documentation

◆ DumpSiPolicy()

VOID DumpSiPolicy ( IN SI_POLICY_PPI * SiPolicyPpi )

Print out all silicon policy information.

Parameters
[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
Return values
none

◆ SiCreateConfigBlocks()

EFI_STATUS SiCreateConfigBlocks ( OUT SI_POLICY_PPI ** SiPolicyPpi )

SiCreateConfigBlocks creates the config blocksg of Silicon Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiCreatePreMemConfigBlocks()

EFI_STATUS SiCreatePreMemConfigBlocks ( OUT SI_PREMEM_POLICY_PPI ** SiPreMemPolicyPpi )

SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy.

It allocates and zero out buffer, and fills in the Intel default settings.

Parameters
[out] SiPreMemPolicyPpi The pointer to get Silicon PREMEM Policy PPI instance
Return values
EFI_SUCCESS | The policy default is initialized.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiInstallPolicyPpi()

EFI_STATUS SiInstallPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

SiInstallPolicyPpi installs SiPolicyPpi.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiInstallPolicyReadyPpi()

EFI_STATUS SiInstallPolicyReadyPpi ( VOID )

SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiPreMemInstallPolicyPpi()

EFI_STATUS SiPreMemInstallPolicyPpi ( IN SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Parameters
[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance
Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiPreMemInstallPolicyReadyPpi()

EFI_STATUS SiPreMemInstallPolicyReadyPpi ( VOID )

SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.

While installed, RC assumes the Policy is ready and finalized. So please update and override any setting before calling this function.

Return values
EFI_SUCCESS | The policy is installed.
EFI_OUT_OF_RESOURCES | Insufficient resources to create buffer

◆ SiPreMemPrintPolicyPpi()

VOID SiPreMemPrintPolicyPpi ( IN SI_PREMEM_POLICY_PPI * SiPreMemPolicyPpi )

Print whole SI_PREMEM_POLICY_PPI and serial out.

Parameters
[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance

◆ SiPrintPolicyPpi()

VOID SiPrintPolicyPpi ( IN SI_POLICY_PPI * SiPolicyPpi )

Print whole SI_POLICY_PPI and serial out.

Parameters
[in] SiPolicyPpi The RC Policy PPI instance
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SiPolicyLib.h
Go to the documentation of this file.
1 /** @file
2 Prototype of the SiPolicyLib library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_POLICY_LIB_H_
36 #define _SI_POLICY_LIB_H_
37
38 #include <Ppi/SiPolicy.h>
39
40 /**
41 Print whole SI_PREMEM_POLICY_PPI and serial out.
42
43 @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance
44 **/
45 VOID
46 EFIAPI
47 SiPreMemPrintPolicyPpi (
48 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
49 );
50
51 /**
52 Print whole SI_POLICY_PPI and serial out.
53
54 @param[in] SiPolicyPpi The RC Policy PPI instance
55 **/
56 VOID
57 EFIAPI
58 SiPrintPolicyPpi (
59 IN SI_POLICY_PPI *SiPolicyPpi
60 );
61
62 /**
63 SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy.
64 It allocates and zero out buffer, and fills in the Intel default settings.
65
66 @param[out] SiPreMemPolicyPpi The pointer to get Silicon PREMEM Policy PPI instance
67
68 @retval EFI_SUCCESS The policy default is initialized.
69 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
70 **/
71 EFI_STATUS
72 EFIAPI
73 SiCreatePreMemConfigBlocks (
74 OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi
75 );
76
77 /**
78 SiCreateConfigBlocks creates the config blocksg of Silicon Policy.
79 It allocates and zero out buffer, and fills in the Intel default settings.
80
81 @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI instance
82
83 @retval EFI_SUCCESS The policy default is initialized.
84 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
85 **/
86 EFI_STATUS
87 EFIAPI
88 SiCreateConfigBlocks (
89 OUT SI_POLICY_PPI **SiPolicyPpi
90 );
91
92 /**
93 SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
94 While installed, RC assumes the Policy is ready and finalized. So please update and override
95 any setting before calling this function.
96
97 @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI instance
98
99 @retval EFI_SUCCESS The policy is installed.
100 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
101 **/
102 EFI_STATUS
103 EFIAPI
104 SiPreMemInstallPolicyPpi (
105 IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
106 );
107
108 /**
109 SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
110 While installed, RC assumes the Policy is ready and finalized. So please update and override
111 any setting before calling this function.
112
113 @retval EFI_SUCCESS The policy is installed.
114 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
115 **/
116 EFI_STATUS
117 EFIAPI
118 SiPreMemInstallPolicyReadyPpi (
119 VOID
120 );
121
122 /**
123 SiInstallPolicyPpi installs SiPolicyPpi.
124 While installed, RC assumes the Policy is ready and finalized. So please update and override
125 any setting before calling this function.
126
127 @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
128
129 @retval EFI_SUCCESS The policy is installed.
130 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
131 **/
132 EFI_STATUS
133 EFIAPI
134 SiInstallPolicyPpi (
135 IN SI_POLICY_PPI *SiPolicyPpi
136 );
137
138 /**
139 SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
140 While installed, RC assumes the Policy is ready and finalized. So please update and override
141 any setting before calling this function.
142
143 @retval EFI_SUCCESS The policy is installed.
144 @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
145 **/
146 EFI_STATUS
147 EFIAPI
148 SiInstallPolicyReadyPpi (
149 VOID
150 );
151
152 /**
153 Print out all silicon policy information.
154
155 @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance
156
157 @retval none
158 **/
159 VOID
160 DumpSiPolicy (
161 IN SI_POLICY_PPI *SiPolicyPpi
162 );
163 #endif // _SI_POLICY_LIB_H_
DumpSiPolicy
VOID DumpSiPolicy(IN SI_POLICY_PPI *SiPolicyPpi)
Print out all silicon policy information.
SiCreatePreMemConfigBlocks
EFI_STATUS SiCreatePreMemConfigBlocks(OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi)
SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy.
SiPreMemPrintPolicyPpi
VOID SiPreMemPrintPolicyPpi(IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
Print whole SI_PREMEM_POLICY_PPI and serial out.
SiInstallPolicyPpi
EFI_STATUS SiInstallPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
SiInstallPolicyPpi installs SiPolicyPpi.
SiPrintPolicyPpi
VOID SiPrintPolicyPpi(IN SI_POLICY_PPI *SiPolicyPpi)
Print whole SI_POLICY_PPI and serial out.
SiCreateConfigBlocks
EFI_STATUS SiCreateConfigBlocks(OUT SI_POLICY_PPI **SiPolicyPpi)
SiCreateConfigBlocks creates the config blocksg of Silicon Policy.
SiInstallPolicyReadyPpi
EFI_STATUS SiInstallPolicyReadyPpi(VOID)
SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
SiPreMemInstallPolicyReadyPpi
EFI_STATUS SiPreMemInstallPolicyReadyPpi(VOID)
SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
SiPreMemInstallPolicyPpi
EFI_STATUS SiPreMemInstallPolicyPpi(IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi)
SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes
SiPolicyProtocol.h File Reference

Protocol used for specifying platform related Silicon information and policy setting. More...

#include <IndustryStandard/Hsti.h>
Include dependency graph for SiPolicyProtocol.h:

Go to the source code of this file.

Classes

struct DXE_SI_POLICY_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the Silicon drivers will use to configure the processor in the DXE phase. More...

Detailed Description

Protocol used for specifying platform related Silicon information and policy setting.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file SiPolicyProtocol.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
SiPolicyProtocol.h
Go to the documentation of this file.
1 /** @file
2 Protocol used for specifying platform related Silicon information and policy setting.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _SI_POLICY_PROTOCOL_H_
36 #define _SI_POLICY_PROTOCOL_H_
37
38 #include <IndustryStandard/Hsti.h>
39
40 //
41 // DXE_SI_POLICY_PROTOCOL revisions
42 //
43 #define DXE_SI_POLICY_PROTOCOL_REVISION 2
44
45 extern EFI_GUID gDxeSiPolicyProtocolGuid;
46
47 #pragma pack (push,1)
48
49 /**
50 The protocol allows the platform code to publish a set of configuration information that the
51 Silicon drivers will use to configure the processor in the DXE phase.
52 This Policy Protocol needs to be initialized for Silicon configuration.
53 @note The Protocol has to be published before processor DXE drivers are dispatched.
54 **/
55 typedef struct {
56 /**
57 This member specifies the revision of the Si Policy protocol. This field is used to indicate backward
58 compatible changes to the protocol. Any such changes to this protocol will result in an update in the revision number.
59
60 <b>Revision 1</b>:
61 - Initial version
62 <b>Revision 2</b>:
63 - Added SmbiosOemTypeFirmwareVersionInfo to determines the SMBIOS OEM type
64 **/
65 UINT8 Revision;
66 /**
67 SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
68 values 0-0x7F will be treated as disable FVI reporting.
69 FVI structure uses it as SMBIOS OEM type to provide version information.
70 **/
71 UINT8 SmbiosOemTypeFirmwareVersionInfo;
72 UINT8 ReservedByte[6]; ///< Reserved bytes, align to multiple 8.
73 /**
74 This member describes a pointer to Hsti results from previous boot. In order to mitigate the large performance cost
75 of performing all of the platform security tests on each boot, we can save the results across boots and retrieve
76 and point this policy to them prior to the launch of HstiSiliconDxe. Logic should be implemented to not populate this
77 upon major platform changes (i.e changes to setup option or platform hw)to ensure that results accurately reflect the
78 configuration of the platform.
79 **/
80 ADAPTER_INFO_PLATFORM_SECURITY *Hsti; ///< This is a pointer to Hsti results from previous boot
81 UINTN HstiSize; ///< Size of results, if setting Hsti policy to point to previous results
82 } DXE_SI_POLICY_PROTOCOL;
83
84 #pragma pack (pop)
85
86 #endif
DXE_SI_POLICY_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the Silicon ...
Definition: SiPolicyProtocol.h:55
DXE_SI_POLICY_PROTOCOL::SmbiosOemTypeFirmwareVersionInfo
UINT8 SmbiosOemTypeFirmwareVersionInfo
SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,...
Definition: SiPolicyProtocol.h:71
DXE_SI_POLICY_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of the Si Policy protocol.
Definition: SiPolicyProtocol.h:65
DXE_SI_POLICY_PROTOCOL::Hsti
ADAPTER_INFO_PLATFORM_SECURITY * Hsti
This member describes a pointer to Hsti results from previous boot.
Definition: SiPolicyProtocol.h:80
DXE_SI_POLICY_PROTOCOL::HstiSize
UINTN HstiSize
Size of results, if setting Hsti policy to point to previous results.
Definition: SiPolicyProtocol.h:81
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyStruct.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Macros
SiPolicyStruct.h File Reference

Intel reference code configuration policies. More...

#include <ConfigBlock.h>
#include <ConfigBlock/SiPreMemConfig.h>
#include <ConfigBlock/SiConfig.h>
Include dependency graph for SiPolicyStruct.h:
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Classes

struct | _SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem
All SI config block change history will be listed here

. More...
struct | _SI_POLICY_STRUCT
SI Policy PPI
All SI config block change history will be listed here

. More...

Macros

#define | SI_POLICY_REVISION 1
Silicon Policy revision number Any change to this structure will result in an update in the revision number. More...
#define | SI_PREMEM_POLICY_REVISION 1
Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number. More...

Detailed Description

Intel reference code configuration policies.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPolicyStruct.h.

Macro Definition Documentation

◆ SI_POLICY_REVISION

#define SI_POLICY_REVISION 1

Silicon Policy revision number Any change to this structure will result in an update in the revision number.

This member specifies the revision of the Silicon Policy. This field is used to indicate change to the policy structure.

Revision 1:

  • Initial version.

Definition at line 52 of file SiPolicyStruct.h.

◆ SI_PREMEM_POLICY_REVISION

#define SI_PREMEM_POLICY_REVISION 1

Silicon pre-memory Policy revision number Any change to this structure will result in an update in the revision number.

Revision 1:

  • Initial version.

Definition at line 61 of file SiPolicyStruct.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPolicyStruct.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SiPolicyStruct.h
Go to the documentation of this file.
1 /** @file
2 Intel reference code configuration policies.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_POLICY_STRUCT_H_
36 #define _SI_POLICY_STRUCT_H_
37
38 #include <ConfigBlock.h>
39 #include <ConfigBlock/SiPreMemConfig.h>
40 #include <ConfigBlock/SiConfig.h>
41
42 /**
43 Silicon Policy revision number
44 Any change to this structure will result in an update in the revision number
45
46 This member specifies the revision of the Silicon Policy. This field is used to indicate change
47 to the policy structure.
48
49 <b>Revision 1</b>:
50 - Initial version.
51 **/
52 #define SI_POLICY_REVISION 1
53
54 /**
55 Silicon pre-memory Policy revision number
56 Any change to this structure will result in an update in the revision number
57
58 <b>Revision 1</b>:
59 - Initial version.
60 **/
61 #define SI_PREMEM_POLICY_REVISION 1
62
63
64 /**
65 SI Policy PPI in Pre-Mem\n
66 All SI config block change history will be listed here\n\n
67
68 - <b>Revision 1</b>:
69 - Initial version.\n
70 **/
71 struct _SI_PREMEM_POLICY_STRUCT {
72 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
73 /*
74 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
75 */
76 };
77
78 /**
79 SI Policy PPI\n
80 All SI config block change history will be listed here\n\n
81
82 - <b>Revision 1</b>:
83 - Initial version.\n
84 **/
85 struct _SI_POLICY_STRUCT {
86 CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
87 /*
88 Individual Config Block Structures are added here in memory as part of AddConfigBlock()
89 */
90 };
91
92 #endif
_SI_PREMEM_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:72
ConfigBlock.h
Header file for Config Block Lib implementation.
SiPreMemConfig.h
Si Config Block PreMem.
_SI_PREMEM_POLICY_STRUCT
SI Policy PPI in Pre-Mem All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:71
_SI_POLICY_STRUCT
SI Policy PPI All SI config block change history will be listed here .
Definition: SiPolicyStruct.h:85
SiConfig.h
Si Config Block.
_CONFIG_BLOCK_TABLE_STRUCT
Config Block Table Header.
Definition: ConfigBlock.h:50
_SI_POLICY_STRUCT::TableHeader
CONFIG_BLOCK_TABLE_HEADER TableHeader
Config Block Table Header.
Definition: SiPolicyStruct.h:86
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
Classes
SiPreMemConfig.h File Reference

Si Config Block PreMem. More...

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Classes

struct SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that the RC drivers will use to configure the silicon hardware. More...

Detailed Description

Si Config Block PreMem.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
SiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 Si Config Block PreMem
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SI_PREMEM_CONFIG_H_
36 #define _SI_PREMEM_CONFIG_H_
37
38 #define SI_PREMEM_CONFIG_REVISION 1
39
40 extern EFI_GUID gSiPreMemConfigGuid;
41
42 typedef enum {
43 ProbeTypeDisabled = 0x00,
44 ProbeTypeDciOob = 0x02,
45 ProbeType2WireDciOob = 0x06,
46 ProbeTypeManual = 0x07,
47 ProbeTypeMax
48 } PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
49
50 #pragma pack (push,1)
51 /**
52 The Silicon PreMem Policy allows the platform code to publish a set of configuration
53 information that the RC drivers will use to configure the silicon hardware.
54
55 <b>Revision 1</b>:
56 - Initial version.
57 **/
58 typedef struct {
59 CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
60 /**
61 Platform Debug Consent
62 As a main switch to enable platform debug capability and relevant settings with specified probe type.
63 Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
64
65 PDC-dependent policies are listed:
66 DciPreMemConfig->DciEn
67 CpuTraceHubConfig->EnableMode
68 CpuTraceHubConfig->CpuTraceHubMemReg0Size
69 CpuTraceHubConfig->CpuTraceHubMemReg1Size
70 PchTraceHubPreMemConfig->EnableMode
71 PchTraceHubPreMemConfig->MemReg0Size
72 PchTraceHubPreMemConfig->MemReg1Size
73
74 Note: DCI OOB (aka BSSB) uses CCA probe.
75 Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
76 <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
77 **/
78 UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
79 UINT32 RsvdBits : 28;
80 /**
81 This is used to skip override boot mode during firmware update boot mode.
82 When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
83 skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
84 <b>0: FALSE</b>, 1: TRUE
85 **/
86 UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
87 UINT8 RsvdBytes[3]; /// offset 33 - 35
88 } SI_PREMEM_CONFIG;
89
90 #pragma pack (pop)
91 #endif // _SI_PREMEM_CONFIG_H_
SI_PREMEM_CONFIG::RsvdBits
UINT32 RsvdBits
offset 28 - 31
Definition: SiPreMemConfig.h:79
SI_PREMEM_CONFIG
The Silicon PreMem Policy allows the platform code to publish a set of configuration information that...
Definition: SiPreMemConfig.h:58
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SI_PREMEM_CONFIG::PlatformDebugConsent
UINT32 PlatformDebugConsent
Platform Debug Consent As a main switch to enable platform debug capability and relevant settings wit...
Definition: SiPreMemConfig.h:78
SI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0 - 27 Config Block Header.
Definition: SiPreMemConfig.h:59
SI_PREMEM_CONFIG::SkipOverrideBootModeWhenFwUpdate
UINT8 SkipOverrideBootModeWhenFwUpdate
This is used to skip override boot mode during firmware update boot mode.
Definition: SiPreMemConfig.h:86
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosCacheInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
SmbiosCacheInfoHob.h File Reference

Header file for SMBIOS Cache Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
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Classes

struct SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Cache Info HOB.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

System Management BIOS (SMBIOS) Reference Specification v3.1.0 dated 2016-Nov-16 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf

Definition in file SmbiosCacheInfoHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosCacheInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SmbiosCacheInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMBIOS Cache Info HOB
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
7
8 This program and the accompanying materials are licensed and made available under
9 the terms and conditions of the BSD License which accompanies this distribution.
10 The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 System Management BIOS (SMBIOS) Reference Specification v3.1.0
17 dated 2016-Nov-16 (DSP0134)
18 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
19 **/
20
21 #ifndef _SMBIOS_CACHE_INFO_HOB_H_
22 #define _SMBIOS_CACHE_INFO_HOB_H_
23
24 #include <Uefi.h>
25 #include <Pi/PiHob.h>
26
27 #pragma pack(1)
28 ///
29 /// SMBIOS Cache Info HOB Structure
30 ///
31 typedef struct {
32 UINT16 ProcessorSocketNumber;
33 UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
34 UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
35 UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.1 Section7.8 Table36
36 UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
37 UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
38 UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
39 UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.1 Section7.8.2
40 UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
41 UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3
42 UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4
43 UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5
44 //
45 // Add for smbios 3.1.0
46 //
47 UINT32 MaximumCacheSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
48 UINT32 InstalledSize2; ///< Format defined in SMBIOS Spec v3.1 Section7.8.1
49 /**
50 String Buffer - each string terminated by NULL "0x00"
51 String buffer terminated by double NULL "0x0000"
52 **/
53 } SMBIOS_CACHE_INFO;
54 #pragma pack()
55
56 #endif // _SMBIOS_CACHE_INFO_HOB_H_
SMBIOS_CACHE_INFO::InstalledSize
UINT16 InstalledSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:37
SMBIOS_CACHE_INFO::SystemCacheType
UINT8 SystemCacheType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.4.
Definition: SmbiosCacheInfoHob.h:42
SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure.
Definition: SmbiosCacheInfoHob.h:31
SMBIOS_CACHE_INFO::InstalledSize2
UINT32 InstalledSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:48
SMBIOS_CACHE_INFO::MaxCacheSize
UINT16 MaxCacheSize
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:36
SMBIOS_CACHE_INFO::SupportedSramType
UINT16 SupportedSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:38
SMBIOS_CACHE_INFO::CacheConfiguration
UINT16 CacheConfiguration
Format defined in SMBIOS Spec v3.1 Section7.8 Table36.
Definition: SmbiosCacheInfoHob.h:35
SMBIOS_CACHE_INFO::Associativity
UINT8 Associativity
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.5.
Definition: SmbiosCacheInfoHob.h:43
SMBIOS_CACHE_INFO::CacheSpeed
UINT8 CacheSpeed
Cache Speed in nanoseconds. 0 if speed is unknown.
Definition: SmbiosCacheInfoHob.h:40
SMBIOS_CACHE_INFO::NumberOfCacheLevels
UINT16 NumberOfCacheLevels
Based on Number of Cache Types L1/L2/L3.
Definition: SmbiosCacheInfoHob.h:33
SMBIOS_CACHE_INFO::ErrorCorrectionType
UINT8 ErrorCorrectionType
ENUM Format defined in SMBIOS Spec v3.1 Section 7.8.3.
Definition: SmbiosCacheInfoHob.h:41
SMBIOS_CACHE_INFO::MaximumCacheSize2
UINT32 MaximumCacheSize2
Format defined in SMBIOS Spec v3.1 Section7.8.1.
Definition: SmbiosCacheInfoHob.h:47
SMBIOS_CACHE_INFO::CurrentSramType
UINT16 CurrentSramType
Format defined in SMBIOS Spec v3.1 Section7.8.2.
Definition: SmbiosCacheInfoHob.h:39
SMBIOS_CACHE_INFO::SocketDesignationStrIndex
UINT8 SocketDesignationStrIndex
String Index in the string Buffer. Example "L1-CACHE".
Definition: SmbiosCacheInfoHob.h:34
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosProcessorInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
SmbiosProcessorInfoHob.h File Reference

Header file for SMBIOS Processor Info HOB. More...

#include <Uefi.h>
#include <Pi/PiHob.h>
Include dependency graph for SmbiosProcessorInfoHob.h:

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Classes

struct SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure. More...

Detailed Description

Header file for SMBIOS Processor Info HOB.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

System Management BIOS (SMBIOS) Reference Specification v3.1.0 dated 2016-Nov-16 (DSP0134) http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf

Definition in file SmbiosProcessorInfoHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosProcessorInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
SmbiosProcessorInfoHob.h
Go to the documentation of this file.
1 /** @file
2 Header file for SMBIOS Processor Info HOB
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 System Management BIOS (SMBIOS) Reference Specification v3.1.0
16 dated 2016-Nov-16 (DSP0134)
17 http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.1.0.pdf
18 **/
19
20 #ifndef _SMBIOS_PROCESSOR_INFO_HOB_H_
21 #define _SMBIOS_PROCESSOR_INFO_HOB_H_
22
23 #include <Uefi.h>
24 #include <Pi/PiHob.h>
25
26 #pragma pack(1)
27 ///
28 /// SMBIOS Processor Info HOB Structure
29 ///
30 typedef struct {
31 UINT16 TotalNumberOfSockets;
32 UINT16 CurrentSocketNumber;
33 UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.1
34 /** This info is used for both ProcessorFamily and ProcessorFamily2 fields
35 See ENUM defined in SMBIOS Spec v3.1 Section 7.5.2
36 **/
37 UINT16 ProcessorFamily;
38 UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
39 UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.3
40 UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
41 UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.4
42 UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
43 UINT16 MaxSpeedInMHz; ///< Snapshot of Max processor speed during boot
44 UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
45 UINT8 Status; ///< Format defined in the SMBIOS Spec v3.1 Table 21
46 UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.1 Section 7.5.5
47 /** This info is used for both CoreCount & CoreCount2 fields
48 See detailed description in SMBIOS Spec v3.1 Section 7.5.6
49 **/
50 UINT16 CoreCount;
51 /** This info is used for both CoreEnabled & CoreEnabled2 fields
52 See detailed description in SMBIOS Spec v3.1 Section 7.5.7
53 **/
54 UINT16 EnabledCoreCount;
55 /** This info is used for both ThreadCount & ThreadCount2 fields
56 See detailed description in SMBIOS Spec v3.1 Section 7.5.8
57 **/
58 UINT16 ThreadCount;
59 UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.1 Section 7.5.9
60 /**
61 String Buffer - each string terminated by NULL "0x00"
62 String buffer terminated by double NULL "0x0000"
63 **/
64 } SMBIOS_PROCESSOR_INFO;
65 #pragma pack()
66
67 #endif // _SMBIOS_PROCESSOR_INFO_HOB_H_
SMBIOS_PROCESSOR_INFO::Voltage
UINT8 Voltage
Format defined in SMBIOS Spec v3.1 Section 7.5.4.
Definition: SmbiosProcessorInfoHob.h:41
SMBIOS_PROCESSOR_INFO::Status
UINT8 Status
Format defined in the SMBIOS Spec v3.1 Table 21.
Definition: SmbiosProcessorInfoHob.h:45
SMBIOS_PROCESSOR_INFO::ProcessorFamily
UINT16 ProcessorFamily
This info is used for both ProcessorFamily and ProcessorFamily2 fields See ENUM defined in SMBIOS Spe...
Definition: SmbiosProcessorInfoHob.h:37
SMBIOS_PROCESSOR_INFO::EnabledCoreCount
UINT16 EnabledCoreCount
This info is used for both CoreEnabled & CoreEnabled2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:54
SMBIOS_PROCESSOR_INFO::ThreadCount
UINT16 ThreadCount
This info is used for both ThreadCount & ThreadCount2 fields See detailed description in SMBIOS Spec ...
Definition: SmbiosProcessorInfoHob.h:58
SMBIOS_PROCESSOR_INFO::ProcessorId
UINT64 ProcessorId
ENUM defined in SMBIOS Spec v3.1 Section 7.5.3.
Definition: SmbiosProcessorInfoHob.h:39
SMBIOS_PROCESSOR_INFO::CurrentSpeedInMHz
UINT16 CurrentSpeedInMHz
Snapshot of current processor speed during boot.
Definition: SmbiosProcessorInfoHob.h:44
SMBIOS_PROCESSOR_INFO::MaxSpeedInMHz
UINT16 MaxSpeedInMHz
Snapshot of Max processor speed during boot.
Definition: SmbiosProcessorInfoHob.h:43
SMBIOS_PROCESSOR_INFO::ProcessorVersionStrIndex
UINT8 ProcessorVersionStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:40
SMBIOS_PROCESSOR_INFO::CoreCount
UINT16 CoreCount
This info is used for both CoreCount & CoreCount2 fields See detailed description in SMBIOS Spec v3....
Definition: SmbiosProcessorInfoHob.h:50
SMBIOS_PROCESSOR_INFO::ProcessorManufacturerStrIndex
UINT8 ProcessorManufacturerStrIndex
Index of the String in the String Buffer.
Definition: SmbiosProcessorInfoHob.h:38
SMBIOS_PROCESSOR_INFO::ProcessorCharacteristics
UINT16 ProcessorCharacteristics
Format defined in SMBIOS Spec v3.1 Section 7.5.9.
Definition: SmbiosProcessorInfoHob.h:59
SMBIOS_PROCESSOR_INFO::ExternalClockInMHz
UINT16 ExternalClockInMHz
External Clock Frequency. Set to 0 if unknown.
Definition: SmbiosProcessorInfoHob.h:42
SMBIOS_PROCESSOR_INFO::ProcessorType
UINT8 ProcessorType
ENUM defined in SMBIOS Spec v3.1 Section 7.5.1.
Definition: SmbiosProcessorInfoHob.h:33
SMBIOS_PROCESSOR_INFO::ProcessorUpgrade
UINT8 ProcessorUpgrade
ENUM defined in SMBIOS Spec v3.1 Section 7.5.5.
Definition: SmbiosProcessorInfoHob.h:46
SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure.
Definition: SmbiosProcessorInfoHob.h:30
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosProcessorLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SmbiosProcessorLib.h File Reference

Header file for SmbiosProcessorLib implementation. More...

Go to the source code of this file.

Functions

EFI_STATUS AddSmbiosProcessorAndCacheTables (VOID)
Add Smbios Cache information (type 7) table and Processor information (type 4) table using the HOB info from Silicon. More...

Detailed Description

Header file for SmbiosProcessorLib implementation.

INTEL CONFIDENTIAL

Copyright (c) 2016, - 2020 Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file SmbiosProcessorLib.h.

Function Documentation

◆ AddSmbiosProcessorAndCacheTables()

EFI_STATUS AddSmbiosProcessorAndCacheTables ( VOID )

Add Smbios Cache information (type 7) table and Processor information (type 4) table using the HOB info from Silicon.

Return values
EFI_SUCCESS - Successfully installed SMBIOS cache information and processor information.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbiosProcessorLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SmbiosProcessorLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SmbiosProcessorLib implementation
3
4 INTEL CONFIDENTIAL
5
6 Copyright (c) 2016, - 2020 Intel Corporation. All rights reserved.<BR>
7 This program and the accompanying materials are licensed and made available under
8 the terms and conditions of the BSD License that accompanies this distribution.
9 The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php.
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _SMBIOS_PROCESSOR_LIB_H_
18 #define _SMBIOS_PROCESSOR_LIB_H_
19
20 /**
21 Add Smbios Cache information (type 7) table and Processor information (type 4) table
22 using the HOB info from Silicon.
23
24 @retval EFI_SUCCESS - Successfully installed SMBIOS cache information and processor information.
25 **/
26 EFI_STATUS
27 EFIAPI
28 AddSmbiosProcessorAndCacheTables (
29 VOID
30 );
31
32 #endif // _SMBIOS_PROCESSOR_LIB_H_
AddSmbiosProcessorAndCacheTables
EFI_STATUS AddSmbiosProcessorAndCacheTables(VOID)
Add Smbios Cache information (type 7) table and Processor information (type 4) table using the HOB in...
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbusConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Classes
SmbusConfig.h File Reference

Smbus policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform. More...

Detailed Description

Smbus policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmbusConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbusConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
SmbusConfig.h
Go to the documentation of this file.
1 /** @file
2 Smbus policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SMBUS_CONFIG_H_
36 #define _SMBUS_CONFIG_H_
37
38 #define PCH_SMBUS_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gSmbusPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 #define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
44
45 ///
46 /// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
47 ///
48 typedef struct {
49 /**
50 Revision 1: Init version
51 **/
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 This member describes whether or not the SMBus controller of PCH should be enabled.
55 0: Disable; <b>1: Enable</b>.
56 **/
57 UINT32 Enable : 1;
58 UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
59 UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
60 ///
61 /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
62 /// For security recommendations, SPD write disable bit must be set.
63 ///
64 UINT32 SpdWriteDisable : 1;
65 UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
66 UINT32 RsvdBits0 : 27; ///< Reserved bits
67 UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
68 UINT8 Rsvd0; ///< Reserved bytes
69 UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
70 /**
71 Array of addresses reserved for non-ARP-capable SMBus devices.
72 **/
73 UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
74 } PCH_SMBUS_PREMEM_CONFIG;
75
76 #pragma pack (pop)
77
78 #endif // _SMBUS_CONFIG_H_
PCH_SMBUS_PREMEM_CONFIG::SmbusIoBase
UINT16 SmbusIoBase
SMBUS Base Address (IO space). Default is 0xEFA0.
Definition: SmbusConfig.h:67
PCH_SMBUS_PREMEM_CONFIG
The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
Definition: SmbusConfig.h:48
PCH_SMBUS_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Revision 1: Init version.
Definition: SmbusConfig.h:52
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_SMBUS_PREMEM_CONFIG::SpdWriteDisable
UINT32 SpdWriteDisable
(Test) SPD Write Disable, 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit.
Definition: SmbusConfig.h:64
PCH_SMBUS_PREMEM_CONFIG::Rsvd0
UINT8 Rsvd0
Reserved bytes.
Definition: SmbusConfig.h:68
PCH_SMBUS_PREMEM_CONFIG::DynamicPowerGating
UINT32 DynamicPowerGating
(Test) Disable or Enable Smbus dynamic power gating.
Definition: SmbusConfig.h:59
PCH_SMBUS_PREMEM_CONFIG::SmbAlertEnable
UINT32 SmbAlertEnable
Enable SMBus Alert pin (SMBALERT#). 0: Disabled, 1: Enabled.
Definition: SmbusConfig.h:65
PCH_SMBUS_PREMEM_CONFIG::NumRsvdSmbusAddresses
UINT8 NumRsvdSmbusAddresses
The number of elements in the RsvdSmbusAddressTable.
Definition: SmbusConfig.h:69
PCH_SMBUS_PREMEM_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SmbusConfig.h:66
PCH_SMBUS_PREMEM_CONFIG::Enable
UINT32 Enable
This member describes whether or not the SMBus controller of PCH should be enabled.
Definition: SmbusConfig.h:57
PCH_SMBUS_PREMEM_CONFIG::ArpEnable
UINT32 ArpEnable
Enable SMBus ARP support, 0: Disable; 1: Enable.
Definition: SmbusConfig.h:58
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbusInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SmbusInfoLib.h File Reference

This file provides Smbus public library. More...

Go to the source code of this file.

Functions

UINT8 | SmbusDevNumber (VOID)
Return Smbus Device Number. More...
UINT8 | SmbusFuncNumber (VOID)
Return Smbus Function Number. More...
BOOLEAN | SmbusIsHostLocked (VOID)
This function checks if SMBUS Host Lock is set. More...
VOID | SmbusClearStatusReg (VOID)
This function clears the Smbus Status Register.

Detailed Description

This file provides Smbus public library.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmbusInfoLib.h.

Function Documentation

◆ SmbusDevNumber()

UINT8 SmbusDevNumber ( VOID )

Return Smbus Device Number.

Return values
Smbus Device Number

◆ SmbusFuncNumber()

UINT8 SmbusFuncNumber ( VOID )

Return Smbus Function Number.

Return values
Smbus Function Number

◆ SmbusIsHostLocked()

BOOLEAN SmbusIsHostLocked ( VOID )

This function checks if SMBUS Host Lock is set.

Return values
SMBUS host Hock state
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmbusInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SmbusInfoLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides Smbus public library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SMBUS_INFO_LIB_H_
36 #define _SMBUS_INFO_LIB_H_
37
38 /**
39 Return Smbus Device Number
40
41 @retval Smbus Device Number
42 **/
43 UINT8
44 SmbusDevNumber (
45 VOID
46 );
47
48 /**
49 Return Smbus Function Number
50
51 @retval Smbus Function Number
52 **/
53 UINT8
54 SmbusFuncNumber (
55 VOID
56 );
57
58 /**
59 This function checks if SMBUS Host Lock is set
60
61 @retval SMBUS host Hock state
62 **/
63 BOOLEAN
64 SmbusIsHostLocked (
65 VOID
66 );
67
68 /**
69 This function clears the Smbus Status Register
70 **/
71 VOID
72 SmbusClearStatusReg (
73 VOID
74 );
75
76
77 #endif // _SMBUS_INFO_LIB_H_
SmbusFuncNumber
UINT8 SmbusFuncNumber(VOID)
Return Smbus Function Number.
SmbusIsHostLocked
BOOLEAN SmbusIsHostLocked(VOID)
This function checks if SMBUS Host Lock is set.
SmbusDevNumber
UINT8 SmbusDevNumber(VOID)
Return Smbus Device Number.
SmbusClearStatusReg
VOID SmbusClearStatusReg(VOID)
This function clears the Smbus Status Register.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmControl.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Typedefs
SmmControl.h File Reference

EFI SMM Control PPI definition. More...

Go to the source code of this file.

Classes

struct _PEI_SMM_CONTROL_PPI
PEI SMM Control PPI is used to initiate SMI/PMI activations. More...

Typedefs

typedef EFI_STATUS(* | PEI_SMM_ACTIVATE) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN OUT INT8 *ArgumentBuffer OPTIONAL, IN OUT UINTN *ArgumentBufferSize OPTIONAL, IN BOOLEAN Periodic OPTIONAL, IN UINTN ActivationInterval OPTIONAL)
Invokes SMI activation from either the preboot or runtime environment. More...
typedef EFI_STATUS(* | PEI_SMM_DEACTIVATE) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN BOOLEAN Periodic OPTIONAL)
Clears any system state that was created in response to the Active call. More...

Detailed Description

EFI SMM Control PPI definition.

This PPI is used to initiate SMI/PMI activations. This protocol could be published by either:

  • A processor driver to abstract the SMI/PMI IPI
  • The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an Intel chipset Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based systems.
Copyright
INTEL CONFIDENTIAL Copyright (c) 2010, - 2020 Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file SmmControl.h.

Typedef Documentation

◆ PEI_SMM_ACTIVATE

typedef EFI_STATUS( * PEI_SMM_ACTIVATE) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN OUT INT8 *ArgumentBuffer OPTIONAL, IN OUT UINTN *ArgumentBufferSize OPTIONAL, IN BOOLEAN Periodic OPTIONAL, IN UINTN ActivationInterval OPTIONAL)

Invokes SMI activation from either the preboot or runtime environment.

Parameters
PeiServices | General purpose services available to every PEIM.
This | The PEI_SMM_CONTROL_PPI instance.
ArgumentBuffer | The optional sized data to pass into the protocol activation.
ArgumentBufferSize | The optional size of the data.
Periodic | An optional mechanism to periodically repeat activation.
ActivationInterval | An optional parameter to repeat at this period one time or, if the Periodic Boolean is set, periodically.
Return values
EFI_SUCCESS | The SMI/PMI has been engendered.
EFI_DEVICE_ERROR | The timing is unsupported.
EFI_INVALID_PARAMETER | The activation period is unsupported.
EFI_NOT_STARTED | The SMM base service has not been initialized.

Definition at line 54 of file SmmControl.h.

◆ PEI_SMM_DEACTIVATE

typedef EFI_STATUS( * PEI_SMM_DEACTIVATE) (IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN BOOLEAN Periodic OPTIONAL)

Clears any system state that was created in response to the Active call.

Parameters
PeiServices | General purpose services available to every PEIM.
This | The PEI_SMM_CONTROL_PPI instance.
Periodic | Optional parameter to repeat at this period one time or, if the Periodic Boolean is set, periodically.
Return values
EFI_SUCCESS | The SMI/PMI has been engendered.
EFI_DEVICE_ERROR | The source could not be cleared.
EFI_INVALID_PARAMETER | The service did not support the Periodic input argument.

Definition at line 78 of file SmmControl.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmControl.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
SmmControl.h
Go to the documentation of this file.
1 /** @file
2 EFI SMM Control PPI definition.
3
4 This PPI is used to initiate SMI/PMI activations. This protocol could be published by either:
5 - A processor driver to abstract the SMI/PMI IPI
6 - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
7 Intel chipset
8 Because of the possibility of performing SMI or PMI IPI transactions, the ability to generate this
9 event from a platform chipset agent is an optional capability for both IA-32 and Itanium-based
10 systems.
11
12 @copyright
13 INTEL CONFIDENTIAL
14 Copyright (c) 2010, - 2020 Intel Corporation. All rights reserved.<BR>
15
16 This program and the accompanying materials
17 are licensed and made available under the terms and conditions
18 of the BSD License which accompanies this distribution. The
19 full text of the license may be found at
20 http://opensource.org/licenses/bsd-license.php
21
22 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
23 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
24
25 **/
26
27
28 #ifndef _SMM_CONTROL_PPI_H_
29 #define _SMM_CONTROL_PPI_H_
30
31 #define PEI_SMM_CONTROL_PPI_GUID \
32 { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0xc5 }
33
34 typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI;
35
36 /**
37 Invokes SMI activation from either the preboot or runtime environment.
38
39 @param PeiServices General purpose services available to every PEIM.
40 @param This The PEI_SMM_CONTROL_PPI instance.
41 @param ArgumentBuffer The optional sized data to pass into the protocol activation.
42 @param ArgumentBufferSize The optional size of the data.
43 @param Periodic An optional mechanism to periodically repeat activation.
44 @param ActivationInterval An optional parameter to repeat at this period one
45 time or, if the Periodic Boolean is set, periodically.
46
47 @retval EFI_SUCCESS The SMI/PMI has been engendered.
48 @retval EFI_DEVICE_ERROR The timing is unsupported.
49 @retval EFI_INVALID_PARAMETER The activation period is unsupported.
50 @retval EFI_NOT_STARTED The SMM base service has not been initialized.
51
52 **/
53 typedef
54 EFI_STATUS
55 (EFIAPI *PEI_SMM_ACTIVATE) (
56 IN EFI_PEI_SERVICES **PeiServices,
57 IN PEI_SMM_CONTROL_PPI * This,
58 IN OUT INT8 *ArgumentBuffer OPTIONAL,
59 IN OUT UINTN *ArgumentBufferSize OPTIONAL,
60 IN BOOLEAN Periodic OPTIONAL,
61 IN UINTN ActivationInterval OPTIONAL
62 );
63
64 /**
65 Clears any system state that was created in response to the Active call.
66
67 @param PeiServices General purpose services available to every PEIM.
68 @param This The PEI_SMM_CONTROL_PPI instance.
69 @param Periodic Optional parameter to repeat at this period one
70 time or, if the Periodic Boolean is set, periodically.
71
72 @retval EFI_SUCCESS The SMI/PMI has been engendered.
73 @retval EFI_DEVICE_ERROR The source could not be cleared.
74 @retval EFI_INVALID_PARAMETER The service did not support the Periodic input argument.
75
76 **/
77 typedef
78 EFI_STATUS
79 (EFIAPI *PEI_SMM_DEACTIVATE) (
80 IN EFI_PEI_SERVICES **PeiServices,
81 IN PEI_SMM_CONTROL_PPI * This,
82 IN BOOLEAN Periodic OPTIONAL
83 );
84
85 ///
86 /// PEI SMM Control PPI is used to initiate SMI/PMI activations. This protocol could be published by either:
87 /// - A processor driver to abstract the SMI/PMI IPI
88 /// - The driver that abstracts the ASIC that is supporting the APM port, such as the ICH in an
89 /// Intel chipset
90 ///
91 struct _PEI_SMM_CONTROL_PPI {
92 PEI_SMM_ACTIVATE Trigger;
93 PEI_SMM_DEACTIVATE Clear;
94 };
95
96 extern EFI_GUID gEfiPeiMmControlPpiGuid;
97
98 #endif
PEI_SMM_ACTIVATE
EFI_STATUS(* PEI_SMM_ACTIVATE)(IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN OUT INT8 *ArgumentBuffer OPTIONAL, IN OUT UINTN *ArgumentBufferSize OPTIONAL, IN BOOLEAN Periodic OPTIONAL, IN UINTN ActivationInterval OPTIONAL)
Invokes SMI activation from either the preboot or runtime environment.
Definition: SmmControl.h:55
PEI_SMM_DEACTIVATE
EFI_STATUS(* PEI_SMM_DEACTIVATE)(IN EFI_PEI_SERVICES **PeiServices, IN PEI_SMM_CONTROL_PPI *This, IN BOOLEAN Periodic OPTIONAL)
Clears any system state that was created in response to the Active call.
Definition: SmmControl.h:79
_PEI_SMM_CONTROL_PPI
PEI SMM Control PPI is used to initiate SMI/PMI activations.
Definition: SmmControl.h:91
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmResourceConfigProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
Classes | Typedefs
SmmResourceConfigProtocol.h File Reference

Protocol used for Configuring SMM Resources (IO / MSR) More...

Go to the source code of this file.

Classes

struct | SMM_RESOURCE_CONFIG_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the CPU drivers will use to configure IO ports & MSR registers access with in SMM. More...
struct | SPS_RING3_EXCEPTION_HANDLER
The protocol allows to handle OEM Ring-3 Exceptions. More...

Typedefs

typedef EFI_STATUS(* | SMM_CONFIG_IO_BITMAP) (IN UINT16 PortBase, IN UINT16 PortLength, IN BOOLEAN DenyRwAccess)
This function configures IO port access through bitmap for all CPUs within SMM. More...
typedef EFI_STATUS(* | SMM_CONFIG_MSR_BITMAP) (IN UINT32 Msr, IN BOOLEAN DenyReadAccess, IN BOOLEAN DenyWriteAccess)
This function configures MSR access through bitmap for all CPUs within SMM. More...
typedef EFI_STATUS(* | SMM_INSTALL_IO_BITMAP) (IN UINTN *Buffer, IN UINT16 BufferLength)
This function allows a caller to install new IO Bitmap on top of the default IO Bitmap. More...
typedef EFI_STATUS(* | SMM_INSTALL_MSR_BITMAP) (IN UINTN *Buffer, IN UINT16 BufferLength)
This function allows a caller to install new MSR Bitmap on top of the default MSR Bitmap. More...
typedef EFI_STATUS(* | EXCEPTION_HANDLER) (IN CONST EFI_EXCEPTION_TYPE InterruptType, IN CONST EFI_SYSTEM_CONTEXT SystemContext)
Function for OEM Ring-3 Exception Handler. More...

Detailed Description

Protocol used for Configuring SMM Resources (IO / MSR)

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2020 Intel Corporation

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file SmmResourceConfigProtocol.h.

Typedef Documentation

◆ EXCEPTION_HANDLER

typedef EFI_STATUS( * EXCEPTION_HANDLER) (IN CONST EFI_EXCEPTION_TYPE InterruptType, IN CONST EFI_SYSTEM_CONTEXT SystemContext)

Function for OEM Ring-3 Exception Handler.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
Return values
EFI_SUCCESS Ring-3 Exception Handling is successful.

Definition at line 163 of file SmmResourceConfigProtocol.h.

◆ SMM_CONFIG_IO_BITMAP

typedef EFI_STATUS( * SMM_CONFIG_IO_BITMAP) (IN UINT16 PortBase, IN UINT16 PortLength, IN BOOLEAN DenyRwAccess)

This function configures IO port access through bitmap for all CPUs within SMM.

ie Using this API, IO port can be configured as read write access or restricted access within SMM. For example: To deny access to IO port 0xCF8 to 0xCFB, invoke this API with PortBase = 0xCF8, PortLength = 4 and DenyRwAccess = TRUE

Parameters
[in] | PortBase | IO Port base address.
[in] | PortLength | Length of IO Port bitmap that needs access configuration.
[in] | DenyRwAccess | 0 = Allow RW Access to port; 1 = Deny RW Access to port.
Return values
EFI_SUCCESS Successfully enabled protection for specified IO range.

Definition at line 54 of file SmmResourceConfigProtocol.h.

◆ SMM_CONFIG_MSR_BITMAP

typedef EFI_STATUS( * SMM_CONFIG_MSR_BITMAP) (IN UINT32 Msr, IN BOOLEAN DenyReadAccess, IN BOOLEAN DenyWriteAccess)

This function configures MSR access through bitmap for all CPUs within SMM.

Using this API, any MSR can be configured as Read only, Write only, Read/Write or no access with in SMM.

For example: To configure MSR 0xE2, Invoke this API with MSR = 0xE2 and

Case1: To revoke both read and write access DenyReadAccess = TRUE, DenyWriteAccess = TRUE.

Case2: To revoke read access and allow Write access DenyReadAccess = TRUE, DenyWriteAccess = FALSE.

Case3: To allow read access and revoke write access DenyReadAccess = FALSE, DenyWriteAccess = TRUE.

Case4: To allow both read and Write access DenyReadAccess = FALSE, DenyWriteAccess = FALSE.

DGR reference code allows access for only specified MSRs and denies access to rest of all MSRs. Refer mAllowedListMsr table structure at Intel<Platform Sample Pkg>\Features\NiftyRock\PpamPlatformSmm\SmmIoMsrAccess.h for list of MSRs allowed for R/W access.

OEM platform SMM driver can use this API to modify access to any MSR before SMM End of Dxe event (gEfiSmmEndOfDxeProtocolGuid).

Parameters
[in] | Msr | MSR base address.
[in] | DenyReadAccess | FALSE - Allow read access, TRUE - Deny read access to MSR.
[in] | DenyWriteAccess | FALSE - Allow write access, TRUE - Deny write access to MSR.
Return values
EFI_SUCCESS | MSR Bitmap has been successfully configured.
EFI_INVALID_PARAMETER | If MSR is not in the range of 0 to 0x1FFF and 0xC0000000 to 0xC0001FFF.
EFI_ACCESS_DENIED | If this protocol is invoked after SMM End of Dxe event.

Definition at line 99 of file SmmResourceConfigProtocol.h.

◆ SMM_INSTALL_IO_BITMAP

typedef EFI_STATUS( * SMM_INSTALL_IO_BITMAP) (IN UINTN *Buffer, IN UINT16 BufferLength)

This function allows a caller to install new IO Bitmap on top of the default IO Bitmap.

Parameters
[in] | Buffer | Buffer address of IO Bitmap.
[in] | BufferLength | Length of the buffer. This should be 0x2000.
Return values
EFI_SUCCESS | IO bitmap has been successfully installed.
EFI_INVALID_PARAMETER | If Buffer length is not equal to 0x2000 (8KB).
EFI_ACCESS_DENIED | If this protocol is invoked after SMM End of Dxe event.

Definition at line 118 of file SmmResourceConfigProtocol.h.

◆ SMM_INSTALL_MSR_BITMAP

typedef EFI_STATUS( * SMM_INSTALL_MSR_BITMAP) (IN UINTN *Buffer, IN UINT16 BufferLength)

This function allows a caller to install new MSR Bitmap on top of the default MSR Bitmap.

Parameters
[in] | Buffer | Buffer address of IO Bitmap.
[in] | BufferLength | Length of the buffer. This should be 0x1000.
Return values
EFI_SUCCESS | MSR bitmap has been successfully installed.
EFI_INVALID_PARAMETER | If Buffer length is not equal to 0x1000 (4KB).
EFI_ACCESS_DENIED | If this protocol is invoked after SMM End of Dxe event.

Definition at line 136 of file SmmResourceConfigProtocol.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmResourceConfigProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
SmmResourceConfigProtocol.h
Go to the documentation of this file.
1 /** @file
2 Protocol used for Configuring SMM Resources (IO / MSR)
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2020 Intel Corporation
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _SMM_RESOURCE_CONFIG_PROTOCOL_H_
36 #define _SMM_RESOURCE_CONFIG_PROTOCOL_H_
37
38 extern EFI_GUID gSmmResourceConfigProtocolGuid;
39
40 /**
41 This function configures IO port access through bitmap for all CPUs within SMM.
42 ie Using this API, IO port can be configured as read write access or restricted access
43 within SMM.
44 For example: To deny access to IO port 0xCF8 to 0xCFB, invoke this API with
45 PortBase = 0xCF8, PortLength = 4 and DenyRwAccess = TRUE
46
47 @param[in] PortBase IO Port base address.
48 @param[in] PortLength Length of IO Port bitmap that needs access configuration.
49 @param[in] DenyRwAccess 0 = Allow RW Access to port; 1 = Deny RW Access to port.
50
51 @retval EFI_SUCCESS Successfully enabled protection for specified IO range.
52 **/
53 typedef
54 EFI_STATUS
55 (EFIAPI *SMM_CONFIG_IO_BITMAP) (
56 IN UINT16 PortBase,
57 IN UINT16 PortLength,
58 IN BOOLEAN DenyRwAccess
59 );
60
61 /**
62 This function configures MSR access through bitmap for all CPUs within SMM.
63 Using this API, any MSR can be configured as Read only, Write only, Read/Write
64 or no access with in SMM.
65
66 For example:
67 To configure MSR 0xE2, Invoke this API with MSR = 0xE2 and
68
69 Case1: To revoke both read and write access
70 DenyReadAccess = TRUE, DenyWriteAccess = TRUE.
71
72 Case2: To revoke read access and allow Write access
73 DenyReadAccess = TRUE, DenyWriteAccess = FALSE.
74
75 Case3: To allow read access and revoke write access
76 DenyReadAccess = FALSE, DenyWriteAccess = TRUE.
77
78 Case4: To allow both read and Write access
79 DenyReadAccess = FALSE, DenyWriteAccess = FALSE.
80
81 DGR reference code allows access for only specified MSRs and denies
82 access to rest of all MSRs. Refer mAllowedListMsr table structure at
83 Intel<Platform Sample Pkg>\Features\NiftyRock\PpamPlatformSmm\SmmIoMsrAccess.h for
84 list of MSRs allowed for R/W access.
85
86 OEM platform SMM driver can use this API to modify access to any MSR before
87 SMM End of Dxe event (gEfiSmmEndOfDxeProtocolGuid).
88
89 @param[in] Msr MSR base address.
90 @param[in] DenyReadAccess FALSE - Allow read access, TRUE - Deny read access to MSR.
91 @param[in] DenyWriteAccess FALSE - Allow write access, TRUE - Deny write access to MSR.
92
93 @retval EFI_SUCCESS MSR Bitmap has been successfully configured.
94 @retval EFI_INVALID_PARAMETER If MSR is not in the range of 0 to 0x1FFF and
95 0xC0000000 to 0xC0001FFF.
96 @retval EFI_ACCESS_DENIED If this protocol is invoked after SMM End of Dxe event.
97 **/
98 typedef
99 EFI_STATUS
100 (EFIAPI *SMM_CONFIG_MSR_BITMAP) (
101 IN UINT32 Msr,
102 IN BOOLEAN DenyReadAccess,
103 IN BOOLEAN DenyWriteAccess
104 );
105
106 /**
107 This function allows a caller to install new IO Bitmap on top of the
108 default IO Bitmap.
109
110 @param[in] Buffer Buffer address of IO Bitmap.
111 @param[in] BufferLength Length of the buffer. This should be 0x2000.
112
113 @retval EFI_SUCCESS IO bitmap has been successfully installed.
114 @retval EFI_INVALID_PARAMETER If Buffer length is not equal to 0x2000 (8KB).
115 @retval EFI_ACCESS_DENIED If this protocol is invoked after SMM End of Dxe event.
116 **/
117 typedef
118 EFI_STATUS
119 (EFIAPI *SMM_INSTALL_IO_BITMAP) (
120 IN UINTN *Buffer,
121 IN UINT16 BufferLength
122 );
123
124 /**
125 This function allows a caller to install new MSR Bitmap on top of the
126 default MSR Bitmap.
127
128 @param[in] Buffer Buffer address of IO Bitmap.
129 @param[in] BufferLength Length of the buffer. This should be 0x1000.
130
131 @retval EFI_SUCCESS MSR bitmap has been successfully installed.
132 @retval EFI_INVALID_PARAMETER If Buffer length is not equal to 0x1000 (4KB).
133 @retval EFI_ACCESS_DENIED If this protocol is invoked after SMM End of Dxe event.
134 **/
135 typedef
136 EFI_STATUS
137 (EFIAPI *SMM_INSTALL_MSR_BITMAP) (
138 IN UINTN *Buffer,
139 IN UINT16 BufferLength
140 );
141
142 /**
143 The protocol allows the platform code to publish a set of configuration information that the
144 CPU drivers will use to configure IO ports & MSR registers access with in SMM.
145 **/
146 typedef struct {
147 SMM_CONFIG_IO_BITMAP SmmConfigIoBitmap;
148 SMM_CONFIG_MSR_BITMAP SmmConfigMsrBitmap;
149 SMM_INSTALL_IO_BITMAP InstallIoBitmap;
150 SMM_INSTALL_MSR_BITMAP InstallMsrBitmap;
151 } SMM_RESOURCE_CONFIG_PROTOCOL;
152
153
154 /**
155 Function for OEM Ring-3 Exception Handler
156
157 @param[in] InterruptType Defines which interrupt or exception to hook.
158 @param[in] SystemContext Pointer to EFI_SYSTEM_CONTEXT.
159
160 @retval EFI_SUCCESS Ring-3 Exception Handling is successful.
161 **/
162 typedef
163 EFI_STATUS
164 (EFIAPI *EXCEPTION_HANDLER) (
165 IN CONST EFI_EXCEPTION_TYPE InterruptType,
166 IN CONST EFI_SYSTEM_CONTEXT SystemContext
167 );
168
169 /**
170 The protocol allows to handle OEM Ring-3 Exceptions.
171 **/
172 typedef struct {
173 EXCEPTION_HANDLER SpsRing3ExceptionHandler;
174 } SPS_RING3_EXCEPTION_HANDLER;
175
176 #endif
SMM_CONFIG_MSR_BITMAP
EFI_STATUS(* SMM_CONFIG_MSR_BITMAP)(IN UINT32 Msr, IN BOOLEAN DenyReadAccess, IN BOOLEAN DenyWriteAccess)
This function configures MSR access through bitmap for all CPUs within SMM.
Definition: SmmResourceConfigProtocol.h:100
SMM_INSTALL_MSR_BITMAP
EFI_STATUS(* SMM_INSTALL_MSR_BITMAP)(IN UINTN *Buffer, IN UINT16 BufferLength)
This function allows a caller to install new MSR Bitmap on top of the default MSR Bitmap.
Definition: SmmResourceConfigProtocol.h:137
SPS_RING3_EXCEPTION_HANDLER
The protocol allows to handle OEM Ring-3 Exceptions.
Definition: SmmResourceConfigProtocol.h:172
SMM_INSTALL_IO_BITMAP
EFI_STATUS(* SMM_INSTALL_IO_BITMAP)(IN UINTN *Buffer, IN UINT16 BufferLength)
This function allows a caller to install new IO Bitmap on top of the default IO Bitmap.
Definition: SmmResourceConfigProtocol.h:119
SMM_CONFIG_IO_BITMAP
EFI_STATUS(* SMM_CONFIG_IO_BITMAP)(IN UINT16 PortBase, IN UINT16 PortLength, IN BOOLEAN DenyRwAccess)
This function configures IO port access through bitmap for all CPUs within SMM.
Definition: SmmResourceConfigProtocol.h:55
EXCEPTION_HANDLER
EFI_STATUS(* EXCEPTION_HANDLER)(IN CONST EFI_EXCEPTION_TYPE InterruptType, IN CONST EFI_SYSTEM_CONTEXT SystemContext)
Function for OEM Ring-3 Exception Handler.
Definition: SmmResourceConfigProtocol.h:164
SMM_RESOURCE_CONFIG_PROTOCOL
The protocol allows the platform code to publish a set of configuration information that the CPU driv...
Definition: SmmResourceConfigProtocol.h:146
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmSmbus.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
SmmSmbus.h File Reference

SmmSmbus Protocol. More...

Go to the source code of this file.

Detailed Description

SmmSmbus Protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2009 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmmSmbus.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmSmbus.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
SmmSmbus.h
Go to the documentation of this file.
1 /** @file
2 SmmSmbus Protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2009 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef __EFI_SMM_SMBUS_PROTOCOL_H__
36 #define __EFI_SMM_SMBUS_PROTOCOL_H__
37
38 extern EFI_GUID gEfiSmmSmbusProtocolGuid;
39
40 #endif
41
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmSpaLogOutputProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
SmmSpaLogOutputProtocol.h File Reference

This header file contains SPA log Output Protocol Interface. More...

Go to the source code of this file.

Detailed Description

This header file contains SPA log Output Protocol Interface.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SmmSpaLogOutputProtocol.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmSpaLogOutputProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
SmmSpaLogOutputProtocol.h
Go to the documentation of this file.
1 /** @file
2 This header file contains SPA log Output Protocol Interface.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef __SMM_SPA_LOG_OUTPUT_PROTOCOL_H__
37 #define __SMM_SPA_LOG_OUTPUT_PROTOCOL_H__
38
39 extern EFI_GUID gEfiSpaLogOutputProtocolGuid;
40
41 typedef struct _EFI_SPA_LOG_OUTPUT_PROTOCOL EFI_SPA_LOG_OUTPUT_PROTOCOL;
42
43 typedef
44 EFI_STATUS
45 (EFIAPI *SPA_LOG_OUTPUT) (
46 IN EFI_SPA_LOG_OUTPUT_PROTOCOL *This,
47 IN CHAR16 *LogString
48 );
49
50 struct _EFI_SPA_LOG_OUTPUT_PROTOCOL {
51 SPA_LOG_OUTPUT SpaLogOutput;
52 };
53
54 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmVariable.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes
SmmVariable.h File Reference

EFI SMM Variable Protocol is related to EDK II-specific implementation of variables and intended for use as a means to store data in the EFI SMM environment. More...

Go to the source code of this file.

Classes

struct _EFI_SMM_VARIABLE_PROTOCOL
EFI SMM Variable Protocol is intended for use as a means to store data in the EFI SMM environment. More...

Detailed Description

EFI SMM Variable Protocol is related to EDK II-specific implementation of variables and intended for use as a means to store data in the EFI SMM environment.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2010, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file SmmVariable.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SmmVariable.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
SmmVariable.h
Go to the documentation of this file.
1 /** @file
2 EFI SMM Variable Protocol is related to EDK II-specific implementation of variables
3 and intended for use as a means to store data in the EFI SMM environment.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
8 This program and the accompanying materials
9 are licensed and made available under the terms and conditions of the BSD License
10 which accompanies this distribution. The full text of the license may be found at
11 http://opensource.org/licenses/bsd-license.php
12
13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15
16 **/
17
18 #ifndef __SMM_VARIABLE_H__
19 #define __SMM_VARIABLE_H__
20
21 #define EFI_SMM_VARIABLE_PROTOCOL_GUID \
22 { \
23 0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7 } \
24 }
25
26 typedef struct _EFI_SMM_VARIABLE_PROTOCOL EFI_SMM_VARIABLE_PROTOCOL;
27
28 ///
29 /// EFI SMM Variable Protocol is intended for use as a means
30 /// to store data in the EFI SMM environment.
31 ///
32 struct _EFI_SMM_VARIABLE_PROTOCOL {
33 EFI_GET_VARIABLE SmmGetVariable;
34 EFI_GET_NEXT_VARIABLE_NAME SmmGetNextVariableName;
35 EFI_SET_VARIABLE SmmSetVariable;
36 EFI_QUERY_VARIABLE_INFO SmmQueryVariableInfo;
37 };
38
39 extern EFI_GUID gEfiSmmVariableProtocolGuid;
40
41 #endif
_EFI_SMM_VARIABLE_PROTOCOL
EFI SMM Variable Protocol is intended for use as a means to store data in the EFI SMM environment.
Definition: SmmVariable.h:32
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Spi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Typedefs
Ppi/Spi.h File Reference

This file defines the PCH SPI PPI which implements the Intel(R) PCH SPI Host Controller Compatibility Interface. More...

#include <Protocol/Spi.h>
Include dependency graph for Ppi/Spi.h:

Go to the source code of this file.

Typedefs

typedef PCH_SPI_PROTOCOL PCH_SPI_PPI
Reuse the PCH_SPI_PROTOCOL definitions This is possible becaues the PPI implementation does not rely on a PeiService pointer, as it uses EDKII Glue Lib to do IO accesses.

Detailed Description

This file defines the PCH SPI PPI which implements the Intel(R) PCH SPI Host Controller Compatibility Interface.

Note
The APIs in this file are designed to be backward compatible with previous versions. Any change in behavior of these APIs will result in newer version of the API.
Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Ppi/Spi.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Spi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi/Spi.h
Go to the documentation of this file.
1 /** @file
2 This file defines the PCH SPI PPI which implements the
3 Intel(R) PCH SPI Host Controller Compatibility Interface.
4
5 @note The APIs in this file are designed to be backward compatible with
6 previous versions. Any change in behavior of these APIs will result in
7 newer version of the API.
8
9 @copyright
10 INTEL CONFIDENTIAL
11 Copyright 2006 - 2020 Intel Corporation.
12
13 The source code contained or described herein and all documents related to the
14 source code ("Material") are owned by Intel Corporation or its suppliers or
15 licensors. Title to the Material remains with Intel Corporation or its suppliers
16 and licensors. The Material may contain trade secrets and proprietary and
17 confidential information of Intel Corporation and its suppliers and licensors,
18 and is protected by worldwide copyright and trade secret laws and treaty
19 provisions. No part of the Material may be used, copied, reproduced, modified,
20 published, uploaded, posted, transmitted, distributed, or disclosed in any way
21 without Intel's prior express written permission.
22
23 No license under any patent, copyright, trade secret or other intellectual
24 property right is granted to or conferred upon you by disclosure or delivery
25 of the Materials, either expressly, by implication, inducement, estoppel or
26 otherwise. Any license under such intellectual property rights must be
27 express and approved by Intel in writing.
28
29 Unless otherwise agreed by Intel in writing, you may not remove or alter
30 this notice or any other notice embedded in Materials by Intel or
31 Intel's suppliers or licensors in any way.
32
33 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
34 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
35 the terms of your license agreement with Intel or your vendor. This file may
36 be modified by the user, subject to additional terms of the license agreement.
37
38 @par Specification Reference:
39 **/
40 #ifndef _PCH_SPI_PPI_H_
41 #define _PCH_SPI_PPI_H_
42
43 #include <Protocol/Spi.h>
44
45 //
46 // Extern the GUID for PPI users.
47 //
48 extern EFI_GUID gPchSpiPpiGuid;
49
50 /**
51 Reuse the PCH_SPI_PROTOCOL definitions
52 This is possible becaues the PPI implementation does not rely on a PeiService pointer,
53 as it uses EDKII Glue Lib to do IO accesses
54 **/
55 typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
56
57 #endif
Spi.h
This file defines the PCH SPI Protocol which implements the Intel(R) PCH SPI Host Controller Compatib...
PCH_SPI_PPI
PCH_SPI_PROTOCOL PCH_SPI_PPI
Reuse the PCH_SPI_PROTOCOL definitions This is possible becaues the PPI implementation does not rely ...
Definition: Ppi/Spi.h:55
_PCH_SPI_PROTOCOL
These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host...
Definition: Protocol/Spi.h:349
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Spi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Macros | Typedefs | Enumerations
Protocol/Spi.h File Reference

This file defines the PCH SPI Protocol which implements the Intel(R) PCH SPI Host Controller Compatibility Interface. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _PCH_SPI_PROTOCOL
These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host Controller Interface. More...

Macros

#define PCH_SPI_SERVICES_REVISION 1
PCH SPI PPI/PROTOCOL revision number. More...

Typedefs

typedef EFI_STATUS(* | PCH_SPI_FLASH_READ) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *Buffer)
Read data from the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_WRITE) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, IN UINT8 *Buffer)
Write data to the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_ERASE) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount)
Erase area on the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_READ_SFDP) (IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *SfdpData)
Read SFDP data from the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_READ_JEDEC_ID) (IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 ByteCount, OUT UINT8 *JedecId)
Read Jedec Id from the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_WRITE_STATUS) (IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, IN UINT8 *StatusValue)
Write the status register in the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_FLASH_READ_STATUS) (IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, OUT UINT8 *StatusValue)
Read status register in the flash part. More...
typedef EFI_STATUS(* | PCH_SPI_GET_REGION_ADDRESS) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, OUT UINT32 *BaseAddress, OUT UINT32 *RegionSize)
Get the SPI region base and size, based on the enum type. More...
typedef EFI_STATUS(* | PCH_SPI_READ_PCH_SOFTSTRAP) (IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)
Read PCH Soft Strap Values. More...
typedef EFI_STATUS(* | PCH_SPI_READ_CPU_SOFTSTRAP) (IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)
Read CPU Soft Strap Values. More...

Enumerations

enum FLASH_REGION_TYPE
Flash Region Type.

Detailed Description

This file defines the PCH SPI Protocol which implements the Intel(R) PCH SPI Host Controller Compatibility Interface.

Note
The APIs in this file are designed to be backward compatible with previous versions. Any change in behavior of these APIs will result in newer version of the API.
Copyright
INTEL CONFIDENTIAL Copyright 2006 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Protocol/Spi.h.

Macro Definition Documentation

◆ PCH_SPI_SERVICES_REVISION

#define PCH_SPI_SERVICES_REVISION 1

PCH SPI PPI/PROTOCOL revision number.

Revision 1: Initial version

Definition at line 372 of file Protocol/Spi.h.

Typedef Documentation

◆ PCH_SPI_FLASH_ERASE

typedef EFI_STATUS( * PCH_SPI_FLASH_ERASE) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount)

Erase area on the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | FlashRegionType | The Flash Region type for flash cycle which is listed in the Descriptor.
[in] | Address | The Flash Linear Address must fall within a region for which BIOS has access permissions.
[in] | ByteCount | Number of bytes in the data portion of the SPI cycle.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 160 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_READ

typedef EFI_STATUS( * PCH_SPI_FLASH_READ) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *Buffer)

Read data from the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | FlashRegionType | The Flash Region type for flash cycle which is listed in the Descriptor.
[in] | Address | The Flash Linear Address must fall within a region for which BIOS has access permissions.
[in] | ByteCount | Number of bytes in the data portion of the SPI cycle.
[out] | Buffer | The Pointer to caller-allocated buffer containing the dada received. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 107 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_READ_JEDEC_ID

typedef EFI_STATUS( * PCH_SPI_FLASH_READ_JEDEC_ID) (IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 ByteCount, OUT UINT8 *JedecId)

Read Jedec Id from the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | ComponentNumber | The Componen Number for chip select
[in] | ByteCount | Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
[out] | JedecId | The Pointer to caller-allocated buffer containing JEDEC ID received. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 214 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_READ_SFDP

typedef EFI_STATUS( * PCH_SPI_FLASH_READ_SFDP) (IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *SfdpData)

Read SFDP data from the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | ComponentNumber | The Componen Number for chip select
[in] | Address | The starting byte address for SFDP data read.
[in] | ByteCount | Number of bytes in SFDP data portion of the SPI cycle
[out] | SfdpData | The Pointer to caller-allocated buffer containing the SFDP data received It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 187 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_READ_STATUS

typedef EFI_STATUS( * PCH_SPI_FLASH_READ_STATUS) (IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, OUT UINT8 *StatusValue)

Read status register in the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | ByteCount | Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
[out] | StatusValue | The Pointer to caller-allocated buffer containing the value of Status register received.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 257 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_WRITE

typedef EFI_STATUS( * PCH_SPI_FLASH_WRITE) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, IN UINT8 *Buffer)

Write data to the flash part.

Remark: Erase may be needed before write to the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | FlashRegionType | The Flash Region type for flash cycle which is listed in the Descriptor.
[in] | Address | The Flash Linear Address must fall within a region for which BIOS has access permissions.
[in] | ByteCount | Number of bytes in the data portion of the SPI cycle.
[in] | Buffer | Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 135 of file Protocol/Spi.h.

◆ PCH_SPI_FLASH_WRITE_STATUS

typedef EFI_STATUS( * PCH_SPI_FLASH_WRITE_STATUS) (IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, IN UINT8 *StatusValue)

Write the status register in the flash part.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | ByteCount | Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
[in] | StatusValue | The Pointer to caller-allocated buffer containing the value of Status register writing
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 236 of file Protocol/Spi.h.

◆ PCH_SPI_GET_REGION_ADDRESS

typedef EFI_STATUS( * PCH_SPI_GET_REGION_ADDRESS) (IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, OUT UINT32 *BaseAddress, OUT UINT32 *RegionSize)

Get the SPI region base and size, based on the enum type.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | FlashRegionType | The Flash Region type for for the base address which is listed in the Descriptor.
[out] | BaseAddress | The Flash Linear Address for the Region 'n' Base
[out] | RegionSize | The size for the Region 'n'
Return values
EFI_SUCCESS | Read success
EFI_INVALID_PARAMETER | Invalid region type given
EFI_DEVICE_ERROR | The region is not used

Definition at line 279 of file Protocol/Spi.h.

◆ PCH_SPI_READ_CPU_SOFTSTRAP

typedef EFI_STATUS( * PCH_SPI_READ_CPU_SOFTSTRAP) (IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)

Read CPU Soft Strap Values.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | SoftStrapAddr | CPU Soft Strap address offset from FCPUSBA.
[in] | ByteCount | Number of bytes in SoftStrap data portion of the SPI cycle.
[out] | SoftStrapValue | The Pointer to caller-allocated buffer containing CPU Soft Strap Value. If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 337 of file Protocol/Spi.h.

◆ PCH_SPI_READ_PCH_SOFTSTRAP

typedef EFI_STATUS( * PCH_SPI_READ_PCH_SOFTSTRAP) (IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)

Read PCH Soft Strap Values.

Parameters
[in] | This | Pointer to the PCH_SPI_PROTOCOL instance.
[in] | SoftStrapAddr | PCH Soft Strap address offset from FPSBA.
[in] | ByteCount | Number of bytes in SoftStrap data portion of the SPI cycle
[out] | SoftStrapValue | The Pointer to caller-allocated buffer containing PCH Soft Strap Value. If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length. It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
Return values
EFI_SUCCESS | Command succeed.
EFI_INVALID_PARAMETER | The parameters specified are not valid.
EFI_DEVICE_ERROR | Device error, command aborts abnormally.

Definition at line 308 of file Protocol/Spi.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Spi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol/Spi.h
Go to the documentation of this file.
1 /** @file
2 This file defines the PCH SPI Protocol which implements the
3 Intel(R) PCH SPI Host Controller Compatibility Interface.
4
5 @note The APIs in this file are designed to be backward compatible with
6 previous versions. Any change in behavior of these APIs will result in
7 newer version of the API.
8
9 @copyright
10 INTEL CONFIDENTIAL
11 Copyright 2006 - 2020 Intel Corporation.
12
13 The source code contained or described herein and all documents related to the
14 source code ("Material") are owned by Intel Corporation or its suppliers or
15 licensors. Title to the Material remains with Intel Corporation or its suppliers
16 and licensors. The Material may contain trade secrets and proprietary and
17 confidential information of Intel Corporation and its suppliers and licensors,
18 and is protected by worldwide copyright and trade secret laws and treaty
19 provisions. No part of the Material may be used, copied, reproduced, modified,
20 published, uploaded, posted, transmitted, distributed, or disclosed in any way
21 without Intel's prior express written permission.
22
23 No license under any patent, copyright, trade secret or other intellectual
24 property right is granted to or conferred upon you by disclosure or delivery
25 of the Materials, either expressly, by implication, inducement, estoppel or
26 otherwise. Any license under such intellectual property rights must be
27 express and approved by Intel in writing.
28
29 Unless otherwise agreed by Intel in writing, you may not remove or alter
30 this notice or any other notice embedded in Materials by Intel or
31 Intel's suppliers or licensors in any way.
32
33 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
34 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
35 the terms of your license agreement with Intel or your vendor. This file may
36 be modified by the user, subject to additional terms of the license agreement.
37
38 @par Specification Reference:
39 **/
40 #ifndef _PCH_SPI_PROTOCOL_H_
41 #define _PCH_SPI_PROTOCOL_H_
42
43 //
44 // Extern the GUID for protocol users.
45 //
46 extern EFI_GUID gPchSpiProtocolGuid;
47 extern EFI_GUID gPchSmmSpiProtocolGuid;
48
49 //
50 // Forward reference for ANSI C compatibility
51 //
52 typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
53
54 //
55 // SPI protocol data structures and definitions
56 //
57
58 /**
59 Flash Region Type
60 **/
61 typedef enum {
62 FlashRegionDescriptor,
63 FlashRegionBios,
64 FlashRegionMe,
65 FlashRegionGbE,
66 FlashRegionPlatformData,
67 FlashRegionDer,
68 FlashRegionSecondaryBios,
69 FlashRegionuCodePatch,
70 FlashRegionEC,
71 FlashRegionDeviceExpansion2,
72 FlashRegionIE,
73 FlashRegion10Gbe_A,
74 FlashRegion10Gbe_B,
75 FlashRegion13,
76 FlashRegion14,
77 FlashRegion15,
78 FlashRegionAll,
79 FlashRegionMax
80 } FLASH_REGION_TYPE;
81
82 //
83 // Protocol member functions
84 //
85
86 /**
87 Read data from the flash part.
88
89 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
90 @param[in] FlashRegionType The Flash Region type for flash cycle which
91 is listed in the Descriptor.
92 @param[in] Address The Flash Linear Address must fall within a
93 region for which BIOS has access permissions.
94 @param[in] ByteCount Number of bytes in the data portion of the
95 SPI cycle.
96 @param[out] Buffer The Pointer to caller-allocated buffer
97 containing the dada received.
98 It is the caller's responsibility to make
99 sure Buffer is large enough for the total
100 number of bytes read.
101
102 @retval EFI_SUCCESS Command succeed.
103 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
104 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
105 **/
106 typedef
107 EFI_STATUS
108 (EFIAPI *PCH_SPI_FLASH_READ) (
109 IN PCH_SPI_PROTOCOL *This,
110 IN FLASH_REGION_TYPE FlashRegionType,
111 IN UINT32 Address,
112 IN UINT32 ByteCount,
113 OUT UINT8 *Buffer
114 );
115
116 /**
117 Write data to the flash part. Remark: Erase may be needed before write to the
118 flash part.
119
120 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
121 @param[in] FlashRegionType The Flash Region type for flash cycle which
122 is listed in the Descriptor.
123 @param[in] Address The Flash Linear Address must fall within a
124 region for which BIOS has access permissions.
125 @param[in] ByteCount Number of bytes in the data portion of the
126 SPI cycle.
127 @param[in] Buffer Pointer to caller-allocated buffer containing
128 the data sent during the SPI cycle.
129
130 @retval EFI_SUCCESS Command succeed.
131 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
132 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
133 **/
134 typedef
135 EFI_STATUS
136 (EFIAPI *PCH_SPI_FLASH_WRITE) (
137 IN PCH_SPI_PROTOCOL *This,
138 IN FLASH_REGION_TYPE FlashRegionType,
139 IN UINT32 Address,
140 IN UINT32 ByteCount,
141 IN UINT8 *Buffer
142 );
143
144 /**
145 Erase area on the flash part.
146
147 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
148 @param[in] FlashRegionType The Flash Region type for flash cycle which
149 is listed in the Descriptor.
150 @param[in] Address The Flash Linear Address must fall within a
151 region for which BIOS has access permissions.
152 @param[in] ByteCount Number of bytes in the data portion of the
153 SPI cycle.
154
155 @retval EFI_SUCCESS Command succeed.
156 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
157 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
158 **/
159 typedef
160 EFI_STATUS
161 (EFIAPI *PCH_SPI_FLASH_ERASE) (
162 IN PCH_SPI_PROTOCOL *This,
163 IN FLASH_REGION_TYPE FlashRegionType,
164 IN UINT32 Address,
165 IN UINT32 ByteCount
166 );
167
168 /**
169 Read SFDP data from the flash part.
170
171 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
172 @param[in] ComponentNumber The Componen Number for chip select
173 @param[in] Address The starting byte address for SFDP data read.
174 @param[in] ByteCount Number of bytes in SFDP data portion of the
175 SPI cycle
176 @param[out] SfdpData The Pointer to caller-allocated buffer
177 containing the SFDP data received
178 It is the caller's responsibility to make
179 sure Buffer is large enough for the total
180 number of bytes read
181
182 @retval EFI_SUCCESS Command succeed.
183 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
184 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
185 **/
186 typedef
187 EFI_STATUS
188 (EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
189 IN PCH_SPI_PROTOCOL *This,
190 IN UINT8 ComponentNumber,
191 IN UINT32 Address,
192 IN UINT32 ByteCount,
193 OUT UINT8 *SfdpData
194 );
195
196 /**
197 Read Jedec Id from the flash part.
198
199 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
200 @param[in] ComponentNumber The Componen Number for chip select
201 @param[in] ByteCount Number of bytes in JedecId data portion of
202 the SPI cycle, the data size is 3 typically
203 @param[out] JedecId The Pointer to caller-allocated buffer
204 containing JEDEC ID received.
205 It is the caller's responsibility to make
206 sure Buffer is large enough for the total
207 number of bytes read.
208
209 @retval EFI_SUCCESS Command succeed.
210 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
211 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
212 **/
213 typedef
214 EFI_STATUS
215 (EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
216 IN PCH_SPI_PROTOCOL *This,
217 IN UINT8 ComponentNumber,
218 IN UINT32 ByteCount,
219 OUT UINT8 *JedecId
220 );
221
222 /**
223 Write the status register in the flash part.
224
225 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
226 @param[in] ByteCount Number of bytes in Status data portion of the
227 SPI cycle, the data size is 1 typically
228 @param[in] StatusValue The Pointer to caller-allocated buffer
229 containing the value of Status register writing
230
231 @retval EFI_SUCCESS Command succeed.
232 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
233 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
234 **/
235 typedef
236 EFI_STATUS
237 (EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
238 IN PCH_SPI_PROTOCOL *This,
239 IN UINT32 ByteCount,
240 IN UINT8 *StatusValue
241 );
242
243 /**
244 Read status register in the flash part.
245
246 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
247 @param[in] ByteCount Number of bytes in Status data portion of the
248 SPI cycle, the data size is 1 typically
249 @param[out] StatusValue The Pointer to caller-allocated buffer
250 containing the value of Status register received.
251
252 @retval EFI_SUCCESS Command succeed.
253 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
254 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
255 **/
256 typedef
257 EFI_STATUS
258 (EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
259 IN PCH_SPI_PROTOCOL *This,
260 IN UINT32 ByteCount,
261 OUT UINT8 *StatusValue
262 );
263
264 /**
265 Get the SPI region base and size, based on the enum type
266
267 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
268 @param[in] FlashRegionType The Flash Region type for for the base address
269 which is listed in the Descriptor.
270 @param[out] BaseAddress The Flash Linear Address for the Region 'n'
271 Base
272 @param[out] RegionSize The size for the Region 'n'
273
274 @retval EFI_SUCCESS Read success
275 @retval EFI_INVALID_PARAMETER Invalid region type given
276 @retval EFI_DEVICE_ERROR The region is not used
277 **/
278 typedef
279 EFI_STATUS
280 (EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
281 IN PCH_SPI_PROTOCOL *This,
282 IN FLASH_REGION_TYPE FlashRegionType,
283 OUT UINT32 *BaseAddress,
284 OUT UINT32 *RegionSize
285 );
286
287 /**
288 Read PCH Soft Strap Values
289
290 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
291 @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
292 @param[in] ByteCount Number of bytes in SoftStrap data portion of
293 the SPI cycle
294 @param[out] SoftStrapValue The Pointer to caller-allocated buffer
295 containing PCH Soft Strap Value.
296 If the value of ByteCount is 0, the data type
297 of SoftStrapValue should be UINT16 and
298 SoftStrapValue will be PCH Soft Strap Length.
299 It is the caller's responsibility to make sure
300 Buffer is large enough for the total number of
301 bytes read.
302
303 @retval EFI_SUCCESS Command succeed.
304 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
305 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
306 **/
307 typedef
308 EFI_STATUS
309 (EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
310 IN PCH_SPI_PROTOCOL *This,
311 IN UINT32 SoftStrapAddr,
312 IN UINT32 ByteCount,
313 OUT VOID *SoftStrapValue
314 );
315
316 /**
317 Read CPU Soft Strap Values
318
319 @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
320 @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
321 @param[in] ByteCount Number of bytes in SoftStrap data portion of
322 the SPI cycle.
323 @param[out] SoftStrapValue The Pointer to caller-allocated buffer
324 containing CPU Soft Strap Value.
325 If the value of ByteCount is 0, the data type
326 of SoftStrapValue should be UINT16 and
327 SoftStrapValue will be PCH Soft Strap Length
328 It is the caller's responsibility to make sure
329 Buffer is large enough for the total number
330 of bytes read.
331
332 @retval EFI_SUCCESS Command succeed.
333 @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
334 @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
335 **/
336 typedef
337 EFI_STATUS
338 (EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
339 IN PCH_SPI_PROTOCOL *This,
340 IN UINT32 SoftStrapAddr,
341 IN UINT32 ByteCount,
342 OUT VOID *SoftStrapValue
343 );
344
345 /**
346 These protocols/PPI allows a platform module to perform SPI operations
347 through the Intel PCH SPI Host Controller Interface.
348 **/
349 struct _PCH_SPI_PROTOCOL {
350 /**
351 This member specifies the revision of this structure. This field is
352 used to indicate backwards compatible changes to the protocol.
353 **/
354 UINT8 Revision;
355 PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
356 PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
357 PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
358 PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
359 PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
360 PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
361 PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
362 PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
363 PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
364 PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
365 };
366
367 /**
368 PCH SPI PPI/PROTOCOL revision number
369
370 Revision 1: Initial version
371 **/
372 #define PCH_SPI_SERVICES_REVISION 1
373
374 #endif
PCH_SPI_READ_CPU_SOFTSTRAP
EFI_STATUS(* PCH_SPI_READ_CPU_SOFTSTRAP)(IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)
Read CPU Soft Strap Values.
Definition: Protocol/Spi.h:338
PCH_SPI_FLASH_READ
EFI_STATUS(* PCH_SPI_FLASH_READ)(IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *Buffer)
Read data from the flash part.
Definition: Protocol/Spi.h:108
PCH_SPI_FLASH_WRITE_STATUS
EFI_STATUS(* PCH_SPI_FLASH_WRITE_STATUS)(IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, IN UINT8 *StatusValue)
Write the status register in the flash part.
Definition: Protocol/Spi.h:237
PCH_SPI_FLASH_WRITE
EFI_STATUS(* PCH_SPI_FLASH_WRITE)(IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount, IN UINT8 *Buffer)
Write data to the flash part.
Definition: Protocol/Spi.h:136
PCH_SPI_FLASH_ERASE
EFI_STATUS(* PCH_SPI_FLASH_ERASE)(IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, IN UINT32 Address, IN UINT32 ByteCount)
Erase area on the flash part.
Definition: Protocol/Spi.h:161
PCH_SPI_FLASH_READ_STATUS
EFI_STATUS(* PCH_SPI_FLASH_READ_STATUS)(IN PCH_SPI_PROTOCOL *This, IN UINT32 ByteCount, OUT UINT8 *StatusValue)
Read status register in the flash part.
Definition: Protocol/Spi.h:258
PCH_SPI_READ_PCH_SOFTSTRAP
EFI_STATUS(* PCH_SPI_READ_PCH_SOFTSTRAP)(IN PCH_SPI_PROTOCOL *This, IN UINT32 SoftStrapAddr, IN UINT32 ByteCount, OUT VOID *SoftStrapValue)
Read PCH Soft Strap Values.
Definition: Protocol/Spi.h:309
FLASH_REGION_TYPE
FLASH_REGION_TYPE
Flash Region Type.
Definition: Protocol/Spi.h:61
_PCH_SPI_PROTOCOL::ReadCpuSoftStrap
PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap
Read CPU Soft Strap Values.
Definition: Protocol/Spi.h:364
_PCH_SPI_PROTOCOL::FlashReadStatus
PCH_SPI_FLASH_READ_STATUS FlashReadStatus
Read status register in the flash part.
Definition: Protocol/Spi.h:361
_PCH_SPI_PROTOCOL::Revision
UINT8 Revision
This member specifies the revision of this structure.
Definition: Protocol/Spi.h:354
_PCH_SPI_PROTOCOL::FlashReadJedecId
PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId
Read Jedec Id from the flash part.
Definition: Protocol/Spi.h:359
_PCH_SPI_PROTOCOL::FlashErase
PCH_SPI_FLASH_ERASE FlashErase
Erase some area on the flash part.
Definition: Protocol/Spi.h:357
_PCH_SPI_PROTOCOL::ReadPchSoftStrap
PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap
Read PCH Soft Strap Values.
Definition: Protocol/Spi.h:363
_PCH_SPI_PROTOCOL::FlashWriteStatus
PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus
Write the status register in the flash part.
Definition: Protocol/Spi.h:360
_PCH_SPI_PROTOCOL::FlashReadSfdp
PCH_SPI_FLASH_READ_SFDP FlashReadSfdp
Read SFDP data from the flash part.
Definition: Protocol/Spi.h:358
PCH_SPI_FLASH_READ_JEDEC_ID
EFI_STATUS(* PCH_SPI_FLASH_READ_JEDEC_ID)(IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 ByteCount, OUT UINT8 *JedecId)
Read Jedec Id from the flash part.
Definition: Protocol/Spi.h:215
_PCH_SPI_PROTOCOL
These protocols/PPI allows a platform module to perform SPI operations through the Intel PCH SPI Host...
Definition: Protocol/Spi.h:349
_PCH_SPI_PROTOCOL::FlashRead
PCH_SPI_FLASH_READ FlashRead
Read data from the flash part.
Definition: Protocol/Spi.h:355
PCH_SPI_GET_REGION_ADDRESS
EFI_STATUS(* PCH_SPI_GET_REGION_ADDRESS)(IN PCH_SPI_PROTOCOL *This, IN FLASH_REGION_TYPE FlashRegionType, OUT UINT32 *BaseAddress, OUT UINT32 *RegionSize)
Get the SPI region base and size, based on the enum type.
Definition: Protocol/Spi.h:280
_PCH_SPI_PROTOCOL::GetRegionAddress
PCH_SPI_GET_REGION_ADDRESS GetRegionAddress
Get the SPI region base and size.
Definition: Protocol/Spi.h:362
_PCH_SPI_PROTOCOL::FlashWrite
PCH_SPI_FLASH_WRITE FlashWrite
Write data to the flash part. Remark: Erase may be needed before write to the flash part.
Definition: Protocol/Spi.h:356
PCH_SPI_FLASH_READ_SFDP
EFI_STATUS(* PCH_SPI_FLASH_READ_SFDP)(IN PCH_SPI_PROTOCOL *This, IN UINT8 ComponentNumber, IN UINT32 Address, IN UINT32 ByteCount, OUT UINT8 *SfdpData)
Read SFDP data from the flash part.
Definition: Protocol/Spi.h:188
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SpiAccessLib.h File Reference

SPI library header for abstraction of SPI HW registers accesses. More...

Go to the source code of this file.

Functions

UINT64 | SpiGetPciCfgAddress (VOID)
Returns SPI PCI Config Space base address. More...
UINT32 | SpiGetBar0 (VOID)
Returns SPI BAR0 value. More...
UINT8 | SpiDeviceNumber (VOID)
Returns SPI Device number. More...
UINT8 | SpiFunctionNumber (VOID)
Returns SPI Function number. More...
UINT32 | SpiGetDescriptorSignature (VOID)
Returns descriptor signature. More...
UINT32 | SpiGetFlashComponentDescription (VOID)
Returns supported features and R/W frequencies of Flash Component. More...
UINT32 | SpiGetFlashComponentsNumber (VOID)
Returns number of Flash Components. More...
UINT32 | SpiGetTotalFlashSize (VOID)
Returns total Flash size with regards to number of flash components. More...
BOOLEAN | SpiIsControllerAvailable (VOID)
Checks if PCH SPI Controler is present and available. More...
BOOLEAN | SpiIsWriteProtectionEnabled (VOID)
Checks BIOS lock bits for proper value and checks if write protection is enabled Expected vales are: LE bit set, EISS bit set and WPD bit cleared. More...
BOOLEAN | SpiIsFlashDescriptorOverrideEnabled (VOID)
Returns Flash Descriptor Override Pin Strap status. More...
BOOLEAN | SpiIsFlashConfigurationLockDownEnabled (VOID)
Returns Flash Configuration Lock Down bit status. More...
BOOLEAN | SpiIsTopSwapEnabled (VOID)
Returns Top Swap functionality enable state. More...
BOOLEAN | SpiGetComponentPropertyParameterTable (IN UINT8 ComponentNumber, OUT UINT32 *CppTable)
Return Component Property Parameter Table for a given component number. More...
BOOLEAN | SpiIsCppValidBitSet (IN UINT32 CppTable)
Returns valid bit status in given Component Property Parameter Table. More...
BOOLEAN | SpiIsFlashDescriptorValid (VOID)
Checks if Flash Descriptor is valid. More...
UINT32 | SpiGetBiosRegionFlashWriteAccess (VOID)
Returns BIOS Region Flash Write Access masked value. More...
UINT32 | SpiGetBiosRegionFlashReadAccess (VOID)
Returns masked BIOS Region Flash Read Access value. More...
UINT32 | SpiGetMasterReadAccess (VOID)
Returns masked BIOS Host Read Access. More...
UINT32 | SpiGetMasterWriteAccess (VOID)
Returns masked BIOS Host Write Access. More...
UINT32 | SpiGetGbeRegionAccess (VOID)
Returns GbE Region Access rights. More...
UINT32 | SpiGetCsmeRegionAccess (VOID)
Returns CSME region access rights. More...
UINT32 | SpiGetEcRegionAccess (VOID)
Returns EC region access right. More...
BOOLEAN | SpiIsSafModeActive (VOID)
Checks if Device Attached Flash (DAF) mode is active. More...
BOOLEAN | SpiIsGbeRegionValid (VOID)
Checks validity of GbE region. More...
BOOLEAN | SpiIsBiosInterfaceLockdownEnabled (VOID)
Returns status of BIOS Interface Lockdown. More...
BOOLEAN | SpiIsBiosBootFromSpi (VOID)
Returns TRUE if BIOS Boot Strap is set to SPI. More...
BOOLEAN | SpiIsWriteStatusDisable (VOID)
Check SPI write status disable is set. More...
BOOLEAN | SpiIsExtendedBiosRegionEnabled (VOID)
Checks if Extended BIOS Region enable status. More...
VOID | SpiGetExtendedBiosRegionRange (UINT64 *RangeBase, UINT64 *RangeLimit)
Gets the extended BIOS region base and limit addresses. More...
BOOLEAN | SpiIsExtendedBiosRegionBaseLocked (VOID)
Checks lock of exnteded BIOS Region base address. More...
VOID | SpiClearBcSyncSs (VOID)
Clears BC_SYNC_SS.

Detailed Description

SPI library header for abstraction of SPI HW registers accesses.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SpiAccessLib.h.

Function Documentation

◆ SpiDeviceNumber()

UINT8 SpiDeviceNumber ( VOID )

Returns SPI Device number.

Return values
UINT8 PCH SPI Device number

◆ SpiFunctionNumber()

UINT8 SpiFunctionNumber ( VOID )

Returns SPI Function number.

Return values
UINT8 PCH SPI Function number

◆ SpiGetBar0()

UINT32 SpiGetBar0 ( VOID )

Returns SPI BAR0 value.

Return values
UINT32 PCH SPI BAR0 value

◆ SpiGetBiosRegionFlashReadAccess()

UINT32 SpiGetBiosRegionFlashReadAccess ( VOID )

Returns masked BIOS Region Flash Read Access value.

Return values
UINT32 Already masked BIOS Region Flash Read access

◆ SpiGetBiosRegionFlashWriteAccess()

UINT32 SpiGetBiosRegionFlashWriteAccess ( VOID )

Returns BIOS Region Flash Write Access masked value.

Return values
UINT32 Already masked BIOS Regsion Flash Write access

◆ SpiGetComponentPropertyParameterTable()

BOOLEAN SpiGetComponentPropertyParameterTable | ( | IN UINT8 | ComponentNumber,
 |  | OUT UINT32 * | CppTable
 | ) |  |

Return Component Property Parameter Table for a given component number.

Parameters
[in] | ComponentNumber | SPI Component number
[out] | CppTable | Component Poperty Parameter Table value
Return values
TRUE Vendor Specific Component Capabilities Register value was read @reval FALSE Vendor Specific Component Capabilities Register value was not present

◆ SpiGetCsmeRegionAccess()

UINT32 SpiGetCsmeRegionAccess ( VOID )

Returns CSME region access rights.

Return values
UINT32 CSME Region Access rights

◆ SpiGetDescriptorSignature()

UINT32 SpiGetDescriptorSignature ( VOID )

Returns descriptor signature.

Return values
UINT32 Descriptor signature

◆ SpiGetEcRegionAccess()

UINT32 SpiGetEcRegionAccess ( VOID )

Returns EC region access right.

Return values
UINT32 EC Region access rights

◆ SpiGetExtendedBiosRegionRange()

VOID SpiGetExtendedBiosRegionRange | ( | UINT64 * | RangeBase,
 |  | UINT64 * | RangeLimit
 | ) |  |

Gets the extended BIOS region base and limit addresses.

Parameters
[out] | UINT64 | Extended BIOS Region Range Base address
[out] | UINT64 | Extended BIOS Region Range Limit address

◆ SpiGetFlashComponentDescription()

UINT32 SpiGetFlashComponentDescription ( VOID )

Returns supported features and R/W frequencies of Flash Component.

Return values
UINT32 Flash Component features descriptor

◆ SpiGetFlashComponentsNumber()

UINT32 SpiGetFlashComponentsNumber ( VOID )

Returns number of Flash Components.

Return values
UINT32 Flash components number

◆ SpiGetGbeRegionAccess()

UINT32 SpiGetGbeRegionAccess ( VOID )

Returns GbE Region Access rights.

Return values
UINT32 GbE Region access rights

◆ SpiGetMasterReadAccess()

UINT32 SpiGetMasterReadAccess ( VOID )

Returns masked BIOS Host Read Access.

Return values
UINT32 Already masked BIOS Host Read Access

◆ SpiGetMasterWriteAccess()

UINT32 SpiGetMasterWriteAccess ( VOID )

Returns masked BIOS Host Write Access.

Return values
UINT32 Already masked BIOS Host Write Access

◆ SpiGetPciCfgAddress()

UINT64 SpiGetPciCfgAddress ( VOID )

Returns SPI PCI Config Space base address.

Return values
UINT64 SPI Config Space base address

◆ SpiGetTotalFlashSize()

UINT32 SpiGetTotalFlashSize ( VOID )

Returns total Flash size with regards to number of flash components.

Return values
UINT32 Total Flash Memory size

◆ SpiIsBiosBootFromSpi()

BOOLEAN SpiIsBiosBootFromSpi ( VOID )

Returns TRUE if BIOS Boot Strap is set to SPI.

Return values
TRUE | BIOS Boot strap is set to SPI
FALSE | BIOS Boot strap is set to LPC/eSPI

◆ SpiIsBiosInterfaceLockdownEnabled()

BOOLEAN SpiIsBiosInterfaceLockdownEnabled ( VOID )

Returns status of BIOS Interface Lockdown.

Return values
TRUE | BIOS Interface Lockdown is enabled
FALSE | BIOS Interface Lockdown is disabled

◆ SpiIsControllerAvailable()

BOOLEAN SpiIsControllerAvailable ( VOID )

Checks if PCH SPI Controler is present and available.

Return values
TRUE | PCH SPI controller is avaialable
FALSE | PCH SPI controller is not available

◆ SpiIsCppValidBitSet()

BOOLEAN SpiIsCppValidBitSet ( IN UINT32 CppTable )

Returns valid bit status in given Component Property Parameter Table.

Parameters
[in] CppTable Component Poperty Parameter Table value
Return values
TRUE Valid bit is set @reval FALSE Valid bit is not set

◆ SpiIsExtendedBiosRegionBaseLocked()

BOOLEAN SpiIsExtendedBiosRegionBaseLocked ( VOID )

Checks lock of exnteded BIOS Region base address.

Return values
TRUE | Extended BIOS Region base address is locked
FALSE | Extended BIOS Region base address is unlocked

◆ SpiIsExtendedBiosRegionEnabled()

BOOLEAN SpiIsExtendedBiosRegionEnabled ( VOID )

Checks if Extended BIOS Region enable status.

Return values
TRUE | Extended BIOS Region access is enabled
FALSE | Extended BIOS Region access is disabled

◆ SpiIsFlashConfigurationLockDownEnabled()

BOOLEAN SpiIsFlashConfigurationLockDownEnabled ( VOID )

Returns Flash Configuration Lock Down bit status.

Return values
TRUE | Flash Configuration Lock Down bit is set
FALSE | Flash Configuration Lock Down bit is not set

◆ SpiIsFlashDescriptorOverrideEnabled()

BOOLEAN SpiIsFlashDescriptorOverrideEnabled ( VOID )

Returns Flash Descriptor Override Pin Strap status.

Return values
TRUE | Flash Descriptor override is enabled
FALSE | Flash Descriptor override is disabled

◆ SpiIsFlashDescriptorValid()

BOOLEAN SpiIsFlashDescriptorValid ( VOID )

Checks if Flash Descriptor is valid.

Return values
TRUE | Flash Descriptor is valid
FALSE | Flash Descriptor is invalid

◆ SpiIsGbeRegionValid()

BOOLEAN SpiIsGbeRegionValid ( VOID )

Checks validity of GbE region.

Return values
TRUE | GbE region is valid
FALSE | GbE regios in invalid

◆ SpiIsSafModeActive()

BOOLEAN SpiIsSafModeActive ( VOID )

Checks if Device Attached Flash (DAF) mode is active.

Return values
TRUE | SAF mode is active
FALSE | SAF mode is not active

◆ SpiIsTopSwapEnabled()

BOOLEAN SpiIsTopSwapEnabled ( VOID )

Returns Top Swap functionality enable state.

Return values
TRUE | Top Swap is enabled
FALSE | Top Swap is disabled

◆ SpiIsWriteProtectionEnabled()

BOOLEAN SpiIsWriteProtectionEnabled ( VOID )

Checks BIOS lock bits for proper value and checks if write protection is enabled Expected vales are: LE bit set, EISS bit set and WPD bit cleared.

Return values
TRUE | All protection bits are set correctly
FALSE | Not all protection bits had exepcted values

◆ SpiIsWriteStatusDisable()

BOOLEAN SpiIsWriteStatusDisable ( VOID )

Check SPI write status disable is set.

Return values
TRUE | Write status disable is set
FALSE | Write status disable is not set
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SpiAccessLib.h
Go to the documentation of this file.
1 /** @file
2 SPI library header for abstraction of SPI HW registers accesses
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SPI_ACCESS_LIB_H_
36 #define _SPI_ACCESS_LIB_H_
37
38 /**
39 Returns SPI PCI Config Space base address
40
41 @retval UINT64 SPI Config Space base address
42 **/
43 UINT64
44 SpiGetPciCfgAddress (
45 VOID
46 );
47
48 /**
49 Returns SPI BAR0 value
50
51 @retval UINT32 PCH SPI BAR0 value
52 **/
53 UINT32
54 SpiGetBar0 (
55 VOID
56 );
57
58 /**
59 Returns SPI Device number
60
61 @retval UINT8 PCH SPI Device number
62 **/
63 UINT8
64 SpiDeviceNumber (
65 VOID
66 );
67
68 /**
69 Returns SPI Function number
70
71 @retval UINT8 PCH SPI Function number
72 **/
73 UINT8
74 SpiFunctionNumber (
75 VOID
76 );
77
78 /**
79 Returns descriptor signature
80
81 @retval UINT32 Descriptor signature
82 **/
83 UINT32
84 SpiGetDescriptorSignature (
85 VOID
86 );
87
88 /**
89 Returns supported features and R/W frequencies of Flash Component
90
91 @retval UINT32 Flash Component features descriptor
92 **/
93 UINT32
94 SpiGetFlashComponentDescription (
95 VOID
96 );
97
98 /**
99 Returns number of Flash Components
100
101 @retval UINT32 Flash components number
102 **/
103 UINT32
104 SpiGetFlashComponentsNumber (
105 VOID
106 );
107
108 /**
109 Returns total Flash size with regards to number of flash components
110
111 @retval UINT32 Total Flash Memory size
112 **/
113 UINT32
114 SpiGetTotalFlashSize (
115 VOID
116 );
117
118 /**
119 Checks if PCH SPI Controler is present and available
120
121 @retval TRUE PCH SPI controller is avaialable
122 @retval FALSE PCH SPI controller is not available
123 **/
124 BOOLEAN
125 SpiIsControllerAvailable (
126 VOID
127 );
128
129 /**
130 Checks BIOS lock bits for proper value and checks if write protection is enabled
131 Expected vales are: LE bit set, EISS bit set and WPD bit cleared
132
133 @retval TRUE All protection bits are set correctly
134 @retval FALSE Not all protection bits had exepcted values
135 **/
136 BOOLEAN
137 SpiIsWriteProtectionEnabled (
138 VOID
139 );
140
141 /**
142 Returns Flash Descriptor Override Pin Strap status
143
144 @retval TRUE Flash Descriptor override is enabled
145 @retval FALSE Flash Descriptor override is disabled
146 **/
147 BOOLEAN
148 SpiIsFlashDescriptorOverrideEnabled (
149 VOID
150 );
151
152 /**
153 Returns Flash Configuration Lock Down bit status
154
155 @retval TRUE Flash Configuration Lock Down bit is set
156 @retval FALSE Flash Configuration Lock Down bit is not set
157 **/
158 BOOLEAN
159 SpiIsFlashConfigurationLockDownEnabled (
160 VOID
161 );
162
163 /**
164 Returns Top Swap functionality enable state
165
166 @retval TRUE Top Swap is enabled
167 @retval FALSE Top Swap is disabled
168 **/
169 BOOLEAN
170 SpiIsTopSwapEnabled (
171 VOID
172 );
173
174 /**
175 Return Component Property Parameter Table for a given component number
176
177 @param[in] ComponentNumber SPI Component number
178 @param[out] CppTable Component Poperty Parameter Table value
179
180 @retval TRUE Vendor Specific Component Capabilities Register value was read
181 @reval FALSE Vendor Specific Component Capabilities Register value was not present
182 **/
183 BOOLEAN
184 SpiGetComponentPropertyParameterTable (
185 IN UINT8 ComponentNumber,
186 OUT UINT32 *CppTable
187 );
188
189 /**
190 Returns valid bit status in given Component Property Parameter Table
191
192 @param[in] CppTable Component Poperty Parameter Table value
193
194 @retval TRUE Valid bit is set
195 @reval FALSE Valid bit is not set
196 **/
197 BOOLEAN
198 SpiIsCppValidBitSet (
199 IN UINT32 CppTable
200 );
201
202 /**
203 Checks if Flash Descriptor is valid
204
205 @retval TRUE Flash Descriptor is valid
206 @retval FALSE Flash Descriptor is invalid
207 **/
208 BOOLEAN
209 SpiIsFlashDescriptorValid (
210 VOID
211 );
212
213 /**
214 Returns BIOS Region Flash Write Access masked value
215
216 @retval UINT32 Already masked BIOS Regsion Flash Write access
217 **/
218 UINT32
219 SpiGetBiosRegionFlashWriteAccess (
220 VOID
221 );
222
223 /**
224 Returns masked BIOS Region Flash Read Access value
225
226 @retval UINT32 Already masked BIOS Region Flash Read access
227 **/
228 UINT32
229 SpiGetBiosRegionFlashReadAccess (
230 VOID
231 );
232
233 /**
234 Returns masked BIOS Host Read Access
235
236 @retval UINT32 Already masked BIOS Host Read Access
237 **/
238 UINT32
239 SpiGetMasterReadAccess (
240 VOID
241 );
242
243 /**
244 Returns masked BIOS Host Write Access
245
246 @retval UINT32 Already masked BIOS Host Write Access
247 **/
248 UINT32
249 SpiGetMasterWriteAccess (
250 VOID
251 );
252
253 /**
254 Returns GbE Region Access rights
255
256 @retval UINT32 GbE Region access rights
257 **/
258 UINT32
259 SpiGetGbeRegionAccess (
260 VOID
261 );
262
263 /**
264 Returns CSME region access rights
265
266 @retval UINT32 CSME Region Access rights
267 **/
268 UINT32
269 SpiGetCsmeRegionAccess (
270 VOID
271 );
272
273 /**
274 Returns EC region access right
275
276 @retval UINT32 EC Region access rights
277 **/
278 UINT32
279 SpiGetEcRegionAccess (
280 VOID
281 );
282
283 /**
284 Checks if Device Attached Flash (DAF) mode is active
285
286 @retval TRUE SAF mode is active
287 @retval FALSE SAF mode is not active
288 **/
289 BOOLEAN
290 SpiIsSafModeActive (
291 VOID
292 );
293
294 /**
295 Checks validity of GbE region
296
297 @retval TRUE GbE region is valid
298 @retval FALSE GbE regios in invalid
299 **/
300 BOOLEAN
301 SpiIsGbeRegionValid (
302 VOID
303 );
304
305 /**
306 Returns status of BIOS Interface Lockdown
307
308 @retval TRUE BIOS Interface Lockdown is enabled
309 @retval FALSE BIOS Interface Lockdown is disabled
310 **/
311 BOOLEAN
312 SpiIsBiosInterfaceLockdownEnabled (
313 VOID
314 );
315
316 /**
317 Returns TRUE if BIOS Boot Strap is set to SPI
318
319 @retval TRUE BIOS Boot strap is set to SPI
320 @retval FALSE BIOS Boot strap is set to LPC/eSPI
321 **/
322 BOOLEAN
323 SpiIsBiosBootFromSpi (
324 VOID
325 );
326
327 /**
328 Check SPI write status disable is set
329
330 @retval TRUE Write status disable is set
331 @retval FALSE Write status disable is not set
332 **/
333 BOOLEAN
334 SpiIsWriteStatusDisable (
335 VOID
336 );
337
338 /**
339 Checks if Extended BIOS Region enable status
340
341 @retval TRUE Extended BIOS Region access is enabled
342 @retval FALSE Extended BIOS Region access is disabled
343 **/
344 BOOLEAN
345 SpiIsExtendedBiosRegionEnabled (
346 VOID
347 );
348
349 /**
350 Gets the extended BIOS region base and limit addresses
351
352 @param[out] UINT64 Extended BIOS Region Range Base address
353 @param[out] UINT64 Extended BIOS Region Range Limit address
354 **/
355 VOID
356 SpiGetExtendedBiosRegionRange (
357 UINT64 *RangeBase,
358 UINT64 *RangeLimit
359 );
360
361 /**
362 Checks lock of exnteded BIOS Region base address
363
364 @retval TRUE Extended BIOS Region base address is locked
365 @retval FALSE Extended BIOS Region base address is unlocked
366 **/
367 BOOLEAN
368 SpiIsExtendedBiosRegionBaseLocked (
369 VOID
370 );
371
372 /**
373 Clears BC_SYNC_SS.
374 **/
375 VOID
376 SpiClearBcSyncSs(
377 VOID
378 );
379
380 #endif // _SPI_ACCESS_LIB_H_
SpiIsWriteProtectionEnabled
BOOLEAN SpiIsWriteProtectionEnabled(VOID)
Checks BIOS lock bits for proper value and checks if write protection is enabled Expected vales are: ...
SpiGetGbeRegionAccess
UINT32 SpiGetGbeRegionAccess(VOID)
Returns GbE Region Access rights.
SpiGetDescriptorSignature
UINT32 SpiGetDescriptorSignature(VOID)
Returns descriptor signature.
SpiGetBar0
UINT32 SpiGetBar0(VOID)
Returns SPI BAR0 value.
SpiGetMasterWriteAccess
UINT32 SpiGetMasterWriteAccess(VOID)
Returns masked BIOS Host Write Access.
SpiIsWriteStatusDisable
BOOLEAN SpiIsWriteStatusDisable(VOID)
Check SPI write status disable is set.
SpiGetCsmeRegionAccess
UINT32 SpiGetCsmeRegionAccess(VOID)
Returns CSME region access rights.
SpiIsFlashDescriptorOverrideEnabled
BOOLEAN SpiIsFlashDescriptorOverrideEnabled(VOID)
Returns Flash Descriptor Override Pin Strap status.
SpiGetExtendedBiosRegionRange
VOID SpiGetExtendedBiosRegionRange(UINT64 *RangeBase, UINT64 *RangeLimit)
Gets the extended BIOS region base and limit addresses.
SpiClearBcSyncSs
VOID SpiClearBcSyncSs(VOID)
Clears BC_SYNC_SS.
SpiIsBiosInterfaceLockdownEnabled
BOOLEAN SpiIsBiosInterfaceLockdownEnabled(VOID)
Returns status of BIOS Interface Lockdown.
SpiIsFlashConfigurationLockDownEnabled
BOOLEAN SpiIsFlashConfigurationLockDownEnabled(VOID)
Returns Flash Configuration Lock Down bit status.
SpiGetMasterReadAccess
UINT32 SpiGetMasterReadAccess(VOID)
Returns masked BIOS Host Read Access.
SpiGetEcRegionAccess
UINT32 SpiGetEcRegionAccess(VOID)
Returns EC region access right.
SpiGetBiosRegionFlashWriteAccess
UINT32 SpiGetBiosRegionFlashWriteAccess(VOID)
Returns BIOS Region Flash Write Access masked value.
SpiGetComponentPropertyParameterTable
BOOLEAN SpiGetComponentPropertyParameterTable(IN UINT8 ComponentNumber, OUT UINT32 *CppTable)
Return Component Property Parameter Table for a given component number.
SpiFunctionNumber
UINT8 SpiFunctionNumber(VOID)
Returns SPI Function number.
SpiIsBiosBootFromSpi
BOOLEAN SpiIsBiosBootFromSpi(VOID)
Returns TRUE if BIOS Boot Strap is set to SPI.
SpiIsFlashDescriptorValid
BOOLEAN SpiIsFlashDescriptorValid(VOID)
Checks if Flash Descriptor is valid.
SpiIsControllerAvailable
BOOLEAN SpiIsControllerAvailable(VOID)
Checks if PCH SPI Controler is present and available.
SpiIsExtendedBiosRegionBaseLocked
BOOLEAN SpiIsExtendedBiosRegionBaseLocked(VOID)
Checks lock of exnteded BIOS Region base address.
SpiIsExtendedBiosRegionEnabled
BOOLEAN SpiIsExtendedBiosRegionEnabled(VOID)
Checks if Extended BIOS Region enable status.
SpiGetPciCfgAddress
UINT64 SpiGetPciCfgAddress(VOID)
Returns SPI PCI Config Space base address.
SpiIsSafModeActive
BOOLEAN SpiIsSafModeActive(VOID)
Checks if Device Attached Flash (DAF) mode is active.
SpiIsCppValidBitSet
BOOLEAN SpiIsCppValidBitSet(IN UINT32 CppTable)
Returns valid bit status in given Component Property Parameter Table.
SpiIsTopSwapEnabled
BOOLEAN SpiIsTopSwapEnabled(VOID)
Returns Top Swap functionality enable state.
SpiDeviceNumber
UINT8 SpiDeviceNumber(VOID)
Returns SPI Device number.
SpiGetFlashComponentDescription
UINT32 SpiGetFlashComponentDescription(VOID)
Returns supported features and R/W frequencies of Flash Component.
SpiGetFlashComponentsNumber
UINT32 SpiGetFlashComponentsNumber(VOID)
Returns number of Flash Components.
SpiGetTotalFlashSize
UINT32 SpiGetTotalFlashSize(VOID)
Returns total Flash size with regards to number of flash components.
SpiIsGbeRegionValid
BOOLEAN SpiIsGbeRegionValid(VOID)
Checks validity of GbE region.
SpiGetBiosRegionFlashReadAccess
UINT32 SpiGetBiosRegionFlashReadAccess(VOID)
Returns masked BIOS Region Flash Read Access value.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
Classes
SpiConfig.h File Reference

PCH SPI Flash Controller config block. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct SPI_CONFIG
Basic configuration for option features of PCH SPI Flash controller. More...

Detailed Description

PCH SPI Flash Controller config block.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SpiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
SpiConfig.h
Go to the documentation of this file.
1 /** @file
2 PCH SPI Flash Controller config block
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _SPI_CONFIG_H_
37 #define _SPI_CONFIG_H_
38
39 #define SPI_CONFIG_REVISION 1
40 extern EFI_GUID gSpiConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 Basic configuration for option features of PCH SPI Flash controller
46 **/
47 typedef struct {
48 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
49 /**
50 Enable extended BIOS Direct Read Region feature
51 Enabling this will make all memory accesses in a decode range to be translated
52 to BIOS region reads from SPI flash
53 <b>0: Disabled</b>, 1: Enabled
54 **/
55 UINT32 ExtendedBiosDecodeRangeEnable : 1;
56 UINT32 RsvdBits0 : 31; ///< Reserved bits
57 /**
58 Base address that will be used for Extended Decode Range.
59 This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.
60 **/
61 UINT32 ExtendedBiosDecodeRangeBase;
62 /**
63 Limit address that will be used for Extended Decode Range.
64 This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.
65 **/
66 UINT32 ExtendedBiosDecodeRangeLimit;
67 } SPI_CONFIG;
68
69 #pragma pack (pop)
70
71 #endif // _SPI_CONFIG_H_
SPI_CONFIG
Basic configuration for option features of PCH SPI Flash controller.
Definition: SpiConfig.h:47
SPI_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: SpiConfig.h:56
SPI_CONFIG::ExtendedBiosDecodeRangeBase
UINT32 ExtendedBiosDecodeRangeBase
Base address that will be used for Extended Decode Range.
Definition: SpiConfig.h:61
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
SPI_CONFIG::ExtendedBiosDecodeRangeEnable
UINT32 ExtendedBiosDecodeRangeEnable
Enable extended BIOS Direct Read Region feature Enabling this will make all memory accesses in a deco...
Definition: SpiConfig.h:55
SPI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: SpiConfig.h:48
SPI_CONFIG::ExtendedBiosDecodeRangeLimit
UINT32 ExtendedBiosDecodeRangeLimit
Limit address that will be used for Extended Decode Range.
Definition: SpiConfig.h:66
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SpiLib.h File Reference

Header file for Spi Library. More...

Go to the source code of this file.

Functions

EFI_STATUS SpiServiceInit (VOID)
This function Initial SPI services. More...

Detailed Description

Header file for Spi Library.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file SpiLib.h.

Function Documentation

◆ SpiServiceInit()

EFI_STATUS SpiServiceInit ( VOID )

This function Initial SPI services.

Return values
EFI_STATUS Results of the installation of the SPI services
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SpiLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SpiLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for Spi Library.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification
34 **/
35 #ifndef _SPI_LIB_H_
36 #define _SPI_LIB_H_
37
38 /**
39 This function Initial SPI services
40
41 @retval EFI_STATUS Results of the installation of the SPI services
42 **/
43 EFI_STATUS
44 EFIAPI
45 SpiServiceInit (
46 VOID
47 );
48
49 #endif
SpiServiceInit
EFI_STATUS SpiServiceInit(VOID)
This function Initial SPI services.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SsaPeiInit.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Ppi
Variables
SsaPeiInit.h File Reference

Interface definition between MRC and SsaInit modules. More...

Go to the source code of this file.

Variables

EFI_GUID gSsaBiosCallBacksPpiGuid
Extern the GUID for PPI users.

Detailed Description

Interface definition between MRC and SsaInit modules.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SsaPeiInit.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SsaPeiInit.h Source File

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Ppi
SsaPeiInit.h
Go to the documentation of this file.
1 /** @file
2 Interface definition between MRC and SsaInit modules.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _SSA_PEI_INIT_H_
36 #define _SSA_PEI_INIT_H_
37
38
39 ///
40 /// Extern the GUID for PPI users.
41 ///
42 extern EFI_GUID gSsaBiosCallBacksPpiGuid;
43 extern EFI_GUID gSsaBiosServicesPpiGuid;
44
45 #endif
gSsaBiosCallBacksPpiGuid
EFI_GUID gSsaBiosCallBacksPpiGuid
Extern the GUID for PPI users.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): StallPpiLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
StallPpiLib.h File Reference

Header file for a library to install StallPpi. More...

Go to the source code of this file.

Functions

EFI_STATUS InstallStallPpi (VOID)
This function is to install StallPpi. More...

Detailed Description

Header file for a library to install StallPpi.

Copyright
INTEL CONFIDENTIAL Copyright 2017 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file StallPpiLib.h.

Function Documentation

◆ InstallStallPpi()

EFI_STATUS InstallStallPpi ( VOID )

This function is to install StallPpi.

Return values
EFI_SUCCESS if Ppi is installed successfully.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): StallPpiLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
StallPpiLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for a library to install StallPpi.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _STALL_PPI_LIB_H_
37 #define _STALL_PPI_LIB_H_
38
39 /**
40 This function is to install StallPpi
41
42 @retval EFI_SUCCESS if Ppi is installed successfully.
43 **/
44 EFI_STATUS
45 EFIAPI
46 InstallStallPpi(
47 VOID
48 );
49 #endif //_STALL_PPI_LIB_H_
InstallStallPpi
EFI_STATUS InstallStallPpi(VOID)
This function is to install StallPpi.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemTimeLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
SystemTimeLib.h File Reference

Header file for SystemTimeLib. More...

#include <Uefi.h>
#include <Library/DebugLib.h>
Include dependency graph for SystemTimeLib.h:

Go to the source code of this file.

Functions

VOID | GetSystemTime (OUT SYSTEM_TIME *const SystemTime)
This funtion will output the system time in (YYYY-MM-DD-HH-MM-SS) format. More...
UINT64 | ConvertSystemTimeToUnixFormat (IN SYSTEM_TIME *SystemTime)
This funtion returns Unix Time: The number of milliseconds since 1 January 1970. More...

Detailed Description

Header file for SystemTimeLib.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file SystemTimeLib.h.

Function Documentation

◆ ConvertSystemTimeToUnixFormat()

UINT64 ConvertSystemTimeToUnixFormat ( IN SYSTEM_TIME * SystemTime )

This funtion returns Unix Time: The number of milliseconds since 1 January 1970.

Parameters
[in] SYSTEM_TIME typedef struct for system time
Return values
UINT64 Total time in milli seconds

◆ GetSystemTime()

VOID GetSystemTime ( OUT SYSTEM_TIME *const SystemTime )

This funtion will output the system time in (YYYY-MM-DD-HH-MM-SS) format.

Parameters
[out] SYSTEM_TIME typedef struct for system time
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemTimeLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
SystemTimeLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SystemTimeLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef BASE_SYSTEM_TIME_LIB_H_
36 #define BASE_SYSTEM_TIME_LIB_H_
37
38 #include <Uefi.h>
39 #include <Library/DebugLib.h>
40
41 #define RTC_INDEX_REGISTER (0x70)
42 #define RTC_TARGET_REGISTER (0x71)
43
44 #define RTC_INDEX_MASK (0x7F)
45 #define RTC_BANK_SIZE (0x80)
46
47 #define RTC_SECONDS (0x00)
48 #define RTC_MINUTES (0x02)
49 #define RTC_HOURS (0x04)
50 #define RTC_DAY_OF_MONTH (0x07)
51 #define RTC_MONTH (0x08)
52 #define RTC_YEAR (0x09)
53 #define CMOS_REGA (0x0A)
54 #define CMOS_REGB (0x0B)
55 #define CMOS_REGC (0x0C)
56 #define CMOS_REGD (0x0D)
57
58 #define RTC_UPDATE_IN_PROGRESS (0x80)
59 #define RTC_HOLD (0x80)
60 #define RTC_MODE_24HOUR (0x02)
61 #define RTC_CLOCK_DIVIDER (0x20)
62 #define RTC_RATE_SELECT (0x06)
63
64 #define BCD2BINARY(A) (((((A) >> 4) & 0xF) * 10) + ((A) & 0xF))
65 #define CENTURY_OFFSET (2000)
66
67 #pragma pack(1)
68 typedef union {
69 struct {
70 UINT8 Seconds;
71 UINT8 Minutes;
72 UINT8 Hours;
73 UINT8 DayOfMonth;
74 UINT8 Month;
75 UINT16 Year;
76 UINT8 Reserved;
77 } Data;
78 UINT64 Data64;
79 } SYSTEM_TIME;
80 #pragma pack()
81
82 /**
83 This funtion will output the system time in (YYYY-MM-DD-HH-MM-SS) format
84
85 @param[out] SYSTEM_TIME typedef struct for system time
86 **/
87 VOID
88 GetSystemTime (
89 OUT SYSTEM_TIME *const SystemTime
90 );
91
92 /**
93 This funtion returns Unix Time: The number of milliseconds since 1 January 1970.
94
95 @param[in] SYSTEM_TIME typedef struct for system time
96
97 @retval UINT64 Total time in milli seconds
98 **/
99 UINT64
100 ConvertSystemTimeToUnixFormat (
101 IN SYSTEM_TIME *SystemTime
102 );
103
104 #endif /* BASE_SYSTEM_TIME_LIB_H_ */
GetSystemTime
VOID GetSystemTime(OUT SYSTEM_TIME *const SystemTime)
This funtion will output the system time in (YYYY-MM-DD-HH-MM-SS) format.
ConvertSystemTimeToUnixFormat
UINT64 ConvertSystemTimeToUnixFormat(IN SYSTEM_TIME *SystemTime)
This funtion returns Unix Time: The number of milliseconds since 1 January 1970.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtCommonLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TbtCommonLib.h File Reference

Header file of TBT common library. More...

#include <Library/BaseLib.h>
#include <Library/TimerLib.h>
#include <Library/PciSegmentLib.h>
#include <IndustryStandard/Pci22.h>
#include <TbtMailBoxCmdDefinition.h>
Include dependency graph for TbtCommonLib.h:

Go to the source code of this file.

Functions

BOOLEAN | InternalWaitforCommandCompletion (IN UINT64 CommandOffsetAddress, IN UINT32 TimeOut, IN BOOLEAN Tbt2PcieDone, OUT UINT32 *Tbt2PcieValue)
Internal function to Wait for Tbt2PcieDone Bit.to Set or clear. More...
UINT8 | TbtGetSecLevel (IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 Command, IN UINT32 Timeout)
Get Security Level. More...
BOOLEAN | TbtSetSecLevel (IN UINT8 Data, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 Command, IN UINT32 Timeout)
Set Security Level. More...
BOOLEAN | TbtSetDmaSsidSvid (IN UINT8 Command, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT32 Timeout, IN UINT32 Data)
Program DAM SSID SVID. More...
BOOLEAN | TbtSetPcie2TbtCommand (IN UINT8 Command, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT32 Timeout)
Execute TBT Mailbox Command without data. More...
EFI_STATUS | GetITbtDmaDevFun (IN UINT8 Controller, OUT UINTN *Segment, OUT UINTN *Bus, OUT UINTN *Device, OUT UINTN *Function)
Get Segment, Bus, Device and Function Number for ITBT DMA controller by Root Port physical number. More...
VOID | TbtClearVgaRegisters (IN UINTN Segment, IN UINTN Bus, IN UINTN Device, IN UINTN Function)
VGA Enable and VGA 16-bit decode registers of Bridge control register of Intergrated and Discrete Thunderbolt root port should be cleaned. More...

Detailed Description

Header file of TBT common library.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TbtCommonLib.h.

Function Documentation

◆ GetITbtDmaDevFun()

EFI_STATUS GetITbtDmaDevFun | ( | IN UINT8 | Controller,
 |  | OUT UINTN * | Segment,
 |  | OUT UINTN * | Bus,
 |  | OUT UINTN * | Device,
 |  | OUT UINTN * | Function
 | ) |  |

Get Segment, Bus, Device and Function Number for ITBT DMA controller by Root Port physical number.

Parameters
[in] | Controller | Controller number. (0-based)
[out] | Segment | Return corresponding Tbt HIA Segment number.
[out] | Bus | Return corresponding Tbt HIA Bus number.
[out] | Device | Return corresponding Tbt HIA device number.
[out] | Function | Return corresponding Tbt HIA function number.
Return values
EFI_SUCCESS Root port device and function is retrieved

◆ InternalWaitforCommandCompletion()

BOOLEAN InternalWaitforCommandCompletion | ( | IN UINT64 | CommandOffsetAddress,
 |  | IN UINT32 | TimeOut,
 |  | IN BOOLEAN | Tbt2PcieDone,
 |  | OUT UINT32 * | Tbt2PcieValue
 | ) |  |

Internal function to Wait for Tbt2PcieDone Bit.to Set or clear.

Parameters
[in] | CommandOffsetAddress | Tbt2Pcie Register Address
[in] | TimeOut | The number of 1 ms units to delay
[in] | Tbt2PcieDone | Wait condition (wait for Bit to Clear/Set)
[out] | *Tbt2PcieValue | Function Register value
Return values
TRUE If command executes succesfully

◆ TbtClearVgaRegisters()

VOID TbtClearVgaRegisters | ( | IN UINTN | Segment,
 |  | IN UINTN | Bus,
 |  | IN UINTN | Device,
 |  | IN UINTN | Function
 | ) |  |

VGA Enable and VGA 16-bit decode registers of Bridge control register of Intergrated and Discrete Thunderbolt root port should be cleaned.

Parameters
[in] | Segment | Segment number
[in] | Bus | Bus number
[in] | Device | Device number
[in] | Function | Function number

◆ TbtGetSecLevel()

UINT8 TbtGetSecLevel | ( | IN UINT16 | Tbt2PcieOffset,
 |  | IN UINT16 | Pcie2TbtOffset,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT8 | Command,
 |  | IN UINT32 | Timeout
 | ) |  |

Get Security Level.

Parameters
[in] | Tbt2PcieOffset | TBT2PCIE Register Offset
[in] | Pcie2TbtOffset | PCIE2TBT Register Offset
[in] | Bus | Bus number for HIA (ITBT) or Host Router (DTBT)
[in] | Device | Device number for HIA (ITBT) or Host Router (DTBT)
[in] | Function | Function number for HIA (ITBT) or Host Router (DTBT)
[in] | Timeout | Time out with 100 ms garnularity

◆ TbtSetDmaSsidSvid()

BOOLEAN TbtSetDmaSsidSvid | ( | IN UINT8 | Command,
 |  | IN UINT16 | Tbt2PcieOffset,
 |  | IN UINT16 | Pcie2TbtOffset,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT32 | Timeout,
 |  | IN UINT32 | Data
 | ) |  |

Program DAM SSID SVID.

Parameters
[in] | Command | TBT Command
[in] | Tbt2PcieOffset | TBT2PCIE Register Offset
[in] | Pcie2TbtOffset | PCIE2TBT Register Offset
[in] | Bus | Bus number for HIA (ITBT) or Host Router (DTBT)
[in] | Device | Device number for HIA (ITBT) or Host Router (DTBT)
[in] | Function | Function number for HIA (ITBT) or Host Router (DTBT)
[in] | Timeout | Time out with 1 ms garnularity
[in] | Data | SSID SVID data
Return values
TRUE If command executes succesfully

◆ TbtSetPcie2TbtCommand()

BOOLEAN TbtSetPcie2TbtCommand | ( | IN UINT8 | Command,
 |  | IN UINT16 | Tbt2PcieOffset,
 |  | IN UINT16 | Pcie2TbtOffset,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT32 | Timeout
 | ) |  |

Execute TBT Mailbox Command without data.

1.Load PCIE2TBT register with command and set VALID bit of PCIE2TBT register to indicate a new command sent 2.Wait for DONE bit set by LC acknowledging the command sent from the host before timeout 3.Clear PCIE2TBT register valid bit which should be cleared by host SW after command done 4.Wait for DONE bit cleared by LC if it is iTBT controller

Parameters
[in] | Command | TBT Command
[in] | Tbt2PcieOffset | TBT2PCIE Register Offset
[in] | Pcie2TbtOffset | PCIE2TBT Register Offset
[in] | Bus | Bus number for HIA (ITBT) or Host Router (DTBT)
[in] | Device | Device number for HIA (ITBT) or Host Router (DTBT)
[in] | Function | Function number for HIA (ITBT) or Host Router (DTBT)
[in] | Timeout | Time out with 1 ms garnularity
Return values
TRUE If command executes succesfully

◆ TbtSetSecLevel()

BOOLEAN TbtSetSecLevel | ( | IN UINT8 | Data,
 |  | IN UINT16 | Tbt2PcieOffset,
 |  | IN UINT16 | Pcie2TbtOffset,
 |  | IN UINT8 | Bus,
 |  | IN UINT8 | Device,
 |  | IN UINT8 | Function,
 |  | IN UINT8 | Command,
 |  | IN UINT32 | Timeout
 | ) |  |

Set Security Level.

Parameters
[in] | Data | Security State
[in] | Tbt2PcieOffset | TBT2PCIE Register Offset
[in] | Pcie2TbtOffset | PCIE2TBT Register Offset
[in] | Bus | Bus number for HIA (ITBT) or Host Router (DTBT)
[in] | Device | Device number for HIA (ITBT) or Host Router (DTBT)
[in] | Function | Function number for HIA (ITBT) or Host Router (DTBT)
[in] | Timeout | Time out with 100 ms garnularity
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtCommonLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TbtCommonLib.h
Go to the documentation of this file.
1 /**@file
2 Header file of TBT common library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34
35 **/
36 #ifndef _TBT_COMMON_LIB_H_
37 #define _TBT_COMMON_LIB_H_
38
39 #include <Library/BaseLib.h>
40 #include <Library/TimerLib.h>
41 #include <Library/PciSegmentLib.h>
42 #include <IndustryStandard/Pci22.h>
43 #include <TbtMailBoxCmdDefinition.h>
44
45 #define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0
46 #define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0
47 #define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D
48 #define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02
49
50 typedef struct _DEV_ID {
51 UINT8 Segment;
52 UINT8 Bus;
53 UINT8 Dev;
54 UINT8 Fun;
55 } DEV_ID;
56
57 #ifdef __GNUC__
58 #pragma GCC diagnostic warning "-Wunused-variable"
59 #endif
60
61 /**
62 Internal function to Wait for Tbt2PcieDone Bit.to Set or clear
63 @param[in] CommandOffsetAddress Tbt2Pcie Register Address
64 @param[in] TimeOut The number of 1 ms units to delay
65 @param[in] Tbt2PcieDone Wait condition (wait for Bit to Clear/Set)
66 @param[out] *Tbt2PcieValue Function Register value
67 @retval TRUE If command executes succesfully
68 **/
69 BOOLEAN
70 InternalWaitforCommandCompletion(
71 IN UINT64 CommandOffsetAddress,
72 IN UINT32 TimeOut,
73 IN BOOLEAN Tbt2PcieDone,
74 OUT UINT32 *Tbt2PcieValue
75 );
76
77 /**
78 Get Security Level.
79 @param[in] Tbt2PcieOffset TBT2PCIE Register Offset
80 @param[in] Pcie2TbtOffset PCIE2TBT Register Offset
81 @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
82 @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
83 @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
84 @param[in] Timeout Time out with 100 ms garnularity
85 **/
86 UINT8
87 TbtGetSecLevel (
88 IN UINT16 Tbt2PcieOffset,
89 IN UINT16 Pcie2TbtOffset,
90 IN UINT8 Bus,
91 IN UINT8 Device,
92 IN UINT8 Function,
93 IN UINT8 Command,
94 IN UINT32 Timeout
95 );
96
97 /**
98 Set Security Level.
99 @param[in] Data Security State
100 @param[in] Tbt2PcieOffset TBT2PCIE Register Offset
101 @param[in] Pcie2TbtOffset PCIE2TBT Register Offset
102 @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
103 @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
104 @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
105 @param[in] Timeout Time out with 100 ms garnularity
106 **/
107 BOOLEAN
108 TbtSetSecLevel (
109 IN UINT8 Data,
110 IN UINT16 Tbt2PcieOffset,
111 IN UINT16 Pcie2TbtOffset,
112 IN UINT8 Bus,
113 IN UINT8 Device,
114 IN UINT8 Function,
115 IN UINT8 Command,
116 IN UINT32 Timeout
117 );
118
119 /**
120 Program DAM SSID SVID
121
122 @param[in] Command TBT Command
123 @param[in] Tbt2PcieOffset TBT2PCIE Register Offset
124 @param[in] Pcie2TbtOffset PCIE2TBT Register Offset
125 @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
126 @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
127 @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
128 @param[in] Timeout Time out with 1 ms garnularity
129 @param[in] Data SSID SVID data
130
131 @retval TRUE If command executes succesfully
132 **/
133 BOOLEAN
134 TbtSetDmaSsidSvid (
135 IN UINT8 Command,
136 IN UINT16 Tbt2PcieOffset,
137 IN UINT16 Pcie2TbtOffset,
138 IN UINT8 Bus,
139 IN UINT8 Device,
140 IN UINT8 Function,
141 IN UINT32 Timeout,
142 IN UINT32 Data
143 );
144
145 /**
146 Execute TBT Mailbox Command without data
147
148 1.Load PCIE2TBT register with command and set VALID bit of PCIE2TBT register to indicate a new command sent
149 2.Wait for DONE bit set by LC acknowledging the command sent from the host before timeout
150 3.Clear PCIE2TBT register valid bit which should be cleared by host SW after command done
151 4.Wait for DONE bit cleared by LC if it is iTBT controller
152
153 @param[in] Command TBT Command
154 @param[in] Tbt2PcieOffset TBT2PCIE Register Offset
155 @param[in] Pcie2TbtOffset PCIE2TBT Register Offset
156 @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT)
157 @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT)
158 @param[in] Function Function number for HIA (ITBT) or Host Router (DTBT)
159 @param[in] Timeout Time out with 1 ms garnularity
160 @retval TRUE If command executes succesfully
161 **/
162 BOOLEAN
163 TbtSetPcie2TbtCommand(
164 IN UINT8 Command,
165 IN UINT16 Tbt2PcieOffset,
166 IN UINT16 Pcie2TbtOffset,
167 IN UINT8 Bus,
168 IN UINT8 Device,
169 IN UINT8 Function,
170 IN UINT32 Timeout
171 );
172
173 /**
174 Get Segment, Bus, Device and Function Number for ITBT DMA controller by Root Port physical number
175
176 @param[in] Controller Controller number. (0-based)
177 @param[out] Segment Return corresponding Tbt HIA Segment number.
178 @param[out] Bus Return corresponding Tbt HIA Bus number.
179 @param[out] Device Return corresponding Tbt HIA device number.
180 @param[out] Function Return corresponding Tbt HIA function number.
181
182 @retval EFI_SUCCESS Root port device and function is retrieved
183 **/
184 EFI_STATUS
185 EFIAPI
186 GetITbtDmaDevFun(
187 IN UINT8 Controller,
188 OUT UINTN *Segment,
189 OUT UINTN *Bus,
190 OUT UINTN *Device,
191 OUT UINTN *Function
192 );
193
194 /**
195 VGA Enable and VGA 16-bit decode registers of Bridge control register of Intergrated and Discrete Thunderbolt root port
196 should be cleaned
197
198 @param[in] Segment Segment number
199 @param[in] Bus Bus number
200 @param[in] Device Device number
201 @param[in] Function Function number
202 **/
203 VOID
204 TbtClearVgaRegisters(
205 IN UINTN Segment,
206 IN UINTN Bus,
207 IN UINTN Device,
208 IN UINTN Function
209 );
210
211 #endif
TbtSetPcie2TbtCommand
BOOLEAN TbtSetPcie2TbtCommand(IN UINT8 Command, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT32 Timeout)
Execute TBT Mailbox Command without data.
GetITbtDmaDevFun
EFI_STATUS GetITbtDmaDevFun(IN UINT8 Controller, OUT UINTN *Segment, OUT UINTN *Bus, OUT UINTN *Device, OUT UINTN *Function)
Get Segment, Bus, Device and Function Number for ITBT DMA controller by Root Port physical number.
TbtGetSecLevel
UINT8 TbtGetSecLevel(IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 Command, IN UINT32 Timeout)
Get Security Level.
InternalWaitforCommandCompletion
BOOLEAN InternalWaitforCommandCompletion(IN UINT64 CommandOffsetAddress, IN UINT32 TimeOut, IN BOOLEAN Tbt2PcieDone, OUT UINT32 *Tbt2PcieValue)
Internal function to Wait for Tbt2PcieDone Bit.to Set or clear.
TbtMailBoxCmdDefinition.h
Header file of TBT MailBox Command Definition shared by C and ASL code.
TbtSetSecLevel
BOOLEAN TbtSetSecLevel(IN UINT8 Data, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT8 Command, IN UINT32 Timeout)
Set Security Level.
TbtSetDmaSsidSvid
BOOLEAN TbtSetDmaSsidSvid(IN UINT8 Command, IN UINT16 Tbt2PcieOffset, IN UINT16 Pcie2TbtOffset, IN UINT8 Bus, IN UINT8 Device, IN UINT8 Function, IN UINT32 Timeout, IN UINT32 Data)
Program DAM SSID SVID.
TbtClearVgaRegisters
VOID TbtClearVgaRegisters(IN UINTN Segment, IN UINTN Bus, IN UINTN Device, IN UINTN Function)
VGA Enable and VGA 16-bit decode registers of Bridge control register of Intergrated and Discrete Thu...
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtDisBmeProtocol.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Typedefs
TbtDisBmeProtocol.h File Reference

Definitions for DisableBmeProtocol. More...

Go to the source code of this file.

Typedefs

typedef VOID(* DISABLE_BUS_MASTER_ENABLE) (IN EFI_EVENT Event, IN VOID *Context)
Disabling TBT BME bit under UEFI Shell environment. More...

Detailed Description

Definitions for DisableBmeProtocol.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TbtDisBmeProtocol.h.

Typedef Documentation

◆ DISABLE_BUS_MASTER_ENABLE

typedef VOID( * DISABLE_BUS_MASTER_ENABLE) (IN EFI_EVENT Event, IN VOID *Context)

Disabling TBT BME bit under UEFI Shell environment.

Parameters
[in] | Event | - A pointer to the Event that triggered the callback.
[in] | Context | - A pointer to private data registered with the callback function.

Definition at line 50 of file TbtDisBmeProtocol.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtDisBmeProtocol.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
TbtDisBmeProtocol.h
Go to the documentation of this file.
1 /** @file
2 Definitions for DisableBmeProtocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DISABLE_TBT_BME_PROTOCOL_H_
36 #define _DISABLE_TBT_BME_PROTOCOL_H_
37
38 //
39 // Forward reference for pure ANSI compatability
40 //
41 typedef struct _EFI_DISABLE_TBT_BME_PROTOCOL EFI_DISABLE_TBT_BME_PROTOCOL;
42
43 /**
44 Disabling TBT BME bit under UEFI Shell environment
45
46 @param[in] Event - A pointer to the Event that triggered the callback.
47 @param[in] Context - A pointer to private data registered with the callback function.
48 **/
49 typedef
50 VOID
51 (EFIAPI *DISABLE_BUS_MASTER_ENABLE) (
52 IN EFI_EVENT Event,
53 IN VOID *Context
54 );
55
56 //
57 // Disable TBT BME Protocol structure.
58 //
59 struct _EFI_DISABLE_TBT_BME_PROTOCOL {
60 DISABLE_BUS_MASTER_ENABLE DisableBme;
61 };
62
63 //
64 // Disable iTBT BME Protocol GUID variable.
65 //
66 extern EFI_GUID gDxeDisableITbtBmeProtocolGuid;
67
68 #endif
DISABLE_BUS_MASTER_ENABLE
VOID(* DISABLE_BUS_MASTER_ENABLE)(IN EFI_EVENT Event, IN VOID *Context)
Disabling TBT BME bit under UEFI Shell environment.
Definition: TbtDisBmeProtocol.h:51
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtMailBoxCmdDefinition.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros
TbtMailBoxCmdDefinition.h File Reference

Header file of TBT MailBox Command Definition shared by C and ASL code. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | TBT_MAILBOX_DELAY 1000
1ms
#define | SET_CM_TIMEOUT_IN_MS 500
10 * TBT_MAILBOX_DELAY = 500ms
#define | PCIE2TBT_GO2SX 0x04
Mailbox command value to controller is generic on all types of TBT controllers. More...
#define | PCIE2TBT_GO2SX_NO_WAKE 0x06
Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx without wake support.
#define | PCIE2TBT_SX_EXIT_TBT_CONNECTED 0x08
Mailbox command to controller to exit Sx and the system went to sleep with attached devices previously.
#define | PCIE2TBT_CONNECT_TOPOLOGY_COMMAND 0x3E
Mailbox command to CM to ensure all connected TBT devices are available on PCIe.
#define | ENABLE_PCIE_TUNNELING_FOR_USB4 0x0
Extra data of mailbox command.
#define | PCIE2TBT_SSID_SVID_CFG 0x60
Mailbox command to program DMA 0/1 SSID SVID.

Detailed Description

Header file of TBT MailBox Command Definition shared by C and ASL code.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TbtMailBoxCmdDefinition.h.

Macro Definition Documentation

◆ PCIE2TBT_GO2SX

#define PCIE2TBT_GO2SX 0x04

Mailbox command value to controller is generic on all types of TBT controllers.

Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx with wake support

Definition at line 48 of file TbtMailBoxCmdDefinition.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TbtMailBoxCmdDefinition.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
TbtMailBoxCmdDefinition.h
Go to the documentation of this file.
1 /**@file
2 Header file of TBT MailBox Command Definition shared by C and ASL code.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34
35 **/
36
37 #define PCIE2TBT_VLD_B BIT0
38 #define TBT2PCIE_DON_R BIT0
39 #define TBT_MAILBOX_DELAY 1000 ///< 1ms
40 #define SET_CM_TIMEOUT_IN_MS 500 ///< 10 * TBT_MAILBOX_DELAY = 500ms
41
42 ///
43 ///Mailbox command value to controller is generic on all types of TBT controllers
44 ///
45 /**
46 Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx with wake support
47 **/
48 #define PCIE2TBT_GO2SX 0x04 //(0x02 << 1)
49 /**
50 Mailbox command to link controller (LC) and Connection Manager (CM) to enter Sx without wake support
51 **/
52 #define PCIE2TBT_GO2SX_NO_WAKE 0x06 //(0x03 << 1)
53 /**
54 Mailbox command to controller to exit Sx and the system went to sleep with attached devices previously
55 **/
56 #define PCIE2TBT_SX_EXIT_TBT_CONNECTED 0x08 //(0x04 << 1)
57 #define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED 0x0A //(0x05 << 1)
58 #define PCIE2TBT_OS_UP 0x0C //(0x06 << 1)
59 #define PCIE2TBT_SET_SECURITY_LEVEL 0x10 //(0x08 << 1)
60 #define PCIE2TBT_GET_SECURITY_LEVEL 0x12 //(0x09 << 1)
61 #define PCIE2TBT_CM_AUTH_MODE_ENTER 0x20 //(0x10 << 1)
62 #define PCIE2TBT_CM_AUTH_MODE_EXIT 0x22 //(0x11 << 1)
63 #define PCIE2TBT_BOOT_ON 0x30 //(0x18 << 1)
64 #define PCIE2TBT_BOOT_OFF 0x32 //(0x19 << 1)
65 #define PCIE2TBT_USB_ON 0x32 //(0x19 << 1)
66 #define PCIE2TBT_GET_ENUMERATION_METHOD 0x34 //(0x1A << 1)
67 #define PCIE2TBT_SET_ENUMERATION_METHOD 0x36 //(0x1B << 1)
68 #define PCIE2TBT_POWER_CYCLE 0x38 //(0x1C << 1)
69 /**
70 Mailbox command to CM to ensure all connected TBT devices are available on PCIe
71 **/
72 #define PCIE2TBT_CONNECT_TOPOLOGY_COMMAND 0x3E //(0x1F << 1)
73 #define PCIE2TBT_FIRMWARE_CM_MODE 0x44 //(0x22 << 1)
74 #define PCIE2TBT_PASS_THROUGH_MODE 0x46 //(0x23 << 1)
75 #define PCIE2TBT_GO_2_SLEEP 0x48 //(0x24 << 1)
76 /**
77 Extra data of mailbox command
78 **/
79 #define ENABLE_PCIE_TUNNELING_FOR_USB4 0x0
80 #define DISABLE_PCIE_TUNNELING_FOR_USB4 0x5
81 /**
82 Mailbox command to program DMA 0/1 SSID SVID
83 **/
84 #define PCIE2TBT_SSID_SVID_CFG 0x60 //(0x30 << 1)
85 #define PCIE2TBT_SSID_SVID_DATA_OFFSET 0xF4
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TccLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TccLib.h File Reference

Header file for TCC Lib. More...

Go to the source code of this file.

Functions

BOOLEAN IsTccSku (VOID)
Check whether TCC is Indu TCC SKU. More...

Detailed Description

Header file for TCC Lib.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TccLib.h.

Function Documentation

◆ IsTccSku()

BOOLEAN IsTccSku ( VOID )

Check whether TCC is Indu TCC SKU.

Return values
TRUE | TSN is enabled
FALSE | TSN is disabled
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TccLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TccLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for TCC Lib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCC_LIB_H_
36 #define _TCC_LIB_H_
37
38 /**
39 Check whether TCC is Indu TCC SKU
40
41 @retval TRUE TSN is enabled
42 @retval FALSE TSN is disabled
43 **/
44 BOOLEAN
45 IsTccSku (
46 VOID
47 );
48
49 #endif // _TCC_LIB_H_
IsTccSku
BOOLEAN IsTccSku(VOID)
Check whether TCC is Indu TCC SKU.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TcoLib.h File Reference

Header file for TcoLib. More...

Go to the source code of this file.

Functions

BOOLEAN | TcoSecondToHappened (VOID)
Check TCO second timeout status. More...
VOID | TcoClearSecondToStatus (VOID)
This function clears the Second TO status bit.
BOOLEAN | TcoIsSmiLock (VOID)
Check TCO SMI ENABLE is locked. More...
VOID | TcoHaltTimer (VOID)
Halts Tco timer.

Detailed Description

Header file for TcoLib.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcoLib.h.

Function Documentation

◆ TcoIsSmiLock()

BOOLEAN TcoIsSmiLock ( VOID )

Check TCO SMI ENABLE is locked.

Return values
TRUE TCO SMI ENABLE is locked FALSE TCO SMI ENABLE is not locked

◆ TcoSecondToHappened()

BOOLEAN TcoSecondToHappened ( VOID )

Check TCO second timeout status.

Return values
TRUE | TCO reboot happened.
FALSE | TCO reboot didn't happen.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TcoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for TcoLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCO_LIB_H_
36 #define _TCO_LIB_H_
37
38 /**
39 Check TCO second timeout status.
40
41 @retval TRUE TCO reboot happened.
42 @retval FALSE TCO reboot didn't happen.
43 **/
44 BOOLEAN
45 TcoSecondToHappened (
46 VOID
47 );
48
49 /**
50 This function clears the Second TO status bit
51 **/
52 VOID
53 TcoClearSecondToStatus (
54 VOID
55 );
56
57 /**
58 Check TCO SMI ENABLE is locked
59
60 @retval TRUE TCO SMI ENABLE is locked
61 FALSE TCO SMI ENABLE is not locked
62 **/
63 BOOLEAN
64 TcoIsSmiLock (
65 VOID
66 );
67
68 /**
69 Halts Tco timer
70 **/
71 VOID
72 TcoHaltTimer (
73 VOID
74 );
75
76 #endif // _TCO_LIB_H_
TcoIsSmiLock
BOOLEAN TcoIsSmiLock(VOID)
Check TCO SMI ENABLE is locked.
TcoSecondToHappened
BOOLEAN TcoSecondToHappened(VOID)
Check TCO second timeout status.
TcoHaltTimer
VOID TcoHaltTimer(VOID)
Halts Tco timer.
TcoClearSecondToStatus
VOID TcoClearSecondToStatus(VOID)
This function clears the Second TO status bit.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcoRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
TcoRegs.h File Reference

Register names for PCH TCO device. More...

Go to the source code of this file.

Macros

#define R_TCO_IO_TWDS 0x0E
TCO_WDSTATUS register.

Detailed Description

Register names for PCH TCO device.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification

Definition in file TcoRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcoRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
TcoRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for PCH TCO device
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification
63 **/
64 #ifndef _TCO_REGS_H_
65 #define _TCO_REGS_H_
66
67 //
68 // TCO register I/O map
69 //
70 #define R_TCO_IO_RLD 0x0
71 #define R_TCO_IO_TCO1_STS 0x04
72 #define S_TCO_IO_TCO1_STS 2
73 #define B_TCO_IO_TCO1_STS_DMISERR BIT12
74 #define B_TCO_IO_TCO1_STS_DMISMI BIT10
75 #define B_TCO_IO_TCO1_STS_DMISCI BIT9
76 #define B_TCO_IO_TCO1_STS_BIOSWR BIT8
77 #define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
78 #define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
79 #define B_TCO_IO_TCO1_STS_TCO_INT BIT2
80 #define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
81 #define N_TCO_IO_TCO1_STS_DMISMI 10
82 #define N_TCO_IO_TCO1_STS_BIOSWR 8
83 #define N_TCO_IO_TCO1_STS_NEWCENTURY 7
84 #define N_TCO_IO_TCO1_STS_TIMEOUT 3
85 #define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
86 #define N_TCO_IO_TCO1_STS_NMI2SMI 0
87
88 #define R_TCO_IO_TCO2_STS 0x06
89 #define S_TCO_IO_TCO2_STS 2
90 #define B_TCO_IO_TCO2_STS_BOOT BIT2
91 #define B_TCO_IO_TCO2_STS_SECOND_TO BIT1
92 #define B_TCO_IO_TCO2_STS_INTRD_DET BIT0
93 #define N_TCO_IO_TCO2_STS_INTRD_DET 0
94
95 #define R_TCO_IO_TCO1_CNT 0x08
96 #define S_TCO_IO_TCO1_CNT 2
97 #define B_TCO_IO_TCO1_CNT_LOCK BIT12
98 #define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11
99 #define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
100 #define B_TCO_IO_TCO1_CNT_NR_MSUS BIT0 //NO_REBOOT
101
102 #define R_TCO_IO_TCO2_CNT 0x0A
103 #define S_TCO_IO_TCO2_CNT 2
104 #define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
105
106 #define R_TCO_IO_TWDS 0x0E ///< TCO_WDSTATUS register.
107 #define R_TCO_IO_TMR 0x12
108
109 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
TcssDataHob.h File Reference

This file contains definitions of TCSS Data. More...

#include <Base.h>
#include <TcssInfo.h>
#include <ConfigBlock.h>
#include <ConfigBlock/SiConfig.h>
Include dependency graph for TcssDataHob.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | TBT_IMR_STATUS
Structure for Tbt firmware status from IMR. More...
union | MG_IMR_STATUS
Structure for MG image status from IMR. More...
struct | TCSS_DATA
TCSS data definition. More...
struct | TCSS_DATA_HOB
TCSS Data Hob. More...
struct | TCSS_DATA_SSID_HOB
TCSS SSID Data Hob. More...

Detailed Description

This file contains definitions of TCSS Data.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssDataHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
TcssDataHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions of TCSS Data.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_DATA_HOB_H_
36 #define _TCSS_DATA_HOB_H_
37
38 #include <Base.h>
39 #include <TcssInfo.h>
40 #include <ConfigBlock.h>
41 #include <ConfigBlock/SiConfig.h>
42
43 extern EFI_GUID gTcssHobGuid;
44 extern EFI_GUID gTcssSsidHobGuid;
45
46 //
47 // CM mode in Pre-boot - bit 2:0
48 //
49 #define USB4_CM_MODE_FW_CM 0x00
50 #define USB4_CM_MODE_SW_CM 0x01
51
52 //
53 // CM mode switch unsupport bit - bit 3
54 //
55 #define USB4_CM_MODE_SWITCH_UNSUPPORTED 0x08
56
57 //
58 // CM mode setup option - bit 2:0
59 //
60 #define SETUP_OPTION_USB4_CM_MODE_FW 0x00
61 #define SETUP_OPTION_USB4_CM_MODE_SW 0x01
62 #define SETUP_OPTION_USB4_CM_MODE_OS 0x02
63 #define SETUP_OPTION_USB4_CM_MODE_THROUGH 0x03
64
65 #pragma pack (push,1)
66
67 ///
68 /// Structure for Tbt firmware status from IMR.
69 ///
70 typedef union {
71 UINT32 RegValue;
72 struct {
73 UINT32 TbtFwVersion:16; ///< Bits 15:0
74 UINT32 Reserved:6; ///< Bits 21:16
75 UINT32 ErrorCode:8; ///< Bits 29:22
76 UINT32 Valid:1; ///< Bits 30 - 00 = untrusted FW, 01 = successful authentication
77 UINT32 Done:1; ///< Bits 31 - 01 = FW download to IMR is done
78 } Bits;
79 } TBT_IMR_STATUS;
80
81 ///
82 /// Structure for MG image status from IMR.
83 ///
84 typedef union {
85 UINT32 RegValue;
86 struct {
87 UINT32 MgFwVersion:16; ///< Bits 15:0
88 UINT32 Reserved:6; ///< Bits 21:16
89 UINT32 ErrorCode:8; ///< Bits 29:22
90 UINT32 Valid:1; ///< Bits 30 - 00 = untrusted FW, 01 = successful authentication
91 UINT32 Done:1; ///< Bits 31 - 01 = FW download to IMR is done
92 } Bits;
93 } MG_IMR_STATUS;
94
95 /**
96 TCSS data definition
97 **/
98 typedef struct {
99 UINT32 IOMReady:1; ///< Indicate the IOM ready.
100 UINT32 PcieMultipleSegmentEnabled:1; /// Deprecate < Indicate the extra segment of iTBT PCIe is enabled or not.
101 UINT32 Rsvd:30; ///< Reserved for future use.
102 UINT32 IomFwVersion; ///< IOM FW version.
103 UINT32 IomFwEngrVersion; ///< IOM FW Engineer version. Non-zero value used to identify engineering versions / hotfixes. Shall be zero for official releases.
104 TBT_IMR_STATUS TbtImrStatus; ///< Tbt FW IMR Status.
105 UINT32 ItbtPcieSegMap; ///< iTBT PCIE RP 0-3 Segment Map
106 UINT32 ItbtPcieFuncMap; ///< iTBT PCIE RP 0-3 Function Map
107 UINT8 ItbtPcieRpEn[MAX_ITBT_PCIE_PORT]; ///< ItbtPcieRpEn PCIE RP Device Enable
108 UINT8 ItbtXhciEn; ///< ItbtPcieRpEn XHCI Device Enable
109 UINT8 ItbtXdciEn; ///< ItbtPcieRpEn XDCI Device Enable
110 UINT8 ItbtDmaEn[MAX_HOST_ITBT_DMA_NUMBER]; ///< ItbtPcieRpEn DMA Device Enable
111 UINT8 TcssxDCIInt; ///< iTBT xDCI Int Pin number
112 UINT8 TcssxDCIIrq; ///< iTBT xDCI APIC IRQ number
113 UINT8 TcssRtd3; ///< TCSS RTD3
114 UINT8 ItbtForcePower; ///< iTBT Force Power status
115 MG_IMR_STATUS MgImrStatus; ///< MG IMR Status
116 UINT8 TcssIomVccSt; ///< IOM VCCST request.
117 UINT8 DeepstTcState; ///< Maximum TC C State limit
118 } TCSS_DATA;
119
120 typedef struct {
121 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
122 UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
123 UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
124 UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
125 UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
126 UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
127 UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
128 UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
129 UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
130 UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
131 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
132 } ITBT_PCILTR_DATA;
133
134 ///
135 /// TCSS Data Hob
136 ///
137 typedef struct {
138 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gTcssHobGuid
139 TCSS_DATA TcssData; ///< Offset 24 TCSS data definition.
140 ITBT_PCILTR_DATA PcieItbtLtrData[MAX_ITBT_PCIE_PORT];
141 } TCSS_DATA_HOB;
142
143 ///
144 /// TCSS SSID Data Hob
145 ///
146 typedef struct {
147 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID
148 SVID_SID_SKIP_TABLE *TcssSsidTable; ///< TCSS SSID table
149 UINT16 NumberOfTcssSsidTable; ///< number of TCSS SSID table
150 UINT8 Reserved[2]; ///< Reserved for Hob size allignment
151 } TCSS_DATA_SSID_HOB;
152 #pragma pack (pop)
153 #endif
TCSS_DATA::TbtImrStatus
TBT_IMR_STATUS TbtImrStatus
Tbt FW IMR Status.
Definition: TcssDataHob.h:104
TCSS_DATA_SSID_HOB::NumberOfTcssSsidTable
UINT16 NumberOfTcssSsidTable
number of TCSS SSID table
Definition: TcssDataHob.h:149
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_DATA::TcssRtd3
UINT8 TcssRtd3
TCSS RTD3.
Definition: TcssDataHob.h:113
TCSS_DATA::Rsvd
UINT32 Rsvd
Deprecate < Indicate the extra segment of iTBT PCIe is enabled or not.
Definition: TcssDataHob.h:101
TBT_IMR_STATUS::Valid
UINT32 Valid
Bits 30 - 00 = untrusted FW, 01 = successful authentication.
Definition: TcssDataHob.h:76
TCSS_DATA_SSID_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
GUID.
Definition: TcssDataHob.h:147
TCSS_DATA::ItbtPcieFuncMap
UINT32 ItbtPcieFuncMap
iTBT PCIE RP 0-3 Function Map
Definition: TcssDataHob.h:106
TCSS_DATA_SSID_HOB
TCSS SSID Data Hob.
Definition: TcssDataHob.h:146
MG_IMR_STATUS
Structure for MG image status from IMR.
Definition: TcssDataHob.h:84
TCSS_DATA::TcssxDCIIrq
UINT8 TcssxDCIIrq
iTBT xDCI APIC IRQ number
Definition: TcssDataHob.h:112
MG_IMR_STATUS::ErrorCode
UINT32 ErrorCode
Bits 29:22.
Definition: TcssDataHob.h:89
TBT_IMR_STATUS::Reserved
UINT32 Reserved
Bits 21:16.
Definition: TcssDataHob.h:74
TCSS_DATA
TCSS data definition.
Definition: TcssDataHob.h:98
TCSS_DATA::ItbtForcePower
UINT8 ItbtForcePower
iTBT Force Power status
Definition: TcssDataHob.h:114
TCSS_DATA::IomFwVersion
UINT32 IomFwVersion
IOM FW version.
Definition: TcssDataHob.h:102
TCSS_DATA::TcssxDCIInt
UINT8 TcssxDCIInt
iTBT xDCI Int Pin number
Definition: TcssDataHob.h:111
TCSS_DATA::IOMReady
UINT32 IOMReady
Indicate the IOM ready.
Definition: TcssDataHob.h:99
TBT_IMR_STATUS::Done
UINT32 Done
Bits 31 - 01 = FW download to IMR is done.
Definition: TcssDataHob.h:77
TCSS_DATA::DeepstTcState
UINT8 DeepstTcState
Maximum TC C State limit.
Definition: TcssDataHob.h:117
TCSS_DATA_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
Offset 0 - 23: GUID Hob type structure for gTcssHobGuid.
Definition: TcssDataHob.h:138
TCSS_DATA::MgImrStatus
MG_IMR_STATUS MgImrStatus
MG IMR Status.
Definition: TcssDataHob.h:115
MG_IMR_STATUS::MgFwVersion
UINT32 MgFwVersion
Bits 15:0.
Definition: TcssDataHob.h:87
MG_IMR_STATUS::Reserved
UINT32 Reserved
Bits 21:16.
Definition: TcssDataHob.h:88
TCSS_DATA::ItbtXhciEn
UINT8 ItbtXhciEn
ItbtPcieRpEn XHCI Device Enable.
Definition: TcssDataHob.h:108
TCSS_DATA::ItbtXdciEn
UINT8 ItbtXdciEn
ItbtPcieRpEn XDCI Device Enable.
Definition: TcssDataHob.h:109
TCSS_DATA_HOB::TcssData
TCSS_DATA TcssData
Offset 24 TCSS data definition.
Definition: TcssDataHob.h:139
MG_IMR_STATUS::Done
UINT32 Done
Bits 31 - 01 = FW download to IMR is done.
Definition: TcssDataHob.h:91
TCSS_DATA_HOB
TCSS Data Hob.
Definition: TcssDataHob.h:137
SiConfig.h
Si Config Block.
TBT_IMR_STATUS
Structure for Tbt firmware status from IMR.
Definition: TcssDataHob.h:70
TBT_IMR_STATUS::TbtFwVersion
UINT32 TbtFwVersion
Bits 15:0.
Definition: TcssDataHob.h:73
TBT_IMR_STATUS::ErrorCode
UINT32 ErrorCode
Bits 29:22.
Definition: TcssDataHob.h:75
MG_IMR_STATUS::Valid
UINT32 Valid
Bits 30 - 00 = untrusted FW, 01 = successful authentication.
Definition: TcssDataHob.h:90
TCSS_DATA_SSID_HOB::TcssSsidTable
SVID_SID_SKIP_TABLE * TcssSsidTable
TCSS SSID table.
Definition: TcssDataHob.h:148
TCSS_DATA::IomFwEngrVersion
UINT32 IomFwEngrVersion
IOM FW Engineer version. Non-zero value used to identify engineering versions / hotfixes....
Definition: TcssDataHob.h:103
TCSS_DATA::TcssIomVccSt
UINT8 TcssIomVccSt
IOM VCCST request.
Definition: TcssDataHob.h:116
TCSS_DATA::ItbtPcieSegMap
UINT32 ItbtPcieSegMap
iTBT PCIE RP 0-3 Segment Map
Definition: TcssDataHob.h:105
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TcssInfoLib.h File Reference

Header file for SmmTcss Private Info Lib implementation. More...

#include <Uefi.h>
#include <Library/BaseLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
Include dependency graph for TcssInfoLib.h:

Go to the source code of this file.

Functions

UINT64 | GetTbtDmaBusNumber (VOID)
GetTbtDmaBusNumber: Get TbtDma Bus Number. More...
UINT64 | GetTbtDmaDevNumber (VOID)
GetTbtDmaDevNumber: Get TbtDma Dev Number. More...
UINT64 | GetTbtDma0FuncNumber (VOID)
GetTbtDma0FuncNumber: Get TbtDma Fun Number. More...
UINT64 | GetCpuXhciBusNumber (VOID)
GetCpuXhciBusNumber: Get CpuXhci Bus Number. More...
UINT64 | GetCpuXhciDevNumber (VOID)
GetCpuXhciDevNumber: Get CpuXhci Dev Number. More...
UINT64 | GetCpuXhciFuncNumber (VOID)
GetCpuXhciFunNumber: Get CpuXhci Fun Number. More...
UINT64 | GetITbtPcieDevNumber (VOID)
GetITbtPcieDevNumber: Get ITbt PCIe Dev Number. More...

Detailed Description

Header file for SmmTcss Private Info Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssInfoLib.h.

Function Documentation

◆ GetCpuXhciBusNumber()

UINT64 GetCpuXhciBusNumber ( VOID )

GetCpuXhciBusNumber: Get CpuXhci Bus Number.

Return values
PCI bus number for CpuXhci

◆ GetCpuXhciDevNumber()

UINT64 GetCpuXhciDevNumber ( VOID )

GetCpuXhciDevNumber: Get CpuXhci Dev Number.

Return values
PCI dev number for CpuXhci

◆ GetCpuXhciFuncNumber()

UINT64 GetCpuXhciFuncNumber ( VOID )

GetCpuXhciFunNumber: Get CpuXhci Fun Number.

Return values
PCI fun number for CpuXhci

◆ GetITbtPcieDevNumber()

UINT64 GetITbtPcieDevNumber ( VOID )

GetITbtPcieDevNumber: Get ITbt PCIe Dev Number.

Return values
ITbt PCIe dev number for ITbt PCIe

◆ GetTbtDma0FuncNumber()

UINT64 GetTbtDma0FuncNumber ( VOID )

GetTbtDma0FuncNumber: Get TbtDma Fun Number.

Return values
PCI fun number for TbtDma

◆ GetTbtDmaBusNumber()

UINT64 GetTbtDmaBusNumber ( VOID )

GetTbtDmaBusNumber: Get TbtDma Bus Number.

Return values
PCI bus number for TbtDma

◆ GetTbtDmaDevNumber()

UINT64 GetTbtDmaDevNumber ( VOID )

GetTbtDmaDevNumber: Get TbtDma Dev Number.

Return values
PCI dev number for TbtDma
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TcssInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for SmmTcss Private Info Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _SMM_TCSS_INFO_LIB_H_
37 #define _SMM_TCSS_INFO_LIB_H_
38
39 #include <Uefi.h>
40 #include <Library/BaseLib.h>
41 #include <Library/DebugLib.h>
42 #include <Library/IoLib.h>
43
44 /**
45 GetTbtDmaBusNumber: Get TbtDma Bus Number
46
47 @retval PCI bus number for TbtDma
48 **/
49 UINT64
50 GetTbtDmaBusNumber (
51 VOID
52 );
53
54 /**
55 GetTbtDmaDevNumber: Get TbtDma Dev Number
56
57 @retval PCI dev number for TbtDma
58 **/
59 UINT64
60 GetTbtDmaDevNumber (
61 VOID
62 );
63
64 /**
65 GetTbtDma0FuncNumber: Get TbtDma Fun Number
66
67 @retval PCI fun number for TbtDma
68 **/
69 UINT64
70 GetTbtDma0FuncNumber (
71 VOID
72 );
73
74 /**
75 GetCpuXhciBusNumber: Get CpuXhci Bus Number
76
77 @retval PCI bus number for CpuXhci
78 **/
79 UINT64
80 GetCpuXhciBusNumber (
81 VOID
82 );
83
84 /**
85 GetCpuXhciDevNumber: Get CpuXhci Dev Number
86
87 @retval PCI dev number for CpuXhci
88 **/
89 UINT64
90 GetCpuXhciDevNumber (
91 VOID
92 );
93
94 /**
95 GetCpuXhciFunNumber: Get CpuXhci Fun Number
96
97 @retval PCI fun number for CpuXhci
98 **/
99 UINT64
100 GetCpuXhciFuncNumber (
101 VOID
102 );
103
104 /**
105 GetITbtPcieDevNumber: Get ITbt PCIe Dev Number
106
107 @retval ITbt PCIe dev number for ITbt PCIe
108 **/
109 UINT64
110 GetITbtPcieDevNumber (
111 VOID
112 );
113
114 #endif
GetTbtDmaBusNumber
UINT64 GetTbtDmaBusNumber(VOID)
GetTbtDmaBusNumber: Get TbtDma Bus Number.
GetCpuXhciBusNumber
UINT64 GetCpuXhciBusNumber(VOID)
GetCpuXhciBusNumber: Get CpuXhci Bus Number.
GetITbtPcieDevNumber
UINT64 GetITbtPcieDevNumber(VOID)
GetITbtPcieDevNumber: Get ITbt PCIe Dev Number.
GetTbtDmaDevNumber
UINT64 GetTbtDmaDevNumber(VOID)
GetTbtDmaDevNumber: Get TbtDma Dev Number.
GetTbtDma0FuncNumber
UINT64 GetTbtDma0FuncNumber(VOID)
GetTbtDma0FuncNumber: Get TbtDma Fun Number.
GetCpuXhciFuncNumber
UINT64 GetCpuXhciFuncNumber(VOID)
GetCpuXhciFunNumber: Get CpuXhci Fun Number.
GetCpuXhciDevNumber
UINT64 GetCpuXhciDevNumber(VOID)
GetCpuXhciDevNumber: Get CpuXhci Dev Number.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
TcssPeiConfig.h File Reference

TCSS PEI policy. More...

#include <ConfigBlock.h>
#include <UsbConfig.h>
#include <TcssInfo.h>
Include dependency graph for TcssPeiConfig.h:

Go to the source code of this file.

Classes

struct | IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. More...
struct | IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC. More...
struct | PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC. More...
struct | SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number. More...
struct | TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. More...
struct | TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. More...
struct | TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS. More...
struct | TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. More...
struct | TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA. More...

Detailed Description

TCSS PEI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_CONFIG_H_
36 #define _TCSS_PEI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <UsbConfig.h>
40 #include <TcssInfo.h>
41
42 #define TCSS_PEI_CONFIG_REVISION 4
43 extern EFI_GUID gTcssPeiConfigGuid;
44
45 #pragma pack (push,1)
46
47
48 #define MAX_IOM_AUX_BIAS_COUNT 4
49
50 ///
51 /// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
52 /// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
53 /// IOM needs know Pull-Up and Pull-Down pin for Bias control
54 ///
55 typedef struct {
56 UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
57 UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
58 } IOM_AUX_ORI_PAD_CONFIG;
59
60 ///
61 /// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
62 ///
63
64 typedef struct {
65 UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
66 UINT32 UsbOverride; ///< IOM to override USB connection.
67 UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
68 UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
69 } IOM_INTERFACE_CONFIG;
70
71 ///
72 /// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
73 ///
74 typedef struct {
75 UINT8 PmcPdEnable; ///< PMC PD Solution Enable
76 UINT8 Rsvd[3];
77 } PMC_INTERFACE_CONFIG;
78
79 ///
80 /// The SA XDCI INT Pin and IRQ number
81 ///
82 typedef struct {
83 UINT8 IntPing; ///< Int Pin Number
84 UINT8 Irq; ///< Irq Number
85 UINT16 Rsvd;
86 } SA_XDCI_IRQ_INT_CONFIG;
87
88 ///
89 /// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
90 ///
91 typedef struct {
92 UINT8 AcsEnabled; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
93 UINT8 DpcEnabled; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
94 UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
95 UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
96 UINT8 PtmEnabled; ///< Enables PTM capability
97
98 UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>
99 UINT8 SlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
100 UINT8 SlotPowerLimitScale; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
101 UINT16 SlotPowerLimitValue; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
102
103 UINT8 AdvancedErrorReporting; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
104 UINT8 UnsupportedRequestReport; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
105 UINT8 FatalErrorReport; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
106 UINT8 NoFatalErrorReport; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
107 UINT8 CorrectableErrorReport; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
108 UINT8 SystemErrorOnFatalError; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
109 UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
110 UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
111
112 UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Reporting, Max Snoop Latency.
113 UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Reporting, Max Non-Snoop Latency.
114 UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Snoop Latency Override Mode.
115 UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Snoop Latency Override Multiplier.
116 UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Snoop Latency Override Value.
117 UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
118 UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
119 UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Reporting, Non-Snoop Latency Override Value.
120 UINT8 ForceLtrOverride; ///< <b>0: Disable</b>; 1: Enable.
121 UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
122 } TCSS_PCIE_PORT_POLICY;
123
124 ///
125 /// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
126 ///
127 typedef struct {
128 TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];
129 } TCSS_PCIE_PEI_POLICY;
130
131 ///
132 /// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
133 ///
134 typedef struct {
135 UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
136 UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
137 } TCSS_IOM_ORI_OVERRIDE;
138
139 ///
140 /// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
141 ///
142 typedef struct {
143 IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
144 TCSS_IOM_ORI_OVERRIDE IomOverrides;
145 IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
146 PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
147 UINT8 TcStateLimit; ///< Tcss C-State deep stage
148 UINT8 Reserved[3]; ///< Reserved bytes for future use
149 } TCSS_IOM_PEI_CONFIG;
150
151 ///
152 /// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
153 ///
154 typedef struct {
155 SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and Irq setting
156 UINT8 EnableTcssCovTypeA[MAX_TCSS_USB3_PORTS]; ///< Enable / Disable Type C Port X Convert to TypeA
157 UINT8 MappingPchXhciUsbA[MAX_TCSS_USB3_PORTS]; ///< PCH xhci port number for Type C Port x mapping
158 UINT8 IomStayInTCColdSeconds; ///< Set IOM stay in TC cold seconds.
159 UINT8 IomBeforeEnteringTCColdSeconds; ///< Set IOM before entering TC cold seconds.
160 UINT8 Rsvd[2]; ///< Reserved bytes for future use.
161 } TCSS_MISC_PEI_CONFIG;
162
163 ///
164 /// The TCSS_PEI_CONFIG block describes TCSS settings for SA.
165 ///
166 typedef struct {
167 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
168 TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config
169 USB_CONFIG UsbConfig; ///< USB config is shared between PCH and SA.
170 TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config
171 TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config
172 } TCSS_PEI_CONFIG;
173
174 #pragma pack (pop)
175
176 #endif /* _TCSS_PEI_CONFIG_H_ */
IOM_AUX_ORI_PAD_CONFIG
The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
Definition: TcssPeiConfig.h:55
TCSS_IOM_PEI_CONFIG::IomInterface
IOM_INTERFACE_CONFIG IomInterface
Config settings are BIOS <-> IOM interface.
Definition: TcssPeiConfig.h:145
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_PCIE_PORT_POLICY::DpcEnabled
UINT8 DpcEnabled
Downstream Port Containment. 0: Disable; 1: Enable
Definition: TcssPeiConfig.h:93
TCSS_PCIE_PORT_POLICY::RpDpcExtensionsEnabled
UINT8 RpDpcExtensionsEnabled
RP Extensions for Downstream Port Containment. 0: Disable; 1: Enable
Definition: TcssPeiConfig.h:94
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideValue
UINT16 NonSnoopLatencyOverrideValue
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
Definition: TcssPeiConfig.h:119
USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to ...
Definition: UsbConfig.h:106
TCSS_IOM_PEI_CONFIG::PmcInterface
PMC_INTERFACE_CONFIG PmcInterface
Config settings for BIOS <-> PMC interface.
Definition: TcssPeiConfig.h:146
TCSS_PCIE_PORT_POLICY::SystemErrorOnNonFatalError
UINT8 SystemErrorOnNonFatalError
Indicate whether the System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:109
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMultiplier
UINT8 SnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:115
IOM_INTERFACE_CONFIG::D3ColdEnable
UINT32 D3ColdEnable
Enable/disable D3 Cold support in TCSS.
Definition: TcssPeiConfig.h:67
PMC_INTERFACE_CONFIG::PmcPdEnable
UINT8 PmcPdEnable
PMC PD Solution Enable.
Definition: TcssPeiConfig.h:75
TCSS_PCIE_PORT_POLICY::SlotPowerLimitValue
UINT16 SlotPowerLimitValue
(Test) Specifies upper limit on power supplies by slot. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:101
TCSS_IOM_PEI_CONFIG
The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiConfig.h:142
TCSS_PCIE_PORT_POLICY::LtrEnable
UINT8 LtrEnable
Latency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:95
IOM_INTERFACE_CONFIG
The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
Definition: TcssPeiConfig.h:64
TCSS_PCIE_PORT_POLICY::AcsEnabled
UINT8 AcsEnabled
Indicate whether the ACS is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:92
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideValue
UINT16 SnoopLatencyOverrideValue
Latency Tolerance Reporting, Snoop Latency Override Value.
Definition: TcssPeiConfig.h:116
TCSS_PCIE_PORT_POLICY::NoFatalErrorReport
UINT8 NoFatalErrorReport
Indicate whether the No Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:106
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
TCSS_PCIE_PORT_POLICY::UnsupportedRequestReport
UINT8 UnsupportedRequestReport
Indicate whether the Unsupported Request Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:104
TCSS_PCIE_PORT_POLICY::SystemErrorOnFatalError
UINT8 SystemErrorOnFatalError
Indicate whether the System Error on Fatal Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:108
PMC_INTERFACE_CONFIG
The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC.
Definition: TcssPeiConfig.h:74
TCSS_PCIE_PORT_POLICY::FatalErrorReport
UINT8 FatalErrorReport
Indicate whether the Fatal Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:105
TCSS_PEI_CONFIG::UsbConfig
USB_CONFIG UsbConfig
USB config is shared between PCH and SA.
Definition: TcssPeiConfig.h:169
TCSS_PCIE_PEI_POLICY
TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.
Definition: TcssPeiConfig.h:127
TCSS_PCIE_PORT_POLICY::ForceLtrOverride
UINT8 ForceLtrOverride
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:120
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PCIE_PORT_POLICY::SnoopLatencyOverrideMode
UINT8 SnoopLatencyOverrideMode
Latency Tolerance Reporting, Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:114
TCSS_IOM_ORI_OVERRIDE::AuxOri
UINT16 AuxOri
Bits defining value for IOM Aux Orientation Register.
Definition: TcssPeiConfig.h:135
TCSS_PCIE_PORT_POLICY::SlotNumber
UINT8 SlotNumber
Indicates the slot number for the root port. Default is the value as root port index.
Definition: TcssPeiConfig.h:99
TCSS_PCIE_PORT_POLICY::SlotPowerLimitScale
UINT8 SlotPowerLimitScale
(Test) Specifies scale used for slot power limit value. Leave as 0 to set to default....
Definition: TcssPeiConfig.h:100
TCSS_PCIE_PORT_POLICY::SystemErrorOnCorrectableError
UINT8 SystemErrorOnCorrectableError
Indicate whether the System Error on Correctable Error is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:110
IOM_AUX_ORI_PAD_CONFIG::GpioPullN
UINT32 GpioPullN
GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
Definition: TcssPeiConfig.h:56
SA_XDCI_IRQ_INT_CONFIG
The SA XDCI INT Pin and IRQ number.
Definition: TcssPeiConfig.h:82
SA_XDCI_IRQ_INT_CONFIG::IntPing
UINT8 IntPing
Int Pin Number.
Definition: TcssPeiConfig.h:83
TCSS_PCIE_PORT_POLICY
The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.
Definition: TcssPeiConfig.h:91
TCSS_PEI_CONFIG::PciePolicy
TCSS_PCIE_PEI_POLICY PciePolicy
The PCIe Config.
Definition: TcssPeiConfig.h:168
SA_XDCI_IRQ_INT_CONFIG::Irq
UINT8 Irq
Irq Number.
Definition: TcssPeiConfig.h:84
TCSS_MISC_PEI_CONFIG::IomBeforeEnteringTCColdSeconds
UINT8 IomBeforeEnteringTCColdSeconds
Set IOM before entering TC cold seconds.
Definition: TcssPeiConfig.h:159
TCSS_PCIE_PORT_POLICY::LtrConfigLock
UINT8 LtrConfigLock
0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:121
IOM_INTERFACE_CONFIG::VccSt
UINT32 VccSt
IOM VCCST request. (Not equal to actual VCCST value)
Definition: TcssPeiConfig.h:65
TCSS_PEI_CONFIG::IomConfig
TCSS_IOM_PEI_CONFIG IomConfig
The Iom Config.
Definition: TcssPeiConfig.h:170
TCSS_PEI_CONFIG::MiscConfig
TCSS_MISC_PEI_CONFIG MiscConfig
The MISC Config.
Definition: TcssPeiConfig.h:171
TCSS_MISC_PEI_CONFIG::IomStayInTCColdSeconds
UINT8 IomStayInTCColdSeconds
Set IOM stay in TC cold seconds.
Definition: TcssPeiConfig.h:158
TCSS_PCIE_PORT_POLICY::CorrectableErrorReport
UINT8 CorrectableErrorReport
Indicate whether the Correctable Error Report is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:107
TCSS_PEI_CONFIG
The TCSS_PEI_CONFIG block describes TCSS settings for SA.
Definition: TcssPeiConfig.h:166
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMultiplier
UINT8 NonSnoopLatencyOverrideMultiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
Definition: TcssPeiConfig.h:118
TCSS_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiConfig.h:167
TCSS_PCIE_PORT_POLICY::PtmEnabled
UINT8 PtmEnabled
Enables PTM capability.
Definition: TcssPeiConfig.h:96
IOM_INTERFACE_CONFIG::UsbOverride
UINT32 UsbOverride
IOM to override USB connection.
Definition: TcssPeiConfig.h:66
TCSS_PCIE_PORT_POLICY::Aspm
UINT8 Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
Definition: TcssPeiConfig.h:98
TCSS_PCIE_PORT_POLICY::LtrMaxNoSnoopLatency
UINT16 LtrMaxNoSnoopLatency
Latency Tolerance Reporting, Max Non-Snoop Latency.
Definition: TcssPeiConfig.h:113
TCSS_MISC_PEI_CONFIG::SaXdci
SA_XDCI_IRQ_INT_CONFIG SaXdci
System Agent Xdci Int Pin and Irq setting.
Definition: TcssPeiConfig.h:155
TCSS_IOM_ORI_OVERRIDE
The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
Definition: TcssPeiConfig.h:134
TCSS_MISC_PEI_CONFIG
The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.
Definition: TcssPeiConfig.h:154
IOM_INTERFACE_CONFIG::D3HotEnable
UINT32 D3HotEnable
Enable/disable D3 Hot support in TCSS.
Definition: TcssPeiConfig.h:68
TCSS_PCIE_PORT_POLICY::NonSnoopLatencyOverrideMode
UINT8 NonSnoopLatencyOverrideMode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
Definition: TcssPeiConfig.h:117
TCSS_PCIE_PORT_POLICY::LtrMaxSnoopLatency
UINT16 LtrMaxSnoopLatency
Latency Tolerance Reporting, Max Snoop Latency.
Definition: TcssPeiConfig.h:112
TCSS_PCIE_PORT_POLICY::AdvancedErrorReporting
UINT8 AdvancedErrorReporting
Indicate whether the Advanced Error Reporting is enabled. 0: Disable; 1: Enable.
Definition: TcssPeiConfig.h:103
IOM_AUX_ORI_PAD_CONFIG::GpioPullP
UINT32 GpioPullP
GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
Definition: TcssPeiConfig.h:57
TCSS_IOM_ORI_OVERRIDE::HslOri
UINT16 HslOri
Bits defining value for IOM HSL Orientation Register.
Definition: TcssPeiConfig.h:136
TCSS_IOM_PEI_CONFIG::TcStateLimit
UINT8 TcStateLimit
Tcss C-State deep stage.
Definition: TcssPeiConfig.h:147
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssPeiPreMemConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Classes
TcssPeiPreMemConfig.h File Reference

TCSS PEI PreMem policy. More...

#include <ConfigBlock.h>
Include dependency graph for TcssPeiPreMemConfig.h:

Go to the source code of this file.

Classes

union | TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS. More...
struct | TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS. More...
struct | TCSS_MISC_PEI_PREMEM_CONFIG
The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS. More...
struct | TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings. More...

Detailed Description

TCSS PEI PreMem policy.

Copyright
INTEL CONFIDENTIAL Copyright 2016 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TcssPeiPreMemConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TcssPeiPreMemConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
TcssPeiPreMemConfig.h
Go to the documentation of this file.
1 /** @file
2 TCSS PEI PreMem policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2016 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TCSS_PEI_PREMEM_CONFIG_H_
36 #define _TCSS_PEI_PREMEM_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define TCSS_PEI_PREMEM_CONFIG_REVISION 2
41 extern EFI_GUID gTcssPeiPreMemConfigGuid;
42
43 #pragma pack (push,1)
44
45 ///
46 /// The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
47 ///
48 typedef union {
49 UINT32 TcssDevEn; ///< Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH
50 struct{
51 UINT32 TcssItbtPcie0En:1;
52 UINT32 TcssItbtPcie1En:1;
53 UINT32 TcssItbtPcie2En:1;
54 UINT32 TcssItbtPcie3En:1;
55 UINT32 :4;
56 UINT32 TcssXhciEn:1;
57 UINT32 TcssXdciEn:1;
58 UINT32 TcssDma0En:1;
59 UINT32 TcssDma1En:1;
60 UINT32 :20;
61 } TcssDevEnBit;
62 } TCSS_DEVEN_PEI_PREMEM_CONFIG;
63
64 ///
65 /// The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
66 ///
67 typedef struct {
68 UINT32 UsbTcPortEn : 4; ///< bitmap for USB Type C enabled ports
69 UINT32 Rsvd : 28; ///< Reserved bytes for future use
70 } TCSS_USBTC_PEI_PERMEM_CONFIG;
71
72 /**
73 The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.\n
74 <b>Revision 1</b>: - Initial version.
75 **/
76 typedef struct {
77 /**
78 This is policy to control Multiple Segment setting.
79 When Disabled all the iTBT PCIe RP are located at Segment0
80 When Enabled all the iTBT PCIe RP are located at Segment1,
81 FSP Wrapper need to update PCIEXBAR and PcdPciExpressRegionLength to 512MB
82 prior to FspmWrapperPeim.
83 <b>0: Disable</b>, 1: Enable
84 **/
85 UINT8 PcieMultipleSegmentEnabled; /// Deprecate
86 UINT8 Rsvd[3]; ///< Reserved bytes for future use, align to multiple 4
87 } TCSS_MISC_PEI_PREMEM_CONFIG;
88
89 /**
90 This configuration block describes TCSS settings.\n
91 <b>Revision 1</b>:
92 - Initial version.
93 <b>Revision 2</b>:
94 - Deprecate PcieMultipleSegmentEnabled
95 **/
96 typedef struct {
97 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
98 TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig;///< TCSS DEVEN
99 TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig;///< USB Type C Port Configuration
100 TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig; ///< The MISC PreMem Config
101 } TCSS_PEI_PREMEM_CONFIG;
102
103 #pragma pack (pop)
104
105 #endif /* _TCSS_PEI_PREMEM_CONFIG_H_ */
ConfigBlock.h
Header file for Config Block Lib implementation.
TCSS_USBTC_PEI_PERMEM_CONFIG::UsbTcPortEn
UINT32 UsbTcPortEn
bitmap for USB Type C enabled ports
Definition: TcssPeiPreMemConfig.h:68
TCSS_DEVEN_PEI_PREMEM_CONFIG::TcssDevEn
UINT32 TcssDevEn
Maps to bits in TCSS_DEVEN_0_0_0_MCHBAR_IMPH.
Definition: TcssPeiPreMemConfig.h:49
TCSS_PEI_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: TcssPeiPreMemConfig.h:97
TCSS_DEVEN_PEI_PREMEM_CONFIG
The TCSS_DEVEN_PEI_PREMEM_CONFIG block describes Device Enable settings for TCSS.
Definition: TcssPeiPreMemConfig.h:48
TCSS_MISC_PEI_PREMEM_CONFIG
The TCSS_MISC_PEI_PREMEM_CONFIG block describes MISC settings for TCSS.
Definition: TcssPeiPreMemConfig.h:76
TCSS_PEI_PREMEM_CONFIG
This configuration block describes TCSS settings.
Definition: TcssPeiPreMemConfig.h:96
TCSS_USBTC_PEI_PERMEM_CONFIG::Rsvd
UINT32 Rsvd
Reserved bytes for future use.
Definition: TcssPeiPreMemConfig.h:69
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TCSS_PEI_PREMEM_CONFIG::DevEnConfig
TCSS_DEVEN_PEI_PREMEM_CONFIG DevEnConfig
TCSS DEVEN.
Definition: TcssPeiPreMemConfig.h:98
TCSS_PEI_PREMEM_CONFIG::UsbTcConfig
TCSS_USBTC_PEI_PERMEM_CONFIG UsbTcConfig
USB Type C Port Configuration.
Definition: TcssPeiPreMemConfig.h:99
TCSS_PEI_PREMEM_CONFIG::MiscConfig
TCSS_MISC_PEI_PREMEM_CONFIG MiscConfig
The MISC PreMem Config.
Definition: TcssPeiPreMemConfig.h:100
TCSS_USBTC_PEI_PERMEM_CONFIG
The TCSS_USBTC_PEI_PERMEM_CONFIG block describes IOM settings for TCSS.
Definition: TcssPeiPreMemConfig.h:67
TCSS_MISC_PEI_PREMEM_CONFIG::PcieMultipleSegmentEnabled
UINT8 PcieMultipleSegmentEnabled
This is policy to control Multiple Segment setting.
Definition: TcssPeiPreMemConfig.h:85
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TelemetryLib.h File Reference

Header file for TelemetryLib. More...

Go to the source code of this file.

Functions

EFI_STATUS | GetCpuCrashLogCapability (OUT TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap)
Find the address of Cpu CrashLog ID. More...
UINT32 | GetCpuCrashLogBarAddress (IN TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap)
This function returns the value of CPU CrashLog BAR. More...
EFI_STATUS | CpuCrashLogClear (VOID)
This function clears cpu crash log. More...
EFI_STATUS | CpuCrashLogReArm (VOID)
This function send re-arm command to rearm the trigger. More...
VOID | GetCrashLogHeader (IN UINT32 BaseAddr, OUT CPU_CRASHLOG_HEADER *CrashLogHeaderBuff)
Get CPU CrashLog Header data. More...
EFI_STATUS | CpuCrashLogDiscovery (OUT CPU_CRASHLOG_STRUCT *CrashLogStruct)
This function discovers CPU crashLog and gets the size of each. More...

Detailed Description

Header file for TelemetryLib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 -2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TelemetryLib.h.

Function Documentation

◆ CpuCrashLogClear()

EFI_STATUS CpuCrashLogClear ( VOID )

This function clears cpu crash log.

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Mailbox command failed with an error
EFI_TIMEOUT | Mailbox command did not complete

◆ CpuCrashLogDiscovery()

EFI_STATUS CpuCrashLogDiscovery ( OUT CPU_CRASHLOG_STRUCT * CrashLogStruct )

This function discovers CPU crashLog and gets the size of each.

Parameters
[out] CrashLogStruct Pointer to CrashLog Discovery Data
Return values
EFI_UNSUPPORTED | Cpu CrashLog is not supported
EFI_SUCCESS | Cpu CrashLog is supported

◆ CpuCrashLogReArm()

EFI_STATUS CpuCrashLogReArm ( VOID )

This function send re-arm command to rearm the trigger.

Return values
EFI_SUCCESS | Command was executed successfully
EFI_DEVICE_ERROR | Mailbox command failed with an error
EFI_TIMEOUT | Mailbox command did not complete

◆ GetCpuCrashLogBarAddress()

UINT32 GetCpuCrashLogBarAddress ( IN TEL_CRASHLOG_DEVSC_CAP * CrashLogDevscCap )

This function returns the value of CPU CrashLog BAR.

Parameters
[in] CrashLogDevscCap Structure of CrashLog DEVSC Data
Return values
BaseAddr MMIO address of CrashLog BAR

◆ GetCpuCrashLogCapability()

EFI_STATUS GetCpuCrashLogCapability ( OUT TEL_CRASHLOG_DEVSC_CAP * CrashLogDevscCap )

Find the address of Cpu CrashLog ID.

Parameters
[out] CrashLogDevscCap Pointer to structure of CrashLog DEVSC Data
Return values
EFI_UNSUPPORTED | Cpu CrashLog ID not found
EFI_SUCCESS | Cpu CrashLog ID found

◆ GetCrashLogHeader()

VOID GetCrashLogHeader | ( | IN UINT32 | BaseAddr,
 |  | OUT CPU_CRASHLOG_HEADER * | CrashLogHeaderBuff
 | ) |  |

Get CPU CrashLog Header data.

Parameters
[in] | BaseAddr | Pci configuration space MMIO address of CrashLog BAR
[out] | *CrashLogHeaderBuff | Pointer to CrashLog Discovery Data
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TelemetryLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for TelemetryLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 -2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TELEMETRY_LIB_H_
36 #define _TELEMETRY_LIB_H_
37
38 //
39 // Structure of DEVSC registers
40 //
41 typedef union {
42 struct {
43 UINT32 PcieCapId : 16; ///< PCI Express Capability ID
44 UINT32 CapVer : 4; ///< Capability Version
45 UINT32 NextCapOffset : 12; ///< Next Capability Offset
46 } Fields;
47 UINT32 Data;
48 } CAP_DATA;
49
50 typedef union {
51 struct {
52 UINT64 DevscVenId : 16; ///< DVSEC_VENID
53 UINT64 DevscVer : 4; ///< DVSEC_VER
54 UINT64 DevscLen : 12; ///< DVSEC_LEN
55 UINT64 DevscId : 16; ///< DVSEC_ID
56 UINT64 NumEntries : 8; ///< Number of entries, describes the number of telemetry aggregators that would exist in this capability lookup table.
57 UINT64 EntrySize : 8; ///< Entry Size in DWORDS
58 } Fields;
59 UINT64 Data64;
60 UINT32 Data32[2];
61 } DEVSC_DATA;
62
63 typedef union {
64 struct {
65 UINT32 TBir : 3; ///< tBIR, The BAR to be used
66 UINT32 DiscoveryTableOffset : 29; ///< Discovery Table Offset
67 } Fields;
68 UINT32 Data;
69 } DISCOVERY_DATA;
70
71 typedef struct {
72 CAP_DATA CapData;
73 DEVSC_DATA DevscData;
74 DISCOVERY_DATA DiscoveryData;
75 } TEL_CRASHLOG_DEVSC_CAP;
76
77 //
78 // Structure of Cpu CrashLog Header
79 //
80 typedef union {
81 struct {
82 UINT32 AccessType : 4; ///< Access Type
83 UINT32 CrashType : 4; ///< Crash Type
84 UINT32 Count : 8;
85 UINT32 Reserved : 16;
86 } Fields;
87 UINT32 HeaderData;
88 } CPU_CRASHLOG_HEADER_DATA;
89
90 typedef union {
91 struct {
92 UINT32 CrashlogSupported : 1;
93 UINT32 DisableSupported : 1;
94 UINT32 DiscoveryMechanism : 2;
95 UINT32 ManualTriggerSupported : 1;
96 UINT32 ClearSupported : 1;
97 UINT32 TriggerOnAllResetSupported : 1;
98 UINT32 ReArmSupported : 1;
99 UINT32 Reserved : 20;
100 UINT32 CrashlogRequestorFlowInProgressStatus : 1;
101 UINT32 ReArmStatus : 1;
102 UINT32 TriggerOnAllResetStatus : 1;
103 UINT32 DisableStatus : 1;
104 } Fields;
105 UINT32 Guid; ///< GLOBALLY_UNIQUE_ID
106 } CPU_CRASHLOG_CAPABILITY;
107
108 typedef struct {
109 CPU_CRASHLOG_HEADER_DATA CrashlogHeaderData;
110 CPU_CRASHLOG_CAPABILITY CrashlogCapability;
111 } CPU_CRASHLOG_HEADER;
112
113 //
114 // Structure of Cpu CrashLog Buffer
115 //
116 typedef union {
117 struct {
118 UINT32 DataBuffAddress; ///< Base address within this BAR for the crashLog data buffer.
119 UINT32 DataBuffSize; ///< Number of dwords of data contained in the crashLog buffer.
120 } Fields;
121 UINT64 Data;
122 } CPU_CRASHLOG_BUFFER;
123
124 //
125 // Structure of Cpu CrashLog Struct
126 //
127 typedef struct {
128 CPU_CRASHLOG_BUFFER MainBuffer;
129 CPU_CRASHLOG_BUFFER TelemetryBuffer;
130 CPU_CRASHLOG_BUFFER TraceBuffer;
131 } CPU_CRASHLOG_STRUCT;
132
133 /**
134 Find the address of Cpu CrashLog ID
135
136 @param[out] CrashLogDevscCap Pointer to structure of CrashLog DEVSC Data
137
138 @retval EFI_UNSUPPORTED Cpu CrashLog ID not found
139 @retval EFI_SUCCESS Cpu CrashLog ID found
140 **/
141 EFI_STATUS
142 GetCpuCrashLogCapability (
143 OUT TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap
144 );
145
146 /**
147 This function returns the value of CPU CrashLog BAR.
148
149 @param[in] CrashLogDevscCap Structure of CrashLog DEVSC Data
150
151 @retval BaseAddr MMIO address of CrashLog BAR
152 **/
153 UINT32
154 GetCpuCrashLogBarAddress (
155 IN TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap
156 );
157
158 /**
159 This function clears cpu crash log
160
161 @retval EFI_SUCCESS Command was executed successfully
162 @retval EFI_DEVICE_ERROR Mailbox command failed with an error
163 @retval EFI_TIMEOUT Mailbox command did not complete
164 **/
165 EFI_STATUS
166 CpuCrashLogClear (
167 VOID
168 );
169
170 /**
171 This function send re-arm command to rearm the trigger
172
173 @retval EFI_SUCCESS Command was executed successfully
174 @retval EFI_DEVICE_ERROR Mailbox command failed with an error
175 @retval EFI_TIMEOUT Mailbox command did not complete
176 **/
177 EFI_STATUS
178 CpuCrashLogReArm (
179 VOID
180 );
181
182 /**
183 Get CPU CrashLog Header data
184
185 @param[in] BaseAddr Pci configuration space MMIO address of CrashLog BAR
186 @param[out] *CrashLogHeaderBuff Pointer to CrashLog Discovery Data
187 **/
188 VOID
189 GetCrashLogHeader (
190 IN UINT32 BaseAddr,
191 OUT CPU_CRASHLOG_HEADER *CrashLogHeaderBuff
192 );
193
194 /**
195 This function discovers CPU crashLog and gets the size of each
196
197 @param[out] CrashLogStruct Pointer to CrashLog Discovery Data
198
199 @retval EFI_UNSUPPORTED Cpu CrashLog is not supported
200 @retval EFI_SUCCESS Cpu CrashLog is supported
201 **/
202 EFI_STATUS
203 CpuCrashLogDiscovery (
204 OUT CPU_CRASHLOG_STRUCT *CrashLogStruct
205 );
206 #endif // _TELEMETRY_LIB_H_
CpuCrashLogDiscovery
EFI_STATUS CpuCrashLogDiscovery(OUT CPU_CRASHLOG_STRUCT *CrashLogStruct)
This function discovers CPU crashLog and gets the size of each.
GetCrashLogHeader
VOID GetCrashLogHeader(IN UINT32 BaseAddr, OUT CPU_CRASHLOG_HEADER *CrashLogHeaderBuff)
Get CPU CrashLog Header data.
CpuCrashLogClear
EFI_STATUS CpuCrashLogClear(VOID)
This function clears cpu crash log.
GetCpuCrashLogBarAddress
UINT32 GetCpuCrashLogBarAddress(IN TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap)
This function returns the value of CPU CrashLog BAR.
GetCpuCrashLogCapability
EFI_STATUS GetCpuCrashLogCapability(OUT TEL_CRASHLOG_DEVSC_CAP *CrashLogDevscCap)
Find the address of Cpu CrashLog ID.
CpuCrashLogReArm
EFI_STATUS CpuCrashLogReArm(VOID)
This function send re-arm command to rearm the trigger.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Classes
TelemetryPeiConfig.h File Reference

Configurations for Telemetry. More...

#include <ConfigBlock.h>
Include dependency graph for TelemetryPeiConfig.h:

Go to the source code of this file.

Classes

struct | TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem. More...
struct | TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem. More...

Detailed Description

Configurations for Telemetry.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TelemetryPeiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
TelemetryPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for Telemetry
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TELEMETRY_CONFIG_H_
36 #define _TELEMETRY_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #pragma pack (push,1)
41
42 #define TELEMETRY_PEI_CONFIG_REVISION 1
43 #define TELEMETRY_PEI_PREMEM_CONFIG_REVISION 1
44
45 extern EFI_GUID gTelemetryPeiConfigGuid;
46 extern EFI_GUID gTelemetryPeiPreMemConfigGuid;
47
48 /**
49 This configuration block describes Telemetry settings in PreMem.\n
50 <b>Revision 1</b>:
51 - Initial version.
52 **/
53 typedef struct {
54 CONFIG_BLOCK_HEADER Header; /// Config Block Header
55 UINT32 CpuCrashLogDevice; /// Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
56 } TELEMETRY_PEI_PREMEM_CONFIG;
57
58 /**
59 This configuration block describes Telemetry settings in PostMem.\n
60 <b>Revision 1</b>:
61 - Initial version.
62 **/
63 typedef struct {
64 CONFIG_BLOCK_HEADER Header; /// Config Block Header
65 UINT32 CpuCrashLogEnable; /// Enable or Disable CrashLog feature 0- Disable, <b>1- Enable</b>
66 } TELEMETRY_PEI_CONFIG;
67
68 #pragma pack (pop)
69
70 #endif
ConfigBlock.h
Header file for Config Block Lib implementation.
TELEMETRY_PEI_PREMEM_CONFIG
This configuration block describes Telemetry settings in PreMem.
Definition: TelemetryPeiConfig.h:53
TELEMETRY_PEI_PREMEM_CONFIG::CpuCrashLogDevice
UINT32 CpuCrashLogDevice
Config Block Header.
Definition: TelemetryPeiConfig.h:55
TELEMETRY_PEI_CONFIG
This configuration block describes Telemetry settings in PostMem.
Definition: TelemetryPeiConfig.h:63
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TELEMETRY_PEI_CONFIG::CpuCrashLogEnable
UINT32 CpuCrashLogEnable
Config Block Header.
Definition: TelemetryPeiConfig.h:65
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
TelemetryRegs.h File Reference

Register names for Telemetry Conventions: More...

Go to the source code of this file.

Detailed Description

Register names for Telemetry Conventions:

  • Prefixes:
    • Definitions beginning with "R_" are registers
    • Definitions beginning with "B_" are bits within registers
    • Definitions beginning with "V_" are meaningful values of bits within the registers
    • Definitions beginning with "S_" are register sizes
    • Definitions beginning with "N_" are the bit position
Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TelemetryRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TelemetryRegs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
TelemetryRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for Telemetry
3 <b>Conventions</b>:
4 - Prefixes:
5 - Definitions beginning with "R_" are registers
6 - Definitions beginning with "B_" are bits within registers
7 - Definitions beginning with "V_" are meaningful values of bits within the registers
8 - Definitions beginning with "S_" are register sizes
9 - Definitions beginning with "N_" are the bit position
10
11 @copyright
12 INTEL CONFIDENTIAL
13 Copyright 2018 - 2020 Intel Corporation.
14
15 The source code contained or described herein and all documents related to the
16 source code ("Material") are owned by Intel Corporation or its suppliers or
17 licensors. Title to the Material remains with Intel Corporation or its suppliers
18 and licensors. The Material may contain trade secrets and proprietary and
19 confidential information of Intel Corporation and its suppliers and licensors,
20 and is protected by worldwide copyright and trade secret laws and treaty
21 provisions. No part of the Material may be used, copied, reproduced, modified,
22 published, uploaded, posted, transmitted, distributed, or disclosed in any way
23 without Intel's prior express written permission.
24
25 No license under any patent, copyright, trade secret or other intellectual
26 property right is granted to or conferred upon you by disclosure or delivery
27 of the Materials, either expressly, by implication, inducement, estoppel or
28 otherwise. Any license under such intellectual property rights must be
29 express and approved by Intel in writing.
30
31 Unless otherwise agreed by Intel in writing, you may not remove or alter
32 this notice or any other notice embedded in Materials by Intel or
33 Intel's suppliers or licensors in any way.
34
35 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
36 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
37 the terms of your license agreement with Intel or your vendor. This file may
38 be modified by the user, subject to additional terms of the license agreement.
39
40 @par Specification Reference:
41 **/
42
43 #ifndef _REGS_TELEMETRY_H_
44 #define _REGS_TELEMETRY_H_
45
46 //
47 // Device 10 Memory Mapped IO Register Offset Equates
48 //
49 #define TEL_BUS_NUM 0x00
50 #define TEL_DEV_NUM 0x0A
51 #define TEL_FUN_NUM 0x00
52
53 //
54 // PCI Configuration Space Registers
55 //
56 #define R_TEL_CFG_BAR0 0x10
57 #define R_TEL_CFG_BAR1 0x14
58
59 //
60 // DVSEC capability Registers
61 //
62 #define R_TEL_DVSEC_OFFSET 0x100
63
64 #define R_TEL_DVSEC_PCIE_CAP_ID 0x0 // PCI Express Capability ID
65 #define R_TEL_DVSEC_NEXT_CAP 0x2 // Next Capability Offset
66 #define R_TEL_DVSEV_ID 0x8 // DVSEC_ID
67 #define R_TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC // Discovery Table Offset
68
69
70 #define V_TELEMETRY_EXTENDED_CAP_ID 0x23 // Indicates that this is a Telemetry Aggregator Extended Capability
71 #define V_CRASHLOG_DVSEC_ID 0x04 // CrashLog DEVSC ID
72 #define V_TEL_DVSEC_TBIR_BAR0 0
73 #define V_TEL_DVSEC_TBIR_BAR1 1
74
75 //
76 // CPU CrashLog MMIO Registers
77 //
78 #define R_CRASHLOG_HEADER_ADDRESS 0x6030
79
80 #define R_CRASHLOG_MAILBOX_INTERFACE_ADDRESS 0x6038
81
82 #define R_CRASHLOG_MAIN_POINTER_OFFSET 0x6040
83 #define R_CRASHLOG_TELEMETRY_POINTER_OFFSET 0x6048
84 #define R_CRASHLOG_TRACE_POINTER_OFFSET 0x6050
85
86 #define R_CRASHLOG_POINTER_BASE_ADDRESS_FIELD_OFFSET 0x00
87 #define R_CRASHLOG_POINTER_SIZE_FIELD_OFFSET 0x04
88
89 //
90 // CPU CrashLog Mailbox commands
91 //
92 #define V_CPU_CRASHLOG_CMD_DISABLE 0
93 #define V_CPU_CRASHLOG_CMD_TRIGGER 1
94 #define V_CPU_CRASHLOG_CMD_CLEAR 2
95 #define V_CPU_CRASHLOG_CMD_DISCOVERY 3
96 #define V_CPU_CRASHLOG_CMD_CRASHLOG_ON_ALL_RESET 4
97 #define V_CPU_CRASHLOG_CMD_REARM 5
98
99 #define CPU_CRASHLOG_MAILBOX_WAIT_STALL 1
100 #define CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT 1000
101
102 #endif // _SA_REGS_TELEMETRY_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TempRamExitPpi.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Classes | Macros | Typedefs
TempRamExitPpi.h File Reference

This file defines the Silicon Temp Ram Exit PPI which implements the MTRR values initialization. More...

Go to the source code of this file.

Classes

struct _FSP_TEMP_RAM_EXIT_PPI
This PPI provides function to program MTRR values. More...

Macros

#define FSP_TEMP_RAM_EXIT_GUID
Global ID for the FSP_TEMP_RAM_EXIT_PPI.

Typedefs

typedef EFI_STATUS(* FSP_TEMP_RAM_EXIT) (IN VOID *TempRamExitParamPtr)
Program MTRR values and print MTRRs.

Detailed Description

This file defines the Silicon Temp Ram Exit PPI which implements the MTRR values initialization.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TempRamExitPpi.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TempRamExitPpi.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
TempRamExitPpi.h
Go to the documentation of this file.
1 /** @file
2 This file defines the Silicon Temp Ram Exit PPI which implements the MTRR values initialization.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _FSP_TEMP_RAM_EXIT_PPI_H_
36 #define _FSP_TEMP_RAM_EXIT_PPI_H_
37
38 ///
39 /// Global ID for the FSP_TEMP_RAM_EXIT_PPI.
40 ///
41 #define FSP_TEMP_RAM_EXIT_GUID \
42 { \
43 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \
44 }
45
46 //
47 // Forward declaration for the FSP_TEMP_RAM_EXIT_PPI.
48 //
49 typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI;
50
51 /**
52 Program MTRR values and print MTRRs.
53 **/
54 typedef
55 EFI_STATUS
56 (EFIAPI *FSP_TEMP_RAM_EXIT) (
57 IN VOID *TempRamExitParamPtr
58 );
59
60 ///
61 /// This PPI provides function to program MTRR values
62 ///
63 struct _FSP_TEMP_RAM_EXIT_PPI {
64 FSP_TEMP_RAM_EXIT TempRamExit;
65 };
66
67 extern EFI_GUID gFspTempRamExitPpiGuid;
68
69 #endif // _FSP_TEMP_RAM_EXIT_PPI_H_
FSP_TEMP_RAM_EXIT
EFI_STATUS(* FSP_TEMP_RAM_EXIT)(IN VOID *TempRamExitParamPtr)
Program MTRR values and print MTRRs.
Definition: TempRamExitPpi.h:56
_FSP_TEMP_RAM_EXIT_PPI
This PPI provides function to program MTRR values.
Definition: TempRamExitPpi.h:63
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Thc.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
Thc.h File Reference

Touch Host Controller Protocol for Thc feature. More...

Go to the source code of this file.

Classes

struct _THC_PROTOCOL
Protocol used by Thc Once installed allows to detect if it is already running on given device Also used for obtaining Thc context. More...

Typedefs

typedef EFI_STATUS(* | HID_GET_FEATURE) (IN THC_PROTOCOL *This, IN UINT32 Length, IN OUT UINT8 *Buffer, IN UINTN Timeout)
Performs GetFeature function as described in Human Interface Device specification. More...
typedef EFI_STATUS(* | HID_SET_FEATURE) (IN THC_PROTOCOL *This, IN UINT32 Length, IN UINT8 *Buffer, IN UINTN Timeout)
Performs SetFeature function as described in Human Interface Device specification. More...
typedef EFI_STATUS(* | HID_ENABLE_AFTER_RESET) (IN THC_PROTOCOL *This)
Enables end point device. More...

Detailed Description

Touch Host Controller Protocol for Thc feature.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Note
The APIs in this file are designed to be backward compatible with previous versions. Any change in behavior of these APIs will result in newer version of the API
Specification Reference:

Definition in file Thc.h.

Typedef Documentation

◆ HID_ENABLE_AFTER_RESET

typedef EFI_STATUS( * HID_ENABLE_AFTER_RESET) (IN THC_PROTOCOL *This)

Enables end point device.

  • Reads all Touch Panels devices registers
  • Sets TouchEnable
Parameters
[in] This Pointer to instance of protocol.
Return values
EFI_SUCCESS | Enabling completed
EFI_DEVICE_ERROR | TSSDONE not set or ERR set
EFI_TIMEOUT | Timeout

Definition at line 110 of file Thc.h.

◆ HID_GET_FEATURE

typedef EFI_STATUS( * HID_GET_FEATURE) (IN THC_PROTOCOL *This, IN UINT32 Length, IN OUT UINT8 *Buffer, IN UINTN Timeout)

Performs GetFeature function as described in Human Interface Device specification.

Parameters
[in] | This | Pointer to instance of protocol.
[in] | Length | Size of buffer.
[in] | Buffer | On input, contains ReportId in 1st byte. On output, filled with Feature data from external device.
[in] | Timeout | 0 - No timeout, do not wait for response 1 or higher - will wait for that amount of time and copy response results to the same buffer.
Return values
EFI_NOT_READY | THC is not ready
EFI_ALREADY_STARTED | HID transaction is still active
EFI_NOT_AVAILABLE_YET | THC read transaction is ongoing
EFI_TIMEOUT | a) Response did not come in time OR b) DMA transaction did not finish in time
EFI_BUFFER_TOO_SMALL | THC DMA buffer is unable to fit that much data
EFI_SUCCESS | Get feature completed

Definition at line 64 of file Thc.h.

◆ HID_SET_FEATURE

typedef EFI_STATUS( * HID_SET_FEATURE) (IN THC_PROTOCOL *This, IN UINT32 Length, IN UINT8 *Buffer, IN UINTN Timeout)

Performs SetFeature function as described in Human Interface Device specification.

Parameters
[in] | This | Pointer to instance of protocol.
[in] | Length | Size of buffer.
[in] | Buffer | On input, contains ReportId in 1st byte. On output, filled with Feature data from external device.
[in] | Timeout | 0 - No timeout, do not wait for response 1 or higher - will wait for that amount of time and copy response results to the same buffer.
Return values
EFI_NOT_READY | THC is not ready
EFI_ALREADY_STARTED | HID transaction is still active
EFI_NOT_AVAILABLE_YET | THC read transaction is ongoing
EFI_TIMEOUT | a) Response did not come in time OR b) DMA transaction did not finish in time
EFI_BUFFER_TOO_SMALL | THC DMA buffer is unable to fit that much data
EFI_SUCCESS | Set feature completed

Definition at line 90 of file Thc.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Thc.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Thc.h
Go to the documentation of this file.
1 /** @file
2 Touch Host Controller Protocol for Thc feature
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @note
34 The APIs in this file are designed to be backward compatible with previous versions.
35 Any change in behavior of these APIs will result in newer version of the API
36
37 @par Specification Reference:
38 **/
39 #ifndef _THC_PROTOCOL_H_
40 #define _THC_PROTOCOL_H_
41
42 typedef struct _THC_PROTOCOL THC_PROTOCOL;
43
44 #define THC_PROTOCOL_REVISION 1
45
46 /**
47 Performs GetFeature function as described in Human Interface Device specification.
48
49 @param[in] This Pointer to instance of protocol.
50 @param[in] Length Size of buffer.
51 @param[in] Buffer On input, contains ReportId in 1st byte. On output, filled with Feature data from external device.
52 @param[in] Timeout 0 - No timeout, do not wait for response
53 1 or higher - will wait for that amount of time and copy response results to the same buffer.
54
55 @retval EFI_NOT_READY THC is not ready
56 @retval EFI_ALREADY_STARTED HID transaction is still active
57 @retval EFI_NOT_AVAILABLE_YET THC read transaction is ongoing
58 @retval EFI_TIMEOUT a) Response did not come in time OR
59 b) DMA transaction did not finish in time
60 @retval EFI_BUFFER_TOO_SMALL THC DMA buffer is unable to fit that much data
61 @retval EFI_SUCCESS Get feature completed
62 **/
63 typedef
64 EFI_STATUS
65 (EFIAPI *HID_GET_FEATURE)(
66 IN THC_PROTOCOL *This,
67 IN UINT32 Length,
68 IN OUT UINT8 *Buffer,
69 IN UINTN Timeout
70 );
71
72 /**
73 Performs SetFeature function as described in Human Interface Device specification.
74
75 @param[in] This Pointer to instance of protocol.
76 @param[in] Length Size of buffer.
77 @param[in] Buffer On input, contains ReportId in 1st byte. On output, filled with Feature data from external device.
78 @param[in] Timeout 0 - No timeout, do not wait for response
79 1 or higher - will wait for that amount of time and copy response results to the same buffer.
80
81 @retval EFI_NOT_READY THC is not ready
82 @retval EFI_ALREADY_STARTED HID transaction is still active
83 @retval EFI_NOT_AVAILABLE_YET THC read transaction is ongoing
84 @retval EFI_TIMEOUT a) Response did not come in time OR
85 b) DMA transaction did not finish in time
86 @retval EFI_BUFFER_TOO_SMALL THC DMA buffer is unable to fit that much data
87 @retval EFI_SUCCESS Set feature completed
88 **/
89 typedef
90 EFI_STATUS
91 (EFIAPI *HID_SET_FEATURE)(
92 IN THC_PROTOCOL *This,
93 IN UINT32 Length,
94 IN UINT8 *Buffer,
95 IN UINTN Timeout
96 );
97
98 /**
99 Enables end point device.
100 - Reads all Touch Panels devices registers
101 - Sets TouchEnable
102
103 @param[in] This Pointer to instance of protocol.
104
105 @retval EFI_SUCCESS Enabling completed
106 @retval EFI_DEVICE_ERROR TSSDONE not set or ERR set
107 @retval EFI_TIMEOUT Timeout
108 **/
109 typedef
110 EFI_STATUS
111 (EFIAPI *HID_ENABLE_AFTER_RESET) (
112 IN THC_PROTOCOL *This
113 );
114
115 /**
116 Protocol used by Thc
117 Once installed allows to detect if it is already running on given device
118 Also used for obtaining Thc context
119
120 @note
121 Designed to be backward compatible with previous versions.
122
123 **/
124 struct _THC_PROTOCOL {
125 UINT8 Revision;
126 /**
127 Devices Status:
128 EFI_NOT_READY - Thc initialization is still in progress
129 EFI_DEVICE_ERROR - Thc Initialization failed
130 EFI_SUCCESS - Thc is functional
131 **/
132 EFI_STATUS DeviceStatus;
133 HID_GET_FEATURE HidGetFeature;
134 HID_SET_FEATURE HidSetFeature;
135 HID_ENABLE_AFTER_RESET HidEnableAfterReset;
136 };
137
138 extern EFI_GUID gThcProtocolGuid;
139
140 #endif // _THC_PROTOCOL_H_
_THC_PROTOCOL
Protocol used by Thc Once installed allows to detect if it is already running on given device Also us...
Definition: Thc.h:124
HID_ENABLE_AFTER_RESET
EFI_STATUS(* HID_ENABLE_AFTER_RESET)(IN THC_PROTOCOL *This)
Enables end point device.
Definition: Thc.h:111
HID_GET_FEATURE
EFI_STATUS(* HID_GET_FEATURE)(IN THC_PROTOCOL *This, IN UINT32 Length, IN OUT UINT8 *Buffer, IN UINTN Timeout)
Performs GetFeature function as described in Human Interface Device specification.
Definition: Thc.h:65
_THC_PROTOCOL::DeviceStatus
EFI_STATUS DeviceStatus
Devices Status: EFI_NOT_READY - Thc initialization is still in progress EFI_DEVICE_ERROR - Thc Initia...
Definition: Thc.h:132
HID_SET_FEATURE
EFI_STATUS(* HID_SET_FEATURE)(IN THC_PROTOCOL *This, IN UINT32 Length, IN UINT8 *Buffer, IN UINTN Timeout)
Performs SetFeature function as described in Human Interface Device specification.
Definition: Thc.h:91
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThcConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Classes | Enumerations
ThcConfig.h File Reference

Touch Host Controller policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | THC_HID_OVER_SPI
THC Hid Over SPI mode related settings. More...
struct | THC_PORT
Port Configuration structure required for each Port that THC might use. More...
struct | THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers. More...

Enumerations

enum | THC_PORT_ASSIGNMENT
Available Port Assignments. More...
enum | THC_MODE
Available modes. More...

Detailed Description

Touch Host Controller policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThcConfig.h.

Enumeration Type Documentation

◆ THC_MODE

enum THC_MODE

Available modes.

Enumerator
Thc | Intel THC protocol.
HidOverSpi | Hid Over SPI protocol.

Definition at line 57 of file ThcConfig.h.

◆ THC_PORT_ASSIGNMENT

enum THC_PORT_ASSIGNMENT

Available Port Assignments.

Enumerator
ThcAssignmentNone | None of the avaialbe controllers assigned.
ThcAssignmentThc0 | Port assigned to THC0.
ThcAssignmentThc1 | Port assigned to THC1.

Definition at line 48 of file ThcConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThcConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
ThcConfig.h
Go to the documentation of this file.
1 /** @file
2 Touch Host Controller policy.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _THC_CONFIG_H_
37 #define _THC_CONFIG_H_
38
39 #define THC_CONFIG_REVISION 3
40 extern EFI_GUID gThcConfigGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 Available Port Assignments
46
47 **/
48 typedef enum {
49 ThcAssignmentNone, ///< None of the avaialbe controllers assigned
50 ThcAssignmentThc0, ///< Port assigned to THC0
51 ThcAssignmentThc1 ///< Port assigned to THC1
52 } THC_PORT_ASSIGNMENT;
53
54 /**
55 Available modes
56 **/
57 typedef enum {
58 Thc, ///< Intel THC protocol
59 HidOverSpi ///< Hid Over SPI protocol
60 } THC_MODE;
61
62
63 /**
64 THC Hid Over SPI mode related settings. Only applicable when HidOverSpi is enbled.
65 **/
66 typedef struct {
67 UINT32 ResetPad; ///< Reset Pad - <b>0x0 = THC HW default</b> BIOS will pass Pad infromation to ACPI, this Pad is used in _RST function or by the BIOS Quick SPI driver
68 UINT32 ResetPadTrigger; ///< Reset Pad Trigger
69 UINT32 Frequency; ///< Connection Speed - SPI Frequency in Hz
70 UINT32 InputReportHeaderAddress; ///< Input Report Header Address
71 UINT32 InputReportBodyAddress; ///< Input Report Body Address
72 UINT32 OutputReportAddress; ///< Output Report Address
73 UINT32 ReadOpcode; ///< Read Opcode
74 UINT32 WriteOpcode; ///< Write Opcode
75 UINT32 Flags; ///< Flags
76 } THC_HID_OVER_SPI;
77
78 /**
79 Port Configuration structure required for each Port that THC might use.
80
81 **/
82 typedef struct {
83 UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGNMENT
84 UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*
85 UINT8 WakeOnTouch; ///< 1 = Enable <b>0 = Disable</b>. Based on this setting vGPIO for given THC will be in native mode, and additional _CRS for wake will be exposed in ACPI
86 UINT8 Mode; ///< 1 = Hid over SPI <b>0 = THC</b>. Switch between Intel THC protcol and Industry standard HID Over SPI protocol.
87 UINT8 Reserved[2]; ///< Reserved
88 THC_HID_OVER_SPI HidOverSpi; ///< Hid Over Spi mode settings
89 UINT32 ActiveLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Active Ltr
90 UINT32 IdleLtr; ///< <b>0xFFFFFFFF = Driver Default </b> Idle Ltr
91 UINT32 LimitPacketSize; ///< Limit Packet Size
92 UINT32 PerformanceLimitation; ///< Performance Limitation
93 } THC_PORT;
94
95 /**
96 THC_CONFIG block provides the configurations forTouch Host Controllers
97
98 Assignment field in each THC port controlls the THC behavior.
99
100 Available scenarios:
101 1: Single Port 0 used by THC0
102 - THC0 Enabled
103 - Port0 assigned to THC0
104 - Port1 unassigned
105 - THC1 will be automatically Disabled.
106 2: Both ports used by THC0
107 - THC0 Enabled
108 - Port0 assigned to THC0
109 - Port1 assigned to THC0
110 - THC1 will be automatically Disabled.
111 3: Port 0 used by THC0 and Port 1 used by THC1
112 - THC0 Enabled
113 - Port0 assigned to THC0
114 - THC1 Enabled
115 - Port1 assigned to THC1.
116 <b>4: Both Ports unassigned.</b>
117 Both THC Controllers will be disabled in that case.
118
119 @note
120 Invalid scenario that will cause ASSERT.
121 1. Same port Number assigned to THC0 or THC1.
122 2. Two Ports assigned to THC1.
123
124 **/
125 typedef struct {
126 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
127 THC_PORT ThcPort[2]; ///< Port Configuration
128 } THC_CONFIG;
129
130 #pragma pack (pop)
131
132 #endif // _THC_CONFIG_H_
THC_HID_OVER_SPI::Frequency
UINT32 Frequency
Connection Speed - SPI Frequency in Hz.
Definition: ThcConfig.h:69
THC_HID_OVER_SPI::ReadOpcode
UINT32 ReadOpcode
Read Opcode.
Definition: ThcConfig.h:73
THC_MODE
THC_MODE
Available modes.
Definition: ThcConfig.h:57
THC_HID_OVER_SPI::Flags
UINT32 Flags
Flags.
Definition: ThcConfig.h:75
ThcAssignmentNone
@ ThcAssignmentNone
None of the avaialbe controllers assigned.
Definition: ThcConfig.h:49
HidOverSpi
@ HidOverSpi
Hid Over SPI protocol.
Definition: ThcConfig.h:59
THC_HID_OVER_SPI::ResetPad
UINT32 ResetPad
Reset Pad - 0x0 = THC HW default BIOS will pass Pad infromation to ACPI, this Pad is used in _RST fun...
Definition: ThcConfig.h:67
ThcAssignmentThc1
@ ThcAssignmentThc1
Port assigned to THC1.
Definition: ThcConfig.h:51
THC_PORT::InterruptPinMuxing
UINT32 InterruptPinMuxing
Each GPIO PORTx/SPIx INTB Pin has different muxing options refer to GPIO_*_MUXING_THC_SPIx_*.
Definition: ThcConfig.h:84
THC_PORT
Port Configuration structure required for each Port that THC might use.
Definition: ThcConfig.h:82
THC_PORT::Assignment
UINT32 Assignment
Sets THCx assignment see THC_PORT_ASSIGNMENT.
Definition: ThcConfig.h:83
Thc
@ Thc
Intel THC protocol.
Definition: ThcConfig.h:58
THC_PORT::IdleLtr
UINT32 IdleLtr
0xFFFFFFFF = Driver Default Idle Ltr
Definition: ThcConfig.h:90
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
THC_PORT::HidOverSpi
THC_HID_OVER_SPI HidOverSpi
Hid Over Spi mode settings.
Definition: ThcConfig.h:88
THC_PORT::LimitPacketSize
UINT32 LimitPacketSize
Limit Packet Size.
Definition: ThcConfig.h:91
THC_HID_OVER_SPI
THC Hid Over SPI mode related settings.
Definition: ThcConfig.h:66
THC_PORT::WakeOnTouch
UINT8 WakeOnTouch
1 = Enable 0 = Disable. Based on this setting vGPIO for given THC will be in native mode,...
Definition: ThcConfig.h:85
THC_HID_OVER_SPI::InputReportBodyAddress
UINT32 InputReportBodyAddress
Input Report Body Address.
Definition: ThcConfig.h:71
THC_PORT::PerformanceLimitation
UINT32 PerformanceLimitation
Performance Limitation.
Definition: ThcConfig.h:92
THC_HID_OVER_SPI::OutputReportAddress
UINT32 OutputReportAddress
Output Report Address.
Definition: ThcConfig.h:72
THC_HID_OVER_SPI::InputReportHeaderAddress
UINT32 InputReportHeaderAddress
Input Report Header Address.
Definition: ThcConfig.h:70
THC_PORT::ActiveLtr
UINT32 ActiveLtr
0xFFFFFFFF = Driver Default Active Ltr
Definition: ThcConfig.h:89
THC_PORT_ASSIGNMENT
THC_PORT_ASSIGNMENT
Available Port Assignments.
Definition: ThcConfig.h:48
THC_HID_OVER_SPI::ResetPadTrigger
UINT32 ResetPadTrigger
Reset Pad Trigger.
Definition: ThcConfig.h:68
THC_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThcConfig.h:126
ThcAssignmentThc0
@ ThcAssignmentThc0
Port assigned to THC0.
Definition: ThcConfig.h:50
THC_PORT::Mode
UINT8 Mode
1 = Hid over SPI 0 = THC. Switch between Intel THC protcol and Industry standard HID Over SPI protoco...
Definition: ThcConfig.h:86
THC_CONFIG
THC_CONFIG block provides the configurations forTouch Host Controllers.
Definition: ThcConfig.h:125
THC_HID_OVER_SPI::WriteOpcode
UINT32 WriteOpcode
Write Opcode.
Definition: ThcConfig.h:74
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThcLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ThcLib.h File Reference

Touch Host Controller Library. More...

Go to the source code of this file.

Functions

BOOLEAN | ThcIsEnabled (IN UINT8 ThcNumber)
Checks if the Intel Touch Host Controller is Enabled. More...
BOOLEAN | ThcIsSupported (VOID)
Checks if it is possible to enable Intel Touch Host Controller. More...

Detailed Description

Touch Host Controller Library.

All functions from this library are available in PEI, DXE, and SMM, But do not support UEFI RUNTIME environment call.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThcLib.h.

Function Documentation

◆ ThcIsEnabled()

BOOLEAN ThcIsEnabled ( IN UINT8 ThcNumber )

Checks if the Intel Touch Host Controller is Enabled.

Parameters
[in] ThcNumber THC0/THC1 0 or 1
Return values
TRUE | THC is enabled
FALSE | THC PCI device not found

◆ ThcIsSupported()

BOOLEAN ThcIsSupported ( VOID )

Checks if it is possible to enable Intel Touch Host Controller.

Thc Port 0 could be used by THC or Integrated Touch. If Integrated Touch is enabled, CSME will take over its GPIO. Based on the pad ownership BIOS decides if it is possible to enable THC

Return values
TRUE | BIOS is capable of enabling THC
FALSE | THC pins are taken over by some other IP. BIOS is unable to configure THC
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThcLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ThcLib.h
Go to the documentation of this file.
1 /** @file
2 Touch Host Controller Library.
3 All functions from this library are available in PEI, DXE, and SMM,
4 But do not support UEFI RUNTIME environment call.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright 2017 - 2021 Intel Corporation.
9
10 The source code contained or described herein and all documents related to the
11 source code ("Material") are owned by Intel Corporation or its suppliers or
12 licensors. Title to the Material remains with Intel Corporation or its suppliers
13 and licensors. The Material may contain trade secrets and proprietary and
14 confidential information of Intel Corporation and its suppliers and licensors,
15 and is protected by worldwide copyright and trade secret laws and treaty
16 provisions. No part of the Material may be used, copied, reproduced, modified,
17 published, uploaded, posted, transmitted, distributed, or disclosed in any way
18 without Intel's prior express written permission.
19
20 No license under any patent, copyright, trade secret or other intellectual
21 property right is granted to or conferred upon you by disclosure or delivery
22 of the Materials, either expressly, by implication, inducement, estoppel or
23 otherwise. Any license under such intellectual property rights must be
24 express and approved by Intel in writing.
25
26 Unless otherwise agreed by Intel in writing, you may not remove or alter
27 this notice or any other notice embedded in Materials by Intel or
28 Intel's suppliers or licensors in any way.
29
30 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
31 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
32 the terms of your license agreement with Intel or your vendor. This file may
33 be modified by the user, subject to additional terms of the license agreement.
34
35 @par Specification Reference:
36 **/
37
38 #ifndef _THC_LIB_H_
39 #define _THC_LIB_H_
40
41 /**
42 Checks if the Intel Touch Host Controller is Enabled
43
44 @param[in] ThcNumber THC0/THC1 0 or 1
45
46 @retval TRUE THC is enabled
47 @retval FALSE THC PCI device not found
48 **/
49 BOOLEAN
50 ThcIsEnabled (
51 IN UINT8 ThcNumber
52 );
53
54 /**
55 Checks if it is possible to enable Intel Touch Host Controller
56
57 Thc Port 0 could be used by THC or Integrated Touch.
58 If Integrated Touch is enabled, CSME will take over its GPIO.
59 Based on the pad ownership BIOS decides if it is possible to enable THC
60
61 @retval TRUE BIOS is capable of enabling THC
62 @retval FALSE THC pins are taken over by some other IP. BIOS is unable to configure THC
63 **/
64 BOOLEAN
65 ThcIsSupported (
66 VOID
67 );
68 #endif //_THC_LIB_H_
ThcIsEnabled
BOOLEAN ThcIsEnabled(IN UINT8 ThcNumber)
Checks if the Intel Touch Host Controller is Enabled.
ThcIsSupported
BOOLEAN ThcIsSupported(VOID)
Checks if it is possible to enable Intel Touch Host Controller.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThermalAccessLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
ThermalAccessLib.h File Reference

Thermal library header for abstraction of thermal registers access. More...

Go to the source code of this file.

Functions

BOOLEAN | ThermalIsThrottleLock (VOID)
Check thermal throttle level is locked. More...
BOOLEAN | ThermalIsEcThermalReportLock (VOID)
Check thermal EC thermal report is locked. More...
BOOLEAN | ThermalIsPchHotLock (VOID)
Check thermal PCH HOT is locked. More...
BOOLEAN | ThermalIsPmcThrottleLock (VOID)
Check thermal PMC throttle is locked. More...

Detailed Description

Thermal library header for abstraction of thermal registers access.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThermalAccessLib.h.

Function Documentation

◆ ThermalIsEcThermalReportLock()

BOOLEAN ThermalIsEcThermalReportLock ( VOID )

Check thermal EC thermal report is locked.

Return values
TRUE EC thermal report is locked FALSE EC thermal report is not locked

◆ ThermalIsPchHotLock()

BOOLEAN ThermalIsPchHotLock ( VOID )

Check thermal PCH HOT is locked.

Return values
TRUE PCH HOT is locked FALSE PCH HOT is not locked

◆ ThermalIsPmcThrottleLock()

BOOLEAN ThermalIsPmcThrottleLock ( VOID )

Check thermal PMC throttle is locked.

Return values
TRUE PMC throttle is locked FALSE PMC throttle is not locked

◆ ThermalIsThrottleLock()

BOOLEAN ThermalIsThrottleLock ( VOID )

Check thermal throttle level is locked.

Return values
TRUE Thermal throttle level is locked FALSE Thermal throttle level is not locked
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThermalAccessLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
ThermalAccessLib.h
Go to the documentation of this file.
1 /** @file
2 Thermal library header for abstraction of thermal registers access
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _THERMAL_ACCESS_LIB_H_
36 #define _THERMAL_ACCESS_LIB_H_
37
38 /**
39 Check thermal throttle level is locked
40
41 @retval TRUE Thermal throttle level is locked
42 FALSE Thermal throttle level is not locked
43 **/
44 BOOLEAN
45 ThermalIsThrottleLock (
46 VOID
47 );
48
49 /**
50 Check thermal EC thermal report is locked
51
52 @retval TRUE EC thermal report is locked
53 FALSE EC thermal report is not locked
54 **/
55 BOOLEAN
56 ThermalIsEcThermalReportLock (
57 VOID
58 );
59
60 /**
61 Check thermal PCH HOT is locked
62
63 @retval TRUE PCH HOT is locked
64 FALSE PCH HOT is not locked
65 **/
66 BOOLEAN
67 ThermalIsPchHotLock (
68 VOID
69 );
70
71 /**
72 Check thermal PMC throttle is locked
73
74 @retval TRUE PMC throttle is locked
75 FALSE PMC throttle is not locked
76 **/
77 BOOLEAN
78 ThermalIsPmcThrottleLock (
79 VOID
80 );
81
82 #endif // _THERMAL_ACCESS_LIB_H_
83
ThermalIsEcThermalReportLock
BOOLEAN ThermalIsEcThermalReportLock(VOID)
Check thermal EC thermal report is locked.
ThermalIsPchHotLock
BOOLEAN ThermalIsPchHotLock(VOID)
Check thermal PCH HOT is locked.
ThermalIsThrottleLock
BOOLEAN ThermalIsThrottleLock(VOID)
Check thermal throttle level is locked.
ThermalIsPmcThrottleLock
BOOLEAN ThermalIsPmcThrottleLock(VOID)
Check thermal PMC throttle is locked.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThermalConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Classes
ThermalConfig.h File Reference

Thermal policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization. More...
struct | DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design. More...
struct | TS_GPIO_PIN_SETTING
This structure configures PCH memory throttling thermal sensor GPIO PIN settings. More...
struct | PCH_MEMORY_THROTTLING
This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board). More...
struct | THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block. More...

Detailed Description

Thermal policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file ThermalConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ThermalConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
ThermalConfig.h
Go to the documentation of this file.
1 /** @file
2 Thermal policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _THERMAL_CONFIG_H_
36 #define _THERMAL_CONFIG_H_
37
38 #define THERMAL_CONFIG_REVISION 1
39 extern EFI_GUID gThermalConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This structure lists PCH supported throttling register setting for custimization.
45 When the SuggestedSetting is enabled, the customized values are ignored.
46 **/
47 typedef struct {
48 UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
49 UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
50 UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
51 UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
52 /**
53 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
54 If SuggestedSetting is used, this setting is ignored.
55 **/
56 UINT32 TTState13Enable : 1;
57 /**
58 When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
59 If SuggestedSetting is used, this setting is ignored.
60 **/
61 UINT32 TTLock : 1;
62 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
63 /**
64 ULT processors support thermal management and cross thermal throttling between the processor package
65 and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
66 thermal status to the processor which is factored into the processor throttling.
67 Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
68 **/
69 UINT32 PchCrossThrottling : 1;
70 UINT32 Rsvd0; ///< Reserved bytes
71 } THERMAL_THROTTLE_LEVELS;
72
73 //
74 // Supported Thermal Sensor Target Width
75 //
76 typedef enum {
77 DmiThermSensWidthX1 = 0,
78 DmiThermSensWidthX2 = 1,
79 DmiThermSensWidthX4 = 2,
80 DmiThermSensWidthX8 = 3,
81 DmiThermSensWidthX16 = 4
82 } DMI_THERMAL_SENSOR_TARGET_WIDTH;
83
84 /**
85 This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
86 When the SuggestedSetting is enabled, the customized values are ignored.
87 Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values
88 **/
89 typedef struct {
90 UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
91 UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
92 UINT32 RsvdBits0 : 6; ///< Reserved bits
93 UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width (<b>DmiThermSensWidthx8</b>)
94 UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width (<b>DmiThermSensWidthx4</b>)
95 UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width (<b>DmiThermSensWidthx2</b>)
96 UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width (<b>DmiThermSensWidthx1</b>)
97 UINT32 RsvdBits1 : 12; ///< Reserved bits
98 } DMI_HW_WIDTH_CONTROL;
99
100 /**
101 This structure configures PCH memory throttling thermal sensor GPIO PIN settings
102 **/
103 typedef struct {
104 /**
105 GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
106 When enabled, RC will overrides the selected GPIO native mode.
107 For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
108 For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
109 For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
110 **/
111 UINT32 PmsyncEnable : 1;
112 UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
113 UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
114 UINT32 RsvdBits0 : 29;
115 } TS_GPIO_PIN_SETTING;
116
117 enum PCH_PMSYNC_GPIO_X_SELECTION {
118 TsGpioC,
119 TsGpioD,
120 MaxTsGpioPin
121 };
122
123 /**
124 This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
125 **/
126 typedef struct {
127 /**
128 This will enable PCH memory throttling.
129 While this policy is enabled, must also enable EnableExtts in SA policy.
130 <b>0: Disable</b>; 1: Enable
131 **/
132 UINT32 Enable : 1;
133 UINT32 RsvdBits0 : 31;
134 /**
135 GPIO_C and GPIO_D selection for memory throttling.
136 It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
137 and route EXTTS# accordingly.
138 **/
139 TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
140 } PCH_MEMORY_THROTTLING;
141
142 /**
143 The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
144 **/
145 typedef struct {
146 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
147 UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: <b>Disabled<b>, 1: Enabled.
148 UINT32 RsvdBits0 : 31;
149 /**
150 This field decides the settings of Thermal throttling. When the Suggested Setting
151 is enabled, PCH RC will use the suggested representative values.
152 **/
153 THERMAL_THROTTLE_LEVELS TTLevels;
154 /**
155 This field decides the settings of DMI throttling. When the Suggested Setting
156 is enabled, PCH RC will use the suggested representative values.
157 **/
158 DMI_HW_WIDTH_CONTROL DmiHaAWC;
159 /**
160 Memory Thermal Management settings
161 **/
162 PCH_MEMORY_THROTTLING MemoryThrottling;
163 /**
164 The recommendation is the same as Cat Trip point.
165 This field decides the temperature, default is <b>120</b>.
166 Temperature value used for PCHHOT# pin assertion based on 2s complement format
167 - 0x001 positive 1'C
168 - 0x000 0'C
169 - 0x1FF negative 1'C
170 - 0x1D8 negative 40'C
171 - and so on
172 **/
173 UINT16 PchHotLevel;
174 UINT8 Rsvd0[6];
175
176
177 } THERMAL_CONFIG;
178
179 #pragma pack (pop)
180
181 #endif // _THERMAL_CONFIG_H_
DMI_HW_WIDTH_CONTROL::DmiTsawEn
UINT32 DmiTsawEn
DMI Thermal Sensor Autonomous Width Enable.
Definition: ThermalConfig.h:90
THERMAL_THROTTLE_LEVELS::T0Level
UINT32 T0Level
Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:48
TS_GPIO_PIN_SETTING::PmsyncEnable
UINT32 PmsyncEnable
GPIO PM_SYNC enable, 0:Diabled, 1:Enabled When enabled, RC will overrides the selected GPIO native mo...
Definition: ThermalConfig.h:111
TS_GPIO_PIN_SETTING
This structure configures PCH memory throttling thermal sensor GPIO PIN settings.
Definition: ThermalConfig.h:103
THERMAL_THROTTLE_LEVELS::TTEnable
UINT32 TTEnable
Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
Definition: ThermalConfig.h:51
THERMAL_THROTTLE_LEVELS::TTLock
UINT32 TTLock
When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
Definition: ThermalConfig.h:61
DMI_HW_WIDTH_CONTROL::TS0TW
UINT32 TS0TW
Thermal Sensor 0 Target Width (DmiThermSensWidthx8)
Definition: ThermalConfig.h:93
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
DMI_HW_WIDTH_CONTROL::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: ThermalConfig.h:92
THERMAL_CONFIG::MemoryThrottling
PCH_MEMORY_THROTTLING MemoryThrottling
Memory Thermal Management settings.
Definition: ThermalConfig.h:162
THERMAL_THROTTLE_LEVELS
This structure lists PCH supported throttling register setting for custimization.
Definition: ThermalConfig.h:47
DMI_HW_WIDTH_CONTROL::TS2TW
UINT32 TS2TW
Thermal Sensor 2 Target Width (DmiThermSensWidthx2)
Definition: ThermalConfig.h:95
THERMAL_THROTTLE_LEVELS::Rsvd0
UINT32 Rsvd0
Reserved bytes.
Definition: ThermalConfig.h:70
THERMAL_CONFIG::TTLevels
THERMAL_THROTTLE_LEVELS TTLevels
This field decides the settings of Thermal throttling.
Definition: ThermalConfig.h:153
DMI_HW_WIDTH_CONTROL::TS1TW
UINT32 TS1TW
Thermal Sensor 1 Target Width (DmiThermSensWidthx4)
Definition: ThermalConfig.h:94
PCH_MEMORY_THROTTLING
This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
Definition: ThermalConfig.h:126
THERMAL_THROTTLE_LEVELS::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values.
Definition: ThermalConfig.h:62
THERMAL_CONFIG::PchHotEnable
UINT32 PchHotEnable
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: Disabled,...
Definition: ThermalConfig.h:147
THERMAL_CONFIG::DmiHaAWC
DMI_HW_WIDTH_CONTROL DmiHaAWC
This field decides the settings of DMI throttling.
Definition: ThermalConfig.h:158
THERMAL_THROTTLE_LEVELS::TTState13Enable
UINT32 TTState13Enable
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
Definition: ThermalConfig.h:56
THERMAL_CONFIG
The THERMAL_CONFIG block describes the expected configuration of the Thermal IP block.
Definition: ThermalConfig.h:145
DMI_HW_WIDTH_CONTROL::SuggestedSetting
UINT32 SuggestedSetting
0: Disable; 1: Enable suggested representative values
Definition: ThermalConfig.h:91
THERMAL_CONFIG::PchHotLevel
UINT16 PchHotLevel
The recommendation is the same as Cat Trip point.
Definition: ThermalConfig.h:173
TS_GPIO_PIN_SETTING::C0TransmitEnable
UINT32 C0TransmitEnable
GPIO Transmit enable in C0 state, 0:Disabled, 1:Enabled
Definition: ThermalConfig.h:112
DMI_HW_WIDTH_CONTROL::TS3TW
UINT32 TS3TW
Thermal Sensor 3 Target Width (DmiThermSensWidthx1)
Definition: ThermalConfig.h:96
TS_GPIO_PIN_SETTING::PinSelection
UINT32 PinSelection
GPIO Pin assignment selection, 0: default, 1: secondary.
Definition: ThermalConfig.h:113
PCH_MEMORY_THROTTLING::Enable
UINT32 Enable
This will enable PCH memory throttling.
Definition: ThermalConfig.h:132
DMI_HW_WIDTH_CONTROL::RsvdBits1
UINT32 RsvdBits1
Reserved bits.
Definition: ThermalConfig.h:97
THERMAL_THROTTLE_LEVELS::T1Level
UINT32 T1Level
Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:49
THERMAL_THROTTLE_LEVELS::PchCrossThrottling
UINT32 PchCrossThrottling
ULT processors support thermal management and cross thermal throttling between the processor package ...
Definition: ThermalConfig.h:69
DMI_HW_WIDTH_CONTROL
This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec de...
Definition: ThermalConfig.h:89
THERMAL_THROTTLE_LEVELS::T2Level
UINT32 T2Level
Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
Definition: ThermalConfig.h:50
THERMAL_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: ThermalConfig.h:146
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TmeInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TmeInfoLib.h File Reference

Header file to get TME information. More...

Go to the source code of this file.

Functions

BOOLEAN | IsTmeActivated (VOID)
Reports if TME is enabled or not. More...
BOOLEAN | IsTmeActivateLocked (VOID)
Reports if Lock bit in TME Activate MSR locked or not. More...

Detailed Description

Header file to get TME information.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TmeInfoLib.h.

Function Documentation

◆ IsTmeActivated()

BOOLEAN IsTmeActivated ( VOID )

Reports if TME is enabled or not.

Return values
TRUE | If TME is enabled
FALSE | If TME is not enabled

◆ IsTmeActivateLocked()

BOOLEAN IsTmeActivateLocked ( VOID )

Reports if Lock bit in TME Activate MSR locked or not.

Return values
TRUE | If TME Activate MSR is locked
FALSE | If TME Activate MSR is not locked
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TmeInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TmeInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file to get TME information.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TME_INFO_LIB_H_
36 #define _TME_INFO_LIB_H_
37 /**
38 Reports if TME is enabled or not
39
40 @retval TRUE If TME is enabled
41 @retval FALSE If TME is not enabled
42 **/
43 BOOLEAN
44 IsTmeActivated (
45 VOID
46 );
47
48 /**
49 Reports if Lock bit in TME Activate MSR locked or not
50
51 @retval TRUE If TME Activate MSR is locked
52 @retval FALSE If TME Activate MSR is not locked
53 **/
54 BOOLEAN
55 IsTmeActivateLocked (
56 VOID
57 );
58 #endif /* _TME_INFO_LIB_H_ */
IsTmeActivateLocked
BOOLEAN IsTmeActivateLocked(VOID)
Reports if Lock bit in TME Activate MSR locked or not.
IsTmeActivated
BOOLEAN IsTmeActivated(VOID)
Reports if TME is enabled or not.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TopSwapLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TopSwapLib.h File Reference

Header file for TopSwapLib. More...

Go to the source code of this file.

Functions

BOOLEAN | TopSwapStatus (VOID)
Get TopSwap Status. More...
EFI_STATUS | TopSwapSet (IN BOOLEAN TopSwapEnable)
Set TopSwap Status. More...

Detailed Description

Header file for TopSwapLib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TopSwapLib.h.

Function Documentation

◆ TopSwapSet()

EFI_STATUS TopSwapSet ( IN BOOLEAN TopSwapEnable )

Set TopSwap Status.

Parameters
[in] TopSwapEnable Enable TopSwap or Disable it.
Return values
EFI_SUCCESS | TopSwap set successfully
EFI_DEVICE_ERROR | SBI command error

◆ TopSwapStatus()

BOOLEAN TopSwapStatus ( VOID )

Get TopSwap Status.

Return values
TRUE | TopSwap is set
FALSE | TopSwap is clear
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TopSwapLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TopSwapLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for TopSwapLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TOP_SWAP_LIB_H_
36 #define _TOP_SWAP_LIB_H_
37
38 /**
39 Get TopSwap Status
40
41 @retval TRUE TopSwap is set
42 @retval FALSE TopSwap is clear
43 **/
44 BOOLEAN
45 TopSwapStatus (
46 VOID
47 );
48
49 /**
50 Set TopSwap Status
51
52 @param[in] TopSwapEnable Enable TopSwap or Disable it.
53
54 @retval EFI_SUCCESS TopSwap set successfully
55 @retval EFI_DEVICE_ERROR SBI command error
56 **/
57 EFI_STATUS
58 TopSwapSet (
59 IN BOOLEAN TopSwapEnable
60 );
61
62 #endif // _TOP_SWAP_LIB_H_
TopSwapSet
EFI_STATUS TopSwapSet(IN BOOLEAN TopSwapEnable)
Set TopSwap Status.
TopSwapStatus
BOOLEAN TopSwapStatus(VOID)
Get TopSwap Status.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tpm2CommandLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
Tpm2CommandLib.h File Reference

This library is used by other modules to send TPM2 command. More...

#include <IndustryStandard/Tpm20.h>
Include dependency graph for Tpm2CommandLib.h:

Go to the source code of this file.

Functions

EFI_STATUS | Tpm2HashSequenceStart (IN TPMI_ALG_HASH HashAlg, OUT TPMI_DH_OBJECT *SequenceHandle)
This command starts a hash or an Event sequence. More...
EFI_STATUS | Tpm2SequenceUpdate (IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer)
This command is used to add data to a hash or HMAC sequence. More...
EFI_STATUS | Tpm2EventSequenceComplete (IN TPMI_DH_PCR PcrHandle, IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer, OUT TPML_DIGEST_VALUES *Results)
This command adds the last part of data, if any, to an Event sequence and returns the result in a digest list. More...
EFI_STATUS | Tpm2SequenceComplete (IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer, OUT TPM2B_DIGEST *Result)
This command adds the last part of data, if any, to a hash/HMAC sequence and returns the result. More...
EFI_STATUS | Tpm2Startup (IN TPM_SU StartupType)
Send Startup command to TPM2. More...
EFI_STATUS | Tpm2Shutdown (IN TPM_SU ShutdownType)
Send Shutdown command to TPM2. More...
EFI_STATUS | Tpm2SelfTest (IN TPMI_YES_NO FullTest)
This command causes the TPM to perform a test of its capabilities. More...
EFI_STATUS | Tpm2SetPrimaryPolicy (IN TPMI_RH_HIERARCHY_AUTH AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPM2B_DIGEST *AuthPolicy, IN TPMI_ALG_HASH HashAlg)
This command allows setting of the authorization policy for the platform hierarchy (platformPolicy), the storage hierarchy (ownerPolicy), and and the endorsement hierarchy (endorsementPolicy). More...
EFI_STATUS | Tpm2Clear (IN TPMI_RH_CLEAR AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command removes all TPM context associated with a specific Owner. More...
EFI_STATUS | Tpm2ClearControl (IN TPMI_RH_CLEAR AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPMI_YES_NO Disable)
Disables and enables the execution of TPM2_Clear(). More...
EFI_STATUS | Tpm2HierarchyChangeAuth (IN TPMI_RH_HIERARCHY_AUTH AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPM2B_AUTH *NewAuth)
This command allows the authorization secret for a hierarchy or lockout to be changed using the current authorization value as the command authorization. More...
EFI_STATUS | Tpm2ChangeEPS (IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This replaces the current EPS with a value from the RNG and sets the Endorsement hierarchy controls to their default initialization values. More...
EFI_STATUS | Tpm2ChangePPS (IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This replaces the current PPS with a value from the RNG and sets platformPolicy to the default initialization value (the Empty Buffer). More...
EFI_STATUS | Tpm2HierarchyControl (IN TPMI_RH_HIERARCHY AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPMI_RH_HIERARCHY Hierarchy, IN TPMI_YES_NO State)
This command enables and disables use of a hierarchy. More...
EFI_STATUS | Tpm2DictionaryAttackLockReset (IN TPMI_RH_LOCKOUT LockHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This command cancels the effect of a TPM lockout due to a number of successive authorization failures. More...
EFI_STATUS | Tpm2DictionaryAttackParameters (IN TPMI_RH_LOCKOUT LockHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN UINT32 NewMaxTries, IN UINT32 NewRecoveryTime, IN UINT32 LockoutRecovery)
This command cancels the effect of a TPM lockout due to a number of successive authorization failures. More...
EFI_STATUS | Tpm2NvReadPublic (IN TPMI_RH_NV_INDEX NvIndex, OUT TPM2B_NV_PUBLIC *NvPublic, OUT TPM2B_NAME *NvName)
This command is used to read the public area and Name of an NV Index. More...
EFI_STATUS | Tpm2NvDefineSpace (IN TPMI_RH_PROVISION AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_AUTH *Auth, IN TPM2B_NV_PUBLIC *NvPublic)
This command defines the attributes of an NV Index and causes the TPM to reserve space to hold the data associated with the index. More...
EFI_STATUS | Tpm2NvUndefineSpace (IN TPMI_RH_PROVISION AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command removes an index from the TPM. More...
EFI_STATUS | Tpm2NvRead (IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN UINT16 Size, IN UINT16 Offset, IN OUT TPM2B_MAX_BUFFER *OutData)
This command reads a value from an area in NV memory previously defined by TPM2_NV_DefineSpace(). More...
EFI_STATUS | Tpm2NvWrite (IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_MAX_BUFFER *InData, IN UINT16 Offset)
This command writes a value to an area in NV memory that was previously defined by TPM2_NV_DefineSpace(). More...
EFI_STATUS | Tpm2NvReadLock (IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command may be used to prevent further reads of the Index until the next TPM2_Startup (TPM_SU_CLEAR). More...
EFI_STATUS | Tpm2NvWriteLock (IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command may be used to inhibit further writes of the Index. More...
EFI_STATUS | Tpm2NvGlobalWriteLock (IN TPMI_RH_PROVISION AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
The command will SET TPMA_NV_WRITELOCKED for all indexes that have their TPMA_NV_GLOBALLOCK attribute SET. More...
EFI_STATUS | Tpm2PcrExtend (IN TPMI_DH_PCR PcrHandle, IN TPML_DIGEST_VALUES *Digests)
This command is used to cause an update to the indicated PCR. More...
EFI_STATUS | Tpm2PcrEvent (IN TPMI_DH_PCR PcrHandle, IN TPM2B_EVENT *EventData, OUT TPML_DIGEST_VALUES *Digests)
This command is used to cause an update to the indicated PCR. More...
EFI_STATUS | Tpm2PcrRead (IN TPML_PCR_SELECTION *PcrSelectionIn, OUT UINT32 *PcrUpdateCounter, OUT TPML_PCR_SELECTION *PcrSelectionOut, OUT TPML_DIGEST *PcrValues)
This command returns the values of all PCR specified in pcrSelect. More...
EFI_STATUS | Tpm2PcrAllocate (IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPML_PCR_SELECTION *PcrAllocation, OUT TPMI_YES_NO *AllocationSuccess, OUT UINT32 *MaxPCR, OUT UINT32 *SizeNeeded, OUT UINT32 *SizeAvailable)
This command is used to set the desired PCR allocation of PCR and algorithms. More...
EFI_STATUS | Tpm2PcrAllocateBanks (IN TPM2B_AUTH *PlatformAuth, OPTIONAL IN UINT32 SupportedPCRBanks, IN UINT32 PCRBanks)
Alloc PCR data. More...
EFI_STATUS | Tpm2GetCapability (IN TPM_CAP Capability, IN UINT32 Property, IN UINT32 PropertyCount, OUT TPMI_YES_NO *MoreData, OUT TPMS_CAPABILITY_DATA *CapabilityData)
This command returns various information regarding the TPM and its current state. More...
EFI_STATUS | Tpm2GetCapabilityFamily (OUT CHAR8 *Family)
This command returns the information of TPM Family. More...
EFI_STATUS | Tpm2GetCapabilityManufactureID (OUT UINT32 *ManufactureId)
This command returns the information of TPM manufacture ID. More...
EFI_STATUS | Tpm2GetCapabilityFirmwareVersion (OUT UINT32 *FirmwareVersion1, OUT UINT32 *FirmwareVersion2)
This command returns the information of TPM FirmwareVersion. More...
EFI_STATUS | Tpm2GetCapabilityMaxCommandResponseSize (OUT UINT32 *MaxCommandSize, OUT UINT32 *MaxResponseSize)
This command returns the information of the maximum value for commandSize and responseSize in a command. More...
EFI_STATUS | Tpm2GetCapabilitySupportedAlg (OUT TPML_ALG_PROPERTY *AlgList)
This command returns Returns a list of TPMS_ALG_PROPERTIES. More...
EFI_STATUS | Tpm2GetCapabilityLockoutCounter (OUT UINT32 *LockoutCounter)
This command returns the information of TPM LockoutCounter. More...
EFI_STATUS | Tpm2GetCapabilityLockoutInterval (OUT UINT32 *LockoutInterval)
This command returns the information of TPM LockoutInterval. More...
EFI_STATUS | Tpm2GetCapabilityInputBufferSize (OUT UINT32 *InputBufferSize)
This command returns the information of TPM InputBufferSize. More...
EFI_STATUS | Tpm2GetCapabilityPcrs (OUT TPML_PCR_SELECTION *Pcrs)
This command returns the information of TPM PCRs. More...
EFI_STATUS | Tpm2GetCapabilitySupportedAndActivePcrs (OUT UINT32 *TpmHashAlgorithmBitmap, OUT UINT32 *ActivePcrBanks)
This function will query the TPM to determine which hashing algorithms are supported and which PCR banks are currently active. More...
EFI_STATUS | Tpm2GetCapabilityAlgorithmSet (OUT UINT32 *AlgorithmSet)
This command returns the information of TPM AlgorithmSet. More...
EFI_STATUS | Tpm2TestParms (IN TPMT_PUBLIC_PARMS *Parameters)
This command is used to check to see if specific combinations of algorithm parameters are supported. More...
EFI_STATUS | Tpm2SetAlgorithmSet (IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN UINT32 AlgorithmSet)
This command allows the platform to change the set of algorithms that are used by the TPM. More...
EFI_STATUS | Tpm2StartAuthSession (IN TPMI_DH_OBJECT TpmKey, IN TPMI_DH_ENTITY Bind, IN TPM2B_NONCE *NonceCaller, IN TPM2B_ENCRYPTED_SECRET *Salt, IN TPM_SE SessionType, IN TPMT_SYM_DEF *Symmetric, IN TPMI_ALG_HASH AuthHash, OUT TPMI_SH_AUTH_SESSION *SessionHandle, OUT TPM2B_NONCE *NonceTPM)
This command is used to start an authorization session using alternative methods of establishing the session key (sessionKey) that is used for authorization and encrypting value. More...
EFI_STATUS | Tpm2FlushContext (IN TPMI_DH_CONTEXT FlushHandle)
This command causes all context associated with a loaded object or session to be removed from TPM memory. More...
EFI_STATUS | Tpm2PolicySecret (IN TPMI_DH_ENTITY AuthHandle, IN TPMI_SH_POLICY PolicySession, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_NONCE *NonceTPM, IN TPM2B_DIGEST *CpHashA, IN TPM2B_NONCE *PolicyRef, IN INT32 Expiration, OUT TPM2B_TIMEOUT *Timeout, OUT TPMT_TK_AUTH *PolicyTicket)
This command includes a secret-based authorization to a policy. More...
EFI_STATUS | Tpm2PolicyOR (IN TPMI_SH_POLICY PolicySession, IN TPML_DIGEST *HashList)
This command allows options in authorizations without requiring that the TPM evaluate all of the options. More...
EFI_STATUS | Tpm2PolicyCommandCode (IN TPMI_SH_POLICY PolicySession, IN TPM_CC Code)
This command indicates that the authorization will be limited to a specific command code. More...
EFI_STATUS | Tpm2PolicyGetDigest (IN TPMI_SH_POLICY PolicySession, OUT TPM2B_DIGEST *PolicyHash)
This command returns the current policyDigest of the session. More...
EFI_STATUS | Tpm2ReadPublic (IN TPMI_DH_OBJECT ObjectHandle, OUT TPM2B_PUBLIC *OutPublic, OUT TPM2B_NAME *Name, OUT TPM2B_NAME *QualifiedName)
This command allows access to the public area of a loaded object. More...
UINT32 | CopyAuthSessionCommand (IN TPMS_AUTH_COMMAND *AuthSessionIn, OPTIONAL OUT UINT8 *AuthSessionOut)
Copy AuthSessionIn to TPM2 command buffer. More...
UINT32 | CopyAuthSessionResponse (IN UINT8 *AuthSessionIn, OUT TPMS_AUTH_RESPONSE *AuthSessionOut OPTIONAL)
Copy AuthSessionIn from TPM2 response buffer. More...
UINT16 | GetHashSizeFromAlgo (IN TPMI_ALG_HASH HashAlgo)
Return size of digest. More...
UINT32 | GetHashMaskFromAlgo (IN TPMI_ALG_HASH HashAlgo)
Get hash mask from algorithm. More...
BOOLEAN | IsHashAlgSupportedInHashAlgorithmMask (IN TPMI_ALG_HASH HashAlg, IN UINT32 HashAlgorithmMask)
Return if hash alg is supported in HashAlgorithmMask. More...
VOID * | CopyDigestListToBuffer (IN OUT VOID *Buffer, IN TPML_DIGEST_VALUES *DigestList, IN UINT32 HashAlgorithmMask)
Copy TPML_DIGEST_VALUES into a buffer. More...
UINT32 | GetDigestListSize (IN TPML_DIGEST_VALUES *DigestList)
Get TPML_DIGEST_VALUES data size. More...
EFI_STATUS | GetDigestFromDigestList (IN TPMI_ALG_HASH HashAlg, IN TPML_DIGEST_VALUES *DigestList, OUT VOID *Digest)
This function get digest from digest list. More...

Detailed Description

This library is used by other modules to send TPM2 command.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file Tpm2CommandLib.h.

Function Documentation

◆ CopyAuthSessionCommand()

UINT32 CopyAuthSessionCommand | ( | IN TPMS_AUTH_COMMAND * | AuthSessionIn,
 |  | OPTIONAL OUT UINT8 * | AuthSessionOut
 | ) |  |

Copy AuthSessionIn to TPM2 command buffer.

Parameters
[in] | AuthSessionIn | Input AuthSession data
[out] | AuthSessionOut | Output AuthSession data in TPM2 command buffer
Returns
AuthSession size

◆ CopyAuthSessionResponse()

UINT32 CopyAuthSessionResponse | ( | IN UINT8 * | AuthSessionIn,
 |  | OUT TPMS_AUTH_RESPONSE *AuthSessionOut | OPTIONAL
 | ) |  |

Copy AuthSessionIn from TPM2 response buffer.

Parameters
[in] | AuthSessionIn | Input AuthSession data in TPM2 response buffer
[out] | AuthSessionOut | Output AuthSession data
Returns
AuthSession size

◆ CopyDigestListToBuffer()

VOID* CopyDigestListToBuffer | ( | IN OUT VOID * | Buffer,
 |  | IN TPML_DIGEST_VALUES * | DigestList,
 |  | IN UINT32 | HashAlgorithmMask
 | ) |  |

Copy TPML_DIGEST_VALUES into a buffer.

Parameters
[in,out] | Buffer | Buffer to hold copied TPML_DIGEST_VALUES compact binary.
[in] | DigestList | TPML_DIGEST_VALUES to be copied.
[in] | HashAlgorithmMask | HASH bits corresponding to the desired digests to copy.
Returns
The end of buffer to hold TPML_DIGEST_VALUES.

◆ GetDigestFromDigestList()

EFI_STATUS GetDigestFromDigestList | ( | IN TPMI_ALG_HASH | HashAlg,
 |  | IN TPML_DIGEST_VALUES * | DigestList,
 |  | OUT VOID * | Digest
 | ) |  |

This function get digest from digest list.

Parameters
[in] | HashAlg | Digest algorithm
[in] | DigestList | Digest list
[out] | Digest | Digest
Return values
EFI_SUCCESS | Digest is found and returned.
EFI_NOT_FOUND | Digest is not found.

◆ GetDigestListSize()

UINT32 GetDigestListSize ( IN TPML_DIGEST_VALUES * DigestList )

Get TPML_DIGEST_VALUES data size.

Parameters
[in] DigestList TPML_DIGEST_VALUES data.
Returns
TPML_DIGEST_VALUES data size.

◆ GetHashMaskFromAlgo()

UINT32 GetHashMaskFromAlgo ( IN TPMI_ALG_HASH HashAlgo )

Get hash mask from algorithm.

Parameters
[in] HashAlgo Hash algorithm
Returns
Hash mask

◆ GetHashSizeFromAlgo()

UINT16 GetHashSizeFromAlgo ( IN TPMI_ALG_HASH HashAlgo )

Return size of digest.

Parameters
[in] HashAlgo Hash algorithm
Returns
size of digest

◆ IsHashAlgSupportedInHashAlgorithmMask()

BOOLEAN IsHashAlgSupportedInHashAlgorithmMask | ( | IN TPMI_ALG_HASH | HashAlg,
 |  | IN UINT32 | HashAlgorithmMask
 | ) |  |

Return if hash alg is supported in HashAlgorithmMask.

Parameters
HashAlg | Hash algorithm to be checked.
HashAlgorithmMask | Bitfield of allowed hash algorithms.
Return values
TRUE | Hash algorithm is supported.
FALSE | Hash algorithm is not supported.

◆ Tpm2ChangeEPS()

EFI_STATUS Tpm2ChangeEPS | ( | IN TPMI_RH_PLATFORM | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession
 | ) |  |

This replaces the current EPS with a value from the RNG and sets the Endorsement hierarchy controls to their default initialization values.

Parameters
[in] | AuthHandle | TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2ChangePPS()

EFI_STATUS Tpm2ChangePPS | ( | IN TPMI_RH_PLATFORM | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession
 | ) |  |

This replaces the current PPS with a value from the RNG and sets platformPolicy to the default initialization value (the Empty Buffer).

Parameters
[in] | AuthHandle | TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2Clear()

EFI_STATUS Tpm2Clear | ( | IN TPMI_RH_CLEAR | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND *AuthSession | OPTIONAL
 | ) |  |

This command removes all TPM context associated with a specific Owner.

Parameters
[in] | AuthHandle | TPM_RH_LOCKOUT or TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2ClearControl()

EFI_STATUS Tpm2ClearControl | ( | IN TPMI_RH_CLEAR | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | OPTIONAL IN TPMI_YES_NO | Disable
 | ) |  |

Disables and enables the execution of TPM2_Clear().

Parameters
[in] | AuthHandle | TPM_RH_LOCKOUT or TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
[in] | Disable | YES if the disableOwnerClear flag is to be SET, NO if the flag is to be CLEAR.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2DictionaryAttackLockReset()

EFI_STATUS Tpm2DictionaryAttackLockReset | ( | IN TPMI_RH_LOCKOUT | LockHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession
 | ) |  |

This command cancels the effect of a TPM lockout due to a number of successive authorization failures.

If this command is properly authorized, the lockout counter is set to zero.

Parameters
[in] | LockHandle | LockHandle
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2DictionaryAttackParameters()

EFI_STATUS Tpm2DictionaryAttackParameters | ( | IN TPMI_RH_LOCKOUT | LockHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN UINT32 | NewMaxTries,
 |  | IN UINT32 | NewRecoveryTime,
 |  | IN UINT32 | LockoutRecovery
 | ) |  |

This command cancels the effect of a TPM lockout due to a number of successive authorization failures.

If this command is properly authorized, the lockout counter is set to zero.

Parameters
[in] | LockHandle | LockHandle
[in] | AuthSession | Auth Session context
[in] | NewMaxTries | Count of authorization failures before the lockout is imposed
[in] | NewRecoveryTime | Time in seconds before the authorization failure count is automatically decremented
[in] | LockoutRecovery | Time in seconds after a lockoutAuth failure before use of lockoutAuth is allowed
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2EventSequenceComplete()

EFI_STATUS Tpm2EventSequenceComplete | ( | IN TPMI_DH_PCR | PcrHandle,
 |  | IN TPMI_DH_OBJECT | SequenceHandle,
 |  | IN TPM2B_MAX_BUFFER * | Buffer,
 |  | OUT TPML_DIGEST_VALUES * | Results
 | ) |  |

This command adds the last part of data, if any, to an Event sequence and returns the result in a digest list.

If pcrHandle references a PCR and not TPM_RH_NULL, then the returned digest list is processed in the same manner as the digest list input parameter to TPM2_PCR_Extend() with the pcrHandle in each bank extended with the associated digest value.

Parameters
[in] | PcrHandle | PCR to be extended with the Event data
[in] | SequenceHandle | Authorization for the sequence
[in] | Buffer | Data to be added to the Event
[out] | Results | List of digests computed for the PCR
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2FlushContext()

EFI_STATUS Tpm2FlushContext ( IN TPMI_DH_CONTEXT FlushHandle )

This command causes all context associated with a loaded object or session to be removed from TPM memory.

Parameters
[in] FlushHandle The handle of the item to flush.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapability()

EFI_STATUS Tpm2GetCapability | ( | IN TPM_CAP | Capability,
 |  | IN UINT32 | Property,
 |  | IN UINT32 | PropertyCount,
 |  | OUT TPMI_YES_NO * | MoreData,
 |  | OUT TPMS_CAPABILITY_DATA * | CapabilityData
 | ) |  |

This command returns various information regarding the TPM and its current state.

The capability parameter determines the category of data returned. The property parameter selects the first value of the selected category to be returned. If there is no property that corresponds to the value of property, the next higher value is returned, if it exists. The moreData parameter will have a value of YES if there are more values of the requested type that were not returned. If no next capability exists, the TPM will return a zero-length list and moreData will have a value of NO.

NOTE: To simplify this function, leave returned CapabilityData for caller to unpack since there are many capability categories and only few categories will be used in firmware. It means the caller need swap the byte order for the feilds in CapabilityData.

Parameters
[in] | Capability | Group selection; determines the format of the response.
[in] | Property | Further definition of information.
[in] | PropertyCount | Number of properties of the indicated type to return.
[out] | MoreData | Flag to indicate if there are more values of this type.
[out] | CapabilityData | The capability data.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityAlgorithmSet()

EFI_STATUS Tpm2GetCapabilityAlgorithmSet ( OUT UINT32 * AlgorithmSet )

This command returns the information of TPM AlgorithmSet.

This function parse the value got from TPM2_GetCapability and return the AlgorithmSet.

Parameters
[out] AlgorithmSet The AlgorithmSet of TPM.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityFamily()

EFI_STATUS Tpm2GetCapabilityFamily ( OUT CHAR8 * Family )

This command returns the information of TPM Family.

This function parse the value got from TPM2_GetCapability and return the Family.

Parameters
[out] Family The Family of TPM. (a 4-octet character string)
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityFirmwareVersion()

EFI_STATUS Tpm2GetCapabilityFirmwareVersion | ( | OUT UINT32 * | FirmwareVersion1,
 |  | OUT UINT32 * | FirmwareVersion2
 | ) |  |

This command returns the information of TPM FirmwareVersion.

This function parse the value got from TPM2_GetCapability and return the TPM FirmwareVersion.

Parameters
[out] | FirmwareVersion1 | The FirmwareVersion1.
[out] | FirmwareVersion2 | The FirmwareVersion2.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityInputBufferSize()

EFI_STATUS Tpm2GetCapabilityInputBufferSize ( OUT UINT32 * InputBufferSize )

This command returns the information of TPM InputBufferSize.

This function parse the value got from TPM2_GetCapability and return the InputBufferSize.

Parameters
[out] InputBufferSize The InputBufferSize of TPM. the maximum size of a parameter (typically, a TPM2B_MAX_BUFFER)
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityLockoutCounter()

EFI_STATUS Tpm2GetCapabilityLockoutCounter ( OUT UINT32 * LockoutCounter )

This command returns the information of TPM LockoutCounter.

This function parse the value got from TPM2_GetCapability and return the LockoutCounter.

Parameters
[out] LockoutCounter The LockoutCounter of TPM.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityLockoutInterval()

EFI_STATUS Tpm2GetCapabilityLockoutInterval ( OUT UINT32 * LockoutInterval )

This command returns the information of TPM LockoutInterval.

This function parse the value got from TPM2_GetCapability and return the LockoutInterval.

Parameters
[out] LockoutInterval The LockoutInterval of TPM.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityManufactureID()

EFI_STATUS Tpm2GetCapabilityManufactureID ( OUT UINT32 * ManufactureId )

This command returns the information of TPM manufacture ID.

This function parse the value got from TPM2_GetCapability and return the TPM manufacture ID.

Parameters
[out] ManufactureId The manufacture ID of TPM.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityMaxCommandResponseSize()

EFI_STATUS Tpm2GetCapabilityMaxCommandResponseSize | ( | OUT UINT32 * | MaxCommandSize,
 |  | OUT UINT32 * | MaxResponseSize
 | ) |  |

This command returns the information of the maximum value for commandSize and responseSize in a command.

This function parse the value got from TPM2_GetCapability and return the max command size and response size

Parameters
[out] | MaxCommandSize | The maximum value for commandSize in a command.
[out] | MaxResponseSize | The maximum value for responseSize in a command.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilityPcrs()

EFI_STATUS Tpm2GetCapabilityPcrs ( OUT TPML_PCR_SELECTION * Pcrs )

This command returns the information of TPM PCRs.

This function parse the value got from TPM2_GetCapability and return the PcrSelection.

Parameters
[out] Pcrs The Pcr Selection
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilitySupportedAlg()

EFI_STATUS Tpm2GetCapabilitySupportedAlg ( OUT TPML_ALG_PROPERTY * AlgList )

This command returns Returns a list of TPMS_ALG_PROPERTIES.

Each entry is an algorithm ID and a set of properties of the algorithm.

This function parse the value got from TPM2_GetCapability and return the list.

Parameters
[out] AlgList List of algorithm.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2GetCapabilitySupportedAndActivePcrs()

EFI_STATUS Tpm2GetCapabilitySupportedAndActivePcrs | ( | OUT UINT32 * | TpmHashAlgorithmBitmap,
 |  | OUT UINT32 * | ActivePcrBanks
 | ) |  |

This function will query the TPM to determine which hashing algorithms are supported and which PCR banks are currently active.

Parameters
[out] | TpmHashAlgorithmBitmap | A bitmask containing the algorithms supported by the TPM.
[out] | ActivePcrBanks | A bitmask containing the PCRs currently allocated.
Return values
EFI_SUCCESS | TPM was successfully queried and return values can be trusted.
Others | An error occurred, likely in communication with the TPM.

◆ Tpm2HashSequenceStart()

EFI_STATUS Tpm2HashSequenceStart | ( | IN TPMI_ALG_HASH | HashAlg,
 |  | OUT TPMI_DH_OBJECT * | SequenceHandle
 | ) |  |

This command starts a hash or an Event sequence.

If hashAlg is an implemented hash, then a hash sequence is started. If hashAlg is TPM_ALG_NULL, then an Event sequence is started.

Parameters
[in] | HashAlg | The hash algorithm to use for the hash sequence An Event sequence starts if this is TPM_ALG_NULL.
[out] | SequenceHandle | A handle to reference the sequence
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2HierarchyChangeAuth()

EFI_STATUS Tpm2HierarchyChangeAuth | ( | IN TPMI_RH_HIERARCHY_AUTH | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN TPM2B_AUTH * | NewAuth
 | ) |  |

This command allows the authorization secret for a hierarchy or lockout to be changed using the current authorization value as the command authorization.

Parameters
[in] | AuthHandle | TPM_RH_LOCKOUT, TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
[in] | NewAuth | New authorization secret
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2HierarchyControl()

EFI_STATUS Tpm2HierarchyControl | ( | IN TPMI_RH_HIERARCHY | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN TPMI_RH_HIERARCHY | Hierarchy,
 |  | IN TPMI_YES_NO | State
 | ) |  |

This command enables and disables use of a hierarchy.

Parameters
[in] | AuthHandle | TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
[in] | Hierarchy | Hierarchy of the enable being modified
[in] | State | YES if the enable should be SET, NO if the enable should be CLEAR
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2NvDefineSpace()

EFI_STATUS Tpm2NvDefineSpace | ( | IN TPMI_RH_PROVISION | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | OPTIONAL IN TPM2B_AUTH * | Auth,
 |  | IN TPM2B_NV_PUBLIC * | NvPublic
 | ) |  |

This command defines the attributes of an NV Index and causes the TPM to reserve space to hold the data associated with the index.

If a definition already exists at the index, the TPM will return TPM_RC_NV_DEFINED.

Parameters
[in] | AuthHandle | TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
[in] | AuthSession | Auth Session context
[in] | Auth | The authorization data.
[in] | NvPublic | The public area of the index.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_ALREADY_STARTED | The command was returned successfully, but NvIndex is already defined.

◆ Tpm2NvGlobalWriteLock()

EFI_STATUS Tpm2NvGlobalWriteLock | ( | IN TPMI_RH_PROVISION | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND *AuthSession | OPTIONAL
 | ) |  |

The command will SET TPMA_NV_WRITELOCKED for all indexes that have their TPMA_NV_GLOBALLOCK attribute SET.

Parameters
[in] | AuthHandle | TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2NvRead()

EFI_STATUS Tpm2NvRead | ( | IN TPMI_RH_NV_AUTH | AuthHandle,
 |  | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | OPTIONAL IN UINT16 | Size,
 |  | IN UINT16 | Offset,
 |  | IN OUT TPM2B_MAX_BUFFER * | OutData
 | ) |  |

This command reads a value from an area in NV memory previously defined by TPM2_NV_DefineSpace().

Parameters
[in] | AuthHandle | the handle indicating the source of the authorization value.
[in] | NvIndex | The index to be read.
[in] | AuthSession | Auth Session context
[in] | Size | Number of bytes to read.
[in] | Offset | Byte offset into the area.
[in,out] | OutData | The data read.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2NvReadLock()

EFI_STATUS Tpm2NvReadLock | ( | IN TPMI_RH_NV_AUTH | AuthHandle,
 |  | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | IN TPMS_AUTH_COMMAND *AuthSession | OPTIONAL
 | ) |  |

This command may be used to prevent further reads of the Index until the next TPM2_Startup (TPM_SU_CLEAR).

Parameters
[in] | AuthHandle | the handle indicating the source of the authorization value.
[in] | NvIndex | The NV Index of the area to lock.
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2NvReadPublic()

EFI_STATUS Tpm2NvReadPublic | ( | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | OUT TPM2B_NV_PUBLIC * | NvPublic,
 |  | OUT TPM2B_NAME * | NvName
 | ) |  |

This command is used to read the public area and Name of an NV Index.

Parameters
[in] | NvIndex | The NV Index.
[out] | NvPublic | The public area of the index.
[out] | NvName | The Name of the nvIndex.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2NvUndefineSpace()

EFI_STATUS Tpm2NvUndefineSpace | ( | IN TPMI_RH_PROVISION | AuthHandle,
 |  | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | IN TPMS_AUTH_COMMAND *AuthSession | OPTIONAL
 | ) |  |

This command removes an index from the TPM.

Parameters
[in] | AuthHandle | TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
[in] | NvIndex | The NV Index.
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2NvWrite()

EFI_STATUS Tpm2NvWrite | ( | IN TPMI_RH_NV_AUTH | AuthHandle,
 |  | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | OPTIONAL IN TPM2B_MAX_BUFFER * | InData,
 |  | IN UINT16 | Offset
 | ) |  |

This command writes a value to an area in NV memory that was previously defined by TPM2_NV_DefineSpace().

Parameters
[in] | AuthHandle | the handle indicating the source of the authorization value.
[in] | NvIndex | The NV Index of the area to write.
[in] | AuthSession | Auth Session context
[in] | InData | The data to write.
[in] | Offset | The offset into the NV Area.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2NvWriteLock()

EFI_STATUS Tpm2NvWriteLock | ( | IN TPMI_RH_NV_AUTH | AuthHandle,
 |  | IN TPMI_RH_NV_INDEX | NvIndex,
 |  | IN TPMS_AUTH_COMMAND *AuthSession | OPTIONAL
 | ) |  |

This command may be used to inhibit further writes of the Index.

Parameters
[in] | AuthHandle | the handle indicating the source of the authorization value.
[in] | NvIndex | The NV Index of the area to lock.
[in] | AuthSession | Auth Session context
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.
EFI_NOT_FOUND | The command was returned successfully, but NvIndex is not found.

◆ Tpm2PcrAllocate()

EFI_STATUS Tpm2PcrAllocate | ( | IN TPMI_RH_PLATFORM | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN TPML_PCR_SELECTION * | PcrAllocation,
 |  | OUT TPMI_YES_NO * | AllocationSuccess,
 |  | OUT UINT32 * | MaxPCR,
 |  | OUT UINT32 * | SizeNeeded,
 |  | OUT UINT32 * | SizeAvailable
 | ) |  |

This command is used to set the desired PCR allocation of PCR and algorithms.

Parameters
[in] | AuthHandle | TPM_RH_PLATFORM+{PP}
[in] | AuthSession | Auth Session context
[in] | PcrAllocation | The requested allocation
[out] | AllocationSuccess | YES if the allocation succeeded
[out] | MaxPCR | maximum number of PCR that may be in a bank
[out] | SizeNeeded | number of octets required to satisfy the request
[out] | SizeAvailable | Number of octets available. Computed before the allocation
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2PcrAllocateBanks()

EFI_STATUS Tpm2PcrAllocateBanks | ( | IN TPM2B_AUTH * | PlatformAuth,
 |  | OPTIONAL IN UINT32 | SupportedPCRBanks,
 |  | IN UINT32 | PCRBanks
 | ) |  |

Alloc PCR data.

Parameters
[in] | PlatformAuth | platform auth value. NULL means no platform auth change.
[in] | SupportedPCRBanks | Supported PCR banks
[in] | PCRBanks | PCR banks
Return values
EFI_SUCCESS Operation completed successfully.

◆ Tpm2PcrEvent()

EFI_STATUS Tpm2PcrEvent | ( | IN TPMI_DH_PCR | PcrHandle,
 |  | IN TPM2B_EVENT * | EventData,
 |  | OUT TPML_DIGEST_VALUES * | Digests
 | ) |  |

This command is used to cause an update to the indicated PCR.

The data in eventData is hashed using the hash algorithm associated with each bank in which the indicated PCR has been allocated. After the data is hashed, the digests list is returned. If the pcrHandle references an implemented PCR and not TPM_ALG_NULL, digests list is processed as in TPM2_PCR_Extend(). A TPM shall support an Event.size of zero through 1,024 inclusive.

Parameters
[in] | PcrHandle | Handle of the PCR
[in] | EventData | Event data in sized buffer
[out] | Digests | List of digest
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2PcrExtend()

EFI_STATUS Tpm2PcrExtend | ( | IN TPMI_DH_PCR | PcrHandle,
 |  | IN TPML_DIGEST_VALUES * | Digests
 | ) |  |

This command is used to cause an update to the indicated PCR.

The digests parameter contains one or more tagged digest value identified by an algorithm ID. For each digest, the PCR associated with pcrHandle is Extended into the bank identified by the tag (hashAlg).

Parameters
[in] | PcrHandle | Handle of the PCR
[in] | Digests | List of tagged digest values to be extended
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2PcrRead()

EFI_STATUS Tpm2PcrRead | ( | IN TPML_PCR_SELECTION * | PcrSelectionIn,
 |  | OUT UINT32 * | PcrUpdateCounter,
 |  | OUT TPML_PCR_SELECTION * | PcrSelectionOut,
 |  | OUT TPML_DIGEST * | PcrValues
 | ) |  |

This command returns the values of all PCR specified in pcrSelect.

Parameters
[in] | PcrSelectionIn | The selection of PCR to read.
[out] | PcrUpdateCounter | The current value of the PCR update counter.
[out] | PcrSelectionOut | The PCR in the returned list.
[out] | PcrValues | The contents of the PCR indicated in pcrSelect.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2PolicyCommandCode()

EFI_STATUS Tpm2PolicyCommandCode | ( | IN TPMI_SH_POLICY | PolicySession,
 |  | IN TPM_CC | Code
 | ) |  |

This command indicates that the authorization will be limited to a specific command code.

Parameters
[in] | PolicySession | Handle for the policy session being extended.
[in] | Code | The allowed commandCode.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2PolicyGetDigest()

EFI_STATUS Tpm2PolicyGetDigest | ( | IN TPMI_SH_POLICY | PolicySession,
 |  | OUT TPM2B_DIGEST * | PolicyHash
 | ) |  |

This command returns the current policyDigest of the session.

This command allows the TPM to be used to perform the actions required to precompute the authPolicy for an object.

Parameters
[in] | PolicySession | Handle for the policy session.
[out] | PolicyHash | the current value of the policyHash of policySession.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2PolicyOR()

EFI_STATUS Tpm2PolicyOR | ( | IN TPMI_SH_POLICY | PolicySession,
 |  | IN TPML_DIGEST * | HashList
 | ) |  |

This command allows options in authorizations without requiring that the TPM evaluate all of the options.

If a policy may be satisfied by different sets of conditions, the TPM need only evaluate one set that satisfies the policy. This command will indicate that one of the required sets of conditions has been satisfied.

Parameters
[in] | PolicySession | Handle for the policy session being extended.
[in] | HashList | the list of hashes to check for a match.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2PolicySecret()

EFI_STATUS Tpm2PolicySecret | ( | IN TPMI_DH_ENTITY | AuthHandle,
 |  | IN TPMI_SH_POLICY | PolicySession,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | OPTIONAL IN TPM2B_NONCE * | NonceTPM,
 |  | IN TPM2B_DIGEST * | CpHashA,
 |  | IN TPM2B_NONCE * | PolicyRef,
 |  | IN INT32 | Expiration,
 |  | OUT TPM2B_TIMEOUT * | Timeout,
 |  | OUT TPMT_TK_AUTH * | PolicyTicket
 | ) |  |

This command includes a secret-based authorization to a policy.

The caller proves knowledge of the secret value using an authorization session using the authValue associated with authHandle.

Parameters
[in] | AuthHandle | Handle for an entity providing the authorization
[in] | PolicySession | Handle for the policy session being extended.
[in] | AuthSession | Auth Session context
[in] | NonceTPM | The policy nonce for the session.
[in] | CpHashA | Digest of the command parameters to which this authorization is limited.
[in] | PolicyRef | A reference to a policy relating to the authorization.
[in] | Expiration | Time when authorization will expire, measured in seconds from the time that nonceTPM was generated.
[out] | Timeout | Time value used to indicate to the TPM when the ticket expires.
[out] | PolicyTicket | A ticket that includes a value indicating when the authorization expires.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2ReadPublic()

EFI_STATUS Tpm2ReadPublic | ( | IN TPMI_DH_OBJECT | ObjectHandle,
 |  | OUT TPM2B_PUBLIC * | OutPublic,
 |  | OUT TPM2B_NAME * | Name,
 |  | OUT TPM2B_NAME * | QualifiedName
 | ) |  |

This command allows access to the public area of a loaded object.

Parameters
[in] | ObjectHandle | TPM handle of an object
[out] | OutPublic | Structure containing the public area of an object
[out] | Name | Name of the object
[out] | QualifiedName | The Qualified Name of the object
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2SelfTest()

EFI_STATUS Tpm2SelfTest ( IN TPMI_YES_NO FullTest )

This command causes the TPM to perform a test of its capabilities.

If the fullTest is YES, the TPM will test all functions. If fullTest = NO, the TPM will only test those functions that have not previously been tested.

Parameters
[in] FullTest YES if full test to be performed NO if only test of untested functions required
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2SequenceComplete()

EFI_STATUS Tpm2SequenceComplete | ( | IN TPMI_DH_OBJECT | SequenceHandle,
 |  | IN TPM2B_MAX_BUFFER * | Buffer,
 |  | OUT TPM2B_DIGEST * | Result
 | ) |  |

This command adds the last part of data, if any, to a hash/HMAC sequence and returns the result.

Parameters
[in] | SequenceHandle | Authorization for the sequence
[in] | Buffer | Data to be added to the hash/HMAC
[out] | Result | The returned HMAC or digest in a sized buffer
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2SequenceUpdate()

EFI_STATUS Tpm2SequenceUpdate | ( | IN TPMI_DH_OBJECT | SequenceHandle,
 |  | IN TPM2B_MAX_BUFFER * | Buffer
 | ) |  |

This command is used to add data to a hash or HMAC sequence.

The amount of data in buffer may be any size up to the limits of the TPM. NOTE: In all TPM, a buffer size of 1,024 octets is allowed.

Parameters
[in] | SequenceHandle | Handle for the sequence object
[in] | Buffer | Data to be added to hash
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2SetAlgorithmSet()

EFI_STATUS Tpm2SetAlgorithmSet | ( | IN TPMI_RH_PLATFORM | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN UINT32 | AlgorithmSet
 | ) |  |

This command allows the platform to change the set of algorithms that are used by the TPM.

The algorithmSet setting is a vendor-dependent value.

Parameters
[in] | AuthHandle | TPM_RH_PLATFORM
[in] | AuthSession | Auth Session context
[in] | AlgorithmSet | A TPM vendor-dependent value indicating the algorithm set selection
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2SetPrimaryPolicy()

EFI_STATUS Tpm2SetPrimaryPolicy | ( | IN TPMI_RH_HIERARCHY_AUTH | AuthHandle,
 |  | IN TPMS_AUTH_COMMAND * | AuthSession,
 |  | IN TPM2B_DIGEST * | AuthPolicy,
 |  | IN TPMI_ALG_HASH | HashAlg
 | ) |  |

This command allows setting of the authorization policy for the platform hierarchy (platformPolicy), the storage hierarchy (ownerPolicy), and and the endorsement hierarchy (endorsementPolicy).

Parameters
[in] | AuthHandle | TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP} parameters to be validated
[in] | AuthSession | Auth Session context
[in] | AuthPolicy | An authorization policy hash
[in] | HashAlg | The hash algorithm to use for the policy
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2Shutdown()

EFI_STATUS Tpm2Shutdown ( IN TPM_SU ShutdownType )

Send Shutdown command to TPM2.

Parameters
[in] ShutdownType TPM_SU_CLEAR or TPM_SU_STATE.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2StartAuthSession()

EFI_STATUS Tpm2StartAuthSession | ( | IN TPMI_DH_OBJECT | TpmKey,
 |  | IN TPMI_DH_ENTITY | Bind,
 |  | IN TPM2B_NONCE * | NonceCaller,
 |  | IN TPM2B_ENCRYPTED_SECRET * | Salt,
 |  | IN TPM_SE | SessionType,
 |  | IN TPMT_SYM_DEF * | Symmetric,
 |  | IN TPMI_ALG_HASH | AuthHash,
 |  | OUT TPMI_SH_AUTH_SESSION * | SessionHandle,
 |  | OUT TPM2B_NONCE * | NonceTPM
 | ) |  |

This command is used to start an authorization session using alternative methods of establishing the session key (sessionKey) that is used for authorization and encrypting value.

Parameters
[in] | TpmKey | Handle of a loaded decrypt key used to encrypt salt.
[in] | Bind | Entity providing the authValue.
[in] | NonceCaller | Initial nonceCaller, sets nonce size for the session.
[in] | Salt | Value encrypted according to the type of tpmKey.
[in] | SessionType | Indicates the type of the session.
[in] | Symmetric | The algorithm and key size for parameter encryption.
[in] | AuthHash | Hash algorithm to use for the session.
[out] | SessionHandle | Handle for the newly created session.
[out] | NonceTPM | The initial nonce from the TPM, used in the computation of the sessionKey.
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | The command was unsuccessful.

◆ Tpm2Startup()

EFI_STATUS Tpm2Startup ( IN TPM_SU StartupType )

Send Startup command to TPM2.

Parameters
[in] StartupType TPM_SU_CLEAR or TPM_SU_STATE
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.

◆ Tpm2TestParms()

EFI_STATUS Tpm2TestParms ( IN TPMT_PUBLIC_PARMS * Parameters )

This command is used to check to see if specific combinations of algorithm parameters are supported.

Parameters
[in] Parameters Algorithm parameters to be validated
Return values
EFI_SUCCESS | Operation completed successfully.
EFI_DEVICE_ERROR | Unexpected device behavior.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tpm2CommandLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Tpm2CommandLib.h
Go to the documentation of this file.
1 /** @file
2 This library is used by other modules to send TPM2 command.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved. <BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14
15 **/
16
17 #ifndef _TPM2_COMMAND_LIB_H_
18 #define _TPM2_COMMAND_LIB_H_
19
20 #include <IndustryStandard/Tpm20.h>
21
22 /**
23 This command starts a hash or an Event sequence.
24 If hashAlg is an implemented hash, then a hash sequence is started.
25 If hashAlg is TPM_ALG_NULL, then an Event sequence is started.
26
27 @param[in] HashAlg The hash algorithm to use for the hash sequence
28 An Event sequence starts if this is TPM_ALG_NULL.
29 @param[out] SequenceHandle A handle to reference the sequence
30
31 @retval EFI_SUCCESS Operation completed successfully.
32 @retval EFI_DEVICE_ERROR Unexpected device behavior.
33 **/
34 EFI_STATUS
35 EFIAPI
36 Tpm2HashSequenceStart (
37 IN TPMI_ALG_HASH HashAlg,
38 OUT TPMI_DH_OBJECT *SequenceHandle
39 );
40
41 /**
42 This command is used to add data to a hash or HMAC sequence.
43 The amount of data in buffer may be any size up to the limits of the TPM.
44 NOTE: In all TPM, a buffer size of 1,024 octets is allowed.
45
46 @param[in] SequenceHandle Handle for the sequence object
47 @param[in] Buffer Data to be added to hash
48
49 @retval EFI_SUCCESS Operation completed successfully.
50 @retval EFI_DEVICE_ERROR Unexpected device behavior.
51 **/
52 EFI_STATUS
53 EFIAPI
54 Tpm2SequenceUpdate (
55 IN TPMI_DH_OBJECT SequenceHandle,
56 IN TPM2B_MAX_BUFFER *Buffer
57 );
58
59 /**
60 This command adds the last part of data, if any, to an Event sequence and returns the result in a digest list.
61 If pcrHandle references a PCR and not TPM_RH_NULL, then the returned digest list is processed in
62 the same manner as the digest list input parameter to TPM2_PCR_Extend() with the pcrHandle in each
63 bank extended with the associated digest value.
64
65 @param[in] PcrHandle PCR to be extended with the Event data
66 @param[in] SequenceHandle Authorization for the sequence
67 @param[in] Buffer Data to be added to the Event
68 @param[out] Results List of digests computed for the PCR
69
70 @retval EFI_SUCCESS Operation completed successfully.
71 @retval EFI_DEVICE_ERROR Unexpected device behavior.
72 **/
73 EFI_STATUS
74 EFIAPI
75 Tpm2EventSequenceComplete (
76 IN TPMI_DH_PCR PcrHandle,
77 IN TPMI_DH_OBJECT SequenceHandle,
78 IN TPM2B_MAX_BUFFER *Buffer,
79 OUT TPML_DIGEST_VALUES *Results
80 );
81
82 /**
83 This command adds the last part of data, if any, to a hash/HMAC sequence and returns the result.
84
85 @param[in] SequenceHandle Authorization for the sequence
86 @param[in] Buffer Data to be added to the hash/HMAC
87 @param[out] Result The returned HMAC or digest in a sized buffer
88
89 @retval EFI_SUCCESS Operation completed successfully.
90 @retval EFI_DEVICE_ERROR Unexpected device behavior.
91 **/
92 EFI_STATUS
93 EFIAPI
94 Tpm2SequenceComplete (
95 IN TPMI_DH_OBJECT SequenceHandle,
96 IN TPM2B_MAX_BUFFER *Buffer,
97 OUT TPM2B_DIGEST *Result
98 );
99
100 /**
101 Send Startup command to TPM2.
102
103 @param[in] StartupType TPM_SU_CLEAR or TPM_SU_STATE
104
105 @retval EFI_SUCCESS Operation completed successfully.
106 @retval EFI_DEVICE_ERROR Unexpected device behavior.
107 **/
108 EFI_STATUS
109 EFIAPI
110 Tpm2Startup (
111 IN TPM_SU StartupType
112 );
113
114 /**
115 Send Shutdown command to TPM2.
116
117 @param[in] ShutdownType TPM_SU_CLEAR or TPM_SU_STATE.
118
119 @retval EFI_SUCCESS Operation completed successfully.
120 @retval EFI_DEVICE_ERROR Unexpected device behavior.
121 **/
122 EFI_STATUS
123 EFIAPI
124 Tpm2Shutdown (
125 IN TPM_SU ShutdownType
126 );
127
128 /**
129 This command causes the TPM to perform a test of its capabilities.
130 If the fullTest is YES, the TPM will test all functions.
131 If fullTest = NO, the TPM will only test those functions that have not previously been tested.
132
133 @param[in] FullTest YES if full test to be performed
134 NO if only test of untested functions required
135
136 @retval EFI_SUCCESS Operation completed successfully.
137 @retval EFI_DEVICE_ERROR Unexpected device behavior.
138 **/
139 EFI_STATUS
140 EFIAPI
141 Tpm2SelfTest (
142 IN TPMI_YES_NO FullTest
143 );
144
145 /**
146 This command allows setting of the authorization policy for the platform hierarchy (platformPolicy), the
147 storage hierarchy (ownerPolicy), and and the endorsement hierarchy (endorsementPolicy).
148
149 @param[in] AuthHandle TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP} parameters to be validated
150 @param[in] AuthSession Auth Session context
151 @param[in] AuthPolicy An authorization policy hash
152 @param[in] HashAlg The hash algorithm to use for the policy
153
154 @retval EFI_SUCCESS Operation completed successfully.
155 @retval EFI_DEVICE_ERROR Unexpected device behavior.
156 **/
157 EFI_STATUS
158 EFIAPI
159 Tpm2SetPrimaryPolicy (
160 IN TPMI_RH_HIERARCHY_AUTH AuthHandle,
161 IN TPMS_AUTH_COMMAND *AuthSession,
162 IN TPM2B_DIGEST *AuthPolicy,
163 IN TPMI_ALG_HASH HashAlg
164 );
165
166 /**
167 This command removes all TPM context associated with a specific Owner.
168
169 @param[in] AuthHandle TPM_RH_LOCKOUT or TPM_RH_PLATFORM+{PP}
170 @param[in] AuthSession Auth Session context
171
172 @retval EFI_SUCCESS Operation completed successfully.
173 @retval EFI_DEVICE_ERROR Unexpected device behavior.
174 **/
175 EFI_STATUS
176 EFIAPI
177 Tpm2Clear (
178 IN TPMI_RH_CLEAR AuthHandle,
179 IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL
180 );
181
182 /**
183 Disables and enables the execution of TPM2_Clear().
184
185 @param[in] AuthHandle TPM_RH_LOCKOUT or TPM_RH_PLATFORM+{PP}
186 @param[in] AuthSession Auth Session context
187 @param[in] Disable YES if the disableOwnerClear flag is to be SET,
188 NO if the flag is to be CLEAR.
189
190 @retval EFI_SUCCESS Operation completed successfully.
191 @retval EFI_DEVICE_ERROR Unexpected device behavior.
192 **/
193 EFI_STATUS
194 EFIAPI
195 Tpm2ClearControl (
196 IN TPMI_RH_CLEAR AuthHandle,
197 IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL
198 IN TPMI_YES_NO Disable
199 );
200
201 /**
202 This command allows the authorization secret for a hierarchy or lockout to be changed using the current
203 authorization value as the command authorization.
204
205 @param[in] AuthHandle TPM_RH_LOCKOUT, TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}
206 @param[in] AuthSession Auth Session context
207 @param[in] NewAuth New authorization secret
208
209 @retval EFI_SUCCESS Operation completed successfully.
210 @retval EFI_DEVICE_ERROR Unexpected device behavior.
211 **/
212 EFI_STATUS
213 EFIAPI
214 Tpm2HierarchyChangeAuth (
215 IN TPMI_RH_HIERARCHY_AUTH AuthHandle,
216 IN TPMS_AUTH_COMMAND *AuthSession,
217 IN TPM2B_AUTH *NewAuth
218 );
219
220 /**
221 This replaces the current EPS with a value from the RNG and sets the Endorsement hierarchy controls to
222 their default initialization values.
223
224 @param[in] AuthHandle TPM_RH_PLATFORM+{PP}
225 @param[in] AuthSession Auth Session context
226
227 @retval EFI_SUCCESS Operation completed successfully.
228 @retval EFI_DEVICE_ERROR Unexpected device behavior.
229 **/
230 EFI_STATUS
231 EFIAPI
232 Tpm2ChangeEPS (
233 IN TPMI_RH_PLATFORM AuthHandle,
234 IN TPMS_AUTH_COMMAND *AuthSession
235 );
236
237 /**
238 This replaces the current PPS with a value from the RNG and sets platformPolicy to the default
239 initialization value (the Empty Buffer).
240
241 @param[in] AuthHandle TPM_RH_PLATFORM+{PP}
242 @param[in] AuthSession Auth Session context
243
244 @retval EFI_SUCCESS Operation completed successfully.
245 @retval EFI_DEVICE_ERROR Unexpected device behavior.
246 **/
247 EFI_STATUS
248 EFIAPI
249 Tpm2ChangePPS (
250 IN TPMI_RH_PLATFORM AuthHandle,
251 IN TPMS_AUTH_COMMAND *AuthSession
252 );
253
254 /**
255 This command enables and disables use of a hierarchy.
256
257 @param[in] AuthHandle TPM_RH_ENDORSEMENT, TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}
258 @param[in] AuthSession Auth Session context
259 @param[in] Hierarchy Hierarchy of the enable being modified
260 @param[in] State YES if the enable should be SET,
261 NO if the enable should be CLEAR
262
263 @retval EFI_SUCCESS Operation completed successfully.
264 @retval EFI_DEVICE_ERROR Unexpected device behavior.
265 **/
266 EFI_STATUS
267 EFIAPI
268 Tpm2HierarchyControl (
269 IN TPMI_RH_HIERARCHY AuthHandle,
270 IN TPMS_AUTH_COMMAND *AuthSession,
271 IN TPMI_RH_HIERARCHY Hierarchy,
272 IN TPMI_YES_NO State
273 );
274
275 /**
276 This command cancels the effect of a TPM lockout due to a number of successive authorization failures.
277 If this command is properly authorized, the lockout counter is set to zero.
278
279 @param[in] LockHandle LockHandle
280 @param[in] AuthSession Auth Session context
281
282 @retval EFI_SUCCESS Operation completed successfully.
283 @retval EFI_DEVICE_ERROR Unexpected device behavior.
284 **/
285 EFI_STATUS
286 EFIAPI
287 Tpm2DictionaryAttackLockReset (
288 IN TPMI_RH_LOCKOUT LockHandle,
289 IN TPMS_AUTH_COMMAND *AuthSession
290 );
291
292 /**
293 This command cancels the effect of a TPM lockout due to a number of successive authorization failures.
294 If this command is properly authorized, the lockout counter is set to zero.
295
296 @param[in] LockHandle LockHandle
297 @param[in] AuthSession Auth Session context
298 @param[in] NewMaxTries Count of authorization failures before the lockout is imposed
299 @param[in] NewRecoveryTime Time in seconds before the authorization failure count is automatically decremented
300 @param[in] LockoutRecovery Time in seconds after a lockoutAuth failure before use of lockoutAuth is allowed
301
302 @retval EFI_SUCCESS Operation completed successfully.
303 @retval EFI_DEVICE_ERROR Unexpected device behavior.
304 **/
305 EFI_STATUS
306 EFIAPI
307 Tpm2DictionaryAttackParameters (
308 IN TPMI_RH_LOCKOUT LockHandle,
309 IN TPMS_AUTH_COMMAND *AuthSession,
310 IN UINT32 NewMaxTries,
311 IN UINT32 NewRecoveryTime,
312 IN UINT32 LockoutRecovery
313 );
314
315 /**
316 This command is used to read the public area and Name of an NV Index.
317
318 @param[in] NvIndex The NV Index.
319 @param[out] NvPublic The public area of the index.
320 @param[out] NvName The Name of the nvIndex.
321
322 @retval EFI_SUCCESS Operation completed successfully.
323 @retval EFI_DEVICE_ERROR The command was unsuccessful.
324 **/
325 EFI_STATUS
326 EFIAPI
327 Tpm2NvReadPublic (
328 IN TPMI_RH_NV_INDEX NvIndex,
329 OUT TPM2B_NV_PUBLIC *NvPublic,
330 OUT TPM2B_NAME *NvName
331 );
332
333 /**
334 This command defines the attributes of an NV Index and causes the TPM to
335 reserve space to hold the data associated with the index.
336 If a definition already exists at the index, the TPM will return TPM_RC_NV_DEFINED.
337
338 @param[in] AuthHandle TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
339 @param[in] AuthSession Auth Session context
340 @param[in] Auth The authorization data.
341 @param[in] NvPublic The public area of the index.
342
343 @retval EFI_SUCCESS Operation completed successfully.
344 @retval EFI_DEVICE_ERROR The command was unsuccessful.
345 @retval EFI_ALREADY_STARTED The command was returned successfully, but NvIndex is already defined.
346 **/
347 EFI_STATUS
348 EFIAPI
349 Tpm2NvDefineSpace (
350 IN TPMI_RH_PROVISION AuthHandle,
351 IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL
352 IN TPM2B_AUTH *Auth,
353 IN TPM2B_NV_PUBLIC *NvPublic
354 );
355
356 /**
357 This command removes an index from the TPM.
358
359 @param[in] AuthHandle TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
360 @param[in] NvIndex The NV Index.
361 @param[in] AuthSession Auth Session context
362
363 @retval EFI_SUCCESS Operation completed successfully.
364 @retval EFI_DEVICE_ERROR The command was unsuccessful.
365 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
366 **/
367 EFI_STATUS
368 EFIAPI
369 Tpm2NvUndefineSpace (
370 IN TPMI_RH_PROVISION AuthHandle,
371 IN TPMI_RH_NV_INDEX NvIndex,
372 IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL
373 );
374
375 /**
376 This command reads a value from an area in NV memory previously defined by TPM2_NV_DefineSpace().
377
378 @param[in] AuthHandle the handle indicating the source of the authorization value.
379 @param[in] NvIndex The index to be read.
380 @param[in] AuthSession Auth Session context
381 @param[in] Size Number of bytes to read.
382 @param[in] Offset Byte offset into the area.
383 @param[in,out] OutData The data read.
384
385 @retval EFI_SUCCESS Operation completed successfully.
386 @retval EFI_DEVICE_ERROR The command was unsuccessful.
387 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
388 **/
389 EFI_STATUS
390 EFIAPI
391 Tpm2NvRead (
392 IN TPMI_RH_NV_AUTH AuthHandle,
393 IN TPMI_RH_NV_INDEX NvIndex,
394 IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL
395 IN UINT16 Size,
396 IN UINT16 Offset,
397 IN OUT TPM2B_MAX_BUFFER *OutData
398 );
399
400 /**
401 This command writes a value to an area in NV memory that was previously defined by TPM2_NV_DefineSpace().
402
403 @param[in] AuthHandle the handle indicating the source of the authorization value.
404 @param[in] NvIndex The NV Index of the area to write.
405 @param[in] AuthSession Auth Session context
406 @param[in] InData The data to write.
407 @param[in] Offset The offset into the NV Area.
408
409 @retval EFI_SUCCESS Operation completed successfully.
410 @retval EFI_DEVICE_ERROR The command was unsuccessful.
411 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
412 **/
413 EFI_STATUS
414 EFIAPI
415 Tpm2NvWrite (
416 IN TPMI_RH_NV_AUTH AuthHandle,
417 IN TPMI_RH_NV_INDEX NvIndex,
418 IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL
419 IN TPM2B_MAX_BUFFER *InData,
420 IN UINT16 Offset
421 );
422
423 /**
424 This command may be used to prevent further reads of the Index until the next TPM2_Startup (TPM_SU_CLEAR).
425
426 @param[in] AuthHandle the handle indicating the source of the authorization value.
427 @param[in] NvIndex The NV Index of the area to lock.
428 @param[in] AuthSession Auth Session context
429
430 @retval EFI_SUCCESS Operation completed successfully.
431 @retval EFI_DEVICE_ERROR The command was unsuccessful.
432 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
433 **/
434 EFI_STATUS
435 EFIAPI
436 Tpm2NvReadLock (
437 IN TPMI_RH_NV_AUTH AuthHandle,
438 IN TPMI_RH_NV_INDEX NvIndex,
439 IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL
440 );
441
442 /**
443 This command may be used to inhibit further writes of the Index.
444
445 @param[in] AuthHandle the handle indicating the source of the authorization value.
446 @param[in] NvIndex The NV Index of the area to lock.
447 @param[in] AuthSession Auth Session context
448
449 @retval EFI_SUCCESS Operation completed successfully.
450 @retval EFI_DEVICE_ERROR The command was unsuccessful.
451 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
452 **/
453 EFI_STATUS
454 EFIAPI
455 Tpm2NvWriteLock (
456 IN TPMI_RH_NV_AUTH AuthHandle,
457 IN TPMI_RH_NV_INDEX NvIndex,
458 IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL
459 );
460
461 /**
462 The command will SET TPMA_NV_WRITELOCKED for all indexes that have their TPMA_NV_GLOBALLOCK attribute SET.
463
464 @param[in] AuthHandle TPM_RH_OWNER or TPM_RH_PLATFORM+{PP}.
465 @param[in] AuthSession Auth Session context
466
467 @retval EFI_SUCCESS Operation completed successfully.
468 @retval EFI_DEVICE_ERROR The command was unsuccessful.
469 @retval EFI_NOT_FOUND The command was returned successfully, but NvIndex is not found.
470 **/
471 EFI_STATUS
472 EFIAPI
473 Tpm2NvGlobalWriteLock (
474 IN TPMI_RH_PROVISION AuthHandle,
475 IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL
476 );
477
478 /**
479 This command is used to cause an update to the indicated PCR.
480 The digests parameter contains one or more tagged digest value identified by an algorithm ID.
481 For each digest, the PCR associated with pcrHandle is Extended into the bank identified by the tag (hashAlg).
482
483 @param[in] PcrHandle Handle of the PCR
484 @param[in] Digests List of tagged digest values to be extended
485
486 @retval EFI_SUCCESS Operation completed successfully.
487 @retval EFI_DEVICE_ERROR Unexpected device behavior.
488 **/
489 EFI_STATUS
490 EFIAPI
491 Tpm2PcrExtend (
492 IN TPMI_DH_PCR PcrHandle,
493 IN TPML_DIGEST_VALUES *Digests
494 );
495
496 /**
497 This command is used to cause an update to the indicated PCR.
498 The data in eventData is hashed using the hash algorithm associated with each bank in which the
499 indicated PCR has been allocated. After the data is hashed, the digests list is returned. If the pcrHandle
500 references an implemented PCR and not TPM_ALG_NULL, digests list is processed as in
501 TPM2_PCR_Extend().
502 A TPM shall support an Event.size of zero through 1,024 inclusive.
503
504 @param[in] PcrHandle Handle of the PCR
505 @param[in] EventData Event data in sized buffer
506 @param[out] Digests List of digest
507
508 @retval EFI_SUCCESS Operation completed successfully.
509 @retval EFI_DEVICE_ERROR Unexpected device behavior.
510 **/
511 EFI_STATUS
512 EFIAPI
513 Tpm2PcrEvent (
514 IN TPMI_DH_PCR PcrHandle,
515 IN TPM2B_EVENT *EventData,
516 OUT TPML_DIGEST_VALUES *Digests
517 );
518
519 /**
520 This command returns the values of all PCR specified in pcrSelect.
521
522 @param[in] PcrSelectionIn The selection of PCR to read.
523 @param[out] PcrUpdateCounter The current value of the PCR update counter.
524 @param[out] PcrSelectionOut The PCR in the returned list.
525 @param[out] PcrValues The contents of the PCR indicated in pcrSelect.
526
527 @retval EFI_SUCCESS Operation completed successfully.
528 @retval EFI_DEVICE_ERROR The command was unsuccessful.
529 **/
530 EFI_STATUS
531 EFIAPI
532 Tpm2PcrRead (
533 IN TPML_PCR_SELECTION *PcrSelectionIn,
534 OUT UINT32 *PcrUpdateCounter,
535 OUT TPML_PCR_SELECTION *PcrSelectionOut,
536 OUT TPML_DIGEST *PcrValues
537 );
538
539 /**
540 This command is used to set the desired PCR allocation of PCR and algorithms.
541
542 @param[in] AuthHandle TPM_RH_PLATFORM+{PP}
543 @param[in] AuthSession Auth Session context
544 @param[in] PcrAllocation The requested allocation
545 @param[out] AllocationSuccess YES if the allocation succeeded
546 @param[out] MaxPCR maximum number of PCR that may be in a bank
547 @param[out] SizeNeeded number of octets required to satisfy the request
548 @param[out] SizeAvailable Number of octets available. Computed before the allocation
549
550 @retval EFI_SUCCESS Operation completed successfully.
551 @retval EFI_DEVICE_ERROR The command was unsuccessful.
552 **/
553 EFI_STATUS
554 EFIAPI
555 Tpm2PcrAllocate (
556 IN TPMI_RH_PLATFORM AuthHandle,
557 IN TPMS_AUTH_COMMAND *AuthSession,
558 IN TPML_PCR_SELECTION *PcrAllocation,
559 OUT TPMI_YES_NO *AllocationSuccess,
560 OUT UINT32 *MaxPCR,
561 OUT UINT32 *SizeNeeded,
562 OUT UINT32 *SizeAvailable
563 );
564
565 /**
566 Alloc PCR data.
567
568 @param[in] PlatformAuth platform auth value. NULL means no platform auth change.
569 @param[in] SupportedPCRBanks Supported PCR banks
570 @param[in] PCRBanks PCR banks
571
572 @retval EFI_SUCCESS Operation completed successfully.
573 **/
574 EFI_STATUS
575 EFIAPI
576 Tpm2PcrAllocateBanks (
577 IN TPM2B_AUTH *PlatformAuth, OPTIONAL
578 IN UINT32 SupportedPCRBanks,
579 IN UINT32 PCRBanks
580 );
581
582 /**
583 This command returns various information regarding the TPM and its current state.
584
585 The capability parameter determines the category of data returned. The property parameter
586 selects the first value of the selected category to be returned. If there is no property
587 that corresponds to the value of property, the next higher value is returned, if it exists.
588 The moreData parameter will have a value of YES if there are more values of the requested
589 type that were not returned.
590 If no next capability exists, the TPM will return a zero-length list and moreData will have
591 a value of NO.
592
593 NOTE:
594 To simplify this function, leave returned CapabilityData for caller to unpack since there are
595 many capability categories and only few categories will be used in firmware. It means the caller
596 need swap the byte order for the feilds in CapabilityData.
597
598 @param[in] Capability Group selection; determines the format of the response.
599 @param[in] Property Further definition of information.
600 @param[in] PropertyCount Number of properties of the indicated type to return.
601 @param[out] MoreData Flag to indicate if there are more values of this type.
602 @param[out] CapabilityData The capability data.
603
604 @retval EFI_SUCCESS Operation completed successfully.
605 @retval EFI_DEVICE_ERROR The command was unsuccessful.
606 **/
607 EFI_STATUS
608 EFIAPI
609 Tpm2GetCapability (
610 IN TPM_CAP Capability,
611 IN UINT32 Property,
612 IN UINT32 PropertyCount,
613 OUT TPMI_YES_NO *MoreData,
614 OUT TPMS_CAPABILITY_DATA *CapabilityData
615 );
616
617 /**
618 This command returns the information of TPM Family.
619
620 This function parse the value got from TPM2_GetCapability and return the Family.
621
622 @param[out] Family The Family of TPM. (a 4-octet character string)
623
624 @retval EFI_SUCCESS Operation completed successfully.
625 @retval EFI_DEVICE_ERROR The command was unsuccessful.
626 **/
627 EFI_STATUS
628 EFIAPI
629 Tpm2GetCapabilityFamily (
630 OUT CHAR8 *Family
631 );
632
633 /**
634 This command returns the information of TPM manufacture ID.
635
636 This function parse the value got from TPM2_GetCapability and return the TPM manufacture ID.
637
638 @param[out] ManufactureId The manufacture ID of TPM.
639
640 @retval EFI_SUCCESS Operation completed successfully.
641 @retval EFI_DEVICE_ERROR The command was unsuccessful.
642 **/
643 EFI_STATUS
644 EFIAPI
645 Tpm2GetCapabilityManufactureID (
646 OUT UINT32 *ManufactureId
647 );
648
649 /**
650 This command returns the information of TPM FirmwareVersion.
651
652 This function parse the value got from TPM2_GetCapability and return the TPM FirmwareVersion.
653
654 @param[out] FirmwareVersion1 The FirmwareVersion1.
655 @param[out] FirmwareVersion2 The FirmwareVersion2.
656
657 @retval EFI_SUCCESS Operation completed successfully.
658 @retval EFI_DEVICE_ERROR The command was unsuccessful.
659 **/
660 EFI_STATUS
661 EFIAPI
662 Tpm2GetCapabilityFirmwareVersion (
663 OUT UINT32 *FirmwareVersion1,
664 OUT UINT32 *FirmwareVersion2
665 );
666
667 /**
668 This command returns the information of the maximum value for commandSize and responseSize in a command.
669
670 This function parse the value got from TPM2_GetCapability and return the max command size and response size
671
672 @param[out] MaxCommandSize The maximum value for commandSize in a command.
673 @param[out] MaxResponseSize The maximum value for responseSize in a command.
674
675 @retval EFI_SUCCESS Operation completed successfully.
676 @retval EFI_DEVICE_ERROR The command was unsuccessful.
677 **/
678 EFI_STATUS
679 EFIAPI
680 Tpm2GetCapabilityMaxCommandResponseSize (
681 OUT UINT32 *MaxCommandSize,
682 OUT UINT32 *MaxResponseSize
683 );
684
685 /**
686 This command returns Returns a list of TPMS_ALG_PROPERTIES. Each entry is an
687 algorithm ID and a set of properties of the algorithm.
688
689 This function parse the value got from TPM2_GetCapability and return the list.
690
691 @param[out] AlgList List of algorithm.
692
693 @retval EFI_SUCCESS Operation completed successfully.
694 @retval EFI_DEVICE_ERROR The command was unsuccessful.
695 **/
696 EFI_STATUS
697 EFIAPI
698 Tpm2GetCapabilitySupportedAlg (
699 OUT TPML_ALG_PROPERTY *AlgList
700 );
701
702 /**
703 This command returns the information of TPM LockoutCounter.
704
705 This function parse the value got from TPM2_GetCapability and return the LockoutCounter.
706
707 @param[out] LockoutCounter The LockoutCounter of TPM.
708
709 @retval EFI_SUCCESS Operation completed successfully.
710 @retval EFI_DEVICE_ERROR The command was unsuccessful.
711 **/
712 EFI_STATUS
713 EFIAPI
714 Tpm2GetCapabilityLockoutCounter (
715 OUT UINT32 *LockoutCounter
716 );
717
718 /**
719 This command returns the information of TPM LockoutInterval.
720
721 This function parse the value got from TPM2_GetCapability and return the LockoutInterval.
722
723 @param[out] LockoutInterval The LockoutInterval of TPM.
724
725 @retval EFI_SUCCESS Operation completed successfully.
726 @retval EFI_DEVICE_ERROR The command was unsuccessful.
727 **/
728 EFI_STATUS
729 EFIAPI
730 Tpm2GetCapabilityLockoutInterval (
731 OUT UINT32 *LockoutInterval
732 );
733
734 /**
735 This command returns the information of TPM InputBufferSize.
736
737 This function parse the value got from TPM2_GetCapability and return the InputBufferSize.
738
739 @param[out] InputBufferSize The InputBufferSize of TPM.
740 the maximum size of a parameter (typically, a TPM2B_MAX_BUFFER)
741
742 @retval EFI_SUCCESS Operation completed successfully.
743 @retval EFI_DEVICE_ERROR The command was unsuccessful.
744 **/
745 EFI_STATUS
746 EFIAPI
747 Tpm2GetCapabilityInputBufferSize (
748 OUT UINT32 *InputBufferSize
749 );
750
751 /**
752 This command returns the information of TPM PCRs.
753
754 This function parse the value got from TPM2_GetCapability and return the PcrSelection.
755
756 @param[out] Pcrs The Pcr Selection
757
758 @retval EFI_SUCCESS Operation completed successfully.
759 @retval EFI_DEVICE_ERROR The command was unsuccessful.
760 **/
761 EFI_STATUS
762 EFIAPI
763 Tpm2GetCapabilityPcrs (
764 OUT TPML_PCR_SELECTION *Pcrs
765 );
766
767 /**
768 This function will query the TPM to determine which hashing algorithms
769 are supported and which PCR banks are currently active.
770
771 @param[out] TpmHashAlgorithmBitmap A bitmask containing the algorithms supported by the TPM.
772 @param[out] ActivePcrBanks A bitmask containing the PCRs currently allocated.
773
774 @retval EFI_SUCCESS TPM was successfully queried and return values can be trusted.
775 @retval Others An error occurred, likely in communication with the TPM.
776
777 **/
778 EFI_STATUS
779 EFIAPI
780 Tpm2GetCapabilitySupportedAndActivePcrs(
781 OUT UINT32 *TpmHashAlgorithmBitmap,
782 OUT UINT32 *ActivePcrBanks
783 );
784
785 /**
786 This command returns the information of TPM AlgorithmSet.
787
788 This function parse the value got from TPM2_GetCapability and return the AlgorithmSet.
789
790 @param[out] AlgorithmSet The AlgorithmSet of TPM.
791
792 @retval EFI_SUCCESS Operation completed successfully.
793 @retval EFI_DEVICE_ERROR The command was unsuccessful.
794 **/
795 EFI_STATUS
796 EFIAPI
797 Tpm2GetCapabilityAlgorithmSet (
798 OUT UINT32 *AlgorithmSet
799 );
800
801 /**
802 This command is used to check to see if specific combinations of algorithm parameters are supported.
803
804 @param[in] Parameters Algorithm parameters to be validated
805
806 @retval EFI_SUCCESS Operation completed successfully.
807 @retval EFI_DEVICE_ERROR Unexpected device behavior.
808 **/
809 EFI_STATUS
810 EFIAPI
811 Tpm2TestParms (
812 IN TPMT_PUBLIC_PARMS *Parameters
813 );
814
815 /**
816 This command allows the platform to change the set of algorithms that are used by the TPM.
817 The algorithmSet setting is a vendor-dependent value.
818
819 @param[in] AuthHandle TPM_RH_PLATFORM
820 @param[in] AuthSession Auth Session context
821 @param[in] AlgorithmSet A TPM vendor-dependent value indicating the
822 algorithm set selection
823
824 @retval EFI_SUCCESS Operation completed successfully.
825 @retval EFI_DEVICE_ERROR Unexpected device behavior.
826 **/
827 EFI_STATUS
828 EFIAPI
829 Tpm2SetAlgorithmSet (
830 IN TPMI_RH_PLATFORM AuthHandle,
831 IN TPMS_AUTH_COMMAND *AuthSession,
832 IN UINT32 AlgorithmSet
833 );
834
835 /**
836 This command is used to start an authorization session using alternative methods of
837 establishing the session key (sessionKey) that is used for authorization and encrypting value.
838
839 @param[in] TpmKey Handle of a loaded decrypt key used to encrypt salt.
840 @param[in] Bind Entity providing the authValue.
841 @param[in] NonceCaller Initial nonceCaller, sets nonce size for the session.
842 @param[in] Salt Value encrypted according to the type of tpmKey.
843 @param[in] SessionType Indicates the type of the session.
844 @param[in] Symmetric The algorithm and key size for parameter encryption.
845 @param[in] AuthHash Hash algorithm to use for the session.
846 @param[out] SessionHandle Handle for the newly created session.
847 @param[out] NonceTPM The initial nonce from the TPM, used in the computation of the sessionKey.
848
849 @retval EFI_SUCCESS Operation completed successfully.
850 @retval EFI_DEVICE_ERROR The command was unsuccessful.
851 **/
852 EFI_STATUS
853 EFIAPI
854 Tpm2StartAuthSession (
855 IN TPMI_DH_OBJECT TpmKey,
856 IN TPMI_DH_ENTITY Bind,
857 IN TPM2B_NONCE *NonceCaller,
858 IN TPM2B_ENCRYPTED_SECRET *Salt,
859 IN TPM_SE SessionType,
860 IN TPMT_SYM_DEF *Symmetric,
861 IN TPMI_ALG_HASH AuthHash,
862 OUT TPMI_SH_AUTH_SESSION *SessionHandle,
863 OUT TPM2B_NONCE *NonceTPM
864 );
865
866 /**
867 This command causes all context associated with a loaded object or session to be removed from TPM memory.
868
869 @param[in] FlushHandle The handle of the item to flush.
870
871 @retval EFI_SUCCESS Operation completed successfully.
872 @retval EFI_DEVICE_ERROR The command was unsuccessful.
873 **/
874 EFI_STATUS
875 EFIAPI
876 Tpm2FlushContext (
877 IN TPMI_DH_CONTEXT FlushHandle
878 );
879
880 /**
881 This command includes a secret-based authorization to a policy.
882 The caller proves knowledge of the secret value using an authorization
883 session using the authValue associated with authHandle.
884
885 @param[in] AuthHandle Handle for an entity providing the authorization
886 @param[in] PolicySession Handle for the policy session being extended.
887 @param[in] AuthSession Auth Session context
888 @param[in] NonceTPM The policy nonce for the session.
889 @param[in] CpHashA Digest of the command parameters to which this authorization is limited.
890 @param[in] PolicyRef A reference to a policy relating to the authorization.
891 @param[in] Expiration Time when authorization will expire, measured in seconds from the time that nonceTPM was generated.
892 @param[out] Timeout Time value used to indicate to the TPM when the ticket expires.
893 @param[out] PolicyTicket A ticket that includes a value indicating when the authorization expires.
894
895 @retval EFI_SUCCESS Operation completed successfully.
896 @retval EFI_DEVICE_ERROR The command was unsuccessful.
897 **/
898 EFI_STATUS
899 EFIAPI
900 Tpm2PolicySecret (
901 IN TPMI_DH_ENTITY AuthHandle,
902 IN TPMI_SH_POLICY PolicySession,
903 IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL
904 IN TPM2B_NONCE *NonceTPM,
905 IN TPM2B_DIGEST *CpHashA,
906 IN TPM2B_NONCE *PolicyRef,
907 IN INT32 Expiration,
908 OUT TPM2B_TIMEOUT *Timeout,
909 OUT TPMT_TK_AUTH *PolicyTicket
910 );
911
912 /**
913 This command allows options in authorizations without requiring that the TPM evaluate all of the options.
914 If a policy may be satisfied by different sets of conditions, the TPM need only evaluate one set that
915 satisfies the policy. This command will indicate that one of the required sets of conditions has been
916 satisfied.
917
918 @param[in] PolicySession Handle for the policy session being extended.
919 @param[in] HashList the list of hashes to check for a match.
920
921 @retval EFI_SUCCESS Operation completed successfully.
922 @retval EFI_DEVICE_ERROR The command was unsuccessful.
923 **/
924 EFI_STATUS
925 EFIAPI
926 Tpm2PolicyOR (
927 IN TPMI_SH_POLICY PolicySession,
928 IN TPML_DIGEST *HashList
929 );
930
931 /**
932 This command indicates that the authorization will be limited to a specific command code.
933
934 @param[in] PolicySession Handle for the policy session being extended.
935 @param[in] Code The allowed commandCode.
936
937 @retval EFI_SUCCESS Operation completed successfully.
938 @retval EFI_DEVICE_ERROR The command was unsuccessful.
939 **/
940 EFI_STATUS
941 EFIAPI
942 Tpm2PolicyCommandCode (
943 IN TPMI_SH_POLICY PolicySession,
944 IN TPM_CC Code
945 );
946
947 /**
948 This command returns the current policyDigest of the session. This command allows the TPM
949 to be used to perform the actions required to precompute the authPolicy for an object.
950
951 @param[in] PolicySession Handle for the policy session.
952 @param[out] PolicyHash the current value of the policyHash of policySession.
953
954 @retval EFI_SUCCESS Operation completed successfully.
955 @retval EFI_DEVICE_ERROR The command was unsuccessful.
956 **/
957 EFI_STATUS
958 EFIAPI
959 Tpm2PolicyGetDigest (
960 IN TPMI_SH_POLICY PolicySession,
961 OUT TPM2B_DIGEST *PolicyHash
962 );
963
964 /**
965 This command allows access to the public area of a loaded object.
966
967 @param[in] ObjectHandle TPM handle of an object
968 @param[out] OutPublic Structure containing the public area of an object
969 @param[out] Name Name of the object
970 @param[out] QualifiedName The Qualified Name of the object
971
972 @retval EFI_SUCCESS Operation completed successfully.
973 @retval EFI_DEVICE_ERROR Unexpected device behavior.
974 **/
975 EFI_STATUS
976 EFIAPI
977 Tpm2ReadPublic (
978 IN TPMI_DH_OBJECT ObjectHandle,
979 OUT TPM2B_PUBLIC *OutPublic,
980 OUT TPM2B_NAME *Name,
981 OUT TPM2B_NAME *QualifiedName
982 );
983
984 //
985 // Help function
986 //
987
988 /**
989 Copy AuthSessionIn to TPM2 command buffer.
990
991 @param [in] AuthSessionIn Input AuthSession data
992 @param [out] AuthSessionOut Output AuthSession data in TPM2 command buffer
993
994 @return AuthSession size
995 **/
996 UINT32
997 EFIAPI
998 CopyAuthSessionCommand (
999 IN TPMS_AUTH_COMMAND *AuthSessionIn, OPTIONAL
1000 OUT UINT8 *AuthSessionOut
1001 );
1002
1003 /**
1004 Copy AuthSessionIn from TPM2 response buffer.
1005
1006 @param [in] AuthSessionIn Input AuthSession data in TPM2 response buffer
1007 @param [out] AuthSessionOut Output AuthSession data
1008
1009 @return AuthSession size
1010 **/
1011 UINT32
1012 EFIAPI
1013 CopyAuthSessionResponse (
1014 IN UINT8 *AuthSessionIn,
1015 OUT TPMS_AUTH_RESPONSE *AuthSessionOut OPTIONAL
1016 );
1017
1018 /**
1019 Return size of digest.
1020
1021 @param[in] HashAlgo Hash algorithm
1022
1023 @return size of digest
1024 **/
1025 UINT16
1026 EFIAPI
1027 GetHashSizeFromAlgo (
1028 IN TPMI_ALG_HASH HashAlgo
1029 );
1030
1031 /**
1032 Get hash mask from algorithm.
1033
1034 @param[in] HashAlgo Hash algorithm
1035
1036 @return Hash mask
1037 **/
1038 UINT32
1039 EFIAPI
1040 GetHashMaskFromAlgo (
1041 IN TPMI_ALG_HASH HashAlgo
1042 );
1043
1044 /**
1045 Return if hash alg is supported in HashAlgorithmMask.
1046
1047 @param HashAlg Hash algorithm to be checked.
1048 @param HashAlgorithmMask Bitfield of allowed hash algorithms.
1049
1050 @retval TRUE Hash algorithm is supported.
1051 @retval FALSE Hash algorithm is not supported.
1052 **/
1053 BOOLEAN
1054 EFIAPI
1055 IsHashAlgSupportedInHashAlgorithmMask(
1056 IN TPMI_ALG_HASH HashAlg,
1057 IN UINT32 HashAlgorithmMask
1058 );
1059
1060 /**
1061 Copy TPML_DIGEST_VALUES into a buffer
1062
1063 @param[in,out] Buffer Buffer to hold copied TPML_DIGEST_VALUES compact binary.
1064 @param[in] DigestList TPML_DIGEST_VALUES to be copied.
1065 @param[in] HashAlgorithmMask HASH bits corresponding to the desired digests to copy.
1066
1067 @return The end of buffer to hold TPML_DIGEST_VALUES.
1068 **/
1069 VOID *
1070 EFIAPI
1071 CopyDigestListToBuffer(
1072 IN OUT VOID *Buffer,
1073 IN TPML_DIGEST_VALUES *DigestList,
1074 IN UINT32 HashAlgorithmMask
1075 );
1076
1077 /**
1078 Get TPML_DIGEST_VALUES data size.
1079
1080 @param[in] DigestList TPML_DIGEST_VALUES data.
1081
1082 @return TPML_DIGEST_VALUES data size.
1083 **/
1084 UINT32
1085 EFIAPI
1086 GetDigestListSize(
1087 IN TPML_DIGEST_VALUES *DigestList
1088 );
1089
1090 /**
1091 This function get digest from digest list.
1092
1093 @param[in] HashAlg Digest algorithm
1094 @param[in] DigestList Digest list
1095 @param[out] Digest Digest
1096
1097 @retval EFI_SUCCESS Digest is found and returned.
1098 @retval EFI_NOT_FOUND Digest is not found.
1099 **/
1100 EFI_STATUS
1101 EFIAPI
1102 GetDigestFromDigestList(
1103 IN TPMI_ALG_HASH HashAlg,
1104 IN TPML_DIGEST_VALUES *DigestList,
1105 OUT VOID *Digest
1106 );
1107
1108 #endif
Tpm2GetCapabilitySupportedAlg
EFI_STATUS Tpm2GetCapabilitySupportedAlg(OUT TPML_ALG_PROPERTY *AlgList)
This command returns Returns a list of TPMS_ALG_PROPERTIES.
GetHashMaskFromAlgo
UINT32 GetHashMaskFromAlgo(IN TPMI_ALG_HASH HashAlgo)
Get hash mask from algorithm.
Tpm2TestParms
EFI_STATUS Tpm2TestParms(IN TPMT_PUBLIC_PARMS *Parameters)
This command is used to check to see if specific combinations of algorithm parameters are supported.
Tpm2PolicyOR
EFI_STATUS Tpm2PolicyOR(IN TPMI_SH_POLICY PolicySession, IN TPML_DIGEST *HashList)
This command allows options in authorizations without requiring that the TPM evaluate all of the opti...
Tpm2NvGlobalWriteLock
EFI_STATUS Tpm2NvGlobalWriteLock(IN TPMI_RH_PROVISION AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
The command will SET TPMA_NV_WRITELOCKED for all indexes that have their TPMA_NV_GLOBALLOCK attribute...
Tpm2GetCapabilityInputBufferSize
EFI_STATUS Tpm2GetCapabilityInputBufferSize(OUT UINT32 *InputBufferSize)
This command returns the information of TPM InputBufferSize.
Tpm2ChangePPS
EFI_STATUS Tpm2ChangePPS(IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This replaces the current PPS with a value from the RNG and sets platformPolicy to the default initia...
Tpm2GetCapabilityMaxCommandResponseSize
EFI_STATUS Tpm2GetCapabilityMaxCommandResponseSize(OUT UINT32 *MaxCommandSize, OUT UINT32 *MaxResponseSize)
This command returns the information of the maximum value for commandSize and responseSize in a comma...
Tpm2PolicySecret
EFI_STATUS Tpm2PolicySecret(IN TPMI_DH_ENTITY AuthHandle, IN TPMI_SH_POLICY PolicySession, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_NONCE *NonceTPM, IN TPM2B_DIGEST *CpHashA, IN TPM2B_NONCE *PolicyRef, IN INT32 Expiration, OUT TPM2B_TIMEOUT *Timeout, OUT TPMT_TK_AUTH *PolicyTicket)
This command includes a secret-based authorization to a policy.
Tpm2GetCapabilityLockoutCounter
EFI_STATUS Tpm2GetCapabilityLockoutCounter(OUT UINT32 *LockoutCounter)
This command returns the information of TPM LockoutCounter.
Tpm2DictionaryAttackLockReset
EFI_STATUS Tpm2DictionaryAttackLockReset(IN TPMI_RH_LOCKOUT LockHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This command cancels the effect of a TPM lockout due to a number of successive authorization failures...
Tpm2GetCapability
EFI_STATUS Tpm2GetCapability(IN TPM_CAP Capability, IN UINT32 Property, IN UINT32 PropertyCount, OUT TPMI_YES_NO *MoreData, OUT TPMS_CAPABILITY_DATA *CapabilityData)
This command returns various information regarding the TPM and its current state.
Tpm2PolicyGetDigest
EFI_STATUS Tpm2PolicyGetDigest(IN TPMI_SH_POLICY PolicySession, OUT TPM2B_DIGEST *PolicyHash)
This command returns the current policyDigest of the session.
Tpm2ReadPublic
EFI_STATUS Tpm2ReadPublic(IN TPMI_DH_OBJECT ObjectHandle, OUT TPM2B_PUBLIC *OutPublic, OUT TPM2B_NAME *Name, OUT TPM2B_NAME *QualifiedName)
This command allows access to the public area of a loaded object.
Tpm2NvUndefineSpace
EFI_STATUS Tpm2NvUndefineSpace(IN TPMI_RH_PROVISION AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command removes an index from the TPM.
Tpm2PcrEvent
EFI_STATUS Tpm2PcrEvent(IN TPMI_DH_PCR PcrHandle, IN TPM2B_EVENT *EventData, OUT TPML_DIGEST_VALUES *Digests)
This command is used to cause an update to the indicated PCR.
IsHashAlgSupportedInHashAlgorithmMask
BOOLEAN IsHashAlgSupportedInHashAlgorithmMask(IN TPMI_ALG_HASH HashAlg, IN UINT32 HashAlgorithmMask)
Return if hash alg is supported in HashAlgorithmMask.
Tpm2SetPrimaryPolicy
EFI_STATUS Tpm2SetPrimaryPolicy(IN TPMI_RH_HIERARCHY_AUTH AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPM2B_DIGEST *AuthPolicy, IN TPMI_ALG_HASH HashAlg)
This command allows setting of the authorization policy for the platform hierarchy (platformPolicy),...
Tpm2HashSequenceStart
EFI_STATUS Tpm2HashSequenceStart(IN TPMI_ALG_HASH HashAlg, OUT TPMI_DH_OBJECT *SequenceHandle)
This command starts a hash or an Event sequence.
Tpm2NvWrite
EFI_STATUS Tpm2NvWrite(IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_MAX_BUFFER *InData, IN UINT16 Offset)
This command writes a value to an area in NV memory that was previously defined by TPM2_NV_DefineSpac...
GetHashSizeFromAlgo
UINT16 GetHashSizeFromAlgo(IN TPMI_ALG_HASH HashAlgo)
Return size of digest.
Tpm2EventSequenceComplete
EFI_STATUS Tpm2EventSequenceComplete(IN TPMI_DH_PCR PcrHandle, IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer, OUT TPML_DIGEST_VALUES *Results)
This command adds the last part of data, if any, to an Event sequence and returns the result in a dig...
Tpm2Startup
EFI_STATUS Tpm2Startup(IN TPM_SU StartupType)
Send Startup command to TPM2.
Tpm2GetCapabilityPcrs
EFI_STATUS Tpm2GetCapabilityPcrs(OUT TPML_PCR_SELECTION *Pcrs)
This command returns the information of TPM PCRs.
Tpm2NvDefineSpace
EFI_STATUS Tpm2NvDefineSpace(IN TPMI_RH_PROVISION AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPM2B_AUTH *Auth, IN TPM2B_NV_PUBLIC *NvPublic)
This command defines the attributes of an NV Index and causes the TPM to reserve space to hold the da...
Tpm2NvWriteLock
EFI_STATUS Tpm2NvWriteLock(IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command may be used to inhibit further writes of the Index.
Tpm2DictionaryAttackParameters
EFI_STATUS Tpm2DictionaryAttackParameters(IN TPMI_RH_LOCKOUT LockHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN UINT32 NewMaxTries, IN UINT32 NewRecoveryTime, IN UINT32 LockoutRecovery)
This command cancels the effect of a TPM lockout due to a number of successive authorization failures...
Tpm2GetCapabilityLockoutInterval
EFI_STATUS Tpm2GetCapabilityLockoutInterval(OUT UINT32 *LockoutInterval)
This command returns the information of TPM LockoutInterval.
Tpm2FlushContext
EFI_STATUS Tpm2FlushContext(IN TPMI_DH_CONTEXT FlushHandle)
This command causes all context associated with a loaded object or session to be removed from TPM mem...
Tpm2ClearControl
EFI_STATUS Tpm2ClearControl(IN TPMI_RH_CLEAR AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN TPMI_YES_NO Disable)
Disables and enables the execution of TPM2_Clear().
Tpm2HierarchyChangeAuth
EFI_STATUS Tpm2HierarchyChangeAuth(IN TPMI_RH_HIERARCHY_AUTH AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPM2B_AUTH *NewAuth)
This command allows the authorization secret for a hierarchy or lockout to be changed using the curre...
Tpm2HierarchyControl
EFI_STATUS Tpm2HierarchyControl(IN TPMI_RH_HIERARCHY AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPMI_RH_HIERARCHY Hierarchy, IN TPMI_YES_NO State)
This command enables and disables use of a hierarchy.
Tpm2GetCapabilityManufactureID
EFI_STATUS Tpm2GetCapabilityManufactureID(OUT UINT32 *ManufactureId)
This command returns the information of TPM manufacture ID.
Tpm2ChangeEPS
EFI_STATUS Tpm2ChangeEPS(IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession)
This replaces the current EPS with a value from the RNG and sets the Endorsement hierarchy controls t...
Tpm2PcrAllocate
EFI_STATUS Tpm2PcrAllocate(IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN TPML_PCR_SELECTION *PcrAllocation, OUT TPMI_YES_NO *AllocationSuccess, OUT UINT32 *MaxPCR, OUT UINT32 *SizeNeeded, OUT UINT32 *SizeAvailable)
This command is used to set the desired PCR allocation of PCR and algorithms.
Tpm2PcrExtend
EFI_STATUS Tpm2PcrExtend(IN TPMI_DH_PCR PcrHandle, IN TPML_DIGEST_VALUES *Digests)
This command is used to cause an update to the indicated PCR.
Tpm2PcrAllocateBanks
EFI_STATUS Tpm2PcrAllocateBanks(IN TPM2B_AUTH *PlatformAuth, OPTIONAL IN UINT32 SupportedPCRBanks, IN UINT32 PCRBanks)
Alloc PCR data.
Tpm2NvReadLock
EFI_STATUS Tpm2NvReadLock(IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command may be used to prevent further reads of the Index until the next TPM2_Startup (TPM_SU_CL...
Tpm2Clear
EFI_STATUS Tpm2Clear(IN TPMI_RH_CLEAR AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession OPTIONAL)
This command removes all TPM context associated with a specific Owner.
Tpm2NvRead
EFI_STATUS Tpm2NvRead(IN TPMI_RH_NV_AUTH AuthHandle, IN TPMI_RH_NV_INDEX NvIndex, IN TPMS_AUTH_COMMAND *AuthSession, OPTIONAL IN UINT16 Size, IN UINT16 Offset, IN OUT TPM2B_MAX_BUFFER *OutData)
This command reads a value from an area in NV memory previously defined by TPM2_NV_DefineSpace().
Tpm2PolicyCommandCode
EFI_STATUS Tpm2PolicyCommandCode(IN TPMI_SH_POLICY PolicySession, IN TPM_CC Code)
This command indicates that the authorization will be limited to a specific command code.
Tpm2Shutdown
EFI_STATUS Tpm2Shutdown(IN TPM_SU ShutdownType)
Send Shutdown command to TPM2.
Tpm2GetCapabilityFamily
EFI_STATUS Tpm2GetCapabilityFamily(OUT CHAR8 *Family)
This command returns the information of TPM Family.
Tpm2SequenceComplete
EFI_STATUS Tpm2SequenceComplete(IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer, OUT TPM2B_DIGEST *Result)
This command adds the last part of data, if any, to a hash/HMAC sequence and returns the result.
Tpm2StartAuthSession
EFI_STATUS Tpm2StartAuthSession(IN TPMI_DH_OBJECT TpmKey, IN TPMI_DH_ENTITY Bind, IN TPM2B_NONCE *NonceCaller, IN TPM2B_ENCRYPTED_SECRET *Salt, IN TPM_SE SessionType, IN TPMT_SYM_DEF *Symmetric, IN TPMI_ALG_HASH AuthHash, OUT TPMI_SH_AUTH_SESSION *SessionHandle, OUT TPM2B_NONCE *NonceTPM)
This command is used to start an authorization session using alternative methods of establishing the ...
Tpm2PcrRead
EFI_STATUS Tpm2PcrRead(IN TPML_PCR_SELECTION *PcrSelectionIn, OUT UINT32 *PcrUpdateCounter, OUT TPML_PCR_SELECTION *PcrSelectionOut, OUT TPML_DIGEST *PcrValues)
This command returns the values of all PCR specified in pcrSelect.
CopyAuthSessionResponse
UINT32 CopyAuthSessionResponse(IN UINT8 *AuthSessionIn, OUT TPMS_AUTH_RESPONSE *AuthSessionOut OPTIONAL)
Copy AuthSessionIn from TPM2 response buffer.
CopyDigestListToBuffer
VOID * CopyDigestListToBuffer(IN OUT VOID *Buffer, IN TPML_DIGEST_VALUES *DigestList, IN UINT32 HashAlgorithmMask)
Copy TPML_DIGEST_VALUES into a buffer.
Tpm2GetCapabilityFirmwareVersion
EFI_STATUS Tpm2GetCapabilityFirmwareVersion(OUT UINT32 *FirmwareVersion1, OUT UINT32 *FirmwareVersion2)
This command returns the information of TPM FirmwareVersion.
Tpm2NvReadPublic
EFI_STATUS Tpm2NvReadPublic(IN TPMI_RH_NV_INDEX NvIndex, OUT TPM2B_NV_PUBLIC *NvPublic, OUT TPM2B_NAME *NvName)
This command is used to read the public area and Name of an NV Index.
Tpm2GetCapabilitySupportedAndActivePcrs
EFI_STATUS Tpm2GetCapabilitySupportedAndActivePcrs(OUT UINT32 *TpmHashAlgorithmBitmap, OUT UINT32 *ActivePcrBanks)
This function will query the TPM to determine which hashing algorithms are supported and which PCR ba...
GetDigestFromDigestList
EFI_STATUS GetDigestFromDigestList(IN TPMI_ALG_HASH HashAlg, IN TPML_DIGEST_VALUES *DigestList, OUT VOID *Digest)
This function get digest from digest list.
CopyAuthSessionCommand
UINT32 CopyAuthSessionCommand(IN TPMS_AUTH_COMMAND *AuthSessionIn, OPTIONAL OUT UINT8 *AuthSessionOut)
Copy AuthSessionIn to TPM2 command buffer.
Tpm2SetAlgorithmSet
EFI_STATUS Tpm2SetAlgorithmSet(IN TPMI_RH_PLATFORM AuthHandle, IN TPMS_AUTH_COMMAND *AuthSession, IN UINT32 AlgorithmSet)
This command allows the platform to change the set of algorithms that are used by the TPM.
Tpm2SelfTest
EFI_STATUS Tpm2SelfTest(IN TPMI_YES_NO FullTest)
This command causes the TPM to perform a test of its capabilities.
GetDigestListSize
UINT32 GetDigestListSize(IN TPML_DIGEST_VALUES *DigestList)
Get TPML_DIGEST_VALUES data size.
Tpm2GetCapabilityAlgorithmSet
EFI_STATUS Tpm2GetCapabilityAlgorithmSet(OUT UINT32 *AlgorithmSet)
This command returns the information of TPM AlgorithmSet.
Tpm2SequenceUpdate
EFI_STATUS Tpm2SequenceUpdate(IN TPMI_DH_OBJECT SequenceHandle, IN TPM2B_MAX_BUFFER *Buffer)
This command is used to add data to a hash or HMAC sequence.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TpmInitialized.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Macros
TpmInitialized.h File Reference

Tag GUID that must be installed by the TPM PEIM after the TPM hardware is initialized. More...

Go to the source code of this file.

Macros

#define | PEI_TPM_INITIALIZED_PPI_GUID
Global ID for the PEI_TPM_INITIALIZED_PPI which always uses a NULL interface.
#define | PEI_TPM_INITIALIZATION_DONE_PPI_GUID
Global ID for the PEI_TPM_INITIALIZATION_DONE_PPI which always uses a NULL interface.

Detailed Description

Tag GUID that must be installed by the TPM PEIM after the TPM hardware is initialized.

PEIMs that must execute after TPM hardware initialization may use this GUID in their dependency expressions.

Copyright
INTEL CONFIDENTIAL Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file TpmInitialized.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TpmInitialized.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
TpmInitialized.h
Go to the documentation of this file.
1 /** @file
2 Tag GUID that must be installed by the TPM PEIM after the TPM hardware is
3 initialized. PEIMs that must execute after TPM hardware initialization
4 may use this GUID in their dependency expressions.
5
6 @copyright
7 INTEL CONFIDENTIAL
8 Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php
13
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16
17 **/
18
19 #ifndef _PEI_TPM_INITIALIZED_PPI_H_
20 #define _PEI_TPM_INITIALIZED_PPI_H_
21
22 ///
23 /// Global ID for the PEI_TPM_INITIALIZED_PPI which always uses a NULL interface.
24 ///
25 #define PEI_TPM_INITIALIZED_PPI_GUID \
26 { \
27 0xe9db0d58, 0xd48d, 0x47f6, 0x9c, 0x6e, 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41 \
28 }
29
30 extern EFI_GUID gPeiTpmInitializedPpiGuid;
31
32 ///
33 /// Global ID for the PEI_TPM_INITIALIZATION_DONE_PPI which always uses a NULL interface.
34 ///
35 #define PEI_TPM_INITIALIZATION_DONE_PPI_GUID \
36 { \
37 0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc \
38 }
39
40 extern EFI_GUID gPeiTpmInitializationDonePpiGuid;
41
42 #endif
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
Classes | Enumerations
TraceHubConfig.h File Reference

Configurations for TraceHub. More...

#include <ConfigBlock.h>
Include dependency graph for TraceHubConfig.h:

Go to the source code of this file.

Classes

struct | TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings. More...
struct | CPU_TRACE_HUB_PREMEM_CONFIG
CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Initial version. More...
struct | PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Initial version. More...

Enumerations

enum | TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
enum | TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.

Detailed Description

Configurations for TraceHub.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TraceHubConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHubConfig.h
Go to the documentation of this file.
1 /** @file
2 Configurations for TraceHub
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TRACE_HUB_CONFIG_H_
36 #define _TRACE_HUB_CONFIG_H_
37
38 #include <ConfigBlock.h>
39
40 #define CPU_TRACE_HUB_PREMEM_CONFIG_REVISION 1
41 #define PCH_TRACE_HUB_PREMEM_CONFIG_REVISION 1
42
43 extern EFI_GUID gPchTraceHubPreMemConfigGuid;
44 extern EFI_GUID gCpuTraceHubPreMemConfigGuid;
45
46 typedef enum {
47 CpuTraceHub,
48 PchTraceHub
49 } TRACE_HUB_DEVICE;
50 ///
51 /// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation
52 ///
53 typedef enum {
54 TraceHubModeDisabled = 0,
55 TraceHubModeTargetDebugger = 1,
56 TraceHubModeHostDebugger = 2,
57 TraceHubModeMax
58 } TRACE_HUB_ENABLE_MODE;
59
60 ///
61 /// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size
62 ///
63 typedef enum {
64 TraceBufferNone,
65 TraceBuffer1M,
66 TraceBuffer8M,
67 TraceBuffer64M,
68 TraceBuffer128M,
69 TraceBuffer256M,
70 TraceBuffer512M,
71 TraceBufferMax
72 } TRACE_BUFFER_SIZE;
73
74 #pragma pack (push,1)
75 ///
76 /// TRACE_HUB_CONFIG block describes TraceHub settings
77 ///
78 typedef struct {
79 /**
80 Trace hub mode. Default is disabled.
81 Target Debugger mode refers to debug tool running on target device itself and it works as a conventional PCI device;
82 Host Debugger mode refers to SUT debugged via probe on host, configured as ACPI device with PCI configuration sapce hidden.
83 <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
84 Refer to TRACE_HUB_ENABLE_MODE
85 **/
86 UINT8 EnableMode;
87 /**
88 Trace hub memory buffer region size policy.
89 The avaliable memory size options are: 0:0MB (none), 1:1MB, <b>2:8MB</b>, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
90 Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB.
91 Refer to TRACE_BUFFER_SIZE
92 **/
93 UINT8 MemReg0Size;
94 UINT8 MemReg1Size;
95 /**
96 AET Trace. AET base address can be set to FW Base either from CPU trace hub or PCH one.
97 AetEnabled must be exclusive, if AetEnabled = 1 for CPU trace hub, must AetEnabled = 0 for PCH one.
98 The default is set to PCH.
99 CPU Trace Hub
100 <b>0 = Disabled</b>; 1 = Enabled
101 PCH Trace Hub
102 0 = Disabled; <b>1 = Enabled</b>
103 **/
104 UINT8 AetEnabled;
105 } TRACE_HUB_CONFIG;
106
107 /**
108 CPU Trace Hub PreMem Configuration
109 Contains Trace Hub settings for CPU side tracing
110 <b>Revision 1</b>: - Initial version.
111 **/
112 typedef struct {
113 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
114 TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
115 } CPU_TRACE_HUB_PREMEM_CONFIG;
116
117 /**
118 PCH Trace Hub PreMem Configuration
119 Contains Trace Hub settings for PCH side tracing
120 <b>Revision 1</b>: - Initial version.
121 **/
122 typedef struct {
123 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
124 TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config
125 } PCH_TRACE_HUB_PREMEM_CONFIG;
126
127 #pragma pack (pop)
128
129 #endif
TRACE_HUB_CONFIG::AetEnabled
UINT8 AetEnabled
AET Trace.
Definition: TraceHubConfig.h:104
CPU_TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:113
ConfigBlock.h
Header file for Config Block Lib implementation.
TRACE_HUB_CONFIG
TRACE_HUB_CONFIG block describes TraceHub settings.
Definition: TraceHubConfig.h:78
TRACE_BUFFER_SIZE
TRACE_BUFFER_SIZE
The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size.
Definition: TraceHubConfig.h:63
TRACE_HUB_CONFIG::EnableMode
UINT8 EnableMode
Trace hub mode.
Definition: TraceHubConfig.h:86
PCH_TRACE_HUB_PREMEM_CONFIG
PCH Trace Hub PreMem Configuration Contains Trace Hub settings for PCH side tracing Revision 1: - Ini...
Definition: TraceHubConfig.h:122
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TRACE_HUB_ENABLE_MODE
TRACE_HUB_ENABLE_MODE
The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation.
Definition: TraceHubConfig.h:53
CPU_TRACE_HUB_PREMEM_CONFIG::TraceHub
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.
Definition: TraceHubConfig.h:114
PCH_TRACE_HUB_PREMEM_CONFIG::TraceHub
TRACE_HUB_CONFIG TraceHub
Trace Hub Config.
Definition: TraceHubConfig.h:124
TRACE_HUB_CONFIG::MemReg0Size
UINT8 MemReg0Size
Trace hub memory buffer region size policy.
Definition: TraceHubConfig.h:93
CPU_TRACE_HUB_PREMEM_CONFIG
CPU Trace Hub PreMem Configuration Contains Trace Hub settings for CPU side tracing Revision 1: - Ini...
Definition: TraceHubConfig.h:112
PCH_TRACE_HUB_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TraceHubConfig.h:123
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubDataHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
TraceHubDataHob.h File Reference

The GUID definition for TraceHub Data Hob. More...

#include <Base.h>
Include dependency graph for TraceHubDataHob.h:

Go to the source code of this file.

Classes

struct TRACEHUB_DATA_HOB
Trace Hub Data Hob. More...

Detailed Description

The GUID definition for TraceHub Data Hob.

Copyright
INTEL CONFIDENTIAL Copyright 2019 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TraceHubDataHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubDataHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
TraceHubDataHob.h
Go to the documentation of this file.
1 /** @file
2 The GUID definition for TraceHub Data Hob
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TRACEHUB_DATA_HOB_H_
36 #define _TRACEHUB_DATA_HOB_H_
37
38 #include <Base.h>
39
40 extern EFI_GUID gTraceHubDataHobGuid;
41
42 #pragma pack (push,1)
43
44 /**
45 Trace Hub Data Hob.
46 **/
47 typedef struct {
48 EFI_HOB_GUID_TYPE EfiHobGuidType;
49 UINT64 TraceHubMemBase;
50 UINT64 TraceHubMemSize;
51 UINT8 TraceHubMode[4];
52 } TRACEHUB_DATA_HOB;
53
54 #pragma pack (pop)
55 #endif
TRACEHUB_DATA_HOB
Trace Hub Data Hob.
Definition: TraceHubDataHob.h:47
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubDebugLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TraceHubDebugLib.h File Reference

Definitions for the TraceHub Debug Lib. More...

Go to the source code of this file.

Functions

RETURN_STATUS | TraceHubDebugWrite (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data from buffer and Severity to TraceHub. More...
VOID | TraceHubWriteCataLog64_0 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id)
Write catalog64 message SVEN event with 0 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_1 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1)
Write catalog64 message SVEN event with 1 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_2 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2)
Write catalog64 message SVEN event with 2 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_3 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3)
Write catalog64 message SVEN event with 3 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_4 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4)
Write catalog64 message SVEN event with 4 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_5 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4, IN UINT32 Param5)
Write catalog64 message SVEN event with 5 parameters to TraceHub. More...
VOID | TraceHubWriteCataLog64_6 (IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4, IN UINT32 Param5, IN UINT32 Param6)
Write catalog64 message SVEN event with 6 parameters to TraceHub. More...

Detailed Description

Definitions for the TraceHub Debug Lib.

Note
The APIs in this file are designed to be backward compatible with previous versions. Any change in behavior of these APIs will result in newer version of the API

INTEL CONFIDENTIAL Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file TraceHubDebugLib.h.

Function Documentation

◆ TraceHubDebugWrite()

RETURN_STATUS TraceHubDebugWrite | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT8 * | Buffer,
 |  | IN UINTN | NumberOfBytes
 | ) |  |

Write data from buffer and Severity to TraceHub.

Writes NumberOfBytes data bytes from Buffer and Severity to TraceHub. If Buffer is NULL and NumberOfBytes is larger than zero, then ASSERT(). If NumberOfBytes is zero, no buffer is written.

Parameters
SeverityType | Severity type of the written data buffer.
Buffer | Pointer to the data buffer to be written.
NumberOfBytes | Number of bytes to written to TraceHub device.
Return values
RETURN_SUCCESS | The number of bytes written to TraceHub.
Other | Fail to write the buffer to TraceHub.

◆ TraceHubWriteCataLog64_0()

VOID TraceHubWriteCataLog64_0 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id
 | ) |  |

Write catalog64 message SVEN event with 0 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID

◆ TraceHubWriteCataLog64_1()

VOID TraceHubWriteCataLog64_1 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1
 | ) |  |

Write catalog64 message SVEN event with 1 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.

◆ TraceHubWriteCataLog64_2()

VOID TraceHubWriteCataLog64_2 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1,
 |  | IN UINT32 | Param2
 | ) |  |

Write catalog64 message SVEN event with 2 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.
Param2 | Parameter 2 passed to catid message event.

◆ TraceHubWriteCataLog64_3()

VOID TraceHubWriteCataLog64_3 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1,
 |  | IN UINT32 | Param2,
 |  | IN UINT32 | Param3
 | ) |  |

Write catalog64 message SVEN event with 3 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.
Param2 | Parameter 2 passed to catid message event.
Param3 | Parameter 3 passed to catid message event.

◆ TraceHubWriteCataLog64_4()

VOID TraceHubWriteCataLog64_4 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1,
 |  | IN UINT32 | Param2,
 |  | IN UINT32 | Param3,
 |  | IN UINT32 | Param4
 | ) |  |

Write catalog64 message SVEN event with 4 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.
Param2 | Parameter 2 passed to catid message event.
Param3 | Parameter 3 passed to catid message event.
Param4 | Parameter 4 passed to catid message event.

◆ TraceHubWriteCataLog64_5()

VOID TraceHubWriteCataLog64_5 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1,
 |  | IN UINT32 | Param2,
 |  | IN UINT32 | Param3,
 |  | IN UINT32 | Param4,
 |  | IN UINT32 | Param5
 | ) |  |

Write catalog64 message SVEN event with 5 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.
Param2 | Parameter 2 passed to catid message event.
Param3 | Parameter 3 passed to catid message event.
Param4 | Parameter 4 passed to catid message event.
Param5 | Parameter 5 passed to catid message event.

◆ TraceHubWriteCataLog64_6()

VOID TraceHubWriteCataLog64_6 | ( | IN TRACE_HUB_SEVERITY_TYPE | SeverityType,
 |  | IN UINT64 | Id,
 |  | IN UINT32 | Param1,
 |  | IN UINT32 | Param2,
 |  | IN UINT32 | Param3,
 |  | IN UINT32 | Param4,
 |  | IN UINT32 | Param5,
 |  | IN UINT32 | Param6
 | ) |  |

Write catalog64 message SVEN event with 6 parameters to TraceHub.

Parameters
SeverityType | Severity type of the catid message event.
Id | Catalog ID
Param1 | Parameter 1 passed to catid message event.
Param2 | Parameter 2 passed to catid message event.
Param3 | Parameter 3 passed to catid message event.
Param4 | Parameter 4 passed to catid message event.
Param5 | Parameter 5 passed to catid message event.
Param6 | Parameter 6 passed to catid message event.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubDebugLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TraceHubDebugLib.h
Go to the documentation of this file.
1 //
2 // This file contains 'Framework Code' and is licensed as such
3 // under the terms of your license agreement with Intel or your
4 // vendor. This file may not be modified, except as allowed by
5 // additional terms of your license agreement.
6 //
7 /** @file
8 Definitions for the TraceHub Debug Lib.
9
10 @note The APIs in this file are designed to be backward compatible with previous versions.
11 Any change in behavior of these APIs will result in newer version of the API
12
13 INTEL CONFIDENTIAL
14 Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
15 This software and associated documentation (if any) is furnished
16 under a license and may only be used or copied in accordance
17 with the terms of the license. Except as permitted by such
18 license, no part of this software or documentation may be
19 reproduced, stored in a retrieval system, or transmitted in any
20 form or by any means without the express written consent of
21 Intel Corporation.
22
23 **/
24
25 #ifndef __TRACE_HUB_DEBUG_LIB_H__
26 #define __TRACE_HUB_DEBUG_LIB_H__
27
28 /*
29 The maximum size of an EFI_DEBUG_INFO structure.
30 */
31 #define EFI_STATUS_CODE_DATA_MAX_SIZE 200
32
33 typedef enum {
34 SeverityNone = 0,
35 SeverityFatal = 1,
36 SeverityError = 2,
37 SeverityWarning = 3,
38 SeverityNormal = 4,
39 SeverityUser1 = 5,
40 SeverityUser2 = 6,
41 SeverityUser3 = 7,
42 SeverityMax
43 } TRACE_HUB_SEVERITY_TYPE;
44
45 /**
46 Write data from buffer and Severity to TraceHub.
47
48 Writes NumberOfBytes data bytes from Buffer and Severity to TraceHub.
49 If Buffer is NULL and NumberOfBytes is larger than zero, then ASSERT().
50 If NumberOfBytes is zero, no buffer is written.
51
52 @param SeverityType Severity type of the written data buffer.
53 @param Buffer Pointer to the data buffer to be written.
54 @param NumberOfBytes Number of bytes to written to TraceHub device.
55
56 @retval RETURN_SUCCESS The number of bytes written to TraceHub.
57 @retval Other Fail to write the buffer to TraceHub.
58
59 **/
60 RETURN_STATUS
61 EFIAPI
62 TraceHubDebugWrite (
63 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
64 IN UINT8 *Buffer,
65 IN UINTN NumberOfBytes
66 );
67
68 /**
69 Write catalog64 message SVEN event with 0 parameters to TraceHub
70
71 @param SeverityType Severity type of the catid message event.
72 @param Id Catalog ID
73
74 **/
75 VOID
76 EFIAPI
77 TraceHubWriteCataLog64_0 (
78 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
79 IN UINT64 Id
80 );
81
82 /**
83 Write catalog64 message SVEN event with 1 parameters to TraceHub
84
85 @param SeverityType Severity type of the catid message event.
86 @param Id Catalog ID
87 @param Param1 Parameter 1 passed to catid message event.
88
89 **/
90 VOID
91 EFIAPI
92 TraceHubWriteCataLog64_1 (
93 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
94 IN UINT64 Id,
95 IN UINT32 Param1
96 );
97
98 /**
99 Write catalog64 message SVEN event with 2 parameters to TraceHub
100
101 @param SeverityType Severity type of the catid message event.
102 @param Id Catalog ID
103 @param Param1 Parameter 1 passed to catid message event.
104 @param Param2 Parameter 2 passed to catid message event.
105
106 **/
107 VOID
108 EFIAPI
109 TraceHubWriteCataLog64_2 (
110 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
111 IN UINT64 Id,
112 IN UINT32 Param1,
113 IN UINT32 Param2
114 );
115
116 /**
117 Write catalog64 message SVEN event with 3 parameters to TraceHub
118
119 @param SeverityType Severity type of the catid message event.
120 @param Id Catalog ID
121 @param Param1 Parameter 1 passed to catid message event.
122 @param Param2 Parameter 2 passed to catid message event.
123 @param Param3 Parameter 3 passed to catid message event.
124
125 **/
126 VOID
127 EFIAPI
128 TraceHubWriteCataLog64_3 (
129 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
130 IN UINT64 Id,
131 IN UINT32 Param1,
132 IN UINT32 Param2,
133 IN UINT32 Param3
134 );
135
136 /**
137 Write catalog64 message SVEN event with 4 parameters to TraceHub
138
139 @param SeverityType Severity type of the catid message event.
140 @param Id Catalog ID
141 @param Param1 Parameter 1 passed to catid message event.
142 @param Param2 Parameter 2 passed to catid message event.
143 @param Param3 Parameter 3 passed to catid message event.
144 @param Param4 Parameter 4 passed to catid message event.
145
146 **/
147 VOID
148 EFIAPI
149 TraceHubWriteCataLog64_4 (
150 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
151 IN UINT64 Id,
152 IN UINT32 Param1,
153 IN UINT32 Param2,
154 IN UINT32 Param3,
155 IN UINT32 Param4
156 );
157
158 /**
159 Write catalog64 message SVEN event with 5 parameters to TraceHub
160
161 @param SeverityType Severity type of the catid message event.
162 @param Id Catalog ID
163 @param Param1 Parameter 1 passed to catid message event.
164 @param Param2 Parameter 2 passed to catid message event.
165 @param Param3 Parameter 3 passed to catid message event.
166 @param Param4 Parameter 4 passed to catid message event.
167 @param Param5 Parameter 5 passed to catid message event.
168
169 **/
170 VOID
171 EFIAPI
172 TraceHubWriteCataLog64_5 (
173 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
174 IN UINT64 Id,
175 IN UINT32 Param1,
176 IN UINT32 Param2,
177 IN UINT32 Param3,
178 IN UINT32 Param4,
179 IN UINT32 Param5
180 );
181
182 /**
183 Write catalog64 message SVEN event with 6 parameters to TraceHub
184
185 @param SeverityType Severity type of the catid message event.
186 @param Id Catalog ID
187 @param Param1 Parameter 1 passed to catid message event.
188 @param Param2 Parameter 2 passed to catid message event.
189 @param Param3 Parameter 3 passed to catid message event.
190 @param Param4 Parameter 4 passed to catid message event.
191 @param Param5 Parameter 5 passed to catid message event.
192 @param Param6 Parameter 6 passed to catid message event.
193
194 **/
195 VOID
196 EFIAPI
197 TraceHubWriteCataLog64_6 (
198 IN TRACE_HUB_SEVERITY_TYPE SeverityType,
199 IN UINT64 Id,
200 IN UINT32 Param1,
201 IN UINT32 Param2,
202 IN UINT32 Param3,
203 IN UINT32 Param4,
204 IN UINT32 Param5,
205 IN UINT32 Param6
206 );
207
208 #endif // _TRACE_HUB_DEBUG_LIB_H_
TraceHubWriteCataLog64_2
VOID TraceHubWriteCataLog64_2(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2)
Write catalog64 message SVEN event with 2 parameters to TraceHub.
TraceHubWriteCataLog64_3
VOID TraceHubWriteCataLog64_3(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3)
Write catalog64 message SVEN event with 3 parameters to TraceHub.
TraceHubWriteCataLog64_6
VOID TraceHubWriteCataLog64_6(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4, IN UINT32 Param5, IN UINT32 Param6)
Write catalog64 message SVEN event with 6 parameters to TraceHub.
TraceHubDebugWrite
RETURN_STATUS TraceHubDebugWrite(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT8 *Buffer, IN UINTN NumberOfBytes)
Write data from buffer and Severity to TraceHub.
TraceHubWriteCataLog64_5
VOID TraceHubWriteCataLog64_5(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4, IN UINT32 Param5)
Write catalog64 message SVEN event with 5 parameters to TraceHub.
TraceHubWriteCataLog64_4
VOID TraceHubWriteCataLog64_4(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1, IN UINT32 Param2, IN UINT32 Param3, IN UINT32 Param4)
Write catalog64 message SVEN event with 4 parameters to TraceHub.
TraceHubWriteCataLog64_1
VOID TraceHubWriteCataLog64_1(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id, IN UINT32 Param1)
Write catalog64 message SVEN event with 1 parameters to TraceHub.
TraceHubWriteCataLog64_0
VOID TraceHubWriteCataLog64_0(IN TRACE_HUB_SEVERITY_TYPE SeverityType, IN UINT64 Id)
Write catalog64 message SVEN event with 0 parameters to TraceHub.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubHookLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TraceHubHookLib.h File Reference

Definitions for the TraceHubHook Lib. More...

Go to the source code of this file.

Functions

RETURN_STATUS | TraceHubMmioTraceAddress (IN UINT32 Master, IN UINT32 Channel, OUT UINT32 *TraceAddress)
Return TraceHub Trace Address. More...
RETURN_STATUS | TraceHubScratchPad2RegValue (OUT UINT8 *ScratchPad2RegValue)
Return Scratch Pad2 Register Value. More...

Detailed Description

Definitions for the TraceHubHook Lib.

INTEL CONFIDENTIAL Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
This software and associated documentation (if any) is furnished under a license and may only be used or copied in accordance with the terms of the license. Except as permitted by such license, no part of this software or documentation may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Definition in file TraceHubHookLib.h.

Function Documentation

◆ TraceHubMmioTraceAddress()

RETURN_STATUS TraceHubMmioTraceAddress | ( | IN UINT32 | Master,
 |  | IN UINT32 | Channel,
 |  | OUT UINT32 * | TraceAddress
 | ) |  |

Return TraceHub Trace Address.

Parameters
[in] | Thread | Host is being used.
[in] | Channel | Channel is being used.
[out] | TraceAddress | TraceHub Address for the Host/Channel is being used.
Return values
RETURN_SUCCESS | Retrieve correct Address.
RETURN_UNSUPPORTED | Not implemented.
Other | Fail to Retrieve correct TraceHub Address.

◆ TraceHubScratchPad2RegValue()

RETURN_STATUS TraceHubScratchPad2RegValue ( OUT UINT8 * ScratchPad2RegValue )

Return Scratch Pad2 Register Value.

Parameters
[out] ScratchPad2RegValue Scratch Pad2 Register Value.
Return values
RETURN_SUCCESS | Retrieve Scratch Pad2 Register Value.
RETURN_UNSUPPORTED | Not implemented.
Other | Fail to Retrieve Scratch Pad2 Register Value.
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHubHookLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TraceHubHookLib.h
Go to the documentation of this file.
1 //
2 // This file contains 'Framework Code' and is licensed as such
3 // under the terms of your license agreement with Intel or your
4 // vendor. This file may not be modified, except as allowed by
5 // additional terms of your license agreement.
6 //
7 /** @file
8 Definitions for the TraceHubHook Lib.
9
10 INTEL CONFIDENTIAL
11 Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
12 This software and associated documentation (if any) is furnished
13 under a license and may only be used or copied in accordance
14 with the terms of the license. Except as permitted by such
15 license, no part of this software or documentation may be
16 reproduced, stored in a retrieval system, or transmitted in any
17 form or by any means without the express written consent of
18 Intel Corporation.
19
20 **/
21
22 #ifndef __TRACE_HUB_HOOK_LIB_H__
23 #define __TRACE_HUB_HOOK_LIB_H__
24
25 /**
26 Return TraceHub Trace Address.
27
28 @param [in] Thread Host is being used.
29 @param [in] Channel Channel is being used.
30 @param [out] TraceAddress TraceHub Address for the Host/Channel
31 is being used.
32
33 @retval RETURN_SUCCESS Retrieve correct Address.
34 @retval RETURN_UNSUPPORTED Not implemented.
35 @retval Other Fail to Retrieve correct TraceHub Address.
36
37 **/
38 RETURN_STATUS
39 EFIAPI
40 TraceHubMmioTraceAddress (
41 IN UINT32 Master,
42 IN UINT32 Channel,
43 OUT UINT32 *TraceAddress
44 );
45
46 /**
47 Return Scratch Pad2 Register Value.
48
49 @param [out] ScratchPad2RegValue Scratch Pad2 Register Value.
50
51 @retval RETURN_SUCCESS Retrieve Scratch Pad2 Register Value.
52 @retval RETURN_UNSUPPORTED Not implemented.
53 @retval Other Fail to Retrieve Scratch Pad2 Register Value.
54
55 **/
56 RETURN_STATUS
57 EFIAPI
58 TraceHubScratchPad2RegValue (
59 OUT UINT8 *ScratchPad2RegValue
60 );
61
62 #endif // _TRACE_HUB_LIB_H_
TraceHubMmioTraceAddress
RETURN_STATUS TraceHubMmioTraceAddress(IN UINT32 Master, IN UINT32 Channel, OUT UINT32 *TraceAddress)
Return TraceHub Trace Address.
TraceHubScratchPad2RegValue
RETURN_STATUS TraceHubScratchPad2RegValue(OUT UINT8 *ScratchPad2RegValue)
Return Scratch Pad2 Register Value.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TsnConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Classes
TsnConfig.h File Reference

TSN Config policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct TSN_CONFIG
The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN) More...

Detailed Description

TSN Config policy.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TsnConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TsnConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
TsnConfig.h
Go to the documentation of this file.
1 /** @file
2 TSN Config policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _TSN_CONFIG_H_
37 #define _TSN_CONFIG_H_
38
39 #define TSN_CONFIG_REVISION 2
40 extern EFI_GUID gTsnConfigGuid;
41
42 #pragma pack (push,1)
43 /**
44 The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
45
46 <b>Revision 1</b>:
47 - Initial version.
48 <b>Revision 2</b>:
49 - Added MultiVcEnable
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 /**
54 Determines if enable PCH internal TSN, 0: Disable; <b>1: Enable</b>.
55 **/
56 UINT8 Enable;
57 UINT8 TsnLinkSpeed; ///< Refer to "TSN_LINK_SPEED_OPTIONS". Default is <b> TSN_LINK_SPEED_2_5G_34MHZ</b>
58 UINT8 MultiVcEnable; ///< Enable Multi-Vc via Tc to DMA mapping. Deafult is </b> 0:disable</b>
59 UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4.
60 UINT32 TsnMacAddressHigh; ///< MAC Address High bits. Only two lower bytes are used.
61 UINT32 TsnMacAddressLow; ///< MAC Address Low bits
62 } TSN_CONFIG;
63
64 #pragma pack (pop)
65
66 typedef enum {
67 TSN_LINK_SPEED_2_5G_24MHZ = 0,
68 TSN_LINK_SPEED_1G_24MHZ,
69 TSN_LINK_SPEED_2_5G_34MHZ,
70 TSN_LINK_SPEED_1G_34MHZ
71 } TSN_LINK_SPEED_OPTIONS;
72
73 #endif
TSN_CONFIG::TsnMacAddressLow
UINT32 TsnMacAddressLow
MAC Address Low bits.
Definition: TsnConfig.h:61
TSN_CONFIG::TsnMacAddressHigh
UINT32 TsnMacAddressHigh
MAC Address High bits. Only two lower bytes are used.
Definition: TsnConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
TSN_CONFIG::Rsvd0
UINT8 Rsvd0
Reserved bytes, align to multiple 4.
Definition: TsnConfig.h:59
TSN_CONFIG::TsnLinkSpeed
UINT8 TsnLinkSpeed
Refer to "TSN_LINK_SPEED_OPTIONS". Default is TSN_LINK_SPEED_2_5G_34MHZ
Definition: TsnConfig.h:57
TSN_CONFIG::MultiVcEnable
UINT8 MultiVcEnable
Enable Multi-Vc via Tc to DMA mapping. Deafult is 0:disable
Definition: TsnConfig.h:58
TSN_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: TsnConfig.h:52
TSN_CONFIG::Enable
UINT8 Enable
Determines if enable PCH internal TSN, 0: Disable; 1: Enable.
Definition: TsnConfig.h:56
TSN_CONFIG
The TSN_CONFIG block describes policies related to Time Sensitive Networking(TSN)
Definition: TsnConfig.h:51
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TsnLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
TsnLib.h File Reference

This file provides Tsn public library. More...

Go to the source code of this file.

Functions

BOOLEAN | IsTsnPresent (VOID)
Check whether TSN controller is enabled in the platform. More...
UINT8 | TsnDevNumber (VOID)
Get Tsn PCI device number. More...
UINT8 | TsnFuncNumber (VOID)
Get Tsn PCI function number. More...

Detailed Description

This file provides Tsn public library.

Copyright
INTEL CONFIDENTIAL Copyright 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TsnLib.h.

Function Documentation

◆ IsTsnPresent()

BOOLEAN IsTsnPresent ( VOID )

Check whether TSN controller is enabled in the platform.

Return values
TRUE | GbE is enabled
FALSE | GbE is disabled

◆ TsnDevNumber()

UINT8 TsnDevNumber ( VOID )

Get Tsn PCI device number.

Return values
PCI dev number

◆ TsnFuncNumber()

UINT8 TsnFuncNumber ( VOID )

Get Tsn PCI function number.

Return values
PCI fun number
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TsnLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
TsnLib.h
Go to the documentation of this file.
1 /** @file
2 This file provides Tsn public library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TSN_LIB_H_
36 #define _TSN_LIB_H_
37
38 /**
39 Check whether TSN controller is enabled in the platform.
40
41 @retval TRUE GbE is enabled
42 @retval FALSE GbE is disabled
43 **/
44 BOOLEAN
45 IsTsnPresent (
46 VOID
47 );
48
49 /**
50 Get Tsn PCI device number
51
52 @retval PCI dev number
53 **/
54 UINT8
55 TsnDevNumber (
56 VOID
57 );
58
59 /**
60 Get Tsn PCI function number
61
62 @retval PCI fun number
63 **/
64 UINT8
65 TsnFuncNumber (
66 VOID
67 );
68
69 #endif // _TSN_LIB_H_
TsnFuncNumber
UINT8 TsnFuncNumber(VOID)
Get Tsn PCI function number.
TsnDevNumber
UINT8 TsnDevNumber(VOID)
Get Tsn PCI device number.
IsTsnPresent
BOOLEAN IsTsnPresent(VOID)
Check whether TSN controller is enabled in the platform.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Txt.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Classes | Macros | Typedefs
Txt.h File Reference

This file contains definitions required to use the TXT BIOS Authenticated Code Module Library. More...

Go to the source code of this file.

Classes

struct | _HEAP_EXT_DATA_ELEMENT
TXT HEAP Memory: Extended data elements. More...
struct | _HEAP_BIOS_SPEC_VER_ELEMENT
TXT HEAP Memory: BIOS spec version element. More...
struct | _HEAP_BIOSACM_ELEMENT
TXT HEAP Memory: BIOS ACM element. More...
struct | _BIOS_OS_DATA_REGION
TXT HEAP Memory: BIOS OS Data region definitions. More...

Macros

#define | TPM_TIME_OUT 750
TPM access polling timeout (~750ms)
#define | TXT_BIOS_SPEC_VER_MAJOR 2
Major number of TXT BIOS spec version.
#define | TXT_BIOS_SPEC_VER_MINOR 1
Minor number of TXT BIOS spec version.
#define | TXT_BIOS_SPEC_VER_REVISION 0
Revision number of TXT BIOS spec version.
#define | HEAP_EXTDATA_TYPE_END 0
Element type identifier: terminator.
#define | HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1
Element type identifier: BIOS spec version.
#define | HEAP_EXTDATA_TYPE_BIOSACM 2
Element type identifier: BIOS ACM version.
#define | BIOS_OS_DATAREGION_VERSION 6
Element type identifier: BIOS OS data region.
#define | TXT_LAUNCH_SCLEAN 0x00
BIOS ACM function #: SCLEAN.
#define | TXT_RESET_EST_BIT 0x01
BIOS ACM function #: Reset establishment bit.
#define | TXT_RESET_AUX 0x02
BIOS ACM function #: Reset AUX index.
#define | TXT_LAUNCH_SCHECK 0x04
BIOS ACM function #: SCHECK.
#define | TXT_LAUNCH_CLEAR_SECRETS 0x05
BIOS ACM function #: CLEAR_SECRETS.
#define | TXT_LAUNCH_LOCK_CONFIG 0x06
BIOS ACM function #: LOCK_CONFIG.
#define | TXT_LAUNCH_ACHECK 0x07
BIOS ACM function #: ACHECK.
#define | TPM_STATUS_REG_ADDRESS 0xFED40000
Address of TPM status register.
#define | TXT_PUBLIC_BASE 0xFED30000
Base address of TXT public space.
#define | TXT_PRIVATE_BASE 0xFED20000
Base address of TXT private space.
#define | TXT_CONFIG_SPACE_LENGTH 0x60000
Size TXT address space.
#define | TXT_ERROR_STATUS_REG_OFF 0x8
Offset of TXT error status register (ESTS)
#define | TXT_CRASHCODE_REG_OFF 0x30
Offset of TXT crash code register (CRASH)
#define | TXT_SPAD_REG_OFF 0xA0
Offset of TXT SPAD register (SPAD)
#define | TXT_SINIT_BASE_REG_OFF 0x270
Offset of SINIT base address register (SINIT_MEMORY_BASE)
#define | TXT_SINIT_SIZE_REG_OFF 0x278
Offset of SINIT size register (SINIT_MEMORY_SIZE)
#define | TXT_SINIT_SIZE_REG_OFF2 0x27C
Offset of SINIT size register (SINIT_MEMORY_SIZE)
#define | TXT_SVMM_JOIN_REG_OFF 0x290
Offset of SVMM join register (SVMM_JOIN)
#define | TXT_SVMM_JOIN_REG_OFF2 0x294
Offset of SVMM join register (SVMM_JOIN)
#define | TXT_HEAP_BASE_REG_OFF 0x300
Offset of TXT heap base address register (HEAP_BASE)
#define | TXT_HEAP_SIZE_REG_OFF 0x308
Offset of TXT heap size register (HEAP_SIZE)
#define | TXT_SCRATCHPAD 0x320
Offset of scratchpad register (LT_SCRATCHPAD)
#define | TXT_SCRATCHPAD2 0x324
Offset of scratchpad register (LT_SCRATCHPAD2)
#define | TXT_SCRATCHPAD3 0x328
Offset of scratchpad register (LT_SCRATCHPAD3)
#define | TXT_SCRATCHPAD4 0x32C
Offset of scratchpad register (LT_SCRATCHPAD4)
#define | TXT_DPR_SIZE_REG_OFF 0x330
Offset of DMA protected range register (DPR)
#define | TXT_PTT_FTIF_OFF 0x800
Offset of Interface Version Number register (VER_FTIF)
#define | TXT_PTT_PRESENT 0x70000
Bitfield indicates location of TPM. More...
#define | TXT_E2STS_REG_OFF 0x8F0
Offset of Extended Error Status register (E2STS)
#define | TXT_BLOCK_MEM_STS BIT2
1: MCH should block memory accesses
#define | TXT_SECRETS_STS BIT1
1: there are any potential secrets in memory
#define | TXT_SLP_ENTRY_ERROR_STS BIT0
1: there has been an improper attempt to go to sleeping state
#define | BIOACM_ADDR TXT_SINIT_SIZE_REG_OFF2
Offset of register containing BIOS ACM base address.
#define | APINIT_ADDR TXT_SVMM_JOIN_REG_OFF
Offset of register containing AP init base address.
#define | SEMAPHORE TXT_SVMM_JOIN_REG_OFF2
Offset of register containing semaphore address.

Typedefs

typedef struct _HEAP_EXT_DATA_ELEMENT | HEAP_EXT_DATA_ELEMENT
TXT HEAP Memory: Extended data elements. More...
typedef struct _HEAP_BIOS_SPEC_VER_ELEMENT | HEAP_BIOS_SPEC_VER_ELEMENT
TXT HEAP Memory: BIOS spec version element. More...
typedef struct _HEAP_BIOSACM_ELEMENT | HEAP_BIOSACM_ELEMENT
TXT HEAP Memory: BIOS ACM element. More...
typedef struct _BIOS_OS_DATA_REGION | BIOS_OS_DATA_REGION
TXT HEAP Memory: BIOS OS Data region definitions. More...

Detailed Description

This file contains definitions required to use the TXT BIOS Authenticated Code Module Library.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Txt.h.

Macro Definition Documentation

◆ TXT_PTT_PRESENT

#define TXT_PTT_PRESENT 0x70000

Bitfield indicates location of TPM.

111: fTPM is present and active

Definition at line 96 of file Txt.h.

Typedef Documentation

◆ BIOS_OS_DATA_REGION

typedef struct _BIOS_OS_DATA_REGION BIOS_OS_DATA_REGION

TXT HEAP Memory: BIOS OS Data region definitions.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide TXT HEAP BIOS OS Data region definitions

◆ HEAP_BIOS_SPEC_VER_ELEMENT

typedef struct _HEAP_BIOS_SPEC_VER_ELEMENT HEAP_BIOS_SPEC_VER_ELEMENT

TXT HEAP Memory: BIOS spec version element.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide TXT HEAP BIOS spec version element

◆ HEAP_BIOSACM_ELEMENT

typedef struct _HEAP_BIOSACM_ELEMENT HEAP_BIOSACM_ELEMENT

TXT HEAP Memory: BIOS ACM element.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide TXT HEAP BIOS ACM element

◆ HEAP_EXT_DATA_ELEMENT

typedef struct _HEAP_EXT_DATA_ELEMENT HEAP_EXT_DATA_ELEMENT

TXT HEAP Memory: Extended data elements.

As defined in Intel(R) TXT Software Development Guide / Measured Launch Environment Developer's Guide TXT HEAP Extended data elements

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Txt.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Txt.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required to use the TXT BIOS
3 Authenticated Code Module Library.
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 1999 - 2020 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _TXT_BIOS_ACM_LIB_H_
37 #define _TXT_BIOS_ACM_LIB_H_
38
39 #define TPM_TIME_OUT 750 ///< TPM access polling timeout (~750ms)
40
41 //
42 // TxT BIOS Spec version
43 //
44 #define TXT_BIOS_SPEC_VER_MAJOR 2 ///< Major number of TXT BIOS spec version
45 #define TXT_BIOS_SPEC_VER_MINOR 1 ///< Minor number of TXT BIOS spec version
46 #define TXT_BIOS_SPEC_VER_REVISION 0 ///< Revision number of TXT BIOS spec version
47
48 //
49 // TXT HEAP extended data type
50 //
51 #define HEAP_EXTDATA_TYPE_END 0 ///< Element type identifier: terminator
52 #define HEAP_EXTDATA_TYPE_BIOS_SPEC_VER 1 ///< Element type identifier: BIOS spec version
53 #define HEAP_EXTDATA_TYPE_BIOSACM 2 ///< Element type identifier: BIOS ACM version
54 #define BIOS_OS_DATAREGION_VERSION 6 ///< Element type identifier: BIOS OS data region
55
56 //
57 // The following are values that are placed in the esi register when
58 // calling the BIOS ACM. These constants are used as parameters to the
59 // TxtSetupandLaunchBiosAcm function.
60 //
61 #define TXT_LAUNCH_SCLEAN 0x00 ///< BIOS ACM function #: SCLEAN
62 #define TXT_RESET_EST_BIT 0x01 ///< BIOS ACM function #: Reset establishment bit
63 #define TXT_RESET_AUX 0x02 ///< BIOS ACM function #: Reset AUX index
64 #define TXT_LAUNCH_SCHECK 0x04 ///< BIOS ACM function #: SCHECK
65 #define TXT_LAUNCH_CLEAR_SECRETS 0x05 ///< BIOS ACM function #: CLEAR_SECRETS
66 #define TXT_LAUNCH_LOCK_CONFIG 0x06 ///< BIOS ACM function #: LOCK_CONFIG
67 #define TXT_LAUNCH_ACHECK 0x07 ///< BIOS ACM function #: ACHECK
68
69
70 #define TPM_STATUS_REG_ADDRESS 0xFED40000 ///< Address of TPM status register
71 #define TXT_PUBLIC_BASE 0xFED30000 ///< Base address of TXT public space
72 #define TXT_PRIVATE_BASE 0xFED20000 ///< Base address of TXT private space
73 #define TXT_CONFIG_SPACE_LENGTH 0x60000 ///< Size TXT address space
74
75 // TXT public address space
76 #define TXT_ERROR_STATUS_REG_OFF 0x8 ///< Offset of TXT error status register (ESTS)
77 #define TXT_CRASHCODE_REG_OFF 0x30 ///< Offset of TXT crash code register (CRASH)
78 #define TXT_SPAD_REG_OFF 0xA0 ///< Offset of TXT SPAD register (SPAD)
79 #define B_BPT_TXT_PASSED BIT30 /// <1 = TXT check passed into SACM; 0 = TXT check failed into SACM
80
81 #define TXT_SINIT_BASE_REG_OFF 0x270 ///< Offset of SINIT base address register (SINIT_MEMORY_BASE)
82 #define TXT_SINIT_SIZE_REG_OFF 0x278 ///< Offset of SINIT size register (SINIT_MEMORY_SIZE)
83 #define TXT_SINIT_SIZE_REG_OFF2 0x27C ///< Offset of SINIT size register (SINIT_MEMORY_SIZE)
84 #define TXT_SVMM_JOIN_REG_OFF 0x290 ///< Offset of SVMM join register (SVMM_JOIN)
85 #define TXT_SVMM_JOIN_REG_OFF2 0x294 ///< Offset of SVMM join register (SVMM_JOIN)
86 #define TXT_HEAP_BASE_REG_OFF 0x300 ///< Offset of TXT heap base address register (HEAP_BASE)
87 #define TXT_HEAP_SIZE_REG_OFF 0x308 ///< Offset of TXT heap size register (HEAP_SIZE)
88 #define TXT_SCRATCHPAD 0x320 ///< Offset of scratchpad register (LT_SCRATCHPAD)
89 #define TXT_SCRATCHPAD2 0x324 ///< Offset of scratchpad register (LT_SCRATCHPAD2)
90 #define TXT_SCRATCHPAD3 0x328 ///< Offset of scratchpad register (LT_SCRATCHPAD3)
91 #define TXT_SCRATCHPAD4 0x32C ///< Offset of scratchpad register (LT_SCRATCHPAD4)
92 #define TXT_DPR_SIZE_REG_OFF 0x330 ///< Offset of DMA protected range register (DPR)
93
94 #define TXT_PTT_FTIF_OFF 0x800 ///< Offset of Interface Version Number register (VER_FTIF)
95 #define TXT_PTT_PRESENT 0x70000 ///< Bitfield indicates location of TPM
96 ///< 111: fTPM is present and active
97
98 #define TXT_E2STS_REG_OFF 0x8F0 ///< Offset of Extended Error Status register (E2STS)
99 #define TXT_BLOCK_MEM_STS BIT2 ///< 1: MCH should block memory accesses
100 #define TXT_SECRETS_STS BIT1 ///< 1: there are any potential secrets in memory
101 #define TXT_SLP_ENTRY_ERROR_STS BIT0 ///< 1: there has been an improper attempt to go to sleeping state
102
103 #define BIOACM_ADDR TXT_SINIT_SIZE_REG_OFF2 ///< Offset of register containing BIOS ACM base address
104 #define APINIT_ADDR TXT_SVMM_JOIN_REG_OFF ///< Offset of register containing AP init base address
105 #define SEMAPHORE TXT_SVMM_JOIN_REG_OFF2 ///< Offset of register containing semaphore address
106
107
108 #pragma pack(push, 1)
109 ///
110 /// TXT HEAP Memory: Extended data elements
111 ///
112 /// As defined in Intel(R) TXT Software Development Guide /
113 /// Measured Launch Environment Developer's Guide
114 ///
115 typedef struct _HEAP_EXT_DATA_ELEMENT {
116 UINT32 Type; ///< Type of HEAP extended data element
117 UINT32 Size; ///< Size of HEAP extended data element
118 } HEAP_EXT_DATA_ELEMENT; ///< TXT HEAP Extended data elements
119
120 ///
121 /// TXT HEAP Memory: BIOS spec version element
122 ///
123 /// As defined in Intel(R) TXT Software Development Guide /
124 /// Measured Launch Environment Developer's Guide
125 ///
126 typedef struct _HEAP_BIOS_SPEC_VER_ELEMENT {
127 HEAP_EXT_DATA_ELEMENT Header; ///< Header of HEAP extended data. Header.Type = <b>1</b>.
128 UINT16 SpecVerMajor; ///< Major number of TXT BIOS spec version
129 UINT16 SpecVerMinor; ///< Minor number of TXT BIOS spec version
130 UINT16 SpecVerRevision; ///< Revision number of TXT BIOS spec version
131 } HEAP_BIOS_SPEC_VER_ELEMENT; ///< TXT HEAP BIOS spec version element
132
133 ///
134 /// TXT HEAP Memory: BIOS ACM element
135 ///
136 /// As defined in Intel(R) TXT Software Development Guide /
137 /// Measured Launch Environment Developer's Guide
138 ///
139 typedef struct _HEAP_BIOSACM_ELEMENT {
140 HEAP_EXT_DATA_ELEMENT Header; ///< Header of HEAP extended data. Header.Type = <b>2</b>.
141 UINT32 NumAcms; ///< Number of BIOS ACMs carried by BIOS
142 } HEAP_BIOSACM_ELEMENT; ///< TXT HEAP BIOS ACM element
143
144 ///
145 /// TXT HEAP Memory: BIOS OS Data region definitions
146 ///
147 /// As defined in Intel(R) TXT Software Development Guide /
148 /// Measured Launch Environment Developer's Guide
149 ///
150 typedef struct _BIOS_OS_DATA_REGION {
151 UINT32 Version; ///< Version number of the BIOS to OS data
152 /**
153 This field indicates the size of the SINIT AC module stored in system firmware.
154 A value of 0 indicates the system firmware is not providing a SINIT module for OS use.
155 **/
156 UINT32 BiosSinitSize;
157 /**
158 Physical base address of the Platform Default Launch Control Policy structure.
159 If the Platform Default Policy does not require additional data this field should
160 be set to 0x00 and will be ignored.
161 **/
162 EFI_PHYSICAL_ADDRESS LcpPdBase;
163 /**
164 Size of the Launch Control Policy Platform Default Policy Data.
165 If the Platform Default Policy does not require additional data this field should
166 be set to 0x00 and will be ignored.
167 **/
168 UINT64 LcpPdSize;
169 UINT32 NumOfLogicalProcessors; ///< The total number of logical processors in the system. The minimum value in this register must be at least <b>0x01</b>.
170 UINT64 Flags; ///< BIOS provided info for SINIT consumption
171 HEAP_EXT_DATA_ELEMENT ExtData; ///< Array/list of extended data element structures
172 } BIOS_OS_DATA_REGION; ///< TXT HEAP BIOS OS Data region definitions
173
174 #pragma pack(pop)
175 #endif
_BIOS_OS_DATA_REGION::Flags
UINT64 Flags
BIOS provided info for SINIT consumption.
Definition: Txt.h:170
_HEAP_BIOS_SPEC_VER_ELEMENT
TXT HEAP Memory: BIOS spec version element.
Definition: Txt.h:126
_HEAP_BIOS_SPEC_VER_ELEMENT::SpecVerRevision
UINT16 SpecVerRevision
Revision number of TXT BIOS spec version.
Definition: Txt.h:130
_HEAP_EXT_DATA_ELEMENT::Size
UINT32 Size
Size of HEAP extended data element.
Definition: Txt.h:117
_BIOS_OS_DATA_REGION
TXT HEAP Memory: BIOS OS Data region definitions.
Definition: Txt.h:150
_HEAP_BIOSACM_ELEMENT::NumAcms
UINT32 NumAcms
Number of BIOS ACMs carried by BIOS.
Definition: Txt.h:141
_BIOS_OS_DATA_REGION::NumOfLogicalProcessors
UINT32 NumOfLogicalProcessors
The total number of logical processors in the system. The minimum value in this register must be at l...
Definition: Txt.h:169
_HEAP_BIOSACM_ELEMENT
TXT HEAP Memory: BIOS ACM element.
Definition: Txt.h:139
_HEAP_EXT_DATA_ELEMENT::Type
UINT32 Type
Type of HEAP extended data element.
Definition: Txt.h:116
_BIOS_OS_DATA_REGION::BiosSinitSize
UINT32 BiosSinitSize
This field indicates the size of the SINIT AC module stored in system firmware.
Definition: Txt.h:156
_HEAP_BIOS_SPEC_VER_ELEMENT::Header
HEAP_EXT_DATA_ELEMENT Header
Header of HEAP extended data. Header.Type = 1.
Definition: Txt.h:127
_HEAP_BIOS_SPEC_VER_ELEMENT::SpecVerMajor
UINT16 SpecVerMajor
Major number of TXT BIOS spec version.
Definition: Txt.h:128
_HEAP_EXT_DATA_ELEMENT
TXT HEAP Memory: Extended data elements.
Definition: Txt.h:115
_HEAP_BIOSACM_ELEMENT::Header
HEAP_EXT_DATA_ELEMENT Header
Header of HEAP extended data. Header.Type = 2.
Definition: Txt.h:140
_HEAP_BIOS_SPEC_VER_ELEMENT::SpecVerMinor
UINT16 SpecVerMinor
Minor number of TXT BIOS spec version.
Definition: Txt.h:129
HEAP_BIOSACM_ELEMENT
struct _HEAP_BIOSACM_ELEMENT HEAP_BIOSACM_ELEMENT
TXT HEAP Memory: BIOS ACM element.
HEAP_EXT_DATA_ELEMENT
struct _HEAP_EXT_DATA_ELEMENT HEAP_EXT_DATA_ELEMENT
TXT HEAP Memory: Extended data elements.
BIOS_OS_DATA_REGION
struct _BIOS_OS_DATA_REGION BIOS_OS_DATA_REGION
TXT HEAP Memory: BIOS OS Data region definitions.
_BIOS_OS_DATA_REGION::ExtData
HEAP_EXT_DATA_ELEMENT ExtData
Array/list of extended data element structures.
Definition: Txt.h:171
_BIOS_OS_DATA_REGION::LcpPdSize
UINT64 LcpPdSize
Size of the Launch Control Policy Platform Default Policy Data.
Definition: Txt.h:168
HEAP_BIOS_SPEC_VER_ELEMENT
struct _HEAP_BIOS_SPEC_VER_ELEMENT HEAP_BIOS_SPEC_VER_ELEMENT
TXT HEAP Memory: BIOS spec version element.
_BIOS_OS_DATA_REGION::Version
UINT32 Version
Version number of the BIOS to OS data.
Definition: Txt.h:151
_BIOS_OS_DATA_REGION::LcpPdBase
EFI_PHYSICAL_ADDRESS LcpPdBase
Physical base address of the Platform Default Launch Control Policy structure.
Definition: Txt.h:162
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TxtInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Classes | Macros | Typedefs
TxtInfoHob.h File Reference

This file contains definitions required for creation of TXT Info HOB. More...

Go to the source code of this file.

Classes

struct | _TXT_INFO_DATA
TXT Info data. More...
struct | _TXT_INFO_HOB
HOB to save TXT Info data. More...

Macros

#define | FLAGS0 0x1
BIT0: FLAGS0 for compatible definition.
#define | TXT_CPU_RESET_REQUIRED 0x2
BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
#define | TPM_INIT_FAILED 0x4
BIT2: TPM_INIT_FAILED for indicate TPM initiate status. More...

Typedefs

typedef struct _TXT_INFO_DATA | TXT_INFO_DATA
TXT Info data. More...
typedef struct _TXT_INFO_HOB | TXT_INFO_HOB
HOB to save TXT Info data. More...

Detailed Description

This file contains definitions required for creation of TXT Info HOB.

Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TxtInfoHob.h.

Macro Definition Documentation

◆ TPM_INIT_FAILED

#define TPM_INIT_FAILED 0x4

BIT2: TPM_INIT_FAILED for indicate TPM initiate status.

If the bit set, ResetEstablishmentBit is skipped in Dxe driver.

Definition at line 90 of file TxtInfoHob.h.

Typedef Documentation

◆ TXT_INFO_DATA

typedef struct _TXT_INFO_DATA TXT_INFO_DATA

TXT Info data.

The data that will be passed to DXE via TXT_INFO_HOB. TXT info

◆ TXT_INFO_HOB

typedef struct _TXT_INFO_HOB TXT_INFO_HOB

HOB to save TXT Info data.

TXT Info HOB is used for passing Policy settings and CPU/chipset information within TXT modules. TXT Info HOB

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TxtInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
TxtInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains definitions required for creation of TXT Info HOB.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 1999 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _TXT_HOB_H_
36 #define _TXT_HOB_H_
37
38
39 #pragma pack(push, 1)
40 ///
41 /// TXT Info data.
42 /// The data that will be passed to DXE via TXT_INFO_HOB.
43 ///
44 typedef struct _TXT_INFO_DATA {
45 UINT64 SinitMemorySize; ///< Size of memory reserved for placement of SINIT module. This memory is used by MLE.
46 UINT64 TxtHeapMemorySize; ///< Size of memory reserved for TXT Heap. This memory is used by MLE.
47 EFI_PHYSICAL_ADDRESS TxtDprMemoryBase; ///< Base address of DPR protected memory reserved for Intel TXT component.
48 UINT64 TxtDprMemorySize; ///< Size of DPR protected memory reserved for TXT component.
49 EFI_PHYSICAL_ADDRESS BiosAcmBase; ///< Base address of BIOS ACM in system firmware.
50 UINT64 BiosAcmSize; ///< Size of BIOS ACM.
51 EFI_PHYSICAL_ADDRESS SinitAcmBase; ///< Base address of SINIT module if installed in system firmware. Zero otherwise.
52 UINT64 SinitAcmSize; ///< Size of SINIT module if installed in system firmware. Zero otherwise.
53 UINT64 TgaSize; ///< Size of Trusted Graphics Aperture if supported by chipset.
54 EFI_PHYSICAL_ADDRESS TxtLcpPdBase; ///< Base address of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
55 UINT64 TxtLcpPdSize; ///< Size of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise.
56 /**
57 Flags passed from BIOS to OS or MRC.
58 - BIT0: FLAGS0 for compatible definition.
59 - BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
60 - BIT2: TPM_INIT_FAILED for indicate TPM initiate status. If the bit set, ResetEstablishmentBit is skipped in Dxe driver.
61 **/
62 UINT64 Flags;
63 EFI_PHYSICAL_ADDRESS ApStartupBase; ///< Base address of AP Startup code
64
65 EFI_PHYSICAL_ADDRESS TsegBase; ///< Physical base address of TSEG region.
66 UINT64 TsegSize; ///< Size of the entity at TSEG region.
67 EFI_PHYSICAL_ADDRESS MsegBase; ///< Physical base address of MSEG region.
68 UINT64 MsegSize; ///< Size of the entity at MSEG region.
69
70 UINT32 AcpiBase:16; ///< Address of PM1a_CNT_BLK register block. It is used by TXT PEIM to clean Sleep Type field of PM1a_CNT_BLK.S4 register before running of SCLEAN.
71 UINT32 ChipsetIsTxtCapable:1; ///< Value is set to 1 if chipset is Intel TXT capable.
72 UINT32 TxtMode:1; ///< Value is set to 1 if Intel TXT mode is enabled in BIOS Setup.
73 UINT32 ResetAux:1; ///< Value is set to 1 if reset Aux is enabled in BIOS Setup.
74 UINT32 TxtAcheckRequest:1; ///< Value is set to 1 if TXT Acheck Request is enabled in BIOS Setup.
75 UINT32 ProcessorIsTxtCapable:1; ///< Value is set to 1 if processor is Intel TXT capable.
76 UINT32 Reserved:11; ///< Reserved for future use
77
78 UINT8 AcmMajorVersion; ///< BIOSACM binary major version
79 UINT8 AcmMinorVersion; ///< BIOSACM binary minor version
80 UINT8 AcmRevision; ///< BIOSACM binary revision
81
82 // Since the biggest element is UINT64, this structure should be aligned with 64 bits.
83 UINT8 Rsvd[1]; ///< Reserved for config block alignment.
84 } TXT_INFO_DATA; ///< TXT info
85
86 // Flags passed from BIOS to OS or MRC.
87 #define FLAGS0 0x1 ///< BIT0: FLAGS0 for compatible definition.
88 #define TXT_CPU_RESET_REQUIRED 0x2 ///< BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required.
89 #define TPM_INIT_FAILED 0x4 ///< BIT2: TPM_INIT_FAILED for indicate TPM initiate status.
90 ///< If the bit set, ResetEstablishmentBit is skipped in Dxe driver.
91
92
93 ///
94 /// HOB to save TXT Info data.
95 /// TXT Info HOB is used for passing Policy settings and CPU/chipset information within TXT modules.
96 ///
97 typedef struct _TXT_INFO_HOB {
98 EFI_HOB_GUID_TYPE EfiHobGuidType; ///< EFI Hob Guid Type.
99 TXT_INFO_DATA Data; ///< TXT Info Data.
100 } TXT_INFO_HOB; ///< TXT Info HOB
101 #pragma pack(pop)
102
103 #endif
_TXT_INFO_DATA::ApStartupBase
EFI_PHYSICAL_ADDRESS ApStartupBase
Base address of AP Startup code.
Definition: TxtInfoHob.h:63
_TXT_INFO_DATA::TxtAcheckRequest
UINT32 TxtAcheckRequest
Value is set to 1 if TXT Acheck Request is enabled in BIOS Setup.
Definition: TxtInfoHob.h:74
_TXT_INFO_DATA::BiosAcmSize
UINT64 BiosAcmSize
Size of BIOS ACM.
Definition: TxtInfoHob.h:50
_TXT_INFO_DATA::BiosAcmBase
EFI_PHYSICAL_ADDRESS BiosAcmBase
Base address of BIOS ACM in system firmware.
Definition: TxtInfoHob.h:49
_TXT_INFO_DATA::AcmMajorVersion
UINT8 AcmMajorVersion
BIOSACM binary major version.
Definition: TxtInfoHob.h:78
_TXT_INFO_DATA::AcmMinorVersion
UINT8 AcmMinorVersion
BIOSACM binary minor version.
Definition: TxtInfoHob.h:79
_TXT_INFO_DATA::TxtDprMemorySize
UINT64 TxtDprMemorySize
Size of DPR protected memory reserved for TXT component.
Definition: TxtInfoHob.h:48
_TXT_INFO_HOB
HOB to save TXT Info data.
Definition: TxtInfoHob.h:97
_TXT_INFO_DATA::TxtDprMemoryBase
EFI_PHYSICAL_ADDRESS TxtDprMemoryBase
Base address of DPR protected memory reserved for Intel TXT component.
Definition: TxtInfoHob.h:47
_TXT_INFO_DATA::SinitAcmBase
EFI_PHYSICAL_ADDRESS SinitAcmBase
Base address of SINIT module if installed in system firmware. Zero otherwise.
Definition: TxtInfoHob.h:51
_TXT_INFO_DATA::SinitAcmSize
UINT64 SinitAcmSize
Size of SINIT module if installed in system firmware. Zero otherwise.
Definition: TxtInfoHob.h:52
_TXT_INFO_DATA::TxtLcpPdBase
EFI_PHYSICAL_ADDRESS TxtLcpPdBase
Base address of Platform Default Launch Control Policy data if installed in system firmware....
Definition: TxtInfoHob.h:54
_TXT_INFO_DATA::TsegSize
UINT64 TsegSize
Size of the entity at TSEG region.
Definition: TxtInfoHob.h:66
_TXT_INFO_DATA::TsegBase
EFI_PHYSICAL_ADDRESS TsegBase
Physical base address of TSEG region.
Definition: TxtInfoHob.h:65
_TXT_INFO_DATA::Flags
UINT64 Flags
Flags passed from BIOS to OS or MRC.
Definition: TxtInfoHob.h:62
_TXT_INFO_DATA::ProcessorIsTxtCapable
UINT32 ProcessorIsTxtCapable
Value is set to 1 if processor is Intel TXT capable.
Definition: TxtInfoHob.h:75
_TXT_INFO_DATA::TxtLcpPdSize
UINT64 TxtLcpPdSize
Size of Platform Default Launch Control Policy data if installed in system firmware....
Definition: TxtInfoHob.h:55
_TXT_INFO_DATA::ResetAux
UINT32 ResetAux
Value is set to 1 if reset Aux is enabled in BIOS Setup.
Definition: TxtInfoHob.h:73
_TXT_INFO_DATA::ChipsetIsTxtCapable
UINT32 ChipsetIsTxtCapable
Value is set to 1 if chipset is Intel TXT capable.
Definition: TxtInfoHob.h:71
_TXT_INFO_DATA
TXT Info data.
Definition: TxtInfoHob.h:44
_TXT_INFO_DATA::AcmRevision
UINT8 AcmRevision
BIOSACM binary revision.
Definition: TxtInfoHob.h:80
_TXT_INFO_DATA::TgaSize
UINT64 TgaSize
Size of Trusted Graphics Aperture if supported by chipset.
Definition: TxtInfoHob.h:53
_TXT_INFO_HOB::Data
TXT_INFO_DATA Data
TXT Info Data.
Definition: TxtInfoHob.h:99
_TXT_INFO_DATA::TxtHeapMemorySize
UINT64 TxtHeapMemorySize
Size of memory reserved for TXT Heap. This memory is used by MLE.
Definition: TxtInfoHob.h:46
_TXT_INFO_DATA::Rsvd
UINT8 Rsvd[1]
Reserved for config block alignment.
Definition: TxtInfoHob.h:83
_TXT_INFO_DATA::MsegSize
UINT64 MsegSize
Size of the entity at MSEG region.
Definition: TxtInfoHob.h:68
TXT_INFO_HOB
struct _TXT_INFO_HOB TXT_INFO_HOB
HOB to save TXT Info data.
_TXT_INFO_DATA::Reserved
UINT32 Reserved
Reserved for future use.
Definition: TxtInfoHob.h:76
TXT_INFO_DATA
struct _TXT_INFO_DATA TXT_INFO_DATA
TXT Info data.
_TXT_INFO_DATA::AcpiBase
UINT32 AcpiBase
Address of PM1a_CNT_BLK register block. It is used by TXT PEIM to clean Sleep Type field of PM1a_CNT_...
Definition: TxtInfoHob.h:70
_TXT_INFO_HOB::EfiHobGuidType
EFI_HOB_GUID_TYPE EfiHobGuidType
EFI Hob Guid Type.
Definition: TxtInfoHob.h:98
_TXT_INFO_DATA::MsegBase
EFI_PHYSICAL_ADDRESS MsegBase
Physical base address of MSEG region.
Definition: TxtInfoHob.h:67
_TXT_INFO_DATA::TxtMode
UINT32 TxtMode
Value is set to 1 if Intel TXT mode is enabled in BIOS Setup.
Definition: TxtInfoHob.h:72
_TXT_INFO_DATA::SinitMemorySize
UINT64 SinitMemorySize
Size of memory reserved for placement of SINIT module. This memory is used by MLE.
Definition: TxtInfoHob.h:45
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TxtLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
Functions
TxtLib.h File Reference

Header file for TXT Lib implementation. More...

Go to the source code of this file.

Functions

UINT32 CheckSmxCapabilities (VOID)
Execute GETSEC[CAPABILITIES] to report the SMX capabilities.

Detailed Description

Header file for TXT Lib implementation.

Copyright
INTEL CONFIDENTIAL Copyright 2012 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file TxtLib.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TxtLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
TxtLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for TXT Lib implementation.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2012 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _TXT_LIB_H_
37 #define _TXT_LIB_H_
38
39
40 ///
41 /// Execute GETSEC[CAPABILITIES] to report the SMX capabilities.
42 ///
43 UINT32
44 CheckSmxCapabilities (
45 VOID
46 )
47 ;
48
49 #endif
CheckSmxCapabilities
UINT32 CheckSmxCapabilities(VOID)
Execute GETSEC[CAPABILITIES] to report the SMX capabilities.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UpidMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes | Enumerations
UpidMsgs.h File Reference

Definitions for Unique Platform ID messages support. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

union | UPID_MESSAGE_HEADER
UPID (Unique Platform Id) Message Header. More...
struct | GET_FEATURE_SUPPORT_REQUEST
Common Features Definitions. More...
struct | GET_FEATURE_STATE_REQUEST
Get/Set Feature State. More...
struct | GET_OS_CONTROL_FEATURE_STATE_REQUEST
Get/Set Os Control Feature State. More...
struct | GET_PLATFORM_ID_REQUEST
Platform Id Feature Defintions. More...
struct | GET_REFURBISH_COUNTER_REQUEST
Get Refurbish Counter. More...
struct | UPDATE_OEM_PLATFORM_ID_REQUEST
Update OEM Platform Id. More...

Enumerations

enum | UPID_FEATURE
Typedef for UPID Feature.
enum | UPID_COMMON_FEATURE
Typedef for common feature commands.
enum | PLAT_ID_FEATURE
Typedef for Platform Id commands.
enum | UPID_STATUS
Typedef for UPID Status.

Detailed Description

Definitions for Unique Platform ID messages support.

Copyright
INTEL CONFIDENTIAL Copyright 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UpidMsgs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UpidMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
UpidMsgs.h
Go to the documentation of this file.
1 /** @file
2 Definitions for Unique Platform ID messages support
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _UPID_MSGS_H_
36 #define _UPID_MSGS_H_
37
38 #pragma pack(1)
39
40 ///
41 /// UPID (Unique Platform Id) Message Header
42 ///
43 typedef union {
44 UINT32 Data;
45 struct {
46 UINT32 Feature : 8;
47 UINT32 Command : 8;
48 UINT32 Length : 16;
49 } Fields;
50 } UPID_MESSAGE_HEADER;
51
52 #define UPID_MESSAGE_BYTE_COUNT_MAP(a) (sizeof(a)-sizeof(UPID_MESSAGE_HEADER))
53
54 ///
55 /// Typedef for UPID Feature
56 ///
57 typedef enum {
58 UpidFeaturePlatId = 0x00
59 } UPID_FEATURE;
60
61 ///
62 /// Typedef for common feature commands
63 ///
64 typedef enum {
65 UpidCommonGetFeatureSupport = 0x00,
66 UpidCommonGetFeatureState = 0x01,
67 UpidCommonSetFeatureState = 0x02,
68 UpidCommonGetOsControlFeatureState = 0x03,
69 UpidCommonSetOsControlFeatureState = 0x04
70 } UPID_COMMON_FEATURE;
71
72 ///
73 /// Typedef for Platform Id commands
74 ///
75 typedef enum {
76 PlatIdGetPlatformId = 0x05,
77 PlatIdGetRefurbishCounter = 0x06,
78 PlatIdUpdateOemPlatformId = 0x07
79 } PLAT_ID_FEATURE;
80
81 ///
82 /// Typedef for UPID Status
83 ///
84 typedef enum {
85 UpidStatusSuccess,
86 UpidStatusFeatureNotSupported,
87 UpidStatusInvalidInputParameter,
88 UpidStatusInternalError,
89 UpidStatusNotAllowedAfterEop,
90 UpidStatusMaxCountersExceeded,
91 } UPID_STATUS;
92
93 ///
94 /// Common Features Definitions
95 ///
96
97 ///
98 /// Get Feature Support
99 ///
100 typedef struct {
101 UPID_MESSAGE_HEADER UpidHeader;
102 } GET_FEATURE_SUPPORT_REQUEST;
103
104 typedef struct {
105 UPID_MESSAGE_HEADER UpidHeader;
106 UINT32 Status;
107 UINT8 PlatIdFeatureSupport;
108 } GET_FEATURE_SUPPORT_RESPONSE;
109
110 typedef union {
111 GET_FEATURE_SUPPORT_REQUEST Request;
112 GET_FEATURE_SUPPORT_RESPONSE Response;
113 } GET_FEATURE_SUPPORT_BUFFER;
114
115 ///
116 /// Get/Set Feature State
117 ///
118 typedef struct {
119 UPID_MESSAGE_HEADER UpidHeader;
120 } GET_FEATURE_STATE_REQUEST;
121
122 typedef struct {
123 UPID_MESSAGE_HEADER UpidHeader;
124 UINT32 Status;
125 UINT8 PlatIdFeatureState;
126 } GET_FEATURE_STATE_RESPONSE;
127
128 typedef union {
129 GET_FEATURE_STATE_REQUEST Request;
130 GET_FEATURE_STATE_RESPONSE Response;
131 } GET_FEATURE_STATE_BUFFER;
132
133 typedef struct {
134 UPID_MESSAGE_HEADER UpidHeader;
135 UINT8 PlatIdFeatureState;
136 } SET_FEATURE_STATE_REQUEST;
137
138 typedef struct {
139 UPID_MESSAGE_HEADER UpidHeader;
140 UINT32 Status;
141 } SET_FEATURE_STATE_RESPONSE;
142
143 typedef union {
144 SET_FEATURE_STATE_REQUEST Request;
145 SET_FEATURE_STATE_RESPONSE Response;
146 } SET_FEATURE_STATE_BUFFER;
147
148 ///
149 /// Get/Set Os Control Feature State
150 ///
151 typedef struct {
152 UPID_MESSAGE_HEADER UpidHeader;
153 } GET_OS_CONTROL_FEATURE_STATE_REQUEST;
154
155 typedef struct {
156 UPID_MESSAGE_HEADER UpidHeader;
157 UINT32 Status;
158 UINT8 PlatIdFeatureOsControlState;
159 } GET_OS_CONTROL_FEATURE_STATE_RESPONSE;
160
161 typedef union {
162 GET_OS_CONTROL_FEATURE_STATE_REQUEST Request;
163 GET_OS_CONTROL_FEATURE_STATE_RESPONSE Response;
164 } GET_OS_CONTROL_FEATURE_STATE_BUFFER;
165
166 typedef struct {
167 UPID_MESSAGE_HEADER UpidHeader;
168 UINT8 PlatIdFeatureOsControlState;
169 } SET_OS_CONTROL_FEATURE_STATE_REQUEST;
170
171 typedef struct {
172 UPID_MESSAGE_HEADER UpidHeader;
173 UINT32 Status;
174 } SET_OS_CONTROL_FEATURE_STATE_RESPONSE;
175
176 typedef union {
177 SET_OS_CONTROL_FEATURE_STATE_REQUEST Request;
178 SET_OS_CONTROL_FEATURE_STATE_RESPONSE Response;
179 } SET_OS_CONTROL_FEATURE_STATE_BUFFER;
180
181 ///
182 /// Platform Id Feature Defintions
183 ///
184
185 ///
186 /// Get Platform Id
187 ///
188 typedef struct {
189 UPID_MESSAGE_HEADER UpidHeader;
190 } GET_PLATFORM_ID_REQUEST;
191
192 #define MAX_PLAT_ID_SIZE 32
193
194 typedef enum {
195 OemPlatIdTypeNotSet,
196 OemPlatIdTypeBinary,
197 OemPlatIdTypePrintableString
198 } OEM_PLAT_ID_TYPE;
199
200 typedef struct {
201 UPID_MESSAGE_HEADER UpidHeader;
202 UINT32 Status;
203 UINT32 OemPlatIdType;
204 UINT8 OemPlatId[MAX_PLAT_ID_SIZE];
205 UINT8 CsmePlatId[MAX_PLAT_ID_SIZE];
206 } GET_PLATFORM_ID_RESPONSE;
207
208 typedef union {
209 GET_PLATFORM_ID_REQUEST Request;
210 GET_PLATFORM_ID_RESPONSE Response;
211 } GET_PLATFORM_ID_BUFFER;
212
213 //
214 /// Get Refurbish Counter
215 ///
216 typedef struct {
217 UPID_MESSAGE_HEADER UpidHeader;
218 } GET_REFURBISH_COUNTER_REQUEST;
219
220 typedef struct {
221 UPID_MESSAGE_HEADER UpidHeader;
222 UINT32 Status;
223 UINT8 RefurbishCounter;
224 } GET_REFURBISH_COUNTER_RESPONSE;
225
226 typedef union {
227 GET_REFURBISH_COUNTER_REQUEST Request;
228 GET_REFURBISH_COUNTER_RESPONSE Response;
229 } GET_REFURBISH_COUNTER_BUFFER;
230
231 ///
232 /// Update OEM Platform Id
233 ///
234 typedef struct {
235 UPID_MESSAGE_HEADER UpidHeader;
236 UINT32 OemPlatIdType;
237 UINT8 OemPlatId[MAX_PLAT_ID_SIZE];
238 UINT8 ManufacturingType;
239 } UPDATE_OEM_PLATFORM_ID_REQUEST;
240
241 typedef struct {
242 UPID_MESSAGE_HEADER UpidHeader;
243 UINT32 Status;
244 } UPDATE_OEM_PLATFORM_ID_RESPONSE;
245
246 typedef union {
247 UPDATE_OEM_PLATFORM_ID_REQUEST Request;
248 UPDATE_OEM_PLATFORM_ID_RESPONSE Response;
249 } UPDATE_OEM_PLATFORM_ID_BUFFER;
250
251 #pragma pack()
252
253 #endif // _UPID_MSGS_H_
254
GET_FEATURE_STATE_REQUEST
Get/Set Feature State.
Definition: UpidMsgs.h:118
UPID_STATUS
UPID_STATUS
Typedef for UPID Status.
Definition: UpidMsgs.h:84
UPDATE_OEM_PLATFORM_ID_REQUEST
Update OEM Platform Id.
Definition: UpidMsgs.h:234
UPID_MESSAGE_HEADER
UPID (Unique Platform Id) Message Header.
Definition: UpidMsgs.h:43
PLAT_ID_FEATURE
PLAT_ID_FEATURE
Typedef for Platform Id commands.
Definition: UpidMsgs.h:75
GET_FEATURE_SUPPORT_REQUEST
Common Features Definitions.
Definition: UpidMsgs.h:100
UPID_FEATURE
UPID_FEATURE
Typedef for UPID Feature.
Definition: UpidMsgs.h:57
GET_PLATFORM_ID_REQUEST
Platform Id Feature Defintions.
Definition: UpidMsgs.h:188
UPID_COMMON_FEATURE
UPID_COMMON_FEATURE
Typedef for common feature commands.
Definition: UpidMsgs.h:64
GET_REFURBISH_COUNTER_REQUEST
Get Refurbish Counter.
Definition: UpidMsgs.h:216
GET_OS_CONTROL_FEATURE_STATE_REQUEST
Get/Set Os Control Feature State.
Definition: UpidMsgs.h:151
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Usb2PhyConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes
Usb2PhyConfig.h File Reference

USB2 PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb2PhyConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings. More...
struct | USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout. More...

Detailed Description

USB2 PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb2PhyConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Usb2PhyConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb2PhyConfig.h
Go to the documentation of this file.
1 /** @file
2 USB2 PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _USB2_PHY_CONFIG_H_
36 #define _USB2_PHY_CONFIG_H_
37
38 #include <UsbConfig.h>
39
40 #define USB2_PHY_CONFIG_REVISION 1
41 extern EFI_GUID gUsb2PhyConfigGuid;
42
43 #pragma pack (push,1)
44
45 /**
46 This structure configures per USB2 AFE settings.
47 It allows to setup the port electrical parameters.
48 **/
49 typedef struct {
50 /** Per Port HS Preemphasis Bias (PERPORTPETXISET)
51 000b - 0mV
52 001b - 11.25mV
53 010b - 16.9mV
54 011b - 28.15mV
55 100b - 28.15mV
56 101b - 39.35mV
57 110b - 45mV
58 111b - 56.3mV
59 **/
60 UINT8 Petxiset;
61 /** Per Port HS Transmitter Bias (PERPORTTXISET)
62 000b - 0mV
63 001b - 11.25mV
64 010b - 16.9mV
65 011b - 28.15mV
66 100b - 28.15mV
67 101b - 39.35mV
68 110b - 45mV
69 111b - 56.3mV
70 **/
71 UINT8 Txiset;
72 /**
73 Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
74 00b - Emphasis OFF
75 01b - De-emphasis ON
76 10b - Pre-emphasis ON
77 11b - Pre-emphasis & De-emphasis ON
78 **/
79 UINT8 Predeemp;
80 /**
81 Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
82 1b - half-bit pre-emphasis
83 0b - full-bit pre-emphasis
84 **/
85 UINT8 Pehalfbit;
86 } USB2_PHY_PARAMETERS;
87
88 /**
89 This structure holds info on how to tune electrical parameters of USB2 ports based on board layout
90
91 <b>Revision 1</b>:
92 - Initial version.
93
94 **/
95 typedef struct {
96 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
97 /**
98 This structure configures per USB2 port physical settings.
99 It allows to setup the port location and port length, and configures the port strength accordingly.
100 Changing this policy values from default ones may require disabling USB2 PHY Sus Well Power Gating
101 through Usb2PhySusPgEnable on PCH-LP
102 **/
103 USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];
104 } USB2_PHY_CONFIG;
105
106 #pragma pack (pop)
107
108 #endif // _USB2_PHY_CONFIG_H_
109
USB2_PHY_PARAMETERS::Pehalfbit
UINT8 Pehalfbit
Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) 1b - half-bit pre-emphasis 0b - full-bit pre-emphasi...
Definition: Usb2PhyConfig.h:85
USB2_PHY_PARAMETERS::Predeemp
UINT8 Predeemp
Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) 00b - Emphasis OFF 01b - De-emphasis ON 10b - Pre...
Definition: Usb2PhyConfig.h:79
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
USB2_PHY_PARAMETERS::Petxiset
UINT8 Petxiset
Per Port HS Preemphasis Bias (PERPORTPETXISET) 000b - 0mV 001b - 11.25mV 010b - 16....
Definition: Usb2PhyConfig.h:60
USB2_PHY_PARAMETERS::Txiset
UINT8 Txiset
Per Port HS Transmitter Bias (PERPORTTXISET) 000b - 0mV 001b - 11.25mV 010b - 16.9mV 011b - 28....
Definition: Usb2PhyConfig.h:71
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB2_PHY_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: Usb2PhyConfig.h:96
USB2_PHY_PARAMETERS
This structure configures per USB2 AFE settings.
Definition: Usb2PhyConfig.h:49
USB2_PHY_CONFIG
This structure holds info on how to tune electrical parameters of USB2 ports based on board layout.
Definition: Usb2PhyConfig.h:95
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Usb3HsioConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes
Usb3HsioConfig.h File Reference

USB3 Mod PHY configuration policy. More...

#include <UsbConfig.h>
Include dependency graph for Usb3HsioConfig.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters. More...
struct | USB3_HSIO_CONFIG
Structure for holding USB3 tuning parameters. More...

Detailed Description

USB3 Mod PHY configuration policy.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2019 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Usb3HsioConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Usb3HsioConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb3HsioConfig.h
Go to the documentation of this file.
1 /** @file
2 USB3 Mod PHY configuration policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2019 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _USB3_HSIO_CONFIG_H_
37 #define _USB3_HSIO_CONFIG_H_
38
39 #include <UsbConfig.h>
40
41 #define USB3_HSIO_CONFIG_REVISION 2
42 extern EFI_GUID gUsb3HsioConfigGuid;
43
44 #pragma pack (push,1)
45
46 /**
47 This structure describes USB3 Port N configuration parameters
48 **/
49 typedef struct {
50 /**
51 USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
52 HSIO_TX_DWORD8[21:16]
53 <b>Default = 00h</b>
54 **/
55 UINT8 HsioTxDownscaleAmp;
56 /**
57 USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
58 HSIO_TX_DWORD5[21:16]
59 <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
60 **/
61 UINT8 HsioTxDeEmph;
62 /**
63 Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_4_0)
64 HSIO_RX_DWORD25 [20:16]
65 Ex: -1 -- 1_0001. +1: 0_0001
66 <b>Default = 0h</b>
67 **/
68 UINT8 HsioCtrlAdaptOffsetCfg;
69 /**
70 LFPS filter select for n (filter_sel_n_2_0)
71 HSIO_RX_DWORD51 [29:27]
72 0h:1.6ns
73 1h:2.4ns
74 2h:3.2ns
75 3h:4.0ns
76 4h:4.8ns
77 5h:5.6ns
78 6h:6.4ns
79 <b>Default = 0h</b>
80 **/
81 UINT8 HsioFilterSelN;
82 /**
83 LFPS filter select for p (filter_sel_p_2_0)
84 HSIO_RX_DWORD51 [26:24]
85 0h:1.6ns
86 1h:2.4ns
87 2h:3.2ns
88 3h:4.0ns
89 4h:4.8ns
90 5h:5.6ns
91 6h:6.4ns
92 <b>Default = 0h</b>
93 **/
94 UINT8 HsioFilterSelP;
95 /**
96 Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)
97 HSIO_RX_DWORD51 [2:0]
98 000 Prohibited
99 001 45K
100 010 Prohibited
101 011 31K
102 100 36K
103 101 36K
104 110 36K
105 111 36K
106 <b>Default = 3h</b>
107 **/
108 UINT8 HsioOlfpsCfgPullUpDwnRes;
109
110 UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
111 UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
112 UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed Magnatude number added to the CTLE code, <b>0: Disable</b>; 1: Enable.
113 UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS filter select for n, <b>0: Disable</b>; 1: Enable.
114 UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS filter select for p, <b>0: Disable</b>; 1: Enable.
115 UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfgpullupdwnres, <b>0: Disable</b>; 1: Enable.
116 /**
117 USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale)
118 HSIO_TX_DWORD9[6:0]
119 <b>Default = 4Ch</b>
120 **/
121 UINT8 HsioTxRate3UniqTran;
122 /**
123 USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale)
124 HSIO_TX_DWORD9[14:8]
125 <b>Default = 4Ch</b>
126 **/
127 UINT8 HsioTxRate2UniqTran;
128 /**
129 USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale)
130 HSIO_TX_DWORD9[22:16]
131 <b>Default = 4Ch</b>
132 **/
133 UINT8 HsioTxRate1UniqTran;
134 /**
135 USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale)
136 HSIO_TX_DWORD9[30:24]
137 <b>Default = 4Ch</b>
138 **/
139 UINT8 HsioTxRate0UniqTran;
140
141 UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, <b>0: Disable</b>; 1: Enable.
142 UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, <b>0: Disable</b>; 1: Enable.
143 UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, <b>0: Disable</b>; 1: Enable.
144 UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, <b>0: Disable</b>; 1: Enable.
145 } HSIO_PARAMETERS;
146
147 /**
148 Structure for holding USB3 tuning parameters
149
150 <b>Revision 1</b>:
151 - Initial version.
152 <b>Revision 2</b>:
153 - USB 3.0 TX Output Unique Transition Bit Scale policies added
154 **/
155 typedef struct {
156 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
157 /**
158 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
159 **/
160 HSIO_PARAMETERS Port[MAX_USB3_PORTS];
161 } USB3_HSIO_CONFIG;
162
163 #pragma pack (pop)
164
165 #endif // _USB3_HSIO_CONFIG_H_
166
HSIO_PARAMETERS::HsioTxRate0UniqTranEnable
UINT8 HsioTxRate0UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:144
USB3_HSIO_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: Usb3HsioConfig.h:156
HSIO_PARAMETERS::HsioTxDownscaleAmp
UINT8 HsioTxDownscaleAmp
USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) HSIO_TX_DWORD8[21:16] Default = 00h
Definition: Usb3HsioConfig.h:55
HSIO_PARAMETERS::HsioTxRate3UniqTran
UINT8 HsioTxRate3UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqTranScale) HSIO_TX_DWORD9[6:0] D...
Definition: Usb3HsioConfig.h:121
HSIO_PARAMETERS::HsioTxRate2UniqTranEnable
UINT8 HsioTxRate2UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:142
HSIO_PARAMETERS::HsioTxDeEmphEnable
UINT8 HsioTxDeEmphEnable
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:110
HSIO_PARAMETERS::HsioFilterSelNEnable
UINT8 HsioFilterSelNEnable
Enable the write to LFPS filter select for n, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:113
HSIO_PARAMETERS::HsioFilterSelPEnable
UINT8 HsioFilterSelPEnable
Enable the write to LFPS filter select for p, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:114
UsbConfig.h
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
USB3_HSIO_CONFIG
Structure for holding USB3 tuning parameters.
Definition: Usb3HsioConfig.h:155
HSIO_PARAMETERS::HsioTxRate3UniqTranEnable
UINT8 HsioTxRate3UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:141
HSIO_PARAMETERS::HsioTxRate1UniqTran
UINT8 HsioTxRate1UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqTranScale) HSIO_TX_DWORD9[22:16]...
Definition: Usb3HsioConfig.h:133
HSIO_PARAMETERS::HsioFilterSelN
UINT8 HsioFilterSelN
LFPS filter select for n (filter_sel_n_2_0) HSIO_RX_DWORD51 [29:27] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:81
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfgEnable
UINT8 HsioCtrlAdaptOffsetCfgEnable
Enable the write to Signed Magnatude number added to the CTLE code, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:112
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
HSIO_PARAMETERS
This structure describes USB3 Port N configuration parameters.
Definition: Usb3HsioConfig.h:49
HSIO_PARAMETERS::HsioTxRate0UniqTran
UINT8 HsioTxRate0UniqTran
USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqTranScale) HSIO_TX_DWORD9[30:24]...
Definition: Usb3HsioConfig.h:139
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnRes
UINT8 HsioOlfpsCfgPullUpDwnRes
Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) HSIO_RX_DWORD51 [2:0] 000 Prohibited 001...
Definition: Usb3HsioConfig.h:108
HSIO_PARAMETERS::HsioTxRate1UniqTranEnable
UINT8 HsioTxRate1UniqTranEnable
Enable the write to USB 3.0 TX Unique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:143
HSIO_PARAMETERS::HsioFilterSelP
UINT8 HsioFilterSelP
LFPS filter select for p (filter_sel_p_2_0) HSIO_RX_DWORD51 [26:24] 0h:1.6ns 1h:2....
Definition: Usb3HsioConfig.h:94
HSIO_PARAMETERS::HsioOlfpsCfgPullUpDwnResEnable
UINT8 HsioOlfpsCfgPullUpDwnResEnable
Enable the write to olfpscfgpullupdwnres, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:115
HSIO_PARAMETERS::HsioTxDownscaleAmpEnable
UINT8 HsioTxDownscaleAmpEnable
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.
Definition: Usb3HsioConfig.h:111
HSIO_PARAMETERS::HsioTxRate2UniqTran
UINT8 HsioTxRate2UniqTran
USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTranScale) HSIO_TX_DWORD9[14:8] D...
Definition: Usb3HsioConfig.h:127
HSIO_PARAMETERS::HsioCtrlAdaptOffsetCfg
UINT8 HsioCtrlAdaptOffsetCfg
Signed Magnatude number added to the CTLE code.
Definition: Usb3HsioConfig.h:68
HSIO_PARAMETERS::HsioTxDeEmph
UINT8 HsioTxDeEmph
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5) HSIO_TX_DWORD5[21:16] D...
Definition: Usb3HsioConfig.h:61
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Classes | Macros
UsbConfig.h File Reference

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection. More...
struct | USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection. More...
struct | XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller. More...
struct | USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to refer Setup options, schematic, BIOS specification to update this field. More...

Macros

#define USB_OC_MAX_PINS 16
Total OC pins number (both physical and virtual)

Detailed Description

Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UsbConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
UsbConfig.h
Go to the documentation of this file.
1 /** @file
2 Common USB policy shared between PCH and CPU
3 Contains general features settings for xHCI and xDCI
4
5 @copyright
6 INTEL CONFIDENTIAL
7 Copyright 2017 - 2021 Intel Corporation.
8
9 The source code contained or described herein and all documents related to the
10 source code ("Material") are owned by Intel Corporation or its suppliers or
11 licensors. Title to the Material remains with Intel Corporation or its suppliers
12 and licensors. The Material may contain trade secrets and proprietary and
13 confidential information of Intel Corporation and its suppliers and licensors,
14 and is protected by worldwide copyright and trade secret laws and treaty
15 provisions. No part of the Material may be used, copied, reproduced, modified,
16 published, uploaded, posted, transmitted, distributed, or disclosed in any way
17 without Intel's prior express written permission.
18
19 No license under any patent, copyright, trade secret or other intellectual
20 property right is granted to or conferred upon you by disclosure or delivery
21 of the Materials, either expressly, by implication, inducement, estoppel or
22 otherwise. Any license under such intellectual property rights must be
23 express and approved by Intel in writing.
24
25 Unless otherwise agreed by Intel in writing, you may not remove or alter
26 this notice or any other notice embedded in Materials by Intel or
27 Intel's suppliers or licensors in any way.
28
29 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
30 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
31 the terms of your license agreement with Intel or your vendor. This file may
32 be modified by the user, subject to additional terms of the license agreement.
33
34 @par Specification Reference:
35 **/
36 #ifndef _USB_CONFIG_H_
37 #define _USB_CONFIG_H_
38
39 #define USB_CONFIG_REVISION 3
40 extern EFI_GUID gUsbConfigGuid;
41
42 #define MAX_USB2_PORTS 16
43 #define MAX_USB3_PORTS 10
44
45 #pragma pack (push,1)
46
47 typedef UINT8 USB_OVERCURRENT_PIN;
48 #define USB_OC_SKIP 0xFF
49 #define USB_OC_MAX_PINS 16 ///< Total OC pins number (both physical and virtual)
50
51 /**
52 This structure configures per USB2.0 port settings like enabling and overcurrent protection
53 **/
54 typedef struct {
55 /**
56 These members describe the specific over current pin number of USB 2.0 Port N.
57 It is SW's responsibility to ensure that a given port's bit map is set only for
58 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
59 **/
60 UINT32 OverCurrentPin : 8;
61 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
62 UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
63 UINT32 RsvdBits0 : 22; ///< Reserved bits
64 } USB2_PORT_CONFIG;
65
66 /**
67 This structure configures per USB3.x port settings like enabling and overcurrent protection
68 **/
69 typedef struct {
70 /**
71 These members describe the specific over current pin number of USB 3.x Port N.
72 It is SW's responsibility to ensure that a given port's bit map is set only for
73 one OC pin Description. USB2 and USB3 on the same combo Port must use the same OC pin.
74 **/
75 UINT32 OverCurrentPin : 8;
76 UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
77 UINT32 RsvdBits0 : 23; ///< Reserved bits
78 } USB3_PORT_CONFIG;
79
80 /**
81 The XDCI_CONFIG block describes the configurations
82 of the xDCI Usb Device controller.
83 **/
84 typedef struct {
85 /**
86 This member describes whether or not the xDCI controller should be enabled.
87 0: Disable; <b>1: Enable</b>.
88 **/
89 UINT32 Enable : 1;
90 UINT32 RsvdBits0 : 31; ///< Reserved bits
91 } XDCI_CONFIG;
92
93
94 /**
95 This member describes the expected configuration of the USB controller,
96 Platform modules may need to refer Setup options, schematic, BIOS specification to update this field.
97 The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring the schematic.
98
99 <b>Revision 1</b>:
100 - Initial version.
101 <b>Revision 2</b>:
102 - Added UaolEnable to control USB Audio Offload Capability.
103 <b>Revision 3</b>:
104 - Add HsiiEnable enable option to control HSII feature
105 **/
106 typedef struct {
107 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
108 /**
109 This policy option when set will make BIOS program Port Disable Override register during PEI phase.
110 When disabled BIOS will not program the PDO during PEI phase and leave PDO register unlocked for later programming.
111 If this is disabled, platform code MUST set it before booting into OS.
112 <b>1: Enable</b>
113 0: Disable
114 **/
115 UINT32 PdoProgramming : 1;
116 /**
117 This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
118 Disabling this feature will disable overcurrent detection functionality.
119 Overcurrent Pin mapping data is contained in respective port structures (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.
120 By default this Overcurrent functionality should be enabled and disabled only for OBS debug usage.
121 <b>1: Will program USB OC pin mapping in respective xHCI controller registers</b>
122 0: Will clear OC pin mapping allow for OBS usage of OC pins
123 **/
124 UINT32 OverCurrentEnable : 1;
125 /**
126 <b>(Test)</b>
127 If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be
128 consumed by xHCI and OC mapping registers will be locked. OverCurrent mapping data is taken from respective port data
129 structure from OverCurrentPin field.
130 If EnableOverCurrent policy is enabled this also should be enabled, otherwise xHCI won't consume OC mapping data.
131 <b>1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping data</b>
132 0: Do not program OCCFDONE bit making it possible to use OBS debug on OC pins.
133 **/
134 UINT32 XhciOcLock : 1;
135 /**
136 Enabling this feature will allow for overriding LTR values for xHCI controller.
137 Values used for programming will be taken from this config block and BIOS will disregard recommended ones.
138 <b>0: disable - do not override recommended LTR values</b>
139 1: enable - override recommended LTR values
140 **/
141 UINT32 LtrOverrideEnable : 1;
142 /**
143 Enable/disable option for USB Audio Offload feture. Disabling this will disable UAOL capability
144 in xHCI and UAOL ACPI definitions will be hidden.
145 0: disable UAOL
146 <b>1: enable UAOL</b>
147 **/
148 UINT32 UaolEnable : 1;
149 /**
150 Enable HS Interrupt IN Alarm
151 0: disable - Disable HSII
152 <b>1: enable - Enable HSII</b>
153 **/
154 UINT32 HsiiEnable : 1;
155 UINT32 RsvdBits0 : 26; ///< Reserved bits
156 /**
157 High Idle Time Control override value
158 This setting is used only if LtrOverrideEnable is enabled
159 **/
160 UINT32 LtrHighIdleTimeOverride;
161 /**
162 Medium Idle Time Control override value
163 This setting is used only if LtrOverrideEnable is enabled
164 **/
165 UINT32 LtrMediumIdleTimeOverride;
166 /**
167 Low Idle Time Control override value
168 This setting is used only if LtrOverrideEnable is enabled
169 **/
170 UINT32 LtrLowIdleTimeOverride;
171 /**
172 These members describe whether the USB2 Port N of PCH is enabled by platform modules.
173 **/
174 USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];
175 /**
176 These members describe whether the USB3 Port N of PCH is enabled by platform modules.
177 **/
178 USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];
179 /**
180 This member describes whether or not the xDCI controller should be enabled.
181 **/
182 XDCI_CONFIG XdciConfig;
183
184 } USB_CONFIG;
185
186 #pragma pack (pop)
187
188 #endif // _USB_CONFIG_H_
USB3_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:76
USB_CONFIG
This member describes the expected configuration of the USB controller, Platform modules may need to ...
Definition: UsbConfig.h:106
USB2_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:63
USB_CONFIG::XhciOcLock
UINT32 XhciOcLock
(Test) If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC m...
Definition: UsbConfig.h:134
USB_CONFIG::UaolEnable
UINT32 UaolEnable
Enable/disable option for USB Audio Offload feture.
Definition: UsbConfig.h:148
USB2_PORT_CONFIG::Enable
UINT32 Enable
0: Disable; 1: Enable.
Definition: UsbConfig.h:61
USB_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:155
XDCI_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:90
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
USB3_PORT_CONFIG
This structure configures per USB3.x port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:69
USB_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: UsbConfig.h:107
USB_CONFIG::XdciConfig
XDCI_CONFIG XdciConfig
This member describes whether or not the xDCI controller should be enabled.
Definition: UsbConfig.h:182
USB_CONFIG::LtrHighIdleTimeOverride
UINT32 LtrHighIdleTimeOverride
High Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:160
USB_CONFIG::LtrMediumIdleTimeOverride
UINT32 LtrMediumIdleTimeOverride
Medium Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:165
XDCI_CONFIG::Enable
UINT32 Enable
This member describes whether or not the xDCI controller should be enabled.
Definition: UsbConfig.h:89
USB_CONFIG::LtrOverrideEnable
UINT32 LtrOverrideEnable
Enabling this feature will allow for overriding LTR values for xHCI controller.
Definition: UsbConfig.h:141
USB_CONFIG::LtrLowIdleTimeOverride
UINT32 LtrLowIdleTimeOverride
Low Idle Time Control override value This setting is used only if LtrOverrideEnable is enabled.
Definition: UsbConfig.h:170
XDCI_CONFIG
The XDCI_CONFIG block describes the configurations of the xDCI Usb Device controller.
Definition: UsbConfig.h:84
USB2_PORT_CONFIG::PortResetMessageEnable
UINT32 PortResetMessageEnable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
Definition: UsbConfig.h:62
USB_CONFIG::OverCurrentEnable
UINT32 OverCurrentEnable
This option allows for control whether USB should program the Overcurrent Pins mapping into xHCI.
Definition: UsbConfig.h:124
USB2_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 2.0 Port N.
Definition: UsbConfig.h:60
USB_CONFIG::PdoProgramming
UINT32 PdoProgramming
This policy option when set will make BIOS program Port Disable Override register during PEI phase.
Definition: UsbConfig.h:115
USB3_PORT_CONFIG::RsvdBits0
UINT32 RsvdBits0
Reserved bits.
Definition: UsbConfig.h:77
USB3_PORT_CONFIG::OverCurrentPin
UINT32 OverCurrentPin
These members describe the specific over current pin number of USB 3.x Port N.
Definition: UsbConfig.h:75
USB_CONFIG::HsiiEnable
UINT32 HsiiEnable
Enable HS Interrupt IN Alarm 0: disable - Disable HSII 1: enable - Enable HSII
Definition: UsbConfig.h:154
USB2_PORT_CONFIG
This structure configures per USB2.0 port settings like enabling and overcurrent protection.
Definition: UsbConfig.h:54
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
UsbLib.h File Reference

Header file of available functions in general USB Library. More...

#include <Uefi/UefiBaseType.h>
Include dependency graph for UsbLib.h:

Go to the source code of this file.

Functions

VOID XhciMmioEnable (VOID)
Set the XHCI controller's PCI CMD.MSE and CMD.BME bits.

Detailed Description

Header file of available functions in general USB Library.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UsbLib.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
UsbLib.h
Go to the documentation of this file.
1 /** @file
2 Header file of available functions in general USB Library
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35
36 #ifndef _USB_LIB_H_
37 #define _USB_LIB_H_
38
39 #include <Uefi/UefiBaseType.h>
40
41 /*
42 Disables requested ports through Port Disable Override register programming
43
44 @param[in] XhciMmioBase xHCI Memory BAR0 address
45 @param[in] Usb2DisabledPorts Disabled ports bitmask with a bit for each USB2 port
46 i.e. BIT0 is Port 0, BIT1 is Port 1 etc
47 @param[in] Usb3DisabledPorts Disabled ports bitmask with a bit for each USB3 port
48 i.e. BIT0 is Port 0, BIT1 is Port 1 etc
49
50 @retval EFI_SUCCESS Programming ended successfully and no errors occured
51 EFI_ACCESS_DENIED Port Disable Override register was locked and write
52 didn't go through. Platform may require restart to unlock.
53 */
54 EFI_STATUS
55 UsbDisablePorts (
56 IN UINTN XhciMmioBase,
57 IN UINT32 Usb2DisabledPorts,
58 IN UINT32 Usb3DisabledPorts
59 );
60
61 /*
62 Disables requested ports through Port Disable Override register programming.
63 This is extended function that allows for defining how many lanes are available
64 since PDO constructed on per lane basis.
65
66 @param[in] XhciMmioBase xHCI Memory BAR0 address
67 @param[in] Usb2DisabledPorts Disabled ports bitmask with a bit for each USB2 port
68 i.e. BIT0 is Port 0, BIT1 is Port 1 etc
69 @param[in] Usb3DisabledPorts Disabled ports bitmask with a bit for each USB3 port
70 i.e. BIT0 is Port 0, BIT1 is Port 1 etc
71 @param[in] Usb2LanesCount Number of USB2 lanes
72 @param[in] Usb3LanesCount Number of USB3 lanes
73
74 @retval EFI_SUCCESS Programming ended successfully and no errors occured
75 EFI_ACCESS_DENIED Port Disable Override register was locked and write
76 didn't go through. Platform may require restart to unlock.
77 */
78 EFI_STATUS
79 UsbDisablePortsEx (
80 IN UINTN XhciMmioBase,
81 IN UINT32 Usb2DisabledPorts,
82 IN UINT32 Usb3DisabledPorts,
83 IN UINT32 Usb2LanesCount,
84 IN UINT32 Usb3LanesCount
85 );
86
87 /**
88 Set the XHCI controller's PCI CMD.MSE and CMD.BME bits.
89
90 **/
91 VOID
92 XhciMmioEnable (
93 VOID
94 );
95
96 #endif // _USB_LIB_H
XhciMmioEnable
VOID XhciMmioEnable(VOID)
Set the XHCI controller's PCI CMD.MSE and CMD.BME bits.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbRegs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Macros
UsbRegs.h File Reference

Register names for USB Host and device controller. More...

Go to the source code of this file.

Macros

#define | B_XHCI_CFG_XHCC2_WRREQSZCTRL (BIT24 | BIT23 | BIT22)
IDMA Write Request Size Control mask.
#define | N_XHCI_CFG_XHCC2_WRREQSZCTRL 22
IDMA Write Request Size Control bit position.
#define | B_XHCI_CFG_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0)
IDMA Read Request Size Control mask.
#define | R_XHCI_CFG_XHCC3 0xFC
XHCI System Bus Configuration 3.
#define | R_XHCI_MEM_PORTSC_START_OFFSET 0x480
Port Status and Control Registers base offset.
#define | S_XHCI_MEM_PORTSC_PORT_SPACING 0x10
Size of space between PortSC register for each port.
#define | B_XHCI_MEM_PORTSCXUSB2_PED BIT1
Port Enable/Disabled.
#define | B_XHCI_MEM_PORTSCXUSB2_CCS BIT0
Current Connect Status.
#define | B_XHCI_MEM_XECP_SUPP_USBX_2_CPC (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
Mask for Compatible Port Count in Capability.
#define | N_XHCI_MEM_XECP_SUPP_USBX_2_CPC 8
Shift for Compatible Port Count.
#define | R_XHCI_MEM_HOST_CTRL_ODMA_REG 0x8098
Host Control ODMA Register.
#define | R_XHCI_MEM_HOST_CTRL_MISC_REG 0x80B0
Host Controller Misc Reg.
#define | R_XHCI_MEM_HOST_CTRL_MISC_REG_2 0x80B4
Host Controller Misc Reg 2.
#define | R_XHCI_MEM_SSPE 0x80B8
Super Speed Port Enables.
#define | R_XHCI_MEM_AUX_CTRL_REG 0x80C0
AUX_CTRL_REG - AUX Reset Control.
#define | R_XHCI_MEM_HOST_CTRL_PORT_LINK_REG 0x80EC
SuperSpeed Port Link Control.
#define | R_XHCI_MEM_HOST_IF_CTRL_REG 0x8108
HOST_IF_CTRL_REG - Host Controller Interface Control Register.
#define | R_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG 0x8138
USB2_PROTOCOL_GAP_TIMER_HIGH_REG - USB2 Protocol Gap Timer HIGH.
#define | R_XHCI_MEM_HOST_IF_PWR_CTRL_REG0 0x8140
HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0.
#define | R_XHCI_MEM_HOST_IF_PWR_CTRL_REG1 0x8144
HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1.
#define | R_XHCI_MEM_AUX_CTRL_REG2 0x8154
AUX_CTRL_REG2 - Aux PM Control Register 2.
#define | R_XHCI_MEM_USBLPM 0x8170
USB LPM Parameters.
#define | R_XHCI_MEM_XLTP_LTV1 0x8174
xHC Latency Tolerance Parameters - LTV Control
#define | B_XHCI_MEM_XLTP_LTV1_USB2_PL0_LTV 0xFFF
USB2 Port L0 LTV.
#define | R_XHCI_MEM_XHCLTVCTL2 0x8178
xHC Latency Tolerance Control 2 - LTV Control 2
#define | B_XHCI_MEM_XHCLTVCTL2_LTV_LIMIT 0x1FFF
LTV Limit field bits.
#define | R_XHCI_MEM_LTVHIT 0x817C
xHC Latency Tolerance Parameters - High Idle Time Control
#define | R_XHCI_MEM_LTVMIT 0x8180
xHC Latency Tolerance Parameters - Medium Idle Time Control
#define | R_XHCI_MEM_LTVLIT 0x8184
xHC Latency Tolerance Parameters - Low Idle Time Control
#define | R_XHCI_MEM_CFG_USB2_LTV_U2_NOREQ_REG 0x8188
ADO USB2 LTR Register.
#define | R_XHCI_MEM_D0I2CTRL 0x81BC
D0I2 Control Register.
#define | N_XHCI_MEM_D0I2CTRL_MSID0I2PWT 16
Bitshift for MSI D0i2 Pre Wake Time.
#define | R_XHCI_MEM_D0I2SCH_ALARM_CTRL 0x81C0
D0i2 Scheduler Alarm Control Register.
#define | B_XHCI_MEM_D0I2SCH_ALARM_CTRL 0x1FFF1FFF
Bitmask for D0i2 Scheduler Alarm Control Register.
#define | N_XHCI_MEM_D0I2SCH_ALARM_CTRL_D0I2IT 16
Bitshift for D0i2 Idle Time.
#define | R_XHCI_MEM_USB2PMCTRL 0x81C4
USB2 Power Management Control.
#define | R_XHCI_MEM_AUX_CTRL_REG3 0x81C8
Aux PM Control 3 Register.
#define | B_XHCI_MEM_AUX_CTRL_REG3_HYSTERESIS_TIMEOUT (BIT9 | BIT8 | BIT7)
Inaccessible Hysteresis Timer.
#define | B_XHCI_MEM_AUX_CTRL_REG3_HYST_TIMEOUT_150US BIT8
Force PG timeout 150us.
#define | R_XHCI_MEM_DBGDEV_CTRL_REG1 0x8754
Debug Device Control Register 1.
#define | R_XHCI_MEM_PMCTRL2 0x8468
PMCTRL2 - Power Management Control 2.
#define | R_XHCI_MEM_MULT_IN_SCH_POLICY 0x82A0
Multiple_in Scheduler Policy Register.
#define | R_XHCI_MEM_GRP0_SAI_WAC_POLICY_LO 0x8308
Group0 SAI Write Access Control Policy Register Low.
#define | R_XHCI_MEM_GRP0_SAI_RAC_POLICY_LO 0x8310
Group0 SAI Read Access Control Policy Low.
#define | R_XHCI_MEM_PMREQ_CTRL_REG 0x83D0
PMREQ Control Register.
#define | R_XHCI_MEM_SURVIVABILITY_REG1 0x83E8
U2U Bridge Survivability Register 1.
#define | R_XHCI_MEM_SURVIVABILITY_REG2 0x83EC
U2U Bridge Survivability Register 2.
#define | R_XHCI_MEM_HOST_CTRL_SSP_TUNNELING_REG 0x8EA0
HOST_CTRL_SSP_TUNNELING_REG.
#define | R_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1 0x8AC8
DAP eSS Port <N> Control1 Register for TCSS CPU XHCI PORT.
#define | S_CPU_XHCI_MEM_ESS_PORT_CONTROL1_SPACING 0x10
Size of space between DAP eSS Port <N> Control1 Register for each port. Max 4 CPU XHCI Port.
#define | B_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1_RTCO BIT3
DAP eSS Port <N> Control1 Register for TCSS CPU XHCI PORT.
#define | R_PCH_XHCI_MEM_USB2PDO 0x84F8
USB2 Port Disable Override register.
#define | R_PCH_XHCI_MEM_USB3PDO 0x84FC
USB3 Port Disable Override register.
#define | R_XHCI_MEM_AUDIO_OFFLOAD_CTR 0x91F4
Audio Offload Control.
#define | R_XHCI_MEM_U2PRM_U2PRDE 0x92F4
Control bits to enable USB2 Port Reset Messaging.
#define | R_XHCI_MEM_DBC_DBCCTL 0x8760
DBCCTL - DbC Control.
#define | N_XHCI_MEM_DBC_DBCCTL_DISC_RXD_CNT 2
Soft Disconnect RX Detect Count bitshift.
#define | R_XHCI_MEM_SOCHWSTSAVE1 0x8504
SOC HW State Save 1 Register.
#define | B_XHCI_MEM_SOCHWSTSAVE1_CMD_SSV BIT31
cmd_ssv flag which indicates that context is saved or not
#define | R_XHCI_MEM_U2OCM 0x90A4
XHCI USB2 Overcurrent Pin N Mapping.
#define | R_XHCI_MEM_U3OCM 0x9124
XHCI USB3 Overcurrent Pin N Mapping.
#define | R_XHCI_PCR_DAP_COMMON_CONTROL_REG 0x440
DAP Common Control register.
#define | R_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0 0x500
DAP USB2 Port0 Control 0 Register.
#define | B_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT (BIT8 | BIT7 | BIT6 | BIT5)
Connector Event (CE) in DAP USB2 Port<N> Control 0 Register.
#define | V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_HOST 0
Host Operation State.
#define | V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DISCONNECT 0x20
Un-subscription Operation State.
#define | V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DBC 0x180
DBC Operation State.
#define | R_XHCI_PCR_DAP_USB2PORT_STATUS_0 0x508
DAP USB2 Port0 Status 0 Register.
#define | B_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)
Operation State (OS) in DAP USB2 Port<N> Status 0 Register.
#define | V_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS_DBC 0x40
DBC Operation State.
#define | R_XHCI_PCR_DAP_ESS_PORT_CONTROL1 0x604
DAP eSS Port <N> Control 1 Register.
#define | S_XHCI_PCR_DAP_ESS_PORT_CONTROL1_SPACING 0x10
Size of space between DAP eSS Port <N> Control 1 Register for each port.
#define | R_XDCI_CFG_PMCSR 0x84
Power Management Control and Status Register.
#define | R_XDCI_CFG_CPGE 0xA2
Chassis Power Gate Enable.
#define | R_XDCI_MEM_GCTL 0xC110
Xdci Global Ctrl.
#define | B_XDCI_MEM_GCTL_GHIBEREN BIT1
Hibernation enable.
#define | R_XDCI_MEM_GUSB2PHYCFG 0xC200
Global USB2 PHY Configuration Register.
#define | B_XDCI_MEM_GUSB2PHYCFG_SUSPHY BIT6
Suspend USB2.0 HS/FS/LS PHY.
#define | R_XDCI_MEM_GUSB3PIPECTL0 0xC2C0
Global USB3 PIPE Control Register 0.
#define | B_XDCI_MEM_GUSB3PIPECTL0_SUSPEN_EN BIT17
Suspend USB3.0 SS PHY (Suspend_en)
#define | R_USB2_PCR_GLOBAL_PORT 0x4001
USB2 GLOBAL PORT.
#define | R_USB2_PCR_PP_LANE_BASE_ADDR 0x4000
PP LANE base address.
#define | R_USB2_PCR_PER_PORT 0x00
USB2 PER PORT Addr[7:2] = 0x00.
#define | R_USB2_PCR_UTMI_MISC_PER_PORT 0x08
UTMI MISC REG PER PORT Addr[7:2] = 0x08.
#define | R_USB2_PCR_PER_PORT_2 0x26
USB2 PER PORT 2 Addr[7:2] = 0x26.
#define | B_USB2_PCR_PER_PORT_2_TXEMPHASISEN (BIT24 | BIT23)
HSNPREDRVSEL bits value USB2 PER PORT2 register.
#define | R_USB2_PCR_GLB_ADP_VBUS_REG 0x402B
GLB ADP VBUS REG.
#define | R_USB2_PCR_GLOBAL_PORT_2 0x402C
USB2 GLOBAL PORT 2.
#define | R_USB2_PCR_PLLDIVRATIOS_0 0x7000
PLLDIVRATIOS_0.
#define | R_USB2_PCR_CONFIG_0 0x7008
CONFIG_0.
#define | R_USB2_PCR_CONFIG_3 0x7014
CONFIG_3.
#define | R_USB2_PCR_DFT_1 0x7024
DFT_1.
#define | R_USB2_PCR_SFRCONFIG_0 0x702C
SFRCONFIG_0.
#define | R_USB2_PCR_PLL1 0x7F02
USB2 PLL1.
#define | R_USB2_PCR_CFG_COMPBG 0x7F04
USB2 COMPBG.
#define | R_USB2_PCR_SNPSPHYSIPPOL 0x00
SNPS PHY SIP POLICIES.
#define | R_USB2_PCR_SNPSPHYSIPPOL_ENCMNONNOVRL1 BIT12
Enable COMMONONN Override In L1.
#define | R_USB2_PCR_SNPSPHYSIPPOL_CLKCORETCGL1 BIT2
CLKCORE (refclk) Trunk Gating Enable on SLEEP/L1.
#define | R_XHCI_MEM_SSIC_CONF_REG2_PORT_1 0x880C
SSIC Configuration Register 2 Port 1.
#define | R_XHCI_MEM_SSIC_CONF_REG2_PORT_2 0x883C
SSIC Configuration Register 2 Port 2.

Detailed Description

Register names for USB Host and device controller.

Conventions:

  • Register definition format: Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
  • Prefix: Definitions beginning with "R_" are registers Definitions beginning with "B_" are bits within registers Definitions beginning with "V_" are meaningful values within the bits Definitions beginning with "S_" are register size Definitions beginning with "N_" are the bit position
  • [GenerationName]: Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). Register name without GenerationName applies to all generations.
  • [ComponentName]: This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) Register name without ComponentName applies to all components. Register that is specific to -H denoted by "_PCH_H_" in component name. Register that is specific to -LP denoted by "_PCH_LP_" in component name.
  • SubsystemName: This field indicates the subsystem name of the component that the register belongs to (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
  • RegisterSpace: MEM - MMIO space register of subsystem. IO - IO space register of subsystem. PCR - Private configuration register of subsystem. CFG - PCI configuration space register of subsystem.
  • RegisterName: Full register name.
Copyright
INTEL CONFIDENTIAL Copyright 1999 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file UsbRegs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): UsbRegs.h Source File

  • Intel
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UsbRegs.h
Go to the documentation of this file.
1 /** @file
2 Register names for USB Host and device controller
3
4 Conventions:
5
6 - Register definition format:
7 Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
8 - Prefix:
9 Definitions beginning with "R_" are registers
10 Definitions beginning with "B_" are bits within registers
11 Definitions beginning with "V_" are meaningful values within the bits
12 Definitions beginning with "S_" are register size
13 Definitions beginning with "N_" are the bit position
14 - [GenerationName]:
15 Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
16 Register name without GenerationName applies to all generations.
17 - [ComponentName]:
18 This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
19 Register name without ComponentName applies to all components.
20 Register that is specific to -H denoted by "_PCH_H_" in component name.
21 Register that is specific to -LP denoted by "_PCH_LP_" in component name.
22 - SubsystemName:
23 This field indicates the subsystem name of the component that the register belongs to
24 (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
25 - RegisterSpace:
26 MEM - MMIO space register of subsystem.
27 IO - IO space register of subsystem.
28 PCR - Private configuration register of subsystem.
29 CFG - PCI configuration space register of subsystem.
30 - RegisterName:
31 Full register name.
32
33 @copyright
34 INTEL CONFIDENTIAL
35 Copyright 1999 - 2021 Intel Corporation.
36
37 The source code contained or described herein and all documents related to the
38 source code ("Material") are owned by Intel Corporation or its suppliers or
39 licensors. Title to the Material remains with Intel Corporation or its suppliers
40 and licensors. The Material may contain trade secrets and proprietary and
41 confidential information of Intel Corporation and its suppliers and licensors,
42 and is protected by worldwide copyright and trade secret laws and treaty
43 provisions. No part of the Material may be used, copied, reproduced, modified,
44 published, uploaded, posted, transmitted, distributed, or disclosed in any way
45 without Intel's prior express written permission.
46
47 No license under any patent, copyright, trade secret or other intellectual
48 property right is granted to or conferred upon you by disclosure or delivery
49 of the Materials, either expressly, by implication, inducement, estoppel or
50 otherwise. Any license under such intellectual property rights must be
51 express and approved by Intel in writing.
52
53 Unless otherwise agreed by Intel in writing, you may not remove or alter
54 this notice or any other notice embedded in Materials by Intel or
55 Intel's suppliers or licensors in any way.
56
57 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
58 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
59 the terms of your license agreement with Intel or your vendor. This file may
60 be modified by the user, subject to additional terms of the license agreement.
61
62 @par Specification Reference:
63 **/
64 #ifndef _USB_REGS_H_
65 #define _USB_REGS_H_
66
67 //
68 // XHCI PCI Config Space registers
69 //
70 #define R_XHCI_CFG_BAR0 PCI_BASE_ADDRESSREG_OFFSET
71 #define B_XHCI_CFG_ALIGN_MASK 0xFFFF
72
73 #define R_XHCI_CFG_XHCC1 0x40
74 #define B_XHCI_CFG_XHCC1_ACCTRL BIT31
75 #define B_XHCI_CFG_XHCC1_URD BIT23
76 #define B_XHCI_CFG_XHCC1_URRE BIT22
77 #define R_XHCI_CFG_XHCC2 0x44
78 #define B_XHCI_CFG_XHCC2_WRREQSZCTRL (BIT24 | BIT23 | BIT22) ///< IDMA Write Request Size Control mask
79 #define N_XHCI_CFG_XHCC2_WRREQSZCTRL 22 ///< IDMA Write Request Size Control bit position
80 #define B_XHCI_CFG_XHCC2_RDREQSZCTRL (BIT2 | BIT1 | BIT0) ///< IDMA Read Request Size Control mask
81 #define B_XHCI_CFG_XHCC2_OCCFDONE BIT31
82 #define R_XHCI_CFG_XHCLKGTEN 0x50
83 #define B_XHCI_CFG_XHCLKGTEN_SSCTGE (BIT19 | BIT18 | BIT17 | BIT16)
84 #define N_XHCI_CFG_XHCLKGTEN_SSCTGE 16
85 #define R_XHCI_CFG_PWR_CNTL_STS 0x74
86 #define B_XHCI_CFG_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)
87 #define V_XHCI_CFG_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
88 #define R_XHCI_CFG_PCE 0xA2
89 #define B_XHCI_CFG_PCE_D3HE BIT2
90 #define R_XHCI_CFG_HSCFG2 0xA4
91 #define R_XHCI_CFG_SSCFG1 0xA8
92 #define R_XHCI_CFG_HSCFG1 0xAC
93 #define R_XHCI_CFG_XHCC3 0xFC ///< XHCI System Bus Configuration 3
94
95 //
96 // xHCI MMIO registers
97 //
98
99 //
100 // 0x00 - 0x1F - Capability Registers
101 //
102 #define R_XHCI_MEM_CAPLENGTH 0x00
103 #define B_XHCI_MEM_HCIVERSION 0xFFFF
104 #define V_XHCI_MEM_HCIVERSION_0120 0x0120
105 #define N_XHCI_MEM_HCIVERSION 16
106 #define R_XHCI_MEM_HCSPARAMS3 0x0C
107 #define B_XHCI_MEM_HCSPARAMS3 (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
108 #define N_XHCI_MEM_HCSPARAMS3_U2DEL 16
109 #define R_XHCI_MEM_HCCPARAMS2 0x1C
110
111 //
112 // 0x80 - 0xBF - Operational Registers
113 //
114 #define R_XHCI_MEM_PORTSC_START_OFFSET 0x480 ///< Port Status and Control Registers base offset
115 #define S_XHCI_MEM_PORTSC_PORT_SPACING 0x10 ///< Size of space between PortSC register for each port
116
117 #define B_XHCI_MEM_PORTSCXUSB2_PED BIT1 ///< Port Enable/Disabled
118 #define B_XHCI_MEM_PORTSCXUSB2_CCS BIT0 ///< Current Connect Status
119 //
120 // 0x2000 - 0x21FF - Runtime Registers
121 // 0x3000 - 0x307F - Doorbell Registers
122 //
123 #define R_XHCI_MEM_XECP_SUPP_USB2_2 0x8008
124 #define R_XHCI_MEM_XECP_SUPP_USB3_2 0x8028
125 #define B_XHCI_MEM_XECP_SUPP_USBX_2_CPC (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) ///< Mask for Compatible Port Count in Capability
126 #define N_XHCI_MEM_XECP_SUPP_USBX_2_CPC 8 ///< Shift for Compatible Port Count
127 #define R_XHCI_MEM_HOST_CTRL_SCH_REG 0x8094
128 #define R_XHCI_MEM_HOST_CTRL_ODMA_REG 0x8098 ///< Host Control ODMA Register
129 #define R_XHCI_MEM_PMCTRL 0x80A4
130 #define R_XHCI_MEM_HOST_CTRL_MISC_REG 0x80B0 ///< Host Controller Misc Reg
131 #define R_XHCI_MEM_HOST_CTRL_MISC_REG_2 0x80B4 ///< Host Controller Misc Reg 2
132 #define R_XHCI_MEM_SSPE 0x80B8 ///< Super Speed Port Enables
133 #define R_XHCI_MEM_AUX_CTRL_REG 0x80C0 ///< AUX_CTRL_REG - AUX Reset Control
134 #define R_XHCI_MEM_DUAL_ROLE_CFG0 0x80D8
135 #define R_XHCI_MEM_DUAL_ROLE_CFG1 0x80DC
136 #define R_XHCI_MEM_HOST_CTRL_PORT_LINK_REG 0x80EC ///< SuperSpeed Port Link Control
137 #define R_XHCI_MEM_HOST_IF_CTRL_REG 0x8108 ///< HOST_IF_CTRL_REG - Host Controller Interface Control Register
138 #define R_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG 0x8138 ///< USB2_PROTOCOL_GAP_TIMER_HIGH_REG - USB2 Protocol Gap Timer HIGH
139 #define B_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG_GAP_TIME_AFTER_LS_TX (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
140 #define N_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG_GAP_TIME_AFTER_LS_TX 16
141 #define R_XHCI_MEM_HOST_IF_PWR_CTRL_REG0 0x8140 ///< HOST_IF_PWR_CTRL_REG0 - Power Scheduler Control 0
142 #define R_XHCI_MEM_HOST_IF_PWR_CTRL_REG1 0x8144 ///< HOST_IF_PWR_CTRL_REG1 - Power Scheduler Control 1
143 #define R_XHCI_MEM_AUX_CTRL_REG2 0x8154 ///< AUX_CTRL_REG2 - Aux PM Control Register 2
144 #define R_XHCI_MEM_USBLPM 0x8170 ///< USB LPM Parameters
145 #define R_XHCI_MEM_XLTP_LTV1 0x8174 ///< xHC Latency Tolerance Parameters - LTV Control
146 #define B_XHCI_MEM_XLTP_LTV1_USB2_PL0_LTV 0xFFF ///< USB2 Port L0 LTV
147 #define R_XHCI_MEM_XHCLTVCTL2 0x8178 ///< xHC Latency Tolerance Control 2 - LTV Control 2
148 #define B_XHCI_MEM_XHCLTVCTL2_LTV_LIMIT 0x1FFF ///< LTV Limit field bits
149 #define R_XHCI_MEM_LTVHIT 0x817C ///< xHC Latency Tolerance Parameters - High Idle Time Control
150 #define R_XHCI_MEM_LTVMIT 0x8180 ///< xHC Latency Tolerance Parameters - Medium Idle Time Control
151 #define R_XHCI_MEM_LTVLIT 0x8184 ///< xHC Latency Tolerance Parameters - Low Idle Time Control
152 #define R_XHCI_MEM_CFG_USB2_LTV_U2_NOREQ_REG 0x8188 ///< ADO USB2 LTR Register
153 #define R_XHCI_MEM_D0I2CTRL 0x81BC ///< D0I2 Control Register
154 #define N_XHCI_MEM_D0I2CTRL_MSID0I2PWT 16 ///< Bitshift for MSI D0i2 Pre Wake Time
155 #define R_XHCI_MEM_D0I2SCH_ALARM_CTRL 0x81C0 ///< D0i2 Scheduler Alarm Control Register
156 #define B_XHCI_MEM_D0I2SCH_ALARM_CTRL 0x1FFF1FFF ///< Bitmask for D0i2 Scheduler Alarm Control Register
157 #define N_XHCI_MEM_D0I2SCH_ALARM_CTRL_D0I2IT 16 ///< Bitshift for D0i2 Idle Time
158 #define R_XHCI_MEM_USB2PMCTRL 0x81C4 ///< USB2 Power Management Control
159 #define R_XHCI_MEM_AUX_CTRL_REG3 0x81C8 ///< Aux PM Control 3 Register
160 #define B_XHCI_MEM_AUX_CTRL_REG3_HYSTERESIS_TIMEOUT (BIT9 | BIT8 | BIT7) ///< Inaccessible Hysteresis Timer
161 #define B_XHCI_MEM_AUX_CTRL_REG3_HYST_TIMEOUT_150US BIT8 ///< Force PG timeout 150us
162
163 #define R_XHCI_MEM_DBGDEV_CTRL_REG1 0x8754 ///< Debug Device Control Register 1
164
165 #define R_XHCI_MEM_PMCTRL2 0x8468 ///< PMCTRL2 - Power Management Control 2
166 #define R_XHCI_MEM_HOST_CTRL_SUS_LINK_PORT_REG 0x81F8
167 #define R_XHCI_MEM_HOST_CTRL_EARLY_DBG_REG 0x81FC
168 #define R_XHCI_MEM_MULT_IN_SCH_POLICY 0x82A0 ///< Multiple_in Scheduler Policy Register
169 #define R_XHCI_MEM_XHCI_ECN_REG 0x82FC
170 #define R_XHCI_MEM_GRP0_SAI_WAC_POLICY_LO 0x8308 ///< Group0 SAI Write Access Control Policy Register Low
171 #define R_XHCI_MEM_GRP0_SAI_RAC_POLICY_LO 0x8310 ///< Group0 SAI Read Access Control Policy Low
172 #define R_XHCI_MEM_PMREQ_CTRL_REG 0x83D0 ///< PMREQ Control Register
173 #define R_XHCI_MEM_SURVIVABILITY_REG1 0x83E8 ///< U2U Bridge Survivability Register 1
174 #define R_XHCI_MEM_SURVIVABILITY_REG2 0x83EC ///< U2U Bridge Survivability Register 2
175 #define B_XHCI_MEM_SURVIVABILITY_REG2_DRIVE_DEV_BYP_CLK_READY BIT14
176 #define R_XHCI_MEM_HOST_CTRL_SSP_LINK_REG2 0x8E68
177 #define R_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG4 0x8E7C
178 #define B_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG4_SCD_LFPS_TIMEOUT (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17)
179 #define N_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG4_SCD_LFPS_TIMEOUT 17
180 #define B_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG4_SCD_TX_COUNT (BIT16 | BIT15 | BIT14)
181 #define N_XHCI_MEM_HOST_CTRL_SSP_LFPS_REG4_SCD_TX_COUNT 14
182 #define R_XHCI_MEM_HOST_CTRL_SSP_CONFIG_REG2 0x8E9C
183 #define R_XHCI_MEM_HOST_CTRL_USB3_RECAL 0x8E84
184 #define R_XHCI_MEM_HOST_CTRL_SSP_TUNNELING_REG 0x8EA0 ///< HOST_CTRL_SSP_TUNNELING_REG
185
186 #define R_XHCI_MEM_HOST_CTRL_USB3_CP13_DEEMPH 0x8E8C
187 #define R_XHCI_MEM_HOST_CTRL_USB3_CP14_DEEMPH 0x8E90
188 #define R_XHCI_MEM_HOST_CTRL_USB3_CP15_DEEMPH 0x8E94
189 #define R_XHCI_MEM_HOST_CTRL_USB3_CP16_DEEMPH 0x8E98
190
191 //
192 // TCSS CPU XHCI DAP ESS PORT Registers in MMIO Space
193 //
194 #define R_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1 0x8AC8 ///< DAP eSS Port <N> Control1 Register for TCSS CPU XHCI PORT.
195 #define S_CPU_XHCI_MEM_ESS_PORT_CONTROL1_SPACING 0x10 ///< Size of space between DAP eSS Port <N> Control1 Register for each port. Max 4 CPU XHCI Port
196 #define B_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1_RTCO BIT3 ///< DAP eSS Port <N> Control1 Register for TCSS CPU XHCI PORT.
197
198 //
199 // Extended Capability Registers
200 //
201 #define R_PCH_XHCI_MEM_USB2PDO 0x84F8 ///< USB2 Port Disable Override register
202 #define R_PCH_XHCI_MEM_USB3PDO 0x84FC ///< USB3 Port Disable Override register
203
204 //
205 // USB Audio Offload registers
206 //
207 #define R_XHCI_MEM_AUDIO_OFFLOAD_CTR 0x91F4 ///< Audio Offload Control
208
209 //
210 // USB2 Port Reset Messaging Enable
211 //
212 #define R_XHCI_MEM_U2PRM_U2PRDE 0x92F4 ///< Control bits to enable USB2 Port Reset Messaging
213
214 //
215 // Debug Capability Descriptor Parameters
216 //
217 #define R_XHCI_MEM_DBC_DBCCTL 0x8760 ///< DBCCTL - DbC Control
218 #define N_XHCI_MEM_DBC_DBCCTL_DISC_RXD_CNT 2 ///< Soft Disconnect RX Detect Count bitshift
219
220 #define R_XHCI_MEM_SOCHWSTSAVE1 0x8504 ///< SOC HW State Save 1 Register
221 #define B_XHCI_MEM_SOCHWSTSAVE1_CMD_SSV BIT31 ///< cmd_ssv flag which indicates that context is saved or not
222
223 //
224 // Over Current Mapping registers
225 //
226 #define R_XHCI_MEM_U2OCM 0x90A4 ///< XHCI USB2 Overcurrent Pin N Mapping
227 #define R_XHCI_MEM_U3OCM 0x9124 ///< XHCI USB3 Overcurrent Pin N Mapping
228
229 #define R_XHCI_MEM_HOST_CTRL_USB3_PORT_CONFIG2 0x9470
230 #define B_XHCI_MEM_HOST_CTRL_USB3_PORT_CONFIG2_USB3_PROG_DONE BIT0
231
232 //
233 // xHCI Private registers
234 //
235 #define R_XHCI_PCR_DAP_COMMON_CONTROL_REG 0x440 ///< DAP Common Control register
236 #define R_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0 0x500 ///< DAP USB2 Port0 Control 0 Register
237 #define B_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT (BIT8 | BIT7 | BIT6 | BIT5) ///< Connector Event (CE) in DAP USB2 Port<N> Control 0 Register
238 #define V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_HOST 0 ///< Host Operation State
239 #define V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DISCONNECT 0x20 ///< Un-subscription Operation State
240 #define V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DBC 0x180 ///< DBC Operation State
241 #define R_XHCI_PCR_DAP_USB2PORT_STATUS_0 0x508 ///< DAP USB2 Port0 Status 0 Register
242 #define B_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0) ///< Operation State (OS) in DAP USB2 Port<N> Status 0 Register
243 #define V_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS_DBC 0x40 ///< DBC Operation State
244 #define R_XHCI_PCR_DAP_ESS_PORT_CONTROL1 0x604 ///< DAP eSS Port <N> Control 1 Register
245 #define S_XHCI_PCR_DAP_ESS_PORT_CONTROL1_SPACING 0x10 ///< Size of space between DAP eSS Port <N> Control 1 Register for each port
246
247 //
248 // xDCI (OTG) PCI Config Space Registers
249 //
250 #define R_XDCI_CFG_PMCSR 0x84 ///< Power Management Control and Status Register
251 #define R_XDCI_CFG_CPGE 0xA2 ///< Chassis Power Gate Enable
252
253 //
254 // xDCI (OTG) MMIO registers
255 //
256 #define R_XDCI_MEM_GCTL 0xC110 ///< Xdci Global Ctrl
257 #define B_XDCI_MEM_GCTL_GHIBEREN BIT1 ///< Hibernation enable
258 #define R_XDCI_MEM_GUSB2PHYCFG 0xC200 ///< Global USB2 PHY Configuration Register
259 #define B_XDCI_MEM_GUSB2PHYCFG_SUSPHY BIT6 ///< Suspend USB2.0 HS/FS/LS PHY
260 #define R_XDCI_MEM_GUSB3PIPECTL0 0xC2C0 ///< Global USB3 PIPE Control Register 0
261 #define B_XDCI_MEM_GUSB3PIPECTL0_SUSPEN_EN BIT17 ///< Suspend USB3.0 SS PHY (Suspend_en)
262 #define R_XDCI_MEM_APBFC_U3PMU_CFG2 0x10F810
263 #define R_XDCI_MEM_APBFC_U3PMU_CFG4 0x10F818
264 #define R_XDCI_MEM_APBFC_U3PMU_CFG5 0x10F81C
265 #define R_XDCI_MEM_APBFC_U3PMU_CFG6 0x10F820
266 #define B_XDCI_MEM_APBFC_U3PMU_CFG6_RXSBCTRLEN BIT13
267 #define B_XDCI_MEM_APBFC_U3PMU_CFG6_ENLRIP2 BIT4
268
269 //
270 // xDCI (OTG) Private Configuration Registers
271 // (PID:OTG)
272 // @todo: Verify PCR vaLidity for CPU
273 //
274 #define R_OTG_PCR_IOSF_PMCTL 0x1D0
275 #define R_OTG_PCR_PCICFGCTRL1 0x200
276 #define B_OTG_PCR_PCICFGCTRL_PCI_IRQ (BIT27 | BIT26 | BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT20)
277 #define N_OTG_PCR_PCICFGCTRL_PCI_IRQ 20
278 #define B_OTG_PCR_PCICFGCTRL_ACPI_IRQ (BIT19 | BIT18 | BIT17 | BIT16 | BIT15 | BIT14 | BIT13 | BIT12)
279 #define N_OTG_PCR_PCICFGCTRL_ACPI_IRQ 12
280 #define B_OTG_PCR_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 | BIT8)
281 #define N_OTG_PCR_PCICFGCTRL_INT_PIN 8
282 #define B_OTG_PCR_PCICFGCTRL_ACPI_INT_EN BIT1
283
284 //
285 // USB2 Private Configuration Registers
286 // USB2 HIP design featured
287 // (PID:USB2)
288 // Doesn't apply to CPU (only USB3 functionality present)
289 //
290 #define R_USB2_PCR_GLOBAL_PORT 0x4001 ///< USB2 GLOBAL PORT
291 #define R_USB2_PCR_PP_LANE_BASE_ADDR 0x4000 ///< PP LANE base address
292 #define R_USB2_PCR_PER_PORT 0x00 ///< USB2 PER PORT Addr[7:2] = 0x00
293 #define B_USB2_PCR_PER_PORT_PERPORTRXISET (BIT19 | BIT18 | BIT17)
294 #define N_USB2_PCR_PER_PORT_PERPORTRXISET 17
295 #define B_USB2_PCR_PER_PORT_PERPORTTXPEHALF BIT14
296 #define N_USB2_PCR_PER_PORT_PERPORTTXPEHALF 14
297 #define B_USB2_PCR_PER_PORT_PERPORTPETXISET (BIT13 | BIT12 | BIT11)
298 #define N_USB2_PCR_PER_PORT_PERPORTPETXISET 11
299 #define B_USB2_PCR_PER_PORT_PERPORTTXISET (BIT10 | BIT9 | BIT8)
300 #define N_USB2_PCR_PER_PORT_PERPORTTXISET 8
301 #define R_USB2_PCR_UTMI_MISC_PER_PORT 0x08 ///< UTMI MISC REG PER PORT Addr[7:2] = 0x08
302 #define R_USB2_PCR_PER_PORT_2 0x26 ///< USB2 PER PORT 2 Addr[7:2] = 0x26
303 #define B_USB2_PCR_PER_PORT_2_TXEMPHASISEN (BIT24 | BIT23) ///< HSNPREDRVSEL bits value USB2 PER PORT2 register
304 #define N_USB2_PCR_PER_PORT_2_TXEMPHASISEN 23
305 #define R_USB2_PCR_GLB_ADP_VBUS_REG 0x402B ///< GLB ADP VBUS REG
306 #define R_USB2_PCR_GLOBAL_PORT_2 0x402C ///< USB2 GLOBAL PORT 2
307 #define R_USB2_PCR_PLLDIVRATIOS_0 0x7000 ///< PLLDIVRATIOS_0
308 #define B_USB2_PCR_PLLDIVRATIOS_0_FBDIVRATIO (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
309 #define N_USB2_PCR_PLLDIVRATIOS_0_FBDIVRATIO 24
310 #define R_USB2_PCR_CONFIG_0 0x7008 ///< CONFIG_0
311 #define B_USB2_PCR_CONFIG_0_INT_COEFF (BIT17 | BIT16 | BIT15 | BIT14 | BIT13)
312 #define N_USB2_PCR_CONFIG_0_INT_COEFF 13
313 #define B_USB2_PCR_CONFIG_0_PROP_COEFF (BIT12 | BIT11 | BIT10 | BIT9)
314 #define N_USB2_PCR_CONFIG_0_PROP_COEFF 9
315 #define R_USB2_PCR_CONFIG_3 0x7014 ///< CONFIG_3
316 #define B_USB2_PCR_CONFIG_3_SFRCALIB_FMINCNT (BIT31 | BIT30 | BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24)
317 #define N_USB2_PCR_CONFIG_3_SFRCALIB_FMINCNT 24
318 #define B_USB2_PCR_CONFIG_3_SFRCALIB_FMAXCNT (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16)
319 #define N_USB2_PCR_CONFIG_3_SFRCALIB_FMAXCNT 16
320 #define B_USB2_PCR_CONFIG_3_TDCCALIB_OSCCNT (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)
321 #define N_USB2_PCR_CONFIG_3_TDCCALIB_OSCCNT 8
322 #define B_USB2_PCR_CONFIG_3_LOCKTIMERCNT_TH (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1)
323 #define N_USB2_PCR_CONFIG_3_LOCKTIMERCNT_TH 1
324 #define R_USB2_PCR_DFT_1 0x7024 ///< DFT_1
325 #define B_USB2_PCR_DFT_1_KPSCALE (BIT16 | BIT15)
326 #define N_USB2_PCR_DFT_1_KPSCALE 15
327 #define B_USB2_PCR_DFT_1_KISCALE (BIT14 | BIT13)
328 #define N_USB2_PCR_DFT_1_KISCALE 13
329 #define R_USB2_PCR_SFRCONFIG_0 0x702C ///< SFRCONFIG_0
330 #define B_USB2_PCR_SFRCONFIG_0_SFRTIMER_COEF (BIT7 | BIT6 | BIT5 | BIT4)
331 #define N_USB2_PCR_SFRCONFIG_0_SFRTIMER_COEF 4
332 #define R_USB2_PCR_PLL1 0x7F02 ///< USB2 PLL1
333 #define R_USB2_PCR_CFG_COMPBG 0x7F04 ///< USB2 COMPBG
334
335 //
336 // External USB2 PHY private registers
337 //
338 #define R_USB2_PCR_SNPSPHYSIPPOL 0x00 ///< SNPS PHY SIP POLICIES
339 #define R_USB2_PCR_SNPSPHYSIPPOL_ENCMNONNOVRL1 BIT12 ///< Enable COMMONONN Override In L1
340 #define R_USB2_PCR_SNPSPHYSIPPOL_CLKCORETCGL1 BIT2 ///< CLKCORE (refclk) Trunk Gating Enable on SLEEP/L1
341
342 //
343 // xHCI SSIC registers
344 //
345 #define R_XHCI_MEM_SSIC_CONF_REG2_PORT_1 0x880C ///< SSIC Configuration Register 2 Port 1
346 #define R_XHCI_MEM_SSIC_CONF_REG2_PORT_2 0x883C ///< SSIC Configuration Register 2 Port 2
347 #define B_XHCI_MEM_SSIC_CONF_REG2_PORT_UNUSED BIT31
348 #define B_XHCI_MEM_SSIC_CONF_REG2_PROG_DONE BIT30
349
350 //
351 // xHCI DCI MMIO Registers
352 //
353 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_PAYLOAD_BP_LOW 0x50
354 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_PAYLOAD_BP_HIGH 0x54
355 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_PAYLOAD_QUALIFIERS 0x58
356 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_STATUS_BP_LOW 0x60
357 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_STATUS_BP_HIGH 0x64
358 #define R_XHCI_PCR_DCI_DBC_TRACE_IN_STATUS_QUALIFIERS 0x68
359 #define V_XHCI_PCR_DCI_DBC_TRACE_QUALIFIERS 0x22B800
360
361 #endif // _USB_REGS_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VmdInfoHob.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
VmdInfoHob.h File Reference

This file contains information about VMD assigned devices. More...

#include <Library/VmdInfoLib.h>
Include dependency graph for VmdInfoHob.h:

Go to the source code of this file.

Classes

struct PORT_INFO
PCIe device detection information. More...

Detailed Description

This file contains information about VMD assigned devices.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VmdInfoHob.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VmdInfoHob.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
VmdInfoHob.h
Go to the documentation of this file.
1 /** @file
2 This file contains information about VMD assigned devices.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VMD_INFO_HOB_H_
36 #define _VMD_INFO_HOB_H_
37
38 #include <Library/VmdInfoLib.h>
39
40 extern EFI_GUID gVmdInfoHobGuid;
41
42 #pragma pack (1)
43
44 /**
45 PCIe device detection information.
46 This information will be used to display BIOS setup option to users.
47 **/
48
49 typedef struct {
50 UINT8 DeviceDetected;
51 UINT32 DevId;
52 UINT8 RpBus;
53 UINT8 RpDev;
54 UINT8 RpFunc;
55 UINT8 PortEn;
56 UINT8 RpIndex;
57 UINT8 Reserved[2];
58 } PORT_INFO;
59
60 //
61 // VMD Port Info
62 //
63 typedef struct {
64 PORT_INFO PortInfo[VMD_MAX_DEVICES];
65 } VMD_PORT_INFO;
66
67 //
68 // VMD Info Hob
69 //
70 typedef struct {
71 EFI_HOB_GUID_TYPE EfiHobGuidType;
72 VMD_PORT_INFO VmdPortInfo;
73 } VMD_INFO_HOB;
74
75 #pragma pack ()
76
77
78 #endif
PORT_INFO
PCIe device detection information.
Definition: VmdInfoHob.h:49
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VmdPeiConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Classes
VmdPeiConfig.h File Reference

VMD PEI policy. More...

#include <ConfigBlock.h>
#include <Library/VmdInfoLib.h>
Include dependency graph for VmdPeiConfig.h:

Go to the source code of this file.

Classes

struct VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI. More...

Detailed Description

VMD PEI policy.

Copyright
INTEL CONFIDENTIAL Copyright 2017 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VmdPeiConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VmdPeiConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
VmdPeiConfig.h
Go to the documentation of this file.
1 /** @file
2 VMD PEI policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2017 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VMD_PEI_CONFIG_H_
36 #define _VMD_PEI_CONFIG_H_
37
38 #include <ConfigBlock.h>
39 #include <Library/VmdInfoLib.h>
40
41 #define VMD_PEI_CONFIG_REVISION 4
42
43 #pragma pack (push,1)
44
45
46 typedef struct {
47 UINT8 RpBus;
48 UINT8 RpDevice;
49 UINT8 RpFunction;
50 UINT8 RpEnable;
51 } RP_BDF_DATA;
52
53 /**
54 This configuration block is to configure VMD related variables used in PostMem PEI.
55 If VMD Device is not supported, all policies can be ignored.
56 <b>Revision 1</b>:
57 - Initial version.
58 <b>Revision 2</b>:
59 - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
60 - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
61 (Added B/D/F fields along with Port Enable for up to max 31 devices).
62 <b>Revision 3</b>:
63 Added policy to get the Bar values from platform PCD.
64 <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
65 **/
66
67 typedef struct {
68 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
69 UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
70 UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
71 UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
72 UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
73 UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
74 UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
75 UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
76 UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
77 UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
78 UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
79 UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
80 UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
81 RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
82 VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
83 UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
84 UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
85 UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
86 } VMD_PEI_CONFIG;
87
88 #pragma pack (pop)
89
90 #endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
VMD_PEI_CONFIG::VmdMemBar1Base
UINT32 VmdMemBar1Base
Temp Address VMD CFG BAR Default is 0xA0000000
Definition: VmdPeiConfig.h:84
VMD_PEI_CONFIG::VmdMemBarSize2
UINT8 VmdMemBarSize2
Offset 37 This is used to set the VMD Mem Bar2 size. 20(1MB).
Definition: VmdPeiConfig.h:78
ConfigBlock.h
Header file for Config Block Lib implementation.
VMD_PEI_CONFIG::VmdPortCEnable
UINT8 VmdPortCEnable
Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:72
VMD_PEI_CONFIG::VmdCfgBarAttr
UINT8 VmdCfgBarAttr
Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFET...
Definition: VmdPeiConfig.h:75
VMD_PEI_CONFIG::VmdMemBar1Attr
UINT8 VmdMemBar1Attr
Offset 36 This is used to set VMD Mem Bar1 Attributes 0: VMD_32BIT_NONPREFETCH(Default) 1: VMD_64BIT...
Definition: VmdPeiConfig.h:77
VMD_PEI_CONFIG::VmdPortDEnable
UINT8 VmdPortDEnable
Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:73
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
VMD_PEI_CONFIG::VmdEnable
UINT8 VmdEnable
Offset 28 This field used to enable VMD controller 1=Enable 0=Disable(default)
Definition: VmdPeiConfig.h:69
VMD_PEI_CONFIG::VmdGlobalMapping
UINT8 VmdGlobalMapping
Offset 39 This field used to enable Global Mapping 1=Enable 0=Disable(default)
Definition: VmdPeiConfig.h:80
VMD_PEI_CONFIG::VmdCfgBarBase
UINT32 VmdCfgBarBase
This config block will be updated as per the EFI variable.
Definition: VmdPeiConfig.h:83
VMD_PEI_CONFIG::VmdPortBEnable
UINT8 VmdPortBEnable
Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:71
VMD_PEI_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VmdPeiConfig.h:68
VMD_PEI_CONFIG
This configuration block is to configure VMD related variables used in PostMem PEI.
Definition: VmdPeiConfig.h:67
VMD_PEI_CONFIG::VmdMemBarSize1
UINT8 VmdMemBarSize1
Offset 35 This is used to set the VMD Mem Bar1 size. 25 (32MB).
Definition: VmdPeiConfig.h:76
VMD_PEI_CONFIG::VmdMemBar2Attr
UINT8 VmdMemBar2Attr
Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH 1: VMD_64BIT_NONPREFET...
Definition: VmdPeiConfig.h:79
VMD_PEI_CONFIG::VmdMemBar2Base
UINT32 VmdMemBar2Base
Temp Address VMD CFG BAR Default is 0xA2000000
Definition: VmdPeiConfig.h:85
VMD_PEI_CONFIG::VmdCfgBarSize
UINT8 VmdCfgBarSize
Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
Definition: VmdPeiConfig.h:74
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VoltageRegulatorCommands.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Macros
VoltageRegulatorCommands.h File Reference

Header file containing Voltage Regulator initialization common definitions. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | AC_DC_LOADLINE_MAX 6249
62.49 mOhm max
#define | CLOCK_FREQUENCY_19MHz 19200000
RFI Definitions.

Detailed Description

Header file containing Voltage Regulator initialization common definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2019 -2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VoltageRegulatorCommands.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VoltageRegulatorCommands.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
VoltageRegulatorCommands.h
Go to the documentation of this file.
1 /** @file
2 Header file containing Voltage Regulator initialization common definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2019 -2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_VR_COMMON_H_
36 #define _PEI_VR_COMMON_H_
37
38 #define MIN_VR_INDEX 0x0
39 #define MAX_VR_INDEX 0x5
40
41 //
42 // VR mailbox commands
43 //
44 #define MAILBOX_VR_CMD_VR_INTERFACE 0x04
45 #define MAILBOX_VR_CMD_SVID_COMMAND_GET_REG 0x07
46
47 #define MAILBOX_VR_CMD_READ_ACOUSTIC_MITIGATION_RANGE 0x07
48 #define MAILBOX_VR_CMD_WRITE_ACOUSTIC_MITIGATION_RANGE 0x08
49 #define MAILBOX_VR_CMD_READ_VR_TDC_CONFIG 0x19
50 #define MAILBOX_VR_CMD_WRITE_VR_TDC_CONFIG 0x1A
51
52 //
53 // MAILBOX_VR_CMD_SVID_VR_HANDLER command set.
54 //
55 #define MAILBOX_VR_CMD_SVID_VR_HANDLER 0x18
56 #define MAILBOX_VR_SUBCMD_SVID_GET_STRAP_CONFIGURATION 0x00
57 #define MAILBOX_VR_SUBCMD_SVID_GET_ACDC_LOADLINE 0x01
58 #define MAILBOX_VR_SUBCMD_SVID_SET_ACDC_LOADLINE 0x02
59 #define MAILBOX_VR_SUBCMD_SVID_SET_PS_CUTOFF 0x03
60 #define MAILBOX_VR_SUBCMD_SVID_SET_IMON_CONFIG 0x04
61 #define MAILBOX_VR_SUBCMD_SVID_GET_MAX_ICC 0x05
62 #define MAILBOX_VR_SUBCMD_SVID_SET_MAX_ICC 0x06
63 #define MAILBOX_VR_SUBCMD_SVID_GET_VOLTAGE_LIMIT 0x07
64 #define MAILBOX_VR_SUBCMD_SVID_SET_VOLTAGE_LIMIT 0x08
65 #define MAILBOX_VR_SUBCMD_SVID_SET_PMON_CONFIG 0x09
66 #define MAILBOX_VR_SUBCMD_SVID_GET_PMON_PMAX 0x0A
67 #define MAILBOX_VR_SUBCMD_SVID_SET_PMON_PMAX 0x0B
68 #define MAILBOX_VR_SUBCMD_SVID_SET_VR_SLEW_RATE 0x0C
69 #define MAILBOX_VR_SUBCMD_SVID_SET_DISABLE_FAST_PKGC_RAMP 0x0D
70 #define MAILBOX_VR_SUBCMD_SVID_SET_PSYS_PS4_DISABLE 0x0E
71 #define MAILBOX_VR_SUBCMD_SVID_GET_PSYS_PS4_DISABLE 0x0F
72 #define MAILBOX_VR_SUBCMD_SVID_GET_PSYS_REGISTER 0x10
73 #define MAILBOX_VR_SUBCMD_SVID_SET_PSYS_REGISTER 0x11
74 #define MAILBOX_VR_SUBCMD_SVID_EXCLUSIVE_MODE 0x12
75 #define MAILBOX_VR_SUBCMD_SVID_GET_PS_CUTOFF 0x13
76 #define MAILBOX_VR_SUBCMD_SVID_GET_IMON_CONFIG 0x14
77 #define MAILBOX_VR_SUBCMD_SVID_READ_REG_WHITELIST 0x15
78 #define MAILBOX_VR_SUBCMD_SVID_WRITE_REG_WHITELIST 0x16
79 #define MAILBOX_VR_SUBCMD_SVID_SET_VCCINAUX_IMON_IMAX 0x17
80 #define MAILBOX_VR_SUBCMD_SVID_GET_VCCINAUX_IMON_IMAX 0x18
81 #define MAILBOX_VR_SUBCMD_SVID_GET_PMON_CONFIG 0x19
82 #define MAILBOX_VR_SUBCMD_SVID_SET_VCCINAUX_IMON_CONFIG 0x1A
83 #define MAILBOX_VR_SUBCMD_SVID_GET_VCCINAUX_IMON_CONFIG 0x1B
84 #define MAILBOX_VR_SUBCMD_SVID_GET_VR_SLEW_RATE 0x1C
85
86 #define MAILBOX_VR_SUBCMD_SVID_SET_VR 0x11
87 #define MAILBOX_VR_SUBCMD_SVID_SET_PSYS_VR 0xD
88 #define MAILBOX_VR_SUBCMD_SVID_SET_VR_VSYS_MODE 0x34
89 #define MAILBOX_VR_SUBCMD_SVID_SET_VR_CRIT_THRESHOLD 0x4A
90 #define MAILBOX_VR_SUBCMD_SVID_SET_VR_CONFIG2 0x4F
91 #define MAILBOX_VR_SUBCMD_SVID_SET_VR_CONFIG1 0x49
92
93 #define MAILBOX_VR_SUBCMD_SVID_SET_PS1_PS0_DYNAMIC_CUTOFF 0x20
94 #define MAILBOX_VR_SUBCMD_SVID_SET_PS2_PS1_DYNAMIC_CUTOFF 0x21
95 #define MAILBOX_VR_SUBCMD_SVID_GET_PS1_PS0_DYNAMIC_CUTOFF 0x22
96 #define MAILBOX_VR_SUBCMD_SVID_GET_PS2_PS1_DYNAMIC_CUTOFF 0x23
97 #define MAILBOX_VR_SUBCMD_SVID_SET_QUIESCENT_POWER_AND_PLATFORM_CAP 0x1E
98 #define MAILBOX_VR_SUBCMD_SVID_GET_QUIESCENT_POWER_AND_PLATFORM_CAP 0x1F
99 #define MAILBOX_VR_SUBCMD_SVID_GET_FAST_VMODE_ICC_LIMIT 0x24
100 #define MAILBOX_VR_SUBCMD_SVID_SET_FAST_VMODE_ICC_LIMIT 0x25
101
102 #define MAILBOX_PCODE_CMD_READ_SOFT_STRAPS 0x1F
103 #define CPU_SOFTSTRAP_SET1_HIGH 1
104 #define CPU_SOFTSTRAP_SET2_LOW 2
105 #define CPU_SOFTSTRAP_SET2_HIGH 3
106 #define STRAP_RAW_VALUE 0
107 #define STRAP_RESOLVED_VALUE 1
108
109 //
110 // VR mailbox commands for Acoustic Noise Mitigation
111 //
112 #define NOISE_MIGITATION_RANGE_MASK 0xFF
113 #define RAMP_UP_OFFSET 8
114 #define RAMP_DOWN_OFFSET 16
115
116 #define VR_ADDRESS_MASK 0xF
117 #define AC_LOADLINE_MASK 0xFFFF
118 #define DC_LOADLINE_MASK 0xFFFF0000
119 #define VR_TDC_ADDRESS_OFFSET 8
120 #define DC_LOADLINE_OFFSET 16
121 #define AC_DC_LOADLINE_MAX 6249 ///< 62.49 mOhm max
122 #define PSI_THRESHOLD_MASK 0x3FF
123 #define PSI2_THRESHOLD_OFFSET_MASK 0xFFC00
124 #define PSI3_THRESHOLD_OFFSET_MASK 0x3FF00000
125 #define PSI2_THRESHOLD_OFFSET 10
126 #define PSI3_THRESHOLD_OFFSET 20
127 #define PSI3_ENABLE_OFFSET 30
128 #define PSI4_ENABLE_OFFSET 31
129 #define VR_IMON_SLOPE_OFFSET 16
130 #define VR_IMON_SLOPE_MASK 0xFFFF0000
131 #define VR_IMON_OFFSET_MASK 0xFFFF
132 #define VR_VOLTAGE_LIMIT_MASK 0xFFFF
133 #define VR_PSYS_SLOPE_OFFSET 16
134 #define VR_PSYS_OFFSET_MASK 0xFFFF
135 #define VR_TDC_CURRENT_LIMIT_MASK 0x7FFF
136 #define VR_TDC_TIME_WINDOW_MASK 0x7F
137 #define VR_TDC_TIME_WINDOW_LOCATION_MASK 0xFE0000
138 #define VR_TDC_ENABLE_OFFSET 15
139 #define VR_TDC_TIME_WINDOW_OFFSET 17
140 #define VR_TDC_IRMS_OFFSET 30
141 #define VR_TDC_LOCK_OFFSET 31
142 #define VR_TDC_TIME_WINDOW_MAX 10
143
144 ///
145 /// RFI Definitions
146 ///
147 #define CLOCK_FREQUENCY_19MHz 19200000
148 #define CLOCK_FREQUENCY_24MHz 24000000
149 #define CLOCK_FREQUENCY_38MHz 38400000
150
151 #define R_EMI_CONTROL_0_0_0_MCHBAR_PCU 0x5A08
152 #define B_SPREAD_SPECTRUM_ENABLE BIT8
153 #define B_SPREAD_SPECTRUM_MASK 0xFF
154 #define V_SPREAD_SPECTRUM_POINT_ONE_ENCODING_MAX 0x1C
155 #define V_FIVR_SPREAD_SPECTRUM_MAX 0x3F
156
157 //24MHz XTAL Clock Frequency
158 #define R_RFI_CONTROL_0_0_0_MCHBAR_PCU 0x5A0C
159 #define N_RFI_FREQ_LO_PF2_OFFSET 2
160 #define N_RFI_FREQ_HI_PF2_OFFSET 16
161 #define B_RFI_FREQ_PF2_MASK (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT3 | BIT2)
162
163 //38.4MHx XTAL Clock Frequency
164 #define R_RFI_CONTROL2_0_0_0_MCHBAR_PCU 0x5A18
165 #define N_RFI_FREQ_LO_PF3_OFFSET 11
166 #define N_RFI_FREQ_HI_PF3_OFFSET 16
167 #define B_RFI_FREQ_PF3_MASK (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT13 | BIT12 | BIT11)
168 #define N_RFI_FREQ_LO_PF3_OFFSET2 10
169 #define B_RFI_FREQ_PF3_MASK2 (BIT23 | BIT22 | BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16 | BIT11 | BIT10)
170
171 #define B_RFI_FREQ_ADJ_MASK 0xFF
172 #define V_RFI_FREQ_ADJ_MAX 0x7F
173 #define B_RFI_FREQ_SPREAD_MASK 0xFF00
174 #define B_RFI_FREQ_UPDATE_MASK 0xFFFF
175 #define N_RFI_FREQ_LO_PF1_OFFSET 0
176 #define N_RFI_FREQ_HI_PF1_OFFSET 8
177 #define B_RFI_FREQ_PF1_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8 | BIT1 | BIT0)
178 #define R_RFI_STATUS_0_0_0_MCHBAR_PCU 0x5A10
179 #define B_RFI_CURRENT_FREQ_MASK 0xFFF
180 #define V_MAX_RFI_VALUE 0x3FF
181
182
183 typedef union {
184 UINT32 VrInterfaceData; ///< All bit fields as a 32-bit value.
185 ///
186 /// Individual bit fields.
187 ///
188 struct {
189 UINT32 VrId : 4; ///< VR ID of the domain
190 UINT32 VrCommand : 5; ///< This field contains VR command
191 UINT32 Rsvd : 7; ///< Reserved for future use
192 UINT32 VrRegAddr : 8; ///< SVID Register Address
193 UINT32 Rsvd2 : 7; ///< Reserved for future use
194 UINT32 Lock : 1; ///< Lock bit
195 } Fields;
196 } MAILBOX_VR_INTERFACE_DATA;
197
198 #endif // _PEI_VR_COMMON_H_
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VtdConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Classes | Typedefs
VtdConfig.h File Reference

VT-d policy definitions. More...

#include <Library/VtdInfoLib.h>
Include dependency graph for VtdConfig.h:
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Classes

struct | VTD_CONFIG
The data elements should be initialized by a Platform Module. More...
struct | VTD_DXE_CONFIG
The data structure is for VT-d driver initialization in DXE
Revision 1: More...

Typedefs

typedef EFI_STATUS(* VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE_INDEX VtdEngineIndex)
Enable DMA buffer in VTd. More...

Detailed Description

VT-d policy definitions.

Copyright
INTEL CONFIDENTIAL Copyright 2014 - 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VtdConfig.h.

Typedef Documentation

◆ VTD_ENABLE_DMA_BUFFER

typedef EFI_STATUS( * VTD_ENABLE_DMA_BUFFER) (IN VTD_ENGINE_INDEX VtdEngineIndex)

Enable DMA buffer in VTd.

Parameters
[in] VtdEngineIndex VTd engine index.
Return values
EFI_SUCCESS | Enable successfully.
EFI_INVALID_PARAMETER | Input parameters are invalid.
EFI_UNSUPPORTED | VTd base is zero.
EFI_OUT_OF_RESOURCES | There is no additional space in the PPI database.

Definition at line 59 of file VtdConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VtdConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
VtdConfig.h
Go to the documentation of this file.
1 /** @file
2 VT-d policy definitions.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2014 - 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VTD_CONFIG_H_
36 #define _VTD_CONFIG_H_
37
38 #include <Library/VtdInfoLib.h>
39 #pragma pack(push, 1)
40
41 #define VTD_CONFIG_REVISION 2
42 #define VTD_DXE_CONFIG_REVISION 3
43
44 //
45 // Forward declaration for the VTd Enable DMA Buffer PPI.
46 //
47
48 /**
49 Enable DMA buffer in VTd
50
51 @param[in] VtdEngineIndex VTd engine index.
52
53 @retval EFI_SUCCESS Enable successfully.
54 @retval EFI_INVALID_PARAMETER Input parameters are invalid.
55 @retval EFI_UNSUPPORTED VTd base is zero.
56 @retval EFI_OUT_OF_RESOURCES There is no additional space in the PPI database.
57 **/
58 typedef
59 EFI_STATUS
60 (EFIAPI *VTD_ENABLE_DMA_BUFFER) (
61 IN VTD_ENGINE_INDEX VtdEngineIndex
62 );
63
64 /**
65 The data elements should be initialized by a Platform Module.
66 The data structure is for VT-d driver initialization\n
67 <b>Revision 1</b>:
68 - Initial version.
69 <b>Revision 2</b>:
70 - Added field EnableDmaBuffer.
71 **/
72 typedef struct {
73 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
74 /**
75 Offset 28:
76 VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
77 This policy is for debug purpose only.
78 If VT-D is not supported, all other policies in this config block will be ignored.
79 <b>0 = To use Vt-d</b>;
80 1 = Avoids programming Vtd bars, Vtd overrides and DMAR table.
81 **/
82 UINT8 VtdDisable;
83 UINT8 X2ApicOptOut; ///< Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
84 UINT8 DmaControlGuarantee; ///< Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=Enable/Set and <b>0=Disable/Clear</b>
85 UINT8 VtdIgdEnable; ///< Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
86 UINT8 VtdIpuEnable; ///< Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
87 UINT8 VtdIopEnable; ///< Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and <b>0=Disable/Clear</b>
88 UINT8 VtdItbtEnable; /// Deprecate
89 UINT8 PreBootDmaMask; ///< Offset 35: Convey PcdVTdPolicyPropertyMask value from EDK2 IntelSiliconPkg
90 UINT32 BaseAddress[VTD_ENGINE_NUMBER]; ///< Offset 36: This field is used to describe the base addresses for VT-d function
91 UINT32 DmaBufferSize; ///< Offset 48: Protect Memory Region (PMR) DMA buffer size
92 UINT32 Reserved; ///< Offset 52: Reserved
93 EFI_PHYSICAL_ADDRESS EnableDmaBuffer; ///< Offset 56: Pointer to EnableDmaBuffer function. Platform code provides an interface to enable DMA buffer.
94 ///< VTD_ENABLE_DMA_BUFFER is a prototype for that interface.
95 } VTD_CONFIG;
96
97 /**
98 The data structure is for VT-d driver initialization in DXE\n
99 <b>Revision 1</b>:
100 - Initial version.
101 <b>Revision 2</b>:
102 - Added TE Disable for Igd.
103 <b>Revision 3</b>:
104 - Removed TE Disable for Igd.
105 **/
106 typedef struct {
107 CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
108 UINT8 Rsvd[4];
109 } VTD_DXE_CONFIG;
110 #pragma pack(pop)
111
112 #endif // _VTD_CONFIG_H_
VTD_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VtdConfig.h:73
VTD_DXE_CONFIG
The data structure is for VT-d driver initialization in DXE Revision 1:
Definition: VtdConfig.h:106
VTD_CONFIG::DmaBufferSize
UINT32 DmaBufferSize
Offset 48: Protect Memory Region (PMR) DMA buffer size.
Definition: VtdConfig.h:91
VTD_CONFIG::Reserved
UINT32 Reserved
Offset 52: Reserved.
Definition: VtdConfig.h:92
VTD_CONFIG::VtdDisable
UINT8 VtdDisable
Offset 28: VT-D Support can be verified by reading CAP ID register as expalined in BIOS Spec.
Definition: VtdConfig.h:82
VTD_ENABLE_DMA_BUFFER
EFI_STATUS(* VTD_ENABLE_DMA_BUFFER)(IN VTD_ENGINE_INDEX VtdEngineIndex)
Enable DMA buffer in VTd.
Definition: VtdConfig.h:60
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
VTD_CONFIG
The data elements should be initialized by a Platform Module.
Definition: VtdConfig.h:72
VTD_CONFIG::DmaControlGuarantee
UINT8 DmaControlGuarantee
Offset 30: This field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table....
Definition: VtdConfig.h:84
VTD_CONFIG::X2ApicOptOut
UINT8 X2ApicOptOut
Offset 29: This field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=Enable/Set and 0=...
Definition: VtdConfig.h:83
VTD_CONFIG::VtdIopEnable
UINT8 VtdIopEnable
Offset 33: This field is used to enable the VtdIopEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:87
VTD_CONFIG::VtdIgdEnable
UINT8 VtdIgdEnable
Offset 31: This field is used to enable the VtdIgdEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:85
VTD_CONFIG::VtdIpuEnable
UINT8 VtdIpuEnable
Offset 32: This field is used to enable the VtdIpuEnable Policy. 1=Enable/Set and 0=Disable/Clear
Definition: VtdConfig.h:86
VTD_DXE_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Offset 0-27 Config Block Header.
Definition: VtdConfig.h:107
VtdInfoLib.h
Header file for VtdInfoLib.
VTD_CONFIG::PreBootDmaMask
UINT8 PreBootDmaMask
Deprecate.
Definition: VtdConfig.h:89
VTD_CONFIG::EnableDmaBuffer
EFI_PHYSICAL_ADDRESS EnableDmaBuffer
Offset 56: Pointer to EnableDmaBuffer function.
Definition: VtdConfig.h:93
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VtdInfoLib.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Functions
VtdInfoLib.h File Reference

Header file for VtdInfoLib. More...

#include <Base.h>
#include <Uefi/UefiBaseType.h>
#include <Library/HobLib.h>
#include <VtdInfo.h>
Include dependency graph for VtdInfoLib.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

UINT32 | GetVtdBaseAddress (IN UINT8 VtdEngineNumber)
Get VTD Engine Base Address from PCD values. More...
UINT32 | ReadVtdBaseAddress (IN UINT8 VtdEngineNumber)
Read VTD Engine Base Address from VTD BAR Offsets. More...
UINT8 | GetMaxVtdEngineNumber (VOID)
GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number. More...
UINT64 | GetIgdVtdOffset (VOID)
GetIgdVtdOffset: Get IGD Vtd Engine Base Address. More...
UINT64 | GetIpuVtdLowOffset (VOID)
GetIpuVtdLowOffset: Get IPU Vtd Engine Low Base Address. More...
UINT32 | GetIopVtdOffset (VOID)
GetIopVtdOffset: Get Iop Vtd Engine Base Address. More...
UINT32 | GetVtdOffset (VOID)
GetVtdOffset: Get Vtd Engine Base Address. More...

Detailed Description

Header file for VtdInfoLib.

Copyright
INTEL CONFIDENTIAL Copyright 2018 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file VtdInfoLib.h.

Function Documentation

◆ GetIgdVtdOffset()

UINT64 GetIgdVtdOffset ( VOID )

GetIgdVtdOffset: Get IGD Vtd Engine Base Address.

Return values
Vtd Engine Base Address for IGD

◆ GetIopVtdOffset()

UINT32 GetIopVtdOffset ( VOID )

GetIopVtdOffset: Get Iop Vtd Engine Base Address.

Return values
Vtd Engine Base Address for all other - PEG, USB, SATA etc

◆ GetIpuVtdLowOffset()

UINT64 GetIpuVtdLowOffset ( VOID )

GetIpuVtdLowOffset: Get IPU Vtd Engine Low Base Address.

Return values
Vtd Engine Low Base Address for IPU

◆ GetMaxVtdEngineNumber()

UINT8 GetMaxVtdEngineNumber ( VOID )

GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number.

Return values
Vtd Engine Number

◆ GetVtdBaseAddress()

UINT32 GetVtdBaseAddress ( IN UINT8 VtdEngineNumber )

Get VTD Engine Base Address from PCD values.

Parameters
[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
Return values
VTD Engine Base Address

◆ GetVtdOffset()

UINT32 GetVtdOffset ( VOID )

GetVtdOffset: Get Vtd Engine Base Address.

Return values
Vtd Engine Base Address for Gfx and Non-Gfx

◆ ReadVtdBaseAddress()

UINT32 ReadVtdBaseAddress ( IN UINT8 VtdEngineNumber )

Read VTD Engine Base Address from VTD BAR Offsets.

Parameters
[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
Return values
VTD Engine Base Address
Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VtdInfoLib.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
VtdInfoLib.h
Go to the documentation of this file.
1 /** @file
2 Header file for VtdInfoLib.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2018 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _VTD_INFO_LIB_H_
36 #define _VTD_INFO_LIB_H_
37
38 #include <Base.h>
39 #include <Uefi/UefiBaseType.h>
40 #include <Library/HobLib.h>
41 #include <VtdInfo.h>
42
43 #pragma pack(1)
44
45 /**
46 Get VTD Engine Base Address from PCD values.
47
48 @param[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
49
50 @retval VTD Engine Base Address
51 **/
52 UINT32
53 GetVtdBaseAddress (
54 IN UINT8 VtdEngineNumber
55 );
56
57 /**
58 Read VTD Engine Base Address from VTD BAR Offsets.
59
60 @param[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
61
62 @retval VTD Engine Base Address
63 **/
64 UINT32
65 ReadVtdBaseAddress (
66 IN UINT8 VtdEngineNumber
67 );
68
69 /**
70 GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number
71
72 @retval Vtd Engine Number
73 **/
74 UINT8
75 GetMaxVtdEngineNumber (
76 VOID
77 );
78
79 /**
80 GetIgdVtdOffset: Get IGD Vtd Engine Base Address
81
82 @retval Vtd Engine Base Address for IGD
83 **/
84 UINT64
85 GetIgdVtdOffset (
86 VOID
87 );
88
89 /**
90 GetIpuVtdLowOffset: Get IPU Vtd Engine Low Base Address
91
92 @retval Vtd Engine Low Base Address for IPU
93 **/
94 UINT64
95 GetIpuVtdLowOffset (
96 VOID
97 );
98
99 /**
100 GetIopVtdOffset: Get Iop Vtd Engine Base Address
101
102 @retval Vtd Engine Base Address for all other - PEG, USB, SATA etc
103 **/
104 UINT32
105 GetIopVtdOffset (
106 VOID
107 );
108
109 /**
110 GetVtdOffset: Get Vtd Engine Base Address
111
112 @retval Vtd Engine Base Address for Gfx and Non-Gfx
113 **/
114 UINT32
115 GetVtdOffset (
116 VOID
117 );
118
119 #pragma pack()
120 #endif // _VTD_INFO_LIB_H_
GetVtdOffset
UINT32 GetVtdOffset(VOID)
GetVtdOffset: Get Vtd Engine Base Address.
GetVtdBaseAddress
UINT32 GetVtdBaseAddress(IN UINT8 VtdEngineNumber)
Get VTD Engine Base Address from PCD values.
GetIpuVtdLowOffset
UINT64 GetIpuVtdLowOffset(VOID)
GetIpuVtdLowOffset: Get IPU Vtd Engine Low Base Address.
ReadVtdBaseAddress
UINT32 ReadVtdBaseAddress(IN UINT8 VtdEngineNumber)
Read VTD Engine Base Address from VTD BAR Offsets.
GetMaxVtdEngineNumber
UINT8 GetMaxVtdEngineNumber(VOID)
GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number.
GetIopVtdOffset
UINT32 GetIopVtdOffset(VOID)
GetIopVtdOffset: Get Iop Vtd Engine Base Address.
GetIgdVtdOffset
UINT64 GetIgdVtdOffset(VOID)
GetIgdVtdOffset: Get IGD Vtd Engine Base Address.
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WatchDogConfig.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Classes
WatchDogConfig.h File Reference

WatchDog policy. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers. More...

Detailed Description

WatchDog policy.

Copyright
INTEL CONFIDENTIAL Copyright 2015 - 2020 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file WatchDogConfig.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WatchDogConfig.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
WatchDogConfig.h
Go to the documentation of this file.
1 /** @file
2 WatchDog policy
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2015 - 2020 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _WATCH_DOG_CONFIG_H_
36 #define _WATCH_DOG_CONFIG_H_
37
38 #define PCH_WDT_PREMEM_CONFIG_REVISION 1
39 extern EFI_GUID gWatchDogPreMemConfigGuid;
40
41 #pragma pack (push,1)
42
43 /**
44 This policy clears status bits and disable watchdog, then lock the
45 WDT registers.
46 while WDT is designed to be disabled and locked by Policy,
47 bios should not enable WDT by WDT PPI. In such case, bios shows the
48 warning message but not disable and lock WDT register to make sure
49 WDT event trigger correctly.
50 **/
51 typedef struct {
52 CONFIG_BLOCK_HEADER Header; ///< Config Block Header
53 UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
54 UINT32 RsvdBits : 31;
55 } PCH_WDT_PREMEM_CONFIG;
56
57 #pragma pack (pop)
58
59 #endif // _WATCH_DOG_CONFIG_H_
PCH_WDT_PREMEM_CONFIG::DisableAndLock
UINT32 DisableAndLock
(Test) Set 1 to clear WDT status, then disable and lock WDT registers. 0: Disable; 1: Enable.
Definition: WatchDogConfig.h:53
_CONFIG_BLOCK_HEADER
Config Block Header.
Definition: ConfigBlock.h:30
PCH_WDT_PREMEM_CONFIG
This policy clears status bits and disable watchdog, then lock the WDT registers.
Definition: WatchDogConfig.h:51
PCH_WDT_PREMEM_CONFIG::Header
CONFIG_BLOCK_HEADER Header
Config Block Header.
Definition: WatchDogConfig.h:52
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Wdt.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Typedefs
Ppi/Wdt.h File Reference

Watchdog Timer PPI. More...

#include <Protocol/Wdt.h>
Include dependency graph for Ppi/Wdt.h:

Go to the source code of this file.

Typedefs

typedef WDT_PROTOCOL WDT_PPI
Reuse WDT_PROTOCOL definition.

Detailed Description

Watchdog Timer PPI.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Ppi/Wdt.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Wdt.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi/Wdt.h
Go to the documentation of this file.
1 /** @file
2 Watchdog Timer PPI
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _PEI_WDT_H_
36 #define _PEI_WDT_H_
37
38 #include <Protocol/Wdt.h>
39 //
40 // MRC takes a lot of time to execute in debug mode
41 //
42 #define WDT_TIMEOUT_BETWEEN_PEI_DXE 60
43
44 //
45 // Extern the GUID for PPI users.
46 //
47 extern EFI_GUID gWdtPpiGuid;
48
49 ///
50 /// Reuse WDT_PROTOCOL definition
51 ///
52 typedef WDT_PROTOCOL WDT_PPI;
53
54 #endif
Wdt.h
Watchdog Timer protocol.
_WDT_PROTOCOL
These protocols and PPI allow a platform module to perform watch dog timer operations through the Int...
Definition: Protocol/Wdt.h:130
WDT_PPI
WDT_PROTOCOL WDT_PPI
Reuse WDT_PROTOCOL definition.
Definition: Ppi/Wdt.h:52
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Wdt.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Classes | Typedefs
Protocol/Wdt.h File Reference

Watchdog Timer protocol. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct _WDT_PROTOCOL
These protocols and PPI allow a platform module to perform watch dog timer operations through the Intel PCH LPC Host Controller Interface. More...

Typedefs

typedef EFI_STATUS(* | WDT_RELOAD_AND_START) (UINT32 TimeoutValue)
Reloads WDT with new timeout value and starts it. More...
typedef UINT8(* | WDT_CHECK_STATUS) (VOID)
Returns WDT failure status. More...
typedef UINT8(* | IS_WDT_REQUIRED) (VOID)
Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application. More...
typedef UINT8(* | IS_WDT_ENABLED) (VOID)
Returns WDT enabled/disabled status. More...
typedef VOID(* | WDT_DISABLE) (VOID)
Disables WDT timer.
typedef VOID(* | WDT_ALLOW_KNOWN_RESET) (VOID)
Normally, each reboot performed while watchdog runs is considered a failure. More...

Detailed Description

Watchdog Timer protocol.

Copyright
INTEL CONFIDENTIAL Copyright 2010 - 2016 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains an 'Intel Peripheral Driver' and is uniquely identified as "Intel Reference Module" and is licensed for Intel CPUs and chipsets under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to additional terms of the license agreement.

Specification Reference:

Definition in file Protocol/Wdt.h.

Typedef Documentation

◆ IS_WDT_ENABLED

typedef UINT8( * IS_WDT_ENABLED) (VOID)

Returns WDT enabled/disabled status.

Return values
TRUE | if WDT is enabled
FALSE | if WDT is disabled

Definition at line 95 of file Protocol/Wdt.h.

◆ IS_WDT_REQUIRED

typedef UINT8( * IS_WDT_REQUIRED) (VOID)

Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.

Return values
TRUE | if WDT was requested
FALSE | if WDT was not requested

Definition at line 83 of file Protocol/Wdt.h.

◆ WDT_ALLOW_KNOWN_RESET

typedef VOID( * WDT_ALLOW_KNOWN_RESET) (VOID)

Normally, each reboot performed while watchdog runs is considered a failure.

This function allows platform to perform expected reboots with WDT running, without being interpreted as failures. In DXE phase, it is enough to call this function any time before reset. In PEI phase, between calling this function and performing reset, ReloadAndStart() must not be called.

Definition at line 118 of file Protocol/Wdt.h.

◆ WDT_CHECK_STATUS

typedef UINT8( * WDT_CHECK_STATUS) (VOID)

Returns WDT failure status.

Return values
V_PCH_OC_WDT_CTL_STATUS_FAILURE | If there was WDT expiration or unexpected reset
V_PCH_OC_WDT_CTL_STATUS_OK | Otherwise

Definition at line 70 of file Protocol/Wdt.h.

◆ WDT_RELOAD_AND_START

typedef EFI_STATUS( * WDT_RELOAD_AND_START) (UINT32 TimeoutValue)

Reloads WDT with new timeout value and starts it.

Also sets Unexpected Reset bit, which causes the next reset to be treated as watchdog expiration - unless AllowKnownReset() function was called too.

Parameters
[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
Return values
EFI_SUCCESS | if everything's OK
EFI_INVALID_PARAMETER | if TimeoutValue parameter is wrong

Definition at line 58 of file Protocol/Wdt.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Wdt.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol/Wdt.h
Go to the documentation of this file.
1 /** @file
2 Watchdog Timer protocol
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2010 - 2016 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains an 'Intel Peripheral Driver' and is uniquely identified as
29 "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
30 the terms of your license agreement with Intel or your vendor. This file may
31 be modified by the user, subject to additional terms of the license agreement.
32
33 @par Specification Reference:
34 **/
35 #ifndef _DXE_WDT_H_
36 #define _DXE_WDT_H_
37
38 //
39 // Extern the GUID for protocol users.
40 //
41 extern EFI_GUID gWdtProtocolGuid;
42 //
43 // Forward reference for ANSI C compatibility
44 //
45 typedef struct _WDT_PROTOCOL WDT_PROTOCOL;
46
47 /**
48 Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
49 causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
50 function was called too.
51
52 @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
53
54 @retval EFI_SUCCESS if everything's OK
55 @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
56 **/
57 typedef
58 EFI_STATUS
59 (EFIAPI *WDT_RELOAD_AND_START) (
60 UINT32 TimeoutValue
61 );
62
63 /**
64 Returns WDT failure status.
65
66 @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
67 @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
68 **/
69 typedef
70 UINT8
71 (EFIAPI *WDT_CHECK_STATUS) (
72 VOID
73 );
74
75 /**
76 Returns information if WDT coverage for the duration of BIOS execution
77 was requested by an OS application.
78
79 @retval TRUE if WDT was requested
80 @retval FALSE if WDT was not requested
81 **/
82 typedef
83 UINT8
84 (EFIAPI *IS_WDT_REQUIRED) (
85 VOID
86 );
87
88 /**
89 Returns WDT enabled/disabled status.
90
91 @retval TRUE if WDT is enabled
92 @retval FALSE if WDT is disabled
93 **/
94 typedef
95 UINT8
96 (EFIAPI *IS_WDT_ENABLED) (
97 VOID
98 );
99
100 /**
101 Disables WDT timer.
102 **/
103 typedef
104 VOID
105 (EFIAPI *WDT_DISABLE) (
106 VOID
107 );
108
109 /**
110 Normally, each reboot performed while watchdog runs is considered a failure.
111 This function allows platform to perform expected reboots with WDT running,
112 without being interpreted as failures.
113 In DXE phase, it is enough to call this function any time before reset.
114 In PEI phase, between calling this function and performing reset, ReloadAndStart()
115 must not be called.
116 **/
117 typedef
118 VOID
119 (EFIAPI *WDT_ALLOW_KNOWN_RESET) (
120 VOID
121 );
122
123 /**
124 These protocols and PPI allow a platform module to perform watch dog timer operations
125 through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
126 implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
127 WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
128 share the identical data structure.
129 **/
130 struct _WDT_PROTOCOL {
131 WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it.
132 WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status.
133 WDT_DISABLE Disable; ///< Disables WDT timer.
134 WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures.
135 IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
136 IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status.
137 };
138
139 #endif
IS_WDT_REQUIRED
UINT8(* IS_WDT_REQUIRED)(VOID)
Returns information if WDT coverage for the duration of BIOS execution was requested by an OS applica...
Definition: Protocol/Wdt.h:84
WDT_RELOAD_AND_START
EFI_STATUS(* WDT_RELOAD_AND_START)(UINT32 TimeoutValue)
Reloads WDT with new timeout value and starts it.
Definition: Protocol/Wdt.h:59
_WDT_PROTOCOL::AllowKnownReset
WDT_ALLOW_KNOWN_RESET AllowKnownReset
Perform expected reboots with WDT running, without being interpreted as failures.
Definition: Protocol/Wdt.h:134
_WDT_PROTOCOL::Disable
WDT_DISABLE Disable
Disables WDT timer.
Definition: Protocol/Wdt.h:133
_WDT_PROTOCOL::ReloadAndStart
WDT_RELOAD_AND_START ReloadAndStart
Reloads WDT with new timeout value and starts it.
Definition: Protocol/Wdt.h:131
IS_WDT_ENABLED
UINT8(* IS_WDT_ENABLED)(VOID)
Returns WDT enabled/disabled status.
Definition: Protocol/Wdt.h:96
_WDT_PROTOCOL::IsWdtRequired
IS_WDT_REQUIRED IsWdtRequired
Returns information if WDT coverage for the duration of BIOS execution was requested by an OS applica...
Definition: Protocol/Wdt.h:135
WDT_ALLOW_KNOWN_RESET
VOID(* WDT_ALLOW_KNOWN_RESET)(VOID)
Normally, each reboot performed while watchdog runs is considered a failure.
Definition: Protocol/Wdt.h:119
_WDT_PROTOCOL
These protocols and PPI allow a platform module to perform watch dog timer operations through the Int...
Definition: Protocol/Wdt.h:130
_WDT_PROTOCOL::IsWdtEnabled
IS_WDT_ENABLED IsWdtEnabled
Returns WDT enabled/disabled status.
Definition: Protocol/Wdt.h:136
WDT_CHECK_STATUS
UINT8(* WDT_CHECK_STATUS)(VOID)
Returns WDT failure status.
Definition: Protocol/Wdt.h:71
_WDT_PROTOCOL::CheckStatus
WDT_CHECK_STATUS CheckStatus
Returns WDT failure status.
Definition: Protocol/Wdt.h:132
WDT_DISABLE
VOID(* WDT_DISABLE)(VOID)
Disables WDT timer.
Definition: Protocol/Wdt.h:105
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WifiProfileSyncAsfMsgs.h File Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Classes
WifiProfileSyncAsfMsgs.h File Reference

Supporting functions for profile sync driver ASF communication. More...

#include "AsfMsgs.h"
Include dependency graph for WifiProfileSyncAsfMsgs.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct | ASF_PROFILE_MESSAGE_HEADER
ASF Message header with profile name char array as data. More...
struct | GET_WIFI_PROFILE_NAME_RESPONSE
Get Wifi profile name response from ASF. More...
union | GET_WIFI_PROFILE_NAME_BUFFER
ASF buffer for Wifi profile name. More...
struct | WIFI_PROFILE_DATA
Get Wifi profile data response from ASF. More...
union | GET_WIFI_PROFILE_DATA_BUFFER
ASF buffer for Wifi profile data. More...
struct | WIFI_8021X_CLIENT_CERT
Get Wifi profile specific 8021X client certificate from ASF. More...
union | GET_WIFI_CLIENT_CERT_BUFFER
ASF buffer for Wifi profile client certificate. More...
struct | WIFI_8021X_CLIENT_KEY
Get Wifi profile specific 8021X client key from ASF. More...
union | GET_WIFI_CLIENT_KEY_BUFFER
ASF buffer for Wifi profile client key. More...

Detailed Description

Supporting functions for profile sync driver ASF communication.

Copyright
INTEL CONFIDENTIAL Copyright 2021 Intel Corporation.

The source code contained or described herein and all documents related to the source code ("Material") are owned by Intel Corporation or its suppliers or licensors. Title to the Material remains with Intel Corporation or its suppliers and licensors. The Material may contain trade secrets and proprietary and confidential information of Intel Corporation and its suppliers and licensors, and is protected by worldwide copyright and trade secret laws and treaty provisions. No part of the Material may be used, copied, reproduced, modified, published, uploaded, posted, transmitted, distributed, or disclosed in any way without Intel's prior express written permission.

No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the Materials, either expressly, by implication, inducement, estoppel or otherwise. Any license under such intellectual property rights must be express and approved by Intel in writing.

Unless otherwise agreed by Intel in writing, you may not remove or alter this notice or any other notice embedded in Materials by Intel or Intel's suppliers or licensors in any way.

This file contains a 'Sample Driver' and is licensed as such under the terms of your license agreement with Intel or your vendor. This file may be modified by the user, subject to the additional terms of the license agreement.

Specification Reference:

Definition in file WifiProfileSyncAsfMsgs.h.

Generated on Wed Jan 5 2022 01:24:03 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): WifiProfileSyncAsfMsgs.h Source File

  • Intel
  • ClientOneSiliconPkg
  • Include
WifiProfileSyncAsfMsgs.h
Go to the documentation of this file.
1 /** @file
2 Supporting functions for profile sync driver ASF communication.
3
4 @copyright
5 INTEL CONFIDENTIAL
6 Copyright 2021 Intel Corporation.
7
8 The source code contained or described herein and all documents related to the
9 source code ("Material") are owned by Intel Corporation or its suppliers or
10 licensors. Title to the Material remains with Intel Corporation or its suppliers
11 and licensors. The Material may contain trade secrets and proprietary and
12 confidential information of Intel Corporation and its suppliers and licensors,
13 and is protected by worldwide copyright and trade secret laws and treaty
14 provisions. No part of the Material may be used, copied, reproduced, modified,
15 published, uploaded, posted, transmitted, distributed, or disclosed in any way
16 without Intel's prior express written permission.
17
18 No license under any patent, copyright, trade secret or other intellectual
19 property right is granted to or conferred upon you by disclosure or delivery
20 of the Materials, either expressly, by implication, inducement, estoppel or
21 otherwise. Any license under such intellectual property rights must be
22 express and approved by Intel in writing.
23
24 Unless otherwise agreed by Intel in writing, you may not remove or alter
25 this notice or any other notice embedded in Materials by Intel or
26 Intel's suppliers or licensors in any way.
27
28 This file contains a 'Sample Driver' and is licensed as such under the terms
29 of your license agreement with Intel or your vendor. This file may be modified
30 by the user, subject to the additional terms of the license agreement.
31
32 @par Specification Reference:
33 **/
34 #ifndef _WIFI_PROFILE_SYNC_ASF_MSGS_H_
35 #define _WIFI_PROFILE_SYNC_ASF_MSGS_H_
36
37 #include "AsfMsgs.h"
38
39 // Root CA index status if no root CA avaliable
40 #define ROOT_CA_NOT_AVAILABLE 0xFFFFFFFF
41
42 //
43 // AMT WiFi profile data defines
44 //
45 #define MAC_ADDR_SIZE 6
46 #define PROFILE_NAME_SIZE 33
47 #define SSID_SIZE 32
48 #define PSK_KEY_SIZE 64
49 #define USER_CRED_IDENTITY_SIZE 81
50 #define USER_CRED_DOMAIN_SIZE 129
51 #define USER_CRED_USERNAME_SIZE 129
52 #define USER_CRED_PASSWORD_SIZE 33
53 #define SERVER_CERT_NAME_SIZE 81
54 #define MAX_CLIENT_KEY_SIZE 6500
55 #define MAX_CLIENT_CERTIFICATE_SIZE 4100
56
57 #pragma pack(push, 1)
58 ///
59 /// ASF Message header with profile name char array as data
60 ///
61 typedef struct {
62 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
63 CHAR8 Data[PROFILE_NAME_SIZE]; ///< ASF Data Request
64 } ASF_PROFILE_MESSAGE_HEADER;
65
66 ///
67 /// Get Wifi profile name response from ASF
68 ///
69 typedef struct {
70 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
71 UINT32 Status; ///< ASF Response Message Status
72 CHAR8 ProfileName[PROFILE_NAME_SIZE]; ///< ASF Return WiFi Profile Name.
73 } GET_WIFI_PROFILE_NAME_RESPONSE;
74
75 ///
76 /// ASF buffer for Wifi profile name
77 ///
78 typedef union {
79 ASF_MESSAGE_HEADER Request; ///< ASF Request
80 GET_WIFI_PROFILE_NAME_RESPONSE Response; ///< ASF Response
81 } GET_WIFI_PROFILE_NAME_BUFFER;
82
83 ///
84 /// Get Wifi profile data response from ASF
85 ///
86 typedef struct {
87 UINT32 Status;
88 UINT8 MACAddress[MAC_ADDR_SIZE];
89 CHAR8 ProfileName[PROFILE_NAME_SIZE];
90 UINT8 SSIdLength;
91 CHAR8 SSId[SSID_SIZE];
92 UINT32 EncryptionMethod;
93 UINT32 AuthenticationMethod;
94 UINT8 PskKeyType;
95 UINT8 PskKeyLen;
96 UINT8 PskKey[PSK_KEY_SIZE];
97 //
98 // The following fields are related to 802.1x Authentication:
99 // (see EDKII_8021XProfile)
100 //
101 UINT32 AuthenticationProtocol_eapMethod;
102 UINT32 AuthenticationProtocolInnerMethod;
103 CHAR8 UserCredentialsRoamingIdentity[USER_CRED_IDENTITY_SIZE];
104 CHAR8 UserCredentialsDomain[USER_CRED_DOMAIN_SIZE];
105 CHAR8 UserCredentialsUsername[USER_CRED_USERNAME_SIZE];
106 CHAR8 UserCredentialsPassword[USER_CRED_PASSWORD_SIZE];
107 UINT8 UserCredentialsClientCertificateAvailable;
108 UINT32 RootCACertificateIndex;
109 CHAR8 ServerCertificateName[SERVER_CERT_NAME_SIZE];
110 UINT16 ServerCertificateNameComparison;
111 } WIFI_PROFILE_DATA;
112
113 typedef struct {
114 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
115 WIFI_PROFILE_DATA Profile; ///< ASF Return WiFi Profile Data.
116 } GET_WIFI_PROFILE_DATA_RESPONSE;
117
118 ///
119 /// ASF buffer for Wifi profile data
120 ///
121 typedef union {
122 ASF_PROFILE_MESSAGE_HEADER Request; ///< ASF Request
123 GET_WIFI_PROFILE_DATA_RESPONSE Response; ///< ASF Response
124 } GET_WIFI_PROFILE_DATA_BUFFER;
125
126 ///
127 /// Get Wifi profile specific 8021X client certificate from ASF
128 ///
129 typedef struct {
130 UINT32 Status;
131 UINT32 CertSize;
132 UINT8 Certificate[MAX_CLIENT_CERTIFICATE_SIZE];
133 } WIFI_8021X_CLIENT_CERT;
134
135 typedef struct {
136 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
137 WIFI_8021X_CLIENT_CERT Cert; ///< ASF Return WiFi Client Certificate.
138 } GET_WIFI_CLIENT_CERT_RESPONSE;
139
140 ///
141 /// ASF buffer for Wifi profile client certificate
142 ///
143 typedef union {
144 ASF_PROFILE_MESSAGE_HEADER Request; ///< ASF Request
145 GET_WIFI_CLIENT_CERT_RESPONSE Response; ///< ASF Resposne
146 } GET_WIFI_CLIENT_CERT_BUFFER;
147
148 ///
149 /// Get Wifi profile specific 8021X client key from ASF
150 ///
151 typedef struct {
152 UINT32 Status;
153 UINT32 KeySize;
154 UINT8 Key[MAX_CLIENT_KEY_SIZE];
155 } WIFI_8021X_CLIENT_KEY;
156
157 typedef struct {
158 ASF_MESSAGE_HEADER AsfHeader; ///< ASF Message Header
159 WIFI_8021X_CLIENT_KEY Key; ///< ASF Return WiFi Client Key.
160 } GET_WIFI_CLIENT_KEY_RESPONSE;
161
162 ///
163 /// ASF buffer for Wifi profile client key
164 ///
165 typedef union {
166 ASF_PROFILE_MESSAGE_HEADER Request; ///< ASF Request
167 GET_WIFI_CLIENT_KEY_RESPONSE Response; ///< ASF Response
168 } GET_WIFI_CLIENT_KEY_BUFFER;
169
170 //
171 // WiFi profile data structure recieved from ASF
172 //
173 typedef struct {
174 WIFI_PROFILE_DATA *ProfileData;
175 WIFI_8021X_CLIENT_CERT *Cert;
176 WIFI_8021X_CLIENT_KEY *Key;
177 ROOT_CA_CERTIFICATE *CaCert;
178 } WIFI_PROFILE;
179
180 #pragma pack(pop)
181
182 #endif
WIFI_8021X_CLIENT_CERT
Get Wifi profile specific 8021X client certificate from ASF.
Definition: WifiProfileSyncAsfMsgs.h:129
GET_WIFI_PROFILE_DATA_BUFFER::Request
ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
Definition: WifiProfileSyncAsfMsgs.h:122
GET_WIFI_PROFILE_NAME_BUFFER::Request
ASF_MESSAGE_HEADER Request
ASF Request.
Definition: WifiProfileSyncAsfMsgs.h:79
GET_WIFI_CLIENT_CERT_BUFFER::Response
GET_WIFI_CLIENT_CERT_RESPONSE Response
ASF Resposne.
Definition: WifiProfileSyncAsfMsgs.h:145
AsfMsgs.h
AMT/ASF Messages.
GET_WIFI_CLIENT_KEY_BUFFER
ASF buffer for Wifi profile client key.
Definition: WifiProfileSyncAsfMsgs.h:165
GET_WIFI_CLIENT_KEY_BUFFER::Response
GET_WIFI_CLIENT_KEY_RESPONSE Response
ASF Response.
Definition: WifiProfileSyncAsfMsgs.h:167
GET_WIFI_PROFILE_NAME_BUFFER::Response
GET_WIFI_PROFILE_NAME_RESPONSE Response
ASF Response.
Definition: WifiProfileSyncAsfMsgs.h:80
GET_WIFI_PROFILE_NAME_RESPONSE::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: WifiProfileSyncAsfMsgs.h:70
GET_WIFI_PROFILE_DATA_BUFFER::Response
GET_WIFI_PROFILE_DATA_RESPONSE Response
ASF Response.
Definition: WifiProfileSyncAsfMsgs.h:123
WIFI_8021X_CLIENT_KEY
Get Wifi profile specific 8021X client key from ASF.
Definition: WifiProfileSyncAsfMsgs.h:151
GET_WIFI_CLIENT_KEY_BUFFER::Request
ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
Definition: WifiProfileSyncAsfMsgs.h:166
GET_WIFI_CLIENT_CERT_BUFFER
ASF buffer for Wifi profile client certificate.
Definition: WifiProfileSyncAsfMsgs.h:143
GET_WIFI_PROFILE_NAME_RESPONSE
Get Wifi profile name response from ASF.
Definition: WifiProfileSyncAsfMsgs.h:69
ASF_MESSAGE_HEADER
Abstract ASF message header.
Definition: AsfMsgs.h:60
WIFI_PROFILE_DATA
Get Wifi profile data response from ASF.
Definition: WifiProfileSyncAsfMsgs.h:86
GET_WIFI_PROFILE_NAME_BUFFER
ASF buffer for Wifi profile name.
Definition: WifiProfileSyncAsfMsgs.h:78
ASF_PROFILE_MESSAGE_HEADER
ASF Message header with profile name char array as data.
Definition: WifiProfileSyncAsfMsgs.h:61
GET_WIFI_PROFILE_NAME_RESPONSE::Status
UINT32 Status
ASF Response Message Status.
Definition: WifiProfileSyncAsfMsgs.h:71
GET_WIFI_PROFILE_DATA_BUFFER
ASF buffer for Wifi profile data.
Definition: WifiProfileSyncAsfMsgs.h:121
GET_WIFI_CLIENT_CERT_BUFFER::Request
ASF_PROFILE_MESSAGE_HEADER Request
ASF Request.
Definition: WifiProfileSyncAsfMsgs.h:144
ASF_PROFILE_MESSAGE_HEADER::AsfHeader
ASF_MESSAGE_HEADER AsfHeader
ASF Message Header.
Definition: WifiProfileSyncAsfMsgs.h:62
Generated on Wed Jan 5 2022 01:24:01 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- a -

  • AC_DC_LOADLINE_MAX : VoltageRegulatorCommands.h
  • AddComponentConfigBlocks() : SiConfigBlockLib.h
  • AddConfigBlock() : ConfigBlockLib.h
  • AddFviEntry() : SiFviLib.h
  • AddSmbiosProcessorAndCacheTables() : SmbiosProcessorLib.h
  • ALIGN_256KB : BiosGuard.h
  • ALIGNMENT_IN_PAGES : BiosGuard.h
  • AMT_CONTROL_MODE : AmthiMsgs.h
  • AMT_ERROR_MSG_ID : AmtConfig.h
  • AMT_MEBX_STATE : AmthiMsgs.h
  • AMT_MEBX_USER_INPUT : AmthiMsgs.h
  • AMT_POLICY_PROTOCOL : AmtPolicy.h
  • AMT_POLICY_PROTOCOL_REVISION : AmtPolicy.h
  • AMT_READY_TO_BOOT_PROTOCOL_REVISION : AmtReadyToBoot.h
  • AMT_READY_TO_BOOT_PROTOCOL_SIGNAL : AmtReadyToBoot.h
  • AMT_REPORT_ERROR : AmtConfig.h
  • AMT_SAVE_MEBX_DATA : AmtSaveMebxProtocol.h
  • AMT_SAVE_MEBX_PROTOCOL_REVISION : AmtSaveMebxProtocol.h
  • AMT_STATUS : AmthiMsgs.h
  • AmtAddConfigBlocks() : PeiAmtPolicyLib.h
  • AmtCreatePolicyDefaults() : DxeAmtPolicyLib.h
  • AmtGetActiveLanInterface() : DxeAmtHeciLib.h
  • AmtGetConfigBlockTotalSize() : PeiAmtPolicyLib.h
  • AMTHI_COMMAND : AmthiMsgs.h
  • AMTHI_PROVISION_MODE : AmthiMsgs.h
  • AmtInstallPolicyProtocol() : DxeAmtPolicyLib.h
  • AmtPrintPolicyPpi() : PeiAmtPolicyLib.h
  • AmtPrintPolicyProtocol() : DxeAmtPolicyLib.h
  • AmtQueryKvm() : DxeAmtHeciLib.h
  • AmtSetActiveLanInterface() : DxeAmtHeciLib.h
  • AmtSetMacPassthrough() : DxeAmtHeciLib.h
  • APINIT_ADDR : Txt.h
  • APPID_BIN_LENGTH : JhiProtocol.h
  • APPID_STR_LENGTH : JhiProtocol.h
  • ARB_SVN_COMMIT_ALL : MkhiMsgs.h
  • AsciiChar2Hex() : DxeJhiSupportLib.h
  • AsciiHex2Char() : DxeJhiSupportLib.h
  • AsciiIsAlphabet() : DxeJhiSupportLib.h
  • AsciiIsDigit() : DxeJhiSupportLib.h
  • AsciiStr2Uuid() : DxeJhiSupportLib.h
  • AsciiStrIsUuid1() : DxeJhiSupportLib.h
  • AsciiStrIsUuid2() : DxeJhiSupportLib.h
  • AsciiToLower() : DxeJhiSupportLib.h
  • AsciiUuid2Str() : DxeJhiSupportLib.h
  • ASF_BOOT_OPTIONS_PRESENT : AsfProtocol.h
  • ASF_ENTITY_INSTANCE_UNSPECIFIED : IndustryStandardAsf.h
  • ASF_ENTITY_INTEL_AMT : IntelAsfExtensions.h
  • ASF_ENTITY_UNSPECIFIED : IndustryStandardAsf.h
  • ASF_EVENT_OFFSET_ENTITY_PRESENT : IndustryStandardAsf.h
  • ASF_EVENT_OFFSET_ONE_CLICK_RECOVERY_ERROR : IntelAsfExtensions.h
  • ASF_EVENT_OFFSET_REMOTE_SECURE_ERASE_FW_ERROR : IntelAsfExtensions.h
  • ASF_EVENT_SENSOR_TYPE_TEMPERATURE : IndustryStandardAsf.h
  • ASF_EVENT_SEVERITY_CODE_MONITOR : IndustryStandardAsf.h
  • ASF_EVENT_SOURCE_TYPE_PLATFORM_FIRMWARE : IndustryStandardAsf.h
  • ASF_EVENT_TYPE_THRESHOLD_BASED : IndustryStandardAsf.h
  • ASF_FE_AMTBX_FAILURE : IntelAsfExtensions.h
  • ASF_FE_EVENT_DATA1 : IndustryStandardAsf.h
  • ASF_FP_AMTBX_INIT : IntelAsfExtensions.h
  • ASF_FP_EVENT_DATA1 : IndustryStandardAsf.h
  • ASF_INDUSTRY_CONVERTED_IANA : AsfProtocol.h
  • ASF_INDUSTRY_IANA : AsfProtocol.h
  • ASF_INFO_TYPE : IndustryStandardAsf.h
  • ASF_INTEL_CONVERTED_IANA : AsfProtocol.h
  • ASF_INTEL_OEM_CMD : AsfProtocol.h
  • ASF_MESSAGE_COMMAND_LAN : IntelAsfExtensions.h
  • ASF_MESSAGE_COMMAND_SENSOR_DEVICE_SYSTEM_STATE : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_CLEAR_BOOT_OPT : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_GET_EVENT_DATA : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_GET_RSE_PASSWORD : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_KVM_QUERY : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_SET_ACTIVE_LAN : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_SET_ALERT_CONFIG : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_SET_MAC_PASSTHROUGH : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_START_WATCH_DOG_TIMER : IndustryStandardAsf.h
  • ASF_OCR_EVENT_DATA3_BOOT_PARAMETER_RECEIVED : IntelAsfExtensions.h
  • ASF_OCR_EVENT_DATA3_SUCCESS : IntelAsfExtensions.h
  • ASF_RBS_BIOS_STATUS_SUCCESS : IntelAsfExtensions.h
  • ASF_RMCP_BOOT_OPTION_SUCCESS : IndustryStandardAsf.h
  • ASF_RPE_EVENT_OFFSET_PROGRESS : IntelAsfExtensions.h
  • ASF_SENSOR_DEVICE : IndustryStandardAsf.h
  • ASF_SENSOR_NUMBER : IndustryStandardAsf.h
  • ASF_START_BIOS_WDT : AsfMsgs.h
  • ASF_WD_EVENT_DATA1 : IndustryStandardAsf.h
  • AsfGetRemoteFlashState() : DxeAsfLib.h
  • AsfGetRootCaCertificate() : DxeAmtHeciLib.h
  • AsfGetSpecialCmdParamHighByte() : DxeAsfLib.h
  • AsfGetSpecialCmdParamLowByte() : DxeAsfLib.h
  • AsfGetSpecialCommand() : DxeAsfLib.h
  • AsfGetStorageRedirectionBootDevice() : DxeAsfLib.h
  • AsfGetUefiBootOptionsState() : DxeAmtHeciLib.h
  • AsfGetUefiBootParameters() : DxeAmtHeciLib.h
  • AsfIsBootOptionsPresent() : DxeAsfLib.h
  • AsfIsConfigurationDataResetEnabled() : DxeAsfLib.h
  • AsfIsConsoleLocked() : DxeAsfLib.h
  • AsfIsEnforceSecureBootEnabled() : DxeAsfLib.h
  • AsfIsEnterSetupEnabled() : DxeAsfLib.h
  • AsfIsFwProgressEnabled() : DxeAsfLib.h
  • AsfIsIndustryIanaId() : DxeAsfLib.h
  • AsfIsKvmEnabled() : DxeAsfLib.h
  • AsfIsPauseBootEnabled() : DxeAsfLib.h
  • AsfIsRemotePlatformEraseEnabled() : DxeAsfLib.h
  • AsfIsSecureEraseEnabled() : DxeAsfLib.h
  • AsfIsSolEnabled() : DxeAsfLib.h
  • AsfIsStorageRedirectionEnabled() : DxeAsfLib.h
  • AsfSetUefiBootOptionsState() : DxeAmtHeciLib.h
  • AsfStartWatchDog() : DxeAmtHeciLib.h
  • AsfStopWatchDog() : DxeAmtHeciLib.h
  • AsfUpdateUefiBootOptions() : DxeAmtHeciLib.h
  • AsfWifiGetClientCertificate() : DxeAmtHeciLib.h
  • AsfWifiGetClientKey() : DxeAmtHeciLib.h
  • AsfWifiGetProfileData() : DxeAmtHeciLib.h
  • AsfWifiGetProfileName() : DxeAmtHeciLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- b -

  • B_ACPI_IO_DEVTRAP_STS_D12_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D6_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D7_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D8_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D9_TRP_STS : PmcRegs.h
  • B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN : PmcRegs.h
  • B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS : PmcRegs.h
  • B_ACPI_IO_GPE_CTRL_SWGPE_CTRL : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_CTL_LCK : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_FORCE_ALL : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV_STS : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_NO_ICCSURV_STS : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SCI_EN : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SLP_EN : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SLP_TYP : PmcRegs.h
  • B_ACPI_IO_PM1_TMR_TMR_VAL : PmcRegs.h
  • B_ACPI_IO_SMI_EN_BIOS_RLS : PmcRegs.h
  • B_ACPI_IO_SMI_EN_EOS : PmcRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_2_LTR_MEC_EN : CnviRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_CAP_2_LTR_MEC_SUP : CnviRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_CTRL_FLR : CnviRegs.h
  • B_CNVI_CFG_WIFI_PMCSR_PS : CnviRegs.h
  • B_CNVI_PCR_WIFI_WIDGET_CONTROL_MEM_INT : CnviRegs.h
  • B_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1_RTCO : UsbRegs.h
  • B_CRB_CONTROL_REQ_COMMAND_READY : PttPtpRegs.h
  • B_CRB_CONTROL_REQ_GO_IDLE : PttPtpRegs.h
  • B_CRB_CONTROL_START : PttPtpRegs.h
  • B_CRB_CONTROL_STS_TPM_IDLE : PttPtpRegs.h
  • B_CRB_CONTROL_STS_TPM_STATUS : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_RELINQUISH : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_REQUEST_ACCESS : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_SEIZE : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_REGISTER_VALID : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_TPM_ESTABLISHED : PttPtpRegs.h
  • B_CRB_LOCALITY_STS_BEEN_SEIZED : PttPtpRegs.h
  • B_CRB_LOCALITY_STS_GRANTED : PttPtpRegs.h
  • B_ESPI_CFG_PCBC_BILD : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWPDS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWRE : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWRS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_EISS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_ESPI_EN : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_LE : PchRegsLpc.h
  • B_ESPI_PCR_CFG_VAL_ESPI_EN : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SAFBLK : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SLV0_FCFEE : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SLV0_FCNFEE : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_LFET1E : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_LFET1S : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_SLCRR : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV1_LFET1E : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCFEE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCNFEE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCNFES : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCRMTARE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCURD : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCURRE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_SLV0_PCURD : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_SLV0_PMMA : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SID : PchRegsLpc.h
  • B_ESPI_PCR_SOFTSTRAPS_CS1_EN : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_SLV0_VWHC10OE : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_VWFEE : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_VWNFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XFES : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XNFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XNFES : PchRegsLpc.h
  • B_ESPI_SLAVE_BME : PchRegsLpc.h
  • B_FLASH_FDBAR_CPUSL : FlashRegs.h
  • B_FLASH_FDBAR_FCBA : FlashRegs.h
  • B_FLASH_FDBAR_FCPUSBA : FlashRegs.h
  • B_FLASH_FDBAR_FMBA : FlashRegs.h
  • B_FLASH_FDBAR_FPSBA : FlashRegs.h
  • B_FLASH_FDBAR_FRBA : FlashRegs.h
  • B_FLASH_FDBAR_NC : FlashRegs.h
  • B_FLASH_FDBAR_NM : FlashRegs.h
  • B_FLASH_FDBAR_NR : FlashRegs.h
  • B_FLASH_FDBAR_PCHSL : FlashRegs.h
  • B_FLASH_FLCOMP_COMP0_MASK : FlashRegs.h
  • B_FLASH_FLCOMP_COMP1_MASK : FlashRegs.h
  • B_FLASH_FLCOMP_FR_SUP : FlashRegs.h
  • B_FLASH_FLCOMP_FRCF_FREQ : FlashRegs.h
  • B_FLASH_FLCOMP_RIDS_FREQ : FlashRegs.h
  • B_FLASH_FLCOMP_WE_FREQ : FlashRegs.h
  • B_FLASH_STRAP_DSCR_0_PTT_SUPP : FlashRegs.h
  • B_FLASH_STRAP_MMP0 : FlashRegs.h
  • B_FLASH_STRAP_SFDP_DIORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_DORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_QIORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_QORE : FlashRegs.h
  • B_FLASH_UMAP1_MDTBA : FlashRegs.h
  • B_FLASH_UMAP1_VTBA : FlashRegs.h
  • B_FLASH_UMAP1_VTL : FlashRegs.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • B_LPC_CFG_BC_BBS : PchRegsLpc.h
  • B_LPC_CFG_BC_BILD : PchRegsLpc.h
  • B_LPC_CFG_BC_EISS : PchRegsLpc.h
  • B_LPC_CFG_BC_LE : PchRegsLpc.h
  • B_LPC_CFG_BC_TS : PchRegsLpc.h
  • B_LPC_CFG_BC_WPD : PchRegsLpc.h
  • B_LPC_CFG_FVEC3_DCMI_CAP : PchRegsLpc.h
  • B_LPC_CFG_FVEC3_NM_CAP : PchRegsLpc.h
  • B_LPC_CFG_IOE_CAE : PchRegsLpc.h
  • B_LPC_CFG_IOE_CBE : PchRegsLpc.h
  • B_LPC_CFG_IOE_FDE : PchRegsLpc.h
  • B_LPC_CFG_IOE_HGE : PchRegsLpc.h
  • B_LPC_CFG_IOE_KE : PchRegsLpc.h
  • B_LPC_CFG_IOE_LGE : PchRegsLpc.h
  • B_LPC_CFG_IOE_ME1 : PchRegsLpc.h
  • B_LPC_CFG_IOE_ME2 : PchRegsLpc.h
  • B_LPC_CFG_IOE_PPE : PchRegsLpc.h
  • B_LPC_CFG_IOE_SE : PchRegsLpc.h
  • B_PCH_DMI14_PCR_DMIC_DMICGEN : PchDmi14Regs.h
  • B_PCH_DMI14_PCR_DMIC_SRL : PchDmi14Regs.h
  • B_PCH_DMI14_PCR_IPCS_PSS : PchDmi14Regs.h
  • B_PCH_DMI15_PCR_BBCLKREQEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CCFG_DCGEISMA : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_DLDHB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L0SPFCUF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L1PL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L1RC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_MRSCDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_PSS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_TCUAPF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_UTPB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL2_CPGEXLCWDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL2_DLDRSP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CWBCTL_CWBE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_EQCFG1_RTLEPCEB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_EQCFG1_RTPCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_IOSFSBCS_SCPTCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_IOSFSBCS_SIID : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TPOSTCO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TPRECO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TPOSTCO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TPRECO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCLKREQEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL2_TLS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_ASPM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_ES : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_RL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_CAM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_GEN2PLLC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_GEN3PLLC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_ORCE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_PLLWAIT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_RUD : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_TLPF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC_FCP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC_SRL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_HAE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_PMCRE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_SE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_CROAOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_CROAOV : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_LBWSSTE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEDBG_SPCE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_DETSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_DISSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_FDCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L1SCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L1SPHYDLPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L23RDYSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_PHYCLPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_DLSULDLSD : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_DLSULPPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_IPACPE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_IPIEP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_PXPG2PLLOFFEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_PXPG3PLLOFFEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_TDFT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_TXCFGCHGWAIT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL3_SQDIRCTRL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL3_SQDIROVREN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL4_SQDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PSSSGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PTOCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PWRCTL_DBUPI : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PWRCTL_RPSEWL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPDBCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPDLCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPPGEN_SEOSCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_SRDBCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_CM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_PT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_URE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS0TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS1TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS2TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS3TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TSAWEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPL0246TP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPL1357TP : PchDmi15Regs.h
  • B_PCH_DMI_PCR_BBS : PchDmiRegs.h
  • B_PCH_DMI_PCR_BILD : PchDmiRegs.h
  • B_PCH_DMI_PCR_GPMRXDID_GPMR1DE : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_APMS : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_EL0 : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_EL1 : PchDmiRegs.h
  • B_PCH_DMI_PCR_RPR : PchDmiRegs.h
  • B_PCH_DMI_PCR_RPRDID : PchDmiRegs.h
  • B_PCH_DMI_PCR_TCOBASE_TCOBA : PchDmiRegs.h
  • B_PCH_DMI_PCR_UCPR_UPRE : PchDmiRegs.h
  • B_PCH_DMI_PCR_V0CTL_ID : PchDmiRegs.h
  • B_PCH_DMI_PCR_V1CTL_ID : PchDmiRegs.h
  • B_PCH_PCIE_CFG_EX_CES_BD : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_EX_CES_BT : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_EX_CES_RE : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LOCK : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR_LTRNSROVR : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR_LTRSROVR : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_PTMECFG_IOSFMADP : PchPcieRpRegs.h
  • B_PCH_SPI_STRP_GBETSN_DIS : FlashRegs.h
  • B_PCH_SPI_STRP_THC0_DIS : FlashRegs.h
  • B_PCH_SPI_STRP_THC1_DIS : FlashRegs.h
  • B_PCI_BRIDGE_BNUM_PBN : PcieRegs.h
  • B_PCI_BRIDGE_BNUM_SBBN : PcieRegs.h
  • B_PCI_BRIDGE_BNUM_SCBN : PcieRegs.h
  • B_PCI_BRIDGE_MBL_MB : PcieRegs.h
  • B_PCI_BRIDGE_MBL_ML : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_I64B : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_I64L : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_PMB : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_PML : PcieRegs.h
  • B_PCIE_DCAP2_LTRMS : PcieRegs.h
  • B_PCIE_DCAP2_OBFFS : PcieRegs.h
  • B_PCIE_DCAP2_PX10BTCS : PcieRegs.h
  • B_PCIE_DCAP2_PX10BTRS : PcieRegs.h
  • B_PCIE_DCAP_E0AL : PcieRegs.h
  • B_PCIE_DCAP_E1AL : PcieRegs.h
  • B_PCIE_DCAP_MPS : PcieRegs.h
  • B_PCIE_DCAP_RBER : PcieRegs.h
  • B_PCIE_DCTL2_AEB : PcieRegs.h
  • B_PCIE_DCTL2_CTD : PcieRegs.h
  • B_PCIE_DCTL2_CTV : PcieRegs.h
  • B_PCIE_DCTL2_LTREN : PcieRegs.h
  • B_PCIE_DCTL2_OBFFEN : PcieRegs.h
  • B_PCIE_DCTL2_PX10BTRE : PcieRegs.h
  • B_PCIE_DCTL_CEE : PcieRegs.h
  • B_PCIE_DCTL_FEE : PcieRegs.h
  • B_PCIE_DCTL_MPS : PcieRegs.h
  • B_PCIE_DCTL_NFE : PcieRegs.h
  • B_PCIE_DCTL_NS : PcieRegs.h
  • B_PCIE_DCTL_RO : PcieRegs.h
  • B_PCIE_DCTL_URE : PcieRegs.h
  • B_PCIE_DSTS_APD : PcieRegs.h
  • B_PCIE_DSTS_CED : PcieRegs.h
  • B_PCIE_DSTS_FED : PcieRegs.h
  • B_PCIE_DSTS_NFED : PcieRegs.h
  • B_PCIE_DSTS_TDP : PcieRegs.h
  • B_PCIE_DSTS_URD : PcieRegs.h
  • B_PCIE_EX_L01EC_DPL0TP : PcieRegs.h
  • B_PCIE_EX_L01EC_DPL1TP : PcieRegs.h
  • B_PCIE_EX_L01EC_UPL0TP : PcieRegs.h
  • B_PCIE_EX_L01EC_UPL1TP : PcieRegs.h
  • B_PCIE_EX_L1SCAP_AL12S : PcieRegs.h
  • B_PCIE_EX_L1SCAP_AL1SS : PcieRegs.h
  • B_PCIE_EX_L1SCAP_L1PSS : PcieRegs.h
  • B_PCIE_EX_L1SCAP_L1SSES : PcieRegs.h
  • B_PCIE_EX_L1SCAP_PPL11S : PcieRegs.h
  • B_PCIE_EX_L1SCAP_PPL12S : PcieRegs.h
  • B_PCIE_EX_L1SCTL1_L12LTRTLSV : PcieRegs.h
  • B_PCIE_EX_L1SCTL1_L12LTRTLV : PcieRegs.h
  • B_PCIE_EX_L23EC_DPL2TP : PcieRegs.h
  • B_PCIE_EX_L23EC_DPL3TP : PcieRegs.h
  • B_PCIE_EX_L23EC_UPL2TP : PcieRegs.h
  • B_PCIE_EX_L23EC_UPL3TP : PcieRegs.h
  • B_PCIE_EX_LCTL3_PE : PcieRegs.h
  • B_PCIE_EX_PTMCAP_PTMRC : PcieRegs.h
  • B_PCIE_EX_PTMCAP_PTMRSPC : PcieRegs.h
  • B_PCIE_EX_UEM_CT : PcieRegs.h
  • B_PCIE_EX_UEM_UC : PcieRegs.h
  • B_PCIE_EXCAP_CID : PcieRegs.h
  • B_PCIE_EXCAP_CV : PcieRegs.h
  • B_PCIE_EXCAP_NCO : PcieRegs.h
  • B_PCIE_LCAP_APMS : PcieRegs.h
  • B_PCIE_LCAP_ASPMOC : PcieRegs.h
  • B_PCIE_LCAP_CPM : PcieRegs.h
  • B_PCIE_LCAP_EL0 : PcieRegs.h
  • B_PCIE_LCAP_EL1 : PcieRegs.h
  • B_PCIE_LCAP_MLS : PcieRegs.h
  • B_PCIE_LCAP_MLW : PcieRegs.h
  • B_PCIE_LCTL2_SD : PcieRegs.h
  • B_PCIE_LCTL2_TLS : PcieRegs.h
  • B_PCIE_LCTL_ASPM : PcieRegs.h
  • B_PCIE_LCTL_CCC : PcieRegs.h
  • B_PCIE_LCTL_ECPM : PcieRegs.h
  • B_PCIE_LCTL_ES : PcieRegs.h
  • B_PCIE_LCTL_LD : PcieRegs.h
  • B_PCIE_LCTL_RL : PcieRegs.h
  • B_PCIE_LSTS2_CDL : PcieRegs.h
  • B_PCIE_LSTS2_EC : PcieRegs.h
  • B_PCIE_LSTS2_EQP1S : PcieRegs.h
  • B_PCIE_LSTS2_EQP2S : PcieRegs.h
  • B_PCIE_LSTS2_EQP3S : PcieRegs.h
  • B_PCIE_LSTS2_LER : PcieRegs.h
  • B_PCIE_LSTS_CLS : PcieRegs.h
  • B_PCIE_LSTS_LA : PcieRegs.h
  • B_PCIE_LSTS_LT : PcieRegs.h
  • B_PCIE_LSTS_NLW : PcieRegs.h
  • B_PCIE_LSTS_SCC : PcieRegs.h
  • B_PCIE_PMC_PMEC : PcieRegs.h
  • B_PCIE_PMC_PMES : PcieRegs.h
  • B_PCIE_PMCS_B23S : PcieRegs.h
  • B_PCIE_PMCS_BPCE : PcieRegs.h
  • B_PCIE_PMCS_NSR : PcieRegs.h
  • B_PCIE_PMCS_PMEE : PcieRegs.h
  • B_PCIE_PMCS_PMES : PcieRegs.h
  • B_PCIE_PMCS_PS : PcieRegs.h
  • B_PCIE_RCTL_PIE : PcieRegs.h
  • B_PCIE_RCTL_SCE : PcieRegs.h
  • B_PCIE_RCTL_SFE : PcieRegs.h
  • B_PCIE_RCTL_SNE : PcieRegs.h
  • B_PCIE_SLCAP_ABP : PcieRegs.h
  • B_PCIE_SLCAP_AIP : PcieRegs.h
  • B_PCIE_SLCAP_HPC : PcieRegs.h
  • B_PCIE_SLCAP_HPS : PcieRegs.h
  • B_PCIE_SLCAP_MRLSP : PcieRegs.h
  • B_PCIE_SLCAP_PCP : PcieRegs.h
  • B_PCIE_SLCAP_PIP : PcieRegs.h
  • B_PCIE_SLCAP_PSN : PcieRegs.h
  • B_PCIE_SLCAP_SLS : PcieRegs.h
  • B_PCIE_SLCAP_SLV : PcieRegs.h
  • B_PCIE_SLCTL_HPE : PcieRegs.h
  • B_PCIE_SLCTL_PDE : PcieRegs.h
  • B_PCIE_SLSTS_PDC : PcieRegs.h
  • B_PCIE_SLSTS_PDS : PcieRegs.h
  • B_PCIE_XCAP_DT : PcieRegs.h
  • B_PCIE_XCAP_SI : PcieRegs.h
  • B_PMC_CFG_ACTL_ACPI_EN : PmcRegs.h
  • B_PMC_CFG_ACTL_PWRM_EN : PmcRegs.h
  • B_PMC_CFG_ACTL_SCIS : PmcRegs.h
  • B_PMC_CFG_PWRM_BASE_MASK : PmcRegs.h
  • B_PMC_DEF_CPU_BCLK_CFG : PmcRegs.h
  • B_PMC_PWRM_ACPI_SCIS : PmcRegs.h
  • B_PMC_PWRM_ADR_CTRL_STS_ADR_RST_STS : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_FEAT_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_GPIO_SEL : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_PLT_ACK_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_HPR_ADR_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_SCALE : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_TOV : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_SCALE : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_TOV : PmcRegs.h
  • B_PMC_PWRM_CFG4_PSON_SLPS0_TMR : PmcRegs.h
  • B_PMC_PWRM_CFG4_SLPS0_PSON_TMR : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_CPPM_G1_QUAL : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LT_G1_SEL : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH_V2 : PmcRegs.h
  • B_PMC_PWRM_CPPM_FIVR_POL1B_TNTE_FIVR_VOLT_PRE_WAKE : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_CPPM_MPHY_QUAL : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_LT_MPHY_SEL : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_LTR_MPHY_THRESH : PmcRegs.h
  • B_PMC_PWRM_CRID_CRID_LK : PmcRegs.h
  • B_PMC_PWRM_CRID_RID_SEL : PmcRegs.h
  • B_PMC_PWRM_CRID_UIP_CRID_UIP : PmcRegs.h
  • B_PMC_PWRM_CS_ACRO_CRO_OVR_EN : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS_XTAL_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN : PmcRegs.h
  • B_PMC_PWRM_EN_PA_SLOW_RING2_GBETSN : PmcRegs.h
  • B_PMC_PWRM_ETR3_CF9GR : PmcRegs.h
  • B_PMC_PWRM_ETR3_CF9LOCK : PmcRegs.h
  • B_PMC_PWRM_ETR3_CWORWRE : PmcRegs.h
  • B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT : PmcRegs.h
  • B_PMC_PWRM_GBL2HOST_EN_HOST_RESET_TIMEOUT : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DISB : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_MEM_SR : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_MS4V : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW0 : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW1 : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW2 : PmcRegs.h
  • B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST : PmcRegs.h
  • B_PMC_PWRM_IPC_STS_BUSY : PmcRegs.h
  • B_PMC_PWRM_IPC_STS_ERROR : PmcRegs.h
  • B_PMC_PWRM_LPM_ADEM_HOST_CTRL_EN : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_C10_QUAL_MPHYPG : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_MLSPDDGE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_MPLSPDDGE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_DRAM_RESET_CTL : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_EN_DBG_MSG : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_PB_DIS : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_PBOP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_DSX_WLAN_PP_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_HOST_MISC_CORE_CFG_CPU_VCC_MAP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_HOST_WLAN_PP_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_SYS_RST_SUP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG4_CPU_IOVR_RAMP_DUR : PmcRegs.h
  • B_PMC_PWRM_PM_CFG4_U2_PHY_PG_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ALLOW_24_OSC_SD : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ALLOW_USB2_CORE_PG : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_COCS : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_DBG_MODE_LOCK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ER_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ER_LOCK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_PMC_READ_DISABLE : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_RPCD_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_SAMAW_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_SSMAW_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_TIMING_TPCH25 : PmcRegs.h
  • B_PMC_PWRM_PM_SYNC_MISC_CFG_PM_SYNC_LOCK : PmcRegs.h
  • B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS : PmcRegs.h
  • B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_SSMC_SSMS : PmcRegs.h
  • B_PMC_PWRM_SSML_SSL : PmcRegs.h
  • B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK : PmcRegs.h
  • B_RTC_PCR_BUC_DSO : RtcRegs.h
  • B_RTC_PCR_BUC_TS : RtcRegs.h
  • B_RTC_PCR_CONF_BILD : RtcRegs.h
  • B_RTC_PCR_CONF_HPM_HW_DIS : RtcRegs.h
  • B_RTC_PCR_CONF_LCMOS_LOCK : RtcRegs.h
  • B_RTC_PCR_CONF_UCMOS_EN : RtcRegs.h
  • B_RTC_PCR_CONF_UCMOS_LOCK : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCPCICLKDCGEN : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCPGCBDCGEN : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCROSIDEDCGEN : RtcRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_TCSO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_CRGC_CRAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRDCGE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRTCGE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_ICAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_TSCAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_CRE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_CREL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_PLS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_PNCAIDL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_RCL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCD : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PLRC : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_IOBRSC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TT : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXCRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXCRCC_TCSO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPBAR_TBAV : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TBIR : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTBAR_TBAV : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TBIR : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TO : SataRegs.h
  • B_SATA_MEM_AHCI_CAP2_APST : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_PMD : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SCLO : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SMPS : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SPM : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SSS : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SXS : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_ESP : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_HPCP : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_MPSP : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_AMXC_AMXV : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_DT : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS_CR1 : SataRegs.h
  • B_SATA_MEM_VS_CAP_NRMBE : SataRegs.h
  • B_SMBUS_IO_STCO : PchRegsSmbus.h
  • B_SMBUS_PCR_GC_FD : PchRegsSmbus.h
  • B_SMBUS_PCR_GC_SMBSCGE : PchRegsSmbus.h
  • B_SMBUS_PCR_PCE_HAE : PchRegsSmbus.h
  • B_SMBUS_PCR_SCTM_SSU : PchRegsSmbus.h
  • B_SMBUS_PCR_SMBTM_SMBCT : PchRegsSmbus.h
  • B_SMBUS_PCR_SMBTM_SMBDG : PchRegsSmbus.h
  • B_SMBUS_PCR_TCOCFG_IE : PchRegsSmbus.h
  • B_SMBUS_PCR_TCOCFG_IS : PchRegsSmbus.h
  • B_SPX_PCR_IMRAMBL_IAMB : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMBL_IAML : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMBL_RS3BN : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE1 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE2 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE3 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE4 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_SRL : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P1D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P2D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P3D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P4D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP1CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP1FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP2CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP2FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP3CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP3FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP4CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP4FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_SRL : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_CRCSEL : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEGMO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPCRC : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPME : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPPS : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIELDO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIELRO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIERIL0O : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIESSM : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIESST : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIETIL0O : PchPcieRpRegs.h
  • B_USB2_PCR_PER_PORT_2_TXEMPHASISEN : UsbRegs.h
  • B_XDCI_MEM_GCTL_GHIBEREN : UsbRegs.h
  • B_XDCI_MEM_GUSB2PHYCFG_SUSPHY : UsbRegs.h
  • B_XDCI_MEM_GUSB3PIPECTL0_SUSPEN_EN : UsbRegs.h
  • B_XHCI_CFG_XHCC2_RDREQSZCTRL : UsbRegs.h
  • B_XHCI_CFG_XHCC2_WRREQSZCTRL : UsbRegs.h
  • B_XHCI_MEM_AUX_CTRL_REG3_HYST_TIMEOUT_150US : UsbRegs.h
  • B_XHCI_MEM_AUX_CTRL_REG3_HYSTERESIS_TIMEOUT : UsbRegs.h
  • B_XHCI_MEM_D0I2SCH_ALARM_CTRL : UsbRegs.h
  • B_XHCI_MEM_PORTSCXUSB2_CCS : UsbRegs.h
  • B_XHCI_MEM_PORTSCXUSB2_PED : UsbRegs.h
  • B_XHCI_MEM_SOCHWSTSAVE1_CMD_SSV : UsbRegs.h
  • B_XHCI_MEM_XECP_SUPP_USBX_2_CPC : UsbRegs.h
  • B_XHCI_MEM_XHCLTVCTL2_LTV_LIMIT : UsbRegs.h
  • B_XHCI_MEM_XLTP_LTV1_USB2_PL0_LTV : UsbRegs.h
  • B_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT : UsbRegs.h
  • B_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS : UsbRegs.h
  • BGPDT_MAJOR_VERSION : BiosGuard.h
  • BGPDT_MINOR_VERSION : BiosGuard.h
  • BGUP_HDR_VERSION : BiosGuard.h
  • BGUP_TSEG_BUFFER_SIZE : BiosGuard.h
  • BGUPC_MEMORY_OFFSET : BiosGuard.h
  • BGUPC_MEMORY_SIZE : BiosGuard.h
  • BIOACM_ADDR : Txt.h
  • BIOS_ASF_HOST_ADDR : CoreBiosMsg.h
  • BIOS_FIXED_HOST_ADDR : CoreBiosMsg.h
  • BIOS_GUARD_CONFIG_REVISION : BiosGuardConfig.h
  • BIOS_MSG_DID_SUCCESS : BupMsgs.h
  • BIOS_OS_DATA_REGION : Txt.h
  • BIOS_OS_DATAREGION_VERSION : Txt.h
  • BIOS_PAUSE : AsfProtocol.h
  • BIOS_SETUP : AsfProtocol.h
  • BIOSGUARD_ATTRIBUTES : BiosGuard.h
  • BIOSGUARD_B0_INDEX : BiosGuard.h
  • BIOSGUARD_BUILD_NUMBER_OFFSET : BiosGuard.h
  • BIOSGUARD_COMMAND_BEGIN : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_CMD_WR_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_CMD_WR_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_RD : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_WR_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_WR_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_STS_RD : BiosGuard.h
  • BIOSGUARD_COMMAND_END : BiosGuard.h
  • BIOSGUARD_COMMAND_ERASE_BLK : BiosGuard.h
  • BIOSGUARD_COMMAND_NOP : BiosGuard.h
  • BIOSGUARD_COMMAND_RD_STS : BiosGuard.h
  • BIOSGUARD_COMMAND_READ_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_READ_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_SET_BUFFER_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_SET_FLASH_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_WRITE_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_WRITE_INDEX : BiosGuard.h
  • BIOSGUARD_ERASE : Protocol/BiosGuard.h
  • BIOSGUARD_EXECUTE : Protocol/BiosGuard.h
  • BIOSGUARD_F0_INDEX : BiosGuard.h
  • BIOSGUARD_IF_INDEX : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_MODULE_ID_OFFSET : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_SE_SVN_OFFSET : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_SVN_OFFSET : BiosGuard.h
  • BIOSGUARD_LOG_MEMORY_OFFSET : BiosGuard.h
  • BIOSGUARD_LOG_MEMORY_SIZE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_BRANCH_TRACE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_DEBUG : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_ERASE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_ERROR : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_WRITE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_STEP_TRACE : BiosGuard.h
  • BIOSGUARD_LOG_VERSION : BiosGuard.h
  • BIOSGUARD_MEMORY_PAGES : BiosGuard.h
  • BIOSGUARD_MODULE_SIZE_IN_PAGES : BiosGuard.h
  • BIOSGUARD_MODULE_SIZE_OFFSET : BiosGuard.h
  • BIOSGUARD_PRODUCT_ID_OFFSET : BiosGuard.h
  • BIOSGUARD_PROTOCOL : Protocol/BiosGuard.h
  • BIOSGUARD_REVISION_ID_MAJOR_OFFSET : BiosGuard.h
  • BIOSGUARD_REVISION_ID_MINOR_OFFSET : BiosGuard.h
  • BIOSGUARD_WRITE : Protocol/BiosGuard.h
  • BIT : CpuRegs.h
  • bmCold : MemInfoHob.h
  • bmFast : MemInfoHob.h
  • bmS3 : MemInfoHob.h
  • bmWarm : MemInfoHob.h
  • BootMediaIsKnown() : BootMediaLib.h
  • BootMediaIsSpi() : BootMediaLib.h
  • BootMediaIsUfs() : BootMediaLib.h
  • BuildFviInfoHob() : SiFvi.h
  • BuildPciImrHob() : PeiPcieRpLib.h
  • BUP_COMMON_GROUP_ID : BupMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- c -

  • C6_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • C7_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • C7s_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • C_STATE_TIME_UNIT : CpuPowerMgmtTestConfig.h
  • CBM_RESET_CMD : MkhiMsgs.h
  • CERT_NAME_MAX_ASCII_STRING : AmthiMsgs.h
  • CFG_EOP_STATE : AmthiMsgs.h
  • CFG_IPV6_ADDR_LEN_MAX : AmthiMsgs.h
  • CFG_MEBX_PWD_CHANGE_POLICY : AmthiMsgs.h
  • CFG_UNPROVISIONING_STATE : AmthiMsgs.h
  • CheckPowerOffNow() : PmcLib.h
  • CheckSmxCapabilities() : TxtLib.h
  • ClearBootOptions() : DxeAsfHeciLib.h
  • ClearD0I3Bit() : MeChipsetLib.h
  • ClearSmiAndWake() : PmcLib.h
  • CLOCK_FREQUENCY_19MHz : VoltageRegulatorCommands.h
  • CNVI_MODE : CnviConfig.h
  • CnviDevNumber() : PchPciBdfLib.h
  • CnviFuncNumber() : PchPciBdfLib.h
  • CnviIsPresent() : CnviLib.h
  • CnviPciCfgBase() : PchPciBdfLib.h
  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h
  • ConvertSystemTimeToUnixFormat() : SystemTimeLib.h
  • CopyAuthSessionCommand() : Tpm2CommandLib.h
  • CopyAuthSessionResponse() : Tpm2CommandLib.h
  • CopyDigestListToBuffer() : Tpm2CommandLib.h
  • CPU_FEATURE_DISABLE : CpuRegs.h
  • CPU_FVI_STRING : SiFvi.h
  • CPU_GENERATION : CpuRegs.h
  • CPU_PCIE_ASPM_CONTROL : CpuPcieConfig.h
  • CPU_PCIE_CONFIG_REVISION : CpuPcieConfig.h
  • CPU_PCIE_EQ_METHOD : CpuPcieConfig.h
  • CPU_PCIE_L1SUBSTATES_CONTROL : CpuPcieConfig.h
  • CPU_SKU : CpuRegs.h
  • CPU_TYPE_CHANGE_ACCEPTED : MkhiMsgs.h
  • CpuAddConfigBlocks() : CpuPolicyLib.h
  • CpuAddPreMemConfigBlocks() : CpuPolicyLib.h
  • CpuCrashLogClear() : TelemetryLib.h
  • CpuCrashLogDiscovery() : TelemetryLib.h
  • CpuCrashLogReArm() : TelemetryLib.h
  • CpuGetConfigBlockTotalSize() : CpuPolicyLib.h
  • CpuGetPreMemConfigBlockTotalSize() : CpuPolicyLib.h
  • CpuPcieEqDefault : CpuPcieConfig.h
  • CpuPcieEqHardware : CpuPcieConfig.h
  • CpuPcieEqStaticCoeff : CpuPcieConfig.h
  • CpuPreMemPrintPolicy() : CpuPolicyLib.h
  • CpuPrintPolicy() : CpuPolicyLib.h
  • CpuRegbarAnd16() : CpuRegbarAccessLib.h
  • CpuRegbarAnd32() : CpuRegbarAccessLib.h
  • CpuRegbarAnd8() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr16() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr32() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr8() : CpuRegbarAccessLib.h
  • CpuRegbarOr16() : CpuRegbarAccessLib.h
  • CpuRegbarOr32() : CpuRegbarAccessLib.h
  • CpuRegbarOr8() : CpuRegbarAccessLib.h
  • CpuRegbarRead16() : CpuRegbarAccessLib.h
  • CpuRegbarRead32() : CpuRegbarAccessLib.h
  • CpuRegbarRead64() : CpuRegbarAccessLib.h
  • CpuRegbarRead8() : CpuRegbarAccessLib.h
  • CpuRegbarWrite16() : CpuRegbarAccessLib.h
  • CpuRegbarWrite32() : CpuRegbarAccessLib.h
  • CpuRegbarWrite64() : CpuRegbarAccessLib.h
  • CpuRegbarWrite8() : CpuRegbarAccessLib.h
  • CpuRpIndex0 : PchPcieSmiDispatch.h
  • CpuWriteTraceHubAcpiBase() : CpuPlatformLib.h
  • CreateConfigBlockTable() : ConfigBlockLib.h
  • CreateITbtDxeConfigBlocks() : DxeITbtPolicyLib.h
  • CreatePchDxeConfigBlocks() : DxePchPolicyLib.h
  • CreateSaDxeConfigBlocks() : DxeSaPolicyLib.h
  • CU_CHIPSET_PC_INTRUDER_DETECT : IntelAsfExtensions.h
  • CU_HP_EC_VID_MISMATCH : IntelAsfExtensions.h
  • CUSTOM_POWER_UNIT : CpuPowerMgmtTestConfig.h
  • CUSTOM_PROFILE : MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- d -

  • DEFAULT_FVI_DATA : SiFvi.h
  • DEFAULT_PCI_SEGMENT_NUMBER_PCH : PchRegs.h
  • DEFAULT_SPD : MemoryConfig.h
  • DID_ACK_NON_PCR : BupMsgs.h
  • DISABLE_BUS_MASTER_ENABLE : TbtDisBmeProtocol.h
  • DisableCacheAsRam() : CacheAsRamLib.h
  • DisableState : MkhiMsgs.h
  • DMI_ASPM : CpuDmiPreMemConfig.h
  • DNX_REQ_SET_CMD : MkhiMsgs.h
  • DRAM_INIT_DONE_CMD : BupMsgs.h
  • DT_POWER_LIMIT1_TIME_DEFAULT : CpuPowerMgmt.h
  • dTpm12 : BootGuardLibVer1.h
  • dTpm20 : BootGuardLibVer1.h
  • DumpFspErrorInfo() : FspErrorInfoLib.h
  • DumpSiPolicy() : SiPolicyLib.h
  • DXE_ITBT_CONFIG : DxeITbtConfig.h
  • DXE_ITBT_GENERIC_CONFIG : DxeITbtConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- e -

  • EC_COMMAND_TYPE : BiosGuardConfig.h
  • EFI_PAGE_SIZE : BiosGuard.h
  • ENABLE_PCIE_TUNNELING_FOR_USB4 : TbtMailBoxCmdDefinition.h
  • ENABLE_REMOTE_PLATFORM_ERASE : AsfProtocol.h
  • ENABLE_SECURE_ERASE : AsfProtocol.h
  • EnablePowerWell2() : GraphicsInfoFruLib.h
  • EnablePowerWell3() : GraphicsInfoFruLib.h
  • EnableState : MkhiMsgs.h
  • ENFORCE_SECURE_BOOT : AsfProtocol.h
  • EnterS3WithImmediateWake() : ResetSystemLib.h
  • EnumMebx : SiFvi.h
  • EnumMeFw : SiFvi.h
  • EnumMeRc : SiFvi.h
  • EOP_DISABLED : MkhiMsgs.h
  • ERR_BAD_BGPDT : BiosGuard.h
  • ERR_BAD_BGUP : BiosGuard.h
  • ERR_BAD_BGUPC : BiosGuard.h
  • ERR_BAD_DIRECTORY : BiosGuard.h
  • ERR_BAD_SVN : BiosGuard.h
  • ERR_EXEC_LIMIT : BiosGuard.h
  • ERR_INTERNAL_ERROR : BiosGuard.h
  • ERR_INVALID_LINE : BiosGuard.h
  • ERR_LAUNCH_FAIL : BiosGuard.h
  • ERR_OK : BiosGuard.h
  • ERR_OVERFLOW : BiosGuard.h
  • ERR_RANGE_VIOLATION : BiosGuard.h
  • ERR_SCRIPT_SYNTAX : BiosGuard.h
  • ERR_SFAM_VIOLATION : BiosGuard.h
  • ERR_UNDEFINED_FLASH_OBJECT : BiosGuard.h
  • ERR_UNEXPECTED_OPCODE : BiosGuard.h
  • ERR_UNSUPPORTED_CPU : BiosGuard.h
  • EspiDevNumber() : PchPciBdfLib.h
  • EspiFuncNumber() : PchPciBdfLib.h
  • EspiPciCfgBase() : PchPciBdfLib.h
  • EXCEPTION_HANDLER : SmmResourceConfigProtocol.h
  • EXTENDED_DATA_RESERVED_BITMASK : MeSmbios.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- f -

  • FIA_INDEX : FiaAccessLib.h
  • FiaGetLos() : FiaAccessLib.h
  • FiaGetMaxLosRegister() : FiaAccessLib.h
  • FileClose() : DxeJhiSupportLib.h
  • FileOpen() : DxeJhiSupportLib.h
  • FileRead() : DxeJhiSupportLib.h
  • FindMeFwStsIndex() : MeFwStsLib.h
  • FIPS_MODE_DISABLED : MkhiMsgs.h
  • FIVR_RAIL_SX_STATE : FivrConfig.h
  • FLAGS0 : TxtInfoHob.h
  • FLASH_REGION_TYPE : Protocol/Spi.h
  • ForceGtRc6() : GraphicsInfoFruLib.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSP_TEMP_RAM_EXIT : TempRamExitPpi.h
  • FSP_TEMP_RAM_EXIT_GUID : TempRamExitPpi.h
  • FspErrorStatusCodeReportWorker() : FspErrorInfoLib.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h
  • FTIF_FT_LOC_MASK : PttPtpRegs.h
  • FTP_PARTITION_NAME_PMCP : MkhiMsgs.h
  • FUSA_CONFIG_REVISION : FusaConfig.h
  • FWCAPS_GET_RULE_CMD : MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- g -

  • gAmtSaveMebxProtocolGuid : AmtSaveMebxProtocol.h
  • GbeDevNumber() : GbeLib.h , PchPciBdfLib.h
  • GbeFuncNumber() : GbeLib.h , PchPciBdfLib.h
  • GbeGetLanPhyRevision() : GbeLib.h
  • GbePciCfgBase() : PchPciBdfLib.h
  • gBiosGuardConfigGuid : BiosGuardConfig.h
  • GEN_GET_MKHI_VERSION_CMD : MkhiMsgs.h
  • GenerateUserNonce() : MeUtilsLib.h
  • GET_MEBX_DATA : MebxConfigProtocol.h
  • GET_PLATFORM_DOCK_STATUS : GopPolicy.h
  • GET_PLATFORM_LID_STATUS : GopPolicy.h
  • GET_VBT_DATA : GopPolicy.h
  • GetActiveSocNorthAtomCoreCount() : CpuPlatformLib.h
  • GetBootGuardInfo() : BootGuardLibVer1.h
  • GetBootMediaType() : BootMediaLib.h
  • GetBootOptions() : DxeAsfHeciLib.h
  • GetBusRatio() : CpuPlatformLib.h
  • GetClkReqForClkSrc() : PchPcieRpLib.h
  • GetComponentConfigBlockTotalSize() : SiConfigBlockLib.h
  • GetConfigBlock() : ConfigBlockLib.h
  • GetConfigTdpLevels() : CpuPlatformLib.h
  • GetConfigTdpLevelsSupported() : CpuPlatformLib.h
  • GetCpuCrashLogBarAddress() : TelemetryLib.h
  • GetCpuCrashLogCapability() : TelemetryLib.h
  • GetCpuFamily() : CpuPlatformLib.h
  • GetCpuGeneration() : CpuPlatformLib.h
  • GetCpuIdentifier() : CpuPlatformLib.h
  • GetCpuIdentifierWithCtdp() : CpuPlatformLib.h
  • GetCpuNumberofCores() : CpuPlatformLib.h
  • GetCpuSku() : CpuPlatformLib.h
  • GetCpuStepping() : CpuPlatformLib.h
  • GetCpuSupportedCoresAndAtomCores() : CpuPlatformLib.h
  • GetCpuUcodeRevision() : CpuPlatformLib.h
  • GetCpuXhciBusNumber() : TcssInfoLib.h
  • GetCpuXhciDevNumber() : TcssInfoLib.h
  • GetCpuXhciFuncNumber() : TcssInfoLib.h
  • GetCrashLogHeader() : TelemetryLib.h
  • GetDigestFromDigestList() : Tpm2CommandLib.h
  • GetDigestListSize() : Tpm2CommandLib.h
  • GetEnabledCoreCount() : CpuPlatformLib.h
  • GetEnabledThreadCount() : CpuPlatformLib.h
  • GetGenerationString() : CpuPlatformLib.h
  • GetGmAdrOffset() : GraphicsInfoLib.h
  • GetGnaBusNumber() : GnaInfoLib.h
  • GetGnaDevNumber() : GnaInfoLib.h
  • GetGnaFuncNumber() : GnaInfoLib.h
  • GetGttMmAdrOffset() : GraphicsInfoLib.h
  • GetHashMaskFromAlgo() : Tpm2CommandLib.h
  • GetHashSizeFromAlgo() : Tpm2CommandLib.h
  • GetHeci() : MeUtilsLib.h
  • GetHeciPciBus() : MeUtilsLib.h
  • GetHeciPciDevice() : MeUtilsLib.h
  • GetHeciPciSegment() : MeUtilsLib.h
  • GetHybridGraphicsRpDevFun() : HybridGraphicsInfoFruLib.h
  • GetIgdBusNumber() : GraphicsInfoLib.h
  • GetIgdDevNumber() : GraphicsInfoLib.h
  • GetIgdDsmSizeInMb() : GraphicsInfoLib.h
  • GetIgdDssmRefClockFreqValue() : GraphicsInfoLib.h
  • GetIgdFuncNumber() : GraphicsInfoLib.h
  • GetIgdGmsSizeInMb() : GraphicsInfoLib.h
  • GetIgdGsmSizeInMb() : GraphicsInfoLib.h
  • GetIgdMsacOffset() : GraphicsInfoLib.h
  • GetIgdVtdOffset() : VtdInfoLib.h
  • GetIgfxApertureOffset() : GraphicsInfoLib.h
  • GetInitComplete() : MeUtilsLib.h
  • GetIopVtdOffset() : VtdInfoLib.h
  • GetIpuBusNumber() : IpuLib.h
  • GetIpuDevNumber() : IpuLib.h
  • GetIpuFuncNumber() : IpuLib.h
  • GetIpuVtdLowOffset() : VtdInfoLib.h
  • GetITbtDmaDevFun() : TbtCommonLib.h
  • GetITbtPcieDevNumber() : TcssInfoLib.h
  • GetMaxDmiBundles() : CpuDmiInfoLib.h
  • GetMaxDmiLanes() : CpuDmiInfoLib.h
  • GetMaxEfficiencyRatio() : CpuPlatformLib.h
  • GetMaxNonTurboRatio() : CpuPlatformLib.h
  • GetMaxNumVrs() : PeiVrDomainLib.h
  • GetMaxPhysicalAddressSize() : CpuPlatformLib.h
  • GetMaxSupportedPrmrrSize() : CpuPlatformLib.h
  • GetMaxVtdEngineNumber() : VtdInfoLib.h
  • GetMcaMsgParams() : MeUtilsLib.h
  • GetMeFwsts1FromHob() : MeUtilsLib.h
  • GetMeFwStsDeviceCount() : MeFwStsLib.h
  • GetMeFwStsOffsetCount() : MeFwStsLib.h
  • GetMeFwTypeSubTypeFromHob() : MeTypeLib.h
  • GetMeModeFromFwstsHob() : MeFwStsLib.h
  • GetMeStatusFromFwstsHob() : MeFwStsLib.h
  • GetMeUefiFwHealthStatus() : MeUefiFwHealthStatusLib.h
  • GetPackageTdp() : CpuPlatformLib.h
  • GetPchHdaMaxDmicLinkNum() : PchInfoLib.h
  • GetPchHdaMaxSndwLinkNum() : PchInfoLib.h
  • GetPchHdaMaxSspLinkNum() : PchInfoLib.h
  • GetPchHsioSataPreMemConfig() : PchPolicyLib.h
  • GetPchMaxIshGpNum() : PchInfoLib.h
  • GetPchMaxIshI2cControllersNum() : PchInfoLib.h
  • GetPchMaxIshSpiControllerCsPinsNum() : PchInfoLib.h
  • GetPchMaxIshSpiControllersNum() : PchInfoLib.h
  • GetPchMaxIshUartControllersNum() : PchInfoLib.h
  • GetPchMaxMeAppletCount() : PchInfoLib.h
  • GetPchMaxMeSessionCount() : PchInfoLib.h
  • GetPchMaxPcieClockNum() : PchInfoLib.h
  • GetPchMaxPcieClockReqNum() : PchInfoLib.h
  • GetPchMaxPcieControllerNum() : PchInfoLib.h
  • GetPchMaxPciePortNum() : PchInfoLib.h
  • GetPchMaxSerialIoI2cControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoI3cControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoSpiChipSelectsNum() : PchInfoLib.h
  • GetPchMaxSerialIoSpiControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoUartControllersNum() : PchInfoLib.h
  • GetPchMaxThcCount() : PchInfoLib.h
  • GetPchMaxTypeCPortNum() : PchInfoLib.h
  • GetPchPcieRpDevFun() : PchPcieRpLib.h
  • GetPchPcieRpNumber() : PchPcieRpLib.h
  • GetPchRstConfig() : PchPolicyLib.h
  • GetPchSataConfig() : PchPolicyLib.h
  • GetPchSpiDmiTarget() : PchInfoLib.h
  • GetPchUsb2MaxPhysicalPortNum() : PchInfoLib.h
  • GetPchUsb3MaxPhysicalPortNum() : PchInfoLib.h
  • GetPchUsbrKvmPortNum() : PchInfoLib.h
  • GetPchUsbrStoragePortNum() : PchInfoLib.h
  • GetPchXhciMaxUsb2PortNum() : PchInfoLib.h
  • GetPchXhciMaxUsb3PortNum() : PchInfoLib.h
  • GetPcieImrPortLocation() : PeiPcieRpLib.h
  • GetPcieImrPortNumber() : PeiPcieRpLib.h
  • GetPcieImrSize() : PeiPcieRpLib.h
  • GetRegBarSize() : HostBridgeInfoLib.h
  • GetRevisionTable() : CpuPlatformLib.h
  • GetRpSbiPid() : PchPcieRpLib.h
  • GetRsePassword() : DxeAmtHeciLib.h
  • GetRsePasswordV2() : DxeAmtHeciLib.h
  • GetSamFwInfo() : HostBridgeInfoLib.h
  • GetSataAbarSize() : SataLib.h
  • GetSataAhciBase() : SataLib.h
  • GetSataPortPresentStatus() : SataLib.h
  • GetSerialIoBar() : SerialIoAccessLib.h
  • GetSerialIoI2cPciCfg() : SerialIoAccessLib.h
  • GetSerialIoSpiPciCfg() : SerialIoAccessLib.h
  • GetSerialIoUartPciCfg() : SerialIoAccessLib.h
  • GetSkuString() : CpuPlatformLib.h
  • GetSpsEndOfPostStatus() : MeUtilsLib.h
  • GetSubCStateSupported() : CpuPlatformLib.h
  • GetSupportedCpuFeatures() : CpuPlatformLib.h
  • GetSupportedSocNorthAtomCores() : CpuPlatformLib.h
  • GetSystemTime() : SystemTimeLib.h
  • GetTbtDma0FuncNumber() : TcssInfoLib.h
  • GetTbtDmaBusNumber() : TcssInfoLib.h
  • GetTbtDmaDevNumber() : TcssInfoLib.h
  • GetVtdBaseAddress() : VtdInfoLib.h
  • GetVtdOffset() : VtdInfoLib.h
  • gHeciAccessPpiGuid : HeciAccessPpi.h
  • gHeciAccessProtocolGuid : HeciAccessProtocol.h
  • gHeciControlPpiGuid : HeciControlPpi.h
  • gHeciControlProtocolGuid : HeciControlProtocol.h
  • gHeciPpiGuid : HeciPpi.h
  • gITbtPolicyProtocolGuid : ITbtPolicy.h
  • gMbpSensitivePpiGuid : MbpSensitivePpi.h
  • GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME : GopComponentName2.h
  • GOP_COMPONENT_NAME2_GET_DRIVER_NAME : GopComponentName2.h
  • GOP_COMPONENT_NAME2_GET_DRIVER_VERSION : GopComponentName2.h
  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_NATIVE_PAD : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_PAD_OWN : GpioLib.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GPIO_SUPPORT : HybridGraphicsConfig.h
  • GPIO_VER2_H_CHIPSET_ID : GpioPinsVer2H.h
  • GPIO_VER2_H_GROUP_GPP_A : GpioPinsVer2H.h
  • GPIO_VER2_H_SPI0_IO_2 : GpioPinsVer2H.h
  • GPIO_VER2_LP_CHIPSET_ID : GpioPinsVer2Lp.h
  • GPIO_VER2_LP_GPP_B0 : GpioPinsVer2Lp.h
  • GPIO_VER2_LP_GROUP_GPP_B : GpioPinsVer2Lp.h
  • GPIO_VER4_S_CHIPSET_ID : GpioPinsVer4S.h
  • GPIO_VER4_S_GPP_I0 : GpioPinsVer4S.h
  • GPIO_VER4_S_GROUP_GPP_I : GpioPinsVer4S.h
  • GpioCheckFor2Tier() : GpioLib.h
  • GpioClearAllGpiSmiSts() : GpioLib.h
  • GpioClearGpiGpeSts() : GpioLib.h
  • GpioClearGpiSmiSts() : GpioLib.h
  • GpioConfigurePads() : GpioLib.h
  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDisableAllGpiSmi() : GpioLib.h
  • GpioDswReset : GpioConfig.h
  • GpioGetGpeNumber() : GpioLib.h
  • GpioGetGpiGpeSts() : GpioLib.h
  • GpioGetGpioPadFromGroupAndPadNumber() : GpioNativeLib.h
  • GpioGetGpioPadFromGroupIndexAndPadNumber() : GpioNativeLib.h
  • GpioGetGpiSmiNum() : GpioLib.h
  • GpioGetGpiSmiSts() : GpioLib.h
  • GpioGetGroupDwToGpeDwX() : GpioLib.h
  • GpioGetGroupFromGpioPad() : GpioNativeLib.h
  • GpioGetGroupFromGroupIndex() : GpioNativeLib.h
  • GpioGetGroupIndexFromGpioPad() : GpioNativeLib.h
  • GpioGetGroupIndexFromGroup() : GpioNativeLib.h
  • GpioGetGroupName() : GpioLib.h
  • GpioGetGroupToGpeDwX() : GpioLib.h
  • GpioGetHighestGroup() : GpioNativeLib.h
  • GpioGetHostSwOwnershipForGroupDw() : GpioLib.h
  • GpioGetHostSwOwnershipForPad() : GpioLib.h
  • GpioGetInputInversion() : GpioLib.h
  • GpioGetInputValue() : GpioLib.h
  • GpioGetLowestGroup() : GpioNativeLib.h
  • GpioGetNativeSignalName() : GpioLib.h
  • GpioGetNumberOfGroups() : GpioNativeLib.h
  • GpioGetOutputValue() : GpioLib.h
  • GpioGetPadCfgLock() : GpioLib.h
  • GpioGetPadCfgLockForGroupDw() : GpioLib.h
  • GpioGetPadCfgLockTx() : GpioLib.h
  • GpioGetPadCfgLockTxForGroupDw() : GpioLib.h
  • GpioGetPadConfig() : GpioLib.h
  • GpioGetPadIoApicIrqNumber() : GpioLib.h
  • GpioGetPadName() : GpioLib.h
  • GpioGetPadNumberFromGpioPad() : GpioNativeLib.h
  • GpioGetPadOwnership() : GpioLib.h
  • GpioGetPadPerGroup() : GpioNativeLib.h
  • GpioGetPadResetConfig() : GpioLib.h
  • GpioGlobalReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioIsSataGpEnabled() : GpioNativeLib.h
  • GpioLockDefault : GpioConfig.h
  • GpioLockPadCfg() : GpioLib.h
  • GpioLockPadCfgForGroupDw() : GpioLib.h
  • GpioLockPadCfgTx() : GpioLib.h
  • GpioLockPadCfgTxForGroupDw() : GpioLib.h
  • GpioLockPads() : GpioLib.h
  • GpioLockTxLockCfgUnLock : GpioConfig.h
  • GpioLockTxUnLockCfgLock : GpioConfig.h
  • GpioMinGetPadCfgLock() : GpioLib.h
  • GpioMinGetPadCfgLockForGroupDw() : GpioLib.h
  • GpioMinGetPadCfgLockTx() : GpioLib.h
  • GpioMinGetPadCfgLockTxForGroupDw() : GpioLib.h
  • GpioMinLockPadCfg() : GpioLib.h
  • GpioMinLockPadCfgTx() : GpioLib.h
  • GpioMinUnlockPadCfg() : GpioLib.h
  • GpioMinUnlockPadCfgTx() : GpioLib.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateUnlock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPadConfigUnlock : GpioConfig.h
  • GpioPadLock : GpioConfig.h
  • GpioPadUnlock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioSetGroupDwToGpeDwX() : GpioLib.h
  • GpioSetGroupToGpeDwX() : GpioLib.h
  • GpioSetHostSwOwnershipForGroupDw() : GpioLib.h
  • GpioSetHostSwOwnershipForPad() : GpioLib.h
  • GpioSetInputInversion() : GpioLib.h
  • GpioSetOutputValue() : GpioLib.h
  • GpioSetPadConfig() : GpioLib.h
  • GpioSetPadElectricalConfig() : GpioLib.h
  • GpioSetPadInterruptConfig() : GpioLib.h
  • GpioSetPadResetConfig() : GpioLib.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h
  • GpioUnlockPadCfg() : GpioLib.h
  • GpioUnlockPadCfgForGroupDw() : GpioLib.h
  • GpioUnlockPadCfgTx() : GpioLib.h
  • GpioUnlockPadCfgTxForGroupDw() : GpioLib.h
  • gSaPolicyProtocolGuid : SaPolicy.h
  • gSmmBiosGuardProtocolGuid : Protocol/BiosGuard.h
  • gSsaBiosCallBacksPpiGuid : SsaPeiInit.h
  • GT_WAIT_TIMEOUT : GraphicsInfoLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- h -

  • H_CB_WW : HeciRegs.h
  • HandleTpmStartupFailureOnS3() : BootGuardLibVer1.h
  • HbmCapabilitiesRequest() : DxeMeLib.h
  • HbmClientDisconnect() : DxeMeLib.h
  • HbmGetClientProperties() : DxeMeLib.h
  • HbmGetFlowControlToken() : DxeMeLib.h
  • HbmHostClientConnect() : DxeMeLib.h
  • HbmHostEnumRequest() : DxeMeLib.h
  • HbmHostStop() : DxeMeLib.h
  • HbmHostVersion() : DxeMeLib.h
  • HbmMapRequest() : DxeMeLib.h
  • HbmSendFlowControlToken() : DxeMeLib.h
  • HbmUnmapRequest() : DxeMeLib.h
  • HdaDevNumber() : PchPciBdfLib.h
  • HdaFuncNumber() : PchPciBdfLib.h
  • HdaPciCfgBase() : PchPciBdfLib.h
  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h
  • HEAP_BIOS_SPEC_VER_ELEMENT : Txt.h
  • HEAP_BIOSACM_ELEMENT : Txt.h
  • HEAP_EXT_DATA_ELEMENT : Txt.h
  • HEAP_EXTDATA_TYPE_BIOS_SPEC_VER : Txt.h
  • HEAP_EXTDATA_TYPE_BIOSACM : Txt.h
  • HEAP_EXTDATA_TYPE_END : Txt.h
  • HECI_ACCESS : HeciAccessProtocol.h
  • HECI_ACCESS_GET_NEXT_HECI : HeciAccessProtocol.h
  • HECI_ACCESS_GET_PARAMETER : HeciAccessProtocol.h
  • HECI_API_VERSION : MeUtilsLib.h
  • HECI_CONTROL : HeciControlProtocol.h
  • HECI_CONTROL_READ_FIRMWARE_STATUS : HeciControlProtocol.h
  • HECI_CONTROL_RECEIVE : HeciControlProtocol.h
  • HECI_CONTROL_RESET : HeciControlProtocol.h
  • HECI_CONTROL_SEND : HeciControlProtocol.h
  • HECI_CONTROL_SEND_AND_RECEIVE : HeciControlProtocol.h
  • HECI_DEFAULT_PCH_ID : HeciControlProtocol.h
  • HECI_DEFAULT_RETRY_NUMBER : HeciControlProtocol.h
  • HECI_GET_ME_MODE : HeciProtocol.h
  • HECI_GET_ME_STATUS : HeciProtocol.h
  • HECI_HBM_MESSAGE_ADDR : CoreBiosMsg.h
  • HECI_INIT : HeciProtocol.h
  • HECI_MAX_ME_FIXED_ADDR : CoreBiosMsg.h
  • HECI_NAME_MAP : MeRegs.h
  • HECI_PPI_REVISION : HeciPpi.h
  • HECI_PROTOCOL : HeciProtocol.h
  • HECI_READ_MESSAGE : HeciProtocol.h
  • HECI_REINIT : HeciProtocol.h
  • HECI_RESET : HeciProtocol.h
  • HECI_RESET_WAIT : HeciProtocol.h
  • HECI_SEND_MESSAGE : HeciProtocol.h
  • HECI_SENDWACK : HeciProtocol.h
  • HeciArbSvnCommitMsg() : DxeMeLib.h
  • HeciArbSvnGetInfoMsg() : DxeMeLib.h
  • HeciAssetUpdateFwMsg() : DxeMeLib.h
  • HeciClearInvocationCode() : DxeMeLib.h
  • HeciCommitFilesMsg() : DxeMeLib.h
  • HeciCoreBiosDoneMsg() : DxeMeLib.h
  • HeciDnxReqClear() : DxeMeLib.h
  • HeciEnable : MeRegs.h
  • HeciFwCapsGetRuleData() : DxeMeLib.h
  • HeciFwCapsSetRuleData() : DxeMeLib.h
  • HeciFwFeatureStateOverride() : DxeMeLib.h
  • HeciGetAmtBiosSyncInfo() : DxeMeLib.h
  • HeciGetCpuTypeChange() : DxeMeLib.h
  • HeciGetDamState() : DxeMeLib.h
  • HeciGetErLog() : DxeMeLib.h
  • HeciGetFipsMode() : DxeMeLib.h
  • HeciGetFwAvailableFeatures() : DxeMeLib.h
  • HeciGetFwCapsSkuMsg() : DxeMeLib.h
  • HeciGetFwFeatureStateMsg() : DxeMeLib.h
  • HeciGetFwUpdateState() : DxeMeLib.h
  • HeciGetFwVersionMsg() : DxeMeLib.h
  • HeciGetHerDataSha384() : MeChipsetLib.h
  • HeciGetIccClockSettings() : DxeMeLib.h
  • HeciGetIccProfile() : DxeMeLib.h
  • HeciGetImageFwVersionMsg() : DxeMeLib.h
  • HeciGetInvocationCode() : DxeMeLib.h
  • HeciGetIsUserConsentRequired() : DxeMeLib.h
  • HeciGetMeasuredBootState() : DxeMeLib.h
  • HeciGetMkhiVersion() : PeiMeLib.h , DxeMeLib.h
  • HeciGetMoffOverrideState() : DxeMeLib.h
  • HeciGetOemTagMsg() : DxeMeLib.h
  • HeciGetPlatformTypeMsg() : DxeMeLib.h
  • HeciGetPlatIdSupportedState() : DxeMeLib.h
  • HeciGetPsrRecord() : DxeMeLib.h
  • HeciGetRpmcStatus() : DxeMeLib.h
  • HeciGetSouthClinkState() : DxeMeLib.h
  • HeciGetUnconfigOnRtcClearDisableMsg() : DxeMeLib.h
  • HeciGetUnconfigureStatus() : DxeMeLib.h
  • HeciGetUpidFeatureState() : DxeMeLib.h
  • HeciGetUpidOsControlState() : DxeMeLib.h
  • HeciGetUpidPlatformId() : DxeMeLib.h
  • HeciGetUpidRefurbishCounter() : DxeMeLib.h
  • HeciGetUserCapabilitiesState() : DxeMeLib.h
  • HeciHmrfpoDisable() : DxeMeLib.h
  • HeciHmrfpoEnable() : DxeMeLib.h
  • HeciHmrfpoGetStatus() : DxeMeLib.h
  • HeciHmrfpoLock() : DxeMeLib.h
  • HeciIsMebxPasswordModified() : DxeMeLib.h
  • HeciModifyMebxPassword() : DxeMeLib.h
  • HeciPdtUnlockMsg() : DxeMeLib.h
  • HeciPdtUpdateMsg() : DxeMeLib.h
  • HeciReadFileExMsg() : DxeMeLib.h
  • HeciSendCbmResetRequest() : DxeMeLib.h
  • HeciSendChassisIntrDetEvent() : DxeMeLib.h
  • HeciSendCpuBrandClassFuse() : DxeMeLib.h
  • HeciSendWithAck() : MeUtilsLib.h
  • HeciSetAcmTpmData() : DxeMeLib.h
  • HeciSetCpuTypeChangeUserResponse() : DxeMeLib.h
  • HeciSetDamState() : DxeMeLib.h
  • HeciSetFileExMsg() : DxeMeLib.h
  • HeciSetFipsMode() : DxeMeLib.h
  • HeciSetFwEnabledFeatures() : DxeMeLib.h
  • HeciSetFwUpdateState() : DxeMeLib.h
  • HeciSetIccClockSettings() : DxeMeLib.h
  • HeciSetIccProfile() : DxeMeLib.h
  • HeciSetInvocationCode() : DxeMeLib.h
  • HeciSetManufacturingMeResetAndHalt() : DxeMeLib.h
  • HeciSetMeasuredBootState() : DxeMeLib.h
  • HeciSetMeDisableMsg() : DxeMeLib.h
  • HeciSetMeEnableMsg() : DxeMeLib.h
  • HeciSetMoffOverrideState() : DxeMeLib.h
  • HeciSetSouthClinkState() : DxeMeLib.h
  • HeciSetUnconfigOnRtcClearDisableMsg() : DxeMeLib.h
  • HeciSetUpidFeatureState() : DxeMeLib.h
  • HeciSetUpidOsControlState() : DxeMeLib.h
  • HeciSetUserCapabilitiesState() : DxeMeLib.h
  • HeciUnconfigWithouPwd() : DxeMeLib.h
  • HeciUpdateUpidOemPlatformId() : DxeMeLib.h
  • HeciValidateMebxPassword() : DxeMeLib.h
  • HID_ENABLE_AFTER_RESET : Thc.h
  • HID_GET_FEATURE : Thc.h
  • HID_SET_FEATURE : Thc.h
  • HidOverSpi : ThcConfig.h
  • HMRFPO_DISABLED : MkhiMsgs.h
  • HMRFPO_ENABLE_CMD_ID : MkhiMsgs.h
  • HMRFPO_ENABLE_SUCCESS : MkhiMsgs.h
  • HMRFPO_LOCK_SUCCESS : MkhiMsgs.h
  • HWA_TABLE_TYPE_INDEX : DxeMeLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- i -

  • ICC_CMD : BupMsgs.h
  • ICC_COMMAND_ID : IccMsgs.h
  • ICC_CURRENT_SETTINGS : IccMsgs.h
  • ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE : IccMsgs.h
  • ICC_PROGRAMMING_TYPE_DYNAMIC : IccMsgs.h
  • ICC_PROGRAMMING_TYPE_PERSISTENT : IccMsgs.h
  • ICC_READ_FROM_MPHY_CMD : IccMsgs.h
  • ICC_SSC_MODE_DOWN : IccMsgs.h
  • ICC_WHITE_MOUNTAIN_PHY_CLK : IccMsgs.h
  • IehDevNumber() : PchPciBdfLib.h
  • IehFuncNumber() : PchPciBdfLib.h
  • IehPciCfgBase() : PchPciBdfLib.h
  • IgfxCmdRegEnabled() : GraphicsInfoLib.h
  • InstallHeciPpi() : PeiMeLib.h
  • InstallStallPpi() : StallPpiLib.h
  • INTEL_IANA_SWAP32 : AsfProtocol.h
  • InternalAsciiToUpper() : DxeJhiSupportLib.h
  • InternalWaitforCommandCompletion() : TbtCommonLib.h
  • IO_TRAP_EX_DISPATCH_CALLBACK : IoTrapExDispatch.h
  • IO_TRAP_EX_DISPATCH_REGISTER : IoTrapExDispatch.h
  • IO_TRAP_EX_DISPATCH_TYPE : IoTrapExDispatch.h
  • IO_TRAP_EX_DISPATCH_UNREGISTER : IoTrapExDispatch.h
  • IS_VER1_PCH_SOL_DEVICE_ID : MeRegs.h
  • IS_WDT_ENABLED : Protocol/Wdt.h
  • IS_WDT_REQUIRED : Protocol/Wdt.h
  • IsAdlPch() : PchInfoLib.h
  • IsAudioInterfaceSupported() : PchInfoLib.h
  • IsBiosGuardEnabled() : CpuPlatformLib.h
  • IsBootGuardSupported() : BootGuardLibVer1.h
  • IsC6dramSupported() : CpuPlatformLib.h
  • IsCiraAvailable() : DxeMeLib.h
  • IsConfigTdpSupported() : CpuPlatformLib.h
  • IsCoreRatioLimitSupported() : CpuPlatformLib.h
  • IsCpuDebugDisabled() : MeFwStsLib.h
  • IsCpuDmiEnabled() : CpuDmiInfoLib.h
  • IsDesktopSku() : SaPlatformLib.h
  • IsDisplayOnlySku() : GraphicsInfoFruLib.h
  • IsDisplayPresent() : GraphicsInfoFruLib.h
  • IsDmiGen4Supported() : CpuDmiInfoLib.h
  • IsDoorbellRangeValid() : GraphicsInfoLib.h
  • IsDsmBaseAndImrMemoryConsistent() : GraphicsInfoLib.h
  • IsEbgPch() : PchInfoLib.h
  • IsEdramEnable() : CpuPlatformLib.h
  • IsEnergyEfficientTurboSupported() : CpuPlatformLib.h
  • IsEspiEnabled() : EspiLib.h
  • IsEspiSecondSlaveSupported() : EspiLib.h
  • IsEspiSlaveChannelSupported() : EspiLib.h
  • IsExtendedBiosRangeDecodeSupported() : PchInfoLib.h
  • IsExtendedMeasuredBootEnabled() : DxeMeLib.h
  • IsGbeEnabled() : GbeLib.h
  • IsGbePresent() : GbeLib.h
  • IsGbeRegionValid() : GbeLib.h
  • IsGcdRc6Locked() : GraphicsInfoLib.h
  • IsGcdRc6RangeValid() : GraphicsInfoLib.h
  • IsGsmBaseAndImrMemoryConsistent() : GraphicsInfoLib.h
  • IsGtPresent() : GraphicsInfoFruLib.h
  • IsHaloSku() : SaPlatformLib.h
  • IsHashAlgSupportedInHashAlgorithmMask() : Tpm2CommandLib.h
  • IshDevNumber() : PchPciBdfLib.h
  • IsHeciDeviceFunction() : MeChipsetLib.h
  • IsHfpgaEnvironment() : PreSiliconEnvDetectLib.h
  • IshFuncNumber() : PchPciBdfLib.h
  • IshPciCfgBase() : PchPciBdfLib.h
  • IsHSLEEnvironment() : PreSiliconEnvDetectLib.h
  • IsHSLEEnvironment_UPF() : PreSiliconEnvDetectLib.h
  • IsHwpSupported() : CpuPlatformLib.h
  • IsHyperThreadingSupported() : CpuPlatformLib.h
  • IsIGfxSupported() : GraphicsInfoLib.h
  • IsInSmm() : MeUtilsLib.h
  • IsIntelProcessorTraceSupported() : CpuPlatformLib.h
  • IsIshPresent() : IshInfoLib.h
  • IsIshSupported() : IshInfoLib.h
  • IsItbmSupported() : CpuPlatformLib.h
  • IsLpmSupported() : CpuPlatformLib.h
  • IsMediaPresent() : GraphicsInfoFruLib.h
  • IsMediaRc6Locked() : GraphicsInfoLib.h
  • IsMediaRc6RangeValid() : GraphicsInfoLib.h
  • IsMobileSku() : SaPlatformLib.h
  • IsOcSupported() : CpuPlatformLib.h
  • IsP2sb20bPcrSupported() : PchInfoLib.h
  • IsPavpBitLocked() : GraphicsInfoLib.h
  • IsPchChipsetInitSyncSupported() : PchInfoLib.h
  • IsPchEmmcSupported() : PchInfoLib.h
  • IsPchH() : PchInfoLib.h
  • IsPchLinkDmi() : CpuDmiInfoLib.h
  • IsPchLp() : PchInfoLib.h
  • IsPchM() : PchInfoLib.h
  • IsPchN() : PchInfoLib.h
  • IsPchP() : PchInfoLib.h
  • IsPchPSOnSupported() : PchInfoLib.h
  • IsPchS() : PchInfoLib.h
  • IsPchSdCardSupported() : PchInfoLib.h
  • IsPchServer() : PchInfoLib.h
  • IsPchSupported() : PchInfoLib.h
  • IsPchThcHidModeSupported() : PchInfoLib.h
  • IsPchThcSupported() : PchInfoLib.h
  • IsPchWithFdmi() : PchInfoLib.h
  • IsPchWithOpdmi() : PchInfoLib.h
  • IsPchWithPdmi() : PchInfoLib.h
  • IsPcieImrEnabled() : PeiPcieRpLib.h
  • IsPfatEnabled() : CpuPlatformLib.h
  • IsPolicyDefaultCheckRequired() : PeiSiPolicyUpdateLib.h
  • IsPpinFeatureAvailable() : CpuPlatformLib.h
  • IsRc6Locked() : GraphicsInfoLib.h
  • IsRc6RangeValid() : GraphicsInfoLib.h
  • IsRemappingSupportedOnSata() : SataSocLib.h
  • IsS3m2Ibl() : PchInfoLib.h
  • IsSaDevice4Enable() : HostBridgeInfoLib.h
  • IsSamEnabled() : HostBridgeInfoLib.h
  • IsSamplePart() : CpuPlatformLib.h
  • IsSataPowerGatingSupported() : SataSocLib.h
  • IsSaVrSupport() : CpuPlatformLib.h
  • IsSecondaryThread() : CpuPlatformLib.h
  • IsSerialIoI2cDeviceId() : SerialIoAccessLib.h
  • IsSerialIoI2cFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoSpiFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoUartFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoUartInPciMode() : SerialIoUartLib.h
  • IsServerSku() : SaPlatformLib.h
  • IsSimicsEnvironment() : PreSiliconEnvDetectLib.h
  • IsSmxSupported() : CpuPlatformLib.h
  • IsTccSku() : TccLib.h
  • IsTimedMwaitSupported() : CpuPlatformLib.h
  • IsTmeActivated() : TmeInfoLib.h
  • IsTmeActivateLocked() : TmeInfoLib.h
  • IsTmeSupported() : CpuPlatformLib.h
  • IsTsegBaseAndImrMemoryConsistent() : HostBridgeInfoLib.h
  • IsTsnPresent() : TsnLib.h
  • IsTurboModeSupported() : CpuPlatformLib.h
  • IsValiduCodeEntry() : CpuPlatformLib.h
  • IsWoPcmBaseRegistersConsistent() : GraphicsInfoLib.h
  • IsWoPcmRangeValid() : GraphicsInfoLib.h
  • IsXETdcTdpLimitSupported() : CpuPlatformLib.h
  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_POLICY_PROTOCOL_REVISION : ITbtPolicy.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h
  • ITbtAddConfigBlocks() : PeiITbtPolicyLib.h
  • ITbtGetConfigBlockTotalSize() : PeiITbtPolicyLib.h
  • ITbtInstallPolicyProtocol() : DxeITbtPolicyLib.h
  • ITbtPrintDxePolicyConfig() : DxeITbtPolicyLib.h
  • ITbtPrintPolicy() : PeiITbtPolicyLib.h
  • ItssGet8254ClockGateState() : ItssLib.h
  • ItssSet8254ClockGateState() : ItssLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- j -

  • JHI_APPID_NOT_EXIST : JhiProtocol.h
  • JHI_APPLET_AUTHENTICATION_FAILURE : JhiProtocol.h
  • JHI_APPLET_FATAL : JhiProtocol.h
  • JHI_APPLET_NOT_INSTALLED : JhiProtocol.h
  • JHI_APPLET_PROPERTY_NOT_SUPPORTED : JhiProtocol.h
  • JHI_APPLET_TIMEOUT : JhiProtocol.h
  • JHI_CLOSE_SESSION : JhiProtocol.h
  • JHI_COMMS_ERROR : JhiProtocol.h
  • JHI_CREATE_SESSION : JhiProtocol.h
  • JHI_DELETE_FROM_REPOSITORY_FAILURE : JhiProtocol.h
  • JHI_ERROR_LOGGING : JhiProtocol.h
  • JHI_ERROR_REGISTRY : JhiProtocol.h
  • JHI_ERROR_REPOSITORY_NOT_FOUND : JhiProtocol.h
  • JHI_EVENTS_NOT_SUPPORTED : JhiProtocol.h
  • JHI_FILE_ERROR_AUTH : JhiProtocol.h
  • JHI_FILE_ERROR_COPY : JhiProtocol.h
  • JHI_FILE_ERROR_DELETE : JhiProtocol.h
  • JHI_FILE_ERROR_OPEN : JhiProtocol.h
  • JHI_FILE_IDENTICAL : JhiProtocol.h
  • JHI_FILE_INVALID : JhiProtocol.h
  • JHI_FILE_MISSING_SRC : JhiProtocol.h
  • JHI_FILE_NOT_FOUND : JhiProtocol.h
  • JHI_FILE_UUID_MISMATCH : JhiProtocol.h
  • JHI_FIRMWARE_OUT_OF_RESOURCES : JhiProtocol.h
  • JHI_GET_APPLET_PROPERTY : JhiProtocol.h
  • JHI_GET_SESSION_INFO : JhiProtocol.h
  • JHI_GET_SESSIONS_COUNT : JhiProtocol.h
  • JHI_GET_VERSION_INFO : JhiProtocol.h
  • JHI_IAC_SERVER_INTERNAL_SESSIONS_EXIST : JhiProtocol.h
  • JHI_IAC_SERVER_SESSION_EXIST : JhiProtocol.h
  • JHI_ILLEGAL_VALUE : JhiProtocol.h
  • JHI_INITIALIZE : JhiProtocol.h
  • JHI_INSTALL_CONTENT : JhiProtocol.h
  • JHI_INSTALL_FAILED : JhiProtocol.h
  • JHI_INSTALL_FAILURE_SESSIONS_EXISTS : JhiProtocol.h
  • JHI_INSTALL_FILE : JhiProtocol.h
  • JHI_INSUFFICIENT_BUFFER : JhiProtocol.h
  • JHI_INTERNAL_ERROR : JhiProtocol.h
  • JHI_INVALID_APPLET_GUID : JhiProtocol.h
  • JHI_INVALID_BUFFER_SIZE : JhiProtocol.h
  • JHI_INVALID_COMM_BUFFER : JhiProtocol.h
  • JHI_INVALID_COMMAND : JhiProtocol.h
  • JHI_INVALID_FILE_EXTENSION : JhiProtocol.h
  • JHI_INVALID_HANDLE : JhiProtocol.h
  • JHI_INVALID_INIT_BUFFER : JhiProtocol.h
  • JHI_INVALID_INSTALL_FILE : JhiProtocol.h
  • JHI_INVALID_PACKAGE_FORMAT : JhiProtocol.h
  • JHI_INVALID_PARAMS : JhiProtocol.h
  • JHI_INVALID_SESSION_HANDLE : JhiProtocol.h
  • JHI_INVALID_SPOOLER : JhiProtocol.h
  • JHI_JOM_ERROR_DOWNLOAD : JhiProtocol.h
  • JHI_JOM_ERROR_UNLOAD : JhiProtocol.h
  • JHI_JOM_FATAL : JhiProtocol.h
  • JHI_JOM_OVERFLOW : JhiProtocol.h
  • JHI_MAX_INSTALLED_APPLETS_REACHED : JhiProtocol.h
  • JHI_MAX_SESSIONS_REACHED : JhiProtocol.h
  • JHI_MAX_SHARED_SESSION_REACHED : JhiProtocol.h
  • JHI_NO_CONNECTION_TO_FIRMWARE : JhiProtocol.h
  • JHI_PROTOCOL_REVISION : JhiProtocol.h
  • JHI_READ_FROM_FILE_FAILED : JhiProtocol.h
  • JHI_SEND_ADN_RECEIVE : JhiProtocol.h
  • JHI_SERVICE_INVALID_GUID : JhiProtocol.h
  • JHI_SERVICE_UNAVAILABLE : JhiProtocol.h
  • JHI_SESSION_ALREADY_REGSITERED : JhiProtocol.h
  • JHI_SESSION_NOT_REGISTERED : JhiProtocol.h
  • JHI_SHARED_SESSION_NOT_SUPPORTED : JhiProtocol.h
  • JHI_SPOOLER_NOT_FOUND : JhiProtocol.h
  • JHI_SUCCESS : JhiProtocol.h
  • JHI_SVL_CHECK_FAIL : JhiProtocol.h
  • JHI_UNINIT : JhiProtocol.h
  • JHI_UNINSTALL : JhiProtocol.h
  • JHI_UNINSTALL_FAILURE_SESSIONS_EXISTS : JhiProtocol.h
  • JHI_UNKNOWN_ERROR : JhiProtocol.h
  • JHI_VM_DLL_FILE_NOT_FOUND : JhiProtocol.h
  • JHI_VM_DLL_VERIFY_FAILED : JhiProtocol.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- k -

  • KVM_MAX_WAIT_TIME : AsfMsgs.h
  • KVM_STALL_1_SECOND : AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- l -

  • LAN_INTERFACE : AmthiMsgs.h
  • LoadMemConfigDefault() : PeiMemPolicyLib.h
  • LoadMemConfigNoCrcDefault() : PeiMemPolicyLib.h
  • LOCAL_FW_UPDATE : MkhiMsgs.h
  • LOCK_POWER_BUTTON : IndustryStandardAsf.h
  • LpcDevNumber() : PchPciBdfLib.h
  • LpcFuncNumber() : PchPciBdfLib.h
  • LpcPciCfgBase() : PchPciBdfLib.h
  • LTR_MAX_NON_SNOOP_LATENCY_VALUE : SaPolicy.h
  • LTR_MAX_SNOOP_LATENCY_VALUE : SaPolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- m -

  • MAILBOX_READ_TIMEOUT : CpuMailboxLib.h
  • MAILBOX_WAIT_STALL : CpuMailboxLib.h
  • MAILBOX_WAIT_TIMEOUT : CpuMailboxLib.h
  • MailboxRead() : CpuMailboxLib.h
  • MailboxWrite() : CpuMailboxLib.h
  • MAX_ADDRESS_LENGTH : AmthiMsgs.h
  • MAX_BIOSGUARD_LOG_PAGE : BiosGuard.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_FWSTS_REG : FwStsSmbiosTable.h
  • MAX_HASH_ENTRIES : AmthiMsgs.h
  • MAX_INTERFACE_ID : AmthiMsgs.h
  • MAX_NUM_ICC_PROFILES : IccMsgs.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MAX_PKG_C_STATE : CpuPowerMgmtTestConfig.h
  • MAX_PWR_PKG_COUNT : AmthiMsgs.h
  • MAX_SFAM_COUNT : BiosGuard.h
  • MAX_SKU_BITMAP : MkhiMsgs.h
  • MAX_SPD_SAVE : MemInfoHob.h
  • MaxSataControllerNum() : SataSocLib.h
  • MaxSataPortNum() : SataSocLib.h
  • MAXSEG : AmthiMsgs.h
  • MB_POWER_LIMIT1_TIME_DEFAULT : CpuPowerMgmt.h
  • MBP_DATA_REVISION : MeBiosPayloadData.h
  • MBP_ITEM_FLAGS : MeBiosPayloadData.h
  • MBP_SENSITIVE_PPI_REVISION : MbpSensitivePpi.h
  • MbpItemFlagRuntime : MeBiosPayloadData.h
  • MbpItemFlagSensitive : MeBiosPayloadData.h
  • MbpItemFlagStoreToNvm : MeBiosPayloadData.h
  • MCA_DAM_FILE_SIZE : MkhiMsgs.h
  • MCA_READ_FILE_CMD : MkhiMsgs.h
  • ME_DEVICE : MeChipsetLib.h
  • ME_DISABLE : MkhiMsgs.h
  • ME_ERROR_MSG_ID : MeDxeConfig.h
  • ME_EWL_SEVERITY : MeEwlLib.h
  • ME_FVI_INDEX : SiFvi.h
  • ME_FVI_STRING : SiFvi.h
  • ME_GET_RESET_TYPE : MePlatformGetResetType.h
  • ME_IMAGE_TYPE : MkhiMsgs.h
  • ME_PLATFORM_GET_RESET_TYPE_PROTOCOL : MePlatformGetResetType.h
  • ME_POLICY_PROTOCOL : MePolicy.h
  • ME_POLICY_PROTOCOL_REVISION : MePolicy.h
  • ME_PWD_STATUS : MkhiMsgs.h
  • ME_PWDSTS_FAILURE : MkhiMsgs.h
  • ME_PWDSTS_INVALID_NEW_PWD : MkhiMsgs.h
  • ME_PWDSTS_INVALID_PWD : MkhiMsgs.h
  • ME_PWDSTS_OPERATION_NOT_ALLOWED : MkhiMsgs.h
  • ME_PWDSTS_OUT_OF_RESOURCES : MkhiMsgs.h
  • ME_PWDSTS_PWD_SUCCESS : MkhiMsgs.h
  • ME_REPORT_ERROR : MeDxeConfig.h
  • ME_SPECIAL_RESET_TYPES : MePlatformGetResetType.h
  • ME_STATUS_IS_ME_FW_BOOT_OPTIONS_PRESENT : MeState.h
  • ME_STATUS_IS_ME_FW_INIT_COMPLETE : MeState.h
  • ME_STATUS_ME_STATE_ONLY : MeState.h
  • ME_STATUS_WITH_ME_INIT_COMPLETE : MeState.h
  • ME_TYPE : MeTypeLib.h
  • ME_UNCONFIG_ERROR : MkhiMsgs.h
  • ME_UNCONFIG_FINISHED : MkhiMsgs.h
  • ME_UNCONFIG_IN_PROGRESS : MkhiMsgs.h
  • ME_UNCONFIG_NOT_IN_PROGRESS : MkhiMsgs.h
  • ME_UNCONFIG_ON_RTC_CLEAR_STATUS : MkhiMsgs.h
  • ME_UNCONFIG_TIMEOUT : MkhiMsgs.h
  • ME_UPDATE_SMBIOS : MeSmbiosUpdateProtocol.h
  • MeAddConfigBlocks() : PeiMePolicyLib.h
  • MeAddConfigBlocksPreMem() : PeiMePolicyLib.h
  • MeBiosGetMeMode() : MeUtilsLib.h
  • MeBiosGetMeStatus() : MeUtilsLib.h
  • MeBiosGetMeStatusRaw() : MeUtilsLib.h
  • MEBX_API_ENTRY_POINT : MebxProtocol.h
  • MEBX_CLEAR_SCREEN : MebxDisplayProtocol.h
  • MEBX_CONFIG_PROTOCOL_REVISION : MebxConfigProtocol.h
  • MEBX_CONFIGURE_SCREEN : MebxDisplayProtocol.h
  • MEBX_DISPLAY_ERROR : MebxDisplayProtocol.h
  • MEBX_DISPLAY_IMAGE : MebxDisplayProtocol.h
  • MEBX_DISPLAY_PROTOCOL : MebxDisplayProtocol.h
  • MEBX_DISPLAY_TEXT : MebxDisplayProtocol.h
  • MEBX_GET_SCREEN_RESOLUTION : MebxDisplayProtocol.h
  • MEBX_GET_USER_INPUT : MebxDisplayProtocol.h
  • MEBX_MSG_ID : MebxDisplayProtocol.h
  • MebxActivateRemoteConfiguration() : DxeMebxWrapperLib.h
  • MebxCfgGetIPv6LanIntStatus() : DxeMebxWrapperLib.h
  • MebxClearScreen() : DxeMebxDisplayWrapperLib.h
  • MebxCloseUserInitiatedConnection() : DxeMebxWrapperLib.h
  • MebxCompleteConfigurationRequest() : DxeMebxWrapperLib.h
  • MebxConfigureScreen() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayError() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayErrorId() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayText() : DxeMebxDisplayWrapperLib.h
  • MebxGetAmtPrivacyLevel() : DxeMebxWrapperLib.h
  • MebxGetConfigServerData() : DxeMebxWrapperLib.h
  • MebxGetConnectionStatus() : DxeMebxWrapperLib.h
  • MebxGetEndOfPostState() : DxeMebxWrapperLib.h
  • MebxGetFqdn() : DxeMebxWrapperLib.h
  • MebxGetHashedCertificates() : DxeMebxWrapperLib.h
  • MebxGetIdleTimeout() : DxeMebxWrapperLib.h
  • MebxGetIpv4Params() : DxeMebxWrapperLib.h
  • MebxGetKvmEnabled() : DxeMebxWrapperLib.h
  • MebxGetMebxPwdPolicy() : DxeMebxWrapperLib.h
  • MebxGetMeSetupAuditRecord() : DxeMebxWrapperLib.h
  • MebxGetPkiFqdnSuffix() : DxeMebxWrapperLib.h
  • MebxGetPlatformOptInPolicy() : DxeMebxWrapperLib.h
  • MebxGetPowerControlSettings() : DxeMebxWrapperLib.h
  • MebxGetProvisioningState() : DxeMebxWrapperLib.h
  • MebxGetRedirectionState() : DxeMebxWrapperLib.h
  • MebxGetZtcEnabledStatus() : DxeMebxWrapperLib.h
  • MebxIsAmthiInterfaceVersionSupported() : DxeMebxWrapperLib.h
  • MebxOpenUserInitiatedConnection() : DxeMebxWrapperLib.h
  • MebxPerformUnprovisioning() : DxeMebxWrapperLib.h
  • MebxReadUserInput() : DxeMebxDisplayWrapperLib.h
  • MebxSetAmtState() : DxeMebxWrapperLib.h
  • MebxSetCertificateHashState() : DxeMebxWrapperLib.h
  • MebxSetConfigServerData() : DxeMebxWrapperLib.h
  • MebxSetFqdn() : DxeMebxWrapperLib.h
  • MebxSetIdleTimeout() : DxeMebxWrapperLib.h
  • MebxSetIpv4Params() : DxeMebxWrapperLib.h
  • MebxSetKvmEnabled() : DxeMebxWrapperLib.h
  • MebxSetMebxPwdPolicy() : DxeMebxWrapperLib.h
  • MebxSetMebxState() : DxeMebxWrapperLib.h
  • MebxSetOptInState() : DxeMebxWrapperLib.h
  • MebxSetPkiFqdnSuffix() : DxeMebxWrapperLib.h
  • MebxSetSolStorageRedir() : DxeMebxWrapperLib.h
  • MebxSetZeroTouchEnabled() : DxeMebxWrapperLib.h
  • MebxStopRemoteConfiguration() : DxeMebxWrapperLib.h
  • MebxUpdatePowerPolicy() : DxeMebxWrapperLib.h
  • MeClientInRecovery() : MeUtilsLib.h
  • MeClientIsCorporate() : MeUtilsLib.h
  • MeClientIsReady() : MeUtilsLib.h
  • MeCoreBiosDoneEnabled() : DxeMeLib.h
  • MeCreatePolicyDefaults() : DxeMePolicyLib.h
  • MeDeviceControl() : MeChipsetLib.h
  • MeDeviceInit() : MeChipsetLib.h
  • MeEndOfPostEnabled() : DxeMeLib.h , PeiMeLib.h
  • MeEwlCommunicationFailures() : MeEwlLib.h
  • MeEwlStateFailures() : MeEwlLib.h
  • MeFwDowngradeSupported() : DxeMeLib.h
  • MeGetConfigBlockTotalSize() : PeiMePolicyLib.h
  • MeGetConfigBlockTotalSizePreMem() : PeiMePolicyLib.h
  • MeGetHeciBarAddress() : PeiMeLib.h
  • MeHeci2Enabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciD0I3Enabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciFullTrace() : DxeMeLib.h , PeiMeLib.h
  • MeHeciMessageCheckEnabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciTimeoutsEnabled() : DxeMeLib.h , PeiMeLib.h
  • MeInstallPolicyProtocol() : DxeMePolicyLib.h
  • MeIsAfterEndOfPost() : DxeMeLib.h , PeiMeLib.h
  • MeIsEnforceEDebugModeEnabled() : PeiMeLib.h
  • MeIsInRecovery() : MeUtilsLib.h
  • MEM_CFG_MAX_CONTROLLERS : MemoryConfig.h
  • MeMbpHobSkipped() : PeiMeLib.h
  • MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING : MemoryDxeConfig.h
  • MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING : MemoryDxeConfig.h
  • MEMORY_DXE_CONFIG_REVISION : MemoryDxeConfig.h
  • MePrintPolicyPpi() : PeiMePolicyLib.h
  • MePrintPolicyPpiPreMem() : PeiMePolicyLib.h
  • MePrintPolicyProtocol() : DxeMePolicyLib.h
  • MEPWDID_ME_BIOS_EXT : MkhiMsgs.h
  • MEPWDMGMT_PWD_MAX_SIZE : MkhiMsgs.h
  • MEPWDMGMT_PWD_MIN_SIZE : MkhiMsgs.h
  • MeReportError() : DxeMeLib.h
  • MeRestoreBars() : MeChipsetLib.h
  • MeSaveBars() : MeChipsetLib.h
  • MeServedrPrintPolicyPpi() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemAddConfigBlocks() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemGetConfigBlockTotalSize() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemPrintPolicyPpi() : PeiMeServerPreMemPolicyLib.h
  • MeSetEndOfPostDone() : DxeMeLib.h , PeiMeLib.h
  • MeSpsInRecovery() : MeUtilsLib.h
  • MeSpsIsNm() : MeUtilsLib.h
  • MeSpsIsReady() : MeUtilsLib.h
  • MeTypeGet() : MeTypeLib.h
  • MeTypeIsClient() : MeTypeLib.h
  • MeTypeIsDfx() : MeTypeLib.h
  • MeTypeIsDisabled() : MeTypeLib.h
  • MeTypeIsIgnition() : MeTypeLib.h
  • MeTypeIsSps() : MeTypeLib.h
  • MeTypeShowDebug() : MeTypeLib.h
  • MFT_KEY_USAGE : MkhiMsgs.h
  • MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST : MkhiMsgs.h
  • MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST : MkhiMsgs.h
  • MIN_SFAM_COUNT : BiosGuard.h
  • MKHI_CBM_GROUP_ID : MkhiMsgs.h
  • MKHI_MSG_VERSION_MAJOR : MkhiMsgs.h
  • MmPciBase() : MmPciLib.h
  • MPHY_READ_FROM_MPHY_CMD : BupMsgs.h
  • MRC_BOOT_MODE : MemInfoHob.h
  • MRC_MAX_RCOMP_TARGETS : MemoryConfig.h
  • MrcAddConfigBlocksPreMem() : PeiMemPolicyLib.h
  • MrcBootModeDelim : MemInfoHob.h
  • MrcBootModeMax : MemInfoHob.h
  • MrcGetConfigBlockTotalSizePreMem() : PeiMemPolicyLib.h
  • MrcLoadSamplePolicyPreMem() : PeiMemPolicyLib.h
  • MrcPrintPolicyPpiPreMem() : PeiMemPolicyLib.h
  • mSecondsToMsrValueMapTable : CpuPlatformLib.h
  • MSR_ACE_SPI_COMMAND : CommonMsr.h
  • MSR_ACE_SPI_CONFIG : CommonMsr.h
  • MSR_ACE_SPI_DATA : CommonMsr.h
  • MSR_ACE_SPI_STATUS : CommonMsr.h
  • MSR_AET_BASE_ADDRESS : CommonMsr.h
  • MSR_AET_EVENT_CTRL : CommonMsr.h
  • MSR_AET_MISC_ENABLE : CommonMsr.h
  • MSR_AMRR_BASE_0_0 : CommonMsr.h
  • MSR_AMRR_BASE_1_1 : CommonMsr.h
  • MSR_AMRR_BASE_2_2 : CommonMsr.h
  • MSR_AMRR_BASE_3_3 : CommonMsr.h
  • MSR_AMRR_BASE_4_4 : CommonMsr.h
  • MSR_AMRR_MASK_0_0 : CommonMsr.h
  • MSR_AMRR_MASK_1_1 : CommonMsr.h
  • MSR_AMRR_MASK_2_2 : CommonMsr.h
  • MSR_AMRR_MASK_3_3 : CommonMsr.h
  • MSR_AMRR_MASK_4_4 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_0_0 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_1_1 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_2_2 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_3_3 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_4_4 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_5_5 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_6_6 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_7_7 : CommonMsr.h
  • MSR_ANC_FORCE_BOOT_POLICY_ENFORCED : CommonMsr.h
  • MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE : CommonMsr.h
  • MSR_ANC_SACM_INFO : CommonMsr.h
  • MSR_APIC_BASE : ArchMsr.h
  • MSR_AVRR_BASE : CommonMsr.h
  • MSR_BIOS_AVX_DIS : CommonMsr.h
  • MSR_BIOS_DEBUG : ArchMsr.h
  • MSR_BIOS_DONE : CommonMsr.h
  • MSR_BIOS_DYNAMIC_UPDATE_PTR : ArchMsr.h
  • MSR_BIOS_INFO_FLAGS : CommonMsr.h
  • MSR_BIOS_MAILBOX_DATA : CommonMsr.h
  • MSR_BIOS_MAILBOX_INTERFACE : CommonMsr.h
  • MSR_BIOS_PKG_CONFIG : CommonMsr.h
  • MSR_BIOS_SE_SVN : CommonMsr.h
  • MSR_BIOS_SIGN_ID : ArchMsr.h
  • MSR_BIOS_TME_KEY_0 : CommonMsr.h
  • MSR_BIOS_TME_KEY_1 : CommonMsr.h
  • MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG : CommonMsr.h
  • MSR_BIOS_UPDT_TRIG : ArchMsr.h
  • MSR_BIOS_UPGD_TRIG : ArchMsr.h
  • MSR_BNDCFGS : ArchMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_0 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_1 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_2 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_3 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_4 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_5 : CommonMsr.h
  • MSR_CC3_RCNTR : CommonMsr.h
  • MSR_CC7_RCNTR : CommonMsr.h
  • MSR_CLOAKING : CommonMsr.h
  • MSR_CLOCK_CST_CONFIG_CONTROL : CommonMsr.h
  • MSR_CLOCK_MODULATION : ArchMsr.h
  • MSR_CLOS_CONFIG : ArchMsr.h
  • MSR_CLR_PERF_LIMIT_REASONS : ArchMsr.h
  • MSR_COMPOUND_CTR_CTRL : CommonMsr.h
  • MSR_COMPOUND_PERF_CTR : CommonMsr.h
  • MSR_CONFIG_TDP_CONTROL : CommonMsr.h
  • MSR_CONFIG_TDP_LEVEL1 : CommonMsr.h
  • MSR_CONFIG_TDP_LEVEL2 : CommonMsr.h
  • MSR_CONFIG_TDP_NOMINAL : CommonMsr.h
  • MSR_COPY_LOCAL_TO_PLATFORM : ArchMsr.h
  • MSR_COPY_PLATFORM_TO_LOCAL : ArchMsr.h
  • MSR_COPY_STATUS : ArchMsr.h
  • MSR_CORE_C1_RESIDENCY : CommonMsr.h
  • MSR_CORE_C6_RESIDENCY_COUNTER : CommonMsr.h
  • MSR_CORE_CAPABILITIES : ArchMsr.h
  • MSR_CORE_MKTME_ACTIVATION : CommonMsr.h
  • MSR_CORE_SDC_RESIDENCY : CommonMsr.h
  • MSR_CORE_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_CORE_SMI_ERR_SRC : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0 : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1 : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_0_0 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_1_1 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_2_2 : CommonMsr.h
  • MSR_CORE_THREAD_COUNT : CommonMsr.h
  • MSR_CORE_UARCH_CTL : CommonMsr.h
  • MSR_COS_WAYS_0 : ArchMsr.h
  • MSR_COS_WAYS_1 : ArchMsr.h
  • MSR_COS_WAYS_2 : ArchMsr.h
  • MSR_COS_WAYS_3 : ArchMsr.h
  • MSR_CPU_BUSNUMBER : CommonMsr.h
  • MSR_CPU_DCA_CAP : ArchMsr.h
  • MSR_CPU_TYPE : CommonMsr.h
  • MSR_CRASHLOG_CONTROL : CommonMsr.h
  • MSR_CSTAR : ArchMsr.h
  • MSR_CUSTOMER_SPECIFIC_FEATURE_ENABLE : CommonMsr.h
  • MSR_DCU_FLUSH_CMD : ArchMsr.h
  • MSR_DCU_MODE_CONTROL : CommonMsr.h
  • MSR_DDR_ENERGY_STATUS : CommonMsr.h
  • MSR_DDR_RAPL_LIMIT : CommonMsr.h
  • MSR_DDR_RAPL_PERF_STATUS : CommonMsr.h
  • MSR_DEBUG_ERR_INJ_CTL : CommonMsr.h
  • MSR_DEBUG_ERR_INJ_CTL2 : CommonMsr.h
  • MSR_DEBUG_RESOURCE_STATUS : CommonMsr.h
  • MSR_DEBUGCTLMSR : ArchMsr.h
  • MSR_DISTRIBUTED_STATUS : CommonMsr.h
  • MSR_DS_AREA : ArchMsr.h
  • MSR_EDRAM_ACM : CommonMsr.h
  • MSR_EE_INIT : CommonMsr.h
  • MSR_EINIT_FAIL_CTR : CommonMsr.h
  • MSR_ELSRR_BASE : CommonMsr.h
  • MSR_ELSRR_MASK : CommonMsr.h
  • MSR_EM_EXCEPTIONS_HANDLING_EIP : CommonMsr.h
  • MSR_EMON_FIXED_CTR0 : ArchMsr.h
  • MSR_EMON_FIXED_CTR1 : ArchMsr.h
  • MSR_EMON_FIXED_CTR2 : ArchMsr.h
  • MSR_EMON_FIXED_CTR3 : ArchMsr.h
  • MSR_EMON_FIXED_CTR_CTRL : ArchMsr.h
  • MSR_EMON_FULL_CTR0 : ArchMsr.h
  • MSR_EMON_FULL_CTR1 : ArchMsr.h
  • MSR_EMON_FULL_CTR2 : ArchMsr.h
  • MSR_EMON_FULL_CTR3 : ArchMsr.h
  • MSR_EMON_FULL_CTR4 : ArchMsr.h
  • MSR_EMON_FULL_CTR5 : ArchMsr.h
  • MSR_EMON_FULL_CTR6 : ArchMsr.h
  • MSR_EMON_FULL_CTR7 : ArchMsr.h
  • MSR_EMON_GEN_CTR0 : ArchMsr.h
  • MSR_EMON_GEN_CTR1 : ArchMsr.h
  • MSR_EMON_GEN_CTR2 : ArchMsr.h
  • MSR_EMON_GEN_CTR3 : ArchMsr.h
  • MSR_EMON_GEN_CTR4 : ArchMsr.h
  • MSR_EMON_GEN_CTR5 : ArchMsr.h
  • MSR_EMON_GEN_CTR6 : ArchMsr.h
  • MSR_EMON_GEN_CTR7 : ArchMsr.h
  • MSR_EMON_PERF_CAPABILITIES : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_CTRL : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_RESET : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_SET : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_STATUS : ArchMsr.h
  • MSR_EMON_PERF_RES_PROGRAMMED : CommonMsr.h
  • MSR_EMRR_BASE : CommonMsr.h
  • MSR_EMRR_MASK : CommonMsr.h
  • MSR_EMXRR_BASE : CommonMsr.h
  • MSR_EMXRR_MASK : CommonMsr.h
  • MSR_ENABLE_DISABLE_CACHE_QOS : CommonMsr.h
  • MSR_ENABLE_LSM : FusaConfig.h
  • MSR_ENERGY_PERF_BIAS_CONFIG : CommonMsr.h
  • MSR_ENERGY_PERFORMANCE_BIAS : ArchMsr.h
  • MSR_ERR_INJ_LCK_UNLOCK_CTL : CommonMsr.h
  • MSR_ERROR_CONTROL : CommonMsr.h
  • MSR_EXTENDED_MCG_PTR : CommonMsr.h
  • MSR_FAST_UNCORE_MSRS_CAPABILITY : CommonMsr.h
  • MSR_FAST_UNCORE_MSRS_CTL : ArchMsr.h
  • MSR_FEATURE_CONFIG : CommonMsr.h
  • MSR_FIT_BIOS_ERROR : CommonMsr.h
  • MSR_FLEX_RATIO : CommonMsr.h
  • MSR_FME_ACTIVATE : CommonMsr.h
  • MSR_FS_BASE : ArchMsr.h
  • MSR_FUSE_KEY1_0 : CommonMsr.h
  • MSR_FUSE_KEY1_1 : CommonMsr.h
  • MSR_FZM_DOMAIN_CONFIG : ArchMsr.h
  • MSR_FZM_RANGE_ENDADDR : ArchMsr.h
  • MSR_FZM_RANGE_INDEX : ArchMsr.h
  • MSR_FZM_RANGE_STARTADDR : ArchMsr.h
  • MSR_FZM_RANGE_WRITESTATUS : ArchMsr.h
  • MSR_GLOBAL_SE_ENABLE : CommonMsr.h
  • MSR_GS_BASE : ArchMsr.h
  • MSR_GT_FLUSH_BCLD_ACK : CommonMsr.h
  • MSR_GT_FLUSH_RELOAD : CommonMsr.h
  • MSR_GT_PERF_LIMIT_REASONS : ArchMsr.h
  • MSR_HW_FB_CONFIG : ArchMsr.h
  • MSR_HW_FB_PTR : ArchMsr.h
  • MSR_HW_GET_LP_PM_META_DATA : CommonMsr.h
  • MSR_HW_SET_LP_PM_META_DATA : CommonMsr.h
  • MSR_HWP_REQUEST_PKG : ArchMsr.h
  • MSR_IA32_CR_EFER : ArchMsr.h
  • MSR_IA32_SE_SVN : CommonMsr.h
  • MSR_IA_PERF_LIMIT_REASONS : CommonMsr.h
  • MSR_ICECTLPMR : CommonMsr.h
  • MSR_ICECTLPMR_2 : CommonMsr.h
  • MSR_ICECTLPMR_PRIOR_STATE : CommonMsr.h
  • MSR_IIOPMONCNTR_0 : CommonMsr.h
  • MSR_IIOPMONCNTR_1 : CommonMsr.h
  • MSR_IIOPMONCNTR_2 : CommonMsr.h
  • MSR_IIOPMONCNTR_3 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_0 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_1 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_10 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_11 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_12 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_13 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_14 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_15 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_2 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_3 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_4 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_5 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_6 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_7 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_8 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_9 : CommonMsr.h
  • MSR_IMC0_MC_CTL : CommonMsr.h
  • MSR_IMC0_MC_STATUS : CommonMsr.h
  • MSR_IMC1_MC9_ADDR : CommonMsr.h
  • MSR_IMC2_MCA_ADDR : CommonMsr.h
  • MSR_INTERRUPT_SSP_TABLE : ArchMsr.h
  • MSR_IO_BW_P_LIMIT_OVERRIDE : CommonMsr.h
  • MSR_IO_MEM_ADDR : CommonMsr.h
  • MSR_IO_QOS_CFG : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RCX : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RDI : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RSI : CommonMsr.h
  • MSR_IOMISCINFO : CommonMsr.h
  • MSR_IOPMONCNTRCFG_0 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_1 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_2 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_3 : CommonMsr.h
  • MSR_IRPPMONCNTRCFG_0 : CommonMsr.h
  • MSR_IRPPMONCNTRCFG_1 : CommonMsr.h
  • MSR_IWKEYBACKUP_STATUS : ArchMsr.h
  • MSR_KERNEL_GSBASE : ArchMsr.h
  • MSR_L2_QOS_CFG : ArchMsr.h
  • MSR_L2_QOS_MASK_0_0 : ArchMsr.h
  • MSR_L2_QOS_MASK_1_1 : ArchMsr.h
  • MSR_L2_QOS_MASK_2_2 : ArchMsr.h
  • MSR_L2_QOS_MASK_3_3 : ArchMsr.h
  • MSR_L2_QOS_MASK_4_4 : ArchMsr.h
  • MSR_L2_QOS_MASK_5_5 : ArchMsr.h
  • MSR_L2_QOS_MASK_6_6 : ArchMsr.h
  • MSR_L2_QOS_MASK_7_7 : ArchMsr.h
  • MSR_L3_PROTECTED_WAYS : CommonMsr.h
  • MSR_LAST_BRANCH_FROM_IP : CommonMsr.h
  • MSR_LAST_BRANCH_INFO : CommonMsr.h
  • MSR_LAST_BRANCH_TO_IP : CommonMsr.h
  • MSR_LAST_INT_FROM_IP : CommonMsr.h
  • MSR_LAST_INT_INFO : CommonMsr.h
  • MSR_LAST_INT_TO_IP : CommonMsr.h
  • MSR_LBR_FROM_IP_0_0 : CommonMsr.h
  • MSR_LBR_FROM_IP_10_10 : CommonMsr.h
  • MSR_LBR_FROM_IP_11_11 : CommonMsr.h
  • MSR_LBR_FROM_IP_18_18 : CommonMsr.h
  • MSR_LBR_FROM_IP_19_19 : CommonMsr.h
  • MSR_LBR_FROM_IP_1_1 : CommonMsr.h
  • MSR_LBR_FROM_IP_20_20 : CommonMsr.h
  • MSR_LBR_FROM_IP_21_21 : CommonMsr.h
  • MSR_LBR_FROM_IP_22_22 : CommonMsr.h
  • MSR_LBR_FROM_IP_23_23 : CommonMsr.h
  • MSR_LBR_FROM_IP_24_24 : CommonMsr.h
  • MSR_LBR_FROM_IP_25_25 : CommonMsr.h
  • MSR_LBR_FROM_IP_26_26 : CommonMsr.h
  • MSR_LBR_FROM_IP_27_27 : CommonMsr.h
  • MSR_LBR_FROM_IP_28_28 : CommonMsr.h
  • MSR_LBR_FROM_IP_29_29 : CommonMsr.h
  • MSR_LBR_FROM_IP_2_2 : CommonMsr.h
  • MSR_LBR_FROM_IP_30_30 : CommonMsr.h
  • MSR_LBR_FROM_IP_31_31 : CommonMsr.h
  • MSR_LBR_FROM_IP_3_3 : CommonMsr.h
  • MSR_LBR_FROM_IP_4_4 : CommonMsr.h
  • MSR_LBR_FROM_IP_5_5 : CommonMsr.h
  • MSR_LBR_FROM_IP_6_6 : CommonMsr.h
  • MSR_LBR_FROM_IP_7_7 : CommonMsr.h
  • MSR_LBR_FROM_IP_8_8 : CommonMsr.h
  • MSR_LBR_FROM_IP_9_9 : CommonMsr.h
  • MSR_LBR_INFO_0_0 : CommonMsr.h
  • MSR_LBR_INFO_10_10 : CommonMsr.h
  • MSR_LBR_INFO_11_11 : CommonMsr.h
  • MSR_LBR_INFO_12_12 : CommonMsr.h
  • MSR_LBR_INFO_13_13 : CommonMsr.h
  • MSR_LBR_INFO_14_14 : CommonMsr.h
  • MSR_LBR_INFO_15_15 : CommonMsr.h
  • MSR_LBR_INFO_16_16 : CommonMsr.h
  • MSR_LBR_INFO_17_17 : CommonMsr.h
  • MSR_LBR_INFO_18_18 : CommonMsr.h
  • MSR_LBR_INFO_19_19 : CommonMsr.h
  • MSR_LBR_INFO_1_1 : CommonMsr.h
  • MSR_LBR_INFO_20_20 : CommonMsr.h
  • MSR_LBR_INFO_21_21 : CommonMsr.h
  • MSR_LBR_INFO_22_22 : CommonMsr.h
  • MSR_LBR_INFO_23_23 : CommonMsr.h
  • MSR_LBR_INFO_24_24 : CommonMsr.h
  • MSR_LBR_INFO_25_25 : CommonMsr.h
  • MSR_LBR_INFO_26_26 : CommonMsr.h
  • MSR_LBR_INFO_27_27 : CommonMsr.h
  • MSR_LBR_INFO_28_28 : CommonMsr.h
  • MSR_LBR_INFO_29_29 : CommonMsr.h
  • MSR_LBR_INFO_2_2 : CommonMsr.h
  • MSR_LBR_INFO_30_30 : CommonMsr.h
  • MSR_LBR_INFO_31_31 : CommonMsr.h
  • MSR_LBR_INFO_3_3 : CommonMsr.h
  • MSR_LBR_INFO_4_4 : CommonMsr.h
  • MSR_LBR_INFO_5_5 : CommonMsr.h
  • MSR_LBR_INFO_6_6 : CommonMsr.h
  • MSR_LBR_INFO_7_7 : CommonMsr.h
  • MSR_LBR_INFO_8_8 : CommonMsr.h
  • MSR_LBR_INFO_9_9 : CommonMsr.h
  • MSR_LBR_SELECT : CommonMsr.h
  • MSR_LBR_TO_IP_0_0 : CommonMsr.h
  • MSR_LBR_TO_IP_10_10 : CommonMsr.h
  • MSR_LBR_TO_IP_11_11 : CommonMsr.h
  • MSR_LBR_TO_IP_12_12 : CommonMsr.h
  • MSR_LBR_TO_IP_13_13 : CommonMsr.h
  • MSR_LBR_TO_IP_14_14 : CommonMsr.h
  • MSR_LBR_TO_IP_15_15 : CommonMsr.h
  • MSR_LBR_TO_IP_16_16 : CommonMsr.h
  • MSR_LBR_TO_IP_17_17 : CommonMsr.h
  • MSR_LBR_TO_IP_18_18 : CommonMsr.h
  • MSR_LBR_TO_IP_19_19 : CommonMsr.h
  • MSR_LBR_TO_IP_1_1 : CommonMsr.h
  • MSR_LBR_TO_IP_20_20 : CommonMsr.h
  • MSR_LBR_TO_IP_21_21 : CommonMsr.h
  • MSR_LBR_TO_IP_22_22 : CommonMsr.h
  • MSR_LBR_TO_IP_23_23 : CommonMsr.h
  • MSR_LBR_TO_IP_24_24 : CommonMsr.h
  • MSR_LBR_TO_IP_25_25 : CommonMsr.h
  • MSR_LBR_TO_IP_26_26 : CommonMsr.h
  • MSR_LBR_TO_IP_27_27 : CommonMsr.h
  • MSR_LBR_TO_IP_28_28 : CommonMsr.h
  • MSR_LBR_TO_IP_29_29 : CommonMsr.h
  • MSR_LBR_TO_IP_2_2 : CommonMsr.h
  • MSR_LBR_TO_IP_30_30 : CommonMsr.h
  • MSR_LBR_TO_IP_31_31 : CommonMsr.h
  • MSR_LBR_TO_IP_3_3 : CommonMsr.h
  • MSR_LBR_TO_IP_4_4 : CommonMsr.h
  • MSR_LBR_TO_IP_5_5 : CommonMsr.h
  • MSR_LBR_TO_IP_6_6 : CommonMsr.h
  • MSR_LBR_TO_IP_7_7 : CommonMsr.h
  • MSR_LBR_TO_IP_8_8 : CommonMsr.h
  • MSR_LBR_TO_IP_9_9 : CommonMsr.h
  • MSR_LBR_TOS : CommonMsr.h
  • MSR_LCLK_PLL_RATIO : CommonMsr.h
  • MSR_LLC_FLUSHED_RCNTR : CommonMsr.h
  • MSR_LLC_QOS_MASK_0 : CommonMsr.h
  • MSR_LLC_QOS_MASK_1 : CommonMsr.h
  • MSR_LLC_QOS_MASK_10_10 : CommonMsr.h
  • MSR_LLC_QOS_MASK_11_11 : CommonMsr.h
  • MSR_LLC_QOS_MASK_12_12 : CommonMsr.h
  • MSR_LLC_QOS_MASK_13_13 : CommonMsr.h
  • MSR_LLC_QOS_MASK_14_14 : CommonMsr.h
  • MSR_LLC_QOS_MASK_2 : CommonMsr.h
  • MSR_LLC_QOS_MASK_3 : CommonMsr.h
  • MSR_LLC_QOS_MASK_4_4 : CommonMsr.h
  • MSR_LLC_QOS_MASK_5_5 : CommonMsr.h
  • MSR_LLC_QOS_MASK_6_6 : CommonMsr.h
  • MSR_LLC_QOS_MASK_7_7 : CommonMsr.h
  • MSR_LLC_QOS_MASK_8_8 : CommonMsr.h
  • MSR_LLC_QOS_MASK_9_9 : CommonMsr.h
  • MSR_LSTAR : ArchMsr.h
  • MSR_LT_SMX_STATE : CommonMsr.h
  • MSR_LT_UNLOCK_MEMORY : CommonMsr.h
  • MSR_M2PPMONCNTRCFG_2 : CommonMsr.h
  • MSR_M2PPMONCNTRCFG_3 : CommonMsr.h
  • MSR_MBA_CFG : CommonMsr.h
  • MSR_MBM_CFG_3DXP : CommonMsr.h
  • MSR_MC0_ADDR : ArchMsr.h
  • MSR_MC0_CTL : ArchMsr.h
  • MSR_MC0_MISC : ArchMsr.h
  • MSR_MC0_MISC2 : ArchMsr.h
  • MSR_MC0_STATUS : ArchMsr.h
  • MSR_MC10_ADDR : ArchMsr.h
  • MSR_MC10_CTL : ArchMsr.h
  • MSR_MC10_CTL2 : ArchMsr.h
  • MSR_MC10_MISC : ArchMsr.h
  • MSR_MC10_STATUS : ArchMsr.h
  • MSR_MC11_ADDR : ArchMsr.h
  • MSR_MC11_CTL : ArchMsr.h
  • MSR_MC11_CTL2 : ArchMsr.h
  • MSR_MC11_MISC : ArchMsr.h
  • MSR_MC11_STATUS : ArchMsr.h
  • MSR_MC12_ADDR : ArchMsr.h
  • MSR_MC12_CTL : ArchMsr.h
  • MSR_MC12_CTL2 : ArchMsr.h
  • MSR_MC12_MISC : ArchMsr.h
  • MSR_MC12_STATUS : ArchMsr.h
  • MSR_MC13_ADDR : ArchMsr.h
  • MSR_MC13_CTL : ArchMsr.h
  • MSR_MC13_CTL2 : ArchMsr.h
  • MSR_MC13_MISC : ArchMsr.h
  • MSR_MC13_STATUS : ArchMsr.h
  • MSR_MC14_ADDR : ArchMsr.h
  • MSR_MC14_CTL : ArchMsr.h
  • MSR_MC14_CTL2 : ArchMsr.h
  • MSR_MC14_MISC : ArchMsr.h
  • MSR_MC14_STATUS : ArchMsr.h
  • MSR_MC15_ADDR : ArchMsr.h
  • MSR_MC15_CTL : ArchMsr.h
  • MSR_MC15_CTL2 : ArchMsr.h
  • MSR_MC15_MISC : ArchMsr.h
  • MSR_MC15_STATUS : ArchMsr.h
  • MSR_MC16_ADDR : ArchMsr.h
  • MSR_MC16_CTL : ArchMsr.h
  • MSR_MC16_CTL2 : ArchMsr.h
  • MSR_MC16_MISC : ArchMsr.h
  • MSR_MC16_STATUS : ArchMsr.h
  • MSR_MC17_ADDR : ArchMsr.h
  • MSR_MC17_CTL : ArchMsr.h
  • MSR_MC17_CTL2 : ArchMsr.h
  • MSR_MC17_MISC : ArchMsr.h
  • MSR_MC17_STATUS : ArchMsr.h
  • MSR_MC18_ADDR : ArchMsr.h
  • MSR_MC18_CTL : ArchMsr.h
  • MSR_MC18_CTL2 : ArchMsr.h
  • MSR_MC18_MISC : ArchMsr.h
  • MSR_MC18_STATUS : ArchMsr.h
  • MSR_MC19_ADDR : ArchMsr.h
  • MSR_MC19_CTL : ArchMsr.h
  • MSR_MC19_CTL2 : ArchMsr.h
  • MSR_MC19_STATUS : ArchMsr.h
  • MSR_MC1_ADDR : ArchMsr.h
  • MSR_MC1_CTL : ArchMsr.h
  • MSR_MC1_MISC : ArchMsr.h
  • MSR_MC1_MISC2 : ArchMsr.h
  • MSR_MC1_STATUS : ArchMsr.h
  • MSR_MC20_ADDR : ArchMsr.h
  • MSR_MC20_CTL : ArchMsr.h
  • MSR_MC20_CTL2 : ArchMsr.h
  • MSR_MC20_STATUS : ArchMsr.h
  • MSR_MC21_ADDR : ArchMsr.h
  • MSR_MC21_CTL : ArchMsr.h
  • MSR_MC21_CTL2 : ArchMsr.h
  • MSR_MC21_MISC : ArchMsr.h
  • MSR_MC21_STATUS : ArchMsr.h
  • MSR_MC22_ADDR : ArchMsr.h
  • MSR_MC22_CTL : ArchMsr.h
  • MSR_MC22_CTL2 : ArchMsr.h
  • MSR_MC22_MISC : ArchMsr.h
  • MSR_MC22_STATUS : ArchMsr.h
  • MSR_MC23_ADDR : ArchMsr.h
  • MSR_MC23_CTL : ArchMsr.h
  • MSR_MC23_CTL2 : ArchMsr.h
  • MSR_MC23_MISC : ArchMsr.h
  • MSR_MC23_STATUS : ArchMsr.h
  • MSR_MC24_ADDR : ArchMsr.h
  • MSR_MC24_CTL : ArchMsr.h
  • MSR_MC24_CTL2 : ArchMsr.h
  • MSR_MC24_MISC : ArchMsr.h
  • MSR_MC24_STATUS : ArchMsr.h
  • MSR_MC2_ADDR : ArchMsr.h
  • MSR_MC2_CTL : ArchMsr.h
  • MSR_MC2_MISC : ArchMsr.h
  • MSR_MC2_MISC2 : ArchMsr.h
  • MSR_MC2_STATUS : ArchMsr.h
  • MSR_MC3_ADDR : ArchMsr.h
  • MSR_MC3_CTL : ArchMsr.h
  • MSR_MC3_MISC : ArchMsr.h
  • MSR_MC3_MISC2 : ArchMsr.h
  • MSR_MC3_STATUS : ArchMsr.h
  • MSR_MC4_ADDR : ArchMsr.h
  • MSR_MC4_CTL : ArchMsr.h
  • MSR_MC4_CTL2 : ArchMsr.h
  • MSR_MC4_MISC : ArchMsr.h
  • MSR_MC4_STATUS : ArchMsr.h
  • MSR_MC5_ADDR : ArchMsr.h
  • MSR_MC5_CTL : ArchMsr.h
  • MSR_MC5_CTL2 : ArchMsr.h
  • MSR_MC5_MISC : ArchMsr.h
  • MSR_MC5_STATUS : ArchMsr.h
  • MSR_MC6_ADDR : ArchMsr.h
  • MSR_MC6_CTL : ArchMsr.h
  • MSR_MC6_CTL2 : ArchMsr.h
  • MSR_MC6_MISC : ArchMsr.h
  • MSR_MC6_STATUS : ArchMsr.h
  • MSR_MC7_ADDR : ArchMsr.h
  • MSR_MC7_CTL : ArchMsr.h
  • MSR_MC7_CTL2 : ArchMsr.h
  • MSR_MC7_MISC : ArchMsr.h
  • MSR_MC7_STATUS : ArchMsr.h
  • MSR_MC8_ADDR : ArchMsr.h
  • MSR_MC8_CTL : ArchMsr.h
  • MSR_MC8_CTL2 : ArchMsr.h
  • MSR_MC8_MISC : ArchMsr.h
  • MSR_MC8_STATUS : ArchMsr.h
  • MSR_MC9_ADDR : ArchMsr.h
  • MSR_MC9_CTL : ArchMsr.h
  • MSR_MC9_CTL2 : ArchMsr.h
  • MSR_MC9_MISC : ArchMsr.h
  • MSR_MC9_STATUS : ArchMsr.h
  • MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN : CommonMsr.h
  • MSR_MCG_CAP : ArchMsr.h
  • MSR_MCG_CONTAIN : CommonMsr.h
  • MSR_MCG_EXE_CTL : CommonMsr.h
  • MSR_MCG_STATUS : ArchMsr.h
  • MSR_MCHECK_BOOT_SCENARIO : CommonMsr.h
  • MSR_MCHECK_CPU_REGISTER_ADDRESS : CommonMsr.h
  • MSR_MCHECK_CPU_REGISTER_DATA : CommonMsr.h
  • MSR_MCI_CTL2 : CommonMsr.h
  • MSR_MEE_SETUP : CommonMsr.h
  • MSR_MEMORY_CONTROL : CommonMsr.h
  • MSR_MISC_ENABLES : ArchMsr.h
  • MSR_MISC_FEATURE_CONTROL : CommonMsr.h
  • MSR_MISC_PWR_MGMT : CommonMsr.h
  • MSR_MISC_THD_FEATURE_ENABLES : CommonMsr.h
  • MSR_MLC_ACNT_COUNTER : ArchMsr.h
  • MSR_MLC_MCNT_COUNTER : ArchMsr.h
  • MSR_MLC_PCNT_COUNTER : ArchMsr.h
  • MSR_MLC_PWR_MGMT_TIMER_CTRL : CommonMsr.h
  • MSR_MLC_VT_TIMER_CONTROL : CommonMsr.h
  • MSR_MLC_VT_TIMER_COUNT : CommonMsr.h
  • MSR_MMCFG_RULE_CFG : CommonMsr.h
  • MSR_MMCFG_RULE_TARGET_LIST : CommonMsr.h
  • MSR_MONITOR_FILTER_SIZE : ArchMsr.h
  • MSR_MPX_FUSE_OVERRIDE : CommonMsr.h
  • MSR_MPX_LAX : ArchMsr.h
  • MSR_MSR_THERM2_CTL : CommonMsr.h
  • MSR_MTRRCAP : ArchMsr.h
  • MSR_MTRRDEFAULT : ArchMsr.h
  • MSR_MTRRFIX16K8 : ArchMsr.h
  • MSR_MTRRFIX16KA : ArchMsr.h
  • MSR_MTRRFIX4KC0 : ArchMsr.h
  • MSR_MTRRFIX4KC8 : ArchMsr.h
  • MSR_MTRRFIX4KD0 : ArchMsr.h
  • MSR_MTRRFIX4KD8 : ArchMsr.h
  • MSR_MTRRFIX4KE0 : ArchMsr.h
  • MSR_MTRRFIX4KE8 : ArchMsr.h
  • MSR_MTRRFIX4KF0 : ArchMsr.h
  • MSR_MTRRFIX4KF8 : ArchMsr.h
  • MSR_MTRRFIX64K : ArchMsr.h
  • MSR_MTRRVARBASE0 : ArchMsr.h
  • MSR_MTRRVARBASE1 : ArchMsr.h
  • MSR_MTRRVARBASE2 : ArchMsr.h
  • MSR_MTRRVARBASE3 : ArchMsr.h
  • MSR_MTRRVARBASE4 : ArchMsr.h
  • MSR_MTRRVARBASE5 : ArchMsr.h
  • MSR_MTRRVARBASE6 : ArchMsr.h
  • MSR_MTRRVARBASE7 : ArchMsr.h
  • MSR_MTRRVARBASE8 : ArchMsr.h
  • MSR_MTRRVARBASE9 : ArchMsr.h
  • MSR_MTRRVARMASK0 : ArchMsr.h
  • MSR_MTRRVARMASK1 : ArchMsr.h
  • MSR_MTRRVARMASK2 : ArchMsr.h
  • MSR_MTRRVARMASK3 : ArchMsr.h
  • MSR_MTRRVARMASK4 : ArchMsr.h
  • MSR_MTRRVARMASK5 : ArchMsr.h
  • MSR_MTRRVARMASK6 : ArchMsr.h
  • MSR_MTRRVARMASK7 : ArchMsr.h
  • MSR_MTRRVARMASK8 : ArchMsr.h
  • MSR_MTRRVARMASK9 : ArchMsr.h
  • MSR_NCUPMONCTRLGLCTR : CommonMsr.h
  • MSR_NCUPMONGLSTS1 : CommonMsr.h
  • MSR_NCUWHOAMI : CommonMsr.h
  • MSR_NEM : CommonMsr.h
  • MSR_NPK_STH_ACPIBAR_BASE : CommonMsr.h
  • MSR_OPTIN_FEATURE_CONTROL : ArchMsr.h
  • MSR_OVERCLOCKING_MAILBOX : CommonMsr.h
  • MSR_P5_MC_ADDR : ArchMsr.h
  • MSR_P6_CR_SMBASE : CommonMsr.h
  • MSR_P6_CR_SMREVID : CommonMsr.h
  • MSR_PACKAGE_ENERGY_STATUS : CommonMsr.h
  • MSR_PACKAGE_POWER_SKU : CommonMsr.h
  • MSR_PACKAGE_POWER_SKU_UNIT : CommonMsr.h
  • MSR_PACKAGE_RAPL_LIMIT : CommonMsr.h
  • MSR_PACKAGE_RAPL_PERF_STATUS : CommonMsr.h
  • MSR_PACKAGE_THERM_INTERRUPT : ArchMsr.h
  • MSR_PACKAGE_THERM_MARGIN : CommonMsr.h
  • MSR_PACKAGE_THERM_STATUS : ArchMsr.h
  • MSR_PAIR_PKG_THREAD_PARTICIPATION : CommonMsr.h
  • MSR_PAIR_THREAD_PARTICIPATION : CommonMsr.h
  • MSR_PAIR_WEIGHT_OVERRIDE : CommonMsr.h
  • MSR_PASID : ArchMsr.h
  • MSR_PAT : ArchMsr.h
  • MSR_PC10_RCNTR : CommonMsr.h
  • MSR_PC2_RCNTR : CommonMsr.h
  • MSR_PC3_RCNTR : CommonMsr.h
  • MSR_PC6_RCNTR : CommonMsr.h
  • MSR_PC7_RCNTR : CommonMsr.h
  • MSR_PC8_RCNTR : CommonMsr.h
  • MSR_PC9_RCNTR : CommonMsr.h
  • MSR_PCH_EA_CONTROL : CommonMsr.h
  • MSR_PCH_EA_STATUS : CommonMsr.h
  • MSR_PCUPMONCNTR_0 : CommonMsr.h
  • MSR_PCUPMONCNTR_1 : CommonMsr.h
  • MSR_PCUPMONCNTR_2 : CommonMsr.h
  • MSR_PCUPMONCNTR_3 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_0 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_1 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_2 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_3 : CommonMsr.h
  • MSR_PDM_GDXC_MSG : CommonMsr.h
  • MSR_PDM_HEADER : CommonMsr.h
  • MSR_PDPTR_0_0 : CommonMsr.h
  • MSR_PDPTR_1_1 : CommonMsr.h
  • MSR_PDPTR_2_2 : CommonMsr.h
  • MSR_PDPTR_3_3 : CommonMsr.h
  • MSR_PEBS_DATA_CFG : ArchMsr.h
  • MSR_PEBS_ENABLE : ArchMsr.h
  • MSR_PEBS_FRONTEND : CommonMsr.h
  • MSR_PEBS_LD_LAT_THRESHOLD : CommonMsr.h
  • MSR_PERF_CTL : ArchMsr.h
  • MSR_PERF_METRICS : ArchMsr.h
  • MSR_PERF_OCCUPANCY_CTRS : ArchMsr.h
  • MSR_PERF_STATUS : ArchMsr.h
  • MSR_PERFCTR0 : CommonMsr.h
  • MSR_PERFCTR1 : CommonMsr.h
  • MSR_PERMEM_CONFIG_INFO : CommonMsr.h
  • MSR_PERMEM_CTRLR_ID : CommonMsr.h
  • MSR_PERMEM_CTRLR_INDEX : CommonMsr.h
  • MSR_PERMON_EVNTSEL_AUX : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR0 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR1 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR2 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR3 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR4 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR5 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR6 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR7 : ArchMsr.h
  • MSR_PFAT_EC_PASSWORD : CommonMsr.h
  • MSR_PFAT_GT_SLEEP_CMDSTS : CommonMsr.h
  • MSR_PFR_EXIT : CommonMsr.h
  • MSR_PFR_VCM_PROVISION : CommonMsr.h
  • MSR_PFR_VCM_PROVISION_STATUS : CommonMsr.h
  • MSR_PIC_EOI : CommonMsr.h
  • MSR_PIC_ERROR_STATUS : CommonMsr.h
  • MSR_PIC_EXTENDED_LOCAL_APIC_ID : CommonMsr.h
  • MSR_PIC_EXTENDED_LOGICAL_DESTINATION : CommonMsr.h
  • MSR_PIC_INTERRUPT_COMMAND : CommonMsr.h
  • MSR_PIC_IRR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_7_7 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_7_7 : CommonMsr.h
  • MSR_PIC_LOCAL_UNIT_VERSION : CommonMsr.h
  • MSR_PIC_LT_DOORBELL : CommonMsr.h
  • MSR_PIC_LVT_CMCI : CommonMsr.h
  • MSR_PIC_LVT_ERROR : CommonMsr.h
  • MSR_PIC_LVT_LINT0 : CommonMsr.h
  • MSR_PIC_LVT_LINT1 : CommonMsr.h
  • MSR_PIC_LVT_PERF : CommonMsr.h
  • MSR_PIC_LVT_THERM : CommonMsr.h
  • MSR_PIC_LVT_TIMER : CommonMsr.h
  • MSR_PIC_MSG_CONTROL : CommonMsr.h
  • MSR_PIC_PROCESSOR_PRIORITY : CommonMsr.h
  • MSR_PIC_SPURIOUS_INTERRUPT : CommonMsr.h
  • MSR_PIC_TASK_PRIORITY : CommonMsr.h
  • MSR_PIC_TIMER_CURRENT_COUNT_REG : CommonMsr.h
  • MSR_PIC_TIMER_DIVIDE_CONFIG_REG : CommonMsr.h
  • MSR_PIC_TIMER_INITIAL_COUNT_REG : CommonMsr.h
  • MSR_PIC_TMR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_7_7 : CommonMsr.h
  • MSR_PKG_GT_AND_IA_OVERLAP : CommonMsr.h
  • MSR_PKG_GT_C0_ANY : CommonMsr.h
  • MSR_PKG_IA_C0_ANY : CommonMsr.h
  • MSR_PKG_IA_C0_ANY_SUM : CommonMsr.h
  • MSR_PKG_SDC_CONFIG_CONTROL : CommonMsr.h
  • MSR_PKG_SDC_CTL : ArchMsr.h
  • MSR_PKG_SDC_DEEP_RESIDENCY : CommonMsr.h
  • MSR_PKG_SDC_SHALLOW_RESIDENCY : CommonMsr.h
  • MSR_PL0_SSP : ArchMsr.h
  • MSR_PL1_SSP : ArchMsr.h
  • MSR_PL2_SSP : ArchMsr.h
  • MSR_PL3_CONTROL : CommonMsr.h
  • MSR_PL3_SSP : ArchMsr.h
  • MSR_PLAT_FRMW_PROT_CTRL : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_0 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_1 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_2 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_3 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_TRIG_PARAM : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_TRIGGER : CommonMsr.h
  • MSR_PLATFORM_ENERGY_STATUS : CommonMsr.h
  • MSR_PLATFORM_ID : ArchMsr.h
  • MSR_PLATFORM_POWER_LIMIT : CommonMsr.h
  • MSR_PM_CTL1 : ArchMsr.h
  • MSR_PMG_IO_CAPTURE_BASE : CommonMsr.h
  • MSR_POWER_CTL : CommonMsr.h
  • MSR_POWERON : CommonMsr.h
  • MSR_PPIN : CommonMsr.h
  • MSR_PPIN_CTL : CommonMsr.h
  • MSR_PPPE_DOORBELL_EXIT_BITMAP : CommonMsr.h
  • MSR_PQOS_CDP_ENABLE : CommonMsr.h
  • MSR_PREDICT_CMD : ArchMsr.h
  • MSR_PRID_0_0 : CommonMsr.h
  • MSR_PRID_1_1 : CommonMsr.h
  • MSR_PRIMARY_PLANE_ENERGY_STATUS : CommonMsr.h
  • MSR_PRIMARY_PLANE_OVERFLOW_STATUS : CommonMsr.h
  • MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT : CommonMsr.h
  • MSR_PRIMARY_PLANE_TURBO_POWER_POLICY : CommonMsr.h
  • MSR_PRIVACY_CONTROL : ArchMsr.h
  • MSR_PRMRR_BASE_0 : CommonMsr.h
  • MSR_PRMRR_BASE_1_1 : CommonMsr.h
  • MSR_PRMRR_BASE_2_2 : CommonMsr.h
  • MSR_PRMRR_BASE_3_3 : CommonMsr.h
  • MSR_PRMRR_BASE_4_4 : CommonMsr.h
  • MSR_PRMRR_BASE_5_5 : CommonMsr.h
  • MSR_PRMRR_BASE_6_6 : CommonMsr.h
  • MSR_PRMRR_BASE_7_7 : CommonMsr.h
  • MSR_PRMRR_MASK : CommonMsr.h
  • MSR_PRMRR_VALID_CONFIG : CommonMsr.h
  • MSR_PROBE_CHANGE_PG : CommonMsr.h
  • MSR_PROBE_CPL : CommonMsr.h
  • MSR_PROBE_GP_REG : CommonMsr.h
  • MSR_PROBE_LT_SPC_CYC : CommonMsr.h
  • MSR_PROBE_MMX2_REG : CommonMsr.h
  • MSR_PROBE_MODE_DR : CommonMsr.h
  • MSR_PROBE_MODE_PPPE_REDIRECTION : CommonMsr.h
  • MSR_PROBE_MODE_PPPE_REDIRECTION_INFO : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_10_10 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_11_11 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_12_12 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_1_1 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_2_2 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_3_3 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_4_4 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_5_5 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_6_6 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_7_7 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_8_8 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_9_9 : CommonMsr.h
  • MSR_PROBE_MODE_VMEXIT_REDIRECTION_REASON : CommonMsr.h
  • MSR_PROBE_MODE_VMX_REDIRECTION_INFO : CommonMsr.h
  • MSR_PROBE_PL_REG : CommonMsr.h
  • MSR_PROBE_SEG_REG_1 : CommonMsr.h
  • MSR_PROBE_SEG_REG_3 : CommonMsr.h
  • MSR_PROBE_TLB_FLUSH : CommonMsr.h
  • MSR_PROBE_TO_FROM_PDR : CommonMsr.h
  • MSR_PROBE_VMX_POINTER : CommonMsr.h
  • MSR_PSMI_BASE : CommonMsr.h
  • MSR_PST_CONFIG_CONTROL : CommonMsr.h
  • MSR_QLRU_CONFIG : CommonMsr.h
  • MSR_QMC : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_0_0 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_10_10 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_11_11 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_12_12 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_13_13 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_14_14 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_1_1 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_2_2 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_3_3 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_4_4 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_5_5 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_6_6 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_7_7 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_8_8 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_9_9 : CommonMsr.h
  • MSR_QOSEVTSEL : CommonMsr.h
  • MSR_QUIESCE_CTL1 : CommonMsr.h
  • MSR_QUIESCE_CTL2 : CommonMsr.h
  • MSR_REGISTER_0 : CommonMsr.h
  • MSR_REGISTER_1 : CommonMsr.h
  • MSR_REGISTER_10 : CommonMsr.h
  • MSR_REGISTER_11 : CommonMsr.h
  • MSR_REGISTER_12 : CommonMsr.h
  • MSR_REGISTER_13 : CommonMsr.h
  • MSR_REGISTER_2 : CommonMsr.h
  • MSR_REGISTER_3 : CommonMsr.h
  • MSR_REGISTER_4 : CommonMsr.h
  • MSR_REGISTER_5 : CommonMsr.h
  • MSR_REGISTER_6 : CommonMsr.h
  • MSR_REGISTER_7 : CommonMsr.h
  • MSR_REGISTER_8 : CommonMsr.h
  • MSR_REGISTER_9 : CommonMsr.h
  • MSR_RESIDENCY_CTR : CommonMsr.h
  • MSR_RESIDENCY_CTR_CONFIG : CommonMsr.h
  • MSR_RESIDENCY_CTR_SELECT : CommonMsr.h
  • MSR_ROP_COUNTER_CONFIG_0 : CommonMsr.h
  • MSR_ROP_COUNTER_CONFIG_1 : CommonMsr.h
  • MSR_ROP_DETECT_CAPABILITIES : CommonMsr.h
  • MSR_ROP_DETECT_CTRL : CommonMsr.h
  • MSR_ROP_DETECT_STATUS : CommonMsr.h
  • MSR_ROP_EVENT_FILTER0 : CommonMsr.h
  • MSR_ROP_EVENT_FILTER0_DATA : CommonMsr.h
  • MSR_RTIT_ADDR0_A : ArchMsr.h
  • MSR_RTIT_ADDR0_B : ArchMsr.h
  • MSR_RTIT_ADDR1_A : ArchMsr.h
  • MSR_RTIT_ADDR1_B : ArchMsr.h
  • MSR_RTIT_CR3_MATCH : ArchMsr.h
  • MSR_RTIT_CTL : ArchMsr.h
  • MSR_RTIT_OUTPUT_BASE : ArchMsr.h
  • MSR_RTIT_OUTPUT_MASK_PTRS : ArchMsr.h
  • MSR_RTIT_STATUS : ArchMsr.h
  • MSR_S_CET : ArchMsr.h
  • MSR_SE_EPOCH_0 : CommonMsr.h
  • MSR_SE_EPOCH_1 : CommonMsr.h
  • MSR_SE_RDINFO_CMD : CommonMsr.h
  • MSR_SECONDARY_PLANE_ENERGY_STATUS : CommonMsr.h
  • MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT : CommonMsr.h
  • MSR_SECONDARY_PLANE_TURBO_POWER_POLICY : CommonMsr.h
  • MSR_SECS_SID : CommonMsr.h
  • MSR_SELF_IPI : CommonMsr.h
  • MSR_SF_QOS_MASK_0_0 : ArchMsr.h
  • MSR_SF_QOS_MASK_10_10 : ArchMsr.h
  • MSR_SF_QOS_MASK_11_11 : ArchMsr.h
  • MSR_SF_QOS_MASK_12_12 : ArchMsr.h
  • MSR_SF_QOS_MASK_13_13 : ArchMsr.h
  • MSR_SF_QOS_MASK_14_14 : ArchMsr.h
  • MSR_SF_QOS_MASK_15_15 : ArchMsr.h
  • MSR_SF_QOS_MASK_1_1 : ArchMsr.h
  • MSR_SF_QOS_MASK_2_2 : ArchMsr.h
  • MSR_SF_QOS_MASK_3_3 : ArchMsr.h
  • MSR_SF_QOS_MASK_4_4 : ArchMsr.h
  • MSR_SF_QOS_MASK_5_5 : ArchMsr.h
  • MSR_SF_QOS_MASK_6_6 : ArchMsr.h
  • MSR_SF_QOS_MASK_7_7 : ArchMsr.h
  • MSR_SF_QOS_MASK_8_8 : ArchMsr.h
  • MSR_SF_QOS_MASK_9_9 : ArchMsr.h
  • MSR_SFMASK : ArchMsr.h
  • MSR_SGX_DEBUG_MODE : CommonMsr.h
  • MSR_SGX_RAS : CommonMsr.h
  • MSR_SGX_RDPCHSGXID_0 : CommonMsr.h
  • MSR_SGX_RDPCHSGXID_1 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH0 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH1 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH2 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH3 : CommonMsr.h
  • MSR_SMBASE_ADDR : CommonMsr.h
  • MSR_SMI_COUNT : CommonMsr.h
  • MSR_SMM_CFG_OPTIONS : CommonMsr.h
  • MSR_SMM_CLEAR_SMI : CommonMsr.h
  • MSR_SMM_ENABLE_MASK : CommonMsr.h
  • MSR_SMM_ENABLE_MATCH : CommonMsr.h
  • MSR_SMM_FEATURE_CONTROL : CommonMsr.h
  • MSR_SMM_MCA_CAP : CommonMsr.h
  • MSR_SMM_PROT_MODE_BASE : CommonMsr.h
  • MSR_SMM_SAVE_CONTROL : CommonMsr.h
  • MSR_SMM_SUPOVR_STATE_LOCK : CommonMsr.h
  • MSR_SMRAM_BNDCFGS : CommonMsr.h
  • MSR_SMRAM_CR0 : CommonMsr.h
  • MSR_SMRAM_CR3 : CommonMsr.h
  • MSR_SMRAM_CR4 : CommonMsr.h
  • MSR_SMRAM_CS_ES : CommonMsr.h
  • MSR_SMRAM_DR6 : CommonMsr.h
  • MSR_SMRAM_DR7 : CommonMsr.h
  • MSR_SMRAM_DS_SS : CommonMsr.h
  • MSR_SMRAM_EFER : CommonMsr.h
  • MSR_SMRAM_EFLAGS : CommonMsr.h
  • MSR_SMRAM_EPTP : CommonMsr.h
  • MSR_SMRAM_EPTP_ENABLE : CommonMsr.h
  • MSR_SMRAM_EVENT_CTL_HLT_IO : CommonMsr.h
  • MSR_SMRAM_GDTR_BASE : CommonMsr.h
  • MSR_SMRAM_GS_FS : CommonMsr.h
  • MSR_SMRAM_IDTR_BASE : CommonMsr.h
  • MSR_SMRAM_IEDBASE : CommonMsr.h
  • MSR_SMRAM_IO_MEM_ADDR : CommonMsr.h
  • MSR_SMRAM_IO_RCX : CommonMsr.h
  • MSR_SMRAM_IO_RDI : CommonMsr.h
  • MSR_SMRAM_IO_RIP : CommonMsr.h
  • MSR_SMRAM_IO_RSI : CommonMsr.h
  • MSR_SMRAM_IOMISCINFO : CommonMsr.h
  • MSR_SMRAM_LDTR_BASE : CommonMsr.h
  • MSR_SMRAM_R10 : CommonMsr.h
  • MSR_SMRAM_R11 : CommonMsr.h
  • MSR_SMRAM_R12 : CommonMsr.h
  • MSR_SMRAM_R13 : CommonMsr.h
  • MSR_SMRAM_R14 : CommonMsr.h
  • MSR_SMRAM_R15 : CommonMsr.h
  • MSR_SMRAM_R8 : CommonMsr.h
  • MSR_SMRAM_R9 : CommonMsr.h
  • MSR_SMRAM_RAX : CommonMsr.h
  • MSR_SMRAM_RBP : CommonMsr.h
  • MSR_SMRAM_RBX : CommonMsr.h
  • MSR_SMRAM_RCX : CommonMsr.h
  • MSR_SMRAM_RDI : CommonMsr.h
  • MSR_SMRAM_RDX : CommonMsr.h
  • MSR_SMRAM_RIP : CommonMsr.h
  • MSR_SMRAM_RSI : CommonMsr.h
  • MSR_SMRAM_RSP : CommonMsr.h
  • MSR_SMRAM_SMBASE : CommonMsr.h
  • MSR_SMRAM_SMM_REVID : CommonMsr.h
  • MSR_SMRAM_TR_LDTR : CommonMsr.h
  • MSR_SMRR2_BASE : CommonMsr.h
  • MSR_SMRR2_MASK : CommonMsr.h
  • MSR_SMRR_BASE : CommonMsr.h
  • MSR_SMRR_MASK : CommonMsr.h
  • MSR_SNC_CONFIG : CommonMsr.h
  • MSR_SNC_RANGE0_BASE : CommonMsr.h
  • MSR_SNC_RANGE1_BASE : CommonMsr.h
  • MSR_SNC_RANGE2_BASE : CommonMsr.h
  • MSR_SNC_RANGE3_BASE : CommonMsr.h
  • MSR_SNC_RANGE4_BASE : CommonMsr.h
  • MSR_SNC_UPPER_BASE : CommonMsr.h
  • MSR_SOCKET_ID : CommonMsr.h
  • MSR_SPCL_CHIPSET_USAGE : CommonMsr.h
  • MSR_SPCL_UNCORE_USAGE : CommonMsr.h
  • MSR_SPEC_CTRL : ArchMsr.h
  • MSR_SSKU_CMD : CommonMsr.h
  • MSR_SSKU_DATA : CommonMsr.h
  • MSR_SSKU_ENFORCE : CommonMsr.h
  • MSR_SSKU_SMM_ADDR : CommonMsr.h
  • MSR_SSKU_SMM_DATA : CommonMsr.h
  • MSR_STAR : ArchMsr.h
  • MSR_SUPPRESS_SHUTDOWN : CommonMsr.h
  • MSR_SW_LTR_OVRD : CommonMsr.h
  • MSR_SYSENTER_CS : ArchMsr.h
  • MSR_SYSENTER_EIP : ArchMsr.h
  • MSR_SYSENTER_ESP : ArchMsr.h
  • MSR_TASK_SWITCH_OR_PROBE_MODE_MISC : CommonMsr.h
  • MSR_TASK_SWITCH_OR_SMI_RIP : CommonMsr.h
  • MSR_TCS_PA : CommonMsr.h
  • MSR_TEMPERATURE_TARGET : CommonMsr.h
  • MSR_THD_LOGICAL_ID : CommonMsr.h
  • MSR_THERM_EVENT_FFM : CommonMsr.h
  • MSR_THERM_INTERRUPT : ArchMsr.h
  • MSR_THERM_STATUS : ArchMsr.h
  • MSR_THREAD_INFO : CommonMsr.h
  • MSR_THREAD_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_THREAD_SMI_ERR_SRC : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_0_0 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_10_10 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_11_11 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_12_12 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_13_13 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_1_1 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_2_2 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_3_3 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_4_4 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_5_5 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_6_6 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_7_7 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_8_8 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_9_9 : CommonMsr.h
  • MSR_THREAD_STALL_COUNTER : CommonMsr.h
  • MSR_THREAD_SW_DEFEATURE : CommonMsr.h
  • MSR_TIME_STAMP_COUNTER : ArchMsr.h
  • MSR_TIO_COPY_ENCRYPT : CommonMsr.h
  • MSR_TIO_DEBUG_STATUS : CommonMsr.h
  • MSR_TIO_PM_DEBUG_STATUS : CommonMsr.h
  • MSR_TIO_PRM_CLEANUP : CommonMsr.h
  • MSR_TIO_UNWRAP : CommonMsr.h
  • MSR_TIORR_PHYSBASE : CommonMsr.h
  • MSR_TIORR_PHYSMASK : CommonMsr.h
  • MSR_TME_ACTIVATE : ArchMsr.h
  • MSR_TME_CAPABILITY : ArchMsr.h
  • MSR_TME_EXCLUDE_BASE : ArchMsr.h
  • MSR_TME_EXCLUDE_MASK : ArchMsr.h
  • MSR_TMPDR6 : CommonMsr.h
  • MSR_TSC_AUX : ArchMsr.h
  • MSR_TSC_DEADLINE : ArchMsr.h
  • MSR_TSC_THREAD_OFFSET : ArchMsr.h
  • MSR_TURBO_ACTIVATION_RATIO : CommonMsr.h
  • MSR_TURBO_RATIO_LIMIT : CpuRegs.h
  • MSR_TURBO_RATIO_LIMIT_CORES : CommonMsr.h
  • MSR_U_CET : ArchMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL0 : CommonMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL1 : CommonMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR : CommonMsr.h
  • MSR_ULI_TARGET_RIP : CommonMsr.h
  • MSR_ULI_VECTOR_INFO : CommonMsr.h
  • MSR_UNCORE_PERF_STATUS : CommonMsr.h
  • MSR_UNCORE_RATIO_LIMIT : CommonMsr.h
  • MSR_UNCORE_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_UNCORE_SMI_ERR_SRC : CommonMsr.h
  • MSR_UNCORE_SPARE_0_0 : CommonMsr.h
  • MSR_UNCORE_SPARE_10_10 : CommonMsr.h
  • MSR_UNCORE_SPARE_11_11 : CommonMsr.h
  • MSR_UNCORE_SPARE_12_12 : CommonMsr.h
  • MSR_UNCORE_SPARE_13_13 : CommonMsr.h
  • MSR_UNCORE_SPARE_1_1 : CommonMsr.h
  • MSR_UNCORE_SPARE_2_2 : CommonMsr.h
  • MSR_UNCORE_SPARE_3_3 : CommonMsr.h
  • MSR_UNCORE_SPARE_4_4 : CommonMsr.h
  • MSR_UNCORE_SPARE_5_5 : CommonMsr.h
  • MSR_UNCORE_SPARE_6_6 : CommonMsr.h
  • MSR_UNCORE_SPARE_7_7 : CommonMsr.h
  • MSR_UNCORE_SPARE_8_8 : CommonMsr.h
  • MSR_UNCORE_SPARE_9_9 : CommonMsr.h
  • MSR_VIRTUAL_APIC_0_0 : CommonMsr.h
  • MSR_VIRTUAL_APIC_100_100 : CommonMsr.h
  • MSR_VIRTUAL_APIC_101_101 : CommonMsr.h
  • MSR_VIRTUAL_APIC_102_102 : CommonMsr.h
  • MSR_VIRTUAL_APIC_103_103 : CommonMsr.h
  • MSR_VIRTUAL_APIC_104_104 : CommonMsr.h
  • MSR_VIRTUAL_APIC_105_105 : CommonMsr.h
  • MSR_VIRTUAL_APIC_106_106 : CommonMsr.h
  • MSR_VIRTUAL_APIC_107_107 : CommonMsr.h
  • MSR_VIRTUAL_APIC_108_108 : CommonMsr.h
  • MSR_VIRTUAL_APIC_109_109 : CommonMsr.h
  • MSR_VIRTUAL_APIC_10_10 : CommonMsr.h
  • MSR_VIRTUAL_APIC_110_110 : CommonMsr.h
  • MSR_VIRTUAL_APIC_111_111 : CommonMsr.h
  • MSR_VIRTUAL_APIC_112_112 : CommonMsr.h
  • MSR_VIRTUAL_APIC_113_113 : CommonMsr.h
  • MSR_VIRTUAL_APIC_114_114 : CommonMsr.h
  • MSR_VIRTUAL_APIC_115_115 : CommonMsr.h
  • MSR_VIRTUAL_APIC_116_116 : CommonMsr.h
  • MSR_VIRTUAL_APIC_117_117 : CommonMsr.h
  • MSR_VIRTUAL_APIC_118_118 : CommonMsr.h
  • MSR_VIRTUAL_APIC_119_119 : CommonMsr.h
  • MSR_VIRTUAL_APIC_11_11 : CommonMsr.h
  • MSR_VIRTUAL_APIC_120_120 : CommonMsr.h
  • MSR_VIRTUAL_APIC_121_121 : CommonMsr.h
  • MSR_VIRTUAL_APIC_122_122 : CommonMsr.h
  • MSR_VIRTUAL_APIC_123_123 : CommonMsr.h
  • MSR_VIRTUAL_APIC_124_124 : CommonMsr.h
  • MSR_VIRTUAL_APIC_125_125 : CommonMsr.h
  • MSR_VIRTUAL_APIC_126_126 : CommonMsr.h
  • MSR_VIRTUAL_APIC_127_127 : CommonMsr.h
  • MSR_VIRTUAL_APIC_128_128 : CommonMsr.h
  • MSR_VIRTUAL_APIC_129_129 : CommonMsr.h
  • MSR_VIRTUAL_APIC_12_12 : CommonMsr.h
  • MSR_VIRTUAL_APIC_130_130 : CommonMsr.h
  • MSR_VIRTUAL_APIC_131_131 : CommonMsr.h
  • MSR_VIRTUAL_APIC_132_132 : CommonMsr.h
  • MSR_VIRTUAL_APIC_133_133 : CommonMsr.h
  • MSR_VIRTUAL_APIC_134_134 : CommonMsr.h
  • MSR_VIRTUAL_APIC_135_135 : CommonMsr.h
  • MSR_VIRTUAL_APIC_136_136 : CommonMsr.h
  • MSR_VIRTUAL_APIC_137_137 : CommonMsr.h
  • MSR_VIRTUAL_APIC_138_138 : CommonMsr.h
  • MSR_VIRTUAL_APIC_139_139 : CommonMsr.h
  • MSR_VIRTUAL_APIC_13_13 : CommonMsr.h
  • MSR_VIRTUAL_APIC_140_140 : CommonMsr.h
  • MSR_VIRTUAL_APIC_141_141 : CommonMsr.h
  • MSR_VIRTUAL_APIC_142_142 : CommonMsr.h
  • MSR_VIRTUAL_APIC_143_143 : CommonMsr.h
  • MSR_VIRTUAL_APIC_144_144 : CommonMsr.h
  • MSR_VIRTUAL_APIC_145_145 : CommonMsr.h
  • MSR_VIRTUAL_APIC_146_146 : CommonMsr.h
  • MSR_VIRTUAL_APIC_147_147 : CommonMsr.h
  • MSR_VIRTUAL_APIC_148_148 : CommonMsr.h
  • MSR_VIRTUAL_APIC_149_149 : CommonMsr.h
  • MSR_VIRTUAL_APIC_14_14 : CommonMsr.h
  • MSR_VIRTUAL_APIC_150_150 : CommonMsr.h
  • MSR_VIRTUAL_APIC_151_151 : CommonMsr.h
  • MSR_VIRTUAL_APIC_152_152 : CommonMsr.h
  • MSR_VIRTUAL_APIC_153_153 : CommonMsr.h
  • MSR_VIRTUAL_APIC_154_154 : CommonMsr.h
  • MSR_VIRTUAL_APIC_155_155 : CommonMsr.h
  • MSR_VIRTUAL_APIC_156_156 : CommonMsr.h
  • MSR_VIRTUAL_APIC_157_157 : CommonMsr.h
  • MSR_VIRTUAL_APIC_158_158 : CommonMsr.h
  • MSR_VIRTUAL_APIC_159_159 : CommonMsr.h
  • MSR_VIRTUAL_APIC_15_15 : CommonMsr.h
  • MSR_VIRTUAL_APIC_160_160 : CommonMsr.h
  • MSR_VIRTUAL_APIC_161_161 : CommonMsr.h
  • MSR_VIRTUAL_APIC_162_162 : CommonMsr.h
  • MSR_VIRTUAL_APIC_163_163 : CommonMsr.h
  • MSR_VIRTUAL_APIC_164_164 : CommonMsr.h
  • MSR_VIRTUAL_APIC_165_165 : CommonMsr.h
  • MSR_VIRTUAL_APIC_166_166 : CommonMsr.h
  • MSR_VIRTUAL_APIC_167_167 : CommonMsr.h
  • MSR_VIRTUAL_APIC_168_168 : CommonMsr.h
  • MSR_VIRTUAL_APIC_169_169 : CommonMsr.h
  • MSR_VIRTUAL_APIC_16_16 : CommonMsr.h
  • MSR_VIRTUAL_APIC_170_170 : CommonMsr.h
  • MSR_VIRTUAL_APIC_171_171 : CommonMsr.h
  • MSR_VIRTUAL_APIC_172_172 : CommonMsr.h
  • MSR_VIRTUAL_APIC_173_173 : CommonMsr.h
  • MSR_VIRTUAL_APIC_174_174 : CommonMsr.h
  • MSR_VIRTUAL_APIC_175_175 : CommonMsr.h
  • MSR_VIRTUAL_APIC_176_176 : CommonMsr.h
  • MSR_VIRTUAL_APIC_177_177 : CommonMsr.h
  • MSR_VIRTUAL_APIC_178_178 : CommonMsr.h
  • MSR_VIRTUAL_APIC_179_179 : CommonMsr.h
  • MSR_VIRTUAL_APIC_17_17 : CommonMsr.h
  • MSR_VIRTUAL_APIC_180_180 : CommonMsr.h
  • MSR_VIRTUAL_APIC_181_181 : CommonMsr.h
  • MSR_VIRTUAL_APIC_182_182 : CommonMsr.h
  • MSR_VIRTUAL_APIC_183_183 : CommonMsr.h
  • MSR_VIRTUAL_APIC_184_184 : CommonMsr.h
  • MSR_VIRTUAL_APIC_185_185 : CommonMsr.h
  • MSR_VIRTUAL_APIC_186_186 : CommonMsr.h
  • MSR_VIRTUAL_APIC_187_187 : CommonMsr.h
  • MSR_VIRTUAL_APIC_188_188 : CommonMsr.h
  • MSR_VIRTUAL_APIC_189_189 : CommonMsr.h
  • MSR_VIRTUAL_APIC_18_18 : CommonMsr.h
  • MSR_VIRTUAL_APIC_190_190 : CommonMsr.h
  • MSR_VIRTUAL_APIC_191_191 : CommonMsr.h
  • MSR_VIRTUAL_APIC_192_192 : CommonMsr.h
  • MSR_VIRTUAL_APIC_193_193 : CommonMsr.h
  • MSR_VIRTUAL_APIC_194_194 : CommonMsr.h
  • MSR_VIRTUAL_APIC_195_195 : CommonMsr.h
  • MSR_VIRTUAL_APIC_196_196 : CommonMsr.h
  • MSR_VIRTUAL_APIC_197_197 : CommonMsr.h
  • MSR_VIRTUAL_APIC_198_198 : CommonMsr.h
  • MSR_VIRTUAL_APIC_199_199 : CommonMsr.h
  • MSR_VIRTUAL_APIC_19_19 : CommonMsr.h
  • MSR_VIRTUAL_APIC_1_1 : CommonMsr.h
  • MSR_VIRTUAL_APIC_200_200 : CommonMsr.h
  • MSR_VIRTUAL_APIC_201_201 : CommonMsr.h
  • MSR_VIRTUAL_APIC_202_202 : CommonMsr.h
  • MSR_VIRTUAL_APIC_203_203 : CommonMsr.h
  • MSR_VIRTUAL_APIC_204_204 : CommonMsr.h
  • MSR_VIRTUAL_APIC_205_205 : CommonMsr.h
  • MSR_VIRTUAL_APIC_206_206 : CommonMsr.h
  • MSR_VIRTUAL_APIC_207_207 : CommonMsr.h
  • MSR_VIRTUAL_APIC_208_208 : CommonMsr.h
  • MSR_VIRTUAL_APIC_209_209 : CommonMsr.h
  • MSR_VIRTUAL_APIC_20_20 : CommonMsr.h
  • MSR_VIRTUAL_APIC_210_210 : CommonMsr.h
  • MSR_VIRTUAL_APIC_211_211 : CommonMsr.h
  • MSR_VIRTUAL_APIC_21_21 : CommonMsr.h
  • MSR_VIRTUAL_APIC_22_22 : CommonMsr.h
  • MSR_VIRTUAL_APIC_23_23 : CommonMsr.h
  • MSR_VIRTUAL_APIC_24_24 : CommonMsr.h
  • MSR_VIRTUAL_APIC_25_25 : CommonMsr.h
  • MSR_VIRTUAL_APIC_26_26 : CommonMsr.h
  • MSR_VIRTUAL_APIC_27_27 : CommonMsr.h
  • MSR_VIRTUAL_APIC_28_28 : CommonMsr.h
  • MSR_VIRTUAL_APIC_29_29 : CommonMsr.h
  • MSR_VIRTUAL_APIC_2_2 : CommonMsr.h
  • MSR_VIRTUAL_APIC_30_30 : CommonMsr.h
  • MSR_VIRTUAL_APIC_31_31 : CommonMsr.h
  • MSR_VIRTUAL_APIC_32_32 : CommonMsr.h
  • MSR_VIRTUAL_APIC_33_33 : CommonMsr.h
  • MSR_VIRTUAL_APIC_34_34 : CommonMsr.h
  • MSR_VIRTUAL_APIC_35_35 : CommonMsr.h
  • MSR_VIRTUAL_APIC_36_36 : CommonMsr.h
  • MSR_VIRTUAL_APIC_37_37 : CommonMsr.h
  • MSR_VIRTUAL_APIC_38_38 : CommonMsr.h
  • MSR_VIRTUAL_APIC_39_39 : CommonMsr.h
  • MSR_VIRTUAL_APIC_3_3 : CommonMsr.h
  • MSR_VIRTUAL_APIC_40_40 : CommonMsr.h
  • MSR_VIRTUAL_APIC_41_41 : CommonMsr.h
  • MSR_VIRTUAL_APIC_42_42 : CommonMsr.h
  • MSR_VIRTUAL_APIC_43_43 : CommonMsr.h
  • MSR_VIRTUAL_APIC_44_44 : CommonMsr.h
  • MSR_VIRTUAL_APIC_45_45 : CommonMsr.h
  • MSR_VIRTUAL_APIC_46_46 : CommonMsr.h
  • MSR_VIRTUAL_APIC_47_47 : CommonMsr.h
  • MSR_VIRTUAL_APIC_48_48 : CommonMsr.h
  • MSR_VIRTUAL_APIC_49_49 : CommonMsr.h
  • MSR_VIRTUAL_APIC_4_4 : CommonMsr.h
  • MSR_VIRTUAL_APIC_50_50 : CommonMsr.h
  • MSR_VIRTUAL_APIC_51_51 : CommonMsr.h
  • MSR_VIRTUAL_APIC_52_52 : CommonMsr.h
  • MSR_VIRTUAL_APIC_53_53 : CommonMsr.h
  • MSR_VIRTUAL_APIC_54_54 : CommonMsr.h
  • MSR_VIRTUAL_APIC_55_55 : CommonMsr.h
  • MSR_VIRTUAL_APIC_56_56 : CommonMsr.h
  • MSR_VIRTUAL_APIC_57_57 : CommonMsr.h
  • MSR_VIRTUAL_APIC_58_58 : CommonMsr.h
  • MSR_VIRTUAL_APIC_59_59 : CommonMsr.h
  • MSR_VIRTUAL_APIC_5_5 : CommonMsr.h
  • MSR_VIRTUAL_APIC_60_60 : CommonMsr.h
  • MSR_VIRTUAL_APIC_61_61 : CommonMsr.h
  • MSR_VIRTUAL_APIC_62_62 : CommonMsr.h
  • MSR_VIRTUAL_APIC_63_63 : CommonMsr.h
  • MSR_VIRTUAL_APIC_64_64 : CommonMsr.h
  • MSR_VIRTUAL_APIC_65_65 : CommonMsr.h
  • MSR_VIRTUAL_APIC_66_66 : CommonMsr.h
  • MSR_VIRTUAL_APIC_67_67 : CommonMsr.h
  • MSR_VIRTUAL_APIC_68_68 : CommonMsr.h
  • MSR_VIRTUAL_APIC_69_69 : CommonMsr.h
  • MSR_VIRTUAL_APIC_6_6 : CommonMsr.h
  • MSR_VIRTUAL_APIC_70_70 : CommonMsr.h
  • MSR_VIRTUAL_APIC_71_71 : CommonMsr.h
  • MSR_VIRTUAL_APIC_72_72 : CommonMsr.h
  • MSR_VIRTUAL_APIC_73_73 : CommonMsr.h
  • MSR_VIRTUAL_APIC_74_74 : CommonMsr.h
  • MSR_VIRTUAL_APIC_75_75 : CommonMsr.h
  • MSR_VIRTUAL_APIC_76_76 : CommonMsr.h
  • MSR_VIRTUAL_APIC_77_77 : CommonMsr.h
  • MSR_VIRTUAL_APIC_78_78 : CommonMsr.h
  • MSR_VIRTUAL_APIC_79_79 : CommonMsr.h
  • MSR_VIRTUAL_APIC_7_7 : CommonMsr.h
  • MSR_VIRTUAL_APIC_80_80 : CommonMsr.h
  • MSR_VIRTUAL_APIC_81_81 : CommonMsr.h
  • MSR_VIRTUAL_APIC_82_82 : CommonMsr.h
  • MSR_VIRTUAL_APIC_83_83 : CommonMsr.h
  • MSR_VIRTUAL_APIC_84_84 : CommonMsr.h
  • MSR_VIRTUAL_APIC_85_85 : CommonMsr.h
  • MSR_VIRTUAL_APIC_86_86 : CommonMsr.h
  • MSR_VIRTUAL_APIC_87_87 : CommonMsr.h
  • MSR_VIRTUAL_APIC_88_88 : CommonMsr.h
  • MSR_VIRTUAL_APIC_89_89 : CommonMsr.h
  • MSR_VIRTUAL_APIC_8_8 : CommonMsr.h
  • MSR_VIRTUAL_APIC_90_90 : CommonMsr.h
  • MSR_VIRTUAL_APIC_91_91 : CommonMsr.h
  • MSR_VIRTUAL_APIC_92_92 : CommonMsr.h
  • MSR_VIRTUAL_APIC_93_93 : CommonMsr.h
  • MSR_VIRTUAL_APIC_94_94 : CommonMsr.h
  • MSR_VIRTUAL_APIC_95_95 : CommonMsr.h
  • MSR_VIRTUAL_APIC_96_96 : CommonMsr.h
  • MSR_VIRTUAL_APIC_97_97 : CommonMsr.h
  • MSR_VIRTUAL_APIC_98_98 : CommonMsr.h
  • MSR_VIRTUAL_APIC_99_99 : CommonMsr.h
  • MSR_VIRTUAL_APIC_9_9 : CommonMsr.h
  • MSR_VLW_CAPABILITY : CommonMsr.h
  • MSR_VMCS_CACHE_BASE : CommonMsr.h
  • MSR_VMSR_U2P_0_0 : CommonMsr.h
  • MSR_VMSR_U2P_1_1 : CommonMsr.h
  • MSR_VMSR_U2P_2_2 : CommonMsr.h
  • MSR_VMSR_U2P_3_3 : CommonMsr.h
  • MSR_VMX_AVRR_REMAP : CommonMsr.h
  • MSR_VMX_IO_EXIT_QUAL : CommonMsr.h
  • MSR_VMX_MSEG_BASE : CommonMsr.h
  • MSR_VMX_MSR_0 : ArchMsr.h
  • MSR_VMX_MSR_1 : ArchMsr.h
  • MSR_VMX_MSR_10 : ArchMsr.h
  • MSR_VMX_MSR_11 : ArchMsr.h
  • MSR_VMX_MSR_12 : ArchMsr.h
  • MSR_VMX_MSR_2 : ArchMsr.h
  • MSR_VMX_MSR_3 : ArchMsr.h
  • MSR_VMX_MSR_4 : ArchMsr.h
  • MSR_VMX_MSR_5 : ArchMsr.h
  • MSR_VMX_MSR_6 : ArchMsr.h
  • MSR_VMX_MSR_7 : ArchMsr.h
  • MSR_VMX_MSR_8 : ArchMsr.h
  • MSR_VMX_MSR_9 : ArchMsr.h
  • MSR_VMX_PLE_FIRST : CommonMsr.h
  • MSR_VMX_PLE_LAST : CommonMsr.h
  • MSR_VMX_PROCBASED_CTLS3 : ArchMsr.h
  • MSR_VMX_TRUE_ENTRY_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_EXIT_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_PINBASED_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_PROCBASED_CTLS : ArchMsr.h
  • MSR_VMX_VMENTRY_AVRR_TBIT_MAILBOX : CommonMsr.h
  • MSR_VMX_VMFUNC_CTLS : ArchMsr.h
  • MSR_VMX_VPPR : CommonMsr.h
  • MSR_VR_CURRENT_CONFIG : CommonMsr.h
  • MSR_VR_MISC_CONFIG2 : CommonMsr.h
  • MSR_XCR0 : CommonMsr.h
  • MSR_XRSTOR_INFO : CommonMsr.h
  • MSR_XRSTOR_XCOMPACTION_VECTOR : CommonMsr.h
  • MSR_XU_MACROINSTRUCTION_ALIAS : CommonMsr.h
  • MSR_XU_RESERVED_10_10 : CommonMsr.h
  • MSR_XU_RESERVED_11_11 : CommonMsr.h
  • MSR_XU_RESERVED_12_12 : CommonMsr.h
  • MSR_XU_RESERVED_13_13 : CommonMsr.h
  • MSR_XU_RESERVED_14_14 : CommonMsr.h
  • MSR_XU_RESERVED_15_15 : CommonMsr.h
  • MSR_XU_RESERVED_16_16 : CommonMsr.h
  • MSR_XU_RESERVED_17_17 : CommonMsr.h
  • MSR_XU_RESERVED_18_18 : CommonMsr.h
  • MSR_XU_RESERVED_19_19 : CommonMsr.h
  • MSR_XU_RESERVED_1_1 : CommonMsr.h
  • MSR_XU_RESERVED_20_20 : CommonMsr.h
  • MSR_XU_RESERVED_21_21 : CommonMsr.h
  • MSR_XU_RESERVED_22_22 : CommonMsr.h
  • MSR_XU_RESERVED_23_23 : CommonMsr.h
  • MSR_XU_RESERVED_24_24 : CommonMsr.h
  • MSR_XU_RESERVED_25_25 : CommonMsr.h
  • MSR_XU_RESERVED_26_26 : CommonMsr.h
  • MSR_XU_RESERVED_27_27 : CommonMsr.h
  • MSR_XU_RESERVED_28_28 : CommonMsr.h
  • MSR_XU_RESERVED_29_29 : CommonMsr.h
  • MSR_XU_RESERVED_2_2 : CommonMsr.h
  • MSR_XU_RESERVED_30_30 : CommonMsr.h
  • MSR_XU_RESERVED_31_31 : CommonMsr.h
  • MSR_XU_RESERVED_3_3 : CommonMsr.h
  • MSR_XU_RESERVED_4_4 : CommonMsr.h
  • MSR_XU_RESERVED_5_5 : CommonMsr.h
  • MSR_XU_RESERVED_6_6 : CommonMsr.h
  • MSR_XU_RESERVED_7_7 : CommonMsr.h
  • MSR_XU_RESERVED_8_8 : CommonMsr.h
  • MSR_XU_RESERVED_9_9 : CommonMsr.h
  • MSR_XU_SMM_STATE : CommonMsr.h
  • MSR_XU_TIO_CF_INFO : CommonMsr.h
  • MSR_XU_TIO_CF_TABLE : CommonMsr.h
  • MSR_XU_VMX_CONTROL : CommonMsr.h
  • MSR_XUCODE_UCODE_COMMAND : CommonMsr.h
  • MtrrTransfer2DefaultWB() : SiMtrrLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- n -

  • N_ESPI_CFG_PCBC_BWPDS : PchRegsLpc.h
  • N_ESPI_CFG_PCBC_BWRE : PchRegsLpc.h
  • N_ESPI_CFG_PCBC_BWRS : PchRegsLpc.h
  • N_ESPI_PCR_FCERR_SLV0_FCFEE : PchRegsLpc.h
  • N_ESPI_PCR_FCERR_SLV0_FCNFEE : PchRegsLpc.h
  • N_ESPI_PCR_LNKERR_SLV0_LFET1E : PchRegsLpc.h
  • N_ESPI_PCR_LNKERR_SLV1_LFET1E : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCFEE : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCNFEE : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCRMTARE : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SID : PchRegsLpc.h
  • N_ESPI_PCR_VWERR_VWFEE : PchRegsLpc.h
  • N_ESPI_PCR_VWERR_VWNFEE : PchRegsLpc.h
  • N_ESPI_PCR_XERR_XFEE : PchRegsLpc.h
  • N_ESPI_PCR_XERR_XNFEE : PchRegsLpc.h
  • N_FLASH_FDBAR_CPUSL : FlashRegs.h
  • N_FLASH_FDBAR_FCPUSBA : FlashRegs.h
  • N_FLASH_FDBAR_FPSBA : FlashRegs.h
  • N_FLASH_FDBAR_FPSBA_REPR : FlashRegs.h
  • N_FLASH_FDBAR_NC : FlashRegs.h
  • N_FLASH_FDBAR_PCHSL : FlashRegs.h
  • N_FLASH_FLCOMP_COMP1 : FlashRegs.h
  • N_FLASH_UMAP1_MDTBA : FlashRegs.h
  • N_FLASH_UMAP1_MDTBA_REPR : FlashRegs.h
  • N_HDC_SUPPORT : CpuPowerMgmt.h
  • N_PCH_DMI15_PCR_CTRL1_L1PL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L0246TPOSTCO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L0246TPRECO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L1357TPOSTCO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L1357TPRECO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_MPC2_ORCE : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_MPC2_PLLWAIT : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PWRCTL_RPSEWL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS0TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS1TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS2TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS3TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPL0246TP : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPL1357TP : PchDmi15Regs.h
  • N_PCH_DMI_PCR_GPMRX_GPMRL1 : PchDmiRegs.h
  • N_PCH_DMI_PCR_LCAP_EL0 : PchDmiRegs.h
  • N_PCH_DMI_PCR_LCAP_EL1 : PchDmiRegs.h
  • N_PCIE_SLCAP_PSN : PcieRegs.h
  • N_PCIE_SLCAP_SLS : PcieRegs.h
  • N_PCIE_SLCAP_SLV : PcieRegs.h
  • N_PMC_DEF_CPU_BCLK_CFG : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_CMD_ID : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_COMMAND : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_SIZE : PmcRegs.h
  • N_PMC_PWRM_PM_CFG2_PBOP : PmcRegs.h
  • N_SATA_MEM_AHCI_CAP_ISS : SataRegs.h
  • N_XHCI_CFG_XHCC2_WRREQSZCTRL : UsbRegs.h
  • N_XHCI_MEM_D0I2CTRL_MSID0I2PWT : UsbRegs.h
  • N_XHCI_MEM_D0I2SCH_ALARM_CTRL_D0I2IT : UsbRegs.h
  • N_XHCI_MEM_DBC_DBCCTL_DISC_RXD_CNT : UsbRegs.h
  • N_XHCI_MEM_XECP_SUPP_USBX_2_CPC : UsbRegs.h
  • NiftyRockSupportLevel() : CpuPlatformLib.h
  • NO_STRING_AVAILABLE : SiFvi.h , SiFviLib.h
  • NOP : IndustryStandardAsf.h
  • NPCR_NOTIFICATION_CMD : BupMsgs.h
  • NumberOfCpuSocketsPopulated() : CpuPlatformLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- o -

  • OC_MAILBOX_FULL : CpuMailboxLib.h
  • OC_MAILBOX_INTERFACE : CpuMailboxLib.h
  • OcWdtInit() : OcWdtLib.h
  • OcWdtResetCheck() : OcWdtLib.h
  • OEM_CAPS_1_RESERVED_BITMASK : MeSmbios.h
  • OEM_CAPS_2_TERMINAL_EMULATION_VT100PLUS : MeSmbios.h
  • OEM_CAPS_3_SECURE_ERASE_BIT_OFFSET : MeSmbios.h
  • OEM_CAPS_4_VPRO_TBT_DOCK_BIT_OFFSET : MeSmbios.h
  • ONE_CLICK_RECOVERY_CAPABILITIES : OneClickRecoveryProtocol.h
  • ONE_CLICK_RECOVERY_ENTRY : OneClickRecoveryProtocol.h
  • ONE_CLICK_RECOVERY_PROTOCOL_REVISION : OneClickRecoveryProtocol.h
  • ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION : OneClickRecoveryProtocol.h
  • OPTIN_POLICY_BITMAP : AmthiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- p -

  • P2sbDevNumber() : PchPciBdfLib.h
  • P2sbFuncNumber() : PchPciBdfLib.h
  • P2sbGetEpmask() : P2sbLib.h
  • P2sbIsEpmaskLock() : P2sbLib.h
  • P2sbPciCfgBase() : PchPciBdfLib.h
  • PCH_ACPI_SMI_DISPATCH_CALLBACK : PchAcpiSmiDispatch.h
  • PCH_ACPI_SMI_DISPATCH_REGISTER : PchAcpiSmiDispatch.h
  • PCH_ACPI_SMI_DISPATCH_REVISION : PchAcpiSmiDispatch.h
  • PCH_ACPI_SMI_DISPATCH_UNREGISTER : PchAcpiSmiDispatch.h
  • PCH_ESPI_SMI_DISPATCH_CALLBACK : PchEspiSmiDispatch.h
  • PCH_ESPI_SMI_DISPATCH_REVISION : PchEspiSmiDispatch.h
  • PCH_ESPI_SMI_REGISTER : PchEspiSmiDispatch.h
  • PCH_ESPI_SMI_UNREGISTER : PchEspiSmiDispatch.h
  • PCH_FIVR_CONFIG_REVISION : FivrConfig.h
  • PCH_FVI_STRING : SiFvi.h
  • PCH_GPIO_2_TIER_MASTER_GPE_NUMBER : GpioRegs.h
  • PCH_GPIO_NUM_SUPPORTED_GPIS : GpioRegs.h
  • PCH_INT_PIN : InterruptConfig.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_SMI_DISPATCH_REVISION : PchPcieSmiDispatch.h
  • PCH_PCIE_SMI_DISPATCH_UNREGISTER : PchPcieSmiDispatch.h
  • PCH_PCIE_SMI_RP_DISPATCH_CALLBACK : PchPcieSmiDispatch.h
  • PCH_PCIE_SMI_RP_DISPATCH_REGISTER : PchPcieSmiDispatch.h
  • PCH_PCR_ADDRESS : PchPcrLib.h
  • PCH_PCR_BOOT_SCRIPT_WRITE : PchPcrLib.h
  • PCH_PREMEM_POLICY : PchPreMemPolicyCommon.h
  • PCH_PREMEM_POLICY_REVISION : PchPreMemPolicyCommon.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PCH_SMI_DISPATCH_CALLBACK : PchSmiDispatch.h
  • PCH_SMI_DISPATCH_REGISTER : PchSmiDispatch.h
  • PCH_SMI_DISPATCH_REVISION : PchSmiDispatch.h
  • PCH_SMI_DISPATCH_UNREGISTER : PchSmiDispatch.h
  • PCH_SMM_IO_TRAP_CONTROL_FUNCTION : PchSmmIoTrapControl.h
  • PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION : PchSmmPeriodicTimerControl.h
  • PCH_SPI_FLASH_ERASE : Protocol/Spi.h
  • PCH_SPI_FLASH_READ : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_JEDEC_ID : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_SFDP : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_STATUS : Protocol/Spi.h
  • PCH_SPI_FLASH_WRITE : Protocol/Spi.h
  • PCH_SPI_FLASH_WRITE_STATUS : Protocol/Spi.h
  • PCH_SPI_GET_REGION_ADDRESS : Protocol/Spi.h
  • PCH_SPI_PPI : Ppi/Spi.h
  • PCH_SPI_READ_CPU_SOFTSTRAP : Protocol/Spi.h
  • PCH_SPI_READ_PCH_SOFTSTRAP : Protocol/Spi.h
  • PCH_SPI_SERVICES_REVISION : Protocol/Spi.h
  • PCH_TCO_SMI_DISPATCH_CALLBACK : PchTcoSmiDispatch.h
  • PCH_TCO_SMI_DISPATCH_REGISTER : PchTcoSmiDispatch.h
  • PCH_TCO_SMI_DISPATCH_REVISION : PchTcoSmiDispatch.h
  • PCH_TCO_SMI_DISPATCH_UNREGISTER : PchTcoSmiDispatch.h
  • PchAddConfigBlocks() : PchPolicyLib.h
  • PchAddPreMemConfigBlocks() : PchPolicyLib.h
  • PchBiosDecodeEnableSet() : PchCycleDecodingLib.h
  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchDmiGetExtendedBiosRegionRange() : PchDmiAccessLib.h
  • PchDmiIsBiosInterfaceLock() : PchDmiAccessLib.h
  • PchDmiIsExtendedBiosRegionLimitLocked() : PchDmiAccessLib.h
  • PchEspiCs1GenIoRangeGet() : PchCycleDecodingLib.h
  • PchEspiCs1GenIoRangeSet() : PchCycleDecodingLib.h
  • PchEspiCs1IoEnableDecodingSet() : PchCycleDecodingLib.h
  • PchEspiCs1MemRangeGet() : PchCycleDecodingLib.h
  • PchEspiCs1MemRangeSet() : PchCycleDecodingLib.h
  • PchEspiSlaveChannelReset() : EspiLib.h
  • PchEspiSlaveGetConfig() : EspiLib.h
  • PchEspiSlaveGetStatus() : EspiLib.h
  • PchEspiSlaveInBandReset() : EspiLib.h
  • PchEspiSlaveSetConfig() : EspiLib.h
  • PchGeneration() : PchInfoLib.h
  • PchGetConfigBlockTotalSize() : PchPolicyLib.h
  • PchGetLpcDid() : PchInfoLib.h
  • PchGetMaxUfsNum() : PchInfoLib.h
  • PchGetPcieControllerSbiPid() : PchPcieRpLib.h
  • PchGetPreMemConfigBlockTotalSize() : PchPolicyLib.h
  • PchGetSeriesStr() : PchInfoLib.h
  • PchGetSkuStr() : PchInfoLib.h
  • PchGetSteppingStr() : PchInfoLib.h
  • PchGetSupportedRstMode() : PchInfoLib.h
  • PchHeci1DevNumber() : PchPciBdfLib.h
  • PchHeci1FuncNumber() : PchPciBdfLib.h
  • PchHeci1PciCfgBase() : PchPciBdfLib.h
  • PchHeci3DevNumber() : PchPciBdfLib.h
  • PchHeci3FuncNumber() : PchPciBdfLib.h
  • PchHeci3PciCfgBase() : PchPciBdfLib.h
  • PchHpetBaseGet() : PchCycleDecodingLib.h
  • PchInstallPolicyProtocol() : DxePchPolicyLib.h
  • PchIoApicBaseGet() : PchCycleDecodingLib.h
  • PchIoPort80DecodeSet() : PchCycleDecodingLib.h
  • PchIsGbeSupported() : PchInfoLib.h
  • PchIsIshSupported() : PchInfoLib.h
  • PchIsPcieL0sSupported() : PchPcieRpLib.h
  • PchIsPcieNativeAspmSupported() : PchPcieRpLib.h
  • PchIsTsnSupported() : PchInfoLib.h
  • PchLpcGenIoRangeClear() : PchCycleDecodingLib.h
  • PchLpcGenIoRangeGet() : PchCycleDecodingLib.h
  • PchLpcGenIoRangeSet() : PchCycleDecodingLib.h
  • PchLpcIoDecodeRangesSet() : PchCycleDecodingLib.h
  • PchLpcIoEnableDecodingAndThenOr() : PchCycleDecodingLib.h
  • PchLpcIoEnableDecodingSet() : PchCycleDecodingLib.h
  • PchLpcMemRangeGet() : PchCycleDecodingLib.h
  • PchLpcMemRangeSet() : PchCycleDecodingLib.h
  • PchNoInt : InterruptConfig.h
  • PchPcieBase() : PchPcieRpLib.h
  • PchPcieRpDevNumber() : PchPciBdfLib.h
  • PchPcieRpFuncNumber() : PchPciBdfLib.h
  • PchPcieRpPciCfgBase() : PchPciBdfLib.h
  • PchPcrAndThenOr16() : PchPcrLib.h
  • PchPcrAndThenOr32() : PchPcrLib.h
  • PchPcrAndThenOr32WithReadback() : PchPcrLib.h
  • PchPcrAndThenOr8() : PchPcrLib.h
  • PchPcrGetPid() : PchPcrLib.h
  • PchPcrRead16() : PchPcrLib.h
  • PchPcrRead32() : PchPcrLib.h
  • PchPcrRead8() : PchPcrLib.h
  • PchPcrWrite16() : PchPcrLib.h
  • PchPcrWrite32() : PchPcrLib.h
  • PchPcrWrite8() : PchPcrLib.h
  • PchPreMemPrintPolicyPpi() : PchPolicyLib.h
  • PchPrintPolicyPpi() : PchPolicyLib.h
  • PchPrintPolicyProtocol() : DxePchPolicyLib.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSeries() : PchInfoLib.h
  • PchSlpS4PchTime : PmConfig.h
  • PchSmmControlInit() : PchSmmControlLib.h
  • PchStepping() : PchInfoLib.h
  • PchTcoBaseGet() : PchCycleDecodingLib.h
  • PchTcoBaseSet() : PchCycleDecodingLib.h
  • PchTraceHubDevNumber() : PchPciBdfLib.h
  • PchTraceHubFuncNumber() : PchPciBdfLib.h
  • PchTraceHubPciCfgBase() : PchPciBdfLib.h
  • PchXdciDevNumber() : PchPciBdfLib.h
  • PchXdciFuncNumber() : PchPciBdfLib.h
  • PchXdciPciCfgBase() : PchPciBdfLib.h
  • PchXhciDevNumber() : PchPciBdfLib.h
  • PchXhciFuncNumber() : PchPciBdfLib.h
  • PchXhciPciCfgBase() : PchPciBdfLib.h
  • PCIE2TBT_CONNECT_TOPOLOGY_COMMAND : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_GO2SX : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_GO2SX_NO_WAKE : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_SSID_SVID_CFG : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_SX_EXIT_TBT_CONNECTED : TbtMailBoxCmdDefinition.h
  • PCIE_BIFURCATION_CONFIG : PchPcieRpLib.h
  • PCIE_COMBINED_RPINDEX : PchPcieSmiDispatch.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h
  • PcieBaseFindCapId() : PcieHelperLib.h
  • PcieBaseFindExtendedCapId() : PcieHelperLib.h
  • PcieFindCapId() : PcieHelperLib.h
  • PcieFindExtendedCapId() : PcieHelperLib.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h
  • PcieRpClearSubordSecondBus() : PcieHelperLib.h
  • PcieRpSetSubordSecondBus() : PcieHelperLib.h
  • PCODE_MAILBOX_FULL : CpuMailboxLib.h
  • PCODE_MAILBOX_INTERFACE : CpuMailboxLib.h
  • PEI_ITBT_CONFIG : PeiITbtConfig.h
  • PEI_MR_SMRAM_ABSEG_MASK : MemoryConfig.h
  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h
  • PEI_SMM_ACTIVATE : SmmControl.h
  • PEI_SMM_DEACTIVATE : SmmControl.h
  • PEI_TPM_INITIALIZATION_DONE_PPI_GUID : TpmInitialized.h
  • PEI_TPM_INITIALIZED_PPI_GUID : TpmInitialized.h
  • PeiHeciBupManufacturingResetAndHalt() : PeiMeLib.h
  • PeiHeciCommitFilesMsg() : PeiMeLib.h
  • PeiHeciDataClear() : PeiMeLib.h
  • PeiHeciDnxReqSet() : PeiMeLib.h
  • PeiHeciFwCapsSetRuleData() : PeiMeLib.h
  • PeiHeciGetAmtBiosSyncInfo() : PeiMeLib.h
  • PeiHeciGetBiosSeed() : PeiMeLib.h
  • PeiHeciGetDebugTokenData() : PeiMeLib.h
  • PeiHeciGetErLog() : PeiMeLib.h
  • PeiHeciGetFwCapsSkuMsg() : PeiMeLib.h
  • PeiHeciGetFwFeatureStateMsg() : PeiMeLib.h
  • PeiHeciGetFwPayload() : PeiMeLib.h
  • PeiHeciGetImrSizeMsg() : PeiMeLib.h
  • PeiHeciGetMbpMsg() : PeiMeLib.h
  • PeiHeciGetPlatformTypeMsg() : PeiMeLib.h
  • PeiHeciGetRpmcStatus() : PeiMeLib.h
  • PeiHeciGetSoftStrpConfigMsg() : PeiMeLib.h
  • PeiHeciGetUnconfigOnRtcClearDisableMsg() : PeiMeLib.h
  • PeiHeciGetUnconfigureStatus() : PeiMeLib.h
  • PeiHeciIccBclkMsg() : PeiMeLib.h
  • PeiHeciOverrideSoftStrapMsg() : PeiMeLib.h
  • PeiHeciReadChipsetInitMsg() : PeiMeLib.h
  • PeiHeciReadFromMphy() : PeiMeLib.h
  • PeiHeciRequestDeviceOwnership() : PeiMeLib.h
  • PeiHeciSendCbmResetRequest() : PeiMeLib.h
  • PeiHeciSendDid() : PeiMeLib.h
  • PeiHeciSendHostResetNotificationMsg() : PeiMeLib.h
  • PeiHeciSetEDebugModeState() : PeiMeLib.h
  • PeiHeciSetFileExMsg() : PeiMeLib.h
  • PeiHeciSetUnconfigOnRtcClearDisableMsg() : PeiMeLib.h
  • PeiHeciTerminateHeci() : PeiMeLib.h
  • PeiHeciWriteChipsetInitMsg() : PeiMeLib.h
  • PERIPHERAL_EMBEDDED_CONTROLLER : IntelAsfExtensions.h
  • PLAT_ID_FEATURE : UpidMsgs.h
  • PLATFORM_BRAND : MkhiMsgs.h
  • PLATFORM_ME_HOOK_PRE_GLOBAL_RESET : PlatformMeHook.h
  • PLATFORM_ME_HOOK_PROTOCOL : PlatformMeHook.h
  • PLATFORM_ME_HOOK_PROTOCOL_REVISION : PlatformMeHook.h
  • PLATFORM_SEND_EC_COMMAND : BiosGuardConfig.h
  • PLATFORM_TARGET_USAGE_TYPE : MkhiMsgs.h
  • PmcClearGlobalResetStatus() : PmcLib.h
  • PmcClearHostResetStatus() : PmcLib.h
  • PmcClearPowerFailureStatus() : PmcLib.h
  • PmcClearSusPowerFailureStatus() : PmcLib.h
  • PmcClearWakeStatus() : PmcLib.h
  • PmcCrashLogClear() : PmcLib.h
  • PmcCrashLogDisable() : PmcLib.h
  • PmcCrashLogDiscovery() : PmcLib.h
  • PmcCrashLogOnAllReset() : PmcLib.h
  • PmcCrashLogProgramGlobalResetTriggerEnableMask() : PmcLib.h
  • PmcCrashLogReadGlobalResetTriggerMask() : PmcLib.h
  • PmcCrashLogReArm() : PmcLib.h
  • PmcCrashLogRestoreGlobalResetTriggerMask() : PmcLib.h
  • PmcDetectIntegratedClockSource() : PmcLib.h
  • PmcDevNumber() : PchPciBdfLib.h
  • PmcDisablePowerButtonSmi() : PmcLib.h
  • PmcEnablePowerButtonSmi() : PmcLib.h
  • PmcFuncNumber() : PchPciBdfLib.h
  • PmcGetAcpiBase() : PmcLib.h
  • PmcGetPwrmBase() : PmcLib.h
  • PmcGetSleepTypeAfterWake() : PmcLib.h
  • PmcGetTimerCount() : PmcLib.h
  • PmcIsDebugModeLocked() : PmcLib.h
  • PmcIsDwrBootMode() : PmcLib.h
  • PmcIsFivrConfigLocked() : PmcLib.h
  • PmcIsGblSmiEn() : PmcLib.h
  • PmcIsPowerButtonOverrideDetected() : PmcLib.h
  • PmcIsPowerFailureDetected() : PmcLib.h
  • PmcIsRtcBatteryGood() : PmcLib.h
  • PmcIsSetStrapMsgInterfaceLocked() : PmcLib.h
  • PmcIsSmiLockSet() : PmcLib.h
  • PmcIsSusPowerFailureDetected() : PmcLib.h
  • PmcPciCfgBase() : PchPciBdfLib.h
  • PmcReadLpmReqData() : PmcLib.h
  • PmcSetDramInitScratchpad() : PmcLib.h
  • PmcSetPlatformStateAfterPowerFailure() : PmcLib.h
  • PmcSetSleepState() : PmcLib.h
  • PmcSetSwGpeSts() : PmcLib.h
  • PmcSetTPch25Timing() : PmcLib.h
  • PmcSsramPciCfgBase() : PchPciBdfLib.h
  • PmicRead8() : PmcLib.h
  • PmicWrite8() : PmcLib.h
  • PmicWriteLock() : PmcLib.h
  • PolicyDefaultCheckInit() : PeiSiPolicyUpdateLib.h
  • PollGtReady() : GraphicsInfoLib.h
  • PollMailboxReady() : CpuMailboxLib.h
  • PowerUnit125MilliWatts : CpuPowerMgmtTestConfig.h
  • PowerUnitWatts : CpuPowerMgmtTestConfig.h
  • PPM_C1 : CpuPowerMgmt.h
  • PPM_C10 : CpuPowerMgmt.h
  • PPM_C1E : CpuPowerMgmt.h
  • PPM_C6 : CpuPowerMgmt.h
  • PPM_C7 : CpuPowerMgmt.h
  • PPM_C7S : CpuPowerMgmt.h
  • PPM_C8 : CpuPowerMgmt.h
  • PPM_C9 : CpuPowerMgmt.h
  • PPM_C_STATES : CpuPowerMgmt.h
  • PPM_CD : CpuPowerMgmt.h
  • PPM_CMP : CpuPowerMgmt.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPowerMgmtCustomConfig.h
  • PPM_EEPST : CpuPowerMgmt.h
  • PPM_EIST : CpuPowerMgmt.h
  • PPM_HWP : CpuPowerMgmt.h
  • PPM_IRM_SETTING : CpuPowerMgmtTestConfig.h
  • PPM_MWAIT_EXT : CpuPowerMgmt.h
  • PPM_OC_UNLOCKED : CpuPowerMgmt.h
  • PPM_TIMED_MWAIT : CpuPowerMgmt.h
  • PPM_TM : CpuPowerMgmt.h
  • PPM_TSTATE_FINE_GRAINED : CpuPowerMgmt.h
  • PPM_TSTATES : CpuPowerMgmt.h
  • PPM_TURBO : CpuPowerMgmt.h
  • PPM_TURBO_BOOST_MAX : CpuPowerMgmt.h
  • PrintMeType() : MeTypeLib.h
  • PROVISIONING_TLS_MODE : AmthiMsgs.h
  • PSL_MAJOR_VERSION : BiosGuard.h
  • PSL_MINOR_VERSION : BiosGuard.h
  • PsthGetIoTrapResourceSetting() : PsthLib.h
  • PT_PROVISIONING_STATE : AmthiMsgs.h
  • Ptt : BootGuardLibVer1.h
  • PttHeciGetCapability() : PttHeciLib.h
  • PttHeciGetState() : PttHeciLib.h
  • PttHeciSetState() : PttHeciLib.h
  • PttHeciUpdateState() : PttHeciLib.h
  • PWD_CHANGE_CMD : MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- q -

  • QUERY_TYPE : AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- r -

  • R_ACPI_IO_DEVTRAP_STS : PmcRegs.h
  • R_ACPI_IO_GPE0_EN_127_96 : PmcRegs.h
  • R_ACPI_IO_GPE0_STS_127_96 : PmcRegs.h
  • R_ACPI_IO_GPE0_STS_31_0 : PmcRegs.h
  • R_ACPI_IO_GPE_CTRL : PmcRegs.h
  • R_ACPI_IO_OC_WDT_CTL : PmcRegs.h
  • R_ACPI_IO_PM1_CNT : PmcRegs.h
  • R_ACPI_IO_PM1_TMR : PmcRegs.h
  • R_ACPI_IO_SMI_EN : PmcRegs.h
  • R_ACPI_IO_SMI_STS : PmcRegs.h
  • R_ACPI_IO_THERM_TIMER_DELAY : PmcRegs.h
  • R_BASE_ADDRESS_OFFSET_0 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_1 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_2 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_3 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_4 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_5 : PcieRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_2 : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CAP : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CAP_2 : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CTRL : CnviRegs.h
  • R_CNVI_CFG_WIFI_PMCSR : CnviRegs.h
  • R_CNVI_PCR_WIFI_WIDGET_CONTROL : CnviRegs.h
  • R_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1 : UsbRegs.h
  • R_ESPI_CFG_PCBC : PchRegsLpc.h
  • R_ESPI_PCR_CFG_VAL : PchRegsLpc.h
  • R_ESPI_PCR_FCERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_LNKERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_LNKERR_SLV1 : PchRegsLpc.h
  • R_ESPI_PCR_PCERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_PCERR_SLV1 : PchRegsLpc.h
  • R_ESPI_PCR_SLV_CFG_REG_CTL : PchRegsLpc.h
  • R_ESPI_PCR_SLV_CFG_REG_DATA : PchRegsLpc.h
  • R_ESPI_PCR_SOFTSTRAPS : PchRegsLpc.h
  • R_ESPI_PCR_VWERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_VWERR_SLV1 : PchRegsLpc.h
  • R_ESPI_SLAVE_CHA_0_CAP_AND_CONF : PchRegsLpc.h
  • R_FLASH_FCBA_FLCOMP : FlashRegs.h
  • R_FLASH_FDBAR_FLVALSIG : FlashRegs.h
  • R_FLASH_STRAP_DSCR_0 : FlashRegs.h
  • R_FLASH_STRAP_MMP0 : FlashRegs.h
  • R_FLASH_STRAP_SFDP : FlashRegs.h
  • R_FLASH_UMAP1 : FlashRegs.h
  • R_HER_BASE : HeciRegs.h
  • R_HERS : HeciRegs.h
  • R_ICC_PCR_MSKCKRQ : PchPcieRpRegs.h
  • R_ICC_PCR_TMCSRCCLK : PchPcieRpRegs.h
  • R_ICC_PCR_TMCSRCCLK2 : PchPcieRpRegs.h
  • R_LPC_CFG_BC : PchRegsLpc.h
  • R_LPC_CFG_BDE : PchRegsLpc.h
  • R_LT_UCS : PttPtpRegs.h
  • R_PCH_DMI14_PCR_DMIC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_DMIHWAWC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_G3L0SCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_IOSFSBCS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_IPCS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_LCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_REC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_UEM : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V0CTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V0STS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V1CTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V1STS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_VMCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_VMSTS : PchDmi14Regs.h
  • R_PCH_DMI15_PCR_CCFG : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CEM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CTRL1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CTRL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CWBCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_EEPPES : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_EQCFG1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_G3L0SCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_IOSFSBCS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L01EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0LFFS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P0P1PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P10PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P1P2P3PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P3P4PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P5P6PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P6P7P8PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P8P9PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L23EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L45EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L67EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCAP : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LSTS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO3 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO4 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_MPC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_MPC2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCE : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIECFG2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEDBG : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEL0SC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIENFTS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEPMECTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEPMECTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL3 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL4 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PWRCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RPDCGEN : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RPPGEN : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RTPCL1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RTPCL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_UEM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_UPHWAWC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V0CTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V0STS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V1CTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V1STS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_VMCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_VMSTS : PchDmi15Regs.h
  • R_PCH_DMI17_PCR_LCAP2 : PchDmi17Regs.h
  • R_PCH_DMI17_PCR_LCTL2 : PchDmi17Regs.h
  • R_PCH_DMI_PCR_GCS : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT4 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LCAP : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCBDE : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCGMR : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCIOD : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCIOE : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR4 : PchDmiRegs.h
  • R_PCH_DMI_PCR_P2SBIOR : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR1E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR2E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR3E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR4DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR4E : PchDmiRegs.h
  • R_PCH_DMI_PCR_SEGIR : PchDmiRegs.h
  • R_PCH_DMI_PCR_SEGMR : PchDmiRegs.h
  • R_PCH_DMI_PCR_TCOBASE : PchDmiRegs.h
  • R_PCH_DMI_PCR_TTTBARB : PchDmiRegs.h
  • R_PCH_DMI_PCR_TTTBARBH : PchDmiRegs.h
  • R_PCH_DMI_PCR_UCPR : PchDmiRegs.h
  • R_PCH_OPDMI14_PCR_LCFG : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_LCTL : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_LPMC : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_STC : PchDmi14Regs.h
  • R_PCH_PCIE_CFG_EX_ACSECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_AECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_CES : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_DPCECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_L1SECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_PTMECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_L1SCTL2 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMECFG : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMLLMT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPD : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC1 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC2 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC3 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC4 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC5 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMULMT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_TNPT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_VC0CTL : PchPcieRpRegs.h
  • R_PCH_SPI_STRP_GBETSN_DIS : FlashRegs.h
  • R_PCH_SPI_STRP_THC_DIS : FlashRegs.h
  • R_PCH_XHCI_MEM_USB2PDO : UsbRegs.h
  • R_PCH_XHCI_MEM_USB3PDO : UsbRegs.h
  • R_PCI_BRIDGE_BNUM : PcieRegs.h
  • R_PCI_BRIDGE_IOBL : PcieRegs.h
  • R_PCI_BRIDGE_MBL : PcieRegs.h
  • R_PCI_BRIDGE_PMBL : PcieRegs.h
  • R_PCI_BRIDGE_PMBU32 : PcieRegs.h
  • R_PCI_BRIDGE_PMLU32 : PcieRegs.h
  • R_PCI_CARDBUS_BRIDGE_SVID : PcieRegs.h
  • R_PCIE_CAP_ID_OFFSET : PcieRegs.h
  • R_PCIE_CAP_NEXT_PRT_OFFSET : PcieRegs.h
  • R_PCIE_DCAP2_OFFSET : PcieRegs.h
  • R_PCIE_DCAP_OFFSET : PcieRegs.h
  • R_PCIE_DCTL2_OFFSET : PcieRegs.h
  • R_PCIE_DCTL_OFFSET : PcieRegs.h
  • R_PCIE_DSTS_OFFSET : PcieRegs.h
  • R_PCIE_EX_ACSCAPR_OFFSET : PcieRegs.h
  • R_PCIE_EX_L01EC_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCAP_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCTL1_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCTL2_OFFSET : PcieRegs.h
  • R_PCIE_EX_L23EC_OFFSET : PcieRegs.h
  • R_PCIE_EX_LCTL3_OFFSET : PcieRegs.h
  • R_PCIE_EX_LES_OFFSET : PcieRegs.h
  • R_PCIE_EX_PTMCAP_OFFSET : PcieRegs.h
  • R_PCIE_EX_PTMCTL_OFFSET : PcieRegs.h
  • R_PCIE_EX_UEM_OFFSET : PcieRegs.h
  • R_PCIE_LCAP_OFFSET : PcieRegs.h
  • R_PCIE_LCTL2_OFFSET : PcieRegs.h
  • R_PCIE_LCTL_OFFSET : PcieRegs.h
  • R_PCIE_LSTS2_OFFSET : PcieRegs.h
  • R_PCIE_LSTS_OFFSET : PcieRegs.h
  • R_PCIE_PMC_OFFSET : PcieRegs.h
  • R_PCIE_PMCS_OFFST : PcieRegs.h
  • R_PCIE_RCTL_OFFSET : PcieRegs.h
  • R_PCIE_RSTS_OFFSET : PcieRegs.h
  • R_PCIE_SLCAP_OFFSET : PcieRegs.h
  • R_PCIE_SLCTL_OFFSET : PcieRegs.h
  • R_PCIE_SLSTS_OFFSET : PcieRegs.h
  • R_PCIE_SUBSYSTEM_VENDOR_ID_OFFSET : PcieRegs.h
  • R_PCIE_XCAP_OFFSET : PcieRegs.h
  • R_PMC_CFG_ACTL : PmcRegs.h
  • R_PMC_CFG_BAR : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_BUILD : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_HOT_FIX : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MAJOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MINOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_BUILD : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_HOT_FIX : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MAJOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MINOR : PmcRegs.h
  • R_PMC_PWRM_ACPI_TMR_CTL : PmcRegs.h
  • R_PMC_PWRM_ACTL : PmcRegs.h
  • R_PMC_PWRM_ADR_CTRL_STS : PmcRegs.h
  • R_PMC_PWRM_ADR_EN : PmcRegs.h
  • R_PMC_PWRM_ADR_GBLRST_EN_0 : PmcRegs.h
  • R_PMC_PWRM_ADR_GEN_CFG : PmcRegs.h
  • R_PMC_PWRM_ADR_GEN_CFG_V2 : PmcRegs.h
  • R_PMC_PWRM_BCLK_CFG : PmcRegs.h
  • R_PMC_PWRM_BIOS_SCRATCHPAD_2 : PmcRegs.h
  • R_PMC_PWRM_BM_CX_CNF : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL1A : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL1B : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL2A : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL3A : PmcRegs.h
  • R_PMC_PWRM_CPPM_MISC_CFG : PmcRegs.h
  • R_PMC_PWRM_CPPM_MPG_POL1A : PmcRegs.h
  • R_PMC_PWRM_CPPMFALIGNCTL_1 : PmcRegs.h
  • R_PMC_PWRM_CPPMVRIC : PmcRegs.h
  • R_PMC_PWRM_CPU_EPOC : PmcRegs.h
  • R_PMC_PWRM_CRID : PmcRegs.h
  • R_PMC_PWRM_CRID_UIP : PmcRegs.h
  • R_PMC_PWRM_CS_SD_CTL1 : PmcRegs.h
  • R_PMC_PWRM_CS_SD_CTL2 : PmcRegs.h
  • R_PMC_PWRM_CS_SD_OVR_EN : PmcRegs.h
  • R_PMC_PWRM_DSX_CFG : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SA : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SA2 : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING_CF : PmcRegs.h
  • R_PMC_PWRM_EN_MISC_EVENT : PmcRegs.h
  • R_PMC_PWRM_EN_NS_SA : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SA_0 : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SA_02 : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SA : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SA2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING_CF : PmcRegs.h
  • R_PMC_PWRM_ETR3 : PmcRegs.h
  • R_PMC_PWRM_GBL2HOST_EN : PmcRegs.h
  • R_PMC_PWRM_GBLRST_CAUSE0 : PmcRegs.h
  • R_PMC_PWRM_GBLRST_CAUSE1 : PmcRegs.h
  • R_PMC_PWRM_GEN_PMCON_A : PmcRegs.h
  • R_PMC_PWRM_GEN_PMCON_B : PmcRegs.h
  • R_PMC_PWRM_GPIO_CFG : PmcRegs.h
  • R_PMC_PWRM_HPR_CAUSE0 : PmcRegs.h
  • R_PMC_PWRM_IPC_CMD : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF0 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF1 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF2 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF3 : PmcRegs.h
  • R_PMC_PWRM_IPC_STS : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF0 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF1 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF2 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF3 : PmcRegs.h
  • R_PMC_PWRM_LPM0_REQ_0 : PmcRegs.h
  • R_PMC_PWRM_LPM7_REQ_5 : PmcRegs.h
  • R_PMC_PWRM_LPM_ADEM_HOST_CTRL : PmcRegs.h
  • R_PMC_PWRM_LPM_EN : PmcRegs.h
  • R_PMC_PWRM_LPM_EN_V2 : PmcRegs.h
  • R_PMC_PWRM_LPM_EN_V3 : PmcRegs.h
  • R_PMC_PWRM_LPM_PRI : PmcRegs.h
  • R_PMC_PWRM_LPM_PRI_V4 : PmcRegs.h
  • R_PMC_PWRM_LTR_IGN : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG1 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG2 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG3 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG5 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG6 : PmcRegs.h
  • R_PMC_PWRM_OBFF_CFG : PmcRegs.h
  • R_PMC_PWRM_PM_CFG : PmcRegs.h
  • R_PMC_PWRM_PM_CFG2 : PmcRegs.h
  • R_PMC_PWRM_PM_CFG3 : PmcRegs.h
  • R_PMC_PWRM_PM_CFG4 : PmcRegs.h
  • R_PMC_PWRM_PM_SYNC_MODE : PmcRegs.h
  • R_PMC_PWRM_PM_SYNC_STATE_HYS : PmcRegs.h
  • R_PMC_PWRM_PMLDOCTRL : PmcRegs.h
  • R_PMC_PWRM_PRSTS : PmcRegs.h
  • R_PMC_PWRM_S0_LDO_OFF_COUNT : PmcRegs.h
  • R_PMC_PWRM_S0IX_LDO_OFF_COUNT : PmcRegs.h
  • R_PMC_PWRM_S3_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_S4_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_S5_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_SLP_S0_RESIDENCY : PmcRegs.h
  • R_PMC_PWRM_SSMC : PmcRegs.h
  • R_PMC_PWRM_SSMD : PmcRegs.h
  • R_PMC_PWRM_SSMD_DW2 : PmcRegs.h
  • R_PMC_PWRM_SSMD_DW3 : PmcRegs.h
  • R_PMC_PWRM_SSML : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_0_V2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_1 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_1_V2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_2_V2 : PmcRegs.h
  • R_PMC_PWRM_TGPIOCTL0 : PmcRegs.h
  • R_PMC_PWRM_TGPIOCTL1 : PmcRegs.h
  • R_PMC_PWRM_WADT_AC : PmcRegs.h
  • R_PMC_SOFT_STRAP_7 : PmcRegs.h
  • R_PTT_HCI_BASE_ADDRESS : PttPtpRegs.h
  • R_RTC_PCR_BUC : RtcRegs.h
  • R_RTC_PCR_CONF : RtcRegs.h
  • R_RTC_PCR_RTCDCG : RtcRegs.h
  • R_SA_PEG_AFEBND0CFG1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFELN0CFG0_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFELN0CFG1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEOVR_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BCTRL_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD22_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD24_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD26_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD28_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI2_FUSE_DWORD15_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0SPARE_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD22_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD24_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD26_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD28_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD14_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD15_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD16_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_CFG4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_CMNSPARE_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DCAP2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DCTL2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DID_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQCFG_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQCTL0_1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPH3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET11_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET1_2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET2_3_4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET4_5_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET6_7_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET7_8_9_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET9_10_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_G3CTL0_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_L0SLAT_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LCTL3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LCTL_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LSTS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_SLOTSTS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_SS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_VC0RSTS_OFFSET : SaPcieDmiRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CADR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CAIR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CRGC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_EGCR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_FDW0 : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_GCR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_GSR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_IOBRSC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MBRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXCRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXPBAR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXPRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXTBAR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXTRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_NRDF : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_RHDF : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_SAPI : SataRegs.h
  • R_SATA_MEM_AHCI_SFM : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_AMXC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMBL : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMXC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_RCR : SataRegs.h
  • R_SMBUS_IO_AUXC : PchRegsSmbus.h
  • R_SMBUS_IO_AUXS : PchRegsSmbus.h
  • R_SMBUS_IO_HBD : PchRegsSmbus.h
  • R_SMBUS_IO_HCMD : PchRegsSmbus.h
  • R_SMBUS_IO_HCTL : PchRegsSmbus.h
  • R_SMBUS_IO_HD0 : PchRegsSmbus.h
  • R_SMBUS_IO_HD1 : PchRegsSmbus.h
  • R_SMBUS_IO_HSTS : PchRegsSmbus.h
  • R_SMBUS_IO_NDA : PchRegsSmbus.h
  • R_SMBUS_IO_NDHB : PchRegsSmbus.h
  • R_SMBUS_IO_NDLB : PchRegsSmbus.h
  • R_SMBUS_IO_PEC : PchRegsSmbus.h
  • R_SMBUS_IO_RSA : PchRegsSmbus.h
  • R_SMBUS_IO_SCMD : PchRegsSmbus.h
  • R_SMBUS_IO_SD : PchRegsSmbus.h
  • R_SMBUS_IO_SMBC : PchRegsSmbus.h
  • R_SMBUS_IO_SMLC : PchRegsSmbus.h
  • R_SMBUS_IO_SSTS : PchRegsSmbus.h
  • R_SMBUS_IO_TSA : PchRegsSmbus.h
  • R_SMBUS_PCR_GC : PchRegsSmbus.h
  • R_SMBUS_PCR_PCE : PchRegsSmbus.h
  • R_SMBUS_PCR_SCTM : PchRegsSmbus.h
  • R_SMBUS_PCR_SMBTM : PchRegsSmbus.h
  • R_SMBUS_PCR_TCOCFG : PchRegsSmbus.h
  • R_SPX_PCR_IMRAMBL : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMBU32 : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMLE : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMLU32 : PchPcieRpRegs.h
  • R_SPX_PCR_PCD : PchPcieRpRegs.h
  • R_SPX_PCR_PCIEHBP : PchPcieRpRegs.h
  • R_SPX_SIP16_PCR_PCD : PchPcieRpRegs.h
  • R_TCO_IO_TWDS : TcoRegs.h
  • R_USB2_PCR_CFG_COMPBG : UsbRegs.h
  • R_USB2_PCR_CONFIG_0 : UsbRegs.h
  • R_USB2_PCR_CONFIG_3 : UsbRegs.h
  • R_USB2_PCR_DFT_1 : UsbRegs.h
  • R_USB2_PCR_GLB_ADP_VBUS_REG : UsbRegs.h
  • R_USB2_PCR_GLOBAL_PORT : UsbRegs.h
  • R_USB2_PCR_GLOBAL_PORT_2 : UsbRegs.h
  • R_USB2_PCR_PER_PORT : UsbRegs.h
  • R_USB2_PCR_PER_PORT_2 : UsbRegs.h
  • R_USB2_PCR_PLL1 : UsbRegs.h
  • R_USB2_PCR_PLLDIVRATIOS_0 : UsbRegs.h
  • R_USB2_PCR_PP_LANE_BASE_ADDR : UsbRegs.h
  • R_USB2_PCR_SFRCONFIG_0 : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL_CLKCORETCGL1 : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL_ENCMNONNOVRL1 : UsbRegs.h
  • R_USB2_PCR_UTMI_MISC_PER_PORT : UsbRegs.h
  • R_XDCI_CFG_CPGE : UsbRegs.h
  • R_XDCI_CFG_PMCSR : UsbRegs.h
  • R_XDCI_MEM_GCTL : UsbRegs.h
  • R_XDCI_MEM_GUSB2PHYCFG : UsbRegs.h
  • R_XDCI_MEM_GUSB3PIPECTL0 : UsbRegs.h
  • R_XHCI_CFG_XHCC3 : UsbRegs.h
  • R_XHCI_MEM_AUDIO_OFFLOAD_CTR : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG2 : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG3 : UsbRegs.h
  • R_XHCI_MEM_CFG_USB2_LTV_U2_NOREQ_REG : UsbRegs.h
  • R_XHCI_MEM_D0I2CTRL : UsbRegs.h
  • R_XHCI_MEM_D0I2SCH_ALARM_CTRL : UsbRegs.h
  • R_XHCI_MEM_DBC_DBCCTL : UsbRegs.h
  • R_XHCI_MEM_DBGDEV_CTRL_REG1 : UsbRegs.h
  • R_XHCI_MEM_GRP0_SAI_RAC_POLICY_LO : UsbRegs.h
  • R_XHCI_MEM_GRP0_SAI_WAC_POLICY_LO : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_MISC_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_MISC_REG_2 : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_ODMA_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_PORT_LINK_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_SSP_TUNNELING_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_PWR_CTRL_REG0 : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_PWR_CTRL_REG1 : UsbRegs.h
  • R_XHCI_MEM_LTVHIT : UsbRegs.h
  • R_XHCI_MEM_LTVLIT : UsbRegs.h
  • R_XHCI_MEM_LTVMIT : UsbRegs.h
  • R_XHCI_MEM_MULT_IN_SCH_POLICY : UsbRegs.h
  • R_XHCI_MEM_PMCTRL2 : UsbRegs.h
  • R_XHCI_MEM_PMREQ_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_PORTSC_START_OFFSET : UsbRegs.h
  • R_XHCI_MEM_SOCHWSTSAVE1 : UsbRegs.h
  • R_XHCI_MEM_SSIC_CONF_REG2_PORT_1 : UsbRegs.h
  • R_XHCI_MEM_SSIC_CONF_REG2_PORT_2 : UsbRegs.h
  • R_XHCI_MEM_SSPE : UsbRegs.h
  • R_XHCI_MEM_SURVIVABILITY_REG1 : UsbRegs.h
  • R_XHCI_MEM_SURVIVABILITY_REG2 : UsbRegs.h
  • R_XHCI_MEM_U2OCM : UsbRegs.h
  • R_XHCI_MEM_U2PRM_U2PRDE : UsbRegs.h
  • R_XHCI_MEM_U3OCM : UsbRegs.h
  • R_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG : UsbRegs.h
  • R_XHCI_MEM_USB2PMCTRL : UsbRegs.h
  • R_XHCI_MEM_USBLPM : UsbRegs.h
  • R_XHCI_MEM_XHCLTVCTL2 : UsbRegs.h
  • R_XHCI_MEM_XLTP_LTV1 : UsbRegs.h
  • R_XHCI_PCR_DAP_COMMON_CONTROL_REG : UsbRegs.h
  • R_XHCI_PCR_DAP_ESS_PORT_CONTROL1 : UsbRegs.h
  • R_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0 : UsbRegs.h
  • R_XHCI_PCR_DAP_USB2PORT_STATUS_0 : UsbRegs.h
  • ReadVtdBaseAddress() : VtdInfoLib.h
  • RecursiveTbtHierarchyConfiguration() : DxeTbtDisBmeLib.h
  • REFLASH_BIOS : AsfProtocol.h
  • RegisterMeReset() : PeiMeLib.h
  • ReportBiosStatus() : DxeAsfHeciLib.h
  • REQUESTED_CLOCK_GEN2_PCIE : IccMsgs.h
  • ReserveMmio64Size() : PeiDxeSmmReserveMmio64SizeLib.h
  • ResetCold() : ResetSystemLib.h
  • ResetHeci1Interface() : MeUtilsLib.h
  • ResetPlatformSpecific() : ResetSystemLib.h
  • ResetShutdown() : ResetSystemLib.h
  • ResetWarm() : ResetSystemLib.h
  • RESPONSE_CODE : AsfMsgs.h
  • RstGetCycleRouterNumber() : RstCrLib.h
  • RtcIsBiosInterfaceLock() : RtcAccessLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- s -

  • S_CPU_XHCI_MEM_ESS_PORT_CONTROL1_SPACING : UsbRegs.h
  • S_ESPI_CFG_PCBC : PchRegsLpc.h
  • S_ESPI_PCR_LNKERR_SLV0 : PchRegsLpc.h
  • S_ESPI_PCR_XERR : PchRegsLpc.h
  • S_PTT_HCI_CRB_LENGTH : PttPtpRegs.h
  • S_SPX_PCR_PCD_RP_FIELD : PchPcieRpRegs.h
  • S_XHCI_MEM_PORTSC_PORT_SPACING : UsbRegs.h
  • S_XHCI_PCR_DAP_ESS_PORT_CONTROL1_SPACING : UsbRegs.h
  • SA_CHANGE_MARGIN : MemoryConfig.h
  • SA_CHANNEL_EXIST : MemoryConfig.h
  • SA_CHECKPOINT : MemoryConfig.h
  • SA_CPU_MAILBOX_READ : MemoryConfig.h
  • SA_CPU_MAILBOX_WRITE : MemoryConfig.h
  • SA_DEBUG_HOOK : MemoryConfig.h
  • SA_DEBUG_PRINT : MemoryConfig.h
  • SA_DELAY_NS : MemoryConfig.h
  • SA_DIV_U64_U64 : MemoryConfig.h
  • SA_FVI_STRING : SiFvi.h
  • SA_GET_CPU_TIME : MemoryConfig.h
  • SA_GET_MEMORY_VDD : MemoryConfig.h
  • SA_GET_PCI_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_PCIE_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_RANDOM_NUMBER : MemoryConfig.h
  • SA_GET_RTC_CMOS : MemoryConfig.h
  • SA_GET_RTC_TIME : MemoryConfig.h
  • SA_GET_SPD_DATA : MemoryConfig.h
  • SA_IO_READ_16 : MemoryConfig.h
  • SA_IO_READ_32 : MemoryConfig.h
  • SA_IO_READ_8 : MemoryConfig.h
  • SA_IO_WRITE_16 : MemoryConfig.h
  • SA_IO_WRITE_32 : MemoryConfig.h
  • SA_IO_WRITE_8 : MemoryConfig.h
  • SA_LEFT_SHIFT_64 : MemoryConfig.h
  • SA_MEMORY_COPY : MemoryConfig.h
  • SA_MEMORY_SET_BYTE : MemoryConfig.h
  • SA_MEMORY_SET_DWORD : MemoryConfig.h
  • SA_MEMORY_SET_WORD : MemoryConfig.h
  • SA_MMIO_READ_16 : MemoryConfig.h
  • SA_MMIO_READ_32 : MemoryConfig.h
  • SA_MMIO_READ_64 : MemoryConfig.h
  • SA_MMIO_READ_8 : MemoryConfig.h
  • SA_MMIO_WRITE_16 : MemoryConfig.h
  • SA_MMIO_WRITE_32 : MemoryConfig.h
  • SA_MMIO_WRITE_64 : MemoryConfig.h
  • SA_MMIO_WRITE_8 : MemoryConfig.h
  • SA_MRC_DRAM_RESET : MemoryConfig.h
  • SA_MRC_RETURN_FROM_SMC : MemoryConfig.h
  • SA_MSR_READ_64 : MemoryConfig.h
  • SA_MSR_WRITE_64 : MemoryConfig.h
  • SA_MULT_U64_U32 : MemoryConfig.h
  • SA_POLICY_PROTOCOL_REVISION : SaPolicy.h
  • SA_PRINTF : MemoryConfig.h
  • SA_RIGHT_SHIFT_64 : MemoryConfig.h
  • SA_SET_MEMORY_PMIC_VOLTAGE : MemoryConfig.h
  • SA_SET_MEMORY_VDD : MemoryConfig.h
  • SA_SHIFT_PI_COMMAND_TRAIN : MemoryConfig.h
  • SA_SIGN_EXTEND : MemoryConfig.h
  • SA_SMBUS_READ_16 : MemoryConfig.h
  • SA_SMBUS_READ_8 : MemoryConfig.h
  • SA_SMBUS_WRITE_16 : MemoryConfig.h
  • SA_SMBUS_WRITE_8 : MemoryConfig.h
  • SA_SPD : MemoryConfig.h
  • SA_UPDATE_VREF : MemoryConfig.h
  • SaAddConfigBlocks() : PeiSaPolicyLib.h
  • SaAddConfigBlocksPreMem() : PeiSaPolicyLib.h
  • SaGetConfigBlockTotalSize() : PeiSaPolicyLib.h
  • SaGetConfigBlockTotalSizePreMem() : PeiSaPolicyLib.h
  • SaInstallPolicyProtocol() : DxeSaPolicyLib.h
  • SaPrintPolicyPpi() : PeiSaPolicyLib.h
  • SaPrintPolicyPpiPreMem() : PeiSaPolicyLib.h
  • SaPrintPolicyProtocol() : DxeSaPolicyLib.h
  • SataControllerFunctionDisableStatus() : SataLib.h
  • SataDevNumber() : PchPciBdfLib.h
  • SataFuncNumber() : PchPciBdfLib.h
  • SataGetController() : SataSocLib.h
  • SataPciCfgBase() : PchPciBdfLib.h
  • ScsEmmcDevNumber() : PchPciBdfLib.h
  • ScsEmmcFuncNumber() : PchPciBdfLib.h
  • ScsEmmcPciCfgBase() : PchPciBdfLib.h
  • ScsSdCardDevNumber() : PchPciBdfLib.h
  • ScsSdCardFuncNumber() : PchPciBdfLib.h
  • ScsSdCardPciCfgBase() : PchPciBdfLib.h
  • ScsUfsDevNumber() : PchPciBdfLib.h
  • ScsUfsFuncNumber() : PchPciBdfLib.h
  • ScsUfsPciCfgBase() : PchPciBdfLib.h
  • SecGetFsptApiParameter() : GetFsptApiParameter.h
  • SecGetPerformance() : SecPlatformLib.h
  • SecPlatformInformation() : SecPlatformLib.h
  • SecPlatformMain() : SecPlatformLib.h
  • SEMAPHORE : Txt.h
  • SendFspErrorInfo() : FspErrorInfoLib.h
  • SendFspErrorInfoStatusCode() : FspErrorInfoLib.h
  • SendOcrPetAlert() : DxeAmtHeciLib.h
  • SendOcrPetEvent() : DxeAmtHeciLib.h
  • SendRpePetAlert() : DxeAmtHeciLib.h
  • SendRsePetAlert() : DxeAmtHeciLib.h
  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h
  • SerialIoI2cBlockWriteRead() : SerialIoI2cLib.h
  • SerialIoI2cDevNumber() : PchPciBdfLib.h
  • SerialIoI2cFuncNumber() : PchPciBdfLib.h
  • SerialIoI2cPciCfgBase() : PchPciBdfLib.h
  • SerialIoI2cRead() : SerialIoI2cLib.h
  • SerialIoI2cWrite() : SerialIoI2cLib.h
  • SerialIoI3cDevNumber() : PchPciBdfLib.h
  • SerialIoI3cFuncNumber() : PchPciBdfLib.h
  • SerialIoI3cPciCfgBase() : PchPciBdfLib.h
  • SerialIoSpiChipSelectConfig() : SerialIoSpiLib.h
  • SerialIoSpiDevNumber() : PchPciBdfLib.h
  • SerialIoSpiFuncNumber() : PchPciBdfLib.h
  • SerialIoSpiPciCfgBase() : PchPciBdfLib.h
  • SerialIoSpiRead() : SerialIoSpiLib.h
  • SerialIoSpiWrite() : SerialIoSpiLib.h
  • SerialIoSpiWriteRead() : SerialIoSpiLib.h
  • SerialIoUartDebugPcdGetAttributes() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetControllerNumber() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetDebugEnable() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetDeviceConfig() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetPciDefaultMmioBase() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDevNumber() : PchPciBdfLib.h
  • SerialIoUartDummyRead() : SerialIoUartLib.h
  • SerialIoUartFuncNumber() : PchPciBdfLib.h
  • SerialIoUartGetOutOfReset() : SerialIoUartLib.h
  • SerialIoUartPciCfgBase() : PchPciBdfLib.h
  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h
  • SerialIoUartPolling() : SerialIoUartLib.h
  • SerialIoUartRead() : SerialIoUartLib.h
  • SerialIoUartSetAttributes() : SerialIoUartLib.h
  • SerialIoUartSetMmioInPciMode() : SerialIoUartLib.h
  • SerialIoUartWrite() : SerialIoUartLib.h
  • SET_CM_TIMEOUT_IN_MS : TbtMailBoxCmdDefinition.h
  • SET_MEBX_DATA : MebxConfigProtocol.h
  • SetD0I3Bit() : MeChipsetLib.h
  • SetInterruptPin() : PchPcrLib.h
  • SetMeUefiFwHealthEfiStatus() : MeUefiFwHealthStatusLib.h
  • SetMeUefiFwHealthStatus() : MeUefiFwHealthStatusLib.h
  • SetPostCodeToScratchPad() : PostCodeToScratchPadLib.h
  • ShowBuffer() : MeShowBufferLib.h
  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • SiCreateConfigBlocks() : SiPolicyLib.h
  • SiCreatePreMemConfigBlocks() : SiPolicyLib.h
  • SiInstallPolicyPpi() : SiPolicyLib.h
  • SiInstallPolicyReadyPpi() : SiPolicyLib.h
  • SiPreMemInstallPolicyPpi() : SiPolicyLib.h
  • SiPreMemInstallPolicyReadyPpi() : SiPolicyLib.h
  • SiPreMemPrintPolicyPpi() : SiPolicyLib.h
  • SiPrintPolicyPpi() : SiPolicyLib.h
  • SKU_TYPE : MkhiMsgs.h
  • SmbusClearStatusReg() : SmbusInfoLib.h
  • SmbusDevNumber() : PchPciBdfLib.h , SmbusInfoLib.h
  • SmbusDmaDevNumber() : PchPciBdfLib.h
  • SmbusDmaFuncNumber() : PchPciBdfLib.h
  • SmbusDmaPciCfgBase() : PchPciBdfLib.h
  • SmbusFuncNumber() : PchPciBdfLib.h , SmbusInfoLib.h
  • SmbusIsHostLocked() : SmbusInfoLib.h
  • SmbusPciCfgBase() : PchPciBdfLib.h
  • SMM_CONFIG_IO_BITMAP : SmmResourceConfigProtocol.h
  • SMM_CONFIG_MSR_BITMAP : SmmResourceConfigProtocol.h
  • SMM_INSTALL_IO_BITMAP : SmmResourceConfigProtocol.h
  • SMM_INSTALL_MSR_BITMAP : SmmResourceConfigProtocol.h
  • SPD_BOOT_MODE : MemoryConfig.h
  • SpdBootModeMax : MemoryConfig.h
  • SpdCold : MemoryConfig.h
  • SpdFast : MemoryConfig.h
  • SPDProfileMax : MemoryConfig.h
  • SpdS3 : MemoryConfig.h
  • SpdWarm : MemoryConfig.h
  • SPI_COMPONENT_SIZE : BiosGuard.h
  • SpiClearBcSyncSs() : SpiAccessLib.h
  • SpiDeviceNumber() : SpiAccessLib.h
  • SpiDevNumber() : PchPciBdfLib.h
  • SpiFuncNumber() : PchPciBdfLib.h
  • SpiFunctionNumber() : SpiAccessLib.h
  • SpiGetBar0() : SpiAccessLib.h
  • SpiGetBiosRegionFlashReadAccess() : SpiAccessLib.h
  • SpiGetBiosRegionFlashWriteAccess() : SpiAccessLib.h
  • SpiGetComponentPropertyParameterTable() : SpiAccessLib.h
  • SpiGetCsmeRegionAccess() : SpiAccessLib.h
  • SpiGetDescriptorSignature() : SpiAccessLib.h
  • SpiGetEcRegionAccess() : SpiAccessLib.h
  • SpiGetExtendedBiosRegionRange() : SpiAccessLib.h
  • SpiGetFlashComponentDescription() : SpiAccessLib.h
  • SpiGetFlashComponentsNumber() : SpiAccessLib.h
  • SpiGetGbeRegionAccess() : SpiAccessLib.h
  • SpiGetMasterReadAccess() : SpiAccessLib.h
  • SpiGetMasterWriteAccess() : SpiAccessLib.h
  • SpiGetPciCfgAddress() : SpiAccessLib.h
  • SpiGetTotalFlashSize() : SpiAccessLib.h
  • SpiIsBiosBootFromSpi() : SpiAccessLib.h
  • SpiIsBiosInterfaceLockdownEnabled() : SpiAccessLib.h
  • SpiIsControllerAvailable() : SpiAccessLib.h
  • SpiIsCppValidBitSet() : SpiAccessLib.h
  • SpiIsExtendedBiosRegionBaseLocked() : SpiAccessLib.h
  • SpiIsExtendedBiosRegionEnabled() : SpiAccessLib.h
  • SpiIsFlashConfigurationLockDownEnabled() : SpiAccessLib.h
  • SpiIsFlashDescriptorOverrideEnabled() : SpiAccessLib.h
  • SpiIsFlashDescriptorValid() : SpiAccessLib.h
  • SpiIsGbeRegionValid() : SpiAccessLib.h
  • SpiIsSafModeActive() : SpiAccessLib.h
  • SpiIsTopSwapEnabled() : SpiAccessLib.h
  • SpiIsWriteProtectionEnabled() : SpiAccessLib.h
  • SpiIsWriteStatusDisable() : SpiAccessLib.h
  • SpiPciCfgBase() : PchPciBdfLib.h
  • SpiServiceInit() : SpiLib.h
  • STORAGE_REDIRECTION_BOOT_DEVICE_MASK : AsfProtocol.h
  • STREAMING_TRACE_SINK : BupMsgs.h
  • SUPPORT_FORCE_PXE : IndustryStandardAsf.h
  • SUPPORT_POWER_CYCLE_RESET : IndustryStandardAsf.h
  • SUPPORT_POWER_CYCLE_RESET_COMBO : IndustryStandardAsf.h
  • SUPPORT_POWER_DOWN : IndustryStandardAsf.h
  • SUPPORT_POWER_DOWN_COMBO : IndustryStandardAsf.h
  • SUPPORT_POWER_UP : IndustryStandardAsf.h
  • SUPPORT_POWER_UP_COMBO : IndustryStandardAsf.h
  • SUPPORT_RESET : IndustryStandardAsf.h
  • SUPPORT_RESET_COMBO : IndustryStandardAsf.h
  • SW_DXE_BS_EC_NO_BOOT_MEDIA : IntelAsfExtensions.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- t -

  • TBT_ALL : PeiTbtTaskDispatchLib.h
  • TBT_BOOT_MODE : PeiTbtTaskDispatchLib.h
  • TBT_MAILBOX_DELAY : TbtMailBoxCmdDefinition.h
  • TBT_NORMAL : PeiTbtTaskDispatchLib.h
  • TBT_NULL : PeiTbtTaskDispatchLib.h
  • TBT_S3 : PeiTbtTaskDispatchLib.h
  • TBT_S4 : PeiTbtTaskDispatchLib.h
  • TbtClearVgaRegisters() : TbtCommonLib.h
  • TbtGetBootMode() : PeiTbtTaskDispatchLib.h
  • TbtGetSecLevel() : TbtCommonLib.h
  • TbtSetDmaSsidSvid() : TbtCommonLib.h
  • TbtSetPcie2TbtCommand() : TbtCommonLib.h
  • TbtSetSecLevel() : TbtCommonLib.h
  • TbtTaskDistpach() : PeiTbtTaskDispatchLib.h
  • TcoClearSecondToStatus() : TcoLib.h
  • TcoHaltTimer() : TcoLib.h
  • TcoIsSmiLock() : TcoLib.h
  • TcoSecondToHappened() : TcoLib.h
  • Thc : ThcConfig.h
  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h
  • ThcDevNumber() : PchPciBdfLib.h
  • ThcFuncNumber() : PchPciBdfLib.h
  • ThcIsEnabled() : ThcLib.h
  • ThcIsSupported() : ThcLib.h
  • ThcPciCfgBase() : PchPciBdfLib.h
  • ThermalDevNumber() : PchPciBdfLib.h
  • ThermalFuncNumber() : PchPciBdfLib.h
  • ThermalIsEcThermalReportLock() : ThermalAccessLib.h
  • ThermalIsPchHotLock() : ThermalAccessLib.h
  • ThermalIsPmcThrottleLock() : ThermalAccessLib.h
  • ThermalIsThrottleLock() : ThermalAccessLib.h
  • ThermalPciCfgBase() : PchPciBdfLib.h
  • TO_BE_FILLED : SiFviLib.h , SiFvi.h
  • TO_BE_FILLED_STRING : SiFviLib.h , SiFvi.h
  • TopSwapSet() : TopSwapLib.h
  • TopSwapStatus() : TopSwapLib.h
  • Tpm2ChangeEPS() : Tpm2CommandLib.h
  • Tpm2ChangePPS() : Tpm2CommandLib.h
  • Tpm2Clear() : Tpm2CommandLib.h
  • Tpm2ClearControl() : Tpm2CommandLib.h
  • Tpm2DictionaryAttackLockReset() : Tpm2CommandLib.h
  • Tpm2DictionaryAttackParameters() : Tpm2CommandLib.h
  • Tpm2EventSequenceComplete() : Tpm2CommandLib.h
  • Tpm2FlushContext() : Tpm2CommandLib.h
  • Tpm2GetCapability() : Tpm2CommandLib.h
  • Tpm2GetCapabilityAlgorithmSet() : Tpm2CommandLib.h
  • Tpm2GetCapabilityFamily() : Tpm2CommandLib.h
  • Tpm2GetCapabilityFirmwareVersion() : Tpm2CommandLib.h
  • Tpm2GetCapabilityInputBufferSize() : Tpm2CommandLib.h
  • Tpm2GetCapabilityLockoutCounter() : Tpm2CommandLib.h
  • Tpm2GetCapabilityLockoutInterval() : Tpm2CommandLib.h
  • Tpm2GetCapabilityManufactureID() : Tpm2CommandLib.h
  • Tpm2GetCapabilityMaxCommandResponseSize() : Tpm2CommandLib.h
  • Tpm2GetCapabilityPcrs() : Tpm2CommandLib.h
  • Tpm2GetCapabilitySupportedAlg() : Tpm2CommandLib.h
  • Tpm2GetCapabilitySupportedAndActivePcrs() : Tpm2CommandLib.h
  • Tpm2HashSequenceStart() : Tpm2CommandLib.h
  • Tpm2HierarchyChangeAuth() : Tpm2CommandLib.h
  • Tpm2HierarchyControl() : Tpm2CommandLib.h
  • Tpm2NvDefineSpace() : Tpm2CommandLib.h
  • Tpm2NvGlobalWriteLock() : Tpm2CommandLib.h
  • Tpm2NvRead() : Tpm2CommandLib.h
  • Tpm2NvReadLock() : Tpm2CommandLib.h
  • Tpm2NvReadPublic() : Tpm2CommandLib.h
  • Tpm2NvUndefineSpace() : Tpm2CommandLib.h
  • Tpm2NvWrite() : Tpm2CommandLib.h
  • Tpm2NvWriteLock() : Tpm2CommandLib.h
  • Tpm2PcrAllocate() : Tpm2CommandLib.h
  • Tpm2PcrAllocateBanks() : Tpm2CommandLib.h
  • Tpm2PcrEvent() : Tpm2CommandLib.h
  • Tpm2PcrExtend() : Tpm2CommandLib.h
  • Tpm2PcrRead() : Tpm2CommandLib.h
  • Tpm2PolicyCommandCode() : Tpm2CommandLib.h
  • Tpm2PolicyGetDigest() : Tpm2CommandLib.h
  • Tpm2PolicyOR() : Tpm2CommandLib.h
  • Tpm2PolicySecret() : Tpm2CommandLib.h
  • Tpm2ReadPublic() : Tpm2CommandLib.h
  • Tpm2SelfTest() : Tpm2CommandLib.h
  • Tpm2SequenceComplete() : Tpm2CommandLib.h
  • Tpm2SequenceUpdate() : Tpm2CommandLib.h
  • Tpm2SetAlgorithmSet() : Tpm2CommandLib.h
  • Tpm2SetPrimaryPolicy() : Tpm2CommandLib.h
  • Tpm2Shutdown() : Tpm2CommandLib.h
  • Tpm2StartAuthSession() : Tpm2CommandLib.h
  • Tpm2Startup() : Tpm2CommandLib.h
  • Tpm2TestParms() : Tpm2CommandLib.h
  • TPM_INIT_FAILED : TxtInfoHob.h
  • TPM_STATUS_REG_ADDRESS : Txt.h
  • TPM_TIME_OUT : Txt.h
  • TPM_TYPE : BootGuardLibVer1.h
  • TpmNone : BootGuardLibVer1.h
  • TpmTypeMax : BootGuardLibVer1.h
  • TPSS_FVID_MAX_STATES : CpuPowerMgmt.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h
  • TraceHubDebugWrite() : TraceHubDebugLib.h
  • TraceHubMmioTraceAddress() : TraceHubHookLib.h
  • TraceHubScratchPad2RegValue() : TraceHubHookLib.h
  • TraceHubWriteCataLog64_0() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_1() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_2() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_3() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_4() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_5() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_6() : TraceHubDebugLib.h
  • TsnDevNumber() : TsnLib.h , PchPciBdfLib.h
  • TsnFuncNumber() : PchPciBdfLib.h , TsnLib.h
  • TsnPciCfgBase() : PchPciBdfLib.h
  • TXT_BIOS_SPEC_VER_MAJOR : Txt.h
  • TXT_BIOS_SPEC_VER_MINOR : Txt.h
  • TXT_BIOS_SPEC_VER_REVISION : Txt.h
  • TXT_BLOCK_MEM_STS : Txt.h
  • TXT_CONFIG_SPACE_LENGTH : Txt.h
  • TXT_CPU_RESET_REQUIRED : TxtInfoHob.h
  • TXT_CRASHCODE_REG_OFF : Txt.h
  • TXT_DPR_SIZE_REG_OFF : Txt.h
  • TXT_E2STS_REG_OFF : Txt.h
  • TXT_ERROR_STATUS_REG_OFF : Txt.h
  • TXT_HEAP_BASE_REG_OFF : Txt.h
  • TXT_HEAP_SIZE_REG_OFF : Txt.h
  • TXT_INFO_DATA : TxtInfoHob.h
  • TXT_INFO_HOB : TxtInfoHob.h
  • TXT_LAUNCH_ACHECK : Txt.h
  • TXT_LAUNCH_CLEAR_SECRETS : Txt.h
  • TXT_LAUNCH_LOCK_CONFIG : Txt.h
  • TXT_LAUNCH_SCHECK : Txt.h
  • TXT_LAUNCH_SCLEAN : Txt.h
  • TXT_PRIVATE_BASE : Txt.h
  • TXT_PTT_FTIF_OFF : Txt.h
  • TXT_PTT_PRESENT : Txt.h
  • TXT_PUBLIC_BASE : Txt.h
  • TXT_RESET_AUX : Txt.h
  • TXT_RESET_EST_BIT : Txt.h
  • TXT_SCRATCHPAD : Txt.h
  • TXT_SCRATCHPAD2 : Txt.h
  • TXT_SCRATCHPAD3 : Txt.h
  • TXT_SCRATCHPAD4 : Txt.h
  • TXT_SECRETS_STS : Txt.h
  • TXT_SINIT_BASE_REG_OFF : Txt.h
  • TXT_SINIT_SIZE_REG_OFF : Txt.h
  • TXT_SINIT_SIZE_REG_OFF2 : Txt.h
  • TXT_SLP_ENTRY_ERROR_STS : Txt.h
  • TXT_SPAD_REG_OFF : Txt.h
  • TXT_SVMM_JOIN_REG_OFF : Txt.h
  • TXT_SVMM_JOIN_REG_OFF2 : Txt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- u -

  • UpdateFviInfo() : SiFvi.h
  • UpdatePeiAmtPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiCpuPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiCpuPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMePolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMePolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMeServerPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMeServerPreMemPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiPchPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiPchPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSaPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSaPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSiPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSiPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiTbtPolicy() : PeiSiPolicyUpdateLib.h
  • UPID_COMMON_FEATURE : UpidMsgs.h
  • UPID_FEATURE : UpidMsgs.h
  • UPID_STATUS : UpidMsgs.h
  • USB_OC_MAX_PINS : UsbConfig.h
  • USE_KVM : AsfProtocol.h
  • USE_SOL : AsfProtocol.h
  • USE_STORAGE_REDIR : AsfProtocol.h
  • USER_FEEDBACK_REQUESTED : MkhiMsgs.h
  • USER_PASSWORD_BYPASS : IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- v -

  • V_ACPI_IO_PM1_TMR_MAX_VAL : PmcRegs.h
  • V_ESPI_PCR_FCERR_SLV0_FCFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_FCERR_SLV0_FCNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV0_LFER1E_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV1_LFER1E_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV1_LFET1E_SMI : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCRMTARE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR : PchRegsLpc.h
  • V_ESPI_PCR_VWERR_VWFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_VWERR_VWNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_XERR_XFEE_SMI : PchRegsLpc.h
  • V_ESPI_PCR_XERR_XNFEE_SMI : PchRegsLpc.h
  • V_FTIF_FTPM_PRESENT : PttPtpRegs.h
  • V_FTIF_SPI_DTPM_PRESENT : PttPtpRegs.h
  • V_INTEL_VENDOR_ID : MeRegs.h
  • V_IO_CAPT_LVL2 : CpuRegs.h
  • V_IO_CAPT_LVL3 : CpuRegs.h
  • V_IO_CAPT_LVL4 : CpuRegs.h
  • V_IO_CAPT_LVL5 : CpuRegs.h
  • V_IO_CAPT_LVL6 : CpuRegs.h
  • V_IO_CAPT_LVL7 : CpuRegs.h
  • V_LPC_CFG_BC_BBS_LPC : PchRegsLpc.h
  • V_LPC_CFG_BC_BBS_SPI : PchRegsLpc.h
  • V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP : PchRegsLpc.h
  • V_MAILBOX_INF_DFX_PWROFF_REQ_DIS : CpuMailboxLib.h
  • V_MAILBOX_INF_DFX_PWROFF_REQ_EN : CpuMailboxLib.h
  • V_ME_VER1_PCH_N_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER2_PCH_H_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER3_PCH_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER4_PCH_S_HECI_DEVICE_ID : MeRegs.h
  • V_PCH_DEFAULT_SID : PchRegs.h
  • V_PCH_DEFAULT_SVID_SID : PchRegs.h
  • V_PCH_DMI15_PCR_CTRL1_L1PL_8US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_DIS : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L0S : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L0SL1 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L1 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_ORCE_EN_GEN2_GEN3 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_PLLWAIT_0US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_PLLWAIT_5US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_PWRCTL_RPSEWL_120NS : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL0TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL1TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL2TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL3TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL4TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL5TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL6TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL7TP : PchDmi15Regs.h
  • V_PCH_DMI_PCR_LCAP_EL0_256NS_512NS : PchDmiRegs.h
  • V_PCH_DMI_PCR_LCAP_EL1_8US_16US : PchDmiRegs.h
  • V_PCH_INTEL_VENDOR_ID : PchRegs.h
  • V_PCIE_DCTL2_OBFFEN_DIS : PcieRegs.h
  • V_PCIE_DCTL2_OBFFEN_WAKE : PcieRegs.h
  • V_PCIE_EX_ACS_CID : PcieRegs.h
  • V_PCIE_EX_AEC_CID : PcieRegs.h
  • V_PCIE_EX_APEC_CID : PcieRegs.h
  • V_PCIE_EX_DLFECH_CID : PcieRegs.h
  • V_PCIE_EX_DPC_CID : PcieRegs.h
  • V_PCIE_EX_G5ECH_CID : PcieRegs.h
  • V_PCIE_EX_IDEEXTCAPHDR_CID : PcieRegs.h
  • V_PCIE_EX_L1S_CID : PcieRegs.h
  • V_PCIE_EX_PL16GECH_CID : PcieRegs.h
  • V_PCIE_EX_PL16MECH_CID : PcieRegs.h
  • V_PCIE_EX_PTM_CID : PcieRegs.h
  • V_PCIE_EX_SPE_CID : PcieRegs.h
  • V_PCIE_EX_VC_CID : PcieRegs.h
  • V_PCIE_FPBCAP_CID : PcieRegs.h
  • V_PMC_DEF_CPU_BCLK_CFG_INTEGRATED : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_MEM_CAL : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_PCI_ENUM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_LOCK : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_WRITE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISCOVERY : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ERASE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ON_RESET : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_PROGRAM_TRIGGER_ENABLES : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_RE_ARM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_READ_TRIGGER_ENABLES : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC1_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC2_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC3_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_LOCK_ENABLE_PMIC_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC1_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC2_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC3_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_CPU_STRAP : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_CRASHLOG : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_DFX_PWR_STATE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_FIVR : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_GEN_COMM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_IO_MARGINING_ENABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_ME_DISABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PMC_PRV_REG_ACCESS : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PMIC : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PROXY : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SNDW_RCOMP : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SSC_STATE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI : PmcRegs.h
  • V_PMC_PWRM_IPC_SRC_CLK_CMD : PmcRegs.h
  • V_PMC_PWRM_IPC_SRC_CLK_PORT_MAPPING_CMD : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_EMI_CTRL0_LOGIC : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_FFFC_FAULT_STATUS : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_FFFC_RFI_STATUS : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_1S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_2S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_3S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_4S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_0S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_2S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_4S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_98ms : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_0_5S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_0S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_1S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_4S : PmcRegs.h
  • V_PTT_HCI_ALL_BITS_CLEAR : PttPtpRegs.h
  • V_PTT_HCI_IGNORE_BITS : PttPtpRegs.h
  • V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR0 : SataRegs.h
  • V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR5 : SataRegs.h
  • V_SATA_MEM_RST_PCIE_STORAGE_REMAP_CONFIG_CR : SataRegs.h
  • V_SATA_MEM_RST_PCIE_STORAGE_REMAP_RP_OFFSET : SataRegs.h
  • V_SATA_MEM_VS_CAP_MSL : SataRegs.h
  • V_SATA_MEM_VS_CAP_NRMO : SataRegs.h
  • V_SMBUS_PCR_TCOCFG_IRQ_20 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_21 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_22 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_23 : PchRegsSmbus.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DBC : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DISCONNECT : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_HOST : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS_DBC : UsbRegs.h
  • VGPIO_CS_CONFIG : GpioConfig.h
  • VgpioCs0 : GpioConfig.h
  • VgpioCs1 : GpioConfig.h
  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- w -

  • WaitFirmwareInitComplete() : MeUtilsLib.h
  • WARM_BOOT : MemInfoHob.h
  • WDT_ALLOW_KNOWN_RESET : Protocol/Wdt.h
  • WDT_CHECK_STATUS : Protocol/Wdt.h
  • WDT_DISABLE : Protocol/Wdt.h
  • WDT_PPI : Ppi/Wdt.h
  • WDT_RELOAD_AND_START : Protocol/Wdt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

Here is a list of all documented file members with links to the documentation:

- x -

  • XhciMmioEnable() : UsbLib.h
  • XMP_PROFILE_1 : MemoryConfig.h
  • XMP_PROFILE_2 : MemoryConfig.h
  • XMP_PROFILE_3 : MemoryConfig.h
  • XMP_USER_PROFILE_4 : MemoryConfig.h
  • XMP_USER_PROFILE_5 : MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- a -

  • AddComponentConfigBlocks() : SiConfigBlockLib.h
  • AddConfigBlock() : ConfigBlockLib.h
  • AddFviEntry() : SiFviLib.h
  • AddSmbiosProcessorAndCacheTables() : SmbiosProcessorLib.h
  • AmtAddConfigBlocks() : PeiAmtPolicyLib.h
  • AmtCreatePolicyDefaults() : DxeAmtPolicyLib.h
  • AmtGetActiveLanInterface() : DxeAmtHeciLib.h
  • AmtGetConfigBlockTotalSize() : PeiAmtPolicyLib.h
  • AmtInstallPolicyProtocol() : DxeAmtPolicyLib.h
  • AmtPrintPolicyPpi() : PeiAmtPolicyLib.h
  • AmtPrintPolicyProtocol() : DxeAmtPolicyLib.h
  • AmtQueryKvm() : DxeAmtHeciLib.h
  • AmtSetActiveLanInterface() : DxeAmtHeciLib.h
  • AmtSetMacPassthrough() : DxeAmtHeciLib.h
  • AsciiChar2Hex() : DxeJhiSupportLib.h
  • AsciiHex2Char() : DxeJhiSupportLib.h
  • AsciiIsAlphabet() : DxeJhiSupportLib.h
  • AsciiIsDigit() : DxeJhiSupportLib.h
  • AsciiStr2Uuid() : DxeJhiSupportLib.h
  • AsciiStrIsUuid1() : DxeJhiSupportLib.h
  • AsciiStrIsUuid2() : DxeJhiSupportLib.h
  • AsciiToLower() : DxeJhiSupportLib.h
  • AsciiUuid2Str() : DxeJhiSupportLib.h
  • AsfGetRemoteFlashState() : DxeAsfLib.h
  • AsfGetRootCaCertificate() : DxeAmtHeciLib.h
  • AsfGetSpecialCmdParamHighByte() : DxeAsfLib.h
  • AsfGetSpecialCmdParamLowByte() : DxeAsfLib.h
  • AsfGetSpecialCommand() : DxeAsfLib.h
  • AsfGetStorageRedirectionBootDevice() : DxeAsfLib.h
  • AsfGetUefiBootOptionsState() : DxeAmtHeciLib.h
  • AsfGetUefiBootParameters() : DxeAmtHeciLib.h
  • AsfIsBootOptionsPresent() : DxeAsfLib.h
  • AsfIsConfigurationDataResetEnabled() : DxeAsfLib.h
  • AsfIsConsoleLocked() : DxeAsfLib.h
  • AsfIsEnforceSecureBootEnabled() : DxeAsfLib.h
  • AsfIsEnterSetupEnabled() : DxeAsfLib.h
  • AsfIsFwProgressEnabled() : DxeAsfLib.h
  • AsfIsIndustryIanaId() : DxeAsfLib.h
  • AsfIsKvmEnabled() : DxeAsfLib.h
  • AsfIsPauseBootEnabled() : DxeAsfLib.h
  • AsfIsRemotePlatformEraseEnabled() : DxeAsfLib.h
  • AsfIsSecureEraseEnabled() : DxeAsfLib.h
  • AsfIsSolEnabled() : DxeAsfLib.h
  • AsfIsStorageRedirectionEnabled() : DxeAsfLib.h
  • AsfSetUefiBootOptionsState() : DxeAmtHeciLib.h
  • AsfStartWatchDog() : DxeAmtHeciLib.h
  • AsfStopWatchDog() : DxeAmtHeciLib.h
  • AsfUpdateUefiBootOptions() : DxeAmtHeciLib.h
  • AsfWifiGetClientCertificate() : DxeAmtHeciLib.h
  • AsfWifiGetClientKey() : DxeAmtHeciLib.h
  • AsfWifiGetProfileData() : DxeAmtHeciLib.h
  • AsfWifiGetProfileName() : DxeAmtHeciLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- b -

  • BootMediaIsKnown() : BootMediaLib.h
  • BootMediaIsSpi() : BootMediaLib.h
  • BootMediaIsUfs() : BootMediaLib.h
  • BuildFviInfoHob() : SiFvi.h
  • BuildPciImrHob() : PeiPcieRpLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- c -

  • CheckPowerOffNow() : PmcLib.h
  • CheckSmxCapabilities() : TxtLib.h
  • ClearBootOptions() : DxeAsfHeciLib.h
  • ClearD0I3Bit() : MeChipsetLib.h
  • ClearSmiAndWake() : PmcLib.h
  • CnviDevNumber() : PchPciBdfLib.h
  • CnviFuncNumber() : PchPciBdfLib.h
  • CnviIsPresent() : CnviLib.h
  • CnviPciCfgBase() : PchPciBdfLib.h
  • ConvertSystemTimeToUnixFormat() : SystemTimeLib.h
  • CopyAuthSessionCommand() : Tpm2CommandLib.h
  • CopyAuthSessionResponse() : Tpm2CommandLib.h
  • CopyDigestListToBuffer() : Tpm2CommandLib.h
  • CpuAddConfigBlocks() : CpuPolicyLib.h
  • CpuAddPreMemConfigBlocks() : CpuPolicyLib.h
  • CpuCrashLogClear() : TelemetryLib.h
  • CpuCrashLogDiscovery() : TelemetryLib.h
  • CpuCrashLogReArm() : TelemetryLib.h
  • CpuGetConfigBlockTotalSize() : CpuPolicyLib.h
  • CpuGetPreMemConfigBlockTotalSize() : CpuPolicyLib.h
  • CpuPreMemPrintPolicy() : CpuPolicyLib.h
  • CpuPrintPolicy() : CpuPolicyLib.h
  • CpuRegbarAnd16() : CpuRegbarAccessLib.h
  • CpuRegbarAnd32() : CpuRegbarAccessLib.h
  • CpuRegbarAnd8() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr16() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr32() : CpuRegbarAccessLib.h
  • CpuRegbarAndThenOr8() : CpuRegbarAccessLib.h
  • CpuRegbarOr16() : CpuRegbarAccessLib.h
  • CpuRegbarOr32() : CpuRegbarAccessLib.h
  • CpuRegbarOr8() : CpuRegbarAccessLib.h
  • CpuRegbarRead16() : CpuRegbarAccessLib.h
  • CpuRegbarRead32() : CpuRegbarAccessLib.h
  • CpuRegbarRead64() : CpuRegbarAccessLib.h
  • CpuRegbarRead8() : CpuRegbarAccessLib.h
  • CpuRegbarWrite16() : CpuRegbarAccessLib.h
  • CpuRegbarWrite32() : CpuRegbarAccessLib.h
  • CpuRegbarWrite64() : CpuRegbarAccessLib.h
  • CpuRegbarWrite8() : CpuRegbarAccessLib.h
  • CpuWriteTraceHubAcpiBase() : CpuPlatformLib.h
  • CreateConfigBlockTable() : ConfigBlockLib.h
  • CreateITbtDxeConfigBlocks() : DxeITbtPolicyLib.h
  • CreatePchDxeConfigBlocks() : DxePchPolicyLib.h
  • CreateSaDxeConfigBlocks() : DxeSaPolicyLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- d -

  • DisableCacheAsRam() : CacheAsRamLib.h
  • DumpFspErrorInfo() : FspErrorInfoLib.h
  • DumpSiPolicy() : SiPolicyLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- e -

  • EnablePowerWell2() : GraphicsInfoFruLib.h
  • EnablePowerWell3() : GraphicsInfoFruLib.h
  • EnterS3WithImmediateWake() : ResetSystemLib.h
  • EspiDevNumber() : PchPciBdfLib.h
  • EspiFuncNumber() : PchPciBdfLib.h
  • EspiPciCfgBase() : PchPciBdfLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- f -

  • FiaGetLos() : FiaAccessLib.h
  • FiaGetMaxLosRegister() : FiaAccessLib.h
  • FileClose() : DxeJhiSupportLib.h
  • FileOpen() : DxeJhiSupportLib.h
  • FileRead() : DxeJhiSupportLib.h
  • FindMeFwStsIndex() : MeFwStsLib.h
  • ForceGtRc6() : GraphicsInfoFruLib.h
  • FspErrorStatusCodeReportWorker() : FspErrorInfoLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- g -

  • GbeDevNumber() : GbeLib.h , PchPciBdfLib.h
  • GbeFuncNumber() : PchPciBdfLib.h , GbeLib.h
  • GbeGetLanPhyRevision() : GbeLib.h
  • GbePciCfgBase() : PchPciBdfLib.h
  • GenerateUserNonce() : MeUtilsLib.h
  • GetActiveSocNorthAtomCoreCount() : CpuPlatformLib.h
  • GetBootGuardInfo() : BootGuardLibVer1.h
  • GetBootMediaType() : BootMediaLib.h
  • GetBootOptions() : DxeAsfHeciLib.h
  • GetBusRatio() : CpuPlatformLib.h
  • GetClkReqForClkSrc() : PchPcieRpLib.h
  • GetComponentConfigBlockTotalSize() : SiConfigBlockLib.h
  • GetConfigBlock() : ConfigBlockLib.h
  • GetConfigTdpLevels() : CpuPlatformLib.h
  • GetConfigTdpLevelsSupported() : CpuPlatformLib.h
  • GetCpuCrashLogBarAddress() : TelemetryLib.h
  • GetCpuCrashLogCapability() : TelemetryLib.h
  • GetCpuFamily() : CpuPlatformLib.h
  • GetCpuGeneration() : CpuPlatformLib.h
  • GetCpuIdentifier() : CpuPlatformLib.h
  • GetCpuIdentifierWithCtdp() : CpuPlatformLib.h
  • GetCpuNumberofCores() : CpuPlatformLib.h
  • GetCpuSku() : CpuPlatformLib.h
  • GetCpuStepping() : CpuPlatformLib.h
  • GetCpuSupportedCoresAndAtomCores() : CpuPlatformLib.h
  • GetCpuUcodeRevision() : CpuPlatformLib.h
  • GetCpuXhciBusNumber() : TcssInfoLib.h
  • GetCpuXhciDevNumber() : TcssInfoLib.h
  • GetCpuXhciFuncNumber() : TcssInfoLib.h
  • GetCrashLogHeader() : TelemetryLib.h
  • GetDigestFromDigestList() : Tpm2CommandLib.h
  • GetDigestListSize() : Tpm2CommandLib.h
  • GetEnabledCoreCount() : CpuPlatformLib.h
  • GetEnabledThreadCount() : CpuPlatformLib.h
  • GetGenerationString() : CpuPlatformLib.h
  • GetGmAdrOffset() : GraphicsInfoLib.h
  • GetGnaBusNumber() : GnaInfoLib.h
  • GetGnaDevNumber() : GnaInfoLib.h
  • GetGnaFuncNumber() : GnaInfoLib.h
  • GetGttMmAdrOffset() : GraphicsInfoLib.h
  • GetHashMaskFromAlgo() : Tpm2CommandLib.h
  • GetHashSizeFromAlgo() : Tpm2CommandLib.h
  • GetHeci() : MeUtilsLib.h
  • GetHeciPciBus() : MeUtilsLib.h
  • GetHeciPciDevice() : MeUtilsLib.h
  • GetHeciPciSegment() : MeUtilsLib.h
  • GetHybridGraphicsRpDevFun() : HybridGraphicsInfoFruLib.h
  • GetIgdBusNumber() : GraphicsInfoLib.h
  • GetIgdDevNumber() : GraphicsInfoLib.h
  • GetIgdDsmSizeInMb() : GraphicsInfoLib.h
  • GetIgdDssmRefClockFreqValue() : GraphicsInfoLib.h
  • GetIgdFuncNumber() : GraphicsInfoLib.h
  • GetIgdGmsSizeInMb() : GraphicsInfoLib.h
  • GetIgdGsmSizeInMb() : GraphicsInfoLib.h
  • GetIgdMsacOffset() : GraphicsInfoLib.h
  • GetIgdVtdOffset() : VtdInfoLib.h
  • GetIgfxApertureOffset() : GraphicsInfoLib.h
  • GetInitComplete() : MeUtilsLib.h
  • GetIopVtdOffset() : VtdInfoLib.h
  • GetIpuBusNumber() : IpuLib.h
  • GetIpuDevNumber() : IpuLib.h
  • GetIpuFuncNumber() : IpuLib.h
  • GetIpuVtdLowOffset() : VtdInfoLib.h
  • GetITbtDmaDevFun() : TbtCommonLib.h
  • GetITbtPcieDevNumber() : TcssInfoLib.h
  • GetMaxDmiBundles() : CpuDmiInfoLib.h
  • GetMaxDmiLanes() : CpuDmiInfoLib.h
  • GetMaxEfficiencyRatio() : CpuPlatformLib.h
  • GetMaxNonTurboRatio() : CpuPlatformLib.h
  • GetMaxNumVrs() : PeiVrDomainLib.h
  • GetMaxPhysicalAddressSize() : CpuPlatformLib.h
  • GetMaxSupportedPrmrrSize() : CpuPlatformLib.h
  • GetMaxVtdEngineNumber() : VtdInfoLib.h
  • GetMcaMsgParams() : MeUtilsLib.h
  • GetMeFwsts1FromHob() : MeUtilsLib.h
  • GetMeFwStsDeviceCount() : MeFwStsLib.h
  • GetMeFwStsOffsetCount() : MeFwStsLib.h
  • GetMeFwTypeSubTypeFromHob() : MeTypeLib.h
  • GetMeModeFromFwstsHob() : MeFwStsLib.h
  • GetMeStatusFromFwstsHob() : MeFwStsLib.h
  • GetMeUefiFwHealthStatus() : MeUefiFwHealthStatusLib.h
  • GetPackageTdp() : CpuPlatformLib.h
  • GetPchHdaMaxDmicLinkNum() : PchInfoLib.h
  • GetPchHdaMaxSndwLinkNum() : PchInfoLib.h
  • GetPchHdaMaxSspLinkNum() : PchInfoLib.h
  • GetPchHsioSataPreMemConfig() : PchPolicyLib.h
  • GetPchMaxIshGpNum() : PchInfoLib.h
  • GetPchMaxIshI2cControllersNum() : PchInfoLib.h
  • GetPchMaxIshSpiControllerCsPinsNum() : PchInfoLib.h
  • GetPchMaxIshSpiControllersNum() : PchInfoLib.h
  • GetPchMaxIshUartControllersNum() : PchInfoLib.h
  • GetPchMaxMeAppletCount() : PchInfoLib.h
  • GetPchMaxMeSessionCount() : PchInfoLib.h
  • GetPchMaxPcieClockNum() : PchInfoLib.h
  • GetPchMaxPcieClockReqNum() : PchInfoLib.h
  • GetPchMaxPcieControllerNum() : PchInfoLib.h
  • GetPchMaxPciePortNum() : PchInfoLib.h
  • GetPchMaxSerialIoI2cControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoI3cControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoSpiChipSelectsNum() : PchInfoLib.h
  • GetPchMaxSerialIoSpiControllersNum() : PchInfoLib.h
  • GetPchMaxSerialIoUartControllersNum() : PchInfoLib.h
  • GetPchMaxThcCount() : PchInfoLib.h
  • GetPchMaxTypeCPortNum() : PchInfoLib.h
  • GetPchPcieRpDevFun() : PchPcieRpLib.h
  • GetPchPcieRpNumber() : PchPcieRpLib.h
  • GetPchRstConfig() : PchPolicyLib.h
  • GetPchSataConfig() : PchPolicyLib.h
  • GetPchSpiDmiTarget() : PchInfoLib.h
  • GetPchUsb2MaxPhysicalPortNum() : PchInfoLib.h
  • GetPchUsb3MaxPhysicalPortNum() : PchInfoLib.h
  • GetPchUsbrKvmPortNum() : PchInfoLib.h
  • GetPchUsbrStoragePortNum() : PchInfoLib.h
  • GetPchXhciMaxUsb2PortNum() : PchInfoLib.h
  • GetPchXhciMaxUsb3PortNum() : PchInfoLib.h
  • GetPcieImrPortLocation() : PeiPcieRpLib.h
  • GetPcieImrPortNumber() : PeiPcieRpLib.h
  • GetPcieImrSize() : PeiPcieRpLib.h
  • GetRegBarSize() : HostBridgeInfoLib.h
  • GetRevisionTable() : CpuPlatformLib.h
  • GetRpSbiPid() : PchPcieRpLib.h
  • GetRsePassword() : DxeAmtHeciLib.h
  • GetRsePasswordV2() : DxeAmtHeciLib.h
  • GetSamFwInfo() : HostBridgeInfoLib.h
  • GetSataAbarSize() : SataLib.h
  • GetSataAhciBase() : SataLib.h
  • GetSataPortPresentStatus() : SataLib.h
  • GetSerialIoBar() : SerialIoAccessLib.h
  • GetSerialIoI2cPciCfg() : SerialIoAccessLib.h
  • GetSerialIoSpiPciCfg() : SerialIoAccessLib.h
  • GetSerialIoUartPciCfg() : SerialIoAccessLib.h
  • GetSkuString() : CpuPlatformLib.h
  • GetSpsEndOfPostStatus() : MeUtilsLib.h
  • GetSubCStateSupported() : CpuPlatformLib.h
  • GetSupportedCpuFeatures() : CpuPlatformLib.h
  • GetSupportedSocNorthAtomCores() : CpuPlatformLib.h
  • GetSystemTime() : SystemTimeLib.h
  • GetTbtDma0FuncNumber() : TcssInfoLib.h
  • GetTbtDmaBusNumber() : TcssInfoLib.h
  • GetTbtDmaDevNumber() : TcssInfoLib.h
  • GetVtdBaseAddress() : VtdInfoLib.h
  • GetVtdOffset() : VtdInfoLib.h
  • GpioCheckFor2Tier() : GpioLib.h
  • GpioClearAllGpiSmiSts() : GpioLib.h
  • GpioClearGpiGpeSts() : GpioLib.h
  • GpioClearGpiSmiSts() : GpioLib.h
  • GpioConfigurePads() : GpioLib.h
  • GpioDisableAllGpiSmi() : GpioLib.h
  • GpioGetGpeNumber() : GpioLib.h
  • GpioGetGpiGpeSts() : GpioLib.h
  • GpioGetGpioPadFromGroupAndPadNumber() : GpioNativeLib.h
  • GpioGetGpioPadFromGroupIndexAndPadNumber() : GpioNativeLib.h
  • GpioGetGpiSmiNum() : GpioLib.h
  • GpioGetGpiSmiSts() : GpioLib.h
  • GpioGetGroupDwToGpeDwX() : GpioLib.h
  • GpioGetGroupFromGpioPad() : GpioNativeLib.h
  • GpioGetGroupFromGroupIndex() : GpioNativeLib.h
  • GpioGetGroupIndexFromGpioPad() : GpioNativeLib.h
  • GpioGetGroupIndexFromGroup() : GpioNativeLib.h
  • GpioGetGroupName() : GpioLib.h
  • GpioGetGroupToGpeDwX() : GpioLib.h
  • GpioGetHighestGroup() : GpioNativeLib.h
  • GpioGetHostSwOwnershipForGroupDw() : GpioLib.h
  • GpioGetHostSwOwnershipForPad() : GpioLib.h
  • GpioGetInputInversion() : GpioLib.h
  • GpioGetInputValue() : GpioLib.h
  • GpioGetLowestGroup() : GpioNativeLib.h
  • GpioGetNativeSignalName() : GpioLib.h
  • GpioGetNumberOfGroups() : GpioNativeLib.h
  • GpioGetOutputValue() : GpioLib.h
  • GpioGetPadCfgLock() : GpioLib.h
  • GpioGetPadCfgLockForGroupDw() : GpioLib.h
  • GpioGetPadCfgLockTx() : GpioLib.h
  • GpioGetPadCfgLockTxForGroupDw() : GpioLib.h
  • GpioGetPadConfig() : GpioLib.h
  • GpioGetPadIoApicIrqNumber() : GpioLib.h
  • GpioGetPadName() : GpioLib.h
  • GpioGetPadNumberFromGpioPad() : GpioNativeLib.h
  • GpioGetPadOwnership() : GpioLib.h
  • GpioGetPadPerGroup() : GpioNativeLib.h
  • GpioGetPadResetConfig() : GpioLib.h
  • GpioIsSataGpEnabled() : GpioNativeLib.h
  • GpioLockPadCfg() : GpioLib.h
  • GpioLockPadCfgForGroupDw() : GpioLib.h
  • GpioLockPadCfgTx() : GpioLib.h
  • GpioLockPadCfgTxForGroupDw() : GpioLib.h
  • GpioLockPads() : GpioLib.h
  • GpioMinGetPadCfgLock() : GpioLib.h
  • GpioMinGetPadCfgLockForGroupDw() : GpioLib.h
  • GpioMinGetPadCfgLockTx() : GpioLib.h
  • GpioMinGetPadCfgLockTxForGroupDw() : GpioLib.h
  • GpioMinLockPadCfg() : GpioLib.h
  • GpioMinLockPadCfgTx() : GpioLib.h
  • GpioMinUnlockPadCfg() : GpioLib.h
  • GpioMinUnlockPadCfgTx() : GpioLib.h
  • GpioSetGroupDwToGpeDwX() : GpioLib.h
  • GpioSetGroupToGpeDwX() : GpioLib.h
  • GpioSetHostSwOwnershipForGroupDw() : GpioLib.h
  • GpioSetHostSwOwnershipForPad() : GpioLib.h
  • GpioSetInputInversion() : GpioLib.h
  • GpioSetOutputValue() : GpioLib.h
  • GpioSetPadConfig() : GpioLib.h
  • GpioSetPadElectricalConfig() : GpioLib.h
  • GpioSetPadInterruptConfig() : GpioLib.h
  • GpioSetPadResetConfig() : GpioLib.h
  • GpioUnlockPadCfg() : GpioLib.h
  • GpioUnlockPadCfgForGroupDw() : GpioLib.h
  • GpioUnlockPadCfgTx() : GpioLib.h
  • GpioUnlockPadCfgTxForGroupDw() : GpioLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- h -

  • HandleTpmStartupFailureOnS3() : BootGuardLibVer1.h
  • HbmCapabilitiesRequest() : DxeMeLib.h
  • HbmClientDisconnect() : DxeMeLib.h
  • HbmGetClientProperties() : DxeMeLib.h
  • HbmGetFlowControlToken() : DxeMeLib.h
  • HbmHostClientConnect() : DxeMeLib.h
  • HbmHostEnumRequest() : DxeMeLib.h
  • HbmHostStop() : DxeMeLib.h
  • HbmHostVersion() : DxeMeLib.h
  • HbmMapRequest() : DxeMeLib.h
  • HbmSendFlowControlToken() : DxeMeLib.h
  • HbmUnmapRequest() : DxeMeLib.h
  • HdaDevNumber() : PchPciBdfLib.h
  • HdaFuncNumber() : PchPciBdfLib.h
  • HdaPciCfgBase() : PchPciBdfLib.h
  • HeciArbSvnCommitMsg() : DxeMeLib.h
  • HeciArbSvnGetInfoMsg() : DxeMeLib.h
  • HeciAssetUpdateFwMsg() : DxeMeLib.h
  • HeciClearInvocationCode() : DxeMeLib.h
  • HeciCommitFilesMsg() : DxeMeLib.h
  • HeciCoreBiosDoneMsg() : DxeMeLib.h
  • HeciDnxReqClear() : DxeMeLib.h
  • HeciFwCapsGetRuleData() : DxeMeLib.h
  • HeciFwCapsSetRuleData() : DxeMeLib.h
  • HeciFwFeatureStateOverride() : DxeMeLib.h
  • HeciGetAmtBiosSyncInfo() : DxeMeLib.h
  • HeciGetCpuTypeChange() : DxeMeLib.h
  • HeciGetDamState() : DxeMeLib.h
  • HeciGetErLog() : DxeMeLib.h
  • HeciGetFipsMode() : DxeMeLib.h
  • HeciGetFwAvailableFeatures() : DxeMeLib.h
  • HeciGetFwCapsSkuMsg() : DxeMeLib.h
  • HeciGetFwFeatureStateMsg() : DxeMeLib.h
  • HeciGetFwUpdateState() : DxeMeLib.h
  • HeciGetFwVersionMsg() : DxeMeLib.h
  • HeciGetHerDataSha384() : MeChipsetLib.h
  • HeciGetIccClockSettings() : DxeMeLib.h
  • HeciGetIccProfile() : DxeMeLib.h
  • HeciGetImageFwVersionMsg() : DxeMeLib.h
  • HeciGetInvocationCode() : DxeMeLib.h
  • HeciGetIsUserConsentRequired() : DxeMeLib.h
  • HeciGetMeasuredBootState() : DxeMeLib.h
  • HeciGetMkhiVersion() : DxeMeLib.h , PeiMeLib.h
  • HeciGetMoffOverrideState() : DxeMeLib.h
  • HeciGetOemTagMsg() : DxeMeLib.h
  • HeciGetPlatformTypeMsg() : DxeMeLib.h
  • HeciGetPlatIdSupportedState() : DxeMeLib.h
  • HeciGetPsrRecord() : DxeMeLib.h
  • HeciGetRpmcStatus() : DxeMeLib.h
  • HeciGetSouthClinkState() : DxeMeLib.h
  • HeciGetUnconfigOnRtcClearDisableMsg() : DxeMeLib.h
  • HeciGetUnconfigureStatus() : DxeMeLib.h
  • HeciGetUpidFeatureState() : DxeMeLib.h
  • HeciGetUpidOsControlState() : DxeMeLib.h
  • HeciGetUpidPlatformId() : DxeMeLib.h
  • HeciGetUpidRefurbishCounter() : DxeMeLib.h
  • HeciGetUserCapabilitiesState() : DxeMeLib.h
  • HeciHmrfpoDisable() : DxeMeLib.h
  • HeciHmrfpoEnable() : DxeMeLib.h
  • HeciHmrfpoGetStatus() : DxeMeLib.h
  • HeciHmrfpoLock() : DxeMeLib.h
  • HeciIsMebxPasswordModified() : DxeMeLib.h
  • HeciModifyMebxPassword() : DxeMeLib.h
  • HeciPdtUnlockMsg() : DxeMeLib.h
  • HeciPdtUpdateMsg() : DxeMeLib.h
  • HeciReadFileExMsg() : DxeMeLib.h
  • HeciSendCbmResetRequest() : DxeMeLib.h
  • HeciSendChassisIntrDetEvent() : DxeMeLib.h
  • HeciSendCpuBrandClassFuse() : DxeMeLib.h
  • HeciSendWithAck() : MeUtilsLib.h
  • HeciSetAcmTpmData() : DxeMeLib.h
  • HeciSetCpuTypeChangeUserResponse() : DxeMeLib.h
  • HeciSetDamState() : DxeMeLib.h
  • HeciSetFileExMsg() : DxeMeLib.h
  • HeciSetFipsMode() : DxeMeLib.h
  • HeciSetFwEnabledFeatures() : DxeMeLib.h
  • HeciSetFwUpdateState() : DxeMeLib.h
  • HeciSetIccClockSettings() : DxeMeLib.h
  • HeciSetIccProfile() : DxeMeLib.h
  • HeciSetInvocationCode() : DxeMeLib.h
  • HeciSetManufacturingMeResetAndHalt() : DxeMeLib.h
  • HeciSetMeasuredBootState() : DxeMeLib.h
  • HeciSetMeDisableMsg() : DxeMeLib.h
  • HeciSetMeEnableMsg() : DxeMeLib.h
  • HeciSetMoffOverrideState() : DxeMeLib.h
  • HeciSetSouthClinkState() : DxeMeLib.h
  • HeciSetUnconfigOnRtcClearDisableMsg() : DxeMeLib.h
  • HeciSetUpidFeatureState() : DxeMeLib.h
  • HeciSetUpidOsControlState() : DxeMeLib.h
  • HeciSetUserCapabilitiesState() : DxeMeLib.h
  • HeciUnconfigWithouPwd() : DxeMeLib.h
  • HeciUpdateUpidOemPlatformId() : DxeMeLib.h
  • HeciValidateMebxPassword() : DxeMeLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- i -

  • IehDevNumber() : PchPciBdfLib.h
  • IehFuncNumber() : PchPciBdfLib.h
  • IehPciCfgBase() : PchPciBdfLib.h
  • IgfxCmdRegEnabled() : GraphicsInfoLib.h
  • InstallHeciPpi() : PeiMeLib.h
  • InstallStallPpi() : StallPpiLib.h
  • InternalAsciiToUpper() : DxeJhiSupportLib.h
  • InternalWaitforCommandCompletion() : TbtCommonLib.h
  • IsAdlPch() : PchInfoLib.h
  • IsAudioInterfaceSupported() : PchInfoLib.h
  • IsBiosGuardEnabled() : CpuPlatformLib.h
  • IsBootGuardSupported() : BootGuardLibVer1.h
  • IsC6dramSupported() : CpuPlatformLib.h
  • IsCiraAvailable() : DxeMeLib.h
  • IsConfigTdpSupported() : CpuPlatformLib.h
  • IsCoreRatioLimitSupported() : CpuPlatformLib.h
  • IsCpuDebugDisabled() : MeFwStsLib.h
  • IsCpuDmiEnabled() : CpuDmiInfoLib.h
  • IsDesktopSku() : SaPlatformLib.h
  • IsDisplayOnlySku() : GraphicsInfoFruLib.h
  • IsDisplayPresent() : GraphicsInfoFruLib.h
  • IsDmiGen4Supported() : CpuDmiInfoLib.h
  • IsDoorbellRangeValid() : GraphicsInfoLib.h
  • IsDsmBaseAndImrMemoryConsistent() : GraphicsInfoLib.h
  • IsEbgPch() : PchInfoLib.h
  • IsEdramEnable() : CpuPlatformLib.h
  • IsEnergyEfficientTurboSupported() : CpuPlatformLib.h
  • IsEspiEnabled() : EspiLib.h
  • IsEspiSecondSlaveSupported() : EspiLib.h
  • IsEspiSlaveChannelSupported() : EspiLib.h
  • IsExtendedBiosRangeDecodeSupported() : PchInfoLib.h
  • IsExtendedMeasuredBootEnabled() : DxeMeLib.h
  • IsGbeEnabled() : GbeLib.h
  • IsGbePresent() : GbeLib.h
  • IsGbeRegionValid() : GbeLib.h
  • IsGcdRc6Locked() : GraphicsInfoLib.h
  • IsGcdRc6RangeValid() : GraphicsInfoLib.h
  • IsGsmBaseAndImrMemoryConsistent() : GraphicsInfoLib.h
  • IsGtPresent() : GraphicsInfoFruLib.h
  • IsHaloSku() : SaPlatformLib.h
  • IsHashAlgSupportedInHashAlgorithmMask() : Tpm2CommandLib.h
  • IshDevNumber() : PchPciBdfLib.h
  • IsHeciDeviceFunction() : MeChipsetLib.h
  • IsHfpgaEnvironment() : PreSiliconEnvDetectLib.h
  • IshFuncNumber() : PchPciBdfLib.h
  • IshPciCfgBase() : PchPciBdfLib.h
  • IsHSLEEnvironment() : PreSiliconEnvDetectLib.h
  • IsHSLEEnvironment_UPF() : PreSiliconEnvDetectLib.h
  • IsHwpSupported() : CpuPlatformLib.h
  • IsHyperThreadingSupported() : CpuPlatformLib.h
  • IsIGfxSupported() : GraphicsInfoLib.h
  • IsInSmm() : MeUtilsLib.h
  • IsIntelProcessorTraceSupported() : CpuPlatformLib.h
  • IsIshPresent() : IshInfoLib.h
  • IsIshSupported() : IshInfoLib.h
  • IsItbmSupported() : CpuPlatformLib.h
  • IsLpmSupported() : CpuPlatformLib.h
  • IsMediaPresent() : GraphicsInfoFruLib.h
  • IsMediaRc6Locked() : GraphicsInfoLib.h
  • IsMediaRc6RangeValid() : GraphicsInfoLib.h
  • IsMobileSku() : SaPlatformLib.h
  • IsOcSupported() : CpuPlatformLib.h
  • IsP2sb20bPcrSupported() : PchInfoLib.h
  • IsPavpBitLocked() : GraphicsInfoLib.h
  • IsPchChipsetInitSyncSupported() : PchInfoLib.h
  • IsPchEmmcSupported() : PchInfoLib.h
  • IsPchH() : PchInfoLib.h
  • IsPchLinkDmi() : CpuDmiInfoLib.h
  • IsPchLp() : PchInfoLib.h
  • IsPchM() : PchInfoLib.h
  • IsPchN() : PchInfoLib.h
  • IsPchP() : PchInfoLib.h
  • IsPchPSOnSupported() : PchInfoLib.h
  • IsPchS() : PchInfoLib.h
  • IsPchSdCardSupported() : PchInfoLib.h
  • IsPchServer() : PchInfoLib.h
  • IsPchSupported() : PchInfoLib.h
  • IsPchThcHidModeSupported() : PchInfoLib.h
  • IsPchThcSupported() : PchInfoLib.h
  • IsPchWithFdmi() : PchInfoLib.h
  • IsPchWithOpdmi() : PchInfoLib.h
  • IsPchWithPdmi() : PchInfoLib.h
  • IsPcieImrEnabled() : PeiPcieRpLib.h
  • IsPfatEnabled() : CpuPlatformLib.h
  • IsPolicyDefaultCheckRequired() : PeiSiPolicyUpdateLib.h
  • IsPpinFeatureAvailable() : CpuPlatformLib.h
  • IsRc6Locked() : GraphicsInfoLib.h
  • IsRc6RangeValid() : GraphicsInfoLib.h
  • IsRemappingSupportedOnSata() : SataSocLib.h
  • IsS3m2Ibl() : PchInfoLib.h
  • IsSaDevice4Enable() : HostBridgeInfoLib.h
  • IsSamEnabled() : HostBridgeInfoLib.h
  • IsSamplePart() : CpuPlatformLib.h
  • IsSataPowerGatingSupported() : SataSocLib.h
  • IsSaVrSupport() : CpuPlatformLib.h
  • IsSecondaryThread() : CpuPlatformLib.h
  • IsSerialIoI2cDeviceId() : SerialIoAccessLib.h
  • IsSerialIoI2cFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoSpiFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoUartFunction0Enabled() : SerialIoAccessLib.h
  • IsSerialIoUartInPciMode() : SerialIoUartLib.h
  • IsServerSku() : SaPlatformLib.h
  • IsSimicsEnvironment() : PreSiliconEnvDetectLib.h
  • IsSmxSupported() : CpuPlatformLib.h
  • IsTccSku() : TccLib.h
  • IsTimedMwaitSupported() : CpuPlatformLib.h
  • IsTmeActivated() : TmeInfoLib.h
  • IsTmeActivateLocked() : TmeInfoLib.h
  • IsTmeSupported() : CpuPlatformLib.h
  • IsTsegBaseAndImrMemoryConsistent() : HostBridgeInfoLib.h
  • IsTsnPresent() : TsnLib.h
  • IsTurboModeSupported() : CpuPlatformLib.h
  • IsValiduCodeEntry() : CpuPlatformLib.h
  • IsWoPcmBaseRegistersConsistent() : GraphicsInfoLib.h
  • IsWoPcmRangeValid() : GraphicsInfoLib.h
  • IsXETdcTdpLimitSupported() : CpuPlatformLib.h
  • ITbtAddConfigBlocks() : PeiITbtPolicyLib.h
  • ITbtGetConfigBlockTotalSize() : PeiITbtPolicyLib.h
  • ITbtInstallPolicyProtocol() : DxeITbtPolicyLib.h
  • ITbtPrintDxePolicyConfig() : DxeITbtPolicyLib.h
  • ITbtPrintPolicy() : PeiITbtPolicyLib.h
  • ItssGet8254ClockGateState() : ItssLib.h
  • ItssSet8254ClockGateState() : ItssLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- l -

  • LoadMemConfigDefault() : PeiMemPolicyLib.h
  • LoadMemConfigNoCrcDefault() : PeiMemPolicyLib.h
  • LpcDevNumber() : PchPciBdfLib.h
  • LpcFuncNumber() : PchPciBdfLib.h
  • LpcPciCfgBase() : PchPciBdfLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- m -

  • MailboxRead() : CpuMailboxLib.h
  • MailboxWrite() : CpuMailboxLib.h
  • MaxSataControllerNum() : SataSocLib.h
  • MaxSataPortNum() : SataSocLib.h
  • MeAddConfigBlocks() : PeiMePolicyLib.h
  • MeAddConfigBlocksPreMem() : PeiMePolicyLib.h
  • MeBiosGetMeMode() : MeUtilsLib.h
  • MeBiosGetMeStatus() : MeUtilsLib.h
  • MeBiosGetMeStatusRaw() : MeUtilsLib.h
  • MebxActivateRemoteConfiguration() : DxeMebxWrapperLib.h
  • MebxCfgGetIPv6LanIntStatus() : DxeMebxWrapperLib.h
  • MebxClearScreen() : DxeMebxDisplayWrapperLib.h
  • MebxCloseUserInitiatedConnection() : DxeMebxWrapperLib.h
  • MebxCompleteConfigurationRequest() : DxeMebxWrapperLib.h
  • MebxConfigureScreen() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayError() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayErrorId() : DxeMebxDisplayWrapperLib.h
  • MebxDisplayText() : DxeMebxDisplayWrapperLib.h
  • MebxGetAmtPrivacyLevel() : DxeMebxWrapperLib.h
  • MebxGetConfigServerData() : DxeMebxWrapperLib.h
  • MebxGetConnectionStatus() : DxeMebxWrapperLib.h
  • MebxGetEndOfPostState() : DxeMebxWrapperLib.h
  • MebxGetFqdn() : DxeMebxWrapperLib.h
  • MebxGetHashedCertificates() : DxeMebxWrapperLib.h
  • MebxGetIdleTimeout() : DxeMebxWrapperLib.h
  • MebxGetIpv4Params() : DxeMebxWrapperLib.h
  • MebxGetKvmEnabled() : DxeMebxWrapperLib.h
  • MebxGetMebxPwdPolicy() : DxeMebxWrapperLib.h
  • MebxGetMeSetupAuditRecord() : DxeMebxWrapperLib.h
  • MebxGetPkiFqdnSuffix() : DxeMebxWrapperLib.h
  • MebxGetPlatformOptInPolicy() : DxeMebxWrapperLib.h
  • MebxGetPowerControlSettings() : DxeMebxWrapperLib.h
  • MebxGetProvisioningState() : DxeMebxWrapperLib.h
  • MebxGetRedirectionState() : DxeMebxWrapperLib.h
  • MebxGetZtcEnabledStatus() : DxeMebxWrapperLib.h
  • MebxIsAmthiInterfaceVersionSupported() : DxeMebxWrapperLib.h
  • MebxOpenUserInitiatedConnection() : DxeMebxWrapperLib.h
  • MebxPerformUnprovisioning() : DxeMebxWrapperLib.h
  • MebxReadUserInput() : DxeMebxDisplayWrapperLib.h
  • MebxSetAmtState() : DxeMebxWrapperLib.h
  • MebxSetCertificateHashState() : DxeMebxWrapperLib.h
  • MebxSetConfigServerData() : DxeMebxWrapperLib.h
  • MebxSetFqdn() : DxeMebxWrapperLib.h
  • MebxSetIdleTimeout() : DxeMebxWrapperLib.h
  • MebxSetIpv4Params() : DxeMebxWrapperLib.h
  • MebxSetKvmEnabled() : DxeMebxWrapperLib.h
  • MebxSetMebxPwdPolicy() : DxeMebxWrapperLib.h
  • MebxSetMebxState() : DxeMebxWrapperLib.h
  • MebxSetOptInState() : DxeMebxWrapperLib.h
  • MebxSetPkiFqdnSuffix() : DxeMebxWrapperLib.h
  • MebxSetSolStorageRedir() : DxeMebxWrapperLib.h
  • MebxSetZeroTouchEnabled() : DxeMebxWrapperLib.h
  • MebxStopRemoteConfiguration() : DxeMebxWrapperLib.h
  • MebxUpdatePowerPolicy() : DxeMebxWrapperLib.h
  • MeClientInRecovery() : MeUtilsLib.h
  • MeClientIsCorporate() : MeUtilsLib.h
  • MeClientIsReady() : MeUtilsLib.h
  • MeCoreBiosDoneEnabled() : DxeMeLib.h
  • MeCreatePolicyDefaults() : DxeMePolicyLib.h
  • MeDeviceControl() : MeChipsetLib.h
  • MeDeviceInit() : MeChipsetLib.h
  • MeEndOfPostEnabled() : PeiMeLib.h , DxeMeLib.h
  • MeEwlCommunicationFailures() : MeEwlLib.h
  • MeEwlStateFailures() : MeEwlLib.h
  • MeFwDowngradeSupported() : DxeMeLib.h
  • MeGetConfigBlockTotalSize() : PeiMePolicyLib.h
  • MeGetConfigBlockTotalSizePreMem() : PeiMePolicyLib.h
  • MeGetHeciBarAddress() : PeiMeLib.h
  • MeHeci2Enabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciD0I3Enabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciFullTrace() : DxeMeLib.h , PeiMeLib.h
  • MeHeciMessageCheckEnabled() : DxeMeLib.h , PeiMeLib.h
  • MeHeciTimeoutsEnabled() : PeiMeLib.h , DxeMeLib.h
  • MeInstallPolicyProtocol() : DxeMePolicyLib.h
  • MeIsAfterEndOfPost() : PeiMeLib.h , DxeMeLib.h
  • MeIsEnforceEDebugModeEnabled() : PeiMeLib.h
  • MeIsInRecovery() : MeUtilsLib.h
  • MeMbpHobSkipped() : PeiMeLib.h
  • MePrintPolicyPpi() : PeiMePolicyLib.h
  • MePrintPolicyPpiPreMem() : PeiMePolicyLib.h
  • MePrintPolicyProtocol() : DxeMePolicyLib.h
  • MeReportError() : DxeMeLib.h
  • MeRestoreBars() : MeChipsetLib.h
  • MeSaveBars() : MeChipsetLib.h
  • MeServedrPrintPolicyPpi() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemAddConfigBlocks() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemGetConfigBlockTotalSize() : PeiMeServerPreMemPolicyLib.h
  • MeServerPreMemPrintPolicyPpi() : PeiMeServerPreMemPolicyLib.h
  • MeSetEndOfPostDone() : PeiMeLib.h , DxeMeLib.h
  • MeSpsInRecovery() : MeUtilsLib.h
  • MeSpsIsNm() : MeUtilsLib.h
  • MeSpsIsReady() : MeUtilsLib.h
  • MeTypeGet() : MeTypeLib.h
  • MeTypeIsClient() : MeTypeLib.h
  • MeTypeIsDfx() : MeTypeLib.h
  • MeTypeIsDisabled() : MeTypeLib.h
  • MeTypeIsIgnition() : MeTypeLib.h
  • MeTypeIsSps() : MeTypeLib.h
  • MeTypeShowDebug() : MeTypeLib.h
  • MmPciBase() : MmPciLib.h
  • MrcAddConfigBlocksPreMem() : PeiMemPolicyLib.h
  • MrcGetConfigBlockTotalSizePreMem() : PeiMemPolicyLib.h
  • MrcLoadSamplePolicyPreMem() : PeiMemPolicyLib.h
  • MrcPrintPolicyPpiPreMem() : PeiMemPolicyLib.h
  • MtrrTransfer2DefaultWB() : SiMtrrLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- n -

  • NiftyRockSupportLevel() : CpuPlatformLib.h
  • NumberOfCpuSocketsPopulated() : CpuPlatformLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- o -

  • OcWdtInit() : OcWdtLib.h
  • OcWdtResetCheck() : OcWdtLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- p -

  • P2sbDevNumber() : PchPciBdfLib.h
  • P2sbFuncNumber() : PchPciBdfLib.h
  • P2sbGetEpmask() : P2sbLib.h
  • P2sbIsEpmaskLock() : P2sbLib.h
  • P2sbPciCfgBase() : PchPciBdfLib.h
  • PchAddConfigBlocks() : PchPolicyLib.h
  • PchAddPreMemConfigBlocks() : PchPolicyLib.h
  • PchBiosDecodeEnableSet() : PchCycleDecodingLib.h
  • PchDmiGetExtendedBiosRegionRange() : PchDmiAccessLib.h
  • PchDmiIsBiosInterfaceLock() : PchDmiAccessLib.h
  • PchDmiIsExtendedBiosRegionLimitLocked() : PchDmiAccessLib.h
  • PchEspiCs1GenIoRangeGet() : PchCycleDecodingLib.h
  • PchEspiCs1GenIoRangeSet() : PchCycleDecodingLib.h
  • PchEspiCs1IoEnableDecodingSet() : PchCycleDecodingLib.h
  • PchEspiCs1MemRangeGet() : PchCycleDecodingLib.h
  • PchEspiCs1MemRangeSet() : PchCycleDecodingLib.h
  • PchEspiSlaveChannelReset() : EspiLib.h
  • PchEspiSlaveGetConfig() : EspiLib.h
  • PchEspiSlaveGetStatus() : EspiLib.h
  • PchEspiSlaveInBandReset() : EspiLib.h
  • PchEspiSlaveSetConfig() : EspiLib.h
  • PchGeneration() : PchInfoLib.h
  • PchGetConfigBlockTotalSize() : PchPolicyLib.h
  • PchGetLpcDid() : PchInfoLib.h
  • PchGetMaxUfsNum() : PchInfoLib.h
  • PchGetPcieControllerSbiPid() : PchPcieRpLib.h
  • PchGetPreMemConfigBlockTotalSize() : PchPolicyLib.h
  • PchGetSeriesStr() : PchInfoLib.h
  • PchGetSkuStr() : PchInfoLib.h
  • PchGetSteppingStr() : PchInfoLib.h
  • PchGetSupportedRstMode() : PchInfoLib.h
  • PchHeci1DevNumber() : PchPciBdfLib.h
  • PchHeci1FuncNumber() : PchPciBdfLib.h
  • PchHeci1PciCfgBase() : PchPciBdfLib.h
  • PchHeci3DevNumber() : PchPciBdfLib.h
  • PchHeci3FuncNumber() : PchPciBdfLib.h
  • PchHeci3PciCfgBase() : PchPciBdfLib.h
  • PchHpetBaseGet() : PchCycleDecodingLib.h
  • PchInstallPolicyProtocol() : DxePchPolicyLib.h
  • PchIoApicBaseGet() : PchCycleDecodingLib.h
  • PchIoPort80DecodeSet() : PchCycleDecodingLib.h
  • PchIsGbeSupported() : PchInfoLib.h
  • PchIsIshSupported() : PchInfoLib.h
  • PchIsPcieL0sSupported() : PchPcieRpLib.h
  • PchIsPcieNativeAspmSupported() : PchPcieRpLib.h
  • PchIsTsnSupported() : PchInfoLib.h
  • PchLpcGenIoRangeClear() : PchCycleDecodingLib.h
  • PchLpcGenIoRangeGet() : PchCycleDecodingLib.h
  • PchLpcGenIoRangeSet() : PchCycleDecodingLib.h
  • PchLpcIoDecodeRangesSet() : PchCycleDecodingLib.h
  • PchLpcIoEnableDecodingAndThenOr() : PchCycleDecodingLib.h
  • PchLpcIoEnableDecodingSet() : PchCycleDecodingLib.h
  • PchLpcMemRangeGet() : PchCycleDecodingLib.h
  • PchLpcMemRangeSet() : PchCycleDecodingLib.h
  • PchPcieBase() : PchPcieRpLib.h
  • PchPcieRpDevNumber() : PchPciBdfLib.h
  • PchPcieRpFuncNumber() : PchPciBdfLib.h
  • PchPcieRpPciCfgBase() : PchPciBdfLib.h
  • PchPcrAndThenOr16() : PchPcrLib.h
  • PchPcrAndThenOr32() : PchPcrLib.h
  • PchPcrAndThenOr32WithReadback() : PchPcrLib.h
  • PchPcrAndThenOr8() : PchPcrLib.h
  • PchPcrGetPid() : PchPcrLib.h
  • PchPcrRead16() : PchPcrLib.h
  • PchPcrRead32() : PchPcrLib.h
  • PchPcrRead8() : PchPcrLib.h
  • PchPcrWrite16() : PchPcrLib.h
  • PchPcrWrite32() : PchPcrLib.h
  • PchPcrWrite8() : PchPcrLib.h
  • PchPreMemPrintPolicyPpi() : PchPolicyLib.h
  • PchPrintPolicyPpi() : PchPolicyLib.h
  • PchPrintPolicyProtocol() : DxePchPolicyLib.h
  • PchSeries() : PchInfoLib.h
  • PchSmmControlInit() : PchSmmControlLib.h
  • PchStepping() : PchInfoLib.h
  • PchTcoBaseGet() : PchCycleDecodingLib.h
  • PchTcoBaseSet() : PchCycleDecodingLib.h
  • PchTraceHubDevNumber() : PchPciBdfLib.h
  • PchTraceHubFuncNumber() : PchPciBdfLib.h
  • PchTraceHubPciCfgBase() : PchPciBdfLib.h
  • PchXdciDevNumber() : PchPciBdfLib.h
  • PchXdciFuncNumber() : PchPciBdfLib.h
  • PchXdciPciCfgBase() : PchPciBdfLib.h
  • PchXhciDevNumber() : PchPciBdfLib.h
  • PchXhciFuncNumber() : PchPciBdfLib.h
  • PchXhciPciCfgBase() : PchPciBdfLib.h
  • PcieBaseFindCapId() : PcieHelperLib.h
  • PcieBaseFindExtendedCapId() : PcieHelperLib.h
  • PcieFindCapId() : PcieHelperLib.h
  • PcieFindExtendedCapId() : PcieHelperLib.h
  • PcieRpClearSubordSecondBus() : PcieHelperLib.h
  • PcieRpSetSubordSecondBus() : PcieHelperLib.h
  • PeiHeciBupManufacturingResetAndHalt() : PeiMeLib.h
  • PeiHeciCommitFilesMsg() : PeiMeLib.h
  • PeiHeciDataClear() : PeiMeLib.h
  • PeiHeciDnxReqSet() : PeiMeLib.h
  • PeiHeciFwCapsSetRuleData() : PeiMeLib.h
  • PeiHeciGetAmtBiosSyncInfo() : PeiMeLib.h
  • PeiHeciGetBiosSeed() : PeiMeLib.h
  • PeiHeciGetDebugTokenData() : PeiMeLib.h
  • PeiHeciGetErLog() : PeiMeLib.h
  • PeiHeciGetFwCapsSkuMsg() : PeiMeLib.h
  • PeiHeciGetFwFeatureStateMsg() : PeiMeLib.h
  • PeiHeciGetFwPayload() : PeiMeLib.h
  • PeiHeciGetImrSizeMsg() : PeiMeLib.h
  • PeiHeciGetMbpMsg() : PeiMeLib.h
  • PeiHeciGetPlatformTypeMsg() : PeiMeLib.h
  • PeiHeciGetRpmcStatus() : PeiMeLib.h
  • PeiHeciGetSoftStrpConfigMsg() : PeiMeLib.h
  • PeiHeciGetUnconfigOnRtcClearDisableMsg() : PeiMeLib.h
  • PeiHeciGetUnconfigureStatus() : PeiMeLib.h
  • PeiHeciIccBclkMsg() : PeiMeLib.h
  • PeiHeciOverrideSoftStrapMsg() : PeiMeLib.h
  • PeiHeciReadChipsetInitMsg() : PeiMeLib.h
  • PeiHeciReadFromMphy() : PeiMeLib.h
  • PeiHeciRequestDeviceOwnership() : PeiMeLib.h
  • PeiHeciSendCbmResetRequest() : PeiMeLib.h
  • PeiHeciSendDid() : PeiMeLib.h
  • PeiHeciSendHostResetNotificationMsg() : PeiMeLib.h
  • PeiHeciSetEDebugModeState() : PeiMeLib.h
  • PeiHeciSetFileExMsg() : PeiMeLib.h
  • PeiHeciSetUnconfigOnRtcClearDisableMsg() : PeiMeLib.h
  • PeiHeciTerminateHeci() : PeiMeLib.h
  • PeiHeciWriteChipsetInitMsg() : PeiMeLib.h
  • PmcClearGlobalResetStatus() : PmcLib.h
  • PmcClearHostResetStatus() : PmcLib.h
  • PmcClearPowerFailureStatus() : PmcLib.h
  • PmcClearSusPowerFailureStatus() : PmcLib.h
  • PmcClearWakeStatus() : PmcLib.h
  • PmcCrashLogClear() : PmcLib.h
  • PmcCrashLogDisable() : PmcLib.h
  • PmcCrashLogDiscovery() : PmcLib.h
  • PmcCrashLogOnAllReset() : PmcLib.h
  • PmcCrashLogProgramGlobalResetTriggerEnableMask() : PmcLib.h
  • PmcCrashLogReadGlobalResetTriggerMask() : PmcLib.h
  • PmcCrashLogReArm() : PmcLib.h
  • PmcCrashLogRestoreGlobalResetTriggerMask() : PmcLib.h
  • PmcDetectIntegratedClockSource() : PmcLib.h
  • PmcDevNumber() : PchPciBdfLib.h
  • PmcDisablePowerButtonSmi() : PmcLib.h
  • PmcEnablePowerButtonSmi() : PmcLib.h
  • PmcFuncNumber() : PchPciBdfLib.h
  • PmcGetAcpiBase() : PmcLib.h
  • PmcGetPwrmBase() : PmcLib.h
  • PmcGetSleepTypeAfterWake() : PmcLib.h
  • PmcGetTimerCount() : PmcLib.h
  • PmcIsDebugModeLocked() : PmcLib.h
  • PmcIsDwrBootMode() : PmcLib.h
  • PmcIsFivrConfigLocked() : PmcLib.h
  • PmcIsGblSmiEn() : PmcLib.h
  • PmcIsPowerButtonOverrideDetected() : PmcLib.h
  • PmcIsPowerFailureDetected() : PmcLib.h
  • PmcIsRtcBatteryGood() : PmcLib.h
  • PmcIsSetStrapMsgInterfaceLocked() : PmcLib.h
  • PmcIsSmiLockSet() : PmcLib.h
  • PmcIsSusPowerFailureDetected() : PmcLib.h
  • PmcPciCfgBase() : PchPciBdfLib.h
  • PmcReadLpmReqData() : PmcLib.h
  • PmcSetDramInitScratchpad() : PmcLib.h
  • PmcSetPlatformStateAfterPowerFailure() : PmcLib.h
  • PmcSetSleepState() : PmcLib.h
  • PmcSetSwGpeSts() : PmcLib.h
  • PmcSetTPch25Timing() : PmcLib.h
  • PmcSsramPciCfgBase() : PchPciBdfLib.h
  • PmicRead8() : PmcLib.h
  • PmicWrite8() : PmcLib.h
  • PmicWriteLock() : PmcLib.h
  • PolicyDefaultCheckInit() : PeiSiPolicyUpdateLib.h
  • PollGtReady() : GraphicsInfoLib.h
  • PollMailboxReady() : CpuMailboxLib.h
  • PrintMeType() : MeTypeLib.h
  • PsthGetIoTrapResourceSetting() : PsthLib.h
  • PttHeciGetCapability() : PttHeciLib.h
  • PttHeciGetState() : PttHeciLib.h
  • PttHeciSetState() : PttHeciLib.h
  • PttHeciUpdateState() : PttHeciLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- r -

  • ReadVtdBaseAddress() : VtdInfoLib.h
  • RecursiveTbtHierarchyConfiguration() : DxeTbtDisBmeLib.h
  • RegisterMeReset() : PeiMeLib.h
  • ReportBiosStatus() : DxeAsfHeciLib.h
  • ReserveMmio64Size() : PeiDxeSmmReserveMmio64SizeLib.h
  • ResetCold() : ResetSystemLib.h
  • ResetHeci1Interface() : MeUtilsLib.h
  • ResetPlatformSpecific() : ResetSystemLib.h
  • ResetShutdown() : ResetSystemLib.h
  • ResetWarm() : ResetSystemLib.h
  • RstGetCycleRouterNumber() : RstCrLib.h
  • RtcIsBiosInterfaceLock() : RtcAccessLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- s -

  • SaAddConfigBlocks() : PeiSaPolicyLib.h
  • SaAddConfigBlocksPreMem() : PeiSaPolicyLib.h
  • SaGetConfigBlockTotalSize() : PeiSaPolicyLib.h
  • SaGetConfigBlockTotalSizePreMem() : PeiSaPolicyLib.h
  • SaInstallPolicyProtocol() : DxeSaPolicyLib.h
  • SaPrintPolicyPpi() : PeiSaPolicyLib.h
  • SaPrintPolicyPpiPreMem() : PeiSaPolicyLib.h
  • SaPrintPolicyProtocol() : DxeSaPolicyLib.h
  • SataControllerFunctionDisableStatus() : SataLib.h
  • SataDevNumber() : PchPciBdfLib.h
  • SataFuncNumber() : PchPciBdfLib.h
  • SataGetController() : SataSocLib.h
  • SataPciCfgBase() : PchPciBdfLib.h
  • ScsEmmcDevNumber() : PchPciBdfLib.h
  • ScsEmmcFuncNumber() : PchPciBdfLib.h
  • ScsEmmcPciCfgBase() : PchPciBdfLib.h
  • ScsSdCardDevNumber() : PchPciBdfLib.h
  • ScsSdCardFuncNumber() : PchPciBdfLib.h
  • ScsSdCardPciCfgBase() : PchPciBdfLib.h
  • ScsUfsDevNumber() : PchPciBdfLib.h
  • ScsUfsFuncNumber() : PchPciBdfLib.h
  • ScsUfsPciCfgBase() : PchPciBdfLib.h
  • SecGetFsptApiParameter() : GetFsptApiParameter.h
  • SecGetPerformance() : SecPlatformLib.h
  • SecPlatformInformation() : SecPlatformLib.h
  • SecPlatformMain() : SecPlatformLib.h
  • SendFspErrorInfo() : FspErrorInfoLib.h
  • SendFspErrorInfoStatusCode() : FspErrorInfoLib.h
  • SendOcrPetAlert() : DxeAmtHeciLib.h
  • SendOcrPetEvent() : DxeAmtHeciLib.h
  • SendRpePetAlert() : DxeAmtHeciLib.h
  • SendRsePetAlert() : DxeAmtHeciLib.h
  • SerialIoI2cBlockWriteRead() : SerialIoI2cLib.h
  • SerialIoI2cDevNumber() : PchPciBdfLib.h
  • SerialIoI2cFuncNumber() : PchPciBdfLib.h
  • SerialIoI2cPciCfgBase() : PchPciBdfLib.h
  • SerialIoI2cRead() : SerialIoI2cLib.h
  • SerialIoI2cWrite() : SerialIoI2cLib.h
  • SerialIoI3cDevNumber() : PchPciBdfLib.h
  • SerialIoI3cFuncNumber() : PchPciBdfLib.h
  • SerialIoI3cPciCfgBase() : PchPciBdfLib.h
  • SerialIoSpiChipSelectConfig() : SerialIoSpiLib.h
  • SerialIoSpiDevNumber() : PchPciBdfLib.h
  • SerialIoSpiFuncNumber() : PchPciBdfLib.h
  • SerialIoSpiPciCfgBase() : PchPciBdfLib.h
  • SerialIoSpiRead() : SerialIoSpiLib.h
  • SerialIoSpiWrite() : SerialIoSpiLib.h
  • SerialIoSpiWriteRead() : SerialIoSpiLib.h
  • SerialIoUartDebugPcdGetAttributes() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetControllerNumber() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetDebugEnable() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetDeviceConfig() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDebugPcdGetPciDefaultMmioBase() : SerialIoUartDebugPropertyPcdLib.h
  • SerialIoUartDevNumber() : PchPciBdfLib.h
  • SerialIoUartDummyRead() : SerialIoUartLib.h
  • SerialIoUartFuncNumber() : PchPciBdfLib.h
  • SerialIoUartGetOutOfReset() : SerialIoUartLib.h
  • SerialIoUartPciCfgBase() : PchPciBdfLib.h
  • SerialIoUartPolling() : SerialIoUartLib.h
  • SerialIoUartRead() : SerialIoUartLib.h
  • SerialIoUartSetAttributes() : SerialIoUartLib.h
  • SerialIoUartSetMmioInPciMode() : SerialIoUartLib.h
  • SerialIoUartWrite() : SerialIoUartLib.h
  • SetD0I3Bit() : MeChipsetLib.h
  • SetInterruptPin() : PchPcrLib.h
  • SetMeUefiFwHealthEfiStatus() : MeUefiFwHealthStatusLib.h
  • SetMeUefiFwHealthStatus() : MeUefiFwHealthStatusLib.h
  • SetPostCodeToScratchPad() : PostCodeToScratchPadLib.h
  • ShowBuffer() : MeShowBufferLib.h
  • SiCreateConfigBlocks() : SiPolicyLib.h
  • SiCreatePreMemConfigBlocks() : SiPolicyLib.h
  • SiInstallPolicyPpi() : SiPolicyLib.h
  • SiInstallPolicyReadyPpi() : SiPolicyLib.h
  • SiPreMemInstallPolicyPpi() : SiPolicyLib.h
  • SiPreMemInstallPolicyReadyPpi() : SiPolicyLib.h
  • SiPreMemPrintPolicyPpi() : SiPolicyLib.h
  • SiPrintPolicyPpi() : SiPolicyLib.h
  • SmbusClearStatusReg() : SmbusInfoLib.h
  • SmbusDevNumber() : SmbusInfoLib.h , PchPciBdfLib.h
  • SmbusDmaDevNumber() : PchPciBdfLib.h
  • SmbusDmaFuncNumber() : PchPciBdfLib.h
  • SmbusDmaPciCfgBase() : PchPciBdfLib.h
  • SmbusFuncNumber() : PchPciBdfLib.h , SmbusInfoLib.h
  • SmbusIsHostLocked() : SmbusInfoLib.h
  • SmbusPciCfgBase() : PchPciBdfLib.h
  • SpiClearBcSyncSs() : SpiAccessLib.h
  • SpiDeviceNumber() : SpiAccessLib.h
  • SpiDevNumber() : PchPciBdfLib.h
  • SpiFuncNumber() : PchPciBdfLib.h
  • SpiFunctionNumber() : SpiAccessLib.h
  • SpiGetBar0() : SpiAccessLib.h
  • SpiGetBiosRegionFlashReadAccess() : SpiAccessLib.h
  • SpiGetBiosRegionFlashWriteAccess() : SpiAccessLib.h
  • SpiGetComponentPropertyParameterTable() : SpiAccessLib.h
  • SpiGetCsmeRegionAccess() : SpiAccessLib.h
  • SpiGetDescriptorSignature() : SpiAccessLib.h
  • SpiGetEcRegionAccess() : SpiAccessLib.h
  • SpiGetExtendedBiosRegionRange() : SpiAccessLib.h
  • SpiGetFlashComponentDescription() : SpiAccessLib.h
  • SpiGetFlashComponentsNumber() : SpiAccessLib.h
  • SpiGetGbeRegionAccess() : SpiAccessLib.h
  • SpiGetMasterReadAccess() : SpiAccessLib.h
  • SpiGetMasterWriteAccess() : SpiAccessLib.h
  • SpiGetPciCfgAddress() : SpiAccessLib.h
  • SpiGetTotalFlashSize() : SpiAccessLib.h
  • SpiIsBiosBootFromSpi() : SpiAccessLib.h
  • SpiIsBiosInterfaceLockdownEnabled() : SpiAccessLib.h
  • SpiIsControllerAvailable() : SpiAccessLib.h
  • SpiIsCppValidBitSet() : SpiAccessLib.h
  • SpiIsExtendedBiosRegionBaseLocked() : SpiAccessLib.h
  • SpiIsExtendedBiosRegionEnabled() : SpiAccessLib.h
  • SpiIsFlashConfigurationLockDownEnabled() : SpiAccessLib.h
  • SpiIsFlashDescriptorOverrideEnabled() : SpiAccessLib.h
  • SpiIsFlashDescriptorValid() : SpiAccessLib.h
  • SpiIsGbeRegionValid() : SpiAccessLib.h
  • SpiIsSafModeActive() : SpiAccessLib.h
  • SpiIsTopSwapEnabled() : SpiAccessLib.h
  • SpiIsWriteProtectionEnabled() : SpiAccessLib.h
  • SpiIsWriteStatusDisable() : SpiAccessLib.h
  • SpiPciCfgBase() : PchPciBdfLib.h
  • SpiServiceInit() : SpiLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- t -

  • TbtClearVgaRegisters() : TbtCommonLib.h
  • TbtGetBootMode() : PeiTbtTaskDispatchLib.h
  • TbtGetSecLevel() : TbtCommonLib.h
  • TbtSetDmaSsidSvid() : TbtCommonLib.h
  • TbtSetPcie2TbtCommand() : TbtCommonLib.h
  • TbtSetSecLevel() : TbtCommonLib.h
  • TbtTaskDistpach() : PeiTbtTaskDispatchLib.h
  • TcoClearSecondToStatus() : TcoLib.h
  • TcoHaltTimer() : TcoLib.h
  • TcoIsSmiLock() : TcoLib.h
  • TcoSecondToHappened() : TcoLib.h
  • ThcDevNumber() : PchPciBdfLib.h
  • ThcFuncNumber() : PchPciBdfLib.h
  • ThcIsEnabled() : ThcLib.h
  • ThcIsSupported() : ThcLib.h
  • ThcPciCfgBase() : PchPciBdfLib.h
  • ThermalDevNumber() : PchPciBdfLib.h
  • ThermalFuncNumber() : PchPciBdfLib.h
  • ThermalIsEcThermalReportLock() : ThermalAccessLib.h
  • ThermalIsPchHotLock() : ThermalAccessLib.h
  • ThermalIsPmcThrottleLock() : ThermalAccessLib.h
  • ThermalIsThrottleLock() : ThermalAccessLib.h
  • ThermalPciCfgBase() : PchPciBdfLib.h
  • TopSwapSet() : TopSwapLib.h
  • TopSwapStatus() : TopSwapLib.h
  • Tpm2ChangeEPS() : Tpm2CommandLib.h
  • Tpm2ChangePPS() : Tpm2CommandLib.h
  • Tpm2Clear() : Tpm2CommandLib.h
  • Tpm2ClearControl() : Tpm2CommandLib.h
  • Tpm2DictionaryAttackLockReset() : Tpm2CommandLib.h
  • Tpm2DictionaryAttackParameters() : Tpm2CommandLib.h
  • Tpm2EventSequenceComplete() : Tpm2CommandLib.h
  • Tpm2FlushContext() : Tpm2CommandLib.h
  • Tpm2GetCapability() : Tpm2CommandLib.h
  • Tpm2GetCapabilityAlgorithmSet() : Tpm2CommandLib.h
  • Tpm2GetCapabilityFamily() : Tpm2CommandLib.h
  • Tpm2GetCapabilityFirmwareVersion() : Tpm2CommandLib.h
  • Tpm2GetCapabilityInputBufferSize() : Tpm2CommandLib.h
  • Tpm2GetCapabilityLockoutCounter() : Tpm2CommandLib.h
  • Tpm2GetCapabilityLockoutInterval() : Tpm2CommandLib.h
  • Tpm2GetCapabilityManufactureID() : Tpm2CommandLib.h
  • Tpm2GetCapabilityMaxCommandResponseSize() : Tpm2CommandLib.h
  • Tpm2GetCapabilityPcrs() : Tpm2CommandLib.h
  • Tpm2GetCapabilitySupportedAlg() : Tpm2CommandLib.h
  • Tpm2GetCapabilitySupportedAndActivePcrs() : Tpm2CommandLib.h
  • Tpm2HashSequenceStart() : Tpm2CommandLib.h
  • Tpm2HierarchyChangeAuth() : Tpm2CommandLib.h
  • Tpm2HierarchyControl() : Tpm2CommandLib.h
  • Tpm2NvDefineSpace() : Tpm2CommandLib.h
  • Tpm2NvGlobalWriteLock() : Tpm2CommandLib.h
  • Tpm2NvRead() : Tpm2CommandLib.h
  • Tpm2NvReadLock() : Tpm2CommandLib.h
  • Tpm2NvReadPublic() : Tpm2CommandLib.h
  • Tpm2NvUndefineSpace() : Tpm2CommandLib.h
  • Tpm2NvWrite() : Tpm2CommandLib.h
  • Tpm2NvWriteLock() : Tpm2CommandLib.h
  • Tpm2PcrAllocate() : Tpm2CommandLib.h
  • Tpm2PcrAllocateBanks() : Tpm2CommandLib.h
  • Tpm2PcrEvent() : Tpm2CommandLib.h
  • Tpm2PcrExtend() : Tpm2CommandLib.h
  • Tpm2PcrRead() : Tpm2CommandLib.h
  • Tpm2PolicyCommandCode() : Tpm2CommandLib.h
  • Tpm2PolicyGetDigest() : Tpm2CommandLib.h
  • Tpm2PolicyOR() : Tpm2CommandLib.h
  • Tpm2PolicySecret() : Tpm2CommandLib.h
  • Tpm2ReadPublic() : Tpm2CommandLib.h
  • Tpm2SelfTest() : Tpm2CommandLib.h
  • Tpm2SequenceComplete() : Tpm2CommandLib.h
  • Tpm2SequenceUpdate() : Tpm2CommandLib.h
  • Tpm2SetAlgorithmSet() : Tpm2CommandLib.h
  • Tpm2SetPrimaryPolicy() : Tpm2CommandLib.h
  • Tpm2Shutdown() : Tpm2CommandLib.h
  • Tpm2StartAuthSession() : Tpm2CommandLib.h
  • Tpm2Startup() : Tpm2CommandLib.h
  • Tpm2TestParms() : Tpm2CommandLib.h
  • TraceHubDebugWrite() : TraceHubDebugLib.h
  • TraceHubMmioTraceAddress() : TraceHubHookLib.h
  • TraceHubScratchPad2RegValue() : TraceHubHookLib.h
  • TraceHubWriteCataLog64_0() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_1() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_2() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_3() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_4() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_5() : TraceHubDebugLib.h
  • TraceHubWriteCataLog64_6() : TraceHubDebugLib.h
  • TsnDevNumber() : TsnLib.h , PchPciBdfLib.h
  • TsnFuncNumber() : PchPciBdfLib.h , TsnLib.h
  • TsnPciCfgBase() : PchPciBdfLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- u -

  • UpdateFviInfo() : SiFvi.h
  • UpdatePeiAmtPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiCpuPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiCpuPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMePolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMePolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMeServerPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiMeServerPreMemPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiPchPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiPchPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSaPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSaPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSiPolicy() : PeiSiPolicyUpdateLib.h
  • UpdatePeiSiPolicyPreMem() : PeiSiPolicyUpdateLib.h
  • UpdatePeiTbtPolicy() : PeiSiPolicyUpdateLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- w -

  • WaitFirmwareInitComplete() : MeUtilsLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- x -

  • XhciMmioEnable() : UsbLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

  • gAmtSaveMebxProtocolGuid : AmtSaveMebxProtocol.h
  • gBiosGuardConfigGuid : BiosGuardConfig.h
  • gHeciAccessPpiGuid : HeciAccessPpi.h
  • gHeciAccessProtocolGuid : HeciAccessProtocol.h
  • gHeciControlPpiGuid : HeciControlPpi.h
  • gHeciControlProtocolGuid : HeciControlProtocol.h
  • gHeciPpiGuid : HeciPpi.h
  • gITbtPolicyProtocolGuid : ITbtPolicy.h
  • gMbpSensitivePpiGuid : MbpSensitivePpi.h
  • gSaPolicyProtocolGuid : SaPolicy.h
  • gSmmBiosGuardProtocolGuid : Protocol/BiosGuard.h
  • gSsaBiosCallBacksPpiGuid : SsaPeiInit.h
  • mSecondsToMsrValueMapTable : CpuPlatformLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- a -

  • AMT_POLICY_PROTOCOL : AmtPolicy.h
  • AMT_READY_TO_BOOT_PROTOCOL_SIGNAL : AmtReadyToBoot.h
  • AMT_REPORT_ERROR : AmtConfig.h
  • AMT_SAVE_MEBX_DATA : AmtSaveMebxProtocol.h

- b -

  • BIOS_OS_DATA_REGION : Txt.h
  • BIOSGUARD_ERASE : Protocol/BiosGuard.h
  • BIOSGUARD_EXECUTE : Protocol/BiosGuard.h
  • BIOSGUARD_PROTOCOL : Protocol/BiosGuard.h
  • BIOSGUARD_WRITE : Protocol/BiosGuard.h

- c -

  • CONFIG_BLOCK : ConfigBlock.h
  • CONFIG_BLOCK_HEADER : ConfigBlock.h
  • CONFIG_BLOCK_TABLE_HEADER : ConfigBlock.h

- d -

  • DISABLE_BUS_MASTER_ENABLE : TbtDisBmeProtocol.h
  • DXE_ITBT_CONFIG : DxeITbtConfig.h
  • DXE_ITBT_GENERIC_CONFIG : DxeITbtConfig.h

- e -

  • EXCEPTION_HANDLER : SmmResourceConfigProtocol.h

- f -

  • FSP_TEMP_RAM_EXIT : TempRamExitPpi.h

- g -

  • GET_MEBX_DATA : MebxConfigProtocol.h
  • GET_PLATFORM_DOCK_STATUS : GopPolicy.h
  • GET_PLATFORM_LID_STATUS : GopPolicy.h
  • GET_VBT_DATA : GopPolicy.h
  • GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME : GopComponentName2.h
  • GOP_COMPONENT_NAME2_GET_DRIVER_NAME : GopComponentName2.h
  • GOP_COMPONENT_NAME2_GET_DRIVER_VERSION : GopComponentName2.h
  • GPIO_GROUP : GpioConfig.h
  • GPIO_NATIVE_PAD : GpioConfig.h
  • GPIO_PAD : GpioConfig.h

- h -

  • HEAP_BIOS_SPEC_VER_ELEMENT : Txt.h
  • HEAP_BIOSACM_ELEMENT : Txt.h
  • HEAP_EXT_DATA_ELEMENT : Txt.h
  • HECI_ACCESS : HeciAccessProtocol.h
  • HECI_ACCESS_GET_NEXT_HECI : HeciAccessProtocol.h
  • HECI_ACCESS_GET_PARAMETER : HeciAccessProtocol.h
  • HECI_CONTROL : HeciControlProtocol.h
  • HECI_CONTROL_READ_FIRMWARE_STATUS : HeciControlProtocol.h
  • HECI_CONTROL_RECEIVE : HeciControlProtocol.h
  • HECI_CONTROL_RESET : HeciControlProtocol.h
  • HECI_CONTROL_SEND : HeciControlProtocol.h
  • HECI_CONTROL_SEND_AND_RECEIVE : HeciControlProtocol.h
  • HECI_GET_ME_MODE : HeciProtocol.h
  • HECI_GET_ME_STATUS : HeciProtocol.h
  • HECI_INIT : HeciProtocol.h
  • HECI_PROTOCOL : HeciProtocol.h
  • HECI_READ_MESSAGE : HeciProtocol.h
  • HECI_REINIT : HeciProtocol.h
  • HECI_RESET : HeciProtocol.h
  • HECI_RESET_WAIT : HeciProtocol.h
  • HECI_SEND_MESSAGE : HeciProtocol.h
  • HECI_SENDWACK : HeciProtocol.h
  • HID_ENABLE_AFTER_RESET : Thc.h
  • HID_GET_FEATURE : Thc.h
  • HID_SET_FEATURE : Thc.h

- i -

  • IO_TRAP_EX_DISPATCH_CALLBACK : IoTrapExDispatch.h
  • IO_TRAP_EX_DISPATCH_REGISTER : IoTrapExDispatch.h
  • IO_TRAP_EX_DISPATCH_UNREGISTER : IoTrapExDispatch.h
  • IS_WDT_ENABLED : Protocol/Wdt.h
  • IS_WDT_REQUIRED : Protocol/Wdt.h
  • ITBT_GENERIC_CONFIG : PeiITbtGenericStructure.h
  • ITBT_ROOTPORT_CONFIG : PeiITbtGenericStructure.h

- j -

  • JHI_CLOSE_SESSION : JhiProtocol.h
  • JHI_CREATE_SESSION : JhiProtocol.h
  • JHI_GET_APPLET_PROPERTY : JhiProtocol.h
  • JHI_GET_SESSION_INFO : JhiProtocol.h
  • JHI_GET_SESSIONS_COUNT : JhiProtocol.h
  • JHI_GET_VERSION_INFO : JhiProtocol.h
  • JHI_INITIALIZE : JhiProtocol.h
  • JHI_INSTALL_CONTENT : JhiProtocol.h
  • JHI_INSTALL_FILE : JhiProtocol.h
  • JHI_SEND_ADN_RECEIVE : JhiProtocol.h
  • JHI_UNINIT : JhiProtocol.h
  • JHI_UNINSTALL : JhiProtocol.h

- m -

  • ME_GET_RESET_TYPE : MePlatformGetResetType.h
  • ME_PLATFORM_GET_RESET_TYPE_PROTOCOL : MePlatformGetResetType.h
  • ME_POLICY_PROTOCOL : MePolicy.h
  • ME_REPORT_ERROR : MeDxeConfig.h
  • ME_UPDATE_SMBIOS : MeSmbiosUpdateProtocol.h
  • MEBX_API_ENTRY_POINT : MebxProtocol.h
  • MEBX_CLEAR_SCREEN : MebxDisplayProtocol.h
  • MEBX_CONFIGURE_SCREEN : MebxDisplayProtocol.h
  • MEBX_DISPLAY_ERROR : MebxDisplayProtocol.h
  • MEBX_DISPLAY_IMAGE : MebxDisplayProtocol.h
  • MEBX_DISPLAY_PROTOCOL : MebxDisplayProtocol.h
  • MEBX_DISPLAY_TEXT : MebxDisplayProtocol.h
  • MEBX_GET_SCREEN_RESOLUTION : MebxDisplayProtocol.h
  • MEBX_GET_USER_INPUT : MebxDisplayProtocol.h
  • MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING : MemoryDxeConfig.h
  • MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING : MemoryDxeConfig.h

- o -

  • OC_MAILBOX_FULL : CpuMailboxLib.h
  • OC_MAILBOX_INTERFACE : CpuMailboxLib.h
  • ONE_CLICK_RECOVERY_CAPABILITIES : OneClickRecoveryProtocol.h
  • ONE_CLICK_RECOVERY_ENTRY : OneClickRecoveryProtocol.h
  • ONE_CLICK_RECOVERY_SAVE_UEFI_BOOT_OPTION : OneClickRecoveryProtocol.h

- p -

  • PCH_ACPI_SMI_DISPATCH_CALLBACK : PchAcpiSmiDispatch.h
  • PCH_ACPI_SMI_DISPATCH_REGISTER : PchAcpiSmiDispatch.h
  • PCH_ACPI_SMI_DISPATCH_UNREGISTER : PchAcpiSmiDispatch.h
  • PCH_ESPI_SMI_DISPATCH_CALLBACK : PchEspiSmiDispatch.h
  • PCH_ESPI_SMI_REGISTER : PchEspiSmiDispatch.h
  • PCH_ESPI_SMI_UNREGISTER : PchEspiSmiDispatch.h
  • PCH_PCIE_SMI_DISPATCH_UNREGISTER : PchPcieSmiDispatch.h
  • PCH_PCIE_SMI_RP_DISPATCH_CALLBACK : PchPcieSmiDispatch.h
  • PCH_PCIE_SMI_RP_DISPATCH_REGISTER : PchPcieSmiDispatch.h
  • PCH_PREMEM_POLICY : PchPreMemPolicyCommon.h
  • PCH_SMI_DISPATCH_CALLBACK : PchSmiDispatch.h
  • PCH_SMI_DISPATCH_REGISTER : PchSmiDispatch.h
  • PCH_SMI_DISPATCH_UNREGISTER : PchSmiDispatch.h
  • PCH_SMM_IO_TRAP_CONTROL_FUNCTION : PchSmmIoTrapControl.h
  • PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION : PchSmmPeriodicTimerControl.h
  • PCH_SPI_FLASH_ERASE : Protocol/Spi.h
  • PCH_SPI_FLASH_READ : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_JEDEC_ID : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_SFDP : Protocol/Spi.h
  • PCH_SPI_FLASH_READ_STATUS : Protocol/Spi.h
  • PCH_SPI_FLASH_WRITE : Protocol/Spi.h
  • PCH_SPI_FLASH_WRITE_STATUS : Protocol/Spi.h
  • PCH_SPI_GET_REGION_ADDRESS : Protocol/Spi.h
  • PCH_SPI_PPI : Ppi/Spi.h
  • PCH_SPI_READ_CPU_SOFTSTRAP : Protocol/Spi.h
  • PCH_SPI_READ_PCH_SOFTSTRAP : Protocol/Spi.h
  • PCH_TCO_SMI_DISPATCH_CALLBACK : PchTcoSmiDispatch.h
  • PCH_TCO_SMI_DISPATCH_REGISTER : PchTcoSmiDispatch.h
  • PCH_TCO_SMI_DISPATCH_UNREGISTER : PchTcoSmiDispatch.h
  • PCODE_MAILBOX_FULL : CpuMailboxLib.h
  • PCODE_MAILBOX_INTERFACE : CpuMailboxLib.h
  • PEI_ITBT_CONFIG : PeiITbtConfig.h
  • PEI_POLICY_INIT : PeiSiDefaultPolicy.h
  • PEI_PREMEM_POLICY_INIT : PeiPreMemSiDefaultPolicy.h
  • PEI_SMM_ACTIVATE : SmmControl.h
  • PEI_SMM_DEACTIVATE : SmmControl.h
  • PLATFORM_ME_HOOK_PRE_GLOBAL_RESET : PlatformMeHook.h
  • PLATFORM_ME_HOOK_PROTOCOL : PlatformMeHook.h
  • PLATFORM_SEND_EC_COMMAND : BiosGuardConfig.h
  • PPM_CUSTOM_CTDP_TABLE : CpuPowerMgmtCustomConfig.h

- s -

  • SA_CHANGE_MARGIN : MemoryConfig.h
  • SA_CHANNEL_EXIST : MemoryConfig.h
  • SA_CHECKPOINT : MemoryConfig.h
  • SA_CPU_MAILBOX_READ : MemoryConfig.h
  • SA_CPU_MAILBOX_WRITE : MemoryConfig.h
  • SA_DEBUG_HOOK : MemoryConfig.h
  • SA_DEBUG_PRINT : MemoryConfig.h
  • SA_DELAY_NS : MemoryConfig.h
  • SA_DIV_U64_U64 : MemoryConfig.h
  • SA_GET_CPU_TIME : MemoryConfig.h
  • SA_GET_MEMORY_VDD : MemoryConfig.h
  • SA_GET_PCI_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_PCIE_DEVICE_ADDRESS : MemoryConfig.h
  • SA_GET_RANDOM_NUMBER : MemoryConfig.h
  • SA_GET_RTC_CMOS : MemoryConfig.h
  • SA_GET_RTC_TIME : MemoryConfig.h
  • SA_GET_SPD_DATA : MemoryConfig.h
  • SA_IO_READ_16 : MemoryConfig.h
  • SA_IO_READ_32 : MemoryConfig.h
  • SA_IO_READ_8 : MemoryConfig.h
  • SA_IO_WRITE_16 : MemoryConfig.h
  • SA_IO_WRITE_32 : MemoryConfig.h
  • SA_IO_WRITE_8 : MemoryConfig.h
  • SA_LEFT_SHIFT_64 : MemoryConfig.h
  • SA_MEMORY_COPY : MemoryConfig.h
  • SA_MEMORY_SET_BYTE : MemoryConfig.h
  • SA_MEMORY_SET_DWORD : MemoryConfig.h
  • SA_MEMORY_SET_WORD : MemoryConfig.h
  • SA_MMIO_READ_16 : MemoryConfig.h
  • SA_MMIO_READ_32 : MemoryConfig.h
  • SA_MMIO_READ_64 : MemoryConfig.h
  • SA_MMIO_READ_8 : MemoryConfig.h
  • SA_MMIO_WRITE_16 : MemoryConfig.h
  • SA_MMIO_WRITE_32 : MemoryConfig.h
  • SA_MMIO_WRITE_64 : MemoryConfig.h
  • SA_MMIO_WRITE_8 : MemoryConfig.h
  • SA_MRC_DRAM_RESET : MemoryConfig.h
  • SA_MRC_RETURN_FROM_SMC : MemoryConfig.h
  • SA_MSR_READ_64 : MemoryConfig.h
  • SA_MSR_WRITE_64 : MemoryConfig.h
  • SA_MULT_U64_U32 : MemoryConfig.h
  • SA_PRINTF : MemoryConfig.h
  • SA_RIGHT_SHIFT_64 : MemoryConfig.h
  • SA_SET_MEMORY_PMIC_VOLTAGE : MemoryConfig.h
  • SA_SET_MEMORY_VDD : MemoryConfig.h
  • SA_SHIFT_PI_COMMAND_TRAIN : MemoryConfig.h
  • SA_SIGN_EXTEND : MemoryConfig.h
  • SA_SMBUS_READ_16 : MemoryConfig.h
  • SA_SMBUS_READ_8 : MemoryConfig.h
  • SA_SMBUS_WRITE_16 : MemoryConfig.h
  • SA_SMBUS_WRITE_8 : MemoryConfig.h
  • SA_UPDATE_VREF : MemoryConfig.h
  • SET_MEBX_DATA : MebxConfigProtocol.h
  • SMM_CONFIG_IO_BITMAP : SmmResourceConfigProtocol.h
  • SMM_CONFIG_MSR_BITMAP : SmmResourceConfigProtocol.h
  • SMM_INSTALL_IO_BITMAP : SmmResourceConfigProtocol.h
  • SMM_INSTALL_MSR_BITMAP : SmmResourceConfigProtocol.h

- t -

  • TXT_INFO_DATA : TxtInfoHob.h
  • TXT_INFO_HOB : TxtInfoHob.h

- v -

  • VTD_ENABLE_DMA_BUFFER : VtdConfig.h

- w -

  • WDT_ALLOW_KNOWN_RESET : Protocol/Wdt.h
  • WDT_CHECK_STATUS : Protocol/Wdt.h
  • WDT_DISABLE : Protocol/Wdt.h
  • WDT_PPI : Ppi/Wdt.h
  • WDT_RELOAD_AND_START : Protocol/Wdt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- a -

  • AMT_CONTROL_MODE : AmthiMsgs.h
  • AMT_ERROR_MSG_ID : AmtConfig.h
  • AMT_MEBX_STATE : AmthiMsgs.h
  • AMT_MEBX_USER_INPUT : AmthiMsgs.h
  • AMT_STATUS : AmthiMsgs.h
  • AMTHI_COMMAND : AmthiMsgs.h
  • AMTHI_PROVISION_MODE : AmthiMsgs.h

- b -

  • BIOSGUARD_ATTRIBUTES : BiosGuard.h

- c -

  • C_STATE_TIME_UNIT : CpuPowerMgmtTestConfig.h
  • CFG_EOP_STATE : AmthiMsgs.h
  • CFG_MEBX_PWD_CHANGE_POLICY : AmthiMsgs.h
  • CFG_UNPROVISIONING_STATE : AmthiMsgs.h
  • CNVI_MODE : CnviConfig.h
  • CPU_GENERATION : CpuRegs.h
  • CPU_PCIE_ASPM_CONTROL : CpuPcieConfig.h
  • CPU_PCIE_EQ_METHOD : CpuPcieConfig.h
  • CPU_PCIE_L1SUBSTATES_CONTROL : CpuPcieConfig.h
  • CPU_SKU : CpuRegs.h
  • CUSTOM_POWER_UNIT : CpuPowerMgmtTestConfig.h

- d -

  • DMI_ASPM : CpuDmiPreMemConfig.h

- e -

  • EC_COMMAND_TYPE : BiosGuardConfig.h

- f -

  • FIA_INDEX : FiaAccessLib.h
  • FIVR_RAIL_SX_STATE : FivrConfig.h
  • FLASH_REGION_TYPE : Protocol/Spi.h

- g -

  • GPIO_DIRECTION : GpioConfig.h
  • GPIO_ELECTRICAL_CONFIG : GpioConfig.h
  • GPIO_HARDWARE_DEFAULT : GpioConfig.h
  • GPIO_HOSTSW_OWN : GpioConfig.h
  • GPIO_INT_CONFIG : GpioConfig.h
  • GPIO_LOCK_CONFIG : GpioConfig.h
  • GPIO_OTHER_CONFIG : GpioConfig.h
  • GPIO_OUTPUT_STATE : GpioConfig.h
  • GPIO_PAD_MODE : GpioConfig.h
  • GPIO_PAD_OWN : GpioLib.h
  • GPIO_RESET_CONFIG : GpioConfig.h
  • GPIO_SUPPORT : HybridGraphicsConfig.h

- h -

  • HECI_API_VERSION : MeUtilsLib.h
  • HWA_TABLE_TYPE_INDEX : DxeMeLib.h

- i -

  • ICC_COMMAND_ID : IccMsgs.h
  • ICC_PCIE_CONTROLLER_SOFTSTRAP_OVERRIDE : IccMsgs.h
  • IO_TRAP_EX_DISPATCH_TYPE : IoTrapExDispatch.h

- l -

  • LAN_INTERFACE : AmthiMsgs.h
  • LOCAL_FW_UPDATE : MkhiMsgs.h

- m -

  • MAX_PKG_C_STATE : CpuPowerMgmtTestConfig.h
  • MBP_ITEM_FLAGS : MeBiosPayloadData.h
  • ME_DEVICE : MeChipsetLib.h
  • ME_ERROR_MSG_ID : MeDxeConfig.h
  • ME_EWL_SEVERITY : MeEwlLib.h
  • ME_FVI_INDEX : SiFvi.h
  • ME_IMAGE_TYPE : MkhiMsgs.h
  • ME_PWD_STATUS : MkhiMsgs.h
  • ME_SPECIAL_RESET_TYPES : MePlatformGetResetType.h
  • ME_TYPE : MeTypeLib.h
  • ME_UNCONFIG_ON_RTC_CLEAR_STATUS : MkhiMsgs.h
  • MEBX_MSG_ID : MebxDisplayProtocol.h
  • MFT_KEY_USAGE : MkhiMsgs.h
  • MRC_BOOT_MODE : MemInfoHob.h

- o -

  • OPTIN_POLICY_BITMAP : AmthiMsgs.h

- p -

  • PCH_INT_PIN : InterruptConfig.h
  • PCH_PCIE_ASPM_CONTROL : PchPcieRpConfig.h
  • PCH_PCIE_CLOCK_USAGE : PchPcieRpConfig.h
  • PCH_PCIE_L1SUBSTATES_CONTROL : PchPcieRpConfig.h
  • PCH_RESERVED_PAGE_ROUTE : PchGeneralConfig.h
  • PCH_SLP_S4_MIN_ASSERT : PmConfig.h
  • PCIE_BIFURCATION_CONFIG : PchPcieRpLib.h
  • PCIE_COMBINED_RPINDEX : PchPcieSmiDispatch.h
  • PCIE_FORM_FACTOR : PcieConfig.h
  • PCIE_LINK_EQ_METHOD : PcieConfig.h
  • PCIE_LINK_EQ_MODE : PcieConfig.h
  • PLAT_ID_FEATURE : UpidMsgs.h
  • PLATFORM_BRAND : MkhiMsgs.h
  • PLATFORM_TARGET_USAGE_TYPE : MkhiMsgs.h
  • PPM_IRM_SETTING : CpuPowerMgmtTestConfig.h
  • PROVISIONING_TLS_MODE : AmthiMsgs.h
  • PT_PROVISIONING_STATE : AmthiMsgs.h

- q -

  • QUERY_TYPE : AsfMsgs.h

- r -

  • RESPONSE_CODE : AsfMsgs.h

- s -

  • SA_SPD : MemoryConfig.h
  • SERIAL_IO_CS_POLARITY : SerialIoDevices.h
  • SERIAL_IO_I2C_MODE : SerialIoDevices.h
  • SERIAL_IO_SPI_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_MODE : SerialIoDevices.h
  • SERIAL_IO_UART_PG : SerialIoDevices.h
  • SKU_TYPE : MkhiMsgs.h
  • SPD_BOOT_MODE : MemoryConfig.h
  • SPI_COMPONENT_SIZE : BiosGuard.h
  • STREAMING_TRACE_SINK : BupMsgs.h

- t -

  • TBT_BOOT_MODE : PeiTbtTaskDispatchLib.h
  • THC_MODE : ThcConfig.h
  • THC_PORT_ASSIGNMENT : ThcConfig.h
  • TPM_TYPE : BootGuardLibVer1.h
  • TRACE_BUFFER_SIZE : TraceHubConfig.h
  • TRACE_HUB_ENABLE_MODE : TraceHubConfig.h

- u -

  • UPID_COMMON_FEATURE : UpidMsgs.h
  • UPID_FEATURE : UpidMsgs.h
  • UPID_STATUS : UpidMsgs.h

- v -

  • VGPIO_CS_CONFIG : GpioConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- b -

  • bmCold : MemInfoHob.h
  • bmFast : MemInfoHob.h
  • bmS3 : MemInfoHob.h
  • bmWarm : MemInfoHob.h

- c -

  • CpuPcieEqDefault : CpuPcieConfig.h
  • CpuPcieEqHardware : CpuPcieConfig.h
  • CpuPcieEqStaticCoeff : CpuPcieConfig.h
  • CpuRpIndex0 : PchPcieSmiDispatch.h
  • CUSTOM_PROFILE : MemoryConfig.h

- d -

  • DEFAULT_SPD : MemoryConfig.h
  • DisableState : MkhiMsgs.h
  • dTpm12 : BootGuardLibVer1.h
  • dTpm20 : BootGuardLibVer1.h

- e -

  • EnableState : MkhiMsgs.h
  • EnumMebx : SiFvi.h
  • EnumMeFw : SiFvi.h
  • EnumMeRc : SiFvi.h

- g -

  • GpioDirDefault : GpioConfig.h
  • GpioDirIn : GpioConfig.h
  • GpioDirInInv : GpioConfig.h
  • GpioDirInInvOut : GpioConfig.h
  • GpioDirInOut : GpioConfig.h
  • GpioDirNone : GpioConfig.h
  • GpioDirOut : GpioConfig.h
  • GpioDswReset : GpioConfig.h
  • GpioGlobalReset : GpioConfig.h
  • GpioHardwareDefault : GpioConfig.h
  • GpioHostDeepReset : GpioConfig.h
  • GpioHostOwnAcpi : GpioConfig.h
  • GpioHostOwnDefault : GpioConfig.h
  • GpioHostOwnGpio : GpioConfig.h
  • GpioIntApic : GpioConfig.h
  • GpioIntBothEdge : GpioConfig.h
  • GpioIntDefault : GpioConfig.h
  • GpioIntDis : GpioConfig.h
  • GpioIntEdge : GpioConfig.h
  • GpioIntLevel : GpioConfig.h
  • GpioIntLvlEdgDis : GpioConfig.h
  • GpioIntNmi : GpioConfig.h
  • GpioIntSci : GpioConfig.h
  • GpioIntSmi : GpioConfig.h
  • GpioLockDefault : GpioConfig.h
  • GpioLockTxLockCfgUnLock : GpioConfig.h
  • GpioLockTxUnLockCfgLock : GpioConfig.h
  • GpioOutDefault : GpioConfig.h
  • GpioOutHigh : GpioConfig.h
  • GpioOutLow : GpioConfig.h
  • GpioOutputStateUnlock : GpioConfig.h
  • GpioPadConfigLock : GpioConfig.h
  • GpioPadConfigUnlock : GpioConfig.h
  • GpioPadLock : GpioConfig.h
  • GpioPadUnlock : GpioConfig.h
  • GpioPlatformReset : GpioConfig.h
  • GpioResetDefault : GpioConfig.h
  • GpioResumeReset : GpioConfig.h
  • GpioRxRaw1Default : GpioConfig.h
  • GpioRxRaw1Dis : GpioConfig.h
  • GpioRxRaw1En : GpioConfig.h
  • GpioTermDefault : GpioConfig.h
  • GpioTermNative : GpioConfig.h
  • GpioTermNone : GpioConfig.h
  • GpioTermWpd20K : GpioConfig.h
  • GpioTermWpd5K : GpioConfig.h
  • GpioTermWpu1K : GpioConfig.h
  • GpioTermWpu1K2K : GpioConfig.h
  • GpioTermWpu20K : GpioConfig.h
  • GpioTermWpu2K : GpioConfig.h
  • GpioTermWpu5K : GpioConfig.h

- h -

  • HidOverSpi : ThcConfig.h

- i -

  • ICC_READ_FROM_MPHY_CMD : IccMsgs.h

- m -

  • MbpItemFlagRuntime : MeBiosPayloadData.h
  • MbpItemFlagSensitive : MeBiosPayloadData.h
  • MbpItemFlagStoreToNvm : MeBiosPayloadData.h
  • ME_PWDSTS_FAILURE : MkhiMsgs.h
  • ME_PWDSTS_INVALID_NEW_PWD : MkhiMsgs.h
  • ME_PWDSTS_INVALID_PWD : MkhiMsgs.h
  • ME_PWDSTS_OPERATION_NOT_ALLOWED : MkhiMsgs.h
  • ME_PWDSTS_OUT_OF_RESOURCES : MkhiMsgs.h
  • ME_PWDSTS_PWD_SUCCESS : MkhiMsgs.h
  • MFT_KEY_USAGE_INDEX_CSE_RBE_MANIFEST : MkhiMsgs.h
  • MFT_KEY_USAGE_INDEX_UNDEFINED_MANIFEST : MkhiMsgs.h
  • MrcBootModeDelim : MemInfoHob.h
  • MrcBootModeMax : MemInfoHob.h

- p -

  • PchClockUsageCpuPcie0 : PchPcieRpConfig.h
  • PchClockUsageUnspecified : PchPcieRpConfig.h
  • PchNoInt : InterruptConfig.h
  • PchReservedPageToLpc : PchGeneralConfig.h
  • PchReservedPageToPcie : PchGeneralConfig.h
  • PchSlpS4PchTime : PmConfig.h
  • PcieLinkEqCoefficientMode : PcieConfig.h
  • PcieLinkEqPresetMode : PcieConfig.h
  • PcieLinkFixedEq : PcieConfig.h
  • PcieLinkHardwareEq : PcieConfig.h
  • PowerUnit125MilliWatts : CpuPowerMgmtTestConfig.h
  • PowerUnitWatts : CpuPowerMgmtTestConfig.h
  • Ptt : BootGuardLibVer1.h

- s -

  • SerialIoUartPgAuto : SerialIoDevices.h
  • SerialIoUartPgDisabled : SerialIoDevices.h
  • SerialIoUartPgEnabled : SerialIoDevices.h
  • SpdBootModeMax : MemoryConfig.h
  • SpdCold : MemoryConfig.h
  • SpdFast : MemoryConfig.h
  • SPDProfileMax : MemoryConfig.h
  • SpdS3 : MemoryConfig.h
  • SpdWarm : MemoryConfig.h

- t -

  • TBT_ALL : PeiTbtTaskDispatchLib.h
  • TBT_NORMAL : PeiTbtTaskDispatchLib.h
  • TBT_NULL : PeiTbtTaskDispatchLib.h
  • TBT_S3 : PeiTbtTaskDispatchLib.h
  • TBT_S4 : PeiTbtTaskDispatchLib.h
  • Thc : ThcConfig.h
  • ThcAssignmentNone : ThcConfig.h
  • ThcAssignmentThc0 : ThcConfig.h
  • ThcAssignmentThc1 : ThcConfig.h
  • TpmNone : BootGuardLibVer1.h
  • TpmTypeMax : BootGuardLibVer1.h

- v -

  • VgpioCs0 : GpioConfig.h
  • VgpioCs1 : GpioConfig.h

- x -

  • XMP_PROFILE_1 : MemoryConfig.h
  • XMP_PROFILE_2 : MemoryConfig.h
  • XMP_PROFILE_3 : MemoryConfig.h
  • XMP_USER_PROFILE_4 : MemoryConfig.h
  • XMP_USER_PROFILE_5 : MemoryConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- a -

  • AC_DC_LOADLINE_MAX : VoltageRegulatorCommands.h
  • ALIGN_256KB : BiosGuard.h
  • ALIGNMENT_IN_PAGES : BiosGuard.h
  • AMT_POLICY_PROTOCOL_REVISION : AmtPolicy.h
  • AMT_READY_TO_BOOT_PROTOCOL_REVISION : AmtReadyToBoot.h
  • AMT_SAVE_MEBX_PROTOCOL_REVISION : AmtSaveMebxProtocol.h
  • APINIT_ADDR : Txt.h
  • APPID_BIN_LENGTH : JhiProtocol.h
  • APPID_STR_LENGTH : JhiProtocol.h
  • ARB_SVN_COMMIT_ALL : MkhiMsgs.h
  • ASF_BOOT_OPTIONS_PRESENT : AsfProtocol.h
  • ASF_ENTITY_INSTANCE_UNSPECIFIED : IndustryStandardAsf.h
  • ASF_ENTITY_INTEL_AMT : IntelAsfExtensions.h
  • ASF_ENTITY_UNSPECIFIED : IndustryStandardAsf.h
  • ASF_EVENT_OFFSET_ENTITY_PRESENT : IndustryStandardAsf.h
  • ASF_EVENT_OFFSET_ONE_CLICK_RECOVERY_ERROR : IntelAsfExtensions.h
  • ASF_EVENT_OFFSET_REMOTE_SECURE_ERASE_FW_ERROR : IntelAsfExtensions.h
  • ASF_EVENT_SENSOR_TYPE_TEMPERATURE : IndustryStandardAsf.h
  • ASF_EVENT_SEVERITY_CODE_MONITOR : IndustryStandardAsf.h
  • ASF_EVENT_SOURCE_TYPE_PLATFORM_FIRMWARE : IndustryStandardAsf.h
  • ASF_EVENT_TYPE_THRESHOLD_BASED : IndustryStandardAsf.h
  • ASF_FE_AMTBX_FAILURE : IntelAsfExtensions.h
  • ASF_FE_EVENT_DATA1 : IndustryStandardAsf.h
  • ASF_FP_AMTBX_INIT : IntelAsfExtensions.h
  • ASF_FP_EVENT_DATA1 : IndustryStandardAsf.h
  • ASF_INDUSTRY_CONVERTED_IANA : AsfProtocol.h
  • ASF_INDUSTRY_IANA : AsfProtocol.h
  • ASF_INFO_TYPE : IndustryStandardAsf.h
  • ASF_INTEL_CONVERTED_IANA : AsfProtocol.h
  • ASF_INTEL_OEM_CMD : AsfProtocol.h
  • ASF_MESSAGE_COMMAND_LAN : IntelAsfExtensions.h
  • ASF_MESSAGE_COMMAND_SENSOR_DEVICE_SYSTEM_STATE : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_CLEAR_BOOT_OPT : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_GET_EVENT_DATA : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_GET_RSE_PASSWORD : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_KVM_QUERY : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_SET_ACTIVE_LAN : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_SET_ALERT_CONFIG : IndustryStandardAsf.h
  • ASF_MESSAGE_SUBCOMMAND_SET_MAC_PASSTHROUGH : IntelAsfExtensions.h
  • ASF_MESSAGE_SUBCOMMAND_START_WATCH_DOG_TIMER : IndustryStandardAsf.h
  • ASF_OCR_EVENT_DATA3_BOOT_PARAMETER_RECEIVED : IntelAsfExtensions.h
  • ASF_OCR_EVENT_DATA3_SUCCESS : IntelAsfExtensions.h
  • ASF_RBS_BIOS_STATUS_SUCCESS : IntelAsfExtensions.h
  • ASF_RMCP_BOOT_OPTION_SUCCESS : IndustryStandardAsf.h
  • ASF_RPE_EVENT_OFFSET_PROGRESS : IntelAsfExtensions.h
  • ASF_SENSOR_DEVICE : IndustryStandardAsf.h
  • ASF_SENSOR_NUMBER : IndustryStandardAsf.h
  • ASF_START_BIOS_WDT : AsfMsgs.h
  • ASF_WD_EVENT_DATA1 : IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- b -

  • B_ACPI_IO_DEVTRAP_STS_D12_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D6_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D7_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D8_TRP_STS : PmcRegs.h
  • B_ACPI_IO_DEVTRAP_STS_D9_TRP_STS : PmcRegs.h
  • B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN : PmcRegs.h
  • B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS : PmcRegs.h
  • B_ACPI_IO_GPE_CTRL_SWGPE_CTRL : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_CTL_LCK : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_FORCE_ALL : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_ICCSURV_STS : PmcRegs.h
  • B_ACPI_IO_OC_WDT_CTL_OC_WDT_NO_ICCSURV_STS : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SCI_EN : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SLP_EN : PmcRegs.h
  • B_ACPI_IO_PM1_CNT_SLP_TYP : PmcRegs.h
  • B_ACPI_IO_PM1_TMR_TMR_VAL : PmcRegs.h
  • B_ACPI_IO_SMI_EN_BIOS_RLS : PmcRegs.h
  • B_ACPI_IO_SMI_EN_EOS : PmcRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_2_LTR_MEC_EN : CnviRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_CAP_2_LTR_MEC_SUP : CnviRegs.h
  • B_CNVI_CFG_WIFI_GIO_DEV_CTRL_FLR : CnviRegs.h
  • B_CNVI_CFG_WIFI_PMCSR_PS : CnviRegs.h
  • B_CNVI_PCR_WIFI_WIDGET_CONTROL_MEM_INT : CnviRegs.h
  • B_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1_RTCO : UsbRegs.h
  • B_CRB_CONTROL_REQ_COMMAND_READY : PttPtpRegs.h
  • B_CRB_CONTROL_REQ_GO_IDLE : PttPtpRegs.h
  • B_CRB_CONTROL_START : PttPtpRegs.h
  • B_CRB_CONTROL_STS_TPM_IDLE : PttPtpRegs.h
  • B_CRB_CONTROL_STS_TPM_STATUS : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_RELINQUISH : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_REQUEST_ACCESS : PttPtpRegs.h
  • B_CRB_LOCALITY_CTL_SEIZE : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_REGISTER_VALID : PttPtpRegs.h
  • B_CRB_LOCALITY_STATE_TPM_ESTABLISHED : PttPtpRegs.h
  • B_CRB_LOCALITY_STS_BEEN_SEIZED : PttPtpRegs.h
  • B_CRB_LOCALITY_STS_GRANTED : PttPtpRegs.h
  • B_ESPI_CFG_PCBC_BILD : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWPDS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWRE : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_BWRS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_EISS : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_ESPI_EN : PchRegsLpc.h
  • B_ESPI_CFG_PCBC_LE : PchRegsLpc.h
  • B_ESPI_PCR_CFG_VAL_ESPI_EN : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SAFBLK : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SLV0_FCFEE : PchRegsLpc.h
  • B_ESPI_PCR_FCERR_SLV0_FCNFEE : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_LFET1E : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_LFET1S : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV0_SLCRR : PchRegsLpc.h
  • B_ESPI_PCR_LNKERR_SLV1_LFET1E : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCFEE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCNFEE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCNFES : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCRMTARE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCURD : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_PCURRE : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_SLV0_PCURD : PchRegsLpc.h
  • B_ESPI_PCR_PCERR_SLV0_PMMA : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT : PchRegsLpc.h
  • B_ESPI_PCR_SLV_CFG_REG_CTL_SID : PchRegsLpc.h
  • B_ESPI_PCR_SOFTSTRAPS_CS1_EN : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_SLV0_VWHC10OE : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_VWFEE : PchRegsLpc.h
  • B_ESPI_PCR_VWERR_VWNFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XFES : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XNFEE : PchRegsLpc.h
  • B_ESPI_PCR_XERR_XNFES : PchRegsLpc.h
  • B_ESPI_SLAVE_BME : PchRegsLpc.h
  • B_FLASH_FDBAR_CPUSL : FlashRegs.h
  • B_FLASH_FDBAR_FCBA : FlashRegs.h
  • B_FLASH_FDBAR_FCPUSBA : FlashRegs.h
  • B_FLASH_FDBAR_FMBA : FlashRegs.h
  • B_FLASH_FDBAR_FPSBA : FlashRegs.h
  • B_FLASH_FDBAR_FRBA : FlashRegs.h
  • B_FLASH_FDBAR_NC : FlashRegs.h
  • B_FLASH_FDBAR_NM : FlashRegs.h
  • B_FLASH_FDBAR_NR : FlashRegs.h
  • B_FLASH_FDBAR_PCHSL : FlashRegs.h
  • B_FLASH_FLCOMP_COMP0_MASK : FlashRegs.h
  • B_FLASH_FLCOMP_COMP1_MASK : FlashRegs.h
  • B_FLASH_FLCOMP_FR_SUP : FlashRegs.h
  • B_FLASH_FLCOMP_FRCF_FREQ : FlashRegs.h
  • B_FLASH_FLCOMP_RIDS_FREQ : FlashRegs.h
  • B_FLASH_FLCOMP_WE_FREQ : FlashRegs.h
  • B_FLASH_STRAP_DSCR_0_PTT_SUPP : FlashRegs.h
  • B_FLASH_STRAP_MMP0 : FlashRegs.h
  • B_FLASH_STRAP_SFDP_DIORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_DORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_QIORE : FlashRegs.h
  • B_FLASH_STRAP_SFDP_QORE : FlashRegs.h
  • B_FLASH_UMAP1_MDTBA : FlashRegs.h
  • B_FLASH_UMAP1_VTBA : FlashRegs.h
  • B_FLASH_UMAP1_VTL : FlashRegs.h
  • B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_SOURCE_MASK : GpioConfig.h
  • B_GPIO_INT_CONFIG_INT_TYPE_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK : GpioConfig.h
  • B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK : GpioConfig.h
  • B_GPIO_OTHER_CONFIG_RXRAW_MASK : GpioConfig.h
  • B_LPC_CFG_BC_BBS : PchRegsLpc.h
  • B_LPC_CFG_BC_BILD : PchRegsLpc.h
  • B_LPC_CFG_BC_EISS : PchRegsLpc.h
  • B_LPC_CFG_BC_LE : PchRegsLpc.h
  • B_LPC_CFG_BC_TS : PchRegsLpc.h
  • B_LPC_CFG_BC_WPD : PchRegsLpc.h
  • B_LPC_CFG_FVEC3_DCMI_CAP : PchRegsLpc.h
  • B_LPC_CFG_FVEC3_NM_CAP : PchRegsLpc.h
  • B_LPC_CFG_IOE_CAE : PchRegsLpc.h
  • B_LPC_CFG_IOE_CBE : PchRegsLpc.h
  • B_LPC_CFG_IOE_FDE : PchRegsLpc.h
  • B_LPC_CFG_IOE_HGE : PchRegsLpc.h
  • B_LPC_CFG_IOE_KE : PchRegsLpc.h
  • B_LPC_CFG_IOE_LGE : PchRegsLpc.h
  • B_LPC_CFG_IOE_ME1 : PchRegsLpc.h
  • B_LPC_CFG_IOE_ME2 : PchRegsLpc.h
  • B_LPC_CFG_IOE_PPE : PchRegsLpc.h
  • B_LPC_CFG_IOE_SE : PchRegsLpc.h
  • B_PCH_DMI14_PCR_DMIC_DMICGEN : PchDmi14Regs.h
  • B_PCH_DMI14_PCR_DMIC_SRL : PchDmi14Regs.h
  • B_PCH_DMI14_PCR_IPCS_PSS : PchDmi14Regs.h
  • B_PCH_DMI15_PCR_BBCLKREQEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CCFG_DCGEISMA : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_DLDHB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L0SPFCUF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L1PL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_L1RC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_MRSCDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_PSS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_TCUAPF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL1_UTPB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL2_CPGEXLCWDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CTRL2_DLDRSP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_CWBCTL_CWBE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_EQCFG1_RTLEPCEB : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_EQCFG1_RTPCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_IOSFSBCS_SCPTCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_IOSFSBCS_SIID : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TPOSTCO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L0246TPRECO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TCOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TPOSTCO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_L1357TPRECO : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCLKREQEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL2_TLS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_ASPM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_ES : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_LCTL_RL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_CAM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_GEN2PLLC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_GEN3PLLC : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_ORCE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_PLLWAIT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_RUD : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC2_TLPF : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC_FCP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_MPC_SRL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_HAE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_PMCRE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCE_SE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_CROAOE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_CROAOV : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIECFG2_LBWSSTE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEDBG_SPCE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_DETSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_DISSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_FDCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L1SCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L1SPHYDLPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_L23RDYSCPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL2_PHYCLPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_DLSULDLSD : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_DLSULPPGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_IPACPE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PCIEPMECTL_IPIEP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_PXPG2PLLOFFEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_PXPG3PLLOFFEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_TDFT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL2_TXCFGCHGWAIT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL3_SQDIRCTRL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL3_SQDIROVREN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PHYCTL4_SQDIS : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PSSSGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PTOCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PWRCTL_DBUPI : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_PWRCTL_RPSEWL : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPDBCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPDLCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_RPPGEN_SEOSCGE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_SRDBCGEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_CM : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_PT : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UEM_URE : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS0TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS1TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS2TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TS3TW : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPHWAWC_TSAWEN : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPL0246TP : PchDmi15Regs.h
  • B_PCH_DMI15_PCR_UPL1357TP : PchDmi15Regs.h
  • B_PCH_DMI_PCR_BBS : PchDmiRegs.h
  • B_PCH_DMI_PCR_BILD : PchDmiRegs.h
  • B_PCH_DMI_PCR_GPMRXDID_GPMR1DE : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_APMS : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_EL0 : PchDmiRegs.h
  • B_PCH_DMI_PCR_LCAP_EL1 : PchDmiRegs.h
  • B_PCH_DMI_PCR_RPR : PchDmiRegs.h
  • B_PCH_DMI_PCR_RPRDID : PchDmiRegs.h
  • B_PCH_DMI_PCR_TCOBASE_TCOBA : PchDmiRegs.h
  • B_PCH_DMI_PCR_UCPR_UPRE : PchDmiRegs.h
  • B_PCH_DMI_PCR_V0CTL_ID : PchDmiRegs.h
  • B_PCH_DMI_PCR_V1CTL_ID : PchDmiRegs.h
  • B_PCH_PCIE_CFG_EX_CES_BD : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_EX_CES_BT : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_EX_CES_RE : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LOCK : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR_LTRNSROVR : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_LTROVR_LTRSROVR : PchPcieRpRegs.h
  • B_PCH_PCIE_CFG_PTMECFG_IOSFMADP : PchPcieRpRegs.h
  • B_PCH_SPI_STRP_GBETSN_DIS : FlashRegs.h
  • B_PCH_SPI_STRP_THC0_DIS : FlashRegs.h
  • B_PCH_SPI_STRP_THC1_DIS : FlashRegs.h
  • B_PCI_BRIDGE_BNUM_PBN : PcieRegs.h
  • B_PCI_BRIDGE_BNUM_SBBN : PcieRegs.h
  • B_PCI_BRIDGE_BNUM_SCBN : PcieRegs.h
  • B_PCI_BRIDGE_MBL_MB : PcieRegs.h
  • B_PCI_BRIDGE_MBL_ML : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_I64B : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_I64L : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_PMB : PcieRegs.h
  • B_PCI_BRIDGE_PMBL_PML : PcieRegs.h
  • B_PCIE_DCAP2_LTRMS : PcieRegs.h
  • B_PCIE_DCAP2_OBFFS : PcieRegs.h
  • B_PCIE_DCAP2_PX10BTCS : PcieRegs.h
  • B_PCIE_DCAP2_PX10BTRS : PcieRegs.h
  • B_PCIE_DCAP_E0AL : PcieRegs.h
  • B_PCIE_DCAP_E1AL : PcieRegs.h
  • B_PCIE_DCAP_MPS : PcieRegs.h
  • B_PCIE_DCAP_RBER : PcieRegs.h
  • B_PCIE_DCTL2_AEB : PcieRegs.h
  • B_PCIE_DCTL2_CTD : PcieRegs.h
  • B_PCIE_DCTL2_CTV : PcieRegs.h
  • B_PCIE_DCTL2_LTREN : PcieRegs.h
  • B_PCIE_DCTL2_OBFFEN : PcieRegs.h
  • B_PCIE_DCTL2_PX10BTRE : PcieRegs.h
  • B_PCIE_DCTL_CEE : PcieRegs.h
  • B_PCIE_DCTL_FEE : PcieRegs.h
  • B_PCIE_DCTL_MPS : PcieRegs.h
  • B_PCIE_DCTL_NFE : PcieRegs.h
  • B_PCIE_DCTL_NS : PcieRegs.h
  • B_PCIE_DCTL_RO : PcieRegs.h
  • B_PCIE_DCTL_URE : PcieRegs.h
  • B_PCIE_DSTS_APD : PcieRegs.h
  • B_PCIE_DSTS_CED : PcieRegs.h
  • B_PCIE_DSTS_FED : PcieRegs.h
  • B_PCIE_DSTS_NFED : PcieRegs.h
  • B_PCIE_DSTS_TDP : PcieRegs.h
  • B_PCIE_DSTS_URD : PcieRegs.h
  • B_PCIE_EX_L01EC_DPL0TP : PcieRegs.h
  • B_PCIE_EX_L01EC_DPL1TP : PcieRegs.h
  • B_PCIE_EX_L01EC_UPL0TP : PcieRegs.h
  • B_PCIE_EX_L01EC_UPL1TP : PcieRegs.h
  • B_PCIE_EX_L1SCAP_AL12S : PcieRegs.h
  • B_PCIE_EX_L1SCAP_AL1SS : PcieRegs.h
  • B_PCIE_EX_L1SCAP_L1PSS : PcieRegs.h
  • B_PCIE_EX_L1SCAP_L1SSES : PcieRegs.h
  • B_PCIE_EX_L1SCAP_PPL11S : PcieRegs.h
  • B_PCIE_EX_L1SCAP_PPL12S : PcieRegs.h
  • B_PCIE_EX_L1SCTL1_L12LTRTLSV : PcieRegs.h
  • B_PCIE_EX_L1SCTL1_L12LTRTLV : PcieRegs.h
  • B_PCIE_EX_L23EC_DPL2TP : PcieRegs.h
  • B_PCIE_EX_L23EC_DPL3TP : PcieRegs.h
  • B_PCIE_EX_L23EC_UPL2TP : PcieRegs.h
  • B_PCIE_EX_L23EC_UPL3TP : PcieRegs.h
  • B_PCIE_EX_LCTL3_PE : PcieRegs.h
  • B_PCIE_EX_PTMCAP_PTMRC : PcieRegs.h
  • B_PCIE_EX_PTMCAP_PTMRSPC : PcieRegs.h
  • B_PCIE_EX_UEM_CT : PcieRegs.h
  • B_PCIE_EX_UEM_UC : PcieRegs.h
  • B_PCIE_EXCAP_CID : PcieRegs.h
  • B_PCIE_EXCAP_CV : PcieRegs.h
  • B_PCIE_EXCAP_NCO : PcieRegs.h
  • B_PCIE_LCAP_APMS : PcieRegs.h
  • B_PCIE_LCAP_ASPMOC : PcieRegs.h
  • B_PCIE_LCAP_CPM : PcieRegs.h
  • B_PCIE_LCAP_EL0 : PcieRegs.h
  • B_PCIE_LCAP_EL1 : PcieRegs.h
  • B_PCIE_LCAP_MLS : PcieRegs.h
  • B_PCIE_LCAP_MLW : PcieRegs.h
  • B_PCIE_LCTL2_SD : PcieRegs.h
  • B_PCIE_LCTL2_TLS : PcieRegs.h
  • B_PCIE_LCTL_ASPM : PcieRegs.h
  • B_PCIE_LCTL_CCC : PcieRegs.h
  • B_PCIE_LCTL_ECPM : PcieRegs.h
  • B_PCIE_LCTL_ES : PcieRegs.h
  • B_PCIE_LCTL_LD : PcieRegs.h
  • B_PCIE_LCTL_RL : PcieRegs.h
  • B_PCIE_LSTS2_CDL : PcieRegs.h
  • B_PCIE_LSTS2_EC : PcieRegs.h
  • B_PCIE_LSTS2_EQP1S : PcieRegs.h
  • B_PCIE_LSTS2_EQP2S : PcieRegs.h
  • B_PCIE_LSTS2_EQP3S : PcieRegs.h
  • B_PCIE_LSTS2_LER : PcieRegs.h
  • B_PCIE_LSTS_CLS : PcieRegs.h
  • B_PCIE_LSTS_LA : PcieRegs.h
  • B_PCIE_LSTS_LT : PcieRegs.h
  • B_PCIE_LSTS_NLW : PcieRegs.h
  • B_PCIE_LSTS_SCC : PcieRegs.h
  • B_PCIE_PMC_PMEC : PcieRegs.h
  • B_PCIE_PMC_PMES : PcieRegs.h
  • B_PCIE_PMCS_B23S : PcieRegs.h
  • B_PCIE_PMCS_BPCE : PcieRegs.h
  • B_PCIE_PMCS_NSR : PcieRegs.h
  • B_PCIE_PMCS_PMEE : PcieRegs.h
  • B_PCIE_PMCS_PMES : PcieRegs.h
  • B_PCIE_PMCS_PS : PcieRegs.h
  • B_PCIE_RCTL_PIE : PcieRegs.h
  • B_PCIE_RCTL_SCE : PcieRegs.h
  • B_PCIE_RCTL_SFE : PcieRegs.h
  • B_PCIE_RCTL_SNE : PcieRegs.h
  • B_PCIE_SLCAP_ABP : PcieRegs.h
  • B_PCIE_SLCAP_AIP : PcieRegs.h
  • B_PCIE_SLCAP_HPC : PcieRegs.h
  • B_PCIE_SLCAP_HPS : PcieRegs.h
  • B_PCIE_SLCAP_MRLSP : PcieRegs.h
  • B_PCIE_SLCAP_PCP : PcieRegs.h
  • B_PCIE_SLCAP_PIP : PcieRegs.h
  • B_PCIE_SLCAP_PSN : PcieRegs.h
  • B_PCIE_SLCAP_SLS : PcieRegs.h
  • B_PCIE_SLCAP_SLV : PcieRegs.h
  • B_PCIE_SLCTL_HPE : PcieRegs.h
  • B_PCIE_SLCTL_PDE : PcieRegs.h
  • B_PCIE_SLSTS_PDC : PcieRegs.h
  • B_PCIE_SLSTS_PDS : PcieRegs.h
  • B_PCIE_XCAP_DT : PcieRegs.h
  • B_PCIE_XCAP_SI : PcieRegs.h
  • B_PMC_CFG_ACTL_ACPI_EN : PmcRegs.h
  • B_PMC_CFG_ACTL_PWRM_EN : PmcRegs.h
  • B_PMC_CFG_ACTL_SCIS : PmcRegs.h
  • B_PMC_CFG_PWRM_BASE_MASK : PmcRegs.h
  • B_PMC_DEF_CPU_BCLK_CFG : PmcRegs.h
  • B_PMC_PWRM_ACPI_SCIS : PmcRegs.h
  • B_PMC_PWRM_ADR_CTRL_STS_ADR_RST_STS : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_FEAT_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_GPIO_SEL : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_ADR_PLT_ACK_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_EN_HPR_ADR_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_SCALE : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P1_TIMER_TOV : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_EN : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_SCALE : PmcRegs.h
  • B_PMC_PWRM_ADR_GEN_CFG_ADR_P2_TIMER_TOV : PmcRegs.h
  • B_PMC_PWRM_CFG4_PSON_SLPS0_TMR : PmcRegs.h
  • B_PMC_PWRM_CFG4_SLPS0_PSON_TMR : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_CPPM_G1_QUAL : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LT_G1_SEL : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH : PmcRegs.h
  • B_PMC_PWRM_CPPM_CG_POL1A_LTR_G1_THRESH_V2 : PmcRegs.h
  • B_PMC_PWRM_CPPM_FIVR_POL1B_TNTE_FIVR_VOLT_PRE_WAKE : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_CPPM_MPHY_QUAL : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_LT_MPHY_SEL : PmcRegs.h
  • B_PMC_PWRM_CPPM_MPG_POL1A_LTR_MPHY_THRESH : PmcRegs.h
  • B_PMC_PWRM_CRID_CRID_LK : PmcRegs.h
  • B_PMC_PWRM_CRID_RID_SEL : PmcRegs.h
  • B_PMC_PWRM_CRID_UIP_CRID_UIP : PmcRegs.h
  • B_PMC_PWRM_CS_ACRO_CRO_OVR_EN : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_CS_SD_CTL1_CS_XTAL_CTL_CFG : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN : PmcRegs.h
  • B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN : PmcRegs.h
  • B_PMC_PWRM_EN_PA_SLOW_RING2_GBETSN : PmcRegs.h
  • B_PMC_PWRM_ETR3_CF9GR : PmcRegs.h
  • B_PMC_PWRM_ETR3_CF9LOCK : PmcRegs.h
  • B_PMC_PWRM_ETR3_CWORWRE : PmcRegs.h
  • B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT : PmcRegs.h
  • B_PMC_PWRM_GBL2HOST_EN_HOST_RESET_TIMEOUT : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DISB : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_MEM_SR : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_MS4V : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK : PmcRegs.h
  • B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW0 : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW1 : PmcRegs.h
  • B_PMC_PWRM_GPIO_CFG_GPE0_DW2 : PmcRegs.h
  • B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST : PmcRegs.h
  • B_PMC_PWRM_IPC_STS_BUSY : PmcRegs.h
  • B_PMC_PWRM_IPC_STS_ERROR : PmcRegs.h
  • B_PMC_PWRM_LPM_ADEM_HOST_CTRL_EN : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_C10_QUAL_MPHYPG : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_MLSPDDGE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG3_MPLSPDDGE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI : PmcRegs.h
  • B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_DRAM_RESET_CTL : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_EN_DBG_MSG : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_PB_DIS : PmcRegs.h
  • B_PMC_PWRM_PM_CFG2_PBOP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_DSX_WLAN_PP_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_HOST_MISC_CORE_CFG_CPU_VCC_MAP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_HOST_WLAN_PP_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG3_SYS_RST_SUP : PmcRegs.h
  • B_PMC_PWRM_PM_CFG4_CPU_IOVR_RAMP_DUR : PmcRegs.h
  • B_PMC_PWRM_PM_CFG4_U2_PHY_PG_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ALLOW_24_OSC_SD : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ALLOW_USB2_CORE_PG : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_COCS : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_DBG_MODE_LOCK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ER_EN : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_ER_LOCK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_PMC_READ_DISABLE : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_RPCD_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_SAMAW_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_SSMAW_MASK : PmcRegs.h
  • B_PMC_PWRM_PM_CFG_TIMING_TPCH25 : PmcRegs.h
  • B_PMC_PWRM_PM_SYNC_MISC_CFG_PM_SYNC_LOCK : PmcRegs.h
  • B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS : PmcRegs.h
  • B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS : PmcRegs.h
  • B_PMC_PWRM_SSMC_SSMS : PmcRegs.h
  • B_PMC_PWRM_SSML_SSL : PmcRegs.h
  • B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK : PmcRegs.h
  • B_RTC_PCR_BUC_DSO : RtcRegs.h
  • B_RTC_PCR_BUC_TS : RtcRegs.h
  • B_RTC_PCR_CONF_BILD : RtcRegs.h
  • B_RTC_PCR_CONF_HPM_HW_DIS : RtcRegs.h
  • B_RTC_PCR_CONF_LCMOS_LOCK : RtcRegs.h
  • B_RTC_PCR_CONF_UCMOS_EN : RtcRegs.h
  • B_RTC_PCR_CONF_UCMOS_LOCK : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCPCICLKDCGEN : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCPGCBDCGEN : RtcRegs.h
  • B_RTC_PCR_RTCDCG_RTCROSIDEDCGEN : RtcRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC_TCSO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_CRGC_CRAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRDCGE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_CRTCGE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_ICAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_EGCR_TSCAS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_CRE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_CREL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_PLS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_PNCAIDL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GCR_RCL : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCD : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PCCS : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_GSR_PLRC : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_IOBRSC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MBRC_TT : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXCRC_RE : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXCRCC_TCSO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPBAR_TBAV : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TBIR : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXPRC_TO : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTBAR_TBAV : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TBIR : SataRegs.h
  • B_SATA_CFG_RST_PCIE_STORAGE_MXTRC_TO : SataRegs.h
  • B_SATA_MEM_AHCI_CAP2_APST : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_PMD : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SCLO : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SMPS : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SPM : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SSS : SataRegs.h
  • B_SATA_MEM_AHCI_CAP_SXS : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_ESP : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_HPCP : SataRegs.h
  • B_SATA_MEM_AHCI_PxCMD_MPSP : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_AMXC_AMXV : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC_DT : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS : SataRegs.h
  • B_SATA_MEM_RST_PCIE_STORAGE_RCR_NRS_CR1 : SataRegs.h
  • B_SATA_MEM_VS_CAP_NRMBE : SataRegs.h
  • B_SMBUS_IO_STCO : PchRegsSmbus.h
  • B_SMBUS_PCR_GC_FD : PchRegsSmbus.h
  • B_SMBUS_PCR_GC_SMBSCGE : PchRegsSmbus.h
  • B_SMBUS_PCR_PCE_HAE : PchRegsSmbus.h
  • B_SMBUS_PCR_SCTM_SSU : PchRegsSmbus.h
  • B_SMBUS_PCR_SMBTM_SMBCT : PchRegsSmbus.h
  • B_SMBUS_PCR_SMBTM_SMBDG : PchRegsSmbus.h
  • B_SMBUS_PCR_TCOCFG_IE : PchRegsSmbus.h
  • B_SMBUS_PCR_TCOCFG_IS : PchRegsSmbus.h
  • B_SPX_PCR_IMRAMBL_IAMB : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMBL_IAML : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMBL_RS3BN : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE1 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE2 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE3 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_IAE4 : PchPcieRpRegs.h
  • B_SPX_PCR_IMRAMLE_SRL : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P1D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P2D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P3D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_P4D : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP1CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP1FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP2CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP2FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP3CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP3FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP4CH : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_RP4FN : PchPcieRpRegs.h
  • B_SPX_PCR_PCD_SRL : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_CRCSEL : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEGMO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPCRC : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPME : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIEHBPPS : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIELDO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIELRO : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIERIL0O : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIESSM : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIESST : PchPcieRpRegs.h
  • B_SPX_PCR_PCIEHBP_PCIETIL0O : PchPcieRpRegs.h
  • B_USB2_PCR_PER_PORT_2_TXEMPHASISEN : UsbRegs.h
  • B_XDCI_MEM_GCTL_GHIBEREN : UsbRegs.h
  • B_XDCI_MEM_GUSB2PHYCFG_SUSPHY : UsbRegs.h
  • B_XDCI_MEM_GUSB3PIPECTL0_SUSPEN_EN : UsbRegs.h
  • B_XHCI_CFG_XHCC2_RDREQSZCTRL : UsbRegs.h
  • B_XHCI_CFG_XHCC2_WRREQSZCTRL : UsbRegs.h
  • B_XHCI_MEM_AUX_CTRL_REG3_HYST_TIMEOUT_150US : UsbRegs.h
  • B_XHCI_MEM_AUX_CTRL_REG3_HYSTERESIS_TIMEOUT : UsbRegs.h
  • B_XHCI_MEM_D0I2SCH_ALARM_CTRL : UsbRegs.h
  • B_XHCI_MEM_PORTSCXUSB2_CCS : UsbRegs.h
  • B_XHCI_MEM_PORTSCXUSB2_PED : UsbRegs.h
  • B_XHCI_MEM_SOCHWSTSAVE1_CMD_SSV : UsbRegs.h
  • B_XHCI_MEM_XECP_SUPP_USBX_2_CPC : UsbRegs.h
  • B_XHCI_MEM_XHCLTVCTL2_LTV_LIMIT : UsbRegs.h
  • B_XHCI_MEM_XLTP_LTV1_USB2_PL0_LTV : UsbRegs.h
  • B_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT : UsbRegs.h
  • B_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS : UsbRegs.h
  • BGPDT_MAJOR_VERSION : BiosGuard.h
  • BGPDT_MINOR_VERSION : BiosGuard.h
  • BGUP_HDR_VERSION : BiosGuard.h
  • BGUP_TSEG_BUFFER_SIZE : BiosGuard.h
  • BGUPC_MEMORY_OFFSET : BiosGuard.h
  • BGUPC_MEMORY_SIZE : BiosGuard.h
  • BIOACM_ADDR : Txt.h
  • BIOS_ASF_HOST_ADDR : CoreBiosMsg.h
  • BIOS_FIXED_HOST_ADDR : CoreBiosMsg.h
  • BIOS_GUARD_CONFIG_REVISION : BiosGuardConfig.h
  • BIOS_MSG_DID_SUCCESS : BupMsgs.h
  • BIOS_OS_DATAREGION_VERSION : Txt.h
  • BIOS_PAUSE : AsfProtocol.h
  • BIOS_SETUP : AsfProtocol.h
  • BIOSGUARD_B0_INDEX : BiosGuard.h
  • BIOSGUARD_BUILD_NUMBER_OFFSET : BiosGuard.h
  • BIOSGUARD_COMMAND_BEGIN : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_CMD_WR_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_CMD_WR_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_RD : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_WR_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_DATA_WR_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_EC_STS_RD : BiosGuard.h
  • BIOSGUARD_COMMAND_END : BiosGuard.h
  • BIOSGUARD_COMMAND_ERASE_BLK : BiosGuard.h
  • BIOSGUARD_COMMAND_NOP : BiosGuard.h
  • BIOSGUARD_COMMAND_RD_STS : BiosGuard.h
  • BIOSGUARD_COMMAND_READ_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_READ_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_SET_BUFFER_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_SET_FLASH_INDEX : BiosGuard.h
  • BIOSGUARD_COMMAND_WRITE_IMM : BiosGuard.h
  • BIOSGUARD_COMMAND_WRITE_INDEX : BiosGuard.h
  • BIOSGUARD_F0_INDEX : BiosGuard.h
  • BIOSGUARD_IF_INDEX : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_MODULE_ID_OFFSET : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_SE_SVN_OFFSET : BiosGuard.h
  • BIOSGUARD_INTERNAL_HEADER_SVN_OFFSET : BiosGuard.h
  • BIOSGUARD_LOG_MEMORY_OFFSET : BiosGuard.h
  • BIOSGUARD_LOG_MEMORY_SIZE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_BRANCH_TRACE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_DEBUG : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_ERASE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_ERROR : BiosGuard.h
  • BIOSGUARD_LOG_OPT_FLASH_WRITE : BiosGuard.h
  • BIOSGUARD_LOG_OPT_STEP_TRACE : BiosGuard.h
  • BIOSGUARD_LOG_VERSION : BiosGuard.h
  • BIOSGUARD_MEMORY_PAGES : BiosGuard.h
  • BIOSGUARD_MODULE_SIZE_IN_PAGES : BiosGuard.h
  • BIOSGUARD_MODULE_SIZE_OFFSET : BiosGuard.h
  • BIOSGUARD_PRODUCT_ID_OFFSET : BiosGuard.h
  • BIOSGUARD_REVISION_ID_MAJOR_OFFSET : BiosGuard.h
  • BIOSGUARD_REVISION_ID_MINOR_OFFSET : BiosGuard.h
  • BIT : CpuRegs.h
  • BUP_COMMON_GROUP_ID : BupMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- c -

  • C6_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • C7_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • C7s_LONG_LATENCY_ENABLE : CpuPowerMgmt.h
  • CBM_RESET_CMD : MkhiMsgs.h
  • CERT_NAME_MAX_ASCII_STRING : AmthiMsgs.h
  • CFG_IPV6_ADDR_LEN_MAX : AmthiMsgs.h
  • CLOCK_FREQUENCY_19MHz : VoltageRegulatorCommands.h
  • CPU_FEATURE_DISABLE : CpuRegs.h
  • CPU_FVI_STRING : SiFvi.h
  • CPU_PCIE_CONFIG_REVISION : CpuPcieConfig.h
  • CPU_TYPE_CHANGE_ACCEPTED : MkhiMsgs.h
  • CU_CHIPSET_PC_INTRUDER_DETECT : IntelAsfExtensions.h
  • CU_HP_EC_VID_MISMATCH : IntelAsfExtensions.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- d -

  • DEFAULT_FVI_DATA : SiFvi.h
  • DEFAULT_PCI_SEGMENT_NUMBER_PCH : PchRegs.h
  • DID_ACK_NON_PCR : BupMsgs.h
  • DNX_REQ_SET_CMD : MkhiMsgs.h
  • DRAM_INIT_DONE_CMD : BupMsgs.h
  • DT_POWER_LIMIT1_TIME_DEFAULT : CpuPowerMgmt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- e -

  • EFI_PAGE_SIZE : BiosGuard.h
  • ENABLE_PCIE_TUNNELING_FOR_USB4 : TbtMailBoxCmdDefinition.h
  • ENABLE_REMOTE_PLATFORM_ERASE : AsfProtocol.h
  • ENABLE_SECURE_ERASE : AsfProtocol.h
  • ENFORCE_SECURE_BOOT : AsfProtocol.h
  • EOP_DISABLED : MkhiMsgs.h
  • ERR_BAD_BGPDT : BiosGuard.h
  • ERR_BAD_BGUP : BiosGuard.h
  • ERR_BAD_BGUPC : BiosGuard.h
  • ERR_BAD_DIRECTORY : BiosGuard.h
  • ERR_BAD_SVN : BiosGuard.h
  • ERR_EXEC_LIMIT : BiosGuard.h
  • ERR_INTERNAL_ERROR : BiosGuard.h
  • ERR_INVALID_LINE : BiosGuard.h
  • ERR_LAUNCH_FAIL : BiosGuard.h
  • ERR_OK : BiosGuard.h
  • ERR_OVERFLOW : BiosGuard.h
  • ERR_RANGE_VIOLATION : BiosGuard.h
  • ERR_SCRIPT_SYNTAX : BiosGuard.h
  • ERR_SFAM_VIOLATION : BiosGuard.h
  • ERR_UNDEFINED_FLASH_OBJECT : BiosGuard.h
  • ERR_UNEXPECTED_OPCODE : BiosGuard.h
  • ERR_UNSUPPORTED_CPU : BiosGuard.h
  • EXTENDED_DATA_RESERVED_BITMASK : MeSmbios.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- f -

  • FIPS_MODE_DISABLED : MkhiMsgs.h
  • FLAGS0 : TxtInfoHob.h
  • FSP_ERROR_INFO_HOB_GUID : FspErrorInfo.h
  • FSP_TEMP_RAM_EXIT_GUID : TempRamExitPpi.h
  • FSPM_ARCH_CONFIG_GUID : FspmArchConfigPpi.h
  • FTIF_FT_LOC_MASK : PttPtpRegs.h
  • FTP_PARTITION_NAME_PMCP : MkhiMsgs.h
  • FUSA_CONFIG_REVISION : FusaConfig.h
  • FWCAPS_GET_RULE_CMD : MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- g -

  • GEN_GET_MKHI_VERSION_CMD : MkhiMsgs.h
  • GPIO_VER2_H_CHIPSET_ID : GpioPinsVer2H.h
  • GPIO_VER2_H_GROUP_GPP_A : GpioPinsVer2H.h
  • GPIO_VER2_H_SPI0_IO_2 : GpioPinsVer2H.h
  • GPIO_VER2_LP_CHIPSET_ID : GpioPinsVer2Lp.h
  • GPIO_VER2_LP_GPP_B0 : GpioPinsVer2Lp.h
  • GPIO_VER2_LP_GROUP_GPP_B : GpioPinsVer2Lp.h
  • GPIO_VER4_S_CHIPSET_ID : GpioPinsVer4S.h
  • GPIO_VER4_S_GPP_I0 : GpioPinsVer4S.h
  • GPIO_VER4_S_GROUP_GPP_I : GpioPinsVer4S.h
  • GT_WAIT_TIMEOUT : GraphicsInfoLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- h -

  • H_CB_WW : HeciRegs.h
  • HDAUDIO_VERB_TABLE_INIT : HdAudioConfig.h
  • HDAUDIO_VERB_TABLE_VIDDID : HdAudioConfig.h
  • HEAP_EXTDATA_TYPE_BIOS_SPEC_VER : Txt.h
  • HEAP_EXTDATA_TYPE_BIOSACM : Txt.h
  • HEAP_EXTDATA_TYPE_END : Txt.h
  • HECI_DEFAULT_PCH_ID : HeciControlProtocol.h
  • HECI_DEFAULT_RETRY_NUMBER : HeciControlProtocol.h
  • HECI_HBM_MESSAGE_ADDR : CoreBiosMsg.h
  • HECI_MAX_ME_FIXED_ADDR : CoreBiosMsg.h
  • HECI_NAME_MAP : MeRegs.h
  • HECI_PPI_REVISION : HeciPpi.h
  • HeciEnable : MeRegs.h
  • HMRFPO_DISABLED : MkhiMsgs.h
  • HMRFPO_ENABLE_CMD_ID : MkhiMsgs.h
  • HMRFPO_ENABLE_SUCCESS : MkhiMsgs.h
  • HMRFPO_LOCK_SUCCESS : MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- i -

  • ICC_CMD : BupMsgs.h
  • ICC_CURRENT_SETTINGS : IccMsgs.h
  • ICC_PROGRAMMING_TYPE_DYNAMIC : IccMsgs.h
  • ICC_PROGRAMMING_TYPE_PERSISTENT : IccMsgs.h
  • ICC_SSC_MODE_DOWN : IccMsgs.h
  • ICC_WHITE_MOUNTAIN_PHY_CLK : IccMsgs.h
  • INTEL_IANA_SWAP32 : AsfProtocol.h
  • IS_VER1_PCH_SOL_DEVICE_ID : MeRegs.h
  • ITBT_POLICY_PROTOCOL_REVISION : ITbtPolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- j -

  • JHI_APPID_NOT_EXIST : JhiProtocol.h
  • JHI_APPLET_AUTHENTICATION_FAILURE : JhiProtocol.h
  • JHI_APPLET_FATAL : JhiProtocol.h
  • JHI_APPLET_NOT_INSTALLED : JhiProtocol.h
  • JHI_APPLET_PROPERTY_NOT_SUPPORTED : JhiProtocol.h
  • JHI_APPLET_TIMEOUT : JhiProtocol.h
  • JHI_COMMS_ERROR : JhiProtocol.h
  • JHI_DELETE_FROM_REPOSITORY_FAILURE : JhiProtocol.h
  • JHI_ERROR_LOGGING : JhiProtocol.h
  • JHI_ERROR_REGISTRY : JhiProtocol.h
  • JHI_ERROR_REPOSITORY_NOT_FOUND : JhiProtocol.h
  • JHI_EVENTS_NOT_SUPPORTED : JhiProtocol.h
  • JHI_FILE_ERROR_AUTH : JhiProtocol.h
  • JHI_FILE_ERROR_COPY : JhiProtocol.h
  • JHI_FILE_ERROR_DELETE : JhiProtocol.h
  • JHI_FILE_ERROR_OPEN : JhiProtocol.h
  • JHI_FILE_IDENTICAL : JhiProtocol.h
  • JHI_FILE_INVALID : JhiProtocol.h
  • JHI_FILE_MISSING_SRC : JhiProtocol.h
  • JHI_FILE_NOT_FOUND : JhiProtocol.h
  • JHI_FILE_UUID_MISMATCH : JhiProtocol.h
  • JHI_FIRMWARE_OUT_OF_RESOURCES : JhiProtocol.h
  • JHI_IAC_SERVER_INTERNAL_SESSIONS_EXIST : JhiProtocol.h
  • JHI_IAC_SERVER_SESSION_EXIST : JhiProtocol.h
  • JHI_ILLEGAL_VALUE : JhiProtocol.h
  • JHI_INSTALL_FAILED : JhiProtocol.h
  • JHI_INSTALL_FAILURE_SESSIONS_EXISTS : JhiProtocol.h
  • JHI_INSUFFICIENT_BUFFER : JhiProtocol.h
  • JHI_INTERNAL_ERROR : JhiProtocol.h
  • JHI_INVALID_APPLET_GUID : JhiProtocol.h
  • JHI_INVALID_BUFFER_SIZE : JhiProtocol.h
  • JHI_INVALID_COMM_BUFFER : JhiProtocol.h
  • JHI_INVALID_COMMAND : JhiProtocol.h
  • JHI_INVALID_FILE_EXTENSION : JhiProtocol.h
  • JHI_INVALID_HANDLE : JhiProtocol.h
  • JHI_INVALID_INIT_BUFFER : JhiProtocol.h
  • JHI_INVALID_INSTALL_FILE : JhiProtocol.h
  • JHI_INVALID_PACKAGE_FORMAT : JhiProtocol.h
  • JHI_INVALID_PARAMS : JhiProtocol.h
  • JHI_INVALID_SESSION_HANDLE : JhiProtocol.h
  • JHI_INVALID_SPOOLER : JhiProtocol.h
  • JHI_JOM_ERROR_DOWNLOAD : JhiProtocol.h
  • JHI_JOM_ERROR_UNLOAD : JhiProtocol.h
  • JHI_JOM_FATAL : JhiProtocol.h
  • JHI_JOM_OVERFLOW : JhiProtocol.h
  • JHI_MAX_INSTALLED_APPLETS_REACHED : JhiProtocol.h
  • JHI_MAX_SESSIONS_REACHED : JhiProtocol.h
  • JHI_MAX_SHARED_SESSION_REACHED : JhiProtocol.h
  • JHI_NO_CONNECTION_TO_FIRMWARE : JhiProtocol.h
  • JHI_PROTOCOL_REVISION : JhiProtocol.h
  • JHI_READ_FROM_FILE_FAILED : JhiProtocol.h
  • JHI_SERVICE_INVALID_GUID : JhiProtocol.h
  • JHI_SERVICE_UNAVAILABLE : JhiProtocol.h
  • JHI_SESSION_ALREADY_REGSITERED : JhiProtocol.h
  • JHI_SESSION_NOT_REGISTERED : JhiProtocol.h
  • JHI_SHARED_SESSION_NOT_SUPPORTED : JhiProtocol.h
  • JHI_SPOOLER_NOT_FOUND : JhiProtocol.h
  • JHI_SUCCESS : JhiProtocol.h
  • JHI_SVL_CHECK_FAIL : JhiProtocol.h
  • JHI_UNINSTALL_FAILURE_SESSIONS_EXISTS : JhiProtocol.h
  • JHI_UNKNOWN_ERROR : JhiProtocol.h
  • JHI_VM_DLL_FILE_NOT_FOUND : JhiProtocol.h
  • JHI_VM_DLL_VERIFY_FAILED : JhiProtocol.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- k -

  • KVM_MAX_WAIT_TIME : AsfMsgs.h
  • KVM_STALL_1_SECOND : AsfMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- l -

  • LOCK_POWER_BUTTON : IndustryStandardAsf.h
  • LTR_MAX_NON_SNOOP_LATENCY_VALUE : SaPolicy.h
  • LTR_MAX_SNOOP_LATENCY_VALUE : SaPolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- m -

  • MAILBOX_READ_TIMEOUT : CpuMailboxLib.h
  • MAILBOX_WAIT_STALL : CpuMailboxLib.h
  • MAILBOX_WAIT_TIMEOUT : CpuMailboxLib.h
  • MAX_ADDRESS_LENGTH : AmthiMsgs.h
  • MAX_BIOSGUARD_LOG_PAGE : BiosGuard.h
  • MAX_CUSTOM_CTDP_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_CUSTOM_RATIO_TABLE_ENTRIES : CpuPowerMgmtCustomConfig.h
  • MAX_FWSTS_REG : FwStsSmbiosTable.h
  • MAX_HASH_ENTRIES : AmthiMsgs.h
  • MAX_INTERFACE_ID : AmthiMsgs.h
  • MAX_NUM_ICC_PROFILES : IccMsgs.h
  • MAX_NUM_VRS : CpuPowerMgmtVrConfig.h
  • MAX_PWR_PKG_COUNT : AmthiMsgs.h
  • MAX_SFAM_COUNT : BiosGuard.h
  • MAX_SKU_BITMAP : MkhiMsgs.h
  • MAX_SPD_SAVE : MemInfoHob.h
  • MAXSEG : AmthiMsgs.h
  • MB_POWER_LIMIT1_TIME_DEFAULT : CpuPowerMgmt.h
  • MBP_DATA_REVISION : MeBiosPayloadData.h
  • MBP_SENSITIVE_PPI_REVISION : MbpSensitivePpi.h
  • MCA_DAM_FILE_SIZE : MkhiMsgs.h
  • MCA_READ_FILE_CMD : MkhiMsgs.h
  • ME_DISABLE : MkhiMsgs.h
  • ME_FVI_STRING : SiFvi.h
  • ME_POLICY_PROTOCOL_REVISION : MePolicy.h
  • ME_STATUS_IS_ME_FW_BOOT_OPTIONS_PRESENT : MeState.h
  • ME_STATUS_IS_ME_FW_INIT_COMPLETE : MeState.h
  • ME_STATUS_ME_STATE_ONLY : MeState.h
  • ME_STATUS_WITH_ME_INIT_COMPLETE : MeState.h
  • ME_UNCONFIG_ERROR : MkhiMsgs.h
  • ME_UNCONFIG_FINISHED : MkhiMsgs.h
  • ME_UNCONFIG_IN_PROGRESS : MkhiMsgs.h
  • ME_UNCONFIG_NOT_IN_PROGRESS : MkhiMsgs.h
  • ME_UNCONFIG_TIMEOUT : MkhiMsgs.h
  • MEBX_CONFIG_PROTOCOL_REVISION : MebxConfigProtocol.h
  • MEM_CFG_MAX_CONTROLLERS : MemoryConfig.h
  • MEMORY_DXE_CONFIG_REVISION : MemoryDxeConfig.h
  • MEPWDID_ME_BIOS_EXT : MkhiMsgs.h
  • MEPWDMGMT_PWD_MAX_SIZE : MkhiMsgs.h
  • MEPWDMGMT_PWD_MIN_SIZE : MkhiMsgs.h
  • MIN_SFAM_COUNT : BiosGuard.h
  • MKHI_CBM_GROUP_ID : MkhiMsgs.h
  • MKHI_MSG_VERSION_MAJOR : MkhiMsgs.h
  • MPHY_READ_FROM_MPHY_CMD : BupMsgs.h
  • MRC_MAX_RCOMP_TARGETS : MemoryConfig.h
  • MSR_ACE_SPI_COMMAND : CommonMsr.h
  • MSR_ACE_SPI_CONFIG : CommonMsr.h
  • MSR_ACE_SPI_DATA : CommonMsr.h
  • MSR_ACE_SPI_STATUS : CommonMsr.h
  • MSR_AET_BASE_ADDRESS : CommonMsr.h
  • MSR_AET_EVENT_CTRL : CommonMsr.h
  • MSR_AET_MISC_ENABLE : CommonMsr.h
  • MSR_AMRR_BASE_0_0 : CommonMsr.h
  • MSR_AMRR_BASE_1_1 : CommonMsr.h
  • MSR_AMRR_BASE_2_2 : CommonMsr.h
  • MSR_AMRR_BASE_3_3 : CommonMsr.h
  • MSR_AMRR_BASE_4_4 : CommonMsr.h
  • MSR_AMRR_MASK_0_0 : CommonMsr.h
  • MSR_AMRR_MASK_1_1 : CommonMsr.h
  • MSR_AMRR_MASK_2_2 : CommonMsr.h
  • MSR_AMRR_MASK_3_3 : CommonMsr.h
  • MSR_AMRR_MASK_4_4 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_0_0 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_1_1 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_2_2 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_3_3 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_4_4 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_5_5 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_6_6 : CommonMsr.h
  • MSR_ANC_BOOT_POLICY_7_7 : CommonMsr.h
  • MSR_ANC_FORCE_BOOT_POLICY_ENFORCED : CommonMsr.h
  • MSR_ANC_INITIAL_BOOT_BLOCK_COMPLETE : CommonMsr.h
  • MSR_ANC_SACM_INFO : CommonMsr.h
  • MSR_APIC_BASE : ArchMsr.h
  • MSR_AVRR_BASE : CommonMsr.h
  • MSR_BIOS_AVX_DIS : CommonMsr.h
  • MSR_BIOS_DEBUG : ArchMsr.h
  • MSR_BIOS_DONE : CommonMsr.h
  • MSR_BIOS_DYNAMIC_UPDATE_PTR : ArchMsr.h
  • MSR_BIOS_INFO_FLAGS : CommonMsr.h
  • MSR_BIOS_MAILBOX_DATA : CommonMsr.h
  • MSR_BIOS_MAILBOX_INTERFACE : CommonMsr.h
  • MSR_BIOS_PKG_CONFIG : CommonMsr.h
  • MSR_BIOS_SE_SVN : CommonMsr.h
  • MSR_BIOS_SIGN_ID : ArchMsr.h
  • MSR_BIOS_TME_KEY_0 : CommonMsr.h
  • MSR_BIOS_TME_KEY_1 : CommonMsr.h
  • MSR_BIOS_UCODE_PM_TMR_EMULATION_CFG : CommonMsr.h
  • MSR_BIOS_UPDT_TRIG : ArchMsr.h
  • MSR_BIOS_UPGD_TRIG : ArchMsr.h
  • MSR_BNDCFGS : ArchMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_0 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_1 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_2 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_3 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_4 : CommonMsr.h
  • MSR_C_STATE_LATENCY_CONTROL_5 : CommonMsr.h
  • MSR_CC3_RCNTR : CommonMsr.h
  • MSR_CC7_RCNTR : CommonMsr.h
  • MSR_CLOAKING : CommonMsr.h
  • MSR_CLOCK_CST_CONFIG_CONTROL : CommonMsr.h
  • MSR_CLOCK_MODULATION : ArchMsr.h
  • MSR_CLOS_CONFIG : ArchMsr.h
  • MSR_CLR_PERF_LIMIT_REASONS : ArchMsr.h
  • MSR_COMPOUND_CTR_CTRL : CommonMsr.h
  • MSR_COMPOUND_PERF_CTR : CommonMsr.h
  • MSR_CONFIG_TDP_CONTROL : CommonMsr.h
  • MSR_CONFIG_TDP_LEVEL1 : CommonMsr.h
  • MSR_CONFIG_TDP_LEVEL2 : CommonMsr.h
  • MSR_CONFIG_TDP_NOMINAL : CommonMsr.h
  • MSR_COPY_LOCAL_TO_PLATFORM : ArchMsr.h
  • MSR_COPY_PLATFORM_TO_LOCAL : ArchMsr.h
  • MSR_COPY_STATUS : ArchMsr.h
  • MSR_CORE_C1_RESIDENCY : CommonMsr.h
  • MSR_CORE_C6_RESIDENCY_COUNTER : CommonMsr.h
  • MSR_CORE_CAPABILITIES : ArchMsr.h
  • MSR_CORE_MKTME_ACTIVATION : CommonMsr.h
  • MSR_CORE_SDC_RESIDENCY : CommonMsr.h
  • MSR_CORE_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_CORE_SMI_ERR_SRC : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_0_0 : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_1_1 : CommonMsr.h
  • MSR_CORE_SPECIFIC_13_BIT_SPARE_2_2 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_0_0 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_1_1 : CommonMsr.h
  • MSR_CORE_SPECIFIC_SPARE_2_2 : CommonMsr.h
  • MSR_CORE_THREAD_COUNT : CommonMsr.h
  • MSR_CORE_UARCH_CTL : CommonMsr.h
  • MSR_COS_WAYS_0 : ArchMsr.h
  • MSR_COS_WAYS_1 : ArchMsr.h
  • MSR_COS_WAYS_2 : ArchMsr.h
  • MSR_COS_WAYS_3 : ArchMsr.h
  • MSR_CPU_BUSNUMBER : CommonMsr.h
  • MSR_CPU_DCA_CAP : ArchMsr.h
  • MSR_CPU_TYPE : CommonMsr.h
  • MSR_CRASHLOG_CONTROL : CommonMsr.h
  • MSR_CSTAR : ArchMsr.h
  • MSR_CUSTOMER_SPECIFIC_FEATURE_ENABLE : CommonMsr.h
  • MSR_DCU_FLUSH_CMD : ArchMsr.h
  • MSR_DCU_MODE_CONTROL : CommonMsr.h
  • MSR_DDR_ENERGY_STATUS : CommonMsr.h
  • MSR_DDR_RAPL_LIMIT : CommonMsr.h
  • MSR_DDR_RAPL_PERF_STATUS : CommonMsr.h
  • MSR_DEBUG_ERR_INJ_CTL : CommonMsr.h
  • MSR_DEBUG_ERR_INJ_CTL2 : CommonMsr.h
  • MSR_DEBUG_RESOURCE_STATUS : CommonMsr.h
  • MSR_DEBUGCTLMSR : ArchMsr.h
  • MSR_DISTRIBUTED_STATUS : CommonMsr.h
  • MSR_DS_AREA : ArchMsr.h
  • MSR_EDRAM_ACM : CommonMsr.h
  • MSR_EE_INIT : CommonMsr.h
  • MSR_EINIT_FAIL_CTR : CommonMsr.h
  • MSR_ELSRR_BASE : CommonMsr.h
  • MSR_ELSRR_MASK : CommonMsr.h
  • MSR_EM_EXCEPTIONS_HANDLING_EIP : CommonMsr.h
  • MSR_EMON_FIXED_CTR0 : ArchMsr.h
  • MSR_EMON_FIXED_CTR1 : ArchMsr.h
  • MSR_EMON_FIXED_CTR2 : ArchMsr.h
  • MSR_EMON_FIXED_CTR3 : ArchMsr.h
  • MSR_EMON_FIXED_CTR_CTRL : ArchMsr.h
  • MSR_EMON_FULL_CTR0 : ArchMsr.h
  • MSR_EMON_FULL_CTR1 : ArchMsr.h
  • MSR_EMON_FULL_CTR2 : ArchMsr.h
  • MSR_EMON_FULL_CTR3 : ArchMsr.h
  • MSR_EMON_FULL_CTR4 : ArchMsr.h
  • MSR_EMON_FULL_CTR5 : ArchMsr.h
  • MSR_EMON_FULL_CTR6 : ArchMsr.h
  • MSR_EMON_FULL_CTR7 : ArchMsr.h
  • MSR_EMON_GEN_CTR0 : ArchMsr.h
  • MSR_EMON_GEN_CTR1 : ArchMsr.h
  • MSR_EMON_GEN_CTR2 : ArchMsr.h
  • MSR_EMON_GEN_CTR3 : ArchMsr.h
  • MSR_EMON_GEN_CTR4 : ArchMsr.h
  • MSR_EMON_GEN_CTR5 : ArchMsr.h
  • MSR_EMON_GEN_CTR6 : ArchMsr.h
  • MSR_EMON_GEN_CTR7 : ArchMsr.h
  • MSR_EMON_PERF_CAPABILITIES : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_CTRL : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_RESET : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_SET : ArchMsr.h
  • MSR_EMON_PERF_GLOBAL_STATUS : ArchMsr.h
  • MSR_EMON_PERF_RES_PROGRAMMED : CommonMsr.h
  • MSR_EMRR_BASE : CommonMsr.h
  • MSR_EMRR_MASK : CommonMsr.h
  • MSR_EMXRR_BASE : CommonMsr.h
  • MSR_EMXRR_MASK : CommonMsr.h
  • MSR_ENABLE_DISABLE_CACHE_QOS : CommonMsr.h
  • MSR_ENABLE_LSM : FusaConfig.h
  • MSR_ENERGY_PERF_BIAS_CONFIG : CommonMsr.h
  • MSR_ENERGY_PERFORMANCE_BIAS : ArchMsr.h
  • MSR_ERR_INJ_LCK_UNLOCK_CTL : CommonMsr.h
  • MSR_ERROR_CONTROL : CommonMsr.h
  • MSR_EXTENDED_MCG_PTR : CommonMsr.h
  • MSR_FAST_UNCORE_MSRS_CAPABILITY : CommonMsr.h
  • MSR_FAST_UNCORE_MSRS_CTL : ArchMsr.h
  • MSR_FEATURE_CONFIG : CommonMsr.h
  • MSR_FIT_BIOS_ERROR : CommonMsr.h
  • MSR_FLEX_RATIO : CommonMsr.h
  • MSR_FME_ACTIVATE : CommonMsr.h
  • MSR_FS_BASE : ArchMsr.h
  • MSR_FUSE_KEY1_0 : CommonMsr.h
  • MSR_FUSE_KEY1_1 : CommonMsr.h
  • MSR_FZM_DOMAIN_CONFIG : ArchMsr.h
  • MSR_FZM_RANGE_ENDADDR : ArchMsr.h
  • MSR_FZM_RANGE_INDEX : ArchMsr.h
  • MSR_FZM_RANGE_STARTADDR : ArchMsr.h
  • MSR_FZM_RANGE_WRITESTATUS : ArchMsr.h
  • MSR_GLOBAL_SE_ENABLE : CommonMsr.h
  • MSR_GS_BASE : ArchMsr.h
  • MSR_GT_FLUSH_BCLD_ACK : CommonMsr.h
  • MSR_GT_FLUSH_RELOAD : CommonMsr.h
  • MSR_GT_PERF_LIMIT_REASONS : ArchMsr.h
  • MSR_HW_FB_CONFIG : ArchMsr.h
  • MSR_HW_FB_PTR : ArchMsr.h
  • MSR_HW_GET_LP_PM_META_DATA : CommonMsr.h
  • MSR_HW_SET_LP_PM_META_DATA : CommonMsr.h
  • MSR_HWP_REQUEST_PKG : ArchMsr.h
  • MSR_IA32_CR_EFER : ArchMsr.h
  • MSR_IA32_SE_SVN : CommonMsr.h
  • MSR_IA_PERF_LIMIT_REASONS : CommonMsr.h
  • MSR_ICECTLPMR : CommonMsr.h
  • MSR_ICECTLPMR_2 : CommonMsr.h
  • MSR_ICECTLPMR_PRIOR_STATE : CommonMsr.h
  • MSR_IIOPMONCNTR_0 : CommonMsr.h
  • MSR_IIOPMONCNTR_1 : CommonMsr.h
  • MSR_IIOPMONCNTR_2 : CommonMsr.h
  • MSR_IIOPMONCNTR_3 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_0 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_1 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_10 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_11 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_12 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_13 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_14 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_15 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_2 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_3 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_4 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_5 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_6 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_7 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_8 : CommonMsr.h
  • MSR_IIOPMONFRCNTR_9 : CommonMsr.h
  • MSR_IMC0_MC_CTL : CommonMsr.h
  • MSR_IMC0_MC_STATUS : CommonMsr.h
  • MSR_IMC1_MC9_ADDR : CommonMsr.h
  • MSR_IMC2_MCA_ADDR : CommonMsr.h
  • MSR_INTERRUPT_SSP_TABLE : ArchMsr.h
  • MSR_IO_BW_P_LIMIT_OVERRIDE : CommonMsr.h
  • MSR_IO_MEM_ADDR : CommonMsr.h
  • MSR_IO_QOS_CFG : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RCX : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RDI : CommonMsr.h
  • MSR_IO_SMI_BACKUP_RSI : CommonMsr.h
  • MSR_IOMISCINFO : CommonMsr.h
  • MSR_IOPMONCNTRCFG_0 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_1 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_2 : CommonMsr.h
  • MSR_IOPMONCNTRCFG_3 : CommonMsr.h
  • MSR_IRPPMONCNTRCFG_0 : CommonMsr.h
  • MSR_IRPPMONCNTRCFG_1 : CommonMsr.h
  • MSR_IWKEYBACKUP_STATUS : ArchMsr.h
  • MSR_KERNEL_GSBASE : ArchMsr.h
  • MSR_L2_QOS_CFG : ArchMsr.h
  • MSR_L2_QOS_MASK_0_0 : ArchMsr.h
  • MSR_L2_QOS_MASK_1_1 : ArchMsr.h
  • MSR_L2_QOS_MASK_2_2 : ArchMsr.h
  • MSR_L2_QOS_MASK_3_3 : ArchMsr.h
  • MSR_L2_QOS_MASK_4_4 : ArchMsr.h
  • MSR_L2_QOS_MASK_5_5 : ArchMsr.h
  • MSR_L2_QOS_MASK_6_6 : ArchMsr.h
  • MSR_L2_QOS_MASK_7_7 : ArchMsr.h
  • MSR_L3_PROTECTED_WAYS : CommonMsr.h
  • MSR_LAST_BRANCH_FROM_IP : CommonMsr.h
  • MSR_LAST_BRANCH_INFO : CommonMsr.h
  • MSR_LAST_BRANCH_TO_IP : CommonMsr.h
  • MSR_LAST_INT_FROM_IP : CommonMsr.h
  • MSR_LAST_INT_INFO : CommonMsr.h
  • MSR_LAST_INT_TO_IP : CommonMsr.h
  • MSR_LBR_FROM_IP_0_0 : CommonMsr.h
  • MSR_LBR_FROM_IP_10_10 : CommonMsr.h
  • MSR_LBR_FROM_IP_11_11 : CommonMsr.h
  • MSR_LBR_FROM_IP_18_18 : CommonMsr.h
  • MSR_LBR_FROM_IP_19_19 : CommonMsr.h
  • MSR_LBR_FROM_IP_1_1 : CommonMsr.h
  • MSR_LBR_FROM_IP_20_20 : CommonMsr.h
  • MSR_LBR_FROM_IP_21_21 : CommonMsr.h
  • MSR_LBR_FROM_IP_22_22 : CommonMsr.h
  • MSR_LBR_FROM_IP_23_23 : CommonMsr.h
  • MSR_LBR_FROM_IP_24_24 : CommonMsr.h
  • MSR_LBR_FROM_IP_25_25 : CommonMsr.h
  • MSR_LBR_FROM_IP_26_26 : CommonMsr.h
  • MSR_LBR_FROM_IP_27_27 : CommonMsr.h
  • MSR_LBR_FROM_IP_28_28 : CommonMsr.h
  • MSR_LBR_FROM_IP_29_29 : CommonMsr.h
  • MSR_LBR_FROM_IP_2_2 : CommonMsr.h
  • MSR_LBR_FROM_IP_30_30 : CommonMsr.h
  • MSR_LBR_FROM_IP_31_31 : CommonMsr.h
  • MSR_LBR_FROM_IP_3_3 : CommonMsr.h
  • MSR_LBR_FROM_IP_4_4 : CommonMsr.h
  • MSR_LBR_FROM_IP_5_5 : CommonMsr.h
  • MSR_LBR_FROM_IP_6_6 : CommonMsr.h
  • MSR_LBR_FROM_IP_7_7 : CommonMsr.h
  • MSR_LBR_FROM_IP_8_8 : CommonMsr.h
  • MSR_LBR_FROM_IP_9_9 : CommonMsr.h
  • MSR_LBR_INFO_0_0 : CommonMsr.h
  • MSR_LBR_INFO_10_10 : CommonMsr.h
  • MSR_LBR_INFO_11_11 : CommonMsr.h
  • MSR_LBR_INFO_12_12 : CommonMsr.h
  • MSR_LBR_INFO_13_13 : CommonMsr.h
  • MSR_LBR_INFO_14_14 : CommonMsr.h
  • MSR_LBR_INFO_15_15 : CommonMsr.h
  • MSR_LBR_INFO_16_16 : CommonMsr.h
  • MSR_LBR_INFO_17_17 : CommonMsr.h
  • MSR_LBR_INFO_18_18 : CommonMsr.h
  • MSR_LBR_INFO_19_19 : CommonMsr.h
  • MSR_LBR_INFO_1_1 : CommonMsr.h
  • MSR_LBR_INFO_20_20 : CommonMsr.h
  • MSR_LBR_INFO_21_21 : CommonMsr.h
  • MSR_LBR_INFO_22_22 : CommonMsr.h
  • MSR_LBR_INFO_23_23 : CommonMsr.h
  • MSR_LBR_INFO_24_24 : CommonMsr.h
  • MSR_LBR_INFO_25_25 : CommonMsr.h
  • MSR_LBR_INFO_26_26 : CommonMsr.h
  • MSR_LBR_INFO_27_27 : CommonMsr.h
  • MSR_LBR_INFO_28_28 : CommonMsr.h
  • MSR_LBR_INFO_29_29 : CommonMsr.h
  • MSR_LBR_INFO_2_2 : CommonMsr.h
  • MSR_LBR_INFO_30_30 : CommonMsr.h
  • MSR_LBR_INFO_31_31 : CommonMsr.h
  • MSR_LBR_INFO_3_3 : CommonMsr.h
  • MSR_LBR_INFO_4_4 : CommonMsr.h
  • MSR_LBR_INFO_5_5 : CommonMsr.h
  • MSR_LBR_INFO_6_6 : CommonMsr.h
  • MSR_LBR_INFO_7_7 : CommonMsr.h
  • MSR_LBR_INFO_8_8 : CommonMsr.h
  • MSR_LBR_INFO_9_9 : CommonMsr.h
  • MSR_LBR_SELECT : CommonMsr.h
  • MSR_LBR_TO_IP_0_0 : CommonMsr.h
  • MSR_LBR_TO_IP_10_10 : CommonMsr.h
  • MSR_LBR_TO_IP_11_11 : CommonMsr.h
  • MSR_LBR_TO_IP_12_12 : CommonMsr.h
  • MSR_LBR_TO_IP_13_13 : CommonMsr.h
  • MSR_LBR_TO_IP_14_14 : CommonMsr.h
  • MSR_LBR_TO_IP_15_15 : CommonMsr.h
  • MSR_LBR_TO_IP_16_16 : CommonMsr.h
  • MSR_LBR_TO_IP_17_17 : CommonMsr.h
  • MSR_LBR_TO_IP_18_18 : CommonMsr.h
  • MSR_LBR_TO_IP_19_19 : CommonMsr.h
  • MSR_LBR_TO_IP_1_1 : CommonMsr.h
  • MSR_LBR_TO_IP_20_20 : CommonMsr.h
  • MSR_LBR_TO_IP_21_21 : CommonMsr.h
  • MSR_LBR_TO_IP_22_22 : CommonMsr.h
  • MSR_LBR_TO_IP_23_23 : CommonMsr.h
  • MSR_LBR_TO_IP_24_24 : CommonMsr.h
  • MSR_LBR_TO_IP_25_25 : CommonMsr.h
  • MSR_LBR_TO_IP_26_26 : CommonMsr.h
  • MSR_LBR_TO_IP_27_27 : CommonMsr.h
  • MSR_LBR_TO_IP_28_28 : CommonMsr.h
  • MSR_LBR_TO_IP_29_29 : CommonMsr.h
  • MSR_LBR_TO_IP_2_2 : CommonMsr.h
  • MSR_LBR_TO_IP_30_30 : CommonMsr.h
  • MSR_LBR_TO_IP_31_31 : CommonMsr.h
  • MSR_LBR_TO_IP_3_3 : CommonMsr.h
  • MSR_LBR_TO_IP_4_4 : CommonMsr.h
  • MSR_LBR_TO_IP_5_5 : CommonMsr.h
  • MSR_LBR_TO_IP_6_6 : CommonMsr.h
  • MSR_LBR_TO_IP_7_7 : CommonMsr.h
  • MSR_LBR_TO_IP_8_8 : CommonMsr.h
  • MSR_LBR_TO_IP_9_9 : CommonMsr.h
  • MSR_LBR_TOS : CommonMsr.h
  • MSR_LCLK_PLL_RATIO : CommonMsr.h
  • MSR_LLC_FLUSHED_RCNTR : CommonMsr.h
  • MSR_LLC_QOS_MASK_0 : CommonMsr.h
  • MSR_LLC_QOS_MASK_1 : CommonMsr.h
  • MSR_LLC_QOS_MASK_10_10 : CommonMsr.h
  • MSR_LLC_QOS_MASK_11_11 : CommonMsr.h
  • MSR_LLC_QOS_MASK_12_12 : CommonMsr.h
  • MSR_LLC_QOS_MASK_13_13 : CommonMsr.h
  • MSR_LLC_QOS_MASK_14_14 : CommonMsr.h
  • MSR_LLC_QOS_MASK_2 : CommonMsr.h
  • MSR_LLC_QOS_MASK_3 : CommonMsr.h
  • MSR_LLC_QOS_MASK_4_4 : CommonMsr.h
  • MSR_LLC_QOS_MASK_5_5 : CommonMsr.h
  • MSR_LLC_QOS_MASK_6_6 : CommonMsr.h
  • MSR_LLC_QOS_MASK_7_7 : CommonMsr.h
  • MSR_LLC_QOS_MASK_8_8 : CommonMsr.h
  • MSR_LLC_QOS_MASK_9_9 : CommonMsr.h
  • MSR_LSTAR : ArchMsr.h
  • MSR_LT_SMX_STATE : CommonMsr.h
  • MSR_LT_UNLOCK_MEMORY : CommonMsr.h
  • MSR_M2PPMONCNTRCFG_2 : CommonMsr.h
  • MSR_M2PPMONCNTRCFG_3 : CommonMsr.h
  • MSR_MBA_CFG : CommonMsr.h
  • MSR_MBM_CFG_3DXP : CommonMsr.h
  • MSR_MC0_ADDR : ArchMsr.h
  • MSR_MC0_CTL : ArchMsr.h
  • MSR_MC0_MISC : ArchMsr.h
  • MSR_MC0_MISC2 : ArchMsr.h
  • MSR_MC0_STATUS : ArchMsr.h
  • MSR_MC10_ADDR : ArchMsr.h
  • MSR_MC10_CTL : ArchMsr.h
  • MSR_MC10_CTL2 : ArchMsr.h
  • MSR_MC10_MISC : ArchMsr.h
  • MSR_MC10_STATUS : ArchMsr.h
  • MSR_MC11_ADDR : ArchMsr.h
  • MSR_MC11_CTL : ArchMsr.h
  • MSR_MC11_CTL2 : ArchMsr.h
  • MSR_MC11_MISC : ArchMsr.h
  • MSR_MC11_STATUS : ArchMsr.h
  • MSR_MC12_ADDR : ArchMsr.h
  • MSR_MC12_CTL : ArchMsr.h
  • MSR_MC12_CTL2 : ArchMsr.h
  • MSR_MC12_MISC : ArchMsr.h
  • MSR_MC12_STATUS : ArchMsr.h
  • MSR_MC13_ADDR : ArchMsr.h
  • MSR_MC13_CTL : ArchMsr.h
  • MSR_MC13_CTL2 : ArchMsr.h
  • MSR_MC13_MISC : ArchMsr.h
  • MSR_MC13_STATUS : ArchMsr.h
  • MSR_MC14_ADDR : ArchMsr.h
  • MSR_MC14_CTL : ArchMsr.h
  • MSR_MC14_CTL2 : ArchMsr.h
  • MSR_MC14_MISC : ArchMsr.h
  • MSR_MC14_STATUS : ArchMsr.h
  • MSR_MC15_ADDR : ArchMsr.h
  • MSR_MC15_CTL : ArchMsr.h
  • MSR_MC15_CTL2 : ArchMsr.h
  • MSR_MC15_MISC : ArchMsr.h
  • MSR_MC15_STATUS : ArchMsr.h
  • MSR_MC16_ADDR : ArchMsr.h
  • MSR_MC16_CTL : ArchMsr.h
  • MSR_MC16_CTL2 : ArchMsr.h
  • MSR_MC16_MISC : ArchMsr.h
  • MSR_MC16_STATUS : ArchMsr.h
  • MSR_MC17_ADDR : ArchMsr.h
  • MSR_MC17_CTL : ArchMsr.h
  • MSR_MC17_CTL2 : ArchMsr.h
  • MSR_MC17_MISC : ArchMsr.h
  • MSR_MC17_STATUS : ArchMsr.h
  • MSR_MC18_ADDR : ArchMsr.h
  • MSR_MC18_CTL : ArchMsr.h
  • MSR_MC18_CTL2 : ArchMsr.h
  • MSR_MC18_MISC : ArchMsr.h
  • MSR_MC18_STATUS : ArchMsr.h
  • MSR_MC19_ADDR : ArchMsr.h
  • MSR_MC19_CTL : ArchMsr.h
  • MSR_MC19_CTL2 : ArchMsr.h
  • MSR_MC19_STATUS : ArchMsr.h
  • MSR_MC1_ADDR : ArchMsr.h
  • MSR_MC1_CTL : ArchMsr.h
  • MSR_MC1_MISC : ArchMsr.h
  • MSR_MC1_MISC2 : ArchMsr.h
  • MSR_MC1_STATUS : ArchMsr.h
  • MSR_MC20_ADDR : ArchMsr.h
  • MSR_MC20_CTL : ArchMsr.h
  • MSR_MC20_CTL2 : ArchMsr.h
  • MSR_MC20_STATUS : ArchMsr.h
  • MSR_MC21_ADDR : ArchMsr.h
  • MSR_MC21_CTL : ArchMsr.h
  • MSR_MC21_CTL2 : ArchMsr.h
  • MSR_MC21_MISC : ArchMsr.h
  • MSR_MC21_STATUS : ArchMsr.h
  • MSR_MC22_ADDR : ArchMsr.h
  • MSR_MC22_CTL : ArchMsr.h
  • MSR_MC22_CTL2 : ArchMsr.h
  • MSR_MC22_MISC : ArchMsr.h
  • MSR_MC22_STATUS : ArchMsr.h
  • MSR_MC23_ADDR : ArchMsr.h
  • MSR_MC23_CTL : ArchMsr.h
  • MSR_MC23_CTL2 : ArchMsr.h
  • MSR_MC23_MISC : ArchMsr.h
  • MSR_MC23_STATUS : ArchMsr.h
  • MSR_MC24_ADDR : ArchMsr.h
  • MSR_MC24_CTL : ArchMsr.h
  • MSR_MC24_CTL2 : ArchMsr.h
  • MSR_MC24_MISC : ArchMsr.h
  • MSR_MC24_STATUS : ArchMsr.h
  • MSR_MC2_ADDR : ArchMsr.h
  • MSR_MC2_CTL : ArchMsr.h
  • MSR_MC2_MISC : ArchMsr.h
  • MSR_MC2_MISC2 : ArchMsr.h
  • MSR_MC2_STATUS : ArchMsr.h
  • MSR_MC3_ADDR : ArchMsr.h
  • MSR_MC3_CTL : ArchMsr.h
  • MSR_MC3_MISC : ArchMsr.h
  • MSR_MC3_MISC2 : ArchMsr.h
  • MSR_MC3_STATUS : ArchMsr.h
  • MSR_MC4_ADDR : ArchMsr.h
  • MSR_MC4_CTL : ArchMsr.h
  • MSR_MC4_CTL2 : ArchMsr.h
  • MSR_MC4_MISC : ArchMsr.h
  • MSR_MC4_STATUS : ArchMsr.h
  • MSR_MC5_ADDR : ArchMsr.h
  • MSR_MC5_CTL : ArchMsr.h
  • MSR_MC5_CTL2 : ArchMsr.h
  • MSR_MC5_MISC : ArchMsr.h
  • MSR_MC5_STATUS : ArchMsr.h
  • MSR_MC6_ADDR : ArchMsr.h
  • MSR_MC6_CTL : ArchMsr.h
  • MSR_MC6_CTL2 : ArchMsr.h
  • MSR_MC6_MISC : ArchMsr.h
  • MSR_MC6_STATUS : ArchMsr.h
  • MSR_MC7_ADDR : ArchMsr.h
  • MSR_MC7_CTL : ArchMsr.h
  • MSR_MC7_CTL2 : ArchMsr.h
  • MSR_MC7_MISC : ArchMsr.h
  • MSR_MC7_STATUS : ArchMsr.h
  • MSR_MC8_ADDR : ArchMsr.h
  • MSR_MC8_CTL : ArchMsr.h
  • MSR_MC8_CTL2 : ArchMsr.h
  • MSR_MC8_MISC : ArchMsr.h
  • MSR_MC8_STATUS : ArchMsr.h
  • MSR_MC9_ADDR : ArchMsr.h
  • MSR_MC9_CTL : ArchMsr.h
  • MSR_MC9_CTL2 : ArchMsr.h
  • MSR_MC9_MISC : ArchMsr.h
  • MSR_MC9_STATUS : ArchMsr.h
  • MSR_MCA_ON_NONNEM_CACHABLEMMIO_EN : CommonMsr.h
  • MSR_MCG_CAP : ArchMsr.h
  • MSR_MCG_CONTAIN : CommonMsr.h
  • MSR_MCG_EXE_CTL : CommonMsr.h
  • MSR_MCG_STATUS : ArchMsr.h
  • MSR_MCHECK_BOOT_SCENARIO : CommonMsr.h
  • MSR_MCHECK_CPU_REGISTER_ADDRESS : CommonMsr.h
  • MSR_MCHECK_CPU_REGISTER_DATA : CommonMsr.h
  • MSR_MCI_CTL2 : CommonMsr.h
  • MSR_MEE_SETUP : CommonMsr.h
  • MSR_MEMORY_CONTROL : CommonMsr.h
  • MSR_MISC_ENABLES : ArchMsr.h
  • MSR_MISC_FEATURE_CONTROL : CommonMsr.h
  • MSR_MISC_PWR_MGMT : CommonMsr.h
  • MSR_MISC_THD_FEATURE_ENABLES : CommonMsr.h
  • MSR_MLC_ACNT_COUNTER : ArchMsr.h
  • MSR_MLC_MCNT_COUNTER : ArchMsr.h
  • MSR_MLC_PCNT_COUNTER : ArchMsr.h
  • MSR_MLC_PWR_MGMT_TIMER_CTRL : CommonMsr.h
  • MSR_MLC_VT_TIMER_CONTROL : CommonMsr.h
  • MSR_MLC_VT_TIMER_COUNT : CommonMsr.h
  • MSR_MMCFG_RULE_CFG : CommonMsr.h
  • MSR_MMCFG_RULE_TARGET_LIST : CommonMsr.h
  • MSR_MONITOR_FILTER_SIZE : ArchMsr.h
  • MSR_MPX_FUSE_OVERRIDE : CommonMsr.h
  • MSR_MPX_LAX : ArchMsr.h
  • MSR_MSR_THERM2_CTL : CommonMsr.h
  • MSR_MTRRCAP : ArchMsr.h
  • MSR_MTRRDEFAULT : ArchMsr.h
  • MSR_MTRRFIX16K8 : ArchMsr.h
  • MSR_MTRRFIX16KA : ArchMsr.h
  • MSR_MTRRFIX4KC0 : ArchMsr.h
  • MSR_MTRRFIX4KC8 : ArchMsr.h
  • MSR_MTRRFIX4KD0 : ArchMsr.h
  • MSR_MTRRFIX4KD8 : ArchMsr.h
  • MSR_MTRRFIX4KE0 : ArchMsr.h
  • MSR_MTRRFIX4KE8 : ArchMsr.h
  • MSR_MTRRFIX4KF0 : ArchMsr.h
  • MSR_MTRRFIX4KF8 : ArchMsr.h
  • MSR_MTRRFIX64K : ArchMsr.h
  • MSR_MTRRVARBASE0 : ArchMsr.h
  • MSR_MTRRVARBASE1 : ArchMsr.h
  • MSR_MTRRVARBASE2 : ArchMsr.h
  • MSR_MTRRVARBASE3 : ArchMsr.h
  • MSR_MTRRVARBASE4 : ArchMsr.h
  • MSR_MTRRVARBASE5 : ArchMsr.h
  • MSR_MTRRVARBASE6 : ArchMsr.h
  • MSR_MTRRVARBASE7 : ArchMsr.h
  • MSR_MTRRVARBASE8 : ArchMsr.h
  • MSR_MTRRVARBASE9 : ArchMsr.h
  • MSR_MTRRVARMASK0 : ArchMsr.h
  • MSR_MTRRVARMASK1 : ArchMsr.h
  • MSR_MTRRVARMASK2 : ArchMsr.h
  • MSR_MTRRVARMASK3 : ArchMsr.h
  • MSR_MTRRVARMASK4 : ArchMsr.h
  • MSR_MTRRVARMASK5 : ArchMsr.h
  • MSR_MTRRVARMASK6 : ArchMsr.h
  • MSR_MTRRVARMASK7 : ArchMsr.h
  • MSR_MTRRVARMASK8 : ArchMsr.h
  • MSR_MTRRVARMASK9 : ArchMsr.h
  • MSR_NCUPMONCTRLGLCTR : CommonMsr.h
  • MSR_NCUPMONGLSTS1 : CommonMsr.h
  • MSR_NCUWHOAMI : CommonMsr.h
  • MSR_NEM : CommonMsr.h
  • MSR_NPK_STH_ACPIBAR_BASE : CommonMsr.h
  • MSR_OPTIN_FEATURE_CONTROL : ArchMsr.h
  • MSR_OVERCLOCKING_MAILBOX : CommonMsr.h
  • MSR_P5_MC_ADDR : ArchMsr.h
  • MSR_P6_CR_SMBASE : CommonMsr.h
  • MSR_P6_CR_SMREVID : CommonMsr.h
  • MSR_PACKAGE_ENERGY_STATUS : CommonMsr.h
  • MSR_PACKAGE_POWER_SKU : CommonMsr.h
  • MSR_PACKAGE_POWER_SKU_UNIT : CommonMsr.h
  • MSR_PACKAGE_RAPL_LIMIT : CommonMsr.h
  • MSR_PACKAGE_RAPL_PERF_STATUS : CommonMsr.h
  • MSR_PACKAGE_THERM_INTERRUPT : ArchMsr.h
  • MSR_PACKAGE_THERM_MARGIN : CommonMsr.h
  • MSR_PACKAGE_THERM_STATUS : ArchMsr.h
  • MSR_PAIR_PKG_THREAD_PARTICIPATION : CommonMsr.h
  • MSR_PAIR_THREAD_PARTICIPATION : CommonMsr.h
  • MSR_PAIR_WEIGHT_OVERRIDE : CommonMsr.h
  • MSR_PASID : ArchMsr.h
  • MSR_PAT : ArchMsr.h
  • MSR_PC10_RCNTR : CommonMsr.h
  • MSR_PC2_RCNTR : CommonMsr.h
  • MSR_PC3_RCNTR : CommonMsr.h
  • MSR_PC6_RCNTR : CommonMsr.h
  • MSR_PC7_RCNTR : CommonMsr.h
  • MSR_PC8_RCNTR : CommonMsr.h
  • MSR_PC9_RCNTR : CommonMsr.h
  • MSR_PCH_EA_CONTROL : CommonMsr.h
  • MSR_PCH_EA_STATUS : CommonMsr.h
  • MSR_PCUPMONCNTR_0 : CommonMsr.h
  • MSR_PCUPMONCNTR_1 : CommonMsr.h
  • MSR_PCUPMONCNTR_2 : CommonMsr.h
  • MSR_PCUPMONCNTR_3 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_0 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_1 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_2 : CommonMsr.h
  • MSR_PCUPMONCNTRCFG_3 : CommonMsr.h
  • MSR_PDM_GDXC_MSG : CommonMsr.h
  • MSR_PDM_HEADER : CommonMsr.h
  • MSR_PDPTR_0_0 : CommonMsr.h
  • MSR_PDPTR_1_1 : CommonMsr.h
  • MSR_PDPTR_2_2 : CommonMsr.h
  • MSR_PDPTR_3_3 : CommonMsr.h
  • MSR_PEBS_DATA_CFG : ArchMsr.h
  • MSR_PEBS_ENABLE : ArchMsr.h
  • MSR_PEBS_FRONTEND : CommonMsr.h
  • MSR_PEBS_LD_LAT_THRESHOLD : CommonMsr.h
  • MSR_PERF_CTL : ArchMsr.h
  • MSR_PERF_METRICS : ArchMsr.h
  • MSR_PERF_OCCUPANCY_CTRS : ArchMsr.h
  • MSR_PERF_STATUS : ArchMsr.h
  • MSR_PERFCTR0 : CommonMsr.h
  • MSR_PERFCTR1 : CommonMsr.h
  • MSR_PERMEM_CONFIG_INFO : CommonMsr.h
  • MSR_PERMEM_CTRLR_ID : CommonMsr.h
  • MSR_PERMEM_CTRLR_INDEX : CommonMsr.h
  • MSR_PERMON_EVNTSEL_AUX : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR0 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR1 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR2 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR3 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR4 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR5 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR6 : ArchMsr.h
  • MSR_PERMON_EVNTSEL_CNTR7 : ArchMsr.h
  • MSR_PFAT_EC_PASSWORD : CommonMsr.h
  • MSR_PFAT_GT_SLEEP_CMDSTS : CommonMsr.h
  • MSR_PFR_EXIT : CommonMsr.h
  • MSR_PFR_VCM_PROVISION : CommonMsr.h
  • MSR_PFR_VCM_PROVISION_STATUS : CommonMsr.h
  • MSR_PIC_EOI : CommonMsr.h
  • MSR_PIC_ERROR_STATUS : CommonMsr.h
  • MSR_PIC_EXTENDED_LOCAL_APIC_ID : CommonMsr.h
  • MSR_PIC_EXTENDED_LOGICAL_DESTINATION : CommonMsr.h
  • MSR_PIC_INTERRUPT_COMMAND : CommonMsr.h
  • MSR_PIC_IRR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_IRR_DWORD_7_7 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_ISR_DWORD_7_7 : CommonMsr.h
  • MSR_PIC_LOCAL_UNIT_VERSION : CommonMsr.h
  • MSR_PIC_LT_DOORBELL : CommonMsr.h
  • MSR_PIC_LVT_CMCI : CommonMsr.h
  • MSR_PIC_LVT_ERROR : CommonMsr.h
  • MSR_PIC_LVT_LINT0 : CommonMsr.h
  • MSR_PIC_LVT_LINT1 : CommonMsr.h
  • MSR_PIC_LVT_PERF : CommonMsr.h
  • MSR_PIC_LVT_THERM : CommonMsr.h
  • MSR_PIC_LVT_TIMER : CommonMsr.h
  • MSR_PIC_MSG_CONTROL : CommonMsr.h
  • MSR_PIC_PROCESSOR_PRIORITY : CommonMsr.h
  • MSR_PIC_SPURIOUS_INTERRUPT : CommonMsr.h
  • MSR_PIC_TASK_PRIORITY : CommonMsr.h
  • MSR_PIC_TIMER_CURRENT_COUNT_REG : CommonMsr.h
  • MSR_PIC_TIMER_DIVIDE_CONFIG_REG : CommonMsr.h
  • MSR_PIC_TIMER_INITIAL_COUNT_REG : CommonMsr.h
  • MSR_PIC_TMR_DWORD_0_0 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_1_1 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_2_2 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_3_3 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_4_4 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_5_5 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_6_6 : CommonMsr.h
  • MSR_PIC_TMR_DWORD_7_7 : CommonMsr.h
  • MSR_PKG_GT_AND_IA_OVERLAP : CommonMsr.h
  • MSR_PKG_GT_C0_ANY : CommonMsr.h
  • MSR_PKG_IA_C0_ANY : CommonMsr.h
  • MSR_PKG_IA_C0_ANY_SUM : CommonMsr.h
  • MSR_PKG_SDC_CONFIG_CONTROL : CommonMsr.h
  • MSR_PKG_SDC_CTL : ArchMsr.h
  • MSR_PKG_SDC_DEEP_RESIDENCY : CommonMsr.h
  • MSR_PKG_SDC_SHALLOW_RESIDENCY : CommonMsr.h
  • MSR_PL0_SSP : ArchMsr.h
  • MSR_PL1_SSP : ArchMsr.h
  • MSR_PL2_SSP : ArchMsr.h
  • MSR_PL3_CONTROL : CommonMsr.h
  • MSR_PL3_SSP : ArchMsr.h
  • MSR_PLAT_FRMW_PROT_CTRL : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_0 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_1 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_2 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_HASH_3 : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_TRIG_PARAM : CommonMsr.h
  • MSR_PLAT_FRMW_PROT_TRIGGER : CommonMsr.h
  • MSR_PLATFORM_ENERGY_STATUS : CommonMsr.h
  • MSR_PLATFORM_ID : ArchMsr.h
  • MSR_PLATFORM_POWER_LIMIT : CommonMsr.h
  • MSR_PM_CTL1 : ArchMsr.h
  • MSR_PMG_IO_CAPTURE_BASE : CommonMsr.h
  • MSR_POWER_CTL : CommonMsr.h
  • MSR_POWERON : CommonMsr.h
  • MSR_PPIN : CommonMsr.h
  • MSR_PPIN_CTL : CommonMsr.h
  • MSR_PPPE_DOORBELL_EXIT_BITMAP : CommonMsr.h
  • MSR_PQOS_CDP_ENABLE : CommonMsr.h
  • MSR_PREDICT_CMD : ArchMsr.h
  • MSR_PRID_0_0 : CommonMsr.h
  • MSR_PRID_1_1 : CommonMsr.h
  • MSR_PRIMARY_PLANE_ENERGY_STATUS : CommonMsr.h
  • MSR_PRIMARY_PLANE_OVERFLOW_STATUS : CommonMsr.h
  • MSR_PRIMARY_PLANE_TURBO_POWER_LIMIT : CommonMsr.h
  • MSR_PRIMARY_PLANE_TURBO_POWER_POLICY : CommonMsr.h
  • MSR_PRIVACY_CONTROL : ArchMsr.h
  • MSR_PRMRR_BASE_0 : CommonMsr.h
  • MSR_PRMRR_BASE_1_1 : CommonMsr.h
  • MSR_PRMRR_BASE_2_2 : CommonMsr.h
  • MSR_PRMRR_BASE_3_3 : CommonMsr.h
  • MSR_PRMRR_BASE_4_4 : CommonMsr.h
  • MSR_PRMRR_BASE_5_5 : CommonMsr.h
  • MSR_PRMRR_BASE_6_6 : CommonMsr.h
  • MSR_PRMRR_BASE_7_7 : CommonMsr.h
  • MSR_PRMRR_MASK : CommonMsr.h
  • MSR_PRMRR_VALID_CONFIG : CommonMsr.h
  • MSR_PROBE_CHANGE_PG : CommonMsr.h
  • MSR_PROBE_CPL : CommonMsr.h
  • MSR_PROBE_GP_REG : CommonMsr.h
  • MSR_PROBE_LT_SPC_CYC : CommonMsr.h
  • MSR_PROBE_MMX2_REG : CommonMsr.h
  • MSR_PROBE_MODE_DR : CommonMsr.h
  • MSR_PROBE_MODE_PPPE_REDIRECTION : CommonMsr.h
  • MSR_PROBE_MODE_PPPE_REDIRECTION_INFO : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_10_10 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_11_11 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_12_12 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_1_1 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_2_2 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_3_3 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_4_4 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_5_5 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_6_6 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_7_7 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_8_8 : CommonMsr.h
  • MSR_PROBE_MODE_RESERVED_9_9 : CommonMsr.h
  • MSR_PROBE_MODE_VMEXIT_REDIRECTION_REASON : CommonMsr.h
  • MSR_PROBE_MODE_VMX_REDIRECTION_INFO : CommonMsr.h
  • MSR_PROBE_PL_REG : CommonMsr.h
  • MSR_PROBE_SEG_REG_1 : CommonMsr.h
  • MSR_PROBE_SEG_REG_3 : CommonMsr.h
  • MSR_PROBE_TLB_FLUSH : CommonMsr.h
  • MSR_PROBE_TO_FROM_PDR : CommonMsr.h
  • MSR_PROBE_VMX_POINTER : CommonMsr.h
  • MSR_PSMI_BASE : CommonMsr.h
  • MSR_PST_CONFIG_CONTROL : CommonMsr.h
  • MSR_QLRU_CONFIG : CommonMsr.h
  • MSR_QMC : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_0_0 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_10_10 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_11_11 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_12_12 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_13_13 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_14_14 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_1_1 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_2_2 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_3_3 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_4_4 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_5_5 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_6_6 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_7_7 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_8_8 : CommonMsr.h
  • MSR_QOS_EXT_BW_THRTL_9_9 : CommonMsr.h
  • MSR_QOSEVTSEL : CommonMsr.h
  • MSR_QUIESCE_CTL1 : CommonMsr.h
  • MSR_QUIESCE_CTL2 : CommonMsr.h
  • MSR_REGISTER_0 : CommonMsr.h
  • MSR_REGISTER_1 : CommonMsr.h
  • MSR_REGISTER_10 : CommonMsr.h
  • MSR_REGISTER_11 : CommonMsr.h
  • MSR_REGISTER_12 : CommonMsr.h
  • MSR_REGISTER_13 : CommonMsr.h
  • MSR_REGISTER_2 : CommonMsr.h
  • MSR_REGISTER_3 : CommonMsr.h
  • MSR_REGISTER_4 : CommonMsr.h
  • MSR_REGISTER_5 : CommonMsr.h
  • MSR_REGISTER_6 : CommonMsr.h
  • MSR_REGISTER_7 : CommonMsr.h
  • MSR_REGISTER_8 : CommonMsr.h
  • MSR_REGISTER_9 : CommonMsr.h
  • MSR_RESIDENCY_CTR : CommonMsr.h
  • MSR_RESIDENCY_CTR_CONFIG : CommonMsr.h
  • MSR_RESIDENCY_CTR_SELECT : CommonMsr.h
  • MSR_ROP_COUNTER_CONFIG_0 : CommonMsr.h
  • MSR_ROP_COUNTER_CONFIG_1 : CommonMsr.h
  • MSR_ROP_DETECT_CAPABILITIES : CommonMsr.h
  • MSR_ROP_DETECT_CTRL : CommonMsr.h
  • MSR_ROP_DETECT_STATUS : CommonMsr.h
  • MSR_ROP_EVENT_FILTER0 : CommonMsr.h
  • MSR_ROP_EVENT_FILTER0_DATA : CommonMsr.h
  • MSR_RTIT_ADDR0_A : ArchMsr.h
  • MSR_RTIT_ADDR0_B : ArchMsr.h
  • MSR_RTIT_ADDR1_A : ArchMsr.h
  • MSR_RTIT_ADDR1_B : ArchMsr.h
  • MSR_RTIT_CR3_MATCH : ArchMsr.h
  • MSR_RTIT_CTL : ArchMsr.h
  • MSR_RTIT_OUTPUT_BASE : ArchMsr.h
  • MSR_RTIT_OUTPUT_MASK_PTRS : ArchMsr.h
  • MSR_RTIT_STATUS : ArchMsr.h
  • MSR_S_CET : ArchMsr.h
  • MSR_SE_EPOCH_0 : CommonMsr.h
  • MSR_SE_EPOCH_1 : CommonMsr.h
  • MSR_SE_RDINFO_CMD : CommonMsr.h
  • MSR_SECONDARY_PLANE_ENERGY_STATUS : CommonMsr.h
  • MSR_SECONDARY_PLANE_TURBO_POWER_LIMIT : CommonMsr.h
  • MSR_SECONDARY_PLANE_TURBO_POWER_POLICY : CommonMsr.h
  • MSR_SECS_SID : CommonMsr.h
  • MSR_SELF_IPI : CommonMsr.h
  • MSR_SF_QOS_MASK_0_0 : ArchMsr.h
  • MSR_SF_QOS_MASK_10_10 : ArchMsr.h
  • MSR_SF_QOS_MASK_11_11 : ArchMsr.h
  • MSR_SF_QOS_MASK_12_12 : ArchMsr.h
  • MSR_SF_QOS_MASK_13_13 : ArchMsr.h
  • MSR_SF_QOS_MASK_14_14 : ArchMsr.h
  • MSR_SF_QOS_MASK_15_15 : ArchMsr.h
  • MSR_SF_QOS_MASK_1_1 : ArchMsr.h
  • MSR_SF_QOS_MASK_2_2 : ArchMsr.h
  • MSR_SF_QOS_MASK_3_3 : ArchMsr.h
  • MSR_SF_QOS_MASK_4_4 : ArchMsr.h
  • MSR_SF_QOS_MASK_5_5 : ArchMsr.h
  • MSR_SF_QOS_MASK_6_6 : ArchMsr.h
  • MSR_SF_QOS_MASK_7_7 : ArchMsr.h
  • MSR_SF_QOS_MASK_8_8 : ArchMsr.h
  • MSR_SF_QOS_MASK_9_9 : ArchMsr.h
  • MSR_SFMASK : ArchMsr.h
  • MSR_SGX_DEBUG_MODE : CommonMsr.h
  • MSR_SGX_RAS : CommonMsr.h
  • MSR_SGX_RDPCHSGXID_0 : CommonMsr.h
  • MSR_SGX_RDPCHSGXID_1 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH0 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH1 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH2 : CommonMsr.h
  • MSR_SGXLEPUBKEYHASH3 : CommonMsr.h
  • MSR_SMBASE_ADDR : CommonMsr.h
  • MSR_SMI_COUNT : CommonMsr.h
  • MSR_SMM_CFG_OPTIONS : CommonMsr.h
  • MSR_SMM_CLEAR_SMI : CommonMsr.h
  • MSR_SMM_ENABLE_MASK : CommonMsr.h
  • MSR_SMM_ENABLE_MATCH : CommonMsr.h
  • MSR_SMM_FEATURE_CONTROL : CommonMsr.h
  • MSR_SMM_MCA_CAP : CommonMsr.h
  • MSR_SMM_PROT_MODE_BASE : CommonMsr.h
  • MSR_SMM_SAVE_CONTROL : CommonMsr.h
  • MSR_SMM_SUPOVR_STATE_LOCK : CommonMsr.h
  • MSR_SMRAM_BNDCFGS : CommonMsr.h
  • MSR_SMRAM_CR0 : CommonMsr.h
  • MSR_SMRAM_CR3 : CommonMsr.h
  • MSR_SMRAM_CR4 : CommonMsr.h
  • MSR_SMRAM_CS_ES : CommonMsr.h
  • MSR_SMRAM_DR6 : CommonMsr.h
  • MSR_SMRAM_DR7 : CommonMsr.h
  • MSR_SMRAM_DS_SS : CommonMsr.h
  • MSR_SMRAM_EFER : CommonMsr.h
  • MSR_SMRAM_EFLAGS : CommonMsr.h
  • MSR_SMRAM_EPTP : CommonMsr.h
  • MSR_SMRAM_EPTP_ENABLE : CommonMsr.h
  • MSR_SMRAM_EVENT_CTL_HLT_IO : CommonMsr.h
  • MSR_SMRAM_GDTR_BASE : CommonMsr.h
  • MSR_SMRAM_GS_FS : CommonMsr.h
  • MSR_SMRAM_IDTR_BASE : CommonMsr.h
  • MSR_SMRAM_IEDBASE : CommonMsr.h
  • MSR_SMRAM_IO_MEM_ADDR : CommonMsr.h
  • MSR_SMRAM_IO_RCX : CommonMsr.h
  • MSR_SMRAM_IO_RDI : CommonMsr.h
  • MSR_SMRAM_IO_RIP : CommonMsr.h
  • MSR_SMRAM_IO_RSI : CommonMsr.h
  • MSR_SMRAM_IOMISCINFO : CommonMsr.h
  • MSR_SMRAM_LDTR_BASE : CommonMsr.h
  • MSR_SMRAM_R10 : CommonMsr.h
  • MSR_SMRAM_R11 : CommonMsr.h
  • MSR_SMRAM_R12 : CommonMsr.h
  • MSR_SMRAM_R13 : CommonMsr.h
  • MSR_SMRAM_R14 : CommonMsr.h
  • MSR_SMRAM_R15 : CommonMsr.h
  • MSR_SMRAM_R8 : CommonMsr.h
  • MSR_SMRAM_R9 : CommonMsr.h
  • MSR_SMRAM_RAX : CommonMsr.h
  • MSR_SMRAM_RBP : CommonMsr.h
  • MSR_SMRAM_RBX : CommonMsr.h
  • MSR_SMRAM_RCX : CommonMsr.h
  • MSR_SMRAM_RDI : CommonMsr.h
  • MSR_SMRAM_RDX : CommonMsr.h
  • MSR_SMRAM_RIP : CommonMsr.h
  • MSR_SMRAM_RSI : CommonMsr.h
  • MSR_SMRAM_RSP : CommonMsr.h
  • MSR_SMRAM_SMBASE : CommonMsr.h
  • MSR_SMRAM_SMM_REVID : CommonMsr.h
  • MSR_SMRAM_TR_LDTR : CommonMsr.h
  • MSR_SMRR2_BASE : CommonMsr.h
  • MSR_SMRR2_MASK : CommonMsr.h
  • MSR_SMRR_BASE : CommonMsr.h
  • MSR_SMRR_MASK : CommonMsr.h
  • MSR_SNC_CONFIG : CommonMsr.h
  • MSR_SNC_RANGE0_BASE : CommonMsr.h
  • MSR_SNC_RANGE1_BASE : CommonMsr.h
  • MSR_SNC_RANGE2_BASE : CommonMsr.h
  • MSR_SNC_RANGE3_BASE : CommonMsr.h
  • MSR_SNC_RANGE4_BASE : CommonMsr.h
  • MSR_SNC_UPPER_BASE : CommonMsr.h
  • MSR_SOCKET_ID : CommonMsr.h
  • MSR_SPCL_CHIPSET_USAGE : CommonMsr.h
  • MSR_SPCL_UNCORE_USAGE : CommonMsr.h
  • MSR_SPEC_CTRL : ArchMsr.h
  • MSR_SSKU_CMD : CommonMsr.h
  • MSR_SSKU_DATA : CommonMsr.h
  • MSR_SSKU_ENFORCE : CommonMsr.h
  • MSR_SSKU_SMM_ADDR : CommonMsr.h
  • MSR_SSKU_SMM_DATA : CommonMsr.h
  • MSR_STAR : ArchMsr.h
  • MSR_SUPPRESS_SHUTDOWN : CommonMsr.h
  • MSR_SW_LTR_OVRD : CommonMsr.h
  • MSR_SYSENTER_CS : ArchMsr.h
  • MSR_SYSENTER_EIP : ArchMsr.h
  • MSR_SYSENTER_ESP : ArchMsr.h
  • MSR_TASK_SWITCH_OR_PROBE_MODE_MISC : CommonMsr.h
  • MSR_TASK_SWITCH_OR_SMI_RIP : CommonMsr.h
  • MSR_TCS_PA : CommonMsr.h
  • MSR_TEMPERATURE_TARGET : CommonMsr.h
  • MSR_THD_LOGICAL_ID : CommonMsr.h
  • MSR_THERM_EVENT_FFM : CommonMsr.h
  • MSR_THERM_INTERRUPT : ArchMsr.h
  • MSR_THERM_STATUS : ArchMsr.h
  • MSR_THREAD_INFO : CommonMsr.h
  • MSR_THREAD_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_THREAD_SMI_ERR_SRC : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_0_0 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_1_1 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_13_BIT_SPARE_2_2 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_0_0 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_10_10 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_11_11 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_12_12 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_13_13 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_1_1 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_2_2 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_3_3 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_4_4 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_5_5 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_6_6 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_7_7 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_8_8 : CommonMsr.h
  • MSR_THREAD_SPECIFIC_SPARE_9_9 : CommonMsr.h
  • MSR_THREAD_STALL_COUNTER : CommonMsr.h
  • MSR_THREAD_SW_DEFEATURE : CommonMsr.h
  • MSR_TIME_STAMP_COUNTER : ArchMsr.h
  • MSR_TIO_COPY_ENCRYPT : CommonMsr.h
  • MSR_TIO_DEBUG_STATUS : CommonMsr.h
  • MSR_TIO_PM_DEBUG_STATUS : CommonMsr.h
  • MSR_TIO_PRM_CLEANUP : CommonMsr.h
  • MSR_TIO_UNWRAP : CommonMsr.h
  • MSR_TIORR_PHYSBASE : CommonMsr.h
  • MSR_TIORR_PHYSMASK : CommonMsr.h
  • MSR_TME_ACTIVATE : ArchMsr.h
  • MSR_TME_CAPABILITY : ArchMsr.h
  • MSR_TME_EXCLUDE_BASE : ArchMsr.h
  • MSR_TME_EXCLUDE_MASK : ArchMsr.h
  • MSR_TMPDR6 : CommonMsr.h
  • MSR_TSC_AUX : ArchMsr.h
  • MSR_TSC_DEADLINE : ArchMsr.h
  • MSR_TSC_THREAD_OFFSET : ArchMsr.h
  • MSR_TURBO_ACTIVATION_RATIO : CommonMsr.h
  • MSR_TURBO_RATIO_LIMIT : CpuRegs.h
  • MSR_TURBO_RATIO_LIMIT_CORES : CommonMsr.h
  • MSR_U_CET : ArchMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL0 : CommonMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MASK_CTL1 : CommonMsr.h
  • MSR_UBOX_PMON_EVENT_NCDEC_MATCH_ADDR : CommonMsr.h
  • MSR_ULI_TARGET_RIP : CommonMsr.h
  • MSR_ULI_VECTOR_INFO : CommonMsr.h
  • MSR_UNCORE_PERF_STATUS : CommonMsr.h
  • MSR_UNCORE_RATIO_LIMIT : CommonMsr.h
  • MSR_UNCORE_SMI_ERR_INJ_CONTROL : CommonMsr.h
  • MSR_UNCORE_SMI_ERR_SRC : CommonMsr.h
  • MSR_UNCORE_SPARE_0_0 : CommonMsr.h
  • MSR_UNCORE_SPARE_10_10 : CommonMsr.h
  • MSR_UNCORE_SPARE_11_11 : CommonMsr.h
  • MSR_UNCORE_SPARE_12_12 : CommonMsr.h
  • MSR_UNCORE_SPARE_13_13 : CommonMsr.h
  • MSR_UNCORE_SPARE_1_1 : CommonMsr.h
  • MSR_UNCORE_SPARE_2_2 : CommonMsr.h
  • MSR_UNCORE_SPARE_3_3 : CommonMsr.h
  • MSR_UNCORE_SPARE_4_4 : CommonMsr.h
  • MSR_UNCORE_SPARE_5_5 : CommonMsr.h
  • MSR_UNCORE_SPARE_6_6 : CommonMsr.h
  • MSR_UNCORE_SPARE_7_7 : CommonMsr.h
  • MSR_UNCORE_SPARE_8_8 : CommonMsr.h
  • MSR_UNCORE_SPARE_9_9 : CommonMsr.h
  • MSR_VIRTUAL_APIC_0_0 : CommonMsr.h
  • MSR_VIRTUAL_APIC_100_100 : CommonMsr.h
  • MSR_VIRTUAL_APIC_101_101 : CommonMsr.h
  • MSR_VIRTUAL_APIC_102_102 : CommonMsr.h
  • MSR_VIRTUAL_APIC_103_103 : CommonMsr.h
  • MSR_VIRTUAL_APIC_104_104 : CommonMsr.h
  • MSR_VIRTUAL_APIC_105_105 : CommonMsr.h
  • MSR_VIRTUAL_APIC_106_106 : CommonMsr.h
  • MSR_VIRTUAL_APIC_107_107 : CommonMsr.h
  • MSR_VIRTUAL_APIC_108_108 : CommonMsr.h
  • MSR_VIRTUAL_APIC_109_109 : CommonMsr.h
  • MSR_VIRTUAL_APIC_10_10 : CommonMsr.h
  • MSR_VIRTUAL_APIC_110_110 : CommonMsr.h
  • MSR_VIRTUAL_APIC_111_111 : CommonMsr.h
  • MSR_VIRTUAL_APIC_112_112 : CommonMsr.h
  • MSR_VIRTUAL_APIC_113_113 : CommonMsr.h
  • MSR_VIRTUAL_APIC_114_114 : CommonMsr.h
  • MSR_VIRTUAL_APIC_115_115 : CommonMsr.h
  • MSR_VIRTUAL_APIC_116_116 : CommonMsr.h
  • MSR_VIRTUAL_APIC_117_117 : CommonMsr.h
  • MSR_VIRTUAL_APIC_118_118 : CommonMsr.h
  • MSR_VIRTUAL_APIC_119_119 : CommonMsr.h
  • MSR_VIRTUAL_APIC_11_11 : CommonMsr.h
  • MSR_VIRTUAL_APIC_120_120 : CommonMsr.h
  • MSR_VIRTUAL_APIC_121_121 : CommonMsr.h
  • MSR_VIRTUAL_APIC_122_122 : CommonMsr.h
  • MSR_VIRTUAL_APIC_123_123 : CommonMsr.h
  • MSR_VIRTUAL_APIC_124_124 : CommonMsr.h
  • MSR_VIRTUAL_APIC_125_125 : CommonMsr.h
  • MSR_VIRTUAL_APIC_126_126 : CommonMsr.h
  • MSR_VIRTUAL_APIC_127_127 : CommonMsr.h
  • MSR_VIRTUAL_APIC_128_128 : CommonMsr.h
  • MSR_VIRTUAL_APIC_129_129 : CommonMsr.h
  • MSR_VIRTUAL_APIC_12_12 : CommonMsr.h
  • MSR_VIRTUAL_APIC_130_130 : CommonMsr.h
  • MSR_VIRTUAL_APIC_131_131 : CommonMsr.h
  • MSR_VIRTUAL_APIC_132_132 : CommonMsr.h
  • MSR_VIRTUAL_APIC_133_133 : CommonMsr.h
  • MSR_VIRTUAL_APIC_134_134 : CommonMsr.h
  • MSR_VIRTUAL_APIC_135_135 : CommonMsr.h
  • MSR_VIRTUAL_APIC_136_136 : CommonMsr.h
  • MSR_VIRTUAL_APIC_137_137 : CommonMsr.h
  • MSR_VIRTUAL_APIC_138_138 : CommonMsr.h
  • MSR_VIRTUAL_APIC_139_139 : CommonMsr.h
  • MSR_VIRTUAL_APIC_13_13 : CommonMsr.h
  • MSR_VIRTUAL_APIC_140_140 : CommonMsr.h
  • MSR_VIRTUAL_APIC_141_141 : CommonMsr.h
  • MSR_VIRTUAL_APIC_142_142 : CommonMsr.h
  • MSR_VIRTUAL_APIC_143_143 : CommonMsr.h
  • MSR_VIRTUAL_APIC_144_144 : CommonMsr.h
  • MSR_VIRTUAL_APIC_145_145 : CommonMsr.h
  • MSR_VIRTUAL_APIC_146_146 : CommonMsr.h
  • MSR_VIRTUAL_APIC_147_147 : CommonMsr.h
  • MSR_VIRTUAL_APIC_148_148 : CommonMsr.h
  • MSR_VIRTUAL_APIC_149_149 : CommonMsr.h
  • MSR_VIRTUAL_APIC_14_14 : CommonMsr.h
  • MSR_VIRTUAL_APIC_150_150 : CommonMsr.h
  • MSR_VIRTUAL_APIC_151_151 : CommonMsr.h
  • MSR_VIRTUAL_APIC_152_152 : CommonMsr.h
  • MSR_VIRTUAL_APIC_153_153 : CommonMsr.h
  • MSR_VIRTUAL_APIC_154_154 : CommonMsr.h
  • MSR_VIRTUAL_APIC_155_155 : CommonMsr.h
  • MSR_VIRTUAL_APIC_156_156 : CommonMsr.h
  • MSR_VIRTUAL_APIC_157_157 : CommonMsr.h
  • MSR_VIRTUAL_APIC_158_158 : CommonMsr.h
  • MSR_VIRTUAL_APIC_159_159 : CommonMsr.h
  • MSR_VIRTUAL_APIC_15_15 : CommonMsr.h
  • MSR_VIRTUAL_APIC_160_160 : CommonMsr.h
  • MSR_VIRTUAL_APIC_161_161 : CommonMsr.h
  • MSR_VIRTUAL_APIC_162_162 : CommonMsr.h
  • MSR_VIRTUAL_APIC_163_163 : CommonMsr.h
  • MSR_VIRTUAL_APIC_164_164 : CommonMsr.h
  • MSR_VIRTUAL_APIC_165_165 : CommonMsr.h
  • MSR_VIRTUAL_APIC_166_166 : CommonMsr.h
  • MSR_VIRTUAL_APIC_167_167 : CommonMsr.h
  • MSR_VIRTUAL_APIC_168_168 : CommonMsr.h
  • MSR_VIRTUAL_APIC_169_169 : CommonMsr.h
  • MSR_VIRTUAL_APIC_16_16 : CommonMsr.h
  • MSR_VIRTUAL_APIC_170_170 : CommonMsr.h
  • MSR_VIRTUAL_APIC_171_171 : CommonMsr.h
  • MSR_VIRTUAL_APIC_172_172 : CommonMsr.h
  • MSR_VIRTUAL_APIC_173_173 : CommonMsr.h
  • MSR_VIRTUAL_APIC_174_174 : CommonMsr.h
  • MSR_VIRTUAL_APIC_175_175 : CommonMsr.h
  • MSR_VIRTUAL_APIC_176_176 : CommonMsr.h
  • MSR_VIRTUAL_APIC_177_177 : CommonMsr.h
  • MSR_VIRTUAL_APIC_178_178 : CommonMsr.h
  • MSR_VIRTUAL_APIC_179_179 : CommonMsr.h
  • MSR_VIRTUAL_APIC_17_17 : CommonMsr.h
  • MSR_VIRTUAL_APIC_180_180 : CommonMsr.h
  • MSR_VIRTUAL_APIC_181_181 : CommonMsr.h
  • MSR_VIRTUAL_APIC_182_182 : CommonMsr.h
  • MSR_VIRTUAL_APIC_183_183 : CommonMsr.h
  • MSR_VIRTUAL_APIC_184_184 : CommonMsr.h
  • MSR_VIRTUAL_APIC_185_185 : CommonMsr.h
  • MSR_VIRTUAL_APIC_186_186 : CommonMsr.h
  • MSR_VIRTUAL_APIC_187_187 : CommonMsr.h
  • MSR_VIRTUAL_APIC_188_188 : CommonMsr.h
  • MSR_VIRTUAL_APIC_189_189 : CommonMsr.h
  • MSR_VIRTUAL_APIC_18_18 : CommonMsr.h
  • MSR_VIRTUAL_APIC_190_190 : CommonMsr.h
  • MSR_VIRTUAL_APIC_191_191 : CommonMsr.h
  • MSR_VIRTUAL_APIC_192_192 : CommonMsr.h
  • MSR_VIRTUAL_APIC_193_193 : CommonMsr.h
  • MSR_VIRTUAL_APIC_194_194 : CommonMsr.h
  • MSR_VIRTUAL_APIC_195_195 : CommonMsr.h
  • MSR_VIRTUAL_APIC_196_196 : CommonMsr.h
  • MSR_VIRTUAL_APIC_197_197 : CommonMsr.h
  • MSR_VIRTUAL_APIC_198_198 : CommonMsr.h
  • MSR_VIRTUAL_APIC_199_199 : CommonMsr.h
  • MSR_VIRTUAL_APIC_19_19 : CommonMsr.h
  • MSR_VIRTUAL_APIC_1_1 : CommonMsr.h
  • MSR_VIRTUAL_APIC_200_200 : CommonMsr.h
  • MSR_VIRTUAL_APIC_201_201 : CommonMsr.h
  • MSR_VIRTUAL_APIC_202_202 : CommonMsr.h
  • MSR_VIRTUAL_APIC_203_203 : CommonMsr.h
  • MSR_VIRTUAL_APIC_204_204 : CommonMsr.h
  • MSR_VIRTUAL_APIC_205_205 : CommonMsr.h
  • MSR_VIRTUAL_APIC_206_206 : CommonMsr.h
  • MSR_VIRTUAL_APIC_207_207 : CommonMsr.h
  • MSR_VIRTUAL_APIC_208_208 : CommonMsr.h
  • MSR_VIRTUAL_APIC_209_209 : CommonMsr.h
  • MSR_VIRTUAL_APIC_20_20 : CommonMsr.h
  • MSR_VIRTUAL_APIC_210_210 : CommonMsr.h
  • MSR_VIRTUAL_APIC_211_211 : CommonMsr.h
  • MSR_VIRTUAL_APIC_21_21 : CommonMsr.h
  • MSR_VIRTUAL_APIC_22_22 : CommonMsr.h
  • MSR_VIRTUAL_APIC_23_23 : CommonMsr.h
  • MSR_VIRTUAL_APIC_24_24 : CommonMsr.h
  • MSR_VIRTUAL_APIC_25_25 : CommonMsr.h
  • MSR_VIRTUAL_APIC_26_26 : CommonMsr.h
  • MSR_VIRTUAL_APIC_27_27 : CommonMsr.h
  • MSR_VIRTUAL_APIC_28_28 : CommonMsr.h
  • MSR_VIRTUAL_APIC_29_29 : CommonMsr.h
  • MSR_VIRTUAL_APIC_2_2 : CommonMsr.h
  • MSR_VIRTUAL_APIC_30_30 : CommonMsr.h
  • MSR_VIRTUAL_APIC_31_31 : CommonMsr.h
  • MSR_VIRTUAL_APIC_32_32 : CommonMsr.h
  • MSR_VIRTUAL_APIC_33_33 : CommonMsr.h
  • MSR_VIRTUAL_APIC_34_34 : CommonMsr.h
  • MSR_VIRTUAL_APIC_35_35 : CommonMsr.h
  • MSR_VIRTUAL_APIC_36_36 : CommonMsr.h
  • MSR_VIRTUAL_APIC_37_37 : CommonMsr.h
  • MSR_VIRTUAL_APIC_38_38 : CommonMsr.h
  • MSR_VIRTUAL_APIC_39_39 : CommonMsr.h
  • MSR_VIRTUAL_APIC_3_3 : CommonMsr.h
  • MSR_VIRTUAL_APIC_40_40 : CommonMsr.h
  • MSR_VIRTUAL_APIC_41_41 : CommonMsr.h
  • MSR_VIRTUAL_APIC_42_42 : CommonMsr.h
  • MSR_VIRTUAL_APIC_43_43 : CommonMsr.h
  • MSR_VIRTUAL_APIC_44_44 : CommonMsr.h
  • MSR_VIRTUAL_APIC_45_45 : CommonMsr.h
  • MSR_VIRTUAL_APIC_46_46 : CommonMsr.h
  • MSR_VIRTUAL_APIC_47_47 : CommonMsr.h
  • MSR_VIRTUAL_APIC_48_48 : CommonMsr.h
  • MSR_VIRTUAL_APIC_49_49 : CommonMsr.h
  • MSR_VIRTUAL_APIC_4_4 : CommonMsr.h
  • MSR_VIRTUAL_APIC_50_50 : CommonMsr.h
  • MSR_VIRTUAL_APIC_51_51 : CommonMsr.h
  • MSR_VIRTUAL_APIC_52_52 : CommonMsr.h
  • MSR_VIRTUAL_APIC_53_53 : CommonMsr.h
  • MSR_VIRTUAL_APIC_54_54 : CommonMsr.h
  • MSR_VIRTUAL_APIC_55_55 : CommonMsr.h
  • MSR_VIRTUAL_APIC_56_56 : CommonMsr.h
  • MSR_VIRTUAL_APIC_57_57 : CommonMsr.h
  • MSR_VIRTUAL_APIC_58_58 : CommonMsr.h
  • MSR_VIRTUAL_APIC_59_59 : CommonMsr.h
  • MSR_VIRTUAL_APIC_5_5 : CommonMsr.h
  • MSR_VIRTUAL_APIC_60_60 : CommonMsr.h
  • MSR_VIRTUAL_APIC_61_61 : CommonMsr.h
  • MSR_VIRTUAL_APIC_62_62 : CommonMsr.h
  • MSR_VIRTUAL_APIC_63_63 : CommonMsr.h
  • MSR_VIRTUAL_APIC_64_64 : CommonMsr.h
  • MSR_VIRTUAL_APIC_65_65 : CommonMsr.h
  • MSR_VIRTUAL_APIC_66_66 : CommonMsr.h
  • MSR_VIRTUAL_APIC_67_67 : CommonMsr.h
  • MSR_VIRTUAL_APIC_68_68 : CommonMsr.h
  • MSR_VIRTUAL_APIC_69_69 : CommonMsr.h
  • MSR_VIRTUAL_APIC_6_6 : CommonMsr.h
  • MSR_VIRTUAL_APIC_70_70 : CommonMsr.h
  • MSR_VIRTUAL_APIC_71_71 : CommonMsr.h
  • MSR_VIRTUAL_APIC_72_72 : CommonMsr.h
  • MSR_VIRTUAL_APIC_73_73 : CommonMsr.h
  • MSR_VIRTUAL_APIC_74_74 : CommonMsr.h
  • MSR_VIRTUAL_APIC_75_75 : CommonMsr.h
  • MSR_VIRTUAL_APIC_76_76 : CommonMsr.h
  • MSR_VIRTUAL_APIC_77_77 : CommonMsr.h
  • MSR_VIRTUAL_APIC_78_78 : CommonMsr.h
  • MSR_VIRTUAL_APIC_79_79 : CommonMsr.h
  • MSR_VIRTUAL_APIC_7_7 : CommonMsr.h
  • MSR_VIRTUAL_APIC_80_80 : CommonMsr.h
  • MSR_VIRTUAL_APIC_81_81 : CommonMsr.h
  • MSR_VIRTUAL_APIC_82_82 : CommonMsr.h
  • MSR_VIRTUAL_APIC_83_83 : CommonMsr.h
  • MSR_VIRTUAL_APIC_84_84 : CommonMsr.h
  • MSR_VIRTUAL_APIC_85_85 : CommonMsr.h
  • MSR_VIRTUAL_APIC_86_86 : CommonMsr.h
  • MSR_VIRTUAL_APIC_87_87 : CommonMsr.h
  • MSR_VIRTUAL_APIC_88_88 : CommonMsr.h
  • MSR_VIRTUAL_APIC_89_89 : CommonMsr.h
  • MSR_VIRTUAL_APIC_8_8 : CommonMsr.h
  • MSR_VIRTUAL_APIC_90_90 : CommonMsr.h
  • MSR_VIRTUAL_APIC_91_91 : CommonMsr.h
  • MSR_VIRTUAL_APIC_92_92 : CommonMsr.h
  • MSR_VIRTUAL_APIC_93_93 : CommonMsr.h
  • MSR_VIRTUAL_APIC_94_94 : CommonMsr.h
  • MSR_VIRTUAL_APIC_95_95 : CommonMsr.h
  • MSR_VIRTUAL_APIC_96_96 : CommonMsr.h
  • MSR_VIRTUAL_APIC_97_97 : CommonMsr.h
  • MSR_VIRTUAL_APIC_98_98 : CommonMsr.h
  • MSR_VIRTUAL_APIC_99_99 : CommonMsr.h
  • MSR_VIRTUAL_APIC_9_9 : CommonMsr.h
  • MSR_VLW_CAPABILITY : CommonMsr.h
  • MSR_VMCS_CACHE_BASE : CommonMsr.h
  • MSR_VMSR_U2P_0_0 : CommonMsr.h
  • MSR_VMSR_U2P_1_1 : CommonMsr.h
  • MSR_VMSR_U2P_2_2 : CommonMsr.h
  • MSR_VMSR_U2P_3_3 : CommonMsr.h
  • MSR_VMX_AVRR_REMAP : CommonMsr.h
  • MSR_VMX_IO_EXIT_QUAL : CommonMsr.h
  • MSR_VMX_MSEG_BASE : CommonMsr.h
  • MSR_VMX_MSR_0 : ArchMsr.h
  • MSR_VMX_MSR_1 : ArchMsr.h
  • MSR_VMX_MSR_10 : ArchMsr.h
  • MSR_VMX_MSR_11 : ArchMsr.h
  • MSR_VMX_MSR_12 : ArchMsr.h
  • MSR_VMX_MSR_2 : ArchMsr.h
  • MSR_VMX_MSR_3 : ArchMsr.h
  • MSR_VMX_MSR_4 : ArchMsr.h
  • MSR_VMX_MSR_5 : ArchMsr.h
  • MSR_VMX_MSR_6 : ArchMsr.h
  • MSR_VMX_MSR_7 : ArchMsr.h
  • MSR_VMX_MSR_8 : ArchMsr.h
  • MSR_VMX_MSR_9 : ArchMsr.h
  • MSR_VMX_PLE_FIRST : CommonMsr.h
  • MSR_VMX_PLE_LAST : CommonMsr.h
  • MSR_VMX_PROCBASED_CTLS3 : ArchMsr.h
  • MSR_VMX_TRUE_ENTRY_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_EXIT_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_PINBASED_CTLS : ArchMsr.h
  • MSR_VMX_TRUE_PROCBASED_CTLS : ArchMsr.h
  • MSR_VMX_VMENTRY_AVRR_TBIT_MAILBOX : CommonMsr.h
  • MSR_VMX_VMFUNC_CTLS : ArchMsr.h
  • MSR_VMX_VPPR : CommonMsr.h
  • MSR_VR_CURRENT_CONFIG : CommonMsr.h
  • MSR_VR_MISC_CONFIG2 : CommonMsr.h
  • MSR_XCR0 : CommonMsr.h
  • MSR_XRSTOR_INFO : CommonMsr.h
  • MSR_XRSTOR_XCOMPACTION_VECTOR : CommonMsr.h
  • MSR_XU_MACROINSTRUCTION_ALIAS : CommonMsr.h
  • MSR_XU_RESERVED_10_10 : CommonMsr.h
  • MSR_XU_RESERVED_11_11 : CommonMsr.h
  • MSR_XU_RESERVED_12_12 : CommonMsr.h
  • MSR_XU_RESERVED_13_13 : CommonMsr.h
  • MSR_XU_RESERVED_14_14 : CommonMsr.h
  • MSR_XU_RESERVED_15_15 : CommonMsr.h
  • MSR_XU_RESERVED_16_16 : CommonMsr.h
  • MSR_XU_RESERVED_17_17 : CommonMsr.h
  • MSR_XU_RESERVED_18_18 : CommonMsr.h
  • MSR_XU_RESERVED_19_19 : CommonMsr.h
  • MSR_XU_RESERVED_1_1 : CommonMsr.h
  • MSR_XU_RESERVED_20_20 : CommonMsr.h
  • MSR_XU_RESERVED_21_21 : CommonMsr.h
  • MSR_XU_RESERVED_22_22 : CommonMsr.h
  • MSR_XU_RESERVED_23_23 : CommonMsr.h
  • MSR_XU_RESERVED_24_24 : CommonMsr.h
  • MSR_XU_RESERVED_25_25 : CommonMsr.h
  • MSR_XU_RESERVED_26_26 : CommonMsr.h
  • MSR_XU_RESERVED_27_27 : CommonMsr.h
  • MSR_XU_RESERVED_28_28 : CommonMsr.h
  • MSR_XU_RESERVED_29_29 : CommonMsr.h
  • MSR_XU_RESERVED_2_2 : CommonMsr.h
  • MSR_XU_RESERVED_30_30 : CommonMsr.h
  • MSR_XU_RESERVED_31_31 : CommonMsr.h
  • MSR_XU_RESERVED_3_3 : CommonMsr.h
  • MSR_XU_RESERVED_4_4 : CommonMsr.h
  • MSR_XU_RESERVED_5_5 : CommonMsr.h
  • MSR_XU_RESERVED_6_6 : CommonMsr.h
  • MSR_XU_RESERVED_7_7 : CommonMsr.h
  • MSR_XU_RESERVED_8_8 : CommonMsr.h
  • MSR_XU_RESERVED_9_9 : CommonMsr.h
  • MSR_XU_SMM_STATE : CommonMsr.h
  • MSR_XU_TIO_CF_INFO : CommonMsr.h
  • MSR_XU_TIO_CF_TABLE : CommonMsr.h
  • MSR_XU_VMX_CONTROL : CommonMsr.h
  • MSR_XUCODE_UCODE_COMMAND : CommonMsr.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- n -

  • N_ESPI_CFG_PCBC_BWPDS : PchRegsLpc.h
  • N_ESPI_CFG_PCBC_BWRE : PchRegsLpc.h
  • N_ESPI_CFG_PCBC_BWRS : PchRegsLpc.h
  • N_ESPI_PCR_FCERR_SLV0_FCFEE : PchRegsLpc.h
  • N_ESPI_PCR_FCERR_SLV0_FCNFEE : PchRegsLpc.h
  • N_ESPI_PCR_LNKERR_SLV0_LFET1E : PchRegsLpc.h
  • N_ESPI_PCR_LNKERR_SLV1_LFET1E : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCFEE : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCNFEE : PchRegsLpc.h
  • N_ESPI_PCR_PCERR_PCRMTARE : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT : PchRegsLpc.h
  • N_ESPI_PCR_SLV_CFG_REG_CTL_SID : PchRegsLpc.h
  • N_ESPI_PCR_VWERR_VWFEE : PchRegsLpc.h
  • N_ESPI_PCR_VWERR_VWNFEE : PchRegsLpc.h
  • N_ESPI_PCR_XERR_XFEE : PchRegsLpc.h
  • N_ESPI_PCR_XERR_XNFEE : PchRegsLpc.h
  • N_FLASH_FDBAR_CPUSL : FlashRegs.h
  • N_FLASH_FDBAR_FCPUSBA : FlashRegs.h
  • N_FLASH_FDBAR_FPSBA : FlashRegs.h
  • N_FLASH_FDBAR_FPSBA_REPR : FlashRegs.h
  • N_FLASH_FDBAR_NC : FlashRegs.h
  • N_FLASH_FDBAR_PCHSL : FlashRegs.h
  • N_FLASH_FLCOMP_COMP1 : FlashRegs.h
  • N_FLASH_UMAP1_MDTBA : FlashRegs.h
  • N_FLASH_UMAP1_MDTBA_REPR : FlashRegs.h
  • N_HDC_SUPPORT : CpuPowerMgmt.h
  • N_PCH_DMI15_PCR_CTRL1_L1PL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_G3L0SCTL_G3ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_G3L0SCTL_G3CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L0246TPOSTCO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L0246TPRECO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L1357TPOSTCO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_L1357TPRECO : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_MPC2_ORCE : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_MPC2_PLLWAIT : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIEL0SC_G1ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIEL0SC_G2ASL0SPL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIENFTS_G1CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PCIENFTS_G2CCNFTS : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_PWRCTL_RPSEWL : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS0TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS1TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS2TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPHWAWC_TS3TW : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPL0246TP : PchDmi15Regs.h
  • N_PCH_DMI15_PCR_UPL1357TP : PchDmi15Regs.h
  • N_PCH_DMI_PCR_GPMRX_GPMRL1 : PchDmiRegs.h
  • N_PCH_DMI_PCR_LCAP_EL0 : PchDmiRegs.h
  • N_PCH_DMI_PCR_LCAP_EL1 : PchDmiRegs.h
  • N_PCIE_SLCAP_PSN : PcieRegs.h
  • N_PCIE_SLCAP_SLS : PcieRegs.h
  • N_PCIE_SLCAP_SLV : PcieRegs.h
  • N_PMC_DEF_CPU_BCLK_CFG : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_CMD_ID : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_COMMAND : PmcRegs.h
  • N_PMC_PWRM_IPC_CMD_SIZE : PmcRegs.h
  • N_PMC_PWRM_PM_CFG2_PBOP : PmcRegs.h
  • N_SATA_MEM_AHCI_CAP_ISS : SataRegs.h
  • N_XHCI_CFG_XHCC2_WRREQSZCTRL : UsbRegs.h
  • N_XHCI_MEM_D0I2CTRL_MSID0I2PWT : UsbRegs.h
  • N_XHCI_MEM_D0I2SCH_ALARM_CTRL_D0I2IT : UsbRegs.h
  • N_XHCI_MEM_DBC_DBCCTL_DISC_RXD_CNT : UsbRegs.h
  • N_XHCI_MEM_XECP_SUPP_USBX_2_CPC : UsbRegs.h
  • NO_STRING_AVAILABLE : SiFvi.h , SiFviLib.h
  • NOP : IndustryStandardAsf.h
  • NPCR_NOTIFICATION_CMD : BupMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- o -

  • OEM_CAPS_1_RESERVED_BITMASK : MeSmbios.h
  • OEM_CAPS_2_TERMINAL_EMULATION_VT100PLUS : MeSmbios.h
  • OEM_CAPS_3_SECURE_ERASE_BIT_OFFSET : MeSmbios.h
  • OEM_CAPS_4_VPRO_TBT_DOCK_BIT_OFFSET : MeSmbios.h
  • ONE_CLICK_RECOVERY_PROTOCOL_REVISION : OneClickRecoveryProtocol.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- p -

  • PCH_ACPI_SMI_DISPATCH_REVISION : PchAcpiSmiDispatch.h
  • PCH_ESPI_SMI_DISPATCH_REVISION : PchEspiSmiDispatch.h
  • PCH_FIVR_CONFIG_REVISION : FivrConfig.h
  • PCH_FVI_STRING : SiFvi.h
  • PCH_GPIO_2_TIER_MASTER_GPE_NUMBER : GpioRegs.h
  • PCH_GPIO_NUM_SUPPORTED_GPIS : GpioRegs.h
  • PCH_MAX_DEVICE_INTERRUPT_CONFIG : InterruptConfig.h
  • PCH_MAX_ITSS_IPC_REGS : InterruptConfig.h
  • PCH_MAX_ITSS_IRQ_NUM : InterruptConfig.h
  • PCH_MAX_PXRC_CONFIG : InterruptConfig.h
  • PCH_PCIE_SMI_DISPATCH_REVISION : PchPcieSmiDispatch.h
  • PCH_PCR_ADDRESS : PchPcrLib.h
  • PCH_PCR_BOOT_SCRIPT_WRITE : PchPcrLib.h
  • PCH_PREMEM_POLICY_REVISION : PchPreMemPolicyCommon.h
  • PCH_SMI_DISPATCH_REVISION : PchSmiDispatch.h
  • PCH_SPI_SERVICES_REVISION : Protocol/Spi.h
  • PCH_TCO_SMI_DISPATCH_REVISION : PchTcoSmiDispatch.h
  • PCIE2TBT_CONNECT_TOPOLOGY_COMMAND : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_GO2SX : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_GO2SX_NO_WAKE : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_SSID_SVID_CFG : TbtMailBoxCmdDefinition.h
  • PCIE2TBT_SX_EXIT_TBT_CONNECTED : TbtMailBoxCmdDefinition.h
  • PEI_MR_SMRAM_ABSEG_MASK : MemoryConfig.h
  • PEI_TPM_INITIALIZATION_DONE_PPI_GUID : TpmInitialized.h
  • PEI_TPM_INITIALIZED_PPI_GUID : TpmInitialized.h
  • PERIPHERAL_EMBEDDED_CONTROLLER : IntelAsfExtensions.h
  • PLATFORM_ME_HOOK_PROTOCOL_REVISION : PlatformMeHook.h
  • PPM_C1 : CpuPowerMgmt.h
  • PPM_C10 : CpuPowerMgmt.h
  • PPM_C1E : CpuPowerMgmt.h
  • PPM_C6 : CpuPowerMgmt.h
  • PPM_C7 : CpuPowerMgmt.h
  • PPM_C7S : CpuPowerMgmt.h
  • PPM_C8 : CpuPowerMgmt.h
  • PPM_C9 : CpuPowerMgmt.h
  • PPM_C_STATES : CpuPowerMgmt.h
  • PPM_CD : CpuPowerMgmt.h
  • PPM_CMP : CpuPowerMgmt.h
  • PPM_EEPST : CpuPowerMgmt.h
  • PPM_EIST : CpuPowerMgmt.h
  • PPM_HWP : CpuPowerMgmt.h
  • PPM_MWAIT_EXT : CpuPowerMgmt.h
  • PPM_OC_UNLOCKED : CpuPowerMgmt.h
  • PPM_TIMED_MWAIT : CpuPowerMgmt.h
  • PPM_TM : CpuPowerMgmt.h
  • PPM_TSTATE_FINE_GRAINED : CpuPowerMgmt.h
  • PPM_TSTATES : CpuPowerMgmt.h
  • PPM_TURBO : CpuPowerMgmt.h
  • PPM_TURBO_BOOST_MAX : CpuPowerMgmt.h
  • PSL_MAJOR_VERSION : BiosGuard.h
  • PSL_MINOR_VERSION : BiosGuard.h
  • PWD_CHANGE_CMD : MkhiMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- r -

  • R_ACPI_IO_DEVTRAP_STS : PmcRegs.h
  • R_ACPI_IO_GPE0_EN_127_96 : PmcRegs.h
  • R_ACPI_IO_GPE0_STS_127_96 : PmcRegs.h
  • R_ACPI_IO_GPE0_STS_31_0 : PmcRegs.h
  • R_ACPI_IO_GPE_CTRL : PmcRegs.h
  • R_ACPI_IO_OC_WDT_CTL : PmcRegs.h
  • R_ACPI_IO_PM1_CNT : PmcRegs.h
  • R_ACPI_IO_PM1_TMR : PmcRegs.h
  • R_ACPI_IO_SMI_EN : PmcRegs.h
  • R_ACPI_IO_SMI_STS : PmcRegs.h
  • R_ACPI_IO_THERM_TIMER_DELAY : PmcRegs.h
  • R_BASE_ADDRESS_OFFSET_0 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_1 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_2 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_3 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_4 : PcieRegs.h
  • R_BASE_ADDRESS_OFFSET_5 : PcieRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_2 : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CAP : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CAP_2 : CnviRegs.h
  • R_CNVI_CFG_WIFI_GIO_DEV_CTRL : CnviRegs.h
  • R_CNVI_CFG_WIFI_PMCSR : CnviRegs.h
  • R_CNVI_PCR_WIFI_WIDGET_CONTROL : CnviRegs.h
  • R_CPU_XHCI_MEM_DAP_ESS_PORT_CONTROL1 : UsbRegs.h
  • R_ESPI_CFG_PCBC : PchRegsLpc.h
  • R_ESPI_PCR_CFG_VAL : PchRegsLpc.h
  • R_ESPI_PCR_FCERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_LNKERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_LNKERR_SLV1 : PchRegsLpc.h
  • R_ESPI_PCR_PCERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_PCERR_SLV1 : PchRegsLpc.h
  • R_ESPI_PCR_SLV_CFG_REG_CTL : PchRegsLpc.h
  • R_ESPI_PCR_SLV_CFG_REG_DATA : PchRegsLpc.h
  • R_ESPI_PCR_SOFTSTRAPS : PchRegsLpc.h
  • R_ESPI_PCR_VWERR_SLV0 : PchRegsLpc.h
  • R_ESPI_PCR_VWERR_SLV1 : PchRegsLpc.h
  • R_ESPI_SLAVE_CHA_0_CAP_AND_CONF : PchRegsLpc.h
  • R_FLASH_FCBA_FLCOMP : FlashRegs.h
  • R_FLASH_FDBAR_FLVALSIG : FlashRegs.h
  • R_FLASH_STRAP_DSCR_0 : FlashRegs.h
  • R_FLASH_STRAP_MMP0 : FlashRegs.h
  • R_FLASH_STRAP_SFDP : FlashRegs.h
  • R_FLASH_UMAP1 : FlashRegs.h
  • R_HER_BASE : HeciRegs.h
  • R_HERS : HeciRegs.h
  • R_ICC_PCR_MSKCKRQ : PchPcieRpRegs.h
  • R_ICC_PCR_TMCSRCCLK : PchPcieRpRegs.h
  • R_ICC_PCR_TMCSRCCLK2 : PchPcieRpRegs.h
  • R_LPC_CFG_BC : PchRegsLpc.h
  • R_LPC_CFG_BDE : PchRegsLpc.h
  • R_LT_UCS : PttPtpRegs.h
  • R_PCH_DMI14_PCR_DMIC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_DMIHWAWC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_G3L0SCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_IOSFSBCS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_IPCS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_LCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_REC : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_UEM : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V0CTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V0STS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V1CTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_V1STS : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_VMCTL : PchDmi14Regs.h
  • R_PCH_DMI14_PCR_VMSTS : PchDmi14Regs.h
  • R_PCH_DMI15_PCR_CCFG : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CEM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CTRL1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CTRL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_CWBCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_EEPPES : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_EQCFG1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_G3L0SCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_IOSFSBCS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L01EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0LFFS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P0P1PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P10PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P1P2P3PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P3P4PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P5P6PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P6P7P8PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L0P8P9PCM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L23EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L45EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_L67EC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCAP : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LCTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LSTS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO3 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_LTCO4 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_MPC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_MPC2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCE : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIECFG2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEDBG : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEL0SC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIENFTS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEPMECTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PCIEPMECTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL3 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PHYCTL4 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_PWRCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RPDCGEN : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RPPGEN : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RTPCL1 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_RTPCL2 : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_UEM : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_UPHWAWC : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V0CTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V0STS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V1CTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_V1STS : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_VMCTL : PchDmi15Regs.h
  • R_PCH_DMI15_PCR_VMSTS : PchDmi15Regs.h
  • R_PCH_DMI17_PCR_LCAP2 : PchDmi17Regs.h
  • R_PCH_DMI17_PCR_LCTL2 : PchDmi17Regs.h
  • R_PCH_DMI_PCR_GCS : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPIOR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_GPMR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_IOT4 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LCAP : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCBDE : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCGMR : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCIOD : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCIOE : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR1 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR2 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR3 : PchDmiRegs.h
  • R_PCH_DMI_PCR_LPCLGIR4 : PchDmiRegs.h
  • R_PCH_DMI_PCR_P2SBIOR : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR1DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR1E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR2DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR2E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR3DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR3E : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR4DID : PchDmiRegs.h
  • R_PCH_DMI_PCR_PCIEPAR4E : PchDmiRegs.h
  • R_PCH_DMI_PCR_SEGIR : PchDmiRegs.h
  • R_PCH_DMI_PCR_SEGMR : PchDmiRegs.h
  • R_PCH_DMI_PCR_TCOBASE : PchDmiRegs.h
  • R_PCH_DMI_PCR_TTTBARB : PchDmiRegs.h
  • R_PCH_DMI_PCR_TTTBARBH : PchDmiRegs.h
  • R_PCH_DMI_PCR_UCPR : PchDmiRegs.h
  • R_PCH_OPDMI14_PCR_LCFG : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_LCTL : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_LPMC : PchDmi14Regs.h
  • R_PCH_OPDMI14_PCR_STC : PchDmi14Regs.h
  • R_PCH_PCIE_CFG_EX_ACSECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_AECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_CES : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_DPCECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_L1SECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_EX_PTMECH : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_L1SCTL2 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMECFG : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMLLMT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPD : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC1 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC2 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC3 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC4 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMPSDC5 : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_PTMULMT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_TNPT : PchPcieRpRegs.h
  • R_PCH_PCIE_CFG_VC0CTL : PchPcieRpRegs.h
  • R_PCH_SPI_STRP_GBETSN_DIS : FlashRegs.h
  • R_PCH_SPI_STRP_THC_DIS : FlashRegs.h
  • R_PCH_XHCI_MEM_USB2PDO : UsbRegs.h
  • R_PCH_XHCI_MEM_USB3PDO : UsbRegs.h
  • R_PCI_BRIDGE_BNUM : PcieRegs.h
  • R_PCI_BRIDGE_IOBL : PcieRegs.h
  • R_PCI_BRIDGE_MBL : PcieRegs.h
  • R_PCI_BRIDGE_PMBL : PcieRegs.h
  • R_PCI_BRIDGE_PMBU32 : PcieRegs.h
  • R_PCI_BRIDGE_PMLU32 : PcieRegs.h
  • R_PCI_CARDBUS_BRIDGE_SVID : PcieRegs.h
  • R_PCIE_CAP_ID_OFFSET : PcieRegs.h
  • R_PCIE_CAP_NEXT_PRT_OFFSET : PcieRegs.h
  • R_PCIE_DCAP2_OFFSET : PcieRegs.h
  • R_PCIE_DCAP_OFFSET : PcieRegs.h
  • R_PCIE_DCTL2_OFFSET : PcieRegs.h
  • R_PCIE_DCTL_OFFSET : PcieRegs.h
  • R_PCIE_DSTS_OFFSET : PcieRegs.h
  • R_PCIE_EX_ACSCAPR_OFFSET : PcieRegs.h
  • R_PCIE_EX_L01EC_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCAP_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCTL1_OFFSET : PcieRegs.h
  • R_PCIE_EX_L1SCTL2_OFFSET : PcieRegs.h
  • R_PCIE_EX_L23EC_OFFSET : PcieRegs.h
  • R_PCIE_EX_LCTL3_OFFSET : PcieRegs.h
  • R_PCIE_EX_LES_OFFSET : PcieRegs.h
  • R_PCIE_EX_PTMCAP_OFFSET : PcieRegs.h
  • R_PCIE_EX_PTMCTL_OFFSET : PcieRegs.h
  • R_PCIE_EX_UEM_OFFSET : PcieRegs.h
  • R_PCIE_LCAP_OFFSET : PcieRegs.h
  • R_PCIE_LCTL2_OFFSET : PcieRegs.h
  • R_PCIE_LCTL_OFFSET : PcieRegs.h
  • R_PCIE_LSTS2_OFFSET : PcieRegs.h
  • R_PCIE_LSTS_OFFSET : PcieRegs.h
  • R_PCIE_PMC_OFFSET : PcieRegs.h
  • R_PCIE_PMCS_OFFST : PcieRegs.h
  • R_PCIE_RCTL_OFFSET : PcieRegs.h
  • R_PCIE_RSTS_OFFSET : PcieRegs.h
  • R_PCIE_SLCAP_OFFSET : PcieRegs.h
  • R_PCIE_SLCTL_OFFSET : PcieRegs.h
  • R_PCIE_SLSTS_OFFSET : PcieRegs.h
  • R_PCIE_SUBSYSTEM_VENDOR_ID_OFFSET : PcieRegs.h
  • R_PCIE_XCAP_OFFSET : PcieRegs.h
  • R_PMC_CFG_ACTL : PmcRegs.h
  • R_PMC_CFG_BAR : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_BUILD : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_HOT_FIX : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MAJOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_INTEL_HSIO_VERSION_MINOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_BUILD : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_HOT_FIX : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MAJOR : PmcRegs.h
  • R_PMC_MEM_SSRAM_OEM_HSIO_VERSION_MINOR : PmcRegs.h
  • R_PMC_PWRM_ACPI_TMR_CTL : PmcRegs.h
  • R_PMC_PWRM_ACTL : PmcRegs.h
  • R_PMC_PWRM_ADR_CTRL_STS : PmcRegs.h
  • R_PMC_PWRM_ADR_EN : PmcRegs.h
  • R_PMC_PWRM_ADR_GBLRST_EN_0 : PmcRegs.h
  • R_PMC_PWRM_ADR_GEN_CFG : PmcRegs.h
  • R_PMC_PWRM_ADR_GEN_CFG_V2 : PmcRegs.h
  • R_PMC_PWRM_BCLK_CFG : PmcRegs.h
  • R_PMC_PWRM_BIOS_SCRATCHPAD_2 : PmcRegs.h
  • R_PMC_PWRM_BM_CX_CNF : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL1A : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL1B : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL2A : PmcRegs.h
  • R_PMC_PWRM_CPPM_CG_POL3A : PmcRegs.h
  • R_PMC_PWRM_CPPM_MISC_CFG : PmcRegs.h
  • R_PMC_PWRM_CPPM_MPG_POL1A : PmcRegs.h
  • R_PMC_PWRM_CPPMFALIGNCTL_1 : PmcRegs.h
  • R_PMC_PWRM_CPPMVRIC : PmcRegs.h
  • R_PMC_PWRM_CPU_EPOC : PmcRegs.h
  • R_PMC_PWRM_CRID : PmcRegs.h
  • R_PMC_PWRM_CRID_UIP : PmcRegs.h
  • R_PMC_PWRM_CS_SD_CTL1 : PmcRegs.h
  • R_PMC_PWRM_CS_SD_CTL2 : PmcRegs.h
  • R_PMC_PWRM_CS_SD_OVR_EN : PmcRegs.h
  • R_PMC_PWRM_DSX_CFG : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SA : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SA2 : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_CW_SLOW_RING_CF : PmcRegs.h
  • R_PMC_PWRM_EN_MISC_EVENT : PmcRegs.h
  • R_PMC_PWRM_EN_NS_SA : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SA_0 : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SA_02 : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_PA_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SA : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SA2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING2 : PmcRegs.h
  • R_PMC_PWRM_EN_SN_SLOW_RING_CF : PmcRegs.h
  • R_PMC_PWRM_ETR3 : PmcRegs.h
  • R_PMC_PWRM_GBL2HOST_EN : PmcRegs.h
  • R_PMC_PWRM_GBLRST_CAUSE0 : PmcRegs.h
  • R_PMC_PWRM_GBLRST_CAUSE1 : PmcRegs.h
  • R_PMC_PWRM_GEN_PMCON_A : PmcRegs.h
  • R_PMC_PWRM_GEN_PMCON_B : PmcRegs.h
  • R_PMC_PWRM_GPIO_CFG : PmcRegs.h
  • R_PMC_PWRM_HPR_CAUSE0 : PmcRegs.h
  • R_PMC_PWRM_IPC_CMD : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF0 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF1 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF2 : PmcRegs.h
  • R_PMC_PWRM_IPC_RBUF3 : PmcRegs.h
  • R_PMC_PWRM_IPC_STS : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF0 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF1 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF2 : PmcRegs.h
  • R_PMC_PWRM_IPC_WBUF3 : PmcRegs.h
  • R_PMC_PWRM_LPM0_REQ_0 : PmcRegs.h
  • R_PMC_PWRM_LPM7_REQ_5 : PmcRegs.h
  • R_PMC_PWRM_LPM_ADEM_HOST_CTRL : PmcRegs.h
  • R_PMC_PWRM_LPM_EN : PmcRegs.h
  • R_PMC_PWRM_LPM_EN_V2 : PmcRegs.h
  • R_PMC_PWRM_LPM_EN_V3 : PmcRegs.h
  • R_PMC_PWRM_LPM_PRI : PmcRegs.h
  • R_PMC_PWRM_LPM_PRI_V4 : PmcRegs.h
  • R_PMC_PWRM_LTR_IGN : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG1 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG2 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG3 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG5 : PmcRegs.h
  • R_PMC_PWRM_MODPHY_PM_CFG6 : PmcRegs.h
  • R_PMC_PWRM_OBFF_CFG : PmcRegs.h
  • R_PMC_PWRM_PM_CFG : PmcRegs.h
  • R_PMC_PWRM_PM_CFG2 : PmcRegs.h
  • R_PMC_PWRM_PM_CFG3 : PmcRegs.h
  • R_PMC_PWRM_PM_CFG4 : PmcRegs.h
  • R_PMC_PWRM_PM_SYNC_MODE : PmcRegs.h
  • R_PMC_PWRM_PM_SYNC_STATE_HYS : PmcRegs.h
  • R_PMC_PWRM_PMLDOCTRL : PmcRegs.h
  • R_PMC_PWRM_PRSTS : PmcRegs.h
  • R_PMC_PWRM_S0_LDO_OFF_COUNT : PmcRegs.h
  • R_PMC_PWRM_S0IX_LDO_OFF_COUNT : PmcRegs.h
  • R_PMC_PWRM_S3_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_S4_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_S5_PWRGATE_POL : PmcRegs.h
  • R_PMC_PWRM_SLP_S0_RESIDENCY : PmcRegs.h
  • R_PMC_PWRM_SSMC : PmcRegs.h
  • R_PMC_PWRM_SSMD : PmcRegs.h
  • R_PMC_PWRM_SSMD_DW2 : PmcRegs.h
  • R_PMC_PWRM_SSMD_DW3 : PmcRegs.h
  • R_PMC_PWRM_SSML : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_0_V2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_1 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_1_V2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_2 : PmcRegs.h
  • R_PMC_PWRM_ST_PG_FDIS_PMC_2_V2 : PmcRegs.h
  • R_PMC_PWRM_TGPIOCTL0 : PmcRegs.h
  • R_PMC_PWRM_TGPIOCTL1 : PmcRegs.h
  • R_PMC_PWRM_WADT_AC : PmcRegs.h
  • R_PMC_SOFT_STRAP_7 : PmcRegs.h
  • R_PTT_HCI_BASE_ADDRESS : PttPtpRegs.h
  • R_RTC_PCR_BUC : RtcRegs.h
  • R_RTC_PCR_CONF : RtcRegs.h
  • R_RTC_PCR_RTCDCG : RtcRegs.h
  • R_SA_PEG_AFEBND0CFG1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEBND0CFG4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFELN0CFG0_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFELN0CFG1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_AFEOVR_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BCTRL_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD22_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD24_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD26_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI0_CR_DWORD28_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0_CRI2_FUSE_DWORD15_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND0SPARE_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD22_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD24_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD26_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI0_CR_DWORD28_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD14_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD15_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_BND10_CRI2_FUSE_DWORD16_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_CFG4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_CMNSPARE_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DCAP2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DCTL2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_DID_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQCFG_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQCTL0_1_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPH3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET11_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET1_2_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET2_3_4_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET4_5_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET6_7_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET7_8_9_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_EQPRESET9_10_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_G3CTL0_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_L0SLAT_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LCTL3_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LCTL_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_LSTS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_SLOTSTS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_SS_OFFSET : SaPcieDmiRegs.h
  • R_SA_PEG_VC0RSTS_OFFSET : SaPcieDmiRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_AIDPCRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CADR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CAIR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_CRGC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_EGCR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_FDW0 : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_GCR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_GSR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_IOBRSC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MBRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXCRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXPBAR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXPRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXTBAR : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_MXTRC : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_NRDF : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_RHDF : SataRegs.h
  • R_SATA_CFG_RST_PCIE_STORAGE_SAPI : SataRegs.h
  • R_SATA_MEM_AHCI_SFM : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_AMXC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DCC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMBL : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_CR1_DMXC : SataRegs.h
  • R_SATA_MEM_RST_PCIE_STORAGE_RCR : SataRegs.h
  • R_SMBUS_IO_AUXC : PchRegsSmbus.h
  • R_SMBUS_IO_AUXS : PchRegsSmbus.h
  • R_SMBUS_IO_HBD : PchRegsSmbus.h
  • R_SMBUS_IO_HCMD : PchRegsSmbus.h
  • R_SMBUS_IO_HCTL : PchRegsSmbus.h
  • R_SMBUS_IO_HD0 : PchRegsSmbus.h
  • R_SMBUS_IO_HD1 : PchRegsSmbus.h
  • R_SMBUS_IO_HSTS : PchRegsSmbus.h
  • R_SMBUS_IO_NDA : PchRegsSmbus.h
  • R_SMBUS_IO_NDHB : PchRegsSmbus.h
  • R_SMBUS_IO_NDLB : PchRegsSmbus.h
  • R_SMBUS_IO_PEC : PchRegsSmbus.h
  • R_SMBUS_IO_RSA : PchRegsSmbus.h
  • R_SMBUS_IO_SCMD : PchRegsSmbus.h
  • R_SMBUS_IO_SD : PchRegsSmbus.h
  • R_SMBUS_IO_SMBC : PchRegsSmbus.h
  • R_SMBUS_IO_SMLC : PchRegsSmbus.h
  • R_SMBUS_IO_SSTS : PchRegsSmbus.h
  • R_SMBUS_IO_TSA : PchRegsSmbus.h
  • R_SMBUS_PCR_GC : PchRegsSmbus.h
  • R_SMBUS_PCR_PCE : PchRegsSmbus.h
  • R_SMBUS_PCR_SCTM : PchRegsSmbus.h
  • R_SMBUS_PCR_SMBTM : PchRegsSmbus.h
  • R_SMBUS_PCR_TCOCFG : PchRegsSmbus.h
  • R_SPX_PCR_IMRAMBL : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMBU32 : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMLE : PchPcieRpRegs.h
  • R_SPX_PCR_IMRAMLU32 : PchPcieRpRegs.h
  • R_SPX_PCR_PCD : PchPcieRpRegs.h
  • R_SPX_PCR_PCIEHBP : PchPcieRpRegs.h
  • R_SPX_SIP16_PCR_PCD : PchPcieRpRegs.h
  • R_TCO_IO_TWDS : TcoRegs.h
  • R_USB2_PCR_CFG_COMPBG : UsbRegs.h
  • R_USB2_PCR_CONFIG_0 : UsbRegs.h
  • R_USB2_PCR_CONFIG_3 : UsbRegs.h
  • R_USB2_PCR_DFT_1 : UsbRegs.h
  • R_USB2_PCR_GLB_ADP_VBUS_REG : UsbRegs.h
  • R_USB2_PCR_GLOBAL_PORT : UsbRegs.h
  • R_USB2_PCR_GLOBAL_PORT_2 : UsbRegs.h
  • R_USB2_PCR_PER_PORT : UsbRegs.h
  • R_USB2_PCR_PER_PORT_2 : UsbRegs.h
  • R_USB2_PCR_PLL1 : UsbRegs.h
  • R_USB2_PCR_PLLDIVRATIOS_0 : UsbRegs.h
  • R_USB2_PCR_PP_LANE_BASE_ADDR : UsbRegs.h
  • R_USB2_PCR_SFRCONFIG_0 : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL_CLKCORETCGL1 : UsbRegs.h
  • R_USB2_PCR_SNPSPHYSIPPOL_ENCMNONNOVRL1 : UsbRegs.h
  • R_USB2_PCR_UTMI_MISC_PER_PORT : UsbRegs.h
  • R_XDCI_CFG_CPGE : UsbRegs.h
  • R_XDCI_CFG_PMCSR : UsbRegs.h
  • R_XDCI_MEM_GCTL : UsbRegs.h
  • R_XDCI_MEM_GUSB2PHYCFG : UsbRegs.h
  • R_XDCI_MEM_GUSB3PIPECTL0 : UsbRegs.h
  • R_XHCI_CFG_XHCC3 : UsbRegs.h
  • R_XHCI_MEM_AUDIO_OFFLOAD_CTR : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG2 : UsbRegs.h
  • R_XHCI_MEM_AUX_CTRL_REG3 : UsbRegs.h
  • R_XHCI_MEM_CFG_USB2_LTV_U2_NOREQ_REG : UsbRegs.h
  • R_XHCI_MEM_D0I2CTRL : UsbRegs.h
  • R_XHCI_MEM_D0I2SCH_ALARM_CTRL : UsbRegs.h
  • R_XHCI_MEM_DBC_DBCCTL : UsbRegs.h
  • R_XHCI_MEM_DBGDEV_CTRL_REG1 : UsbRegs.h
  • R_XHCI_MEM_GRP0_SAI_RAC_POLICY_LO : UsbRegs.h
  • R_XHCI_MEM_GRP0_SAI_WAC_POLICY_LO : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_MISC_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_MISC_REG_2 : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_ODMA_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_PORT_LINK_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_CTRL_SSP_TUNNELING_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_PWR_CTRL_REG0 : UsbRegs.h
  • R_XHCI_MEM_HOST_IF_PWR_CTRL_REG1 : UsbRegs.h
  • R_XHCI_MEM_LTVHIT : UsbRegs.h
  • R_XHCI_MEM_LTVLIT : UsbRegs.h
  • R_XHCI_MEM_LTVMIT : UsbRegs.h
  • R_XHCI_MEM_MULT_IN_SCH_POLICY : UsbRegs.h
  • R_XHCI_MEM_PMCTRL2 : UsbRegs.h
  • R_XHCI_MEM_PMREQ_CTRL_REG : UsbRegs.h
  • R_XHCI_MEM_PORTSC_START_OFFSET : UsbRegs.h
  • R_XHCI_MEM_SOCHWSTSAVE1 : UsbRegs.h
  • R_XHCI_MEM_SSIC_CONF_REG2_PORT_1 : UsbRegs.h
  • R_XHCI_MEM_SSIC_CONF_REG2_PORT_2 : UsbRegs.h
  • R_XHCI_MEM_SSPE : UsbRegs.h
  • R_XHCI_MEM_SURVIVABILITY_REG1 : UsbRegs.h
  • R_XHCI_MEM_SURVIVABILITY_REG2 : UsbRegs.h
  • R_XHCI_MEM_U2OCM : UsbRegs.h
  • R_XHCI_MEM_U2PRM_U2PRDE : UsbRegs.h
  • R_XHCI_MEM_U3OCM : UsbRegs.h
  • R_XHCI_MEM_USB2_PROTOCOL_GAP_TIMER_HIGH_REG : UsbRegs.h
  • R_XHCI_MEM_USB2PMCTRL : UsbRegs.h
  • R_XHCI_MEM_USBLPM : UsbRegs.h
  • R_XHCI_MEM_XHCLTVCTL2 : UsbRegs.h
  • R_XHCI_MEM_XLTP_LTV1 : UsbRegs.h
  • R_XHCI_PCR_DAP_COMMON_CONTROL_REG : UsbRegs.h
  • R_XHCI_PCR_DAP_ESS_PORT_CONTROL1 : UsbRegs.h
  • R_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0 : UsbRegs.h
  • R_XHCI_PCR_DAP_USB2PORT_STATUS_0 : UsbRegs.h
  • REFLASH_BIOS : AsfProtocol.h
  • REQUESTED_CLOCK_GEN2_PCIE : IccMsgs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- s -

  • S_CPU_XHCI_MEM_ESS_PORT_CONTROL1_SPACING : UsbRegs.h
  • S_ESPI_CFG_PCBC : PchRegsLpc.h
  • S_ESPI_PCR_LNKERR_SLV0 : PchRegsLpc.h
  • S_ESPI_PCR_XERR : PchRegsLpc.h
  • S_PTT_HCI_CRB_LENGTH : PttPtpRegs.h
  • S_SPX_PCR_PCD_RP_FIELD : PchPcieRpRegs.h
  • S_XHCI_MEM_PORTSC_PORT_SPACING : UsbRegs.h
  • S_XHCI_PCR_DAP_ESS_PORT_CONTROL1_SPACING : UsbRegs.h
  • SA_FVI_STRING : SiFvi.h
  • SA_POLICY_PROTOCOL_REVISION : SaPolicy.h
  • SEMAPHORE : Txt.h
  • SET_CM_TIMEOUT_IN_MS : TbtMailBoxCmdDefinition.h
  • SI_POLICY_REVISION : SiPolicyStruct.h
  • SI_PREMEM_POLICY_REVISION : SiPolicyStruct.h
  • STORAGE_REDIRECTION_BOOT_DEVICE_MASK : AsfProtocol.h
  • SUPPORT_FORCE_PXE : IndustryStandardAsf.h
  • SUPPORT_POWER_CYCLE_RESET : IndustryStandardAsf.h
  • SUPPORT_POWER_CYCLE_RESET_COMBO : IndustryStandardAsf.h
  • SUPPORT_POWER_DOWN : IndustryStandardAsf.h
  • SUPPORT_POWER_DOWN_COMBO : IndustryStandardAsf.h
  • SUPPORT_POWER_UP : IndustryStandardAsf.h
  • SUPPORT_POWER_UP_COMBO : IndustryStandardAsf.h
  • SUPPORT_RESET : IndustryStandardAsf.h
  • SUPPORT_RESET_COMBO : IndustryStandardAsf.h
  • SW_DXE_BS_EC_NO_BOOT_MEDIA : IntelAsfExtensions.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- t -

  • TBT_MAILBOX_DELAY : TbtMailBoxCmdDefinition.h
  • TO_BE_FILLED : SiFviLib.h , SiFvi.h
  • TO_BE_FILLED_STRING : SiFviLib.h , SiFvi.h
  • TPM_INIT_FAILED : TxtInfoHob.h
  • TPM_STATUS_REG_ADDRESS : Txt.h
  • TPM_TIME_OUT : Txt.h
  • TPSS_FVID_MAX_STATES : CpuPowerMgmt.h
  • TXT_BIOS_SPEC_VER_MAJOR : Txt.h
  • TXT_BIOS_SPEC_VER_MINOR : Txt.h
  • TXT_BIOS_SPEC_VER_REVISION : Txt.h
  • TXT_BLOCK_MEM_STS : Txt.h
  • TXT_CONFIG_SPACE_LENGTH : Txt.h
  • TXT_CPU_RESET_REQUIRED : TxtInfoHob.h
  • TXT_CRASHCODE_REG_OFF : Txt.h
  • TXT_DPR_SIZE_REG_OFF : Txt.h
  • TXT_E2STS_REG_OFF : Txt.h
  • TXT_ERROR_STATUS_REG_OFF : Txt.h
  • TXT_HEAP_BASE_REG_OFF : Txt.h
  • TXT_HEAP_SIZE_REG_OFF : Txt.h
  • TXT_LAUNCH_ACHECK : Txt.h
  • TXT_LAUNCH_CLEAR_SECRETS : Txt.h
  • TXT_LAUNCH_LOCK_CONFIG : Txt.h
  • TXT_LAUNCH_SCHECK : Txt.h
  • TXT_LAUNCH_SCLEAN : Txt.h
  • TXT_PRIVATE_BASE : Txt.h
  • TXT_PTT_FTIF_OFF : Txt.h
  • TXT_PTT_PRESENT : Txt.h
  • TXT_PUBLIC_BASE : Txt.h
  • TXT_RESET_AUX : Txt.h
  • TXT_RESET_EST_BIT : Txt.h
  • TXT_SCRATCHPAD : Txt.h
  • TXT_SCRATCHPAD2 : Txt.h
  • TXT_SCRATCHPAD3 : Txt.h
  • TXT_SCRATCHPAD4 : Txt.h
  • TXT_SECRETS_STS : Txt.h
  • TXT_SINIT_BASE_REG_OFF : Txt.h
  • TXT_SINIT_SIZE_REG_OFF : Txt.h
  • TXT_SINIT_SIZE_REG_OFF2 : Txt.h
  • TXT_SLP_ENTRY_ERROR_STS : Txt.h
  • TXT_SPAD_REG_OFF : Txt.h
  • TXT_SVMM_JOIN_REG_OFF : Txt.h
  • TXT_SVMM_JOIN_REG_OFF2 : Txt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- u -

  • USB_OC_MAX_PINS : UsbConfig.h
  • USE_KVM : AsfProtocol.h
  • USE_SOL : AsfProtocol.h
  • USE_STORAGE_REDIR : AsfProtocol.h
  • USER_FEEDBACK_REQUESTED : MkhiMsgs.h
  • USER_PASSWORD_BYPASS : IndustryStandardAsf.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- v -

  • V_ACPI_IO_PM1_TMR_MAX_VAL : PmcRegs.h
  • V_ESPI_PCR_FCERR_SLV0_FCFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_FCERR_SLV0_FCNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV0_LFER1E_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV1_LFER1E_SERR : PchRegsLpc.h
  • V_ESPI_PCR_LNKERR_SLV1_LFET1E_SMI : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_PCERR_PCRMTARE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS : PchRegsLpc.h
  • V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR : PchRegsLpc.h
  • V_ESPI_PCR_VWERR_VWFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_VWERR_VWNFEE_SERR : PchRegsLpc.h
  • V_ESPI_PCR_XERR_XFEE_SMI : PchRegsLpc.h
  • V_ESPI_PCR_XERR_XNFEE_SMI : PchRegsLpc.h
  • V_FTIF_FTPM_PRESENT : PttPtpRegs.h
  • V_FTIF_SPI_DTPM_PRESENT : PttPtpRegs.h
  • V_INTEL_VENDOR_ID : MeRegs.h
  • V_IO_CAPT_LVL2 : CpuRegs.h
  • V_IO_CAPT_LVL3 : CpuRegs.h
  • V_IO_CAPT_LVL4 : CpuRegs.h
  • V_IO_CAPT_LVL5 : CpuRegs.h
  • V_IO_CAPT_LVL6 : CpuRegs.h
  • V_IO_CAPT_LVL7 : CpuRegs.h
  • V_LPC_CFG_BC_BBS_LPC : PchRegsLpc.h
  • V_LPC_CFG_BC_BBS_SPI : PchRegsLpc.h
  • V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP : PchRegsLpc.h
  • V_MAILBOX_INF_DFX_PWROFF_REQ_DIS : CpuMailboxLib.h
  • V_MAILBOX_INF_DFX_PWROFF_REQ_EN : CpuMailboxLib.h
  • V_ME_VER1_PCH_N_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER2_PCH_H_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER3_PCH_HECI_DEVICE_ID : MeRegs.h
  • V_ME_VER4_PCH_S_HECI_DEVICE_ID : MeRegs.h
  • V_PCH_DEFAULT_SID : PchRegs.h
  • V_PCH_DEFAULT_SVID_SID : PchRegs.h
  • V_PCH_DMI15_PCR_CTRL1_L1PL_8US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_DIS : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L0S : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L0SL1 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_LCTL_ASPM_L1 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_ORCE_EN_GEN2_GEN3 : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_PLLWAIT_0US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_MPC2_PLLWAIT_5US : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_PWRCTL_RPSEWL_120NS : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL0TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL1TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL2TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL3TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL4TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL5TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL6TP : PchDmi15Regs.h
  • V_PCH_DMI15_PCR_UPL7TP : PchDmi15Regs.h
  • V_PCH_DMI_PCR_LCAP_EL0_256NS_512NS : PchDmiRegs.h
  • V_PCH_DMI_PCR_LCAP_EL1_8US_16US : PchDmiRegs.h
  • V_PCH_INTEL_VENDOR_ID : PchRegs.h
  • V_PCIE_DCTL2_OBFFEN_DIS : PcieRegs.h
  • V_PCIE_DCTL2_OBFFEN_WAKE : PcieRegs.h
  • V_PCIE_EX_ACS_CID : PcieRegs.h
  • V_PCIE_EX_AEC_CID : PcieRegs.h
  • V_PCIE_EX_APEC_CID : PcieRegs.h
  • V_PCIE_EX_DLFECH_CID : PcieRegs.h
  • V_PCIE_EX_DPC_CID : PcieRegs.h
  • V_PCIE_EX_G5ECH_CID : PcieRegs.h
  • V_PCIE_EX_IDEEXTCAPHDR_CID : PcieRegs.h
  • V_PCIE_EX_L1S_CID : PcieRegs.h
  • V_PCIE_EX_PL16GECH_CID : PcieRegs.h
  • V_PCIE_EX_PL16MECH_CID : PcieRegs.h
  • V_PCIE_EX_PTM_CID : PcieRegs.h
  • V_PCIE_EX_SPE_CID : PcieRegs.h
  • V_PCIE_EX_VC_CID : PcieRegs.h
  • V_PCIE_FPBCAP_CID : PcieRegs.h
  • V_PMC_DEF_CPU_BCLK_CFG_INTEGRATED : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_MEM_CAL : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_BIOS_RST_CMPL_STS_PCI_ENUM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_LOCK : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CPU_STRAP_WRITE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_DISCOVERY : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ERASE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_ON_RESET : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_PROGRAM_TRIGGER_ENABLES : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_RE_ARM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_CRASHLOG_READ_TRIGGER_ENABLES : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_FIVR_WRITE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC1_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC2_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_READ_PMIC3_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_LOCK_ENABLE_PMIC_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC1_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC2_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_CMD_ID_WRITE_PMIC3_I2C : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_CPU_STRAP : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_CRASHLOG : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_DFX_PWR_STATE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_FIVR : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_GEN_COMM : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_IO_MARGINING_ENABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_ME_DISABLE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PMC_PRV_REG_ACCESS : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PMIC : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_PROXY : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SNDW_RCOMP : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_COMMAND_SSC_STATE : PmcRegs.h
  • V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI : PmcRegs.h
  • V_PMC_PWRM_IPC_SRC_CLK_CMD : PmcRegs.h
  • V_PMC_PWRM_IPC_SRC_CLK_PORT_MAPPING_CMD : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_EMI_CTRL0_LOGIC : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_FFFC_FAULT_STATUS : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_FFFC_RFI_STATUS : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_GEN_COMM_READ : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL0_LOGIC : PmcRegs.h
  • V_PMC_PWRM_IPC_SUBCMD_RFI_CTRL4_LOGIC : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_1S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_2S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_3S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_RPCD_4S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_0S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_2S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_4S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SAMAW_98ms : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_0_5S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_0S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_1S : PmcRegs.h
  • V_PMC_PWRM_PM_CFG_SSMAW_4S : PmcRegs.h
  • V_PTT_HCI_ALL_BITS_CLEAR : PttPtpRegs.h
  • V_PTT_HCI_IGNORE_BITS : PttPtpRegs.h
  • V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR0 : SataRegs.h
  • V_SATA_CFG_RST_PCIE_STORAGE_MBRC_TMB_BAR5 : SataRegs.h
  • V_SATA_MEM_RST_PCIE_STORAGE_REMAP_CONFIG_CR : SataRegs.h
  • V_SATA_MEM_RST_PCIE_STORAGE_REMAP_RP_OFFSET : SataRegs.h
  • V_SATA_MEM_VS_CAP_MSL : SataRegs.h
  • V_SATA_MEM_VS_CAP_NRMO : SataRegs.h
  • V_SMBUS_PCR_TCOCFG_IRQ_20 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_21 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_22 : PchRegsSmbus.h
  • V_SMBUS_PCR_TCOCFG_IRQ_23 : PchRegsSmbus.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DBC : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_DISCONNECT : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2_PORT_CONTROL_0_REG_0_CONNECTOR_EVENT_HOST : UsbRegs.h
  • V_XHCI_PCR_DAP_USB2PORT_STATUS_0_OS_DBC : UsbRegs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): File Members

- w -

  • WARM_BOOT : MemInfoHob.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen4 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4
Gen4 Directory Reference
Directory dependency graph for Gen4:

Files

file CpuPcieConfig.h [code]
Pcie root port policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | DxePchPolicyLib.h [code]
Prototype of the DxePchPolicyLib library.
file | PchCycleDecodingLib.h [code]
Header file for PchCycleDecodingLib.
file | PchInfoDefs.h [code]
Header file for PchInfoDefs.
file | PchInfoLib.h [code]
Header file for PchInfoLib.
file | PchPciBdfLib.h [code]
Header file for PchPciBdfLib.
file | PchPolicyLib.h [code]
Prototype of the PeiPchPolicy library.
file | PchSmmControlLib.h [code]
Header file for SMM Control PEI Library.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | BdatAccess.h [code]
This file abstracts Bdat Access Handler Protocol.
file | MemInfo.h [code]
This protocol provides the memory information data, such as total physical memory size, memory frequency, memory size of each dimm and rank.
file | SaPolicy.h [code]
Interface definition details between System Agent and platform drivers during DXE phase.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gbe Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gbe
Gbe Directory Reference

Files

file GbeConfig.h [code]
Gigabit Ethernet policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Rst Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rst
Rst Directory Reference
Directory dependency graph for Rst:

Files

file RstConfig.h [code]
Rst policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Protocol Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Protocol Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/Include/Protocol
MeSmbios.h | MebxProtocol.h
Library / DxeAmtPolicyLib.h | AmtPolicy.h
Library / DxeITbtPolicyLib.h | ITbtPolicy.h
Library / DxeMebxDisplayWrapperLib.h | MebxDisplayProtocol.h
Library / DxeMeLib.h | HeciProtocol.h
Library / DxeMeLib.h | PlatformMeHook.h
Library / DxeMeLib.h | MePolicy.h
Library / DxeMePolicyLib.h | MePolicy.h
Ppi / HeciAccessPpi.h | HeciAccessProtocol.h
Ppi / HeciControlPpi.h | HeciControlProtocol.h
Ppi / HeciPpi.h | HeciProtocol.h
Ppi / Ppi/Spi.h | Protocol/Spi.h
Ppi / Ppi/Wdt.h | Protocol/Wdt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Cpu Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Cpu Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/Cpu
Library / PeiMemPolicyLib.h | Include / CpuRegs.h
Library / PeiMemPolicyLib.h | Include / Library / CpuPlatformLib.h
ConfigBlock / Overclocking / OverclockingConfig.h | Include / CpuLimits.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> SystemAgent Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
Library / PeiMemPolicyLib.h | Include / SaDataHob.h
Library / PeiMemPolicyLib.h | Include / Library / PeiSaPolicyLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Include Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/SystemAgent/Include
Library / PeiMemPolicyLib.h | SaDataHob.h
Library / PeiMemPolicyLib.h | Library / PeiSaPolicyLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Register Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Register Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/Include/Register
FwStsSmbiosTable.h | MeRegs.h
Library / MeFwStsLib.h | HeciRegs.h
Library / PeiMeLib.h | MeRegs.h
Protocol / HeciProtocol.h | MeRegs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include

Include → Library Relation

File in Intel/ClientOneSiliconPkg/Include | Includes file in Intel/ClientOneSiliconPkg/SystemAgent/Include/Library
Library / PeiMemPolicyLib.h | PeiSaPolicyLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | BootGuardLibVer1.h [code]
Header file for Boot Guard Lib implementation.
file | BootMediaLib.h [code]
Header file for the Boot Media Library.
file | CacheAsRamLib.h [code]
file | CnviLib.h [code]
Header file for CnviLib.
file | ConfigBlockLib.h [code]
Header file for Config Block Lib implementation.
file | CpuDmiInfoLib.h [code]
Header file for CpuDmiInfoLib.
file | CpuMailboxLib.h [code]
Header file for Cpu Mailbox Lib.
file | CpuRegbarAccessLib.h [code]
Header file for CPU REGBAR ACCESS library.
file | DxeAmtHeciLib.h [code]
Header file for AMT functionality.
file | DxeAmtPolicyLib.h [code]
Prototype of the DxeAmtPolicyLib library.
file | DxeAsfHeciLib.h [code]
Header file for ASF functionality.
file | DxeAsfLib.h [code]
Header file for ASF functionality.
file | DxeITbtPolicyLib.h [code]
Prototype of the DxeITbtPolicyLib library.
file | DxeJhiSupportLib.h [code]
Header file for JHI helper functionality.
file | DxeMebxDisplayWrapperLib.h [code]
Wrapper functions for MEBx display protocol functions.
file | DxeMebxWrapperLib.h [code]
Header file for MEBx Wrapper Library.
file | DxeMeLib.h [code]
Header file for functions to get Intel ME information.
file | DxeMePolicyLib.h [code]
Prototype of the DxeMePolicyLib library.
file | DxeTbtDisBmeLib.h [code]
Disable BME on TBT Hierarchy Lib.
file | EspiLib.h [code]
Header file for PchEspiLib.
file | FiaAccessLib.h [code]
Header file for FiaAccessLib.
file | FspErrorInfoLib.h [code]
Library to provide service for sending FSP error information to bootloader.
file | GbeLib.h [code]
Header file for GbeLib.
file | GetFsptApiParameter.h [code]
Library to get FSP-T API parameter.
file | GnaInfoLib.h [code]
This file provides GNA Public Library.
file | GpioConfig.h [code]
Header file for GpioConfig structure used by GPIO library.
file | GpioLib.h [code]
Header file for GpioLib.
file | GpioNativeLib.h [code]
Header file for GpioLib for native and Si specific usage.
file | GraphicsInfoFruLib.h [code]
Header file for Graphics Info Fru Lib implementation.
file | GraphicsInfoLib.h [code]
Header file for Graphics Private Info Lib implementation.
file | HostBridgeInfoLib.h [code]
Header file for Host Bridge Info Lib implementation.
file | HybridGraphicsInfoFruLib.h [code]
Header file for Hybrid Graphics Info Fru Lib implementation.
file | IpuLib.h [code]
This file provides IPU Public Library.
file | IshInfoLib.h [code]
Ish Info Library header file.
file | ItssLib.h [code]
Header file for ItssLib.
file | MeChipsetLib.h [code]
Header file for Me Chipset Lib.
file | MeEwlLib.h [code]
Header file for ME Error Warning Log Lib.
file | MeFwStsLib.h [code]
Definition for Me FWSTS Lib.
file | MeShowBufferLib.h [code]
Definition for Me Debug Lib.
file | MeTypeLib.h [code]
Header for ME type library.
file | MeUefiFwHealthStatusLib.h [code]
Definitions for Me Uefi Health Status Library.
file | MeUtilsLib.h [code]
HECI utilities for use in PEI, DXE, and SMM.
file | MmPciLib.h [code]
Get Pci Express address library implementation.
file | OcWdtLib.h [code]
Header file for OC WDT Library.
file | P2sbLib.h [code]
This file provides P2SB public library.
file | PchDmiAccessLib.h [code]
DMI library header for abstraction of DMI PCR registers access.
file | PchPcieRpLib.h [code]
Header file for PchPcieRpLib.
file | PchPcrLib.h [code]
Header file for PchPcrLib.
file | PcieHelperLib.h [code]
Header file for PCI Express helpers base library.
file | PeiAmtPolicyLib.h [code]
Prototype of the AmtPolicyLibPei library.
file | PeiDxeSmmReserveMmio64SizeLib.h [code]
PEI/DXE/SMM library for reserved 64-bit MMIO space.
file | PeiITbtPolicyLib.h [code]
Prototype of the PeiITbtPolicyLib library.
file | PeiMeLib.h [code]
Header file for PEI Me functionality.
file | PeiMemPolicyLib.h [code]
Header file for the PeiMemPolicyLib library.
file | PeiMePolicyLib.h [code]
Prototype of the MePolicyLibPei library.
file | PeiMeServerPreMemPolicyLib.h [code]
Prototype of the MeServerPolicyLibPei library.
file | PeiPcieRpLib.h [code]
Header file for PEI PCIe functionality.
file | PeiSiPolicyUpdateLib.h [code]
Header file for PEI SiPolicyUpdate Library.
file | PeiTbtTaskDispatchLib.h [code]
PEI TBT Task Dispatch library Header file.
file | PeiVrDomainLib.h [code]
Define Maximum Number of Voltage Regulator Domains.
file | PmcLib.h [code]
Header file for PmcLib.
file | PostCodeToScratchPadLib.h [code]
Header file for writing the postcode value into scratchpad register.
file | PreSiliconEnvDetectLib.h [code]
Prototype of the PreSiliconEnvDetectLib library.
file | PsthLib.h [code]
This file provides PSTH public library.
file | PttHeciLib.h [code]
Platform Trust Technology (PTT) HECI SkuMgr Library.
file | ResetSystemLib.h [code]
System reset Library Services.
file | RstCrLib.h [code]
Header file for RstCrLib.
file | RtcAccessLib.h [code]
RTC library header for abstraction of RTC PCR registers access.
file | SataLib.h [code]
Header file for SataLib.
file | SataSocLib.h [code]
Header file for SATA SoC library.
file | SecPlatformLib.h [code]
Prototype of SEC Platform hook library.
file | SerialIoAccessLib.h [code]
Header file for Serial Io Common Lib.
file | SerialIoI2cLib.h [code]
Basic I2C Librarary that allows I2C communication throguh Read/Write and Command Block operations.
file | SerialIoI2cMasterLib.h [code]
PEI I2C Initiator module.
file | SerialIoSpiLib.h [code]
Basic SPI Library that allows SPI communication through Read/Write/WriteRead operations.
file | SerialIoUartDebugPropertyPcdLib.h [code]
SerialIo Uart Debug Property Pcd Library.
file | SerialIoUartLib.h [code]
Header file for Serial IO UART Lib implementation.
file | SiConfigBlockLib.h [code]
Prototype of the SiConfigBlockLib library.
file | SiFviLib.h [code]
Header file for Reference code Firmware Version Info Interface Lib implementation.
file | SiMtrrLib.h [code]
Header file for Silicon code Mtrr Lib implementation.
file | SiPolicyLib.h [code]
Prototype of the SiPolicyLib library.
file | SmbiosProcessorLib.h [code]
Header file for SmbiosProcessorLib implementation.
file | SmbusInfoLib.h [code]
This file provides Smbus public library.
file | SpiAccessLib.h [code]
SPI library header for abstraction of SPI HW registers accesses.
file | SpiLib.h [code]
Header file for Spi Library.
file | StallPpiLib.h [code]
Header file for a library to install StallPpi.
file | SystemTimeLib.h [code]
Header file for SystemTimeLib.
file | TbtCommonLib.h [code]
Header file of TBT common library.
file | TccLib.h [code]
Header file for TCC Lib.
file | TcoLib.h [code]
Header file for TcoLib.
file | TcssInfoLib.h [code]
Header file for SmmTcss Private Info Lib implementation.
file | TelemetryLib.h [code]
Header file for TelemetryLib.
file | ThcLib.h [code]
Touch Host Controller Library.
file | ThermalAccessLib.h [code]
Thermal library header for abstraction of thermal registers access.
file | TmeInfoLib.h [code]
Header file to get TME information.
file | TopSwapLib.h [code]
Header file for TopSwapLib.
file | Tpm2CommandLib.h [code]
This library is used by other modules to send TPM2 command.
file | TraceHubDebugLib.h [code]
Definitions for the TraceHub Debug Lib.
file | TraceHubHookLib.h [code]
Definitions for the TraceHubHook Lib.
file | TsnLib.h [code]
This file provides Tsn public library.
file | UsbLib.h [code]
Header file of available functions in general USB Library.
file | VtdInfoLib.h [code]
Header file for VtdInfoLib.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Cpu Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
Cpu Directory Reference
Directory dependency graph for Cpu:

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Fusa Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fusa
Fusa Directory Reference

Files

file FusaConfig.h [code]
Functional Safety policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Hda Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hda
Hda Directory Reference
Directory dependency graph for Hda:

Files

file HdAudioConfig.h [code]
HDAUDIO policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gpio Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gpio
Gpio Directory Reference

Files

file GpioDevConfig.h [code]
GPIO device policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Fivr Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Fivr
Fivr Directory Reference

Files

file FivrConfig.h [code]
PCH FIVR policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock -> Cpu Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock

ConfigBlock → Cpu Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock | Includes file in Intel/ClientOneSiliconPkg/Cpu
Overclocking / OverclockingConfig.h | Include / CpuLimits.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock

ConfigBlock → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock | Includes file in Intel/ClientOneSiliconPkg/Include/Library
Amt / AmtConfig.h | ConfigBlockLib.h
CpuPcieRp / Gen3 / CpuPcieConfigGen3.h | GpioLib.h
CpuPcieRp / Gen3 / PciePeiConfig.h | GpioLib.h
CpuPcieRp / Gen4 / CpuPcieConfig.h | GpioLib.h
Sata / SataConfig.h | GpioConfig.h
Vtd / VtdConfig.h | VtdInfoLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchPcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
  • PchPcieRp
PchPcieRp Directory Reference
Directory dependency graph for PchPcieRp:

Files

file PchPcieRpConfig.h [code]
PCH Pcie root port policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SerialIo Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • SerialIo
SerialIo Directory Reference
Directory dependency graph for SerialIo:

Files

file SerialIoConfig.h [code]
Serial IO policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Rtc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Rtc
Rtc Directory Reference

Files

file RtcConfig.h [code]
RTC policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemAgent Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
SystemAgent Directory Reference
Directory dependency graph for SystemAgent:

Directories

Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Thermal Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thermal
Thermal Directory Reference

Files

file ThermalConfig.h [code]
Thermal policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | LockDownConfig.h [code]
Lock down policy.
file | PchGeneralConfig.h [code]
PCH General policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Spi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Spi
Spi Directory Reference

Files

file | FlashProtectionConfig.h [code]
FlashProtection policy.
file | SpiConfig.h [code]
PCH SPI Flash Controller config block.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ish Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ish
Ish Directory Reference

Files

file IshConfig.h [code]
ISH policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Amt -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt

Amt → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Amt | Includes file in Intel/ClientOneSiliconPkg/Include/Library
AmtConfig.h | ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | MemoryDxeConfig.h [code]
Memory DXE Policy definitions.
file | PcieDxeConfig.h [code]
PCIE DXE policy definitions.
file | SaMiscPeiConfig.h [code]
Policy details for miscellaneous configuration in System Agent.
file | SaMiscPeiPreMemConfig.h [code]
Policy details for miscellaneous configuration in System Agent.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Sata Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata
Sata Directory Reference
Directory dependency graph for Sata:

Files

file SataConfig.h [code]
Sata policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gna Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Gna
Gna Directory Reference

Files

file GnaConfig.h [code]
Policy definition for GNA Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> ConfigBlock Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol

Protocol → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock
ITbtPolicy.h | Tbt / DxeITbtConfig.h
MePolicy.h | Me / MeDxeConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol

Protocol → Library Relation

File in Intel/ClientOneSiliconPkg/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/Include/Library
ITbtPolicy.h | ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> Register Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol

Protocol → Register Relation

File in Intel/ClientOneSiliconPkg/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/Include/Register
HeciProtocol.h | MeRegs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | ChipsetInfoHob.h [code]
This file contains definitions of Chipset Info HOB.
file | PchInfoHob.h [code]
This file contains definitions of PCH Info HOB.
file | PchPolicyCommon.h [code]
PCH configuration based on PCH policy.
file | PchPreMemPolicyCommon.h [code]
PCH configuration based on PCH policy.
file | PchResetPlatformSpecific.h [code]
PCH Reset Platform Specific definitions.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Thc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Thc
Thc Directory Reference

Files

file ThcConfig.h [code]
Touch Host Controller policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Guid Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Guid
Guid Directory Reference
Directory dependency graph for Guid:

Files

file | AcpiS3Context.h [code]
Definitions for data structures used in S3 resume.
file | ConsoleOutDevice.h [code]
This GUID can be installed to the device handle to specify that the device is the console-out device.
file | FspErrorInfo.h [code]
FSP Error Information HOB to describe errors inside FSP that bootloader may take some actions to handle those error scenarios.
file | MeFirmwareVersionInfoHobGuid.h [code]
ME Version Info HUB definition.
file | MemoryTypeInformation.h [code]
This file defines: Memory Type Information GUID for HOB and Variable.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Me Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Me
Me Directory Reference

Files

file | MeDxeConfig.h [code]
ME config block for DXE phase.
file | MePeiConfig.h [code]
ME config block for PEI phase.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Dci Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Dci
Dci Directory Reference

Files

file DciConfig.h [code]
Dci policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | AmtPolicy.h [code]
Interface definition details between AMT and platform drivers during DXE phase.
file | AmtReadyToBoot.h [code]
AmtReadyToBoot Protocol definitions.
file | AmtSaveMebxProtocol.h [code]
AmtSaveMebxProtocol definitions - deprecated protocol.
file | AsfProtocol.h [code]
Definition of Alert Standard Format (ASF) 2.0.
file | Protocol/BiosGuard.h [code]
This file defines the BIOS Guard Protocol which implements the Intel(R) BIOS Guard Host Controller Compatibility Interface.
file | GopComponentName2.h [code]
Protocol to retrieve the GOP driver version.
file | GopPolicy.h [code]
Interface definition for GopPolicy Protocol.
file | HeciAccessProtocol.h [code]
ME HECI Access Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
file | HeciControlProtocol.h [code]
ME HECI Control Protocol - allows ME-UEFI FW communication over HECI in DXE and SMM.
file | HeciFlowProtocol.h [code]
HECI Flow Protocol.
file | HeciProtocol.h [code]
HECI Protocol.
file | IgdOpRegion.h [code]
This file is part of the IGD OpRegion Implementation.
file | ITbtPolicy.h [code]
Interface definition details between TBT and platform drivers during DXE phase.
file | JhiProtocol.h [code]
Header file for JHI (Intel DAL Host Interface Service) Protocol.
file | MebxConfigProtocol.h [code]
MebxConfigProtocol definitions.
file | MebxDisplayProtocol.h [code]
MEBx Display Protocol definitions.
file | MebxProtocol.h [code]
EFI MEBx Protocol.
file | MePlatformGetResetType.h [code]
Interface definition Me Platform Get Reset Type.
file | MePolicy.h [code]
Interface definition details between ME and platform drivers during DXE phase.
file | MeSmbiosUpdateProtocol.h [code]
MeSmbiosTablesUpdateProtocol definitions.
file | OneClickRecoveryProtocol.h [code]
APIs for Intel One Click Recovery Main Protocol.
file | PlatformMeHook.h [code]
Interface definition details for platform hook support to ME module during DXE phase.
file | PlatformSpecificResetFilter.h [code]
This Protocol provides services to register a platform specific reset filter for ResetSystem().
file | Protocol/PlatformSpecificResetHandler.h [code]
This protocol provides services to register a platform specific handler for ResetSystem().
file | SiPolicyProtocol.h [code]
Protocol used for specifying platform related Silicon information and policy setting.
file | SmmVariable.h [code]
EFI SMM Variable Protocol is related to EDK II-specific implementation of variables and intended for use as a means to store data in the EFI SMM environment.
file | Protocol/Spi.h [code]
This file defines the PCH SPI Protocol which implements the Intel(R) PCH SPI Host Controller Compatibility Interface.
file | TbtDisBmeProtocol.h [code]
Definitions for DisableBmeProtocol.
file | Thc.h [code]
Touch Host Controller Protocol for Thc feature.
file | Protocol/Wdt.h [code]
Watchdog Timer protocol.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemAgent -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent

SystemAgent → Include Relation

File in Intel/ClientOneSiliconPkg/SystemAgent | Includes file in Intel/ClientOneSiliconPkg/Include
Include / Library / PeiSaPolicyLib.h | Library / ConfigBlockLib.h
Include / Protocol / SaPolicy.h | ConfigBlock.h
Include / Protocol / SaPolicy.h | Library / ConfigBlockLib.h
Include / Protocol / SaPolicy.h | ConfigBlock / Graphics / Gen12 / GraphicsConfig.h
Include / Protocol / SaPolicy.h | ConfigBlock / Vtd / VtdConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemAgent -> ConfigBlock Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent

SystemAgent → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/SystemAgent | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock
Include / Protocol / SaPolicy.h | Graphics / Gen12 / GraphicsConfig.h
Include / Protocol / SaPolicy.h | Vtd / VtdConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): SystemAgent -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent

SystemAgent → Library Relation

File in Intel/ClientOneSiliconPkg/SystemAgent | Includes file in Intel/ClientOneSiliconPkg/Include/Library
Include / Library / PeiSaPolicyLib.h | ConfigBlockLib.h
Include / Protocol / SaPolicy.h | ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include

Include → Include Relation

File in Intel/ClientOneSiliconPkg/SystemAgent/Include | Includes file in Intel/ClientOneSiliconPkg/Include
Library / PeiSaPolicyLib.h | Library / ConfigBlockLib.h
Protocol / SaPolicy.h | ConfigBlock.h
Protocol / SaPolicy.h | Library / ConfigBlockLib.h
Protocol / SaPolicy.h | ConfigBlock / Graphics / Gen12 / GraphicsConfig.h
Protocol / SaPolicy.h | ConfigBlock / Vtd / VtdConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol

Protocol → Include Relation

File in Intel/ClientOneSiliconPkg/SystemAgent/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/Include
SaPolicy.h | ConfigBlock.h
SaPolicy.h | Library / ConfigBlockLib.h
SaPolicy.h | ConfigBlock / Graphics / Gen12 / GraphicsConfig.h
SaPolicy.h | ConfigBlock / Vtd / VtdConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> ConfigBlock Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Protocol

Protocol → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/SystemAgent/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/SystemAgent/Include/ConfigBlock
SaPolicy.h | MemoryDxeConfig.h
SaPolicy.h | PcieDxeConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> ConfigBlock Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock
PmcLib.h | Pmc / PmConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Pmc Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → Pmc Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Pmc
PmcLib.h | PmConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Protocol Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → Protocol Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include/Protocol
DxeAmtPolicyLib.h | AmtPolicy.h
DxeITbtPolicyLib.h | ITbtPolicy.h
DxeMebxDisplayWrapperLib.h | MebxDisplayProtocol.h
DxeMeLib.h | HeciProtocol.h
DxeMeLib.h | MePolicy.h
DxeMeLib.h | PlatformMeHook.h
DxeMePolicyLib.h | MePolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Cpu Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → Cpu Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Cpu
PeiMemPolicyLib.h | Include / Library / CpuPlatformLib.h
PeiMemPolicyLib.h | Include / CpuRegs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> SystemAgent Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → SystemAgent Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/SystemAgent
PeiMemPolicyLib.h | Include / Library / PeiSaPolicyLib.h
PeiMemPolicyLib.h | Include / SaDataHob.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Register Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Library

Library → Register Relation

File in Intel/ClientOneSiliconPkg/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include/Register
MeFwStsLib.h | HeciRegs.h
PeiMeLib.h | MeRegs.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Pch -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch

Pch → Include Relation

File in Intel/ClientOneSiliconPkg/Pch | Includes file in Intel/ClientOneSiliconPkg/Include
Include / Library / PchInfoLib.h | Hda.h
Include / PchPolicyCommon.h | ConfigBlock / Pmc / AdrConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Cnvi / CnviConfig.h
Include / PchPolicyCommon.h | ConfigBlock.h
Include / PchPolicyCommon.h | ConfigBlock / Espi / EspiConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Fivr / FivrConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Spi / FlashProtectionConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Fusa / FusaConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Gbe / GbeConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Hda / HdAudioConfig.h
Include / PchPolicyCommon.h | ConfigBlock / HybridStorage / HybridStorageConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Ieh / IehConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Itss / InterruptConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Itss / IoApicConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Ish / IshConfig.h
Include / PchPolicyCommon.h | ConfigBlock / P2sb / P2sbConfig.h
Include / PchPolicyCommon.h | ConfigBlock / PchDmi / PchDmiConfig.h
Include / PchPolicyCommon.h | ConfigBlock / PcieRp / PchPcieRp / PchPcieRpConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Pmc / PmConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Psf / PsfConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Rst / RstConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Rtc / RtcConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Sata / SataConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Scs / ScsConfig.h
Include / PchPolicyCommon.h | ConfigBlock / SerialIo / SerialIoConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Spi / SpiConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Thc / ThcConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Thermal / ThermalConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Tsn / TsnConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Usb / Usb2PhyConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Usb / Usb3HsioConfig.h
Include / PchPolicyCommon.h | ConfigBlock / Usb / UsbConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Dci / DciConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioPcieConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioSataConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Espi / LpcConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / PchDmi / PchDmiConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Smbus / SmbusConfig.h
Include / PchPreMemPolicyCommon.h | ConfigBlock / Wdt / WatchDogConfig.h
Include / Protocol / PchPolicy.h | ConfigBlock.h
Include / Protocol / PchPolicy.h | Library / ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include

Include → Include Relation

File in Intel/ClientOneSiliconPkg/Pch/Include | Includes file in Intel/ClientOneSiliconPkg/Include
PchPolicyCommon.h | ConfigBlock / Pmc / AdrConfig.h
PchPolicyCommon.h | ConfigBlock / Cnvi / CnviConfig.h
PchPolicyCommon.h | ConfigBlock.h
PchPolicyCommon.h | ConfigBlock / Espi / EspiConfig.h
PchPolicyCommon.h | ConfigBlock / Fivr / FivrConfig.h
PchPolicyCommon.h | ConfigBlock / Spi / FlashProtectionConfig.h
PchPolicyCommon.h | ConfigBlock / Fusa / FusaConfig.h
PchPolicyCommon.h | ConfigBlock / Gbe / GbeConfig.h
PchPolicyCommon.h | ConfigBlock / Hda / HdAudioConfig.h
PchPolicyCommon.h | ConfigBlock / HybridStorage / HybridStorageConfig.h
PchPolicyCommon.h | ConfigBlock / Ieh / IehConfig.h
PchPolicyCommon.h | ConfigBlock / Itss / InterruptConfig.h
PchPolicyCommon.h | ConfigBlock / Itss / IoApicConfig.h
PchPolicyCommon.h | ConfigBlock / Ish / IshConfig.h
PchPolicyCommon.h | ConfigBlock / P2sb / P2sbConfig.h
PchPolicyCommon.h | ConfigBlock / PchDmi / PchDmiConfig.h
PchPolicyCommon.h | ConfigBlock / PcieRp / PchPcieRp / PchPcieRpConfig.h
PchPolicyCommon.h | ConfigBlock / Pmc / PmConfig.h
PchPolicyCommon.h | ConfigBlock / Psf / PsfConfig.h
PchPolicyCommon.h | ConfigBlock / Rst / RstConfig.h
PchPolicyCommon.h | ConfigBlock / Rtc / RtcConfig.h
PchPolicyCommon.h | ConfigBlock / Sata / SataConfig.h
PchPolicyCommon.h | ConfigBlock / Scs / ScsConfig.h
PchPolicyCommon.h | ConfigBlock / SerialIo / SerialIoConfig.h
PchPolicyCommon.h | ConfigBlock / Spi / SpiConfig.h
PchPolicyCommon.h | ConfigBlock / Thc / ThcConfig.h
PchPolicyCommon.h | ConfigBlock / Thermal / ThermalConfig.h
PchPolicyCommon.h | ConfigBlock / Tsn / TsnConfig.h
PchPolicyCommon.h | ConfigBlock / Usb / Usb2PhyConfig.h
PchPolicyCommon.h | ConfigBlock / Usb / Usb3HsioConfig.h
PchPolicyCommon.h | ConfigBlock / Usb / UsbConfig.h
PchPreMemPolicyCommon.h | ConfigBlock.h
PchPreMemPolicyCommon.h | ConfigBlock / Dci / DciConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioPcieConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Hsio / HsioSataConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Espi / LpcConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / PchDmi / PchDmiConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Smbus / SmbusConfig.h
PchPreMemPolicyCommon.h | ConfigBlock / Wdt / WatchDogConfig.h
Library / PchInfoLib.h | Hda.h
Protocol / PchPolicy.h | ConfigBlock.h
Protocol / PchPolicy.h | Library / ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include -> ConfigBlock Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include

Include → ConfigBlock Relation

File in Intel/ClientOneSiliconPkg/Pch/Include | Includes file in Intel/ClientOneSiliconPkg/Pch/Include/ConfigBlock
PchPolicyCommon.h | LockDownConfig.h
PchPolicyCommon.h | PchGeneralConfig.h
PchPreMemPolicyCommon.h | PchGeneralConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Register -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register

Register → Library Relation

File in Intel/ClientOneSiliconPkg/Include/Register | Includes file in Intel/ClientOneSiliconPkg/Include/Library
MeRegs.h | MeChipsetLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Hsio Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Hsio
Hsio Directory Reference

Files

file | HsioConfig.h [code]
HSIO policy.
file | HsioPcieConfig.h [code]
HSIO pcie policy.
file | HsioSataConfig.h [code]
Hsio Sata policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieRp -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp

CpuPcieRp → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp | Includes file in Intel/ClientOneSiliconPkg/Include/Library
Gen3 / CpuPcieConfigGen3.h | GpioLib.h
Gen3 / PciePeiConfig.h | GpioLib.h
Gen4 / CpuPcieConfig.h | GpioLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieRp -> PcieRp Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp

CpuPcieRp → PcieRp Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/PcieRp
Gen3 / CpuPcieConfigGen3.h | PcieConfig.h
Gen4 / CpuPcieConfig.h | PcieConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen4 -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4

Gen4 → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4 | Includes file in Intel/ClientOneSiliconPkg/Include/Library
CpuPcieConfig.h | GpioLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen4 -> PcieRp Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen4

Gen4 → PcieRp Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4 | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/PcieRp
CpuPcieConfig.h | PcieConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen3 -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3

Gen3 → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3 | Includes file in Intel/ClientOneSiliconPkg/Include/Library
CpuPcieConfigGen3.h | GpioLib.h
PciePeiConfig.h | GpioLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen3 -> PcieRp Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3

Gen3 → PcieRp Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3 | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/PcieRp
CpuPcieConfigGen3.h | PcieConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tcss -> Usb Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss

Tcss → Usb Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Tcss | Includes file in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Usb
TcssPeiConfig.h | UsbConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library

Library → Include Relation

File in Intel/ClientOneSiliconPkg/Pch/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include
PchInfoLib.h | Hda.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Protocol Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Library

Library → Protocol Relation

File in Intel/ClientOneSiliconPkg/Pch/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Pch/Include/Protocol
DxePchPolicyLib.h | PchPolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library

Library → Include Relation

File in Intel/ClientOneSiliconPkg/SystemAgent/Include/Library | Includes file in Intel/ClientOneSiliconPkg/Include
PeiSaPolicyLib.h | Library / ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library -> Protocol Relation

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library

Library → Protocol Relation

File in Intel/ClientOneSiliconPkg/SystemAgent/Include/Library | Includes file in Intel/ClientOneSiliconPkg/SystemAgent/Include/Protocol
DxeSaPolicyLib.h | SaPolicy.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ppi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Ppi
Ppi Directory Reference

Files

file SsaPeiInit.h [code]
Interface definition between MRC and SsaInit modules.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ppi -> Protocol Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi

Ppi → Protocol Relation

File in Intel/ClientOneSiliconPkg/Include/Ppi | Includes file in Intel/ClientOneSiliconPkg/Include/Protocol
HeciAccessPpi.h | HeciAccessProtocol.h
HeciControlPpi.h | HeciControlProtocol.h
HeciPpi.h | HeciProtocol.h
Ppi/Spi.h | Protocol/Spi.h
Ppi/Wdt.h | Protocol/Wdt.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuDmi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuDmi
CpuDmi Directory Reference
Directory dependency graph for CpuDmi:

Files

file CpuDmiPreMemConfig.h [code]
DMI policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol -> Include Relation

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol

Protocol → Include Relation

File in Intel/ClientOneSiliconPkg/Pch/Include/Protocol | Includes file in Intel/ClientOneSiliconPkg/Include
PchPolicy.h | ConfigBlock.h
PchPolicy.h | Library / ConfigBlockLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tbt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tbt
Tbt Directory Reference
Directory dependency graph for Tbt:

Files

file | DxeITbtConfig.h [code]
Headr file for iTBT DXE Policy.
file | PeiITbtConfig.h [code]
Header file for TBT PEI Policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Overclocking -> Cpu Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking

Overclocking → Cpu Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Overclocking | Includes file in Intel/ClientOneSiliconPkg/Cpu
OverclockingConfig.h | Include / CpuLimits.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Amt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Amt
Amt Directory Reference
Directory dependency graph for Amt:

Files

file AmtConfig.h [code]
AMT Config Block for PEI/DXE phase.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Sata -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Sata

Sata → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Sata | Includes file in Intel/ClientOneSiliconPkg/Include/Library
SataConfig.h | GpioConfig.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ver2 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
  • Ver2
Ver2 Directory Reference

Files

file MemoryConfig.h [code]
Policy definition of Memory Config Block.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Vtd -> Library Relation

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd

Vtd → Library Relation

File in Intel/ClientOneSiliconPkg/Include/ConfigBlock/Vtd | Includes file in Intel/ClientOneSiliconPkg/Include/Library
VtdConfig.h | VtdInfoLib.h
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Smbus Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Smbus
Smbus Directory Reference

Files

file SmbusConfig.h [code]
Smbus policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | CpuInfo.h [code]
Protocol used to report CPU information.
file | CpuPolicyProtocol.h [code]
Protocol used for specifying platform related CPU information and policy setting.
file | SmmResourceConfigProtocol.h [code]
Protocol used for Configuring SMM Resources (IO / MSR)
file | SmmSpaLogOutputProtocol.h [code]
This header file contains SPA log Output Protocol Interface.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen12 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
  • Gen12
Gen12 Directory Reference

Files

file GraphicsConfig.h [code]
Policy definition for Internal Graphics Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ClientOneSiliconPkg Directory Reference

  • Intel
  • ClientOneSiliconPkg
ClientOneSiliconPkg Directory Reference
Directory dependency graph for ClientOneSiliconPkg:

Directories

directory | Cpu
directory | Pch
directory | SystemAgent
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Memory Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Memory
Memory Directory Reference

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tcss Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tcss
Tcss Directory Reference
Directory dependency graph for Tcss:

Files

file | DpInPreMemConfig.h [code]
DPIN PreMem policy.
file | TcssPeiConfig.h [code]
TCSS PEI policy.
file | TcssPeiPreMemConfig.h [code]
TCSS PEI PreMem policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Usb Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Usb
Usb Directory Reference

Files

file | Usb2PhyConfig.h [code]
USB2 PHY configuration policy.
file | Usb3HsioConfig.h [code]
USB3 Mod PHY configuration policy.
file | UsbConfig.h [code]
Common USB policy shared between PCH and CPU Contains general features settings for xHCI and xDCI.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Pch Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
Pch Directory Reference
Directory dependency graph for Pch:

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): BiosGuard Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • BiosGuard
BiosGuard Directory Reference

Files

file BiosGuardConfig.h [code]
CPU BIOS Guard Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | Bdat4.h [code]
Definition of BDAT data structures that are applicible for all schemas.
file | MemInfoHob.h [code]
This file contains definitions required for creation of Memory S3 Save data, Memory Info data and Memory Platform data hobs.
file | SaDataHob.h [code]
The GUID definition for SaDataHob.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Telemetry Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Telemetry
Telemetry Directory Reference
Directory dependency graph for Telemetry:

Files

file TelemetryPeiConfig.h [code]
Configurations for Telemetry.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridStorage Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridStorage
HybridStorage Directory Reference
Directory dependency graph for HybridStorage:

Files

file HybridStorageConfig.h [code]
Hybrid Storage policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | CpuDataStruct.h [code]
This file declares various data structures used in CPU reference code.
file | CpuLimits.h [code]
This file declares CPU limitated definition.
file | CpuPowerMgmt.h [code]
This file contains define definitions specific to processor.
file | CpuRegs.h [code]
Register names for CPU registers.
file | Txt.h [code]
This file contains definitions required to use the TXT BIOS Authenticated Code Module Library.
file | TxtInfoHob.h [code]
This file contains definitions required for creation of TXT Info HOB.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Intel Directory Reference

  • Intel
Intel Directory Reference
Directory dependency graph for Intel:
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PchDmi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PchDmi
PchDmi Directory Reference

Files

file PchDmiConfig.h [code]
DMI policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Psf Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Psf
Psf Directory Reference
Directory dependency graph for Psf:

Files

file PsfConfig.h [code]
Primary Sideband Fabric policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ieh Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ieh
Ieh Directory Reference
Directory dependency graph for Ieh:

Files

file IehConfig.h [code]
Integrated Error Handler policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HostBridge Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
HostBridge Directory Reference
Directory dependency graph for HostBridge:

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Include Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
Include Directory Reference
Directory dependency graph for Include:

Directories

Files

file | AcpiDebug.h [code]
Header file for ACPI ADBG enable/disable.
file | AmthiMsgs.h [code]
AMTHI Messages.
file | AmtPetQueueHob.h [code]
Definition of AmtPetQueueHob data structures.
file | AsfMsgs.h [code]
AMT/ASF Messages.
file | BiosGuard.h [code]
Describes the functions visible to the rest of the BIOS Guard.
file | BupMsgs.h [code]
BUP Messages - HECI messages exchanged in pre-DID phase with CSME FW.
file | ConfigBlock.h [code]
Header file for Config Block Lib implementation.
file | CoreBiosMsg.h [code]
Core BIOS Messages.
file | CpuDataHob.h [code]
The GUID definition for CpuDataHob.
file | CpuDmiHob.h [code]
The GUID definition for CpuDmiHob.
file | CpuPcieHob.h [code]
The GUID definition for CpuPcieHob.
file | CpuPcieHobGen3.h [code]
The GUID definition for CpuPcieHob.
file | DebugTokenDataHob.h [code]
The HOB definition for DebugTokenDataHob.
file | DxeTbtCommonDefinition.h [code]
TBT DXE Common Definition.
file | FwStsSmbiosTable.h [code]
Header file for Firmware Status Smbios Table Interface implementation.
file | Hda.h [code]
Header file for HD Audio configuration.
file | HgInfoHob.h [code]
This file contains information about Hybrid Graphics.
file | HobUsageDataHob.h [code]
Definitions for Hob Usage data HOB.
file | IccMsgs.h [code]
ICC Messages.
file | IndustryStandardAsf.h [code]
Include file for Industry Standard ASF definition.
file | IntelAsfExtensions.h [code]
Include file for Intel Extended ASF definition.
file | IpuDataHob.h [code]
This file defines the IPU DATA HOB.
file | IshMsgs.h [code]
ISH Messages.
file | ITbtInfoHob.h [code]
HOB definition to be used by iTBT during pre-boot enviornment.
file | MeBiosPayloadData.h [code]
Interface definition details for MBP.
file | MeBiosPayloadHob.h [code]
This file contains definitions of ME BIOS Payload HOB.
file | MebxData.h [code]
MEBx setup data definitions.
file | MeDataHob.h [code]
The GUID definition for MeDataHob.
file | MeDisabledEventHob.h [code]
This file contains definition of ME Disabled Event HOB.
file | MeFwHob.h [code]
The GUID definition for MeFwHob.
file | MeiBusMsg.h [code]
Definitions for MEI Bus message support.
file | MePolicyCommon.h [code]
Definition for ME common policy.
file | MePolicyHob.h [code]
This file contains definitions of ME Policy HOB.
file | MeSmbios.h [code]
Header file for the MeSmbios Driver.
file | MeState.h [code]
Register Definitions for Me States.
file | MeTypeDefs.h [code]
file | MkhiMsgs.h [code]
MKHI Messages.
file | PchDmiHob.h [code]
The GUID definition for CpuDmiHob.
file | PchHybridStorageHob.h [code]
Definitions required to create HybridStorageHob.
file | PchPcieStorageDetectHob.h [code]
Definitions required to create PcieStorageInfoHob.
file | PcieRegs.h [code]
Register names for PCIE standard register.
file | PcieRpMacroDefinition.h [code]
This file contains definitions of PCIE RP MACRO.
file | PeiITbtGenericStructure.h [code]
ITBT Policy definition to be referred in both PEI and DXE phase.
file | PsrMsgs.h [code]
Definitions for querying PSR message.
file | ScsInfoHob.h [code]
The GUID definition for HOBs for SCS.
file | SerialIoDevices.h [code]
Serial IO policy.
file | SiConfigHob.h [code]
Silicon Config HOB is used for gathering platform related Intel silicon information and config setting.
file | SiFvi.h [code]
Header file for Reference code Firmware Version Info Init Lib implementation.
file | SiPolicyStruct.h [code]
Intel reference code configuration policies.
file | SmbiosCacheInfoHob.h [code]
Header file for SMBIOS Cache Info HOB.
file | SmbiosProcessorInfoHob.h [code]
Header file for SMBIOS Processor Info HOB.
file | TbtMailBoxCmdDefinition.h [code]
Header file of TBT MailBox Command Definition shared by C and ASL code.
file | TcssDataHob.h [code]
This file contains definitions of TCSS Data.
file | TraceHubDataHob.h [code]
The GUID definition for TraceHub Data Hob.
file | UpidMsgs.h [code]
Definitions for Unique Platform ID messages support.
file | VmdInfoHob.h [code]
This file contains information about VMD assigned devices.
file | VoltageRegulatorCommands.h [code]
Header file containing Voltage Regulator initialization common definitions.
file | WifiProfileSyncAsfMsgs.h [code]
Supporting functions for profile sync driver ASF communication.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • ConfigBlock
ConfigBlock Directory Reference

Files

file | CpuConfig.h [code]
CPU Config Block.
file | CpuConfigLibPreMemConfig.h [code]
CPU Security PreMemory Config Block.
file | CpuPowerMgmtBasicConfig.h [code]
CPU Power Management Basic Config Block.
file | CpuPowerMgmtCustomConfig.h [code]
CPU Power Managment Custom Config Block.
file | CpuPowerMgmtPsysConfig.h [code]
CPU Power Management Psys(Platform) Config Block.
file | CpuPowerMgmtTestConfig.h [code]
CPU Power Management Test Config Block.
file | CpuSecurityPreMemConfig.h [code]
CPU Security PreMemory Config Block.
file | CpuTestConfig.h [code]
CPU Test Config Block.
file | CpuTxtConfig.h [code]
CPU TXT PreMemory Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | CpuPlatformLib.h [code]
Header file for CpuPlatform Lib.
file | CpuPolicyLib.h [code]
Prototype of the CpuPolicy library.
file | TxtLib.h [code]
Header file for TXT Lib implementation.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Gen3 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
  • Gen3
Gen3 Directory Reference
Directory dependency graph for Gen3:

Files

file | CpuPcieConfigGen3.h [code]
Pcie root port policy.
file | PciePeiConfig.h [code]
Policy definition for PCIe Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ppi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Ppi
Ppi Directory Reference
Directory dependency graph for Ppi:

Files

file | FspmArchConfigPpi.h [code]
Header file for FSP-M Arch Config PPI.
file | HeciAccessPpi.h [code]
ME HECI Access PPI - ME-BIOS communication over HECI in PEI.
file | HeciControlPpi.h [code]
PEI Heci Control PPI - ME-BIOS communication over HECI in PEI.
file | HeciPpi.h [code]
PEI Heci PPI.
file | MbpSensitivePpi.h [code]
MBP Sensitive PPI.
file | PeiPreMemSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.
file | PeiPreMemSiPolicyPrint.h [code]
This file defines the PPI to print PEI Silicon PreMem Policy settings.
file | PeiSiDefaultPolicy.h [code]
This file defines the function to initialize default silicon policy PPI.
file | PeiSiPolicyPrint.h [code]
This file defines the PPI to print PEI Silicon Policy settings.
file | Ppi/PlatformSpecificResetHandler.h [code]
This PPI provides services to register a platform specific handler for ResetSystem().
file | PlatformSpecificResetNotification.h [code]
This PPI provides services to register a platform specific notification callback for ResetSystem().
file | SmmControl.h [code]
EFI SMM Control PPI definition.
file | Ppi/Spi.h [code]
This file defines the PCH SPI PPI which implements the Intel(R) PCH SPI Host Controller Compatibility Interface.
file | TempRamExitPpi.h [code]
This file defines the Silicon Temp Ram Exit PPI which implements the MTRR values initialization.
file | TpmInitialized.h [code]
Tag GUID that must be installed by the TPM PEIM after the TPM hardware is initialized.
file | Ppi/Wdt.h [code]
Watchdog Timer PPI.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): P2sb Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • P2sb
P2sb Directory Reference

Files

file P2sbConfig.h [code]
P2sb policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): TraceHub Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • TraceHub
TraceHub Directory Reference
Directory dependency graph for TraceHub:

Files

file TraceHubConfig.h [code]
Configurations for TraceHub.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): CpuPcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • CpuPcieRp
CpuPcieRp Directory Reference
Directory dependency graph for CpuPcieRp:

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ver1 Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HostBridge
  • Ver1
Ver1 Directory Reference
Directory dependency graph for Ver1:

Files

file HostBridgeConfig.h [code]
Configurations for HostBridge.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Register Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Register
Register Directory Reference
Directory dependency graph for Register:

Files

file | CnviRegs.h [code]
Register names for CNVi.
file | FlashRegs.h [code]
Register names for Flash registers.
file | FlashRegsVer2.h [code]
Register names for Flash registers.
file | GpioRegs.h [code]
Register names for PCH GPIO.
file | GpioRegsVer2.h [code]
Register names for VER2 GPIO.
file | GpioRegsVer4.h [code]
Register names for VER4 GPIO.
file | HeciRegs.h [code]
Register Definitions for HECI.
file | MeRegs.h [code]
Register definition for ME Devices.
file | PchDmi14Regs.h [code]
Register names for PCH DMI SIP14.
file | PchDmi15Regs.h [code]
Register names for PCH DMI and OP-DMI.
file | PchDmi17Regs.h [code]
Register names for PCH DMI starting from SIP 17.
file | PchDmiRegs.h [code]
Register names for PCH DMI and OP-DMI.
file | PchPcieRpRegs.h [code]
Register names for PCH PCI-E root port devices.
file | PchRegsLpc.h [code]
Register names for PCH LPC/eSPI device.
file | PmcRegs.h [code]
Register names for PCH PMC device.
file | PttPtpRegs.h [code]
Register definitions for PTT HCI (Platform Trust Technology - Host Controller Interface).
file | RtcRegs.h [code]
Register names for RTC device.
file | SaPcieDmiRegs.h [code]
Register names for SA DMI and PEG.
file | SataRegs.h [code]
Register names for SATA controllers.
file | SerialIoI2cRegs.h [code]
Register names for Serial IO I2C Controllers.
file | SerialIoRegs.h [code]
Register names for Serial IO Controllers.
file | SerialIoSpiRegs.h [code]
Register names for Serial IO SPI Controllers.
file | SerialIoUartRegs.h [code]
Register names for Serial IO UART Controllers.
file | TcoRegs.h [code]
Register names for PCH TCO device.
file | TelemetryRegs.h [code]
Register names for Telemetry Conventions:
file | UsbRegs.h [code]
Register names for USB Host and device controller.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Cnvi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Cnvi
Cnvi Directory Reference

Files

file CnviConfig.h [code]
CNVi policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Vmd Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vmd
Vmd Directory Reference
Directory dependency graph for Vmd:

Files

file VmdPeiConfig.h [code]
VMD PEI policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): VoltageRegulator Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • VoltageRegulator
VoltageRegulator Directory Reference

Files

file CpuPowerMgmtVrConfig.h [code]
CPU Power Management VR Config Block.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Graphics Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Graphics
Graphics Directory Reference

Directories

Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Vtd Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Vtd
Vtd Directory Reference
Directory dependency graph for Vtd:

Files

file VtdConfig.h [code]
VT-d policy definitions.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Pins Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • Pins
Pins Directory Reference

Files

file | GpioPinsVer2H.h [code]
GPIO pins for TGL-PCH-H,.
file | GpioPinsVer2Lp.h [code]
GPIO pins for TGL-PCH-LP,.
file | GpioPinsVer4S.h [code]
GPIO pins for ADL-PCH-S,.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Protocol Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Protocol
Protocol Directory Reference
Directory dependency graph for Protocol:

Files

file | IoTrapExDispatch.h [code]
PCH IO TrapEx Dispatch Protocol.
file | PchAcpiSmiDispatch.h [code]
APIs of PCH ACPI SMI Dispatch Protocol.
file | PchEspiSmiDispatch.h [code]
SmmEspiDispatch Protocol.
file | PchPcieSmiDispatch.h [code]
APIs of PCH PCIE SMI Dispatch Protocol.
file | PchPolicy.h [code]
Interface definition details between Pch and platform drivers during DXE phase.
file | PchSmiDispatch.h [code]
APIs of PCH SMI Dispatch Protocol.
file | PchSmmIoTrapControl.h [code]
PCH SMM IO Trap Control Protocol.
file | PchSmmPeriodicTimerControl.h [code]
PCH SMM Periodic Timer Control Protocol.
file | PchTcoSmiDispatch.h [code]
APIs of PCH TCO SMI Dispatch Protocol.
file | SmmSmbus.h [code]
SmmSmbus Protocol.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Register Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Cpu
  • Include
  • Register
Register Directory Reference

Files

file | ArchMsr.h [code]
ArchMsr.h.
file | CommonMsr.h [code]
CommonMsr.h.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): PcieRp Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • PcieRp
PcieRp Directory Reference
Directory dependency graph for PcieRp:

Directories

Files

file | PcieConfig.h [code]
PCIe Config Block.
file | PciePreMemConfig.h [code]
PCIe Config Block PreMem.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Library Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • SystemAgent
  • Include
  • Library
Library Directory Reference
Directory dependency graph for Library:

Files

file | DxeSaPolicyLib.h [code]
Prototype of the DxeSaPolicyLib library.
file | PeiSaPolicyLib.h [code]
Prototype of the PeiSaPolicy library.
file | SaPlatformLib.h [code]
Header file for SaPlatformLib.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Tsn Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Tsn
Tsn Directory Reference

Files

file TsnConfig.h [code]
TSN Config policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): HybridGraphics Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • HybridGraphics
HybridGraphics Directory Reference

Files

file HybridGraphicsConfig.h [code]
Hybrid Graphics policy definitions.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): ConfigBlock Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
ConfigBlock Directory Reference
Directory dependency graph for ConfigBlock:

Directories

directory | CpuPcieRp
directory | Graphics
directory | HostBridge
directory | Memory

Files

file | SiConfig.h [code]
Si Config Block.
file | SiPreMemConfig.h [code]
Si Config Block PreMem.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Scs Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Scs
Scs Directory Reference
Directory dependency graph for Scs:

Files

file ScsConfig.h [code]
Scs policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Register Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Pch
  • Include
  • Register
Register Directory Reference

Files

file | PchRegs.h [code]
Generic register definitions for PCH.
file | PchRegsClk.h [code]
Register names for iCLK device.
file | PchRegsSmbus.h [code]
Register names for PCH Smbus Device.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Pmc Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Pmc
Pmc Directory Reference
Directory dependency graph for Pmc:

Files

file | AdrConfig.h [code]
ADR policy.
file | PmConfig.h [code]
Power Management policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Overclocking Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Overclocking
Overclocking Directory Reference
Directory dependency graph for Overclocking:

Files

file OverclockingConfig.h [code]
Overclocking Config Block.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Espi Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Espi
Espi Directory Reference

Files

file | EspiConfig.h [code]
Espi policy.
file | LpcConfig.h [code]
Lpc policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Itss Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Itss
Itss Directory Reference

Files

file | InterruptConfig.h [code]
Interrupt policy.
file | IoApicConfig.h [code]
IoApic policy.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Ipu Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Ipu
Ipu Directory Reference
Directory dependency graph for Ipu:

Files

file IpuPreMemConfig.h [code]
IPU policy definitions.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Wdt Directory Reference

  • Intel
  • ClientOneSiliconPkg
  • Include
  • ConfigBlock
  • Wdt
Wdt Directory Reference

Files

file WatchDogConfig.h [code]
WatchDog policy.
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labelled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labelled with the template parameters of the instance.
Generated on Wed Jan 5 2022 01:24:05 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Main Page

AlderLake Firmware Support Package (FSP) Documentation
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20


AlderLake Firmware Support Package (FSP): Related Pages

Related Pages
Here is a list of all related documentation pages:
Deprecated List
Todo List
Generated on Wed Jan 5 2022 01:24:06 for AlderLake Firmware Support Package (FSP) by doxygen 1.8.20